diff options
Diffstat (limited to 'arch/mips/include/asm/octeon/cvmx-smix-defs.h')
| -rw-r--r-- | arch/mips/include/asm/octeon/cvmx-smix-defs.h | 202 |
1 files changed, 196 insertions, 6 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-smix-defs.h b/arch/mips/include/asm/octeon/cvmx-smix-defs.h index 4f3c0666e94..8a278e6ddba 100644 --- a/arch/mips/include/asm/octeon/cvmx-smix-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-smix-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,15 +28,120 @@ #ifndef __CVMX_SMIX_DEFS_H__ #define __CVMX_SMIX_DEFS_H__ -#define CVMX_SMIX_CLK(offset) (CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256) -#define CVMX_SMIX_CMD(offset) (CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256) -#define CVMX_SMIX_EN(offset) (CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256) -#define CVMX_SMIX_RD_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256) -#define CVMX_SMIX_WR_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256) +static inline uint64_t CVMX_SMIX_CLK(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000003818ull) + (offset) * 128; + } + return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256; +} + +static inline uint64_t CVMX_SMIX_CMD(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000003800ull) + (offset) * 128; + } + return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256; +} + +static inline uint64_t CVMX_SMIX_EN(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000003820ull) + (offset) * 128; + } + return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256; +} + +static inline uint64_t CVMX_SMIX_RD_DAT(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000003810ull) + (offset) * 128; + } + return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256; +} + +static inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000003808ull) + (offset) * 128; + } + return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256; +} union cvmx_smix_clk { uint64_t u64; struct cvmx_smix_clk_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t mode:1; uint64_t reserved_21_23:3; @@ -47,8 +152,21 @@ union cvmx_smix_clk { uint64_t preamble:1; uint64_t sample:4; uint64_t phase:8; +#else + uint64_t phase:8; + uint64_t sample:4; + uint64_t preamble:1; + uint64_t clk_idle:1; + uint64_t reserved_14_14:1; + uint64_t sample_mode:1; + uint64_t sample_hi:5; + uint64_t reserved_21_23:3; + uint64_t mode:1; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_smix_clk_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_21_63:43; uint64_t sample_hi:5; uint64_t sample_mode:1; @@ -57,6 +175,16 @@ union cvmx_smix_clk { uint64_t preamble:1; uint64_t sample:4; uint64_t phase:8; +#else + uint64_t phase:8; + uint64_t sample:4; + uint64_t preamble:1; + uint64_t clk_idle:1; + uint64_t reserved_14_14:1; + uint64_t sample_mode:1; + uint64_t sample_hi:5; + uint64_t reserved_21_63:43; +#endif } cn30xx; struct cvmx_smix_clk_cn30xx cn31xx; struct cvmx_smix_clk_cn30xx cn38xx; @@ -68,27 +196,50 @@ union cvmx_smix_clk { struct cvmx_smix_clk_s cn56xxp1; struct cvmx_smix_clk_cn30xx cn58xx; struct cvmx_smix_clk_cn30xx cn58xxp1; + struct cvmx_smix_clk_s cn61xx; struct cvmx_smix_clk_s cn63xx; struct cvmx_smix_clk_s cn63xxp1; + struct cvmx_smix_clk_s cn66xx; + struct cvmx_smix_clk_s cn68xx; + struct cvmx_smix_clk_s cn68xxp1; + struct cvmx_smix_clk_s cnf71xx; }; union cvmx_smix_cmd { uint64_t u64; struct cvmx_smix_cmd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t phy_op:2; uint64_t reserved_13_15:3; uint64_t phy_adr:5; uint64_t reserved_5_7:3; uint64_t reg_adr:5; +#else + uint64_t reg_adr:5; + uint64_t reserved_5_7:3; + uint64_t phy_adr:5; + uint64_t reserved_13_15:3; + uint64_t phy_op:2; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_smix_cmd_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t phy_op:1; uint64_t reserved_13_15:3; uint64_t phy_adr:5; uint64_t reserved_5_7:3; uint64_t reg_adr:5; +#else + uint64_t reg_adr:5; + uint64_t reserved_5_7:3; + uint64_t phy_adr:5; + uint64_t reserved_13_15:3; + uint64_t phy_op:1; + uint64_t reserved_17_63:47; +#endif } cn30xx; struct cvmx_smix_cmd_cn30xx cn31xx; struct cvmx_smix_cmd_cn30xx cn38xx; @@ -100,15 +251,25 @@ union cvmx_smix_cmd { struct cvmx_smix_cmd_s cn56xxp1; struct cvmx_smix_cmd_cn30xx cn58xx; struct cvmx_smix_cmd_cn30xx cn58xxp1; + struct cvmx_smix_cmd_s cn61xx; struct cvmx_smix_cmd_s cn63xx; struct cvmx_smix_cmd_s cn63xxp1; + struct cvmx_smix_cmd_s cn66xx; + struct cvmx_smix_cmd_s cn68xx; + struct cvmx_smix_cmd_s cn68xxp1; + struct cvmx_smix_cmd_s cnf71xx; }; union cvmx_smix_en { uint64_t u64; struct cvmx_smix_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t en:1; +#else + uint64_t en:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_smix_en_s cn30xx; struct cvmx_smix_en_s cn31xx; @@ -121,17 +282,29 @@ union cvmx_smix_en { struct cvmx_smix_en_s cn56xxp1; struct cvmx_smix_en_s cn58xx; struct cvmx_smix_en_s cn58xxp1; + struct cvmx_smix_en_s cn61xx; struct cvmx_smix_en_s cn63xx; struct cvmx_smix_en_s cn63xxp1; + struct cvmx_smix_en_s cn66xx; + struct cvmx_smix_en_s cn68xx; + struct cvmx_smix_en_s cn68xxp1; + struct cvmx_smix_en_s cnf71xx; }; union cvmx_smix_rd_dat { uint64_t u64; struct cvmx_smix_rd_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t pending:1; uint64_t val:1; uint64_t dat:16; +#else + uint64_t dat:16; + uint64_t val:1; + uint64_t pending:1; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_smix_rd_dat_s cn30xx; struct cvmx_smix_rd_dat_s cn31xx; @@ -144,17 +317,29 @@ union cvmx_smix_rd_dat { struct cvmx_smix_rd_dat_s cn56xxp1; struct cvmx_smix_rd_dat_s cn58xx; struct cvmx_smix_rd_dat_s cn58xxp1; + struct cvmx_smix_rd_dat_s cn61xx; struct cvmx_smix_rd_dat_s cn63xx; struct cvmx_smix_rd_dat_s cn63xxp1; + struct cvmx_smix_rd_dat_s cn66xx; + struct cvmx_smix_rd_dat_s cn68xx; + struct cvmx_smix_rd_dat_s cn68xxp1; + struct cvmx_smix_rd_dat_s cnf71xx; }; union cvmx_smix_wr_dat { uint64_t u64; struct cvmx_smix_wr_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t pending:1; uint64_t val:1; uint64_t dat:16; +#else + uint64_t dat:16; + uint64_t val:1; + uint64_t pending:1; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_smix_wr_dat_s cn30xx; struct cvmx_smix_wr_dat_s cn31xx; @@ -167,8 +352,13 @@ union cvmx_smix_wr_dat { struct cvmx_smix_wr_dat_s cn56xxp1; struct cvmx_smix_wr_dat_s cn58xx; struct cvmx_smix_wr_dat_s cn58xxp1; + struct cvmx_smix_wr_dat_s cn61xx; struct cvmx_smix_wr_dat_s cn63xx; struct cvmx_smix_wr_dat_s cn63xxp1; + struct cvmx_smix_wr_dat_s cn66xx; + struct cvmx_smix_wr_dat_s cn68xx; + struct cvmx_smix_wr_dat_s cn68xxp1; + struct cvmx_smix_wr_dat_s cnf71xx; }; #endif |