diff options
Diffstat (limited to 'arch/mips/kernel')
| -rw-r--r-- | arch/mips/kernel/Makefile | 2 | ||||
| -rw-r--r-- | arch/mips/kernel/cevt-r4k.c | 14 | ||||
| -rw-r--r-- | arch/mips/kernel/csrc-r4k.c | 33 | ||||
| -rw-r--r-- | arch/mips/kernel/head.S | 3 | ||||
| -rw-r--r-- | arch/mips/kernel/process.c | 3 | ||||
| -rw-r--r-- | arch/mips/kernel/setup.c | 31 | ||||
| -rw-r--r-- | arch/mips/kernel/smp-up.c | 67 | ||||
| -rw-r--r-- | arch/mips/kernel/time.c | 116 | ||||
| -rw-r--r-- | arch/mips/kernel/traps.c | 6 | ||||
| -rw-r--r-- | arch/mips/kernel/vpe.c | 4 |
10 files changed, 181 insertions, 98 deletions
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index b551535b7e4..ffa08362de1 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o +obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \ @@ -43,6 +44,7 @@ obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_SMP_UP) += smp-up.o obj-$(CONFIG_MIPS_MT) += mips-mt.o obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index bab935a3d74..24a2d907aa0 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -219,7 +219,7 @@ static int c0_compare_int_usable(void) return 1; } -void __cpuinit mips_clockevent_init(void) +int __cpuinit mips_clockevent_init(void) { uint64_t mips_freq = mips_hpt_frequency; unsigned int cpu = smp_processor_id(); @@ -227,7 +227,7 @@ void __cpuinit mips_clockevent_init(void) unsigned int irq; if (!cpu_has_counter || !mips_hpt_frequency) - return; + return -ENXIO; #ifdef CONFIG_MIPS_MT_SMTC setup_smtc_dummy_clockevent_device(); @@ -237,11 +237,11 @@ void __cpuinit mips_clockevent_init(void) * device. */ if (cpu) - return; + return 0; #endif if (!c0_compare_int_usable()) - return; + return -ENXIO; /* * With vectored interrupts things are getting platform specific. @@ -276,8 +276,8 @@ void __cpuinit mips_clockevent_init(void) clockevents_register_device(cd); - if (!cp0_timer_irq_installed) - return; + if (cp0_timer_irq_installed) + return 0; cp0_timer_irq_installed = 1; @@ -287,4 +287,6 @@ void __cpuinit mips_clockevent_init(void) #else setup_irq(irq, &c0_compare_irqaction); #endif + + return 0; } diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c new file mode 100644 index 00000000000..0e2b5cd81f6 --- /dev/null +++ b/arch/mips/kernel/csrc-r4k.c @@ -0,0 +1,33 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 by Ralf Baechle + */ +#include <linux/clocksource.h> +#include <linux/init.h> + +#include <asm/time.h> + +static cycle_t c0_hpt_read(void) +{ + return read_c0_count(); +} + +static struct clocksource clocksource_mips = { + .name = "MIPS", + .read = c0_hpt_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +void __init init_mips_clocksource(void) +{ + /* Calclate a somewhat reasonable rating value */ + clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; + + clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); + + clocksource_register(&clocksource_mips); +} diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index 23676873106..50be56c9e9e 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -136,7 +136,8 @@ EXPORT(_stext) * kernel load address. This is needed because this platform does * not have a ELF loader yet. */ - __INIT +FEXPORT(__kernel_entry) + j kernel_entry #endif __INIT_REFOK diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 11cb264f59c..2c09a442e5e 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -77,9 +77,8 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) unsigned long status; /* New thread loses kernel privileges. */ - status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|KU_MASK); + status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK); #ifdef CONFIG_64BIT - status &= ~ST0_FR; status |= test_thread_flag(TIF_32BIT_REGS) ? 0 : ST0_FR; #endif status |= KU_USER; diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index a06a27d6cfc..7f6ddcb5d48 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -269,7 +269,7 @@ static void __init bootmem_init(void) static void __init bootmem_init(void) { - unsigned long reserved_end; + unsigned long init_begin, reserved_end; unsigned long mapstart = ~0UL; unsigned long bootmap_size; int i; @@ -342,6 +342,35 @@ static void __init bootmem_init(void) */ bootmap_size = init_bootmem_node(NODE_DATA(0), mapstart, min_low_pfn, max_low_pfn); + + + init_begin = PFN_UP(__pa_symbol(&__init_begin)); + for (i = 0; i < boot_mem_map.nr_map; i++) { + unsigned long start, end; + + start = PFN_UP(boot_mem_map.map[i].addr); + end = PFN_DOWN(boot_mem_map.map[i].addr + + boot_mem_map.map[i].size); + + if (start <= init_begin) + start = init_begin; + if (start >= end) + continue; + +#ifndef CONFIG_HIGHMEM + if (end > max_low_pfn) + end = max_low_pfn; + + /* + * ... finally, is the area going away? + */ + if (end <= start) + continue; +#endif + + add_active_range(0, start, end); + } + /* * Register fully available low RAM pages with the bootmem allocator. */ diff --git a/arch/mips/kernel/smp-up.c b/arch/mips/kernel/smp-up.c new file mode 100644 index 00000000000..ead6c30eeb1 --- /dev/null +++ b/arch/mips/kernel/smp-up.c @@ -0,0 +1,67 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006, 07 by Ralf Baechle (ralf@linux-mips.org) + * + * Symmetric Uniprocessor (TM) Support + */ +#include <linux/kernel.h> +#include <linux/sched.h> + +/* + * Send inter-processor interrupt + */ +void up_send_ipi_single(int cpu, unsigned int action) +{ + panic(KERN_ERR "%s called", __func__); +} + +static inline void up_send_ipi_mask(cpumask_t mask, unsigned int action) +{ + panic(KERN_ERR "%s called", __func__); +} + +/* + * After we've done initial boot, this function is called to allow the + * board code to clean up state, if needed + */ +void __cpuinit up_init_secondary(void) +{ +} + +void __cpuinit up_smp_finish(void) +{ +} + +/* Hook for after all CPUs are online */ +void up_cpus_done(void) +{ +} + +/* + * Firmware CPU startup hook + */ +void __cpuinit up_boot_secondary(int cpu, struct task_struct *idle) +{ +} + +void __init up_smp_setup(void) +{ +} + +void __init up_prepare_cpus(unsigned int max_cpus) +{ +} + +struct plat_smp_ops up_smp_ops = { + .send_ipi_single = up_send_ipi_single, + .send_ipi_mask = up_send_ipi_mask, + .init_secondary = up_init_secondary, + .smp_finish = up_smp_finish, + .cpus_done = up_cpus_done, + .boot_secondary = up_boot_secondary, + .smp_setup = up_smp_setup, + .prepare_cpus = up_prepare_cpus, +}; diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 3284b9b4eca..2995be1ab3c 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -50,14 +50,6 @@ int update_persistent_clock(struct timespec now) return rtc_mips_set_mmss(now.tv_sec); } -/* - * High precision timer functions for a R4k-compatible timer. - */ -static cycle_t c0_hpt_read(void) -{ - return read_c0_count(); -} - int (*mips_timer_state)(void); int null_perf_irq(void) @@ -84,55 +76,6 @@ EXPORT_SYMBOL(perf_irq); unsigned int mips_hpt_frequency; -static struct clocksource clocksource_mips = { - .name = "MIPS", - .read = c0_hpt_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static unsigned int __init calibrate_hpt(void) -{ - cycle_t frequency, hpt_start, hpt_end, hpt_count, hz; - - const int loops = HZ / 10; - int log_2_loops = 0; - int i; - - /* - * We want to calibrate for 0.1s, but to avoid a 64-bit - * division we round the number of loops up to the nearest - * power of 2. - */ - while (loops > 1 << log_2_loops) - log_2_loops++; - i = 1 << log_2_loops; - - /* - * Wait for a rising edge of the timer interrupt. - */ - while (mips_timer_state()); - while (!mips_timer_state()); - - /* - * Now see how many high precision timer ticks happen - * during the calculated number of periods between timer - * interrupts. - */ - hpt_start = clocksource_mips.read(); - do { - while (mips_timer_state()); - while (!mips_timer_state()); - } while (--i); - hpt_end = clocksource_mips.read(); - - hpt_count = (hpt_end - hpt_start) & clocksource_mips.mask; - hz = HZ; - frequency = hpt_count * hz; - - return frequency >> log_2_loops; -} - void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock) { u64 temp; @@ -166,20 +109,6 @@ void __cpuinit clockevent_set_clock(struct clock_event_device *cd, cd->mult = (u32) temp; } -static void __init init_mips_clocksource(void) -{ - /* Calclate a somewhat reasonable rating value */ - clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; - - clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); - - clocksource_register(&clocksource_mips); -} - -void __init __weak plat_time_init(void) -{ -} - /* * This function exists in order to cause an error due to a duplicate * definition if platform code should have its own implementation. The hook @@ -194,21 +123,42 @@ void __init plat_timer_setup(void) BUG(); } +static __init int cpu_has_mfc0_count_bug(void) +{ + switch (current_cpu_type()) { + case CPU_R4000PC: + case CPU_R4000SC: + case CPU_R4000MC: + /* + * V3.0 is documented as suffering from the mfc0 from count bug. + * Afaik this is the last version of the R4000. Later versions + * were marketed as R4400. + */ + return 1; + + case CPU_R4400PC: + case CPU_R4400SC: + case CPU_R4400MC: + /* + * The published errata for the R4400 upto 3.0 say the CPU + * has the mfc0 from count bug. + */ + if ((current_cpu_data.processor_id & 0xff) <= 0x30) + return 1; + + /* + * we assume newer revisions are ok + */ + return 0; + } + + return 0; +} + void __init time_init(void) { plat_time_init(); - if (cpu_has_counter && (mips_hpt_frequency || mips_timer_state)) { - /* We know counter frequency. Or we can get it. */ - if (!mips_hpt_frequency) - mips_hpt_frequency = calibrate_hpt(); - - /* Report the high precision timer rate for a reference. */ - printk("Using %u.%03u MHz high precision timer.\n", - ((mips_hpt_frequency + 500) / 1000) / 1000, - ((mips_hpt_frequency + 500) / 1000) % 1000); + if (mips_clockevent_init() || !cpu_has_mfc0_count_bug()) init_mips_clocksource(); - } - - mips_clockevent_init(); } diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 23e73d0650a..fcae6675297 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1317,12 +1317,12 @@ void __init per_cpu_trap_init(void) #endif if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) status_set |= ST0_XX; + if (cpu_has_dsp) + status_set |= ST0_MX; + change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, status_set); - if (cpu_has_dsp) - set_c0_status(ST0_MX); - #ifdef CONFIG_CPU_MIPSR2 if (cpu_has_mips_r2) { unsigned int enable = 0x0000000f; diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index 38bd33fa2a2..c06eb812a95 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -470,7 +470,7 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location, */ if (v != l->value) { printk(KERN_DEBUG "VPE loader: " - "apply_r_mips_lo16/hi16: " + "apply_r_mips_lo16/hi16: \t" "inconsistent value information\n"); return -ENOEXEC; } @@ -629,7 +629,7 @@ static void simplify_symbols(Elf_Shdr * sechdrs, break; case SHN_MIPS_SCOMMON: - printk(KERN_DEBUG "simplify_symbols: ignoring SHN_MIPS_SCOMMON" + printk(KERN_DEBUG "simplify_symbols: ignoring SHN_MIPS_SCOMMON " "symbol <%s> st_shndx %d\n", strtab + sym[i].st_name, sym[i].st_shndx); // .sbss section |