diff options
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/Makefile | 2 | ||||
| -rw-r--r-- | arch/mips/mm/c-r3k.c | 18 | ||||
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 30 | ||||
| -rw-r--r-- | arch/mips/mm/c-tx39.c | 1 | ||||
| -rw-r--r-- | arch/mips/mm/init.c | 11 | ||||
| -rw-r--r-- | arch/mips/mm/pg-r4k.c | 10 | ||||
| -rw-r--r-- | arch/mips/mm/sc-rm7k.c | 25 | ||||
| -rw-r--r-- | arch/mips/mm/tlb-andes.c | 259 | ||||
| -rw-r--r-- | arch/mips/mm/tlb-r4k.c | 5 | ||||
| -rw-r--r-- | arch/mips/mm/tlbex.c | 47 |
10 files changed, 76 insertions, 332 deletions
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index b0178da019f..4a6220116c9 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -12,7 +12,7 @@ obj-$(CONFIG_HIGHMEM) += highmem.o obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_MIPS64) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_NEVADA) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o -obj-$(CONFIG_CPU_R10000) += c-r4k.o cex-gen.o pg-r4k.o tlb-andes.o +obj-$(CONFIG_CPU_R10000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o pg-r4k.o obj-$(CONFIG_CPU_R4300) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_R4X00) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c index 27f4fa25e8c..9dd1352d574 100644 --- a/arch/mips/mm/c-r3k.c +++ b/arch/mips/mm/c-r3k.c @@ -129,7 +129,7 @@ static void r3k_flush_icache_range(unsigned long start, unsigned long end) "sb\t$0, 0x014(%0)\n\t" "sb\t$0, 0x018(%0)\n\t" "sb\t$0, 0x01c(%0)\n\t" - "sb\t$0, 0x020(%0)\n\t" + "sb\t$0, 0x020(%0)\n\t" "sb\t$0, 0x024(%0)\n\t" "sb\t$0, 0x028(%0)\n\t" "sb\t$0, 0x02c(%0)\n\t" @@ -145,7 +145,7 @@ static void r3k_flush_icache_range(unsigned long start, unsigned long end) "sb\t$0, 0x054(%0)\n\t" "sb\t$0, 0x058(%0)\n\t" "sb\t$0, 0x05c(%0)\n\t" - "sb\t$0, 0x060(%0)\n\t" + "sb\t$0, 0x060(%0)\n\t" "sb\t$0, 0x064(%0)\n\t" "sb\t$0, 0x068(%0)\n\t" "sb\t$0, 0x06c(%0)\n\t" @@ -182,31 +182,31 @@ static void r3k_flush_dcache_range(unsigned long start, unsigned long end) "sb\t$0, 0x004(%0)\n\t" "sb\t$0, 0x008(%0)\n\t" "sb\t$0, 0x00c(%0)\n\t" - "sb\t$0, 0x010(%0)\n\t" + "sb\t$0, 0x010(%0)\n\t" "sb\t$0, 0x014(%0)\n\t" "sb\t$0, 0x018(%0)\n\t" "sb\t$0, 0x01c(%0)\n\t" - "sb\t$0, 0x020(%0)\n\t" + "sb\t$0, 0x020(%0)\n\t" "sb\t$0, 0x024(%0)\n\t" "sb\t$0, 0x028(%0)\n\t" "sb\t$0, 0x02c(%0)\n\t" - "sb\t$0, 0x030(%0)\n\t" + "sb\t$0, 0x030(%0)\n\t" "sb\t$0, 0x034(%0)\n\t" "sb\t$0, 0x038(%0)\n\t" "sb\t$0, 0x03c(%0)\n\t" - "sb\t$0, 0x040(%0)\n\t" + "sb\t$0, 0x040(%0)\n\t" "sb\t$0, 0x044(%0)\n\t" "sb\t$0, 0x048(%0)\n\t" "sb\t$0, 0x04c(%0)\n\t" - "sb\t$0, 0x050(%0)\n\t" + "sb\t$0, 0x050(%0)\n\t" "sb\t$0, 0x054(%0)\n\t" "sb\t$0, 0x058(%0)\n\t" "sb\t$0, 0x05c(%0)\n\t" - "sb\t$0, 0x060(%0)\n\t" + "sb\t$0, 0x060(%0)\n\t" "sb\t$0, 0x064(%0)\n\t" "sb\t$0, 0x068(%0)\n\t" "sb\t$0, 0x06c(%0)\n\t" - "sb\t$0, 0x070(%0)\n\t" + "sb\t$0, 0x070(%0)\n\t" "sb\t$0, 0x074(%0)\n\t" "sb\t$0, 0x078(%0)\n\t" "sb\t$0, 0x07c(%0)\n\t" diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 1b71d91e826..32b7f6aeb98 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -235,7 +235,9 @@ static inline void r4k_blast_scache_page_setup(void) { unsigned long sc_lsize = cpu_scache_line_size(); - if (sc_lsize == 16) + if (scache_size == 0) + r4k_blast_scache_page = (void *)no_sc_noop; + else if (sc_lsize == 16) r4k_blast_scache_page = blast_scache16_page; else if (sc_lsize == 32) r4k_blast_scache_page = blast_scache32_page; @@ -251,7 +253,9 @@ static inline void r4k_blast_scache_page_indexed_setup(void) { unsigned long sc_lsize = cpu_scache_line_size(); - if (sc_lsize == 16) + if (scache_size == 0) + r4k_blast_scache_page_indexed = (void *)no_sc_noop; + else if (sc_lsize == 16) r4k_blast_scache_page_indexed = blast_scache16_page_indexed; else if (sc_lsize == 32) r4k_blast_scache_page_indexed = blast_scache32_page_indexed; @@ -267,7 +271,9 @@ static inline void r4k_blast_scache_setup(void) { unsigned long sc_lsize = cpu_scache_line_size(); - if (sc_lsize == 16) + if (scache_size == 0) + r4k_blast_scache = (void *)no_sc_noop; + else if (sc_lsize == 16) r4k_blast_scache = blast_scache16; else if (sc_lsize == 32) r4k_blast_scache = blast_scache32; @@ -369,6 +375,7 @@ static void r4k_flush_cache_mm(struct mm_struct *mm) struct flush_cache_page_args { struct vm_area_struct *vma; unsigned long addr; + unsigned long pfn; }; static inline void local_r4k_flush_cache_page(void *args) @@ -376,6 +383,7 @@ static inline void local_r4k_flush_cache_page(void *args) struct flush_cache_page_args *fcp_args = args; struct vm_area_struct *vma = fcp_args->vma; unsigned long addr = fcp_args->addr; + unsigned long paddr = fcp_args->pfn << PAGE_SHIFT; int exec = vma->vm_flags & VM_EXEC; struct mm_struct *mm = vma->vm_mm; pgd_t *pgdp; @@ -425,11 +433,12 @@ static inline void local_r4k_flush_cache_page(void *args) * Do indexed flush, too much work to get the (possible) TLB refills * to work correctly. */ - addr = INDEX_BASE + (addr & (dcache_size - 1)); if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { - r4k_blast_dcache_page_indexed(addr); - if (exec && !cpu_icache_snoops_remote_store) - r4k_blast_scache_page_indexed(addr); + r4k_blast_dcache_page_indexed(cpu_has_pindexed_dcache ? + paddr : addr); + if (exec && !cpu_icache_snoops_remote_store) { + r4k_blast_scache_page_indexed(paddr); + } } if (exec) { if (cpu_has_vtag_icache) { @@ -449,6 +458,7 @@ static void r4k_flush_cache_page(struct vm_area_struct *vma, args.vma = vma; args.addr = addr; + args.pfn = pfn; on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1); } @@ -482,7 +492,7 @@ static inline void local_r4k_flush_icache_range(void *args) protected_blast_dcache_range(start, end); } - if (!cpu_icache_snoops_remote_store) { + if (!cpu_icache_snoops_remote_store && scache_size) { if (end - start > scache_size) r4k_blast_scache(); else @@ -651,7 +661,7 @@ static void local_r4k_flush_cache_sigtramp(void * arg) R4600_HIT_CACHEOP_WAR_IMPL; protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); - if (!cpu_icache_snoops_remote_store) + if (!cpu_icache_snoops_remote_store && scache_size) protected_writeback_scache_line(addr & ~(sc_lsize - 1)); protected_flush_icache_line(addr & ~(ic_lsize - 1)); if (MIPS4K_ICACHE_REFILL_WAR) { @@ -776,6 +786,7 @@ static void __init probe_pcache(void) c->dcache.waybit = 0; c->options |= MIPS_CPU_CACHE_CDEX_P; + c->options |= MIPS_CPU_PREFETCH; break; case CPU_R4000PC: @@ -950,6 +961,7 @@ static void __init probe_pcache(void) switch (c->cputype) { case CPU_20KC: case CPU_25KF: + c->dcache.flags |= MIPS_CACHE_PINDEX; case CPU_R10000: case CPU_R12000: case CPU_SB1: diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c index 7c572bea4a9..fe232e3988e 100644 --- a/arch/mips/mm/c-tx39.c +++ b/arch/mips/mm/c-tx39.c @@ -210,7 +210,6 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page * Do indexed flush, too much work to get the (possible) TLB refills * to work correctly. */ - page = (KSEG0 + (page & (dcache_size - 1))); if (cpu_has_dc_aliases || exec) tx39_blast_dcache_page_indexed(page); if (exec) diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 0ff9a348b84..52f7d59fe61 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -54,7 +54,8 @@ unsigned long empty_zero_page, zero_page_mask; */ unsigned long setup_zero_pages(void) { - unsigned long order, size; + unsigned int order; + unsigned long size; struct page *page; if (cpu_has_vce) @@ -67,9 +68,9 @@ unsigned long setup_zero_pages(void) panic("Oh boy, that early out of memory?"); page = virt_to_page(empty_zero_page); + split_page(page, order); while (page < virt_to_page(empty_zero_page + (PAGE_SIZE << order))) { SetPageReserved(page); - set_page_count(page, 1); page++; } @@ -244,7 +245,7 @@ void __init mem_init(void) #ifdef CONFIG_LIMITED_DMA set_page_address(page, lowmem_page_address(page)); #endif - set_page_count(page, 1); + init_page_count(page); __free_page(page); totalhigh_pages++; } @@ -291,7 +292,7 @@ void free_initrd_mem(unsigned long start, unsigned long end) for (; start < end; start += PAGE_SIZE) { ClearPageReserved(virt_to_page(start)); - set_page_count(virt_to_page(start), 1); + init_page_count(virt_to_page(start)); free_page(start); totalram_pages++; } @@ -314,7 +315,7 @@ void free_initmem(void) page = addr; #endif ClearPageReserved(virt_to_page(page)); - set_page_count(virt_to_page(page), 1); + init_page_count(virt_to_page(page)); free_page(page); totalram_pages++; freed += PAGE_SIZE; diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c index f51e180072e..e4390dc3eb4 100644 --- a/arch/mips/mm/pg-r4k.c +++ b/arch/mips/mm/pg-r4k.c @@ -124,7 +124,7 @@ static inline void build_nop(void) static inline void build_src_pref(int advance) { - if (!(load_offset & (cpu_dcache_line_size() - 1))) { + if (!(load_offset & (cpu_dcache_line_size() - 1)) && advance) { union mips_instruction mi; mi.i_format.opcode = pref_op; @@ -166,7 +166,7 @@ static inline void build_load_reg(int reg) static inline void build_dst_pref(int advance) { - if (!(store_offset & (cpu_dcache_line_size() - 1))) { + if (!(store_offset & (cpu_dcache_line_size() - 1)) && advance) { union mips_instruction mi; mi.i_format.opcode = pref_op; @@ -340,6 +340,12 @@ void __init build_clear_page(void) if (cpu_has_prefetch) { switch (current_cpu_data.cputype) { + case CPU_TX49XX: + /* TX49 supports only Pref_Load */ + pref_offset_clear = 0; + pref_offset_copy = 0; + break; + case CPU_RM9000: /* * As a workaround for erratum G105 which make the diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c index 9e8ff8badb1..3b6cc9ba1b0 100644 --- a/arch/mips/mm/sc-rm7k.c +++ b/arch/mips/mm/sc-rm7k.c @@ -9,6 +9,7 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/mm.h> +#include <linux/bitops.h> #include <asm/addrspace.h> #include <asm/bcache.h> @@ -43,14 +44,7 @@ static void rm7k_sc_wback_inv(unsigned long addr, unsigned long size) /* Catch bad driver code */ BUG_ON(size == 0); - a = addr & ~(sc_lsize - 1); - end = (addr + size - 1) & ~(sc_lsize - 1); - while (1) { - flush_scache_line(a); /* Hit_Writeback_Inv_SD */ - if (a == end) - break; - a += sc_lsize; - } + blast_scache_range(addr, addr + size); if (!rm7k_tcache_enabled) return; @@ -74,14 +68,7 @@ static void rm7k_sc_inv(unsigned long addr, unsigned long size) /* Catch bad driver code */ BUG_ON(size == 0); - a = addr & ~(sc_lsize - 1); - end = (addr + size - 1) & ~(sc_lsize - 1); - while (1) { - invalidate_scache_line(a); /* Hit_Invalidate_SD */ - if (a == end) - break; - a += sc_lsize; - } + blast_inv_scache_range(addr, addr + size); if (!rm7k_tcache_enabled) return; @@ -143,11 +130,17 @@ struct bcache_ops rm7k_sc_ops = { void __init rm7k_sc_init(void) { + struct cpuinfo_mips *c = ¤t_cpu_data; unsigned int config = read_c0_config(); if ((config & RM7K_CONF_SC)) return; + c->scache.linesz = sc_lsize; + c->scache.ways = 4; + c->scache.waybit= ffs(scache_size / c->scache.ways) - 1; + c->scache.waysize = scache_size / c->scache.ways; + c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n", (scache_size >> 10), sc_lsize); diff --git a/arch/mips/mm/tlb-andes.c b/arch/mips/mm/tlb-andes.c deleted file mode 100644 index 3f422a849c4..00000000000 --- a/arch/mips/mm/tlb-andes.c +++ /dev/null @@ -1,259 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997, 1998, 1999 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) 2000 Kanoj Sarcar (kanoj@sgi.com) - */ -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/mm.h> -#include <asm/page.h> -#include <asm/pgtable.h> -#include <asm/system.h> -#include <asm/mmu_context.h> - -extern void build_tlb_refill_handler(void); - -#define NTLB_ENTRIES 64 -#define NTLB_ENTRIES_HALF 32 - -void local_flush_tlb_all(void) -{ - unsigned long flags; - unsigned long old_ctx; - unsigned long entry; - - local_irq_save(flags); - /* Save old context and create impossible VPN2 value */ - old_ctx = read_c0_entryhi() & ASID_MASK; - write_c0_entryhi(CKSEG0); - write_c0_entrylo0(0); - write_c0_entrylo1(0); - - entry = read_c0_wired(); - - /* Blast 'em all away. */ - while (entry < NTLB_ENTRIES) { - write_c0_index(entry); - tlb_write_indexed(); - entry++; - } - write_c0_entryhi(old_ctx); - local_irq_restore(flags); -} - -void local_flush_tlb_mm(struct mm_struct *mm) -{ - int cpu = smp_processor_id(); - if (cpu_context(cpu, mm) != 0) { - drop_mmu_context(mm,cpu); - } -} - -void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - int cpu = smp_processor_id(); - - if (cpu_context(cpu, mm) != 0) { - unsigned long flags; - int size; - - local_irq_save(flags); - size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; - size = (size + 1) >> 1; - if (size <= NTLB_ENTRIES_HALF) { - int oldpid = (read_c0_entryhi() & ASID_MASK); - int newpid = (cpu_context(smp_processor_id(), mm) - & ASID_MASK); - - start &= (PAGE_MASK << 1); - end += ((PAGE_SIZE << 1) - 1); - end &= (PAGE_MASK << 1); - while(start < end) { - int idx; - - write_c0_entryhi(start | newpid); - start += (PAGE_SIZE << 1); - tlb_probe(); - idx = read_c0_index(); - write_c0_entrylo0(0); - write_c0_entrylo1(0); - write_c0_entryhi(CKSEG0); - if(idx < 0) - continue; - tlb_write_indexed(); - } - write_c0_entryhi(oldpid); - } else { - drop_mmu_context(mm, cpu); - } - local_irq_restore(flags); - } -} - -void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) -{ - unsigned long flags; - int size; - - size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; - size = (size + 1) >> 1; - - local_irq_save(flags); - if (size <= NTLB_ENTRIES_HALF) { - int pid = read_c0_entryhi(); - - start &= (PAGE_MASK << 1); - end += ((PAGE_SIZE << 1) - 1); - end &= (PAGE_MASK << 1); - - while (start < end) { - int idx; - - write_c0_entryhi(start); - start += (PAGE_SIZE << 1); - tlb_probe(); - idx = read_c0_index(); - write_c0_entrylo0(0); - write_c0_entrylo1(0); - write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT+1))); - if (idx < 0) - continue; - tlb_write_indexed(); - } - write_c0_entryhi(pid); - } else { - local_flush_tlb_all(); - } - local_irq_restore(flags); -} - -void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) -{ - if (cpu_context(smp_processor_id(), vma->vm_mm) != 0) { - unsigned long flags; - int oldpid, newpid, idx; - - newpid = (cpu_context(smp_processor_id(), vma->vm_mm) & - ASID_MASK); - page &= (PAGE_MASK << 1); - local_irq_save(flags); - oldpid = (read_c0_entryhi() & ASID_MASK); - write_c0_entryhi(page | newpid); - tlb_probe(); - idx = read_c0_index(); - write_c0_entrylo0(0); - write_c0_entrylo1(0); - write_c0_entryhi(CKSEG0); - if (idx < 0) - goto finish; - tlb_write_indexed(); - - finish: - write_c0_entryhi(oldpid); - local_irq_restore(flags); - } -} - -/* - * This one is only used for pages with the global bit set so we don't care - * much about the ASID. - */ -void local_flush_tlb_one(unsigned long page) -{ - unsigned long flags; - int oldpid, idx; - - local_irq_save(flags); - page &= (PAGE_MASK << 1); - oldpid = read_c0_entryhi() & 0xff; - write_c0_entryhi(page); - tlb_probe(); - idx = read_c0_index(); - write_c0_entrylo0(0); - write_c0_entrylo1(0); - if (idx >= 0) { - /* Make sure all entries differ. */ - write_c0_entryhi(CKSEG0+(idx<<(PAGE_SHIFT+1))); - tlb_write_indexed(); - } - write_c0_entryhi(oldpid); - - local_irq_restore(flags); -} - -/* XXX Simplify this. On the R10000 writing a TLB entry for an virtual - address that already exists will overwrite the old entry and not result - in TLB malfunction or TLB shutdown. */ -void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) -{ - unsigned long flags; - pgd_t *pgdp; - pud_t *pudp; - pmd_t *pmdp; - pte_t *ptep; - int idx, pid; - - /* - * Handle debugger faulting in for debugee. - */ - if (current->active_mm != vma->vm_mm) - return; - - pid = read_c0_entryhi() & ASID_MASK; - - if ((pid != (cpu_context(smp_processor_id(), vma->vm_mm) & ASID_MASK)) - || (cpu_context(smp_processor_id(), vma->vm_mm) == 0)) { - printk(KERN_WARNING - "%s: Wheee, bogus tlbpid mmpid=%d tlbpid=%d\n", - __FUNCTION__, (int) (cpu_context(smp_processor_id(), - vma->vm_mm) & ASID_MASK), pid); - } - - local_irq_save(flags); - address &= (PAGE_MASK << 1); - write_c0_entryhi(address | (pid)); - pgdp = pgd_offset(vma->vm_mm, address); - tlb_probe(); - pudp = pud_offset(pgdp, address); - pmdp = pmd_offset(pudp, address); - idx = read_c0_index(); - ptep = pte_offset_map(pmdp, address); - write_c0_entrylo0(pte_val(*ptep++) >> 6); - write_c0_entrylo1(pte_val(*ptep) >> 6); - write_c0_entryhi(address | pid); - if (idx < 0) { - tlb_write_random(); - } else { - tlb_write_indexed(); - } - write_c0_entryhi(pid); - local_irq_restore(flags); -} - -void __init tlb_init(void) -{ - /* - * You should never change this register: - * - On R4600 1.7 the tlbp never hits for pages smaller than - * the value in the c0_pagemask register. - * - The entire mm handling assumes the c0_pagemask register to - * be set for 4kb pages. - */ - write_c0_pagemask(PM_4K); - write_c0_wired(0); - write_c0_framemask(0); - - /* From this point on the ARC firmware is dead. */ - local_flush_tlb_all(); - - /* Did I tell you that ARC SUCKS? */ - - build_tlb_refill_handler(); -} diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 8297970f0bb..a865f2394cb 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -424,8 +424,13 @@ void __init tlb_init(void) probe_tlb(config); write_c0_pagemask(PM_DEFAULT_MASK); write_c0_wired(0); + write_c0_framemask(0); temp_tlb_entry = current_cpu_data.tlbsize - 1; + + /* From this point on the ARC firmware is dead. */ local_flush_tlb_all(); + /* Did I tell you that ARC SUCKS? */ + build_tlb_refill_handler(); } diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 0f9485806ba..599b3c29718 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -280,69 +280,69 @@ static void __init build_insn(u32 **buf, enum opcode opc, ...) } #define I_u1u2u3(op) \ - static inline void i##op(u32 **buf, unsigned int a, \ + static inline void __init i##op(u32 **buf, unsigned int a, \ unsigned int b, unsigned int c) \ { \ build_insn(buf, insn##op, a, b, c); \ } #define I_u2u1u3(op) \ - static inline void i##op(u32 **buf, unsigned int a, \ + static inline void __init i##op(u32 **buf, unsigned int a, \ unsigned int b, unsigned int c) \ { \ build_insn(buf, insn##op, b, a, c); \ } #define I_u3u1u2(op) \ - static inline void i##op(u32 **buf, unsigned int a, \ + static inline void __init i##op(u32 **buf, unsigned int a, \ unsigned int b, unsigned int c) \ { \ build_insn(buf, insn##op, b, c, a); \ } #define I_u1u2s3(op) \ - static inline void i##op(u32 **buf, unsigned int a, \ + static inline void __init i##op(u32 **buf, unsigned int a, \ unsigned int b, signed int c) \ { \ build_insn(buf, insn##op, a, b, c); \ } #define I_u2s3u1(op) \ - static inline void i##op(u32 **buf, unsigned int a, \ + static inline void __init i##op(u32 **buf, unsigned int a, \ signed int b, unsigned int c) \ { \ build_insn(buf, insn##op, c, a, b); \ } #define I_u2u1s3(op) \ - static inline void i##op(u32 **buf, unsigned int a, \ + static inline void __init i##op(u32 **buf, unsigned int a, \ unsigned int b, signed int c) \ { \ build_insn(buf, insn##op, b, a, c); \ } #define I_u1u2(op) \ - static inline void i##op(u32 **buf, unsigned int a, \ + static inline void __init i##op(u32 **buf, unsigned int a, \ unsigned int b) \ { \ build_insn(buf, insn##op, a, b); \ } #define I_u1s2(op) \ - static inline void i##op(u32 **buf, unsigned int a, \ + static inline void __init i##op(u32 **buf, unsigned int a, \ signed int b) \ { \ build_insn(buf, insn##op, a, b); \ } #define I_u1(op) \ - static inline void i##op(u32 **buf, unsigned int a) \ + static inline void __init i##op(u32 **buf, unsigned int a) \ { \ build_insn(buf, insn##op, a); \ } #define I_0(op) \ - static inline void i##op(u32 **buf) \ + static inline void __init i##op(u32 **buf) \ { \ build_insn(buf, insn##op); \ } @@ -623,42 +623,42 @@ static __init int __attribute__((unused)) insn_has_bdelay(struct reloc *rel, } /* convenience functions for labeled branches */ -static void __attribute__((unused)) il_bltz(u32 **p, struct reloc **r, - unsigned int reg, enum label_id l) +static void __init __attribute__((unused)) + il_bltz(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) { r_mips_pc16(r, *p, l); i_bltz(p, reg, 0); } -static void __attribute__((unused)) il_b(u32 **p, struct reloc **r, +static void __init __attribute__((unused)) il_b(u32 **p, struct reloc **r, enum label_id l) { r_mips_pc16(r, *p, l); i_b(p, 0); } -static void il_beqz(u32 **p, struct reloc **r, unsigned int reg, +static void __init il_beqz(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) { r_mips_pc16(r, *p, l); i_beqz(p, reg, 0); } -static void __attribute__((unused)) +static void __init __attribute__((unused)) il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) { r_mips_pc16(r, *p, l); i_beqzl(p, reg, 0); } -static void il_bnez(u32 **p, struct reloc **r, unsigned int reg, +static void __init il_bnez(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) { r_mips_pc16(r, *p, l); i_bnez(p, reg, 0); } -static void il_bgezl(u32 **p, struct reloc **r, unsigned int reg, +static void __init il_bgezl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) { r_mips_pc16(r, *p, l); @@ -951,7 +951,6 @@ build_get_pmde64(u32 **p, struct label **l, struct reloc **r, /* No i_nop needed here, since the next insn doesn't touch TMP. */ #ifdef CONFIG_SMP -# ifdef CONFIG_BUILD_ELF64 /* * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 * stored in CONTEXT. @@ -962,18 +961,6 @@ build_get_pmde64(u32 **p, struct label **l, struct reloc **r, i_daddu(p, ptr, ptr, tmp); i_dmfc0(p, tmp, C0_BADVADDR); i_ld(p, ptr, rel_lo(pgdc), ptr); -# else - /* - * 64 bit SMP running in compat space has the lower part of - * &pgd_current[smp_processor_id()] stored in CONTEXT. - */ - if (!in_compat_space_p(pgdc)) - panic("Invalid page directory address!"); - - i_dmfc0(p, ptr, C0_CONTEXT); - i_dsra(p, ptr, ptr, 23); - i_ld(p, ptr, 0, ptr); -# endif #else i_LA_mostly(p, ptr, pgdc); i_ld(p, ptr, rel_lo(pgdc), ptr); |