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-rw-r--r--arch/mips/pci/Makefile14
-rw-r--r--arch/mips/pci/fixup-atlas.c91
-rw-r--r--arch/mips/pci/fixup-jmr3927.c35
-rw-r--r--arch/mips/pci/fixup-rbtx4927.c119
-rw-r--r--arch/mips/pci/fixup-rbtx4938.c53
-rw-r--r--arch/mips/pci/fixup-rc32434.c (renamed from arch/mips/pci/pci-jmr3927.c)59
-rw-r--r--arch/mips/pci/fixup-tx4938.c92
-rw-r--r--arch/mips/pci/fixup-vr4133.c195
-rw-r--r--arch/mips/pci/ops-mace.c7
-rw-r--r--arch/mips/pci/ops-rc32434.c207
-rw-r--r--arch/mips/pci/ops-tx3927.c87
-rw-r--r--arch/mips/pci/ops-tx4927.c517
-rw-r--r--arch/mips/pci/ops-tx4938.c214
-rw-r--r--arch/mips/pci/pci-bcm1480.c3
-rw-r--r--arch/mips/pci/pci-ip27.c1
-rw-r--r--arch/mips/pci/pci-lasat.c14
-rw-r--r--arch/mips/pci/pci-rc32434.c221
-rw-r--r--arch/mips/pci/pci-sb1250.c4
-rw-r--r--arch/mips/pci/pci-tx4927.c83
-rw-r--r--arch/mips/pci/pci-tx4938.c134
-rw-r--r--arch/mips/pci/pci.c5
21 files changed, 1229 insertions, 926 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index ed0c07622ba..15e01aec37f 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -11,17 +11,16 @@ obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o
obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o
obj-$(CONFIG_MIPS_MSC) += ops-msc.o
obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
-obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o
+obj-$(CONFIG_SOC_TX3927) += ops-tx3927.o
obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
-obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
+obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o
#
# These are still pretty much in the old state, watch, go blind.
#
obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o
obj-$(CONFIG_LASAT) += pci-lasat.o
-obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
@@ -42,9 +41,12 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
-obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o
-obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o
-obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o
+obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o
+obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o
+obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o
+obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o
+obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o
obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
+obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
diff --git a/arch/mips/pci/fixup-atlas.c b/arch/mips/pci/fixup-atlas.c
deleted file mode 100644
index 506e883a8c7..00000000000
--- a/arch/mips/pci/fixup-atlas.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
- * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
- * Author: Maciej W. Rozycki <macro@mips.com>
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-#include <linux/init.h>
-#include <linux/pci.h>
-
-#include <asm/mips-boards/atlasint.h>
-
-#define PCIA ATLAS_INT_PCIA
-#define PCIB ATLAS_INT_PCIB
-#define PCIC ATLAS_INT_PCIC
-#define PCID ATLAS_INT_PCID
-#define INTA ATLAS_INT_INTA
-#define INTB ATLAS_INT_INTB
-#define ETH ATLAS_INT_ETH
-#define INTC ATLAS_INT_INTC
-#define SCSI ATLAS_INT_SCSI
-#define INTD ATLAS_INT_INTD
-
-static char irq_tab[][5] __initdata = {
- /* INTA INTB INTC INTD */
- {0, 0, 0, 0, 0 }, /* 0: Unused */
- {0, 0, 0, 0, 0 }, /* 1: Unused */
- {0, 0, 0, 0, 0 }, /* 2: Unused */
- {0, 0, 0, 0, 0 }, /* 3: Unused */
- {0, 0, 0, 0, 0 }, /* 4: Unused */
- {0, 0, 0, 0, 0 }, /* 5: Unused */
- {0, 0, 0, 0, 0 }, /* 6: Unused */
- {0, 0, 0, 0, 0 }, /* 7: Unused */
- {0, 0, 0, 0, 0 }, /* 8: Unused */
- {0, 0, 0, 0, 0 }, /* 9: Unused */
- {0, 0, 0, 0, 0 }, /* 10: Unused */
- {0, 0, 0, 0, 0 }, /* 11: Unused */
- {0, 0, 0, 0, 0 }, /* 12: Unused */
- {0, 0, 0, 0, 0 }, /* 13: Unused */
- {0, 0, 0, 0, 0 }, /* 14: Unused */
- {0, PCIA, PCIB, PCIC, PCID }, /* 15: cPCI (behind 21150) */
- {0, SCSI, 0, 0, 0 }, /* 16: SYM53C810A SCSI */
- {0, 0, 0, 0, 0 }, /* 17: Core */
- {0, INTA, INTB, INTC, INTD }, /* 18: PCI Slot */
- {0, ETH, 0, 0, 0 }, /* 19: SAA9730 Eth. et al. */
- {0, 0, 0, 0, 0 }, /* 20: Unused */
- {0, 0, 0, 0, 0 } /* 21: Unused */
-};
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- return irq_tab[slot][pin];
-}
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
-
-#ifdef CONFIG_KGDB
-/*
- * The PCI scan may have moved the saa9730 I/O address, so reread
- * the address here.
- * This does mean that it's not possible to debug the PCI bus configuration
- * code, but it is better than nothing...
- */
-
-static void atlas_saa9730_base_fixup(struct pci_dev *pdev)
-{
- extern void *saa9730_base;
- if (pdev->bus == 0 && PCI_SLOT(pdev->devfn) == 19)
- (void) pci_read_config_dword(pdev, 0x14, (u32 *)&saa9730_base);
- printk("saa9730_base = %x\n", saa9730_base);
-}
-
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA9730,
- atlas_saa9730_base_fixup);
-
-#endif
diff --git a/arch/mips/pci/fixup-jmr3927.c b/arch/mips/pci/fixup-jmr3927.c
index e974394be7b..0f1069527cb 100644
--- a/arch/mips/pci/fixup-jmr3927.c
+++ b/arch/mips/pci/fixup-jmr3927.c
@@ -28,36 +28,31 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/init.h>
+#include <asm/txx9/pci.h>
+#include <asm/txx9/jmr3927.h>
-#include <asm/jmr3927/jmr3927.h>
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+int __init jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
unsigned char irq = pin;
- /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
- if (dev->vendor == PCI_VENDOR_ID_EFAR &&
- dev->device == PCI_DEVICE_ID_EFAR_SLC90E66_1)
- return irq;
/* IRQ rotation (PICMG) */
irq--; /* 0-3 */
- if (dev->bus->parent == NULL &&
- slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(23)) {
+ if (slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(23)) {
/* PCI CardSlot (IDSEL=A23, DevNu=12) */
/* PCIA => PCIC (IDSEL=A23) */
/* NOTE: JMR3927 JP1 must be set to OPEN */
irq = (irq + 2) % 4;
- } else if (dev->bus->parent == NULL &&
- slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) {
+ } else if (slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) {
/* PCI CardSlot (IDSEL=A22, DevNu=11) */
/* PCIA => PCIA (IDSEL=A22) */
/* NOTE: JMR3927 JP1 must be set to OPEN */
irq = (irq + 0) % 4;
} else {
/* PCI Backplane */
- irq = (irq + 3 + slot) % 4;
+ if (txx9_pci_option & TXX9_PCI_OPT_PICMG)
+ irq = (irq + 33 - slot) % 4;
+ else
+ irq = (irq + 3 + slot) % 4;
}
irq++; /* 1-4 */
@@ -66,15 +61,13 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
irq = JMR3927_IRQ_IOC_PCIA;
break;
case 2:
- // wrong for backplane irq = JMR3927_IRQ_IOC_PCIB;
- irq = JMR3927_IRQ_IOC_PCID;
+ irq = JMR3927_IRQ_IOC_PCIB;
break;
case 3:
irq = JMR3927_IRQ_IOC_PCIC;
break;
case 4:
- // wrong for backplane irq = JMR3927_IRQ_IOC_PCID;
- irq = JMR3927_IRQ_IOC_PCIB;
+ irq = JMR3927_IRQ_IOC_PCID;
break;
}
@@ -84,9 +77,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
irq = JMR3927_IRQ_ETHER0;
return irq;
}
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c
index 7450c335b38..321db265829 100644
--- a/arch/mips/pci/fixup-rbtx4927.c
+++ b/arch/mips/pci/fixup-rbtx4927.c
@@ -33,108 +33,41 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
+#include <asm/txx9/pci.h>
+#include <asm/txx9/rbtx4927.h>
-#include <asm/tx4927/tx4927.h>
-#include <asm/tx4927/tx4927_pci.h>
-
-#undef DEBUG
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif
-
-/* look up table for backplane pci irq for slots 17-20 by pin # */
-static unsigned char backplane_pci_irq[4][4] = {
- /* PJ6 SLOT: 17, PIN: 1 */ {TX4927_IRQ_IOC_PCIA,
- /* PJ6 SLOT: 17, PIN: 2 */
- TX4927_IRQ_IOC_PCIB,
- /* PJ6 SLOT: 17, PIN: 3 */
- TX4927_IRQ_IOC_PCIC,
- /* PJ6 SLOT: 17, PIN: 4 */
- TX4927_IRQ_IOC_PCID},
- /* SB SLOT: 18, PIN: 1 */ {TX4927_IRQ_IOC_PCIB,
- /* SB SLOT: 18, PIN: 2 */
- TX4927_IRQ_IOC_PCIC,
- /* SB SLOT: 18, PIN: 3 */
- TX4927_IRQ_IOC_PCID,
- /* SB SLOT: 18, PIN: 4 */
- TX4927_IRQ_IOC_PCIA},
- /* PJ5 SLOT: 19, PIN: 1 */ {TX4927_IRQ_IOC_PCIC,
- /* PJ5 SLOT: 19, PIN: 2 */
- TX4927_IRQ_IOC_PCID,
- /* PJ5 SLOT: 19, PIN: 3 */
- TX4927_IRQ_IOC_PCIA,
- /* PJ5 SLOT: 19, PIN: 4 */
- TX4927_IRQ_IOC_PCIB},
- /* PJ4 SLOT: 20, PIN: 1 */ {TX4927_IRQ_IOC_PCID,
- /* PJ4 SLOT: 20, PIN: 2 */
- TX4927_IRQ_IOC_PCIA,
- /* PJ4 SLOT: 20, PIN: 3 */
- TX4927_IRQ_IOC_PCIB,
- /* PJ4 SLOT: 20, PIN: 4 */
- TX4927_IRQ_IOC_PCIC}
-};
-
-static int pci_get_irq(const struct pci_dev *dev, int pin)
+int __init rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
unsigned char irq = pin;
- DBG("pci_get_irq: pin is %d\n", pin);
/* IRQ rotation */
irq--; /* 0-3 */
- if (dev->bus->parent == NULL &&
- PCI_SLOT(dev->devfn) == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) {
- printk("Onboard PCI_SLOT(dev->devfn) is %d\n",
- PCI_SLOT(dev->devfn));
- /* IDSEL=A23 is tx4927 onboard pci slot */
- irq = (irq + PCI_SLOT(dev->devfn)) % 4;
- irq++; /* 1-4 */
- DBG("irq is now %d\n", irq);
-
- switch (irq) {
- case 1:
- irq = TX4927_IRQ_IOC_PCIA;
- break;
- case 2:
- irq = TX4927_IRQ_IOC_PCIB;
- break;
- case 3:
- irq = TX4927_IRQ_IOC_PCIC;
- break;
- case 4:
- irq = TX4927_IRQ_IOC_PCID;
- break;
- }
+ if (slot == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) {
+ /* PCI CardSlot (IDSEL=A23) */
+ /* PCIA => PCIA */
+ irq = (irq + 0 + slot) % 4;
} else {
/* PCI Backplane */
- DBG("PCI Backplane PCI_SLOT(dev->devfn) is %d\n",
- PCI_SLOT(dev->devfn));
- irq = backplane_pci_irq[PCI_SLOT(dev->devfn) - 17][irq];
+ if (txx9_pci_option & TXX9_PCI_OPT_PICMG)
+ irq = (irq + 33 - slot) % 4;
+ else
+ irq = (irq + 3 + slot) % 4;
}
- DBG("assigned irq %d\n", irq);
- return irq;
-}
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- unsigned char irq;
-
- printk("PCI Setup for pin %d \n", pin);
-
- if (dev->device == 0x9130) /* IDE */
- irq = 14;
- else
- irq = pci_get_irq(dev, pin);
+ irq++; /* 1-4 */
+ switch (irq) {
+ case 1:
+ irq = RBTX4927_IRQ_IOC_PCIA;
+ break;
+ case 2:
+ irq = RBTX4927_IRQ_IOC_PCIB;
+ break;
+ case 3:
+ irq = RBTX4927_IRQ_IOC_PCIC;
+ break;
+ case 4:
+ irq = RBTX4927_IRQ_IOC_PCID;
+ break;
+ }
return irq;
}
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
diff --git a/arch/mips/pci/fixup-rbtx4938.c b/arch/mips/pci/fixup-rbtx4938.c
new file mode 100644
index 00000000000..a80579af609
--- /dev/null
+++ b/arch/mips/pci/fixup-rbtx4938.c
@@ -0,0 +1,53 @@
+/*
+ * Toshiba rbtx4938 pci routines
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ *
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
+ */
+#include <linux/types.h>
+#include <asm/txx9/pci.h>
+#include <asm/txx9/rbtx4938.h>
+
+int __init rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+ int irq = tx4938_pcic1_map_irq(dev, slot);
+
+ if (irq >= 0)
+ return irq;
+ irq = pin;
+ /* IRQ rotation */
+ irq--; /* 0-3 */
+ if (slot == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) {
+ /* PCI CardSlot (IDSEL=A23) */
+ /* PCIA => PCIA (IDSEL=A23) */
+ irq = (irq + 0 + slot) % 4;
+ } else {
+ /* PCI Backplane */
+ if (txx9_pci_option & TXX9_PCI_OPT_PICMG)
+ irq = (irq + 33 - slot) % 4;
+ else
+ irq = (irq + 3 + slot) % 4;
+ }
+ irq++; /* 1-4 */
+
+ switch (irq) {
+ case 1:
+ irq = RBTX4938_IRQ_IOC_PCIA;
+ break;
+ case 2:
+ irq = RBTX4938_IRQ_IOC_PCIB;
+ break;
+ case 3:
+ irq = RBTX4938_IRQ_IOC_PCIC;
+ break;
+ case 4:
+ irq = RBTX4938_IRQ_IOC_PCID;
+ break;
+ }
+ return irq;
+}
diff --git a/arch/mips/pci/pci-jmr3927.c b/arch/mips/pci/fixup-rc32434.c
index cb84f4e8cca..75b90dcb7a0 100644
--- a/arch/mips/pci/pci-jmr3927.c
+++ b/arch/mips/pci/fixup-rc32434.c
@@ -1,10 +1,7 @@
/*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
- * ahennessy@mvista.com
- *
- * Copyright (C) 2000-2001 Toshiba Corporation
- * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
+ * stevel@mvista.com or source@mvista.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -26,33 +23,47 @@
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
+
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
-#include <asm/jmr3927/jmr3927.h>
-#include <asm/debug.h>
+#include <asm/mach-rc32434/rc32434.h>
-struct resource pci_io_resource = {
- .name = "IO MEM",
- .start = 0x1000, /* reserve regacy I/O space */
- .end = 0x1000 + JMR3927_PCIIO_SIZE - 1,
- .flags = IORESOURCE_IO
+static int __devinitdata irq_map[2][12] = {
+ {0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1},
+ {0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3}
};
-struct resource pci_mem_resource = {
- .name = "PCI MEM",
- .start = JMR3927_PCIMEM,
- .end = JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE - 1,
- .flags = IORESOURCE_MEM
-};
+int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+ int irq = 0;
-extern struct pci_ops jmr3927_pci_ops;
+ if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12)
+ irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)];
-struct pci_controller jmr3927_controller = {
- .pci_ops = &jmr3927_pci_ops,
- .io_resource = &pci_io_resource,
- .mem_resource = &pci_mem_resource,
- .mem_offset = JMR3927_PCIMEM
-};
+ return irq + GROUP4_IRQ_BASE + 4;
+}
+
+static void rc32434_pci_early_fixup(struct pci_dev *dev)
+{
+ if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
+ /* disable prefetched memory range */
+ pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
+ pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
+
+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
+ }
+}
+
+/*
+ * The fixup applies to both the IDT and VIA devices present on the board
+ */
+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, rc32434_pci_early_fixup);
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+ return 0;
+}
diff --git a/arch/mips/pci/fixup-tx4938.c b/arch/mips/pci/fixup-tx4938.c
deleted file mode 100644
index f2ba06ee0c1..00000000000
--- a/arch/mips/pci/fixup-tx4938.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Toshiba rbtx4938 pci routines
- * Copyright (C) 2000-2001 Toshiba Corporation
- *
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
- */
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include <asm/tx4938/rbtx4938.h>
-
-extern struct pci_controller tx4938_pci_controller[];
-
-static int pci_get_irq(const struct pci_dev *dev, int pin)
-{
- int irq = pin;
- u8 slot = PCI_SLOT(dev->devfn);
- struct pci_controller *controller = (struct pci_controller *)dev->sysdata;
-
- if (controller == &tx4938_pci_controller[1]) {
- /* TX4938 PCIC1 */
- switch (slot) {
- case TX4938_PCIC_IDSEL_AD_TO_SLOT(31):
- if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL)
- return RBTX4938_IRQ_IRC + TX4938_IR_ETH0;
- break;
- case TX4938_PCIC_IDSEL_AD_TO_SLOT(30):
- if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL)
- return RBTX4938_IRQ_IRC + TX4938_IR_ETH1;
- break;
- }
- return 0;
- }
-
- /* IRQ rotation */
- irq--; /* 0-3 */
- if (dev->bus->parent == NULL &&
- (slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) {
- /* PCI CardSlot (IDSEL=A23) */
- /* PCIA => PCIA (IDSEL=A23) */
- irq = (irq + 0 + slot) % 4;
- } else {
- /* PCI Backplane */
- irq = (irq + 33 - slot) % 4;
- }
- irq++; /* 1-4 */
-
- switch (irq) {
- case 1:
- irq = RBTX4938_IRQ_IOC_PCIA;
- break;
- case 2:
- irq = RBTX4938_IRQ_IOC_PCIB;
- break;
- case 3:
- irq = RBTX4938_IRQ_IOC_PCIC;
- break;
- case 4:
- irq = RBTX4938_IRQ_IOC_PCID;
- break;
- }
- return irq;
-}
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- unsigned char irq = 0;
-
- irq = pci_get_irq(dev, pin);
-
- printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n",
- dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn),
- PCI_FUNC(dev->devfn), irq);
-
- return irq;
-}
-
-/*
- * Do platform specific device initialization at pci_enable_device() time
- */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
-
diff --git a/arch/mips/pci/fixup-vr4133.c b/arch/mips/pci/fixup-vr4133.c
deleted file mode 100644
index de5e5f6bbf4..00000000000
--- a/arch/mips/pci/fixup-vr4133.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * arch/mips/pci/fixup-vr4133.c
- *
- * The NEC CMB-VR4133 Board specific PCI fixups.
- *
- * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
- * Alex Sapkov <asapkov@ru.mvista.com>
- *
- * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Modified for support in 2.6
- * Author: Manish Lachwani (mlachwani@mvista.com)
- *
- */
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-
-#include <asm/io.h>
-#include <asm/i8259.h>
-#include <asm/vr41xx/cmbvr4133.h>
-
-extern int vr4133_rockhopper;
-extern void ali_m1535plus_init(struct pci_dev *dev);
-extern void ali_m5229_init(struct pci_dev *dev);
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- /*
- * We have to reset AMD PCnet adapter on Rockhopper since
- * PMON leaves it enabled and generating interrupts. This leads
- * to a lock if some PCI device driver later enables the IRQ line
- * shared with PCnet and there is no AMD PCnet driver to catch its
- * interrupts.
- */
-#ifdef CONFIG_ROCKHOPPER
- if (dev->vendor == PCI_VENDOR_ID_AMD &&
- dev->device == PCI_DEVICE_ID_AMD_LANCE) {
- inl(pci_resource_start(dev, 0) + 0x18);
- }
-#endif
-
- /*
- * we have to open the bridges' windows down to 0 because otherwise
- * we cannot access ISA south bridge I/O registers that get mapped from
- * 0. for example, 8259 PIC would be unaccessible without that
- */
- if(dev->vendor == PCI_VENDOR_ID_INTEL && dev->device == PCI_DEVICE_ID_INTEL_S21152BB) {
- pci_write_config_byte(dev, PCI_IO_BASE, 0);
- if(dev->bus->number == 0) {
- pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 0);
- } else {
- pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 1);
- }
- }
-
- return 0;
-}
-
-/*
- * M1535 IRQ mapping
- * Feel free to change this, although it shouldn't be needed
- */
-#define M1535_IRQ_INTA 7
-#define M1535_IRQ_INTB 9
-#define M1535_IRQ_INTC 10
-#define M1535_IRQ_INTD 11
-
-#define M1535_IRQ_USB 9
-#define M1535_IRQ_IDE 14
-#define M1535_IRQ_IDE2 15
-#define M1535_IRQ_PS2 12
-#define M1535_IRQ_RTC 8
-#define M1535_IRQ_FDC 6
-#define M1535_IRQ_AUDIO 5
-#define M1535_IRQ_COM1 4
-#define M1535_IRQ_COM2 4
-#define M1535_IRQ_IRDA 3
-#define M1535_IRQ_KBD 1
-#define M1535_IRQ_TMR 0
-
-/* Rockhopper "slots" assignment; this is hard-coded ... */
-#define ROCKHOPPER_M5451_SLOT 1
-#define ROCKHOPPER_M1535_SLOT 2
-#define ROCKHOPPER_M5229_SLOT 11
-#define ROCKHOPPER_M5237_SLOT 15
-#define ROCKHOPPER_PMU_SLOT 12
-/* ... and hard-wired. */
-#define ROCKHOPPER_PCI1_SLOT 3
-#define ROCKHOPPER_PCI2_SLOT 4
-#define ROCKHOPPER_PCI3_SLOT 5
-#define ROCKHOPPER_PCI4_SLOT 6
-#define ROCKHOPPER_PCNET_SLOT 1
-
-#define M1535_IRQ_MASK(n) (1 << (n))
-
-#define M1535_IRQ_EDGE (M1535_IRQ_MASK(M1535_IRQ_TMR) | \
- M1535_IRQ_MASK(M1535_IRQ_KBD) | \
- M1535_IRQ_MASK(M1535_IRQ_COM1) | \
- M1535_IRQ_MASK(M1535_IRQ_COM2) | \
- M1535_IRQ_MASK(M1535_IRQ_IRDA) | \
- M1535_IRQ_MASK(M1535_IRQ_RTC) | \
- M1535_IRQ_MASK(M1535_IRQ_FDC) | \
- M1535_IRQ_MASK(M1535_IRQ_PS2))
-
-#define M1535_IRQ_LEVEL (M1535_IRQ_MASK(M1535_IRQ_IDE) | \
- M1535_IRQ_MASK(M1535_IRQ_USB) | \
- M1535_IRQ_MASK(M1535_IRQ_INTA) | \
- M1535_IRQ_MASK(M1535_IRQ_INTB) | \
- M1535_IRQ_MASK(M1535_IRQ_INTC) | \
- M1535_IRQ_MASK(M1535_IRQ_INTD))
-
-struct irq_map_entry {
- u16 bus;
- u8 slot;
- u8 irq;
-};
-static struct irq_map_entry int_map[] = {
- {1, ROCKHOPPER_M5451_SLOT, M1535_IRQ_AUDIO}, /* Audio controller */
- {1, ROCKHOPPER_PCI1_SLOT, M1535_IRQ_INTD}, /* PCI slot #1 */
- {1, ROCKHOPPER_PCI2_SLOT, M1535_IRQ_INTC}, /* PCI slot #2 */
- {1, ROCKHOPPER_M5237_SLOT, M1535_IRQ_USB}, /* USB host controller */
- {1, ROCKHOPPER_M5229_SLOT, IDE_PRIMARY_IRQ}, /* IDE controller */
- {2, ROCKHOPPER_PCNET_SLOT, M1535_IRQ_INTD}, /* AMD Am79c973 on-board
- ethernet */
- {2, ROCKHOPPER_PCI3_SLOT, M1535_IRQ_INTB}, /* PCI slot #3 */
- {2, ROCKHOPPER_PCI4_SLOT, M1535_IRQ_INTC} /* PCI slot #4 */
-};
-
-static int pci_intlines[] =
- { M1535_IRQ_INTA, M1535_IRQ_INTB, M1535_IRQ_INTC, M1535_IRQ_INTD };
-
-/* Determine the Rockhopper IRQ line number for the PCI device */
-int rockhopper_get_irq(struct pci_dev *dev, u8 pin, u8 slot)
-{
- struct pci_bus *bus;
- int i;
-
- bus = dev->bus;
- if (bus == NULL)
- return -1;
-
- for (i = 0; i < ARRAY_SIZE(int_map); i++) {
- if (int_map[i].bus == bus->number && int_map[i].slot == slot) {
- int line;
- for (line = 0; line < 4; line++)
- if (pci_intlines[line] == int_map[i].irq)
- break;
- if (line < 4)
- return pci_intlines[(line + (pin - 1)) % 4];
- else
- return int_map[i].irq;
- }
- }
- return -1;
-}
-
-#ifdef CONFIG_ROCKHOPPER
-void i8259_init(void)
-{
- init_i8259_irqs();
-
- outb(0x00, 0x4d0);
- outb(0x02, 0x4d1); /* USB IRQ9 is level */
-}
-#endif
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- extern int pci_probe_only;
- pci_probe_only = 1;
-
-#ifdef CONFIG_ROCKHOPPER
- if( dev->bus->number == 1 && vr4133_rockhopper ) {
- if(slot == ROCKHOPPER_PCI1_SLOT || slot == ROCKHOPPER_PCI2_SLOT)
- dev->irq = CMBVR41XX_INTA_IRQ;
- else
- dev->irq = rockhopper_get_irq(dev, pin, slot);
- } else
- dev->irq = CMBVR41XX_INTA_IRQ;
-#else
- dev->irq = CMBVR41XX_INTA_IRQ;
-#endif
-
- return dev->irq;
-}
-
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, ali_m1535plus_init);
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, ali_m5229_init);
-
-
diff --git a/arch/mips/pci/ops-mace.c b/arch/mips/pci/ops-mace.c
index e95881897ec..1cfb5588699 100644
--- a/arch/mips/pci/ops-mace.c
+++ b/arch/mips/pci/ops-mace.c
@@ -61,6 +61,13 @@ mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
/* ack possible master abort */
mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT;
mace->pci.control = control;
+ /*
+ * someone forgot to set the ultra bit for the onboard
+ * scsi chips; we fake it here
+ */
+ if (bus->number == 0 && reg == 0x40 && size == 4 &&
+ (devfn == (1 << 3) || devfn == (2 << 3)))
+ *val |= 0x1000;
DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val);
diff --git a/arch/mips/pci/ops-rc32434.c b/arch/mips/pci/ops-rc32434.c
new file mode 100644
index 00000000000..d1f8fa210ca
--- /dev/null
+++ b/arch/mips/pci/ops-rc32434.c
@@ -0,0 +1,207 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ * pci_ops for IDT EB434 board
+ *
+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
+ * Copyright 2006 Felix Fietkau <nbd@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+
+#include <asm/cpu.h>
+#include <asm/mach-rc32434/rc32434.h>
+#include <asm/mach-rc32434/pci.h>
+
+#define PCI_ACCESS_READ 0
+#define PCI_ACCESS_WRITE 1
+
+
+#define PCI_CFG_SET(bus, slot, func, off) \
+ (rc32434_pci->pcicfga = (0x80000000 | \
+ ((bus) << 16) | ((slot)<<11) | \
+ ((func)<<8) | (off)))
+
+static inline int config_access(unsigned char access_type,
+ struct pci_bus *bus, unsigned int devfn,
+ unsigned char where, u32 *data)
+{
+ unsigned int slot = PCI_SLOT(devfn);
+ u8 func = PCI_FUNC(devfn);
+
+ /* Setup address */
+ PCI_CFG_SET(bus->number, slot, func, where);
+ rc32434_sync();
+
+ if (access_type == PCI_ACCESS_WRITE)
+ rc32434_pci->pcicfgd = *data;
+ else
+ *data = rc32434_pci->pcicfgd;
+
+ rc32434_sync();
+
+ return 0;
+}
+
+
+/*
+ * We can't address 8 and 16 bit words directly. Instead we have to
+ * read/write a 32bit word and mask/modify the data we actually want.
+ */
+static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
+ int where, u8 *val)
+{
+ u32 data;
+ int ret;
+
+ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+ *val = (data >> ((where & 3) << 3)) & 0xff;
+ return ret;
+}
+
+static int read_config_word(struct pci_bus *bus, unsigned int devfn,
+ int where, u16 *val)
+{
+ u32 data;
+ int ret;
+
+ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+ *val = (data >> ((where & 3) << 3)) & 0xffff;
+ return ret;
+}
+
+static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
+ int where, u32 *val)
+{
+ int ret;
+ int delay = 1;
+
+ /*
+ * Don't scan too far, else there will be errors with plugged in
+ * daughterboard (rb564).
+ */
+ if (bus->number == 0 && PCI_SLOT(devfn) > 21)
+ return 0;
+
+retry:
+ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
+
+ /*
+ * Certain devices react delayed at device scan time, this
+ * gives them time to settle
+ */
+ if (where == PCI_VENDOR_ID) {
+ if (ret == 0xffffffff || ret == 0x00000000 ||
+ ret == 0x0000ffff || ret == 0xffff0000) {
+ if (delay > 4)
+ return 0;
+ delay *= 2;
+ msleep(delay);
+ goto retry;
+ }
+ }
+
+ return ret;
+}
+
+static int
+write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
+ u8 val)
+{
+ u32 data = 0;
+
+ if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+ return -1;
+
+ data = (data & ~(0xff << ((where & 3) << 3))) |
+ (val << ((where & 3) << 3));
+
+ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+ return -1;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+
+static int
+write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
+ u16 val)
+{
+ u32 data = 0;
+
+ if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+ return -1;
+
+ data = (data & ~(0xffff << ((where & 3) << 3))) |
+ (val << ((where & 3) << 3));
+
+ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+ return -1;
+
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+
+static int
+write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
+ u32 val)
+{
+ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
+ return -1;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ switch (size) {
+ case 1:
+ return read_config_byte(bus, devfn, where, (u8 *) val);
+ case 2:
+ return read_config_word(bus, devfn, where, (u16 *) val);
+ default:
+ return read_config_dword(bus, devfn, where, val);
+ }
+}
+
+static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ switch (size) {
+ case 1:
+ return write_config_byte(bus, devfn, where, (u8) val);
+ case 2:
+ return write_config_word(bus, devfn, where, (u16) val);
+ default:
+ return write_config_dword(bus, devfn, where, val);
+ }
+}
+
+struct pci_ops rc32434_pci_ops = {
+ .read = pci_config_read,
+ .write = pci_config_write,
+};
diff --git a/arch/mips/pci/ops-tx3927.c b/arch/mips/pci/ops-tx3927.c
index aa698bd0d5e..8a17a39e5bf 100644
--- a/arch/mips/pci/ops-tx3927.c
+++ b/arch/mips/pci/ops-tx3927.c
@@ -8,7 +8,7 @@
*
* Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
*
- * Define the pci_ops for JMR3927.
+ * Define the pci_ops for TX3927.
*
* Much of the code is derived from the original DDB5074 port by
* Geert Uytterhoeven <geert@sonycom.com>
@@ -39,7 +39,7 @@
#include <linux/init.h>
#include <asm/addrspace.h>
-#include <asm/jmr3927/jmr3927.h>
+#include <asm/txx9/tx3927.h>
static inline int mkaddr(unsigned char bus, unsigned char dev_fn,
unsigned char where)
@@ -68,7 +68,7 @@ static inline int check_abort(void)
return PCIBIOS_SUCCESSFUL;
}
-static int jmr3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+static int tx3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 * val)
{
int ret;
@@ -94,7 +94,7 @@ static int jmr3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
return check_abort();
}
-static int jmr3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+static int tx3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val)
{
int ret;
@@ -125,7 +125,80 @@ static int jmr3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
return check_abort();
}
-struct pci_ops jmr3927_pci_ops = {
- jmr3927_pci_read_config,
- jmr3927_pci_write_config,
+static struct pci_ops tx3927_pci_ops = {
+ .read = tx3927_pci_read_config,
+ .write = tx3927_pci_write_config,
};
+
+void __init tx3927_pcic_setup(struct pci_controller *channel,
+ unsigned long sdram_size, int extarb)
+{
+ unsigned long flags;
+ unsigned long io_base =
+ channel->io_resource->start + mips_io_port_base - IO_BASE;
+ unsigned long io_size =
+ channel->io_resource->end - channel->io_resource->start;
+ unsigned long io_pciaddr =
+ channel->io_resource->start - channel->io_offset;
+ unsigned long mem_base =
+ channel->mem_resource->start;
+ unsigned long mem_size =
+ channel->mem_resource->end - channel->mem_resource->start;
+ unsigned long mem_pciaddr =
+ channel->mem_resource->start - channel->mem_offset;
+
+ printk(KERN_INFO "TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s",
+ tx3927_pcicptr->did, tx3927_pcicptr->vid,
+ tx3927_pcicptr->rid,
+ extarb ? "External" : "Internal");
+ channel->pci_ops = &tx3927_pci_ops;
+
+ local_irq_save(flags);
+ /* Disable External PCI Config. Access */
+ tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
+#ifdef __BIG_ENDIAN
+ tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
+ TX3927_PCIC_LBC_TIBSE |
+ TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
+#endif
+ /* LB->PCI mappings */
+ tx3927_pcicptr->iomas = ~(io_size - 1);
+ tx3927_pcicptr->ilbioma = io_base;
+ tx3927_pcicptr->ipbioma = io_pciaddr;
+ tx3927_pcicptr->mmas = ~(mem_size - 1);
+ tx3927_pcicptr->ilbmma = mem_base;
+ tx3927_pcicptr->ipbmma = mem_pciaddr;
+ /* PCI->LB mappings */
+ tx3927_pcicptr->iobas = 0xffffffff;
+ tx3927_pcicptr->ioba = 0;
+ tx3927_pcicptr->tlbioma = 0;
+ tx3927_pcicptr->mbas = ~(sdram_size - 1);
+ tx3927_pcicptr->mba = 0;
+ tx3927_pcicptr->tlbmma = 0;
+ /* Enable Direct mapping Address Space Decoder */
+ tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
+
+ /* Clear All Local Bus Status */
+ tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
+ /* Enable All Local Bus Interrupts */
+ tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
+ /* Clear All PCI Status Error */
+ tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
+ /* Enable All PCI Status Error Interrupts */
+ tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
+
+ /* PCIC Int => IRC IRQ10 */
+ tx3927_pcicptr->il = TX3927_IR_PCI;
+ /* Target Control (per errata) */
+ tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
+
+ /* Enable Bus Arbiter */
+ if (!extarb)
+ tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
+
+ tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY |
+ PCI_COMMAND_IO |
+ PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
+ local_irq_restore(flags);
+}
diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c
index 150419c8b41..c6b49bccd27 100644
--- a/arch/mips/pci/ops-tx4927.c
+++ b/arch/mips/pci/ops-tx4927.c
@@ -1,209 +1,408 @@
/*
- * Copyright 2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * ahennessy@mvista.com
+ * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc.
*
- * Copyright (C) 2000-2001 Toshiba Corporation
- * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
- *
- * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
- *
- * Define the pci_ops for the Toshiba rbtx4927
- *
- * Much of the code is derived from the original DDB5074 port by
- * Geert Uytterhoeven <geert@sonycom.com>
- *
- * Copyright 2004 MontaVista Software Inc.
- * Author: Manish Lachwani (mlachwani@mvista.com)
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
+ * Based on linux/arch/mips/pci/ops-tx4938.c,
+ * linux/arch/mips/pci/fixup-rbtx4938.c,
+ * linux/arch/mips/txx9/rbtx4938/setup.c,
+ * and RBTX49xx patch from CELF patch archive.
*
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 2003-2005 (c) MontaVista Software, Inc.
+ * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
+ * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
*
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
*/
-#include <linux/types.h>
-#include <linux/pci.h>
#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include <asm/addrspace.h>
-#include <asm/byteorder.h>
-#include <asm/tx4927/tx4927_pci.h>
-
-/* initialize in setup */
-struct resource pci_io_resource = {
- .name = "TX4927 PCI IO SPACE",
- .start = 0x1000,
- .end = (0x1000 + (TX4927_PCIIO_SIZE)) - 1,
- .flags = IORESOURCE_IO
-};
+#include <asm/txx9/tx4927pcic.h>
-/* initialize in setup */
-struct resource pci_mem_resource = {
- .name = "TX4927 PCI MEM SPACE",
- .start = TX4927_PCIMEM,
- .end = TX4927_PCIMEM + TX4927_PCIMEM_SIZE - 1,
- .flags = IORESOURCE_MEM
-};
+static struct {
+ struct pci_controller *channel;
+ struct tx4927_pcic_reg __iomem *pcicptr;
+} pcicptrs[2]; /* TX4938 has 2 pcic */
+
+static void __init set_tx4927_pcicptr(struct pci_controller *channel,
+ struct tx4927_pcic_reg __iomem *pcicptr)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
+ if (pcicptrs[i].channel == channel) {
+ pcicptrs[i].pcicptr = pcicptr;
+ return;
+ }
+ }
+ for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
+ if (!pcicptrs[i].channel) {
+ pcicptrs[i].channel = channel;
+ pcicptrs[i].pcicptr = pcicptr;
+ return;
+ }
+ }
+ BUG();
+}
-static int mkaddr(int bus, int dev_fn, int where, int *flagsp)
+struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
+ struct pci_controller *channel)
{
- if (bus > 0) {
- /* Type 1 configuration */
- tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
- ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1;
- } else {
- if (dev_fn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0))
- return -1;
+ int i;
- /* Type 0 configuration */
- tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
- ((dev_fn & 0xff) << 0x08) | (where & 0xfc);
+ for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
+ if (pcicptrs[i].channel == channel)
+ return pcicptrs[i].pcicptr;
}
+ return NULL;
+}
+
+static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where,
+ struct tx4927_pcic_reg __iomem *pcicptr)
+{
+ if (bus->parent == NULL &&
+ devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0))
+ return -1;
+ __raw_writel(((bus->number & 0xff) << 0x10)
+ | ((devfn & 0xff) << 0x08) | (where & 0xfc)
+ | (bus->parent ? 1 : 0),
+ &pcicptr->g2pcfgadrs);
/* clear M_ABORT and Disable M_ABORT Int. */
- tx4927_pcicptr->pcistatus =
- (tx4927_pcicptr->pcistatus & 0x0000ffff) |
- (PCI_STATUS_REC_MASTER_ABORT << 16);
- tx4927_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT;
+ __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
+ | (PCI_STATUS_REC_MASTER_ABORT << 16),
+ &pcicptr->pcistatus);
return 0;
}
-static int check_abort(int flags)
+static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr)
{
int code = PCIBIOS_SUCCESSFUL;
- if (tx4927_pcicptr->
- pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
- tx4927_pcicptr->pcistatus =
- (tx4927_pcicptr->
- pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
- << 16);
- tx4927_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT;
+
+ /* wait write cycle completion before checking error status */
+ while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB)
+ ;
+ if (__raw_readl(&pcicptr->pcistatus)
+ & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
+ __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
+ | (PCI_STATUS_REC_MASTER_ABORT << 16),
+ &pcicptr->pcistatus);
code = PCIBIOS_DEVICE_NOT_FOUND;
}
return code;
}
-static int tx4927_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, int where,
- int size, u32 * val)
+static u8 icd_readb(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
+{
+#ifdef __BIG_ENDIAN
+ offset ^= 3;
+#endif
+ return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset);
+}
+static u16 icd_readw(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
+{
+#ifdef __BIG_ENDIAN
+ offset ^= 2;
+#endif
+ return __raw_readw((void __iomem *)&pcicptr->g2pcfgdata + offset);
+}
+static u32 icd_readl(struct tx4927_pcic_reg __iomem *pcicptr)
+{
+ return __raw_readl(&pcicptr->g2pcfgdata);
+}
+static void icd_writeb(u8 val, int offset,
+ struct tx4927_pcic_reg __iomem *pcicptr)
+{
+#ifdef __BIG_ENDIAN
+ offset ^= 3;
+#endif
+ __raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
+}
+static void icd_writew(u16 val, int offset,
+ struct tx4927_pcic_reg __iomem *pcicptr)
+{
+#ifdef __BIG_ENDIAN
+ offset ^= 2;
+#endif
+ __raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
+}
+static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr)
{
- int flags, retval, dev, busno, func;
+ __raw_writel(val, &pcicptr->g2pcfgdata);
+}
- busno = bus->number;
- dev = PCI_SLOT(devfn);
- func = PCI_FUNC(devfn);
+static struct tx4927_pcic_reg __iomem *pci_bus_to_pcicptr(struct pci_bus *bus)
+{
+ struct pci_controller *channel = bus->sysdata;
+ return get_tx4927_pcicptr(channel);
+}
- /* check if the bus is top-level */
- if (bus->parent != NULL) {
- busno = bus->number;
- } else {
- busno = 0;
- }
+static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
- if (mkaddr(busno, devfn, where, &flags))
+ if (mkaddr(bus, devfn, where, pcicptr)) {
+ *val = 0xffffffff;
return -1;
-
+ }
switch (size) {
case 1:
- *val = *(volatile u8 *) ((unsigned long) & tx4927_pcicptr->
- g2pcfgdata |
-#ifdef __LITTLE_ENDIAN
- (where & 3));
-#else
- ((where & 0x3) ^ 0x3));
-#endif
+ *val = icd_readb(where & 3, pcicptr);
break;
case 2:
- *val = *(volatile u16 *) ((unsigned long) & tx4927_pcicptr->
- g2pcfgdata |
-#ifdef __LITTLE_ENDIAN
- (where & 3));
-#else
- ((where & 0x3) ^ 0x2));
-#endif
- break;
- case 4:
- *val = tx4927_pcicptr->g2pcfgdata;
+ *val = icd_readw(where & 3, pcicptr);
break;
+ default:
+ *val = icd_readl(pcicptr);
}
+ return check_abort(pcicptr);
+}
- retval = check_abort(flags);
- if (retval == PCIBIOS_DEVICE_NOT_FOUND)
- *val = 0xffffffff;
+static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
- return retval;
+ if (mkaddr(bus, devfn, where, pcicptr))
+ return -1;
+ switch (size) {
+ case 1:
+ icd_writeb(val, where & 3, pcicptr);
+ break;
+ case 2:
+ icd_writew(val, where & 3, pcicptr);
+ break;
+ default:
+ icd_writel(val, pcicptr);
+ }
+ return check_abort(pcicptr);
}
-static int tx4927_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where,
- int size, u32 val)
+static struct pci_ops tx4927_pci_ops = {
+ .read = tx4927_pci_config_read,
+ .write = tx4927_pci_config_write,
+};
+
+static struct {
+ u8 trdyto;
+ u8 retryto;
+ u16 gbwc;
+} tx4927_pci_opts __devinitdata = {
+ .trdyto = 0,
+ .retryto = 0,
+ .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */
+};
+
+void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
+ struct pci_controller *channel, int extarb)
{
- int flags, dev, busno, func;
- busno = bus->number;
- dev = PCI_SLOT(devfn);
- func = PCI_FUNC(devfn);
+ int i;
+ unsigned long flags;
- /* check if the bus is top-level */
- if (bus->parent != NULL) {
- busno = bus->number;
- } else {
- busno = 0;
- }
+ set_tx4927_pcicptr(channel, pcicptr);
- if (mkaddr(busno, devfn, where, &flags))
- return -1;
+ if (!channel->pci_ops)
+ printk(KERN_INFO
+ "PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
+ __raw_readl(&pcicptr->pciid) >> 16,
+ __raw_readl(&pcicptr->pciid) & 0xffff,
+ __raw_readl(&pcicptr->pciccrev) & 0xff,
+ extarb ? "External" : "Internal");
+ channel->pci_ops = &tx4927_pci_ops;
- switch (size) {
- case 1:
- *(volatile u8 *) ((unsigned long) & tx4927_pcicptr->
- g2pcfgdata |
-#ifdef __LITTLE_ENDIAN
- (where & 3)) = val;
+ local_irq_save(flags);
+
+ /* Disable All Initiator Space */
+ __raw_writel(__raw_readl(&pcicptr->pciccfg)
+ & ~(TX4927_PCIC_PCICCFG_G2PMEN(0)
+ | TX4927_PCIC_PCICCFG_G2PMEN(1)
+ | TX4927_PCIC_PCICCFG_G2PMEN(2)
+ | TX4927_PCIC_PCICCFG_G2PIOEN),
+ &pcicptr->pciccfg);
+
+ /* GB->PCI mappings */
+ __raw_writel((channel->io_resource->end - channel->io_resource->start)
+ >> 4,
+ &pcicptr->g2piomask);
+ ____raw_writeq((channel->io_resource->start +
+ channel->io_map_base - IO_BASE) |
+#ifdef __BIG_ENDIAN
+ TX4927_PCIC_G2PIOGBASE_ECHG
#else
- ((where & 0x3) ^ 0x3)) = val;
+ TX4927_PCIC_G2PIOGBASE_BSDIS
#endif
- break;
-
- case 2:
- *(volatile u16 *) ((unsigned long) & tx4927_pcicptr->
- g2pcfgdata |
-#ifdef __LITTLE_ENDIAN
- (where & 3)) = val;
+ , &pcicptr->g2piogbase);
+ ____raw_writeq(channel->io_resource->start - channel->io_offset,
+ &pcicptr->g2piopbase);
+ for (i = 0; i < 3; i++) {
+ __raw_writel(0, &pcicptr->g2pmmask[i]);
+ ____raw_writeq(0, &pcicptr->g2pmgbase[i]);
+ ____raw_writeq(0, &pcicptr->g2pmpbase[i]);
+ }
+ if (channel->mem_resource->end) {
+ __raw_writel((channel->mem_resource->end
+ - channel->mem_resource->start) >> 4,
+ &pcicptr->g2pmmask[0]);
+ ____raw_writeq(channel->mem_resource->start |
+#ifdef __BIG_ENDIAN
+ TX4927_PCIC_G2PMnGBASE_ECHG
#else
- ((where & 0x3) ^ 0x2)) = val;
+ TX4927_PCIC_G2PMnGBASE_BSDIS
#endif
- break;
- case 4:
- tx4927_pcicptr->g2pcfgdata = val;
- break;
+ , &pcicptr->g2pmgbase[0]);
+ ____raw_writeq(channel->mem_resource->start -
+ channel->mem_offset,
+ &pcicptr->g2pmpbase[0]);
+ }
+ /* PCI->GB mappings (I/O 256B) */
+ __raw_writel(0, &pcicptr->p2giopbase); /* 256B */
+ ____raw_writeq(0, &pcicptr->p2giogbase);
+ /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
+ __raw_writel(0, &pcicptr->p2gm0plbase);
+ __raw_writel(0, &pcicptr->p2gm0pubase);
+ ____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN |
+#ifdef __BIG_ENDIAN
+ TX4927_PCIC_P2GMnGBASE_TECHG
+#else
+ TX4927_PCIC_P2GMnGBASE_TBSDIS
+#endif
+ , &pcicptr->p2gmgbase[0]);
+ /* PCI->GB mappings (MEM 16MB) */
+ __raw_writel(0xffffffff, &pcicptr->p2gm1plbase);
+ __raw_writel(0xffffffff, &pcicptr->p2gm1pubase);
+ ____raw_writeq(0, &pcicptr->p2gmgbase[1]);
+ /* PCI->GB mappings (MEM 1MB) */
+ __raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */
+ ____raw_writeq(0, &pcicptr->p2gmgbase[2]);
+
+ /* Clear all (including IRBER) except for GBWC */
+ __raw_writel((tx4927_pci_opts.gbwc << 16)
+ & TX4927_PCIC_PCICCFG_GBWC_MASK,
+ &pcicptr->pciccfg);
+ /* Enable Initiator Memory Space */
+ if (channel->mem_resource->end)
+ __raw_writel(__raw_readl(&pcicptr->pciccfg)
+ | TX4927_PCIC_PCICCFG_G2PMEN(0),
+ &pcicptr->pciccfg);
+ /* Enable Initiator I/O Space */
+ if (channel->io_resource->end)
+ __raw_writel(__raw_readl(&pcicptr->pciccfg)
+ | TX4927_PCIC_PCICCFG_G2PIOEN,
+ &pcicptr->pciccfg);
+ /* Enable Initiator Config */
+ __raw_writel(__raw_readl(&pcicptr->pciccfg)
+ | TX4927_PCIC_PCICCFG_ICAEN | TX4927_PCIC_PCICCFG_TCAR,
+ &pcicptr->pciccfg);
+
+ /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
+ __raw_writel(0, &pcicptr->pcicfg1);
+
+ __raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff)
+ | (tx4927_pci_opts.trdyto & 0xff)
+ | ((tx4927_pci_opts.retryto & 0xff) << 8),
+ &pcicptr->g2ptocnt);
+
+ /* Clear All Local Bus Status */
+ __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
+ /* Enable All Local Bus Interrupts */
+ __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask);
+ /* Clear All Initiator Status */
+ __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
+ /* Enable All Initiator Interrupts */
+ __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask);
+ /* Clear All PCI Status Error */
+ __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
+ | (TX4927_PCIC_PCISTATUS_ALL << 16),
+ &pcicptr->pcistatus);
+ /* Enable All PCI Status Error Interrupts */
+ __raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask);
+
+ if (!extarb) {
+ /* Reset Bus Arbiter */
+ __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
+ __raw_writel(0, &pcicptr->pbabm);
+ /* Enable Bus Arbiter */
+ __raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg);
}
- return check_abort(flags);
+ __raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
+ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
+ &pcicptr->pcistatus);
+ local_irq_restore(flags);
+
+ printk(KERN_DEBUG
+ "PCI: COMMAND=%04x,PCIMASK=%04x,"
+ "TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n",
+ __raw_readl(&pcicptr->pcistatus) & 0xffff,
+ __raw_readl(&pcicptr->pcimask) & 0xffff,
+ __raw_readl(&pcicptr->g2ptocnt) & 0xff,
+ (__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8,
+ (__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff);
}
-struct pci_ops tx4927_pci_ops = {
- tx4927_pcibios_read_config,
- tx4927_pcibios_write_config
-};
+static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem *pcicptr)
+{
+ __u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16);
+ __u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus);
+ __u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus);
+ static struct {
+ __u32 flag;
+ const char *str;
+ } pcistat_tbl[] = {
+ { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
+ { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
+ { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
+ { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
+ { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
+ { PCI_STATUS_PARITY, "MasterParityError" },
+ }, g2pstat_tbl[] = {
+ { TX4927_PCIC_G2PSTATUS_TTOE, "TIOE" },
+ { TX4927_PCIC_G2PSTATUS_RTOE, "RTOE" },
+ }, pcicstat_tbl[] = {
+ { TX4927_PCIC_PCICSTATUS_PME, "PME" },
+ { TX4927_PCIC_PCICSTATUS_TLB, "TLB" },
+ { TX4927_PCIC_PCICSTATUS_NIB, "NIB" },
+ { TX4927_PCIC_PCICSTATUS_ZIB, "ZIB" },
+ { TX4927_PCIC_PCICSTATUS_PERR, "PERR" },
+ { TX4927_PCIC_PCICSTATUS_SERR, "SERR" },
+ { TX4927_PCIC_PCICSTATUS_GBE, "GBE" },
+ { TX4927_PCIC_PCICSTATUS_IWB, "IWB" },
+ };
+ int i, cont;
-/*
- * h/w only supports devices 0x00 to 0x14
- */
-struct pci_controller tx4927_controller = {
- .pci_ops = &tx4927_pci_ops,
- .io_resource = &pci_io_resource,
- .mem_resource = &pci_mem_resource,
-};
+ printk(KERN_ERR "");
+ if (pcistatus & TX4927_PCIC_PCISTATUS_ALL) {
+ printk(KERN_CONT "pcistat:%04x(", pcistatus);
+ for (i = 0, cont = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
+ if (pcistatus & pcistat_tbl[i].flag)
+ printk(KERN_CONT "%s%s",
+ cont++ ? " " : "", pcistat_tbl[i].str);
+ printk(KERN_CONT ") ");
+ }
+ if (g2pstatus & TX4927_PCIC_G2PSTATUS_ALL) {
+ printk(KERN_CONT "g2pstatus:%08x(", g2pstatus);
+ for (i = 0, cont = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
+ if (g2pstatus & g2pstat_tbl[i].flag)
+ printk(KERN_CONT "%s%s",
+ cont++ ? " " : "", g2pstat_tbl[i].str);
+ printk(KERN_CONT ") ");
+ }
+ if (pcicstatus & TX4927_PCIC_PCICSTATUS_ALL) {
+ printk(KERN_CONT "pcicstatus:%08x(", pcicstatus);
+ for (i = 0, cont = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
+ if (pcicstatus & pcicstat_tbl[i].flag)
+ printk(KERN_CONT "%s%s",
+ cont++ ? " " : "", pcicstat_tbl[i].str);
+ printk(KERN_CONT ")");
+ }
+ printk(KERN_CONT "\n");
+}
+
+void tx4927_report_pcic_status(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
+ if (pcicptrs[i].pcicptr)
+ tx4927_report_pcic_status1(pcicptrs[i].pcicptr);
+ }
+}
diff --git a/arch/mips/pci/ops-tx4938.c b/arch/mips/pci/ops-tx4938.c
deleted file mode 100644
index a450c406203..00000000000
--- a/arch/mips/pci/ops-tx4938.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Define the pci_ops for the Toshiba rbtx4938
- * Copyright (C) 2000-2001 Toshiba Corporation
- *
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
- */
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include <asm/addrspace.h>
-#include <asm/tx4938/rbtx4938.h>
-
-/* initialize in setup */
-struct resource pci_io_resource = {
- .name = "pci IO space",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_IO
-};
-
-/* initialize in setup */
-struct resource pci_mem_resource = {
- .name = "pci memory space",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_MEM
-};
-
-struct resource tx4938_pcic1_pci_io_resource = {
- .name = "PCI1 IO",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_IO
-};
-struct resource tx4938_pcic1_pci_mem_resource = {
- .name = "PCI1 mem",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_MEM
-};
-
-static int mkaddr(int bus, int dev_fn, int where,
- struct tx4938_pcic_reg *pcicptr)
-{
- if (bus > 0) {
- /* Type 1 configuration */
- pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
- ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1;
- } else {
- if (dev_fn >= PCI_DEVFN(TX4938_PCIC_MAX_DEVNU, 0))
- return -1;
-
- /* Type 0 configuration */
- pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
- ((dev_fn & 0xff) << 0x08) | (where & 0xfc);
- }
- /* clear M_ABORT and Disable M_ABORT Int. */
- pcicptr->pcistatus =
- (pcicptr->pcistatus & 0x0000ffff) |
- (PCI_STATUS_REC_MASTER_ABORT << 16);
- pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT;
-
- return 0;
-}
-
-static int check_abort(struct tx4938_pcic_reg *pcicptr)
-{
- int code = PCIBIOS_SUCCESSFUL;
- /* wait write cycle completion before checking error status */
- while (pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB)
- ;
- if (pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
- pcicptr->pcistatus =
- (pcicptr->
- pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
- << 16);
- pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT;
- code = PCIBIOS_DEVICE_NOT_FOUND;
- }
- return code;
-}
-
-extern struct pci_controller tx4938_pci_controller[];
-extern struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch);
-
-static struct tx4938_pcic_reg *pci_bus_to_pcicptr(struct pci_bus *bus)
-{
- struct pci_controller *channel = bus->sysdata;
- return get_tx4938_pcicptr(channel - &tx4938_pci_controller[0]);
-}
-
-static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 * val)
-{
- int retval, dev, busno, func;
- struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus);
- void __iomem *cfgdata =
- (void __iomem *)(unsigned long)&pcicptr->g2pcfgdata;
-
- dev = PCI_SLOT(devfn);
- func = PCI_FUNC(devfn);
-
- /* check if the bus is top-level */
- if (bus->parent != NULL)
- busno = bus->number;
- else {
- busno = 0;
- }
-
- if (mkaddr(busno, devfn, where, pcicptr))
- return -1;
-
- switch (size) {
- case 1:
-#ifdef __BIG_ENDIAN
- cfgdata += (where & 3) ^ 3;
-#else
- cfgdata += where & 3;
-#endif
- *val = __raw_readb(cfgdata);
- break;
- case 2:
-#ifdef __BIG_ENDIAN
- cfgdata += (where & 2) ^ 2;
-#else
- cfgdata += where & 2;
-#endif
- *val = __raw_readw(cfgdata);
- break;
- case 4:
- *val = __raw_readl(cfgdata);
- break;
- }
-
- retval = check_abort(pcicptr);
- if (retval == PCIBIOS_DEVICE_NOT_FOUND)
- *val = 0xffffffff;
-
- return retval;
-}
-
-static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where,
- int size, u32 val)
-{
- int dev, busno, func;
- struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus);
- void __iomem *cfgdata =
- (void __iomem *)(unsigned long)&pcicptr->g2pcfgdata;
-
- busno = bus->number;
- dev = PCI_SLOT(devfn);
- func = PCI_FUNC(devfn);
-
- /* check if the bus is top-level */
- if (bus->parent != NULL) {
- busno = bus->number;
- } else {
- busno = 0;
- }
-
- if (mkaddr(busno, devfn, where, pcicptr))
- return -1;
-
- switch (size) {
- case 1:
-#ifdef __BIG_ENDIAN
- cfgdata += (where & 3) ^ 3;
-#else
- cfgdata += where & 3;
-#endif
- __raw_writeb(val, cfgdata);
- break;
- case 2:
-#ifdef __BIG_ENDIAN
- cfgdata += (where & 2) ^ 2;
-#else
- cfgdata += where & 2;
-#endif
- __raw_writew(val, cfgdata);
- break;
- case 4:
- __raw_writel(val, cfgdata);
- break;
- }
-
- return check_abort(pcicptr);
-}
-
-struct pci_ops tx4938_pci_ops = {
- tx4938_pcibios_read_config,
- tx4938_pcibios_write_config
-};
-
-struct pci_controller tx4938_pci_controller[] = {
- /* h/w only supports devices 0x00 to 0x14 */
- {
- .pci_ops = &tx4938_pci_ops,
- .io_resource = &pci_io_resource,
- .mem_resource = &pci_mem_resource,
- },
- /* h/w only supports devices 0x00 to 0x14 */
- {
- .pci_ops = &tx4938_pci_ops,
- .io_resource = &tx4938_pcic1_pci_io_resource,
- .mem_resource = &tx4938_pcic1_pci_mem_resource,
- }
-};
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index 87e2c8f54e2..a9060c77184 100644
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -202,7 +202,6 @@ static int __init bcm1480_pcibios_init(void)
{
uint32_t cmdreg;
uint64_t reg;
- extern int pci_probe_only;
/* CFE will assign PCI resources */
pci_probe_only = 1;
@@ -254,8 +253,6 @@ static int __init bcm1480_pcibios_init(void)
ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536);
bcm1480_controller.io_map_base -= bcm1480_controller.io_offset;
set_io_port_base(bcm1480_controller.io_map_base);
- isa_slot_offset = (unsigned long)
- ioremap(A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, 1024*1024);
register_pci_controller(&bcm1480_controller);
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index a18516925cd..ce92f82b16d 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -47,7 +47,6 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
static int num_bridges = 0;
bridge_t *bridge;
int slot;
- extern int pci_probe_only;
pci_probe_only = 1;
diff --git a/arch/mips/pci/pci-lasat.c b/arch/mips/pci/pci-lasat.c
index e70ae3236e0..a98e543a514 100644
--- a/arch/mips/pci/pci-lasat.c
+++ b/arch/mips/pci/pci-lasat.c
@@ -10,7 +10,7 @@
#include <linux/pci.h>
#include <linux/types.h>
-#include <asm/bootinfo.h>
+#include <asm/lasat/lasat.h>
#include <irq.h>
@@ -39,16 +39,10 @@ static int __init lasat_pci_setup(void)
{
printk(KERN_DEBUG "PCI: starting\n");
- switch (mips_machtype) {
- case MACH_LASAT_100:
- lasat_pci_controller.pci_ops = &gt64xxx_pci0_ops;
- break;
- case MACH_LASAT_200:
+ if (IS_LASAT_200())
lasat_pci_controller.pci_ops = &nile4_pci_ops;
- break;
- default:
- panic("pcibios_init: mips_machtype incorrect");
- }
+ else
+ lasat_pci_controller.pci_ops = &gt64xxx_pci0_ops;
register_pci_controller(&lasat_pci_controller);
diff --git a/arch/mips/pci/pci-rc32434.c b/arch/mips/pci/pci-rc32434.c
new file mode 100644
index 00000000000..1c2821e2f49
--- /dev/null
+++ b/arch/mips/pci/pci-rc32434.c
@@ -0,0 +1,221 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ * PCI initialization for IDT EB434 board
+ *
+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/mach-rc32434/rc32434.h>
+#include <asm/mach-rc32434/pci.h>
+
+#define PCI_ACCESS_READ 0
+#define PCI_ACCESS_WRITE 1
+
+/* define an unsigned array for the PCI registers */
+static unsigned int korina_cnfg_regs[25] = {
+ KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
+ KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
+ KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
+ KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
+ KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
+ KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
+};
+static struct resource rc32434_res_pci_mem1;
+static struct resource rc32434_res_pci_mem2;
+
+static struct resource rc32434_res_pci_mem1 = {
+ .name = "PCI MEM1",
+ .start = 0x50000000,
+ .end = 0x5FFFFFFF,
+ .flags = IORESOURCE_MEM,
+ .parent = &rc32434_res_pci_mem1,
+ .sibling = NULL,
+ .child = &rc32434_res_pci_mem2
+};
+
+static struct resource rc32434_res_pci_mem2 = {
+ .name = "PCI Mem2",
+ .start = 0x60000000,
+ .end = 0x6FFFFFFF,
+ .flags = IORESOURCE_MEM,
+ .parent = &rc32434_res_pci_mem1,
+ .sibling = NULL,
+ .child = NULL
+};
+
+static struct resource rc32434_res_pci_io1 = {
+ .name = "PCI I/O1",
+ .start = 0x18800000,
+ .end = 0x188FFFFF,
+ .flags = IORESOURCE_IO,
+};
+
+extern struct pci_ops rc32434_pci_ops;
+
+#define PCI_MEM1_START PCI_ADDR_START
+#define PCI_MEM1_END (PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1)
+#define PCI_MEM2_START (PCI_ADDR_START + CPUTOPCI_MEM_WIN)
+#define PCI_MEM2_END (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) - 1)
+#define PCI_IO1_START (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN))
+#define PCI_IO1_END \
+ (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN - 1)
+#define PCI_IO2_START \
+ (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN)
+#define PCI_IO2_END \
+ (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) - 1)
+
+struct pci_controller rc32434_controller2;
+
+struct pci_controller rc32434_controller = {
+ .pci_ops = &rc32434_pci_ops,
+ .mem_resource = &rc32434_res_pci_mem1,
+ .io_resource = &rc32434_res_pci_io1,
+ .mem_offset = 0,
+ .io_offset = 0,
+
+};
+
+#ifdef __MIPSEB__
+#define PCI_ENDIAN_FLAG PCILBAC_sb_m
+#else
+#define PCI_ENDIAN_FLAG 0
+#endif
+
+static int __init rc32434_pcibridge_init(void)
+{
+ unsigned int pcicvalue, pcicdata = 0;
+ unsigned int dummyread, pcicntlval;
+ int loopCount;
+ unsigned int pci_config_addr;
+
+ pcicvalue = rc32434_pci->pcic;
+ pcicvalue = (pcicvalue >> PCIM_SHFT) & PCIM_BIT_LEN;
+ if (!((pcicvalue == PCIM_H_EA) ||
+ (pcicvalue == PCIM_H_IA_FIX) ||
+ (pcicvalue == PCIM_H_IA_RR))) {
+ pr_err(KERN_ERR "PCI init error!!!\n");
+ /* Not in Host Mode, return ERROR */
+ return -1;
+ }
+ /* Enables the Idle Grant mode, Arbiter Parking */
+ pcicdata |= (PCI_CTL_IGM | PCI_CTL_EAP | PCI_CTL_EN);
+ rc32434_pci->pcic = pcicdata; /* Enable the PCI bus Interface */
+ /* Zero out the PCI status & PCI Status Mask */
+ for (;;) {
+ pcicdata = rc32434_pci->pcis;
+ if (!(pcicdata & PCI_STAT_RIP))
+ break;
+ }
+
+ rc32434_pci->pcis = 0;
+ rc32434_pci->pcism = 0xFFFFFFFF;
+ /* Zero out the PCI decoupled registers */
+ rc32434_pci->pcidac = 0; /*
+ * disable PCI decoupled accesses at
+ * initialization
+ */
+ rc32434_pci->pcidas = 0; /* clear the status */
+ rc32434_pci->pcidasm = 0x0000007F; /* Mask all the interrupts */
+ /* Mask PCI Messaging Interrupts */
+ rc32434_pci_msg->pciiic = 0;
+ rc32434_pci_msg->pciiim = 0xFFFFFFFF;
+ rc32434_pci_msg->pciioic = 0;
+ rc32434_pci_msg->pciioim = 0;
+
+
+ /* Setup PCILB0 as Memory Window */
+ rc32434_pci->pcilba[0].address = (unsigned int) (PCI_ADDR_START);
+
+ /* setup the PCI map address as same as the local address */
+
+ rc32434_pci->pcilba[0].mapping = (unsigned int) (PCI_ADDR_START);
+
+
+ /* Setup PCILBA1 as MEM */
+ rc32434_pci->pcilba[0].control =
+ (((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
+ dummyread = rc32434_pci->pcilba[0].control; /* flush the CPU write Buffers */
+ rc32434_pci->pcilba[1].address = 0x60000000;
+ rc32434_pci->pcilba[1].mapping = 0x60000000;
+
+ /* setup PCILBA2 as IO Window */
+ rc32434_pci->pcilba[1].control =
+ (((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
+ dummyread = rc32434_pci->pcilba[1].control; /* flush the CPU write Buffers */
+ rc32434_pci->pcilba[2].address = 0x18C00000;
+ rc32434_pci->pcilba[2].mapping = 0x18FFFFFF;
+
+ /* setup PCILBA2 as IO Window */
+ rc32434_pci->pcilba[2].control =
+ (((SIZE_4MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
+ dummyread = rc32434_pci->pcilba[2].control; /* flush the CPU write Buffers */
+
+ /* Setup PCILBA3 as IO Window */
+ rc32434_pci->pcilba[3].address = 0x18800000;
+ rc32434_pci->pcilba[3].mapping = 0x18800000;
+ rc32434_pci->pcilba[3].control =
+ ((((SIZE_1MB & 0x1ff) << PCI_LBAC_SIZE_BIT) | PCI_LBAC_MSI) |
+ PCI_ENDIAN_FLAG);
+ dummyread = rc32434_pci->pcilba[3].control; /* flush the CPU write Buffers */
+
+ pci_config_addr = (unsigned int) (0x80000004);
+ for (loopCount = 0; loopCount < 24; loopCount++) {
+ rc32434_pci->pcicfga = pci_config_addr;
+ dummyread = rc32434_pci->pcicfga;
+ rc32434_pci->pcicfgd = korina_cnfg_regs[loopCount];
+ dummyread = rc32434_pci->pcicfgd;
+ pci_config_addr += 4;
+ }
+ rc32434_pci->pcitc =
+ (unsigned int) ((PCITC_RTIMER_VAL & 0xff) << PCI_TC_RTIMER_BIT) |
+ ((PCITC_DTIMER_VAL & 0xff) << PCI_TC_DTIMER_BIT);
+
+ pcicntlval = rc32434_pci->pcic;
+ pcicntlval &= ~PCI_CTL_TNR;
+ rc32434_pci->pcic = pcicntlval;
+ pcicntlval = rc32434_pci->pcic;
+
+ return 0;
+}
+
+static int __init rc32434_pci_init(void)
+{
+ pr_info("PCI: Initializing PCI\n");
+
+ ioport_resource.start = rc32434_res_pci_io1.start;
+ ioport_resource.end = rc32434_res_pci_io1.end;
+
+ rc32434_pcibridge_init();
+
+ register_pci_controller(&rc32434_controller);
+ rc32434_sync();
+
+ return 0;
+}
+
+arch_initcall(rc32434_pci_init);
diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index 2a09ad91ec8..bf639590b8b 100644
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -210,7 +210,6 @@ static int __init sb1250_pcibios_init(void)
void __iomem *io_map_base;
uint32_t cmdreg;
uint64_t reg;
- extern int pci_probe_only;
/* CFE will assign PCI resources */
pci_probe_only = 1;
@@ -254,9 +253,6 @@ static int __init sb1250_pcibios_init(void)
* works correctly with most of Linux's drivers.
* XXX ehs: Should this happen in PCI Device mode?
*/
- isa_slot_offset = (unsigned long)
- ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 1024 * 1024);
-
io_map_base = ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 1024 * 1024);
sb1250_controller.io_map_base = io_map_base;
set_io_port_base((unsigned long)io_map_base);
diff --git a/arch/mips/pci/pci-tx4927.c b/arch/mips/pci/pci-tx4927.c
new file mode 100644
index 00000000000..27e86a09dd4
--- /dev/null
+++ b/arch/mips/pci/pci-tx4927.c
@@ -0,0 +1,83 @@
+/*
+ * linux/arch/mips/pci/pci-tx4927.c
+ *
+ * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
+ * and RBTX49xx patch from CELF patch archive.
+ *
+ * Copyright 2001, 2003-2005 MontaVista Software Inc.
+ * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
+ * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <asm/txx9/generic.h>
+#include <asm/txx9/tx4927.h>
+
+int __init tx4927_report_pciclk(void)
+{
+ int pciclk = 0;
+
+ printk(KERN_INFO "PCIC --%s PCICLK:",
+ (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) ?
+ " PCI66" : "");
+ if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) {
+ u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg);
+ switch ((unsigned long)ccfg &
+ TX4927_CCFG_PCIDIVMODE_MASK) {
+ case TX4927_CCFG_PCIDIVMODE_2_5:
+ pciclk = txx9_cpu_clock * 2 / 5; break;
+ case TX4927_CCFG_PCIDIVMODE_3:
+ pciclk = txx9_cpu_clock / 3; break;
+ case TX4927_CCFG_PCIDIVMODE_5:
+ pciclk = txx9_cpu_clock / 5; break;
+ case TX4927_CCFG_PCIDIVMODE_6:
+ pciclk = txx9_cpu_clock / 6; break;
+ }
+ printk("Internal(%u.%uMHz)",
+ (pciclk + 50000) / 1000000,
+ ((pciclk + 50000) / 100000) % 10);
+ } else {
+ printk("External");
+ pciclk = -1;
+ }
+ printk("\n");
+ return pciclk;
+}
+
+int __init tx4927_pciclk66_setup(void)
+{
+ int pciclk;
+
+ /* Assert M66EN */
+ tx4927_ccfg_set(TX4927_CCFG_PCI66);
+ /* Double PCICLK (if possible) */
+ if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) {
+ unsigned int pcidivmode = 0;
+ u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg);
+ pcidivmode = (unsigned long)ccfg &
+ TX4927_CCFG_PCIDIVMODE_MASK;
+ switch (pcidivmode) {
+ case TX4927_CCFG_PCIDIVMODE_5:
+ case TX4927_CCFG_PCIDIVMODE_2_5:
+ pcidivmode = TX4927_CCFG_PCIDIVMODE_2_5;
+ pciclk = txx9_cpu_clock * 2 / 5;
+ break;
+ case TX4927_CCFG_PCIDIVMODE_6:
+ case TX4927_CCFG_PCIDIVMODE_3:
+ default:
+ pcidivmode = TX4927_CCFG_PCIDIVMODE_3;
+ pciclk = txx9_cpu_clock / 3;
+ }
+ tx4927_ccfg_change(TX4927_CCFG_PCIDIVMODE_MASK,
+ pcidivmode);
+ printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
+ (unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg));
+ } else
+ pciclk = -1;
+ return pciclk;
+}
diff --git a/arch/mips/pci/pci-tx4938.c b/arch/mips/pci/pci-tx4938.c
new file mode 100644
index 00000000000..e5375511c2b
--- /dev/null
+++ b/arch/mips/pci/pci-tx4938.c
@@ -0,0 +1,134 @@
+/*
+ * linux/arch/mips/pci/pci-tx4938.c
+ *
+ * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
+ * and RBTX49xx patch from CELF patch archive.
+ *
+ * Copyright 2001, 2003-2005 MontaVista Software Inc.
+ * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
+ * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <asm/txx9/generic.h>
+#include <asm/txx9/tx4938.h>
+
+int __init tx4938_report_pciclk(void)
+{
+ int pciclk = 0;
+
+ printk(KERN_INFO "PCIC --%s PCICLK:",
+ (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) ?
+ " PCI66" : "");
+ if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) {
+ u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
+ switch ((unsigned long)ccfg &
+ TX4938_CCFG_PCIDIVMODE_MASK) {
+ case TX4938_CCFG_PCIDIVMODE_4:
+ pciclk = txx9_cpu_clock / 4; break;
+ case TX4938_CCFG_PCIDIVMODE_4_5:
+ pciclk = txx9_cpu_clock * 2 / 9; break;
+ case TX4938_CCFG_PCIDIVMODE_5:
+ pciclk = txx9_cpu_clock / 5; break;
+ case TX4938_CCFG_PCIDIVMODE_5_5:
+ pciclk = txx9_cpu_clock * 2 / 11; break;
+ case TX4938_CCFG_PCIDIVMODE_8:
+ pciclk = txx9_cpu_clock / 8; break;
+ case TX4938_CCFG_PCIDIVMODE_9:
+ pciclk = txx9_cpu_clock / 9; break;
+ case TX4938_CCFG_PCIDIVMODE_10:
+ pciclk = txx9_cpu_clock / 10; break;
+ case TX4938_CCFG_PCIDIVMODE_11:
+ pciclk = txx9_cpu_clock / 11; break;
+ }
+ printk("Internal(%u.%uMHz)",
+ (pciclk + 50000) / 1000000,
+ ((pciclk + 50000) / 100000) % 10);
+ } else {
+ printk("External");
+ pciclk = -1;
+ }
+ printk("\n");
+ return pciclk;
+}
+
+void __init tx4938_report_pci1clk(void)
+{
+ __u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
+ unsigned int pciclk =
+ txx9_gbus_clock / ((ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2);
+
+ printk(KERN_INFO "PCIC1 -- %sPCICLK:%u.%uMHz\n",
+ (ccfg & TX4938_CCFG_PCI1_66) ? "PCI66 " : "",
+ (pciclk + 50000) / 1000000,
+ ((pciclk + 50000) / 100000) % 10);
+}
+
+int __init tx4938_pciclk66_setup(void)
+{
+ int pciclk;
+
+ /* Assert M66EN */
+ tx4938_ccfg_set(TX4938_CCFG_PCI66);
+ /* Double PCICLK (if possible) */
+ if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) {
+ unsigned int pcidivmode = 0;
+ u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
+ pcidivmode = (unsigned long)ccfg &
+ TX4938_CCFG_PCIDIVMODE_MASK;
+ switch (pcidivmode) {
+ case TX4938_CCFG_PCIDIVMODE_8:
+ case TX4938_CCFG_PCIDIVMODE_4:
+ pcidivmode = TX4938_CCFG_PCIDIVMODE_4;
+ pciclk = txx9_cpu_clock / 4;
+ break;
+ case TX4938_CCFG_PCIDIVMODE_9:
+ case TX4938_CCFG_PCIDIVMODE_4_5:
+ pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5;
+ pciclk = txx9_cpu_clock * 2 / 9;
+ break;
+ case TX4938_CCFG_PCIDIVMODE_10:
+ case TX4938_CCFG_PCIDIVMODE_5:
+ pcidivmode = TX4938_CCFG_PCIDIVMODE_5;
+ pciclk = txx9_cpu_clock / 5;
+ break;
+ case TX4938_CCFG_PCIDIVMODE_11:
+ case TX4938_CCFG_PCIDIVMODE_5_5:
+ default:
+ pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5;
+ pciclk = txx9_cpu_clock * 2 / 11;
+ break;
+ }
+ tx4938_ccfg_change(TX4938_CCFG_PCIDIVMODE_MASK,
+ pcidivmode);
+ printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
+ (unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg));
+ } else
+ pciclk = -1;
+ return pciclk;
+}
+
+int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
+{
+ if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4938_pcic1ptr) {
+ switch (slot) {
+ case TX4927_PCIC_IDSEL_AD_TO_SLOT(31):
+ if (__raw_readq(&tx4938_ccfgptr->pcfg) &
+ TX4938_PCFG_ETH0_SEL)
+ return TXX9_IRQ_BASE + TX4938_IR_ETH0;
+ break;
+ case TX4927_PCIC_IDSEL_AD_TO_SLOT(30):
+ if (__raw_readq(&tx4938_ccfgptr->pcfg) &
+ TX4938_PCFG_ETH1_SEL)
+ return TXX9_IRQ_BASE + TX4938_IR_ETH1;
+ break;
+ }
+ return 0;
+ }
+ return -1;
+}
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 358ad621094..77bd5b68dc4 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -29,8 +29,7 @@ unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
* The PCI controller list.
*/
-struct pci_controller *hose_head, **hose_tail = &hose_head;
-struct pci_controller *pci_isa_hose;
+static struct pci_controller *hose_head, **hose_tail = &hose_head;
unsigned long PCIBIOS_MIN_IO = 0x0000;
unsigned long PCIBIOS_MIN_MEM = 0;
@@ -205,7 +204,7 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask)
* If we set up a device for bus mastering, we need to check the latency
* timer as certain crappy BIOSes forget to set it properly.
*/
-unsigned int pcibios_max_latency = 255;
+static unsigned int pcibios_max_latency = 255;
void pcibios_set_master(struct pci_dev *dev)
{
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2024-11-16 13:36:02 +0000