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Diffstat (limited to 'arch/powerpc/boot/dts/mpc8610_hpcd.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8610_hpcd.dts30
1 files changed, 22 insertions, 8 deletions
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index 08a780d8980..981941e5d7a 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -172,14 +172,28 @@
};
mpic: interrupt-controller@40000 {
- clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
- big-endian;
+ };
+
+ msi@41600 {
+ compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
};
global-utilities@e0000 {
@@ -251,14 +265,14 @@
dma@c300 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma";
+ compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
cell-index = <1>;
reg = <0xc300 0x4>; /* DMA general status register */
ranges = <0x0 0xc100 0x200>;
dma-channel@0 {
compatible = "fsl,mpc8610-dma-channel",
- "fsl,mpc8540-dma-channel";
+ "fsl,eloplus-dma-channel";
cell-index = <0>;
reg = <0x0 0x80>;
interrupt-parent = <&mpic>;
@@ -266,7 +280,7 @@
};
dma-channel@1 {
compatible = "fsl,mpc8610-dma-channel",
- "fsl,mpc8540-dma-channel";
+ "fsl,eloplus-dma-channel";
cell-index = <1>;
reg = <0x80 0x80>;
interrupt-parent = <&mpic>;
@@ -274,7 +288,7 @@
};
dma-channel@2 {
compatible = "fsl,mpc8610-dma-channel",
- "fsl,mpc8540-dma-channel";
+ "fsl,eloplus-dma-channel";
cell-index = <2>;
reg = <0x100 0x80>;
interrupt-parent = <&mpic>;
@@ -282,7 +296,7 @@
};
dma-channel@3 {
compatible = "fsl,mpc8610-dma-channel",
- "fsl,mpc8540-dma-channel";
+ "fsl,eloplus-dma-channel";
cell-index = <3>;
reg = <0x180 0x80>;
interrupt-parent = <&mpic>;
@@ -349,7 +363,7 @@
0xe000 0 0 4 &mpic 1 1
/* IDSEL 0x1f */
- 0xf800 0 0 1 &mpic 3 0
+ 0xf800 0 0 1 &mpic 3 2
0xf800 0 0 2 &mpic 0 1
>;