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-rw-r--r--arch/powerpc/boot/.gitignore9
-rw-r--r--arch/powerpc/boot/44x.c85
-rw-r--r--arch/powerpc/boot/44x.h5
-rw-r--r--arch/powerpc/boot/4xx.c300
-rw-r--r--arch/powerpc/boot/4xx.h22
-rw-r--r--arch/powerpc/boot/Makefile25
-rw-r--r--arch/powerpc/boot/bamboo.c47
-rw-r--r--arch/powerpc/boot/cpm-serial.c269
-rw-r--r--arch/powerpc/boot/cuboot-52xx.c59
-rw-r--r--arch/powerpc/boot/cuboot-83xx.c1
-rw-r--r--arch/powerpc/boot/cuboot-85xx.c1
-rw-r--r--arch/powerpc/boot/cuboot-8xx.c47
-rw-r--r--arch/powerpc/boot/cuboot-bamboo.c30
-rw-r--r--arch/powerpc/boot/cuboot-hpc2.c48
-rw-r--r--arch/powerpc/boot/cuboot-pq2.c261
-rw-r--r--arch/powerpc/boot/cuboot-sequoia.c56
-rw-r--r--arch/powerpc/boot/cuboot.c3
-rw-r--r--arch/powerpc/boot/dcr.h18
-rw-r--r--arch/powerpc/boot/devtree.c99
-rw-r--r--arch/powerpc/boot/dts/bamboo.dts244
-rw-r--r--arch/powerpc/boot/dts/ebony.dts35
-rw-r--r--arch/powerpc/boot/dts/ep88xc.dts214
-rw-r--r--arch/powerpc/boot/dts/holly.dts5
-rw-r--r--arch/powerpc/boot/dts/kilauea.dts252
-rw-r--r--arch/powerpc/boot/dts/kuroboxHD.dts9
-rw-r--r--arch/powerpc/boot/dts/kuroboxHG.dts9
-rw-r--r--arch/powerpc/boot/dts/lite5200.dts59
-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts119
-rw-r--r--arch/powerpc/boot/dts/mpc7448hpc2.dts9
-rw-r--r--arch/powerpc/boot/dts/mpc8272ads.dts431
-rw-r--r--arch/powerpc/boot/dts/mpc8313erdb.dts67
-rw-r--r--arch/powerpc/boot/dts/mpc832x_mds.dts122
-rw-r--r--arch/powerpc/boot/dts/mpc832x_rdb.dts72
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitx.dts104
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitxgp.dts52
-rw-r--r--arch/powerpc/boot/dts/mpc834x_mds.dts249
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts123
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts175
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts228
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts377
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts404
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts228
-rw-r--r--arch/powerpc/boot/dts/mpc8560ads.dts267
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts160
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dts404
-rw-r--r--arch/powerpc/boot/dts/mpc8610_hpcd.dts191
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn.dts289
-rw-r--r--arch/powerpc/boot/dts/mpc866ads.dts5
-rw-r--r--arch/powerpc/boot/dts/mpc885ads.dts211
-rw-r--r--arch/powerpc/boot/dts/pq2fads.dts240
-rw-r--r--arch/powerpc/boot/dts/prpmc2800.dts5
-rw-r--r--arch/powerpc/boot/dts/sequoia.dts302
-rw-r--r--arch/powerpc/boot/dts/walnut.dts190
-rw-r--r--arch/powerpc/boot/ebony.c45
-rw-r--r--arch/powerpc/boot/ep88xc.c54
-rw-r--r--arch/powerpc/boot/fixed-head.S4
-rw-r--r--arch/powerpc/boot/flatdevtree.c100
-rw-r--r--arch/powerpc/boot/flatdevtree.h8
-rw-r--r--arch/powerpc/boot/flatdevtree_env.h20
-rw-r--r--arch/powerpc/boot/flatdevtree_misc.c8
-rw-r--r--arch/powerpc/boot/fsl-soc.c57
-rw-r--r--arch/powerpc/boot/fsl-soc.h8
-rw-r--r--arch/powerpc/boot/gunzip_util.c8
-rw-r--r--arch/powerpc/boot/holly.c5
-rw-r--r--arch/powerpc/boot/io.h49
-rw-r--r--arch/powerpc/boot/main.c10
-rw-r--r--arch/powerpc/boot/mpc52xx-psc.c69
-rw-r--r--arch/powerpc/boot/mpc8xx.c82
-rw-r--r--arch/powerpc/boot/mpc8xx.h11
-rw-r--r--arch/powerpc/boot/mpsc.c1
-rw-r--r--arch/powerpc/boot/mv64x60_i2c.c2
-rw-r--r--arch/powerpc/boot/of.c2
-rw-r--r--arch/powerpc/boot/ops.h36
-rw-r--r--arch/powerpc/boot/planetcore.c166
-rw-r--r--arch/powerpc/boot/planetcore.h49
-rw-r--r--arch/powerpc/boot/ppcboot.h7
-rw-r--r--arch/powerpc/boot/pq2.c102
-rw-r--r--arch/powerpc/boot/pq2.h11
-rw-r--r--arch/powerpc/boot/prpmc2800.c6
-rw-r--r--arch/powerpc/boot/ps3.c4
-rw-r--r--arch/powerpc/boot/serial.c23
-rw-r--r--arch/powerpc/boot/stdlib.c45
-rw-r--r--arch/powerpc/boot/stdlib.h6
-rw-r--r--arch/powerpc/boot/string.S37
-rw-r--r--arch/powerpc/boot/string.h3
-rw-r--r--arch/powerpc/boot/treeboot-bamboo.c43
-rw-r--r--arch/powerpc/boot/treeboot-ebony.c2
-rw-r--r--arch/powerpc/boot/treeboot-walnut.c131
-rw-r--r--arch/powerpc/boot/uartlite.c79
-rwxr-xr-xarch/powerpc/boot/wrapper20
90 files changed, 6467 insertions, 2082 deletions
diff --git a/arch/powerpc/boot/.gitignore b/arch/powerpc/boot/.gitignore
index eec7af7e599..65f4118cbe7 100644
--- a/arch/powerpc/boot/.gitignore
+++ b/arch/powerpc/boot/.gitignore
@@ -18,14 +18,15 @@ kernel-vmlinux.strip.c
kernel-vmlinux.strip.gz
mktree
uImage
-cuImage
-cuImage.bin.gz
-cuImage.elf
+cuImage.*
+treeImage.*
zImage
+zImage.bin.*
zImage.chrp
zImage.coff
zImage.coff.lds
-zImage.lds
+zImage.ep*
+zImage.*lds
zImage.miboot
zImage.pmac
zImage.pseries
diff --git a/arch/powerpc/boot/44x.c b/arch/powerpc/boot/44x.c
deleted file mode 100644
index 9f64e840bef..00000000000
--- a/arch/powerpc/boot/44x.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright 2007 David Gibson, IBM Corporation.
- *
- * Based on earlier code:
- * Matt Porter <mporter@kernel.crashing.org>
- * Copyright 2002-2005 MontaVista Software Inc.
- *
- * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
- * Copyright (c) 2003, 2004 Zultys Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <stddef.h>
-#include "types.h"
-#include "string.h"
-#include "stdio.h"
-#include "ops.h"
-#include "reg.h"
-#include "dcr.h"
-
-/* Read the 44x memory controller to get size of system memory. */
-void ibm44x_fixup_memsize(void)
-{
- int i;
- unsigned long memsize, bank_config;
-
- memsize = 0;
- for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) {
- mtdcr(DCRN_SDRAM0_CFGADDR, sdram_bxcr[i]);
- bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
-
- if (bank_config & SDRAM_CONFIG_BANK_ENABLE)
- memsize += SDRAM_CONFIG_BANK_SIZE(bank_config);
- }
-
- dt_fixup_memory(0, memsize);
-}
-
-#define SPRN_DBCR0 0x134
-#define DBCR0_RST_SYSTEM 0x30000000
-
-void ibm44x_dbcr_reset(void)
-{
- unsigned long tmp;
-
- asm volatile (
- "mfspr %0,%1\n"
- "oris %0,%0,%2@h\n"
- "mtspr %1,%0"
- : "=&r"(tmp) : "i"(SPRN_DBCR0), "i"(DBCR0_RST_SYSTEM)
- );
-
-}
-
-/* Read 4xx EBC bus bridge registers to get mappings of the peripheral
- * banks into the OPB address space */
-void ibm4xx_fixup_ebc_ranges(const char *ebc)
-{
- void *devp;
- u32 bxcr;
- u32 ranges[EBC_NUM_BANKS*4];
- u32 *p = ranges;
- int i;
-
- for (i = 0; i < EBC_NUM_BANKS; i++) {
- mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i));
- bxcr = mfdcr(DCRN_EBC0_CFGDATA);
-
- if ((bxcr & EBC_BXCR_BU) != EBC_BXCR_BU_OFF) {
- *p++ = i;
- *p++ = 0;
- *p++ = bxcr & EBC_BXCR_BAS;
- *p++ = EBC_BXCR_BANK_SIZE(bxcr);
- }
- }
-
- devp = finddevice(ebc);
- if (! devp)
- fatal("Couldn't locate EBC node %s\n\r", ebc);
-
- setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32));
-}
diff --git a/arch/powerpc/boot/44x.h b/arch/powerpc/boot/44x.h
index 577982c9a3c..02563443788 100644
--- a/arch/powerpc/boot/44x.h
+++ b/arch/powerpc/boot/44x.h
@@ -10,10 +10,7 @@
#ifndef _PPC_BOOT_44X_H_
#define _PPC_BOOT_44X_H_
-void ibm44x_fixup_memsize(void);
-void ibm4xx_fixup_ebc_ranges(const char *ebc);
-
-void ibm44x_dbcr_reset(void);
void ebony_init(void *mac0, void *mac1);
+void bamboo_init(void *mac0, void *mac1);
#endif /* _PPC_BOOT_44X_H_ */
diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c
new file mode 100644
index 00000000000..ebf9e217612
--- /dev/null
+++ b/arch/powerpc/boot/4xx.c
@@ -0,0 +1,300 @@
+/*
+ * Copyright 2007 David Gibson, IBM Corporation.
+ *
+ * Based on earlier code:
+ * Matt Porter <mporter@kernel.crashing.org>
+ * Copyright 2002-2005 MontaVista Software Inc.
+ *
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ * Copyright (c) 2003, 2004 Zultys Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <stddef.h>
+#include "types.h"
+#include "string.h"
+#include "stdio.h"
+#include "ops.h"
+#include "reg.h"
+#include "dcr.h"
+
+/* Read the 4xx SDRAM controller to get size of system memory. */
+void ibm4xx_fixup_memsize(void)
+{
+ int i;
+ unsigned long memsize, bank_config;
+
+ memsize = 0;
+ for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) {
+ mtdcr(DCRN_SDRAM0_CFGADDR, sdram_bxcr[i]);
+ bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
+
+ if (bank_config & SDRAM_CONFIG_BANK_ENABLE)
+ memsize += SDRAM_CONFIG_BANK_SIZE(bank_config);
+ }
+
+ dt_fixup_memory(0, memsize);
+}
+
+/* 4xx DDR1/2 Denali memory controller support */
+/* DDR0 registers */
+#define DDR0_02 2
+#define DDR0_08 8
+#define DDR0_10 10
+#define DDR0_14 14
+#define DDR0_42 42
+#define DDR0_43 43
+
+/* DDR0_02 */
+#define DDR_START 0x1
+#define DDR_START_SHIFT 0
+#define DDR_MAX_CS_REG 0x3
+#define DDR_MAX_CS_REG_SHIFT 24
+#define DDR_MAX_COL_REG 0xf
+#define DDR_MAX_COL_REG_SHIFT 16
+#define DDR_MAX_ROW_REG 0xf
+#define DDR_MAX_ROW_REG_SHIFT 8
+/* DDR0_08 */
+#define DDR_DDR2_MODE 0x1
+#define DDR_DDR2_MODE_SHIFT 0
+/* DDR0_10 */
+#define DDR_CS_MAP 0x3
+#define DDR_CS_MAP_SHIFT 8
+/* DDR0_14 */
+#define DDR_REDUC 0x1
+#define DDR_REDUC_SHIFT 16
+/* DDR0_42 */
+#define DDR_APIN 0x7
+#define DDR_APIN_SHIFT 24
+/* DDR0_43 */
+#define DDR_COL_SZ 0x7
+#define DDR_COL_SZ_SHIFT 8
+#define DDR_BANK8 0x1
+#define DDR_BANK8_SHIFT 0
+
+#define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask))
+
+static inline u32 mfdcr_sdram0(u32 reg)
+{
+ mtdcr(DCRN_SDRAM0_CFGADDR, reg);
+ return mfdcr(DCRN_SDRAM0_CFGDATA);
+}
+
+void ibm4xx_denali_fixup_memsize(void)
+{
+ u32 val, max_cs, max_col, max_row;
+ u32 cs, col, row, bank, dpath;
+ unsigned long memsize;
+
+ val = mfdcr_sdram0(DDR0_02);
+ if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT))
+ fatal("DDR controller is not initialized\n");
+
+ /* get maximum cs col and row values */
+ max_cs = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT);
+ max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT);
+ max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
+
+ /* get CS value */
+ val = mfdcr_sdram0(DDR0_10);
+
+ val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
+ cs = 0;
+ while (val) {
+ if (val && 0x1)
+ cs++;
+ val = val >> 1;
+ }
+
+ if (!cs)
+ fatal("No memory installed\n");
+ if (cs > max_cs)
+ fatal("DDR wrong CS configuration\n");
+
+ /* get data path bytes */
+ val = mfdcr_sdram0(DDR0_14);
+
+ if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT))
+ dpath = 8; /* 64 bits */
+ else
+ dpath = 4; /* 32 bits */
+
+ /* get adress pins (rows) */
+ val = mfdcr_sdram0(DDR0_42);
+
+ row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT);
+ if (row > max_row)
+ fatal("DDR wrong APIN configuration\n");
+ row = max_row - row;
+
+ /* get collomn size and banks */
+ val = mfdcr_sdram0(DDR0_43);
+
+ col = DDR_GET_VAL(val, DDR_COL_SZ, DDR_COL_SZ_SHIFT);
+ if (col > max_col)
+ fatal("DDR wrong COL configuration\n");
+ col = max_col - col;
+
+ if (DDR_GET_VAL(val, DDR_BANK8, DDR_BANK8_SHIFT))
+ bank = 8; /* 8 banks */
+ else
+ bank = 4; /* 4 banks */
+
+ memsize = cs * (1 << (col+row)) * bank * dpath;
+ dt_fixup_memory(0, memsize);
+}
+
+#define SPRN_DBCR0_40X 0x3F2
+#define SPRN_DBCR0_44X 0x134
+#define DBCR0_RST_SYSTEM 0x30000000
+
+void ibm44x_dbcr_reset(void)
+{
+ unsigned long tmp;
+
+ asm volatile (
+ "mfspr %0,%1\n"
+ "oris %0,%0,%2@h\n"
+ "mtspr %1,%0"
+ : "=&r"(tmp) : "i"(SPRN_DBCR0_44X), "i"(DBCR0_RST_SYSTEM)
+ );
+
+}
+
+void ibm40x_dbcr_reset(void)
+{
+ unsigned long tmp;
+
+ asm volatile (
+ "mfspr %0,%1\n"
+ "oris %0,%0,%2@h\n"
+ "mtspr %1,%0"
+ : "=&r"(tmp) : "i"(SPRN_DBCR0_40X), "i"(DBCR0_RST_SYSTEM)
+ );
+}
+
+#define EMAC_RESET 0x20000000
+void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)
+{
+ /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't do this for us */
+ if (emac0)
+ *emac0 = EMAC_RESET;
+ if (emac1)
+ *emac1 = EMAC_RESET;
+
+ mtdcr(DCRN_MAL0_CFG, MAL_RESET);
+}
+
+/* Read 4xx EBC bus bridge registers to get mappings of the peripheral
+ * banks into the OPB address space */
+void ibm4xx_fixup_ebc_ranges(const char *ebc)
+{
+ void *devp;
+ u32 bxcr;
+ u32 ranges[EBC_NUM_BANKS*4];
+ u32 *p = ranges;
+ int i;
+
+ for (i = 0; i < EBC_NUM_BANKS; i++) {
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i));
+ bxcr = mfdcr(DCRN_EBC0_CFGDATA);
+
+ if ((bxcr & EBC_BXCR_BU) != EBC_BXCR_BU_OFF) {
+ *p++ = i;
+ *p++ = 0;
+ *p++ = bxcr & EBC_BXCR_BAS;
+ *p++ = EBC_BXCR_BANK_SIZE(bxcr);
+ }
+ }
+
+ devp = finddevice(ebc);
+ if (! devp)
+ fatal("Couldn't locate EBC node %s\n\r", ebc);
+
+ setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32));
+}
+
+#define SPRN_CCR1 0x378
+void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
+{
+ u32 cpu, plb, opb, ebc, tb, uart0, m, vco;
+ u32 reg;
+ u32 fwdva, fwdvb, fbdv, lfbdv, opbdv0, perdv0, spcid0, prbdv0, tmp;
+
+ mtdcr(DCRN_CPR0_ADDR, CPR0_PLLD0);
+ reg = mfdcr(DCRN_CPR0_DATA);
+ tmp = (reg & 0x000F0000) >> 16;
+ fwdva = tmp ? tmp : 16;
+ tmp = (reg & 0x00000700) >> 8;
+ fwdvb = tmp ? tmp : 8;
+ tmp = (reg & 0x1F000000) >> 24;
+ fbdv = tmp ? tmp : 32;
+ lfbdv = (reg & 0x0000007F);
+
+ mtdcr(DCRN_CPR0_ADDR, CPR0_OPBD0);
+ reg = mfdcr(DCRN_CPR0_DATA);
+ tmp = (reg & 0x03000000) >> 24;
+ opbdv0 = tmp ? tmp : 4;
+
+ mtdcr(DCRN_CPR0_ADDR, CPR0_PERD0);
+ reg = mfdcr(DCRN_CPR0_DATA);
+ tmp = (reg & 0x07000000) >> 24;
+ perdv0 = tmp ? tmp : 8;
+
+ mtdcr(DCRN_CPR0_ADDR, CPR0_PRIMBD0);
+ reg = mfdcr(DCRN_CPR0_DATA);
+ tmp = (reg & 0x07000000) >> 24;
+ prbdv0 = tmp ? tmp : 8;
+
+ mtdcr(DCRN_CPR0_ADDR, CPR0_SCPID);
+ reg = mfdcr(DCRN_CPR0_DATA);
+ tmp = (reg & 0x03000000) >> 24;
+ spcid0 = tmp ? tmp : 4;
+
+ /* Calculate M */
+ mtdcr(DCRN_CPR0_ADDR, CPR0_PLLC0);
+ reg = mfdcr(DCRN_CPR0_DATA);
+ tmp = (reg & 0x03000000) >> 24;
+ if (tmp == 0) { /* PLL output */
+ tmp = (reg & 0x20000000) >> 29;
+ if (!tmp) /* PLLOUTA */
+ m = fbdv * lfbdv * fwdva;
+ else
+ m = fbdv * lfbdv * fwdvb;
+ }
+ else if (tmp == 1) /* CPU output */
+ m = fbdv * fwdva;
+ else
+ m = perdv0 * opbdv0 * fwdvb;
+
+ vco = (m * sysclk) + (m >> 1);
+ cpu = vco / fwdva;
+ plb = vco / fwdvb / prbdv0;
+ opb = plb / opbdv0;
+ ebc = plb / perdv0;
+
+ /* FIXME */
+ uart0 = ser_clk;
+
+ /* Figure out timebase. Either CPU or default TmrClk */
+ asm volatile (
+ "mfspr %0,%1\n"
+ :
+ "=&r"(reg) : "i"(SPRN_CCR1));
+ if (reg & 0x0080)
+ tb = 25000000; /* TmrClk is 25MHz */
+ else
+ tb = cpu;
+
+ dt_fixup_cpu_clocks(cpu, tb, 0);
+ dt_fixup_clock("/plb", plb);
+ dt_fixup_clock("/plb/opb", opb);
+ dt_fixup_clock("/plb/opb/ebc", ebc);
+ dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
+ dt_fixup_clock("/plb/opb/serial@ef600400", uart0);
+ dt_fixup_clock("/plb/opb/serial@ef600500", uart0);
+ dt_fixup_clock("/plb/opb/serial@ef600600", uart0);
+}
diff --git a/arch/powerpc/boot/4xx.h b/arch/powerpc/boot/4xx.h
new file mode 100644
index 00000000000..adba6a599a9
--- /dev/null
+++ b/arch/powerpc/boot/4xx.h
@@ -0,0 +1,22 @@
+/*
+ * PowerPC 4xx related functions
+ *
+ * Copyright 2007 IBM Corporation.
+ * Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef _POWERPC_BOOT_4XX_H_
+#define _POWERPC_BOOT_4XX_H_
+
+void ibm4xx_fixup_memsize(void);
+void ibm4xx_denali_fixup_memsize(void);
+void ibm44x_dbcr_reset(void);
+void ibm40x_dbcr_reset(void);
+void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1);
+void ibm4xx_fixup_ebc_ranges(const char *ebc);
+void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk);
+
+#endif /* _POWERPC_BOOT_4XX_H_ */
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 61a6f34ca5e..18e32719d0e 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -25,14 +25,19 @@ BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
-isystem $(shell $(CROSS32CC) -print-file-name=include)
BOOTAFLAGS := -D__ASSEMBLY__ $(BOOTCFLAGS) -traditional -nostdinc
+ifdef CONFIG_DEBUG_INFO
+BOOTCFLAGS += -g
+endif
+
ifeq ($(call cc-option-yn, -fstack-protector),y)
BOOTCFLAGS += -fno-stack-protector
endif
BOOTCFLAGS += -I$(obj) -I$(srctree)/$(obj)
-$(obj)/44x.o: BOOTCFLAGS += -mcpu=440
+$(obj)/4xx.o: BOOTCFLAGS += -mcpu=440
$(obj)/ebony.o: BOOTCFLAGS += -mcpu=440
+$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
zlib := inffast.c inflate.c inftrees.c
zlibheader := inffast.h inffixed.h inflate.h inftrees.h infutil.h
@@ -44,10 +49,14 @@ $(addprefix $(obj)/,$(zlib) gunzip_util.o main.o): \
src-wlib := string.S crt0.S stdio.c main.c flatdevtree.c flatdevtree_misc.c \
ns16550.c serial.c simple_alloc.c div64.S util.S \
gunzip_util.c elf_util.c $(zlib) devtree.c oflib.c ofconsole.c \
- 44x.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c
-src-plat := of.c cuboot-83xx.c cuboot-85xx.c holly.c \
+ 4xx.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c bamboo.c \
+ cpm-serial.c stdlib.c mpc52xx-psc.c planetcore.c uartlite.c \
+ fsl-soc.c mpc8xx.c pq2.c
+src-plat := of.c cuboot-52xx.c cuboot-83xx.c cuboot-85xx.c holly.c \
cuboot-ebony.c treeboot-ebony.c prpmc2800.c \
- ps3-head.S ps3-hvcall.S ps3.c
+ ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \
+ cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c cuboot-bamboo.c \
+ fixed-head.S ep88xc.c cuboot-hpc2.c
src-boot := $(src-wlib) $(src-plat) empty.c
src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -139,9 +148,17 @@ image-$(CONFIG_PPC_ISERIES) += zImage.iseries
image-$(CONFIG_DEFAULT_UIMAGE) += uImage
ifneq ($(CONFIG_DEVICE_TREE),"")
+image-$(CONFIG_PPC_8xx) += cuImage.8xx
+image-$(CONFIG_PPC_EP88XC) += zImage.ep88xc
+image-$(CONFIG_8260) += cuImage.pq2
+image-$(CONFIG_PPC_MPC52xx) += cuImage.52xx
image-$(CONFIG_PPC_83xx) += cuImage.83xx
image-$(CONFIG_PPC_85xx) += cuImage.85xx
+image-$(CONFIG_MPC7448HPC2) += cuImage.hpc2
image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
+image-$(CONFIG_BAMBOO) += treeImage.bamboo cuImage.bamboo
+image-$(CONFIG_SEQUOIA) += cuImage.sequoia
+image-$(CONFIG_WALNUT) += treeImage.walnut
endif
# For 32-bit powermacs, build the COFF and miboot images
diff --git a/arch/powerpc/boot/bamboo.c b/arch/powerpc/boot/bamboo.c
new file mode 100644
index 00000000000..f61fcdab1c7
--- /dev/null
+++ b/arch/powerpc/boot/bamboo.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright IBM Corporation, 2007
+ * Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ *
+ * Based on ebony wrapper:
+ * Copyright 2007 David Gibson, IBM Corporation.
+ *
+ * Clocking code based on code by:
+ * Stefan Roese <sr@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2 of the License
+ */
+#include <stdarg.h>
+#include <stddef.h>
+#include "types.h"
+#include "elf.h"
+#include "string.h"
+#include "stdio.h"
+#include "page.h"
+#include "ops.h"
+#include "dcr.h"
+#include "4xx.h"
+#include "44x.h"
+
+static u8 *bamboo_mac0, *bamboo_mac1;
+
+static void bamboo_fixups(void)
+{
+ unsigned long sysclk = 33333333;
+
+ ibm440ep_fixup_clocks(sysclk, 11059200);
+ ibm4xx_fixup_memsize();
+ ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
+ dt_fixup_mac_addresses(bamboo_mac0, bamboo_mac1);
+}
+
+void bamboo_init(void *mac0, void *mac1)
+{
+ platform_ops.fixups = bamboo_fixups;
+ platform_ops.exit = ibm44x_dbcr_reset;
+ bamboo_mac0 = mac0;
+ bamboo_mac1 = mac1;
+ ft_init(_dtb_start, 0, 32);
+ serial_console_init();
+}
diff --git a/arch/powerpc/boot/cpm-serial.c b/arch/powerpc/boot/cpm-serial.c
new file mode 100644
index 00000000000..28296facb2a
--- /dev/null
+++ b/arch/powerpc/boot/cpm-serial.c
@@ -0,0 +1,269 @@
+/*
+ * CPM serial console support.
+ *
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * It is assumed that the firmware (or the platform file) has already set
+ * up the port.
+ */
+
+#include "types.h"
+#include "io.h"
+#include "ops.h"
+
+struct cpm_scc {
+ u32 gsmrl;
+ u32 gsmrh;
+ u16 psmr;
+ u8 res1[2];
+ u16 todr;
+ u16 dsr;
+ u16 scce;
+ u8 res2[2];
+ u16 sccm;
+ u8 res3;
+ u8 sccs;
+ u8 res4[8];
+};
+
+struct cpm_smc {
+ u8 res1[2];
+ u16 smcmr;
+ u8 res2[2];
+ u8 smce;
+ u8 res3[3];
+ u8 smcm;
+ u8 res4[5];
+};
+
+struct cpm_param {
+ u16 rbase;
+ u16 tbase;
+ u8 rfcr;
+ u8 tfcr;
+};
+
+struct cpm_bd {
+ u16 sc; /* Status and Control */
+ u16 len; /* Data length in buffer */
+ u8 *addr; /* Buffer address in host memory */
+};
+
+static void *cpcr;
+static struct cpm_param *param;
+static struct cpm_smc *smc;
+static struct cpm_scc *scc;
+struct cpm_bd *tbdf, *rbdf;
+static u32 cpm_cmd;
+static u8 *muram_start;
+static u32 muram_offset;
+
+static void (*do_cmd)(int op);
+static void (*enable_port)(void);
+static void (*disable_port)(void);
+
+#define CPM_CMD_STOP_TX 4
+#define CPM_CMD_RESTART_TX 6
+#define CPM_CMD_INIT_RX_TX 0
+
+static void cpm1_cmd(int op)
+{
+ while (in_be16(cpcr) & 1)
+ ;
+
+ out_be16(cpcr, (op << 8) | cpm_cmd | 1);
+
+ while (in_be16(cpcr) & 1)
+ ;
+}
+
+static void cpm2_cmd(int op)
+{
+ while (in_be32(cpcr) & 0x10000)
+ ;
+
+ out_be32(cpcr, op | cpm_cmd | 0x10000);
+
+ while (in_be32(cpcr) & 0x10000)
+ ;
+}
+
+static void smc_disable_port(void)
+{
+ do_cmd(CPM_CMD_STOP_TX);
+ out_be16(&smc->smcmr, in_be16(&smc->smcmr) & ~3);
+}
+
+static void scc_disable_port(void)
+{
+ do_cmd(CPM_CMD_STOP_TX);
+ out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) & ~0x30);
+}
+
+static void smc_enable_port(void)
+{
+ out_be16(&smc->smcmr, in_be16(&smc->smcmr) | 3);
+ do_cmd(CPM_CMD_RESTART_TX);
+}
+
+static void scc_enable_port(void)
+{
+ out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) | 0x30);
+ do_cmd(CPM_CMD_RESTART_TX);
+}
+
+static int cpm_serial_open(void)
+{
+ disable_port();
+
+ out_8(&param->rfcr, 0x10);
+ out_8(&param->tfcr, 0x10);
+
+ rbdf = (struct cpm_bd *)muram_start;
+ rbdf->addr = (u8 *)(rbdf + 2);
+ rbdf->sc = 0xa000;
+ rbdf->len = 1;
+
+ tbdf = rbdf + 1;
+ tbdf->addr = (u8 *)(rbdf + 2) + 1;
+ tbdf->sc = 0x2000;
+ tbdf->len = 1;
+
+ sync();
+ out_be16(&param->rbase, muram_offset);
+ out_be16(&param->tbase, muram_offset + sizeof(struct cpm_bd));
+
+ do_cmd(CPM_CMD_INIT_RX_TX);
+
+ enable_port();
+ return 0;
+}
+
+static void cpm_serial_putc(unsigned char c)
+{
+ while (tbdf->sc & 0x8000)
+ barrier();
+
+ sync();
+
+ tbdf->addr[0] = c;
+ eieio();
+ tbdf->sc |= 0x8000;
+}
+
+static unsigned char cpm_serial_tstc(void)
+{
+ barrier();
+ return !(rbdf->sc & 0x8000);
+}
+
+static unsigned char cpm_serial_getc(void)
+{
+ unsigned char c;
+
+ while (!cpm_serial_tstc())
+ ;
+
+ sync();
+ c = rbdf->addr[0];
+ eieio();
+ rbdf->sc |= 0x8000;
+
+ return c;
+}
+
+int cpm_console_init(void *devp, struct serial_console_data *scdp)
+{
+ void *reg_virt[2];
+ int is_smc = 0, is_cpm2 = 0, n;
+ unsigned long reg_phys;
+ void *parent, *muram;
+
+ if (dt_is_compatible(devp, "fsl,cpm1-smc-uart")) {
+ is_smc = 1;
+ } else if (dt_is_compatible(devp, "fsl,cpm2-scc-uart")) {
+ is_cpm2 = 1;
+ } else if (dt_is_compatible(devp, "fsl,cpm2-smc-uart")) {
+ is_cpm2 = 1;
+ is_smc = 1;
+ }
+
+ if (is_smc) {
+ enable_port = smc_enable_port;
+ disable_port = smc_disable_port;
+ } else {
+ enable_port = scc_enable_port;
+ disable_port = scc_disable_port;
+ }
+
+ if (is_cpm2)
+ do_cmd = cpm2_cmd;
+ else
+ do_cmd = cpm1_cmd;
+
+ n = getprop(devp, "fsl,cpm-command", &cpm_cmd, 4);
+ if (n < 4)
+ return -1;
+
+ n = getprop(devp, "virtual-reg", reg_virt, sizeof(reg_virt));
+ if (n < (int)sizeof(reg_virt)) {
+ for (n = 0; n < 2; n++) {
+ if (!dt_xlate_reg(devp, n, &reg_phys, NULL))
+ return -1;
+
+ reg_virt[n] = (void *)reg_phys;
+ }
+ }
+
+ if (is_smc)
+ smc = reg_virt[0];
+ else
+ scc = reg_virt[0];
+
+ param = reg_virt[1];
+
+ parent = get_parent(devp);
+ if (!parent)
+ return -1;
+
+ n = getprop(parent, "virtual-reg", reg_virt, sizeof(reg_virt));
+ if (n < (int)sizeof(reg_virt)) {
+ if (!dt_xlate_reg(parent, 0, &reg_phys, NULL))
+ return -1;
+
+ reg_virt[0] = (void *)reg_phys;
+ }
+
+ cpcr = reg_virt[0];
+
+ muram = finddevice("/soc/cpm/muram/data");
+ if (!muram)
+ return -1;
+
+ /* For bootwrapper-compatible device trees, we assume that the first
+ * entry has at least 18 bytes, and that #address-cells/#data-cells
+ * is one for both parent and child.
+ */
+
+ n = getprop(muram, "virtual-reg", reg_virt, sizeof(reg_virt));
+ if (n < (int)sizeof(reg_virt)) {
+ if (!dt_xlate_reg(muram, 0, &reg_phys, NULL))
+ return -1;
+
+ reg_virt[0] = (void *)reg_phys;
+ }
+
+ muram_start = reg_virt[0];
+
+ n = getprop(muram, "reg", &muram_offset, 4);
+ if (n < 4)
+ return -1;
+
+ scdp->open = cpm_serial_open;
+ scdp->putc = cpm_serial_putc;
+ scdp->getc = cpm_serial_getc;
+ scdp->tstc = cpm_serial_tstc;
+
+ return 0;
+}
diff --git a/arch/powerpc/boot/cuboot-52xx.c b/arch/powerpc/boot/cuboot-52xx.c
new file mode 100644
index 00000000000..9256a26d40e
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-52xx.c
@@ -0,0 +1,59 @@
+/*
+ * Old U-boot compatibility for MPC5200
+ *
+ * Author: Grant Likely <grant.likely@secretlab.ca>
+ *
+ * Copyright (c) 2007 Secret Lab Technologies Ltd.
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "stdio.h"
+#include "io.h"
+#include "cuboot.h"
+
+#define TARGET_PPC_MPC52xx
+#include "ppcboot.h"
+
+static bd_t bd;
+
+static void platform_fixups(void)
+{
+ void *soc, *reg;
+ int div;
+ u32 sysfreq;
+
+
+ dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
+ dt_fixup_mac_addresses(bd.bi_enetaddr);
+ dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
+
+ /* Unfortunately, the specific model number is encoded in the
+ * soc node name in existing dts files -- once that is fixed,
+ * this can do a simple path lookup.
+ */
+ soc = find_node_by_devtype(NULL, "soc");
+ if (soc) {
+ setprop(soc, "bus-frequency", &bd.bi_ipbfreq,
+ sizeof(bd.bi_ipbfreq));
+
+ if (!dt_xlate_reg(soc, 0, (void*)&reg, NULL))
+ return;
+ div = in_8(reg + 0x204) & 0x0020 ? 8 : 4;
+ sysfreq = bd.bi_busfreq * div;
+ setprop(soc, "system-frequency", &sysfreq, sizeof(sysfreq));
+ }
+}
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ CUBOOT_INIT();
+ ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
+ serial_console_init();
+ platform_ops.fixups = platform_fixups;
+}
diff --git a/arch/powerpc/boot/cuboot-83xx.c b/arch/powerpc/boot/cuboot-83xx.c
index 296025d8b29..a0505509abc 100644
--- a/arch/powerpc/boot/cuboot-83xx.c
+++ b/arch/powerpc/boot/cuboot-83xx.c
@@ -18,7 +18,6 @@
#include "ppcboot.h"
static bd_t bd;
-extern char _dtb_start[], _dtb_end[];
static void platform_fixups(void)
{
diff --git a/arch/powerpc/boot/cuboot-85xx.c b/arch/powerpc/boot/cuboot-85xx.c
index 10f0f697c93..345dcbecef0 100644
--- a/arch/powerpc/boot/cuboot-85xx.c
+++ b/arch/powerpc/boot/cuboot-85xx.c
@@ -18,7 +18,6 @@
#include "ppcboot.h"
static bd_t bd;
-extern char _dtb_start[], _dtb_end[];
static void platform_fixups(void)
{
diff --git a/arch/powerpc/boot/cuboot-8xx.c b/arch/powerpc/boot/cuboot-8xx.c
new file mode 100644
index 00000000000..0e82015a5f9
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-8xx.c
@@ -0,0 +1,47 @@
+/*
+ * Old U-boot compatibility for 8xx
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "stdio.h"
+#include "cuboot.h"
+
+#define TARGET_8xx
+#define TARGET_HAS_ETH1
+#include "ppcboot.h"
+
+static bd_t bd;
+
+static void platform_fixups(void)
+{
+ void *node;
+
+ dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
+ dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
+ dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 16, bd.bi_busfreq);
+
+ node = finddevice("/soc/cpm");
+ if (node)
+ setprop(node, "clock-frequency", &bd.bi_busfreq, 4);
+
+ node = finddevice("/soc/cpm/brg");
+ if (node)
+ setprop(node, "clock-frequency", &bd.bi_busfreq, 4);
+}
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ CUBOOT_INIT();
+ ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
+ serial_console_init();
+ platform_ops.fixups = platform_fixups;
+}
diff --git a/arch/powerpc/boot/cuboot-bamboo.c b/arch/powerpc/boot/cuboot-bamboo.c
new file mode 100644
index 00000000000..900c7ff2b7e
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-bamboo.c
@@ -0,0 +1,30 @@
+/*
+ * Old U-boot compatibility for Bamboo
+ *
+ * Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ *
+ * Copyright 2007 IBM Corporation
+ *
+ * Based on cuboot-ebony.c
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "stdio.h"
+#include "44x.h"
+#include "cuboot.h"
+
+#define TARGET_44x
+#include "ppcboot.h"
+
+static bd_t bd;
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ CUBOOT_INIT();
+ bamboo_init(&bd.bi_enetaddr, &bd.bi_enet1addr);
+}
diff --git a/arch/powerpc/boot/cuboot-hpc2.c b/arch/powerpc/boot/cuboot-hpc2.c
new file mode 100644
index 00000000000..d333898bca3
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-hpc2.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * Description:
+ * Old U-boot compatibility for mpc7448hpc2 board
+ * Based on the code of Scott Wood <scottwood@freescale.com>
+ * for 83xx and 85xx.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include "ops.h"
+#include "stdio.h"
+#include "cuboot.h"
+
+#define TARGET_HAS_ETH1
+#include "ppcboot.h"
+
+static bd_t bd;
+extern char _dtb_start[], _dtb_end[];
+
+static void platform_fixups(void)
+{
+ void *tsi;
+
+ dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
+ dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
+ dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
+ tsi = find_node_by_devtype(NULL, "tsi-bridge");
+ if (tsi)
+ setprop(tsi, "bus-frequency", &bd.bi_busfreq,
+ sizeof(bd.bi_busfreq));
+}
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ CUBOOT_INIT();
+ ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
+ serial_console_init();
+ platform_ops.fixups = platform_fixups;
+}
diff --git a/arch/powerpc/boot/cuboot-pq2.c b/arch/powerpc/boot/cuboot-pq2.c
new file mode 100644
index 00000000000..61574f3272d
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-pq2.c
@@ -0,0 +1,261 @@
+/*
+ * Old U-boot compatibility for PowerQUICC II
+ * (a.k.a. 82xx with CPM, not the 8240 family of chips)
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "stdio.h"
+#include "cuboot.h"
+#include "io.h"
+#include "fsl-soc.h"
+
+#define TARGET_CPM2
+#define TARGET_HAS_ETH1
+#include "ppcboot.h"
+
+static bd_t bd;
+
+struct cs_range {
+ u32 csnum;
+ u32 base; /* must be zero */
+ u32 addr;
+ u32 size;
+};
+
+struct pci_range {
+ u32 flags;
+ u32 pci_addr[2];
+ u32 phys_addr;
+ u32 size[2];
+};
+
+struct cs_range cs_ranges_buf[MAX_PROP_LEN / sizeof(struct cs_range)];
+struct pci_range pci_ranges_buf[MAX_PROP_LEN / sizeof(struct pci_range)];
+
+/* Different versions of u-boot put the BCSR in different places, and
+ * some don't set up the PCI PIC at all, so we assume the device tree is
+ * sane and update the BRx registers appropriately.
+ *
+ * For any node defined as compatible with fsl,pq2-localbus,
+ * #address/#size must be 2/1 for the localbus, and 1/1 for the parent bus.
+ * Ranges must be for whole chip selects.
+ */
+static void update_cs_ranges(void)
+{
+ void *bus_node, *parent_node;
+ u32 *ctrl_addr;
+ unsigned long ctrl_size;
+ u32 naddr, nsize;
+ int len;
+ int i;
+
+ bus_node = finddevice("/localbus");
+ if (!bus_node || !dt_is_compatible(bus_node, "fsl,pq2-localbus"))
+ return;
+
+ dt_get_reg_format(bus_node, &naddr, &nsize);
+ if (naddr != 2 || nsize != 1)
+ goto err;
+
+ parent_node = get_parent(bus_node);
+ if (!parent_node)
+ goto err;
+
+ dt_get_reg_format(parent_node, &naddr, &nsize);
+ if (naddr != 1 || nsize != 1)
+ goto err;
+
+ if (!dt_xlate_reg(bus_node, 0, (unsigned long *)&ctrl_addr,
+ &ctrl_size))
+ goto err;
+
+ len = getprop(bus_node, "ranges", cs_ranges_buf, sizeof(cs_ranges_buf));
+
+ for (i = 0; i < len / sizeof(struct cs_range); i++) {
+ u32 base, option;
+ int cs = cs_ranges_buf[i].csnum;
+ if (cs >= ctrl_size / 8)
+ goto err;
+
+ if (cs_ranges_buf[i].base != 0)
+ goto err;
+
+ base = in_be32(&ctrl_addr[cs * 2]);
+
+ /* If CS is already valid, use the existing flags.
+ * Otherwise, guess a sane default.
+ */
+ if (base & 1) {
+ base &= 0x7fff;
+ option = in_be32(&ctrl_addr[cs * 2 + 1]) & 0x7fff;
+ } else {
+ base = 0x1801;
+ option = 0x10;
+ }
+
+ out_be32(&ctrl_addr[cs * 2], 0);
+ out_be32(&ctrl_addr[cs * 2 + 1],
+ option | ~(cs_ranges_buf[i].size - 1));
+ out_be32(&ctrl_addr[cs * 2], base | cs_ranges_buf[i].addr);
+ }
+
+ return;
+
+err:
+ printf("Bad /localbus node\r\n");
+}
+
+/* Older u-boots don't set PCI up properly. Update the hardware to match
+ * the device tree. The prefetch mem region and non-prefetch mem region
+ * must be contiguous in the host bus. As required by the PCI binding,
+ * PCI #addr/#size must be 3/2. The parent bus must be 1/1. Only
+ * 32-bit PCI is supported. All three region types (prefetchable mem,
+ * non-prefetchable mem, and I/O) must be present.
+ */
+static void fixup_pci(void)
+{
+ struct pci_range *mem = NULL, *mmio = NULL,
+ *io = NULL, *mem_base = NULL;
+ u32 *pci_regs[3];
+ u8 *soc_regs;
+ int i, len;
+ void *node, *parent_node;
+ u32 naddr, nsize, mem_log2;
+
+ node = finddevice("/pci");
+ if (!node || !dt_is_compatible(node, "fsl,pq2-pci"))
+ return;
+
+ for (i = 0; i < 3; i++)
+ if (!dt_xlate_reg(node, i,
+ (unsigned long *)&pci_regs[i], NULL))
+ goto err;
+
+ soc_regs = (u8 *)fsl_get_immr();
+ if (!soc_regs)
+ goto err;
+
+ dt_get_reg_format(node, &naddr, &nsize);
+ if (naddr != 3 || nsize != 2)
+ goto err;
+
+ parent_node = get_parent(node);
+ if (!parent_node)
+ goto err;
+
+ dt_get_reg_format(parent_node, &naddr, &nsize);
+ if (naddr != 1 || nsize != 1)
+ goto err;
+
+ len = getprop(node, "ranges", pci_ranges_buf,
+ sizeof(pci_ranges_buf));
+
+ for (i = 0; i < len / sizeof(struct pci_range); i++) {
+ u32 flags = pci_ranges_buf[i].flags & 0x43000000;
+
+ if (flags == 0x42000000)
+ mem = &pci_ranges_buf[i];
+ else if (flags == 0x02000000)
+ mmio = &pci_ranges_buf[i];
+ else if (flags == 0x01000000)
+ io = &pci_ranges_buf[i];
+ }
+
+ if (!mem || !mmio || !io)
+ goto err;
+
+ if (mem->phys_addr + mem->size[1] == mmio->phys_addr)
+ mem_base = mem;
+ else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr)
+ mem_base = mmio;
+ else
+ goto err;
+
+ out_be32(&pci_regs[1][0], mem_base->phys_addr | 1);
+ out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1));
+
+ out_be32(&pci_regs[1][1], io->phys_addr | 1);
+ out_be32(&pci_regs[2][1], ~(io->size[1] - 1));
+
+ out_le32(&pci_regs[0][0], mem->pci_addr[1] >> 12);
+ out_le32(&pci_regs[0][2], mem->phys_addr >> 12);
+ out_le32(&pci_regs[0][4], (~(mem->size[1] - 1) >> 12) | 0xa0000000);
+
+ out_le32(&pci_regs[0][6], mmio->pci_addr[1] >> 12);
+ out_le32(&pci_regs[0][8], mmio->phys_addr >> 12);
+ out_le32(&pci_regs[0][10], (~(mmio->size[1] - 1) >> 12) | 0x80000000);
+
+ out_le32(&pci_regs[0][12], io->pci_addr[1] >> 12);
+ out_le32(&pci_regs[0][14], io->phys_addr >> 12);
+ out_le32(&pci_regs[0][16], (~(io->size[1] - 1) >> 12) | 0xc0000000);
+
+ /* Inbound translation */
+ out_le32(&pci_regs[0][58], 0);
+ out_le32(&pci_regs[0][60], 0);
+
+ mem_log2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1);
+ out_le32(&pci_regs[0][62], 0xa0000000 | ~((1 << (mem_log2 - 12)) - 1));
+
+ /* If PCI is disabled, drive RST high to enable. */
+ if (!(in_le32(&pci_regs[0][32]) & 1)) {
+ /* Tpvrh (Power valid to RST# high) 100 ms */
+ udelay(100000);
+
+ out_le32(&pci_regs[0][32], 1);
+
+ /* Trhfa (RST# high to first cfg access) 2^25 clocks */
+ udelay(1020000);
+ }
+
+ /* Enable bus master and memory access */
+ out_le32(&pci_regs[0][64], 0x80000004);
+ out_le32(&pci_regs[0][65], in_le32(&pci_regs[0][65]) | 6);
+
+ /* Park the bus on PCI, and elevate PCI's arbitration priority,
+ * as required by section 9.6 of the user's manual.
+ */
+ out_8(&soc_regs[0x10028], 3);
+ out_be32((u32 *)&soc_regs[0x1002c], 0x01236745);
+
+ return;
+
+err:
+ printf("Bad PCI node\r\n");
+}
+
+static void pq2_platform_fixups(void)
+{
+ void *node;
+
+ dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
+ dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
+ dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
+
+ node = finddevice("/soc/cpm");
+ if (node)
+ setprop(node, "clock-frequency", &bd.bi_cpmfreq, 4);
+
+ node = finddevice("/soc/cpm/brg");
+ if (node)
+ setprop(node, "clock-frequency", &bd.bi_brgfreq, 4);
+
+ update_cs_ranges();
+ fixup_pci();
+}
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ CUBOOT_INIT();
+ ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
+ serial_console_init();
+ platform_ops.fixups = pq2_platform_fixups;
+}
diff --git a/arch/powerpc/boot/cuboot-sequoia.c b/arch/powerpc/boot/cuboot-sequoia.c
new file mode 100644
index 00000000000..ec635e0bd4e
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-sequoia.c
@@ -0,0 +1,56 @@
+/*
+ * Old U-boot compatibility for Sequoia
+ *
+ * Valentine Barshak <vbarshak@ru.mvista.com>
+ * Copyright 2007 MontaVista Software, Inc
+ *
+ * Based on Ebony code by David Gibson <david@gibson.dropbear.id.au>
+ * Copyright IBM Corporation, 2007
+ *
+ * Based on Bamboo code by Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ * Copyright IBM Corporation, 2007
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2 of the License
+ */
+
+#include <stdarg.h>
+#include <stddef.h>
+#include "types.h"
+#include "elf.h"
+#include "string.h"
+#include "stdio.h"
+#include "page.h"
+#include "ops.h"
+#include "dcr.h"
+#include "4xx.h"
+#include "44x.h"
+#include "cuboot.h"
+
+#define TARGET_4xx
+#define TARGET_44x
+#include "ppcboot.h"
+
+static bd_t bd;
+
+
+static void sequoia_fixups(void)
+{
+ unsigned long sysclk = 33333333;
+
+ ibm440ep_fixup_clocks(sysclk, 11059200);
+ ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
+ ibm4xx_denali_fixup_memsize();
+ dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
+}
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ CUBOOT_INIT();
+ platform_ops.fixups = sequoia_fixups;
+ platform_ops.exit = ibm44x_dbcr_reset;
+ ft_init(_dtb_start, 0, 32);
+ serial_console_init();
+}
diff --git a/arch/powerpc/boot/cuboot.c b/arch/powerpc/boot/cuboot.c
index 65795468ad6..7768b2306b7 100644
--- a/arch/powerpc/boot/cuboot.c
+++ b/arch/powerpc/boot/cuboot.c
@@ -17,9 +17,6 @@
#include "ppcboot.h"
-extern char _end[];
-extern char _dtb_start[], _dtb_end[];
-
void cuboot_init(unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7,
unsigned long end_of_ram)
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h
index 14b44aa96fe..83b88aa9288 100644
--- a/arch/powerpc/boot/dcr.h
+++ b/arch/powerpc/boot/dcr.h
@@ -121,4 +121,22 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2C
#define DCRN_CPC0_MIRQ1 0x0ed
#define DCRN_CPC0_JTAGID 0x0ef
+#define DCRN_MAL0_CFG 0x180
+#define MAL_RESET 0x80000000
+
+/* 440EP Clock/Power-on Reset regs */
+#define DCRN_CPR0_ADDR 0xc
+#define DCRN_CPR0_DATA 0xd
+#define CPR0_PLLD0 0x60
+#define CPR0_OPBD0 0xc0
+#define CPR0_PERD0 0xe0
+#define CPR0_PRIMBD0 0xa0
+#define CPR0_SCPID 0x120
+#define CPR0_PLLC0 0x40
+
+/* 405GP Clocking/Power Management/Chip Control regs */
+#define DCRN_CPC0_PLLMR 0xb0
+#define DCRN_405_CPC0_CR0 0xb1
+#define DCRN_405_CPC0_CR1 0xb2
+
#endif /* _PPC_BOOT_DCR_H_ */
diff --git a/arch/powerpc/boot/devtree.c b/arch/powerpc/boot/devtree.c
index c9951550ed2..e5dfe449731 100644
--- a/arch/powerpc/boot/devtree.c
+++ b/arch/powerpc/boot/devtree.c
@@ -74,6 +74,8 @@ void dt_fixup_cpu_clocks(u32 cpu, u32 tb, u32 bus)
if (bus > 0)
setprop_val(devp, "bus-frequency", bus);
}
+
+ timebase_period_ns = 1000000000 / tb;
}
void dt_fixup_clock(const char *path, u32 freq)
@@ -86,34 +88,38 @@ void dt_fixup_clock(const char *path, u32 freq)
}
}
+void dt_fixup_mac_address(u32 index, const u8 *addr)
+{
+ void *devp = find_node_by_prop_value(NULL, "linux,network-index",
+ (void*)&index, sizeof(index));
+
+ if (devp) {
+ printf("ENET%d: local-mac-address <-"
+ " %02x:%02x:%02x:%02x:%02x:%02x\n\r", index,
+ addr[0], addr[1], addr[2],
+ addr[3], addr[4], addr[5]);
+
+ setprop(devp, "local-mac-address", addr, 6);
+ }
+}
+
void __dt_fixup_mac_addresses(u32 startindex, ...)
{
va_list ap;
u32 index = startindex;
- void *devp;
const u8 *addr;
va_start(ap, startindex);
- while ((addr = va_arg(ap, const u8 *))) {
- devp = find_node_by_prop_value(NULL, "linux,network-index",
- (void*)&index, sizeof(index));
-
- printf("ENET%d: local-mac-address <-"
- " %02x:%02x:%02x:%02x:%02x:%02x\n\r", index,
- addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
- if (devp)
- setprop(devp, "local-mac-address", addr, 6);
+ while ((addr = va_arg(ap, const u8 *)))
+ dt_fixup_mac_address(index++, addr);
- index++;
- }
va_end(ap);
}
#define MAX_ADDR_CELLS 4
-#define MAX_RANGES 8
-static void get_reg_format(void *node, u32 *naddr, u32 *nsize)
+void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize)
{
if (getprop(node, "#address-cells", naddr, 4) != 4)
*naddr = 2;
@@ -207,7 +213,7 @@ static int find_range(u32 *reg, u32 *ranges, int nregaddr,
* In particular, PCI is not supported. Also, only the beginning of the
* reg block is tracked; size is ignored except in ranges.
*/
-static u32 dt_xlate_buf[MAX_ADDR_CELLS * MAX_RANGES * 3];
+static u32 prop_buf[MAX_PROP_LEN / 4];
static int dt_xlate(void *node, int res, int reglen, unsigned long *addr,
unsigned long *size)
@@ -216,14 +222,14 @@ static int dt_xlate(void *node, int res, int reglen, unsigned long *addr,
u32 this_addr[MAX_ADDR_CELLS];
void *parent;
u64 ret_addr, ret_size;
- u32 naddr, nsize, prev_naddr;
+ u32 naddr, nsize, prev_naddr, prev_nsize;
int buflen, offset;
parent = get_parent(node);
if (!parent)
return 0;
- get_reg_format(parent, &naddr, &nsize);
+ dt_get_reg_format(parent, &naddr, &nsize);
if (nsize > 2)
return 0;
@@ -231,41 +237,47 @@ static int dt_xlate(void *node, int res, int reglen, unsigned long *addr,
offset = (naddr + nsize) * res;
if (reglen < offset + naddr + nsize ||
- sizeof(dt_xlate_buf) < offset + naddr + nsize)
+ MAX_PROP_LEN < (offset + naddr + nsize) * 4)
return 0;
- copy_val(last_addr, dt_xlate_buf + offset, naddr);
+ copy_val(last_addr, prop_buf + offset, naddr);
- ret_size = dt_xlate_buf[offset + naddr];
+ ret_size = prop_buf[offset + naddr];
if (nsize == 2) {
ret_size <<= 32;
- ret_size |= dt_xlate_buf[offset + naddr + 1];
+ ret_size |= prop_buf[offset + naddr + 1];
}
- while ((node = get_parent(node))) {
+ for (;;) {
prev_naddr = naddr;
+ prev_nsize = nsize;
+ node = parent;
+
+ parent = get_parent(node);
+ if (!parent)
+ break;
- get_reg_format(node, &naddr, &nsize);
+ dt_get_reg_format(parent, &naddr, &nsize);
- buflen = getprop(node, "ranges", dt_xlate_buf,
- sizeof(dt_xlate_buf));
- if (buflen < 0)
+ buflen = getprop(node, "ranges", prop_buf,
+ sizeof(prop_buf));
+ if (buflen == 0)
continue;
- if (buflen > sizeof(dt_xlate_buf))
+ if (buflen < 0 || buflen > sizeof(prop_buf))
return 0;
- offset = find_range(last_addr, dt_xlate_buf, prev_naddr,
- naddr, nsize, buflen / 4);
+ offset = find_range(last_addr, prop_buf, prev_naddr,
+ naddr, prev_nsize, buflen / 4);
if (offset < 0)
return 0;
- copy_val(this_addr, dt_xlate_buf + offset, prev_naddr);
+ copy_val(this_addr, prop_buf + offset, prev_naddr);
if (!sub_reg(last_addr, this_addr))
return 0;
- copy_val(this_addr, dt_xlate_buf + offset + prev_naddr, naddr);
+ copy_val(this_addr, prop_buf + offset + prev_naddr, naddr);
if (!add_reg(last_addr, this_addr, naddr))
return 0;
@@ -292,16 +304,35 @@ int dt_xlate_reg(void *node, int res, unsigned long *addr, unsigned long *size)
{
int reglen;
- reglen = getprop(node, "reg", dt_xlate_buf, sizeof(dt_xlate_buf)) / 4;
+ reglen = getprop(node, "reg", prop_buf, sizeof(prop_buf)) / 4;
return dt_xlate(node, res, reglen, addr, size);
}
int dt_xlate_addr(void *node, u32 *buf, int buflen, unsigned long *xlated_addr)
{
- if (buflen > sizeof(dt_xlate_buf))
+ if (buflen > sizeof(prop_buf))
return 0;
- memcpy(dt_xlate_buf, buf, buflen);
+ memcpy(prop_buf, buf, buflen);
return dt_xlate(node, 0, buflen / 4, xlated_addr, NULL);
}
+
+int dt_is_compatible(void *node, const char *compat)
+{
+ char *buf = (char *)prop_buf;
+ int len, pos;
+
+ len = getprop(node, "compatible", buf, MAX_PROP_LEN);
+ if (len < 0)
+ return 0;
+
+ for (pos = 0; pos < len; pos++) {
+ if (!strcmp(buf + pos, compat))
+ return 1;
+
+ pos += strnlen(&buf[pos], len - pos);
+ }
+
+ return 0;
+}
diff --git a/arch/powerpc/boot/dts/bamboo.dts b/arch/powerpc/boot/dts/bamboo.dts
new file mode 100644
index 00000000000..a88ae3d218a
--- /dev/null
+++ b/arch/powerpc/boot/dts/bamboo.dts
@@ -0,0 +1,244 @@
+/*
+ * Device Tree Source for AMCC Bamboo
+ *
+ * Copyright (c) 2006, 2007 IBM Corp.
+ * Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ *
+ * FIXME: Draft only!
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ model = "amcc,bamboo";
+ compatible = "amcc,bamboo";
+ dcr-parent = <&/cpus/PowerPC,440EP@0>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,440EP@0 {
+ device_type = "cpu";
+ reg = <0>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ timebase-frequency = <0>; /* Filled in by zImage */
+ i-cache-line-size = <20>;
+ d-cache-line-size = <20>;
+ i-cache-size = <8000>;
+ d-cache-size = <8000>;
+ dcr-controller;
+ dcr-access-method = "native";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0 0>; /* Filled in by zImage */
+ };
+
+ UIC0: interrupt-controller0 {
+ compatible = "ibm,uic-440ep","ibm,uic";
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0c0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ UIC1: interrupt-controller1 {
+ compatible = "ibm,uic-440ep","ibm,uic";
+ interrupt-controller;
+ cell-index = <1>;
+ dcr-reg = <0d0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <1e 4 1f 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ SDR0: sdr {
+ compatible = "ibm,sdr-440ep";
+ dcr-reg = <00e 002>;
+ };
+
+ CPR0: cpr {
+ compatible = "ibm,cpr-440ep";
+ dcr-reg = <00c 002>;
+ };
+
+ plb {
+ compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ SDRAM0: sdram {
+ compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
+ dcr-reg = <010 2>;
+ };
+
+ DMA0: dma {
+ compatible = "ibm,dma-440ep", "ibm,dma-440gp";
+ dcr-reg = <100 027>;
+ };
+
+ MAL0: mcmal {
+ compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";
+ dcr-reg = <180 62>;
+ num-tx-chans = <4>;
+ num-rx-chans = <2>;
+ interrupt-parent = <&MAL0>;
+ interrupts = <0 1 2 3 4>;
+ #interrupt-cells = <1>;
+ interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
+ /*RXEOB*/ 1 &UIC0 b 4
+ /*SERR*/ 2 &UIC1 0 4
+ /*TXDE*/ 3 &UIC1 1 4
+ /*RXDE*/ 4 &UIC1 3 4>;
+ };
+
+ POB0: opb {
+ compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* Bamboo is oddball in the 44x world and doesn't use the ERPN
+ * bits.
+ */
+ ranges = <00000000 0 00000000 80000000
+ 80000000 0 80000000 80000000>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <7 4>;
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ EBC0: ebc {
+ compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
+ dcr-reg = <012 2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ ranges;
+ interrupts = <5 1>;
+ interrupt-parent = <&UIC1>;
+ };
+
+ UART0: serial@ef600300 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600300 8>;
+ virtual-reg = <ef600300>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ current-speed = <1c200>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0 4>;
+ };
+
+ UART1: serial@ef600400 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600400 8>;
+ virtual-reg = <ef600400>;
+ clock-frequency = <0>;
+ current-speed = <0>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <1 4>;
+ };
+
+ UART2: serial@ef600500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600500 8>;
+ virtual-reg = <ef600500>;
+ clock-frequency = <0>;
+ current-speed = <0>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <3 4>;
+ };
+
+ UART3: serial@ef600600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600600 8>;
+ virtual-reg = <ef600600>;
+ clock-frequency = <0>;
+ current-speed = <0>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <4 4>;
+ };
+
+ IIC0: i2c@ef600700 {
+ device_type = "i2c";
+ compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
+ reg = <ef600700 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <2 4>;
+ };
+
+ IIC1: i2c@ef600800 {
+ device_type = "i2c";
+ compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
+ reg = <ef600800 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <7 4>;
+ };
+
+ ZMII0: emac-zmii@ef600d00 {
+ device_type = "zmii-interface";
+ compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
+ reg = <ef600d00 c>;
+ };
+
+ EMAC0: ethernet@ef600e00 {
+ device_type = "network";
+ compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
+ interrupt-parent = <&UIC1>;
+ interrupts = <1c 4 1d 4>;
+ reg = <ef600e00 70>;
+ local-mac-address = [000000000000];
+ mal-device = <&MAL0>;
+ mal-tx-channel = <0 1>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rmii";
+ phy-map = <00000001>;
+ zmii-device = <&ZMII0>;
+ zmii-channel = <0>;
+ };
+
+ EMAC1: ethernet@ef600f00 {
+ device_type = "network";
+ compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
+ interrupt-parent = <&UIC1>;
+ interrupts = <1e 4 1f 4>;
+ reg = <ef600f00 70>;
+ local-mac-address = [000000000000];
+ mal-device = <&MAL0>;
+ mal-tx-channel = <2 3>;
+ mal-rx-channel = <1>;
+ cell-index = <1>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rmii";
+ phy-map = <00000001>;
+ zmii-device = <&ZMII0>;
+ zmii-channel = <1>;
+ };
+ };
+ };
+
+ chosen {
+ linux,stdout-path = "/plb/opb/serial@ef600300";
+ bootargs = "console=ttyS0,115200";
+ };
+};
diff --git a/arch/powerpc/boot/dts/ebony.dts b/arch/powerpc/boot/dts/ebony.dts
index c5f99613fc7..bc259972aaa 100644
--- a/arch/powerpc/boot/dts/ebony.dts
+++ b/arch/powerpc/boot/dts/ebony.dts
@@ -9,10 +9,6 @@
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
- *
- * To build:
- * dtc -I dts -O asm -o ebony.S -b 0 ebony.dts
- * dtc -I dts -O dtb -o ebony.dtb -b 0 ebony.dts
*/
/ {
@@ -142,13 +138,16 @@
interrupt-parent = <&UIC1>;
small-flash@0,80000 {
- device_type = "rom";
- compatible = "direct-mapped";
- probe-type = "JEDEC";
+ compatible = "jedec-flash";
bank-width = <1>;
- partitions = <0 80000>;
- partition-names = "OpenBIOS";
reg = <0 80000 80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "OpenBIOS";
+ reg = <0 80000>;
+ read-only;
+ };
};
ds1743@1,0 {
@@ -158,14 +157,19 @@
};
large-flash@2,0 {
- device_type = "rom";
- compatible = "direct-mapped";
- probe-type = "JEDEC";
+ compatible = "jedec-flash";
bank-width = <1>;
- partitions = <0 380000
- 380000 80000>;
- partition-names = "fs", "firmware";
reg = <2 0 400000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "fs";
+ reg = <0 380000>;
+ };
+ partition@380000 {
+ label = "firmware";
+ reg = <380000 80000>;
+ };
};
ir@3,0 {
@@ -175,6 +179,7 @@
fpga@7,0 {
compatible = "Ebony-FPGA";
reg = <7 0 10>;
+ virtual-reg = <e8300000>;
};
};
diff --git a/arch/powerpc/boot/dts/ep88xc.dts b/arch/powerpc/boot/dts/ep88xc.dts
new file mode 100644
index 00000000000..02705f29979
--- /dev/null
+++ b/arch/powerpc/boot/dts/ep88xc.dts
@@ -0,0 +1,214 @@
+/*
+ * EP88xC Device Tree Source
+ *
+ * Copyright 2006 MontaVista Software, Inc.
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+
+/ {
+ model = "EP88xC";
+ compatible = "fsl,ep88xc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,885@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <d#16>;
+ i-cache-line-size = <d#16>;
+ d-cache-size = <d#8192>;
+ i-cache-size = <d#8192>;
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ interrupts = <f 2>; // decrementer interrupt
+ interrupt-parent = <&PIC>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0>;
+ };
+
+ localbus@fa200100 {
+ compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <fa200100 40>;
+
+ ranges = <
+ 0 0 fc000000 04000000
+ 3 0 fa000000 01000000
+ >;
+
+ flash@0,2000000 {
+ compatible = "cfi-flash";
+ reg = <0 2000000 2000000>;
+ bank-width = <4>;
+ device-width = <2>;
+ };
+
+ board-control@3,400000 {
+ reg = <3 400000 10>;
+ compatible = "fsl,ep88xc-bcsr";
+ };
+ };
+
+ soc@fa200000 {
+ compatible = "fsl,mpc885", "fsl,pq1-soc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <0 fa200000 00004000>;
+ bus-frequency = <0>;
+
+ // Temporary -- will go away once kernel uses ranges for get_immrbase().
+ reg = <fa200000 4000>;
+
+ mdio@e00 {
+ compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
+ reg = <e00 188>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PHY0: ethernet-phy@0 {
+ reg = <0>;
+ device_type = "ethernet-phy";
+ };
+
+ PHY1: ethernet-phy@1 {
+ reg = <1>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ ethernet@e00 {
+ device_type = "network";
+ compatible = "fsl,mpc885-fec-enet",
+ "fsl,pq1-fec-enet";
+ reg = <e00 188>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <3 1>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&PHY0>;
+ linux,network-index = <0>;
+ };
+
+ ethernet@1e00 {
+ device_type = "network";
+ compatible = "fsl,mpc885-fec-enet",
+ "fsl,pq1-fec-enet";
+ reg = <1e00 188>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <7 1>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&PHY1>;
+ linux,network-index = <1>;
+ };
+
+ PIC: interrupt-controller@0 {
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0 24>;
+ compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
+ };
+
+ pcmcia@80 {
+ #address-cells = <3>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ compatible = "fsl,pq-pcmcia";
+ device_type = "pcmcia";
+ reg = <80 80>;
+ interrupt-parent = <&PIC>;
+ interrupts = <d 1>;
+ };
+
+ cpm@9c0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc885-cpm", "fsl,cpm1";
+ command-proc = <9c0>;
+ interrupts = <0>; // cpm error interrupt
+ interrupt-parent = <&CPM_PIC>;
+ reg = <9c0 40>;
+ ranges;
+
+ muram@2000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 2000 2000>;
+
+ data@0 {
+ compatible = "fsl,cpm-muram-data";
+ reg = <0 1c00>;
+ };
+ };
+
+ brg@9f0 {
+ compatible = "fsl,mpc885-brg",
+ "fsl,cpm1-brg",
+ "fsl,cpm-brg";
+ reg = <9f0 10>;
+ };
+
+ CPM_PIC: interrupt-controller@930 {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <5 2 0 2>;
+ interrupt-parent = <&PIC>;
+ reg = <930 20>;
+ compatible = "fsl,mpc885-cpm-pic",
+ "fsl,cpm1-pic";
+ };
+
+ // MON-1
+ serial@a80 {
+ device_type = "serial";
+ compatible = "fsl,mpc885-smc-uart",
+ "fsl,cpm1-smc-uart";
+ reg = <a80 10 3e80 40>;
+ interrupts = <4>;
+ interrupt-parent = <&CPM_PIC>;
+ fsl,cpm-brg = <1>;
+ fsl,cpm-command = <0090>;
+ linux,planetcore-label = "SMC1";
+ };
+
+ // SER-1
+ serial@a20 {
+ device_type = "serial";
+ compatible = "fsl,mpc885-scc-uart",
+ "fsl,cpm1-scc-uart";
+ reg = <a20 20 3d00 80>;
+ interrupts = <1d>;
+ interrupt-parent = <&CPM_PIC>;
+ fsl,cpm-brg = <2>;
+ fsl,cpm-command = <0040>;
+ linux,planetcore-label = "SCC2";
+ };
+
+ usb@a00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,mpc885-usb",
+ "fsl,cpm1-usb";
+ reg = <a00 18 1c00 80>;
+ interrupt-parent = <&CPM_PIC>;
+ interrupts = <1e>;
+ fsl,cpm-command = <0000>;
+ };
+ };
+ };
+};
diff --git a/arch/powerpc/boot/dts/holly.dts b/arch/powerpc/boot/dts/holly.dts
index 80a4fab8ee3..b5d87895fe0 100644
--- a/arch/powerpc/boot/dts/holly.dts
+++ b/arch/powerpc/boot/dts/holly.dts
@@ -8,10 +8,6 @@
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
- *
- * To build:
- * dtc -I dts -O asm -o holly.S -b 0 holly.dts
- * dtc -I dts -O dtb -o holly.dtb -b 0 holly.dts
*/
/ {
@@ -35,7 +31,6 @@
timebase-frequency = <2faf080>;
clock-frequency = <23c34600>;
bus-frequency = <bebc200>;
- 32-bit;
};
};
diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
new file mode 100644
index 00000000000..c824e8f0645
--- /dev/null
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -0,0 +1,252 @@
+/*
+ * Device Tree Source for AMCC Kilauea (405EX)
+ *
+ * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "amcc,kilauea";
+ compatible = "amcc,kilauea";
+ dcr-parent = <&/cpus/PowerPC,405EX@0>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,405EX@0 {
+ device_type = "cpu";
+ reg = <0>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ timebase-frequency = <0>; /* Filled in by U-Boot */
+ i-cache-line-size = <20>;
+ d-cache-line-size = <20>;
+ i-cache-size = <4000>; /* 16 kB */
+ d-cache-size = <4000>; /* 16 kB */
+ dcr-controller;
+ dcr-access-method = "native";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0>; /* Filled in by U-Boot */
+ };
+
+ UIC0: interrupt-controller {
+ compatible = "ibm,uic-405ex", "ibm,uic";
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0c0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ UIC1: interrupt-controller1 {
+ compatible = "ibm,uic-405ex","ibm,uic";
+ interrupt-controller;
+ cell-index = <1>;
+ dcr-reg = <0d0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <1e 4 1f 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC2: interrupt-controller2 {
+ compatible = "ibm,uic-405ex","ibm,uic";
+ interrupt-controller;
+ cell-index = <2>;
+ dcr-reg = <0e0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <1c 4 1d 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ plb {
+ compatible = "ibm,plb-405ex", "ibm,plb4";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+
+ SDRAM0: memory-controller {
+ compatible = "ibm,sdram-405ex";
+ dcr-reg = <010 2>;
+ };
+
+ MAL0: mcmal {
+ compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
+ dcr-reg = <180 62>;
+ num-tx-chans = <2>;
+ num-rx-chans = <2>;
+ interrupt-parent = <&MAL0>;
+ interrupts = <0 1 2 3 4>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
+ /*RXEOB*/ 1 &UIC0 b 4
+ /*SERR*/ 2 &UIC1 0 4
+ /*TXDE*/ 3 &UIC1 1 4
+ /*RXDE*/ 4 &UIC1 2 4>;
+ interrupt-map-mask = <ffffffff>;
+ };
+
+ POB0: opb {
+ compatible = "ibm,opb-405ex", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <80000000 80000000 10000000
+ ef600000 ef600000 a00000
+ f0000000 f0000000 10000000>;
+ dcr-reg = <0a0 5>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+
+ EBC0: ebc {
+ compatible = "ibm,ebc-405ex", "ibm,ebc";
+ dcr-reg = <012 2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ /* ranges property is supplied by U-Boot */
+ interrupts = <5 1>;
+ interrupt-parent = <&UIC1>;
+
+ nor_flash@0,0 {
+ compatible = "amd,s29gl512n", "cfi-flash";
+ bank-width = <2>;
+ reg = <0 000000 4000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "kernel";
+ reg = <0 200000>;
+ };
+ partition@200000 {
+ label = "root";
+ reg = <200000 200000>;
+ };
+ partition@400000 {
+ label = "user";
+ reg = <400000 3b60000>;
+ };
+ partition@3f60000 {
+ label = "env";
+ reg = <3f60000 40000>;
+ };
+ partition@3fa0000 {
+ label = "u-boot";
+ reg = <3fa0000 60000>;
+ };
+ };
+ };
+
+ UART0: serial@ef600200 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600200 8>;
+ virtual-reg = <ef600200>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ current-speed = <0>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <1a 4>;
+ };
+
+ UART1: serial@ef600300 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600300 8>;
+ virtual-reg = <ef600300>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ current-speed = <0>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <1 4>;
+ };
+
+ IIC0: i2c@ef600400 {
+ device_type = "i2c";
+ compatible = "ibm,iic-405ex", "ibm,iic";
+ reg = <ef600400 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <2 4>;
+ };
+
+ IIC1: i2c@ef600500 {
+ device_type = "i2c";
+ compatible = "ibm,iic-405ex", "ibm,iic";
+ reg = <ef600500 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <7 4>;
+ };
+
+
+ RGMII0: emac-rgmii@ef600b00 {
+ device_type = "rgmii-interface";
+ compatible = "ibm,rgmii-405ex", "ibm,rgmii";
+ reg = <ef600b00 104>;
+ };
+
+ EMAC0: ethernet@ef600900 {
+ linux,network-index = <0>;
+ device_type = "network";
+ compatible = "ibm,emac-405ex", "ibm,emac4";
+ interrupt-parent = <&EMAC0>;
+ interrupts = <0 1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0 &UIC0 18 4
+ /*Wake*/ 1 &UIC1 1d 4>;
+ reg = <ef600900 70>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <0>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rgmii";
+ phy-map = <00000000>;
+ rgmii-device = <&RGMII0>;
+ rgmii-channel = <0>;
+ };
+
+ EMAC1: ethernet@ef600a00 {
+ linux,network-index = <1>;
+ device_type = "network";
+ compatible = "ibm,emac-405ex", "ibm,emac4";
+ interrupt-parent = <&EMAC1>;
+ interrupts = <0 1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0 &UIC0 19 4
+ /*Wake*/ 1 &UIC1 1f 4>;
+ reg = <ef600a00 70>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <1>;
+ mal-rx-channel = <1>;
+ cell-index = <1>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rgmii";
+ phy-map = <00000000>;
+ rgmii-device = <&RGMII0>;
+ rgmii-channel = <1>;
+ };
+ };
+ };
+};
diff --git a/arch/powerpc/boot/dts/kuroboxHD.dts b/arch/powerpc/boot/dts/kuroboxHD.dts
index 122537419d9..ec71ab819fe 100644
--- a/arch/powerpc/boot/dts/kuroboxHD.dts
+++ b/arch/powerpc/boot/dts/kuroboxHD.dts
@@ -15,9 +15,6 @@
XXXX add flash parts, rtc, ??
-build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
-
-
*/
/ {
@@ -50,7 +47,6 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
compatible = "mpc10x";
store-gathering = <0>; /* 0 == off, !0 == on */
@@ -72,7 +68,7 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
rtc@32 {
device_type = "rtc";
- compatible = "ricoh,rs5c372b";
+ compatible = "ricoh,rs5c372a";
reg = <32>;
};
};
@@ -83,7 +79,7 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
reg = <80004500 8>;
clock-frequency = <5d08d88>;
current-speed = <2580>;
- interrupts = <9 2>;
+ interrupts = <9 0>;
interrupt-parent = <&mpic>;
};
@@ -104,7 +100,6 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
compatible = "chrp,open-pic";
interrupt-controller;
reg = <80040000 40000>;
- built-in;
};
pci@fec00000 {
diff --git a/arch/powerpc/boot/dts/kuroboxHG.dts b/arch/powerpc/boot/dts/kuroboxHG.dts
index 579aa8b967d..32ecd231992 100644
--- a/arch/powerpc/boot/dts/kuroboxHG.dts
+++ b/arch/powerpc/boot/dts/kuroboxHG.dts
@@ -15,9 +15,6 @@
XXXX add flash parts, rtc, ??
-build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
-
-
*/
/ {
@@ -50,7 +47,6 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
compatible = "mpc10x";
store-gathering = <0>; /* 0 == off, !0 == on */
@@ -72,7 +68,7 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
rtc@32 {
device_type = "rtc";
- compatible = "ricoh,rs5c372b";
+ compatible = "ricoh,rs5c372a";
reg = <32>;
};
};
@@ -83,7 +79,7 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
reg = <80004500 8>;
clock-frequency = <7c044a8>;
current-speed = <2580>;
- interrupts = <9 2>;
+ interrupts = <9 0>;
interrupt-parent = <&mpic>;
};
@@ -104,7 +100,6 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
compatible = "chrp,open-pic";
interrupt-controller;
reg = <80040000 40000>;
- built-in;
};
pci@fec00000 {
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index d29308fe4c2..bc45f5fbb06 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -19,7 +19,7 @@
/ {
model = "fsl,lite5200";
// revision = "1.0";
- compatible = "fsl,lite5200\0generic-mpc5200";
+ compatible = "fsl,lite5200","generic-mpc5200";
#address-cells = <1>;
#size-cells = <1>;
@@ -37,7 +37,6 @@
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
- 32-bit;
};
};
@@ -50,10 +49,9 @@
model = "fsl,mpc5200";
compatible = "mpc5200";
revision = ""; // from bootloader
- #interrupt-cells = <3>;
device_type = "soc";
- ranges = <0 f0000000 f0010000>;
- reg = <f0000000 00010000>;
+ ranges = <0 f0000000 0000c000>;
+ reg = <f0000000 00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
@@ -69,7 +67,6 @@
device_type = "interrupt-controller";
compatible = "mpc5200-pic";
reg = <500 80>;
- built-in;
};
gpt@600 { // General Purpose Timer
@@ -185,27 +182,6 @@
interrupt-parent = <&mpc5200_pic>;
};
- pci@0d00 {
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- device_type = "pci";
- compatible = "mpc5200-pci";
- reg = <d00 100>;
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
- c000 0 0 2 &mpc5200_pic 0 0 3
- c000 0 0 3 &mpc5200_pic 0 0 3
- c000 0 0 4 &mpc5200_pic 0 0 3>;
- clock-frequency = <0>; // From boot loader
- interrupts = <2 8 0 2 9 0 2 a 0>;
- interrupt-parent = <&mpc5200_pic>;
- bus-range = <0 0>;
- ranges = <42000000 0 80000000 80000000 0 20000000
- 02000000 0 a0000000 a0000000 0 10000000
- 01000000 0 00000000 b0000000 0 01000000>;
- };
-
spi@f00 {
device_type = "spi";
compatible = "mpc5200-spi";
@@ -216,7 +192,7 @@
usb@1000 {
device_type = "usb-ohci-be";
- compatible = "mpc5200-ohci\0ohci-be";
+ compatible = "mpc5200-ohci","ohci-be";
reg = <1000 ff>;
interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -317,7 +293,7 @@
i2c@3d00 {
device_type = "i2c";
- compatible = "mpc5200-i2c\0fsl-i2c";
+ compatible = "mpc5200-i2c","fsl-i2c";
cell-index = <0>;
reg = <3d00 40>;
interrupts = <2 f 0>;
@@ -327,7 +303,7 @@
i2c@3d40 {
device_type = "i2c";
- compatible = "mpc5200-i2c\0fsl-i2c";
+ compatible = "mpc5200-i2c","fsl-i2c";
cell-index = <1>;
reg = <3d40 40>;
interrupts = <2 10 0>;
@@ -336,8 +312,29 @@
};
sram@8000 {
device_type = "sram";
- compatible = "mpc5200-sram\0sram";
+ compatible = "mpc5200-sram","sram";
reg = <8000 4000>;
};
};
+
+ pci@f0000d00 {
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ compatible = "mpc5200-pci";
+ reg = <f0000d00 100>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
+ c000 0 0 2 &mpc5200_pic 0 0 3
+ c000 0 0 3 &mpc5200_pic 0 0 3
+ c000 0 0 4 &mpc5200_pic 0 0 3>;
+ clock-frequency = <0>; // From boot loader
+ interrupts = <2 8 0 2 9 0 2 a 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ bus-range = <0 0>;
+ ranges = <42000000 0 80000000 80000000 0 20000000
+ 02000000 0 a0000000 a0000000 0 10000000
+ 01000000 0 00000000 b0000000 0 01000000>;
+ };
};
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index f242531f045..a6bb1d0558e 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -19,7 +19,7 @@
/ {
model = "fsl,lite5200b";
// revision = "1.0";
- compatible = "fsl,lite5200b\0generic-mpc5200";
+ compatible = "fsl,lite5200b","generic-mpc5200";
#address-cells = <1>;
#size-cells = <1>;
@@ -37,7 +37,6 @@
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
- 32-bit;
};
};
@@ -50,15 +49,14 @@
model = "fsl,mpc5200b";
compatible = "mpc5200";
revision = ""; // from bootloader
- #interrupt-cells = <3>;
device_type = "soc";
- ranges = <0 f0000000 f0010000>;
- reg = <f0000000 00010000>;
+ ranges = <0 f0000000 0000c000>;
+ reg = <f0000000 00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
cdm@200 {
- compatible = "mpc5200b-cdm\0mpc5200-cdm";
+ compatible = "mpc5200b-cdm","mpc5200-cdm";
reg = <200 38>;
};
@@ -67,13 +65,12 @@
interrupt-controller;
#interrupt-cells = <3>;
device_type = "interrupt-controller";
- compatible = "mpc5200b-pic\0mpc5200-pic";
+ compatible = "mpc5200b-pic","mpc5200-pic";
reg = <500 80>;
- built-in;
};
gpt@600 { // General Purpose Timer
- compatible = "mpc5200b-gpt\0mpc5200-gpt";
+ compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <0>;
reg = <600 10>;
@@ -83,7 +80,7 @@
};
gpt@610 { // General Purpose Timer
- compatible = "mpc5200b-gpt\0mpc5200-gpt";
+ compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <1>;
reg = <610 10>;
@@ -92,7 +89,7 @@
};
gpt@620 { // General Purpose Timer
- compatible = "mpc5200b-gpt\0mpc5200-gpt";
+ compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <2>;
reg = <620 10>;
@@ -101,7 +98,7 @@
};
gpt@630 { // General Purpose Timer
- compatible = "mpc5200b-gpt\0mpc5200-gpt";
+ compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <3>;
reg = <630 10>;
@@ -110,7 +107,7 @@
};
gpt@640 { // General Purpose Timer
- compatible = "mpc5200b-gpt\0mpc5200-gpt";
+ compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <4>;
reg = <640 10>;
@@ -119,7 +116,7 @@
};
gpt@650 { // General Purpose Timer
- compatible = "mpc5200b-gpt\0mpc5200-gpt";
+ compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <5>;
reg = <650 10>;
@@ -128,7 +125,7 @@
};
gpt@660 { // General Purpose Timer
- compatible = "mpc5200b-gpt\0mpc5200-gpt";
+ compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <6>;
reg = <660 10>;
@@ -137,7 +134,7 @@
};
gpt@670 { // General Purpose Timer
- compatible = "mpc5200b-gpt\0mpc5200-gpt";
+ compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <7>;
reg = <670 10>;
@@ -146,7 +143,7 @@
};
rtc@800 { // Real time clock
- compatible = "mpc5200b-rtc\0mpc5200-rtc";
+ compatible = "mpc5200b-rtc","mpc5200-rtc";
device_type = "rtc";
reg = <800 100>;
interrupts = <1 5 0 1 6 0>;
@@ -155,7 +152,7 @@
mscan@900 {
device_type = "mscan";
- compatible = "mpc5200b-mscan\0mpc5200-mscan";
+ compatible = "mpc5200b-mscan","mpc5200-mscan";
cell-index = <0>;
interrupts = <2 11 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -164,7 +161,7 @@
mscan@980 {
device_type = "mscan";
- compatible = "mpc5200b-mscan\0mpc5200-mscan";
+ compatible = "mpc5200b-mscan","mpc5200-mscan";
cell-index = <1>;
interrupts = <2 12 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -172,48 +169,22 @@
};
gpio@b00 {
- compatible = "mpc5200b-gpio\0mpc5200-gpio";
+ compatible = "mpc5200b-gpio","mpc5200-gpio";
reg = <b00 40>;
interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>;
};
gpio-wkup@c00 {
- compatible = "mpc5200b-gpio-wkup\0mpc5200-gpio-wkup";
+ compatible = "mpc5200b-gpio-wkup","mpc5200-gpio-wkup";
reg = <c00 40>;
interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>;
};
- pci@0d00 {
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- device_type = "pci";
- compatible = "mpc5200b-pci\0mpc5200-pci";
- reg = <d00 100>;
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
- c000 0 0 2 &mpc5200_pic 1 1 3
- c000 0 0 3 &mpc5200_pic 1 2 3
- c000 0 0 4 &mpc5200_pic 1 3 3
-
- c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
- c800 0 0 2 &mpc5200_pic 1 2 3
- c800 0 0 3 &mpc5200_pic 1 3 3
- c800 0 0 4 &mpc5200_pic 0 0 3>;
- clock-frequency = <0>; // From boot loader
- interrupts = <2 8 0 2 9 0 2 a 0>;
- interrupt-parent = <&mpc5200_pic>;
- bus-range = <0 0>;
- ranges = <42000000 0 80000000 80000000 0 20000000
- 02000000 0 a0000000 a0000000 0 10000000
- 01000000 0 00000000 b0000000 0 01000000>;
- };
-
spi@f00 {
device_type = "spi";
- compatible = "mpc5200b-spi\0mpc5200-spi";
+ compatible = "mpc5200b-spi","mpc5200-spi";
reg = <f00 20>;
interrupts = <2 d 0 2 e 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -221,7 +192,7 @@
usb@1000 {
device_type = "usb-ohci-be";
- compatible = "mpc5200b-ohci\0mpc5200-ohci\0ohci-be";
+ compatible = "mpc5200b-ohci","mpc5200-ohci","ohci-be";
reg = <1000 ff>;
interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -229,7 +200,7 @@
bestcomm@1200 {
device_type = "dma-controller";
- compatible = "mpc5200b-bestcomm\0mpc5200-bestcomm";
+ compatible = "mpc5200b-bestcomm","mpc5200-bestcomm";
reg = <1200 80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
@@ -239,13 +210,13 @@
};
xlb@1f00 {
- compatible = "mpc5200b-xlb\0mpc5200-xlb";
+ compatible = "mpc5200b-xlb","mpc5200-xlb";
reg = <1f00 100>;
};
serial@2000 { // PSC1
device_type = "serial";
- compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
+ compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
cell-index = <0>;
reg = <2000 100>;
@@ -256,7 +227,7 @@
// PSC2 in ac97 mode example
//ac97@2200 { // PSC2
// device_type = "sound";
- // compatible = "mpc5200b-psc-ac97\0mpc5200-psc-ac97";
+ // compatible = "mpc5200b-psc-ac97","mpc5200-psc-ac97";
// cell-index = <1>;
// reg = <2200 100>;
// interrupts = <2 2 0>;
@@ -276,7 +247,7 @@
// PSC4 in uart mode example
//serial@2600 { // PSC4
// device_type = "serial";
- // compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
+ // compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
// cell-index = <3>;
// reg = <2600 100>;
// interrupts = <2 b 0>;
@@ -286,7 +257,7 @@
// PSC5 in uart mode example
//serial@2800 { // PSC5
// device_type = "serial";
- // compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
+ // compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
// cell-index = <4>;
// reg = <2800 100>;
// interrupts = <2 c 0>;
@@ -296,7 +267,7 @@
// PSC6 in spi mode example
//spi@2c00 { // PSC6
// device_type = "spi";
- // compatible = "mpc5200b-psc-spi\0mpc5200-psc-spi";
+ // compatible = "mpc5200b-psc-spi","mpc5200-psc-spi";
// cell-index = <5>;
// reg = <2c00 100>;
// interrupts = <2 4 0>;
@@ -305,7 +276,7 @@
ethernet@3000 {
device_type = "network";
- compatible = "mpc5200b-fec\0mpc5200-fec";
+ compatible = "mpc5200b-fec","mpc5200-fec";
reg = <3000 800>;
mac-address = [ 02 03 04 05 06 07 ]; // Bad!
interrupts = <2 5 0>;
@@ -314,7 +285,7 @@
ata@3a00 {
device_type = "ata";
- compatible = "mpc5200b-ata\0mpc5200-ata";
+ compatible = "mpc5200b-ata","mpc5200-ata";
reg = <3a00 100>;
interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -322,7 +293,7 @@
i2c@3d00 {
device_type = "i2c";
- compatible = "mpc5200b-i2c\0mpc5200-i2c\0fsl-i2c";
+ compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c";
cell-index = <0>;
reg = <3d00 40>;
interrupts = <2 f 0>;
@@ -332,7 +303,7 @@
i2c@3d40 {
device_type = "i2c";
- compatible = "mpc5200b-i2c\0mpc5200-i2c\0fsl-i2c";
+ compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c";
cell-index = <1>;
reg = <3d40 40>;
interrupts = <2 10 0>;
@@ -341,8 +312,34 @@
};
sram@8000 {
device_type = "sram";
- compatible = "mpc5200b-sram\0mpc5200-sram\0sram";
+ compatible = "mpc5200b-sram","mpc5200-sram","sram";
reg = <8000 4000>;
};
};
+
+ pci@f0000d00 {
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ compatible = "mpc5200b-pci","mpc5200-pci";
+ reg = <f0000d00 100>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
+ c000 0 0 2 &mpc5200_pic 1 1 3
+ c000 0 0 3 &mpc5200_pic 1 2 3
+ c000 0 0 4 &mpc5200_pic 1 3 3
+
+ c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
+ c800 0 0 2 &mpc5200_pic 1 2 3
+ c800 0 0 3 &mpc5200_pic 1 3 3
+ c800 0 0 4 &mpc5200_pic 0 0 3>;
+ clock-frequency = <0>; // From boot loader
+ interrupts = <2 8 0 2 9 0 2 a 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ bus-range = <0 0>;
+ ranges = <42000000 0 80000000 80000000 0 20000000
+ 02000000 0 a0000000 a0000000 0 10000000
+ 01000000 0 00000000 b0000000 0 01000000>;
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc7448hpc2.dts b/arch/powerpc/boot/dts/mpc7448hpc2.dts
index b9158eb2797..8fb54238743 100644
--- a/arch/powerpc/boot/dts/mpc7448hpc2.dts
+++ b/arch/powerpc/boot/dts/mpc7448hpc2.dts
@@ -31,7 +31,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
clock-frequency = <0>; // From U-Boot
bus-frequency = <0>; // From U-Boot
- 32-bit;
};
};
@@ -44,7 +43,6 @@
tsi108@c0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "tsi-bridge";
ranges = <00000000 c0000000 00010000>;
reg = <c0000000 00010000>;
@@ -80,6 +78,7 @@
};
ethernet@6200 {
+ linux,network-index = <0>;
#size-cells = <0>;
device_type = "network";
compatible = "tsi108-ethernet";
@@ -92,6 +91,7 @@
};
ethernet@6600 {
+ linux,network-index = <1>;
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
@@ -128,7 +128,6 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <7400 400>;
- built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
@@ -180,12 +179,14 @@
device_type = "pic-router";
#address-cells = <0>;
#interrupt-cells = <2>;
- built-in;
big-endian;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
};
};
+ chosen {
+ linux,stdout-path = "/tsi108@c0000000/serial@7808";
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts b/arch/powerpc/boot/dts/mpc8272ads.dts
index 1934b800278..7285ca1325f 100644
--- a/arch/powerpc/boot/dts/mpc8272ads.dts
+++ b/arch/powerpc/boot/dts/mpc8272ads.dts
@@ -10,207 +10,240 @@
*/
/ {
- model = "MPC8272ADS";
- compatible = "MPC8260ADS";
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,8272@0 {
- device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <20>; // 32 bytes
- i-cache-line-size = <20>; // 32 bytes
- d-cache-size = <4000>; // L1, 16K
- i-cache-size = <4000>; // L1, 16K
- timebase-frequency = <0>;
- bus-frequency = <0>;
- clock-frequency = <0>;
- 32-bit;
- };
- };
-
- pci_pic: interrupt-controller@f8200000 {
- #address-cells = <0>;
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <f8200000 f8200004>;
- built-in;
- device_type = "pci-pic";
- };
- memory {
- device_type = "memory";
- reg = <00000000 4000000 f4500000 00000020>;
- };
-
- chosen {
- name = "chosen";
- linux,platform = <0>;
- interrupt-controller = <&Cpm_pic>;
- };
-
- soc8272@f0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- #interrupt-cells = <2>;
- device_type = "soc";
- ranges = <00000000 f0000000 00053000>;
- reg = <f0000000 10000>;
-
- mdio@0 {
- device_type = "mdio";
- compatible = "fs_enet";
- reg = <0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- phy0:ethernet-phy@0 {
- interrupt-parent = <&Cpm_pic>;
- interrupts = <17 4>;
- reg = <0>;
- bitbang = [ 12 12 13 02 02 01 ];
- device_type = "ethernet-phy";
- };
- phy1:ethernet-phy@1 {
- interrupt-parent = <&Cpm_pic>;
- interrupts = <17 4>;
- bitbang = [ 12 12 13 02 02 01 ];
- reg = <3>;
- device_type = "ethernet-phy";
- };
- };
-
- ethernet@24000 {
- #address-cells = <1>;
- #size-cells = <0>;
- device_type = "network";
- device-id = <1>;
- compatible = "fs_enet";
- model = "FCC";
- reg = <11300 20 8400 100 11380 30>;
- mac-address = [ 00 11 2F 99 43 54 ];
- interrupts = <20 2>;
- interrupt-parent = <&Cpm_pic>;
- phy-handle = <&Phy0>;
- rx-clock = <13>;
- tx-clock = <12>;
- };
-
- ethernet@25000 {
- device_type = "network";
- device-id = <2>;
- compatible = "fs_enet";
- model = "FCC";
- reg = <11320 20 8500 100 113b0 30>;
- mac-address = [ 00 11 2F 99 44 54 ];
- interrupts = <21 2>;
- interrupt-parent = <&Cpm_pic>;
- phy-handle = <&Phy1>;
- rx-clock = <17>;
- tx-clock = <18>;
- };
-
- cpm@f0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- #interrupt-cells = <2>;
- device_type = "cpm";
- model = "CPM2";
- ranges = <00000000 00000000 20000>;
- reg = <0 20000>;
- command-proc = <119c0>;
- brg-frequency = <17D7840>;
- cpm_clk = <BEBC200>;
-
- scc@11a00 {
- device_type = "serial";
- compatible = "cpm_uart";
- model = "SCC";
- device-id = <1>;
- reg = <11a00 20 8000 100>;
- current-speed = <1c200>;
- interrupts = <28 2>;
- interrupt-parent = <&Cpm_pic>;
- clock-setup = <0 00ffffff>;
- rx-clock = <1>;
- tx-clock = <1>;
- };
-
- scc@11a60 {
- device_type = "serial";
- compatible = "cpm_uart";
- model = "SCC";
- device-id = <4>;
- reg = <11a60 20 8300 100>;
- current-speed = <1c200>;
- interrupts = <2b 2>;
- interrupt-parent = <&Cpm_pic>;
- clock-setup = <1b ffffff00>;
- rx-clock = <4>;
- tx-clock = <4>;
- };
-
- };
- cpm_pic:interrupt-controller@10c00 {
- #address-cells = <0>;
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <10c00 80>;
- built-in;
- device_type = "cpm-pic";
- compatible = "CPM2";
- };
- pci@0500 {
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "8272";
- device_type = "pci";
- reg = <10430 4dc>;
- clock-frequency = <3f940aa>;
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x16 */
- b000 0 0 1 f8200000 40 8
- b000 0 0 2 f8200000 41 8
- b000 0 0 3 f8200000 42 8
- b000 0 0 4 f8200000 43 8
-
- /* IDSEL 0x17 */
- b800 0 0 1 f8200000 43 8
- b800 0 0 2 f8200000 40 8
- b800 0 0 3 f8200000 41 8
- b800 0 0 4 f8200000 42 8
-
- /* IDSEL 0x18 */
- c000 0 0 1 f8200000 42 8
- c000 0 0 2 f8200000 43 8
- c000 0 0 3 f8200000 40 8
- c000 0 0 4 f8200000 41 8>;
- interrupt-parent = <&Cpm_pic>;
- interrupts = <14 8>;
- bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 40000000
- 01000000 0 00000000 f6000000 0 02000000>;
- };
+ model = "MPC8272ADS";
+ compatible = "fsl,mpc8272ads";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8272@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <d#32>;
+ i-cache-line-size = <d#32>;
+ d-cache-size = <d#16384>;
+ i-cache-size = <d#16384>;
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0>;
+ };
+
+ localbus@f0010100 {
+ compatible = "fsl,mpc8272-localbus",
+ "fsl,pq2-localbus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <f0010100 40>;
+
+ ranges = <0 0 fe000000 02000000
+ 1 0 f4500000 00008000
+ 3 0 f8200000 00008000>;
+
+ flash@0,0 {
+ compatible = "jedec-flash";
+ reg = <0 0 2000000>;
+ bank-width = <4>;
+ device-width = <1>;
+ };
+
+ board-control@1,0 {
+ reg = <1 0 20>;
+ compatible = "fsl,mpc8272ads-bcsr";
+ };
+
+ PCI_PIC: interrupt-controller@3,0 {
+ compatible = "fsl,mpc8272ads-pci-pic",
+ "fsl,pq2ads-pci-pic";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ reg = <3 0 8>;
+ interrupt-parent = <&PIC>;
+ interrupts = <14 8>;
+ };
+ };
+
+
+ pci@f0010800 {
+ device_type = "pci";
+ reg = <f0010800 10c f00101ac 8 f00101c4 8>;
+ compatible = "fsl,mpc8272-pci", "fsl,pq2-pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ clock-frequency = <d#66666666>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x16 */
+ b000 0 0 1 &PCI_PIC 0
+ b000 0 0 2 &PCI_PIC 1
+ b000 0 0 3 &PCI_PIC 2
+ b000 0 0 4 &PCI_PIC 3
+
+ /* IDSEL 0x17 */
+ b800 0 0 1 &PCI_PIC 4
+ b800 0 0 2 &PCI_PIC 5
+ b800 0 0 3 &PCI_PIC 6
+ b800 0 0 4 &PCI_PIC 7
+
+ /* IDSEL 0x18 */
+ c000 0 0 1 &PCI_PIC 8
+ c000 0 0 2 &PCI_PIC 9
+ c000 0 0 3 &PCI_PIC a
+ c000 0 0 4 &PCI_PIC b>;
+
+ interrupt-parent = <&PIC>;
+ interrupts = <12 8>;
+ ranges = <42000000 0 80000000 80000000 0 20000000
+ 02000000 0 a0000000 a0000000 0 20000000
+ 01000000 0 00000000 f6000000 0 02000000>;
+ };
+
+ soc@f0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,mpc8272", "fsl,pq2-soc";
+ ranges = <00000000 f0000000 00053000>;
+
+ // Temporary -- will go away once kernel uses ranges for get_immrbase().
+ reg = <f0000000 00053000>;
+
+ cpm@119c0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
+ reg = <119c0 30>;
+ ranges;
+
+ muram@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 10000>;
+
+ data@0 {
+ compatible = "fsl,cpm-muram-data";
+ reg = <0 2000 9800 800>;
+ };
+ };
+
+ brg@119f0 {
+ compatible = "fsl,mpc8272-brg",
+ "fsl,cpm2-brg",
+ "fsl,cpm-brg";
+ reg = <119f0 10 115f0 10>;
+ };
+
+ serial@11a00 {
+ device_type = "serial";
+ compatible = "fsl,mpc8272-scc-uart",
+ "fsl,cpm2-scc-uart";
+ reg = <11a00 20 8000 100>;
+ interrupts = <28 8>;
+ interrupt-parent = <&PIC>;
+ fsl,cpm-brg = <1>;
+ fsl,cpm-command = <00800000>;
+ };
+
+ serial@11a60 {
+ device_type = "serial";
+ compatible = "fsl,mpc8272-scc-uart",
+ "fsl,cpm2-scc-uart";
+ reg = <11a60 20 8300 100>;
+ interrupts = <2b 8>;
+ interrupt-parent = <&PIC>;
+ fsl,cpm-brg = <4>;
+ fsl,cpm-command = <0ce00000>;
+ };
+
+ mdio@10d40 {
+ device_type = "mdio";
+ compatible = "fsl,mpc8272ads-mdio-bitbang",
+ "fsl,mpc8272-mdio-bitbang",
+ "fsl,cpm2-mdio-bitbang";
+ reg = <10d40 14>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ fsl,mdio-pin = <12>;
+ fsl,mdc-pin = <13>;
+
+ PHY0: ethernet-phy@0 {
+ interrupt-parent = <&PIC>;
+ interrupts = <17 8>;
+ reg = <0>;
+ device_type = "ethernet-phy";
+ };
+
+ PHY1: ethernet-phy@1 {
+ interrupt-parent = <&PIC>;
+ interrupts = <17 8>;
+ reg = <3>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ ethernet@11300 {
+ device_type = "network";
+ compatible = "fsl,mpc8272-fcc-enet",
+ "fsl,cpm2-fcc-enet";
+ reg = <11300 20 8400 100 11390 1>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <20 8>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&PHY0>;
+ linux,network-index = <0>;
+ fsl,cpm-command = <12000300>;
+ };
+
+ ethernet@11320 {
+ device_type = "network";
+ compatible = "fsl,mpc8272-fcc-enet",
+ "fsl,cpm2-fcc-enet";
+ reg = <11320 20 8500 100 113b0 1>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <21 8>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&PHY1>;
+ linux,network-index = <1>;
+ fsl,cpm-command = <16200300>;
+ };
+ };
+
+ PIC: interrupt-controller@10c00 {
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <10c00 80>;
+ compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
+ };
/* May need to remove if on a part without crypto engine */
- crypto@30000 {
- device_type = "crypto";
- model = "SEC2";
- compatible = "talitos";
- reg = <30000 10000>;
- interrupts = <b 2>;
- interrupt-parent = <&Cpm_pic>;
- num-channels = <4>;
- channel-fifo-len = <18>;
- exec-units-mask = <0000007e>;
+ crypto@30000 {
+ device_type = "crypto";
+ model = "SEC2";
+ compatible = "fsl,mpc8272-talitos-sec2",
+ "fsl,talitos-sec2",
+ "fsl,talitos",
+ "talitos";
+ reg = <30000 10000>;
+ interrupts = <b 8>;
+ interrupt-parent = <&PIC>;
+ num-channels = <4>;
+ channel-fifo-len = <18>;
+ exec-units-mask = <0000007e>;
/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
- descriptor-types-mask = <01010ebf>;
- };
+ descriptor-types-mask = <01010ebf>;
+ };
+ };
- };
+ chosen {
+ linux,stdout-path = "/soc/cpm/serial@11a00";
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index c5adbe40364..9e7eba97326 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -29,7 +29,6 @@
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
- 32-bit;
};
};
@@ -41,7 +40,6 @@
soc8313@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@@ -73,11 +71,11 @@
spi@7000 {
device_type = "spi";
- compatible = "mpc83xx_spi";
+ compatible = "fsl_spi";
reg = <7000 1000>;
interrupts = <10 8>;
interrupt-parent = < &ipic >;
- mode = <0>;
+ mode = "cpu";
};
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
@@ -152,36 +150,6 @@
interrupt-parent = < &ipic >;
};
- pci@8500 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x0E -mini PCI */
- 7000 0 0 1 &ipic 12 8
- 7000 0 0 2 &ipic 12 8
- 7000 0 0 3 &ipic 12 8
- 7000 0 0 4 &ipic 12 8
-
- /* IDSEL 0x0F - PCI slot */
- 7800 0 0 1 &ipic 11 8
- 7800 0 0 2 &ipic 12 8
- 7800 0 0 3 &ipic 11 8
- 7800 0 0 4 &ipic 12 8>;
- interrupt-parent = < &ipic >;
- interrupts = <42 8>;
- bus-range = <0 0>;
- ranges = <02000000 0 90000000 90000000 0 10000000
- 42000000 0 80000000 80000000 0 10000000
- 01000000 0 00000000 e2000000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8500 100>;
- compatible = "fsl,mpc8349-pci";
- device_type = "pci";
- };
-
crypto@30000 {
device_type = "crypto";
model = "SEC2";
@@ -207,8 +175,37 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
- built-in;
device_type = "ipic";
};
};
+
+ pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x0E -mini PCI */
+ 7000 0 0 1 &ipic 12 8
+ 7000 0 0 2 &ipic 12 8
+ 7000 0 0 3 &ipic 12 8
+ 7000 0 0 4 &ipic 12 8
+
+ /* IDSEL 0x0F - PCI slot */
+ 7800 0 0 1 &ipic 11 8
+ 7800 0 0 2 &ipic 12 8
+ 7800 0 0 3 &ipic 11 8
+ 7800 0 0 4 &ipic 12 8>;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 90000000 90000000 0 10000000
+ 42000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index f158ed781ba..fcd333c391e 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -29,7 +29,6 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
- 32-bit;
};
};
@@ -46,7 +45,6 @@
soc8323@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@@ -99,71 +97,11 @@
descriptor-types-mask = <0122003f>;
};
- pci@8500 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x11 AD17 */
- 8800 0 0 1 &ipic 14 8
- 8800 0 0 2 &ipic 15 8
- 8800 0 0 3 &ipic 16 8
- 8800 0 0 4 &ipic 17 8
-
- /* IDSEL 0x12 AD18 */
- 9000 0 0 1 &ipic 16 8
- 9000 0 0 2 &ipic 17 8
- 9000 0 0 3 &ipic 14 8
- 9000 0 0 4 &ipic 15 8
-
- /* IDSEL 0x13 AD19 */
- 9800 0 0 1 &ipic 17 8
- 9800 0 0 2 &ipic 14 8
- 9800 0 0 3 &ipic 15 8
- 9800 0 0 4 &ipic 16 8
-
- /* IDSEL 0x15 AD21*/
- a800 0 0 1 &ipic 14 8
- a800 0 0 2 &ipic 15 8
- a800 0 0 3 &ipic 16 8
- a800 0 0 4 &ipic 17 8
-
- /* IDSEL 0x16 AD22*/
- b000 0 0 1 &ipic 17 8
- b000 0 0 2 &ipic 14 8
- b000 0 0 3 &ipic 15 8
- b000 0 0 4 &ipic 16 8
-
- /* IDSEL 0x17 AD23*/
- b800 0 0 1 &ipic 16 8
- b800 0 0 2 &ipic 17 8
- b800 0 0 3 &ipic 14 8
- b800 0 0 4 &ipic 15 8
-
- /* IDSEL 0x18 AD24*/
- c000 0 0 1 &ipic 15 8
- c000 0 0 2 &ipic 16 8
- c000 0 0 3 &ipic 17 8
- c000 0 0 4 &ipic 14 8>;
- interrupt-parent = < &ipic >;
- interrupts = <42 8>;
- bus-range = <0 0>;
- ranges = <02000000 0 90000000 90000000 0 10000000
- 42000000 0 80000000 80000000 0 10000000
- 01000000 0 00000000 d0000000 0 00100000>;
- clock-frequency = <0>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8500 100>;
- compatible = "fsl,mpc8349-pci";
- device_type = "pci";
- };
-
ipic: pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
- built-in;
device_type = "ipic";
};
@@ -333,10 +271,68 @@
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
- built-in;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = < &ipic >;
};
};
+
+ pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x11 AD17 */
+ 8800 0 0 1 &ipic 14 8
+ 8800 0 0 2 &ipic 15 8
+ 8800 0 0 3 &ipic 16 8
+ 8800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x12 AD18 */
+ 9000 0 0 1 &ipic 16 8
+ 9000 0 0 2 &ipic 17 8
+ 9000 0 0 3 &ipic 14 8
+ 9000 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x13 AD19 */
+ 9800 0 0 1 &ipic 17 8
+ 9800 0 0 2 &ipic 14 8
+ 9800 0 0 3 &ipic 15 8
+ 9800 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x15 AD21*/
+ a800 0 0 1 &ipic 14 8
+ a800 0 0 2 &ipic 15 8
+ a800 0 0 3 &ipic 16 8
+ a800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x16 AD22*/
+ b000 0 0 1 &ipic 17 8
+ b000 0 0 2 &ipic 14 8
+ b000 0 0 3 &ipic 15 8
+ b000 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x17 AD23*/
+ b800 0 0 1 &ipic 16 8
+ b800 0 0 2 &ipic 17 8
+ b800 0 0 3 &ipic 14 8
+ b800 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x18 AD24*/
+ c000 0 0 1 &ipic 15 8
+ c000 0 0 2 &ipic 16 8
+ c000 0 0 3 &ipic 17 8
+ c000 0 0 4 &ipic 14 8>;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 90000000 90000000 0 10000000
+ 42000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 d0000000 0 00100000>;
+ clock-frequency = <0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 7c4beff3e20..388c8a7012e 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -29,7 +29,6 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
- 32-bit;
};
};
@@ -41,7 +40,6 @@
soc8323@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@@ -94,45 +92,11 @@
descriptor-types-mask = <0122003f>;
};
- pci@8500 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x10 AD16 (USB) */
- 8000 0 0 1 &pic 11 8
-
- /* IDSEL 0x11 AD17 (Mini1)*/
- 8800 0 0 1 &pic 12 8
- 8800 0 0 2 &pic 13 8
- 8800 0 0 3 &pic 14 8
- 8800 0 0 4 &pic 30 8
-
- /* IDSEL 0x12 AD18 (PCI/Mini2) */
- 9000 0 0 1 &pic 13 8
- 9000 0 0 2 &pic 14 8
- 9000 0 0 3 &pic 30 8
- 9000 0 0 4 &pic 11 8>;
-
- interrupt-parent = <&pic>;
- interrupts = <42 8>;
- bus-range = <0 0>;
- ranges = <42000000 0 80000000 80000000 0 10000000
- 02000000 0 90000000 90000000 0 10000000
- 01000000 0 d0000000 d0000000 0 04000000>;
- clock-frequency = <0>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8500 100>;
- compatible = "fsl,mpc8349-pci";
- device_type = "pci";
- };
-
pic:pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
- built-in;
device_type = "ipic";
};
@@ -211,7 +175,7 @@
reg = <4c0 40>;
interrupts = <2>;
interrupt-parent = <&qeic>;
- mode = "cpu";
+ mode = "cpu-qe";
};
spi@500 {
@@ -292,10 +256,42 @@
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
- built-in;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = <&pic>;
};
};
+
+ pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x10 AD16 (USB) */
+ 8000 0 0 1 &pic 11 8
+
+ /* IDSEL 0x11 AD17 (Mini1)*/
+ 8800 0 0 1 &pic 12 8
+ 8800 0 0 2 &pic 13 8
+ 8800 0 0 3 &pic 14 8
+ 8800 0 0 4 &pic 30 8
+
+ /* IDSEL 0x12 AD18 (PCI/Mini2) */
+ 9000 0 0 1 &pic 13 8
+ 9000 0 0 2 &pic 14 8
+ 9000 0 0 3 &pic 30 8
+ 9000 0 0 4 &pic 11 8>;
+
+ interrupt-parent = <&pic>;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <42000000 0 80000000 80000000 0 10000000
+ 02000000 0 90000000 90000000 0 10000000
+ 01000000 0 d0000000 d0000000 0 04000000>;
+ clock-frequency = <0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index 44c065a6b5e..5072f6d0a46 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -28,7 +28,6 @@
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
- 32-bit;
};
};
@@ -40,7 +39,6 @@
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@@ -72,11 +70,11 @@
spi@7000 {
device_type = "spi";
- compatible = "mpc83xx_spi";
+ compatible = "fsl_spi";
reg = <7000 1000>;
interrupts = <10 8>;
interrupt-parent = < &ipic >;
- mode = <0>;
+ mode = "cpu";
};
usb@22000 {
@@ -142,6 +140,7 @@
interrupts = <20 8 21 8 22 8>;
interrupt-parent = < &ipic >;
phy-handle = < &phy1c >;
+ linux,network-index = <0>;
};
ethernet@25000 {
@@ -161,6 +160,7 @@
interrupts = <23 8 24 8 25 8>;
interrupt-parent = < &ipic >;
phy-handle = < &phy1f >;
+ linux,network-index = <1>;
};
serial@4500 {
@@ -181,52 +181,6 @@
interrupt-parent = < &ipic >;
};
- pci@8500 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x10 - SATA */
- 8000 0 0 1 &ipic 16 8 /* SATA_INTA */
- >;
- interrupt-parent = < &ipic >;
- interrupts = <42 8>;
- bus-range = <0 0>;
- ranges = <42000000 0 80000000 80000000 0 10000000
- 02000000 0 90000000 90000000 0 10000000
- 01000000 0 00000000 e2000000 0 01000000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8500 100>;
- compatible = "fsl,mpc8349-pci";
- device_type = "pci";
- };
-
- pci@8600 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x0E - MiniPCI Slot */
- 7000 0 0 1 &ipic 15 8 /* PCI_INTA */
-
- /* IDSEL 0x0F - PCI Slot */
- 7800 0 0 1 &ipic 14 8 /* PCI_INTA */
- 7800 0 0 2 &ipic 15 8 /* PCI_INTB */
- >;
- interrupt-parent = < &ipic >;
- interrupts = <43 8>;
- bus-range = <1 1>;
- ranges = <42000000 0 a0000000 a0000000 0 10000000
- 02000000 0 b0000000 b0000000 0 10000000
- 01000000 0 00000000 e3000000 0 01000000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8600 100>;
- compatible = "fsl,mpc8349-pci";
- device_type = "pci";
- };
-
crypto@30000 {
device_type = "crypto";
model = "SEC2";
@@ -245,8 +199,56 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
- built-in;
device_type = "ipic";
};
};
+
+ pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x10 - SATA */
+ 8000 0 0 1 &ipic 16 8 /* SATA_INTA */
+ >;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <42000000 0 80000000 80000000 0 10000000
+ 02000000 0 90000000 90000000 0 10000000
+ 01000000 0 00000000 e2000000 0 01000000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
+
+ pci@e0008600 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0E - MiniPCI Slot */
+ 7000 0 0 1 &ipic 15 8 /* PCI_INTA */
+
+ /* IDSEL 0x0F - PCI Slot */
+ 7800 0 0 1 &ipic 14 8 /* PCI_INTA */
+ 7800 0 0 2 &ipic 15 8 /* PCI_INTB */
+ >;
+ interrupt-parent = < &ipic >;
+ interrupts = <43 8>;
+ bus-range = <0 0>;
+ ranges = <42000000 0 a0000000 a0000000 0 10000000
+ 02000000 0 b0000000 b0000000 0 10000000
+ 01000000 0 00000000 e3000000 0 01000000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008600 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
+
+
+
};
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
index 0b8387141d8..074f7a2ab7e 100644
--- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -28,7 +28,6 @@
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
- 32-bit;
};
};
@@ -40,7 +39,6 @@
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@@ -72,11 +70,11 @@
spi@7000 {
device_type = "spi";
- compatible = "mpc83xx_spi";
+ compatible = "fsl_spi";
reg = <7000 1000>;
interrupts = <10 8>;
interrupt-parent = < &ipic >;
- mode = <0>;
+ mode = "cpu";
};
usb@23000 {
@@ -116,6 +114,7 @@
interrupts = <20 8 21 8 22 8>;
interrupt-parent = < &ipic >;
phy-handle = < &phy1c >;
+ linux,network-index = <0>;
};
serial@4500 {
@@ -136,28 +135,6 @@
interrupt-parent = < &ipic >;
};
- pci@8600 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x0F - PCI Slot */
- 7800 0 0 1 &ipic 14 8 /* PCI_INTA */
- 7800 0 0 2 &ipic 15 8 /* PCI_INTB */
- >;
- interrupt-parent = < &ipic >;
- interrupts = <43 8>;
- bus-range = <1 1>;
- ranges = <42000000 0 a0000000 a0000000 0 10000000
- 02000000 0 b0000000 b0000000 0 10000000
- 01000000 0 00000000 e3000000 0 01000000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8600 100>;
- compatible = "fsl,mpc8349-pci";
- device_type = "pci";
- };
-
crypto@30000 {
device_type = "crypto";
model = "SEC2";
@@ -176,8 +153,29 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
- built-in;
device_type = "ipic";
};
};
+
+ pci@e0008600 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0F - PCI Slot */
+ 7800 0 0 1 &ipic 14 8 /* PCI_INTA */
+ 7800 0 0 2 &ipic 15 8 /* PCI_INTB */
+ >;
+ interrupt-parent = < &ipic >;
+ interrupts = <43 8>;
+ bus-range = <1 1>;
+ ranges = <42000000 0 a0000000 a0000000 0 10000000
+ 02000000 0 b0000000 b0000000 0 10000000
+ 01000000 0 00000000 e3000000 0 01000000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008600 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index 481099756e4..e5a84ef9f4b 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -29,7 +29,6 @@
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
- 32-bit;
};
};
@@ -46,7 +45,6 @@
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@@ -78,11 +76,11 @@
spi@7000 {
device_type = "spi";
- compatible = "mpc83xx_spi";
+ compatible = "fsl_spi";
reg = <7000 1000>;
interrupts = <10 8>;
interrupt-parent = < &ipic >;
- mode = <0>;
+ mode = "cpu";
};
/* phy type (ULPI or SERIAL) are only types supportted for MPH */
@@ -146,6 +144,7 @@
interrupts = <20 8 21 8 22 8>;
interrupt-parent = < &ipic >;
phy-handle = < &phy0 >;
+ linux,network-index = <0>;
};
ethernet@25000 {
@@ -165,6 +164,7 @@
interrupts = <23 8 24 8 25 8>;
interrupt-parent = < &ipic >;
phy-handle = < &phy1 >;
+ linux,network-index = <1>;
};
serial@4500 {
@@ -185,126 +185,6 @@
interrupt-parent = < &ipic >;
};
- pci@8500 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x11 */
- 8800 0 0 1 &ipic 14 8
- 8800 0 0 2 &ipic 15 8
- 8800 0 0 3 &ipic 16 8
- 8800 0 0 4 &ipic 17 8
-
- /* IDSEL 0x12 */
- 9000 0 0 1 &ipic 16 8
- 9000 0 0 2 &ipic 17 8
- 9000 0 0 3 &ipic 14 8
- 9000 0 0 4 &ipic 15 8
-
- /* IDSEL 0x13 */
- 9800 0 0 1 &ipic 17 8
- 9800 0 0 2 &ipic 14 8
- 9800 0 0 3 &ipic 15 8
- 9800 0 0 4 &ipic 16 8
-
- /* IDSEL 0x15 */
- a800 0 0 1 &ipic 14 8
- a800 0 0 2 &ipic 15 8
- a800 0 0 3 &ipic 16 8
- a800 0 0 4 &ipic 17 8
-
- /* IDSEL 0x16 */
- b000 0 0 1 &ipic 17 8
- b000 0 0 2 &ipic 14 8
- b000 0 0 3 &ipic 15 8
- b000 0 0 4 &ipic 16 8
-
- /* IDSEL 0x17 */
- b800 0 0 1 &ipic 16 8
- b800 0 0 2 &ipic 17 8
- b800 0 0 3 &ipic 14 8
- b800 0 0 4 &ipic 15 8
-
- /* IDSEL 0x18 */
- c000 0 0 1 &ipic 15 8
- c000 0 0 2 &ipic 16 8
- c000 0 0 3 &ipic 17 8
- c000 0 0 4 &ipic 14 8>;
- interrupt-parent = < &ipic >;
- interrupts = <42 8>;
- bus-range = <0 0>;
- ranges = <02000000 0 90000000 90000000 0 10000000
- 42000000 0 80000000 80000000 0 10000000
- 01000000 0 00000000 e2000000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8500 100>;
- compatible = "fsl,mpc8349-pci";
- device_type = "pci";
- };
-
- pci@8600 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x11 */
- 8800 0 0 1 &ipic 14 8
- 8800 0 0 2 &ipic 15 8
- 8800 0 0 3 &ipic 16 8
- 8800 0 0 4 &ipic 17 8
-
- /* IDSEL 0x12 */
- 9000 0 0 1 &ipic 16 8
- 9000 0 0 2 &ipic 17 8
- 9000 0 0 3 &ipic 14 8
- 9000 0 0 4 &ipic 15 8
-
- /* IDSEL 0x13 */
- 9800 0 0 1 &ipic 17 8
- 9800 0 0 2 &ipic 14 8
- 9800 0 0 3 &ipic 15 8
- 9800 0 0 4 &ipic 16 8
-
- /* IDSEL 0x15 */
- a800 0 0 1 &ipic 14 8
- a800 0 0 2 &ipic 15 8
- a800 0 0 3 &ipic 16 8
- a800 0 0 4 &ipic 17 8
-
- /* IDSEL 0x16 */
- b000 0 0 1 &ipic 17 8
- b000 0 0 2 &ipic 14 8
- b000 0 0 3 &ipic 15 8
- b000 0 0 4 &ipic 16 8
-
- /* IDSEL 0x17 */
- b800 0 0 1 &ipic 16 8
- b800 0 0 2 &ipic 17 8
- b800 0 0 3 &ipic 14 8
- b800 0 0 4 &ipic 15 8
-
- /* IDSEL 0x18 */
- c000 0 0 1 &ipic 15 8
- c000 0 0 2 &ipic 16 8
- c000 0 0 3 &ipic 17 8
- c000 0 0 4 &ipic 14 8>;
- interrupt-parent = < &ipic >;
- interrupts = <42 8>;
- bus-range = <0 0>;
- ranges = <02000000 0 b0000000 b0000000 0 10000000
- 42000000 0 a0000000 a0000000 0 10000000
- 01000000 0 00000000 e2100000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8600 100>;
- compatible = "fsl,mpc8349-pci";
- device_type = "pci";
- };
-
/* May need to remove if on a part without crypto engine */
crypto@30000 {
device_type = "crypto";
@@ -332,8 +212,127 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
- built-in;
device_type = "ipic";
};
};
+
+ pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x11 */
+ 8800 0 0 1 &ipic 14 8
+ 8800 0 0 2 &ipic 15 8
+ 8800 0 0 3 &ipic 16 8
+ 8800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x12 */
+ 9000 0 0 1 &ipic 16 8
+ 9000 0 0 2 &ipic 17 8
+ 9000 0 0 3 &ipic 14 8
+ 9000 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x13 */
+ 9800 0 0 1 &ipic 17 8
+ 9800 0 0 2 &ipic 14 8
+ 9800 0 0 3 &ipic 15 8
+ 9800 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &ipic 14 8
+ a800 0 0 2 &ipic 15 8
+ a800 0 0 3 &ipic 16 8
+ a800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x16 */
+ b000 0 0 1 &ipic 17 8
+ b000 0 0 2 &ipic 14 8
+ b000 0 0 3 &ipic 15 8
+ b000 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x17 */
+ b800 0 0 1 &ipic 16 8
+ b800 0 0 2 &ipic 17 8
+ b800 0 0 3 &ipic 14 8
+ b800 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x18 */
+ c000 0 0 1 &ipic 15 8
+ c000 0 0 2 &ipic 16 8
+ c000 0 0 3 &ipic 17 8
+ c000 0 0 4 &ipic 14 8>;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 90000000 90000000 0 10000000
+ 42000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
+
+ pci@e0008600 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x11 */
+ 8800 0 0 1 &ipic 14 8
+ 8800 0 0 2 &ipic 15 8
+ 8800 0 0 3 &ipic 16 8
+ 8800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x12 */
+ 9000 0 0 1 &ipic 16 8
+ 9000 0 0 2 &ipic 17 8
+ 9000 0 0 3 &ipic 14 8
+ 9000 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x13 */
+ 9800 0 0 1 &ipic 17 8
+ 9800 0 0 2 &ipic 14 8
+ 9800 0 0 3 &ipic 15 8
+ 9800 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &ipic 14 8
+ a800 0 0 2 &ipic 15 8
+ a800 0 0 3 &ipic 16 8
+ a800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x16 */
+ b000 0 0 1 &ipic 17 8
+ b000 0 0 2 &ipic 14 8
+ b000 0 0 3 &ipic 15 8
+ b000 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x17 */
+ b800 0 0 1 &ipic 16 8
+ b800 0 0 2 &ipic 17 8
+ b800 0 0 3 &ipic 14 8
+ b800 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x18 */
+ c000 0 0 1 &ipic 15 8
+ c000 0 0 2 &ipic 16 8
+ c000 0 0 3 &ipic 17 8
+ c000 0 0 4 &ipic 14 8>;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 b0000000 b0000000 0 10000000
+ 42000000 0 a0000000 a0000000 0 10000000
+ 01000000 0 00000000 e2100000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008600 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index e3f7c128206..fbd1573c348 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -34,7 +34,6 @@
timebase-frequency = <3EF1480>;
bus-frequency = <FBC5200>;
clock-frequency = <1F78A400>;
- 32-bit;
};
};
@@ -51,7 +50,6 @@
soc8360@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@@ -113,72 +111,11 @@
descriptor-types-mask = <01010ebf>;
};
- pci@8500 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x11 AD17 */
- 8800 0 0 1 &ipic 14 8
- 8800 0 0 2 &ipic 15 8
- 8800 0 0 3 &ipic 16 8
- 8800 0 0 4 &ipic 17 8
-
- /* IDSEL 0x12 AD18 */
- 9000 0 0 1 &ipic 16 8
- 9000 0 0 2 &ipic 17 8
- 9000 0 0 3 &ipic 14 8
- 9000 0 0 4 &ipic 15 8
-
- /* IDSEL 0x13 AD19 */
- 9800 0 0 1 &ipic 17 8
- 9800 0 0 2 &ipic 14 8
- 9800 0 0 3 &ipic 15 8
- 9800 0 0 4 &ipic 16 8
-
- /* IDSEL 0x15 AD21*/
- a800 0 0 1 &ipic 14 8
- a800 0 0 2 &ipic 15 8
- a800 0 0 3 &ipic 16 8
- a800 0 0 4 &ipic 17 8
-
- /* IDSEL 0x16 AD22*/
- b000 0 0 1 &ipic 17 8
- b000 0 0 2 &ipic 14 8
- b000 0 0 3 &ipic 15 8
- b000 0 0 4 &ipic 16 8
-
- /* IDSEL 0x17 AD23*/
- b800 0 0 1 &ipic 16 8
- b800 0 0 2 &ipic 17 8
- b800 0 0 3 &ipic 14 8
- b800 0 0 4 &ipic 15 8
-
- /* IDSEL 0x18 AD24*/
- c000 0 0 1 &ipic 15 8
- c000 0 0 2 &ipic 16 8
- c000 0 0 3 &ipic 17 8
- c000 0 0 4 &ipic 14 8>;
- interrupt-parent = < &ipic >;
- interrupts = <42 8>;
- bus-range = <0 0>;
- ranges = <02000000 0 a0000000 a0000000 0 10000000
- 42000000 0 80000000 80000000 0 10000000
- 01000000 0 00000000 e2000000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8500 100>;
- compatible = "fsl,mpc8349-pci";
- device_type = "pci";
- };
-
ipic: pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
- built-in;
device_type = "ipic";
};
@@ -364,11 +301,69 @@
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
- built-in;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = < &ipic >;
};
+ };
+ pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x11 AD17 */
+ 8800 0 0 1 &ipic 14 8
+ 8800 0 0 2 &ipic 15 8
+ 8800 0 0 3 &ipic 16 8
+ 8800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x12 AD18 */
+ 9000 0 0 1 &ipic 16 8
+ 9000 0 0 2 &ipic 17 8
+ 9000 0 0 3 &ipic 14 8
+ 9000 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x13 AD19 */
+ 9800 0 0 1 &ipic 17 8
+ 9800 0 0 2 &ipic 14 8
+ 9800 0 0 3 &ipic 15 8
+ 9800 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x15 AD21*/
+ a800 0 0 1 &ipic 14 8
+ a800 0 0 2 &ipic 15 8
+ a800 0 0 3 &ipic 16 8
+ a800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x16 AD22*/
+ b000 0 0 1 &ipic 17 8
+ b000 0 0 2 &ipic 14 8
+ b000 0 0 3 &ipic 15 8
+ b000 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x17 AD23*/
+ b800 0 0 1 &ipic 16 8
+ b800 0 0 2 &ipic 17 8
+ b800 0 0 3 &ipic 14 8
+ b800 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x18 AD24*/
+ c000 0 0 1 &ipic 15 8
+ c000 0 0 2 &ipic 16 8
+ c000 0 0 3 &ipic 17 8
+ c000 0 0 4 &ipic 14 8>;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 a0000000 a0000000 0 10000000
+ 42000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
};
};
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index fc8dff9f620..6442a717ec3 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -30,7 +30,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
- 32-bit;
};
};
@@ -42,7 +41,6 @@
soc8540@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>; // CCSRBAR 1M
@@ -173,105 +171,104 @@
interrupts = <2a 2>;
interrupt-parent = <&mpic>;
};
- pci@8000 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
+ mpic: pic@40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <40000 40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ big-endian;
+ };
+ };
- /* IDSEL 0x02 */
- 1000 0 0 1 &mpic 1 1
- 1000 0 0 2 &mpic 2 1
- 1000 0 0 3 &mpic 3 1
- 1000 0 0 4 &mpic 4 1
+ pci@e0008000 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
- /* IDSEL 0x03 */
- 1800 0 0 1 &mpic 4 1
- 1800 0 0 2 &mpic 1 1
- 1800 0 0 3 &mpic 2 1
- 1800 0 0 4 &mpic 3 1
+ /* IDSEL 0x02 */
+ 1000 0 0 1 &mpic 1 1
+ 1000 0 0 2 &mpic 2 1
+ 1000 0 0 3 &mpic 3 1
+ 1000 0 0 4 &mpic 4 1
- /* IDSEL 0x04 */
- 2000 0 0 1 &mpic 3 1
- 2000 0 0 2 &mpic 4 1
- 2000 0 0 3 &mpic 1 1
- 2000 0 0 4 &mpic 2 1
+ /* IDSEL 0x03 */
+ 1800 0 0 1 &mpic 4 1
+ 1800 0 0 2 &mpic 1 1
+ 1800 0 0 3 &mpic 2 1
+ 1800 0 0 4 &mpic 3 1
- /* IDSEL 0x05 */
- 2800 0 0 1 &mpic 2 1
- 2800 0 0 2 &mpic 3 1
- 2800 0 0 3 &mpic 4 1
- 2800 0 0 4 &mpic 1 1
+ /* IDSEL 0x04 */
+ 2000 0 0 1 &mpic 3 1
+ 2000 0 0 2 &mpic 4 1
+ 2000 0 0 3 &mpic 1 1
+ 2000 0 0 4 &mpic 2 1
- /* IDSEL 0x0c */
- 6000 0 0 1 &mpic 1 1
- 6000 0 0 2 &mpic 2 1
- 6000 0 0 3 &mpic 3 1
- 6000 0 0 4 &mpic 4 1
+ /* IDSEL 0x05 */
+ 2800 0 0 1 &mpic 2 1
+ 2800 0 0 2 &mpic 3 1
+ 2800 0 0 3 &mpic 4 1
+ 2800 0 0 4 &mpic 1 1
- /* IDSEL 0x0d */
- 6800 0 0 1 &mpic 4 1
- 6800 0 0 2 &mpic 1 1
- 6800 0 0 3 &mpic 2 1
- 6800 0 0 4 &mpic 3 1
+ /* IDSEL 0x0c */
+ 6000 0 0 1 &mpic 1 1
+ 6000 0 0 2 &mpic 2 1
+ 6000 0 0 3 &mpic 3 1
+ 6000 0 0 4 &mpic 4 1
- /* IDSEL 0x0e */
- 7000 0 0 1 &mpic 3 1
- 7000 0 0 2 &mpic 4 1
- 7000 0 0 3 &mpic 1 1
- 7000 0 0 4 &mpic 2 1
+ /* IDSEL 0x0d */
+ 6800 0 0 1 &mpic 4 1
+ 6800 0 0 2 &mpic 1 1
+ 6800 0 0 3 &mpic 2 1
+ 6800 0 0 4 &mpic 3 1
- /* IDSEL 0x0f */
- 7800 0 0 1 &mpic 2 1
- 7800 0 0 2 &mpic 3 1
- 7800 0 0 3 &mpic 4 1
- 7800 0 0 4 &mpic 1 1
+ /* IDSEL 0x0e */
+ 7000 0 0 1 &mpic 3 1
+ 7000 0 0 2 &mpic 4 1
+ 7000 0 0 3 &mpic 1 1
+ 7000 0 0 4 &mpic 2 1
- /* IDSEL 0x12 */
- 9000 0 0 1 &mpic 1 1
- 9000 0 0 2 &mpic 2 1
- 9000 0 0 3 &mpic 3 1
- 9000 0 0 4 &mpic 4 1
+ /* IDSEL 0x0f */
+ 7800 0 0 1 &mpic 2 1
+ 7800 0 0 2 &mpic 3 1
+ 7800 0 0 3 &mpic 4 1
+ 7800 0 0 4 &mpic 1 1
- /* IDSEL 0x13 */
- 9800 0 0 1 &mpic 4 1
- 9800 0 0 2 &mpic 1 1
- 9800 0 0 3 &mpic 2 1
- 9800 0 0 4 &mpic 3 1
+ /* IDSEL 0x12 */
+ 9000 0 0 1 &mpic 1 1
+ 9000 0 0 2 &mpic 2 1
+ 9000 0 0 3 &mpic 3 1
+ 9000 0 0 4 &mpic 4 1
- /* IDSEL 0x14 */
- a000 0 0 1 &mpic 3 1
- a000 0 0 2 &mpic 4 1
- a000 0 0 3 &mpic 1 1
- a000 0 0 4 &mpic 2 1
+ /* IDSEL 0x13 */
+ 9800 0 0 1 &mpic 4 1
+ 9800 0 0 2 &mpic 1 1
+ 9800 0 0 3 &mpic 2 1
+ 9800 0 0 4 &mpic 3 1
- /* IDSEL 0x15 */
- a800 0 0 1 &mpic 2 1
- a800 0 0 2 &mpic 3 1
- a800 0 0 3 &mpic 4 1
- a800 0 0 4 &mpic 1 1>;
- interrupt-parent = <&mpic>;
- interrupts = <18 2>;
- bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e2000000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8000 1000>;
- compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
- device_type = "pci";
- };
+ /* IDSEL 0x14 */
+ a000 0 0 1 &mpic 3 1
+ a000 0 0 2 &mpic 4 1
+ a000 0 0 3 &mpic 1 1
+ a000 0 0 4 &mpic 2 1
- mpic: pic@40000 {
- clock-frequency = <0>;
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <40000 40000>;
- built-in;
- compatible = "chrp,open-pic";
- device_type = "open-pic";
- big-endian;
- };
+ /* IDSEL 0x15 */
+ a800 0 0 1 &mpic 2 1
+ a800 0 0 2 &mpic 3 1
+ a800 0 0 3 &mpic 4 1
+ a800 0 0 4 &mpic 1 1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008000 1000>;
+ compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
+ device_type = "pci";
};
};
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index fb0b647f8c2..f3f4d79deb6 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -30,7 +30,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
- 32-bit;
};
};
@@ -42,10 +41,9 @@
soc8541@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
- reg = <e0000000 00100000>; // CCSRBAR 1M
+ reg = <e0000000 00001000>; // CCSRBAR 1M
bus-frequency = <0>;
memory-controller@2000 {
@@ -137,113 +135,145 @@
interrupt-parent = <&mpic>;
};
- pci1: pci@8000 {
- interrupt-map-mask = <1f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x10 */
- 08000 0 0 1 &mpic 0 1
- 08000 0 0 2 &mpic 1 1
- 08000 0 0 3 &mpic 2 1
- 08000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x11 */
- 08800 0 0 1 &mpic 0 1
- 08800 0 0 2 &mpic 1 1
- 08800 0 0 3 &mpic 2 1
- 08800 0 0 4 &mpic 3 1
-
- /* IDSEL 0x12 (Slot 1) */
- 09000 0 0 1 &mpic 0 1
- 09000 0 0 2 &mpic 1 1
- 09000 0 0 3 &mpic 2 1
- 09000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x13 (Slot 2) */
- 09800 0 0 1 &mpic 1 1
- 09800 0 0 2 &mpic 2 1
- 09800 0 0 3 &mpic 3 1
- 09800 0 0 4 &mpic 0 1
-
- /* IDSEL 0x14 (Slot 3) */
- 0a000 0 0 1 &mpic 2 1
- 0a000 0 0 2 &mpic 3 1
- 0a000 0 0 3 &mpic 0 1
- 0a000 0 0 4 &mpic 1 1
-
- /* IDSEL 0x15 (Slot 4) */
- 0a800 0 0 1 &mpic 3 1
- 0a800 0 0 2 &mpic 0 1
- 0a800 0 0 3 &mpic 1 1
- 0a800 0 0 4 &mpic 2 1
-
- /* Bus 1 (Tundra Bridge) */
- /* IDSEL 0x12 (ISA bridge) */
- 19000 0 0 1 &mpic 0 1
- 19000 0 0 2 &mpic 1 1
- 19000 0 0 3 &mpic 2 1
- 19000 0 0 4 &mpic 3 1>;
- interrupt-parent = <&mpic>;
- interrupts = <18 2>;
- bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e2000000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8000 1000>;
- compatible = "fsl,mpc8540-pci";
- device_type = "pci";
-
- i8259@19000 {
- clock-frequency = <0>;
+ mpic: pic@40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <40000 40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ big-endian;
+ };
+
+ cpm@919c0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
+ reg = <919c0 30>;
+ ranges;
+
+ muram@80000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 80000 10000>;
+
+ data@0 {
+ compatible = "fsl,cpm-muram-data";
+ reg = <0 2000 9000 1000>;
+ };
+ };
+
+ brg@919f0 {
+ compatible = "fsl,mpc8541-brg",
+ "fsl,cpm2-brg",
+ "fsl,cpm-brg";
+ reg = <919f0 10 915f0 10>;
+ };
+
+ cpmpic: pic@90c00 {
interrupt-controller;
- device_type = "interrupt-controller";
- reg = <19000 0 0 0 1>;
#address-cells = <0>;
#interrupt-cells = <2>;
- built-in;
- compatible = "chrp,iic";
- big-endian;
- interrupts = <1>;
- interrupt-parent = <&pci1>;
+ interrupts = <2e 2>;
+ interrupt-parent = <&mpic>;
+ reg = <90c00 80>;
+ compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
};
};
+ };
- pci@9000 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
+ pci1: pci@e0008000 {
+ interrupt-map-mask = <1f800 0 0 7>;
+ interrupt-map = <
- /* IDSEL 0x15 */
- a800 0 0 1 &mpic b 1
- a800 0 0 2 &mpic b 1
- a800 0 0 3 &mpic b 1
- a800 0 0 4 &mpic b 1>;
- interrupt-parent = <&mpic>;
- interrupts = <19 2>;
- bus-range = <0 0>;
- ranges = <02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 e3000000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <9000 1000>;
- compatible = "fsl,mpc8540-pci";
- device_type = "pci";
- };
+ /* IDSEL 0x10 */
+ 08000 0 0 1 &mpic 0 1
+ 08000 0 0 2 &mpic 1 1
+ 08000 0 0 3 &mpic 2 1
+ 08000 0 0 4 &mpic 3 1
- mpic: pic@40000 {
- clock-frequency = <0>;
+ /* IDSEL 0x11 */
+ 08800 0 0 1 &mpic 0 1
+ 08800 0 0 2 &mpic 1 1
+ 08800 0 0 3 &mpic 2 1
+ 08800 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x12 (Slot 1) */
+ 09000 0 0 1 &mpic 0 1
+ 09000 0 0 2 &mpic 1 1
+ 09000 0 0 3 &mpic 2 1
+ 09000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x13 (Slot 2) */
+ 09800 0 0 1 &mpic 1 1
+ 09800 0 0 2 &mpic 2 1
+ 09800 0 0 3 &mpic 3 1
+ 09800 0 0 4 &mpic 0 1
+
+ /* IDSEL 0x14 (Slot 3) */
+ 0a000 0 0 1 &mpic 2 1
+ 0a000 0 0 2 &mpic 3 1
+ 0a000 0 0 3 &mpic 0 1
+ 0a000 0 0 4 &mpic 1 1
+
+ /* IDSEL 0x15 (Slot 4) */
+ 0a800 0 0 1 &mpic 3 1
+ 0a800 0 0 2 &mpic 0 1
+ 0a800 0 0 3 &mpic 1 1
+ 0a800 0 0 4 &mpic 2 1
+
+ /* Bus 1 (Tundra Bridge) */
+ /* IDSEL 0x12 (ISA bridge) */
+ 19000 0 0 1 &mpic 0 1
+ 19000 0 0 2 &mpic 1 1
+ 19000 0 0 3 &mpic 2 1
+ 19000 0 0 4 &mpic 3 1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008000 1000>;
+ compatible = "fsl,mpc8540-pci";
+ device_type = "pci";
+
+ i8259@19000 {
interrupt-controller;
+ device_type = "interrupt-controller";
+ reg = <19000 0 0 0 1>;
#address-cells = <0>;
#interrupt-cells = <2>;
- reg = <40000 40000>;
- built-in;
- compatible = "chrp,open-pic";
- device_type = "open-pic";
- big-endian;
+ compatible = "chrp,iic";
+ interrupts = <1>;
+ interrupt-parent = <&pci1>;
};
};
+
+ pci@e0009000 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &mpic b 1
+ a800 0 0 2 &mpic b 1
+ a800 0 0 3 &mpic b 1
+ a800 0 0 4 &mpic b 1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <19 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 a0000000 a0000000 0 20000000
+ 01000000 0 00000000 e3000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0009000 1000>;
+ compatible = "fsl,mpc8540-pci";
+ device_type = "pci";
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 3e79bf0a315..3f9d15cf13e 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -30,7 +30,6 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
- 32-bit;
};
};
@@ -42,19 +41,9 @@
soc8544@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
-
- ranges = <00001000 e0001000 000ff000
- 80000000 80000000 20000000
- a0000000 a0000000 10000000
- b0000000 b0000000 00100000
- c0000000 c0000000 20000000
- b0100000 b0100000 00100000
- e1000000 e1000000 00010000
- e1010000 e1010000 00010000
- e1020000 e1020000 00010000>;
+ ranges = <00000000 e0000000 00100000>;
reg = <e0000000 00001000>; // CCSRBAR 1M
bus-frequency = <0>; // Filled out by uboot.
@@ -149,115 +138,173 @@
interrupt-parent = <&mpic>;
};
- pci@8000 {
- compatible = "fsl,mpc8540-pci";
- device_type = "pci";
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x11 J17 Slot 1 */
- 8800 0 0 1 &mpic 2 1
- 8800 0 0 2 &mpic 3 1
- 8800 0 0 3 &mpic 4 1
- 8800 0 0 4 &mpic 1 1
+ global-utilities@e0000 { //global utilities block
+ compatible = "fsl,mpc8548-guts";
+ reg = <e0000 1000>;
+ fsl,has-rstcr;
+ };
- /* IDSEL 0x12 J16 Slot 2 */
+ mpic: pic@40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <40000 40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ big-endian;
+ };
+ };
- 9000 0 0 1 &mpic 3 1
- 9000 0 0 2 &mpic 4 1
- 9000 0 0 3 &mpic 2 1
- 9000 0 0 4 &mpic 1 1>;
+ pci@e0008000 {
+ compatible = "fsl,mpc8540-pci";
+ device_type = "pci";
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x11 J17 Slot 1 */
+ 8800 0 0 1 &mpic 2 1
+ 8800 0 0 2 &mpic 3 1
+ 8800 0 0 3 &mpic 4 1
+ 8800 0 0 4 &mpic 1 1
+
+ /* IDSEL 0x12 J16 Slot 2 */
+
+ 9000 0 0 1 &mpic 3 1
+ 9000 0 0 2 &mpic 4 1
+ 9000 0 0 3 &mpic 2 1
+ 9000 0 0 4 &mpic 1 1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 c0000000 c0000000 0 20000000
+ 01000000 0 00000000 e1000000 0 00010000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008000 1000>;
+ };
- interrupt-parent = <&mpic>;
- interrupts = <18 2>;
- bus-range = <0 ff>;
- ranges = <02000000 0 c0000000 c0000000 0 20000000
- 01000000 0 00000000 e1000000 0 00010000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
+ pcie@e0009000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0009000 1000>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 e1010000 0 00010000>;
+ clock-frequency = <1fca055>;
+ interrupt-parent = <&mpic>;
+ interrupts = <1a 2>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 4 1
+ 0000 0 0 2 &mpic 5 1
+ 0000 0 0 3 &mpic 6 1
+ 0000 0 0 4 &mpic 7 1
+ >;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <8000 1000>;
- };
-
- pcie@9000 {
- compatible = "fsl,mpc8548-pcie";
device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <9000 1000>;
- bus-range = <0 ff>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e1010000 0 00010000>;
- clock-frequency = <1fca055>;
- interrupt-parent = <&mpic>;
- interrupts = <1a 2>;
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x0 */
- 0000 0 0 1 &mpic 4 1
- 0000 0 0 2 &mpic 5 1
- 0000 0 0 3 &mpic 6 1
- 0000 0 0 4 &mpic 7 1
- >;
+ ranges = <02000000 0 80000000
+ 02000000 0 80000000
+ 0 20000000
+
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00010000>;
};
+ };
- pcie@a000 {
- compatible = "fsl,mpc8548-pcie";
- device_type = "pci";
- #interrupt-cells = <1>;
+ pcie@e000a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e000a000 1000>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 a0000000 a0000000 0 10000000
+ 01000000 0 00000000 e1020000 0 00010000>;
+ clock-frequency = <1fca055>;
+ interrupt-parent = <&mpic>;
+ interrupts = <19 2>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 0 1
+ 0000 0 0 2 &mpic 1 1
+ 0000 0 0 3 &mpic 2 1
+ 0000 0 0 4 &mpic 3 1
+ >;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <a000 1000>;
- bus-range = <0 ff>;
- ranges = <02000000 0 a0000000 a0000000 0 10000000
- 01000000 0 00000000 e1020000 0 00010000>;
- clock-frequency = <1fca055>;
- interrupt-parent = <&mpic>;
- interrupts = <19 2>;
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x0 */
- 0000 0 0 1 &mpic 0 1
- 0000 0 0 2 &mpic 1 1
- 0000 0 0 3 &mpic 2 1
- 0000 0 0 4 &mpic 3 1
- >;
+ device_type = "pci";
+ ranges = <02000000 0 a0000000
+ 02000000 0 a0000000
+ 0 10000000
+
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00010000>;
};
+ };
- pcie@b000 {
- compatible = "fsl,mpc8548-pcie";
- device_type = "pci";
- #interrupt-cells = <1>;
+ pcie@e000b000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e000b000 1000>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 b0000000 b0000000 0 00100000
+ 01000000 0 00000000 b0100000 0 00100000>;
+ clock-frequency = <1fca055>;
+ interrupt-parent = <&mpic>;
+ interrupts = <1b 2>;
+ interrupt-map-mask = <fb00 0 0 0>;
+ interrupt-map = <
+ // IDSEL 0x1c USB
+ e000 0 0 0 &i8259 c 2
+ e100 0 0 0 &i8259 9 2
+ e200 0 0 0 &i8259 a 2
+ e300 0 0 0 &i8259 b 2
+
+ // IDSEL 0x1d Audio
+ e800 0 0 0 &i8259 6 2
+
+ // IDSEL 0x1e Legacy
+ f000 0 0 0 &i8259 7 2
+ f100 0 0 0 &i8259 7 2
+
+ // IDSEL 0x1f IDE/SATA
+ f800 0 0 0 &i8259 e 2
+ f900 0 0 0 &i8259 5 2
+ >;
+
+ pcie@0 {
+ reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <b000 1000>;
- bus-range = <0 ff>;
- ranges = <02000000 0 b0000000 b0000000 0 00100000
- 01000000 0 00000000 b0100000 0 00100000>;
- clock-frequency = <1fca055>;
- interrupt-parent = <&mpic>;
- interrupts = <1b 2>;
- interrupt-map-mask = <fb00 0 0 0>;
- interrupt-map = <
- // IDSEL 0x1c USB
- e000 0 0 0 &i8259 c 2
- e100 0 0 0 &i8259 9 2
- e200 0 0 0 &i8259 a 2
- e300 0 0 0 &i8259 b 2
-
- // IDSEL 0x1d Audio
- e800 0 0 0 &i8259 6 2
-
- // IDSEL 0x1e Legacy
- f000 0 0 0 &i8259 7 2
- f100 0 0 0 &i8259 7 2
-
- // IDSEL 0x1f IDE/SATA
- f800 0 0 0 &i8259 e 2
- f900 0 0 0 &i8259 5 2
- >;
+ device_type = "pci";
+ ranges = <02000000 0 b0000000
+ 02000000 0 b0000000
+ 0 00100000
+
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00100000>;
+
uli1575@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
@@ -265,95 +312,63 @@
ranges = <02000000 0 b0000000
02000000 0 b0000000
0 00100000
+
01000000 0 00000000
01000000 0 00000000
0 00100000>;
-
- pci_bridge@0 {
- reg = <0 0 0 0 0>;
- #size-cells = <2>;
- #address-cells = <3>;
- ranges = <02000000 0 b0000000
- 02000000 0 b0000000
- 0 00100000
- 01000000 0 00000000
- 01000000 0 00000000
- 0 00100000>;
-
- isa@1e {
- device_type = "isa";
+ isa@1e {
+ device_type = "isa";
+ #interrupt-cells = <2>;
+ #size-cells = <1>;
+ #address-cells = <2>;
+ reg = <f000 0 0 0 0>;
+ ranges = <1 0
+ 01000000 0 0
+ 00001000>;
+ interrupt-parent = <&i8259>;
+
+ i8259: interrupt-controller@20 {
+ reg = <1 20 2
+ 1 a0 2
+ 1 4d0 2>;
+ interrupt-controller;
+ device_type = "interrupt-controller";
+ #address-cells = <0>;
#interrupt-cells = <2>;
- #size-cells = <1>;
- #address-cells = <2>;
- reg = <f000 0 0 0 0>;
- ranges = <1 0
- 01000000 0 0
- 00001000>;
+ compatible = "chrp,iic";
+ interrupts = <9 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ i8042@60 {
+ #size-cells = <0>;
+ #address-cells = <1>;
+ reg = <1 60 1 1 64 1>;
+ interrupts = <1 3 c 3>;
interrupt-parent = <&i8259>;
- i8259: interrupt-controller@20 {
- reg = <1 20 2
- 1 a0 2
- 1 4d0 2>;
- clock-frequency = <0>;
- interrupt-controller;
- device_type = "interrupt-controller";
- #address-cells = <0>;
- #interrupt-cells = <2>;
- built-in;
- compatible = "chrp,iic";
- interrupts = <9 2>;
- interrupt-parent = <&mpic>;
+ keyboard@0 {
+ reg = <0>;
+ compatible = "pnpPNP,303";
};
- i8042@60 {
- #size-cells = <0>;
- #address-cells = <1>;
- reg = <1 60 1 1 64 1>;
- interrupts = <1 3 c 3>;
- interrupt-parent = <&i8259>;
-
- keyboard@0 {
- reg = <0>;
- compatible = "pnpPNP,303";
- };
-
- mouse@1 {
- reg = <1>;
- compatible = "pnpPNP,f03";
- };
+ mouse@1 {
+ reg = <1>;
+ compatible = "pnpPNP,f03";
};
+ };
- rtc@70 {
- compatible = "pnpPNP,b00";
- reg = <1 70 2>;
- };
+ rtc@70 {
+ compatible = "pnpPNP,b00";
+ reg = <1 70 2>;
+ };
- gpio@400 {
- reg = <1 400 80>;
- };
+ gpio@400 {
+ reg = <1 400 80>;
};
};
};
-
};
- global-utilities@e0000 { //global utilities block
- compatible = "fsl,mpc8548-guts";
- reg = <e0000 1000>;
- fsl,has-rstcr;
- };
-
- mpic: pic@40000 {
- clock-frequency = <0>;
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <40000 40000>;
- built-in;
- compatible = "chrp,open-pic";
- device_type = "open-pic";
- big-endian;
- };
};
};
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index d215d21fff4..69ca5025d97 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -30,7 +30,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
- 32-bit;
};
};
@@ -42,15 +41,8 @@
soc8548@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
- ranges = <00001000 e0001000 000ff000
- 80000000 80000000 10000000
- e2000000 e2000000 00800000
- 90000000 90000000 10000000
- e2800000 e2800000 00800000
- a0000000 a0000000 20000000
- e3000000 e3000000 01000000>;
+ ranges = <00000000 e0000000 00100000>;
reg = <e0000000 00001000>; // CCSRBAR
bus-frequency = <0>;
@@ -189,215 +181,225 @@
fsl,has-rstcr;
};
- pci@8000 {
+ mpic: pic@40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <40000 40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ big-endian;
+ };
+ };
+
+ pci@e0008000 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x4 (PCIX Slot 2) */
+ 02000 0 0 1 &mpic 0 1
+ 02000 0 0 2 &mpic 1 1
+ 02000 0 0 3 &mpic 2 1
+ 02000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x5 (PCIX Slot 3) */
+ 02800 0 0 1 &mpic 1 1
+ 02800 0 0 2 &mpic 2 1
+ 02800 0 0 3 &mpic 3 1
+ 02800 0 0 4 &mpic 0 1
+
+ /* IDSEL 0x6 (PCIX Slot 4) */
+ 03000 0 0 1 &mpic 2 1
+ 03000 0 0 2 &mpic 3 1
+ 03000 0 0 3 &mpic 0 1
+ 03000 0 0 4 &mpic 1 1
+
+ /* IDSEL 0x8 (PCIX Slot 5) */
+ 04000 0 0 1 &mpic 0 1
+ 04000 0 0 2 &mpic 1 1
+ 04000 0 0 3 &mpic 2 1
+ 04000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0xC (Tsi310 bridge) */
+ 06000 0 0 1 &mpic 0 1
+ 06000 0 0 2 &mpic 1 1
+ 06000 0 0 3 &mpic 2 1
+ 06000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x14 (Slot 2) */
+ 0a000 0 0 1 &mpic 0 1
+ 0a000 0 0 2 &mpic 1 1
+ 0a000 0 0 3 &mpic 2 1
+ 0a000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x15 (Slot 3) */
+ 0a800 0 0 1 &mpic 1 1
+ 0a800 0 0 2 &mpic 2 1
+ 0a800 0 0 3 &mpic 3 1
+ 0a800 0 0 4 &mpic 0 1
+
+ /* IDSEL 0x16 (Slot 4) */
+ 0b000 0 0 1 &mpic 2 1
+ 0b000 0 0 2 &mpic 3 1
+ 0b000 0 0 3 &mpic 0 1
+ 0b000 0 0 4 &mpic 1 1
+
+ /* IDSEL 0x18 (Slot 5) */
+ 0c000 0 0 1 &mpic 0 1
+ 0c000 0 0 2 &mpic 1 1
+ 0c000 0 0 3 &mpic 2 1
+ 0c000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
+ 0E000 0 0 1 &mpic 0 1
+ 0E000 0 0 2 &mpic 1 1
+ 0E000 0 0 3 &mpic 2 1
+ 0E000 0 0 4 &mpic 3 1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e2000000 0 00800000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008000 1000>;
+ compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
+ device_type = "pci";
+
+ pci_bridge@1c {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
- /* IDSEL 0x4 (PCIX Slot 2) */
- 02000 0 0 1 &mpic 0 1
- 02000 0 0 2 &mpic 1 1
- 02000 0 0 3 &mpic 2 1
- 02000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x5 (PCIX Slot 3) */
- 02800 0 0 1 &mpic 1 1
- 02800 0 0 2 &mpic 2 1
- 02800 0 0 3 &mpic 3 1
- 02800 0 0 4 &mpic 0 1
-
- /* IDSEL 0x6 (PCIX Slot 4) */
- 03000 0 0 1 &mpic 2 1
- 03000 0 0 2 &mpic 3 1
- 03000 0 0 3 &mpic 0 1
- 03000 0 0 4 &mpic 1 1
-
- /* IDSEL 0x8 (PCIX Slot 5) */
- 04000 0 0 1 &mpic 0 1
- 04000 0 0 2 &mpic 1 1
- 04000 0 0 3 &mpic 2 1
- 04000 0 0 4 &mpic 3 1
-
- /* IDSEL 0xC (Tsi310 bridge) */
- 06000 0 0 1 &mpic 0 1
- 06000 0 0 2 &mpic 1 1
- 06000 0 0 3 &mpic 2 1
- 06000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x14 (Slot 2) */
- 0a000 0 0 1 &mpic 0 1
- 0a000 0 0 2 &mpic 1 1
- 0a000 0 0 3 &mpic 2 1
- 0a000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x15 (Slot 3) */
- 0a800 0 0 1 &mpic 1 1
- 0a800 0 0 2 &mpic 2 1
- 0a800 0 0 3 &mpic 3 1
- 0a800 0 0 4 &mpic 0 1
-
- /* IDSEL 0x16 (Slot 4) */
- 0b000 0 0 1 &mpic 2 1
- 0b000 0 0 2 &mpic 3 1
- 0b000 0 0 3 &mpic 0 1
- 0b000 0 0 4 &mpic 1 1
-
- /* IDSEL 0x18 (Slot 5) */
- 0c000 0 0 1 &mpic 0 1
- 0c000 0 0 2 &mpic 1 1
- 0c000 0 0 3 &mpic 2 1
- 0c000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
- 0E000 0 0 1 &mpic 0 1
- 0E000 0 0 2 &mpic 1 1
- 0E000 0 0 3 &mpic 2 1
- 0E000 0 0 4 &mpic 3 1>;
- interrupt-parent = <&mpic>;
- interrupts = <18 2>;
- bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 10000000
- 01000000 0 00000000 e2000000 0 00800000>;
- clock-frequency = <3f940aa>;
+ /* IDSEL 0x00 (PrPMC Site) */
+ 0000 0 0 1 &mpic 0 1
+ 0000 0 0 2 &mpic 1 1
+ 0000 0 0 3 &mpic 2 1
+ 0000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x04 (VIA chip) */
+ 2000 0 0 1 &mpic 0 1
+ 2000 0 0 2 &mpic 1 1
+ 2000 0 0 3 &mpic 2 1
+ 2000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x05 (8139) */
+ 2800 0 0 1 &mpic 1 1
+
+ /* IDSEL 0x06 (Slot 6) */
+ 3000 0 0 1 &mpic 2 1
+ 3000 0 0 2 &mpic 3 1
+ 3000 0 0 3 &mpic 0 1
+ 3000 0 0 4 &mpic 1 1
+
+ /* IDESL 0x07 (Slot 7) */
+ 3800 0 0 1 &mpic 3 1
+ 3800 0 0 2 &mpic 0 1
+ 3800 0 0 3 &mpic 1 1
+ 3800 0 0 4 &mpic 2 1>;
+
+ reg = <e000 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <8000 1000>;
- compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
- device_type = "pci";
+ ranges = <02000000 0 80000000
+ 02000000 0 80000000
+ 0 20000000
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00080000>;
+ clock-frequency = <1fca055>;
- pci_bridge@1c {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x00 (PrPMC Site) */
- 0000 0 0 1 &mpic 0 1
- 0000 0 0 2 &mpic 1 1
- 0000 0 0 3 &mpic 2 1
- 0000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x04 (VIA chip) */
- 2000 0 0 1 &mpic 0 1
- 2000 0 0 2 &mpic 1 1
- 2000 0 0 3 &mpic 2 1
- 2000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x05 (8139) */
- 2800 0 0 1 &mpic 1 1
-
- /* IDSEL 0x06 (Slot 6) */
- 3000 0 0 1 &mpic 2 1
- 3000 0 0 2 &mpic 3 1
- 3000 0 0 3 &mpic 0 1
- 3000 0 0 4 &mpic 1 1
-
- /* IDESL 0x07 (Slot 7) */
- 3800 0 0 1 &mpic 3 1
- 3800 0 0 2 &mpic 0 1
- 3800 0 0 3 &mpic 1 1
- 3800 0 0 4 &mpic 2 1>;
-
- reg = <e000 0 0 0 0>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- ranges = <02000000 0 80000000
- 02000000 0 80000000
- 0 20000000
- 01000000 0 00000000
- 01000000 0 00000000
- 0 00080000>;
- clock-frequency = <1fca055>;
-
- isa@4 {
- device_type = "isa";
+ isa@4 {
+ device_type = "isa";
+ #interrupt-cells = <2>;
+ #size-cells = <1>;
+ #address-cells = <2>;
+ reg = <2000 0 0 0 0>;
+ ranges = <1 0 01000000 0 0 00001000>;
+ interrupt-parent = <&i8259>;
+
+ i8259: interrupt-controller@20 {
+ interrupt-controller;
+ device_type = "interrupt-controller";
+ reg = <1 20 2
+ 1 a0 2
+ 1 4d0 2>;
+ #address-cells = <0>;
#interrupt-cells = <2>;
- #size-cells = <1>;
- #address-cells = <2>;
- reg = <2000 0 0 0 0>;
- ranges = <1 0 01000000 0 0 00001000>;
- interrupt-parent = <&i8259>;
-
- i8259: interrupt-controller@20 {
- clock-frequency = <0>;
- interrupt-controller;
- device_type = "interrupt-controller";
- reg = <1 20 2
- 1 a0 2
- 1 4d0 2>;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- built-in;
- compatible = "chrp,iic";
- interrupts = <0 1>;
- interrupt-parent = <&mpic>;
- };
-
- rtc@70 {
- compatible = "pnpPNP,b00";
- reg = <1 70 2>;
- };
+ compatible = "chrp,iic";
+ interrupts = <0 1>;
+ interrupt-parent = <&mpic>;
};
- };
- };
- pci@9000 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x15 */
- a800 0 0 1 &mpic b 1
- a800 0 0 2 &mpic 1 1
- a800 0 0 3 &mpic 2 1
- a800 0 0 4 &mpic 3 1>;
-
- interrupt-parent = <&mpic>;
- interrupts = <19 2>;
- bus-range = <0 0>;
- ranges = <02000000 0 90000000 90000000 0 10000000
- 01000000 0 00000000 e2800000 0 00800000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <9000 1000>;
- compatible = "fsl,mpc8540-pci";
- device_type = "pci";
+ rtc@70 {
+ compatible = "pnpPNP,b00";
+ reg = <1 70 2>;
+ };
+ };
};
- /* PCI Express */
- pcie@a000 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
+ };
- /* IDSEL 0x0 (PEX) */
- 00000 0 0 1 &mpic 0 1
- 00000 0 0 2 &mpic 1 1
- 00000 0 0 3 &mpic 2 1
- 00000 0 0 4 &mpic 3 1>;
+ pci@e0009000 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &mpic b 1
+ a800 0 0 2 &mpic 1 1
+ a800 0 0 3 &mpic 2 1
+ a800 0 0 4 &mpic 3 1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <19 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 90000000 90000000 0 10000000
+ 01000000 0 00000000 e2800000 0 00800000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0009000 1000>;
+ compatible = "fsl,mpc8540-pci";
+ device_type = "pci";
+ };
- interrupt-parent = <&mpic>;
- interrupts = <1a 2>;
- bus-range = <0 ff>;
- ranges = <02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 e3000000 0 08000000>;
- clock-frequency = <1fca055>;
- #interrupt-cells = <1>;
+ pcie@e000a000 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x0 (PEX) */
+ 00000 0 0 1 &mpic 0 1
+ 00000 0 0 2 &mpic 1 1
+ 00000 0 0 3 &mpic 2 1
+ 00000 0 0 4 &mpic 3 1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <1a 2>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 a0000000 a0000000 0 20000000
+ 01000000 0 00000000 e3000000 0 08000000>;
+ clock-frequency = <1fca055>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e000a000 1000>;
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ pcie@0 {
+ reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <a000 1000>;
- compatible = "fsl,mpc8548-pcie";
device_type = "pci";
- };
+ ranges = <02000000 0 a0000000
+ 02000000 0 a0000000
+ 0 20000000
- mpic: pic@40000 {
- clock-frequency = <0>;
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <40000 40000>;
- built-in;
- compatible = "chrp,open-pic";
- device_type = "open-pic";
- big-endian;
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 08000000>;
};
};
};
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index c3c88825212..57029cca32b 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -30,7 +30,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
- 32-bit;
};
};
@@ -42,10 +41,9 @@
soc8555@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
- reg = <e0000000 00100000>; // CCSRBAR 1M
+ reg = <e0000000 00001000>; // CCSRBAR 1M
bus-frequency = <0>;
memory-controller@2000 {
@@ -137,113 +135,145 @@
interrupt-parent = <&mpic>;
};
- pci1: pci@8000 {
- interrupt-map-mask = <1f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x10 */
- 08000 0 0 1 &mpic 0 1
- 08000 0 0 2 &mpic 1 1
- 08000 0 0 3 &mpic 2 1
- 08000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x11 */
- 08800 0 0 1 &mpic 0 1
- 08800 0 0 2 &mpic 1 1
- 08800 0 0 3 &mpic 2 1
- 08800 0 0 4 &mpic 3 1
-
- /* IDSEL 0x12 (Slot 1) */
- 09000 0 0 1 &mpic 0 1
- 09000 0 0 2 &mpic 1 1
- 09000 0 0 3 &mpic 2 1
- 09000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x13 (Slot 2) */
- 09800 0 0 1 &mpic 1 1
- 09800 0 0 2 &mpic 2 1
- 09800 0 0 3 &mpic 3 1
- 09800 0 0 4 &mpic 0 1
-
- /* IDSEL 0x14 (Slot 3) */
- 0a000 0 0 1 &mpic 2 1
- 0a000 0 0 2 &mpic 3 1
- 0a000 0 0 3 &mpic 0 1
- 0a000 0 0 4 &mpic 1 1
-
- /* IDSEL 0x15 (Slot 4) */
- 0a800 0 0 1 &mpic 3 1
- 0a800 0 0 2 &mpic 0 1
- 0a800 0 0 3 &mpic 1 1
- 0a800 0 0 4 &mpic 2 1
-
- /* Bus 1 (Tundra Bridge) */
- /* IDSEL 0x12 (ISA bridge) */
- 19000 0 0 1 &mpic 0 1
- 19000 0 0 2 &mpic 1 1
- 19000 0 0 3 &mpic 2 1
- 19000 0 0 4 &mpic 3 1>;
- interrupt-parent = <&mpic>;
- interrupts = <18 2>;
- bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e2000000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8000 1000>;
- compatible = "fsl,mpc8540-pci";
- device_type = "pci";
-
- i8259@19000 {
- clock-frequency = <0>;
+ mpic: pic@40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <40000 40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ big-endian;
+ };
+
+ cpm@919c0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
+ reg = <919c0 30>;
+ ranges;
+
+ muram@80000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 80000 10000>;
+
+ data@0 {
+ compatible = "fsl,cpm-muram-data";
+ reg = <0 2000 9000 1000>;
+ };
+ };
+
+ brg@919f0 {
+ compatible = "fsl,mpc8555-brg",
+ "fsl,cpm2-brg",
+ "fsl,cpm-brg";
+ reg = <919f0 10 915f0 10>;
+ };
+
+ cpmpic: pic@90c00 {
interrupt-controller;
- device_type = "interrupt-controller";
- reg = <19000 0 0 0 1>;
#address-cells = <0>;
#interrupt-cells = <2>;
- built-in;
- compatible = "chrp,iic";
- big-endian;
- interrupts = <1>;
- interrupt-parent = <&pci1>;
+ interrupts = <2e 2>;
+ interrupt-parent = <&mpic>;
+ reg = <90c00 80>;
+ compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
};
};
+ };
- pci@9000 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
+ pci1: pci@e0008000 {
+ interrupt-map-mask = <1f800 0 0 7>;
+ interrupt-map = <
- /* IDSEL 0x15 */
- a800 0 0 1 &mpic b 1
- a800 0 0 2 &mpic b 1
- a800 0 0 3 &mpic b 1
- a800 0 0 4 &mpic b 1>;
- interrupt-parent = <&mpic>;
- interrupts = <19 2>;
- bus-range = <0 0>;
- ranges = <02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 e3000000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <9000 1000>;
- compatible = "fsl,mpc8540-pci";
- device_type = "pci";
- };
+ /* IDSEL 0x10 */
+ 08000 0 0 1 &mpic 0 1
+ 08000 0 0 2 &mpic 1 1
+ 08000 0 0 3 &mpic 2 1
+ 08000 0 0 4 &mpic 3 1
- mpic: pic@40000 {
- clock-frequency = <0>;
+ /* IDSEL 0x11 */
+ 08800 0 0 1 &mpic 0 1
+ 08800 0 0 2 &mpic 1 1
+ 08800 0 0 3 &mpic 2 1
+ 08800 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x12 (Slot 1) */
+ 09000 0 0 1 &mpic 0 1
+ 09000 0 0 2 &mpic 1 1
+ 09000 0 0 3 &mpic 2 1
+ 09000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x13 (Slot 2) */
+ 09800 0 0 1 &mpic 1 1
+ 09800 0 0 2 &mpic 2 1
+ 09800 0 0 3 &mpic 3 1
+ 09800 0 0 4 &mpic 0 1
+
+ /* IDSEL 0x14 (Slot 3) */
+ 0a000 0 0 1 &mpic 2 1
+ 0a000 0 0 2 &mpic 3 1
+ 0a000 0 0 3 &mpic 0 1
+ 0a000 0 0 4 &mpic 1 1
+
+ /* IDSEL 0x15 (Slot 4) */
+ 0a800 0 0 1 &mpic 3 1
+ 0a800 0 0 2 &mpic 0 1
+ 0a800 0 0 3 &mpic 1 1
+ 0a800 0 0 4 &mpic 2 1
+
+ /* Bus 1 (Tundra Bridge) */
+ /* IDSEL 0x12 (ISA bridge) */
+ 19000 0 0 1 &mpic 0 1
+ 19000 0 0 2 &mpic 1 1
+ 19000 0 0 3 &mpic 2 1
+ 19000 0 0 4 &mpic 3 1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008000 1000>;
+ compatible = "fsl,mpc8540-pci";
+ device_type = "pci";
+
+ i8259@19000 {
interrupt-controller;
+ device_type = "interrupt-controller";
+ reg = <19000 0 0 0 1>;
#address-cells = <0>;
#interrupt-cells = <2>;
- reg = <40000 40000>;
- built-in;
- compatible = "chrp,open-pic";
- device_type = "open-pic";
- big-endian;
+ compatible = "chrp,iic";
+ interrupts = <1>;
+ interrupt-parent = <&pci1>;
};
};
+
+ pci@e0009000 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &mpic b 1
+ a800 0 0 2 &mpic b 1
+ a800 0 0 3 &mpic b 1
+ a800 0 0 4 &mpic b 1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <19 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 a0000000 a0000000 0 20000000
+ 01000000 0 00000000 e3000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0009000 1000>;
+ compatible = "fsl,mpc8540-pci";
+ device_type = "pci";
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index 16dbe848cec..6b362f8222c 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -30,7 +30,6 @@
timebase-frequency = <04ead9a0>;
bus-frequency = <13ab6680>;
clock-frequency = <312c8040>;
- 32-bit;
};
};
@@ -42,7 +41,6 @@
soc8560@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@@ -132,115 +130,39 @@
phy-handle = <&phy1>;
};
- pci@8000 {
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
- device_type = "pci";
- reg = <8000 1000>;
- clock-frequency = <3f940aa>;
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x2 */
- 1000 0 0 1 &mpic 1 1
- 1000 0 0 2 &mpic 2 1
- 1000 0 0 3 &mpic 3 1
- 1000 0 0 4 &mpic 4 1
-
- /* IDSEL 0x3 */
- 1800 0 0 1 &mpic 4 1
- 1800 0 0 2 &mpic 1 1
- 1800 0 0 3 &mpic 2 1
- 1800 0 0 4 &mpic 3 1
-
- /* IDSEL 0x4 */
- 2000 0 0 1 &mpic 3 1
- 2000 0 0 2 &mpic 4 1
- 2000 0 0 3 &mpic 1 1
- 2000 0 0 4 &mpic 2 1
-
- /* IDSEL 0x5 */
- 2800 0 0 1 &mpic 2 1
- 2800 0 0 2 &mpic 3 1
- 2800 0 0 3 &mpic 4 1
- 2800 0 0 4 &mpic 1 1
-
- /* IDSEL 12 */
- 6000 0 0 1 &mpic 1 1
- 6000 0 0 2 &mpic 2 1
- 6000 0 0 3 &mpic 3 1
- 6000 0 0 4 &mpic 4 1
-
- /* IDSEL 13 */
- 6800 0 0 1 &mpic 4 1
- 6800 0 0 2 &mpic 1 1
- 6800 0 0 3 &mpic 2 1
- 6800 0 0 4 &mpic 3 1
-
- /* IDSEL 14*/
- 7000 0 0 1 &mpic 3 1
- 7000 0 0 2 &mpic 4 1
- 7000 0 0 3 &mpic 1 1
- 7000 0 0 4 &mpic 2 1
-
- /* IDSEL 15 */
- 7800 0 0 1 &mpic 2 1
- 7800 0 0 2 &mpic 3 1
- 7800 0 0 3 &mpic 4 1
- 7800 0 0 4 &mpic 1 1
-
- /* IDSEL 18 */
- 9000 0 0 1 &mpic 1 1
- 9000 0 0 2 &mpic 2 1
- 9000 0 0 3 &mpic 3 1
- 9000 0 0 4 &mpic 4 1
-
- /* IDSEL 19 */
- 9800 0 0 1 &mpic 4 1
- 9800 0 0 2 &mpic 1 1
- 9800 0 0 3 &mpic 2 1
- 9800 0 0 4 &mpic 3 1
-
- /* IDSEL 20 */
- a000 0 0 1 &mpic 3 1
- a000 0 0 2 &mpic 4 1
- a000 0 0 3 &mpic 1 1
- a000 0 0 4 &mpic 2 1
-
- /* IDSEL 21 */
- a800 0 0 1 &mpic 2 1
- a800 0 0 2 &mpic 3 1
- a800 0 0 3 &mpic 4 1
- a800 0 0 4 &mpic 1 1>;
-
- interrupt-parent = <&mpic>;
- interrupts = <18 2>;
- bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e2000000 0 01000000>;
- };
-
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
- built-in;
device_type = "open-pic";
};
- cpm@e0000000 {
+ cpm@919c0 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
- device_type = "cpm";
- model = "CPM2";
- ranges = <0 0 c0000>;
- reg = <80000 40000>;
- command-proc = <919c0>;
- brg-frequency = <9d5b340>;
+ compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
+ reg = <919c0 30>;
+ ranges;
+
+ muram@80000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 80000 10000>;
+
+ data@0 {
+ compatible = "fsl,cpm-muram-data";
+ reg = <0 4000 9000 2000>;
+ };
+ };
+
+ brg@919f0 {
+ compatible = "fsl,mpc8560-brg",
+ "fsl,cpm2-brg",
+ "fsl,cpm-brg";
+ reg = <919f0 10 915f0 10>;
+ clock-frequency = <d#165000000>;
+ };
cpmpic: pic@90c00 {
interrupt-controller;
@@ -249,44 +171,38 @@
interrupts = <2e 2>;
interrupt-parent = <&mpic>;
reg = <90c00 80>;
- built-in;
- device_type = "cpm-pic";
+ compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
};
- scc@91a00 {
+ serial@91a00 {
device_type = "serial";
- compatible = "cpm_uart";
- model = "SCC";
- device-id = <1>;
+ compatible = "fsl,mpc8560-scc-uart",
+ "fsl,cpm2-scc-uart";
reg = <91a00 20 88000 100>;
- clock-setup = <00ffffff 0>;
- rx-clock = <1>;
- tx-clock = <1>;
+ fsl,cpm-brg = <1>;
+ fsl,cpm-command = <00800000>;
current-speed = <1c200>;
interrupts = <28 8>;
interrupt-parent = <&cpmpic>;
};
- scc@91a20 {
+ serial@91a20 {
device_type = "serial";
- compatible = "cpm_uart";
- model = "SCC";
- device-id = <2>;
+ compatible = "fsl,mpc8560-scc-uart",
+ "fsl,cpm2-scc-uart";
reg = <91a20 20 88100 100>;
- clock-setup = <ff00ffff 90000>;
- rx-clock = <2>;
- tx-clock = <2>;
+ fsl,cpm-brg = <2>;
+ fsl,cpm-command = <04a00000>;
current-speed = <1c200>;
interrupts = <29 8>;
interrupt-parent = <&cpmpic>;
};
- fcc@91320 {
+ ethernet@91320 {
device_type = "network";
- compatible = "fs_enet";
- model = "FCC";
- device-id = <2>;
- reg = <91320 20 88500 100 913a0 30>;
+ compatible = "fsl,mpc8560-fcc-enet",
+ "fsl,cpm2-fcc-enet";
+ reg = <91320 20 88500 100 913b0 1>;
/*
* mac-address is deprecated and will be removed
* in 2.6.25. Only recent versions of
@@ -294,20 +210,17 @@
*/
mac-address = [ 00 00 00 00 00 00 ];
local-mac-address = [ 00 00 00 00 00 00 ];
- clock-setup = <ff00ffff 250000>;
- rx-clock = <15>;
- tx-clock = <16>;
+ fsl,cpm-command = <16200300>;
interrupts = <21 8>;
interrupt-parent = <&cpmpic>;
phy-handle = <&phy2>;
};
- fcc@91340 {
+ ethernet@91340 {
device_type = "network";
- compatible = "fs_enet";
- model = "FCC";
- device-id = <3>;
- reg = <91340 20 88600 100 913d0 30>;
+ compatible = "fsl,mpc8560-fcc-enet",
+ "fsl,cpm2-fcc-enet";
+ reg = <91340 20 88600 100 913d0 1>;
/*
* mac-address is deprecated and will be removed
* in 2.6.25. Only recent versions of
@@ -315,13 +228,101 @@
*/
mac-address = [ 00 00 00 00 00 00 ];
local-mac-address = [ 00 00 00 00 00 00 ];
- clock-setup = <ffff00ff 3700>;
- rx-clock = <17>;
- tx-clock = <18>;
+ fsl,cpm-command = <1a400300>;
interrupts = <22 8>;
interrupt-parent = <&cpmpic>;
phy-handle = <&phy3>;
};
};
};
+
+ pci@e0008000 {
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
+ device_type = "pci";
+ reg = <e0008000 1000>;
+ clock-frequency = <3f940aa>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x2 */
+ 1000 0 0 1 &mpic 1 1
+ 1000 0 0 2 &mpic 2 1
+ 1000 0 0 3 &mpic 3 1
+ 1000 0 0 4 &mpic 4 1
+
+ /* IDSEL 0x3 */
+ 1800 0 0 1 &mpic 4 1
+ 1800 0 0 2 &mpic 1 1
+ 1800 0 0 3 &mpic 2 1
+ 1800 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x4 */
+ 2000 0 0 1 &mpic 3 1
+ 2000 0 0 2 &mpic 4 1
+ 2000 0 0 3 &mpic 1 1
+ 2000 0 0 4 &mpic 2 1
+
+ /* IDSEL 0x5 */
+ 2800 0 0 1 &mpic 2 1
+ 2800 0 0 2 &mpic 3 1
+ 2800 0 0 3 &mpic 4 1
+ 2800 0 0 4 &mpic 1 1
+
+ /* IDSEL 12 */
+ 6000 0 0 1 &mpic 1 1
+ 6000 0 0 2 &mpic 2 1
+ 6000 0 0 3 &mpic 3 1
+ 6000 0 0 4 &mpic 4 1
+
+ /* IDSEL 13 */
+ 6800 0 0 1 &mpic 4 1
+ 6800 0 0 2 &mpic 1 1
+ 6800 0 0 3 &mpic 2 1
+ 6800 0 0 4 &mpic 3 1
+
+ /* IDSEL 14*/
+ 7000 0 0 1 &mpic 3 1
+ 7000 0 0 2 &mpic 4 1
+ 7000 0 0 3 &mpic 1 1
+ 7000 0 0 4 &mpic 2 1
+
+ /* IDSEL 15 */
+ 7800 0 0 1 &mpic 2 1
+ 7800 0 0 2 &mpic 3 1
+ 7800 0 0 3 &mpic 4 1
+ 7800 0 0 4 &mpic 1 1
+
+ /* IDSEL 18 */
+ 9000 0 0 1 &mpic 1 1
+ 9000 0 0 2 &mpic 2 1
+ 9000 0 0 3 &mpic 3 1
+ 9000 0 0 4 &mpic 4 1
+
+ /* IDSEL 19 */
+ 9800 0 0 1 &mpic 4 1
+ 9800 0 0 2 &mpic 1 1
+ 9800 0 0 3 &mpic 2 1
+ 9800 0 0 4 &mpic 3 1
+
+ /* IDSEL 20 */
+ a000 0 0 1 &mpic 3 1
+ a000 0 0 2 &mpic 4 1
+ a000 0 0 3 &mpic 1 1
+ a000 0 0 4 &mpic 2 1
+
+ /* IDSEL 21 */
+ a800 0 0 1 &mpic 2 1
+ a800 0 0 2 &mpic 3 1
+ a800 0 0 3 &mpic 4 1
+ a800 0 0 4 &mpic 1 1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 e2000000 0 01000000>;
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index b1dcfbe8c1f..54394372b12 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -34,7 +34,6 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
- 32-bit;
};
};
@@ -51,10 +50,9 @@
soc8568@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
- reg = <e0000000 00100000>;
+ reg = <e0000000 00001000>;
bus-frequency = <0>;
memory-controller@2000 {
@@ -74,15 +72,24 @@
};
i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
device_type = "i2c";
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <2b 2>;
interrupt-parent = <&mpic>;
dfsrr;
+
+ rtc@68 {
+ compatible = "dallas,ds1374";
+ reg = <68>;
+ };
};
i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
device_type = "i2c";
compatible = "fsl-i2c";
reg = <3100 100>;
@@ -97,10 +104,10 @@
device_type = "mdio";
compatible = "gianfar";
reg = <24520 20>;
- phy0: ethernet-phy@0 {
+ phy0: ethernet-phy@7 {
interrupt-parent = <&mpic>;
interrupts = <1 1>;
- reg = <0>;
+ reg = <7>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
@@ -176,60 +183,6 @@
fsl,has-rstcr;
};
- pci@8000 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x12 AD18 */
- 9000 0 0 1 &mpic 5 1
- 9000 0 0 2 &mpic 6 1
- 9000 0 0 3 &mpic 7 1
- 9000 0 0 4 &mpic 4 1
-
- /* IDSEL 0x13 AD19 */
- 9800 0 0 1 &mpic 6 1
- 9800 0 0 2 &mpic 7 1
- 9800 0 0 3 &mpic 4 1
- 9800 0 0 4 &mpic 5 1>;
-
- interrupt-parent = <&mpic>;
- interrupts = <18 2>;
- bus-range = <0 ff>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e2000000 0 00800000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8000 1000>;
- compatible = "fsl,mpc8540-pci";
- device_type = "pci";
- };
-
- /* PCI Express */
- pcie@a000 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x0 (PEX) */
- 00000 0 0 1 &mpic 0 1
- 00000 0 0 2 &mpic 1 1
- 00000 0 0 3 &mpic 2 1
- 00000 0 0 4 &mpic 3 1>;
-
- interrupt-parent = <&mpic>;
- interrupts = <1a 2>;
- bus-range = <0 ff>;
- ranges = <02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 e3000000 0 08000000>;
- clock-frequency = <1fca055>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <a000 1000>;
- compatible = "fsl,mpc8548-pcie";
- device_type = "pci";
- };
-
serial@4600 {
device_type = "serial";
compatible = "ns16550";
@@ -258,11 +211,11 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
- built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
+
par_io@e0100 {
reg = <e0100 100>;
device_type = "par_io";
@@ -289,12 +242,13 @@
4 1a 2 0 2 0 /* RxD7 */
4 0b 1 0 2 0 /* TX_EN */
4 18 1 0 2 0 /* TX_ER */
- 4 0f 2 0 2 0 /* RX_DV */
+ 4 10 2 0 2 0 /* RX_DV */
4 1e 2 0 2 0 /* RX_ER */
4 11 2 0 2 0 /* RX_CLK */
4 13 1 0 2 0 /* GTX_CLK */
1 1f 2 0 3 0>; /* GTX125 */
};
+
pio2: ucc_pin@02 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
@@ -380,10 +334,10 @@
mac-address = [ 00 00 00 00 00 00 ];
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock = <0>;
- tx-clock = <19>;
- phy-handle = <&qe_phy0>;
- phy-connection-type = "gmii";
+ tx-clock = <20>;
pio-handle = <&pio1>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "rgmii-id";
};
ucc@3000 {
@@ -402,10 +356,10 @@
mac-address = [ 00 00 00 00 00 00 ];
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock = <0>;
- tx-clock = <14>;
- phy-handle = <&qe_phy1>;
- phy-connection-type = "gmii";
+ tx-clock = <20>;
pio-handle = <&pio2>;
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
};
mdio@2120 {
@@ -417,10 +371,10 @@
/* These are the same PHYs as on
* gianfar's MDIO bus */
- qe_phy0: ethernet-phy@00 {
+ qe_phy0: ethernet-phy@07 {
interrupt-parent = <&mpic>;
interrupts = <1 1>;
- reg = <0>;
+ reg = <7>;
device_type = "ethernet-phy";
};
qe_phy1: ethernet-phy@01 {
@@ -449,11 +403,77 @@
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
- built-in;
big-endian;
interrupts = <2e 2 2e 2>; //high:30 low:30
interrupt-parent = <&mpic>;
};
};
+
+ pci@e0008000 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x12 AD18 */
+ 9000 0 0 1 &mpic 5 1
+ 9000 0 0 2 &mpic 6 1
+ 9000 0 0 3 &mpic 7 1
+ 9000 0 0 4 &mpic 4 1
+
+ /* IDSEL 0x13 AD19 */
+ 9800 0 0 1 &mpic 6 1
+ 9800 0 0 2 &mpic 7 1
+ 9800 0 0 3 &mpic 4 1
+ 9800 0 0 4 &mpic 5 1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 e2000000 0 00800000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008000 1000>;
+ compatible = "fsl,mpc8540-pci";
+ device_type = "pci";
+ };
+
+ /* PCI Express */
+ pcie@e000a000 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x0 (PEX) */
+ 00000 0 0 1 &mpic 0 1
+ 00000 0 0 2 &mpic 1 1
+ 00000 0 0 3 &mpic 2 1
+ 00000 0 0 4 &mpic 3 1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <1a 2>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 a0000000 a0000000 0 10000000
+ 01000000 0 00000000 e2800000 0 00800000>;
+ clock-frequency = <1fca055>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e000a000 1000>;
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <02000000 0 a0000000
+ 02000000 0 a0000000
+ 0 10000000
+
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00800000>;
+ };
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
new file mode 100644
index 00000000000..d638deec765
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -0,0 +1,404 @@
+/*
+ * MPC8572 DS Device Tree Source
+ *
+ * Copyright 2007 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/ {
+ model = "fsl,MPC8572DS";
+ compatible = "fsl,MPC8572DS";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8572@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <20>; // 32 bytes
+ i-cache-line-size = <20>; // 32 bytes
+ d-cache-size = <8000>; // L1, 32K
+ i-cache-size = <8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <00000000 00000000>; // Filled by U-Boot
+ };
+
+ soc8572@ffe00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <00000000 ffe00000 00100000>;
+ reg = <ffe00000 00001000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
+ bus-frequency = <0>; // Filled out by uboot.
+
+ memory-controller@2000 {
+ compatible = "fsl,mpc8572-memory-controller";
+ reg = <2000 1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <12 2>;
+ };
+
+ memory-controller@6000 {
+ compatible = "fsl,mpc8572-memory-controller";
+ reg = <6000 1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <12 2>;
+ };
+
+ l2-cache-controller@20000 {
+ compatible = "fsl,mpc8572-l2-cache-controller";
+ reg = <20000 1000>;
+ cache-line-size = <20>; // 32 bytes
+ cache-size = <80000>; // L2, 512K
+ interrupt-parent = <&mpic>;
+ interrupts = <10 2>;
+ };
+
+ i2c@3000 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ reg = <3000 100>;
+ interrupts = <2b 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ reg = <3100 100>;
+ interrupts = <2b 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ mdio@24520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "mdio";
+ compatible = "gianfar";
+ reg = <24520 20>;
+ phy0: ethernet-phy@0 {
+ interrupt-parent = <&mpic>;
+ interrupts = <a 1>;
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <a 1>;
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ interrupt-parent = <&mpic>;
+ interrupts = <a 1>;
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ interrupt-parent = <&mpic>;
+ interrupts = <a 1>;
+ reg = <3>;
+ };
+ };
+
+ ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <24000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <1d 2 1e 2 22 2>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ ethernet@25000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <25000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <23 2 24 2 28 2>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ ethernet@26000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <26000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <1f 2 20 2 21 2>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy2>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ ethernet@27000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <27000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <25 2 26 2 27 2>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy3>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ serial@4500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4500 100>;
+ clock-frequency = <0>;
+ interrupts = <2a 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial@4600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4600 100>;
+ clock-frequency = <0>;
+ interrupts = <2a 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities@e0000 { //global utilities block
+ compatible = "fsl,mpc8572-guts";
+ reg = <e0000 1000>;
+ fsl,has-rstcr;
+ };
+
+ mpic: pic@40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <40000 40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ big-endian;
+ };
+ };
+
+ pcie@ffe08000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <ffe08000 1000>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 ffc00000 0 00010000>;
+ clock-frequency = <1fca055>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ interrupt-map-mask = <fb00 0 0 0>;
+ interrupt-map = <
+ /* IDSEL 0x11 - PCI slot 1 */
+ 8800 0 0 1 &mpic 2 1
+ 8800 0 0 2 &mpic 3 1
+ 8800 0 0 3 &mpic 4 1
+ 8800 0 0 4 &mpic 1 1
+
+ /* IDSEL 0x12 - PCI slot 2 */
+ 9000 0 0 1 &mpic 3 1
+ 9000 0 0 2 &mpic 4 1
+ 9000 0 0 3 &mpic 1 1
+ 9000 0 0 4 &mpic 2 1
+
+ // IDSEL 0x1c USB
+ e000 0 0 0 &i8259 c 2
+ e100 0 0 0 &i8259 9 2
+ e200 0 0 0 &i8259 a 2
+ e300 0 0 0 &i8259 b 2
+
+ // IDSEL 0x1d Audio
+ e800 0 0 0 &i8259 6 2
+
+ // IDSEL 0x1e Legacy
+ f000 0 0 0 &i8259 7 2
+ f100 0 0 0 &i8259 7 2
+
+ // IDSEL 0x1f IDE/SATA
+ f800 0 0 0 &i8259 e 2
+ f900 0 0 0 &i8259 5 2
+
+ >;
+
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <02000000 0 80000000
+ 02000000 0 80000000
+ 0 20000000
+
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00100000>;
+ uli1575@0 {
+ reg = <0 0 0 0 0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ ranges = <02000000 0 80000000
+ 02000000 0 80000000
+ 0 20000000
+
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00100000>;
+ isa@1e {
+ device_type = "isa";
+ #interrupt-cells = <2>;
+ #size-cells = <1>;
+ #address-cells = <2>;
+ reg = <f000 0 0 0 0>;
+ ranges = <1 0 01000000 0 0
+ 00001000>;
+ interrupt-parent = <&i8259>;
+
+ i8259: interrupt-controller@20 {
+ reg = <1 20 2
+ 1 a0 2
+ 1 4d0 2>;
+ interrupt-controller;
+ device_type = "interrupt-controller";
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ compatible = "chrp,iic";
+ interrupts = <9 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ i8042@60 {
+ #size-cells = <0>;
+ #address-cells = <1>;
+ reg = <1 60 1 1 64 1>;
+ interrupts = <1 3 c 3>;
+ interrupt-parent =
+ <&i8259>;
+
+ keyboard@0 {
+ reg = <0>;
+ compatible = "pnpPNP,303";
+ };
+
+ mouse@1 {
+ reg = <1>;
+ compatible = "pnpPNP,f03";
+ };
+ };
+
+ rtc@70 {
+ compatible = "pnpPNP,b00";
+ reg = <1 70 2>;
+ };
+
+ gpio@400 {
+ reg = <1 400 80>;
+ };
+ };
+ };
+ };
+
+ };
+
+ pcie@ffe09000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <ffe09000 1000>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 a0000000 a0000000 0 20000000
+ 01000000 0 00000000 ffc10000 0 00010000>;
+ clock-frequency = <1fca055>;
+ interrupt-parent = <&mpic>;
+ interrupts = <1a 2>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 4 1
+ 0000 0 0 2 &mpic 5 1
+ 0000 0 0 3 &mpic 6 1
+ 0000 0 0 4 &mpic 7 1
+ >;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <02000000 0 a0000000
+ 02000000 0 a0000000
+ 0 20000000
+
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00100000>;
+ };
+ };
+
+ pcie@ffe0a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <ffe0a000 1000>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 c0000000 c0000000 0 20000000
+ 01000000 0 00000000 ffc20000 0 00010000>;
+ clock-frequency = <1fca055>;
+ interrupt-parent = <&mpic>;
+ interrupts = <1b 2>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 0 1
+ 0000 0 0 2 &mpic 1 1
+ 0000 0 0 3 &mpic 2 1
+ 0000 0 0 4 &mpic 3 1
+ >;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <02000000 0 c0000000
+ 02000000 0 c0000000
+ 0 20000000
+
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00100000>;
+ };
+ };
+};
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
new file mode 100644
index 00000000000..966edf1161a
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -0,0 +1,191 @@
+/*
+ * MPC8610 HPCD Device Tree Source
+ *
+ * Copyright 2007 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License Version 2 as published
+ * by the Free Software Foundation.
+ */
+
+
+/ {
+ model = "MPC8610HPCD";
+ compatible = "fsl,MPC8610HPCD";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8610@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <d# 32>; // bytes
+ i-cache-line-size = <d# 32>; // bytes
+ d-cache-size = <8000>; // L1, 32K
+ i-cache-size = <8000>; // L1, 32K
+ timebase-frequency = <0>; // 33 MHz, from uboot
+ bus-frequency = <0>; // From uboot
+ clock-frequency = <0>; // From uboot
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <00000000 20000000>; // 512M at 0x0
+ };
+
+ soc@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <2>;
+ device_type = "soc";
+ ranges = <0 e0000000 00100000>;
+ reg = <e0000000 1000>;
+ bus-frequency = <0>;
+
+ i2c@3000 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3000 100>;
+ interrupts = <2b 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3100 100>;
+ interrupts = <2b 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ serial@4500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4500 100>;
+ clock-frequency = <0>;
+ interrupts = <2a 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial@4600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4600 100>;
+ clock-frequency = <0>;
+ interrupts = <1c 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+
+ mpic: interrupt-controller@40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <40000 40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ big-endian;
+ };
+
+ global-utilities@e0000 {
+ compatible = "fsl,mpc8610-guts";
+ reg = <e0000 1000>;
+ fsl,has-rstcr;
+ };
+ };
+
+ pci@e0008000 {
+ compatible = "fsl,mpc8610-pci";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008000 1000>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e1000000 0 00100000>;
+ clock-frequency = <1fca055>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x11 */
+ 8800 0 0 1 &mpic 4 1
+ 8800 0 0 2 &mpic 5 1
+ 8800 0 0 3 &mpic 6 1
+ 8800 0 0 4 &mpic 7 1
+
+ /* IDSEL 0x12 */
+ 9000 0 0 1 &mpic 5 1
+ 9000 0 0 2 &mpic 6 1
+ 9000 0 0 3 &mpic 7 1
+ 9000 0 0 4 &mpic 4 1
+ >;
+ };
+
+ pcie@e000a000 {
+ compatible = "fsl,mpc8641-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e000a000 1000>;
+ bus-range = <1 3>;
+ ranges = <02000000 0 a0000000 a0000000 0 10000000
+ 01000000 0 00000000 e3000000 0 00100000>;
+ clock-frequency = <1fca055>;
+ interrupt-parent = <&mpic>;
+ interrupts = <1a 2>;
+ interrupt-map-mask = <f800 0 0 7>;
+
+ interrupt-map = <
+ /* IDSEL 0x1b */
+ d800 0 0 1 &mpic 2 1
+
+ /* IDSEL 0x1c*/
+ e000 0 0 1 &mpic 1 1
+ e000 0 0 2 &mpic 1 1
+ e000 0 0 3 &mpic 1 1
+ e000 0 0 4 &mpic 1 1
+
+ /* IDSEL 0x1f */
+ f800 0 0 1 &mpic 3 0
+ f800 0 0 2 &mpic 0 1
+ >;
+
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <02000000 0 a0000000
+ 02000000 0 a0000000
+ 0 10000000
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00100000>;
+ uli1575@0 {
+ reg = <0 0 0 0 0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ ranges = <02000000 0 a0000000
+ 02000000 0 a0000000
+ 0 10000000
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00100000>;
+ };
+ };
+ };
+};
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index b0166e5c177..367765937a0 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -30,7 +30,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
- 32-bit;
};
PowerPC,8641@1 {
device_type = "cpu";
@@ -42,7 +41,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
- 32-bit;
};
};
@@ -54,13 +52,8 @@
soc8641@f8000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
- ranges = <00001000 f8001000 000ff000
- 80000000 80000000 20000000
- e2000000 e2000000 00100000
- a0000000 a0000000 20000000
- e3000000 e3000000 00100000>;
+ ranges = <00000000 f8000000 00100000>;
reg = <f8000000 00001000>; // CCSRBAR
bus-frequency = <0>;
@@ -211,50 +204,81 @@
interrupt-parent = <&mpic>;
};
- pcie@8000 {
- compatible = "fsl,mpc8641-pcie";
- device_type = "pci";
- #interrupt-cells = <1>;
+ mpic: pic@40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <40000 40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ big-endian;
+ };
+
+ global-utilities@e0000 {
+ compatible = "fsl,mpc8641-guts";
+ reg = <e0000 1000>;
+ fsl,has-rstcr;
+ };
+ };
+
+ pcie@f8008000 {
+ compatible = "fsl,mpc8641-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <f8008000 1000>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <1fca055>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ interrupt-map-mask = <fb00 0 0 0>;
+ interrupt-map = <
+ /* IDSEL 0x11 */
+ 8800 0 0 1 &i8259 9 2
+ 8800 0 0 2 &i8259 a 2
+ 8800 0 0 3 &i8259 b 2
+ 8800 0 0 4 &i8259 c 2
+
+ /* IDSEL 0x12 */
+ 9000 0 0 1 &i8259 a 2
+ 9000 0 0 2 &i8259 b 2
+ 9000 0 0 3 &i8259 c 2
+ 9000 0 0 4 &i8259 9 2
+
+ // IDSEL 0x1c USB
+ e000 0 0 0 &i8259 c 2
+ e100 0 0 0 &i8259 9 2
+ e200 0 0 0 &i8259 a 2
+ e300 0 0 0 &i8259 b 2
+
+ // IDSEL 0x1d Audio
+ e800 0 0 0 &i8259 6 2
+
+ // IDSEL 0x1e Legacy
+ f000 0 0 0 &i8259 7 2
+ f100 0 0 0 &i8259 7 2
+
+ // IDSEL 0x1f IDE/SATA
+ f800 0 0 0 &i8259 e 2
+ f900 0 0 0 &i8259 5 2
+ >;
+
+ pcie@0 {
+ reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <8000 1000>;
- bus-range = <0 ff>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e2000000 0 00100000>;
- clock-frequency = <1fca055>;
- interrupt-parent = <&mpic>;
- interrupts = <18 2>;
- interrupt-map-mask = <fb00 0 0 0>;
- interrupt-map = <
- /* IDSEL 0x11 */
- 8800 0 0 1 &i8259 9 2
- 8800 0 0 2 &i8259 a 2
- 8800 0 0 3 &i8259 b 2
- 8800 0 0 4 &i8259 c 2
-
- /* IDSEL 0x12 */
- 9000 0 0 1 &i8259 a 2
- 9000 0 0 2 &i8259 b 2
- 9000 0 0 3 &i8259 c 2
- 9000 0 0 4 &i8259 9 2
-
- // IDSEL 0x1c USB
- e000 0 0 0 &i8259 c 2
- e100 0 0 0 &i8259 9 2
- e200 0 0 0 &i8259 a 2
- e300 0 0 0 &i8259 b 2
-
- // IDSEL 0x1d Audio
- e800 0 0 0 &i8259 6 2
-
- // IDSEL 0x1e Legacy
- f000 0 0 0 &i8259 7 2
- f100 0 0 0 &i8259 7 2
-
- // IDSEL 0x1f IDE/SATA
- f800 0 0 0 &i8259 e 2
- f900 0 0 0 &i8259 5 2
- >;
+ device_type = "pci";
+ ranges = <02000000 0 80000000
+ 02000000 0 80000000
+ 0 20000000
+
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00100000>;
uli1575@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
@@ -265,111 +289,96 @@
01000000 0 00000000
01000000 0 00000000
0 00100000>;
+ isa@1e {
+ device_type = "isa";
+ #interrupt-cells = <2>;
+ #size-cells = <1>;
+ #address-cells = <2>;
+ reg = <f000 0 0 0 0>;
+ ranges = <1 0 01000000 0 0
+ 00001000>;
+ interrupt-parent = <&i8259>;
- pci_bridge@0 {
- reg = <0 0 0 0 0>;
- #size-cells = <2>;
- #address-cells = <3>;
- ranges = <02000000 0 80000000
- 02000000 0 80000000
- 0 20000000
- 01000000 0 00000000
- 01000000 0 00000000
- 0 00100000>;
-
- isa@1e {
- device_type = "isa";
+ i8259: interrupt-controller@20 {
+ reg = <1 20 2
+ 1 a0 2
+ 1 4d0 2>;
+ interrupt-controller;
+ device_type = "interrupt-controller";
+ #address-cells = <0>;
#interrupt-cells = <2>;
- #size-cells = <1>;
- #address-cells = <2>;
- reg = <f000 0 0 0 0>;
- ranges = <1 0 01000000 0 0
- 00001000>;
- interrupt-parent = <&i8259>;
-
- i8259: interrupt-controller@20 {
- reg = <1 20 2
- 1 a0 2
- 1 4d0 2>;
- clock-frequency = <0>;
- interrupt-controller;
- device_type = "interrupt-controller";
- #address-cells = <0>;
- #interrupt-cells = <2>;
- built-in;
- compatible = "chrp,iic";
- interrupts = <9 2>;
- interrupt-parent =
- <&mpic>;
- };
+ compatible = "chrp,iic";
+ interrupts = <9 2>;
+ interrupt-parent = <&mpic>;
+ };
- i8042@60 {
- #size-cells = <0>;
- #address-cells = <1>;
- reg = <1 60 1 1 64 1>;
- interrupts = <1 3 c 3>;
- interrupt-parent =
- <&i8259>;
-
- keyboard@0 {
- reg = <0>;
- compatible = "pnpPNP,303";
- };
-
- mouse@1 {
- reg = <1>;
- compatible = "pnpPNP,f03";
- };
- };
+ i8042@60 {
+ #size-cells = <0>;
+ #address-cells = <1>;
+ reg = <1 60 1 1 64 1>;
+ interrupts = <1 3 c 3>;
+ interrupt-parent =
+ <&i8259>;
- rtc@70 {
- compatible =
- "pnpPNP,b00";
- reg = <1 70 2>;
+ keyboard@0 {
+ reg = <0>;
+ compatible = "pnpPNP,303";
};
- gpio@400 {
- reg = <1 400 80>;
+ mouse@1 {
+ reg = <1>;
+ compatible = "pnpPNP,f03";
};
};
+
+ rtc@70 {
+ compatible =
+ "pnpPNP,b00";
+ reg = <1 70 2>;
+ };
+
+ gpio@400 {
+ reg = <1 400 80>;
+ };
};
};
-
};
- pcie@9000 {
- compatible = "fsl,mpc8641-pcie";
- device_type = "pci";
- #interrupt-cells = <1>;
+ };
+
+ pcie@f8009000 {
+ compatible = "fsl,mpc8641-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <f8009000 1000>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 a0000000 a0000000 0 20000000
+ 01000000 0 00000000 e3000000 0 00100000>;
+ clock-frequency = <1fca055>;
+ interrupt-parent = <&mpic>;
+ interrupts = <19 2>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 4 1
+ 0000 0 0 2 &mpic 5 1
+ 0000 0 0 3 &mpic 6 1
+ 0000 0 0 4 &mpic 7 1
+ >;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <9000 1000>;
- bus-range = <0 ff>;
- ranges = <02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 e3000000 0 00100000>;
- clock-frequency = <1fca055>;
- interrupt-parent = <&mpic>;
- interrupts = <19 2>;
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x0 */
- 0000 0 0 1 &mpic 4 1
- 0000 0 0 2 &mpic 5 1
- 0000 0 0 3 &mpic 6 1
- 0000 0 0 4 &mpic 7 1
- >;
- };
+ device_type = "pci";
+ ranges = <02000000 0 a0000000
+ 02000000 0 a0000000
+ 0 20000000
- mpic: pic@40000 {
- clock-frequency = <0>;
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <40000 40000>;
- built-in;
- compatible = "chrp,open-pic";
- device_type = "open-pic";
- big-endian;
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00100000>;
};
};
};
diff --git a/arch/powerpc/boot/dts/mpc866ads.dts b/arch/powerpc/boot/dts/mpc866ads.dts
index e5e7726ddb0..90f2293ed3c 100644
--- a/arch/powerpc/boot/dts/mpc866ads.dts
+++ b/arch/powerpc/boot/dts/mpc866ads.dts
@@ -30,7 +30,6 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
- 32-bit;
interrupts = <f 2>; // decrementer interrupt
interrupt-parent = <&Mpc8xx_pic>;
};
@@ -44,7 +43,6 @@
soc866@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 ff000000 00100000>;
reg = <ff000000 00000200>;
@@ -78,7 +76,6 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0 24>;
- built-in;
device_type = "mpc8xx-pic";
compatible = "CPM";
};
@@ -86,7 +83,6 @@
cpm@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "cpm";
model = "CPM";
ranges = <0 0 4000>;
@@ -103,7 +99,6 @@
interrupts = <5 2 0 2>;
interrupt-parent = <&Mpc8xx_pic>;
reg = <930 20>;
- built-in;
device_type = "cpm-pic";
compatible = "CPM";
};
diff --git a/arch/powerpc/boot/dts/mpc885ads.dts b/arch/powerpc/boot/dts/mpc885ads.dts
index dc7ab9c8061..8848e637293 100644
--- a/arch/powerpc/boot/dts/mpc885ads.dts
+++ b/arch/powerpc/boot/dts/mpc885ads.dts
@@ -2,6 +2,7 @@
* MPC885 ADS Device Tree Source
*
* Copyright 2006 MontaVista Software, Inc.
+ * Copyright 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -12,7 +13,7 @@
/ {
model = "MPC885ADS";
- compatible = "mpc8xx";
+ compatible = "fsl,mpc885ads";
#address-cells = <1>;
#size-cells = <1>;
@@ -23,161 +24,199 @@
PowerPC,885@0 {
device_type = "cpu";
reg = <0>;
- d-cache-line-size = <20>; // 32 bytes
- i-cache-line-size = <20>; // 32 bytes
- d-cache-size = <2000>; // L1, 8K
- i-cache-size = <2000>; // L1, 8K
+ d-cache-line-size = <d#16>;
+ i-cache-line-size = <d#16>;
+ d-cache-size = <d#8192>;
+ i-cache-size = <d#8192>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
- 32-bit;
interrupts = <f 2>; // decrementer interrupt
- interrupt-parent = <&Mpc8xx_pic>;
+ interrupt-parent = <&PIC>;
};
};
memory {
device_type = "memory";
- reg = <00000000 800000>;
+ reg = <0 0>;
};
- soc885@ff000000 {
+ localbus@ff000100 {
+ compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <ff000100 40>;
+
+ ranges = <
+ 0 0 fe000000 00800000
+ 1 0 ff080000 00008000
+ 5 0 ff0a0000 00008000
+ >;
+
+ flash@0,0 {
+ compatible = "jedec-flash";
+ reg = <0 0 800000>;
+ bank-width = <4>;
+ device-width = <1>;
+ };
+
+ board-control@1,0 {
+ reg = <1 0 20 5 300 4>;
+ compatible = "fsl,mpc885ads-bcsr";
+ };
+ };
+
+ soc@ff000000 {
+ compatible = "fsl,mpc885", "fsl,pq1-soc";
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
- ranges = <0 ff000000 00100000>;
- reg = <ff000000 00000200>;
+ ranges = <0 ff000000 00004000>;
bus-frequency = <0>;
- mdio@e80 {
- device_type = "mdio";
- compatible = "fs_enet";
- reg = <e80 8>;
+
+ // Temporary -- will go away once kernel uses ranges for get_immrbase().
+ reg = <ff000000 4000>;
+
+ mdio@e00 {
+ compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
+ reg = <e00 188>;
#address-cells = <1>;
#size-cells = <0>;
- Phy0: ethernet-phy@0 {
+
+ PHY0: ethernet-phy@0 {
reg = <0>;
device_type = "ethernet-phy";
};
- Phy1: ethernet-phy@1 {
+
+ PHY1: ethernet-phy@1 {
reg = <1>;
device_type = "ethernet-phy";
};
- Phy2: ethernet-phy@2 {
+
+ PHY2: ethernet-phy@2 {
reg = <2>;
device_type = "ethernet-phy";
};
};
- fec@e00 {
+ ethernet@e00 {
device_type = "network";
- compatible = "fs_enet";
- model = "FEC";
- device-id = <1>;
+ compatible = "fsl,mpc885-fec-enet",
+ "fsl,pq1-fec-enet";
reg = <e00 188>;
- mac-address = [ 00 00 0C 00 01 FD ];
+ local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <3 1>;
- interrupt-parent = <&Mpc8xx_pic>;
- phy-handle = <&Phy1>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&PHY0>;
+ linux,network-index = <0>;
};
- fec@1e00 {
+ ethernet@1e00 {
device_type = "network";
- compatible = "fs_enet";
- model = "FEC";
- device-id = <2>;
+ compatible = "fsl,mpc885-fec-enet",
+ "fsl,pq1-fec-enet";
reg = <1e00 188>;
- mac-address = [ 00 00 0C 00 02 FD ];
+ local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <7 1>;
- interrupt-parent = <&Mpc8xx_pic>;
- phy-handle = <&Phy2>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&PHY1>;
+ linux,network-index = <1>;
};
- Mpc8xx_pic: pic@ff000000 {
+ PIC: interrupt-controller@0 {
interrupt-controller;
- #address-cells = <0>;
#interrupt-cells = <2>;
reg = <0 24>;
- built-in;
- device_type = "mpc8xx-pic";
- compatible = "CPM";
+ compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
};
- pcmcia@0080 {
+ pcmcia@80 {
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
compatible = "fsl,pq-pcmcia";
device_type = "pcmcia";
reg = <80 80>;
- interrupt-parent = <&Mpc8xx_pic>;
+ interrupt-parent = <&PIC>;
interrupts = <d 1>;
};
- cpm@ff000000 {
+ cpm@9c0 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
- device_type = "cpm";
- model = "CPM";
- ranges = <0 0 4000>;
- reg = <860 f0>;
+ compatible = "fsl,mpc885-cpm", "fsl,cpm1";
command-proc = <9c0>;
- brg-frequency = <0>;
- interrupts = <0 2>; // cpm error interrupt
- interrupt-parent = <&Cpm_pic>;
+ interrupts = <0>; // cpm error interrupt
+ interrupt-parent = <&CPM_PIC>;
+ reg = <9c0 40>;
+ ranges;
+
+ muram@2000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 2000 2000>;
- Cpm_pic: pic@930 {
+ data@0 {
+ compatible = "fsl,cpm-muram-data";
+ reg = <0 1c00>;
+ };
+ };
+
+ brg@9f0 {
+ compatible = "fsl,mpc885-brg",
+ "fsl,cpm1-brg",
+ "fsl,cpm-brg";
+ reg = <9f0 10>;
+ };
+
+ CPM_PIC: interrupt-controller@930 {
interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
+ #interrupt-cells = <1>;
interrupts = <5 2 0 2>;
- interrupt-parent = <&Mpc8xx_pic>;
+ interrupt-parent = <&PIC>;
reg = <930 20>;
- built-in;
- device_type = "cpm-pic";
- compatible = "CPM";
+ compatible = "fsl,mpc885-cpm-pic",
+ "fsl,cpm1-pic";
};
- smc@a80 {
+ serial@a80 {
device_type = "serial";
- compatible = "cpm_uart";
- model = "SMC";
- device-id = <1>;
+ compatible = "fsl,mpc885-smc-uart",
+ "fsl,cpm1-smc-uart";
reg = <a80 10 3e80 40>;
- clock-setup = <00ffffff 0>;
- rx-clock = <1>;
- tx-clock = <1>;
- current-speed = <0>;
- interrupts = <4 3>;
- interrupt-parent = <&Cpm_pic>;
+ interrupts = <4>;
+ interrupt-parent = <&CPM_PIC>;
+ fsl,cpm-brg = <1>;
+ fsl,cpm-command = <0090>;
};
- smc@a90 {
+ serial@a90 {
device_type = "serial";
- compatible = "cpm_uart";
- model = "SMC";
- device-id = <2>;
- reg = <a90 20 3f80 40>;
- clock-setup = <ff00ffff 90000>;
- rx-clock = <2>;
- tx-clock = <2>;
- current-speed = <0>;
- interrupts = <3 3>;
- interrupt-parent = <&Cpm_pic>;
+ compatible = "fsl,mpc885-smc-uart",
+ "fsl,cpm1-smc-uart";
+ reg = <a90 10 3f80 40>;
+ interrupts = <3>;
+ interrupt-parent = <&CPM_PIC>;
+ fsl,cpm-brg = <2>;
+ fsl,cpm-command = <00d0>;
};
- scc@a40 {
+ ethernet@a40 {
device_type = "network";
- compatible = "fs_enet";
- model = "SCC";
- device-id = <3>;
- reg = <a40 18 3e00 80>;
- mac-address = [ 00 00 0C 00 03 FD ];
- interrupts = <1c 3>;
- interrupt-parent = <&Cpm_pic>;
- phy-handle = <&Phy2>;
+ compatible = "fsl,mpc885-scc-enet",
+ "fsl,cpm1-scc-enet";
+ reg = <a40 18 3e00 100>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <1c>;
+ interrupt-parent = <&CPM_PIC>;
+ phy-handle = <&PHY2>;
+ fsl,cpm-command = <0080>;
+ linux,network-index = <2>;
};
};
};
+
+ chosen {
+ linux,stdout-path = "/soc/cpm/serial@a80";
+ };
};
diff --git a/arch/powerpc/boot/dts/pq2fads.dts b/arch/powerpc/boot/dts/pq2fads.dts
new file mode 100644
index 00000000000..2d564921897
--- /dev/null
+++ b/arch/powerpc/boot/dts/pq2fads.dts
@@ -0,0 +1,240 @@
+/*
+ * Device Tree for the PQ2FADS-ZU board with an MPC8280 chip.
+ *
+ * Copyright 2007 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/ {
+ model = "pq2fads";
+ compatible = "fsl,pq2fads";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <d#32>;
+ i-cache-line-size = <d#32>;
+ d-cache-size = <d#16384>;
+ i-cache-size = <d#16384>;
+ timebase-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0>;
+ };
+
+ localbus@f0010100 {
+ compatible = "fsl,mpc8280-localbus",
+ "fsl,pq2-localbus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <f0010100 60>;
+
+ ranges = <0 0 fe000000 00800000
+ 1 0 f4500000 00008000
+ 8 0 f8200000 00008000>;
+
+ flash@0,0 {
+ compatible = "jedec-flash";
+ reg = <0 0 800000>;
+ bank-width = <4>;
+ device-width = <1>;
+ };
+
+ bcsr@1,0 {
+ reg = <1 0 20>;
+ compatible = "fsl,pq2fads-bcsr";
+ };
+
+ PCI_PIC: pic@8,0 {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ reg = <8 0 8>;
+ compatible = "fsl,pq2ads-pci-pic";
+ interrupt-parent = <&PIC>;
+ interrupts = <18 8>;
+ };
+ };
+
+ pci@f0010800 {
+ device_type = "pci";
+ reg = <f0010800 10c f00101ac 8 f00101c4 8>;
+ compatible = "fsl,mpc8280-pci", "fsl,pq2-pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ clock-frequency = <d#66000000>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x16 */
+ b000 0 0 1 &PCI_PIC 0
+ b000 0 0 2 &PCI_PIC 1
+ b000 0 0 3 &PCI_PIC 2
+ b000 0 0 4 &PCI_PIC 3
+
+ /* IDSEL 0x17 */
+ b800 0 0 1 &PCI_PIC 4
+ b800 0 0 2 &PCI_PIC 5
+ b800 0 0 3 &PCI_PIC 6
+ b800 0 0 4 &PCI_PIC 7
+
+ /* IDSEL 0x18 */
+ c000 0 0 1 &PCI_PIC 8
+ c000 0 0 2 &PCI_PIC 9
+ c000 0 0 3 &PCI_PIC a
+ c000 0 0 4 &PCI_PIC b>;
+
+ interrupt-parent = <&PIC>;
+ interrupts = <12 8>;
+ ranges = <42000000 0 80000000 80000000 0 20000000
+ 02000000 0 a0000000 a0000000 0 20000000
+ 01000000 0 00000000 f6000000 0 02000000>;
+ };
+
+ soc@f0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,mpc8280", "fsl,pq2-soc";
+ ranges = <00000000 f0000000 00053000>;
+
+ // Temporary -- will go away once kernel uses ranges for get_immrbase().
+ reg = <f0000000 00053000>;
+
+ cpm@119c0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <2>;
+ compatible = "fsl,mpc8280-cpm", "fsl,cpm2";
+ reg = <119c0 30>;
+ ranges;
+
+ muram@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 10000>;
+
+ data@0 {
+ compatible = "fsl,cpm-muram-data";
+ reg = <0 2000 9800 800>;
+ };
+ };
+
+ brg@119f0 {
+ compatible = "fsl,mpc8280-brg",
+ "fsl,cpm2-brg",
+ "fsl,cpm-brg";
+ reg = <119f0 10 115f0 10>;
+ };
+
+ serial@11a00 {
+ device_type = "serial";
+ compatible = "fsl,mpc8280-scc-uart",
+ "fsl,cpm2-scc-uart";
+ reg = <11a00 20 8000 100>;
+ interrupts = <28 8>;
+ interrupt-parent = <&PIC>;
+ fsl,cpm-brg = <1>;
+ fsl,cpm-command = <00800000>;
+ };
+
+ serial@11a20 {
+ device_type = "serial";
+ compatible = "fsl,mpc8280-scc-uart",
+ "fsl,cpm2-scc-uart";
+ reg = <11a20 20 8100 100>;
+ interrupts = <29 8>;
+ interrupt-parent = <&PIC>;
+ fsl,cpm-brg = <2>;
+ fsl,cpm-command = <04a00000>;
+ };
+
+ ethernet@11320 {
+ device_type = "network";
+ compatible = "fsl,mpc8280-fcc-enet",
+ "fsl,cpm2-fcc-enet";
+ reg = <11320 20 8500 100 113b0 1>;
+ interrupts = <21 8>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&PHY0>;
+ linux,network-index = <0>;
+ fsl,cpm-command = <16200300>;
+ };
+
+ ethernet@11340 {
+ device_type = "network";
+ compatible = "fsl,mpc8280-fcc-enet",
+ "fsl,cpm2-fcc-enet";
+ reg = <11340 20 8600 100 113d0 1>;
+ interrupts = <22 8>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&PHY1>;
+ linux,network-index = <1>;
+ fsl,cpm-command = <1a400300>;
+ local-mac-address = [00 e0 0c 00 79 01];
+ };
+
+ mdio@10d40 {
+ device_type = "mdio";
+ compatible = "fsl,pq2fads-mdio-bitbang",
+ "fsl,mpc8280-mdio-bitbang",
+ "fsl,cpm2-mdio-bitbang";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <10d40 14>;
+ fsl,mdio-pin = <9>;
+ fsl,mdc-pin = <a>;
+
+ PHY0: ethernet-phy@0 {
+ interrupt-parent = <&PIC>;
+ interrupts = <19 2>;
+ reg = <0>;
+ device_type = "ethernet-phy";
+ };
+
+ PHY1: ethernet-phy@1 {
+ interrupt-parent = <&PIC>;
+ interrupts = <19 2>;
+ reg = <3>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ usb@11b60 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,mpc8280-usb",
+ "fsl,cpm2-usb";
+ reg = <11b60 18 8b00 100>;
+ interrupt-parent = <&PIC>;
+ interrupts = <b 8>;
+ fsl,cpm-command = <2e600000>;
+ };
+ };
+
+ PIC: interrupt-controller@10c00 {
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <10c00 80>;
+ compatible = "fsl,mpc8280-pic", "fsl,cpm2-pic";
+ };
+
+ };
+
+ chosen {
+ linux,stdout-path = "/soc/cpm/serial@11a00";
+ };
+};
diff --git a/arch/powerpc/boot/dts/prpmc2800.dts b/arch/powerpc/boot/dts/prpmc2800.dts
index 5300b50cdc2..297dfa53fe9 100644
--- a/arch/powerpc/boot/dts/prpmc2800.dts
+++ b/arch/powerpc/boot/dts/prpmc2800.dts
@@ -9,10 +9,6 @@
*
* Property values that are labeled as "Default" will be updated by bootwrapper
* if it can determine the exact PrPMC type.
- *
- * To build:
- * dtc -I dts -O asm -o prpmc2800.S -b 0 prpmc2800.dts
- * dtc -I dts -O dtb -o prpmc2800.dtb -b 0 prpmc2800.dts
*/
/ {
@@ -47,7 +43,6 @@
mv64x60@f1000000 { /* Marvell Discovery */
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <1>;
model = "mv64360"; /* Default */
compatible = "marvell,mv64x60";
clock-frequency = <7f28155>; /* 133.333333 MHz */
diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts
new file mode 100644
index 00000000000..36be75b04de
--- /dev/null
+++ b/arch/powerpc/boot/dts/sequoia.dts
@@ -0,0 +1,302 @@
+/*
+ * Device Tree Source for AMCC Sequoia
+ *
+ * Based on Bamboo code by Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ * Copyright (c) 2006, 2007 IBM Corp.
+ *
+ * FIXME: Draft only!
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ *
+ */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ model = "amcc,sequoia";
+ compatible = "amcc,sequoia";
+ dcr-parent = <&/cpus/PowerPC,440EPx@0>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,440EPx@0 {
+ device_type = "cpu";
+ reg = <0>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ timebase-frequency = <0>; /* Filled in by zImage */
+ i-cache-line-size = <20>;
+ d-cache-line-size = <20>;
+ i-cache-size = <8000>;
+ d-cache-size = <8000>;
+ dcr-controller;
+ dcr-access-method = "native";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0 0>; /* Filled in by zImage */
+ };
+
+ UIC0: interrupt-controller0 {
+ compatible = "ibm,uic-440epx","ibm,uic";
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0c0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ UIC1: interrupt-controller1 {
+ compatible = "ibm,uic-440epx","ibm,uic";
+ interrupt-controller;
+ cell-index = <1>;
+ dcr-reg = <0d0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <1e 4 1f 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC2: interrupt-controller2 {
+ compatible = "ibm,uic-440epx","ibm,uic";
+ interrupt-controller;
+ cell-index = <2>;
+ dcr-reg = <0e0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <1c 4 1d 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ SDR0: sdr {
+ compatible = "ibm,sdr-440epx", "ibm,sdr-440ep";
+ dcr-reg = <00e 002>;
+ };
+
+ CPR0: cpr {
+ compatible = "ibm,cpr-440epx", "ibm,cpr-440ep";
+ dcr-reg = <00c 002>;
+ };
+
+ plb {
+ compatible = "ibm,plb-440epx", "ibm,plb4";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ SDRAM0: sdram {
+ device_type = "memory-controller";
+ compatible = "ibm,sdram-440epx", "ibm,sdram-44x-ddr2denali";
+ dcr-reg = <010 2>;
+ };
+
+ DMA0: dma {
+ compatible = "ibm,dma-440epx", "ibm,dma-4xx";
+ dcr-reg = <100 027>;
+ };
+
+ MAL0: mcmal {
+ compatible = "ibm,mcmal-440epx", "ibm,mcmal2";
+ dcr-reg = <180 62>;
+ num-tx-chans = <2>;
+ num-rx-chans = <2>;
+ interrupt-parent = <&MAL0>;
+ interrupts = <0 1 2 3 4>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
+ /*RXEOB*/ 1 &UIC0 b 4
+ /*SERR*/ 2 &UIC1 0 4
+ /*TXDE*/ 3 &UIC1 1 4
+ /*RXDE*/ 4 &UIC1 2 4>;
+ interrupt-map-mask = <ffffffff>;
+ };
+
+ POB0: opb {
+ compatible = "ibm,opb-440epx", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <00000000 1 00000000 80000000
+ 80000000 1 80000000 80000000>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <7 4>;
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ EBC0: ebc {
+ compatible = "ibm,ebc-440epx", "ibm,ebc";
+ dcr-reg = <012 2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ interrupts = <5 1>;
+ interrupt-parent = <&UIC1>;
+
+ nor_flash@0,0 {
+ compatible = "amd,s29gl256n", "cfi-flash";
+ bank-width = <2>;
+ reg = <0 000000 4000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "Kernel";
+ reg = <0 180000>;
+ };
+ partition@180000 {
+ label = "ramdisk";
+ reg = <180000 200000>;
+ };
+ partition@380000 {
+ label = "file system";
+ reg = <380000 3aa0000>;
+ };
+ partition@3e20000 {
+ label = "kozio";
+ reg = <3e20000 140000>;
+ };
+ partition@3f60000 {
+ label = "env";
+ reg = <3f60000 40000>;
+ };
+ partition@3fa0000 {
+ label = "u-boot";
+ reg = <3fa0000 60000>;
+ };
+ };
+
+ };
+
+ UART0: serial@ef600300 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600300 8>;
+ virtual-reg = <ef600300>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ current-speed = <1c200>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0 4>;
+ };
+
+ UART1: serial@ef600400 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600400 8>;
+ virtual-reg = <ef600400>;
+ clock-frequency = <0>;
+ current-speed = <0>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <1 4>;
+ };
+
+ UART2: serial@ef600500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600500 8>;
+ virtual-reg = <ef600500>;
+ clock-frequency = <0>;
+ current-speed = <0>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <3 4>;
+ };
+
+ UART3: serial@ef600600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600600 8>;
+ virtual-reg = <ef600600>;
+ clock-frequency = <0>;
+ current-speed = <0>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <4 4>;
+ };
+
+ IIC0: i2c@ef600700 {
+ device_type = "i2c";
+ compatible = "ibm,iic-440epx", "ibm,iic";
+ reg = <ef600700 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <2 4>;
+ };
+
+ IIC1: i2c@ef600800 {
+ device_type = "i2c";
+ compatible = "ibm,iic-440epx", "ibm,iic";
+ reg = <ef600800 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <7 4>;
+ };
+
+ ZMII0: emac-zmii@ef600d00 {
+ device_type = "zmii-interface";
+ compatible = "ibm,zmii-440epx", "ibm,zmii";
+ reg = <ef600d00 c>;
+ };
+
+ EMAC0: ethernet@ef600e00 {
+ linux,network-index = <0>;
+ device_type = "network";
+ compatible = "ibm,emac-440epx", "ibm,emac4";
+ interrupt-parent = <&EMAC0>;
+ interrupts = <0 1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0 &UIC0 18 4
+ /*Wake*/ 1 &UIC1 1d 4>;
+ reg = <ef600e00 70>;
+ local-mac-address = [000000000000];
+ mal-device = <&MAL0>;
+ mal-tx-channel = <0>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rmii";
+ phy-map = <00000000>;
+ zmii-device = <&ZMII0>;
+ zmii-channel = <0>;
+ };
+
+ EMAC1: ethernet@ef600f00 {
+ linux,network-index = <1>;
+ device_type = "network";
+ compatible = "ibm,emac-440epx", "ibm,emac4";
+ interrupt-parent = <&EMAC1>;
+ interrupts = <0 1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0 &UIC0 19 4
+ /*Wake*/ 1 &UIC1 1f 4>;
+ reg = <ef600f00 70>;
+ local-mac-address = [000000000000];
+ mal-device = <&MAL0>;
+ mal-tx-channel = <1>;
+ mal-rx-channel = <1>;
+ cell-index = <1>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rmii";
+ phy-map = <00000000>;
+ zmii-device = <&ZMII0>;
+ zmii-channel = <1>;
+ };
+ };
+ };
+
+ chosen {
+ linux,stdout-path = "/plb/opb/serial@ef600300";
+ bootargs = "console=ttyS0,115200";
+ };
+};
diff --git a/arch/powerpc/boot/dts/walnut.dts b/arch/powerpc/boot/dts/walnut.dts
new file mode 100644
index 00000000000..ec54f4e04ad
--- /dev/null
+++ b/arch/powerpc/boot/dts/walnut.dts
@@ -0,0 +1,190 @@
+/*
+ * Device Tree Source for IBM Walnut
+ *
+ * Copyright 2007 IBM Corp.
+ * Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "ibm,walnut";
+ compatible = "ibm,walnut";
+ dcr-parent = <&/cpus/PowerPC,405GP@0>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,405GP@0 {
+ device_type = "cpu";
+ reg = <0>;
+ clock-frequency = <bebc200>; /* Filled in by zImage */
+ timebase-frequency = <0>; /* Filled in by zImage */
+ i-cache-line-size = <20>;
+ d-cache-line-size = <20>;
+ i-cache-size = <4000>;
+ d-cache-size = <4000>;
+ dcr-controller;
+ dcr-access-method = "native";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0>; /* Filled in by zImage */
+ };
+
+ UIC0: interrupt-controller {
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0c0 9>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ plb {
+ compatible = "ibm,plb3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ SDRAM0: memory-controller {
+ compatible = "ibm,sdram-405gp";
+ dcr-reg = <010 2>;
+ };
+
+ MAL: mcmal {
+ compatible = "ibm,mcmal-405gp", "ibm,mcmal";
+ dcr-reg = <180 62>;
+ num-tx-chans = <2>;
+ num-rx-chans = <1>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <a 4 b 4 c 4 d 4 e 4>;
+ };
+
+ POB0: opb {
+ compatible = "ibm,opb-405gp", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <ef600000 ef600000 a00000>;
+ dcr-reg = <0a0 5>;
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ UART0: serial@ef600300 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600300 8>;
+ virtual-reg = <ef600300>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ current-speed = <2580>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0 4>;
+ };
+
+ UART1: serial@ef600400 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600400 8>;
+ virtual-reg = <ef600400>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ current-speed = <2580>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <1 4>;
+ };
+
+ IIC: i2c@ef600500 {
+ compatible = "ibm,iic-405gp", "ibm,iic";
+ reg = <ef600500 11>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <2 4>;
+ };
+
+ GPIO: gpio@ef600700 {
+ compatible = "ibm,gpio-405gp";
+ reg = <ef600700 20>;
+ };
+
+ EMAC: ethernet@ef600800 {
+ linux,network-index = <0>;
+ device_type = "network";
+ compatible = "ibm,emac-405gp", "ibm,emac";
+ interrupt-parent = <&UIC0>;
+ interrupts = <9 4 f 4>;
+ reg = <ef600800 70>;
+ mal-device = <&MAL>;
+ mal-tx-channel = <0 1>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rmii";
+ phy-map = <00000001>;
+ };
+
+ };
+
+ EBC0: ebc {
+ compatible = "ibm,ebc-405gp", "ibm,ebc";
+ dcr-reg = <012 2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* The ranges property is supplied by the bootwrapper
+ * and is based on the firmware's configuration of the
+ * EBC bridge
+ */
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ sram@0,0 {
+ reg = <0 0 80000>;
+ };
+
+ flash@0,80000 {
+ compatible = "jedec-flash";
+ bank-width = <1>;
+ reg = <0 80000 80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "OpenBIOS";
+ reg = <0 80000>;
+ read-only;
+ };
+ };
+
+ ds1743@1,0 {
+ /* NVRAM and RTC */
+ compatible = "ds1743";
+ reg = <1 0 2000>;
+ };
+
+ keyboard@2,0 {
+ compatible = "intel,82C42PC";
+ reg = <2 0 2>;
+ };
+
+ ir@3,0 {
+ compatible = "ti,TIR2000PAG";
+ reg = <3 0 10>;
+ };
+
+ fpga@7,0 {
+ compatible = "Walnut-FPGA";
+ reg = <7 0 10>;
+ virtual-reg = <f0300005>;
+ };
+ };
+ };
+
+ chosen {
+ linux,stdout-path = "/plb/opb/serial@ef600300";
+ };
+};
diff --git a/arch/powerpc/boot/ebony.c b/arch/powerpc/boot/ebony.c
index 75daedafd0a..86c0f5df0a8 100644
--- a/arch/powerpc/boot/ebony.c
+++ b/arch/powerpc/boot/ebony.c
@@ -24,12 +24,11 @@
#include "page.h"
#include "ops.h"
#include "reg.h"
+#include "io.h"
#include "dcr.h"
+#include "4xx.h"
#include "44x.h"
-extern char _dtb_start[];
-extern char _dtb_end[];
-
static u8 *ebony_mac0, *ebony_mac1;
/* Calculate 440GP clocks */
@@ -92,15 +91,53 @@ void ibm440gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
dt_fixup_clock("/plb/opb/serial@40000300", uart1);
}
+#define EBONY_FPGA_PATH "/plb/opb/ebc/fpga"
+#define EBONY_FPGA_FLASH_SEL 0x01
+#define EBONY_SMALL_FLASH_PATH "/plb/opb/ebc/small-flash"
+
+static void ebony_flashsel_fixup(void)
+{
+ void *devp;
+ u32 reg[3] = {0x0, 0x0, 0x80000};
+ u8 *fpga;
+ u8 fpga_reg0 = 0x0;
+
+ devp = finddevice(EBONY_FPGA_PATH);
+ if (!devp)
+ fatal("Couldn't locate FPGA node %s\n\r", EBONY_FPGA_PATH);
+
+ if (getprop(devp, "virtual-reg", &fpga, sizeof(fpga)) != sizeof(fpga))
+ fatal("%s has missing or invalid virtual-reg property\n\r",
+ EBONY_FPGA_PATH);
+
+ fpga_reg0 = in_8(fpga);
+
+ devp = finddevice(EBONY_SMALL_FLASH_PATH);
+ if (!devp)
+ fatal("Couldn't locate small flash node %s\n\r",
+ EBONY_SMALL_FLASH_PATH);
+
+ if (getprop(devp, "reg", reg, sizeof(reg)) != sizeof(reg))
+ fatal("%s has reg property of unexpected size\n\r",
+ EBONY_SMALL_FLASH_PATH);
+
+ /* Invert address bit 14 (IBM-endian) if FLASH_SEL fpga bit is set */
+ if (fpga_reg0 & EBONY_FPGA_FLASH_SEL)
+ reg[1] ^= 0x80000;
+
+ setprop(devp, "reg", reg, sizeof(reg));
+}
+
static void ebony_fixups(void)
{
// FIXME: sysclk should be derived by reading the FPGA registers
unsigned long sysclk = 33000000;
ibm440gp_fixup_clocks(sysclk, 6 * 1843200);
- ibm44x_fixup_memsize();
+ ibm4xx_fixup_memsize();
dt_fixup_mac_addresses(ebony_mac0, ebony_mac1);
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
+ ebony_flashsel_fixup();
}
void ebony_init(void *mac0, void *mac1)
diff --git a/arch/powerpc/boot/ep88xc.c b/arch/powerpc/boot/ep88xc.c
new file mode 100644
index 00000000000..6b87cdce3fe
--- /dev/null
+++ b/arch/powerpc/boot/ep88xc.c
@@ -0,0 +1,54 @@
+/*
+ * Embedded Planet EP88xC with PlanetCore firmware
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "stdio.h"
+#include "planetcore.h"
+#include "mpc8xx.h"
+
+static char *table;
+static u64 mem_size;
+
+static void platform_fixups(void)
+{
+ u64 val;
+
+ dt_fixup_memory(0, mem_size);
+ planetcore_set_mac_addrs(table);
+
+ if (!planetcore_get_decimal(table, PLANETCORE_KEY_CRYSTAL_HZ, &val)) {
+ printf("No PlanetCore crystal frequency key.\r\n");
+ return;
+ }
+
+ mpc885_fixup_clocks(val);
+}
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ table = (char *)r3;
+ planetcore_prepare_table(table);
+
+ if (!planetcore_get_decimal(table, PLANETCORE_KEY_MB_RAM, &mem_size))
+ return;
+
+ mem_size *= 1024 * 1024;
+ simple_alloc_init(_end, mem_size - (unsigned long)_end, 32, 64);
+
+ ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
+
+ planetcore_set_stdout_path(table);
+
+ serial_console_init();
+ platform_ops.fixups = platform_fixups;
+}
diff --git a/arch/powerpc/boot/fixed-head.S b/arch/powerpc/boot/fixed-head.S
new file mode 100644
index 00000000000..8e14cd9e1a5
--- /dev/null
+++ b/arch/powerpc/boot/fixed-head.S
@@ -0,0 +1,4 @@
+ .text
+ .global _zimage_start
+_zimage_start:
+ b _zimage_start_lib
diff --git a/arch/powerpc/boot/flatdevtree.c b/arch/powerpc/boot/flatdevtree.c
index 13761bf160c..cf30675c611 100644
--- a/arch/powerpc/boot/flatdevtree.c
+++ b/arch/powerpc/boot/flatdevtree.c
@@ -354,16 +354,21 @@ static void ft_put_bin(struct ft_cxt *cxt, const void *data, unsigned int sz)
cxt->p += sza;
}
-int ft_begin_node(struct ft_cxt *cxt, const char *name)
+char *ft_begin_node(struct ft_cxt *cxt, const char *name)
{
unsigned long nlen = strlen(name) + 1;
unsigned long len = 8 + _ALIGN(nlen, 4);
+ char *ret;
if (!ft_make_space(cxt, &cxt->p, FT_STRUCT, len))
- return -1;
+ return NULL;
+
+ ret = cxt->p;
+
ft_put_word(cxt, OF_DT_BEGIN_NODE);
ft_put_bin(cxt, name, strlen(name) + 1);
- return 0;
+
+ return ret;
}
void ft_end_node(struct ft_cxt *cxt)
@@ -625,25 +630,17 @@ void ft_end_tree(struct ft_cxt *cxt)
bph->dt_strings_size = cpu_to_be32(ssize);
}
-void *ft_find_device(struct ft_cxt *cxt, const char *srch_path)
-{
- char *node;
-
- /* require absolute path */
- if (srch_path[0] != '/')
- return NULL;
- node = ft_find_descendent(cxt, ft_root_node(cxt), srch_path);
- return ft_get_phandle(cxt, node);
-}
-
-void *ft_find_device_rel(struct ft_cxt *cxt, const void *top,
- const char *srch_path)
+void *ft_find_device(struct ft_cxt *cxt, const void *top, const char *srch_path)
{
char *node;
- node = ft_node_ph2node(cxt, top);
- if (node == NULL)
- return NULL;
+ if (top) {
+ node = ft_node_ph2node(cxt, top);
+ if (node == NULL)
+ return NULL;
+ } else {
+ node = ft_root_node(cxt);
+ }
node = ft_find_descendent(cxt, node, srch_path);
return ft_get_phandle(cxt, node);
@@ -945,7 +942,7 @@ int ft_del_prop(struct ft_cxt *cxt, const void *phandle, const char *propname)
void *ft_create_node(struct ft_cxt *cxt, const void *parent, const char *name)
{
struct ft_atom atom;
- char *p, *next;
+ char *p, *next, *ret;
int depth = 0;
if (parent) {
@@ -970,11 +967,70 @@ void *ft_create_node(struct ft_cxt *cxt, const void *parent, const char *name)
break;
/* end of node, insert here */
cxt->p = p;
- ft_begin_node(cxt, name);
+ ret = ft_begin_node(cxt, name);
ft_end_node(cxt);
- return p;
+ return ft_get_phandle(cxt, ret);
}
p = next;
}
return NULL;
}
+
+/* Returns the start of the path within the provided buffer, or NULL on
+ * error.
+ */
+char *ft_get_path(struct ft_cxt *cxt, const void *phandle,
+ char *buf, int len)
+{
+ const char *path_comp[FT_MAX_DEPTH];
+ struct ft_atom atom;
+ char *p, *next, *pos;
+ int depth = 0, i;
+ void *node;
+
+ node = ft_node_ph2node(cxt, phandle);
+ if (node == NULL)
+ return NULL;
+
+ p = ft_root_node(cxt);
+
+ while ((next = ft_next(cxt, p, &atom)) != NULL) {
+ switch (atom.tag) {
+ case OF_DT_BEGIN_NODE:
+ path_comp[depth++] = atom.name;
+ if (p == node)
+ goto found;
+
+ break;
+
+ case OF_DT_END_NODE:
+ if (--depth == 0)
+ return NULL;
+ }
+
+ p = next;
+ }
+
+found:
+ pos = buf;
+ for (i = 1; i < depth; i++) {
+ int this_len;
+
+ if (len <= 1)
+ return NULL;
+
+ *pos++ = '/';
+ len--;
+
+ strncpy(pos, path_comp[i], len);
+
+ if (pos[len - 1] != 0)
+ return NULL;
+
+ this_len = strlen(pos);
+ len -= this_len;
+ pos += this_len;
+ }
+
+ return buf;
+}
diff --git a/arch/powerpc/boot/flatdevtree.h b/arch/powerpc/boot/flatdevtree.h
index cb26325d72d..b0957a2d967 100644
--- a/arch/powerpc/boot/flatdevtree.h
+++ b/arch/powerpc/boot/flatdevtree.h
@@ -76,7 +76,7 @@ struct ft_cxt {
unsigned int nodes_used;
};
-int ft_begin_node(struct ft_cxt *cxt, const char *name);
+char *ft_begin_node(struct ft_cxt *cxt, const char *name);
void ft_end_node(struct ft_cxt *cxt);
void ft_begin_tree(struct ft_cxt *cxt);
@@ -96,9 +96,8 @@ int ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size);
void ft_dump_blob(const void *bphp);
void ft_merge_blob(struct ft_cxt *cxt, void *blob);
-void *ft_find_device(struct ft_cxt *cxt, const char *srch_path);
-void *ft_find_device_rel(struct ft_cxt *cxt, const void *top,
- const char *srch_path);
+void *ft_find_device(struct ft_cxt *cxt, const void *top,
+ const char *srch_path);
void *ft_find_descendent(struct ft_cxt *cxt, void *top, const char *srch_path);
int ft_get_prop(struct ft_cxt *cxt, const void *phandle, const char *propname,
void *buf, const unsigned int buflen);
@@ -109,5 +108,6 @@ void *ft_find_node_by_prop_value(struct ft_cxt *cxt, const void *prev,
const char *propname, const char *propval,
int proplen);
void *ft_create_node(struct ft_cxt *cxt, const void *parent, const char *name);
+char *ft_get_path(struct ft_cxt *cxt, const void *phandle, char *buf, int len);
#endif /* FLATDEVTREE_H */
diff --git a/arch/powerpc/boot/flatdevtree_env.h b/arch/powerpc/boot/flatdevtree_env.h
index 83bc1c71883..ad0420da892 100644
--- a/arch/powerpc/boot/flatdevtree_env.h
+++ b/arch/powerpc/boot/flatdevtree_env.h
@@ -24,24 +24,4 @@
#define be64_to_cpu(x) (x)
#define cpu_to_be64(x) (x)
-static inline int strncmp(const char *cs, const char *ct, size_t count)
-{
- signed char __res = 0;
-
- while (count) {
- if ((__res = *cs - *ct++) != 0 || !*cs++)
- break;
- count--;
- }
- return __res;
-}
-
-static inline char *strchr(const char *s, int c)
-{
- for (; *s != (char)c; ++s)
- if (*s == '\0')
- return NULL;
- return (char *)s;
-}
-
#endif /* _PPC_BOOT_FLATDEVTREE_ENV_H_ */
diff --git a/arch/powerpc/boot/flatdevtree_misc.c b/arch/powerpc/boot/flatdevtree_misc.c
index 4341e6558c1..b3670096fa7 100644
--- a/arch/powerpc/boot/flatdevtree_misc.c
+++ b/arch/powerpc/boot/flatdevtree_misc.c
@@ -18,7 +18,7 @@ static struct ft_cxt cxt;
static void *fdtm_finddevice(const char *name)
{
- return ft_find_device(&cxt, name);
+ return ft_find_device(&cxt, NULL, name);
}
static int fdtm_getprop(const void *phandle, const char *propname,
@@ -58,6 +58,11 @@ static unsigned long fdtm_finalize(void)
return (unsigned long)cxt.bph;
}
+static char *fdtm_get_path(const void *phandle, char *buf, int len)
+{
+ return ft_get_path(&cxt, phandle, buf, len);
+}
+
int ft_init(void *dt_blob, unsigned int max_size, unsigned int max_find_device)
{
dt_ops.finddevice = fdtm_finddevice;
@@ -67,6 +72,7 @@ int ft_init(void *dt_blob, unsigned int max_size, unsigned int max_find_device)
dt_ops.create_node = fdtm_create_node;
dt_ops.find_node_by_prop_value = fdtm_find_node_by_prop_value;
dt_ops.finalize = fdtm_finalize;
+ dt_ops.get_path = fdtm_get_path;
return ft_open(&cxt, dt_blob, max_size, max_find_device,
platform_ops.realloc);
diff --git a/arch/powerpc/boot/fsl-soc.c b/arch/powerpc/boot/fsl-soc.c
new file mode 100644
index 00000000000..b835ed69e1a
--- /dev/null
+++ b/arch/powerpc/boot/fsl-soc.c
@@ -0,0 +1,57 @@
+/*
+ * Freescale SOC support functions
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "types.h"
+#include "fsl-soc.h"
+#include "stdio.h"
+
+static u32 prop_buf[MAX_PROP_LEN / 4];
+
+u32 *fsl_get_immr(void)
+{
+ void *soc;
+ unsigned long ret = 0;
+
+ soc = find_node_by_devtype(NULL, "soc");
+ if (soc) {
+ int size;
+ u32 naddr;
+
+ size = getprop(soc, "#address-cells", prop_buf, MAX_PROP_LEN);
+ if (size == 4)
+ naddr = prop_buf[0];
+ else
+ naddr = 2;
+
+ if (naddr != 1 && naddr != 2)
+ goto err;
+
+ size = getprop(soc, "ranges", prop_buf, MAX_PROP_LEN);
+
+ if (size < 12)
+ goto err;
+ if (prop_buf[0] != 0)
+ goto err;
+ if (naddr == 2 && prop_buf[1] != 0)
+ goto err;
+
+ if (!dt_xlate_addr(soc, prop_buf + naddr, 8, &ret))
+ ret = 0;
+ }
+
+err:
+ if (!ret)
+ printf("fsl_get_immr: Failed to find immr base\r\n");
+
+ return (u32 *)ret;
+}
diff --git a/arch/powerpc/boot/fsl-soc.h b/arch/powerpc/boot/fsl-soc.h
new file mode 100644
index 00000000000..5da26fc6e3c
--- /dev/null
+++ b/arch/powerpc/boot/fsl-soc.h
@@ -0,0 +1,8 @@
+#ifndef _PPC_BOOT_FSL_SOC_H_
+#define _PPC_BOOT_FSL_SOC_H_
+
+#include "types.h"
+
+u32 *fsl_get_immr(void);
+
+#endif
diff --git a/arch/powerpc/boot/gunzip_util.c b/arch/powerpc/boot/gunzip_util.c
index df8ab07e9ff..ef2aed0f63c 100644
--- a/arch/powerpc/boot/gunzip_util.c
+++ b/arch/powerpc/boot/gunzip_util.c
@@ -78,6 +78,7 @@ void gunzip_start(struct gunzip_state *state, void *src, int srclen)
fatal("inflateInit2 returned %d\n\r", r);
}
+ state->s.total_in = hdrlen;
state->s.next_in = src + hdrlen;
state->s.avail_in = srclen - hdrlen;
}
@@ -193,13 +194,10 @@ int gunzip_finish(struct gunzip_state *state, void *dst, int dstlen)
{
int len;
+ len = gunzip_partial(state, dst, dstlen);
+
if (state->s.workspace) {
- len = gunzip_partial(state, dst, dstlen);
zlib_inflateEnd(&state->s);
- } else {
- /* uncompressed image */
- len = min(state->s.avail_in, (unsigned)dstlen);
- memcpy(dst, state->s.next_in, len);
}
return len;
diff --git a/arch/powerpc/boot/holly.c b/arch/powerpc/boot/holly.c
index 7d6539f5e22..199e783aea4 100644
--- a/arch/powerpc/boot/holly.c
+++ b/arch/powerpc/boot/holly.c
@@ -21,11 +21,6 @@
#include "ops.h"
#include "io.h"
-extern char _start[];
-extern char _end[];
-extern char _dtb_start[];
-extern char _dtb_end[];
-
BSS_STACK(4096);
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5)
diff --git a/arch/powerpc/boot/io.h b/arch/powerpc/boot/io.h
index 32974ed49e0..ccaedaec50d 100644
--- a/arch/powerpc/boot/io.h
+++ b/arch/powerpc/boot/io.h
@@ -1,5 +1,8 @@
#ifndef _IO_H
#define __IO_H
+
+#include "types.h"
+
/*
* Low-level I/O routines.
*
@@ -20,6 +23,37 @@ static inline void out_8(volatile unsigned char *addr, int val)
: "=m" (*addr) : "r" (val));
}
+static inline unsigned in_le16(const volatile u16 *addr)
+{
+ unsigned ret;
+
+ __asm__ __volatile__("lhbrx %0,0,%1; twi 0,%0,0; isync"
+ : "=r" (ret) : "r" (addr), "m" (*addr));
+
+ return ret;
+}
+
+static inline unsigned in_be16(const volatile u16 *addr)
+{
+ unsigned ret;
+
+ __asm__ __volatile__("lhz%U1%X1 %0,%1; twi 0,%0,0; isync"
+ : "=r" (ret) : "m" (*addr));
+ return ret;
+}
+
+static inline void out_le16(volatile u16 *addr, int val)
+{
+ __asm__ __volatile__("sthbrx %1,0,%2; sync" : "=m" (*addr)
+ : "r" (val), "r" (addr));
+}
+
+static inline void out_be16(volatile u16 *addr, int val)
+{
+ __asm__ __volatile__("sth%U0%X0 %1,%0; sync"
+ : "=m" (*addr) : "r" (val));
+}
+
static inline unsigned in_le32(const volatile unsigned *addr)
{
unsigned ret;
@@ -50,4 +84,19 @@ static inline void out_be32(volatile unsigned *addr, int val)
: "=m" (*addr) : "r" (val));
}
+static inline void sync(void)
+{
+ asm volatile("sync" : : : "memory");
+}
+
+static inline void eieio(void)
+{
+ asm volatile("eieio" : : : "memory");
+}
+
+static inline void barrier(void)
+{
+ asm volatile("" : : : "memory");
+}
+
#endif /* _IO_H */
diff --git a/arch/powerpc/boot/main.c b/arch/powerpc/boot/main.c
index 416dc3857bf..1b496b37eca 100644
--- a/arch/powerpc/boot/main.c
+++ b/arch/powerpc/boot/main.c
@@ -19,16 +19,6 @@
#include "flatdevtree.h"
#include "reg.h"
-extern char _start[];
-extern char __bss_start[];
-extern char _end[];
-extern char _vmlinux_start[];
-extern char _vmlinux_end[];
-extern char _initrd_start[];
-extern char _initrd_end[];
-extern char _dtb_start[];
-extern char _dtb_end[];
-
static struct gunzip_state gzstate;
struct addr_range {
diff --git a/arch/powerpc/boot/mpc52xx-psc.c b/arch/powerpc/boot/mpc52xx-psc.c
new file mode 100644
index 00000000000..1074626e6a3
--- /dev/null
+++ b/arch/powerpc/boot/mpc52xx-psc.c
@@ -0,0 +1,69 @@
+/*
+ * MPC5200 PSC serial console support.
+ *
+ * Author: Grant Likely <grant.likely@secretlab.ca>
+ *
+ * Copyright (c) 2007 Secret Lab Technologies Ltd.
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ *
+ * It is assumed that the firmware (or the platform file) has already set
+ * up the port.
+ */
+
+#include "types.h"
+#include "io.h"
+#include "ops.h"
+
+/* Programmable Serial Controller (PSC) status register bits */
+#define MPC52xx_PSC_SR 0x04
+#define MPC52xx_PSC_SR_RXRDY 0x0100
+#define MPC52xx_PSC_SR_RXFULL 0x0200
+#define MPC52xx_PSC_SR_TXRDY 0x0400
+#define MPC52xx_PSC_SR_TXEMP 0x0800
+
+#define MPC52xx_PSC_BUFFER 0x0C
+
+static void *psc;
+
+static int psc_open(void)
+{
+ /* Assume the firmware has already configured the PSC into
+ * uart mode */
+ return 0;
+}
+
+static void psc_putc(unsigned char c)
+{
+ while (!(in_be16(psc + MPC52xx_PSC_SR) & MPC52xx_PSC_SR_TXRDY)) ;
+ out_8(psc + MPC52xx_PSC_BUFFER, c);
+}
+
+static unsigned char psc_tstc(void)
+{
+ return (in_be16(psc + MPC52xx_PSC_SR) & MPC52xx_PSC_SR_RXRDY) != 0;
+}
+
+static unsigned char psc_getc(void)
+{
+ while (!(in_be16(psc + MPC52xx_PSC_SR) & MPC52xx_PSC_SR_RXRDY)) ;
+ return in_8(psc + MPC52xx_PSC_BUFFER);
+}
+
+int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp)
+{
+ int n;
+
+ /* Get the base address of the psc registers */
+ n = getprop(devp, "virtual-reg", &psc, sizeof(psc));
+ if (n != sizeof(psc)) {
+ if (!dt_xlate_reg(devp, 0, (void *)&psc, NULL))
+ return -1;
+ }
+
+ scdp->open = psc_open;
+ scdp->putc = psc_putc;
+ scdp->getc = psc_getc;
+ scdp->tstc = psc_tstc;
+
+ return 0;
+}
diff --git a/arch/powerpc/boot/mpc8xx.c b/arch/powerpc/boot/mpc8xx.c
new file mode 100644
index 00000000000..add55a7f184
--- /dev/null
+++ b/arch/powerpc/boot/mpc8xx.c
@@ -0,0 +1,82 @@
+/*
+ * MPC8xx support functions
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "types.h"
+#include "fsl-soc.h"
+#include "mpc8xx.h"
+#include "stdio.h"
+#include "io.h"
+
+#define MPC8XX_PLPRCR (0x284/4) /* PLL and Reset Control Register */
+
+/* Return system clock from crystal frequency */
+u32 mpc885_get_clock(u32 crystal)
+{
+ u32 *immr;
+ u32 plprcr;
+ int mfi, mfn, mfd, pdf, div;
+ u32 ret;
+
+ immr = fsl_get_immr();
+ if (!immr) {
+ printf("mpc885_get_clock: Couldn't get IMMR base.\r\n");
+ return 0;
+ }
+
+ plprcr = in_be32(&immr[MPC8XX_PLPRCR]);
+
+ mfi = (plprcr >> 16) & 15;
+ if (mfi < 5) {
+ printf("Warning: PLPRCR[MFI] value of %d out-of-bounds\r\n",
+ mfi);
+ mfi = 5;
+ }
+
+ pdf = (plprcr >> 1) & 0xf;
+ div = (plprcr >> 20) & 3;
+ mfd = (plprcr >> 22) & 0x1f;
+ mfn = (plprcr >> 27) & 0x1f;
+
+ ret = crystal * mfi;
+
+ if (mfn != 0)
+ ret += crystal * mfn / (mfd + 1);
+
+ return ret / (pdf + 1);
+}
+
+/* Set common device tree fields based on the given clock frequencies. */
+void mpc8xx_set_clocks(u32 sysclk)
+{
+ void *node;
+
+ dt_fixup_cpu_clocks(sysclk, sysclk / 16, sysclk);
+
+ node = finddevice("/soc/cpm");
+ if (node)
+ setprop(node, "clock-frequency", &sysclk, 4);
+
+ node = finddevice("/soc/cpm/brg");
+ if (node)
+ setprop(node, "clock-frequency", &sysclk, 4);
+}
+
+int mpc885_fixup_clocks(u32 crystal)
+{
+ u32 sysclk = mpc885_get_clock(crystal);
+ if (!sysclk)
+ return 0;
+
+ mpc8xx_set_clocks(sysclk);
+ return 1;
+}
diff --git a/arch/powerpc/boot/mpc8xx.h b/arch/powerpc/boot/mpc8xx.h
new file mode 100644
index 00000000000..3f59901ab1c
--- /dev/null
+++ b/arch/powerpc/boot/mpc8xx.h
@@ -0,0 +1,11 @@
+#ifndef _PPC_BOOT_MPC8xx_H_
+#define _PPC_BOOT_MPC8xx_H_
+
+#include "types.h"
+
+void mpc8xx_set_clocks(u32 sysclk);
+
+u32 mpc885_get_clock(u32 crystal);
+int mpc885_fixup_clocks(u32 crystal);
+
+#endif
diff --git a/arch/powerpc/boot/mpsc.c b/arch/powerpc/boot/mpsc.c
index f1c0e965e5c..802ea53790d 100644
--- a/arch/powerpc/boot/mpsc.c
+++ b/arch/powerpc/boot/mpsc.c
@@ -17,7 +17,6 @@
#include "io.h"
#include "ops.h"
-extern void udelay(long delay);
#define MPSC_CHR_1 0x000c
diff --git a/arch/powerpc/boot/mv64x60_i2c.c b/arch/powerpc/boot/mv64x60_i2c.c
index 435fe852868..d085377be3b 100644
--- a/arch/powerpc/boot/mv64x60_i2c.c
+++ b/arch/powerpc/boot/mv64x60_i2c.c
@@ -21,8 +21,6 @@
#include "ops.h"
#include "mv64x60.h"
-extern void udelay(long);
-
/* Register defines */
#define MV64x60_I2C_REG_SLAVE_ADDR 0x00
#define MV64x60_I2C_REG_DATA 0x04
diff --git a/arch/powerpc/boot/of.c b/arch/powerpc/boot/of.c
index 385e08b83b7..61d9899aa0d 100644
--- a/arch/powerpc/boot/of.c
+++ b/arch/powerpc/boot/of.c
@@ -17,8 +17,6 @@
#include "of.h"
-extern char _end[];
-
/* Value picked to match that used by yaboot */
#define PROG_START 0x01400000 /* only used on 64-bit systems */
#define RAM_END (512<<20) /* Fixme: use OF */
diff --git a/arch/powerpc/boot/ops.h b/arch/powerpc/boot/ops.h
index 86077066cd7..a180b6505f4 100644
--- a/arch/powerpc/boot/ops.h
+++ b/arch/powerpc/boot/ops.h
@@ -47,6 +47,7 @@ struct dt_ops {
const char *propname,
const char *propval, int proplen);
unsigned long (*finalize)(void);
+ char *(*get_path)(const void *phandle, char *buf, int len);
};
extern struct dt_ops dt_ops;
@@ -82,11 +83,16 @@ int ft_init(void *dt_blob, unsigned int max_size, unsigned int max_find_device);
int serial_console_init(void);
int ns16550_console_init(void *devp, struct serial_console_data *scdp);
int mpsc_console_init(void *devp, struct serial_console_data *scdp);
+int cpm_console_init(void *devp, struct serial_console_data *scdp);
+int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp);
+int uartlite_console_init(void *devp, struct serial_console_data *scdp);
void *simple_alloc_init(char *base, unsigned long heap_size,
unsigned long granularity, unsigned long max_allocs);
extern void flush_cache(void *, unsigned long);
int dt_xlate_reg(void *node, int res, unsigned long *addr, unsigned long *size);
int dt_xlate_addr(void *node, u32 *buf, int buflen, unsigned long *xlated_addr);
+int dt_is_compatible(void *node, const char *compat);
+void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize);
static inline void *finddevice(const char *name)
{
@@ -156,6 +162,7 @@ static inline void *find_node_by_devtype(const void *prev,
void dt_fixup_memory(u64 start, u64 size);
void dt_fixup_cpu_clocks(u32 cpufreq, u32 tbfreq, u32 busfreq);
void dt_fixup_clock(const char *path, u32 freq);
+void dt_fixup_mac_address(u32 index, const u8 *addr);
void __dt_fixup_mac_addresses(u32 startindex, ...);
#define dt_fixup_mac_addresses(...) \
__dt_fixup_mac_addresses(0, __VA_ARGS__, NULL)
@@ -167,6 +174,14 @@ static inline void *find_node_by_linuxphandle(const u32 linuxphandle)
(char *)&linuxphandle, sizeof(u32));
}
+static inline char *get_path(const void *phandle, char *buf, int len)
+{
+ if (dt_ops.get_path)
+ return dt_ops.get_path(phandle, buf, len);
+
+ return NULL;
+}
+
static inline void *malloc(unsigned long size)
{
return (platform_ops.malloc) ? platform_ops.malloc(size) : NULL;
@@ -191,4 +206,25 @@ static inline void exit(void)
static char _bss_stack[size]; \
void *_platform_stack_top = _bss_stack + sizeof(_bss_stack);
+extern unsigned long timebase_period_ns;
+void udelay(long delay);
+
+extern char _start[];
+extern char __bss_start[];
+extern char _end[];
+extern char _vmlinux_start[];
+extern char _vmlinux_end[];
+extern char _initrd_start[];
+extern char _initrd_end[];
+extern char _dtb_start[];
+extern char _dtb_end[];
+
+static inline __attribute__((const))
+int __ilog2_u32(u32 n)
+{
+ int bit;
+ asm ("cntlzw %0,%1" : "=r" (bit) : "r" (n));
+ return 31 - bit;
+}
+
#endif /* _PPC_BOOT_OPS_H_ */
diff --git a/arch/powerpc/boot/planetcore.c b/arch/powerpc/boot/planetcore.c
new file mode 100644
index 00000000000..0d8558a475b
--- /dev/null
+++ b/arch/powerpc/boot/planetcore.c
@@ -0,0 +1,166 @@
+/*
+ * PlanetCore configuration data support functions
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "stdio.h"
+#include "stdlib.h"
+#include "ops.h"
+#include "planetcore.h"
+#include "io.h"
+
+/* PlanetCore passes information to the OS in the form of
+ * a table of key=value strings, separated by newlines.
+ *
+ * The list is terminated by an empty string (i.e. two
+ * consecutive newlines).
+ *
+ * To make it easier to parse, we first convert all the
+ * newlines into null bytes.
+ */
+
+void planetcore_prepare_table(char *table)
+{
+ do {
+ if (*table == '\n')
+ *table = 0;
+
+ table++;
+ } while (*(table - 1) || *table != '\n');
+
+ *table = 0;
+}
+
+const char *planetcore_get_key(const char *table, const char *key)
+{
+ int keylen = strlen(key);
+
+ do {
+ if (!strncmp(table, key, keylen) && table[keylen] == '=')
+ return table + keylen + 1;
+
+ table += strlen(table) + 1;
+ } while (strlen(table) != 0);
+
+ return NULL;
+}
+
+int planetcore_get_decimal(const char *table, const char *key, u64 *val)
+{
+ const char *str = planetcore_get_key(table, key);
+ if (!str)
+ return 0;
+
+ *val = strtoull(str, NULL, 10);
+ return 1;
+}
+
+int planetcore_get_hex(const char *table, const char *key, u64 *val)
+{
+ const char *str = planetcore_get_key(table, key);
+ if (!str)
+ return 0;
+
+ *val = strtoull(str, NULL, 16);
+ return 1;
+}
+
+static u64 mac_table[4] = {
+ 0x000000000000,
+ 0x000000800000,
+ 0x000000400000,
+ 0x000000c00000,
+};
+
+void planetcore_set_mac_addrs(const char *table)
+{
+ u8 addr[4][6];
+ u64 int_addr;
+ u32 i;
+ int j;
+
+ if (!planetcore_get_hex(table, PLANETCORE_KEY_MAC_ADDR, &int_addr))
+ return;
+
+ for (i = 0; i < 4; i++) {
+ u64 this_dev_addr = (int_addr & ~0x000000c00000) |
+ mac_table[i];
+
+ for (j = 5; j >= 0; j--) {
+ addr[i][j] = this_dev_addr & 0xff;
+ this_dev_addr >>= 8;
+ }
+
+ dt_fixup_mac_address(i, addr[i]);
+ }
+}
+
+static char prop_buf[MAX_PROP_LEN];
+
+void planetcore_set_stdout_path(const char *table)
+{
+ char *path;
+ const char *label;
+ void *node, *chosen;
+
+ label = planetcore_get_key(table, PLANETCORE_KEY_SERIAL_PORT);
+ if (!label)
+ return;
+
+ node = find_node_by_prop_value_str(NULL, "linux,planetcore-label",
+ label);
+ if (!node)
+ return;
+
+ path = get_path(node, prop_buf, MAX_PROP_LEN);
+ if (!path)
+ return;
+
+ chosen = finddevice("/chosen");
+ if (!chosen)
+ chosen = create_node(NULL, "chosen");
+ if (!chosen)
+ return;
+
+ setprop_str(chosen, "linux,stdout-path", path);
+}
+
+void planetcore_set_serial_speed(const char *table)
+{
+ void *chosen, *stdout;
+ u64 baud;
+ u32 baud32;
+ int len;
+
+ chosen = finddevice("/chosen");
+ if (!chosen)
+ return;
+
+ len = getprop(chosen, "linux,stdout-path", prop_buf, MAX_PROP_LEN);
+ if (len <= 0)
+ return;
+
+ stdout = finddevice(prop_buf);
+ if (!stdout) {
+ printf("planetcore_set_serial_speed: "
+ "Bad /chosen/linux,stdout-path.\r\n");
+
+ return;
+ }
+
+ if (!planetcore_get_decimal(table, PLANETCORE_KEY_SERIAL_BAUD,
+ &baud)) {
+ printf("planetcore_set_serial_speed: No SB tag.\r\n");
+ return;
+ }
+
+ baud32 = baud;
+ setprop(stdout, "current-speed", &baud32, 4);
+}
diff --git a/arch/powerpc/boot/planetcore.h b/arch/powerpc/boot/planetcore.h
new file mode 100644
index 00000000000..0d4094f1771
--- /dev/null
+++ b/arch/powerpc/boot/planetcore.h
@@ -0,0 +1,49 @@
+#ifndef _PPC_BOOT_PLANETCORE_H_
+#define _PPC_BOOT_PLANETCORE_H_
+
+#include "types.h"
+
+#define PLANETCORE_KEY_BOARD_TYPE "BO"
+#define PLANETCORE_KEY_BOARD_REV "BR"
+#define PLANETCORE_KEY_MB_RAM "D1"
+#define PLANETCORE_KEY_MAC_ADDR "EA"
+#define PLANETCORE_KEY_FLASH_SPEED "FS"
+#define PLANETCORE_KEY_IP_ADDR "IP"
+#define PLANETCORE_KEY_KB_NVRAM "NV"
+#define PLANETCORE_KEY_PROCESSOR "PR"
+#define PLANETCORE_KEY_PROC_VARIANT "PV"
+#define PLANETCORE_KEY_SERIAL_BAUD "SB"
+#define PLANETCORE_KEY_SERIAL_PORT "SP"
+#define PLANETCORE_KEY_SWITCH "SW"
+#define PLANETCORE_KEY_TEMP_OFFSET "TC"
+#define PLANETCORE_KEY_TARGET_IP "TIP"
+#define PLANETCORE_KEY_CRYSTAL_HZ "XT"
+
+/* Prepare the table for processing, by turning all newlines
+ * into NULL bytes.
+ */
+void planetcore_prepare_table(char *table);
+
+/* Return the value associated with a given key in text,
+ * decimal, or hex format.
+ *
+ * Returns zero/NULL on failure, non-zero on success.
+ */
+const char *planetcore_get_key(const char *table, const char *key);
+int planetcore_get_decimal(const char *table, const char *key, u64 *val);
+int planetcore_get_hex(const char *table, const char *key, u64 *val);
+
+/* Updates the device tree local-mac-address properties based
+ * on the EA tag.
+ */
+void planetcore_set_mac_addrs(const char *table);
+
+/* Sets the linux,stdout-path in the /chosen node. This requires the
+ * linux,planetcore-label property in each serial node.
+ */
+void planetcore_set_stdout_path(const char *table);
+
+/* Sets the current-speed property in the serial node. */
+void planetcore_set_serial_speed(const char *table);
+
+#endif
diff --git a/arch/powerpc/boot/ppcboot.h b/arch/powerpc/boot/ppcboot.h
index 5290ff2c2b2..6ae6f906395 100644
--- a/arch/powerpc/boot/ppcboot.h
+++ b/arch/powerpc/boot/ppcboot.h
@@ -78,17 +78,18 @@ typedef struct bd_info {
hymod_conf_t bi_hymod_conf; /* hymod configuration information */
#endif
#if defined(TARGET_EVB64260) || defined(TARGET_405EP) || defined(TARGET_44x) || \
- defined(TARGET_85xx) || defined(TARGET_83xx)
+ defined(TARGET_85xx) || defined(TARGET_83xx) || defined(TARGET_HAS_ETH1)
/* second onboard ethernet port */
unsigned char bi_enet1addr[6];
#define HAVE_ENET1ADDR
#endif
-#if defined(TARGET_EVB64260) || defined(TARGET_440GX) || defined(TARGET_85xx)
+#if defined(TARGET_EVB64260) || defined(TARGET_440GX) || \
+ defined(TARGET_85xx) || defined(TARGET_HAS_ETH2)
/* third onboard ethernet ports */
unsigned char bi_enet2addr[6];
#define HAVE_ENET2ADDR
#endif
-#if defined(TARGET_440GX)
+#if defined(TARGET_440GX) || defined(TARGET_HAS_ETH3)
/* fourth onboard ethernet ports */
unsigned char bi_enet3addr[6];
#define HAVE_ENET3ADDR
diff --git a/arch/powerpc/boot/pq2.c b/arch/powerpc/boot/pq2.c
new file mode 100644
index 00000000000..f6d118558f1
--- /dev/null
+++ b/arch/powerpc/boot/pq2.c
@@ -0,0 +1,102 @@
+/*
+ * PowerQUICC II support functions
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "types.h"
+#include "fsl-soc.h"
+#include "pq2.h"
+#include "stdio.h"
+#include "io.h"
+
+#define PQ2_SCCR (0x10c80/4) /* System Clock Configuration Register */
+#define PQ2_SCMR (0x10c88/4) /* System Clock Mode Register */
+
+static int pq2_corecnf_map[] = {
+ 3, 2, 2, 2, 4, 4, 5, 9, 6, 11, 8, 10, 3, 12, 7, -1,
+ 6, 5, 13, 2, 14, 4, 15, 9, 0, 11, 8, 10, 16, 12, 7, -1
+};
+
+/* Get various clocks from crystal frequency.
+ * Returns zero on failure and non-zero on success.
+ */
+int pq2_get_clocks(u32 crystal, u32 *sysfreq, u32 *corefreq,
+ u32 *timebase, u32 *brgfreq)
+{
+ u32 *immr;
+ u32 sccr, scmr, mainclk, busclk;
+ int corecnf, busdf, plldf, pllmf, dfbrg;
+
+ immr = fsl_get_immr();
+ if (!immr) {
+ printf("pq2_get_clocks: Couldn't get IMMR base.\r\n");
+ return 0;
+ }
+
+ sccr = in_be32(&immr[PQ2_SCCR]);
+ scmr = in_be32(&immr[PQ2_SCMR]);
+
+ dfbrg = sccr & 3;
+ corecnf = (scmr >> 24) & 0x1f;
+ busdf = (scmr >> 20) & 0xf;
+ plldf = (scmr >> 12) & 1;
+ pllmf = scmr & 0xfff;
+
+ mainclk = crystal * (pllmf + 1) / (plldf + 1);
+ busclk = mainclk / (busdf + 1);
+
+ if (sysfreq)
+ *sysfreq = mainclk / 2;
+ if (timebase)
+ *timebase = busclk / 4;
+ if (brgfreq)
+ *brgfreq = mainclk / (1 << ((dfbrg + 1) * 2));
+
+ if (corefreq) {
+ int coremult = pq2_corecnf_map[corecnf];
+
+ if (coremult < 0)
+ *corefreq = mainclk / 2;
+ else if (coremult == 0)
+ return 0;
+ else
+ *corefreq = busclk * coremult / 2;
+ }
+
+ return 1;
+}
+
+/* Set common device tree fields based on the given clock frequencies. */
+void pq2_set_clocks(u32 sysfreq, u32 corefreq, u32 timebase, u32 brgfreq)
+{
+ void *node;
+
+ dt_fixup_cpu_clocks(corefreq, timebase, sysfreq);
+
+ node = finddevice("/soc/cpm");
+ if (node)
+ setprop(node, "clock-frequency", &sysfreq, 4);
+
+ node = finddevice("/soc/cpm/brg");
+ if (node)
+ setprop(node, "clock-frequency", &brgfreq, 4);
+}
+
+int pq2_fixup_clocks(u32 crystal)
+{
+ u32 sysfreq, corefreq, timebase, brgfreq;
+
+ if (!pq2_get_clocks(crystal, &sysfreq, &corefreq, &timebase, &brgfreq))
+ return 0;
+
+ pq2_set_clocks(sysfreq, corefreq, timebase, brgfreq);
+ return 1;
+}
diff --git a/arch/powerpc/boot/pq2.h b/arch/powerpc/boot/pq2.h
new file mode 100644
index 00000000000..481698c7a51
--- /dev/null
+++ b/arch/powerpc/boot/pq2.h
@@ -0,0 +1,11 @@
+#ifndef _PPC_BOOT_PQ2_H_
+#define _PPC_BOOT_PQ2_H_
+
+#include "types.h"
+
+int pq2_get_clocks(u32 crystal, u32 *sysfreq, u32 *corefreq,
+ u32 *timebase, u32 *brgfreq);
+void pq2_set_clocks(u32 sysfreq, u32 corefreq, u32 timebase, u32 brgfreq);
+int pq2_fixup_clocks(u32 crystal);
+
+#endif
diff --git a/arch/powerpc/boot/prpmc2800.c b/arch/powerpc/boot/prpmc2800.c
index f428bac10d4..9614e1db9da 100644
--- a/arch/powerpc/boot/prpmc2800.c
+++ b/arch/powerpc/boot/prpmc2800.c
@@ -21,12 +21,6 @@
#include "gunzip_util.h"
#include "mv64x60.h"
-extern char _end[];
-extern char _vmlinux_start[], _vmlinux_end[];
-extern char _dtb_start[], _dtb_end[];
-
-extern void udelay(long delay);
-
#define KB 1024U
#define MB (KB*KB)
#define GB (KB*MB)
diff --git a/arch/powerpc/boot/ps3.c b/arch/powerpc/boot/ps3.c
index 893d59339c2..d6661151b49 100644
--- a/arch/powerpc/boot/ps3.c
+++ b/arch/powerpc/boot/ps3.c
@@ -120,10 +120,6 @@ void ps3_copy_vectors(void)
void platform_init(void)
{
- extern char _end[];
- extern char _dtb_start[];
- extern char _initrd_start[];
- extern char _initrd_end[];
const u32 heapsize = 0x1000000 - (u32)_end; /* 16MiB */
void *chosen;
unsigned long ft_addr;
diff --git a/arch/powerpc/boot/serial.c b/arch/powerpc/boot/serial.c
index eaa0d3ae351..cafeece20ac 100644
--- a/arch/powerpc/boot/serial.c
+++ b/arch/powerpc/boot/serial.c
@@ -19,8 +19,6 @@
#include "io.h"
#include "ops.h"
-extern void udelay(long delay);
-
static int serial_open(void)
{
struct serial_console_data *scdp = console_ops.data;
@@ -114,29 +112,36 @@ int serial_console_init(void)
{
void *devp;
int rc = -1;
- char compat[MAX_PROP_LEN];
devp = serial_get_stdout_devp();
if (devp == NULL)
goto err_out;
- if (getprop(devp, "compatible", compat, sizeof(compat)) < 0)
- goto err_out;
-
- if (!strcmp(compat, "ns16550"))
+ if (dt_is_compatible(devp, "ns16550"))
rc = ns16550_console_init(devp, &serial_cd);
- else if (!strcmp(compat, "marvell,mpsc"))
+ else if (dt_is_compatible(devp, "marvell,mpsc"))
rc = mpsc_console_init(devp, &serial_cd);
+ else if (dt_is_compatible(devp, "fsl,cpm1-scc-uart") ||
+ dt_is_compatible(devp, "fsl,cpm1-smc-uart") ||
+ dt_is_compatible(devp, "fsl,cpm2-scc-uart") ||
+ dt_is_compatible(devp, "fsl,cpm2-smc-uart"))
+ rc = cpm_console_init(devp, &serial_cd);
+ else if (dt_is_compatible(devp, "mpc5200-psc-uart"))
+ rc = mpc5200_psc_console_init(devp, &serial_cd);
+ else if (dt_is_compatible(devp, "xilinx,uartlite"))
+ rc = uartlite_console_init(devp, &serial_cd);
/* Add other serial console driver calls here */
if (!rc) {
console_ops.open = serial_open;
console_ops.write = serial_write;
- console_ops.edit_cmdline = serial_edit_cmdline;
console_ops.close = serial_close;
console_ops.data = &serial_cd;
+ if (serial_cd.getc)
+ console_ops.edit_cmdline = serial_edit_cmdline;
+
return 0;
}
err_out:
diff --git a/arch/powerpc/boot/stdlib.c b/arch/powerpc/boot/stdlib.c
new file mode 100644
index 00000000000..e00d58c29ee
--- /dev/null
+++ b/arch/powerpc/boot/stdlib.c
@@ -0,0 +1,45 @@
+/*
+ * stdlib functions
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "stdlib.h"
+
+/* Not currently supported: leading whitespace, sign, 0x prefix, zero base */
+unsigned long long int strtoull(const char *ptr, char **end, int base)
+{
+ unsigned long long ret = 0;
+
+ if (base > 36)
+ goto out;
+
+ while (*ptr) {
+ int digit;
+
+ if (*ptr >= '0' && *ptr <= '9' && *ptr < '0' + base)
+ digit = *ptr - '0';
+ else if (*ptr >= 'A' && *ptr < 'A' + base - 10)
+ digit = *ptr - 'A' + 10;
+ else if (*ptr >= 'a' && *ptr < 'a' + base - 10)
+ digit = *ptr - 'a' + 10;
+ else
+ break;
+
+ ret *= base;
+ ret += digit;
+ ptr++;
+ }
+
+out:
+ if (end)
+ *end = (char *)ptr;
+
+ return ret;
+}
diff --git a/arch/powerpc/boot/stdlib.h b/arch/powerpc/boot/stdlib.h
new file mode 100644
index 00000000000..1bf01ac73ab
--- /dev/null
+++ b/arch/powerpc/boot/stdlib.h
@@ -0,0 +1,6 @@
+#ifndef _PPC_BOOT_STDLIB_H_
+#define _PPC_BOOT_STDLIB_H_
+
+unsigned long long int strtoull(const char *ptr, char **end, int base);
+
+#endif
diff --git a/arch/powerpc/boot/string.S b/arch/powerpc/boot/string.S
index ac3d43b6a32..643e4cb2f11 100644
--- a/arch/powerpc/boot/string.S
+++ b/arch/powerpc/boot/string.S
@@ -49,6 +49,17 @@ strcat:
bne 1b
blr
+ .globl strchr
+strchr:
+ addi r3,r3,-1
+1: lbzu r0,1(r3)
+ cmpw 0,r0,r4
+ beqlr
+ cmpwi 0,r0,0
+ bne 1b
+ li r3,0
+ blr
+
.globl strcmp
strcmp:
addi r5,r3,-1
@@ -61,6 +72,19 @@ strcmp:
beq 1b
blr
+ .globl strncmp
+strncmp:
+ mtctr r5
+ addi r5,r3,-1
+ addi r4,r4,-1
+1: lbzu r3,1(r5)
+ cmpwi 1,r3,0
+ lbzu r0,1(r4)
+ subf. r3,r0,r3
+ beqlr 1
+ bdnzt eq,1b
+ blr
+
.globl strlen
strlen:
addi r4,r3,-1
@@ -195,6 +219,19 @@ backwards_memcpy:
mtctr r7
b 1b
+ .globl memchr
+memchr:
+ cmpwi 0,r5,0
+ blelr
+ mtctr r5
+ addi r3,r3,-1
+1: lbzu r0,1(r3)
+ cmpw r0,r4
+ beqlr
+ bdnz 1b
+ li r3,0
+ blr
+
.globl memcmp
memcmp:
cmpwi 0,r5,0
diff --git a/arch/powerpc/boot/string.h b/arch/powerpc/boot/string.h
index 9fdff1cc0d7..50091cc0eed 100644
--- a/arch/powerpc/boot/string.h
+++ b/arch/powerpc/boot/string.h
@@ -5,13 +5,16 @@
extern char *strcpy(char *dest, const char *src);
extern char *strncpy(char *dest, const char *src, size_t n);
extern char *strcat(char *dest, const char *src);
+extern char *strchr(const char *s, int c);
extern int strcmp(const char *s1, const char *s2);
+extern int strncmp(const char *s1, const char *s2, size_t n);
extern size_t strlen(const char *s);
extern size_t strnlen(const char *s, size_t count);
extern void *memset(void *s, int c, size_t n);
extern void *memmove(void *dest, const void *src, unsigned long n);
extern void *memcpy(void *dest, const void *src, unsigned long n);
+extern void *memchr(const void *s, int c, size_t n);
extern int memcmp(const void *s1, const void *s2, size_t n);
#endif /* _PPC_BOOT_STRING_H_ */
diff --git a/arch/powerpc/boot/treeboot-bamboo.c b/arch/powerpc/boot/treeboot-bamboo.c
new file mode 100644
index 00000000000..9eee48fc711
--- /dev/null
+++ b/arch/powerpc/boot/treeboot-bamboo.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright IBM Corporation, 2007
+ * Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ *
+ * Based on ebony wrapper:
+ * Copyright 2007 David Gibson, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2 of the License
+ */
+#include "ops.h"
+#include "stdio.h"
+#include "44x.h"
+#include "stdlib.h"
+
+BSS_STACK(4096);
+
+#define PIBS_MAC0 0xfffc0400
+#define PIBS_MAC1 0xfffc0500
+char pibs_mac0[6];
+char pibs_mac1[6];
+
+static void read_pibs_mac(void)
+{
+ unsigned long long mac64;
+
+ mac64 = strtoull((char *)PIBS_MAC0, 0, 16);
+ memcpy(&pibs_mac0, (char *)&mac64+2, 6);
+
+ mac64 = strtoull((char *)PIBS_MAC1, 0, 16);
+ memcpy(&pibs_mac1, (char *)&mac64+2, 6);
+}
+
+void platform_init(void)
+{
+ unsigned long end_of_ram = 0x8000000;
+ unsigned long avail_ram = end_of_ram - (unsigned long)_end;
+
+ simple_alloc_init(_end, avail_ram, 32, 64);
+ read_pibs_mac();
+ bamboo_init((u8 *)&pibs_mac0, (u8 *)&pibs_mac1);
+}
diff --git a/arch/powerpc/boot/treeboot-ebony.c b/arch/powerpc/boot/treeboot-ebony.c
index 8436a9c5519..21cc4834a38 100644
--- a/arch/powerpc/boot/treeboot-ebony.c
+++ b/arch/powerpc/boot/treeboot-ebony.c
@@ -16,8 +16,6 @@
#include "stdio.h"
#include "44x.h"
-extern char _end[];
-
BSS_STACK(4096);
#define OPENBIOS_MAC_BASE 0xfffffe0c
diff --git a/arch/powerpc/boot/treeboot-walnut.c b/arch/powerpc/boot/treeboot-walnut.c
new file mode 100644
index 00000000000..3adf2d08a23
--- /dev/null
+++ b/arch/powerpc/boot/treeboot-walnut.c
@@ -0,0 +1,131 @@
+/*
+ * Old U-boot compatibility for Walnut
+ *
+ * Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ *
+ * Copyright 2007 IBM Corporation
+ * Based on cuboot-83xx.c, which is:
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "stdio.h"
+#include "dcr.h"
+#include "4xx.h"
+#include "io.h"
+
+BSS_STACK(4096);
+
+void ibm405gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
+{
+ u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);
+ u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);
+ u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1);
+ u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
+ u32 fwdv, fbdv, cbdv, opdv, epdv, udiv;
+
+ fwdv = (8 - ((pllmr & 0xe0000000) >> 29));
+ fbdv = (pllmr & 0x1e000000) >> 25;
+ cbdv = ((pllmr & 0x00060000) >> 17) + 1;
+ opdv = ((pllmr & 0x00018000) >> 15) + 1;
+ epdv = ((pllmr & 0x00001800) >> 13) + 2;
+ udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
+
+ m = fwdv * fbdv * cbdv;
+
+ cpu = sysclk * m / fwdv;
+ plb = cpu / cbdv;
+ opb = plb / opdv;
+ ebc = plb / epdv;
+
+ if (cpc0_cr0 & 0x80) {
+ /* uart0 uses the external clock */
+ uart0 = ser_clk;
+ } else {
+ uart0 = cpu / udiv;
+ }
+
+ if (cpc0_cr0 & 0x40) {
+ /* uart1 uses the external clock */
+ uart1 = ser_clk;
+ } else {
+ uart1 = cpu / udiv;
+ }
+
+ /* setup the timebase clock to tick at the cpu frequency */
+ cpc0_cr1 = cpc0_cr1 & ~ 0x00800000;
+ mtdcr(DCRN_CPC0_CR1, cpc0_cr1);
+ tb = cpu;
+
+ dt_fixup_cpu_clocks(cpu, tb, 0);
+ dt_fixup_clock("/plb", plb);
+ dt_fixup_clock("/plb/opb", opb);
+ dt_fixup_clock("/plb/ebc", ebc);
+ dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
+ dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
+}
+
+static void walnut_flashsel_fixup(void)
+{
+ void *devp, *sram;
+ u32 reg_flash[3] = {0x0, 0x0, 0x80000};
+ u32 reg_sram[3] = {0x0, 0x0, 0x80000};
+ u8 *fpga;
+ u8 fpga_brds1 = 0x0;
+
+ devp = finddevice("/plb/ebc/fpga");
+ if (!devp)
+ fatal("Couldn't locate FPGA node\n\r");
+
+ if (getprop(devp, "virtual-reg", &fpga, sizeof(fpga)) != sizeof(fpga))
+ fatal("no virtual-reg property\n\r");
+
+ fpga_brds1 = in_8(fpga);
+
+ devp = finddevice("/plb/ebc/flash");
+ if (!devp)
+ fatal("Couldn't locate flash node\n\r");
+
+ if (getprop(devp, "reg", reg_flash, sizeof(reg_flash)) != sizeof(reg_flash))
+ fatal("flash reg property has unexpected size\n\r");
+
+ sram = finddevice("/plb/ebc/sram");
+ if (!sram)
+ fatal("Couldn't locate sram node\n\r");
+
+ if (getprop(sram, "reg", reg_sram, sizeof(reg_sram)) != sizeof(reg_sram))
+ fatal("sram reg property has unexpected size\n\r");
+
+ if (fpga_brds1 & 0x1) {
+ reg_flash[1] ^= 0x80000;
+ reg_sram[1] ^= 0x80000;
+ }
+
+ setprop(devp, "reg", reg_flash, sizeof(reg_flash));
+ setprop(sram, "reg", reg_sram, sizeof(reg_sram));
+}
+
+static void walnut_fixups(void)
+{
+ ibm4xx_fixup_memsize();
+ ibm405gp_fixup_clocks(33330000, 0xa8c000);
+ ibm4xx_quiesce_eth((u32 *)0xef600800, NULL);
+ ibm4xx_fixup_ebc_ranges("/plb/ebc");
+ walnut_flashsel_fixup();
+}
+
+void platform_init(void)
+{
+ unsigned long end_of_ram = 0x2000000;
+ unsigned long avail_ram = end_of_ram - (unsigned long) _end;
+
+ simple_alloc_init(_end, avail_ram, 32, 32);
+ platform_ops.fixups = walnut_fixups;
+ platform_ops.exit = ibm40x_dbcr_reset;
+ ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
+ serial_console_init();
+}
diff --git a/arch/powerpc/boot/uartlite.c b/arch/powerpc/boot/uartlite.c
new file mode 100644
index 00000000000..46bed69b416
--- /dev/null
+++ b/arch/powerpc/boot/uartlite.c
@@ -0,0 +1,79 @@
+/*
+ * Xilinx UARTLITE bootloader driver
+ *
+ * Copyright (C) 2007 Secret Lab Technologies Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <stdarg.h>
+#include <stddef.h>
+#include "types.h"
+#include "string.h"
+#include "stdio.h"
+#include "io.h"
+#include "ops.h"
+
+#define ULITE_RX 0x00
+#define ULITE_TX 0x04
+#define ULITE_STATUS 0x08
+#define ULITE_CONTROL 0x0c
+
+#define ULITE_STATUS_RXVALID 0x01
+#define ULITE_STATUS_TXFULL 0x08
+
+#define ULITE_CONTROL_RST_RX 0x02
+
+static void * reg_base;
+
+static int uartlite_open(void)
+{
+ /* Clear the RX FIFO */
+ out_be32(reg_base + ULITE_CONTROL, ULITE_CONTROL_RST_RX);
+ return 0;
+}
+
+static void uartlite_putc(unsigned char c)
+{
+ u32 reg = ULITE_STATUS_TXFULL;
+ while (reg & ULITE_STATUS_TXFULL) /* spin on TXFULL bit */
+ reg = in_be32(reg_base + ULITE_STATUS);
+ out_be32(reg_base + ULITE_TX, c);
+}
+
+static unsigned char uartlite_getc(void)
+{
+ u32 reg = 0;
+ while (!(reg & ULITE_STATUS_RXVALID)) /* spin waiting for RXVALID bit */
+ reg = in_be32(reg_base + ULITE_STATUS);
+ return in_be32(reg_base + ULITE_RX);
+}
+
+static u8 uartlite_tstc(void)
+{
+ u32 reg = in_be32(reg_base + ULITE_STATUS);
+ return reg & ULITE_STATUS_RXVALID;
+}
+
+int uartlite_console_init(void *devp, struct serial_console_data *scdp)
+{
+ int n;
+ unsigned long reg_phys;
+
+ n = getprop(devp, "virtual-reg", &reg_base, sizeof(reg_base));
+ if (n != sizeof(reg_base)) {
+ if (!dt_xlate_reg(devp, 0, &reg_phys, NULL))
+ return -1;
+
+ reg_base = (void *)reg_phys;
+ }
+
+ scdp->open = uartlite_open;
+ scdp->putc = uartlite_putc;
+ scdp->getc = uartlite_getc;
+ scdp->tstc = uartlite_tstc;
+ scdp->close = NULL;
+ return 0;
+}
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index 65f68547917..39b27e5ef6c 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -29,6 +29,7 @@ initrd=
dtb=
dts=
cacheit=
+binary=
gzip=.gz
# cross-compilation prefix
@@ -142,17 +143,23 @@ miboot|uboot)
isection=initrd
;;
cuboot*)
+ binary=y
gzip=
;;
ps3)
platformo="$object/ps3-head.o $object/ps3-hvcall.o $object/ps3.o"
lds=$object/zImage.ps3.lds
+ binary=y
gzip=
ext=bin
objflags="-O binary --set-section-flags=.bss=contents,alloc,load,data"
ksection=.kernel:vmlinux.bin
isection=.kernel:initrd
;;
+ep88xc)
+ platformo="$object/fixed-head.o $object/$platform.o"
+ binary=y
+ ;;
esac
vmz="$tmpdir/`basename \"$kernel\"`.$ext"
@@ -224,6 +231,11 @@ fi
base=0x`${CROSS}nm "$ofile" | grep ' _start$' | cut -d' ' -f1`
entry=`${CROSS}objdump -f "$ofile" | grep '^start address ' | cut -d' ' -f3`
+if [ -n "$binary" ]; then
+ mv "$ofile" "$ofile".elf
+ ${CROSS}objcopy -O binary "$ofile".elf "$ofile".bin
+fi
+
# post-processing needed for some platforms
case "$platform" in
pseries|chrp)
@@ -234,8 +246,6 @@ coff)
$object/hack-coff "$ofile"
;;
cuboot*)
- mv "$ofile" "$ofile".elf
- ${CROSS}objcopy -O binary "$ofile".elf "$ofile".bin
gzip -f -9 "$ofile".bin
mkimage -A ppc -O linux -T kernel -C gzip -a "$base" -e "$entry" \
$uboot_version -d "$ofile".bin.gz "$ofile"
@@ -259,11 +269,11 @@ ps3)
# then copied to offset 0x100. At runtime the bootwrapper program
# copies the 0x100 bytes at __system_reset_kernel to addr 0x100.
- system_reset_overlay=0x`${CROSS}nm "$ofile" \
+ system_reset_overlay=0x`${CROSS}nm "$ofile".elf \
| grep ' __system_reset_overlay$' \
| cut -d' ' -f1`
system_reset_overlay=`printf "%d" $system_reset_overlay`
- system_reset_kernel=0x`${CROSS}nm "$ofile" \
+ system_reset_kernel=0x`${CROSS}nm "$ofile".elf \
| grep ' __system_reset_kernel$' \
| cut -d' ' -f1`
system_reset_kernel=`printf "%d" $system_reset_kernel`
@@ -272,8 +282,6 @@ ps3)
rm -f "$object/otheros.bld"
- ${CROSS}objcopy -O binary "$ofile" "$ofile.bin"
-
msg=$(dd if="$ofile.bin" of="$ofile.bin" conv=notrunc \
skip=$overlay_dest seek=$system_reset_kernel \
count=$overlay_size bs=1 2>&1)