diff options
Diffstat (limited to 'arch/powerpc/mm')
| -rw-r--r-- | arch/powerpc/mm/hash_low_32.S | 8 | ||||
| -rw-r--r-- | arch/powerpc/mm/hash_utils_64.c | 15 | ||||
| -rw-r--r-- | arch/powerpc/mm/slb.c | 6 |
3 files changed, 22 insertions, 7 deletions
diff --git a/arch/powerpc/mm/hash_low_32.S b/arch/powerpc/mm/hash_low_32.S index 7f830a4888d..e10d76a860d 100644 --- a/arch/powerpc/mm/hash_low_32.S +++ b/arch/powerpc/mm/hash_low_32.S @@ -44,6 +44,9 @@ mmu_hash_lock: #ifdef CONFIG_SMP .text _GLOBAL(hash_page_sync) + mfmsr r10 + rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ + mtmsr r0 lis r8,mmu_hash_lock@h ori r8,r8,mmu_hash_lock@l lis r0,0x0fff @@ -60,8 +63,9 @@ _GLOBAL(hash_page_sync) eieio li r0,0 stw r0,0(r8) - blr -#endif + mtmsr r10 + blr +#endif /* CONFIG_SMP */ /* * Load a PTE into the hash table, if possible. diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c index 32f416175db..a83dfa3cf40 100644 --- a/arch/powerpc/mm/hash_utils_64.c +++ b/arch/powerpc/mm/hash_utils_64.c @@ -351,9 +351,14 @@ static void __init htab_init_page_sizes(void) mmu_vmalloc_psize = MMU_PAGE_64K; if (mmu_linear_psize == MMU_PAGE_4K) mmu_linear_psize = MMU_PAGE_64K; - if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) - mmu_io_psize = MMU_PAGE_64K; - else + if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) { + /* + * Don't use 64k pages for ioremap on pSeries, since + * that would stop us accessing the HEA ethernet. + */ + if (!machine_is(pseries)) + mmu_io_psize = MMU_PAGE_64K; + } else mmu_ci_restrictions = 1; } #endif /* CONFIG_PPC_64K_PAGES */ @@ -506,10 +511,10 @@ void __init htab_initialize(void) } else { /* Find storage for the HPT. Must be contiguous in * the absolute address space. On cell we want it to be - * in the first 1 Gig. + * in the first 2 Gig so we can use it for IOMMU hacks. */ if (machine_is(cell)) - limit = 0x40000000; + limit = 0x80000000; else limit = 0; diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c index 47b06bad24a..906daeda59a 100644 --- a/arch/powerpc/mm/slb.c +++ b/arch/powerpc/mm/slb.c @@ -124,6 +124,12 @@ void slb_flush_and_rebolt(void) ksp_vsid_data = get_slb_shadow()->save_area[2].vsid; } + /* + * We can't take a PMU exception in the following code, so hard + * disable interrupts. + */ + hard_irq_disable(); + /* We need to do this all in asm, so we're sure we don't touch * the stack between the slbia and rebolting it. */ asm volatile("isync\n" |