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-rw-r--r--arch/ppc/mm/init.c46
1 files changed, 16 insertions, 30 deletions
diff --git a/arch/ppc/mm/init.c b/arch/ppc/mm/init.c
index f421a4b337f..45f0782059f 100644
--- a/arch/ppc/mm/init.c
+++ b/arch/ppc/mm/init.c
@@ -69,15 +69,12 @@ int init_bootmem_done;
int boot_mapsize;
#ifdef CONFIG_PPC_PMAC
unsigned long agp_special_page;
+EXPORT_SYMBOL(agp_special_page);
#endif
extern char _end[];
extern char etext[], _stext[];
extern char __init_begin, __init_end;
-extern char __prep_begin, __prep_end;
-extern char __chrp_begin, __chrp_end;
-extern char __pmac_begin, __pmac_end;
-extern char __openfirmware_begin, __openfirmware_end;
#ifdef CONFIG_HIGHMEM
pte_t *kmap_pte;
@@ -167,14 +164,6 @@ void free_initmem(void)
printk ("Freeing unused kernel memory:");
FREESEC(init);
- if (_machine != _MACH_Pmac)
- FREESEC(pmac);
- if (_machine != _MACH_chrp)
- FREESEC(chrp);
- if (_machine != _MACH_prep)
- FREESEC(prep);
- if (!have_of)
- FREESEC(openfirmware);
printk("\n");
ppc_md.progress = NULL;
#undef FREESEC
@@ -608,21 +597,20 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
if (pfn_valid(pfn)) {
struct page *page = pfn_to_page(pfn);
- if (!PageReserved(page)
- && !test_bit(PG_arch_1, &page->flags)) {
- if (vma->vm_mm == current->active_mm) {
#ifdef CONFIG_8xx
- /* On 8xx, cache control instructions (particularly
- * "dcbst" from flush_dcache_icache) fault as write
- * operation if there is an unpopulated TLB entry
- * for the address in question. To workaround that,
- * we invalidate the TLB here, thus avoiding dcbst
- * misbehaviour.
- */
- _tlbie(address);
+ /* On 8xx, the TLB handlers work in 2 stages:
+ * First, a zeroed entry is loaded by TLBMiss handler,
+ * which causes the TLBError handler to be triggered.
+ * That means the zeroed TLB has to be invalidated
+ * whenever a page miss occurs.
+ */
+ _tlbie(address);
#endif
+ if (!PageReserved(page)
+ && !test_bit(PG_arch_1, &page->flags)) {
+ if (vma->vm_mm == current->active_mm)
__flush_dcache_icache((void *) address);
- } else
+ else
flush_dcache_icache_page(page);
set_bit(PG_arch_1, &page->flags);
}
@@ -648,18 +636,16 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
*/
int page_is_ram(unsigned long pfn)
{
- unsigned long paddr = (pfn << PAGE_SHIFT);
-
- return paddr < __pa(high_memory);
+ return pfn < max_pfn;
}
-pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
+pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
unsigned long size, pgprot_t vma_prot)
{
if (ppc_md.phys_mem_access_prot)
- return ppc_md.phys_mem_access_prot(file, addr, size, vma_prot);
+ return ppc_md.phys_mem_access_prot(file, pfn, size, vma_prot);
- if (!page_is_ram(addr >> PAGE_SHIFT))
+ if (!page_is_ram(pfn))
vma_prot = __pgprot(pgprot_val(vma_prot)
| _PAGE_GUARDED | _PAGE_NO_CACHE);
return vma_prot;