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-rw-r--r--arch/ppc/platforms/4xx/ebony.c7
-rw-r--r--arch/ppc/platforms/4xx/luan.c5
-rw-r--r--arch/ppc/platforms/4xx/ocotea.c5
-rw-r--r--arch/ppc/platforms/chrp_pci.c7
-rw-r--r--arch/ppc/platforms/chrp_setup.c2
-rw-r--r--arch/ppc/platforms/pmac_cache.S54
-rw-r--r--arch/ppc/platforms/pmac_feature.c216
-rw-r--r--arch/ppc/platforms/pmac_low_i2c.c10
-rw-r--r--arch/ppc/platforms/pmac_sleep.S4
-rw-r--r--arch/ppc/platforms/pmac_smp.c14
-rw-r--r--arch/ppc/platforms/pmac_time.c7
-rw-r--r--arch/ppc/platforms/radstone_ppc7d.c60
-rw-r--r--arch/ppc/platforms/radstone_ppc7d.h1
13 files changed, 240 insertions, 152 deletions
diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c
index f63bca83e75..cd11734ef7c 100644
--- a/arch/ppc/platforms/4xx/ebony.c
+++ b/arch/ppc/platforms/4xx/ebony.c
@@ -149,7 +149,7 @@ ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
static void __init
ebony_setup_pcix(void)
{
- void *pcix_reg_base;
+ void __iomem *pcix_reg_base;
pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
@@ -210,9 +210,8 @@ ebony_setup_hose(void)
hose->io_space.end = EBONY_PCI_UPPER_IO;
hose->mem_space.start = EBONY_PCI_LOWER_MEM;
hose->mem_space.end = EBONY_PCI_UPPER_MEM;
- isa_io_base =
- (unsigned long)ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
- hose->io_base_virt = (void *)isa_io_base;
+ hose->io_base_virt = ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
+ isa_io_base = (unsigned long)hose->io_base_virt;
setup_indirect_pci(hose,
EBONY_PCI_CFGA_PLB32,
diff --git a/arch/ppc/platforms/4xx/luan.c b/arch/ppc/platforms/4xx/luan.c
index 1df2339f1f6..95359f748e7 100644
--- a/arch/ppc/platforms/4xx/luan.c
+++ b/arch/ppc/platforms/4xx/luan.c
@@ -223,9 +223,8 @@ luan_setup_hose(struct pci_controller *hose,
hose->io_space.end = LUAN_PCIX_UPPER_IO;
hose->mem_space.start = lower_mem;
hose->mem_space.end = upper_mem;
- isa_io_base =
- (unsigned long)ioremap64(pcix_io_base, PCIX_IO_SIZE);
- hose->io_base_virt = (void *)isa_io_base;
+ hose->io_base_virt = ioremap64(pcix_io_base, PCIX_IO_SIZE);
+ isa_io_base = (unsigned long) hose->io_base_virt;
setup_indirect_pci(hose, cfga, cfgd);
hose->set_cfg_type = 1;
diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
index 28de707434f..5f82a6bc704 100644
--- a/arch/ppc/platforms/4xx/ocotea.c
+++ b/arch/ppc/platforms/4xx/ocotea.c
@@ -227,9 +227,8 @@ ocotea_setup_hose(void)
hose->io_space.end = OCOTEA_PCI_UPPER_IO;
hose->mem_space.start = OCOTEA_PCI_LOWER_MEM;
hose->mem_space.end = OCOTEA_PCI_UPPER_MEM;
- isa_io_base =
- (unsigned long)ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE);
- hose->io_base_virt = (void *)isa_io_base;
+ hose->io_base_virt = ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE);
+ isa_io_base = (unsigned long) hose->io_base_virt;
setup_indirect_pci(hose,
OCOTEA_PCI_CFGA_PLB32,
diff --git a/arch/ppc/platforms/chrp_pci.c b/arch/ppc/platforms/chrp_pci.c
index 5bb6492ecf8..7d0ee308f66 100644
--- a/arch/ppc/platforms/chrp_pci.c
+++ b/arch/ppc/platforms/chrp_pci.c
@@ -129,7 +129,7 @@ static struct pci_ops rtas_pci_ops =
rtas_write_config
};
-volatile struct Hydra *Hydra = NULL;
+volatile struct Hydra __iomem *Hydra = NULL;
int __init
hydra_init(void)
@@ -175,13 +175,14 @@ chrp_pcibios_fixup(void)
static void __init
setup_python(struct pci_controller *hose, struct device_node *dev)
{
- u32 *reg, val;
+ u32 __iomem *reg;
+ u32 val;
unsigned long addr = dev->addrs[0].address;
setup_indirect_pci(hose, addr + 0xf8000, addr + 0xf8010);
/* Clear the magic go-slow bit */
- reg = (u32 *) ioremap(dev->addrs[0].address + 0xf6000, 0x40);
+ reg = ioremap(dev->addrs[0].address + 0xf6000, 0x40);
val = in_be32(&reg[12]);
if (val & PRG_CL_RESET_VALID) {
out_be32(&reg[12], val & ~PRG_CL_RESET_VALID);
diff --git a/arch/ppc/platforms/chrp_setup.c b/arch/ppc/platforms/chrp_setup.c
index f23c4f32076..57f29ab29bd 100644
--- a/arch/ppc/platforms/chrp_setup.c
+++ b/arch/ppc/platforms/chrp_setup.c
@@ -356,7 +356,7 @@ static void __init chrp_find_openpic(void)
struct device_node *np;
int len, i;
unsigned int *iranges;
- void *isu;
+ void __iomem *isu;
np = find_type_devices("open-pic");
if (np == NULL || np->n_addrs == 0)
diff --git a/arch/ppc/platforms/pmac_cache.S b/arch/ppc/platforms/pmac_cache.S
index da34a9bc929..fb977de6b70 100644
--- a/arch/ppc/platforms/pmac_cache.S
+++ b/arch/ppc/platforms/pmac_cache.S
@@ -64,27 +64,39 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
mtspr SPRN_HID0,r4 /* Disable DPM */
sync
- /* disp-flush L1 */
- li r4,0x4000
- mtctr r4
+ /* Disp-flush L1. We have a weird problem here that I never
+ * totally figured out. On 750FX, using the ROM for the flush
+ * results in a non-working flush. We use that workaround for
+ * now until I finally understand what's going on. --BenH
+ */
+
+ /* ROM base by default */
lis r4,0xfff0
-1: lwzx r0,r0,r4
+ mfpvr r3
+ srwi r3,r3,16
+ cmplwi cr0,r3,0x7000
+ bne+ 1f
+ /* RAM base on 750FX */
+ li r4,0
+1: li r4,0x4000
+ mtctr r4
+1: lwz r0,0(r4)
addi r4,r4,32
bdnz 1b
sync
isync
- /* disable / invalidate / enable L1 data */
+ /* Disable / invalidate / enable L1 data */
mfspr r3,SPRN_HID0
- rlwinm r0,r0,0,~HID0_DCE
+ rlwinm r3,r3,0,~(HID0_DCE | HID0_ICE)
mtspr SPRN_HID0,r3
sync
isync
- ori r3,r3,HID0_DCE|HID0_DCI
+ ori r3,r3,(HID0_DCE|HID0_DCI|HID0_ICE|HID0_ICFI)
sync
isync
mtspr SPRN_HID0,r3
- xori r3,r3,HID0_DCI
+ xori r3,r3,(HID0_DCI|HID0_ICFI)
mtspr SPRN_HID0,r3
sync
@@ -110,11 +122,20 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
lis r4,2
mtctr r4
lis r4,0xfff0
-1: lwzx r0,r0,r4
+1: lwz r0,0(r4)
+ addi r4,r4,32
+ bdnz 1b
+ sync
+ isync
+ lis r4,2
+ mtctr r4
+ lis r4,0xfff0
+1: dcbf 0,r4
addi r4,r4,32
bdnz 1b
sync
isync
+
/* now disable L2 */
rlwinm r5,r5,0,~L2CR_L2E
b 2f
@@ -135,6 +156,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
mtspr SPRN_L2CR,r4
sync
isync
+
+ /* Wait for the invalidation to complete */
+1: mfspr r3,SPRN_L2CR
+ rlwinm. r0,r3,0,31,31
+ bne 1b
+
+ /* Clear L2I */
xoris r4,r4,L2CR_L2I@h
sync
mtspr SPRN_L2CR,r4
@@ -142,14 +170,16 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
/* now disable the L1 data cache */
mfspr r0,SPRN_HID0
- rlwinm r0,r0,0,~HID0_DCE
+ rlwinm r0,r0,0,~(HID0_DCE|HID0_ICE)
mtspr SPRN_HID0,r0
sync
isync
/* Restore HID0[DPM] to whatever it was before */
sync
- mtspr SPRN_HID0,r8
+ mfspr r0,SPRN_HID0
+ rlwimi r0,r8,0,11,11 /* Turn back HID0[DPM] */
+ mtspr SPRN_HID0,r0
sync
/* restore DR and EE */
@@ -201,7 +231,7 @@ flush_disable_745x:
mtctr r4
li r4,0
1:
- lwzx r0,r0,r4
+ lwz r0,0(r4)
addi r4,r4,32 /* Go to start of next cache line */
bdnz 1b
isync
diff --git a/arch/ppc/platforms/pmac_feature.c b/arch/ppc/platforms/pmac_feature.c
index 46cbf36722d..867336ad5d3 100644
--- a/arch/ppc/platforms/pmac_feature.c
+++ b/arch/ppc/platforms/pmac_feature.c
@@ -1590,6 +1590,114 @@ intrepid_shutdown(struct macio_chip* macio, int sleep_mode)
mdelay(10);
}
+
+void __pmac pmac_tweak_clock_spreading(int enable)
+{
+ struct macio_chip* macio = &macio_chips[0];
+
+ /* Hack for doing clock spreading on some machines PowerBooks and
+ * iBooks. This implements the "platform-do-clockspreading" OF
+ * property as decoded manually on various models. For safety, we also
+ * check the product ID in the device-tree in cases we'll whack the i2c
+ * chip to make reasonably sure we won't set wrong values in there
+ *
+ * Of course, ultimately, we have to implement a real parser for
+ * the platform-do-* stuff...
+ */
+
+ if (macio->type == macio_intrepid) {
+ if (enable)
+ UN_OUT(UNI_N_CLOCK_SPREADING, 2);
+ else
+ UN_OUT(UNI_N_CLOCK_SPREADING, 0);
+ mdelay(40);
+ }
+
+ while (machine_is_compatible("PowerBook5,2") ||
+ machine_is_compatible("PowerBook5,3") ||
+ machine_is_compatible("PowerBook6,2") ||
+ machine_is_compatible("PowerBook6,3")) {
+ struct device_node *ui2c = of_find_node_by_type(NULL, "i2c");
+ struct device_node *dt = of_find_node_by_name(NULL, "device-tree");
+ u8 buffer[9];
+ u32 *productID;
+ int i, rc, changed = 0;
+
+ if (dt == NULL)
+ break;
+ productID = (u32 *)get_property(dt, "pid#", NULL);
+ if (productID == NULL)
+ break;
+ while(ui2c) {
+ struct device_node *p = of_get_parent(ui2c);
+ if (p && !strcmp(p->name, "uni-n"))
+ break;
+ ui2c = of_find_node_by_type(ui2c, "i2c");
+ }
+ if (ui2c == NULL)
+ break;
+ DBG("Trying to bump clock speed for PID: %08x...\n", *productID);
+ rc = pmac_low_i2c_open(ui2c, 1);
+ if (rc != 0)
+ break;
+ pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined);
+ rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9);
+ DBG("read result: %d,", rc);
+ if (rc != 0) {
+ pmac_low_i2c_close(ui2c);
+ break;
+ }
+ for (i=0; i<9; i++)
+ DBG(" %02x", buffer[i]);
+ DBG("\n");
+
+ switch(*productID) {
+ case 0x1182: /* AlBook 12" rev 2 */
+ case 0x1183: /* iBook G4 12" */
+ buffer[0] = (buffer[0] & 0x8f) | 0x70;
+ buffer[2] = (buffer[2] & 0x7f) | 0x00;
+ buffer[5] = (buffer[5] & 0x80) | 0x31;
+ buffer[6] = (buffer[6] & 0x40) | 0xb0;
+ buffer[7] = (buffer[7] & 0x00) | (enable ? 0xc0 : 0xba);
+ buffer[8] = (buffer[8] & 0x00) | 0x30;
+ changed = 1;
+ break;
+ case 0x3142: /* AlBook 15" (ATI M10) */
+ case 0x3143: /* AlBook 17" (ATI M10) */
+ buffer[0] = (buffer[0] & 0xaf) | 0x50;
+ buffer[2] = (buffer[2] & 0x7f) | 0x00;
+ buffer[5] = (buffer[5] & 0x80) | 0x31;
+ buffer[6] = (buffer[6] & 0x40) | 0xb0;
+ buffer[7] = (buffer[7] & 0x00) | (enable ? 0xd0 : 0xc0);
+ buffer[8] = (buffer[8] & 0x00) | 0x30;
+ changed = 1;
+ break;
+ default:
+ DBG("i2c-hwclock: Machine model not handled\n");
+ break;
+ }
+ if (!changed) {
+ pmac_low_i2c_close(ui2c);
+ break;
+ }
+ pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_stdsub);
+ rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_write, 0x80, buffer, 9);
+ DBG("write result: %d,", rc);
+ pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined);
+ rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9);
+ DBG("read result: %d,", rc);
+ if (rc != 0) {
+ pmac_low_i2c_close(ui2c);
+ break;
+ }
+ for (i=0; i<9; i++)
+ DBG(" %02x", buffer[i]);
+ pmac_low_i2c_close(ui2c);
+ break;
+ }
+}
+
+
static int __pmac
core99_sleep(void)
{
@@ -1601,12 +1709,6 @@ core99_sleep(void)
macio->type != macio_intrepid)
return -ENODEV;
- /* The device-tree contains that in the hwclock node */
- if (macio->type == macio_intrepid) {
- UN_OUT(UNI_N_CLOCK_SPREADING, 0);
- mdelay(40);
- }
-
/* We power off the wireless slot in case it was not done
* by the driver. We don't power it on automatically however
*/
@@ -1749,12 +1851,6 @@ core99_wake_up(void)
UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl);
udelay(100);
- /* Restore clock spreading */
- if (macio->type == macio_intrepid) {
- UN_OUT(UNI_N_CLOCK_SPREADING, 2);
- mdelay(40);
- }
-
return 0;
}
@@ -2149,7 +2245,7 @@ static struct pmac_mb_def pmac_mb_defs[] __pmacdata = {
},
{ "PowerBook1,1", "PowerBook 101 (Lombard)",
PMAC_TYPE_101_PBOOK, paddington_features,
- PMAC_MB_MAY_SLEEP | PMAC_MB_MOBILE
+ PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
},
{ "PowerBook2,1", "iBook (first generation)",
PMAC_TYPE_ORIG_IBOOK, core99_features,
@@ -2718,97 +2814,11 @@ set_initial_features(void)
MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
}
- /* Hack for bumping clock speed on the new PowerBooks and the
- * iBook G4. This implements the "platform-do-clockspreading" OF
- * property. For safety, we also check the product ID in the
- * device-tree to make reasonably sure we won't set wrong values
- * in the clock chip.
- *
- * Of course, ultimately, we have to implement a real parser for
- * the platform-do-* stuff...
+ /* Some machine models need the clock chip to be properly setup for
+ * clock spreading now. This should be a platform function but we
+ * don't do these at the moment
*/
- while (machine_is_compatible("PowerBook5,2") ||
- machine_is_compatible("PowerBook5,3") ||
- machine_is_compatible("PowerBook6,2") ||
- machine_is_compatible("PowerBook6,3")) {
- struct device_node *ui2c = of_find_node_by_type(NULL, "i2c");
- struct device_node *dt = of_find_node_by_name(NULL, "device-tree");
- u8 buffer[9];
- u32 *productID;
- int i, rc, changed = 0;
-
- if (dt == NULL)
- break;
- productID = (u32 *)get_property(dt, "pid#", NULL);
- if (productID == NULL)
- break;
- while(ui2c) {
- struct device_node *p = of_get_parent(ui2c);
- if (p && !strcmp(p->name, "uni-n"))
- break;
- ui2c = of_find_node_by_type(ui2c, "i2c");
- }
- if (ui2c == NULL)
- break;
- DBG("Trying to bump clock speed for PID: %08x...\n", *productID);
- rc = pmac_low_i2c_open(ui2c, 1);
- if (rc != 0)
- break;
- pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined);
- rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9);
- DBG("read result: %d,", rc);
- if (rc != 0) {
- pmac_low_i2c_close(ui2c);
- break;
- }
- for (i=0; i<9; i++)
- DBG(" %02x", buffer[i]);
- DBG("\n");
-
- switch(*productID) {
- case 0x1182: /* AlBook 12" rev 2 */
- case 0x1183: /* iBook G4 12" */
- buffer[0] = (buffer[0] & 0x8f) | 0x70;
- buffer[2] = (buffer[2] & 0x7f) | 0x00;
- buffer[5] = (buffer[5] & 0x80) | 0x31;
- buffer[6] = (buffer[6] & 0x40) | 0xb0;
- buffer[7] = (buffer[7] & 0x00) | 0xc0;
- buffer[8] = (buffer[8] & 0x00) | 0x30;
- changed = 1;
- break;
- case 0x3142: /* AlBook 15" (ATI M10) */
- case 0x3143: /* AlBook 17" (ATI M10) */
- buffer[0] = (buffer[0] & 0xaf) | 0x50;
- buffer[2] = (buffer[2] & 0x7f) | 0x00;
- buffer[5] = (buffer[5] & 0x80) | 0x31;
- buffer[6] = (buffer[6] & 0x40) | 0xb0;
- buffer[7] = (buffer[7] & 0x00) | 0xd0;
- buffer[8] = (buffer[8] & 0x00) | 0x30;
- changed = 1;
- break;
- default:
- DBG("i2c-hwclock: Machine model not handled\n");
- break;
- }
- if (!changed) {
- pmac_low_i2c_close(ui2c);
- break;
- }
- pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_stdsub);
- rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_write, 0x80, buffer, 9);
- DBG("write result: %d,", rc);
- pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined);
- rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9);
- DBG("read result: %d,", rc);
- if (rc != 0) {
- pmac_low_i2c_close(ui2c);
- break;
- }
- for (i=0; i<9; i++)
- DBG(" %02x", buffer[i]);
- pmac_low_i2c_close(ui2c);
- break;
- }
+ pmac_tweak_clock_spreading(1);
#endif /* CONFIG_POWER4 */
diff --git a/arch/ppc/platforms/pmac_low_i2c.c b/arch/ppc/platforms/pmac_low_i2c.c
index d07579f2b8b..08583fce169 100644
--- a/arch/ppc/platforms/pmac_low_i2c.c
+++ b/arch/ppc/platforms/pmac_low_i2c.c
@@ -54,7 +54,7 @@ struct low_i2c_host
int mode; /* Current mode */
int channel; /* Current channel */
int num_channels; /* Number of channels */
- unsigned long base; /* For keywest-i2c, base address */
+ void __iomem * base; /* For keywest-i2c, base address */
int bsteps; /* And register stepping */
int speed; /* And speed */
};
@@ -154,14 +154,12 @@ static const char *__kw_state_names[] = {
static inline u8 __kw_read_reg(struct low_i2c_host *host, reg_t reg)
{
- return in_8(((volatile u8 *)host->base)
- + (((unsigned)reg) << host->bsteps));
+ return in_8(host->base + (((unsigned)reg) << host->bsteps));
}
static inline void __kw_write_reg(struct low_i2c_host *host, reg_t reg, u8 val)
{
- out_8(((volatile u8 *)host->base)
- + (((unsigned)reg) << host->bsteps), val);
+ out_8(host->base + (((unsigned)reg) << host->bsteps), val);
(void)__kw_read_reg(host, reg_subaddr);
}
@@ -370,7 +368,7 @@ static void keywest_low_i2c_add(struct device_node *np)
break;
}
host->mode = pmac_low_i2c_mode_std;
- host->base = (unsigned long)ioremap(np->addrs[0].address + aoffset,
+ host->base = ioremap(np->addrs[0].address + aoffset,
np->addrs[0].size);
host->func = keywest_low_i2c_func;
}
diff --git a/arch/ppc/platforms/pmac_sleep.S b/arch/ppc/platforms/pmac_sleep.S
index 3139b6766ad..f459ade1bd6 100644
--- a/arch/ppc/platforms/pmac_sleep.S
+++ b/arch/ppc/platforms/pmac_sleep.S
@@ -267,6 +267,10 @@ grackle_wake_up:
/* Restore various CPU config stuffs */
bl __restore_cpu_setup
+ /* Make sure all FPRs have been initialized */
+ bl reloc_offset
+ bl __init_fpu_registers
+
/* Invalidate & enable L1 cache, we don't care about
* whatever the ROM may have tried to write to memory
*/
diff --git a/arch/ppc/platforms/pmac_smp.c b/arch/ppc/platforms/pmac_smp.c
index 731841f9a5b..8e049dab4e6 100644
--- a/arch/ppc/platforms/pmac_smp.c
+++ b/arch/ppc/platforms/pmac_smp.c
@@ -91,11 +91,11 @@ extern void __secondary_start_psurge3(void); /* Temporary horrible hack */
#define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
/* virtual addresses for the above */
-static volatile u8 *hhead_base;
-static volatile u8 *quad_base;
-static volatile u32 *psurge_pri_intr;
-static volatile u8 *psurge_sec_intr;
-static volatile u32 *psurge_start;
+static volatile u8 __iomem *hhead_base;
+static volatile u8 __iomem *quad_base;
+static volatile u32 __iomem *psurge_pri_intr;
+static volatile u8 __iomem *psurge_sec_intr;
+static volatile u32 __iomem *psurge_start;
/* values for psurge_type */
#define PSURGE_NONE -1
@@ -322,10 +322,10 @@ static int __init smp_psurge_probe(void)
/* All released cards using this HW design have 4 CPUs */
ncpus = 4;
} else {
- iounmap((void *) quad_base);
+ iounmap(quad_base);
if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
/* not a dual-cpu card */
- iounmap((void *) hhead_base);
+ iounmap(hhead_base);
psurge_type = PSURGE_NONE;
return 1;
}
diff --git a/arch/ppc/platforms/pmac_time.c b/arch/ppc/platforms/pmac_time.c
index 09636546f44..de60ccc7db9 100644
--- a/arch/ppc/platforms/pmac_time.c
+++ b/arch/ppc/platforms/pmac_time.c
@@ -165,7 +165,7 @@ int __init
via_calibrate_decr(void)
{
struct device_node *vias;
- volatile unsigned char *via;
+ volatile unsigned char __iomem *via;
int count = VIA_TIMER_FREQ_6 / 100;
unsigned int dstart, dend;
@@ -176,8 +176,7 @@ via_calibrate_decr(void)
vias = find_devices("via");
if (vias == 0 || vias->n_addrs == 0)
return 0;
- via = (volatile unsigned char *)
- ioremap(vias->addrs[0].address, vias->addrs[0].size);
+ via = ioremap(vias->addrs[0].address, vias->addrs[0].size);
/* set timer 1 for continuous interrupts */
out_8(&via[ACR], (via[ACR] & ~T1MODE) | T1MODE_CONT);
@@ -202,7 +201,7 @@ via_calibrate_decr(void)
printk(KERN_INFO "via_calibrate_decr: ticks per jiffy = %u (%u ticks)\n",
tb_ticks_per_jiffy, dstart - dend);
- iounmap((void*)via);
+ iounmap(via);
return 1;
}
diff --git a/arch/ppc/platforms/radstone_ppc7d.c b/arch/ppc/platforms/radstone_ppc7d.c
index 2a99b43737a..c30607a972d 100644
--- a/arch/ppc/platforms/radstone_ppc7d.c
+++ b/arch/ppc/platforms/radstone_ppc7d.c
@@ -68,6 +68,7 @@
#define PPC7D_RST_PIN 17 /* GPP17 */
extern u32 mv64360_irq_base;
+extern spinlock_t rtc_lock;
static struct mv64x60_handle bh;
static int ppc7d_has_alma;
@@ -75,6 +76,11 @@ static int ppc7d_has_alma;
extern void gen550_progress(char *, unsigned short);
extern void gen550_init(int, struct uart_port *);
+/* FIXME - move to h file */
+extern int ds1337_do_command(int id, int cmd, void *arg);
+#define DS1337_GET_DATE 0
+#define DS1337_SET_DATE 1
+
/* residual data */
unsigned char __res[sizeof(bd_t)];
@@ -253,6 +259,8 @@ static int ppc7d_show_cpuinfo(struct seq_file *m)
u8 val1, val2;
static int flash_sizes[4] = { 64, 32, 0, 16 };
static int flash_banks[4] = { 4, 3, 2, 1 };
+ static int sdram_bank_sizes[4] = { 128, 256, 512, 1 };
+ int sdram_num_banks = 2;
static char *pci_modes[] = { "PCI33", "PCI66",
"Unknown", "Unknown",
"PCIX33", "PCIX66",
@@ -279,13 +287,17 @@ static int ppc7d_show_cpuinfo(struct seq_file *m)
(val1 == PPC7D_CPLD_MB_TYPE_PLL_100) ? 100 :
(val1 == PPC7D_CPLD_MB_TYPE_PLL_64) ? 64 : 0);
+ val = inb(PPC7D_CPLD_MEM_CONFIG);
+ if (val & PPC7D_CPLD_SDRAM_BANK_NUM_MASK) sdram_num_banks--;
+
val = inb(PPC7D_CPLD_MEM_CONFIG_EXTEND);
- val1 = val & PPC7D_CPLD_SDRAM_BANK_SIZE_MASK;
- seq_printf(m, "SDRAM\t\t: %d%c",
- (val1 == PPC7D_CPLD_SDRAM_BANK_SIZE_128M) ? 128 :
- (val1 == PPC7D_CPLD_SDRAM_BANK_SIZE_256M) ? 256 :
- (val1 == PPC7D_CPLD_SDRAM_BANK_SIZE_512M) ? 512 : 1,
- (val1 == PPC7D_CPLD_SDRAM_BANK_SIZE_1G) ? 'G' : 'M');
+ val1 = (val & PPC7D_CPLD_SDRAM_BANK_SIZE_MASK) >> 6;
+ seq_printf(m, "SDRAM\t\t: %d banks of %d%c, total %d%c",
+ sdram_num_banks,
+ sdram_bank_sizes[val1],
+ (sdram_bank_sizes[val1] < 128) ? 'G' : 'M',
+ sdram_num_banks * sdram_bank_sizes[val1],
+ (sdram_bank_sizes[val1] < 128) ? 'G' : 'M');
if (val2 & PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK) {
seq_printf(m, " [ECC %sabled]",
(val2 & PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK) ? "en" :
@@ -1236,6 +1248,38 @@ static void __init ppc7d_setup_arch(void)
printk(KERN_INFO "Radstone Technology PPC7D\n");
if (ppc_md.progress)
ppc_md.progress("ppc7d_setup_arch: exit", 0);
+
+}
+
+/* Real Time Clock support.
+ * PPC7D has a DS1337 accessed by I2C.
+ */
+static ulong ppc7d_get_rtc_time(void)
+{
+ struct rtc_time tm;
+ int result;
+
+ spin_lock(&rtc_lock);
+ result = ds1337_do_command(0, DS1337_GET_DATE, &tm);
+ spin_unlock(&rtc_lock);
+
+ if (result == 0)
+ result = mktime(tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec);
+
+ return result;
+}
+
+static int ppc7d_set_rtc_time(unsigned long nowtime)
+{
+ struct rtc_time tm;
+ int result;
+
+ spin_lock(&rtc_lock);
+ to_tm(nowtime, &tm);
+ result = ds1337_do_command(0, DS1337_SET_DATE, &tm);
+ spin_unlock(&rtc_lock);
+
+ return result;
}
/* This kernel command line parameter can be used to have the target
@@ -1293,6 +1337,10 @@ static void ppc7d_init2(void)
data8 |= 0x07;
outb(data8, PPC7D_CPLD_LEDS);
+ /* Hook up RTC. We couldn't do this earlier because we need the I2C subsystem */
+ ppc_md.set_rtc_time = ppc7d_set_rtc_time;
+ ppc_md.get_rtc_time = ppc7d_get_rtc_time;
+
pr_debug("%s: exit\n", __FUNCTION__);
}
diff --git a/arch/ppc/platforms/radstone_ppc7d.h b/arch/ppc/platforms/radstone_ppc7d.h
index 4546fff2b0c..938375510be 100644
--- a/arch/ppc/platforms/radstone_ppc7d.h
+++ b/arch/ppc/platforms/radstone_ppc7d.h
@@ -240,6 +240,7 @@
#define PPC7D_CPLD_FLASH_CNTL 0x086E
/* MEMORY_CONFIG_EXTEND */
+#define PPC7D_CPLD_SDRAM_BANK_NUM_MASK 0x02
#define PPC7D_CPLD_SDRAM_BANK_SIZE_MASK 0xc0
#define PPC7D_CPLD_SDRAM_BANK_SIZE_128M 0
#define PPC7D_CPLD_SDRAM_BANK_SIZE_256M 0x40
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-03-06 04:25:57 +0000