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-rw-r--r--arch/s390/kernel/head.S2
-rw-r--r--arch/s390/kernel/reipl64.S2
-rw-r--r--arch/s390/kernel/setup.c2
-rw-r--r--arch/s390/kernel/switch_cpu.S4
-rw-r--r--arch/s390/kernel/switch_cpu64.S4
-rw-r--r--arch/s390/kernel/time.c6
-rw-r--r--arch/s390/kernel/vtime.c2
7 files changed, 13 insertions, 9 deletions
diff --git a/arch/s390/kernel/head.S b/arch/s390/kernel/head.S
index 7061398341d..fb317bf2c37 100644
--- a/arch/s390/kernel/head.S
+++ b/arch/s390/kernel/head.S
@@ -460,7 +460,7 @@ startup:
#ifndef CONFIG_MARCH_G5
# check capabilities against MARCH_{G5,Z900,Z990,Z9_109,Z10}
xc __LC_STFL_FAC_LIST(8),__LC_STFL_FAC_LIST
- stfl __LC_STFL_FAC_LIST # store facility list
+ .insn s,0xb2b10000,__LC_STFL_FAC_LIST # store facility list
tm __LC_STFL_FAC_LIST,0x01 # stfle available ?
jz 0f
la %r0,0
diff --git a/arch/s390/kernel/reipl64.S b/arch/s390/kernel/reipl64.S
index 5e73dee63ba..9eabbc90795 100644
--- a/arch/s390/kernel/reipl64.S
+++ b/arch/s390/kernel/reipl64.S
@@ -78,7 +78,7 @@ do_reipl_asm: basr %r13,0
* in the ESA psw.
* Bit 31 of the addresses has to be 0 for the
* 31bit lpswe instruction a fact they appear to have
- * ommited from the pop.
+ * omitted from the pop.
*/
.Lnewpsw: .quad 0x0000000080000000
.quad .Lpg1
diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
index ed183c2c616..f5434d1ecb3 100644
--- a/arch/s390/kernel/setup.c
+++ b/arch/s390/kernel/setup.c
@@ -708,7 +708,7 @@ static void __init setup_hwcaps(void)
* and 1ULL<<0 as bit 63. Bits 0-31 contain the same information
* as stored by stfl, bits 32-xxx contain additional facilities.
* How many facility words are stored depends on the number of
- * doublewords passed to the instruction. The additional facilites
+ * doublewords passed to the instruction. The additional facilities
* are:
* Bit 42: decimal floating point facility is installed
* Bit 44: perform floating point operation facility is installed
diff --git a/arch/s390/kernel/switch_cpu.S b/arch/s390/kernel/switch_cpu.S
index 469f11b574f..20530dd2eab 100644
--- a/arch/s390/kernel/switch_cpu.S
+++ b/arch/s390/kernel/switch_cpu.S
@@ -46,7 +46,9 @@ smp_restart_cpu:
ltr %r4,%r4 /* New stack ? */
jz 1f
lr %r15,%r4
-1: basr %r14,%r2
+1: lr %r14,%r2 /* r14: Function to call */
+ lr %r2,%r3 /* r2 : Parameter for function*/
+ basr %r14,%r14 /* Call function */
.gprregs_addr:
.long .gprregs
diff --git a/arch/s390/kernel/switch_cpu64.S b/arch/s390/kernel/switch_cpu64.S
index d94aacc898c..5be3f43898f 100644
--- a/arch/s390/kernel/switch_cpu64.S
+++ b/arch/s390/kernel/switch_cpu64.S
@@ -42,7 +42,9 @@ smp_restart_cpu:
ltgr %r4,%r4 /* New stack ? */
jz 1f
lgr %r15,%r4
-1: basr %r14,%r2
+1: lgr %r14,%r2 /* r14: Function to call */
+ lgr %r2,%r3 /* r2 : Parameter for function*/
+ basr %r14,%r14 /* Call function */
.section .data,"aw",@progbits
.gprregs:
diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c
index 9e7b039458d..87be655557a 100644
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -724,7 +724,7 @@ static void clock_sync_cpu(struct clock_sync_data *sync)
}
/*
- * Sync the TOD clock using the port refered to by aibp. This port
+ * Sync the TOD clock using the port referred to by aibp. This port
* has to be enabled and the other port has to be disabled. The
* last eacr update has to be more than 1.6 seconds in the past.
*/
@@ -1012,7 +1012,7 @@ static void etr_work_fn(struct work_struct *work)
eacr = etr_handle_update(&aib, eacr);
/*
- * Select ports to enable. The prefered synchronization mode is PPS.
+ * Select ports to enable. The preferred synchronization mode is PPS.
* If a port can be enabled depends on a number of things:
* 1) The port needs to be online and uptodate. A port is not
* disabled just because it is not uptodate, but it is only
@@ -1091,7 +1091,7 @@ static void etr_work_fn(struct work_struct *work)
/*
* Update eacr and try to synchronize the clock. If the update
* of eacr caused a stepping port switch (or if we have to
- * assume that a stepping port switch has occured) or the
+ * assume that a stepping port switch has occurred) or the
* clock syncing failed, reset the sync check control bit
* and set up a timer to try again after 0.5 seconds
*/
diff --git a/arch/s390/kernel/vtime.c b/arch/s390/kernel/vtime.c
index 1ccdf4d8aa8..5e8ead4b4ab 100644
--- a/arch/s390/kernel/vtime.c
+++ b/arch/s390/kernel/vtime.c
@@ -44,7 +44,7 @@ static inline void set_vtimer(__u64 expires)
__u64 timer;
asm volatile (" STPT %0\n" /* Store current cpu timer value */
- " SPT %1" /* Set new value immediatly afterwards */
+ " SPT %1" /* Set new value immediately afterwards */
: "=m" (timer) : "m" (expires) );
S390_lowcore.system_timer += S390_lowcore.last_update_timer - timer;
S390_lowcore.last_update_timer = expires;