diff options
Diffstat (limited to 'arch/sh/boards/mach-microdev')
| -rw-r--r-- | arch/sh/boards/mach-microdev/Makefile | 5 | ||||
| -rw-r--r-- | arch/sh/boards/mach-microdev/fdc37c93xapm.c | 160 | ||||
| -rw-r--r-- | arch/sh/boards/mach-microdev/irq.c | 36 | ||||
| -rw-r--r-- | arch/sh/boards/mach-microdev/led.c | 101 | ||||
| -rw-r--r-- | arch/sh/boards/mach-microdev/setup.c | 196 |
5 files changed, 174 insertions, 324 deletions
diff --git a/arch/sh/boards/mach-microdev/Makefile b/arch/sh/boards/mach-microdev/Makefile index 1387dd6c85e..4e3588e8806 100644 --- a/arch/sh/boards/mach-microdev/Makefile +++ b/arch/sh/boards/mach-microdev/Makefile @@ -2,7 +2,4 @@ # Makefile for the SuperH MicroDev specific parts of the kernel # -obj-y := setup.o irq.o io.o - -obj-$(CONFIG_HEARTBEAT) += led.o - +obj-y := setup.o irq.o io.o fdc37c93xapm.o diff --git a/arch/sh/boards/mach-microdev/fdc37c93xapm.c b/arch/sh/boards/mach-microdev/fdc37c93xapm.c new file mode 100644 index 00000000000..458a7cf5fb4 --- /dev/null +++ b/arch/sh/boards/mach-microdev/fdc37c93xapm.c @@ -0,0 +1,160 @@ +/* + * + * Setup for the SMSC FDC37C93xAPM + * + * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) + * Copyright (C) 2003, 2004 SuperH, Inc. + * Copyright (C) 2004, 2005 Paul Mundt + * + * SuperH SH4-202 MicroDev board support. + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + */ +#include <linux/init.h> +#include <linux/ioport.h> +#include <linux/io.h> +#include <linux/err.h> +#include <mach/microdev.h> + +#define SMSC_CONFIG_PORT_ADDR (0x3F0) +#define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR +#define SMSC_DATA_PORT_ADDR (SMSC_INDEX_PORT_ADDR + 1) + +#define SMSC_ENTER_CONFIG_KEY 0x55 +#define SMSC_EXIT_CONFIG_KEY 0xaa + +#define SMCS_LOGICAL_DEV_INDEX 0x07 /* Logical Device Number */ +#define SMSC_DEVICE_ID_INDEX 0x20 /* Device ID */ +#define SMSC_DEVICE_REV_INDEX 0x21 /* Device Revision */ +#define SMSC_ACTIVATE_INDEX 0x30 /* Activate */ +#define SMSC_PRIMARY_BASE_INDEX 0x60 /* Primary Base Address */ +#define SMSC_SECONDARY_BASE_INDEX 0x62 /* Secondary Base Address */ +#define SMSC_PRIMARY_INT_INDEX 0x70 /* Primary Interrupt Select */ +#define SMSC_SECONDARY_INT_INDEX 0x72 /* Secondary Interrupt Select */ +#define SMSC_HDCS0_INDEX 0xf0 /* HDCS0 Address Decoder */ +#define SMSC_HDCS1_INDEX 0xf1 /* HDCS1 Address Decoder */ + +#define SMSC_IDE1_DEVICE 1 /* IDE #1 logical device */ +#define SMSC_IDE2_DEVICE 2 /* IDE #2 logical device */ +#define SMSC_PARALLEL_DEVICE 3 /* Parallel Port logical device */ +#define SMSC_SERIAL1_DEVICE 4 /* Serial #1 logical device */ +#define SMSC_SERIAL2_DEVICE 5 /* Serial #2 logical device */ +#define SMSC_KEYBOARD_DEVICE 7 /* Keyboard logical device */ +#define SMSC_CONFIG_REGISTERS 8 /* Configuration Registers (Aux I/O) */ + +#define SMSC_READ_INDEXED(index) ({ \ + outb((index), SMSC_INDEX_PORT_ADDR); \ + inb(SMSC_DATA_PORT_ADDR); }) +#define SMSC_WRITE_INDEXED(val, index) ({ \ + outb((index), SMSC_INDEX_PORT_ADDR); \ + outb((val), SMSC_DATA_PORT_ADDR); }) + +#define IDE1_PRIMARY_BASE 0x01f0 /* Task File Registe base for IDE #1 */ +#define IDE1_SECONDARY_BASE 0x03f6 /* Miscellaneous AT registers for IDE #1 */ +#define IDE2_PRIMARY_BASE 0x0170 /* Task File Registe base for IDE #2 */ +#define IDE2_SECONDARY_BASE 0x0376 /* Miscellaneous AT registers for IDE #2 */ + +#define SERIAL1_PRIMARY_BASE 0x03f8 +#define SERIAL2_PRIMARY_BASE 0x02f8 + +#define MSB(x) ( (x) >> 8 ) +#define LSB(x) ( (x) & 0xff ) + + /* General-Purpose base address on CPU-board FPGA */ +#define MICRODEV_FPGA_GP_BASE 0xa6100000ul + +static int __init smsc_superio_setup(void) +{ + + unsigned char devid, devrev; + + /* Initially the chip is in run state */ + /* Put it into configuration state */ + outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); + + /* Read device ID info */ + devid = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX); + devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX); + + if ((devid == 0x30) && (devrev == 0x01)) + printk("SMSC FDC37C93xAPM SuperIO device detected\n"); + else + return -ENODEV; + + /* Select the keyboard device */ + SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX); + /* enable it */ + SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); + /* enable the interrupts */ + SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX); + SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX); + + /* Select the Serial #1 device */ + SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX); + /* enable it */ + SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); + /* program with port addresses */ + SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); + SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); + SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX); + /* enable the interrupts */ + SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX); + + /* Select the Serial #2 device */ + SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX); + /* enable it */ + SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); + /* program with port addresses */ + SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); + SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); + SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX); + /* enable the interrupts */ + SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX); + + /* Select the IDE#1 device */ + SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX); + /* enable it */ + SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); + /* program with port addresses */ + SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); + SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); + SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0); + SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1); + SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX); + SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX); + /* select the interrupt */ + SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX); + + /* Select the IDE#2 device */ + SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX); + /* enable it */ + SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); + /* program with port addresses */ + SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); + SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); + SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0); + SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1); + /* select the interrupt */ + SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX); + + /* Select the configuration registers */ + SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX); + /* enable the appropriate GPIO pins for IDE functionality: + * bit[0] In/Out 1==input; 0==output + * bit[1] Polarity 1==invert; 0==no invert + * bit[2] Int Enb #1 1==Enable Combined IRQ #1; 0==disable + * bit[3:4] Function Select 00==original; 01==Alternate Function #1 + */ + SMSC_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */ + SMSC_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */ + SMSC_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */ + SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */ + SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */ + + /* Exit the configuration state */ + outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); + + return 0; +} +device_initcall(smsc_superio_setup); diff --git a/arch/sh/boards/mach-microdev/irq.c b/arch/sh/boards/mach-microdev/irq.c index 702753cbd28..b551963579c 100644 --- a/arch/sh/boards/mach-microdev/irq.c +++ b/arch/sh/boards/mach-microdev/irq.c @@ -67,27 +67,13 @@ static const struct { static void enable_microdev_irq(unsigned int irq); static void disable_microdev_irq(unsigned int irq); - - /* shutdown is same as "disable" */ -#define shutdown_microdev_irq disable_microdev_irq - static void mask_and_ack_microdev(unsigned int); -static void end_microdev_irq(unsigned int irq); - -static unsigned int startup_microdev_irq(unsigned int irq) -{ - enable_microdev_irq(irq); - return 0; /* never anything pending */ -} -static struct hw_interrupt_type microdev_irq_type = { - .typename = "MicroDev-IRQ", - .startup = startup_microdev_irq, - .shutdown = shutdown_microdev_irq, - .enable = enable_microdev_irq, - .disable = disable_microdev_irq, +static struct irq_chip microdev_irq_type = { + .name = "MicroDev-IRQ", + .unmask = enable_microdev_irq, + .mask = disable_microdev_irq, .ack = mask_and_ack_microdev, - .end = end_microdev_irq }; static void disable_microdev_irq(unsigned int irq) @@ -130,11 +116,11 @@ static void enable_microdev_irq(unsigned int irq) ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG); } - /* This functions sets the desired irq handler to be a MicroDev type */ +/* This function sets the desired irq handler to be a MicroDev type */ static void __init make_microdev_irq(unsigned int irq) { disable_irq_nosync(irq); - irq_desc[irq].chip = µdev_irq_type; + set_irq_chip_and_handler(irq, µdev_irq_type, handle_level_irq); disable_microdev_irq(irq); } @@ -143,17 +129,11 @@ static void mask_and_ack_microdev(unsigned int irq) disable_microdev_irq(irq); } -static void end_microdev_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_microdev_irq(irq); -} - extern void __init init_microdev_irq(void) { int i; - /* disable interrupts on the FPGA INTC register */ + /* disable interrupts on the FPGA INTC register */ ctrl_outl(~0ul, MICRODEV_FPGA_INTDSB_REG); for (i = 0; i < NUM_EXTERNAL_IRQS; i++) @@ -179,5 +159,3 @@ extern void microdev_print_fpga_intc_status(void) printk("FPGA_INTPRI[3..0] = %08x:%08x:%08x:%08x\n", *intprid, *intpric, *intprib, *intpria); printk("-------------------------------------------------------------------------------\n"); } - - diff --git a/arch/sh/boards/mach-microdev/led.c b/arch/sh/boards/mach-microdev/led.c deleted file mode 100644 index 36e54b47a75..00000000000 --- a/arch/sh/boards/mach-microdev/led.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * linux/arch/sh/boards/superh/microdev/led.c - * - * Copyright (C) 2002 Stuart Menefy <stuart.menefy@st.com> - * Copyright (C) 2003 Richard Curnow (Richard.Curnow@superh.com) - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - */ - -#include <asm/io.h> - -#define LED_REGISTER 0xa6104d20 - -static void mach_led_d9(int value) -{ - unsigned long reg; - reg = ctrl_inl(LED_REGISTER); - reg &= ~1; - reg |= (value & 1); - ctrl_outl(reg, LED_REGISTER); - return; -} - -static void mach_led_d10(int value) -{ - unsigned long reg; - reg = ctrl_inl(LED_REGISTER); - reg &= ~2; - reg |= ((value & 1) << 1); - ctrl_outl(reg, LED_REGISTER); - return; -} - - -#ifdef CONFIG_HEARTBEAT -#include <linux/sched.h> - -static unsigned char banner_table[] = { - 0x11, 0x01, 0x11, 0x01, 0x11, 0x03, - 0x11, 0x01, 0x11, 0x01, 0x13, 0x03, - 0x11, 0x01, 0x13, 0x01, 0x13, 0x01, 0x11, 0x03, - 0x11, 0x03, - 0x11, 0x01, 0x13, 0x01, 0x11, 0x03, - 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x11, 0x07, - 0x13, 0x01, 0x13, 0x03, - 0x11, 0x01, 0x11, 0x03, - 0x13, 0x01, 0x11, 0x01, 0x13, 0x01, 0x11, 0x03, - 0x11, 0x01, 0x13, 0x01, 0x11, 0x03, - 0x13, 0x01, 0x13, 0x01, 0x13, 0x03, - 0x13, 0x01, 0x11, 0x01, 0x11, 0x03, - 0x11, 0x03, - 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x13, 0x07, - 0xff -}; - -static void banner(void) -{ - static int pos = 0; - static int count = 0; - - if (count) { - count--; - } else { - int val = banner_table[pos]; - if (val == 0xff) { - pos = 0; - val = banner_table[pos]; - } - pos++; - mach_led_d10((val >> 4) & 1); - count = 10 * (val & 0xf); - } -} - -/* From heartbeat_harp in the stboards directory */ -/* acts like an actual heart beat -- ie thump-thump-pause... */ -void microdev_heartbeat(void) -{ - static unsigned cnt = 0, period = 0, dist = 0; - - if (cnt == 0 || cnt == dist) - mach_led_d9(1); - else if (cnt == 7 || cnt == dist+7) - mach_led_d9(0); - - if (++cnt > period) { - cnt = 0; - /* The hyperbolic function below modifies the heartbeat period - * length in dependency of the current (5min) load. It goes - * through the points f(0)=126, f(1)=86, f(5)=51, - * f(inf)->30. */ - period = ((672<<FSHIFT)/(5*avenrun[0]+(7<<FSHIFT))) + 30; - dist = period / 4; - } - - banner(); -} - -#endif diff --git a/arch/sh/boards/mach-microdev/setup.c b/arch/sh/boards/mach-microdev/setup.c index a9202fe3cb5..d1df2a4fb9b 100644 --- a/arch/sh/boards/mach-microdev/setup.c +++ b/arch/sh/boards/mach-microdev/setup.c @@ -17,70 +17,12 @@ #include <mach/microdev.h> #include <asm/io.h> #include <asm/machvec.h> - -extern void microdev_heartbeat(void); - - -/****************************************************************************/ - - - /* - * Setup for the SMSC FDC37C93xAPM - */ -#define SMSC_CONFIG_PORT_ADDR (0x3F0) -#define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR -#define SMSC_DATA_PORT_ADDR (SMSC_INDEX_PORT_ADDR + 1) - -#define SMSC_ENTER_CONFIG_KEY 0x55 -#define SMSC_EXIT_CONFIG_KEY 0xaa - -#define SMCS_LOGICAL_DEV_INDEX 0x07 /* Logical Device Number */ -#define SMSC_DEVICE_ID_INDEX 0x20 /* Device ID */ -#define SMSC_DEVICE_REV_INDEX 0x21 /* Device Revision */ -#define SMSC_ACTIVATE_INDEX 0x30 /* Activate */ -#define SMSC_PRIMARY_BASE_INDEX 0x60 /* Primary Base Address */ -#define SMSC_SECONDARY_BASE_INDEX 0x62 /* Secondary Base Address */ -#define SMSC_PRIMARY_INT_INDEX 0x70 /* Primary Interrupt Select */ -#define SMSC_SECONDARY_INT_INDEX 0x72 /* Secondary Interrupt Select */ -#define SMSC_HDCS0_INDEX 0xf0 /* HDCS0 Address Decoder */ -#define SMSC_HDCS1_INDEX 0xf1 /* HDCS1 Address Decoder */ - -#define SMSC_IDE1_DEVICE 1 /* IDE #1 logical device */ -#define SMSC_IDE2_DEVICE 2 /* IDE #2 logical device */ -#define SMSC_PARALLEL_DEVICE 3 /* Parallel Port logical device */ -#define SMSC_SERIAL1_DEVICE 4 /* Serial #1 logical device */ -#define SMSC_SERIAL2_DEVICE 5 /* Serial #2 logical device */ -#define SMSC_KEYBOARD_DEVICE 7 /* Keyboard logical device */ -#define SMSC_CONFIG_REGISTERS 8 /* Configuration Registers (Aux I/O) */ - -#define SMSC_READ_INDEXED(index) ({ \ - outb((index), SMSC_INDEX_PORT_ADDR); \ - inb(SMSC_DATA_PORT_ADDR); }) -#define SMSC_WRITE_INDEXED(val, index) ({ \ - outb((index), SMSC_INDEX_PORT_ADDR); \ - outb((val), SMSC_DATA_PORT_ADDR); }) - -#define IDE1_PRIMARY_BASE 0x01f0 /* Task File Registe base for IDE #1 */ -#define IDE1_SECONDARY_BASE 0x03f6 /* Miscellaneous AT registers for IDE #1 */ -#define IDE2_PRIMARY_BASE 0x0170 /* Task File Registe base for IDE #2 */ -#define IDE2_SECONDARY_BASE 0x0376 /* Miscellaneous AT registers for IDE #2 */ - -#define SERIAL1_PRIMARY_BASE 0x03f8 -#define SERIAL2_PRIMARY_BASE 0x02f8 - -#define MSB(x) ( (x) >> 8 ) -#define LSB(x) ( (x) & 0xff ) - - /* General-Purpose base address on CPU-board FPGA */ -#define MICRODEV_FPGA_GP_BASE 0xa6100000ul - - /* assume a Keyboard Controller is present */ -int microdev_kbd_controller_present = 1; +#include <asm/sizes.h> static struct resource smc91x_resources[] = { [0] = { .start = 0x300, - .end = 0x300 + 0x0001000 - 1, + .end = 0x300 + SZ_4K - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -97,7 +39,6 @@ static struct platform_device smc91x_device = { .resource = smc91x_resources, }; -#ifdef CONFIG_FB_S1D13XXX static struct s1d13xxxfb_regval s1d13806_initregs[] = { { S1DREG_MISC, 0x00 }, { S1DREG_COM_DISP_MODE, 0x00 }, @@ -216,12 +157,12 @@ static struct s1d13xxxfb_pdata s1d13806_platform_data = { static struct resource s1d13806_resources[] = { [0] = { .start = 0x07200000, - .end = 0x07200000 + 0x00200000 - 1, + .end = 0x07200000 + SZ_2M - 1, .flags = IORESOURCE_MEM, }, [1] = { .start = 0x07000000, - .end = 0x07000000 + 0x00200000 - 1, + .end = 0x07000000 + SZ_2M - 1, .flags = IORESOURCE_MEM, }, }; @@ -236,145 +177,24 @@ static struct platform_device s1d13806_device = { .platform_data = &s1d13806_platform_data, }, }; -#endif static struct platform_device *microdev_devices[] __initdata = { &smc91x_device, -#ifdef CONFIG_FB_S1D13XXX &s1d13806_device, -#endif }; static int __init microdev_devices_setup(void) { return platform_add_devices(microdev_devices, ARRAY_SIZE(microdev_devices)); } - -/* - * Setup for the SMSC FDC37C93xAPM - */ -static int __init smsc_superio_setup(void) -{ - - unsigned char devid, devrev; - - /* Initially the chip is in run state */ - /* Put it into configuration state */ - outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); - - /* Read device ID info */ - devid = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX); - devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX); - if ( (devid==0x30) && (devrev==0x01) ) - { - printk("SMSC FDC37C93xAPM SuperIO device detected\n"); - } - else - { /* not the device identity we expected */ - printk("Not detected a SMSC FDC37C93xAPM SuperIO device (devid=0x%02x, rev=0x%02x)\n", - devid, devrev); - /* inform the keyboard driver that we have no keyboard controller */ - microdev_kbd_controller_present = 0; - /* little point in doing anything else in this functon */ - return 0; - } - - /* Select the keyboard device */ - SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX); - /* enable it */ - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); - /* enable the interrupts */ - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX); - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX); - - /* Select the Serial #1 device */ - SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX); - /* enable it */ - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); - /* program with port addresses */ - SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); - SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); - SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX); - /* enable the interrupts */ - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX); - - /* Select the Serial #2 device */ - SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX); - /* enable it */ - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); - /* program with port addresses */ - SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); - SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); - SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX); - /* enable the interrupts */ - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX); - - /* Select the IDE#1 device */ - SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX); - /* enable it */ - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); - /* program with port addresses */ - SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); - SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); - SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0); - SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1); - SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX); - SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX); - /* select the interrupt */ - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX); - - /* Select the IDE#2 device */ - SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX); - /* enable it */ - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); - /* program with port addresses */ - SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); - SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); - SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0); - SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1); - /* select the interrupt */ - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX); - - /* Select the configuration registers */ - SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX); - /* enable the appropriate GPIO pins for IDE functionality: - * bit[0] In/Out 1==input; 0==output - * bit[1] Polarity 1==invert; 0==no invert - * bit[2] Int Enb #1 1==Enable Combined IRQ #1; 0==disable - * bit[3:4] Function Select 00==original; 01==Alternate Function #1 - */ - SMSC_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */ - SMSC_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */ - SMSC_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */ - SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */ - SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */ - - /* Exit the configuration state */ - outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); - - return 0; -} - -static void __init microdev_setup(char **cmdline_p) -{ - int * const fpgaRevisionRegister = (int*)(MICRODEV_FPGA_GP_BASE + 0x8ul); - const int fpgaRevision = *fpgaRevisionRegister; - int * const CacheControlRegister = (int*)CCR; - - device_initcall(microdev_devices_setup); - device_initcall(smsc_superio_setup); - - printk("SuperH %s board (FPGA rev: 0x%0x, CCR: 0x%0x)\n", - get_system_type(), fpgaRevision, *CacheControlRegister); -} +device_initcall(microdev_devices_setup); /* * The Machine Vector */ static struct sh_machine_vector mv_sh4202_microdev __initmv = { .mv_name = "SH4-202 MicroDev", - .mv_setup = microdev_setup, - .mv_nr_irqs = 72, /* QQQ need to check this - use the MACRO */ + .mv_nr_irqs = 72, .mv_inb = microdev_inb, .mv_inw = microdev_inw, @@ -398,8 +218,4 @@ static struct sh_machine_vector mv_sh4202_microdev __initmv = { .mv_outsl = microdev_outsl, .mv_init_irq = init_microdev_irq, - -#ifdef CONFIG_HEARTBEAT - .mv_heartbeat = microdev_heartbeat, -#endif }; |