diff options
Diffstat (limited to 'arch/sh/kernel')
43 files changed, 1905 insertions, 682 deletions
diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile index 9104b625764..1f141a8ba17 100644 --- a/arch/sh/kernel/Makefile +++ b/arch/sh/kernel/Makefile @@ -4,10 +4,9 @@ extra-y := head.o init_task.o vmlinux.lds -obj-y := process.o signal.o traps.o irq.o \ - ptrace.o setup.o time.o sys_sh.o semaphore.o \ - io.o io_generic.o sh_ksyms.o syscalls.o \ - debugtraps.o +obj-y := debugtraps.o io.o io_generic.o irq.o machvec.o process.o ptrace.o \ + semaphore.o setup.o signal.o sys_sh.o syscalls.o \ + time.o topology.o traps.o obj-y += cpu/ timers/ obj-$(CONFIG_VSYSCALL) += vsyscall/ @@ -17,7 +16,7 @@ obj-$(CONFIG_CF_ENABLER) += cf-enabler.o obj-$(CONFIG_SH_STANDARD_BIOS) += sh_bios.o obj-$(CONFIG_SH_KGDB) += kgdb_stub.o kgdb_jmp.o obj-$(CONFIG_SH_CPU_FREQ) += cpufreq.o -obj-$(CONFIG_MODULES) += module.o +obj-$(CONFIG_MODULES) += sh_ksyms.o module.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o obj-$(CONFIG_CRASH_DUMP) += crash_dump.o diff --git a/arch/sh/kernel/cf-enabler.c b/arch/sh/kernel/cf-enabler.c index ebc73b85094..1c3b99642e1 100644 --- a/arch/sh/kernel/cf-enabler.c +++ b/arch/sh/kernel/cf-enabler.c @@ -75,11 +75,7 @@ static int __init cf_init_default(void) #if defined(CONFIG_CPU_SH4) allocate_cf_area(); #endif -#if defined(CONFIG_SH_UNKNOWN) - /* This should be done in each board's init_xxx_irq. */ - make_imask_irq(14); - disable_irq(14); -#endif + return 0; } diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c index 63251549e9a..92807ffa8e2 100644 --- a/arch/sh/kernel/cpu/clock.c +++ b/arch/sh/kernel/cpu/clock.c @@ -229,6 +229,22 @@ void clk_recalc_rate(struct clk *clk) } EXPORT_SYMBOL_GPL(clk_recalc_rate); +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (likely(clk->ops && clk->ops->round_rate)) { + unsigned long flags, rounded; + + spin_lock_irqsave(&clock_lock, flags); + rounded = clk->ops->round_rate(clk, rate); + spin_unlock_irqrestore(&clock_lock, flags); + + return rounded; + } + + return clk_get_rate(clk); +} +EXPORT_SYMBOL_GPL(clk_round_rate); + /* * Returns a clock. Note that we first try to use device id on the bus * and clock name. If this fails, we try to use clock name only. diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c index 6451ad63017..9172e97dc26 100644 --- a/arch/sh/kernel/cpu/init.c +++ b/arch/sh/kernel/cpu/init.c @@ -21,8 +21,7 @@ #include <asm/cacheflush.h> #include <asm/cache.h> #include <asm/io.h> - -extern void detect_cpu_and_cache_system(void); +#include <asm/ubc.h> /* * Generic wrapper for command line arguments to disable on-chip @@ -152,15 +151,6 @@ static void __init cache_init(void) flags |= CCR_CACHE_CB; #endif -#ifdef CONFIG_SH_OCRAM - /* Turn on OCRAM -- halve the OC */ - flags |= CCR_CACHE_ORA; - current_cpu_data.dcache.sets >>= 1; - - current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * - current_cpu_data.dcache.linesz; -#endif - ctrl_outl(flags, CCR); back_to_P1(); } @@ -269,7 +259,6 @@ asmlinkage void __init sh_cpu_init(void) } #endif -#ifdef CONFIG_UBC_WAKEUP /* * Some brain-damaged loaders decided it would be a good idea to put * the UBC to sleep. This causes some issues when it comes to things @@ -277,7 +266,5 @@ asmlinkage void __init sh_cpu_init(void) * we wake it up and hope that all is well. */ ubc_wakeup(); -#endif - speculative_execution_init(); } diff --git a/arch/sh/kernel/cpu/irq/Makefile b/arch/sh/kernel/cpu/irq/Makefile index 1c23308cfc2..9ddb446ac93 100644 --- a/arch/sh/kernel/cpu/irq/Makefile +++ b/arch/sh/kernel/cpu/irq/Makefile @@ -6,4 +6,5 @@ obj-y += imask.o obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o obj-$(CONFIG_CPU_HAS_PINT_IRQ) += pint.o obj-$(CONFIG_CPU_HAS_MASKREG_IRQ) += maskreg.o +obj-$(CONFIG_CPU_HAS_INTC_IRQ) += intc.o obj-$(CONFIG_CPU_HAS_INTC2_IRQ) += intc2.o diff --git a/arch/sh/kernel/cpu/irq/intc.c b/arch/sh/kernel/cpu/irq/intc.c new file mode 100644 index 00000000000..9345a7130e9 --- /dev/null +++ b/arch/sh/kernel/cpu/irq/intc.c @@ -0,0 +1,405 @@ +/* + * Shared interrupt handling code for IPR and INTC2 types of IRQs. + * + * Copyright (C) 2007 Magnus Damm + * + * Based on intc2.c and ipr.c + * + * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi + * Copyright (C) 2000 Kazumoto Kojima + * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) + * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> + * Copyright (C) 2005, 2006 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/module.h> +#include <linux/io.h> +#include <linux/interrupt.h> + +#define _INTC_MK(fn, idx, bit, value) \ + ((fn) << 24 | ((value) << 16) | ((idx) << 8) | (bit)) +#define _INTC_FN(h) (h >> 24) +#define _INTC_VALUE(h) ((h >> 16) & 0xff) +#define _INTC_IDX(h) ((h >> 8) & 0xff) +#define _INTC_BIT(h) (h & 0xff) + +#define _INTC_PTR(desc, member, data) \ + (desc->member + _INTC_IDX(data)) + +static inline struct intc_desc *get_intc_desc(unsigned int irq) +{ + struct irq_chip *chip = get_irq_chip(irq); + return (void *)((char *)chip - offsetof(struct intc_desc, chip)); +} + +static inline unsigned int set_field(unsigned int value, + unsigned int field_value, + unsigned int width, + unsigned int shift) +{ + value &= ~(((1 << width) - 1) << shift); + value |= field_value << shift; + return value; +} + +static inline unsigned int set_prio_field(struct intc_desc *desc, + unsigned int value, + unsigned int priority, + unsigned int data) +{ + unsigned int width = _INTC_PTR(desc, prio_regs, data)->field_width; + + return set_field(value, priority, width, _INTC_BIT(data)); +} + +static void disable_prio_16(struct intc_desc *desc, unsigned int data) +{ + unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg; + + ctrl_outw(set_prio_field(desc, ctrl_inw(addr), 0, data), addr); +} + +static void enable_prio_16(struct intc_desc *desc, unsigned int data) +{ + unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg; + unsigned int prio = _INTC_VALUE(data); + + ctrl_outw(set_prio_field(desc, ctrl_inw(addr), prio, data), addr); +} + +static void disable_prio_32(struct intc_desc *desc, unsigned int data) +{ + unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg; + + ctrl_outl(set_prio_field(desc, ctrl_inl(addr), 0, data), addr); +} + +static void enable_prio_32(struct intc_desc *desc, unsigned int data) +{ + unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg; + unsigned int prio = _INTC_VALUE(data); + + ctrl_outl(set_prio_field(desc, ctrl_inl(addr), prio, data), addr); +} + +static void disable_mask_8(struct intc_desc *desc, unsigned int data) +{ + ctrl_outb(1 << _INTC_BIT(data), + _INTC_PTR(desc, mask_regs, data)->set_reg); +} + +static void enable_mask_8(struct intc_desc *desc, unsigned int data) +{ + ctrl_outb(1 << _INTC_BIT(data), + _INTC_PTR(desc, mask_regs, data)->clr_reg); +} + +static void disable_mask_32(struct intc_desc *desc, unsigned int data) +{ + ctrl_outl(1 << _INTC_BIT(data), + _INTC_PTR(desc, mask_regs, data)->set_reg); +} + +static void enable_mask_32(struct intc_desc *desc, unsigned int data) +{ + ctrl_outl(1 << _INTC_BIT(data), + _INTC_PTR(desc, mask_regs, data)->clr_reg); +} + +enum { REG_FN_ERROR=0, + REG_FN_MASK_8, REG_FN_MASK_32, + REG_FN_PRIO_16, REG_FN_PRIO_32 }; + +static struct { + void (*enable)(struct intc_desc *, unsigned int); + void (*disable)(struct intc_desc *, unsigned int); +} intc_reg_fns[] = { + [REG_FN_MASK_8] = { enable_mask_8, disable_mask_8 }, + [REG_FN_MASK_32] = { enable_mask_32, disable_mask_32 }, + [REG_FN_PRIO_16] = { enable_prio_16, disable_prio_16 }, + [REG_FN_PRIO_32] = { enable_prio_32, disable_prio_32 }, +}; + +static void intc_enable(unsigned int irq) +{ + struct intc_desc *desc = get_intc_desc(irq); + unsigned int data = (unsigned int) get_irq_chip_data(irq); + + intc_reg_fns[_INTC_FN(data)].enable(desc, data); +} + +static void intc_disable(unsigned int irq) +{ + struct intc_desc *desc = get_intc_desc(irq); + unsigned int data = (unsigned int) get_irq_chip_data(irq); + + intc_reg_fns[_INTC_FN(data)].disable(desc, data); +} + +static void set_sense_16(struct intc_desc *desc, unsigned int data) +{ + unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg; + unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width; + unsigned int bit = _INTC_BIT(data); + unsigned int value = _INTC_VALUE(data); + + ctrl_outw(set_field(ctrl_inw(addr), value, width, bit), addr); +} + +static void set_sense_32(struct intc_desc *desc, unsigned int data) +{ + unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg; + unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width; + unsigned int bit = _INTC_BIT(data); + unsigned int value = _INTC_VALUE(data); + + ctrl_outl(set_field(ctrl_inl(addr), value, width, bit), addr); +} + +#define VALID(x) (x | 0x80) + +static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = { + [IRQ_TYPE_EDGE_FALLING] = VALID(0), + [IRQ_TYPE_EDGE_RISING] = VALID(1), + [IRQ_TYPE_LEVEL_LOW] = VALID(2), + [IRQ_TYPE_LEVEL_HIGH] = VALID(3), +}; + +static int intc_set_sense(unsigned int irq, unsigned int type) +{ + struct intc_desc *desc = get_intc_desc(irq); + unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK]; + unsigned int i, j, data, bit; + intc_enum enum_id = 0; + + for (i = 0; i < desc->nr_vectors; i++) { + struct intc_vect *vect = desc->vectors + i; + + if (evt2irq(vect->vect) != irq) + continue; + + enum_id = vect->enum_id; + break; + } + + if (!enum_id || !value) + return -EINVAL; + + value ^= VALID(0); + + for (i = 0; i < desc->nr_sense_regs; i++) { + struct intc_sense_reg *sr = desc->sense_regs + i; + + for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) { + if (sr->enum_ids[j] != enum_id) + continue; + + bit = sr->reg_width - ((j + 1) * sr->field_width); + data = _INTC_MK(0, i, bit, value); + + switch(sr->reg_width) { + case 16: + set_sense_16(desc, data); + break; + case 32: + set_sense_32(desc, data); + break; + } + + return 0; + } + } + + return -EINVAL; +} + +static unsigned int __init intc_find_mask_handler(unsigned int width) +{ + switch (width) { + case 8: + return REG_FN_MASK_8; + case 32: + return REG_FN_MASK_32; + } + + BUG(); + return REG_FN_ERROR; +} + +static unsigned int __init intc_find_prio_handler(unsigned int width) +{ + switch (width) { + case 16: + return REG_FN_PRIO_16; + case 32: + return REG_FN_PRIO_32; + } + + BUG(); + return REG_FN_ERROR; +} + +static intc_enum __init intc_grp_id(struct intc_desc *desc, intc_enum enum_id) +{ + struct intc_group *g = desc->groups; + unsigned int i, j; + + for (i = 0; g && enum_id && i < desc->nr_groups; i++) { + g = desc->groups + i; + + for (j = 0; g->enum_ids[j]; j++) { + if (g->enum_ids[j] != enum_id) + continue; + + return g->enum_id; + } + } + + return 0; +} + +static unsigned int __init intc_prio_value(struct intc_desc *desc, + intc_enum enum_id, int do_grps) +{ + struct intc_prio *p = desc->priorities; + unsigned int i; + + for (i = 0; p && enum_id && i < desc->nr_priorities; i++) { + p = desc->priorities + i; + + if (p->enum_id != enum_id) + continue; + + return p->priority; + } + + if (do_grps) + return intc_prio_value(desc, intc_grp_id(desc, enum_id), 0); + + /* default to the lowest priority possible if no priority is set + * - this needs to be at least 2 for 5-bit priorities on 7780 + */ + + return 2; +} + +static unsigned int __init intc_mask_data(struct intc_desc *desc, + intc_enum enum_id, int do_grps) +{ + struct intc_mask_reg *mr = desc->mask_regs; + unsigned int i, j, fn; + + for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) { + mr = desc->mask_regs + i; + + for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) { + if (mr->enum_ids[j] != enum_id) + continue; + + fn = intc_find_mask_handler(mr->reg_width); + if (fn == REG_FN_ERROR) + return 0; + + return _INTC_MK(fn, i, (mr->reg_width - 1) - j, 0); + } + } + + if (do_grps) + return intc_mask_data(desc, intc_grp_id(desc, enum_id), 0); + + return 0; +} + +static unsigned int __init intc_prio_data(struct intc_desc *desc, + intc_enum enum_id, int do_grps) +{ + struct intc_prio_reg *pr = desc->prio_regs; + unsigned int i, j, fn, bit, prio; + + for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) { + pr = desc->prio_regs + i; + + for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) { + if (pr->enum_ids[j] != enum_id) + continue; + + fn = intc_find_prio_handler(pr->reg_width); + if (fn == REG_FN_ERROR) + return 0; + + prio = intc_prio_value(desc, enum_id, 1); + bit = pr->reg_width - ((j + 1) * pr->field_width); + + BUG_ON(bit < 0); + + return _INTC_MK(fn, i, bit, prio); + } + } + + if (do_grps) + return intc_prio_data(desc, intc_grp_id(desc, enum_id), 0); + + return 0; +} + +static void __init intc_register_irq(struct intc_desc *desc, intc_enum enum_id, + unsigned int irq) +{ + unsigned int data[2], primary; + + /* Prefer single interrupt source bitmap over other combinations: + * 1. bitmap, single interrupt source + * 2. priority, single interrupt source + * 3. bitmap, multiple interrupt sources (groups) + * 4. priority, multiple interrupt sources (groups) + */ + + data[0] = intc_mask_data(desc, enum_id, 0); + data[1] = intc_prio_data(desc, enum_id, 0); + + primary = 0; + if (!data[0] && data[1]) + primary = 1; + + data[0] = data[0] ? data[0] : intc_mask_data(desc, enum_id, 1); + data[1] = data[1] ? data[1] : intc_prio_data(desc, enum_id, 1); + + if (!data[primary]) + primary ^= 1; + + BUG_ON(!data[primary]); /* must have primary masking method */ + + disable_irq_nosync(irq); + set_irq_chip_and_handler_name(irq, &desc->chip, + handle_level_irq, "level"); + set_irq_chip_data(irq, (void *)data[primary]); + + /* enable secondary masking method if present */ + if (data[!primary]) + intc_reg_fns[_INTC_FN(data[!primary])].enable(desc, + data[!primary]); + + /* irq should be disabled by default */ + desc->chip.mask(irq); +} + +void __init register_intc_controller(struct intc_desc *desc) +{ + unsigned int i; + + desc->chip.mask = intc_disable; + desc->chip.unmask = intc_enable; + desc->chip.mask_ack = intc_disable; + desc->chip.set_type = intc_set_sense; + + for (i = 0; i < desc->nr_vectors; i++) { + struct intc_vect *vect = desc->vectors + i; + + intc_register_irq(desc, vect->enum_id, evt2irq(vect->vect)); + } +} diff --git a/arch/sh/kernel/cpu/irq/intc2.c b/arch/sh/kernel/cpu/irq/intc2.c index d8e22f4ff0f..cc5221390e0 100644 --- a/arch/sh/kernel/cpu/irq/intc2.c +++ b/arch/sh/kernel/cpu/irq/intc2.c @@ -13,36 +13,31 @@ #include <linux/kernel.h> #include <linux/interrupt.h> #include <linux/io.h> +#include <asm/smp.h> -#if defined(CONFIG_CPU_SUBTYPE_SH7760) -#define INTC2_BASE 0xfe080000 -#define INTC2_INTMSK (INTC2_BASE + 0x40) -#define INTC2_INTMSKCLR (INTC2_BASE + 0x60) -#elif defined(CONFIG_CPU_SUBTYPE_SH7780) || \ - defined(CONFIG_CPU_SUBTYPE_SH7785) -#define INTC2_BASE 0xffd40000 -#define INTC2_INTMSK (INTC2_BASE + 0x38) -#define INTC2_INTMSKCLR (INTC2_BASE + 0x3c) -#endif +static inline struct intc2_desc *get_intc2_desc(unsigned int irq) +{ + struct irq_chip *chip = get_irq_chip(irq); + return (void *)((char *)chip - offsetof(struct intc2_desc, chip)); +} static void disable_intc2_irq(unsigned int irq) { struct intc2_data *p = get_irq_chip_data(irq); - ctrl_outl(1 << p->msk_shift, INTC2_INTMSK + p->msk_offset); + struct intc2_desc *d = get_intc2_desc(irq); + + ctrl_outl(1 << p->msk_shift, d->msk_base + p->msk_offset + + (hard_smp_processor_id() * 4)); } static void enable_intc2_irq(unsigned int irq) { struct intc2_data *p = get_irq_chip_data(irq); - ctrl_outl(1 << p->msk_shift, INTC2_INTMSKCLR + p->msk_offset); -} + struct intc2_desc *d = get_intc2_desc(irq); -static struct irq_chip intc2_irq_chip = { - .name = "INTC2", - .mask = disable_intc2_irq, - .unmask = enable_intc2_irq, - .mask_ack = disable_intc2_irq, -}; + ctrl_outl(1 << p->msk_shift, d->mskclr_base + p->msk_offset + + (hard_smp_processor_id() * 4)); +} /* * Setup an INTC2 style interrupt. @@ -56,30 +51,36 @@ static struct irq_chip intc2_irq_chip = { * * in the intc2_data table. */ -void make_intc2_irq(struct intc2_data *table, unsigned int nr_irqs) +void register_intc2_controller(struct intc2_desc *desc) { int i; - for (i = 0; i < nr_irqs; i++) { + desc->chip.mask = disable_intc2_irq; + desc->chip.unmask = enable_intc2_irq; + desc->chip.mask_ack = disable_intc2_irq; + + for (i = 0; i < desc->nr_irqs; i++) { unsigned long ipr, flags; - struct intc2_data *p = table + i; + struct intc2_data *p = desc->intc2_data + i; disable_irq_nosync(p->irq); - /* Set the priority level */ - local_irq_save(flags); + if (desc->prio_base) { + /* Set the priority level */ + local_irq_save(flags); - ipr = ctrl_inl(INTC2_BASE + p->ipr_offset); - ipr &= ~(0xf << p->ipr_shift); - ipr |= p->priority << p->ipr_shift; - ctrl_outl(ipr, INTC2_BASE + p->ipr_offset); + ipr = ctrl_inl(desc->prio_base + p->ipr_offset); + ipr &= ~(0xf << p->ipr_shift); + ipr |= p->priority << p->ipr_shift; + ctrl_outl(ipr, desc->prio_base + p->ipr_offset); - local_irq_restore(flags); + local_irq_restore(flags); + } - set_irq_chip_and_handler_name(p->irq, &intc2_irq_chip, + set_irq_chip_and_handler_name(p->irq, &desc->chip, handle_level_irq, "level"); set_irq_chip_data(p->irq, p); - enable_intc2_irq(p->irq); + disable_intc2_irq(p->irq); } } diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c index 210280b6fdd..98e84f40c71 100644 --- a/arch/sh/kernel/cpu/irq/ipr.c +++ b/arch/sh/kernel/cpu/irq/ipr.c @@ -22,58 +22,57 @@ #include <linux/io.h> #include <linux/interrupt.h> +static inline struct ipr_desc *get_ipr_desc(unsigned int irq) +{ + struct irq_chip *chip = get_irq_chip(irq); + return (void *)((char *)chip - offsetof(struct ipr_desc, chip)); +} + static void disable_ipr_irq(unsigned int irq) { struct ipr_data *p = get_irq_chip_data(irq); + unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx]; /* Set the priority in IPR to 0 */ - ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << p->shift)), p->addr); + ctrl_outw(ctrl_inw(addr) & (0xffff ^ (0xf << p->shift)), addr); } static void enable_ipr_irq(unsigned int irq) { struct ipr_data *p = get_irq_chip_data(irq); + unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx]; /* Set priority in IPR back to original value */ - ctrl_outw(ctrl_inw(p->addr) | (p->priority << p->shift), p->addr); + ctrl_outw(ctrl_inw(addr) | (p->priority << p->shift), addr); } -static struct irq_chip ipr_irq_chip = { - .name = "IPR", - .mask = disable_ipr_irq, - .unmask = enable_ipr_irq, - .mask_ack = disable_ipr_irq, -}; - -unsigned int map_ipridx_to_addr(int idx) __attribute__ ((weak)); -unsigned int map_ipridx_to_addr(int idx) -{ - return 0; -} +/* + * The shift value is now the number of bits to shift, not the number of + * bits/4. This is to make it easier to read the value directly from the + * datasheets. The IPR address is calculated using the ipr_offset table. + */ -void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs) +void register_ipr_controller(struct ipr_desc *desc) { int i; - for (i = 0; i < nr_irqs; i++) { - unsigned int irq = table[i].irq; + desc->chip.mask = disable_ipr_irq; + desc->chip.unmask = enable_ipr_irq; + desc->chip.mask_ack = disable_ipr_irq; - if (!irq) - irq = table[i].irq = i; + for (i = 0; i < desc->nr_irqs; i++) { + struct ipr_data *p = desc->ipr_data + i; - /* could the IPR index be mapped, if not we ignore this */ - if (!table[i].addr) { - table[i].addr = map_ipridx_to_addr(table[i].ipr_idx); - if (!table[i].addr) - continue; - } + BUG_ON(p->ipr_idx >= desc->nr_offsets); + BUG_ON(!desc->ipr_offsets[p->ipr_idx]); - disable_irq_nosync(irq); - set_irq_chip_and_handler_name(irq, &ipr_irq_chip, + disable_irq_nosync(p->irq); + set_irq_chip_and_handler_name(p->irq, &desc->chip, handle_level_irq, "level"); - set_irq_chip_data(irq, &table[i]); - enable_ipr_irq(irq); + set_irq_chip_data(p->irq, p); + disable_ipr_irq(p->irq); } } -EXPORT_SYMBOL(make_ipr_irq); + +EXPORT_SYMBOL(register_ipr_controller); #if !defined(CONFIG_CPU_HAS_PINT_IRQ) int ipr_irq_demux(int irq) diff --git a/arch/sh/kernel/cpu/sh2/entry.S b/arch/sh/kernel/cpu/sh2/entry.S index c16dc8fec48..ee8f1fe84b0 100644 --- a/arch/sh/kernel/cpu/sh2/entry.S +++ b/arch/sh/kernel/cpu/sh2/entry.S @@ -311,6 +311,7 @@ restore_all: rte nop + .align 2 #ifdef CONFIG_TRACE_IRQFLAGS 1: .long trace_hardirqs_off #endif diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c index 108e81b682e..abbf17427e5 100644 --- a/arch/sh/kernel/cpu/sh2/probe.c +++ b/arch/sh/kernel/cpu/sh2/probe.c @@ -9,23 +9,14 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. */ - - #include <linux/init.h> +#include <linux/smp.h> #include <asm/processor.h> #include <asm/cache.h> int __init detect_cpu_and_cache_system(void) { -#if defined(CONFIG_CPU_SUBTYPE_SH7604) - current_cpu_data.type = CPU_SH7604; - current_cpu_data.dcache.ways = 4; - current_cpu_data.dcache.way_incr = (1<<10); - current_cpu_data.dcache.sets = 64; - current_cpu_data.dcache.entry_shift = 4; - current_cpu_data.dcache.linesz = L1_CACHE_BYTES; - current_cpu_data.dcache.flags = 0; -#elif defined(CONFIG_CPU_SUBTYPE_SH7619) +#if defined(CONFIG_CPU_SUBTYPE_SH7619) current_cpu_data.type = CPU_SH7619; current_cpu_data.dcache.ways = 4; current_cpu_data.dcache.way_incr = (1<<12); diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c index f83ff8a68f3..a979b981e6a 100644 --- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c +++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c @@ -52,7 +52,7 @@ static int __init sh7619_devices_setup(void) } __initcall(sh7619_devices_setup); -static struct ipr_data sh7619_ipr_map[] = { +static struct ipr_data ipr_irq_table[] = { { 86, 0, 4, 2 }, /* CMI0 */ { 88, 1, 12, 3 }, /* SCIF0_ERI */ { 89, 1, 12, 3 }, /* SCIF0_RXI */ @@ -68,7 +68,7 @@ static struct ipr_data sh7619_ipr_map[] = { { 99, 1, 4, 3 }, /* SCIF2_TXI */ }; -static unsigned int ipr_offsets[] = { +static unsigned long ipr_offsets[] = { 0xf8080000, /* IPRC */ 0xf8080002, /* IPRD */ 0xf8080004, /* IPRE */ @@ -76,15 +76,19 @@ static unsigned int ipr_offsets[] = { 0xf8080008, /* IPRG */ }; -/* given the IPR index return the address of the IPR register */ -unsigned int map_ipridx_to_addr(int idx) -{ - if (unlikely(idx >= ARRAY_SIZE(ipr_offsets))) - return 0; - return ipr_offsets[idx]; -} +static struct ipr_desc ipr_irq_desc = { + .ipr_offsets = ipr_offsets, + .nr_offsets = ARRAY_SIZE(ipr_offsets), + + .ipr_data = ipr_irq_table, + .nr_irqs = ARRAY_SIZE(ipr_irq_table), + + .chip = { + .name = "IPR-sh7619", + }, +}; -void __init init_IRQ_ipr(void) +void __init plat_irq_setup(void) { - make_ipr_irq(sh7619_ipr_map, ARRAY_SIZE(sh7619_ipr_map)); + register_ipr_controller(&ipr_irq_desc); } diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c index 4ed9110632b..deab1650016 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c @@ -57,7 +57,7 @@ static int __init sh7206_devices_setup(void) } __initcall(sh7206_devices_setup); -static struct ipr_data sh7206_ipr_map[] = { +static struct ipr_data ipr_irq_table[] = { { 140, 7, 12, 2 }, /* CMI0 */ { 164, 8, 4, 2 }, /* MTU2_TGI1A */ { 240, 13, 12, 3 }, /* SCIF0_BRI */ @@ -78,7 +78,7 @@ static struct ipr_data sh7206_ipr_map[] = { { 255, 13, 0, 3 }, /* SCIF3_TXI */ }; -static unsigned int ipr_offsets[] = { +static unsigned long ipr_offsets[] = { 0xfffe0818, /* IPR01 */ 0xfffe081a, /* IPR02 */ 0, /* unused */ @@ -95,15 +95,19 @@ static unsigned int ipr_offsets[] = { 0xfffe0c10, /* IPR14 */ }; -/* given the IPR index return the address of the IPR register */ -unsigned int map_ipridx_to_addr(int idx) -{ - if (unlikely(idx >= ARRAY_SIZE(ipr_offsets))) - return 0; - return ipr_offsets[idx]; -} +static struct ipr_desc ipr_irq_desc = { + .ipr_offsets = ipr_offsets, + .nr_offsets = ARRAY_SIZE(ipr_offsets), + + .ipr_data = ipr_irq_table, + .nr_irqs = ARRAY_SIZE(ipr_irq_table), + + .chip = { + .name = "IPR-sh7206", + }, +}; -void __init init_IRQ_ipr(void) +void __init plat_irq_setup(void) { - make_ipr_irq(sh7206_ipr_map, ARRAY_SIZE(sh7206_ipr_map)); + register_ipr_controller(&ipr_irq_desc); } diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S index b0b59d4a33c..d8e122971c3 100644 --- a/arch/sh/kernel/cpu/sh3/entry.S +++ b/arch/sh/kernel/cpu/sh3/entry.S @@ -340,8 +340,27 @@ ENTRY(vbr_base) general_exception: mov.l 1f, k2 mov.l 2f, k3 +#ifdef CONFIG_CPU_SUBTYPE_SHX3 + mov.l @k2, k2 + + ! Is EXPEVT larger than 0x800? + mov #0x8, k0 + shll8 k0 + cmp/hs k0, k2 + bf 0f + + ! then add 0x580 (k2 is 0xd80 or 0xda0) + mov #0x58, k0 + shll2 k0 + shll2 k0 + add k0, k2 +0: + bra handle_exception + nop +#else bra handle_exception mov.l @k2, k2 +#endif .align 2 1: .long EXPEVT 2: .long ret_from_exception diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c index 1983fb7ad6e..ebd9d06d8bd 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c @@ -48,7 +48,7 @@ static int __init sh7705_devices_setup(void) } __initcall(sh7705_devices_setup); -static struct ipr_data sh7705_ipr_map[] = { +static struct ipr_data ipr_irq_table[] = { /* IRQ, IPR-idx, shift, priority */ { 16, 0, 12, 2 }, /* TMU0 TUNI*/ { 17, 0, 8, 2 }, /* TMU1 TUNI */ @@ -70,25 +70,29 @@ static struct ipr_data sh7705_ipr_map[] = { }; static unsigned long ipr_offsets[] = { - 0xFFFFFEE2 /* 0: IPRA */ -, 0xFFFFFEE4 /* 1: IPRB */ -, 0xA4000016 /* 2: IPRC */ -, 0xA4000018 /* 3: IPRD */ -, 0xA400001A /* 4: IPRE */ -, 0xA4080000 /* 5: IPRF */ -, 0xA4080002 /* 6: IPRG */ -, 0xA4080004 /* 7: IPRH */ + 0xFFFFFEE2, /* 0: IPRA */ + 0xFFFFFEE4, /* 1: IPRB */ + 0xA4000016, /* 2: IPRC */ + 0xA4000018, /* 3: IPRD */ + 0xA400001A, /* 4: IPRE */ + 0xA4080000, /* 5: IPRF */ + 0xA4080002, /* 6: IPRG */ + 0xA4080004, /* 7: IPRH */ }; -/* given the IPR index return the address of the IPR register */ -unsigned int map_ipridx_to_addr(int idx) -{ - if (idx >= ARRAY_SIZE(ipr_offsets)) - return 0; - return ipr_offsets[idx]; -} +static struct ipr_desc ipr_irq_desc = { + .ipr_offsets = ipr_offsets, + .nr_offsets = ARRAY_SIZE(ipr_offsets), + + .ipr_data = ipr_irq_table, + .nr_irqs = ARRAY_SIZE(ipr_irq_table), + + .chip = { + .name = "IPR-sh7705", + }, +}; -void __init init_IRQ_ipr() +void __init plat_irq_setup(void) { - make_ipr_irq(sh7705_ipr_map, ARRAY_SIZE(sh7705_ipr_map)); + register_ipr_controller(&ipr_irq_desc); } diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7709.c b/arch/sh/kernel/cpu/sh3/setup-sh7709.c index c7d7c35fc83..086f8e2545a 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7709.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7709.c @@ -12,6 +12,26 @@ #include <linux/serial.h> #include <asm/sci.h> +static struct resource rtc_resources[] = { + [0] = { + .start = 0xfffffec0, + .end = 0xfffffec0 + 0x1e, + .flags = IORESOURCE_IO, + }, + [1] = { + .start = 20, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 21, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = 22, + .flags = IORESOURCE_IRQ, + }, +}; + static struct plat_sci_port sci_platform_data[] = { { .mapbase = 0xfffffe80, @@ -41,8 +61,16 @@ static struct platform_device sci_device = { }, }; +static struct platform_device rtc_device = { + .name = "sh-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, +}; + static struct platform_device *sh7709_devices[] __initdata = { &sci_device, + &rtc_device, }; static int __init sh7709_devices_setup(void) @@ -52,32 +80,66 @@ static int __init sh7709_devices_setup(void) } __initcall(sh7709_devices_setup); -#define IPRx(A,N) .addr=A, .shift=N -#define IPRA(N) IPRx(0xfffffee2UL,N) -#define IPRB(N) IPRx(0xfffffee4UL,N) -#define IPRC(N) IPRx(0xa4000016UL,N) -#define IPRD(N) IPRx(0xa4000018UL,N) -#define IPRE(N) IPRx(0xa400001aUL,N) - -static struct ipr_data sh7709_ipr_map[] = { - [16] = { IPRA(12), 2 }, /* TMU TUNI0 */ - [17] = { IPRA(8), 4 }, /* TMU TUNI1 */ - [18 ... 19] = { IPRA(4), 1 }, /* TMU TUNI1 */ - [20 ... 22] = { IPRA(0), 2 }, /* RTC CUI */ - [23 ... 26] = { IPRB(4), 3 }, /* SCI */ - [27] = { IPRB(12), 2 }, /* WDT ITI */ - [32] = { IPRC(0), 1 }, /* IRQ 0 */ - [33] = { IPRC(4), 1 }, /* IRQ 1 */ - [34] = { IPRC(8), 1 }, /* IRQ 2 APM */ - [35] = { IPRC(12), 1 }, /* IRQ 3 TOUCHSCREEN */ - [36] = { IPRD(0), 1 }, /* IRQ 4 */ - [37] = { IPRD(4), 1 }, /* IRQ 5 */ - [48 ... 51] = { IPRE(12), 7 }, /* DMA */ - [52 ... 55] = { IPRE(8), 3 }, /* IRDA */ - [56 ... 59] = { IPRE(4), 3 }, /* SCIF */ +static struct ipr_data ipr_irq_table[] = { + { 16, 0, 12, 2 }, /* TMU TUNI0 */ + { 17, 0, 8, 4 }, /* TMU TUNI1 */ + { 18, 0, 4, 1 }, /* TMU TUNI1 */ + { 19, 0, 4, 1 }, /* TMU TUNI1 */ + { 20, 0, 0, 2 }, /* RTC CUI */ + { 21, 0, 0, 2 }, /* RTC CUI */ + { 22, 0, 0, 2 }, /* RTC CUI */ + + { 23, 1, 4, 3 }, /* SCI */ + { 24, 1, 4, 3 }, /* SCI */ + { 25, 1, 4, 3 }, /* SCI */ + { 26, 1, 4, 3 }, /* SCI */ + { 27, 1, 12, 3 }, /* WDT ITI */ + + { 32, 2, 0, 1 }, /* IRQ 0 */ + { 33, 2, 4, 1 }, /* IRQ 1 */ + { 34, 2, 8, 1 }, /* IRQ 2 APM */ + { 35, 2, 12, 1 }, /* IRQ 3 TOUCHSCREEN */ + + { 36, 3, 0, 1 }, /* IRQ 4 */ + { 37, 3, 4, 1 }, /* IRQ 5 */ + + { 48, 4, 12, 7 }, /* DMA */ + { 49, 4, 12, 7 }, /* DMA */ + { 50, 4, 12, 7 }, /* DMA */ + { 51, 4, 12, 7 }, /* DMA */ + + { 52, 4, 8, 3 }, /* IRDA */ + { 53, 4, 8, 3 }, /* IRDA */ + { 54, 4, 8, 3 }, /* IRDA */ + { 55, 4, 8, 3 }, /* IRDA */ + + { 56, 4, 4, 3 }, /* SCIF */ + { 57, 4, 4, 3 }, /* SCIF */ + { 58, 4, 4, 3 }, /* SCIF */ + { 59, 4, 4, 3 }, /* SCIF */ +}; + +static unsigned long ipr_offsets[] = { + 0xfffffee2, /* 0: IPRA */ + 0xfffffee4, /* 1: IPRB */ + 0xa4000016, /* 2: IPRC */ + 0xa4000018, /* 3: IPRD */ + 0xa400001a, /* 4: IPRE */ +}; + +static struct ipr_desc ipr_irq_desc = { + .ipr_offsets = ipr_offsets, + .nr_offsets = ARRAY_SIZE(ipr_offsets), + + .ipr_data = ipr_irq_table, + .nr_irqs = ARRAY_SIZE(ipr_irq_table), + + .chip = { + .name = "IPR-sh7709", + }, }; -void __init init_IRQ_ipr() +void __init plat_irq_setup(void) { - make_ipr_irq(sh7709_ipr_map, ARRAY_SIZE(sh7709_ipr_map)); + register_ipr_controller(&ipr_irq_desc); } diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c index 51760a7e7f1..13228489337 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c @@ -49,7 +49,7 @@ static int __init sh7710_devices_setup(void) } __initcall(sh7710_devices_setup); -static struct ipr_data sh7710_ipr_map[] = { +static struct ipr_data ipr_irq_table[] = { /* IRQ, IPR-idx, shift, priority */ { 16, 0, 12, 2 }, /* TMU0 TUNI*/ { 17, 0, 8, 2 }, /* TMU1 TUNI */ @@ -78,26 +78,30 @@ static struct ipr_data sh7710_ipr_map[] = { }; static unsigned long ipr_offsets[] = { - 0xA414FEE2 /* 0: IPRA */ -, 0xA414FEE4 /* 1: IPRB */ -, 0xA4140016 /* 2: IPRC */ -, 0xA4140018 /* 3: IPRD */ -, 0xA414001A /* 4: IPRE */ -, 0xA4080000 /* 5: IPRF */ -, 0xA4080002 /* 6: IPRG */ -, 0xA4080004 /* 7: IPRH */ -, 0xA4080006 /* 8: IPRI */ + 0xA414FEE2, /* 0: IPRA */ + 0xA414FEE4, /* 1: IPRB */ + 0xA4140016, /* 2: IPRC */ + 0xA4140018, /* 3: IPRD */ + 0xA414001A, /* 4: IPRE */ + 0xA4080000, /* 5: IPRF */ + 0xA4080002, /* 6: IPRG */ + 0xA4080004, /* 7: IPRH */ + 0xA4080006, /* 8: IPRI */ }; -/* given the IPR index return the address of the IPR register */ -unsigned int map_ipridx_to_addr(int idx) -{ - if (idx >= ARRAY_SIZE(ipr_offsets)) - return 0; - return ipr_offsets[idx]; -} +static struct ipr_desc ipr_irq_desc = { + .ipr_offsets = ipr_offsets, + .nr_offsets = ARRAY_SIZE(ipr_offsets), + + .ipr_data = ipr_irq_table, + .nr_irqs = ARRAY_SIZE(ipr_irq_table), + + .chip = { + .name = "IPR-sh7710", + }, +}; -void __init init_IRQ_ipr() +void __init plat_irq_setup(void) { - make_ipr_irq(sh7710_ipr_map, ARRAY_SIZE(sh7710_ipr_map)); + register_ipr_controller(&ipr_irq_desc); } diff --git a/arch/sh/kernel/cpu/sh4/Makefile b/arch/sh/kernel/cpu/sh4/Makefile index 8add10bd826..dadd6bffc12 100644 --- a/arch/sh/kernel/cpu/sh4/Makefile +++ b/arch/sh/kernel/cpu/sh4/Makefile @@ -10,7 +10,11 @@ obj-$(CONFIG_SH_STORE_QUEUES) += sq.o # CPU subtype setup obj-$(CONFIG_CPU_SUBTYPE_SH7750) += setup-sh7750.o +obj-$(CONFIG_CPU_SUBTYPE_SH7750R) += setup-sh7750.o +obj-$(CONFIG_CPU_SUBTYPE_SH7750S) += setup-sh7750.o +obj-$(CONFIG_CPU_SUBTYPE_SH7091) += setup-sh7750.o obj-$(CONFIG_CPU_SUBTYPE_SH7751) += setup-sh7750.o +obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += setup-sh7750.o obj-$(CONFIG_CPU_SUBTYPE_SH7760) += setup-sh7760.o obj-$(CONFIG_CPU_SUBTYPE_SH4_202) += setup-sh4-202.o diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c index fab2eb07196..66c3f75647b 100644 --- a/arch/sh/kernel/cpu/sh4/probe.c +++ b/arch/sh/kernel/cpu/sh4/probe.c @@ -141,6 +141,14 @@ int __init detect_cpu_and_cache_system(void) current_cpu_data.flags |= CPU_HAS_LLSC; } break; + case 0x4000: /* 1st cut */ + case 0x4001: /* 2nd cut */ + current_cpu_data.type = CPU_SHX3; + current_cpu_data.icache.ways = 4; + current_cpu_data.dcache.ways = 4; + current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | + CPU_HAS_LLSC; + break; case 0x8000: current_cpu_data.type = CPU_ST40RA; current_cpu_data.flags |= CPU_HAS_FPU; diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c index 03b14cf78dd..f2286de22bd 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c @@ -82,72 +82,213 @@ static int __init sh7750_devices_setup(void) } __initcall(sh7750_devices_setup); -static struct ipr_data sh7750_ipr_map[] = { - /* IRQ, IPR-idx, shift, priority */ - { 16, 0, 12, 2 }, /* TMU0 TUNI*/ - { 17, 0, 12, 2 }, /* TMU1 TUNI */ - { 18, 0, 4, 2 }, /* TMU2 TUNI */ - { 19, 0, 4, 2 }, /* TMU2 TIPCI */ - { 27, 1, 12, 2 }, /* WDT ITI */ - { 20, 0, 0, 2 }, /* RTC ATI (alarm) */ - { 21, 0, 0, 2 }, /* RTC PRI (period) */ - { 22, 0, 0, 2 }, /* RTC CUI (carry) */ - { 23, 1, 4, 3 }, /* SCI ERI */ - { 24, 1, 4, 3 }, /* SCI RXI */ - { 25, 1, 4, 3 }, /* SCI TXI */ - { 40, 2, 4, 3 }, /* SCIF ERI */ - { 41, 2, 4, 3 }, /* SCIF RXI */ - { 42, 2, 4, 3 }, /* SCIF BRI */ - { 43, 2, 4, 3 }, /* SCIF TXI */ - { 34, 2, 8, 7 }, /* DMAC DMTE0 */ - { 35, 2, 8, 7 }, /* DMAC DMTE1 */ - { 36, 2, 8, 7 }, /* DMAC DMTE2 */ - { 37, 2, 8, 7 }, /* DMAC DMTE3 */ - { 38, 2, 8, 7 }, /* DMAC DMAE */ -}; - -#ifdef CONFIG_CPU_SUBTYPE_SH7751 -static struct ipr_data sh7751_ipr_map[] = { - { 44, 2, 8, 7 }, /* DMAC DMTE4 */ - { 45, 2, 8, 7 }, /* DMAC DMTE5 */ - { 46, 2, 8, 7 }, /* DMAC DMTE6 */ - { 47, 2, 8, 7 }, /* DMAC DMTE7 */ - /* The following use INTC_INPRI00 for masking, which is a 32-bit - register, not a 16-bit register like the IPRx registers, so it - would need special support */ - /*{ 72, INTPRI00, 8, ? },*/ /* TMU3 TUNI */ - /*{ 76, INTPRI00, 12, ? },*/ /* TMU4 TUNI */ +enum { + UNUSED = 0, + + /* interrupt sources */ + IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */ + HUDI, GPIOI, + DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3, + DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7, + DMAC_DMAE, + PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, + PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, + TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, + RTC_ATI, RTC_PRI, RTC_CUI, + SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI, + SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI, + WDT, + REF_RCMI, REF_ROVI, + + /* interrupt groups */ + DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, +}; + +static struct intc_vect vectors[] = { + INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), + INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), + INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), + INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), + INTC_VECT(RTC_CUI, 0x4c0), + INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500), + INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540), + INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720), + INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760), + INTC_VECT(WDT, 0x560), + INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), +}; + +static struct intc_group groups[] = { + INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), + INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), + INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI), + INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI), + INTC_GROUP(REF, REF_RCMI, REF_ROVI), +}; + +static struct intc_prio priorities[] = { + INTC_PRIO(SCIF, 3), + INTC_PRIO(SCI1, 3), + INTC_PRIO(DMAC, 7), +}; + +static struct intc_prio_reg prio_registers[] = { + { 0xffd00004, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, + { 0xffd00008, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, + { 0xffd0000c, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, + { 0xffd00010, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, + { 0xfe080000, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, + TMU4, TMU3, + PCIC1, PCIC0_PCISERR } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups, + priorities, NULL, prio_registers, NULL); + +/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ +#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ + defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ + defined(CONFIG_CPU_SUBTYPE_SH7751) || \ + defined(CONFIG_CPU_SUBTYPE_SH7091) +static struct intc_vect vectors_dma4[] = { + INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), + INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), + INTC_VECT(DMAC_DMAE, 0x6c0), +}; + +static struct intc_group groups_dma4[] = { + INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, + DMAC_DMTE3, DMAC_DMAE), +}; + +static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4", + vectors_dma4, groups_dma4, + priorities, NULL, prio_registers, NULL); +#endif + +/* SH7750R and SH7751R both have 8-channel DMA controllers */ +#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R) +static struct intc_vect vectors_dma8[] = { + INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), + INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), + INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), + INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), + INTC_VECT(DMAC_DMAE, 0x6c0), +}; + +static struct intc_group groups_dma8[] = { + INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, + DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, + DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), +}; + +static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8", + vectors_dma8, groups_dma8, + priorities, NULL, prio_registers, NULL); +#endif + +/* SH7750R, SH7751 and SH7751R all have two extra timer channels */ +#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ + defined(CONFIG_CPU_SUBTYPE_SH7751) || \ + defined(CONFIG_CPU_SUBTYPE_SH7751R) +static struct intc_vect vectors_tmu34[] = { + INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), +}; + +static struct intc_mask_reg mask_registers[] = { + { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, TMU4, TMU3, + PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, + PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, + PCIC1_PCIDMA3, PCIC0_PCISERR } }, }; + +static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34", + vectors_tmu34, NULL, priorities, + mask_registers, prio_registers, NULL); #endif -static unsigned long ipr_offsets[] = { - 0xffd00004UL, /* 0: IPRA */ - 0xffd00008UL, /* 1: IPRB */ - 0xffd0000cUL, /* 2: IPRC */ - 0xffd00010UL, /* 3: IPRD */ +/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ +static struct intc_vect vectors_irlm[] = { + INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), + INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), +}; + +static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL, + priorities, NULL, prio_registers, NULL); + +/* SH7751 and SH7751R both have PCI */ +#if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R) +static struct intc_vect vectors_pci[] = { + INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), + INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), + INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), + INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), }; -/* given the IPR index return the address of the IPR register */ -unsigned int map_ipridx_to_addr(int idx) +static struct intc_group groups_pci[] = { + INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, + PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), +}; + +static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci, + priorities, mask_registers, prio_registers, NULL); +#endif + +#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ + defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ + defined(CONFIG_CPU_SUBTYPE_SH7091) +void __init plat_irq_setup(void) { - if (idx >= ARRAY_SIZE(ipr_offsets)) - return 0; - return ipr_offsets[idx]; + /* + * same vectors for SH7750, SH7750S and SH7091 except for IRLM, + * see below.. + */ + register_intc_controller(&intc_desc); + register_intc_controller(&intc_desc_dma4); } +#endif -#define INTC_ICR 0xffd00000UL -#define INTC_ICR_IRLM (1<<7) +#if defined(CONFIG_CPU_SUBTYPE_SH7750R) +void __init plat_irq_setup(void) +{ + register_intc_controller(&intc_desc); + register_intc_controller(&intc_desc_dma8); + register_intc_controller(&intc_desc_tmu34); +} +#endif -/* enable individual interrupt mode for external interupts */ -void ipr_irq_enable_irlm(void) +#if defined(CONFIG_CPU_SUBTYPE_SH7751) +void __init plat_irq_setup(void) { - ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); + register_intc_controller(&intc_desc); + register_intc_controller(&intc_desc_dma4); + register_intc_controller(&intc_desc_tmu34); + register_intc_controller(&intc_desc_pci); } +#endif -void __init init_IRQ_ipr() +#if defined(CONFIG_CPU_SUBTYPE_SH7751R) +void __init plat_irq_setup(void) { - make_ipr_irq(sh7750_ipr_map, ARRAY_SIZE(sh7750_ipr_map)); -#ifdef CONFIG_CPU_SUBTYPE_SH7751 - make_ipr_irq(sh7751_ipr_map, ARRAY_SIZE(sh7751_ipr_map)); + register_intc_controller(&intc_desc); + register_intc_controller(&intc_desc_dma8); + register_intc_controller(&intc_desc_tmu34); + register_intc_controller(&intc_desc_pci); +} #endif + +#define INTC_ICR 0xffd00000UL +#define INTC_ICR_IRLM (1<<7) + +/* enable individual interrupt mode for external interupts */ +void __init ipr_irq_enable_irlm(void) +{ +#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091) + BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */ +#endif + register_intc_controller(&intc_desc_irlm); + + ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); } diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c index b7c702821e6..47fa2705625 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c @@ -96,7 +96,20 @@ static struct intc2_data intc2_irq_table[] = { {109,12, 0, 4, 0, 3}, /* CMTI */ }; -static struct ipr_data sh7760_ipr_map[] = { +static struct intc2_desc intc2_irq_desc __read_mostly = { + .prio_base = 0xfe080000, + .msk_base = 0xfe080040, + .mskclr_base = 0xfe080060, + + .intc2_data = intc2_irq_table, + .nr_irqs = ARRAY_SIZE(intc2_irq_table), + + .chip = { + .name = "INTC2-sh7760", + }, +}; + +static struct ipr_data ipr_irq_table[] = { /* IRQ, IPR-idx, shift, priority */ { 16, 0, 12, 2 }, /* TMU0 TUNI*/ { 17, 0, 8, 2 }, /* TMU1 TUNI */ @@ -133,20 +146,20 @@ static unsigned long ipr_offsets[] = { 0xffd00010UL, /* 3: IPRD */ }; -/* given the IPR index return the address of the IPR register */ -unsigned int map_ipridx_to_addr(int idx) -{ - if (idx >= ARRAY_SIZE(ipr_offsets)) - return 0; - return ipr_offsets[idx]; -} +static struct ipr_desc ipr_irq_desc = { + .ipr_offsets = ipr_offsets, + .nr_offsets = ARRAY_SIZE(ipr_offsets), -void __init init_IRQ_intc2(void) -{ - make_intc2_irq(intc2_irq_table, ARRAY_SIZE(intc2_irq_table)); -} + .ipr_data = ipr_irq_table, + .nr_irqs = ARRAY_SIZE(ipr_irq_table), + + .chip = { + .name = "IPR-sh7760", + }, +}; -void __init init_IRQ_ipr(void) +void __init plat_irq_setup(void) { - make_ipr_irq(sh7760_ipr_map, ARRAY_SIZE(sh7760_ipr_map)); + register_intc2_controller(&intc2_irq_desc); + register_ipr_controller(&ipr_irq_desc); } diff --git a/arch/sh/kernel/cpu/sh4/sq.c b/arch/sh/kernel/cpu/sh4/sq.c index d7fff752e56..b98d6c3e6f3 100644 --- a/arch/sh/kernel/cpu/sh4/sq.c +++ b/arch/sh/kernel/cpu/sh4/sq.c @@ -371,8 +371,7 @@ static int __init sq_api_init(void) printk(KERN_NOTICE "sq: Registering store queue API.\n"); sq_cache = kmem_cache_create("store_queue_cache", - sizeof(struct sq_mapping), 0, 0, - NULL, NULL); + sizeof(struct sq_mapping), 0, 0, NULL); if (unlikely(!sq_cache)) return ret; diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile index ab7422f8f82..40062328648 100644 --- a/arch/sh/kernel/cpu/sh4a/Makefile +++ b/arch/sh/kernel/cpu/sh4a/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o obj-$(CONFIG_CPU_SUBTYPE_SH73180) += setup-sh73180.o obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o +obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o # Primary on-chip clocks (common) clock-$(CONFIG_CPU_SUBTYPE_SH73180) := clock-sh73180.o @@ -17,5 +18,6 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o +clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o obj-y += $(clock-y) diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c index 51b386d454d..a0fd8bb21f7 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c @@ -387,9 +387,24 @@ out_err: return err; } +static long sh7722_frqcr_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long parent_rate = clk->parent->rate; + int div; + + /* look for multiplier/divisor pair */ + div = sh7722_find_divisors(parent_rate, rate); + if (div < 0) + return clk->rate; + + /* calculate new value of clock rate */ + return parent_rate * 2 / div; +} + static struct clk_ops sh7722_frqcr_clk_ops = { .recalc = sh7722_frqcr_recalc, .set_rate = sh7722_frqcr_set_rate, + .round_rate = sh7722_frqcr_round_rate, }; /* diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c new file mode 100644 index 00000000000..c630b29e06a --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c @@ -0,0 +1,135 @@ +/* + * arch/sh/kernel/cpu/sh4/clock-shx3.c + * + * SH-X3 support for the clock framework + * + * Copyright (C) 2006-2007 Renesas Technology Corp. + * Copyright (C) 2006-2007 Renesas Solutions Corp. + * Copyright (C) 2006-2007 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <asm/clock.h> +#include <asm/freq.h> +#include <asm/io.h> + +static int ifc_divisors[] = { 1, 2, 4 ,6 }; +static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 }; +static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18, 24, 32, 36, 48 }; +static int cfc_divisors[] = { 1, 1, 4, 6 }; + +#define IFC_POS 28 +#define IFC_MSK 0x0003 +#define BFC_MSK 0x000f +#define PFC_MSK 0x000f +#define CFC_MSK 0x0003 +#define BFC_POS 16 +#define PFC_POS 0 +#define CFC_POS 20 + +static void master_clk_init(struct clk *clk) +{ + clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK]; +} + +static struct clk_ops shx3_master_clk_ops = { + .init = master_clk_init, +}; + +static void module_clk_recalc(struct clk *clk) +{ + int idx = ((ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK); + clk->rate = clk->parent->rate / pfc_divisors[idx]; +} + +static struct clk_ops shx3_module_clk_ops = { + .recalc = module_clk_recalc, +}; + +static void bus_clk_recalc(struct clk *clk) +{ + int idx = ((ctrl_inl(FRQCR) >> BFC_POS) & BFC_MSK); + clk->rate = clk->parent->rate / bfc_divisors[idx]; +} + +static struct clk_ops shx3_bus_clk_ops = { + .recalc = bus_clk_recalc, +}; + +static void cpu_clk_recalc(struct clk *clk) +{ + int idx = ((ctrl_inl(FRQCR) >> IFC_POS) & IFC_MSK); + clk->rate = clk->parent->rate / ifc_divisors[idx]; +} + +static struct clk_ops shx3_cpu_clk_ops = { + .recalc = cpu_clk_recalc, +}; + +static struct clk_ops *shx3_clk_ops[] = { + &shx3_master_clk_ops, + &shx3_module_clk_ops, + &shx3_bus_clk_ops, + &shx3_cpu_clk_ops, +}; + +void __init arch_init_clk_ops(struct clk_ops **ops, int idx) +{ + if (idx < ARRAY_SIZE(shx3_clk_ops)) + *ops = shx3_clk_ops[idx]; +} + +static void shyway_clk_recalc(struct clk *clk) +{ + int idx = ((ctrl_inl(FRQCR) >> CFC_POS) & CFC_MSK); + clk->rate = clk->parent->rate / cfc_divisors[idx]; +} + +static struct clk_ops shx3_shyway_clk_ops = { + .recalc = shyway_clk_recalc, +}; + +static struct clk shx3_shyway_clk = { + .name = "shyway_clk", + .flags = CLK_ALWAYS_ENABLED, + .ops = &shx3_shyway_clk_ops, +}; + +/* + * Additional SHx3-specific on-chip clocks that aren't already part of the + * clock framework + */ +static struct clk *shx3_onchip_clocks[] = { + &shx3_shyway_clk, +}; + +static int __init shx3_clk_init(void) +{ + struct clk *clk = clk_get(NULL, "master_clk"); + int i; + + for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) { + struct clk *clkp = shx3_onchip_clocks[i]; + + clkp->parent = clk; + clk_register(clkp); + clk_enable(clkp); + } + + /* + * Now that we have the rest of the clocks registered, we need to + * force the parent clock to propagate so that these clocks will + * automatically figure out their rate. We cheat by handing the + * parent clock its current rate and forcing child propagation. + */ + clk_set_rate(clk, clk_get_rate(clk)); + + clk_put(clk); + + return 0; +} +arch_initcall(shx3_clk_init); diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index 1143fbf65fa..25b913e07e2 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c @@ -1,7 +1,7 @@ /* * SH7722 Setup * - * Copyright (C) 2006 Paul Mundt + * Copyright (C) 2006 - 2007 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -10,6 +10,8 @@ #include <linux/platform_device.h> #include <linux/init.h> #include <linux/serial.h> +#include <linux/mm.h> +#include <asm/mmzone.h> #include <asm/sci.h> static struct plat_sci_port sci_platform_data[] = { @@ -17,8 +19,21 @@ static struct plat_sci_port sci_platform_data[] = { .mapbase = 0xffe00000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 80, 81, 83, 82 }, - }, { + .irqs = { 80, 80, 80, 80 }, + }, + { + .mapbase = 0xffe10000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 81, 81, 81, 81 }, + }, + { + .mapbase = 0xffe20000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 82, 82, 82, 82 }, + }, + { .flags = 0, } }; @@ -42,39 +57,149 @@ static int __init sh7722_devices_setup(void) } __initcall(sh7722_devices_setup); -static struct ipr_data sh7722_ipr_map[] = { - /* IRQ, IPR-idx, shift, prio */ - { 16, 0, 12, 2 }, /* TMU0 */ - { 17, 0, 8, 2 }, /* TMU1 */ - { 80, 6, 12, 3 }, /* SCIF ERI */ - { 81, 6, 12, 3 }, /* SCIF RXI */ - { 82, 6, 12, 3 }, /* SCIF BRI */ - { 83, 6, 12, 3 }, /* SCIF TXI */ +enum { + UNUSED=0, + + /* interrupt sources */ + IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, + HUDI, + SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, + RTC_ATI, RTC_PRI, RTC_CUI, + DMAC0, DMAC1, DMAC2, DMAC3, + VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, + VPU, TPU, + USB_USBI0, USB_USBI1, + DMAC4, DMAC5, DMAC_DADERR, + KEYSC, + SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO, + FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, + I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, + SDHI0, SDHI1, SDHI2, SDHI3, + CMT, TSIF, SIU, TWODG, + TMU0, TMU1, TMU2, + IRDA, JPU, LCDC, + + /* interrupt groups */ + + SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI, +}; + +static struct intc_vect vectors[] = { + INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), + INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), + INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), + INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), + INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720), + INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760), + INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0), + INTC_VECT(RTC_CUI, 0x7c0), + INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), + INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), + INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), + INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), + INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0), + INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40), + INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), + INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0), + INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20), + INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80), + INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00), + INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), + INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), + INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), + INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), + INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), + INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), + INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), + INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0), + INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), + INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480), + INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580), +}; + +static struct intc_group groups[] = { + INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI), + INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), + INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), + INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), + INTC_GROUP(USB, USB_USBI0, USB_USBI1), + INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), + INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, + FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), + INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), + INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), +}; + +static struct intc_prio priorities[] = { + INTC_PRIO(SCIF0, 3), + INTC_PRIO(SCIF1, 3), + INTC_PRIO(SCIF2, 3), + INTC_PRIO(TMU0, 2), + INTC_PRIO(TMU1, 2), +}; + +static struct intc_mask_reg mask_registers[] = { + { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ + { } }, + { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ + { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, + { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ + { 0, 0, 0, VPU, } }, + { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ + { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } }, + { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ + { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } }, + { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ + { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } }, + { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ + { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } }, + { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ + { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, + FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, + { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ + { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } }, + { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ + { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } }, + { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ + { } }, + { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ + { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } }, + { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ + { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, }; -static unsigned long ipr_offsets[] = { - 0xa4080000, /* 0: IPRA */ - 0xa4080004, /* 1: IPRB */ - 0xa4080008, /* 2: IPRC */ - 0xa408000c, /* 3: IPRD */ - 0xa4080010, /* 4: IPRE */ - 0xa4080014, /* 5: IPRF */ - 0xa4080018, /* 6: IPRG */ - 0xa408001c, /* 7: IPRH */ - 0xa4080020, /* 8: IPRI */ - 0xa4080024, /* 9: IPRJ */ - 0xa4080028, /* 10: IPRK */ - 0xa408002c, /* 11: IPRL */ +static struct intc_prio_reg prio_registers[] = { + { 0xa4080000, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } }, + { 0xa4080004, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, + { 0xa4080008, 16, 4, /* IPRC */ { } }, + { 0xa408000c, 16, 4, /* IPRD */ { } }, + { 0xa4080010, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } }, + { 0xa4080014, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } }, + { 0xa4080018, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } }, + { 0xa408001c, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } }, + { 0xa4080020, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } }, + { 0xa4080024, 16, 4, /* IPRJ */ { 0, 0, SIU } }, + { 0xa4080028, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } }, + { 0xa408002c, 16, 4, /* IPRL */ { TWODG, 0, TPU } }, + { 0xa4140010, 32, 4, /* INTPRI00 */ + { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, }; -unsigned int map_ipridx_to_addr(int idx) +static struct intc_sense_reg sense_registers[] = { + { 0xa414001c, 16, 2, /* ICR1 */ + { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "sh7722", vectors, groups, priorities, + mask_registers, prio_registers, sense_registers); + +void __init plat_irq_setup(void) { - if (unlikely(idx >= ARRAY_SIZE(ipr_offsets))) - return 0; - return ipr_offsets[idx]; + register_intc_controller(&intc_desc); } -void __init init_IRQ_ipr(void) +void __init plat_mem_setup(void) { - make_ipr_irq(sh7722_ipr_map, ARRAY_SIZE(sh7722_ipr_map)); + /* Register the URAM space as Node 1 */ + setup_bootmem_node(1, 0x055f0000, 0x05610000); } diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c index 9aeaa2ddaa2..a4127ec1520 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c @@ -30,7 +30,7 @@ static struct resource rtc_resources[] = { }, [3] = { /* Alarm IRQ */ - .start = 23, + .start = 20, .flags = IORESOURCE_IRQ, }, }; @@ -78,31 +78,205 @@ static int __init sh7780_devices_setup(void) } __initcall(sh7780_devices_setup); -static struct intc2_data intc2_irq_table[] = { - { 28, 0, 24, 0, 0, 2 }, /* TMU0 */ +enum { + UNUSED = 0, - { 21, 1, 0, 0, 2, 2 }, - { 22, 1, 1, 0, 2, 2 }, - { 23, 1, 2, 0, 2, 2 }, + /* interrupt sources */ - { 40, 8, 24, 0, 3, 3 }, /* SCIF0 ERI */ - { 41, 8, 24, 0, 3, 3 }, /* SCIF0 RXI */ - { 42, 8, 24, 0, 3, 3 }, /* SCIF0 BRI */ - { 43, 8, 24, 0, 3, 3 }, /* SCIF0 TXI */ + IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, + IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, + IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, + IRL_HHLL, IRL_HHLH, IRL_HHHL, - { 76, 8, 16, 0, 4, 3 }, /* SCIF1 ERI */ - { 77, 8, 16, 0, 4, 3 }, /* SCIF1 RXI */ - { 78, 8, 16, 0, 4, 3 }, /* SCIF1 BRI */ - { 79, 8, 16, 0, 4, 3 }, /* SCIF1 TXI */ + IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, + RTC_ATI, RTC_PRI, RTC_CUI, + WDT, + TMU0, TMU1, TMU2, TMU2_TICPI, + HUDI, + DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMAE, + SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI, + DMAC0_DMINT4, DMAC0_DMINT5, DMAC1_DMINT6, DMAC1_DMINT7, + CMT, HAC, + PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, + PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0, + SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI, + SIOF, HSPI, + MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY, + DMAC1_DMINT8, DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11, + TMU3, TMU4, TMU5, + SSI, + FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1, + GPIOI0, GPIOI1, GPIOI2, GPIOI3, - { 64, 0x10, 8, 0, 14, 2 }, /* PCIC0 */ - { 65, 0x10, 0, 0, 15, 2 }, /* PCIC1 */ - { 66, 0x14, 24, 0, 16, 2 }, /* PCIC2 */ - { 67, 0x14, 16, 0, 17, 2 }, /* PCIC3 */ - { 68, 0x14, 8, 0, 18, 2 }, /* PCIC4 */ + /* interrupt groups */ + + RTC, TMU012, DMAC0, SCIF0, DMAC45, DMAC1, + PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO, +}; + +static struct intc_vect vectors[] = { + INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), + INTC_VECT(RTC_CUI, 0x4c0), + INTC_VECT(WDT, 0x560), + INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), + INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), + INTC_VECT(HUDI, 0x600), + INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660), + INTC_VECT(DMAC0_DMINT2, 0x680), INTC_VECT(DMAC0_DMINT3, 0x6a0), + INTC_VECT(DMAC0_DMAE, 0x6c0), + INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720), + INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760), + INTC_VECT(DMAC0_DMINT4, 0x780), INTC_VECT(DMAC0_DMINT5, 0x7a0), + INTC_VECT(DMAC1_DMINT6, 0x7c0), INTC_VECT(DMAC1_DMINT7, 0x7e0), + INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980), + INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), + INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), + INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0), + INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0), + INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20), + INTC_VECT(SCIF1_ERI, 0xb80), INTC_VECT(SCIF1_RXI, 0xba0), + INTC_VECT(SCIF1_BRI, 0xbc0), INTC_VECT(SCIF1_TXI, 0xbe0), + INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80), + INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20), + INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60), + INTC_VECT(DMAC1_DMINT8, 0xd80), INTC_VECT(DMAC1_DMINT9, 0xda0), + INTC_VECT(DMAC1_DMINT10, 0xdc0), INTC_VECT(DMAC1_DMINT11, 0xde0), + INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), + INTC_VECT(TMU5, 0xe40), + INTC_VECT(SSI, 0xe80), + INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20), + INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60), + INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0), + INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0), +}; + +static struct intc_group groups[] = { + INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), + INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), + INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, + DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE), + INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), + INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, + DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11), + INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0), + INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI), + INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY), + INTC_GROUP(TMU345, TMU3, TMU4, TMU5), + INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND, + FLCTL_FLTRQ0, FLCTL_FLTRQ1), + INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3), +}; + +static struct intc_prio priorities[] = { + INTC_PRIO(SCIF0, 3), + INTC_PRIO(SCIF1, 3), +}; + +static struct intc_mask_reg mask_registers[] = { + { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ + { 0, 0, 0, 0, 0, 0, GPIO, FLCTL, + SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB, + PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0, + HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } }, }; -void __init init_IRQ_intc2(void) +static struct intc_prio_reg prio_registers[] = { + { 0xffd40000, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, TMU2, TMU2_TICPI } }, + { 0xffd40004, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } }, + { 0xffd40008, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } }, + { 0xffd4000c, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } }, + { 0xffd40010, 32, 8, /* INT2PRI4 */ { CMT, HAC, PCISERR, PCIINTA, } }, + { 0xffd40014, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC, + PCIINTD, PCIC5 } }, + { 0xffd40018, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } }, + { 0xffd4001c, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, priorities, + mask_registers, prio_registers, NULL); + +/* Support for external interrupt pins in IRQ mode */ + +static struct intc_vect irq_vectors[] = { + INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), + INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), + INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), + INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), +}; + +static struct intc_mask_reg irq_mask_registers[] = { + { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ + { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, +}; + +static struct intc_prio_reg irq_prio_registers[] = { + { 0xffd00010, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, + IRQ4, IRQ5, IRQ6, IRQ7 } }, +}; + +static struct intc_sense_reg irq_sense_registers[] = { + { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, + IRQ4, IRQ5, IRQ6, IRQ7 } }, +}; + +static DECLARE_INTC_DESC(intc_irq_desc, "sh7780-irq", irq_vectors, + NULL, NULL, irq_mask_registers, irq_prio_registers, + irq_sense_registers); + +/* External interrupt pins in IRL mode */ + +static struct intc_vect irl_vectors[] = { + INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), + INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), + INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), + INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0), + INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320), + INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360), + INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0), + INTC_VECT(IRL_HHHL, 0x3c0), +}; + +static struct intc_mask_reg irl3210_mask_registers[] = { + { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */ + { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, + IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, + IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, + IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, +}; + +static struct intc_mask_reg irl7654_mask_registers[] = { + { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, + IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, + IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, + IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, +}; + +static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors, + NULL, NULL, irl7654_mask_registers, NULL, NULL); + +static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors, + NULL, NULL, irl3210_mask_registers, NULL, NULL); + +void __init plat_irq_setup(void) { - make_intc2_irq(intc2_irq_table, ARRAY_SIZE(intc2_irq_table)); + register_intc_controller(&intc_desc); +} + +void __init plat_irq_setup_pins(int mode) +{ + switch (mode) { + case IRQ_MODE_IRQ: + register_intc_controller(&intc_irq_desc); + break; + case IRQ_MODE_IRL7654: + register_intc_controller(&intc_irl7654_desc); + break; + case IRQ_MODE_IRL3210: + register_intc_controller(&intc_irl3210_desc); + break; + default: + BUG(); + } } diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c index 07b0de82cfe..cf047562e43 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c @@ -97,7 +97,21 @@ static struct intc2_data intc2_irq_table[] = { { 60, 12, 16, 0, 7, 3 }, /* SCIF5 ERI, RXI, BRI, TXI */ }; -void __init init_IRQ_intc2(void) +static struct intc2_desc intc2_irq_desc __read_mostly = { + .prio_base = 0xffd40000, + .msk_base = 0xffd40038, + .mskclr_base = 0xffd4003c, + + .intc2_data = intc2_irq_table, + .nr_irqs = ARRAY_SIZE(intc2_irq_table), + + .chip = { + .name = "INTC2-sh7785", + }, +}; + +void __init plat_irq_setup(void) { - make_intc2_irq(intc2_irq_table, ARRAY_SIZE(intc2_irq_table)); + register_intc2_controller(&intc2_irq_desc); } + diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c new file mode 100644 index 00000000000..704c064f70d --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c @@ -0,0 +1,85 @@ +/* + * SH-X3 Setup + * + * Copyright (C) 2007 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/platform_device.h> +#include <linux/init.h> +#include <linux/serial.h> +#include <linux/io.h> +#include <asm/sci.h> + +static struct plat_sci_port sci_platform_data[] = { + { + .mapbase = 0xffc30000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 40, 41, 43, 42 }, + }, { + .mapbase = 0xffc40000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 44, 45, 47, 46 }, + }, { + .mapbase = 0xffc50000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 48, 49, 51, 50 }, + }, { + .mapbase = 0xffc60000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 52, 53, 55, 54 }, + }, { + .flags = 0, + } +}; + +static struct platform_device sci_device = { + .name = "sh-sci", + .id = -1, + .dev = { + .platform_data = sci_platform_data, + }, +}; + +static struct platform_device *shx3_devices[] __initdata = { + &sci_device, +}; + +static int __init shx3_devices_setup(void) +{ + return platform_add_devices(shx3_devices, + ARRAY_SIZE(shx3_devices)); +} +__initcall(shx3_devices_setup); + +static struct intc2_data intc2_irq_table[] = { + { 16, 0, 0, 0, 1, 2 }, /* TMU0 */ + { 40, 4, 0, 0x20, 0, 3 }, /* SCIF0 ERI */ + { 41, 4, 0, 0x20, 1, 3 }, /* SCIF0 RXI */ + { 42, 4, 0, 0x20, 2, 3 }, /* SCIF0 BRI */ + { 43, 4, 0, 0x20, 3, 3 }, /* SCIF0 TXI */ +}; + +static struct intc2_desc intc2_irq_desc __read_mostly = { + .prio_base = 0xfe410000, + .msk_base = 0xfe410820, + .mskclr_base = 0xfe410850, + + .intc2_data = intc2_irq_table, + .nr_irqs = ARRAY_SIZE(intc2_irq_table), + + .chip = { + .name = "INTC2-SHX3", + }, +}; + +void __init plat_irq_setup(void) +{ + register_intc2_controller(&intc2_irq_desc); +} diff --git a/arch/sh/kernel/cpufreq.c b/arch/sh/kernel/cpufreq.c index 47abf6e49df..e61890217c5 100644 --- a/arch/sh/kernel/cpufreq.c +++ b/arch/sh/kernel/cpufreq.c @@ -3,89 +3,46 @@ * * cpufreq driver for the SuperH processors. * - * Copyright (C) 2002, 2003, 2004, 2005 Paul Mundt + * Copyright (C) 2002 - 2007 Paul Mundt * Copyright (C) 2002 M. R. Brown * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * Clock framework bits from arch/avr32/mach-at32ap/cpufreq.c + * + * Copyright (C) 2004-2007 Atmel Corporation + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. */ #include <linux/types.h> #include <linux/cpufreq.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/slab.h> #include <linux/init.h> -#include <linux/delay.h> +#include <linux/err.h> #include <linux/cpumask.h> #include <linux/smp.h> #include <linux/sched.h> /* set_cpus_allowed() */ +#include <linux/clk.h> -#include <asm/processor.h> -#include <asm/watchdog.h> -#include <asm/freq.h> -#include <asm/io.h> - -/* - * For SuperH, each policy change requires that we change the IFC, BFC, and - * PFC at the same time. Here we define sane values that won't trash the - * system. - * - * Note the max set is computed at runtime, we use the divisors that we booted - * with to setup our maximum operating frequencies. - */ -struct clock_set { - unsigned int ifc; - unsigned int bfc; - unsigned int pfc; -} clock_sets[] = { -#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH2) - { 0, 0, 0 }, /* not implemented yet */ -#elif defined(CONFIG_CPU_SH4) - { 4, 8, 8 }, /* min - IFC: 1/4, BFC: 1/8, PFC: 1/8 */ - { 1, 2, 2 }, /* max - IFC: 1, BFC: 1/2, PFC: 1/2 */ -#endif -}; - -#define MIN_CLOCK_SET 0 -#define MAX_CLOCK_SET (ARRAY_SIZE(clock_sets) - 1) - -/* - * For the time being, we only support two frequencies, which in turn are - * aimed at the POWERSAVE and PERFORMANCE policies, which in turn are derived - * directly from the respective min/max clock sets. Technically we could - * support a wider range of frequencies, but these vary far too much for each - * CPU subtype (and we'd have to construct a frequency table for each subtype). - * - * Maybe something to implement in the future.. - */ -#define SH_FREQ_MAX 0 -#define SH_FREQ_MIN 1 - -static struct cpufreq_frequency_table sh_freqs[] = { - { SH_FREQ_MAX, 0 }, - { SH_FREQ_MIN, 0 }, - { 0, CPUFREQ_TABLE_END }, -}; +static struct clk *cpuclk; -static void sh_cpufreq_update_clocks(unsigned int set) +static unsigned int sh_cpufreq_get(unsigned int cpu) { - current_cpu_data.cpu_clock = current_cpu_data.master_clock / clock_sets[set].ifc; - current_cpu_data.bus_clock = current_cpu_data.master_clock / clock_sets[set].bfc; - current_cpu_data.module_clock = current_cpu_data.master_clock / clock_sets[set].pfc; - current_cpu_data.loops_per_jiffy = loops_per_jiffy; + return (clk_get_rate(cpuclk) + 500) / 1000; } -/* XXX: This needs to be split out per CPU and CPU subtype. */ /* * Here we notify other drivers of the proposed change and the final change. */ -static int sh_cpufreq_setstate(unsigned int cpu, unsigned int set) +static int sh_cpufreq_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) { - unsigned short frqcr = ctrl_inw(FRQCR); + unsigned int cpu = policy->cpu; cpumask_t cpus_allowed; struct cpufreq_freqs freqs; + long freq; if (!cpu_online(cpu)) return -ENODEV; @@ -95,125 +52,109 @@ static int sh_cpufreq_setstate(unsigned int cpu, unsigned int set) BUG_ON(smp_processor_id() != cpu); - freqs.cpu = cpu; - freqs.old = current_cpu_data.cpu_clock / 1000; - freqs.new = (current_cpu_data.master_clock / clock_sets[set].ifc) / 1000; + /* Convert target_freq from kHz to Hz */ + freq = clk_round_rate(cpuclk, target_freq * 1000); - cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); -#if defined(CONFIG_CPU_SH3) - frqcr |= (newstate & 0x4000) << 14; - frqcr |= (newstate & 0x000c) << 2; -#elif defined(CONFIG_CPU_SH4) - /* - * FRQCR.PLL2EN is 1, we need to allow the PLL to stabilize by - * initializing the WDT. - */ - if (frqcr & (1 << 9)) { - __u8 csr; - - /* - * Set the overflow period to the highest available, - * in this case a 1/4096 division ratio yields a 5.25ms - * overflow period. See asm-sh/watchdog.h for more - * information and a range of other divisors. - */ - csr = sh_wdt_read_csr(); - csr |= WTCSR_CKS_4096; - sh_wdt_write_csr(csr); - - sh_wdt_write_cnt(0); - } - frqcr &= 0x0e00; /* Clear ifc, bfc, pfc */ - frqcr |= get_ifc_value(clock_sets[set].ifc) << 6; - frqcr |= get_bfc_value(clock_sets[set].bfc) << 3; - frqcr |= get_pfc_value(clock_sets[set].pfc); -#endif - ctrl_outw(frqcr, FRQCR); - sh_cpufreq_update_clocks(set); + if (freq < (policy->min * 1000) || freq > (policy->max * 1000)) + return -EINVAL; + + pr_debug("cpufreq: requested frequency %u Hz\n", target_freq * 1000); + freqs.cpu = cpu; + freqs.old = sh_cpufreq_get(cpu); + freqs.new = (freq + 500) / 1000; + freqs.flags = 0; + + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); set_cpus_allowed(current, cpus_allowed); + clk_set_rate(cpuclk, freq); cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + pr_debug("cpufreq: set frequency %lu Hz\n", freq); + return 0; } static int sh_cpufreq_cpu_init(struct cpufreq_policy *policy) { - unsigned int min_freq, max_freq; - unsigned int ifc, bfc, pfc; + printk(KERN_INFO "cpufreq: SuperH CPU frequency driver.\n"); if (!cpu_online(policy->cpu)) return -ENODEV; - /* Update our maximum clock set */ - get_current_frequency_divisors(&ifc, &bfc, &pfc); - clock_sets[MAX_CLOCK_SET].ifc = ifc; - clock_sets[MAX_CLOCK_SET].bfc = bfc; - clock_sets[MAX_CLOCK_SET].pfc = pfc; - - /* Convert from Hz to kHz */ - max_freq = current_cpu_data.cpu_clock / 1000; - min_freq = (current_cpu_data.master_clock / clock_sets[MIN_CLOCK_SET].ifc) / 1000; - - sh_freqs[SH_FREQ_MAX].frequency = max_freq; - sh_freqs[SH_FREQ_MIN].frequency = min_freq; + cpuclk = clk_get(NULL, "cpu_clk"); + if (IS_ERR(cpuclk)) { + printk(KERN_ERR "cpufreq: couldn't get CPU clk\n"); + return PTR_ERR(cpuclk); + } /* cpuinfo and default policy values */ - policy->governor = CPUFREQ_DEFAULT_GOVERNOR; + policy->cpuinfo.min_freq = (clk_round_rate(cpuclk, 1) + 500) / 1000; + policy->cpuinfo.max_freq = (clk_round_rate(cpuclk, ~0UL) + 500) / 1000; policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; - policy->cur = max_freq; - return cpufreq_frequency_table_cpuinfo(policy, &sh_freqs[0]); -} + policy->governor = CPUFREQ_DEFAULT_GOVERNOR; + policy->cur = sh_cpufreq_get(policy->cpu); + policy->min = policy->cpuinfo.min_freq; + policy->max = policy->cpuinfo.max_freq; -static int sh_cpufreq_verify(struct cpufreq_policy *policy) -{ - return cpufreq_frequency_table_verify(policy, &sh_freqs[0]); -} -static int sh_cpufreq_target(struct cpufreq_policy *policy, - unsigned int target_freq, - unsigned int relation) -{ - unsigned int set, idx = 0; + /* + * Catch the cases where the clock framework hasn't been wired up + * properly to support scaling. + */ + if (unlikely(policy->min == policy->max)) { + printk(KERN_ERR "cpufreq: clock framework rate rounding " + "not supported on this CPU.\n"); - if (cpufreq_frequency_table_target(policy, &sh_freqs[0], target_freq, relation, &idx)) + clk_put(cpuclk); return -EINVAL; + } - set = (idx == SH_FREQ_MIN) ? MIN_CLOCK_SET : MAX_CLOCK_SET; + printk(KERN_INFO "cpufreq: Frequencies - Minimum %u.%03u MHz, " + "Maximum %u.%03u MHz.\n", + policy->min / 1000, policy->min % 1000, + policy->max / 1000, policy->max % 1000); - sh_cpufreq_setstate(policy->cpu, set); + return 0; +} +static int sh_cpufreq_verify(struct cpufreq_policy *policy) +{ + cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, + policy->cpuinfo.max_freq); + return 0; +} + +static int sh_cpufreq_exit(struct cpufreq_policy *policy) +{ + clk_put(cpuclk); return 0; } static struct cpufreq_driver sh_cpufreq_driver = { .owner = THIS_MODULE, - .name = "SH cpufreq", + .name = "sh", .init = sh_cpufreq_cpu_init, .verify = sh_cpufreq_verify, .target = sh_cpufreq_target, + .get = sh_cpufreq_get, + .exit = sh_cpufreq_exit, }; -static int __init sh_cpufreq_init(void) +static int __init sh_cpufreq_module_init(void) { - if (!current_cpu_data.cpu_clock) - return -EINVAL; - if (cpufreq_register_driver(&sh_cpufreq_driver)) - return -EINVAL; - - return 0; + return cpufreq_register_driver(&sh_cpufreq_driver); } -static void __exit sh_cpufreq_exit(void) +static void __exit sh_cpufreq_module_exit(void) { cpufreq_unregister_driver(&sh_cpufreq_driver); } -module_init(sh_cpufreq_init); -module_exit(sh_cpufreq_exit); +module_init(sh_cpufreq_module_init); +module_exit(sh_cpufreq_module_exit); MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>"); MODULE_DESCRIPTION("cpufreq driver for SuperH"); MODULE_LICENSE("GPL"); - diff --git a/arch/sh/kernel/head.S b/arch/sh/kernel/head.S index 71a3ad7d283..0bccc0ca5a0 100644 --- a/arch/sh/kernel/head.S +++ b/arch/sh/kernel/head.S @@ -36,7 +36,8 @@ ENTRY(empty_zero_page) 1: .skip PAGE_SIZE - empty_zero_page - 1b - .text + .section .text.head, "ax" + /* * Condition at the entry of _stext: * diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c index 27b923c45b3..03404987528 100644 --- a/arch/sh/kernel/irq.c +++ b/arch/sh/kernel/irq.c @@ -158,15 +158,11 @@ asmlinkage int do_IRQ(unsigned int irq, struct pt_regs *regs) } #ifdef CONFIG_4KSTACKS -/* - * These should really be __section__(".bss.page_aligned") as well, but - * gcc's 3.0 and earlier don't handle that correctly. - */ static char softirq_stack[NR_CPUS * THREAD_SIZE] - __attribute__((__aligned__(THREAD_SIZE))); + __attribute__((__section__(".bss.page_aligned"))); static char hardirq_stack[NR_CPUS * THREAD_SIZE] - __attribute__((__aligned__(THREAD_SIZE))); + __attribute__((__section__(".bss.page_aligned"))); /* * allocate per-cpu stacks for hardirq and for softirq processing @@ -257,14 +253,7 @@ void __init init_IRQ(void) #ifdef CONFIG_CPU_HAS_PINT_IRQ init_IRQ_pint(); #endif - -#ifdef CONFIG_CPU_HAS_INTC2_IRQ - init_IRQ_intc2(); -#endif - -#ifdef CONFIG_CPU_HAS_IPR_IRQ - init_IRQ_ipr(); -#endif + plat_irq_setup(); /* Perform the machine specific initialisation */ if (sh_mv.mv_init_irq) diff --git a/arch/sh/kernel/machvec.c b/arch/sh/kernel/machvec.c new file mode 100644 index 00000000000..23c5948f012 --- /dev/null +++ b/arch/sh/kernel/machvec.c @@ -0,0 +1,130 @@ +/* + * arch/sh/kernel/machvec.c + * + * The SuperH machine vector setup handlers, yanked from setup.c + * + * Copyright (C) 1999 Niibe Yutaka + * Copyright (C) 2002 - 2007 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/string.h> +#include <asm/machvec.h> +#include <asm/sections.h> +#include <asm/io.h> +#include <asm/irq.h> + +#define MV_NAME_SIZE 32 + +#define for_each_mv(mv) \ + for ((mv) = (struct sh_machine_vector *)&__machvec_start; \ + (mv) && (unsigned long)(mv) < (unsigned long)&__machvec_end; \ + (mv)++) + +static struct sh_machine_vector * __init get_mv_byname(const char *name) +{ + struct sh_machine_vector *mv; + + for_each_mv(mv) + if (strcasecmp(name, mv->mv_name) == 0) + return mv; + + return NULL; +} + +static unsigned int __initdata machvec_selected; + +static int __init early_parse_mv(char *from) +{ + char mv_name[MV_NAME_SIZE] = ""; + char *mv_end; + char *mv_comma; + int mv_len; + struct sh_machine_vector *mvp; + + mv_end = strchr(from, ' '); + if (mv_end == NULL) + mv_end = from + strlen(from); + + mv_comma = strchr(from, ','); + mv_len = mv_end - from; + if (mv_len > (MV_NAME_SIZE-1)) + mv_len = MV_NAME_SIZE-1; + memcpy(mv_name, from, mv_len); + mv_name[mv_len] = '\0'; + from = mv_end; + + machvec_selected = 1; + + /* Boot with the generic vector */ + if (strcmp(mv_name, "generic") == 0) + return 0; + + mvp = get_mv_byname(mv_name); + if (unlikely(!mvp)) { + printk("Available vectors:\n\n\t'%s', ", sh_mv.mv_name); + for_each_mv(mvp) + printk("'%s', ", mvp->mv_name); + printk("\n\n"); + panic("Failed to select machvec '%s' -- halting.\n", + mv_name); + } else + sh_mv = *mvp; + + return 0; +} +early_param("sh_mv", early_parse_mv); + +void __init sh_mv_setup(void) +{ + /* + * Only overload the machvec if one hasn't been selected on + * the command line with sh_mv= + */ + if (!machvec_selected) { + unsigned long machvec_size; + + machvec_size = ((unsigned long)&__machvec_end - + (unsigned long)&__machvec_start); + + /* + * If the machvec hasn't been preselected, use the first + * vector (usually the only one) from .machvec.init. + */ + if (machvec_size >= sizeof(struct sh_machine_vector)) + sh_mv = *(struct sh_machine_vector *)&__machvec_start; + } + + printk(KERN_NOTICE "Booting machvec: %s\n", get_system_type()); + + /* + * Manually walk the vec, fill in anything that the board hasn't yet + * by hand, wrapping to the generic implementation. + */ +#define mv_set(elem) do { \ + if (!sh_mv.mv_##elem) \ + sh_mv.mv_##elem = generic_##elem; \ +} while (0) + + mv_set(inb); mv_set(inw); mv_set(inl); + mv_set(outb); mv_set(outw); mv_set(outl); + + mv_set(inb_p); mv_set(inw_p); mv_set(inl_p); + mv_set(outb_p); mv_set(outw_p); mv_set(outl_p); + + mv_set(insb); mv_set(insw); mv_set(insl); + mv_set(outsb); mv_set(outsw); mv_set(outsl); + + mv_set(readb); mv_set(readw); mv_set(readl); + mv_set(writeb); mv_set(writew); mv_set(writel); + + mv_set(ioport_map); + mv_set(ioport_unmap); + mv_set(irq_demux); + + if (!sh_mv.mv_nr_irqs) + sh_mv.mv_nr_irqs = NR_IRQS; +} diff --git a/arch/sh/kernel/process.c b/arch/sh/kernel/process.c index a11e2aa73cb..6334a4c54c7 100644 --- a/arch/sh/kernel/process.c +++ b/arch/sh/kernel/process.c @@ -17,6 +17,7 @@ #include <linux/kexec.h> #include <linux/kdebug.h> #include <linux/tick.h> +#include <linux/reboot.h> #include <asm/uaccess.h> #include <asm/mmu_context.h> #include <asm/pgalloc.h> @@ -319,9 +320,7 @@ static void ubc_set_tracing(int asid, unsigned long pc) ctrl_outl(pc, UBC_BARA); #ifdef CONFIG_MMU - /* We don't have any ASID settings for the SH-2! */ - if (current_cpu_data.type != CPU_SH7604) - ctrl_outb(asid, UBC_BASRA); + ctrl_outb(asid, UBC_BASRA); #endif ctrl_outl(0, UBC_BAMRA); @@ -405,8 +404,8 @@ asmlinkage int sys_fork(unsigned long r4, unsigned long r5, unsigned long r6, unsigned long r7, struct pt_regs __regs) { - struct pt_regs *regs = RELOC_HIDE(&__regs, 0); #ifdef CONFIG_MMU + struct pt_regs *regs = RELOC_HIDE(&__regs, 0); return do_fork(SIGCHLD, regs->regs[15], regs, 0, NULL, NULL); #else /* fork almost works, enough to trick you into looking elsewhere :-( */ @@ -449,23 +448,20 @@ asmlinkage int sys_vfork(unsigned long r4, unsigned long r5, /* * sys_execve() executes a new program. */ -asmlinkage int sys_execve(char *ufilename, char **uargv, - char **uenvp, unsigned long r7, +asmlinkage int sys_execve(char __user *ufilename, char __user * __user *uargv, + char __user * __user *uenvp, unsigned long r7, struct pt_regs __regs) { struct pt_regs *regs = RELOC_HIDE(&__regs, 0); int error; char *filename; - filename = getname((char __user *)ufilename); + filename = getname(ufilename); error = PTR_ERR(filename); if (IS_ERR(filename)) goto out; - error = do_execve(filename, - (char __user * __user *)uargv, - (char __user * __user *)uenvp, - regs); + error = do_execve(filename, uargv, uenvp, regs); if (error == 0) { task_lock(current); current->ptrace &= ~PT_DTRACE; diff --git a/arch/sh/kernel/ptrace.c b/arch/sh/kernel/ptrace.c index 3fb5fc0b550..891d1d46c90 100644 --- a/arch/sh/kernel/ptrace.c +++ b/arch/sh/kernel/ptrace.c @@ -91,17 +91,8 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) switch (request) { /* when I and D space are separate, these will need to be fixed. */ case PTRACE_PEEKTEXT: /* read word at location addr. */ - case PTRACE_PEEKDATA: { - unsigned long tmp; - int copied; - - copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0); - ret = -EIO; - if (copied != sizeof(tmp)) - break; - ret = put_user(tmp,(unsigned long *) data); - break; - } + case PTRACE_PEEKDATA: + ret = generic_ptrace_peekdata(child, addr, data); /* read the word at location addr in the USER area. */ case PTRACE_PEEKUSR: { @@ -128,17 +119,14 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) tmp = !!tsk_used_math(child); else tmp = 0; - ret = put_user(tmp, (unsigned long *)data); + ret = put_user(tmp, (unsigned long __user *)data); break; } /* when I and D space are separate, this will have to be fixed. */ case PTRACE_POKETEXT: /* write the word at location addr. */ case PTRACE_POKEDATA: - ret = 0; - if (access_process_vm(child, addr, &data, sizeof(data), 1) == sizeof(data)) - break; - ret = -EIO; + ret = generic_ptrace_pokedata(child, addr, data); break; case PTRACE_POKEUSR: /* write the word at location addr in the USER area */ @@ -196,7 +184,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) case PTRACE_SINGLESTEP: { /* set the trap flag. */ long pc; - struct pt_regs *dummy = NULL; + struct pt_regs *regs = NULL; ret = -EIO; if (!valid_signal(data)) @@ -207,7 +195,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) child->ptrace |= PT_DTRACE; } - pc = get_stack_long(child, (long)&dummy->pc); + pc = get_stack_long(child, (long)®s->pc); /* Next scheduling will set up UBC */ if (child->thread.ubc_pc == 0) diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index c2772913593..c14a3e95d0b 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -21,8 +21,10 @@ #include <linux/fs.h> #include <linux/mm.h> #include <linux/kexec.h> +#include <linux/module.h> #include <asm/uaccess.h> #include <asm/io.h> +#include <asm/page.h> #include <asm/sections.h> #include <asm/irq.h> #include <asm/setup.h> @@ -41,20 +43,19 @@ extern void * __rd_start, * __rd_end; * The bigger value means no problem. */ struct sh_cpuinfo boot_cpu_data = { CPU_SH_NONE, 10000000, }; + +/* + * The machine vector. First entry in .machvec.init, or clobbered by + * sh_mv= on the command line, prior to .machvec.init teardown. + */ +struct sh_machine_vector sh_mv = { .mv_name = "generic", }; + #ifdef CONFIG_VT struct screen_info screen_info; #endif -#if defined(CONFIG_SH_UNKNOWN) -struct sh_machine_vector sh_mv; -#endif - extern int root_mountflags; -#define MV_NAME_SIZE 32 - -static struct sh_machine_vector* __init get_mv_byname(const char* name); - /* * This is set up by the setup-routine at boot-time */ @@ -78,133 +79,23 @@ static char __initdata command_line[COMMAND_LINE_SIZE] = { 0, }; static struct resource code_resource = { .name = "Kernel code", }; static struct resource data_resource = { .name = "Kernel data", }; -unsigned long memory_start, memory_end; +unsigned long memory_start; +EXPORT_SYMBOL(memory_start); -static inline void parse_cmdline (char ** cmdline_p, char mv_name[MV_NAME_SIZE], - struct sh_machine_vector** mvp, - unsigned long *mv_io_base) -{ - char c = ' ', *to = command_line, *from = COMMAND_LINE; - int len = 0; +unsigned long memory_end; +EXPORT_SYMBOL(memory_end); - /* Save unparsed command line copy for /proc/cmdline */ - memcpy(boot_command_line, COMMAND_LINE, COMMAND_LINE_SIZE); - boot_command_line[COMMAND_LINE_SIZE-1] = '\0'; - - memory_start = (unsigned long)PAGE_OFFSET+__MEMORY_START; - memory_end = memory_start + __MEMORY_SIZE; - - for (;;) { - /* - * "mem=XXX[kKmM]" defines a size of memory. - */ - if (c == ' ' && !memcmp(from, "mem=", 4)) { - if (to != command_line) - to--; - { - unsigned long mem_size; - - mem_size = memparse(from+4, &from); - memory_end = memory_start + mem_size; - } - } - - if (c == ' ' && !memcmp(from, "sh_mv=", 6)) { - char* mv_end; - char* mv_comma; - int mv_len; - if (to != command_line) - to--; - from += 6; - mv_end = strchr(from, ' '); - if (mv_end == NULL) - mv_end = from + strlen(from); - - mv_comma = strchr(from, ','); - if ((mv_comma != NULL) && (mv_comma < mv_end)) { - int ints[3]; - get_options(mv_comma+1, ARRAY_SIZE(ints), ints); - *mv_io_base = ints[1]; - mv_len = mv_comma - from; - } else { - mv_len = mv_end - from; - } - if (mv_len > (MV_NAME_SIZE-1)) - mv_len = MV_NAME_SIZE-1; - memcpy(mv_name, from, mv_len); - mv_name[mv_len] = '\0'; - from = mv_end; - - *mvp = get_mv_byname(mv_name); - } - - c = *(from++); - if (!c) - break; - if (COMMAND_LINE_SIZE <= ++len) - break; - *(to++) = c; - } - *to = '\0'; - *cmdline_p = command_line; -} - -static int __init sh_mv_setup(char **cmdline_p) +static int __init early_parse_mem(char *p) { -#ifdef CONFIG_SH_UNKNOWN - extern struct sh_machine_vector mv_unknown; -#endif - struct sh_machine_vector *mv = NULL; - char mv_name[MV_NAME_SIZE] = ""; - unsigned long mv_io_base = 0; - - parse_cmdline(cmdline_p, mv_name, &mv, &mv_io_base); - -#ifdef CONFIG_SH_UNKNOWN - if (mv == NULL) { - mv = &mv_unknown; - if (*mv_name != '\0') { - printk("Warning: Unsupported machine %s, using unknown\n", - mv_name); - } - } - sh_mv = *mv; -#endif - - /* - * Manually walk the vec, fill in anything that the board hasn't yet - * by hand, wrapping to the generic implementation. - */ -#define mv_set(elem) do { \ - if (!sh_mv.mv_##elem) \ - sh_mv.mv_##elem = generic_##elem; \ -} while (0) - - mv_set(inb); mv_set(inw); mv_set(inl); - mv_set(outb); mv_set(outw); mv_set(outl); - - mv_set(inb_p); mv_set(inw_p); mv_set(inl_p); - mv_set(outb_p); mv_set(outw_p); mv_set(outl_p); - - mv_set(insb); mv_set(insw); mv_set(insl); - mv_set(outsb); mv_set(outsw); mv_set(outsl); - - mv_set(readb); mv_set(readw); mv_set(readl); - mv_set(writeb); mv_set(writew); mv_set(writel); + unsigned long size; - mv_set(ioport_map); - mv_set(ioport_unmap); - mv_set(irq_demux); - -#ifdef CONFIG_SH_UNKNOWN - __set_io_port_base(mv_io_base); -#endif - - if (!sh_mv.mv_nr_irqs) - sh_mv.mv_nr_irqs = NR_IRQS; + memory_start = (unsigned long)PAGE_OFFSET+__MEMORY_START; + size = memparse(p, &p); + memory_end = memory_start + size; return 0; } +early_param("mem", early_parse_mem); /* * Register fully available low RAM pages with the bootmem allocator. @@ -230,7 +121,7 @@ static void __init register_bootmem_low_pages(void) free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(pages)); } -void __init setup_bootmem_allocator(unsigned long start_pfn) +void __init setup_bootmem_allocator(unsigned long free_pfn) { unsigned long bootmap_size; @@ -239,9 +130,10 @@ void __init setup_bootmem_allocator(unsigned long start_pfn) * bootstrap step all allocations (until the page allocator * is intact) must be done via bootmem_alloc(). */ - bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn, + bootmap_size = init_bootmem_node(NODE_DATA(0), free_pfn, min_low_pfn, max_low_pfn); + add_active_range(0, min_low_pfn, max_low_pfn); register_bootmem_low_pages(); node_set_online(0); @@ -254,7 +146,7 @@ void __init setup_bootmem_allocator(unsigned long start_pfn) * an invalid RAM area. */ reserve_bootmem(__MEMORY_START+PAGE_SIZE, - (PFN_PHYS(start_pfn)+bootmap_size+PAGE_SIZE-1)-__MEMORY_START); + (PFN_PHYS(free_pfn)+bootmap_size+PAGE_SIZE-1)-__MEMORY_START); /* * reserve physical page 0 - it's a special BIOS page on many boxes, @@ -262,6 +154,8 @@ void __init setup_bootmem_allocator(unsigned long start_pfn) */ reserve_bootmem(__MEMORY_START, PAGE_SIZE); + sparse_memory_present_with_active_regions(0); + #ifdef CONFIG_BLK_DEV_INITRD ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0); if (&__rd_start != &__rd_end) { @@ -315,10 +209,6 @@ void __init setup_arch(char **cmdline_p) { enable_mmu(); -#ifdef CONFIG_CMDLINE_BOOL - strcpy(COMMAND_LINE, CONFIG_CMDLINE); -#endif - ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV); #ifdef CONFIG_BLK_DEV_RAM @@ -339,9 +229,22 @@ void __init setup_arch(char **cmdline_p) data_resource.start = virt_to_phys(_etext); data_resource.end = virt_to_phys(_edata)-1; + memory_start = (unsigned long)PAGE_OFFSET+__MEMORY_START; + memory_end = memory_start + __MEMORY_SIZE; + +#ifdef CONFIG_CMDLINE_BOOL + strlcpy(command_line, CONFIG_CMDLINE, sizeof(command_line)); +#else + strlcpy(command_line, COMMAND_LINE, sizeof(command_line)); +#endif + + /* Save unparsed command line copy for /proc/cmdline */ + memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); + *cmdline_p = command_line; + parse_early_param(); - sh_mv_setup(cmdline_p); + sh_mv_setup(); /* * Find the highest page frame number we have available @@ -355,8 +258,9 @@ void __init setup_arch(char **cmdline_p) min_low_pfn = __MEMORY_START >> PAGE_SHIFT; nodes_clear(node_online_map); + + /* Setup bootmem with available RAM */ setup_memory(); - paging_init(); sparse_init(); #ifdef CONFIG_DUMMY_CONSOLE @@ -366,46 +270,13 @@ void __init setup_arch(char **cmdline_p) /* Perform the machine specific initialisation */ if (likely(sh_mv.mv_setup)) sh_mv.mv_setup(cmdline_p); -} - -struct sh_machine_vector* __init get_mv_byname(const char* name) -{ - extern long __machvec_start, __machvec_end; - struct sh_machine_vector *all_vecs = - (struct sh_machine_vector *)&__machvec_start; - - int i, n = ((unsigned long)&__machvec_end - - (unsigned long)&__machvec_start)/ - sizeof(struct sh_machine_vector); - - for (i = 0; i < n; ++i) { - struct sh_machine_vector *mv = &all_vecs[i]; - if (mv == NULL) - continue; - if (strcasecmp(name, get_system_type()) == 0) { - return mv; - } - } - return NULL; -} - -static struct cpu cpu[NR_CPUS]; - -static int __init topology_init(void) -{ - int cpu_id; - for_each_possible_cpu(cpu_id) - register_cpu(&cpu[cpu_id], cpu_id); - - return 0; + paging_init(); } -subsys_initcall(topology_init); - static const char *cpu_name[] = { [CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619", - [CPU_SH7604] = "SH7604", [CPU_SH7300] = "SH7300", + [CPU_SH7300] = "SH7300", [CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706", [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708", [CPU_SH7709] = "SH7709", [CPU_SH7710] = "SH7710", @@ -419,7 +290,7 @@ static const char *cpu_name[] = { [CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785", [CPU_SH7722] = "SH7722", - [CPU_SH_NONE] = "Unknown" + [CPU_SHX3] = "SH-X3", [CPU_SH_NONE] = "Unknown" }; const char *get_cpu_subtype(struct sh_cpuinfo *c) diff --git a/arch/sh/kernel/sh_bios.c b/arch/sh/kernel/sh_bios.c index 5b53e10bb9c..d1bcac4fa26 100644 --- a/arch/sh/kernel/sh_bios.c +++ b/arch/sh/kernel/sh_bios.c @@ -5,7 +5,7 @@ * Copyright (C) 2000 Greg Banks, Mitch Davis * */ - +#include <linux/module.h> #include <asm/sh_bios.h> #define BIOS_CALL_CONSOLE_WRITE 0 @@ -63,6 +63,7 @@ void sh_bios_gdb_detach(void) { sh_bios_call(BIOS_CALL_GDB_DETACH, 0, 0, 0, 0); } +EXPORT_SYMBOL(sh_bios_gdb_detach); void sh_bios_get_node_addr (unsigned char *node_addr) { diff --git a/arch/sh/kernel/sh_ksyms.c b/arch/sh/kernel/sh_ksyms.c index c1cfcb9f047..37aef0a8519 100644 --- a/arch/sh/kernel/sh_ksyms.c +++ b/arch/sh/kernel/sh_ksyms.c @@ -63,10 +63,43 @@ EXPORT_SYMBOL(__const_udelay); /* These symbols are generated by the compiler itself */ DECLARE_EXPORT(__udivsi3); DECLARE_EXPORT(__sdivsi3); +DECLARE_EXPORT(__ashrsi3); +DECLARE_EXPORT(__ashlsi3); DECLARE_EXPORT(__ashrdi3); DECLARE_EXPORT(__ashldi3); +DECLARE_EXPORT(__ashiftrt_r4_6); +DECLARE_EXPORT(__ashiftrt_r4_7); +DECLARE_EXPORT(__ashiftrt_r4_8); +DECLARE_EXPORT(__ashiftrt_r4_9); +DECLARE_EXPORT(__ashiftrt_r4_10); +DECLARE_EXPORT(__ashiftrt_r4_11); +DECLARE_EXPORT(__ashiftrt_r4_12); +DECLARE_EXPORT(__ashiftrt_r4_13); +DECLARE_EXPORT(__ashiftrt_r4_14); +DECLARE_EXPORT(__ashiftrt_r4_15); +DECLARE_EXPORT(__ashiftrt_r4_20); +DECLARE_EXPORT(__ashiftrt_r4_21); +DECLARE_EXPORT(__ashiftrt_r4_22); +DECLARE_EXPORT(__ashiftrt_r4_23); +DECLARE_EXPORT(__ashiftrt_r4_24); +DECLARE_EXPORT(__ashiftrt_r4_27); +DECLARE_EXPORT(__ashiftrt_r4_30); +DECLARE_EXPORT(__lshrsi3); DECLARE_EXPORT(__lshrdi3); +DECLARE_EXPORT(__movstrSI8); +DECLARE_EXPORT(__movstrSI12); DECLARE_EXPORT(__movstrSI16); +DECLARE_EXPORT(__movstrSI20); +DECLARE_EXPORT(__movstrSI24); +DECLARE_EXPORT(__movstrSI28); +DECLARE_EXPORT(__movstrSI32); +DECLARE_EXPORT(__movstrSI36); +DECLARE_EXPORT(__movstrSI40); +DECLARE_EXPORT(__movstrSI44); +DECLARE_EXPORT(__movstrSI48); +DECLARE_EXPORT(__movstrSI52); +DECLARE_EXPORT(__movstrSI56); +DECLARE_EXPORT(__movstrSI60); #if __GNUC__ == 4 DECLARE_EXPORT(__movmem); #else @@ -78,6 +111,16 @@ DECLARE_EXPORT(__movstr); DECLARE_EXPORT(__movmem_i4_even); DECLARE_EXPORT(__movmem_i4_odd); DECLARE_EXPORT(__movmemSI12_i4); + +#if (__GNUC_MINOR__ == 2 || defined(__GNUC_STM_RELEASE__)) +/* + * GCC 4.2 emits these for division, as do GCC 4.1.x versions of the ST + * compiler which include backported patches. + */ +DECLARE_EXPORT(__sdivsi3_i4i); +DECLARE_EXPORT(__udiv_qrnnd_16); +DECLARE_EXPORT(__udivsi3_i4i); +#endif #else /* GCC 3.x */ DECLARE_EXPORT(__movstr_i4_even); DECLARE_EXPORT(__movstr_i4_odd); @@ -105,7 +148,9 @@ EXPORT_SYMBOL(synchronize_irq); #endif EXPORT_SYMBOL(csum_partial); +EXPORT_SYMBOL(csum_partial_copy_generic); #ifdef CONFIG_IPV6 EXPORT_SYMBOL(csum_ipv6_magic); #endif EXPORT_SYMBOL(clear_page); +EXPORT_SYMBOL(__clear_user); diff --git a/arch/sh/kernel/signal.c b/arch/sh/kernel/signal.c index e323e299878..706d81ccd10 100644 --- a/arch/sh/kernel/signal.c +++ b/arch/sh/kernel/signal.c @@ -23,6 +23,7 @@ #include <linux/personality.h> #include <linux/binfmts.h> #include <linux/freezer.h> +#include <linux/io.h> #include <asm/system.h> #include <asm/ucontext.h> #include <asm/uaccess.h> @@ -261,7 +262,7 @@ asmlinkage int sys_rt_sigreturn(unsigned long r4, unsigned long r5, goto badframe; /* It is more difficult to avoid calling this function than to call it and ignore errors. */ - do_sigaltstack(&st, NULL, regs->regs[15]); + do_sigaltstack((const stack_t __user *)&st, NULL, (unsigned long)frame); return r0; diff --git a/arch/sh/kernel/syscalls.S b/arch/sh/kernel/syscalls.S index 7db1c2dc599..91fb7024e06 100644 --- a/arch/sh/kernel/syscalls.S +++ b/arch/sh/kernel/syscalls.S @@ -308,9 +308,9 @@ ENTRY(sys_call_table) .long sys_utimes .long sys_fadvise64_64_wrapper .long sys_ni_syscall /* Reserved for vserver */ - .long sys_ni_syscall /* Reserved for mbind */ - .long sys_ni_syscall /* 275 - get_mempolicy */ - .long sys_ni_syscall /* set_mempolicy */ + .long sys_mbind + .long sys_get_mempolicy /* 275 */ + .long sys_set_mempolicy .long sys_mq_open .long sys_mq_unlink .long sys_mq_timedsend @@ -358,3 +358,4 @@ ENTRY(sys_call_table) .long sys_signalfd .long sys_timerfd .long sys_eventfd + .long sys_fallocate diff --git a/arch/sh/kernel/timers/timer-tmu.c b/arch/sh/kernel/timers/timer-tmu.c index 2d997e2a5b6..7aca37d7976 100644 --- a/arch/sh/kernel/timers/timer-tmu.c +++ b/arch/sh/kernel/timers/timer-tmu.c @@ -30,7 +30,7 @@ static int tmu_timer_start(void) { - ctrl_outb(ctrl_inb(TMU_TSTR) | 0x3, TMU_TSTR); + ctrl_outb(ctrl_inb(TMU_012_TSTR) | 0x3, TMU_012_TSTR); return 0; } @@ -52,7 +52,7 @@ static void tmu0_timer_set_interval(unsigned long interval, unsigned int reload) static int tmu_timer_stop(void) { - ctrl_outb(ctrl_inb(TMU_TSTR) & ~0x3, TMU_TSTR); + ctrl_outb(ctrl_inb(TMU_012_TSTR) & ~0x3, TMU_012_TSTR); return 0; } @@ -80,6 +80,7 @@ static void tmu_set_mode(enum clock_event_mode mode, break; case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_RESUME: break; } } @@ -174,7 +175,8 @@ static int tmu_timer_init(void) #if !defined(CONFIG_CPU_SUBTYPE_SH7300) && \ !defined(CONFIG_CPU_SUBTYPE_SH7760) && \ - !defined(CONFIG_CPU_SUBTYPE_SH7785) + !defined(CONFIG_CPU_SUBTYPE_SH7785) && \ + !defined(CONFIG_CPU_SUBTYPE_SHX3) ctrl_outb(TMU_TOCR_INIT, TMU_TOCR); #endif diff --git a/arch/sh/kernel/topology.c b/arch/sh/kernel/topology.c new file mode 100644 index 00000000000..9b5844a1bda --- /dev/null +++ b/arch/sh/kernel/topology.c @@ -0,0 +1,49 @@ +/* + * arch/sh/kernel/topology.c + * + * Copyright (C) 2007 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/cpu.h> +#include <linux/cpumask.h> +#include <linux/init.h> +#include <linux/percpu.h> +#include <linux/node.h> +#include <linux/nodemask.h> + +static DEFINE_PER_CPU(struct cpu, cpu_devices); + +static int __init topology_init(void) +{ + int i, ret; + +#ifdef CONFIG_NEED_MULTIPLE_NODES + for_each_online_node(i) + register_one_node(i); +#endif + + for_each_present_cpu(i) { + ret = register_cpu(&per_cpu(cpu_devices, i), i); + if (unlikely(ret)) + printk(KERN_WARNING "%s: register_cpu %d failed (%d)\n", + __FUNCTION__, i, ret); + } + +#if defined(CONFIG_NUMA) && !defined(CONFIG_SMP) + /* + * In the UP case, make sure the CPU association is still + * registered under each node. Without this, sysfs fails + * to make the connection between nodes other than node0 + * and cpu0. + */ + for_each_online_node(i) + if (i != numa_node_id()) + register_cpu_under_node(raw_smp_processor_id(), i); +#endif + + return 0; +} +subsys_initcall(topology_init); diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c index 8f18930d5bf..502d43e4785 100644 --- a/arch/sh/kernel/traps.c +++ b/arch/sh/kernel/traps.c @@ -103,6 +103,7 @@ void die(const char * str, struct pt_regs * regs, long err) (unsigned long)task_stack_page(current)); bust_spinlocks(0); + add_taint(TAINT_DIE); spin_unlock_irq(&die_lock); if (kexec_should_crash(current)) @@ -584,7 +585,7 @@ uspace_segv: info.si_signo = SIGBUS; info.si_errno = 0; info.si_code = si_code; - info.si_addr = (void *) address; + info.si_addr = (void __user *)address; force_sig_info(SIGBUS, &info, current); } else { if (regs->pc & 1) @@ -617,7 +618,7 @@ uspace_segv: */ int is_dsp_inst(struct pt_regs *regs) { - unsigned short inst; + unsigned short inst = 0; /* * Safe guard if DSP mode is already enabled or we're lacking @@ -645,7 +646,6 @@ asmlinkage void do_divide_error(unsigned long r4, unsigned long r5, unsigned long r6, unsigned long r7, struct pt_regs __regs) { - struct pt_regs *regs = RELOC_HIDE(&__regs, 0); siginfo_t info; switch (r4) { @@ -874,7 +874,7 @@ void __init trap_init(void) void handle_BUG(struct pt_regs *regs) { enum bug_trap_type tt; - tt = report_bug(regs->pc); + tt = report_bug(regs->pc, regs); if (tt == BUG_TRAP_TYPE_WARN) { regs->pc += 2; return; diff --git a/arch/sh/kernel/vmlinux.lds.S b/arch/sh/kernel/vmlinux.lds.S index 4c5b57e9c3c..9cb95af7b09 100644 --- a/arch/sh/kernel/vmlinux.lds.S +++ b/arch/sh/kernel/vmlinux.lds.S @@ -22,6 +22,7 @@ SECTIONS *(.empty_zero_page) } = 0 .text : { + *(.text.head) TEXT_TEXT SCHED_TEXT LOCK_TEXT @@ -60,10 +61,7 @@ SECTIONS . = ALIGN(PAGE_SIZE); __nosave_end = .; - . = ALIGN(PAGE_SIZE); - __per_cpu_start = .; - .data.percpu : { *(.data.percpu) } - __per_cpu_end = .; + PERCPU(PAGE_SIZE) .data.cacheline_aligned : { *(.data.cacheline_aligned) } _edata = .; /* End of data section */ @@ -97,18 +95,20 @@ SECTIONS __initramfs_end = .; #endif + . = ALIGN(4); __machvec_start = .; - .init.machvec : { *(.init.machvec) } + .machvec.init : { *(.machvec.init) } __machvec_end = .; - . = ALIGN(PAGE_SIZE); - __init_end = .; - - . = ALIGN(4); - __bss_start = .; /* BSS */ - .bss : { *(.bss) } - . = ALIGN(4); - _end = . ; + . = ALIGN(PAGE_SIZE); + .bss : { + __init_end = .; + __bss_start = .; /* BSS */ + *(.bss.page_aligned) + *(.bss) + . = ALIGN(4); + _end = . ; + } /* When something in the kernel is NOT compiled as a module, the * module cleanup code and data are put into these segments. Both |