obj-$(CONFIG_IA32_EMULATION) += ia32/

obj-y += platform/

config X86_32

def_bool !64BIT

config X86_64

def_bool 64BIT

config X86

def_bool y

select HAVE_AOUT if X86_32

select HAVE_UNSTABLE_SCHED_CLOCK

select HAVE_IDE

select HAVE_OPROFILE

select HAVE_PERF_EVENTS

select HAVE_IRQ_WORK

select HAVE_IOREMAP_PROT

select HAVE_GENERIC_HARDIRQS

select HAVE_SPARSE_IRQ

select GENERIC_FIND_FIRST_BIT

select GENERIC_IRQ_PROBE

select GENERIC_PENDING_IRQ if SMP

select GENERIC_IRQ_SHOW

select IRQ_FORCED_THREADING

select USE_GENERIC_SMP_HELPERS if SMP

config INSTRUCTION_DECODER

def_bool (KPROBES || PERF_EVENTS)

config GENERIC_CLOCKEVENTS

def_bool y

config GENERIC_CLOCKEVENTS_BROADCAST

def_bool y

depends on X86_64 || (X86_32 && X86_LOCAL_APIC)

def_bool y

config ZONE_DMA

config SBUS

bool

# Following is an alphabetically sorted list of 32 bit extended platforms

# Please maintain the alphabetic order if and when there are additions

config X86_INTEL_CE

bool "CE4100 TV platform"

depends on PCI

This option compiles in support for the CE4100 SOC for settop

boxes and media devices.

config X86_MRST

bool "Moorestown MID platform"

depends on PCI

depends on PCI_GOANY

depends on X86_IO_APIC

select APB_TIMER

select I2C

nor standard legacy replacement devices/features. e.g. Moorestown does

not contain i8259, i8254, HPET, legacy BIOS, most of the io ports.

config X86_RDC321X

bool "RDC R-321x SoC"

depends on X86_32

if PARAVIRT_GUEST

source "arch/x86/xen/Kconfig"

config KVM_CLOCK

config APB_TIMER

def_bool y if MRST

prompt "Langwell APB Timer Support" if X86_MRST

help

APB timer is the replacement for 8254, HPET on X86 MID platforms.

The APBT provides a stable time base on SMP

Calgary anyway, pass 'iommu=calgary' on the kernel command line.

If unsure, say Y.

# need this always selected by IOMMU for the VIA workaround

config SWIOTLB

def_bool y if X86_64

config IOMMU_HELPER

def_bool (CALGARY_IOMMU || GART_IOMMU || SWIOTLB || AMD_IOMMU)

config MAXSMP

bool "Enable Maximum number of SMP Processors and NUMA Nodes"

depends on X86_64 && SMP && DEBUG_KERNEL && EXPERIMENTAL

config I8K

tristate "Dell laptop support"

---help---

This adds a driver to safely access the System Management Mode

of the CPU on the Dell Inspiron 8000. The System Management Mode

config NUMA_EMU

bool "NUMA emulation"

---help---

Enable NUMA emulation. A flat machine will be split

into virtual nodes when booted with "numa=fake=N", where N is the

def_bool y

depends on X86_32 && NUMA

config ARCH_HAVE_MEMORY_PRESENT

def_bool y

depends on X86_32 && DISCONTIGMEM

def_bool y

depends on X86_32 && (DISCONTIGMEM || SPARSEMEM)

config ARCH_FLATMEM_ENABLE

def_bool y

config ARCH_DISCONTIGMEM_ENABLE

def_bool y

def_bool y

depends on NUMA && X86_32

config ARCH_SPARSEMEM_ENABLE

def_bool y

depends on X86_64 || NUMA || (EXPERIMENTAL && X86_32) || X86_32_NON_STANDARD

select SPARSEMEM_STATIC if X86_32

select SPARSEMEM_VMEMMAP_ENABLE if X86_64

config ARCH_SELECT_MEMORY_MODEL

def_bool y

depends on ARCH_SPARSEMEM_ENABLE

def_bool X86_64

depends on MEMORY_HOTPLUG

config ILLEGAL_POINTER_VALUE

hex

default 0 if X86_32

def_bool y

depends on MEMORY_HOTPLUG

config USE_PERCPU_NUMA_NODE_ID

def_bool y

depends on NUMA

machines with more than one CPU.

In order to use APM, you will need supporting software. For location

<http://www.tldp.org/docs.html#howto>.

This driver does not spin down disk drives (see the hdparm(8)

endif # APM

source "drivers/cpuidle/Kconfig"

# x86-64 doesn't support PCI BIOS access from long mode so always go direct.

config PCI_DIRECT

def_bool y

config PCI_MMCONFIG

def_bool y

You should say N unless you know you need this.

source "drivers/pci/pcie/Kconfig"

source "drivers/pci/Kconfig"

depends on !X86_PAE

select GPIOLIB

select OF

---help---

Add support for detecting the unique features of the OLPC

XO hardware.

endif # X86_32

# Put here option for CPU selection and depending optimization

choice

prompt "Processor family"

default M686 if X86_32

stores for this CPU, which can increase performance of some

operations.

config MGEODEGX1

bool "GeodeGX1"

depends on X86_32

This is really intended for distributors who need more

generic optimizations.

#

# Define implied options from the CPU selection here

config X86_INTERNODE_CACHE_SHIFT

config CMPXCHG_LOCAL

def_bool X86_64 || (X86_32 && !M386)

config X86_L1_CACHE_SHIFT

int

default "7" if MPENTIUM4 || MPSC

default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU

default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX

config X86_XADD

config X86_ALIGNMENT_16

def_bool y

config X86_INTEL_USERCOPY

def_bool y

This option will cause messages to be printed if free stack space

drops below a certain limit.

config X86_PTDUMP

bool "Export kernel pagetable layout to userspace via debugfs"

depends on DEBUG_KERNEL

$(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic))

# AMD Elan support

# Geode GX1 support

cflags-$(CONFIG_MGEODEGX1) += -march=pentium-mmx

# Changed by many, many contributors over the years.

#

# If you want to preset the SVGA mode, uncomment the next line and

# set SVGA_MODE to whatever number you want.

# Set it to -DSVGA_MODE=NORMAL_VGA if you just want the EGA/VGA mode.

$(obj)/bzImage: asflags-y := $(SVGA_MODE)

quiet_cmd_image = BUILD $@

$(obj)/bzImage: $(obj)/setup.bin $(obj)/vmlinux.bin $(obj)/tools/build FORCE

$(call if_changed,image)

if (oreg.ax > 15*1024) {

return -1; /* Bogus! */

} else if (oreg.ax == 15*1024) {

} else {

/*

* This ignores memory above 16MB if we have a memory

static void usage(void)

{

}

int main(int argc, char ** argv)

unsigned int i, sz, setup_sectors;

int c;

u32 sys_size;

struct stat sb;

FILE *file;

int fd;

void *kernel;

u32 crc = 0xffffffffUL;

usage();

/* Copy the setup code */

file = fopen(argv[1], "r");

memset(buf+c, 0, i-c);

/* Set the default root device */

fprintf(stderr, "Setup is %d bytes (padded to %d bytes).\n", c, i);

CONFIG_AUDIT=y

CONFIG_LOG_BUF_SHIFT=18

CONFIG_CGROUPS=y

CONFIG_CGROUP_FREEZER=y

CONFIG_CPUSETS=y

CONFIG_CGROUP_CPUACCT=y

CONFIG_AUDIT=y

CONFIG_LOG_BUF_SHIFT=18

CONFIG_CGROUPS=y

CONFIG_CGROUP_FREEZER=y

CONFIG_CPUSETS=y

CONFIG_CGROUP_CPUACCT=y

# Arch-specific CryptoAPI modules.

#

obj-$(CONFIG_CRYPTO_AES_586) += aes-i586.o

obj-$(CONFIG_CRYPTO_TWOFISH_586) += twofish-i586.o

obj-$(CONFIG_CRYPTO_SALSA20_586) += salsa20-i586.o

twofish-x86_64-y := twofish-x86_64-asm_64.o twofish_glue.o

salsa20-x86_64-y := salsa20-x86_64-asm_64.o salsa20_glue.o

ghash-clmulni-intel-y := ghash-clmulni-intel_asm.o ghash-clmulni-intel_glue.o

const u8 *in, unsigned int len, u8 *iv);

asmlinkage void aesni_cbc_dec(struct crypto_aes_ctx *ctx, u8 *out,

const u8 *in, unsigned int len, u8 *iv);

#ifdef CONFIG_X86_64

asmlinkage void aesni_ctr_enc(struct crypto_aes_ctx *ctx, u8 *out,

const u8 *in, unsigned int len, u8 *iv);

return -ENODEV;

}

if ((err = crypto_register_alg(&aesni_alg)))

goto aes_err;

if ((err = crypto_register_alg(&__aesni_alg)))

__aes_err:

crypto_unregister_alg(&aesni_alg);

aes_err:

return err;

}

crypto_unregister_alg(&blk_ecb_alg);

crypto_unregister_alg(&__aesni_alg);

crypto_unregister_alg(&aesni_alg);

}

module_init(aesni_init);

.module = THIS_MODULE,

};

{

return crypto_register_template(&crypto_fpu_tmpl);

}

{

crypto_unregister_template(&crypto_fpu_tmpl);

}

crypto_ahash_set_flags(tfm, crypto_ahash_get_flags(child)

& CRYPTO_TFM_RES_MASK);

}

static int ghash_async_init_tfm(struct crypto_tfm *tfm)

asmlinkage long sys32_sigsuspend(int history0, int history1, old_sigset_t mask)

{

current->saved_sigmask = current->blocked;

current->state = TASK_INTERRUPTIBLE;

schedule();

set_restore_sigmask();

return -ERESTARTNOHAND;

}

goto badframe;

sigdelsetmask(&set, ~_BLOCKABLE);

if (ia32_restore_sigcontext(regs, &frame->sc, &ax))

goto badframe;

goto badframe;

sigdelsetmask(&set, ~_BLOCKABLE);

if (ia32_restore_sigcontext(regs, &frame->uc.uc_mcontext, &ax))

goto badframe;

CFI_REL_OFFSET rip,0

pushq_cfi %rax

cld

/* no need to do an access_ok check here because rbp has been

32bit zero extended */

1: movl (%rbp),%ebp

andl $~0x200,EFLAGS-R11(%rsp)

movl RIP-R11(%rsp),%edx /* User %eip */

CFI_REGISTER rip,rdx

xorq %r8,%r8

xorq %r9,%r9

xorq %r10,%r10

* disabled irqs and here we enable it straight after entry:

*/

ENABLE_INTERRUPTS(CLBR_NONE)

movl %eax,%eax /* zero extension */

movq %rax,ORIG_RAX-ARGOFFSET(%rsp)

movq %rcx,RIP-ARGOFFSET(%rsp)

jnz sysretl_audit

sysretl_from_sys_call:

andl $~TS_COMPAT,TI_status(%r10)

movl RIP-ARGOFFSET(%rsp),%ecx

CFI_REGISTER rip,rcx

movl EFLAGS-ARGOFFSET(%rsp),%r11d

cld

/* note the registers are not zero extended to the sf.

this could be a problem. */

GET_THREAD_INFO(%r10)

orl $TS_COMPAT,TI_status(%r10)

testl $_TIF_WORK_SYSCALL_ENTRY,TI_flags(%r10)

.quad compat_sys_open_by_handle_at

.quad compat_sys_clock_adjtime

.quad sys_syncfs

ia32_syscall_end:

#include <asm/mman.h>

#include <asm/types.h>

#include <asm/uaccess.h>

#include <asm/vgtod.h>

#include <asm/sys_ia32.h>

boot_cpu_data.x86_model <= 0x05 &&

boot_cpu_data.x86_mask < 0x0A)

return 1;

return 1;

else

return max_cstate;

#define ARCH_HAS_POWER_INIT 1

#ifdef CONFIG_ACPI_NUMA

extern int acpi_numa;

extern int x86_acpi_numa_init(void);

.endm

#endif

#endif /* __ASSEMBLY__ */

#include <linux/types.h>

#include <linux/stddef.h>

#include <linux/stringify.h>

#include <asm/asm.h>

/*

#endif

struct alt_instr {

u16 cpuid; /* cpuid bit set for replacement */

u8 instrlen; /* length of original instruction */

u8 replacementlen; /* length of new instruction, <= instrlen */

"661:\n\t" oldinstr "\n662:\n" \

".section .altinstructions,\"a\"\n" \

_ASM_ALIGN "\n" \

" .word " __stringify(feature) "\n" /* feature bit */ \

" .byte 662b-661b\n" /* sourcelen */ \

" .byte 664f-663f\n" /* replacementlen */ \

extern void *text_poke_smp(void *addr, const void *opcode, size_t len);

extern void text_poke_smp_batch(struct text_poke_param *params, int n);

#endif /* _ASM_X86_ALTERNATIVE_H */

extern const struct pci_device_id amd_nb_misc_ids[];

extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];

extern bool early_is_amd_nb(u32 value);

extern int amd_cache_northbridges(void);

#ifdef CONFIG_APB_TIMER

/* default memory mapped register base */

#define LNW_SCU_ADDR 0xFF100000

#define LNW_EXT_TIMER_OFFSET 0x1B800

#define LNW_EXT_TIMER_PGOFFSET 0x800

/* APBT clock speed range from PCLK to fabric base, 25-100MHz */

#define APBT_MMAP_SIZE 1024

#define APBT_DEV_USED 1

extern void apbt_time_init(void);

extern unsigned long apbt_quick_calibrate(void);

extern int arch_setup_apbt_irqs(int irq, int trigger, int mask, int cpu);

extern void apbt_setup_secondary_clock(void);

#else /* CONFIG_APB_TIMER */

static inline unsigned long apbt_quick_calibrate(void) {return 0; }

#endif

#endif /* ASM_X86_APBT_H */

#include <asm/cpufeature.h>

#include <asm/processor.h>

#include <asm/apicdef.h>

#include <asm/fixmap.h>

#include <asm/mpspec.h>

#include <asm/system.h>

*/

int (*x86_32_early_logical_apicid)(int cpu);

int (*x86_32_numa_cpu_node)(int cpu);

#endif

};

extern struct apic *apic;

/*

* APIC functionality to boot other CPUs - only used on SMP:

*/

#ifdef CONFIG_SMP

#define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469

#ifdef CONFIG_X86_64

extern int default_acpi_madt_oem_check(char *, char *);

extern void apic_send_IPI_self(int vector);

DECLARE_PER_CPU(int, x2apic_extra_bits);

extern int default_cpu_present_to_apicid(int mps_cpu);

return;

}

#ifdef CONFIG_X86_LOCAL_APIC

#ifdef CONFIG_X86_32

static inline int noop_x86_32_early_logical_apicid(int cpu)

{

return BAD_APICID;

return cpuid_apic >> index_msb;

}

#endif

static inline unsigned int

#define APIC_DEST_LOGICAL 0x00800

#define APIC_DEST_PHYSICAL 0x00000

#define APIC_DM_FIXED 0x00000

#define APIC_DM_LOWEST 0x00100

#define APIC_DM_SMI 0x00200

#define APIC_DM_REMRD 0x00300

#ifdef __ASSEMBLY__

# define __ASM_FORM(x) x

# define __ASM_EX_SEC .section __ex_table, "a"

#else

# define __ASM_FORM(x) " " #x " "

# define __ASM_EX_SEC " .section __ex_table,\"a\"\n"

#endif

# define __ASM_SEL(a,b) __ASM_FORM(b)

#endif

#define __ASM_REG(reg) __ASM_SEL(e##reg, r##reg)

#define _ASM_PTR __ASM_SEL(.long, .quad)

}

/**

* @v: pointer of type atomic_t

* @a: the amount to add to v...

* @u: ...unless v is equal to u.

*

* Atomically adds @a to @v, so long as @v was not already @u.

*/

{

int c, old;

c = atomic_read(v);

break;

c = old;

}

}

/*

* atomic_dec_if_positive - decrement by 1 if old value positive

# include "atomic64_64.h"

#endif

#endif /* _ASM_X86_ATOMIC_H */

* @u: ...unless v is equal to u.

*

* Atomically adds @a to @v, so long as it was not @u.

*/

static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)

{

* @u: ...unless v is equal to u.

*

* Atomically adds @a to @v, so long as it was not @u.

*/

static inline int atomic64_add_unless(atomic64_t *v, long a, long u)

{

#include <asm/io.h>

/*

*/

static inline unsigned int get_bios_ebda(void)

{

unsigned int address = *(unsigned short *)phys_to_virt(0x40E);

address <<= 4;

return address; /* 0 means none */

}

void reserve_ebda_region(void);

#ifdef CONFIG_X86_CHECK_BIOS_CORRUPTION

#include <asm-generic/bitops/le.h>

#endif /* __KERNEL__ */

#endif /* _ASM_X86_BITOPS_H */

*/

/*

* 64-bit system call stack frame layout defines and helpers, for

#define ARGOFFSET R11

#define SWFRAME ORIG_RAX

subq $9*8+\addskip, %rsp

CFI_ADJUST_CFA_OFFSET 9*8+\addskip

.endif

.endif

.endm

#define ARG_SKIP (9*8)

.endif

.endif

.endif

.endif

.endif

.if ARG_SKIP+\addskip > 0

addq $ARG_SKIP+\addskip, %rsp

CFI_ADJUST_CFA_OFFSET -(ARG_SKIP+\addskip)

.macro SAVE_REST

subq $REST_SKIP, %rsp

CFI_ADJUST_CFA_OFFSET REST_SKIP

.endm

.macro RESTORE_REST

addq $REST_SKIP, %rsp

CFI_ADJUST_CFA_OFFSET -(REST_SKIP)

.endm

.macro RESTORE_ALL addskip=0

RESTORE_REST

.endm

.macro icebp

#endif

#endif /* _ASM_X86_CMPXCHG_32_H */

cmpxchg_local((ptr), (o), (n)); \

})

#endif /* _ASM_X86_CMPXCHG_64_H */

#define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */

#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */

#define X86_FEATURE_F16C (4*32+29) /* 16-bit fp conversions */

#define X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */

/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */

/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */

#define X86_FEATURE_FSGSBASE (9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/

#if defined(__KERNEL__) && !defined(__ASSEMBLY__)

#define test_cpu_cap(c, bit) \

test_bit(bit, (unsigned long *)((c)->x86_capability))

( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \

(((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \

(((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \

(((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \

(((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) || \

(((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) || \

test_cpu_cap(c, bit))

#define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit)

#define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability))

#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR)

#define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ)

#define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE)

#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)

# define cpu_has_invlpg 1

"2:\n"

".section .altinstructions,\"a\"\n"

_ASM_ALIGN "\n"

" .word %P0\n" /* feature bit */

" .byte 2b - 1b\n" /* source len */

" .byte 0\n" /* replacement len */

"2:\n"

".section .altinstructions,\"a\"\n"

_ASM_ALIGN "\n"

" .word %P1\n" /* feature bit */

" .byte 2b - 1b\n" /* source len */

" .byte 4f - 3f\n" /* replacement len */

#ifndef _ASM_X86_DELAY_H

#define _ASM_X86_DELAY_H

void use_tsc_delay(void);

#include <asm/desc_defs.h>

#include <asm/ldt.h>

#include <asm/mmu.h>

#include <linux/smp.h>

/*

* Don't allow setting of the lm bit. It is useless anyway

* because 64bit system calls require __USER_CS:

*/

}

extern struct desc_ptr idt_descr;

struct gdt_page {

struct desc_struct gdt[GDT_ENTRIES];

} __attribute__((aligned(PAGE_SIZE)));

DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page);

static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)

static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,

unsigned dpl, unsigned ist, unsigned seg)

{

}

#else

unsigned short seg)

{

gate->a = (seg << 16) | (base & 0xffff);

}

#endif

static inline int desc_empty(const void *ptr)

{

const u32 *desc = ptr;

return !(desc[0] | desc[1]);

}

#ifdef CONFIG_PARAVIRT

#include <asm/paravirt.h>

#else

static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)

{

#define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))

{

memcpy(&idt[entry], gate, sizeof(*gate));

}

{

memcpy(&ldt[entry], desc, 8);

}

{

unsigned int size;

switch (type) {

}

memcpy(&gdt[entry], desc, size);

}

}

{

#ifdef CONFIG_X86_64

struct ldttss_desc64 *desc = d;

memset(desc, 0, sizeof(*desc));

#else

pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0);

#endif

static inline unsigned long native_store_tr(void)

{

unsigned long tr;

asm volatile("str %0":"=r" (tr));

return tr;

}

static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)

{

struct desc_struct *gdt = get_cpu_gdt_table(cpu);

for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)

gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];

unsigned dpl, unsigned ist, unsigned seg)

{

gate_desc s;

pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);

/*

* does not need to be atomic because it is only done once at

set_bit(vector, used_vectors);

if (first_system_vector > vector)

first_system_vector = vector;

BUG();

}

static inline void alloc_intr_gate(unsigned int n, void *addr)

#define MAX_DMA_CHANNELS 8

/* 16MB ISA DMA zone */

#define MAX_DMA_PFN ((16 * 1024 * 1024) >> PAGE_SHIFT)

/* 4GB broken PCI/AGP hardware bus master zone */

#define MAX_DMA32_PFN ((4UL * 1024 * 1024 * 1024) >> PAGE_SHIFT)

/* Compat define for old dma zone */

#define MAX_DMA_ADDRESS ((unsigned long)__va(MAX_DMA_PFN << PAGE_SHIFT))

#endif

/* 8237 DMA controllers */

#endif /* CONFIG_X86_32 */

extern int add_efi_memmap;

extern void efi_memblock_x86_reserve_range(void);

extern void efi_call_phys_prelog(void);

extern void efi_call_phys_epilog(void);

BUILD_INTERRUPT(threshold_interrupt,THRESHOLD_APIC_VECTOR)

#endif

#endif

VSYSCALL_LAST_PAGE,

VSYSCALL_FIRST_PAGE = VSYSCALL_LAST_PAGE

+ ((VSYSCALL_END-VSYSCALL_START) >> PAGE_SHIFT) - 1,

VSYSCALL_HPET,

#endif

FIX_DBGP_BASE,

#ifdef __ASSEMBLY__

#include <asm/dwarf2.h>

/* The annotation hides the frame from the unwinder and makes it look

frame pointer later */

#ifdef CONFIG_FRAME_POINTER

.macro FRAME

.endm

.macro ENDFRAME

.endm

#else

.macro FRAME

static inline unsigned long ftrace_call_adjust(unsigned long addr)

{

/*

*/

}

#ifdef CONFIG_DYNAMIC_FTRACE

* Don't enable translation but enable GART IO and CPU accesses.

* Also, set DISTLBWALKPRB since GART tables memory is UC.

*/

pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);

}

{

u32 tmp, ctl;

}

static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)

#include <linux/profile.h>

#include <linux/smp.h>

#include <asm/irq.h>

#include <asm/sections.h>

extern void spurious_interrupt(void);

extern void thermal_interrupt(void);

extern void reschedule_interrupt(void);

extern void invalidate_interrupt(void);

extern void invalidate_interrupt0(void);

static inline void exit_idle(void) { }

#endif /* CONFIG_X86_64 */

#endif /* _ASM_X86_IDLE_H */

#include <linux/string.h>

#include <linux/compiler.h>

#include <asm/page.h>

#include <xen/xen.h>

build_mmio_read(readq, "q", unsigned long, "=r", :"memory")

build_mmio_write(writeq, "q", unsigned long, "r", :"memory")

#define readq_relaxed(a) readq(a)

#define __raw_readq(a) readq(a)

#define readq readq

#define writeq writeq

/**

* virt_to_phys - map virtual addresses to physical

* @address: address to remap

* # of IO-APICs and # of IRQ routing registers

*/

extern int nr_ioapics;

/* # of MP IRQ source entries */

extern int mp_irq_entries;

extern void ioapic_and_gsi_init(void);

extern void ioapic_insert_resources(void);

extern int get_nr_irqs_gsi(void);

static inline int io_apic_set_pci_routing(struct device *dev, int irq,

struct io_apic_irq_attr *irq_attr) { return 0; }

{

return -ENOMEM;

}

{

return -ENOMEM;

}

* Vectors 0 ... 31 : system traps and exceptions - hardcoded events

* Vectors 32 ... 127 : device interrupts

* Vector 128 : legacy int80 syscall interface

* Vectors INVALIDATE_TLB_VECTOR_START ... 255 : special interrupts

*

* 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table.

#ifdef CONFIG_X86_32

# define SYSCALL_VECTOR 0x80

#endif

/*

* Vectors 0x30-0x3f are used for ISA interrupts.

#define UV_BAU_MESSAGE 0xf5

/* Xen vector callback to receive events in a HVM domain */

#define XEN_HVM_EVTCHN_CALLBACK 0xf3

#include <asm/paravirt.h>

#else

#ifndef __ASSEMBLY__

{

return native_save_fl();

}

{

native_restore_fl(flags);

}

{

native_irq_disable();

}

{

native_irq_enable();

}

/*

* For spinlocks, etc:

*/

{

unsigned long flags = arch_local_save_flags();

arch_local_irq_disable();

#include <linux/types.h>

#include <asm/nops.h>

#define JUMP_LABEL_NOP_SIZE 5

#endif /* __KERNEL__ */

extern void show_trace(struct task_struct *t, struct pt_regs *regs,

unsigned long *sp, unsigned long bp);

extern void __show_regs(struct pt_regs *regs, int all);

extern unsigned long oops_begin(void);

extern void oops_end(unsigned long, struct pt_regs *, int signr);

#ifdef CONFIG_KEXEC

}

#define BREAK_INSTR_SIZE 1

#define CACHE_FLUSH_IS_SAFE 1

extern int kgdb_ll_trap(int cmd, const char *str,

struct pt_regs *regs, long err, int trap, int sig);

#include <asm/desc_defs.h>

struct x86_emulate_ctxt;

struct x86_exception {

u8 vector;

};

/*

* x86_emulate_ops:

*

* These operations represent the instruction emulator's interface to memory.

#define X86EMUL_RETRY_INSTR 3 /* retry the instruction for some reason */

#define X86EMUL_CMPXCHG_FAILED 4 /* cmpxchg did not see expected value */

#define X86EMUL_IO_NEEDED 5 /* IO is needed to complete emulation */

struct x86_emulate_ops {

/*

* @val: [OUT] Value read from memory, zero-extended to 'u_long'.

* @bytes: [IN ] Number of bytes to read from memory.

*/

struct x86_exception *fault);

/*

* @val: [OUT] Value write to memory, zero-extended to 'u_long'.

* @bytes: [IN ] Number of bytes to write to memory.

*/

struct x86_exception *fault);

/*

* fetch: Read bytes of standard (non-emulated/special) memory.

* @val: [OUT] Value read from memory, zero-extended to 'u_long'.

* @bytes: [IN ] Number of bytes to read from memory.

*/

struct x86_exception *fault);

/*

* @val: [OUT] Value read from memory, zero-extended to 'u_long'.

* @bytes: [IN ] Number of bytes to read from memory.

*/

/*

* write_emulated: Write bytes to emulated/special memory area.

* required).

* @bytes: [IN ] Number of bytes to write to memory.

*/

unsigned int bytes,

/*

* cmpxchg_emulated: Emulate an atomic (LOCKed) CMPXCHG operation on an

* @new: [IN ] Value to write to @addr.

* @bytes: [IN ] Number of bytes to access using CMPXCHG.

*/

const void *old,

const void *new,

unsigned int bytes,

};

/* Type, address-of, and value of an instruction's operand. */

struct operand {

unsigned int bytes;

union {

unsigned long orig_val;

ulong ea;

unsigned seg;

} mem;

} addr;

union {

unsigned long val;

u64 val64;

char valptr[sizeof(unsigned long) + 2];

};

};

unsigned long end;

};

u8 twobyte;

u8 b;

u8 lock_prefix;

u8 rep_prefix;

u8 op_bytes;

u8 seg_override;

unsigned int d;

int (*execute)(struct x86_emulate_ctxt *ctxt);

/* modrm */

u8 modrm;

u8 modrm_mod;

u8 modrm_rm;

u8 modrm_seg;

bool rip_relative;

struct fetch_cache fetch;

struct read_cache io_read;

struct read_cache mem_read;

};

/* Repeat String Operation Prefix */

/* Execution mode, passed to the emulator. */

#define X86EMUL_MODE_REAL 0 /* Real mode. */

#define X86EMUL_MODE_PROT32 4 /* 32-bit protected mode. */

#define X86EMUL_MODE_PROT64 8 /* 64-bit (long) mode. */

/* Host execution mode. */

#if defined(CONFIG_X86_32)

#define X86EMUL_MODE_HOST X86EMUL_MODE_PROT32

#define EMULATION_FAILED -1

#define EMULATION_OK 0

#define EMULATION_RESTART 1

int x86_emulate_insn(struct x86_emulate_ctxt *ctxt);

int emulator_task_switch(struct x86_emulate_ctxt *ctxt,

u16 tss_selector, int reason,

bool has_error_code, u32 error_code);

#endif /* _ASM_X86_KVM_X86_EMULATE_H */

#define KVM_MEMORY_SLOTS 32

/* memory slots that does not exposed to userspace */

#define KVM_PRIVATE_MEM_SLOTS 4

#define KVM_PIO_PAGE_OFFSET 1

#define KVM_COALESCED_MMIO_PAGE_OFFSET 2

#define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1)

#define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD))

#define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS | \

0xFFFFFF0000000000ULL)

#define INVALID_PAGE (~(hpa_t)0)

#define VALID_PAGE(x) ((x) != INVALID_PAGE)

enum kvm_reg_ex {

VCPU_EXREG_PDPTR = NR_VCPU_REGS,

VCPU_EXREG_CR3,

};

enum {

unsigned invalid:1;

unsigned nxe:1;

unsigned cr0_wp:1;

};

};

* in this shadow page.

*/

DECLARE_BITMAP(slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);

bool unsync;

int root_count; /* Currently serving as active root */

unsigned int unsync_children;