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-rw-r--r--arch/i386/boot/edd.c54
-rw-r--r--arch/i386/boot/video.c2
-rw-r--r--arch/powerpc/boot/flatdevtree.c18
-rw-r--r--arch/powerpc/kernel/Makefile1
-rw-r--r--arch/powerpc/kernel/misc_32.S12
-rw-r--r--arch/powerpc/mm/hash_utils_64.c2
-rw-r--r--arch/powerpc/platforms/cell/spu_syscalls.c1
-rw-r--r--arch/powerpc/platforms/ps3/device-init.c2
-rw-r--r--arch/ppc/kernel/misc.S12
9 files changed, 39 insertions, 65 deletions
diff --git a/arch/i386/boot/edd.c b/arch/i386/boot/edd.c
index 658834d9f92..82b5c846a19 100644
--- a/arch/i386/boot/edd.c
+++ b/arch/i386/boot/edd.c
@@ -19,40 +19,12 @@
#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
-struct edd_dapa {
- u8 pkt_size;
- u8 rsvd;
- u16 sector_cnt;
- u16 buf_off, buf_seg;
- u64 lba;
- u64 buf_lin_addr;
-};
-
/*
* Read the MBR (first sector) from a specific device.
*/
static int read_mbr(u8 devno, void *buf)
{
- struct edd_dapa dapa;
- u16 ax, bx, cx, dx, si;
-
- memset(&dapa, 0, sizeof dapa);
- dapa.pkt_size = sizeof(dapa);
- dapa.sector_cnt = 1;
- dapa.buf_off = (size_t)buf;
- dapa.buf_seg = ds();
- /* dapa.lba = 0; */
-
- ax = 0x4200; /* Extended Read */
- si = (size_t)&dapa;
- dx = devno;
- asm("pushfl; stc; int $0x13; setc %%al; popfl"
- : "+a" (ax), "+S" (si), "+d" (dx)
- : "m" (dapa)
- : "ebx", "ecx", "edi", "memory");
-
- if (!(u8)ax)
- return 0; /* OK */
+ u16 ax, bx, cx, dx;
ax = 0x0201; /* Legacy Read, one sector */
cx = 0x0001; /* Sector 0-0-1 */
@@ -65,11 +37,10 @@ static int read_mbr(u8 devno, void *buf)
return -(u8)ax; /* 0 or -1 */
}
-static u32 read_mbr_sig(u8 devno, struct edd_info *ei)
+static u32 read_mbr_sig(u8 devno, struct edd_info *ei, u32 *mbrsig)
{
int sector_size;
char *mbrbuf_ptr, *mbrbuf_end;
- u32 mbrsig;
u32 buf_base, mbr_base;
extern char _end[];
@@ -85,15 +56,15 @@ static u32 read_mbr_sig(u8 devno, struct edd_info *ei)
/* Make sure we actually have space on the heap... */
if (!(boot_params.hdr.loadflags & CAN_USE_HEAP))
- return 0;
+ return -1;
if (mbrbuf_end > (char *)(size_t)boot_params.hdr.heap_end_ptr)
- return 0;
+ return -1;
if (read_mbr(devno, mbrbuf_ptr))
- return 0;
+ return -1;
- mbrsig = *(u32 *)&mbrbuf_ptr[EDD_MBR_SIG_OFFSET];
- return mbrsig;
+ *mbrsig = *(u32 *)&mbrbuf_ptr[EDD_MBR_SIG_OFFSET];
+ return 0;
}
static int get_edd_info(u8 devno, struct edd_info *ei)
@@ -160,6 +131,7 @@ void query_edd(void)
int do_edd = 1;
int devno;
struct edd_info ei, *edp;
+ u32 *mbrptr;
if (cmdline_find_option("edd", eddarg, sizeof eddarg) > 0) {
if (!strcmp(eddarg, "skipmbr") || !strcmp(eddarg, "skip"))
@@ -168,7 +140,8 @@ void query_edd(void)
do_edd = 0;
}
- edp = (struct edd_info *)boot_params.eddbuf;
+ edp = boot_params.eddbuf;
+ mbrptr = boot_params.edd_mbr_sig_buffer;
if (!do_edd)
return;
@@ -186,11 +159,8 @@ void query_edd(void)
boot_params.eddbuf_entries++;
}
- if (do_mbr) {
- u32 mbr_sig;
- mbr_sig = read_mbr_sig(devno, &ei);
- boot_params.edd_mbr_sig_buffer[devno-0x80] = mbr_sig;
- }
+ if (do_mbr && !read_mbr_sig(devno, &ei, mbrptr++))
+ boot_params.edd_mbr_sig_buf_entries = devno-0x80+1;
}
}
diff --git a/arch/i386/boot/video.c b/arch/i386/boot/video.c
index 958130ef004..693f20d3102 100644
--- a/arch/i386/boot/video.c
+++ b/arch/i386/boot/video.c
@@ -61,7 +61,7 @@ static void store_video_mode(void)
/* Not all BIOSes are clean with respect to the top bit */
boot_params.screen_info.orig_video_mode = ax & 0x7f;
- boot_params.screen_info.orig_video_page = page;
+ boot_params.screen_info.orig_video_page = page >> 8;
}
/*
diff --git a/arch/powerpc/boot/flatdevtree.c b/arch/powerpc/boot/flatdevtree.c
index b732644788d..13761bf160c 100644
--- a/arch/powerpc/boot/flatdevtree.c
+++ b/arch/powerpc/boot/flatdevtree.c
@@ -134,20 +134,6 @@ static char *ft_next(struct ft_cxt *cxt, char *p, struct ft_atom *ret)
#define HDR_SIZE _ALIGN(sizeof(struct boot_param_header), 8)
#define EXPAND_INCR 1024 /* alloc this much extra when expanding */
-/* See if the regions are in the standard order and non-overlapping */
-static int ft_ordered(struct ft_cxt *cxt)
-{
- char *p = (char *)cxt->bph + HDR_SIZE;
- enum ft_rgn_id r;
-
- for (r = FT_RSVMAP; r <= FT_STRINGS; ++r) {
- if (p > cxt->rgn[r].start)
- return 0;
- p = cxt->rgn[r].start + cxt->rgn[r].size;
- }
- return p <= (char *)cxt->bph + cxt->max_size;
-}
-
/* Copy the tree to a newly-allocated region and put things in order */
static int ft_reorder(struct ft_cxt *cxt, int nextra)
{
@@ -573,10 +559,6 @@ int ft_open(struct ft_cxt *cxt, void *blob, unsigned int max_size,
cxt->rgn[FT_STRUCT].size = struct_size(cxt);
cxt->rgn[FT_STRINGS].start = blob + be32_to_cpu(bph->off_dt_strings);
cxt->rgn[FT_STRINGS].size = be32_to_cpu(bph->dt_strings_size);
- /* Leave as '0' to force first ft_make_space call to do a ft_reorder
- * and move dt to an area allocated by realloc.
- cxt->isordered = ft_ordered(cxt);
- */
cxt->p = cxt->rgn[FT_STRUCT].start;
cxt->str_anchor = cxt->rgn[FT_STRINGS].start;
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index f39a72f30aa..b0cb2e662c2 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -81,6 +81,7 @@ obj-y += iomap.o
endif
ifeq ($(CONFIG_PPC_ISERIES),y)
+CFLAGS_lparmap.s += -g0
extra-y += lparmap.s
$(obj)/head_64.o: $(obj)/lparmap.s
AFLAGS_head_64.o += -I$(obj)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index e708ab7ca9e..8533de50347 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -301,9 +301,19 @@ _GLOBAL(_tlbie)
mfspr r4,SPRN_MMUCR
mfspr r5,SPRN_PID /* Get PID */
rlwimi r4,r5,0,24,31 /* Set TID */
- mtspr SPRN_MMUCR,r4
+ /* We have to run the search with interrupts disabled, even critical
+ * and debug interrupts (in fact the only critical exceptions we have
+ * are debug and machine check). Otherwise an interrupt which causes
+ * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */
+ mfmsr r5
+ lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha
+ addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l
+ andc r6,r5,r6
+ mtmsr r6
+ mtspr SPRN_MMUCR,r4
tlbsx. r3, 0, r3
+ mtmsr r5
bne 10f
sync
/* There are only 64 TLB entries, so r3 < 64,
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index f1789578747..a47151e806c 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -795,7 +795,7 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
#ifdef CONFIG_PPC_MM_SLICES
/* We only prefault standard pages for now */
- if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize));
+ if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
return;
#endif
diff --git a/arch/powerpc/platforms/cell/spu_syscalls.c b/arch/powerpc/platforms/cell/spu_syscalls.c
index dd2c6688c8a..027ac32cc63 100644
--- a/arch/powerpc/platforms/cell/spu_syscalls.c
+++ b/arch/powerpc/platforms/cell/spu_syscalls.c
@@ -45,6 +45,7 @@ asmlinkage long sys_spu_create(const char __user *name,
if (owner && try_module_get(owner)) {
if (flags & SPU_CREATE_AFFINITY_SPU) {
neighbor = fget_light(neighbor_fd, &fput_needed);
+ ret = -EBADF;
if (neighbor) {
ret = spufs_calls.create_thread(name, flags,
mode, neighbor);
diff --git a/arch/powerpc/platforms/ps3/device-init.c b/arch/powerpc/platforms/ps3/device-init.c
index e23a5a874ad..ce15cada88d 100644
--- a/arch/powerpc/platforms/ps3/device-init.c
+++ b/arch/powerpc/platforms/ps3/device-init.c
@@ -372,7 +372,7 @@ static int ps3_storage_wait_for_device(const struct ps3_repository_device *repo)
notify_event->dev_type == repo->dev_type) {
pr_debug("%s:%u: device ready: dev_id %u\n", __func__,
__LINE__, repo->dev_id);
- result = 0;
+ error = 0;
break;
}
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index 0da55368655..a22e1f4d94c 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -237,9 +237,19 @@ _GLOBAL(_tlbie)
mfspr r4,SPRN_MMUCR
mfspr r5,SPRN_PID /* Get PID */
rlwimi r4,r5,0,24,31 /* Set TID */
- mtspr SPRN_MMUCR,r4
+ /* We have to run the search with interrupts disabled, even critical
+ * and debug interrupts (in fact the only critical exceptions we have
+ * are debug and machine check). Otherwise an interrupt which causes
+ * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */
+ mfmsr r5
+ lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha
+ addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l
+ andc r6,r5,r6
+ mtmsr r6
+ mtspr SPRN_MMUCR,r4
tlbsx. r3, 0, r3
+ mtmsr r5
bne 10f
sync
/* There are only 64 TLB entries, so r3 < 64,