diff options
Diffstat (limited to 'arch')
604 files changed, 21487 insertions, 15022 deletions
diff --git a/arch/arc/boot/dts/abilis_tb100_dvk.dts b/arch/arc/boot/dts/abilis_tb100_dvk.dts index c0fd3623c39..0fa0d4abe79 100644 --- a/arch/arc/boot/dts/abilis_tb100_dvk.dts +++ b/arch/arc/boot/dts/abilis_tb100_dvk.dts @@ -37,7 +37,7 @@ soc100 { uart@FF100000 { - pinctrl-names = "abilis,simple-default"; + pinctrl-names = "default"; pinctrl-0 = <&pctl_uart0>; }; ethernet@FE100000 { diff --git a/arch/arc/boot/dts/abilis_tb101_dvk.dts b/arch/arc/boot/dts/abilis_tb101_dvk.dts index 6f8c381f626..a4d80ce283a 100644 --- a/arch/arc/boot/dts/abilis_tb101_dvk.dts +++ b/arch/arc/boot/dts/abilis_tb101_dvk.dts @@ -37,7 +37,7 @@ soc100 { uart@FF100000 { - pinctrl-names = "abilis,simple-default"; + pinctrl-names = "default"; pinctrl-0 = <&pctl_uart0>; }; ethernet@FE100000 { diff --git a/arch/arc/boot/dts/abilis_tb10x.dtsi b/arch/arc/boot/dts/abilis_tb10x.dtsi index a6139fc5aaa..b97e3051ba4 100644 --- a/arch/arc/boot/dts/abilis_tb10x.dtsi +++ b/arch/arc/boot/dts/abilis_tb10x.dtsi @@ -88,8 +88,7 @@ }; uart@FF100000 { - compatible = "snps,dw-apb-uart", - "abilis,simple-pinctrl"; + compatible = "snps,dw-apb-uart"; reg = <0xFF100000 0x100>; clock-frequency = <166666666>; interrupts = <25 1>; @@ -184,8 +183,7 @@ #address-cells = <1>; #size-cells = <0>; cell-index = <1>; - compatible = "abilis,tb100-spi", - "abilis,simple-pinctrl"; + compatible = "abilis,tb100-spi"; num-cs = <2>; reg = <0xFE011000 0x20>; interrupt-parent = <&tb10x_ictl>; diff --git a/arch/arc/include/asm/cacheflush.h b/arch/arc/include/asm/cacheflush.h index 9f841af4109..ef62682e8d9 100644 --- a/arch/arc/include/asm/cacheflush.h +++ b/arch/arc/include/asm/cacheflush.h @@ -93,14 +93,16 @@ static inline int cache_is_vipt_aliasing(void) #endif } -#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & 3) +#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & 1) /* * checks if two addresses (after page aligning) index into same cache set */ #define addr_not_cache_congruent(addr1, addr2) \ +({ \ cache_is_vipt_aliasing() ? \ - (CACHE_COLOR(addr1) != CACHE_COLOR(addr2)) : 0 \ + (CACHE_COLOR(addr1) != CACHE_COLOR(addr2)) : 0; \ +}) #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ do { \ diff --git a/arch/arc/include/asm/page.h b/arch/arc/include/asm/page.h index 374a3551411..ab84bf131fe 100644 --- a/arch/arc/include/asm/page.h +++ b/arch/arc/include/asm/page.h @@ -19,13 +19,6 @@ #define clear_page(paddr) memset((paddr), 0, PAGE_SIZE) #define copy_page(to, from) memcpy((to), (from), PAGE_SIZE) -#ifndef CONFIG_ARC_CACHE_VIPT_ALIASING - -#define clear_user_page(addr, vaddr, pg) clear_page(addr) -#define copy_user_page(vto, vfrom, vaddr, pg) copy_page(vto, vfrom) - -#else /* VIPT aliasing dcache */ - struct vm_area_struct; struct page; @@ -35,8 +28,6 @@ void copy_user_highpage(struct page *to, struct page *from, unsigned long u_vaddr, struct vm_area_struct *vma); void clear_user_page(void *to, unsigned long u_vaddr, struct page *page); -#endif /* CONFIG_ARC_CACHE_VIPT_ALIASING */ - #undef STRICT_MM_TYPECHECKS #ifdef STRICT_MM_TYPECHECKS diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h index 1cc4720facc..95b1522212a 100644 --- a/arch/arc/include/asm/pgtable.h +++ b/arch/arc/include/asm/pgtable.h @@ -57,9 +57,9 @@ #define _PAGE_ACCESSED (1<<1) /* Page is accessed (S) */ #define _PAGE_CACHEABLE (1<<2) /* Page is cached (H) */ -#define _PAGE_EXECUTE (1<<3) /* Page has user execute perm (H) */ -#define _PAGE_WRITE (1<<4) /* Page has user write perm (H) */ -#define _PAGE_READ (1<<5) /* Page has user read perm (H) */ +#define _PAGE_U_EXECUTE (1<<3) /* Page has user execute perm (H) */ +#define _PAGE_U_WRITE (1<<4) /* Page has user write perm (H) */ +#define _PAGE_U_READ (1<<5) /* Page has user read perm (H) */ #define _PAGE_K_EXECUTE (1<<6) /* Page has kernel execute perm (H) */ #define _PAGE_K_WRITE (1<<7) /* Page has kernel write perm (H) */ #define _PAGE_K_READ (1<<8) /* Page has kernel perm (H) */ @@ -72,9 +72,9 @@ /* PD1 */ #define _PAGE_CACHEABLE (1<<0) /* Page is cached (H) */ -#define _PAGE_EXECUTE (1<<1) /* Page has user execute perm (H) */ -#define _PAGE_WRITE (1<<2) /* Page has user write perm (H) */ -#define _PAGE_READ (1<<3) /* Page has user read perm (H) */ +#define _PAGE_U_EXECUTE (1<<1) /* Page has user execute perm (H) */ +#define _PAGE_U_WRITE (1<<2) /* Page has user write perm (H) */ +#define _PAGE_U_READ (1<<3) /* Page has user read perm (H) */ #define _PAGE_K_EXECUTE (1<<4) /* Page has kernel execute perm (H) */ #define _PAGE_K_WRITE (1<<5) /* Page has kernel write perm (H) */ #define _PAGE_K_READ (1<<6) /* Page has kernel perm (H) */ @@ -93,7 +93,8 @@ #endif /* Kernel allowed all permissions for all pages */ -#define _K_PAGE_PERMS (_PAGE_K_EXECUTE | _PAGE_K_WRITE | _PAGE_K_READ) +#define _K_PAGE_PERMS (_PAGE_K_EXECUTE | _PAGE_K_WRITE | _PAGE_K_READ | \ + _PAGE_GLOBAL | _PAGE_PRESENT) #ifdef CONFIG_ARC_CACHE_PAGES #define _PAGE_DEF_CACHEABLE _PAGE_CACHEABLE @@ -106,7 +107,11 @@ * -by default cached, unless config otherwise * -present in memory */ -#define ___DEF (_PAGE_PRESENT | _K_PAGE_PERMS | _PAGE_DEF_CACHEABLE) +#define ___DEF (_PAGE_PRESENT | _PAGE_DEF_CACHEABLE) + +#define _PAGE_READ (_PAGE_U_READ | _PAGE_K_READ) +#define _PAGE_WRITE (_PAGE_U_WRITE | _PAGE_K_WRITE) +#define _PAGE_EXECUTE (_PAGE_U_EXECUTE | _PAGE_K_EXECUTE) /* Set of bits not changed in pte_modify */ #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED) @@ -125,11 +130,10 @@ * kernel vaddr space - visible in all addr spaces, but kernel mode only * Thus Global, all-kernel-access, no-user-access, cached */ -#define PAGE_KERNEL __pgprot(___DEF | _PAGE_GLOBAL) +#define PAGE_KERNEL __pgprot(_K_PAGE_PERMS | _PAGE_DEF_CACHEABLE) /* ioremap */ -#define PAGE_KERNEL_NO_CACHE __pgprot(_PAGE_PRESENT | _K_PAGE_PERMS | \ - _PAGE_GLOBAL) +#define PAGE_KERNEL_NO_CACHE __pgprot(_K_PAGE_PERMS) /************************************************************************** * Mapping of vm_flags (Generic VM) to PTE flags (arch specific) diff --git a/arch/arc/include/asm/tlb.h b/arch/arc/include/asm/tlb.h index 85b6df839bd..cb0c708ca66 100644 --- a/arch/arc/include/asm/tlb.h +++ b/arch/arc/include/asm/tlb.h @@ -16,7 +16,7 @@ /* Masks for actual TLB "PD"s */ #define PTE_BITS_IN_PD0 (_PAGE_GLOBAL | _PAGE_PRESENT) #define PTE_BITS_IN_PD1 (PAGE_MASK | _PAGE_CACHEABLE | \ - _PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ | \ + _PAGE_U_EXECUTE | _PAGE_U_WRITE | _PAGE_U_READ | \ _PAGE_K_EXECUTE | _PAGE_K_WRITE | _PAGE_K_READ) #ifndef __ASSEMBLY__ diff --git a/arch/arc/mm/cache_arc700.c b/arch/arc/mm/cache_arc700.c index 2f12bca8aef..aedce190544 100644 --- a/arch/arc/mm/cache_arc700.c +++ b/arch/arc/mm/cache_arc700.c @@ -610,7 +610,7 @@ void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len) local_irq_save(flags); __ic_line_inv_vaddr(paddr, vaddr, len); - __dc_line_op(paddr, vaddr, len, OP_FLUSH); + __dc_line_op(paddr, vaddr, len, OP_FLUSH_N_INV); local_irq_restore(flags); } @@ -676,6 +676,17 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start, flush_cache_all(); } +void flush_anon_page(struct vm_area_struct *vma, struct page *page, + unsigned long u_vaddr) +{ + /* TBD: do we really need to clear the kernel mapping */ + __flush_dcache_page(page_address(page), u_vaddr); + __flush_dcache_page(page_address(page), page_address(page)); + +} + +#endif + void copy_user_highpage(struct page *to, struct page *from, unsigned long u_vaddr, struct vm_area_struct *vma) { @@ -725,16 +736,6 @@ void clear_user_page(void *to, unsigned long u_vaddr, struct page *page) set_bit(PG_arch_1, &page->flags); } -void flush_anon_page(struct vm_area_struct *vma, struct page *page, - unsigned long u_vaddr) -{ - /* TBD: do we really need to clear the kernel mapping */ - __flush_dcache_page(page_address(page), u_vaddr); - __flush_dcache_page(page_address(page), page_address(page)); - -} - -#endif /********************************************************************** * Explicit Cache flush request from user space via syscall diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c index 066145b5f34..fe1c5a073af 100644 --- a/arch/arc/mm/tlb.c +++ b/arch/arc/mm/tlb.c @@ -444,7 +444,8 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned, * so userspace sees the right data. * (Avoids the flush for Non-exec + congruent mapping case) */ - if (vma->vm_flags & VM_EXEC || addr_not_cache_congruent(paddr, vaddr)) { + if ((vma->vm_flags & VM_EXEC) || + addr_not_cache_congruent(paddr, vaddr)) { struct page *page = pfn_to_page(pte_pfn(*ptep)); int dirty = test_and_clear_bit(PG_arch_1, &page->flags); diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S index 9df765dc7c3..3357d26ffe5 100644 --- a/arch/arc/mm/tlbex.S +++ b/arch/arc/mm/tlbex.S @@ -277,7 +277,7 @@ ARC_ENTRY EV_TLBMissI ;---------------------------------------------------------------- ; VERIFY_PTE: Check if PTE permissions approp for executing code cmp_s r2, VMALLOC_START - mov.lo r2, (_PAGE_PRESENT | _PAGE_READ | _PAGE_EXECUTE) + mov.lo r2, (_PAGE_PRESENT | _PAGE_U_READ | _PAGE_U_EXECUTE) mov.hs r2, (_PAGE_PRESENT | _PAGE_K_READ | _PAGE_K_EXECUTE) and r3, r0, r2 ; Mask out NON Flag bits from PTE @@ -320,9 +320,9 @@ ARC_ENTRY EV_TLBMissD mov_s r2, 0 lr r3, [ecr] btst_s r3, ECR_C_BIT_DTLB_LD_MISS ; Read Access - or.nz r2, r2, _PAGE_READ ; chk for Read flag in PTE + or.nz r2, r2, _PAGE_U_READ ; chk for Read flag in PTE btst_s r3, ECR_C_BIT_DTLB_ST_MISS ; Write Access - or.nz r2, r2, _PAGE_WRITE ; chk for Write flag in PTE + or.nz r2, r2, _PAGE_U_WRITE ; chk for Write flag in PTE ; Above laddering takes care of XCHG access ; which is both Read and Write diff --git a/arch/arc/plat-tb10x/tb10x.c b/arch/arc/plat-tb10x/tb10x.c index d3567691c7e..06cb3092946 100644 --- a/arch/arc/plat-tb10x/tb10x.c +++ b/arch/arc/plat-tb10x/tb10x.c @@ -34,31 +34,6 @@ static void __init tb10x_platform_init(void) of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } -static void __init tb10x_platform_late_init(void) -{ - struct device_node *dn; - - /* - * Pinctrl documentation recommends setting up the iomux here for - * all modules which don't require control over the pins themselves. - * Modules which need this kind of assistance are compatible with - * "abilis,simple-pinctrl", i.e. we can easily iterate over them. - * TODO: Does this recommended method work cleanly with pins required - * by modules? - */ - for_each_compatible_node(dn, NULL, "abilis,simple-pinctrl") { - struct platform_device *pd = of_find_device_by_node(dn); - struct pinctrl *pctl; - - pctl = pinctrl_get_select(&pd->dev, "abilis,simple-default"); - if (IS_ERR(pctl)) { - int ret = PTR_ERR(pctl); - dev_err(&pd->dev, "Could not set up pinctrl: %d\n", - ret); - } - } -} - static const char *tb10x_compat[] __initdata = { "abilis,arc-tb10x", NULL, @@ -67,5 +42,4 @@ static const char *tb10x_compat[] __initdata = { MACHINE_START(TB10x, "tb10x") .dt_compat = tb10x_compat, .init_machine = tb10x_platform_init, - .init_late = tb10x_platform_late_init, MACHINE_END diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f06e65bbef7..db5aa5f2d1d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -9,7 +9,7 @@ config ARM select BUILDTIME_EXTABLE_SORT if MMU select CPU_PM if (SUSPEND || CPU_IDLE) select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU - select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) + select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) select GENERIC_CLOCKEVENTS_BROADCAST if SMP select GENERIC_IRQ_PROBE select GENERIC_IRQ_SHOW @@ -366,11 +366,12 @@ config ARCH_CLPS711X select ARCH_REQUIRE_GPIOLIB select AUTO_ZRELADDR select CLKDEV_LOOKUP + select CLKSRC_MMIO select COMMON_CLK select CPU_ARM720T select GENERIC_CLOCKEVENTS + select MFD_SYSCON select MULTI_IRQ_HANDLER - select NEED_MACH_MEMORY_H select SPARSE_IRQ help Support for Cirrus Logic 711x/721x/731x based boards. @@ -502,6 +503,7 @@ config ARCH_DOVE config ARCH_KIRKWOOD bool "Marvell Kirkwood" + select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB select CPU_FEROCEON select GENERIC_CLOCKEVENTS @@ -695,6 +697,7 @@ config ARCH_S3C24XX select CLKDEV_LOOKUP select CLKSRC_MMIO select GENERIC_CLOCKEVENTS + select GPIO_SAMSUNG select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -702,6 +705,7 @@ config ARCH_S3C24XX select MULTI_IRQ_HANDLER select NEED_MACH_GPIO_H select NEED_MACH_IO_H + select SAMSUNG_ATAGS help Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST @@ -717,6 +721,7 @@ config ARCH_S3C64XX select CLKSRC_MMIO select CPU_V6 select GENERIC_CLOCKEVENTS + select GPIO_SAMSUNG select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -726,6 +731,7 @@ config ARCH_S3C64XX select PLAT_SAMSUNG select S3C_DEV_NAND select S3C_GPIO_TRACK + select SAMSUNG_ATAGS select SAMSUNG_CLKSRC select SAMSUNG_GPIOLIB_4BIT select SAMSUNG_IRQ_VIC_TIMER @@ -739,11 +745,13 @@ config ARCH_S5P64X0 select CLKSRC_MMIO select CPU_V6 select GENERIC_CLOCKEVENTS + select GPIO_SAMSUNG select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS select NEED_MACH_GPIO_H + select SAMSUNG_ATAGS help Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, SMDK6450. @@ -755,11 +763,13 @@ config ARCH_S5PC100 select CLKSRC_MMIO select CPU_V7 select GENERIC_CLOCKEVENTS + select GPIO_SAMSUNG select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS select NEED_MACH_GPIO_H + select SAMSUNG_ATAGS help Samsung S5PC100 series based systems @@ -772,12 +782,14 @@ config ARCH_S5PV210 select CLKSRC_MMIO select CPU_V7 select GENERIC_CLOCKEVENTS + select GPIO_SAMSUNG select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS select NEED_MACH_GPIO_H select NEED_MACH_MEMORY_H + select SAMSUNG_ATAGS help Samsung S5PV210/S5PC110 series based systems @@ -785,7 +797,9 @@ config ARCH_EXYNOS bool "Samsung EXYNOS" select ARCH_HAS_CPUFREQ select ARCH_HAS_HOLES_MEMORYMODEL + select ARCH_REQUIRE_GPIOLIB select ARCH_SPARSEMEM_ENABLE + select ARM_GIC select CLKDEV_LOOKUP select COMMON_CLK select CPU_V7 @@ -794,8 +808,9 @@ config ARCH_EXYNOS select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS - select NEED_MACH_GPIO_H select NEED_MACH_MEMORY_H + select SPARSE_IRQ + select USE_OF help Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) @@ -813,23 +828,6 @@ config ARCH_SHARK Support for the StrongARM based Digital DNARD machine, also known as "Shark" (<http://www.shark-linux.de/shark.html>). -config ARCH_U300 - bool "ST-Ericsson U300 Series" - depends on MMU - select ARCH_REQUIRE_GPIOLIB - select ARM_AMBA - select ARM_PATCH_PHYS_VIRT - select ARM_VIC - select CLKDEV_LOOKUP - select CLKSRC_MMIO - select COMMON_CLK - select CPU_ARM926T - select GENERIC_CLOCKEVENTS - select HAVE_TCM - select SPARSE_IRQ - help - Support for ST-Ericsson U300 series mobile platforms. - config ARCH_DAVINCI bool "TI DaVinci" select ARCH_HAS_HOLES_MEMORYMODEL @@ -840,6 +838,7 @@ config ARCH_DAVINCI select GENERIC_IRQ_CHIP select HAVE_IDE select NEED_MACH_GPIO_H + select TI_PRIV_EDMA select USE_OF select ZONE_DMA help @@ -948,6 +947,8 @@ source "arch/arm/mach-iop13xx/Kconfig" source "arch/arm/mach-ixp4xx/Kconfig" +source "arch/arm/mach-keystone/Kconfig" + source "arch/arm/mach-kirkwood/Kconfig" source "arch/arm/mach-ks8695/Kconfig" @@ -981,6 +982,8 @@ source "arch/arm/mach-mmp/Kconfig" source "arch/arm/mach-realview/Kconfig" +source "arch/arm/mach-rockchip/Kconfig" + source "arch/arm/mach-sa1100/Kconfig" source "arch/arm/plat-samsung/Kconfig" @@ -1560,6 +1563,7 @@ config ARCH_NR_GPIO int default 1024 if ARCH_SHMOBILE || ARCH_TEGRA default 512 if SOC_OMAP5 + default 512 if ARCH_KEYSTONE default 392 if ARCH_U8500 default 352 if ARCH_VT8500 default 288 if ARCH_SUNXI @@ -1585,7 +1589,7 @@ config SCHED_HRTICK config THUMB2_KERNEL bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY - depends on CPU_V7 && !CPU_V6 && !CPU_V6K + depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K default y if CPU_THUMBONLY select AEABI select ARM_ASM_UNIFIED @@ -2040,7 +2044,7 @@ config CRASH_DUMP config AUTO_ZRELADDR bool "Auto calculation of the decompressed kernel image address" - depends on !ZBOOT_ROM && !ARCH_U300 + depends on !ZBOOT_ROM help ZRELADDR is the physical address where the decompressed kernel image will be placed. If AUTO_ZRELADDR is selected, the address diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu index 2cef8e13f9f..c859495da48 100644 --- a/arch/arm/Kconfig-nommu +++ b/arch/arm/Kconfig-nommu @@ -28,7 +28,7 @@ config FLASH_SIZE config PROCESSOR_ID hex 'Hard wire the processor ID' default 0x00007700 - depends on !CPU_CP15 + depends on !(CPU_CP15 || CPU_V7M) help If processor has no CP15 register, this processor ID is used instead of the auto-probing which utilizes the register. diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 1d41908d5cd..ab95f07e154 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -251,6 +251,27 @@ choice Say Y here if you want kernel low-level debugging support on i.MX6Q/DL. + config DEBUG_IMX6SL_UART + bool "i.MX6SL Debug UART" + depends on SOC_IMX6SL + help + Say Y here if you want kernel low-level debugging support + on i.MX6SL. + + config DEBUG_KEYSTONE_UART0 + bool "Kernel low-level debugging on KEYSTONE2 using UART0" + depends on ARCH_KEYSTONE + help + Say Y here if you want the debug print routines to direct + their output to UART0 serial port on KEYSTONE2 devices. + + config DEBUG_KEYSTONE_UART1 + bool "Kernel low-level debugging on KEYSTONE2 using UART1" + depends on ARCH_KEYSTONE + help + Say Y here if you want the debug print routines to direct + their output to UART1 serial port on KEYSTONE2 devices. + config DEBUG_MMP_UART2 bool "Kernel low-level debugging message via MMP UART2" depends on ARCH_MMP @@ -303,12 +324,37 @@ choice their output to the serial port on MSM 8960 devices. config DEBUG_MVEBU_UART - bool "Kernel low-level debugging messages via MVEBU UART" + bool "Kernel low-level debugging messages via MVEBU UART (old bootloaders)" depends on ARCH_MVEBU help Say Y here if you want kernel low-level debugging support on MVEBU based platforms. + This option should be used with the old bootloaders + that left the internal registers mapped at + 0xd0000000. As of today, this is the case on + platforms such as the Globalscale Mirabox or the + Plathome OpenBlocks AX3, when using the original + bootloader. + + If the wrong DEBUG_MVEBU_UART* option is selected, + when u-boot hands over to the kernel, the system + silently crashes, with no serial output at all. + + config DEBUG_MVEBU_UART_ALTERNATE + bool "Kernel low-level debugging messages via MVEBU UART (new bootloaders)" + depends on ARCH_MVEBU + help + Say Y here if you want kernel low-level debugging support + on MVEBU based platforms. + + This option should be used with the new bootloaders + that remap the internal registers at 0xf1000000. + + If the wrong DEBUG_MVEBU_UART* option is selected, + when u-boot hands over to the kernel, the system + silently crashes, with no serial output at all. + config DEBUG_NOMADIK_UART bool "Kernel low-level debugging messages via NOMADIK UART" depends on ARCH_NOMADIK @@ -353,6 +399,13 @@ choice their output to the standard serial port on the RealView PB1176 platform. + config DEBUG_ROCKCHIP_UART + bool "Kernel low-level debugging messages via Rockchip UART" + depends on ARCH_ROCKCHIP + help + Say Y here if you want kernel low-level debugging support + on Rockchip based platforms. + config DEBUG_S3C_UART0 depends on PLAT_SAMSUNG select DEBUG_EXYNOS_UART if ARCH_EXYNOS @@ -443,6 +496,13 @@ choice Say Y here if you want the debug print routines to direct their output to the uart1 port on SiRFmarco devices. + config DEBUG_U300_UART + bool "Kernel low-level debugging messages via U300 UART0" + depends on ARCH_U300 + help + Say Y here if you want the debug print routines to direct + their output to the uart port on U300 devices. + config DEBUG_UX500_UART depends on ARCH_U8500 bool "Use Ux500 UART for low-level debug" @@ -532,7 +592,8 @@ config DEBUG_IMX_UART_PORT DEBUG_IMX35_UART || \ DEBUG_IMX51_UART || \ DEBUG_IMX53_UART || \ - DEBUG_IMX6Q_UART + DEBUG_IMX6Q_UART || \ + DEBUG_IMX6SL_UART default 1 depends on ARCH_MXC help @@ -589,6 +650,32 @@ endchoice choice prompt "Low-level debug console UART" + depends on DEBUG_ROCKCHIP_UART + + config DEBUG_RK29_UART0 + bool "RK29 UART0" + + config DEBUG_RK29_UART1 + bool "RK29 UART1" + + config DEBUG_RK29_UART2 + bool "RK29 UART2" + + config DEBUG_RK3X_UART0 + bool "RK3X UART0" + + config DEBUG_RK3X_UART1 + bool "RK3X UART1" + + config DEBUG_RK3X_UART2 + bool "RK3X UART2" + + config DEBUG_RK3X_UART3 + bool "RK3X UART3" +endchoice + +choice + prompt "Low-level debug console UART" depends on DEBUG_LL && DEBUG_TEGRA_UART config TEGRA_DEBUG_UART_AUTO_ODMDATA @@ -631,18 +718,24 @@ config DEBUG_LL_INCLUDE DEBUG_IMX35_UART || \ DEBUG_IMX51_UART || \ DEBUG_IMX53_UART ||\ - DEBUG_IMX6Q_UART - default "debug/mvebu.S" if DEBUG_MVEBU_UART + DEBUG_IMX6Q_UART || \ + DEBUG_IMX6SL_UART + default "debug/keystone.S" if DEBUG_KEYSTONE_UART0 || \ + DEBUG_KEYSTONE_UART1 + default "debug/mvebu.S" if DEBUG_MVEBU_UART || \ + DEBUG_MVEBU_UART_ALTERNATE default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART default "debug/nomadik.S" if DEBUG_NOMADIK_UART default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART default "debug/pxa.S" if DEBUG_PXA_UART1 || DEBUG_MMP_UART2 || \ DEBUG_MMP_UART3 + default "debug/rockchip.S" if DEBUG_ROCKCHIP_UART default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1 default "debug/socfpga.S" if DEBUG_SOCFPGA_UART default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1 default "debug/tegra.S" if DEBUG_TEGRA_UART + default "debug/u300.S" if DEBUG_U300_UART default "debug/ux500.S" if DEBUG_UX500_UART default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \ DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 1ba358ba16b..daf19a86b8e 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -59,6 +59,7 @@ comma = , # Note that GCC does not numerically define an architecture version # macro, but instead defines a whole series of macros which makes # testing for a specific architecture or later rather impossible. +arch-$(CONFIG_CPU_32v7M) :=-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m arch-$(CONFIG_CPU_32v7) :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a) arch-$(CONFIG_CPU_32v6) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6) # Only override the compiler option if ARMv6. The ARMv6K extensions are @@ -171,6 +172,7 @@ machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell machine-$(CONFIG_ARCH_PRIMA2) += prima2 machine-$(CONFIG_ARCH_PXA) += pxa machine-$(CONFIG_ARCH_REALVIEW) += realview +machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_ARCH_RPC) += rpc machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx @@ -194,9 +196,11 @@ machine-$(CONFIG_PLAT_SPEAR) += spear machine-$(CONFIG_ARCH_VIRT) += virt machine-$(CONFIG_ARCH_ZYNQ) += zynq machine-$(CONFIG_ARCH_SUNXI) += sunxi +machine-$(CONFIG_ARCH_KEYSTONE) += keystone # Platform directory name. This list is sorted alphanumerically # by CONFIG_* macro name. +plat-$(CONFIG_ARCH_EXYNOS) += samsung plat-$(CONFIG_ARCH_OMAP) += omap plat-$(CONFIG_ARCH_S3C64XX) += samsung plat-$(CONFIG_PLAT_IOP) += iop diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 3580d57ea21..79e9bdbfc49 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -124,7 +124,7 @@ KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) endif ccflags-y := -fpic -mno-single-pic-base -fno-builtin -I$(obj) -asflags-y := -Wa,-march=all -DZIMAGE +asflags-y := -DZIMAGE # Supply kernel BSS size to the decompressor via a linker symbol. KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \ diff --git a/arch/arm/boot/compressed/debug.S b/arch/arm/boot/compressed/debug.S index 6e8382d5b7a..5392ee63338 100644 --- a/arch/arm/boot/compressed/debug.S +++ b/arch/arm/boot/compressed/debug.S @@ -1,6 +1,8 @@ #include <linux/linkage.h> #include <asm/assembler.h> +#ifndef CONFIG_DEBUG_SEMIHOSTING + #include CONFIG_DEBUG_LL_INCLUDE ENTRY(putc) @@ -10,3 +12,29 @@ ENTRY(putc) busyuart r3, r1 mov pc, lr ENDPROC(putc) + +#else + +ENTRY(putc) + adr r1, 1f + ldmia r1, {r2, r3} + add r2, r2, r1 + ldr r1, [r2, r3] + strb r0, [r1] + mov r0, #0x03 @ SYS_WRITEC + ARM( svc #0x123456 ) + THUMB( svc #0xab ) + mov pc, lr + .align 2 +1: .word _GLOBAL_OFFSET_TABLE_ - . + .word semi_writec_buf(GOT) +ENDPROC(putc) + + .bss + .global semi_writec_buf + .type semi_writec_buf, %object +semi_writec_buf: + .space 4 + .size semi_writec_buf, 4 + +#endif diff --git a/arch/arm/boot/compressed/head-sa1100.S b/arch/arm/boot/compressed/head-sa1100.S index 6179d94dd5c..3115e313d9f 100644 --- a/arch/arm/boot/compressed/head-sa1100.S +++ b/arch/arm/boot/compressed/head-sa1100.S @@ -11,6 +11,7 @@ #include <asm/mach-types.h> .section ".start", "ax" + .arch armv4 __SA1100_start: diff --git a/arch/arm/boot/compressed/head-shark.S b/arch/arm/boot/compressed/head-shark.S index 089c560e07f..92b56897ed6 100644 --- a/arch/arm/boot/compressed/head-shark.S +++ b/arch/arm/boot/compressed/head-shark.S @@ -18,6 +18,7 @@ .section ".start", "ax" + .arch armv4 b __beginning __ofw_data: .long 0 @ the number of memory blocks diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index fe4d9c3ad76..032a8d98714 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -11,6 +11,7 @@ #include <linux/linkage.h> #include <asm/assembler.h> + .arch armv7-a /* * Debugging stuff * @@ -805,8 +806,8 @@ call_cache_fn: adr r12, proc_types .align 2 .type proc_types,#object proc_types: - .word 0x00000000 @ old ARM ID - .word 0x0000f000 + .word 0x41000000 @ old ARM ID + .word 0xff00f000 mov pc, lr THUMB( nop ) mov pc, lr diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b9f7121e6ec..f9eae2f0ae5 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -64,6 +64,8 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ integratorcp.dtb dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ + kirkwood-db-88f6281.dtb \ + kirkwood-db-88f6282.dtb \ kirkwood-dns320.dtb \ kirkwood-dns325.dtb \ kirkwood-dockstar.dtb \ @@ -177,7 +179,9 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ spear320-evb.dtb \ spear320-hmi.dtb dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun4i-a10-cubieboard.dtb \ +dtb-$(CONFIG_ARCH_SUNXI) += \ + sun4i-a10-cubieboard.dtb \ + sun4i-a10-mini-xplus.dtb \ sun4i-a10-hackberry.dtb \ sun5i-a13-olinuxino.dtb dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ @@ -197,6 +201,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra114-pluto.dtb dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \ versatile-pb.dtb +dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ vexpress-v2p-ca9.dtb \ vexpress-v2p-ca15-tc1.dtb \ diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 1460d9b88ad..8e1248f01fa 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -409,8 +409,8 @@ ti,hwmods = "gpmc"; reg = <0x50000000 0x2000>; interrupts = <100>; - num-cs = <7>; - num-waitpins = <2>; + gpmc,num-cs = <7>; + gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; status = "disabled"; diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 272bbc65fab..52a1f5efc08 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -33,7 +33,8 @@ #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&mpic>; - ranges = <0 0 0xd0000000 0x100000>; + ranges = <0 0 0xd0000000 0x0100000 /* internal registers */ + 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>; internal-regs { compatible = "simple-bus"; @@ -79,7 +80,7 @@ sata@a0000 { compatible = "marvell,orion-sata"; - reg = <0xa0000 0x2400>; + reg = <0xa0000 0x5000>; interrupts = <55>; clocks = <&gateclk 15>, <&gateclk 30>; clock-names = "0", "1"; @@ -95,7 +96,7 @@ ethernet@70000 { compatible = "marvell,armada-370-neta"; - reg = <0x70000 0x2500>; + reg = <0x70000 0x4000>; interrupts = <8>; clocks = <&gateclk 4>; status = "disabled"; @@ -103,7 +104,7 @@ ethernet@74000 { compatible = "marvell,armada-370-neta"; - reg = <0x74000 0x2500>; + reg = <0x74000 0x4000>; interrupts = <10>; clocks = <&gateclk 3>; status = "disabled"; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index b2c1b5af974..aee2b1866ce 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -29,7 +29,8 @@ }; soc { - ranges = <0 0xd0000000 0x100000>; + ranges = <0 0xd0000000 0x0100000 /* internal registers */ + 0xe0000000 0xe0000000 0x8100000 /* PCIe */>; internal-regs { system-controller@18200 { compatible = "marvell,armada-370-xp-system-controller"; @@ -38,12 +39,12 @@ L2: l2-cache { compatible = "marvell,aurora-outer-cache"; - reg = <0xd0008000 0x1000>; + reg = <0x08000 0x1000>; cache-id-part = <0x100>; wt-override; }; - mpic: interrupt-controller@20000 { + interrupt-controller@20000 { reg = <0x20a00 0x1d0>, <0x21870 0x58>; }; diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 26ad06fc147..76db557adbe 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -39,6 +39,10 @@ }; soc { + ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ + 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ + 0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB */>; + internal-regs { serial@12000 { clock-frequency = <250000000>; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 6ab56bd35de..488ca5eb9a5 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -107,7 +107,7 @@ ethernet@34000 { compatible = "marvell,armada-370-neta"; - reg = <0x34000 0x2500>; + reg = <0x34000 0x4000>; interrupts = <14>; clocks = <&gateclk 1>; status = "disabled"; diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index f14d36c4615..fdea75c7341 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -27,6 +27,10 @@ }; soc { + ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ + 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ + 0xf0000000 0 0xf0000000 0x8000000 /* Device Bus, NOR 128MiB */>; + internal-regs { serial@12000 { clock-frequency = <250000000>; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index bacab11c10d..1ee8540b0eb 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -31,7 +31,7 @@ wt-override; }; - mpic: interrupt-controller@20000 { + interrupt-controller@20000 { reg = <0x20a00 0x2d0>, <0x21070 0x58>; }; @@ -88,7 +88,7 @@ ethernet@30000 { compatible = "marvell,armada-370-neta"; - reg = <0x30000 0x2500>; + reg = <0x30000 0x4000>; interrupts = <12>; clocks = <&gateclk 2>; status = "disabled"; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 70b5ccbac23..84c4bef2d72 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -264,7 +264,7 @@ atmel,pins = <0 10 0x2 0x0 /* PA10 periph B */ 0 11 0x2 0x0 /* PA11 periph B */ - 0 24 0x2 0x0 /* PA24 periph B */ + 0 22 0x2 0x0 /* PA22 periph B */ 0 25 0x2 0x0 /* PA25 periph B */ 0 26 0x2 0x0 /* PA26 periph B */ 0 27 0x2 0x0 /* PA27 periph B */ diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 3de8e6dfbcb..8d25f889928 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -57,6 +57,7 @@ compatible = "atmel,at91rm9200-aic"; interrupt-controller; reg = <0xfffff000 0x200>; + atmel,external-irqs = <31>; }; ramc0: ramc@ffffe800 { diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts index 3b40d11d65e..315250b4995 100644 --- a/arch/arm/boot/dts/at91sam9x25ek.dts +++ b/arch/arm/boot/dts/at91sam9x25ek.dts @@ -11,7 +11,7 @@ /include/ "at91sam9x5ek.dtsi" / { - model = "Atmel AT91SAM9G25-EK"; + model = "Atmel AT91SAM9X25-EK"; compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; ahb { diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index f0052dccf9a..1e12aeff403 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -44,6 +44,7 @@ reg = <0x7e201000 0x1000>; interrupts = <2 25>; clock-frequency = <3000000>; + arm,primecell-periphid = <0x00241011>; }; gpio: gpio { diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 98dfc3ea5c0..0673524238a 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -497,6 +497,21 @@ clock-names = "usbhost"; }; + usbphy@12130000 { + compatible = "samsung,exynos5250-usb2phy"; + reg = <0x12130000 0x100>; + clocks = <&clock 1>, <&clock 285>; + clock-names = "ext_xtal", "usbhost"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usbphy-sys { + reg = <0x10040704 0x8>, + <0x10050230 0x4>; + }; + }; + amba { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index d2550e0bca2..701153992c6 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -141,8 +141,8 @@ #size-cells = <0>; compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; reg = <0x43fa4000 0x4000>; - clocks = <&clks 62>; - clock-names = "ipg"; + clocks = <&clks 62>, <&clks 62>; + clock-names = "ipg", "per"; interrupts = <14>; status = "disabled"; }; @@ -182,8 +182,8 @@ compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; reg = <0x50004000 0x4000>; interrupts = <0>; - clocks = <&clks 80>; - clock-names = "ipg"; + clocks = <&clks 80>, <&clks 80>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -210,8 +210,8 @@ #size-cells = <0>; compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; reg = <0x50010000 0x4000>; - clocks = <&clks 79>; - clock-names = "ipg"; + clocks = <&clks 79>, <&clks 79>; + clock-names = "ipg", "per"; interrupts = <13>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index ff4bd4873ed..75bd1138651 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -131,7 +131,7 @@ compatible = "fsl,imx27-cspi"; reg = <0x1000e000 0x1000>; interrupts = <16>; - clocks = <&clks 53>, <&clks 0>; + clocks = <&clks 53>, <&clks 53>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -142,7 +142,7 @@ compatible = "fsl,imx27-cspi"; reg = <0x1000f000 0x1000>; interrupts = <15>; - clocks = <&clks 52>, <&clks 0>; + clocks = <&clks 52>, <&clks 52>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -223,7 +223,7 @@ compatible = "fsl,imx27-cspi"; reg = <0x10017000 0x1000>; interrupts = <6>; - clocks = <&clks 51>, <&clks 0>; + clocks = <&clks 51>, <&clks 51>; clock-names = "ipg", "per"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 21bb786c5b3..53fdde69bbf 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -631,7 +631,7 @@ compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; reg = <0x83fc0000 0x4000>; interrupts = <38>; - clocks = <&clks 55>, <&clks 0>; + clocks = <&clks 55>, <&clks 55>; clock-names = "ipg", "per"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 845982eaac2..eb83aa039b8 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -714,7 +714,7 @@ compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; reg = <0x63fc0000 0x4000>; interrupts = <38>; - clocks = <&clks 55>, <&clks 0>; + clocks = <&clks 55>, <&clks 55>; clock-names = "ipg", "per"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index c9c3fa34464..03f23b7a0ab 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -39,6 +39,47 @@ valid-mask = <0x003fffff>; }; + pci: pciv3@62000000 { + compatible = "v3,v360epc-pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x62000000 0x10000>; + interrupt-parent = <&pic>; + interrupts = <17>; /* Bus error IRQ */ + ranges = <0x00000000 0 0x61000000 /* config space */ + 0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */ + 0x01000000 0 0x60000000 /* I/O space */ + 0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */ + 0x02000000 0 0x40000000 /* non-prefectable memory */ + 0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */ + 0x42000000 0 0x50000000 /* prefetchable memory */ + 0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */ + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = < + /* IDSEL 9 */ + 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */ + 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */ + 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */ + 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */ + /* IDSEL 10 */ + 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */ + 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */ + 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */ + 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */ + /* IDSEL 11 */ + 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */ + 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */ + 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */ + 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */ + /* IDSEL 12 */ + 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */ + 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */ + 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */ + 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */ + >; + }; + fpga { /* * The Integator/AP predates the idea to have magic numbers diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dts new file mode 100644 index 00000000000..1334b42c6b7 --- /dev/null +++ b/arch/arm/boot/dts/keystone.dts @@ -0,0 +1,117 @@ +/* + * Copyright 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +/include/ "skeleton.dtsi" + +/ { + model = "Texas Instruments Keystone 2 SoC"; + compatible = "ti,keystone-evm"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + }; + + memory { + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gic>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + }; + }; + + gic: interrupt-controller { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + #address-cells = <1>; + interrupt-controller; + reg = <0x0 0x02561000 0x0 0x1000>, + <0x0 0x02562000 0x0 0x2000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0x308>; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <0 20 0xf01>, + <0 21 0xf01>, + <0 22 0xf01>, + <0 23 0xf01>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ti,keystone","simple-bus"; + interrupt-parent = <&gic>; + ranges = <0x0 0x0 0x0 0xc0000000>; + + rstctrl: reset-controller { + compatible = "ti,keystone-reset"; + reg = <0x023100e8 4>; /* pll reset control reg */ + }; + + uart0: serial@02530c00 { + compatible = "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02530c00 0x100>; + clock-frequency = <133120000>; + interrupts = <0 277 0xf01>; + }; + + uart1: serial@02531000 { + compatible = "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02531000 0x100>; + clock-frequency = <133120000>; + interrupts = <0 280 0xf01>; + }; + + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index d6c9d65cbae..51376683dbc 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@ -40,5 +40,36 @@ marvell,function = "sdio"; }; }; + + pcie-controller { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index 23991e45bc5..66a751ab551 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -65,5 +65,53 @@ clocks = <&gate_clk 7>; status = "disabled"; }; + + pcie-controller { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x00044000 0x00044000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 10>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 18>; + status = "disabled"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts new file mode 100644 index 00000000000..9d777edd1f3 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts @@ -0,0 +1,30 @@ +/* + * Marvell DB-88F6281-BP Development Board Setup + * + * Saeed Bishara <saeed@marvell.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +/include/ "kirkwood-db.dtsi" +/include/ "kirkwood-6281.dtsi" + +/ { + model = "Marvell DB-88F6281-BP Development Board"; + compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + ocp@f1000000 { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts new file mode 100644 index 00000000000..f4c852886d2 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts @@ -0,0 +1,34 @@ +/* + * Marvell DB-88F6282-BP Development Board Setup + * + * Saeed Bishara <saeed@marvell.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +/include/ "kirkwood-db.dtsi" +/include/ "kirkwood-6282.dtsi" + +/ { + model = "Marvell DB-88F6282-BP Development Board"; + compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + ocp@f1000000 { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + + pcie@2,0 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi new file mode 100644 index 00000000000..c87cfb81612 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-db.dtsi @@ -0,0 +1,89 @@ +/* + * Marvell DB-{88F6281,88F6282}-BP Development Board Setup + * + * Saeed Bishara <saeed@marvell.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file contains the definitions that are common between the 6281 + * and 6282 variants of the Marvell Kirkwood Development Board. + */ + +/include/ "kirkwood.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + ocp@f1000000 { + pinctrl@10000 { + pmx_sdio_gpios: pmx-sdio-gpios { + marvell,pins = "mpp37", "mpp38"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; + clock-frequency = <200000000>; + status = "ok"; + }; + + nand@3000000 { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + chip-delay = <25>; + status = "okay"; + + partition@0 { + label = "uboot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x400000>; + }; + + partition@500000 { + label = "root"; + reg = <0x500000 0x1fb00000>; + }; + }; + + sata@80000 { + nr-ports = <2>; + status = "okay"; + }; + + ehci@50000 { + status = "okay"; + }; + + mvsdio@90000 { + pinctrl-0 = <&pmx_sdio_gpios>; + pinctrl-names = "default"; + wp-gpios = <&gpio1 5 0>; + cd-gpios = <&gpio1 6 0>; + status = "okay"; + }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 12ccf74ac3c..e591d5df769 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -109,6 +109,14 @@ reg = <0x980000 0x1f400000>; }; }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; gpio-leds { diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index 758824118a9..90501cf129b 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts @@ -139,6 +139,14 @@ cd-gpios = <&gpio1 15 0>; /* No WP GPIO */ }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; gpio-leds { diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index 1ca66ab83ad..0f852b40f5c 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -111,6 +111,14 @@ status = "okay"; nr-ports = <2>; }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; gpio-leds { diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index a7412b937a8..9ddf218f2cb 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts @@ -176,6 +176,14 @@ reg = <0x5040000 0x2fc0000>; }; }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; gpio_keys { diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts index 8295c833887..42648ab77c6 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts @@ -1,7 +1,8 @@ /dts-v1/; -/include/ "kirkwood-ts219.dtsi" +/include/ "kirkwood.dtsi" /include/ "kirkwood-6281.dtsi" +/include/ "kirkwood-ts219.dtsi" / { ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts index df3f95dfba3..95ceeb93ba5 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts @@ -1,7 +1,8 @@ /dts-v1/; -/include/ "kirkwood-ts219.dtsi" +/include/ "kirkwood.dtsi" /include/ "kirkwood-6282.dtsi" +/include/ "kirkwood-ts219.dtsi" / { ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi index 64ea27cb329..7c022fd4aef 100644 --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi @@ -1,5 +1,3 @@ -/include/ "kirkwood.dtsi" - / { model = "QNAP TS219 family"; compatible = "qnap,ts219", "marvell,kirkwood"; @@ -74,5 +72,12 @@ status = "okay"; nr-ports = <2>; }; + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index fada7e6d24d..7eef88f00fe 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -19,6 +19,7 @@ ocp@f1000000 { compatible = "simple-bus"; ranges = <0x00000000 0xf1000000 0x4000000 + 0xe0000000 0xe0000000 0x8100000 /* PCIE */ 0xf5000000 0xf5000000 0x0000400>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 82a404da1c0..99ba6e14ebf 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -516,7 +516,7 @@ usb_otg_hs: usb_otg_hs@480ab000 { compatible = "ti,omap3-musb"; reg = <0x480ab000 0x1000>; - interrupts = <0 92 0x4>, <0 93 0x4>; + interrupts = <92>, <93>; interrupt-names = "mc", "dma"; ti,hwmods = "usb_otg_hs"; multipoint = <1>; diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 03bd60deb52..eeb734e2570 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -56,9 +56,23 @@ }; }; +&omap4_pmx_wkup { + pinctrl-names = "default"; + pinctrl-0 = < + &twl6030_wkup_pins + >; + + twl6030_wkup_pins: pinmux_twl6030_wkup_pins { + pinctrl-single,pins = < + 0x14 0x2 /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */ + >; + }; +}; + &omap4_pmx_core { pinctrl-names = "default"; pinctrl-0 = < + &twl6030_pins &twl6040_pins &mcpdm_pins &mcbsp1_pins @@ -66,6 +80,12 @@ &tpd12s015_pins >; + twl6030_pins: pinmux_twl6030_pins { + pinctrl-single,pins = < + 0x15e 0x4118 /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */ + >; + }; + twl6040_pins: pinmux_twl6040_pins { pinctrl-single,pins = < 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */ diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index a35d9cd5806..98505a2ef16 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -142,9 +142,23 @@ }; }; +&omap4_pmx_wkup { + pinctrl-names = "default"; + pinctrl-0 = < + &twl6030_wkup_pins + >; + + twl6030_wkup_pins: pinmux_twl6030_wkup_pins { + pinctrl-single,pins = < + 0x14 0x2 /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */ + >; + }; +}; + &omap4_pmx_core { pinctrl-names = "default"; pinctrl-0 = < + &twl6030_pins &twl6040_pins &mcpdm_pins &dmic_pins @@ -179,6 +193,12 @@ >; }; + twl6030_pins: pinmux_twl6030_pins { + pinctrl-single,pins = < + 0x15e 0x4118 /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */ + >; + }; + twl6040_pins: pinmux_twl6040_pins { pinctrl-single,pins = < 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */ diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 3dd7ff82582..635cae28301 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -538,6 +538,7 @@ interrupts = <0 41 0x4>; ti,hwmods = "timer5"; ti,timer-dsp; + ti,timer-pwm; }; timer6: timer@4013a000 { @@ -574,6 +575,7 @@ reg = <0x4803e000 0x80>; interrupts = <0 45 0x4>; ti,hwmods = "timer9"; + ti,timer-pwm; }; timer10: timer@48086000 { @@ -581,6 +583,7 @@ reg = <0x48086000 0x80>; interrupts = <0 46 0x4>; ti,hwmods = "timer10"; + ti,timer-pwm; }; timer11: timer@48088000 { diff --git a/arch/arm/boot/dts/rk3066a-clocks.dtsi b/arch/arm/boot/dts/rk3066a-clocks.dtsi new file mode 100644 index 00000000000..6e307fc4c45 --- /dev/null +++ b/arch/arm/boot/dts/rk3066a-clocks.dtsi @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * This is a dummy clock, to be used as placeholder on + * other mux clocks when a specific parent clock is not + * yet implemented. It should be dropped when the driver + * is complete. + */ + dummy: dummy { + compatible = "fixed-clock"; + clock-frequency = <0>; + #clock-cells = <0>; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + + dummy48m: dummy48m { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + dummy150m: dummy150m { + compatible = "fixed-clock"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + clk_gates0: gate-clk@200000d0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d0 0x4>; + clocks = <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_core_periph", "gate_cpu_gpll", + "gate_ddrphy", "gate_aclk_cpu", + "gate_hclk_cpu", "gate_pclk_cpu", + "gate_atclk_cpu", "gate_i2s0", + "gate_i2s0_frac", "gate_i2s1", + "gate_i2s1_frac", "gate_i2s2", + "gate_i2s2_frac", "gate_spdif", + "gate_spdif_frac", "gate_testclk"; + + #clock-cells = <1>; + }; + + clk_gates1: gate-clk@200000d4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d4 0x4>; + clocks = <&xin24m>, <&xin24m>, + <&xin24m>, <&dummy>, + <&dummy>, <&xin24m>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>; + + clock-output-names = + "gate_timer0", "gate_timer1", + "gate_timer2", "gate_jtag", + "gate_aclk_lcdc1_src", "gate_otgphy0", + "gate_otgphy1", "gate_ddr_gpll", + "gate_uart0", "gate_frac_uart0", + "gate_uart1", "gate_frac_uart1", + "gate_uart2", "gate_frac_uart2", + "gate_uart3", "gate_frac_uart3"; + + #clock-cells = <1>; + }; + + clk_gates2: gate-clk@200000d8 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d8 0x4>; + clocks = <&clk_gates2 1>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&clk_gates2 3>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy48m>, + <&dummy>, <&dummy48m>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_periph_src", "gate_aclk_periph", + "gate_hclk_periph", "gate_pclk_periph", + "gate_smc", "gate_mac", + "gate_hsadc", "gate_hsadc_frac", + "gate_saradc", "gate_spi0", + "gate_spi1", "gate_mmc0", + "gate_mac_lbtest", "gate_mmc1", + "gate_emmc", "gate_tsadc"; + + #clock-cells = <1>; + }; + + clk_gates3: gate-clk@200000dc { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000dc 0x4>; + clocks = <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_aclk_lcdc0_src", "gate_dclk_lcdc0", + "gate_dclk_lcdc1", "gate_pclkin_cif0", + "gate_pclkin_cif1", "reserved", + "reserved", "gate_cif0_out", + "gate_cif1_out", "gate_aclk_vepu", + "gate_hclk_vepu", "gate_aclk_vdpu", + "gate_hclk_vdpu", "gate_gpu_src", + "reserved", "gate_xin27m"; + + #clock-cells = <1>; + }; + + clk_gates4: gate-clk@200000e0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000e0 0x4>; + clocks = <&clk_gates2 2>, <&clk_gates2 3>, + <&clk_gates2 1>, <&clk_gates2 1>, + <&clk_gates2 1>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates2 2>, + <&clk_gates0 4>, <&clk_gates0 4>, + <&clk_gates0 3>, <&clk_gates0 3>, + <&clk_gates0 3>, <&clk_gates2 3>, + <&clk_gates0 4>; + + clock-output-names = + "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix", + "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix", + "gate_aclk_pei_niu", "gate_hclk_usb_peri", + "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri", + "gate_hclk_cpubus", "gate_hclk_ahb2apb", + "gate_aclk_strc_sys", "gate_aclk_l2mem_con", + "gate_aclk_intmem", "gate_pclk_tsadc", + "gate_hclk_hdmi"; + + #clock-cells = <1>; + }; + + clk_gates5: gate-clk@200000e4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000e4 0x4>; + clocks = <&clk_gates0 3>, <&clk_gates2 1>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates0 4>, <&clk_gates0 5>, + <&clk_gates2 1>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates4 5>, + <&clk_gates4 5>, <&dummy>; + + clock-output-names = + "gate_aclk_dmac1", "gate_aclk_dmac2", + "gate_pclk_efuse", "gate_pclk_tzpc", + "gate_pclk_grf", "gate_pclk_pmu", + "gate_hclk_rom", "gate_pclk_ddrupctl", + "gate_aclk_smc", "gate_hclk_nandc", + "gate_hclk_mmc0", "gate_hclk_mmc1", + "gate_hclk_emmc", "gate_hclk_otg0", + "gate_hclk_otg1", "gate_aclk_gpu"; + + #clock-cells = <1>; + }; + + clk_gates6: gate-clk@200000e8 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000e8 0x4>; + clocks = <&clk_gates3 0>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates1 4>, + <&clk_gates0 4>, <&clk_gates3 0>, + <&clk_gates0 4>, <&clk_gates1 4>, + <&clk_gates3 0>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates1 4>, + <&clk_gates0 4>, <&clk_gates3 0>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_aclk_lcdc0", "gate_hclk_lcdc0", + "gate_hclk_lcdc1", "gate_aclk_lcdc1", + "gate_hclk_cif0", "gate_aclk_cif0", + "gate_hclk_cif1", "gate_aclk_cif1", + "gate_aclk_ipp", "gate_hclk_ipp", + "gate_hclk_rga", "gate_aclk_rga", + "gate_hclk_vio_bus", "gate_aclk_vio0", + "gate_aclk_vcodec", "gate_shclk_vio_h2h"; + + #clock-cells = <1>; + }; + + clk_gates7: gate-clk@200000ec { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000ec 0x4>; + clocks = <&clk_gates2 2>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates2 3>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&clk_gates2 3>, <&clk_gates2 3>; + + clock-output-names = + "gate_hclk_emac", "gate_hclk_spdif", + "gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch", + "gate_hclk_i2s_8ch", "gate_hclk_hsadc", + "gate_hclk_pidf", "gate_pclk_timer0", + "gate_pclk_timer1", "gate_pclk_timer2", + "gate_pclk_pwm01", "gate_pclk_pwm23", + "gate_pclk_spi0", "gate_pclk_spi1", + "gate_pclk_saradc", "gate_pclk_wdt"; + + #clock-cells = <1>; + }; + + clk_gates8: gate-clk@200000f0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000f0 0x4>; + clocks = <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&clk_gates2 3>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&dummy>, <&clk_gates0 5>; + + clock-output-names = + "gate_pclk_uart0", "gate_pclk_uart1", + "gate_pclk_uart2", "gate_pclk_uart3", + "gate_pclk_i2c0", "gate_pclk_i2c1", + "gate_pclk_i2c2", "gate_pclk_i2c3", + "gate_pclk_i2c4", "gate_pclk_gpio0", + "gate_pclk_gpio1", "gate_pclk_gpio2", + "gate_pclk_gpio3", "gate_pclk_gpio4", + "reserved", "gate_pclk_gpio6"; + + #clock-cells = <1>; + }; + + clk_gates9: gate-clk@200000f4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000f4 0x4>; + clocks = <&dummy>, <&clk_gates0 5>, + <&dummy>, <&dummy>, + <&dummy>, <&clk_gates1 4>, + <&clk_gates0 5>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>; + + clock-output-names = + "gate_clk_core_dbg", "gate_pclk_dbg", + "gate_clk_trace", "gate_atclk", + "gate_clk_l2c", "gate_aclk_vio1", + "gate_pclk_publ", "gate_aclk_intmem0", + "gate_aclk_intmem1", "gate_aclk_intmem2", + "gate_aclk_intmem3"; + + #clock-cells = <1>; + }; + }; + +}; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi new file mode 100644 index 00000000000..56bfac93d3f --- /dev/null +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "skeleton.dtsi" +#include "rk3066a-clocks.dtsi" + +/ { + compatible = "rockchip,rk3066a"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x1>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@1013d000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1013d000 0x1000>, + <0x1013c100 0x0100>; + }; + + L2: l2-cache-controller@10138000 { + compatible = "arm,pl310-cache"; + reg = <0x10138000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + local-timer@1013c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1013c600 0x20>; + interrupts = <GIC_PPI 13 0x304>; + clocks = <&dummy150m>; + }; + + timer@20038000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x20038000 0x100>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates1 0>, <&clk_gates7 7>; + clock-names = "timer", "pclk"; + }; + + timer@2003a000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2003a000 0x100>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates1 1>, <&clk_gates7 8>; + clock-names = "timer", "pclk"; + }; + + timer@2000e000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2000e000 0x100>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates1 2>, <&clk_gates7 9>; + clock-names = "timer", "pclk"; + }; + + pinctrl@20008000 { + compatible = "rockchip,rk3066a-pinctrl"; + reg = <0x20008000 0x150>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@20034000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20034000 0x100>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 9>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 10>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@2003e000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003e000 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 11>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 12>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio4@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 13>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio6@2000a000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2000a000 0x100>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 15>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_default: pcfg_pull_default { + bias-pull-pin-default; + }; + + pcfg_pull_none: pcfg_pull_none { + bias-disable; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + /* no rts / cts for uart2 */ + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart3_cts: uart3-cts { + rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart3_rts: uart3-rts { + rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + + sd0 { + sd0_clk: sd0-clk { + rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_cmd: sd0-cmd { + rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_cd: sd0-cd { + rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_wp: sd0-wp { + rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_bus1: sd0-bus-width1 { + rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_bus4: sd0-bus-width4 { + rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + + sd1 { + sd1_clk: sd1-clk { + rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_cmd: sd1-cmd { + rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_cd: sd1-cd { + rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_wp: sd1-wp { + rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_bus1: sd1-bus-width1 { + rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_bus4: sd1-bus-width4 { + rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + }; + + uart0: serial@10124000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10124000 0x400>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 8>; + status = "disabled"; + }; + + uart1: serial@10126000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10126000 0x400>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 10>; + status = "disabled"; + }; + + uart2: serial@20064000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20064000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 12>; + status = "disabled"; + }; + + uart3: serial@20068000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20068000 0x400>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 14>; + status = "disabled"; + }; + + dwmmc@10214000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10214000 0x1000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&clk_gates5 10>, <&clk_gates2 11>; + clock-names = "biu", "ciu"; + + status = "disabled"; + }; + + dwmmc@10218000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10218000 0x1000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&clk_gates5 11>, <&clk_gates2 13>; + clock-names = "biu", "ciu"; + + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 2e643ea51cc..5000e0d4284 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -75,11 +75,6 @@ compatible = "atmel,at91sam9x5-spi"; reg = <0xf0004000 0x100>; interrupts = <24 4 3>; - cs-gpios = <&pioD 13 0 - &pioD 14 0 /* conflicts with SCK0 and CANRX0 */ - &pioD 15 0 /* conflicts with CTS0 and CANTX0 */ - &pioD 16 0 /* conflicts with RTS0 and PWMFI3 */ - >; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; status = "disabled"; @@ -156,7 +151,7 @@ }; macb0: ethernet@f0028000 { - compatible = "cnds,pc302-gem", "cdns,gem"; + compatible = "cdns,pc302-gem", "cdns,gem"; reg = <0xf0028000 0x100>; interrupts = <34 4 3>; pinctrl-names = "default"; @@ -203,11 +198,6 @@ compatible = "atmel,at91sam9x5-spi"; reg = <0xf8008000 0x100>; interrupts = <25 4 3>; - cs-gpios = <&pioC 25 0 - &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */ - &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */ - &pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */ - >; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; status = "disabled"; diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index 1f8ed404626..b336e7787cb 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -32,6 +32,10 @@ ahb { apb { + spi0: spi@f0004000 { + cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; + }; + macb0: ethernet@f0028000 { phy-mode = "rgmii"; }; diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts index b28fbf3408e..6f82d936894 100644 --- a/arch/arm/boot/dts/ste-nomadik-s8815.dts +++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts @@ -14,13 +14,19 @@ bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk"; }; + /* This is where the interrupt is routed on the S8815 board */ + external-bus@34000000 { + ethernet@300 { + interrupt-parent = <&gpio3>; + interrupts = <8 0x1>; + }; + }; + /* Custom board node with GPIO pins to active etc */ usb-s8815 { /* The S8815 is using this very GPIO pin for the SMSC91x IRQs */ ethernet-gpio { - gpios = <&gpio3 19 0x1>; - interrupts = <19 0x1>; - interrupt-parent = <&gpio3>; + gpios = <&gpio3 8 0x1>; }; /* This will bias the MMC/SD card detect line */ mmcsd-gpio { diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts new file mode 100644 index 00000000000..8a1032c1ffc --- /dev/null +++ b/arch/arm/boot/dts/ste-u300.dts @@ -0,0 +1,473 @@ +/* + * Device Tree for the ST-Ericsson U300 Machine and SoC + */ + +/dts-v1/; +/include/ "skeleton.dtsi" + +/ { + model = "ST-Ericsson U300"; + compatible = "stericsson,u300"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + bootargs = "root=/dev/ram0 console=ttyAMA0,115200n8 earlyprintk"; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + memory { + reg = <0x48000000 0x03c00000>; + }; + + s365 { + compatible = "stericsson,s365"; + vana15-supply = <&ab3100_ldo_d_reg>; + syscon = <&syscon>; + }; + + syscon: syscon@c0011000 { + compatible = "stericsson,u300-syscon", "syscon"; + reg = <0xc0011000 0x1000>; + clk32: app_32_clk@32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + pll13: pll13@13M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + /* Slow bridge clocks under PLL13 */ + slow_clk: slow_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <0>; + clocks = <&pll13>; + }; + uart0_clk: uart0_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <1>; + clocks = <&slow_clk>; + }; + gpio_clk: gpio_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <4>; + clocks = <&slow_clk>; + }; + rtc_clk: rtc_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <6>; + clocks = <&slow_clk>; + }; + apptimer_clk: app_tmr_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <7>; + clocks = <&slow_clk>; + }; + acc_tmr_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <8>; + clocks = <&slow_clk>; + }; + pll208: pll208@208M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <208000000>; + }; + app208: app_208_clk@208M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&pll208>; + }; + cpu_clk@208M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <3>; + clocks = <&app208>; + }; + app104: app_104_clk@104M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <2>; + clock-mult = <1>; + clocks = <&pll208>; + }; + semi_clk@104M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <9>; + clocks = <&app104>; + }; + app52: app_52_clk@52M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <4>; + clock-mult = <1>; + clocks = <&pll208>; + }; + /* AHB subsystem clocks */ + ahb_clk: ahb_subsys_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <10>; + clocks = <&app52>; + }; + intcon_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <12>; + clocks = <&ahb_clk>; + }; + emif_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <5>; + clocks = <&ahb_clk>; + }; + dmac_clk: dmac_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <4>; + clocks = <&app52>; + }; + fsmc_clk: fsmc_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <6>; + clocks = <&app52>; + }; + xgam_clk: xgam_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <8>; + clocks = <&app52>; + }; + app26: app_26_clk@26M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <2>; + clock-mult = <1>; + clocks = <&app52>; + }; + /* Fast bridge clocks */ + fast_clk: fast_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <0>; + clocks = <&app26>; + }; + i2c0_clk: i2c0_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <1>; + clocks = <&fast_clk>; + }; + i2c1_clk: i2c1_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <2>; + clocks = <&fast_clk>; + }; + mmc_pclk: mmc_p_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <5>; + clocks = <&fast_clk>; + }; + mmc_mclk: mmc_mclk { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-mclk"; + clocks = <&mmc_pclk>; + }; + spi_clk: spi_p_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <6>; + clocks = <&fast_clk>; + }; + }; + + timer: timer@c0014000 { + compatible = "stericsson,u300-apptimer"; + reg = <0xc0014000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <24 25 26 27>; + clocks = <&apptimer_clk>; + }; + + gpio: gpio@c0016000 { + compatible = "stericsson,gpio-coh901"; + reg = <0xc0016000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <0 1 2 18 21 22 23>; + clocks = <&gpio_clk>; + interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + pinctrl: pinctrl@c0011000 { + compatible = "stericsson,pinctrl-u300"; + reg = <0xc0011000 0x1000>; + }; + + watchdog: watchdog@c0012000 { + compatible = "stericsson,coh901327"; + reg = <0xc0012000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <3>; + clocks = <&clk32>; + }; + + rtc: rtc@c0017000 { + compatible = "stericsson,coh901331"; + reg = <0xc0017000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <10>; + clocks = <&rtc_clk>; + }; + + dmac: dma-controller@c00020000 { + compatible = "stericsson,coh901318"; + reg = <0xc0020000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <2>; + #dma-cells = <1>; + dma-channels = <40>; + clocks = <&dmac_clk>; + }; + + /* A NAND flash of 128 MiB */ + fsmc: flash@40000000 { + compatible = "stericsson,fsmc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x9f800000 0x1000>, /* FSMC Register*/ + <0x80000000 0x4000>, /* NAND Base DATA */ + <0x80020000 0x4000>, /* NAND Base ADDR */ + <0x80010000 0x4000>; /* NAND Base CMD */ + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; + nand-skip-bbtscan; + clocks = <&fsmc_clk>; + + partition@0 { + label = "boot records"; + reg = <0x0 0x20000>; + }; + partition@20000 { + label = "free"; + reg = <0x20000 0x7e0000>; + }; + partition@800000 { + label = "platform"; + reg = <0x800000 0xf800000>; + }; + }; + + i2c0: i2c@c0004000 { + compatible = "st,ddci2c"; + reg = <0xc0004000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <8>; + clocks = <&i2c0_clk>; + #address-cells = <1>; + #size-cells = <0>; + ab3100: ab3100@0x48 { + compatible = "stericsson,ab3100"; + reg = <0x48>; + interrupt-parent = <&vica>; + interrupts = <0>; /* EXT0 IRQ */ + ab3100-regulators { + compatible = "stericsson,ab3100-regulators"; + ab3100_ldo_a_reg: ab3100_ldo_a { + regulator-compatible = "ab3100_ldo_a"; + startup-delay-us = <200>; + regulator-always-on; + regulator-boot-on; + }; + ab3100_ldo_c_reg: ab3100_ldo_c { + regulator-compatible = "ab3100_ldo_c"; + startup-delay-us = <200>; + }; + ab3100_ldo_d_reg: ab3100_ldo_d { + regulator-compatible = "ab3100_ldo_d"; + startup-delay-us = <200>; + }; + ab3100_ldo_e_reg: ab3100_ldo_e { + regulator-compatible = "ab3100_ldo_e"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <200>; + regulator-always-on; + regulator-boot-on; + }; + ab3100_ldo_f_reg: ab3100_ldo_f { + regulator-compatible = "ab3100_ldo_f"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + startup-delay-us = <600>; + regulator-always-on; + regulator-boot-on; + }; + ab3100_ldo_g_reg: ab3100_ldo_g { + regulator-compatible = "ab3100_ldo_g"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2850000>; + startup-delay-us = <400>; + }; + ab3100_ldo_h_reg: ab3100_ldo_h { + regulator-compatible = "ab3100_ldo_h"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2750000>; + startup-delay-us = <200>; + }; + ab3100_ldo_k_reg: ab3100_ldo_k { + regulator-compatible = "ab3100_ldo_k"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2750000>; + startup-delay-us = <200>; + }; + ab3100_ext_reg: ab3100_ext { + regulator-compatible = "ab3100_ext"; + }; + ab3100_buck_reg: ab3100_buck { + regulator-compatible = "ab3100_buck"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <1000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + + i2c1: i2c@c0005000 { + compatible = "st,ddci2c"; + reg = <0xc0005000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <9>; + clocks = <&i2c1_clk>; + #address-cells = <1>; + #size-cells = <0>; + fwcam0: fwcam@0x10 { + reg = <0x10>; + }; + fwcam1: fwcam@0x5d { + reg = <0x5d>; + }; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vica: interrupt-controller@a0001000 { + compatible = "arm,versatile-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xa0001000 0x20>; + }; + + vicb: interrupt-controller@a0002000 { + compatible = "arm,versatile-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xa0002000 0x20>; + }; + + uart0: serial@c0013000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xc0013000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <22>; + clocks = <&uart0_clk>, <&uart0_clk>; + clock-names = "apb_pclk", "uart0_clk"; + dmas = <&dmac 17 &dmac 18>; + dma-names = "tx", "rx"; + }; + + uart1: serial@c0007000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xc0007000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <20>; + dmas = <&dmac 38 &dmac 39>; + dma-names = "tx", "rx"; + }; + + mmcsd: mmcsd@c0001000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0xc0001000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <6 7>; + clocks = <&mmc_pclk>, <&mmc_mclk>; + clock-names = "apb_pclk", "mclk"; + max-frequency = <24000000>; + bus-width = <4>; // SD-card slot + mmc-cap-mmc-highspeed; + mmc-cap-sd-highspeed; + cd-gpios = <&gpio 12 0x4>; + cd-inverted; + vmmc-supply = <&ab3100_ldo_g_reg>; + dmas = <&dmac 14>; + dma-names = "rx"; + }; + + spi: ssp@c0006000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xc0006000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <23>; + clocks = <&spi_clk>, <&spi_clk>; + clock-names = "apb_pclk", "spi_clk"; + dmas = <&dmac 27 &dmac 28>; + dma-names = "tx", "rx"; + num-cs = <3>; + #address-cells = <1>; + #size-cells = <0>; + spi-dummy@1 { + compatible = "arm,pl022-dummy"; + reg = <1>; + spi-max-frequency = <20000000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index 4a7c35d6726..078ed7f618d 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -22,8 +22,8 @@ bootargs = "earlyprintk console=ttyS0,115200"; }; - soc { - uart0: uart@01c28000 { + soc@01c20000 { + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; status = "okay"; diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 14fb2e609ba..0dbee2c2390 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -49,16 +49,18 @@ uart0: uart@e0000000 { compatible = "xlnx,xuartps"; + clocks = <&clkc 23>, <&clkc 40>; + clock-names = "ref_clk", "aper_clk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; - clocks = <&uart_clk 0>; }; uart1: uart@e0001000 { compatible = "xlnx,xuartps"; + clocks = <&clkc 24>, <&clkc 41>; + clock-names = "ref_clk", "aper_clk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; - clocks = <&uart_clk 1>; }; slcr: slcr@f8000000 { @@ -69,50 +71,21 @@ #address-cells = <1>; #size-cells = <0>; - ps_clk: ps_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* clock-frequency set in board-specific file */ - clock-output-names = "ps_clk"; - }; - armpll: armpll { - #clock-cells = <0>; - compatible = "xlnx,zynq-pll"; - clocks = <&ps_clk>; - reg = <0x100 0x110>; - clock-output-names = "armpll"; - }; - ddrpll: ddrpll { - #clock-cells = <0>; - compatible = "xlnx,zynq-pll"; - clocks = <&ps_clk>; - reg = <0x104 0x114>; - clock-output-names = "ddrpll"; - }; - iopll: iopll { - #clock-cells = <0>; - compatible = "xlnx,zynq-pll"; - clocks = <&ps_clk>; - reg = <0x108 0x118>; - clock-output-names = "iopll"; - }; - uart_clk: uart_clk { - #clock-cells = <1>; - compatible = "xlnx,zynq-periph-clock"; - clocks = <&iopll &armpll &ddrpll>; - reg = <0x154>; - clock-output-names = "uart0_ref_clk", - "uart1_ref_clk"; - }; - cpu_clk: cpu_clk { + clkc: clkc { #clock-cells = <1>; - compatible = "xlnx,zynq-cpu-clock"; - clocks = <&iopll &armpll &ddrpll>; - reg = <0x120 0x1C4>; - clock-output-names = "cpu_6x4x", - "cpu_3x2x", - "cpu_2x", - "cpu_1x"; + compatible = "xlnx,ps7-clkc"; + ps-clk-frequency = <33333333>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", + "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", + "dci", "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", + "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", + "dma", "usb0_aper", "usb1_aper", "gem0_aper", + "gem1_aper", "sdio0_aper", "sdio1_aper", + "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", + "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", + "gpio_aper", "lqspi_aper", "smc_aper", "swdt", + "dbg_trc", "dbg_apb"; }; }; }; @@ -121,9 +94,8 @@ interrupt-parent = <&intc>; interrupts = < 0 10 4 0 11 4 0 12 4 >; compatible = "cdns,ttc"; + clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; - clocks = <&cpu_clk 3>; - clock-names = "cpu_1x"; clock-ranges; }; @@ -131,9 +103,8 @@ interrupt-parent = <&intc>; interrupts = < 0 37 4 0 38 4 0 39 4 >; compatible = "cdns,ttc"; + clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; - clocks = <&cpu_clk 3>; - clock-names = "cpu_1x"; clock-ranges; }; scutimer: scutimer@f8f00600 { @@ -141,7 +112,7 @@ interrupts = < 1 13 0x301 >; compatible = "arm,cortex-a9-twd-timer"; reg = < 0xf8f00600 0x20 >; - clocks = <&cpu_clk 1>; + clocks = <&clkc 4>; } ; }; }; diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index 86f44d5b026..e25a307438a 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -28,7 +28,3 @@ }; }; - -&ps_clk { - clock-frequency = <33333330>; -}; diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig index 9353184d730..c3a4e9ceba3 100644 --- a/arch/arm/common/Kconfig +++ b/arch/arm/common/Kconfig @@ -17,3 +17,6 @@ config SHARP_PARAM config SHARP_SCOOP bool + +config TI_PRIV_EDMA + bool diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index 48434cbe3e8..8c60f473e97 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o AFLAGS_mcpm_head.o := -march=armv7-a AFLAGS_vlock.o := -march=armv7-a +obj-$(CONFIG_TI_PRIV_EDMA) += edma.o diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/common/edma.c index 45b7c71d9cc..a1db6cd8cf7 100644 --- a/arch/arm/mach-davinci/dma.c +++ b/arch/arm/common/edma.c @@ -25,7 +25,7 @@ #include <linux/io.h> #include <linux/slab.h> -#include <mach/edma.h> +#include <linux/platform_data/edma.h> /* Offsets matching "struct edmacc_param" */ #define PARM_OPT 0x00 @@ -494,26 +494,6 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) return IRQ_HANDLED; } -/****************************************************************************** - * - * Transfer controller error interrupt handlers - * - *****************************************************************************/ - -#define tc_errs_handled false /* disabled as long as they're NOPs */ - -static irqreturn_t dma_tc0err_handler(int irq, void *data) -{ - dev_dbg(data, "dma_tc0err_handler\n"); - return IRQ_HANDLED; -} - -static irqreturn_t dma_tc1err_handler(int irq, void *data) -{ - dev_dbg(data, "dma_tc1err_handler\n"); - return IRQ_HANDLED; -} - static int reserve_contiguous_slots(int ctlr, unsigned int id, unsigned int num_slots, unsigned int start_slot) @@ -1541,23 +1521,6 @@ static int __init edma_probe(struct platform_device *pdev) arch_num_cc++; } - if (tc_errs_handled) { - status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0, - "edma_tc0", &pdev->dev); - if (status < 0) { - dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", - IRQ_TCERRINT0, status); - return status; - } - status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0, - "edma_tc1", &pdev->dev); - if (status < 0) { - dev_dbg(&pdev->dev, "request_irq %d --> %d\n", - IRQ_TCERRINT, status); - return status; - } - } - return 0; fail: diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig index 1cd94c36321..9e8c8316d6b 100644 --- a/arch/arm/configs/clps711x_defconfig +++ b/arch/arm/configs/clps711x_defconfig @@ -31,21 +31,18 @@ CONFIG_EP7211_DONGLE=y # CONFIG_WIRELESS is not set CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_AUTCPU12=y CONFIG_MTD_PLATRAM=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_GPIO=y CONFIG_NETDEVICES=y # CONFIG_NET_CADENCE is not set # CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CHELSIO is not set CONFIG_CS89x0=y CONFIG_CS89x0_PLATFORM=y # CONFIG_NET_VENDOR_FARADAY is not set @@ -63,7 +60,11 @@ CONFIG_CS89x0_PLATFORM=y # CONFIG_VT is not set CONFIG_SERIAL_CLPS711X_CONSOLE=y # CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_GPIO=y CONFIG_SPI=y +CONFIG_SPI_CLPS711X=y +CONFIG_GPIO_CLPS711X=y CONFIG_GPIO_GENERIC_PLATFORM=y # CONFIG_HWMON is not set CONFIG_FB=y @@ -87,4 +88,3 @@ CONFIG_DEBUG_LL=y CONFIG_EARLY_PRINTK=y # CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set -# CONFIG_CRC32 is not set diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index e40b435d204..ad7dfbbafa4 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -1,4 +1,4 @@ -CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_BLK_DEV_INITRD=y @@ -7,17 +7,18 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y -CONFIG_EFI_PARTITION=y CONFIG_ARCH_EXYNOS=y -CONFIG_S3C_LOWLEVEL_UART_PORT=1 +CONFIG_S3C_LOWLEVEL_UART_PORT=3 CONFIG_S3C24XX_PWM=y CONFIG_ARCH_EXYNOS5=y CONFIG_MACH_EXYNOS4_DT=y -CONFIG_MACH_EXYNOS5_DT=y CONFIG_SMP=y CONFIG_NR_CPUS=2 CONFIG_PREEMPT=y CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M" @@ -30,35 +31,59 @@ CONFIG_NET_KEY=y CONFIG_INET=y CONFIG_RFKILL_REGULATOR=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=m CONFIG_NETDEVICES=y CONFIG_SMSC911X=y CONFIG_USB_USBNET=y CONFIG_USB_NET_SMSC75XX=y CONFIG_USB_NET_SMSC95XX=y CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_CROS_EC=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_MOUSE_CYAPA=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_SAMSUNG=y CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_HW_RANDOM=y +CONFIG_TCG_TPM=y +CONFIG_TCG_TIS_I2C_INFINEON=y CONFIG_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_ARB_GPIO_CHALLENGE=y +CONFIG_I2C_S3C2410=y +CONFIG_DEBUG_GPIO=y # CONFIG_HWMON is not set +CONFIG_MFD_CROS_EC=y +CONFIG_MFD_CROS_EC_I2C=y +CONFIG_MFD_MAX77686=y +CONFIG_MFD_MAX8997=y +CONFIG_MFD_SEC_CORE=y CONFIG_MFD_TPS65090=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_MAX8997=y +CONFIG_REGULATOR_MAX77686=y +CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_TPS65090=y CONFIG_FB=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_SIMPLE=y CONFIG_EXYNOS_VIDEO=y CONFIG_EXYNOS_MIPI_DSI=y CONFIG_EXYNOS_DP=y @@ -67,6 +92,22 @@ CONFIG_FONTS=y CONFIG_FONT_7x14=y CONFIG_LOGO=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_S5P=y +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_PHY=y +CONFIG_SAMSUNG_USB2PHY=y +CONFIG_SAMSUNG_USB3PHY=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_S3C=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_IDMAC=y +CONFIG_MMC_DW_EXYNOS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S3C=y +CONFIG_COMMON_CLK_MAX77686=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS=y @@ -79,6 +120,7 @@ CONFIG_ROMFS_FS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DETECT_HUNG_TASK=y @@ -87,6 +129,5 @@ CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_INFO=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y -CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_SHA256=y CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 6ec010f248b..06686e7303a 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -37,6 +37,8 @@ CONFIG_MACH_IMX51_DT=y CONFIG_MACH_EUKREA_CPUIMX51SD=y CONFIG_SOC_IMX53=y CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_SOC_VF610=y CONFIG_MXC_PWM=y CONFIG_SMP=y CONFIG_VMSPLIT_2G=y @@ -47,6 +49,7 @@ CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" CONFIG_VFP=y CONFIG_NEON=y CONFIG_BINFMT_MISC=m +CONFIG_PM_RUNTIME=y CONFIG_PM_DEBUG=y CONFIG_PM_TEST_SUSPEND=y CONFIG_NET=y @@ -170,6 +173,7 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_FONTS=y @@ -182,6 +186,7 @@ CONFIG_SND_SOC=y CONFIG_SND_IMX_SOC=y CONFIG_SND_SOC_PHYCORE_AC97=y CONFIG_SND_SOC_EUKREA_TLV320=y +CONFIG_SND_SOC_IMX_WM8962=y CONFIG_SND_SOC_IMX_SGTL5000=y CONFIG_SND_SOC_IMX_MC13783=y CONFIG_USB=y @@ -208,10 +213,15 @@ CONFIG_IMX_SDMA=y CONFIG_MXS_DMA=y CONFIG_STAGING=y CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_FB_HELPER=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y CONFIG_DRM_IMX_IPUV3_CORE=y CONFIG_DRM_IMX_IPUV3=y CONFIG_COMMON_CLK_DEBUG=y # CONFIG_IOMMU_SUPPORT is not set +CONFIG_PWM=y +CONFIG_PWM_IMX=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig new file mode 100644 index 00000000000..62e968cac9d --- /dev/null +++ b/arch/arm/configs/keystone_defconfig @@ -0,0 +1,157 @@ +# CONFIG_SWAP is not set +CONFIG_POSIX_MQUEUE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_ELF_CORE is not set +# CONFIG_BASE_FULL is not set +CONFIG_EMBEDDED=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_ARCH_KEYSTONE=y +CONFIG_ARM_LPAE=y +CONFIG_SMP=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_SUSPEND is not set +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=y +CONFIG_NET_IPGRE_DEMUX=y +CONFIG_NET_IPGRE=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V2=y +CONFIG_INET_AH=y +CONFIG_INET_IPCOMP=y +CONFIG_IPV6=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_CPU=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_ULOG=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_CLUSTERIP=y +CONFIG_IP_NF_TARGET_ECN=y +CONFIG_IP_NF_TARGET_TTL=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP_SCTP=y +CONFIG_VLAN_8021Q=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_CMA=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_PLATRAM=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_UBI=y +CONFIG_PROC_DEVICETREE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_EEPROM_AT24=y +CONFIG_NETDEVICES=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_SPI=y +CONFIG_SPI_SPIDEV=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_USB_SUPPORT is not set +CONFIG_DMADEVICES=y +CONFIG_COMMON_CLK_DEBUG=y +CONFIG_MEMORY=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_WBUF_VERIFY=y +CONFIG_UBIFS_FS=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_SHIRQ=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_USER=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_XCBC=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_USER_API_SKCIPHER=y diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig index a1d8252e9ec..0f2aa61911a 100644 --- a/arch/arm/configs/kirkwood_defconfig +++ b/arch/arm/configs/kirkwood_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y @@ -31,6 +30,7 @@ CONFIG_MACH_T5325=y CONFIG_MACH_TS219=y CONFIG_MACH_TS41X=y CONFIG_MACH_CLOUDBOX_DT=y +CONFIG_MACH_DB88F628X_BP_DT=y CONFIG_MACH_DLINK_KIRKWOOD_DT=y CONFIG_MACH_DOCKSTAR_DT=y CONFIG_MACH_DREAMPLUG_DT=y @@ -50,14 +50,19 @@ CONFIG_MACH_NETSPACE_V2_DT=y CONFIG_MACH_NSA310_DT=y CONFIG_MACH_OPENBLOCKS_A6_DT=y CONFIG_MACH_READYNAS_DT=y +CONFIG_MACH_SHEEVAPLUG_DT=y CONFIG_MACH_TOPKICK_DT=y CONFIG_MACH_TS219_DT=y # CONFIG_CPU_FEROCEON_OLD_ID is not set +CONFIG_PCI_MVEBU=y CONFIG_PREEMPT=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPU_IDLE=y CONFIG_NET=y CONFIG_PACKET=y @@ -68,14 +73,12 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y # CONFIG_IPV6 is not set -CONFIG_NET_DSA=y CONFIG_NET_PKTGEN=m CONFIG_CFG80211=y CONFIG_MAC80211=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y @@ -140,6 +143,7 @@ CONFIG_HID_TOPSEED=y CONFIG_HID_THRUSTMASTER=y CONFIG_HID_ZEROPLUS=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_PRINTER=m diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 2e67a272df7..4aa64010661 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -31,10 +31,12 @@ CONFIG_SATA_HIGHBANK=y CONFIG_SATA_MV=y CONFIG_SATA_AHCI_PLATFORM=y CONFIG_NETDEVICES=y +CONFIG_SUN4I_EMAC=y CONFIG_NET_CALXEDA_XGMAC=y CONFIG_SMSC911X=y CONFIG_STMMAC_ETH=y CONFIG_SERIO_AMBAKMI=y +CONFIG_MDIO_SUN4I=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DW=y diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig index f3e8ae001ff..731814e2c18 100644 --- a/arch/arm/configs/mvebu_defconfig +++ b/arch/arm/configs/mvebu_defconfig @@ -13,6 +13,8 @@ CONFIG_MACH_ARMADA_370=y CONFIG_MACH_ARMADA_XP=y # CONFIG_CACHE_L2X0 is not set # CONFIG_SWP_EMULATE is not set +CONFIG_PCI=y +CONFIG_PCI_MVEBU=y CONFIG_SMP=y CONFIG_AEABI=y CONFIG_HIGHMEM=y @@ -60,6 +62,8 @@ CONFIG_USB_SUPPORT=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_STORAGE=y +CONFIG_USB_XHCI_HCD=y CONFIG_MMC=y CONFIG_MMC_MVSDIO=y CONFIG_NEW_LEDS=y @@ -96,5 +100,3 @@ CONFIG_TIMER_STATS=y # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_INFO=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y -CONFIG_EARLY_PRINTK=y diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig index 7e0ebb64a7f..9940f7b4e43 100644 --- a/arch/arm/configs/omap1_defconfig +++ b/arch/arm/configs/omap1_defconfig @@ -199,7 +199,6 @@ CONFIG_USB_PHY=y CONFIG_USB_DEBUG=y CONFIG_USB_DEVICEFS=y # CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_SUSPEND=y CONFIG_USB_MON=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index c1ef64bc5ab..abbe31937c6 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -20,6 +20,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y # CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_MULTI_V6=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_OMAP_RESET_CLOCKS=y CONFIG_OMAP_MUX_DEBUG=y @@ -204,7 +205,6 @@ CONFIG_USB=y CONFIG_USB_DEBUG=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_DEVICEFS=y -CONFIG_USB_SUSPEND=y CONFIG_USB_MON=y CONFIG_USB_WDM=y CONFIG_USB_STORAGE=y diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index a5f0485133c..f7ba316164d 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -153,6 +153,7 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_VIDEO_CLASS=m CONFIG_DRM=y +CONFIG_TEGRA_HOST1X=y CONFIG_DRM_TEGRA=y CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set @@ -202,7 +203,7 @@ CONFIG_TEGRA20_APB_DMA=y CONFIG_STAGING=y CONFIG_SENSORS_ISL29018=y CONFIG_SENSORS_ISL29028=y -CONFIG_SENSORS_AK8975=y +CONFIG_AK8975=y CONFIG_MFD_NVEC=y CONFIG_KEYBOARD_NVEC=y CONFIG_SERIO_NVEC_PS2=y diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig index 374000ec4e4..fd81a1b99cc 100644 --- a/arch/arm/configs/u300_defconfig +++ b/arch/arm/configs/u300_defconfig @@ -1,7 +1,8 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_SWAP is not set CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_EXPERT=y # CONFIG_AIO is not set @@ -11,12 +12,9 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_LBDAF is not set # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_CFQ is not set +# CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_U300=y -CONFIG_MACH_U300=y -CONFIG_MACH_U300_BS335=y CONFIG_MACH_U300_SPIDUMMY=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_ZBOOT_ROM_TEXT=0x0 @@ -44,14 +42,15 @@ CONFIG_I2C=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_FB=y CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set CONFIG_MMC=y -CONFIG_MMC_CLKGATE=y +CONFIG_MMC_UNSAFE_RESUME=y +# CONFIG_MMC_BLOCK_BOUNCE is not set CONFIG_MMC_ARMMMCI=y CONFIG_RTC_CLASS=y # CONFIG_RTC_HCTOSYS is not set @@ -70,4 +69,3 @@ CONFIG_DEBUG_FS=y CONFIG_TIMER_STATS=y # CONFIG_DEBUG_PREEMPT is not set CONFIG_DEBUG_INFO=y -# CONFIG_CRC32 is not set diff --git a/arch/arm/crypto/sha1-armv4-large.S b/arch/arm/crypto/sha1-armv4-large.S index 92c6eed7aac..99207c45ec1 100644 --- a/arch/arm/crypto/sha1-armv4-large.S +++ b/arch/arm/crypto/sha1-armv4-large.S @@ -195,6 +195,7 @@ ENTRY(sha1_block_data_order) add r3,r3,r10 @ E+=F_00_19(B,C,D) cmp r14,sp bne .L_00_15 @ [((11+4)*5+2)*3] + sub sp,sp,#25*4 #if __ARM_ARCH__<7 ldrb r10,[r1,#2] ldrb r9,[r1,#3] @@ -290,7 +291,6 @@ ENTRY(sha1_block_data_order) add r3,r3,r10 @ E+=F_00_19(B,C,D) ldr r8,.LK_20_39 @ [+15+16*4] - sub sp,sp,#25*4 cmn sp,#0 @ [+3], clear carry to denote 20_39 .L_20_39_or_60_79: ldr r9,[r14,#15*4] diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 05ee9eebad6..a5fef710af3 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -136,7 +136,11 @@ * assumes FIQs are enabled, and that the processor is in SVC mode. */ .macro save_and_disable_irqs, oldcpsr +#ifdef CONFIG_CPU_V7M + mrs \oldcpsr, primask +#else mrs \oldcpsr, cpsr +#endif disable_irq .endm @@ -150,7 +154,11 @@ * guarantee that this will preserve the flags. */ .macro restore_irqs_notrace, oldcpsr +#ifdef CONFIG_CPU_V7M + msr primask, \oldcpsr +#else msr cpsr_c, \oldcpsr +#endif .endm .macro restore_irqs, oldcpsr @@ -229,7 +237,14 @@ #endif .endm -#ifdef CONFIG_THUMB2_KERNEL +#if defined(CONFIG_CPU_V7M) + /* + * setmode is used to assert to be in svc mode during boot. For v7-M + * this is done in __v7m_setup, so setmode can be empty here. + */ + .macro setmode, mode, reg + .endm +#elif defined(CONFIG_THUMB2_KERNEL) .macro setmode, mode, reg mov \reg, #\mode msr cpsr_c, \reg diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h index 1f3262e99d8..cedd3721318 100644 --- a/arch/arm/include/asm/cp15.h +++ b/arch/arm/include/asm/cp15.h @@ -61,6 +61,20 @@ static inline void set_cr(unsigned int val) isb(); } +static inline unsigned int get_auxcr(void) +{ + unsigned int val; + asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val)); + return val; +} + +static inline void set_auxcr(unsigned int val) +{ + asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR" + : : "r" (val)); + isb(); +} + #ifndef CONFIG_SMP extern void adjust_cr(unsigned long mask, unsigned long set); #endif diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index 7652712d1d1..ec635ff32f4 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -10,6 +10,22 @@ #define CPUID_TLBTYPE 3 #define CPUID_MPIDR 5 +#ifdef CONFIG_CPU_V7M +#define CPUID_EXT_PFR0 0x40 +#define CPUID_EXT_PFR1 0x44 +#define CPUID_EXT_DFR0 0x48 +#define CPUID_EXT_AFR0 0x4c +#define CPUID_EXT_MMFR0 0x50 +#define CPUID_EXT_MMFR1 0x54 +#define CPUID_EXT_MMFR2 0x58 +#define CPUID_EXT_MMFR3 0x5c +#define CPUID_EXT_ISAR0 0x60 +#define CPUID_EXT_ISAR1 0x64 +#define CPUID_EXT_ISAR2 0x68 +#define CPUID_EXT_ISAR3 0x6c +#define CPUID_EXT_ISAR4 0x70 +#define CPUID_EXT_ISAR5 0x74 +#else #define CPUID_EXT_PFR0 "c1, 0" #define CPUID_EXT_PFR1 "c1, 1" #define CPUID_EXT_DFR0 "c1, 2" @@ -24,6 +40,7 @@ #define CPUID_EXT_ISAR3 "c2, 3" #define CPUID_EXT_ISAR4 "c2, 4" #define CPUID_EXT_ISAR5 "c2, 5" +#endif #define MPIDR_SMP_BITMASK (0x3 << 30) #define MPIDR_SMP_VALUE (0x2 << 30) @@ -79,7 +96,23 @@ extern unsigned int processor_id; __val; \ }) -#else /* ifdef CONFIG_CPU_CP15 */ +#elif defined(CONFIG_CPU_V7M) + +#include <asm/io.h> +#include <asm/v7m.h> + +#define read_cpuid(reg) \ + ({ \ + WARN_ON_ONCE(1); \ + 0; \ + }) + +static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset) +{ + return readl(BASEADDR_V7M_SCB + offset); +} + +#else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */ /* * read_cpuid and read_cpuid_ext should only ever be called on machines that @@ -106,7 +139,14 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void) return read_cpuid(CPUID_ID); } -#else /* ifdef CONFIG_CPU_CP15 */ +#elif defined(CONFIG_CPU_V7M) + +static inline unsigned int __attribute_const__ read_cpuid_id(void) +{ + return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID); +} + +#else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */ static inline unsigned int __attribute_const__ read_cpuid_id(void) { diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h index ea289e1435e..c81adc08b3f 100644 --- a/arch/arm/include/asm/glue-cache.h +++ b/arch/arm/include/asm/glue-cache.h @@ -117,10 +117,37 @@ # endif #endif +#if defined(CONFIG_CPU_V7M) +# ifdef _CACHE +# define MULTI_CACHE 1 +# else +# define _CACHE nop +# endif +#endif + #if !defined(_CACHE) && !defined(MULTI_CACHE) #error Unknown cache maintenance model #endif +#ifndef __ASSEMBLER__ +extern inline void nop_flush_icache_all(void) { } +extern inline void nop_flush_kern_cache_all(void) { } +extern inline void nop_flush_kern_cache_louis(void) { } +extern inline void nop_flush_user_cache_all(void) { } +extern inline void nop_flush_user_cache_range(unsigned long a, + unsigned long b, unsigned int c) { } + +extern inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { } +extern inline int nop_coherent_user_range(unsigned long a, + unsigned long b) { return 0; } +extern inline void nop_flush_kern_dcache_area(void *a, size_t s) { } + +extern inline void nop_dma_flush_range(const void *a, const void *b) { } + +extern inline void nop_dma_map_area(const void *s, size_t l, int f) { } +extern inline void nop_dma_unmap_area(const void *s, size_t l, int f) { } +#endif + #ifndef MULTI_CACHE #define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all) #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h index b6e9f2c108b..6b70f1b46a6 100644 --- a/arch/arm/include/asm/glue-df.h +++ b/arch/arm/include/asm/glue-df.h @@ -95,6 +95,14 @@ # endif #endif +#ifdef CONFIG_CPU_ABRT_NOMMU +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 +# else +# define CPU_DABORT_HANDLER nommu_early_abort +# endif +#endif + #ifndef CPU_DABORT_HANDLER #error Unknown data abort handler type #endif diff --git a/arch/arm/include/asm/glue-proc.h b/arch/arm/include/asm/glue-proc.h index ac1dd54724b..f2f39bcf794 100644 --- a/arch/arm/include/asm/glue-proc.h +++ b/arch/arm/include/asm/glue-proc.h @@ -230,6 +230,15 @@ # endif #endif +#ifdef CONFIG_CPU_V7M +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_v7m +# endif +#endif + #ifndef MULTI_CPU #define cpu_proc_init __glue(CPU_NAME,_proc_init) #define cpu_proc_fin __glue(CPU_NAME,_proc_fin) diff --git a/arch/arm/include/asm/hardware/pci_v3.h b/arch/arm/include/asm/hardware/pci_v3.h deleted file mode 100644 index 2811c7e2cfd..00000000000 --- a/arch/arm/include/asm/hardware/pci_v3.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * arch/arm/include/asm/hardware/pci_v3.h - * - * Internal header file PCI V3 chip - * - * Copyright (C) ARM Limited - * Copyright (C) 2000-2001 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef ASM_ARM_HARDWARE_PCI_V3_H -#define ASM_ARM_HARDWARE_PCI_V3_H - -/* ------------------------------------------------------------------------------- - * V3 Local Bus to PCI Bridge definitions - * ------------------------------------------------------------------------------- - * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04 - * All V3 register names are prefaced by V3_ to avoid clashing with any other - * PCI definitions. Their names match the user's manual. - * - * I'm assuming that I20 is disabled. - * - */ -#define V3_PCI_VENDOR 0x00000000 -#define V3_PCI_DEVICE 0x00000002 -#define V3_PCI_CMD 0x00000004 -#define V3_PCI_STAT 0x00000006 -#define V3_PCI_CC_REV 0x00000008 -#define V3_PCI_HDR_CFG 0x0000000C -#define V3_PCI_IO_BASE 0x00000010 -#define V3_PCI_BASE0 0x00000014 -#define V3_PCI_BASE1 0x00000018 -#define V3_PCI_SUB_VENDOR 0x0000002C -#define V3_PCI_SUB_ID 0x0000002E -#define V3_PCI_ROM 0x00000030 -#define V3_PCI_BPARAM 0x0000003C -#define V3_PCI_MAP0 0x00000040 -#define V3_PCI_MAP1 0x00000044 -#define V3_PCI_INT_STAT 0x00000048 -#define V3_PCI_INT_CFG 0x0000004C -#define V3_LB_BASE0 0x00000054 -#define V3_LB_BASE1 0x00000058 -#define V3_LB_MAP0 0x0000005E -#define V3_LB_MAP1 0x00000062 -#define V3_LB_BASE2 0x00000064 -#define V3_LB_MAP2 0x00000066 -#define V3_LB_SIZE 0x00000068 -#define V3_LB_IO_BASE 0x0000006E -#define V3_FIFO_CFG 0x00000070 -#define V3_FIFO_PRIORITY 0x00000072 -#define V3_FIFO_STAT 0x00000074 -#define V3_LB_ISTAT 0x00000076 -#define V3_LB_IMASK 0x00000077 -#define V3_SYSTEM 0x00000078 -#define V3_LB_CFG 0x0000007A -#define V3_PCI_CFG 0x0000007C -#define V3_DMA_PCI_ADR0 0x00000080 -#define V3_DMA_PCI_ADR1 0x00000090 -#define V3_DMA_LOCAL_ADR0 0x00000084 -#define V3_DMA_LOCAL_ADR1 0x00000094 -#define V3_DMA_LENGTH0 0x00000088 -#define V3_DMA_LENGTH1 0x00000098 -#define V3_DMA_CSR0 0x0000008B -#define V3_DMA_CSR1 0x0000009B -#define V3_DMA_CTLB_ADR0 0x0000008C -#define V3_DMA_CTLB_ADR1 0x0000009C -#define V3_DMA_DELAY 0x000000E0 -#define V3_MAIL_DATA 0x000000C0 -#define V3_PCI_MAIL_IEWR 0x000000D0 -#define V3_PCI_MAIL_IERD 0x000000D2 -#define V3_LB_MAIL_IEWR 0x000000D4 -#define V3_LB_MAIL_IERD 0x000000D6 -#define V3_MAIL_WR_STAT 0x000000D8 -#define V3_MAIL_RD_STAT 0x000000DA -#define V3_QBA_MAP 0x000000DC - -/* PCI COMMAND REGISTER bits - */ -#define V3_COMMAND_M_FBB_EN (1 << 9) -#define V3_COMMAND_M_SERR_EN (1 << 8) -#define V3_COMMAND_M_PAR_EN (1 << 6) -#define V3_COMMAND_M_MASTER_EN (1 << 2) -#define V3_COMMAND_M_MEM_EN (1 << 1) -#define V3_COMMAND_M_IO_EN (1 << 0) - -/* SYSTEM REGISTER bits - */ -#define V3_SYSTEM_M_RST_OUT (1 << 15) -#define V3_SYSTEM_M_LOCK (1 << 14) - -/* PCI_CFG bits - */ -#define V3_PCI_CFG_M_I2O_EN (1 << 15) -#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14) -#define V3_PCI_CFG_M_IO_DIS (1 << 13) -#define V3_PCI_CFG_M_EN3V (1 << 12) -#define V3_PCI_CFG_M_RETRY_EN (1 << 10) -#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) -#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) - -/* PCI_BASE register bits (PCI -> Local Bus) - */ -#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000 -#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00 -#define V3_PCI_BASE_M_PREFETCH (1 << 3) -#define V3_PCI_BASE_M_TYPE (3 << 1) -#define V3_PCI_BASE_M_IO (1 << 0) - -/* PCI MAP register bits (PCI -> Local bus) - */ -#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 -#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) -#define V3_PCI_MAP_M_ROM_SIZE (3 << 10) -#define V3_PCI_MAP_M_SWAP (3 << 8) -#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 -#define V3_PCI_MAP_M_REG_EN (1 << 1) -#define V3_PCI_MAP_M_ENABLE (1 << 0) - -/* - * LB_BASE0,1 register bits (Local bus -> PCI) - */ -#define V3_LB_BASE_ADR_BASE 0xfff00000 -#define V3_LB_BASE_SWAP (3 << 8) -#define V3_LB_BASE_ADR_SIZE (15 << 4) -#define V3_LB_BASE_PREFETCH (1 << 3) -#define V3_LB_BASE_ENABLE (1 << 0) - -#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) -#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) -#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) -#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) -#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) -#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) -#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) -#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) -#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) -#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) -#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) -#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) - -#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) - -/* - * LB_MAP0,1 register bits (Local bus -> PCI) - */ -#define V3_LB_MAP_MAP_ADR 0xfff0 -#define V3_LB_MAP_TYPE (7 << 1) -#define V3_LB_MAP_AD_LOW_EN (1 << 0) - -#define V3_LB_MAP_TYPE_IACK (0 << 1) -#define V3_LB_MAP_TYPE_IO (1 << 1) -#define V3_LB_MAP_TYPE_MEM (3 << 1) -#define V3_LB_MAP_TYPE_CONFIG (5 << 1) -#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) - -#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) - -/* - * LB_BASE2 register bits (Local bus -> PCI IO) - */ -#define V3_LB_BASE2_ADR_BASE 0xff00 -#define V3_LB_BASE2_SWAP (3 << 6) -#define V3_LB_BASE2_ENABLE (1 << 0) - -#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) - -/* - * LB_MAP2 register bits (Local bus -> PCI IO) - */ -#define V3_LB_MAP2_MAP_ADR 0xff00 - -#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) - -#endif diff --git a/arch/arm/include/asm/irqflags.h b/arch/arm/include/asm/irqflags.h index 1e6cca55c75..3b763d6652a 100644 --- a/arch/arm/include/asm/irqflags.h +++ b/arch/arm/include/asm/irqflags.h @@ -8,6 +8,16 @@ /* * CPU interrupt mask handling. */ +#ifdef CONFIG_CPU_V7M +#define IRQMASK_REG_NAME_R "primask" +#define IRQMASK_REG_NAME_W "primask" +#define IRQMASK_I_BIT 1 +#else +#define IRQMASK_REG_NAME_R "cpsr" +#define IRQMASK_REG_NAME_W "cpsr_c" +#define IRQMASK_I_BIT PSR_I_BIT +#endif + #if __LINUX_ARM_ARCH__ >= 6 static inline unsigned long arch_local_irq_save(void) @@ -15,7 +25,7 @@ static inline unsigned long arch_local_irq_save(void) unsigned long flags; asm volatile( - " mrs %0, cpsr @ arch_local_irq_save\n" + " mrs %0, " IRQMASK_REG_NAME_R " @ arch_local_irq_save\n" " cpsid i" : "=r" (flags) : : "memory", "cc"); return flags; @@ -129,7 +139,7 @@ static inline unsigned long arch_local_save_flags(void) { unsigned long flags; asm volatile( - " mrs %0, cpsr @ local_save_flags" + " mrs %0, " IRQMASK_REG_NAME_R " @ local_save_flags" : "=r" (flags) : : "memory", "cc"); return flags; } @@ -140,7 +150,7 @@ static inline unsigned long arch_local_save_flags(void) static inline void arch_local_irq_restore(unsigned long flags) { asm volatile( - " msr cpsr_c, %0 @ local_irq_restore" + " msr " IRQMASK_REG_NAME_W ", %0 @ local_irq_restore" : : "r" (flags) : "memory", "cc"); @@ -148,8 +158,8 @@ static inline void arch_local_irq_restore(unsigned long flags) static inline int arch_irqs_disabled_flags(unsigned long flags) { - return flags & PSR_I_BIT; + return flags & IRQMASK_I_BIT; } -#endif -#endif +#endif /* ifdef __KERNEL__ */ +#endif /* ifndef __ASM_ARM_IRQFLAGS_H */ diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h index 308ad7d6f98..75bf07910b8 100644 --- a/arch/arm/include/asm/mach/arch.h +++ b/arch/arm/include/asm/mach/arch.h @@ -8,6 +8,8 @@ * published by the Free Software Foundation. */ +#include <linux/types.h> + #ifndef __ASSEMBLY__ struct tag; @@ -16,8 +18,10 @@ struct pt_regs; struct smp_operations; #ifdef CONFIG_SMP #define smp_ops(ops) (&(ops)) +#define smp_init_ops(ops) (&(ops)) #else #define smp_ops(ops) (struct smp_operations *)NULL +#define smp_init_ops(ops) (bool (*)(void))NULL #endif struct machine_desc { @@ -41,6 +45,7 @@ struct machine_desc { unsigned char reserve_lp2 :1; /* never has lp2 */ char restart_mode; /* default restart mode */ struct smp_operations *smp; /* SMP operations */ + bool (*smp_init)(void); void (*fixup)(struct tag *, char **, struct meminfo *); void (*reserve)(void);/* reserve mem blocks */ diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index 7d2c3c84380..a1c90d7feb0 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -16,6 +16,7 @@ struct pci_sys_data; struct pci_ops; struct pci_bus; +struct device; struct hw_pci { #ifdef CONFIG_PCI_DOMAINS @@ -68,7 +69,16 @@ struct pci_sys_data { /* * Call this with your hw_pci struct to initialise the PCI system. */ -void pci_common_init(struct hw_pci *); +void pci_common_init_dev(struct device *, struct hw_pci *); + +/* + * Compatibility wrapper for older platforms that do not care about + * passing the parent device. + */ +static inline void pci_common_init(struct hw_pci *hw) +{ + pci_common_init_dev(NULL, hw); +} /* * Setup early fixed I/O mapping. @@ -96,9 +106,4 @@ extern struct pci_ops via82c505_ops; extern int via82c505_setup(int nr, struct pci_sys_data *); extern void via82c505_init(void *sysdata); -extern struct pci_ops pci_v3_ops; -extern int pci_v3_setup(int nr, struct pci_sys_data *); -extern void pci_v3_preinit(void); -extern void pci_v3_postinit(void); - #endif /* __ASM_MACH_PCI_H */ diff --git a/arch/arm/include/asm/percpu.h b/arch/arm/include/asm/percpu.h index 968c0a14e0a..209e6504922 100644 --- a/arch/arm/include/asm/percpu.h +++ b/arch/arm/include/asm/percpu.h @@ -30,8 +30,15 @@ static inline void set_my_cpu_offset(unsigned long off) static inline unsigned long __my_cpu_offset(void) { unsigned long off; - /* Read TPIDRPRW */ - asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) : : "memory"); + register unsigned long *sp asm ("sp"); + + /* + * Read TPIDRPRW. + * We want to allow caching the value, so avoid using volatile and + * instead use a fake stack read to hazard against barrier(). + */ + asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) : "Q" (*sp)); + return off; } #define __my_cpu_offset __my_cpu_offset() diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h index ce0dbe7c162..c4ae171850f 100644 --- a/arch/arm/include/asm/psci.h +++ b/arch/arm/include/asm/psci.h @@ -32,5 +32,14 @@ struct psci_operations { }; extern struct psci_operations psci_ops; +extern struct smp_operations psci_smp_ops; + +#ifdef CONFIG_ARM_PSCI +void psci_init(void); +bool psci_smp_available(void); +#else +static inline void psci_init(void) { } +static inline bool psci_smp_available(void) { return false; } +#endif #endif /* __ASM_ARM_PSCI_H */ diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index 3d52ee1bfb3..04c99f36ff7 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h @@ -45,6 +45,7 @@ struct pt_regs { */ static inline int valid_user_regs(struct pt_regs *regs) { +#ifndef CONFIG_CPU_V7M unsigned long mode = regs->ARM_cpsr & MODE_MASK; /* @@ -67,6 +68,9 @@ static inline int valid_user_regs(struct pt_regs *regs) regs->ARM_cpsr |= USR_MODE; return 0; +#else /* ifndef CONFIG_CPU_V7M */ + return 1; +#endif } static inline long regs_return_value(struct pt_regs *regs) diff --git a/arch/arm/include/asm/system_info.h b/arch/arm/include/asm/system_info.h index dfd386d0c02..720ea0320a6 100644 --- a/arch/arm/include/asm/system_info.h +++ b/arch/arm/include/asm/system_info.h @@ -11,6 +11,7 @@ #define CPU_ARCH_ARMv5TEJ 7 #define CPU_ARCH_ARMv6 8 #define CPU_ARCH_ARMv7 9 +#define CPU_ARCH_ARMv7M 10 #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h index 99a19512ee2..bdf2b8458ec 100644 --- a/arch/arm/include/asm/tlb.h +++ b/arch/arm/include/asm/tlb.h @@ -33,18 +33,6 @@ #include <asm/pgalloc.h> #include <asm/tlbflush.h> -/* - * We need to delay page freeing for SMP as other CPUs can access pages - * which have been removed but not yet had their TLB entries invalidated. - * Also, as ARMv7 speculative prefetch can drag new entries into the TLB, - * we need to apply this same delaying tactic to ensure correct operation. - */ -#if defined(CONFIG_SMP) || defined(CONFIG_CPU_32v7) -#define tlb_fast_mode(tlb) 0 -#else -#define tlb_fast_mode(tlb) 1 -#endif - #define MMU_GATHER_BUNDLE 8 /* @@ -112,12 +100,10 @@ static inline void __tlb_alloc_page(struct mmu_gather *tlb) static inline void tlb_flush_mmu(struct mmu_gather *tlb) { tlb_flush(tlb); - if (!tlb_fast_mode(tlb)) { - free_pages_and_swap_cache(tlb->pages, tlb->nr); - tlb->nr = 0; - if (tlb->pages == tlb->local) - __tlb_alloc_page(tlb); - } + free_pages_and_swap_cache(tlb->pages, tlb->nr); + tlb->nr = 0; + if (tlb->pages == tlb->local) + __tlb_alloc_page(tlb); } static inline void @@ -178,11 +164,6 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma) static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page) { - if (tlb_fast_mode(tlb)) { - free_page_and_swap_cache(page); - return 1; /* avoid calling tlb_flush_mmu */ - } - tlb->pages[tlb->nr++] = page; VM_BUG_ON(tlb->nr > tlb->max); return tlb->max - tlb->nr; diff --git a/arch/arm/include/asm/v7m.h b/arch/arm/include/asm/v7m.h new file mode 100644 index 00000000000..fa88d09fa3d --- /dev/null +++ b/arch/arm/include/asm/v7m.h @@ -0,0 +1,44 @@ +/* + * Common defines for v7m cpus + */ +#define V7M_SCS_ICTR IOMEM(0xe000e004) +#define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f + +#define BASEADDR_V7M_SCB IOMEM(0xe000ed00) + +#define V7M_SCB_CPUID 0x00 + +#define V7M_SCB_ICSR 0x04 +#define V7M_SCB_ICSR_PENDSVSET (1 << 28) +#define V7M_SCB_ICSR_PENDSVCLR (1 << 27) +#define V7M_SCB_ICSR_RETTOBASE (1 << 11) + +#define V7M_SCB_VTOR 0x08 + +#define V7M_SCB_SCR 0x10 +#define V7M_SCB_SCR_SLEEPDEEP (1 << 2) + +#define V7M_SCB_CCR 0x14 +#define V7M_SCB_CCR_STKALIGN (1 << 9) + +#define V7M_SCB_SHPR2 0x1c +#define V7M_SCB_SHPR3 0x20 + +#define V7M_SCB_SHCSR 0x24 +#define V7M_SCB_SHCSR_USGFAULTENA (1 << 18) +#define V7M_SCB_SHCSR_BUSFAULTENA (1 << 17) +#define V7M_SCB_SHCSR_MEMFAULTENA (1 << 16) + +#define V7M_xPSR_FRAMEPTRALIGN 0x00000200 +#define V7M_xPSR_EXCEPTIONNO 0x000001ff + +/* + * When branching to an address that has bits [31:28] == 0xf an exception return + * occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP + * extension Bit [4] defines if the exception frame has space allocated for FP + * state information, SBOP otherwise. Bit [3] defines the mode that is returned + * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used + * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01. + */ +#define EXC_RET_STACK_MASK 0x00000004 +#define EXC_RET_THREADMODE_PROCESSSTACK 0xfffffffd diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h index 91d38e38a0b..29da84e183f 100644 --- a/arch/arm/include/debug/imx-uart.h +++ b/arch/arm/include/debug/imx-uart.h @@ -65,6 +65,14 @@ #define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR #define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n) +#define IMX6SL_UART1_BASE_ADDR 0x02020000 +#define IMX6SL_UART2_BASE_ADDR 0x02024000 +#define IMX6SL_UART3_BASE_ADDR 0x02034000 +#define IMX6SL_UART4_BASE_ADDR 0x02038000 +#define IMX6SL_UART5_BASE_ADDR 0x02018000 +#define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR +#define IMX6SL_UART_BASE(n) IMX6SL_UART_BASE_ADDR(n) + #define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT) #ifdef CONFIG_DEBUG_IMX1_UART @@ -83,6 +91,8 @@ #define UART_PADDR IMX_DEBUG_UART_BASE(IMX53) #elif defined(CONFIG_DEBUG_IMX6Q_UART) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q) +#elif defined(CONFIG_DEBUG_IMX6SL_UART) +#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL) #endif #endif /* __DEBUG_IMX_UART_H */ diff --git a/arch/arm/include/debug/keystone.S b/arch/arm/include/debug/keystone.S new file mode 100644 index 00000000000..9aef9ba3f4f --- /dev/null +++ b/arch/arm/include/debug/keystone.S @@ -0,0 +1,43 @@ +/* + * Early serial debug output macro for Keystone SOCs + * + * Copyright 2013 Texas Instruments, Inc. + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * Based on RMKs low level debug code. + * Copyright (C) 1994-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/serial_reg.h> + +#define UART_SHIFT 2 +#if defined(CONFIG_DEBUG_KEYSTONE_UART0) +#define UART_PHYS 0x02530c00 +#define UART_VIRT 0xfeb30c00 +#elif defined(CONFIG_DEBUG_KEYSTONE_UART1) +#define UART_PHYS 0x02531000 +#define UART_VIRT 0xfeb31000 +#endif + + .macro addruart, rp, rv, tmp + ldr \rv, =UART_VIRT @ physical base address + ldr \rp, =UART_PHYS @ virtual base address + .endm + + .macro senduart,rd,rx + str \rd, [\rx, #UART_TX << UART_SHIFT] + .endm + + .macro busyuart,rd,rx +1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT] + and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE + teq \rd, #UART_LSR_TEMT | UART_LSR_THRE + bne 1002b + .endm + + .macro waituart,rd,rx + .endm diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S index df191afa3be..6517311a1c9 100644 --- a/arch/arm/include/debug/mvebu.S +++ b/arch/arm/include/debug/mvebu.S @@ -11,7 +11,12 @@ * published by the Free Software Foundation. */ +#ifdef CONFIG_DEBUG_MVEBU_UART_ALTERNATE +#define ARMADA_370_XP_REGS_PHYS_BASE 0xf1000000 +#else #define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 +#endif + #define ARMADA_370_XP_REGS_VIRT_BASE 0xfec00000 .macro addruart, rp, rv, tmp diff --git a/arch/arm/include/debug/rockchip.S b/arch/arm/include/debug/rockchip.S new file mode 100644 index 00000000000..cfd883e6958 --- /dev/null +++ b/arch/arm/include/debug/rockchip.S @@ -0,0 +1,42 @@ +/* + * Early serial output macro for Rockchip SoCs + * + * Copyright (C) 2012 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#if defined(CONFIG_DEBUG_RK29_UART0) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20060000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed60000 +#elif defined(CONFIG_DEBUG_RK29_UART1) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000 +#elif defined(CONFIG_DEBUG_RK29_UART2) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000 +#elif defined(CONFIG_DEBUG_RK3X_UART0) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10124000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb24000 +#elif defined(CONFIG_DEBUG_RK3X_UART1) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10126000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb26000 +#elif defined(CONFIG_DEBUG_RK3X_UART2) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000 +#elif defined(CONFIG_DEBUG_RK3X_UART3) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000 +#endif + + .macro addruart, rp, rv, tmp + ldr \rp, =ROCKCHIP_UART_DEBUG_PHYS_BASE + ldr \rv, =ROCKCHIP_UART_DEBUG_VIRT_BASE + .endm + +#define UART_SHIFT 2 +#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/include/debug/u300.S index 8ae8e4ab34b..6f04f08a203 100644 --- a/arch/arm/mach-u300/include/mach/debug-macro.S +++ b/arch/arm/include/debug/u300.S @@ -1,14 +1,11 @@ /* - * - * arch-arm/mach-u300/include/mach/debug-macro.S - * - * - * Copyright (C) 2006-2009 ST-Ericsson AB + * Copyright (C) 2006-2013 ST-Ericsson AB * License terms: GNU General Public License (GPL) version 2 * Debugging macro include header. * Author: Linus Walleij <linus.walleij@stericsson.com> */ -#include <mach/hardware.h> +#define U300_SLOW_PER_PHYS_BASE 0xc0010000 +#define U300_SLOW_PER_VIRT_BASE 0xff000000 .macro addruart, rp, rv, tmp /* If we move the address using MMU, use this. */ diff --git a/arch/arm/include/debug/ux500.S b/arch/arm/include/debug/ux500.S index 2848857f5b6..fbd24beeb1f 100644 --- a/arch/arm/include/debug/ux500.S +++ b/arch/arm/include/debug/ux500.S @@ -24,9 +24,9 @@ #define U8500_UART0_PHYS_BASE (0x80120000) #define U8500_UART1_PHYS_BASE (0x80121000) #define U8500_UART2_PHYS_BASE (0x80007000) -#define U8500_UART0_VIRT_BASE (0xa8120000) -#define U8500_UART1_VIRT_BASE (0xa8121000) -#define U8500_UART2_VIRT_BASE (0xa8007000) +#define U8500_UART0_VIRT_BASE (0xf8120000) +#define U8500_UART1_VIRT_BASE (0xf8121000) +#define U8500_UART2_VIRT_BASE (0xf8007000) #define __UX500_PHYS_UART(n) U8500_UART##n##_PHYS_BASE #define __UX500_VIRT_UART(n) U8500_UART##n##_VIRT_BASE #endif diff --git a/arch/arm/include/uapi/asm/ptrace.h b/arch/arm/include/uapi/asm/ptrace.h index 96ee0929790..5af0ed1b825 100644 --- a/arch/arm/include/uapi/asm/ptrace.h +++ b/arch/arm/include/uapi/asm/ptrace.h @@ -34,28 +34,47 @@ /* * PSR bits + * Note on V7M there is no mode contained in the PSR */ #define USR26_MODE 0x00000000 #define FIQ26_MODE 0x00000001 #define IRQ26_MODE 0x00000002 #define SVC26_MODE 0x00000003 +#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M) +/* + * Use 0 here to get code right that creates a userspace + * or kernel space thread. + */ +#define USR_MODE 0x00000000 +#define SVC_MODE 0x00000000 +#else #define USR_MODE 0x00000010 +#define SVC_MODE 0x00000013 +#endif #define FIQ_MODE 0x00000011 #define IRQ_MODE 0x00000012 -#define SVC_MODE 0x00000013 #define ABT_MODE 0x00000017 #define HYP_MODE 0x0000001a #define UND_MODE 0x0000001b #define SYSTEM_MODE 0x0000001f #define MODE32_BIT 0x00000010 #define MODE_MASK 0x0000001f -#define PSR_T_BIT 0x00000020 -#define PSR_F_BIT 0x00000040 -#define PSR_I_BIT 0x00000080 -#define PSR_A_BIT 0x00000100 -#define PSR_E_BIT 0x00000200 -#define PSR_J_BIT 0x01000000 -#define PSR_Q_BIT 0x08000000 + +#define V4_PSR_T_BIT 0x00000020 /* >= V4T, but not V7M */ +#define V7M_PSR_T_BIT 0x01000000 +#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M) +#define PSR_T_BIT V7M_PSR_T_BIT +#else +/* for compatibility */ +#define PSR_T_BIT V4_PSR_T_BIT +#endif + +#define PSR_F_BIT 0x00000040 /* >= V4, but not V7M */ +#define PSR_I_BIT 0x00000080 /* >= V4, but not V7M */ +#define PSR_A_BIT 0x00000100 /* >= V6, but not V7M */ +#define PSR_E_BIT 0x00000200 /* >= V6, but not V7M */ +#define PSR_J_BIT 0x01000000 /* >= V5J, but not V7M */ +#define PSR_Q_BIT 0x08000000 /* >= V5E, including V7M */ #define PSR_V_BIT 0x10000000 #define PSR_C_BIT 0x20000000 #define PSR_Z_BIT 0x40000000 diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 5f3338eacad..f4285b5ffb0 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -15,7 +15,7 @@ CFLAGS_REMOVE_return_address.o = -pg # Object file lists. -obj-y := elf.o entry-armv.o entry-common.o irq.o opcodes.o \ +obj-y := elf.o entry-common.o irq.o opcodes.o \ process.o ptrace.o return_address.o sched_clock.o \ setup.o signal.o stacktrace.o sys_arm.o time.o traps.o @@ -23,6 +23,12 @@ obj-$(CONFIG_ATAGS) += atags_parse.o obj-$(CONFIG_ATAGS_PROC) += atags_proc.o obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += atags_compat.o +ifeq ($(CONFIG_CPU_V7M),y) +obj-y += entry-v7m.o +else +obj-y += entry-armv.o +endif + obj-$(CONFIG_OC_ETM) += etm.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ISA_DMA_API) += dma.o @@ -82,6 +88,9 @@ obj-$(CONFIG_DEBUG_LL) += debug.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_ARM_VIRT_EXT) += hyp-stub.o -obj-$(CONFIG_ARM_PSCI) += psci.o +ifeq ($(CONFIG_ARM_PSCI),y) +obj-y += psci.o +obj-$(CONFIG_SMP) += psci_smp.o +endif extra-y := $(head-y) vmlinux.lds diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index b2ed73c4548..261fcc82616 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -445,7 +445,8 @@ static int pcibios_init_resources(int busnr, struct pci_sys_data *sys) return 0; } -static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head) +static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, + struct list_head *head) { struct pci_sys_data *sys = NULL; int ret; @@ -480,7 +481,7 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head) if (hw->scan) sys->bus = hw->scan(nr, sys); else - sys->bus = pci_scan_root_bus(NULL, sys->busnr, + sys->bus = pci_scan_root_bus(parent, sys->busnr, hw->ops, sys, &sys->resources); if (!sys->bus) @@ -497,7 +498,7 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head) } } -void pci_common_init(struct hw_pci *hw) +void pci_common_init_dev(struct device *parent, struct hw_pci *hw) { struct pci_sys_data *sys; LIST_HEAD(head); @@ -505,7 +506,7 @@ void pci_common_init(struct hw_pci *hw) pci_add_flags(PCI_REASSIGN_ALL_RSRC); if (hw->preinit) hw->preinit(); - pcibios_init_hw(hw, &head); + pcibios_init_hw(parent, hw, &head); if (hw->postinit) hw->postinit(); diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index bc5bc0a9713..85a72b0809c 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -350,6 +350,9 @@ ENDPROC(ftrace_stub) .align 5 ENTRY(vector_swi) +#ifdef CONFIG_CPU_V7M + v7m_exception_entry +#else sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Calling r0 - r12 ARM( add r8, sp, #S_PC ) @@ -360,6 +363,7 @@ ENTRY(vector_swi) str lr, [sp, #S_PC] @ Save calling PC str r8, [sp, #S_PSR] @ Save CPSR str r0, [sp, #S_OLD_R0] @ Save OLD_R0 +#endif zero_fp /* diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index 160f3376ba6..de23a9beed1 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -5,6 +5,7 @@ #include <asm/asm-offsets.h> #include <asm/errno.h> #include <asm/thread_info.h> +#include <asm/v7m.h> @ Bad Abort numbers @ ----------------- @@ -44,6 +45,116 @@ #endif .endm +#ifdef CONFIG_CPU_V7M +/* + * ARMv7-M exception entry/exit macros. + * + * xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are + * automatically saved on the current stack (32 words) before + * switching to the exception stack (SP_main). + * + * If exception is taken while in user mode, SP_main is + * empty. Otherwise, SP_main is aligned to 64 bit automatically + * (CCR.STKALIGN set). + * + * Linux assumes that the interrupts are disabled when entering an + * exception handler and it may BUG if this is not the case. Interrupts + * are disabled during entry and reenabled in the exit macro. + * + * v7m_exception_slow_exit is used when returning from SVC or PendSV. + * When returning to kernel mode, we don't return from exception. + */ + .macro v7m_exception_entry + @ determine the location of the registers saved by the core during + @ exception entry. Depending on the mode the cpu was in when the + @ exception happend that is either on the main or the process stack. + @ Bit 2 of EXC_RETURN stored in the lr register specifies which stack + @ was used. + tst lr, #EXC_RET_STACK_MASK + mrsne r12, psp + moveq r12, sp + + @ we cannot rely on r0-r3 and r12 matching the value saved in the + @ exception frame because of tail-chaining. So these have to be + @ reloaded. + ldmia r12!, {r0-r3} + + @ Linux expects to have irqs off. Do it here before taking stack space + cpsid i + + sub sp, #S_FRAME_SIZE-S_IP + stmdb sp!, {r0-r11} + + @ load saved r12, lr, return address and xPSR. + @ r0-r7 are used for signals and never touched from now on. Clobbering + @ r8-r12 is OK. + mov r9, r12 + ldmia r9!, {r8, r10-r12} + + @ calculate the original stack pointer value. + @ r9 currently points to the memory location just above the auto saved + @ xPSR. + @ The cpu might automatically 8-byte align the stack. Bit 9 + @ of the saved xPSR specifies if stack aligning took place. In this case + @ another 32-bit value is included in the stack. + + tst r12, V7M_xPSR_FRAMEPTRALIGN + addne r9, r9, #4 + + @ store saved r12 using str to have a register to hold the base for stm + str r8, [sp, #S_IP] + add r8, sp, #S_SP + @ store r13-r15, xPSR + stmia r8!, {r9-r12} + @ store old_r0 + str r0, [r8] + .endm + + /* + * PENDSV and SVCALL are configured to have the same exception + * priorities. As a kernel thread runs at SVCALL execution priority it + * can never be preempted and so we will never have to return to a + * kernel thread here. + */ + .macro v7m_exception_slow_exit ret_r0 + cpsid i + ldr lr, =EXC_RET_THREADMODE_PROCESSSTACK + + @ read original r12, sp, lr, pc and xPSR + add r12, sp, #S_IP + ldmia r12, {r1-r5} + + @ an exception frame is always 8-byte aligned. To tell the hardware if + @ the sp to be restored is aligned or not set bit 9 of the saved xPSR + @ accordingly. + tst r2, #4 + subne r2, r2, #4 + orrne r5, V7M_xPSR_FRAMEPTRALIGN + biceq r5, V7M_xPSR_FRAMEPTRALIGN + + @ write basic exception frame + stmdb r2!, {r1, r3-r5} + ldmia sp, {r1, r3-r5} + .if \ret_r0 + stmdb r2!, {r0, r3-r5} + .else + stmdb r2!, {r1, r3-r5} + .endif + + @ restore process sp + msr psp, r2 + + @ restore original r4-r11 + ldmia sp!, {r0-r11} + + @ restore main sp + add sp, sp, #S_FRAME_SIZE-S_IP + + cpsie i + bx lr + .endm +#endif /* CONFIG_CPU_V7M */ + @ @ Store/load the USER SP and LR registers by switching to the SYS @ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not @@ -165,6 +276,18 @@ rfeia sp! .endm +#ifdef CONFIG_CPU_V7M + /* + * Note we don't need to do clrex here as clearing the local monitor is + * part of each exception entry and exit sequence. + */ + .macro restore_user_regs, fast = 0, offset = 0 + .if \offset + add sp, #\offset + .endif + v7m_exception_slow_exit ret_r0 = \fast + .endm +#else /* ifdef CONFIG_CPU_V7M */ .macro restore_user_regs, fast = 0, offset = 0 clrex @ clear the exclusive monitor mov r2, sp @@ -181,6 +304,7 @@ add sp, sp, #S_FRAME_SIZE - S_SP movs pc, lr @ return & move spsr_svc into cpsr .endm +#endif /* ifdef CONFIG_CPU_V7M / else */ .macro get_thread_info, rd mov \rd, sp diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S new file mode 100644 index 00000000000..e00621f1403 --- /dev/null +++ b/arch/arm/kernel/entry-v7m.S @@ -0,0 +1,143 @@ +/* + * linux/arch/arm/kernel/entry-v7m.S + * + * Copyright (C) 2008 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Low-level vector interface routines for the ARMv7-M architecture + */ +#include <asm/memory.h> +#include <asm/glue.h> +#include <asm/thread_notify.h> +#include <asm/v7m.h> + +#include <mach/entry-macro.S> + +#include "entry-header.S" + +#ifdef CONFIG_TRACE_IRQFLAGS +#error "CONFIG_TRACE_IRQFLAGS not supported on the current ARMv7M implementation" +#endif + +__invalid_entry: + v7m_exception_entry + adr r0, strerr + mrs r1, ipsr + mov r2, lr + bl printk + mov r0, sp + bl show_regs +1: b 1b +ENDPROC(__invalid_entry) + +strerr: .asciz "\nUnhandled exception: IPSR = %08lx LR = %08lx\n" + + .align 2 +__irq_entry: + v7m_exception_entry + + @ + @ Invoke the IRQ handler + @ + mrs r0, ipsr + ldr r1, =V7M_xPSR_EXCEPTIONNO + and r0, r1 + sub r0, #16 + mov r1, sp + stmdb sp!, {lr} + @ routine called with r0 = irq number, r1 = struct pt_regs * + bl nvic_do_IRQ + + pop {lr} + @ + @ Check for any pending work if returning to user + @ + ldr r1, =BASEADDR_V7M_SCB + ldr r0, [r1, V7M_SCB_ICSR] + tst r0, V7M_SCB_ICSR_RETTOBASE + beq 2f + + get_thread_info tsk + ldr r2, [tsk, #TI_FLAGS] + tst r2, #_TIF_WORK_MASK + beq 2f @ no work pending + mov r0, #V7M_SCB_ICSR_PENDSVSET + str r0, [r1, V7M_SCB_ICSR] @ raise PendSV + +2: + @ registers r0-r3 and r12 are automatically restored on exception + @ return. r4-r7 were not clobbered in v7m_exception_entry so for + @ correctness they don't need to be restored. So only r8-r11 must be + @ restored here. The easiest way to do so is to restore r0-r7, too. + ldmia sp!, {r0-r11} + add sp, #S_FRAME_SIZE-S_IP + cpsie i + bx lr +ENDPROC(__irq_entry) + +__pendsv_entry: + v7m_exception_entry + + ldr r1, =BASEADDR_V7M_SCB + mov r0, #V7M_SCB_ICSR_PENDSVCLR + str r0, [r1, V7M_SCB_ICSR] @ clear PendSV + + @ execute the pending work, including reschedule + get_thread_info tsk + mov why, #0 + b ret_to_user +ENDPROC(__pendsv_entry) + +/* + * Register switch for ARMv7-M processors. + * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info + * previous and next are guaranteed not to be the same. + */ +ENTRY(__switch_to) + .fnstart + .cantunwind + add ip, r1, #TI_CPU_SAVE + stmia ip!, {r4 - r11} @ Store most regs on stack + str sp, [ip], #4 + str lr, [ip], #4 + mov r5, r0 + add r4, r2, #TI_CPU_SAVE + ldr r0, =thread_notify_head + mov r1, #THREAD_NOTIFY_SWITCH + bl atomic_notifier_call_chain + mov ip, r4 + mov r0, r5 + ldmia ip!, {r4 - r11} @ Load all regs saved previously + ldr sp, [ip] + ldr pc, [ip, #4]! + .fnend +ENDPROC(__switch_to) + + .data + .align 8 +/* + * Vector table (64 words => 256 bytes natural alignment) + */ +ENTRY(vector_table) + .long 0 @ 0 - Reset stack pointer + .long __invalid_entry @ 1 - Reset + .long __invalid_entry @ 2 - NMI + .long __invalid_entry @ 3 - HardFault + .long __invalid_entry @ 4 - MemManage + .long __invalid_entry @ 5 - BusFault + .long __invalid_entry @ 6 - UsageFault + .long __invalid_entry @ 7 - Reserved + .long __invalid_entry @ 8 - Reserved + .long __invalid_entry @ 9 - Reserved + .long __invalid_entry @ 10 - Reserved + .long vector_swi @ 11 - SVCall + .long __invalid_entry @ 12 - Debug Monitor + .long __invalid_entry @ 13 - Reserved + .long __pendsv_entry @ 14 - PendSV + .long __invalid_entry @ 15 - SysTick + .rept 64 - 16 + .long __irq_entry @ 16..64 - External Interrupts + .endr diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S index 6a2e09c952c..8812ce88f7a 100644 --- a/arch/arm/kernel/head-nommu.S +++ b/arch/arm/kernel/head-nommu.S @@ -19,6 +19,7 @@ #include <asm/asm-offsets.h> #include <asm/cp15.h> #include <asm/thread_info.h> +#include <asm/v7m.h> /* * Kernel startup entry point. @@ -50,10 +51,13 @@ ENTRY(stext) setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode @ and irqs disabled -#ifndef CONFIG_CPU_CP15 - ldr r9, =CONFIG_PROCESSOR_ID -#else +#if defined(CONFIG_CPU_CP15) mrc p15, 0, r9, c0, c0 @ get processor id +#elif defined(CONFIG_CPU_V7M) + ldr r9, =BASEADDR_V7M_SCB + ldr r9, [r9, V7M_SCB_CPUID] +#else + ldr r9, =CONFIG_PROCESSOR_ID #endif bl __lookup_processor_type @ r5=procinfo r9=cpuid movs r10, r5 @ invalid processor (r5=0)? diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index f2197031683..282de4826ab 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -411,7 +411,6 @@ static struct vm_area_struct gate_vma = { .vm_start = 0xffff0000, .vm_end = 0xffff0000 + PAGE_SIZE, .vm_flags = VM_READ | VM_EXEC | VM_MAYREAD | VM_MAYEXEC, - .vm_mm = &init_mm, }; static int __init gate_vma_init(void) diff --git a/arch/arm/kernel/psci.c b/arch/arm/kernel/psci.c index 36531643cc2..46931880093 100644 --- a/arch/arm/kernel/psci.c +++ b/arch/arm/kernel/psci.c @@ -158,7 +158,7 @@ static const struct of_device_id psci_of_match[] __initconst = { {}, }; -static int __init psci_init(void) +void __init psci_init(void) { struct device_node *np; const char *method; @@ -166,7 +166,7 @@ static int __init psci_init(void) np = of_find_matching_node(NULL, psci_of_match); if (!np) - return 0; + return; pr_info("probing function IDs from device-tree\n"); @@ -206,6 +206,5 @@ static int __init psci_init(void) out_put_node: of_node_put(np); - return 0; + return; } -early_initcall(psci_init); diff --git a/arch/arm/kernel/psci_smp.c b/arch/arm/kernel/psci_smp.c new file mode 100644 index 00000000000..23a11424c56 --- /dev/null +++ b/arch/arm/kernel/psci_smp.c @@ -0,0 +1,84 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Copyright (C) 2012 ARM Limited + * + * Author: Will Deacon <will.deacon@arm.com> + */ + +#include <linux/init.h> +#include <linux/irqchip/arm-gic.h> +#include <linux/smp.h> +#include <linux/of.h> + +#include <asm/psci.h> +#include <asm/smp_plat.h> + +/* + * psci_smp assumes that the following is true about PSCI: + * + * cpu_suspend Suspend the execution on a CPU + * @state we don't currently describe affinity levels, so just pass 0. + * @entry_point the first instruction to be executed on return + * returns 0 success, < 0 on failure + * + * cpu_off Power down a CPU + * @state we don't currently describe affinity levels, so just pass 0. + * no return on successful call + * + * cpu_on Power up a CPU + * @cpuid cpuid of target CPU, as from MPIDR + * @entry_point the first instruction to be executed on return + * returns 0 success, < 0 on failure + * + * migrate Migrate the context to a different CPU + * @cpuid cpuid of target CPU, as from MPIDR + * returns 0 success, < 0 on failure + * + */ + +extern void secondary_startup(void); + +static int __cpuinit psci_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + if (psci_ops.cpu_on) + return psci_ops.cpu_on(cpu_logical_map(cpu), + __pa(secondary_startup)); + return -ENODEV; +} + +#ifdef CONFIG_HOTPLUG_CPU +void __ref psci_cpu_die(unsigned int cpu) +{ + const struct psci_power_state ps = { + .type = PSCI_POWER_STATE_TYPE_POWER_DOWN, + }; + + if (psci_ops.cpu_off) + psci_ops.cpu_off(ps); + + /* We should never return */ + panic("psci: cpu %d failed to shutdown\n", cpu); +} +#else +#define psci_cpu_die NULL +#endif + +bool __init psci_smp_available(void) +{ + /* is cpu_on available at least? */ + return (psci_ops.cpu_on != NULL); +} + +struct smp_operations __initdata psci_smp_ops = { + .smp_boot_secondary = psci_boot_secondary, + .cpu_die = psci_cpu_die, +}; diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 1522c7ae31b..a1a2fbaaa31 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -37,6 +37,7 @@ #include <asm/cputype.h> #include <asm/elf.h> #include <asm/procinfo.h> +#include <asm/psci.h> #include <asm/sections.h> #include <asm/setup.h> #include <asm/smp_plat.h> @@ -128,7 +129,9 @@ struct stack { u32 und[3]; } ____cacheline_aligned; +#ifndef CONFIG_CPU_V7M static struct stack stacks[NR_CPUS]; +#endif char elf_platform[ELF_PLATFORM_SIZE]; EXPORT_SYMBOL(elf_platform); @@ -207,7 +210,7 @@ static const char *proc_arch[] = { "5TEJ", "6TEJ", "7", - "?(11)", + "7M", "?(12)", "?(13)", "?(14)", @@ -216,6 +219,12 @@ static const char *proc_arch[] = { "?(17)", }; +#ifdef CONFIG_CPU_V7M +static int __get_cpu_architecture(void) +{ + return CPU_ARCH_ARMv7M; +} +#else static int __get_cpu_architecture(void) { int cpu_arch; @@ -248,6 +257,7 @@ static int __get_cpu_architecture(void) return cpu_arch; } +#endif int __pure cpu_architecture(void) { @@ -293,7 +303,9 @@ static void __init cacheid_init(void) { unsigned int arch = cpu_architecture(); - if (arch >= CPU_ARCH_ARMv6) { + if (arch == CPU_ARCH_ARMv7M) { + cacheid = 0; + } else if (arch >= CPU_ARCH_ARMv6) { unsigned int cachetype = read_cpuid_cachetype(); if ((cachetype & (7 << 29)) == 4 << 29) { /* ARMv7 register format */ @@ -392,6 +404,7 @@ static void __init feat_v6_fixup(void) */ void notrace cpu_init(void) { +#ifndef CONFIG_CPU_V7M unsigned int cpu = smp_processor_id(); struct stack *stk = &stacks[cpu]; @@ -442,6 +455,7 @@ void notrace cpu_init(void) "I" (offsetof(struct stack, und[0])), PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE) : "r14"); +#endif } int __cpu_logical_map[NR_CPUS]; @@ -796,9 +810,15 @@ void __init setup_arch(char **cmdline_p) unflatten_device_tree(); arm_dt_init_cpu_maps(); + psci_init(); #ifdef CONFIG_SMP if (is_smp()) { - smp_set_ops(mdesc->smp); + if (!mdesc->smp_init || !mdesc->smp_init()) { + if (psci_smp_available()) + smp_set_ops(&psci_smp_ops); + else if (mdesc->smp) + smp_set_ops(mdesc->smp); + } smp_init_cpus(); } #endif diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 47ab90563bf..550d63cef68 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -251,7 +251,7 @@ void __ref cpu_die(void) * this returns, power and/or clocks can be removed at any point * from this CPU and its cache by platform_cpu_kill(). */ - RCU_NONIDLE(complete(&cpu_died)); + complete(&cpu_died); /* * Ensure that the cache lines associated with that completion are diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index f10316b4ecd..c5a59546a25 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -13,6 +13,7 @@ #include <linux/cpu.h> #include <linux/cpumask.h> +#include <linux/export.h> #include <linux/init.h> #include <linux/percpu.h> #include <linux/node.h> @@ -200,6 +201,7 @@ static inline void update_cpu_power(unsigned int cpuid, unsigned int mpidr) {} * cpu topology table */ struct cputopo_arm cpu_topology[NR_CPUS]; +EXPORT_SYMBOL_GPL(cpu_topology); const struct cpumask *cpu_coregroup_mask(int cpu) { diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 18b32e8e449..486e12a0f26 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -812,6 +812,7 @@ static void __init kuser_get_tls_init(unsigned long vectors) void __init early_trap_init(void *vectors_base) { +#ifndef CONFIG_CPU_V7M unsigned long vectors = (unsigned long)vectors_base; extern char __stubs_start[], __stubs_end[]; extern char __vectors_start[], __vectors_end[]; @@ -843,4 +844,11 @@ void __init early_trap_init(void *vectors_base) flush_icache_range(vectors, vectors + PAGE_SIZE); modify_domain(DOMAIN_USER, DOMAIN_CLIENT); +#else /* ifndef CONFIG_CPU_V7M */ + /* + * on V7-M there is no need to copy the vector table to a dedicated + * memory area. The address is configurable and so a table in the kernel + * image can be used. + */ +#endif } diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c index 37d216d814c..ef1703b9587 100644 --- a/arch/arm/kvm/arm.c +++ b/arch/arm/kvm/arm.c @@ -492,6 +492,11 @@ static void vcpu_pause(struct kvm_vcpu *vcpu) wait_event_interruptible(*wq, !vcpu->arch.pause); } +static int kvm_vcpu_initialized(struct kvm_vcpu *vcpu) +{ + return vcpu->arch.target >= 0; +} + /** * kvm_arch_vcpu_ioctl_run - the main VCPU run function to execute guest code * @vcpu: The VCPU pointer @@ -508,8 +513,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) int ret; sigset_t sigsaved; - /* Make sure they initialize the vcpu with KVM_ARM_VCPU_INIT */ - if (unlikely(vcpu->arch.target < 0)) + if (unlikely(!kvm_vcpu_initialized(vcpu))) return -ENOEXEC; ret = kvm_vcpu_first_run_init(vcpu); @@ -710,6 +714,10 @@ long kvm_arch_vcpu_ioctl(struct file *filp, case KVM_SET_ONE_REG: case KVM_GET_ONE_REG: { struct kvm_one_reg reg; + + if (unlikely(!kvm_vcpu_initialized(vcpu))) + return -ENOEXEC; + if (copy_from_user(®, argp, sizeof(reg))) return -EFAULT; if (ioctl == KVM_SET_ONE_REG) @@ -722,6 +730,9 @@ long kvm_arch_vcpu_ioctl(struct file *filp, struct kvm_reg_list reg_list; unsigned n; + if (unlikely(!kvm_vcpu_initialized(vcpu))) + return -ENOEXEC; + if (copy_from_user(®_list, user_list, sizeof(reg_list))) return -EFAULT; n = reg_list.n; diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c index 965706578f1..84ba67b982c 100644 --- a/arch/arm/kvm/mmu.c +++ b/arch/arm/kvm/mmu.c @@ -43,7 +43,14 @@ static phys_addr_t hyp_idmap_vector; static void kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) { - kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, kvm, ipa); + /* + * This function also gets called when dealing with HYP page + * tables. As HYP doesn't have an associated struct kvm (and + * the HYP page tables are fairly static), we don't do + * anything there. + */ + if (kvm) + kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, kvm, ipa); } static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, @@ -78,18 +85,20 @@ static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) return p; } -static void clear_pud_entry(pud_t *pud) +static void clear_pud_entry(struct kvm *kvm, pud_t *pud, phys_addr_t addr) { pmd_t *pmd_table = pmd_offset(pud, 0); pud_clear(pud); + kvm_tlb_flush_vmid_ipa(kvm, addr); pmd_free(NULL, pmd_table); put_page(virt_to_page(pud)); } -static void clear_pmd_entry(pmd_t *pmd) +static void clear_pmd_entry(struct kvm *kvm, pmd_t *pmd, phys_addr_t addr) { pte_t *pte_table = pte_offset_kernel(pmd, 0); pmd_clear(pmd); + kvm_tlb_flush_vmid_ipa(kvm, addr); pte_free_kernel(NULL, pte_table); put_page(virt_to_page(pmd)); } @@ -100,11 +109,12 @@ static bool pmd_empty(pmd_t *pmd) return page_count(pmd_page) == 1; } -static void clear_pte_entry(pte_t *pte) +static void clear_pte_entry(struct kvm *kvm, pte_t *pte, phys_addr_t addr) { if (pte_present(*pte)) { kvm_set_pte(pte, __pte(0)); put_page(virt_to_page(pte)); + kvm_tlb_flush_vmid_ipa(kvm, addr); } } @@ -114,7 +124,8 @@ static bool pte_empty(pte_t *pte) return page_count(pte_page) == 1; } -static void unmap_range(pgd_t *pgdp, unsigned long long start, u64 size) +static void unmap_range(struct kvm *kvm, pgd_t *pgdp, + unsigned long long start, u64 size) { pgd_t *pgd; pud_t *pud; @@ -138,15 +149,15 @@ static void unmap_range(pgd_t *pgdp, unsigned long long start, u64 size) } pte = pte_offset_kernel(pmd, addr); - clear_pte_entry(pte); + clear_pte_entry(kvm, pte, addr); range = PAGE_SIZE; /* If we emptied the pte, walk back up the ladder */ if (pte_empty(pte)) { - clear_pmd_entry(pmd); + clear_pmd_entry(kvm, pmd, addr); range = PMD_SIZE; if (pmd_empty(pmd)) { - clear_pud_entry(pud); + clear_pud_entry(kvm, pud, addr); range = PUD_SIZE; } } @@ -165,14 +176,14 @@ void free_boot_hyp_pgd(void) mutex_lock(&kvm_hyp_pgd_mutex); if (boot_hyp_pgd) { - unmap_range(boot_hyp_pgd, hyp_idmap_start, PAGE_SIZE); - unmap_range(boot_hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE); + unmap_range(NULL, boot_hyp_pgd, hyp_idmap_start, PAGE_SIZE); + unmap_range(NULL, boot_hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE); kfree(boot_hyp_pgd); boot_hyp_pgd = NULL; } if (hyp_pgd) - unmap_range(hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE); + unmap_range(NULL, hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE); kfree(init_bounce_page); init_bounce_page = NULL; @@ -200,9 +211,10 @@ void free_hyp_pgds(void) if (hyp_pgd) { for (addr = PAGE_OFFSET; virt_addr_valid(addr); addr += PGDIR_SIZE) - unmap_range(hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE); + unmap_range(NULL, hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE); for (addr = VMALLOC_START; is_vmalloc_addr((void*)addr); addr += PGDIR_SIZE) - unmap_range(hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE); + unmap_range(NULL, hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE); + kfree(hyp_pgd); hyp_pgd = NULL; } @@ -393,7 +405,7 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm) */ static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size) { - unmap_range(kvm->arch.pgd, start, size); + unmap_range(kvm, kvm->arch.pgd, start, size); } /** @@ -675,7 +687,6 @@ static void handle_hva_to_gpa(struct kvm *kvm, static void kvm_unmap_hva_handler(struct kvm *kvm, gpa_t gpa, void *data) { unmap_stage2_range(kvm, gpa, PAGE_SIZE); - kvm_tlb_flush_vmid_ipa(kvm, gpa); } int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index 2acdff4c1df..180b3024bec 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c @@ -174,6 +174,7 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) static struct clock_event_device clkevt = { .name = "at91_tick", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, .rating = 150, .set_next_event = clkevt32k_next_event, .set_mode = clkevt32k_mode, @@ -264,9 +265,11 @@ void __init at91rm9200_timer_init(void) at91_st_write(AT91_ST_RTMR, 1); /* Setup timer clockevent, with minimum of two ticks (important!!) */ + clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift); + clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt); + clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1; clkevt.cpumask = cpumask_of(0); - clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK, - 2, AT91_ST_ALMV); + clockevents_register_device(&clkevt); /* register clocksource */ clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK); diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c index 13cdbcd48f5..c7d670d1180 100644 --- a/arch/arm/mach-at91/at91sam9n12.c +++ b/arch/arm/mach-at91/at91sam9n12.c @@ -223,13 +223,7 @@ static void __init at91sam9n12_map_io(void) at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE); } -void __init at91sam9n12_initialize(void) -{ - at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0); -} - AT91_SOC_START(at91sam9n12) .map_io = at91sam9n12_map_io, .register_clocks = at91sam9n12_register_clocks, - .init = at91sam9n12_initialize, AT91_SOC_END diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 31df12029c4..2bd7f51b0b8 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -179,9 +179,9 @@ extern void __iomem *at91_pmc_base; #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ #define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor Value */ #define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */ -#define AT91_PMC_PCR_DIV2 0x2 /* Peripheral clock is MCK/2 */ -#define AT91_PMC_PCR_DIV4 0x4 /* Peripheral clock is MCK/4 */ -#define AT91_PMC_PCR_DIV8 0x8 /* Peripheral clock is MCK/8 */ +#define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */ +#define AT91_PMC_PCR_DIV4 0x2 /* Peripheral clock is MCK/4 */ +#define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */ #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ #endif diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig index 2d00165e85e..01ad4d41e72 100644 --- a/arch/arm/mach-clps711x/Kconfig +++ b/arch/arm/mach-clps711x/Kconfig @@ -22,8 +22,7 @@ config ARCH_CLEP7312 config ARCH_EDB7211 bool "EDB7211" - select ARCH_SELECT_MEMORY_MODEL - select ARCH_SPARSEMEM_ENABLE + select ARCH_HAS_HOLES_MEMORYMODEL help Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211 evaluation board. diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile index 992995af666..f30ed2b496f 100644 --- a/arch/arm/mach-clps711x/Makefile +++ b/arch/arm/mach-clps711x/Makefile @@ -4,10 +4,7 @@ # Object file lists. -obj-y := common.o -obj-m := -obj-n := -obj- := +obj-y := common.o devices.o obj-$(CONFIG_ARCH_AUTCPU12) += board-autcpu12.o obj-$(CONFIG_ARCH_CDB89712) += board-cdb89712.o diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c index f38584709df..5867aebd8d0 100644 --- a/arch/arm/mach-clps711x/board-autcpu12.c +++ b/arch/arm/mach-clps711x/board-autcpu12.c @@ -26,6 +26,8 @@ #include <linux/gpio.h> #include <linux/ioport.h> #include <linux/interrupt.h> +#include <linux/mtd/physmap.h> +#include <linux/mtd/plat-ram.h> #include <linux/mtd/partitions.h> #include <linux/mtd/nand-gpio.h> #include <linux/platform_device.h> @@ -40,38 +42,49 @@ #include <asm/page.h> #include <asm/mach/map.h> -#include <mach/autcpu12.h> #include "common.h" +#include "devices.h" -#define AUTCPU12_CS8900_BASE (CS2_PHYS_BASE + 0x300) -#define AUTCPU12_CS8900_IRQ (IRQ_EINT3) +/* NOR flash */ +#define AUTCPU12_FLASH_BASE (CS0_PHYS_BASE) + +/* Board specific hardware definitions */ +#define AUTCPU12_CHAR_LCD_BASE (CS1_PHYS_BASE + 0x00000000) +#define AUTCPU12_CSAUX1_BASE (CS1_PHYS_BASE + 0x04000000) +#define AUTCPU12_CAN_BASE (CS1_PHYS_BASE + 0x08000000) +#define AUTCPU12_TOUCH_BASE (CS1_PHYS_BASE + 0x0a000000) +#define AUTCPU12_IO_BASE (CS1_PHYS_BASE + 0x0c000000) +#define AUTCPU12_LPT_BASE (CS1_PHYS_BASE + 0x0e000000) + +/* NVRAM */ +#define AUTCPU12_NVRAM_BASE (CS1_PHYS_BASE + 0x02000000) +/* SmartMedia flash */ #define AUTCPU12_SMC_BASE (CS1_PHYS_BASE + 0x06000000) #define AUTCPU12_SMC_SEL_BASE (AUTCPU12_SMC_BASE + 0x10) +/* Ethernet */ +#define AUTCPU12_CS8900_BASE (CS2_PHYS_BASE + 0x300) +#define AUTCPU12_CS8900_IRQ (IRQ_EINT3) + +/* NAND flash */ #define AUTCPU12_MMGPIO_BASE (CLPS711X_NR_GPIO) #define AUTCPU12_SMC_NCE (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */ #define AUTCPU12_SMC_RDY CLPS711X_GPIO(1, 2) #define AUTCPU12_SMC_ALE CLPS711X_GPIO(1, 3) #define AUTCPU12_SMC_CLE CLPS711X_GPIO(1, 3) +/* LCD contrast digital potentiometer */ +#define AUTCPU12_DPOT_CS CLPS711X_GPIO(4, 0) +#define AUTCPU12_DPOT_CLK CLPS711X_GPIO(4, 1) +#define AUTCPU12_DPOT_UD CLPS711X_GPIO(4, 2) + static struct resource autcpu12_cs8900_resource[] __initdata = { DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K), DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ), }; -static struct resource autcpu12_nvram_resource[] __initdata = { - DEFINE_RES_MEM_NAMED(AUTCPU12_PHYS_NVRAM, SZ_128K, "SRAM"), -}; - -static struct platform_device autcpu12_nvram_pdev __initdata = { - .name = "autcpu12_nvram", - .id = -1, - .resource = autcpu12_nvram_resource, - .num_resources = ARRAY_SIZE(autcpu12_nvram_resource), -}; - static struct resource autcpu12_nand_resource[] __initdata = { DEFINE_RES_MEM(AUTCPU12_SMC_BASE, SZ_16), }; @@ -147,17 +160,106 @@ static struct platform_device autcpu12_mmgpio_pdev __initdata = { }, }; +static const struct gpio autcpu12_gpios[] __initconst = { + { AUTCPU12_DPOT_CS, GPIOF_OUT_INIT_HIGH, "DPOT CS" }, + { AUTCPU12_DPOT_CLK, GPIOF_OUT_INIT_LOW, "DPOT CLK" }, + { AUTCPU12_DPOT_UD, GPIOF_OUT_INIT_LOW, "DPOT UD" }, +}; + +static struct mtd_partition autcpu12_flash_partitions[] = { + { + .name = "NOR.0", + .offset = 0, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data autcpu12_flash_pdata = { + .width = 4, + .parts = autcpu12_flash_partitions, + .nr_parts = ARRAY_SIZE(autcpu12_flash_partitions), +}; + +static struct resource autcpu12_flash_resources[] __initdata = { + DEFINE_RES_MEM(AUTCPU12_FLASH_BASE, SZ_8M), +}; + +static struct platform_device autcpu12_flash_pdev __initdata = { + .name = "physmap-flash", + .id = 0, + .resource = autcpu12_flash_resources, + .num_resources = ARRAY_SIZE(autcpu12_flash_resources), + .dev = { + .platform_data = &autcpu12_flash_pdata, + }, +}; + +static struct resource autcpu12_nvram_resource[] __initdata = { + DEFINE_RES_MEM(AUTCPU12_NVRAM_BASE, 0), +}; + +static struct platdata_mtd_ram autcpu12_nvram_pdata = { + .bankwidth = 4, +}; + +static struct platform_device autcpu12_nvram_pdev __initdata = { + .name = "mtd-ram", + .id = 0, + .resource = autcpu12_nvram_resource, + .num_resources = ARRAY_SIZE(autcpu12_nvram_resource), + .dev = { + .platform_data = &autcpu12_nvram_pdata, + }, +}; + +static void __init autcpu12_nvram_init(void) +{ + void __iomem *nvram; + unsigned int save[2]; + resource_size_t nvram_size = SZ_128K; + + /* + * Check for 32K/128K + * Read ofs 0K + * Read ofs 64K + * Write complement to ofs 64K + * Read and check result on ofs 0K + * Restore contents + */ + nvram = ioremap(autcpu12_nvram_resource[0].start, SZ_128K); + if (nvram) { + save[0] = readl(nvram + 0); + save[1] = readl(nvram + SZ_64K); + writel(~save[0], nvram + SZ_64K); + if (readl(nvram + 0) != save[0]) { + writel(save[0], nvram + 0); + nvram_size = SZ_32K; + } else + writel(save[1], nvram + SZ_64K); + iounmap(nvram); + + autcpu12_nvram_resource[0].end = + autcpu12_nvram_resource[0].start + nvram_size - 1; + platform_device_register(&autcpu12_nvram_pdev); + } else + pr_err("Failed to remap NVRAM resource\n"); +} + static void __init autcpu12_init(void) { + clps711x_devices_init(); + platform_device_register(&autcpu12_flash_pdev); platform_device_register_simple("video-clps711x", 0, NULL, 0); platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource, ARRAY_SIZE(autcpu12_cs8900_resource)); platform_device_register(&autcpu12_mmgpio_pdev); - platform_device_register(&autcpu12_nvram_pdev); + autcpu12_nvram_init(); } static void __init autcpu12_init_late(void) { + gpio_request_array(autcpu12_gpios, ARRAY_SIZE(autcpu12_gpios)); + if (IS_ENABLED(MTD_NAND_GPIO) && IS_ENABLED(GPIO_GENERIC_PLATFORM)) { /* We are need both drivers to handle NAND */ platform_device_register(&autcpu12_nand_pdev); @@ -169,6 +271,7 @@ MACHINE_START(AUTCPU12, "autronix autcpu12") .atag_offset = 0x20000, .nr_irqs = CLPS711X_NR_IRQS, .map_io = clps711x_map_io, + .init_early = clps711x_init_early, .init_irq = clps711x_init_irq, .init_time = clps711x_timer_init, .init_machine = autcpu12_init, diff --git a/arch/arm/mach-clps711x/board-cdb89712.c b/arch/arm/mach-clps711x/board-cdb89712.c index baab7da33c9..a9e38c6bcfb 100644 --- a/arch/arm/mach-clps711x/board-cdb89712.c +++ b/arch/arm/mach-clps711x/board-cdb89712.c @@ -39,6 +39,7 @@ #include <asm/mach/map.h> #include "common.h" +#include "devices.h" #define CDB89712_CS8900_BASE (CS2_PHYS_BASE + 0x300) #define CDB89712_CS8900_IRQ (IRQ_EINT3) @@ -127,6 +128,7 @@ static struct platform_device cdb89712_sram_pdev __initdata = { static void __init cdb89712_init(void) { + clps711x_devices_init(); platform_device_register(&cdb89712_flash_pdev); platform_device_register(&cdb89712_bootrom_pdev); platform_device_register(&cdb89712_sram_pdev); @@ -139,6 +141,7 @@ MACHINE_START(CDB89712, "Cirrus-CDB89712") .atag_offset = 0x100, .nr_irqs = CLPS711X_NR_IRQS, .map_io = clps711x_map_io, + .init_early = clps711x_init_early, .init_irq = clps711x_init_irq, .init_time = clps711x_timer_init, .init_machine = cdb89712_init, diff --git a/arch/arm/mach-clps711x/board-clep7312.c b/arch/arm/mach-clps711x/board-clep7312.c index 014aa3c19a0..b4764246d0f 100644 --- a/arch/arm/mach-clps711x/board-clep7312.c +++ b/arch/arm/mach-clps711x/board-clep7312.c @@ -39,6 +39,7 @@ MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312") .nr_irqs = CLPS711X_NR_IRQS, .fixup = fixup_clep7312, .map_io = clps711x_map_io, + .init_early = clps711x_init_early, .init_irq = clps711x_init_irq, .init_time = clps711x_timer_init, .handle_irq = clps711x_handle_irq, diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c index 5f928e9ed2e..9dfb990f080 100644 --- a/arch/arm/mach-clps711x/board-edb7211.c +++ b/arch/arm/mach-clps711x/board-edb7211.c @@ -12,6 +12,7 @@ #include <linux/delay.h> #include <linux/memblock.h> #include <linux/types.h> +#include <linux/i2c-gpio.h> #include <linux/interrupt.h> #include <linux/backlight.h> #include <linux/platform_device.h> @@ -29,6 +30,7 @@ #include <mach/hardware.h> #include "common.h" +#include "devices.h" #define VIDEORAM_SIZE SZ_128K @@ -36,11 +38,24 @@ #define EDB7211_LCDEN CLPS711X_GPIO(3, 2) #define EDB7211_LCDBL CLPS711X_GPIO(3, 3) +#define EDB7211_I2C_SDA CLPS711X_GPIO(3, 4) +#define EDB7211_I2C_SCL CLPS711X_GPIO(3, 5) + #define EDB7211_FLASH0_BASE (CS0_PHYS_BASE) #define EDB7211_FLASH1_BASE (CS1_PHYS_BASE) + #define EDB7211_CS8900_BASE (CS2_PHYS_BASE + 0x300) #define EDB7211_CS8900_IRQ (IRQ_EINT3) +/* The extra 8 lines of the keyboard matrix */ +#define EDB7211_EXTKBD_BASE (CS3_PHYS_BASE) + +static struct i2c_gpio_platform_data edb7211_i2c_pdata __initdata = { + .sda_pin = EDB7211_I2C_SDA, + .scl_pin = EDB7211_I2C_SCL, + .scl_is_output_only = 1, +}; + static struct resource edb7211_cs8900_resource[] __initdata = { DEFINE_RES_MEM(EDB7211_CS8900_BASE, SZ_1K), DEFINE_RES_IRQ(EDB7211_CS8900_IRQ), @@ -94,13 +109,14 @@ static struct plat_lcd_data edb7211_lcd_power_pdata = { static void edb7211_lcd_backlight_set_intensity(int intensity) { - gpio_set_value(EDB7211_LCDBL, intensity); + gpio_set_value(EDB7211_LCDBL, !!intensity); + clps_writel((clps_readl(PMPCON) & 0xf0ff) | (intensity << 8), PMPCON); } static struct generic_bl_info edb7211_lcd_backlight_pdata = { .name = "lcd-backlight.0", .default_intensity = 0x01, - .max_intensity = 0x01, + .max_intensity = 0x0f, .set_bl_intensity = edb7211_lcd_backlight_set_intensity, }; @@ -112,8 +128,8 @@ static struct gpio edb7211_gpios[] __initconst = { static struct map_desc edb7211_io_desc[] __initdata = { { /* Memory-mapped extra keyboard row */ - .virtual = IO_ADDRESS(EP7211_PHYS_EXTKBD), - .pfn = __phys_to_pfn(EP7211_PHYS_EXTKBD), + .virtual = IO_ADDRESS(EDB7211_EXTKBD_BASE), + .pfn = __phys_to_pfn(EDB7211_EXTKBD_BASE), .length = SZ_1M, .type = MT_DEVICE, }, @@ -151,6 +167,11 @@ fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi) static void __init edb7211_init(void) { + clps711x_devices_init(); +} + +static void __init edb7211_init_late(void) +{ gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios)); platform_device_register(&edb7211_flash_pdev); @@ -163,6 +184,9 @@ static void __init edb7211_init(void) platform_device_register_simple("video-clps711x", 0, NULL, 0); platform_device_register_simple("cs89x0", 0, edb7211_cs8900_resource, ARRAY_SIZE(edb7211_cs8900_resource)); + platform_device_register_data(&platform_bus, "i2c-gpio", 0, + &edb7211_i2c_pdata, + sizeof(edb7211_i2c_pdata)); } MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)") @@ -172,9 +196,11 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)") .fixup = fixup_edb7211, .reserve = edb7211_reserve, .map_io = edb7211_map_io, + .init_early = clps711x_init_early, .init_irq = clps711x_init_irq, .init_time = clps711x_timer_init, .init_machine = edb7211_init, + .init_late = edb7211_init_late, .handle_irq = clps711x_handle_irq, .restart = clps711x_restart, MACHINE_END diff --git a/arch/arm/mach-clps711x/board-fortunet.c b/arch/arm/mach-clps711x/board-fortunet.c index c5675efc8c6..b1561e3d7c5 100644 --- a/arch/arm/mach-clps711x/board-fortunet.c +++ b/arch/arm/mach-clps711x/board-fortunet.c @@ -77,6 +77,7 @@ MACHINE_START(FORTUNET, "ARM-FortuNet") .nr_irqs = CLPS711X_NR_IRQS, .fixup = fortunet_fixup, .map_io = clps711x_map_io, + .init_early = clps711x_init_early, .init_irq = clps711x_init_irq, .init_time = clps711x_timer_init, .handle_irq = clps711x_handle_irq, diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c index 8d3ee677113..dd81b06f68f 100644 --- a/arch/arm/mach-clps711x/board-p720t.c +++ b/arch/arm/mach-clps711x/board-p720t.c @@ -23,10 +23,12 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/io.h> +#include <linux/gpio.h> #include <linux/slab.h> #include <linux/leds.h> #include <linux/sizes.h> #include <linux/backlight.h> +#include <linux/basic_mmio_gpio.h> #include <linux/platform_device.h> #include <linux/mtd/partitions.h> #include <linux/mtd/nand-gpio.h> @@ -38,11 +40,11 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <mach/syspld.h> #include <video/platform_lcd.h> #include "common.h" +#include "devices.h" #define P720T_USERLED CLPS711X_GPIO(3, 0) #define P720T_NAND_CLE CLPS711X_GPIO(4, 0) @@ -51,6 +53,178 @@ #define P720T_NAND_BASE (CLPS711X_SDRAM1_BASE) +#define P720T_MMGPIO_BASE (CLPS711X_NR_GPIO) + +#define SYSPLD_PHYS_BASE IOMEM(CS1_PHYS_BASE) + +#define PLD_INT (SYSPLD_PHYS_BASE + 0x000000) +#define PLD_INT_MMGPIO_BASE (P720T_MMGPIO_BASE + 0) +#define PLD_INT_PENIRQ (PLD_INT_MMGPIO_BASE + 5) +#define PLD_INT_UCB_IRQ (PLD_INT_MMGPIO_BASE + 1) +#define PLD_INT_KBD_ATN (PLD_INT_MMGPIO_BASE + 0) /* EINT1 */ + +#define PLD_PWR (SYSPLD_PHYS_BASE + 0x000004) +#define PLD_PWR_MMGPIO_BASE (P720T_MMGPIO_BASE + 8) +#define PLD_PWR_EXT (PLD_PWR_MMGPIO_BASE + 5) +#define PLD_PWR_MODE (PLD_PWR_MMGPIO_BASE + 4) /* 1 = PWM, 0 = PFM */ +#define PLD_S4_ON (PLD_PWR_MMGPIO_BASE + 3) /* LCD bias voltage enable */ +#define PLD_S3_ON (PLD_PWR_MMGPIO_BASE + 2) /* LCD backlight enable */ +#define PLD_S2_ON (PLD_PWR_MMGPIO_BASE + 1) /* LCD 3V3 supply enable */ +#define PLD_S1_ON (PLD_PWR_MMGPIO_BASE + 0) /* LCD 3V supply enable */ + +#define PLD_KBD (SYSPLD_PHYS_BASE + 0x000008) +#define PLD_KBD_MMGPIO_BASE (P720T_MMGPIO_BASE + 16) +#define PLD_KBD_WAKE (PLD_KBD_MMGPIO_BASE + 1) +#define PLD_KBD_EN (PLD_KBD_MMGPIO_BASE + 0) + +#define PLD_SPI (SYSPLD_PHYS_BASE + 0x00000c) +#define PLD_SPI_MMGPIO_BASE (P720T_MMGPIO_BASE + 24) +#define PLD_SPI_EN (PLD_SPI_MMGPIO_BASE + 0) + +#define PLD_IO (SYSPLD_PHYS_BASE + 0x000010) +#define PLD_IO_MMGPIO_BASE (P720T_MMGPIO_BASE + 32) +#define PLD_IO_BOOTSEL (PLD_IO_MMGPIO_BASE + 6) /* Boot sel switch */ +#define PLD_IO_USER (PLD_IO_MMGPIO_BASE + 5) /* User defined switch */ +#define PLD_IO_LED3 (PLD_IO_MMGPIO_BASE + 4) +#define PLD_IO_LED2 (PLD_IO_MMGPIO_BASE + 3) +#define PLD_IO_LED1 (PLD_IO_MMGPIO_BASE + 2) +#define PLD_IO_LED0 (PLD_IO_MMGPIO_BASE + 1) +#define PLD_IO_LEDEN (PLD_IO_MMGPIO_BASE + 0) + +#define PLD_IRDA (SYSPLD_PHYS_BASE + 0x000014) +#define PLD_IRDA_MMGPIO_BASE (P720T_MMGPIO_BASE + 40) +#define PLD_IRDA_EN (PLD_IRDA_MMGPIO_BASE + 0) + +#define PLD_COM2 (SYSPLD_PHYS_BASE + 0x000018) +#define PLD_COM2_MMGPIO_BASE (P720T_MMGPIO_BASE + 48) +#define PLD_COM2_EN (PLD_COM2_MMGPIO_BASE + 0) + +#define PLD_COM1 (SYSPLD_PHYS_BASE + 0x00001c) +#define PLD_COM1_MMGPIO_BASE (P720T_MMGPIO_BASE + 56) +#define PLD_COM1_EN (PLD_COM1_MMGPIO_BASE + 0) + +#define PLD_AUD (SYSPLD_PHYS_BASE + 0x000020) +#define PLD_AUD_MMGPIO_BASE (P720T_MMGPIO_BASE + 64) +#define PLD_AUD_DIV1 (PLD_AUD_MMGPIO_BASE + 6) +#define PLD_AUD_DIV0 (PLD_AUD_MMGPIO_BASE + 5) +#define PLD_AUD_CLK_SEL1 (PLD_AUD_MMGPIO_BASE + 4) +#define PLD_AUD_CLK_SEL0 (PLD_AUD_MMGPIO_BASE + 3) +#define PLD_AUD_MIC_PWR (PLD_AUD_MMGPIO_BASE + 2) +#define PLD_AUD_MIC_GAIN (PLD_AUD_MMGPIO_BASE + 1) +#define PLD_AUD_CODEC_EN (PLD_AUD_MMGPIO_BASE + 0) + +#define PLD_CF (SYSPLD_PHYS_BASE + 0x000024) +#define PLD_CF_MMGPIO_BASE (P720T_MMGPIO_BASE + 72) +#define PLD_CF2_SLEEP (PLD_CF_MMGPIO_BASE + 5) +#define PLD_CF1_SLEEP (PLD_CF_MMGPIO_BASE + 4) +#define PLD_CF2_nPDREQ (PLD_CF_MMGPIO_BASE + 3) +#define PLD_CF1_nPDREQ (PLD_CF_MMGPIO_BASE + 2) +#define PLD_CF2_nIRQ (PLD_CF_MMGPIO_BASE + 1) +#define PLD_CF1_nIRQ (PLD_CF_MMGPIO_BASE + 0) + +#define PLD_SDC (SYSPLD_PHYS_BASE + 0x000028) +#define PLD_SDC_MMGPIO_BASE (P720T_MMGPIO_BASE + 80) +#define PLD_SDC_INT_EN (PLD_SDC_MMGPIO_BASE + 2) +#define PLD_SDC_WP (PLD_SDC_MMGPIO_BASE + 1) +#define PLD_SDC_CD (PLD_SDC_MMGPIO_BASE + 0) + +#define PLD_CODEC (SYSPLD_PHYS_BASE + 0x400000) +#define PLD_CODEC_MMGPIO_BASE (P720T_MMGPIO_BASE + 88) +#define PLD_CODEC_IRQ3 (PLD_CODEC_MMGPIO_BASE + 4) +#define PLD_CODEC_IRQ2 (PLD_CODEC_MMGPIO_BASE + 3) +#define PLD_CODEC_IRQ1 (PLD_CODEC_MMGPIO_BASE + 2) +#define PLD_CODEC_EN (PLD_CODEC_MMGPIO_BASE + 0) + +#define PLD_BRITE (SYSPLD_PHYS_BASE + 0x400004) +#define PLD_BRITE_MMGPIO_BASE (P720T_MMGPIO_BASE + 96) +#define PLD_BRITE_UP (PLD_BRITE_MMGPIO_BASE + 1) +#define PLD_BRITE_DN (PLD_BRITE_MMGPIO_BASE + 0) + +#define PLD_LCDEN (SYSPLD_PHYS_BASE + 0x400008) +#define PLD_LCDEN_MMGPIO_BASE (P720T_MMGPIO_BASE + 104) +#define PLD_LCDEN_EN (PLD_LCDEN_MMGPIO_BASE + 0) + +#define PLD_TCH (SYSPLD_PHYS_BASE + 0x400010) +#define PLD_TCH_MMGPIO_BASE (P720T_MMGPIO_BASE + 112) +#define PLD_TCH_PENIRQ (PLD_TCH_MMGPIO_BASE + 1) +#define PLD_TCH_EN (PLD_TCH_MMGPIO_BASE + 0) + +#define PLD_GPIO (SYSPLD_PHYS_BASE + 0x400014) +#define PLD_GPIO_MMGPIO_BASE (P720T_MMGPIO_BASE + 120) +#define PLD_GPIO2 (PLD_GPIO_MMGPIO_BASE + 2) +#define PLD_GPIO1 (PLD_GPIO_MMGPIO_BASE + 1) +#define PLD_GPIO0 (PLD_GPIO_MMGPIO_BASE + 0) + +static struct gpio p720t_gpios[] __initconst = { + { PLD_S1_ON, GPIOF_OUT_INIT_LOW, "PLD_S1_ON" }, + { PLD_S2_ON, GPIOF_OUT_INIT_LOW, "PLD_S2_ON" }, + { PLD_S3_ON, GPIOF_OUT_INIT_LOW, "PLD_S3_ON" }, + { PLD_S4_ON, GPIOF_OUT_INIT_LOW, "PLD_S4_ON" }, + { PLD_KBD_EN, GPIOF_OUT_INIT_LOW, "PLD_KBD_EN" }, + { PLD_SPI_EN, GPIOF_OUT_INIT_LOW, "PLD_SPI_EN" }, + { PLD_IO_USER, GPIOF_OUT_INIT_LOW, "PLD_IO_USER" }, + { PLD_IO_LED0, GPIOF_OUT_INIT_LOW, "PLD_IO_LED0" }, + { PLD_IO_LED1, GPIOF_OUT_INIT_LOW, "PLD_IO_LED1" }, + { PLD_IO_LED2, GPIOF_OUT_INIT_LOW, "PLD_IO_LED2" }, + { PLD_IO_LED3, GPIOF_OUT_INIT_LOW, "PLD_IO_LED3" }, + { PLD_IO_LEDEN, GPIOF_OUT_INIT_LOW, "PLD_IO_LEDEN" }, + { PLD_IRDA_EN, GPIOF_OUT_INIT_LOW, "PLD_IRDA_EN" }, + { PLD_COM1_EN, GPIOF_OUT_INIT_HIGH, "PLD_COM1_EN" }, + { PLD_COM2_EN, GPIOF_OUT_INIT_HIGH, "PLD_COM2_EN" }, + { PLD_CODEC_EN, GPIOF_OUT_INIT_LOW, "PLD_CODEC_EN" }, + { PLD_LCDEN_EN, GPIOF_OUT_INIT_LOW, "PLD_LCDEN_EN" }, + { PLD_TCH_EN, GPIOF_OUT_INIT_LOW, "PLD_TCH_EN" }, + { P720T_USERLED,GPIOF_OUT_INIT_LOW, "USER_LED" }, +}; + +static struct resource p720t_mmgpio_resource[] __initdata = { + DEFINE_RES_MEM_NAMED(0, 4, "dat"), +}; + +static struct bgpio_pdata p720t_mmgpio_pdata = { + .ngpio = 8, +}; + +static struct platform_device p720t_mmgpio __initdata = { + .name = "basic-mmio-gpio", + .id = -1, + .resource = p720t_mmgpio_resource, + .num_resources = ARRAY_SIZE(p720t_mmgpio_resource), + .dev = { + .platform_data = &p720t_mmgpio_pdata, + }, +}; + +static void __init p720t_mmgpio_init(void __iomem *addrbase, int gpiobase) +{ + p720t_mmgpio_resource[0].start = (unsigned long)addrbase; + p720t_mmgpio_pdata.base = gpiobase; + + platform_device_register(&p720t_mmgpio); +} + +static struct { + void __iomem *addrbase; + int gpiobase; +} mmgpios[] __initconst = { + { PLD_INT, PLD_INT_MMGPIO_BASE }, + { PLD_PWR, PLD_PWR_MMGPIO_BASE }, + { PLD_KBD, PLD_KBD_MMGPIO_BASE }, + { PLD_SPI, PLD_SPI_MMGPIO_BASE }, + { PLD_IO, PLD_IO_MMGPIO_BASE }, + { PLD_IRDA, PLD_IRDA_MMGPIO_BASE }, + { PLD_COM2, PLD_COM2_MMGPIO_BASE }, + { PLD_COM1, PLD_COM1_MMGPIO_BASE }, + { PLD_AUD, PLD_AUD_MMGPIO_BASE }, + { PLD_CF, PLD_CF_MMGPIO_BASE }, + { PLD_SDC, PLD_SDC_MMGPIO_BASE }, + { PLD_CODEC, PLD_CODEC_MMGPIO_BASE }, + { PLD_BRITE, PLD_BRITE_MMGPIO_BASE }, + { PLD_LCDEN, PLD_LCDEN_MMGPIO_BASE }, + { PLD_TCH, PLD_TCH_MMGPIO_BASE }, + { PLD_GPIO, PLD_GPIO_MMGPIO_BASE }, +}; + static struct resource p720t_nand_resource[] __initdata = { DEFINE_RES_MEM(P720T_NAND_BASE, SZ_4), }; @@ -92,11 +266,15 @@ static struct platform_device p720t_nand_pdev __initdata = { static void p720t_lcd_power_set(struct plat_lcd_data *pd, unsigned int power) { if (power) { - PLD_LCDEN = PLD_LCDEN_EN; - PLD_PWR |= PLD_S4_ON | PLD_S2_ON | PLD_S1_ON; + gpio_set_value(PLD_LCDEN_EN, 1); + gpio_set_value(PLD_S1_ON, 1); + gpio_set_value(PLD_S2_ON, 1); + gpio_set_value(PLD_S4_ON, 1); } else { - PLD_PWR &= ~(PLD_S4_ON | PLD_S2_ON | PLD_S1_ON); - PLD_LCDEN = 0; + gpio_set_value(PLD_S1_ON, 0); + gpio_set_value(PLD_S2_ON, 0); + gpio_set_value(PLD_S4_ON, 0); + gpio_set_value(PLD_LCDEN_EN, 0); } } @@ -106,10 +284,7 @@ static struct plat_lcd_data p720t_lcd_power_pdata = { static void p720t_lcd_backlight_set_intensity(int intensity) { - if (intensity) - PLD_PWR |= PLD_S3_ON; - else - PLD_PWR = 0; + gpio_set_value(PLD_S3_ON, intensity); } static struct generic_bl_info p720t_lcd_backlight_pdata = { @@ -119,19 +294,6 @@ static struct generic_bl_info p720t_lcd_backlight_pdata = { .set_bl_intensity = p720t_lcd_backlight_set_intensity, }; -/* - * Map the P720T system PLD. It occupies two address spaces: - * 0x10000000 and 0x10400000. We map both regions as one. - */ -static struct map_desc p720t_io_desc[] __initdata = { - { - .virtual = SYSPLD_VIRT_BASE, - .pfn = __phys_to_pfn(SYSPLD_PHYS_BASE), - .length = SZ_8M, - .type = MT_DEVICE, - }, -}; - static void __init fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi) { @@ -157,33 +319,6 @@ fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi) } } -static void __init p720t_map_io(void) -{ - clps711x_map_io(); - iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc)); -} - -static void __init p720t_init_early(void) -{ - /* - * Power down as much as possible in case we don't - * have the drivers loaded. - */ - PLD_LCDEN = 0; - PLD_PWR &= ~(PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON); - - PLD_KBD = 0; - PLD_IO = 0; - PLD_IRDA = 0; - PLD_CODEC = 0; - PLD_TCH = 0; - PLD_SPI = 0; - if (!IS_ENABLED(CONFIG_DEBUG_LL)) { - PLD_COM2 = 0; - PLD_COM1 = 0; - } -} - static struct gpio_led p720t_gpio_leds[] = { { .name = "User LED", @@ -199,7 +334,20 @@ static struct gpio_led_platform_data p720t_gpio_led_pdata __initdata = { static void __init p720t_init(void) { + int i; + + clps711x_devices_init(); + + for (i = 0; i < ARRAY_SIZE(mmgpios); i++) + p720t_mmgpio_init(mmgpios[i].addrbase, mmgpios[i].gpiobase); + platform_device_register(&p720t_nand_pdev); +} + +static void __init p720t_init_late(void) +{ + WARN_ON(gpio_request_array(p720t_gpios, ARRAY_SIZE(p720t_gpios))); + platform_device_register_data(&platform_bus, "platform-lcd", 0, &p720t_lcd_power_pdata, sizeof(p720t_lcd_power_pdata)); @@ -207,10 +355,6 @@ static void __init p720t_init(void) &p720t_lcd_backlight_pdata, sizeof(p720t_lcd_backlight_pdata)); platform_device_register_simple("video-clps711x", 0, NULL, 0); -} - -static void __init p720t_init_late(void) -{ platform_device_register_data(&platform_bus, "leds-gpio", 0, &p720t_gpio_led_pdata, sizeof(p720t_gpio_led_pdata)); @@ -221,8 +365,8 @@ MACHINE_START(P720T, "ARM-Prospector720T") .atag_offset = 0x100, .nr_irqs = CLPS711X_NR_IRQS, .fixup = fixup_p720t, - .map_io = p720t_map_io, - .init_early = p720t_init_early, + .map_io = clps711x_map_io, + .init_early = clps711x_init_early, .init_irq = clps711x_init_irq, .init_time = clps711x_timer_init, .init_machine = p720t_init, diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c index 20ff50f3ccf..f6d1746366d 100644 --- a/arch/arm/mach-clps711x/common.c +++ b/arch/arm/mach-clps711x/common.c @@ -27,12 +27,14 @@ #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/clockchips.h> +#include <linux/clocksource.h> #include <linux/clk-provider.h> #include <asm/exception.h> #include <asm/mach/irq.h> #include <asm/mach/map.h> #include <asm/mach/time.h> +#include <asm/sched_clock.h> #include <asm/system_misc.h> #include <mach/hardware.h> @@ -213,7 +215,7 @@ void __init clps711x_init_irq(void) } } -inline u32 fls16(u32 x) +static inline u32 fls16(u32 x) { u32 r = 15; @@ -237,27 +239,52 @@ inline u32 fls16(u32 x) asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs) { - u32 irqstat; - void __iomem *base = CLPS711X_VIRT_BASE; - - irqstat = readl_relaxed(base + INTSR1) & readl_relaxed(base + INTMR1); - if (irqstat) { - handle_IRQ(fls16(irqstat), regs); - return; - } + do { + u32 irqstat; + void __iomem *base = CLPS711X_VIRT_BASE; + + irqstat = readw_relaxed(base + INTSR1) & + readw_relaxed(base + INTMR1); + if (irqstat) + handle_IRQ(fls16(irqstat), regs); + + irqstat = readw_relaxed(base + INTSR2) & + readw_relaxed(base + INTMR2); + if (irqstat) { + handle_IRQ(fls16(irqstat) + 16, regs); + continue; + } + + break; + } while (1); +} - irqstat = readl_relaxed(base + INTSR2) & readl_relaxed(base + INTMR2); - if (likely(irqstat)) - handle_IRQ(fls16(irqstat) + 16, regs); +static u32 notrace clps711x_sched_clock_read(void) +{ + return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D); } static void clps711x_clockevent_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { + disable_irq(IRQ_TC2OI); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + enable_irq(IRQ_TC2OI); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* Not supported */ + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_RESUME: + /* Left event sources disabled, no more interrupts appear */ + break; + } } static struct clock_event_device clockevent_clps711x = { - .name = "CLPS711x Clockevents", + .name = "clps711x-clockevent", .rating = 300, .features = CLOCK_EVT_FEAT_PERIODIC, .set_mode = clps711x_clockevent_set_mode, @@ -271,8 +298,8 @@ static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id) } static struct irqaction clps711x_timer_irq = { - .name = "CLPS711x Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .name = "clps711x-timer", + .flags = IRQF_TIMER | IRQF_IRQPOLL, .handler = clps711x_timer_interrupt, }; @@ -301,6 +328,7 @@ void __init clps711x_timer_init(void) cpu = ext; bus = cpu; spi = 135400; + pll = 0; } else { cpu = pll; if (cpu >= 36864000) @@ -319,9 +347,9 @@ void __init clps711x_timer_init(void) else timh = 541440; } else - timh = cpu / 144; + timh = DIV_ROUND_CLOSEST(cpu, 144); - timl = timh / 256; + timl = DIV_ROUND_CLOSEST(timh, 256); /* All clocks are fixed */ add_fixed_clk(clk_pll, "pll", pll); @@ -334,13 +362,24 @@ void __init clps711x_timer_init(void) pr_info("CPU frequency set at %i Hz.\n", cpu); + /* Start Timer1 in free running mode (Low frequency) */ + tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M); + clps_writel(tmp, SYSCON1); + + setup_sched_clock(clps711x_sched_clock_read, 16, timl); + + clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D, + "clps711x_clocksource", timl, 300, 16, + clocksource_mmio_readw_down); + + /* Set Timer2 prescaler */ clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D); - tmp = clps_readl(SYSCON1); - tmp |= SYSCON1_TC2S | SYSCON1_TC2M; + /* Start Timer2 in prescale mode (High frequency)*/ + tmp = clps_readl(SYSCON1) | SYSCON1_TC2M | SYSCON1_TC2S; clps_writel(tmp, SYSCON1); - clockevents_config_and_register(&clockevent_clps711x, timh, 1, 0xffff); + clockevents_config_and_register(&clockevent_clps711x, timh, 0, 0); setup_irq(IRQ_TC2OI, &clps711x_timer_irq); } @@ -353,15 +392,11 @@ void clps711x_restart(char mode, const char *cmd) static void clps711x_idle(void) { clps_writel(1, HALT); - __asm__ __volatile__( - "mov r0, r0\n\ - mov r0, r0"); + asm("mov r0, r0"); + asm("mov r0, r0"); } -static int __init clps711x_idle_init(void) +void __init clps711x_init_early(void) { arm_pm_idle = clps711x_idle; - return 0; } - -arch_initcall(clps711x_idle_init); diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h index f84a7292c70..2a22f4c6cc7 100644 --- a/arch/arm/mach-clps711x/common.h +++ b/arch/arm/mach-clps711x/common.h @@ -13,3 +13,4 @@ extern void clps711x_init_irq(void); extern void clps711x_timer_init(void); extern void clps711x_handle_irq(struct pt_regs *regs); extern void clps711x_restart(char mode, const char *cmd); +extern void clps711x_init_early(void); diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c new file mode 100644 index 00000000000..856b81cf2f8 --- /dev/null +++ b/arch/arm/mach-clps711x/devices.c @@ -0,0 +1,68 @@ +/* + * CLPS711X common devices definitions + * + * Author: Alexander Shiyan <shc_work@mail.ru>, 2013 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/platform_device.h> +#include <linux/sizes.h> + +#include <mach/hardware.h> + +static const phys_addr_t clps711x_gpios[][2] __initconst = { + { PADR, PADDR }, + { PBDR, PBDDR }, + { PCDR, PCDDR }, + { PDDR, PDDDR }, + { PEDR, PEDDR }, +}; + +static void __init clps711x_add_gpio(void) +{ + unsigned i; + struct resource gpio_res[2]; + + memset(gpio_res, 0, sizeof(gpio_res)); + + gpio_res[0].flags = IORESOURCE_MEM; + gpio_res[1].flags = IORESOURCE_MEM; + + for (i = 0; i < ARRAY_SIZE(clps711x_gpios); i++) { + gpio_res[0].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][0]; + gpio_res[0].end = gpio_res[0].start; + gpio_res[1].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][1]; + gpio_res[1].end = gpio_res[1].start; + + platform_device_register_simple("clps711x-gpio", i, + gpio_res, ARRAY_SIZE(gpio_res)); + } +} + +const struct resource clps711x_syscon_res[] __initconst = { + /* SYSCON1, SYSFLG1 */ + DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON1, SZ_128), + /* SYSCON2, SYSFLG2 */ + DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON2, SZ_128), + /* SYSCON3 */ + DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON3, SZ_64), +}; + +static void __init clps711x_add_syscon(void) +{ + unsigned i; + + for (i = 0; i < ARRAY_SIZE(clps711x_syscon_res); i++) + platform_device_register_simple("clps711x-syscon", i + 1, + &clps711x_syscon_res[i], 1); +} + +void __init clps711x_devices_init(void) +{ + clps711x_add_gpio(); + clps711x_add_syscon(); +} diff --git a/arch/arm/mach-clps711x/devices.h b/arch/arm/mach-clps711x/devices.h new file mode 100644 index 00000000000..a5efc1744b8 --- /dev/null +++ b/arch/arm/mach-clps711x/devices.h @@ -0,0 +1,12 @@ +/* + * CLPS711X common devices definitions + * + * Copyright (C) 2013 Alexander Shiyan <shc_work@mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +void clps711x_devices_init(void); diff --git a/arch/arm/mach-clps711x/include/mach/autcpu12.h b/arch/arm/mach-clps711x/include/mach/autcpu12.h deleted file mode 100644 index 0452f5f3f03..00000000000 --- a/arch/arm/mach-clps711x/include/mach/autcpu12.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * AUTCPU12 specific defines - * - * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_AUTCPU12_H -#define __ASM_ARCH_AUTCPU12_H - -/* - * The flash bank is wired to chip select 0 - */ -#define AUTCPU12_PHYS_FLASH CS0_PHYS_BASE /* physical */ - -/* offset for device specific information structure */ -#define AUTCPU12_LCDINFO_OFFS (0x00010000) - -/* Videomemory in the internal SRAM (CS 6) */ -#define AUTCPU12_PHYS_VIDEO CS6_PHYS_BASE - -/* -* All special IO's are tied to CS1 -*/ -#define AUTCPU12_PHYS_CHAR_LCD CS1_PHYS_BASE +0x00000000 /* physical */ - -#define AUTCPU12_PHYS_NVRAM CS1_PHYS_BASE +0x02000000 /* physical */ - -#define AUTCPU12_PHYS_CSAUX1 CS1_PHYS_BASE +0x04000000 /* physical */ - -#define AUTCPU12_PHYS_CAN CS1_PHYS_BASE +0x08000000 /* physical */ - -#define AUTCPU12_PHYS_TOUCH CS1_PHYS_BASE +0x0A000000 /* physical */ - -#define AUTCPU12_PHYS_IO CS1_PHYS_BASE +0x0C000000 /* physical */ - -#define AUTCPU12_PHYS_LPT CS1_PHYS_BASE +0x0E000000 /* physical */ - -/* -* defines for lcd contrast -*/ -#define AUTCPU12_DPOT_PORT_OFFSET PEDR -#define AUTCPU12_DPOT_CS (1<<0) -#define AUTCPU12_DPOT_CLK (1<<1) -#define AUTCPU12_DPOT_UD (1<<2) - -#endif diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h index 01d1b955971..0286f4bf994 100644 --- a/arch/arm/mach-clps711x/include/mach/clps711x.h +++ b/arch/arm/mach-clps711x/include/mach/clps711x.h @@ -21,6 +21,8 @@ #ifndef __MACH_CLPS711X_H #define __MACH_CLPS711X_H +#include <linux/mfd/syscon/clps711x.h> + #define CLPS711X_PHYS_BASE (0x80000000) #define PADR (0x0000) @@ -96,83 +98,9 @@ #define RANDID2 (0x2708) #define RANDID3 (0x270c) -/* common bits: SYSCON1 / SYSCON2 */ -#define SYSCON_UARTEN (1 << 8) - -#define SYSCON1_KBDSCAN(x) ((x) & 15) -#define SYSCON1_KBDSCANMASK (15) -#define SYSCON1_TC1M (1 << 4) -#define SYSCON1_TC1S (1 << 5) -#define SYSCON1_TC2M (1 << 6) -#define SYSCON1_TC2S (1 << 7) -#define SYSCON1_UART1EN SYSCON_UARTEN -#define SYSCON1_BZTOG (1 << 9) -#define SYSCON1_BZMOD (1 << 10) -#define SYSCON1_DBGEN (1 << 11) -#define SYSCON1_LCDEN (1 << 12) -#define SYSCON1_CDENTX (1 << 13) -#define SYSCON1_CDENRX (1 << 14) -#define SYSCON1_SIREN (1 << 15) -#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16) -#define SYSCON1_ADCKSEL_MASK (3 << 16) -#define SYSCON1_EXCKEN (1 << 18) -#define SYSCON1_WAKEDIS (1 << 19) -#define SYSCON1_IRTXM (1 << 20) - -/* common bits: SYSFLG1 / SYSFLG2 */ -#define SYSFLG_UBUSY (1 << 11) -#define SYSFLG_URXFE (1 << 22) -#define SYSFLG_UTXFF (1 << 23) - -#define SYSFLG1_MCDR (1 << 0) -#define SYSFLG1_DCDET (1 << 1) -#define SYSFLG1_WUDR (1 << 2) -#define SYSFLG1_WUON (1 << 3) -#define SYSFLG1_CTS (1 << 8) -#define SYSFLG1_DSR (1 << 9) -#define SYSFLG1_DCD (1 << 10) -#define SYSFLG1_UBUSY SYSFLG_UBUSY -#define SYSFLG1_NBFLG (1 << 12) -#define SYSFLG1_RSTFLG (1 << 13) -#define SYSFLG1_PFFLG (1 << 14) -#define SYSFLG1_CLDFLG (1 << 15) -#define SYSFLG1_URXFE SYSFLG_URXFE -#define SYSFLG1_UTXFF SYSFLG_UTXFF -#define SYSFLG1_CRXFE (1 << 24) -#define SYSFLG1_CTXFF (1 << 25) -#define SYSFLG1_SSIBUSY (1 << 26) -#define SYSFLG1_ID (1 << 29) -#define SYSFLG1_VERID(x) (((x) >> 30) & 3) -#define SYSFLG1_VERID_MASK (3 << 30) - -#define SYSFLG2_SSRXOF (1 << 0) -#define SYSFLG2_RESVAL (1 << 1) -#define SYSFLG2_RESFRM (1 << 2) -#define SYSFLG2_SS2RXFE (1 << 3) -#define SYSFLG2_SS2TXFF (1 << 4) -#define SYSFLG2_SS2TXUF (1 << 5) -#define SYSFLG2_CKMODE (1 << 6) -#define SYSFLG2_UBUSY SYSFLG_UBUSY -#define SYSFLG2_URXFE SYSFLG_URXFE -#define SYSFLG2_UTXFF SYSFLG_UTXFF - #define LCDCON_GSEN (1 << 30) #define LCDCON_GSMD (1 << 31) -#define SYSCON2_SERSEL (1 << 0) -#define SYSCON2_KBD6 (1 << 1) -#define SYSCON2_DRAMZ (1 << 2) -#define SYSCON2_KBWEN (1 << 3) -#define SYSCON2_SS2TXEN (1 << 4) -#define SYSCON2_PCCARD1 (1 << 5) -#define SYSCON2_PCCARD2 (1 << 6) -#define SYSCON2_SS2RXEN (1 << 7) -#define SYSCON2_UART2EN SYSCON_UARTEN -#define SYSCON2_SS2MAEN (1 << 9) -#define SYSCON2_OSTB (1 << 12) -#define SYSCON2_CLKENSL (1 << 13) -#define SYSCON2_BUZFREQ (1 << 14) - /* common bits: UARTDR1 / UARTDR2 */ #define UARTDR_FRMERR (1 << 8) #define UARTDR_PARERR (1 << 9) @@ -228,18 +156,6 @@ #define DAI64FS_MCLK256EN (1 << 3) #define DAI64FS_LOOPBACK (1 << 5) -#define SYSCON3_ADCCON (1 << 0) -#define SYSCON3_CLKCTL0 (1 << 1) -#define SYSCON3_CLKCTL1 (1 << 2) -#define SYSCON3_DAISEL (1 << 3) -#define SYSCON3_ADCCKNSEN (1 << 4) -#define SYSCON3_VERSN(x) (((x) >> 5) & 7) -#define SYSCON3_VERSN_MASK (7 << 5) -#define SYSCON3_FASTWAKE (1 << 8) -#define SYSCON3_DAIEN (1 << 9) -#define SYSCON3_128FS SYSCON3_DAIEN -#define SYSCON3_ENPD67 (1 << 10) - #define SDCONF_ACTIVE (1 << 10) #define SDCONF_CLKCTL (1 << 9) #define SDCONF_WIDTH_4 (0 << 7) diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h index 2f23dd5d73e..c5a8ea6839e 100644 --- a/arch/arm/mach-clps711x/include/mach/hardware.h +++ b/arch/arm/mach-clps711x/include/mach/hardware.h @@ -70,11 +70,4 @@ #define CLPS711X_SDRAM0_BASE (0xc0000000) #define CLPS711X_SDRAM1_BASE (0xd0000000) -#if defined (CONFIG_ARCH_EDB7211) - -/* The extra 8 lines of the keyboard matrix are wired to chip select 3 */ -#define EP7211_PHYS_EXTKBD CS3_PHYS_BASE - -#endif /* CONFIG_ARCH_EDB7211 */ - #endif diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h deleted file mode 100644 index fc0e028d940..00000000000 --- a/arch/arm/mach-clps711x/include/mach/memory.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * arch/arm/mach-clps711x/include/mach/memory.h - * - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* - * Physical DRAM offset. - */ -#define PLAT_PHYS_OFFSET UL(0xc0000000) - -/* - * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211 - * uses only one of the two banks (bank #1). However, even within - * bank #1, memory is discontiguous. - * - * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between - * them, so we use 24 for the node max shift to get 16MB node sizes. - */ - -#define SECTION_SIZE_BITS 24 -#define MAX_PHYSMEM_BITS 32 - -#endif - diff --git a/arch/arm/mach-clps711x/include/mach/syspld.h b/arch/arm/mach-clps711x/include/mach/syspld.h deleted file mode 100644 index 9a433155bf5..00000000000 --- a/arch/arm/mach-clps711x/include/mach/syspld.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * arch/arm/mach-clps711x/include/mach/syspld.h - * - * System Control PLD register definitions. - * - * Copyright (C) 2000 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_SYSPLD_H -#define __ASM_ARCH_SYSPLD_H - -#define SYSPLD_PHYS_BASE (0x10000000) -#define SYSPLD_VIRT_BASE IO_ADDRESS(SYSPLD_PHYS_BASE) - -#define SYSPLD_REG(type, off) (*(volatile type *)(SYSPLD_VIRT_BASE + (off))) - -#define PLD_INT SYSPLD_REG(u32, 0x000000) -#define PLD_INT_PENIRQ (1 << 5) -#define PLD_INT_UCB_IRQ (1 << 1) -#define PLD_INT_KBD_ATN (1 << 0) /* EINT1 */ - -#define PLD_PWR SYSPLD_REG(u32, 0x000004) -#define PLD_PWR_EXT (1 << 5) -#define PLD_PWR_MODE (1 << 4) /* 1 = PWM, 0 = PFM */ -#define PLD_S4_ON (1 << 3) /* LCD bias voltage enable */ -#define PLD_S3_ON (1 << 2) /* LCD backlight enable */ -#define PLD_S2_ON (1 << 1) /* LCD 3V3 supply enable */ -#define PLD_S1_ON (1 << 0) /* LCD 3V supply enable */ - -#define PLD_KBD SYSPLD_REG(u32, 0x000008) -#define PLD_KBD_WAKE (1 << 1) -#define PLD_KBD_EN (1 << 0) - -#define PLD_SPI SYSPLD_REG(u32, 0x00000c) -#define PLD_SPI_EN (1 << 0) - -#define PLD_IO SYSPLD_REG(u32, 0x000010) -#define PLD_IO_BOOTSEL (1 << 6) /* boot sel switch */ -#define PLD_IO_USER (1 << 5) /* user defined switch */ -#define PLD_IO_LED3 (1 << 4) -#define PLD_IO_LED2 (1 << 3) -#define PLD_IO_LED1 (1 << 2) -#define PLD_IO_LED0 (1 << 1) -#define PLD_IO_LEDEN (1 << 0) - -#define PLD_IRDA SYSPLD_REG(u32, 0x000014) -#define PLD_IRDA_EN (1 << 0) - -#define PLD_COM2 SYSPLD_REG(u32, 0x000018) -#define PLD_COM2_EN (1 << 0) - -#define PLD_COM1 SYSPLD_REG(u32, 0x00001c) -#define PLD_COM1_EN (1 << 0) - -#define PLD_AUD SYSPLD_REG(u32, 0x000020) -#define PLD_AUD_DIV1 (1 << 6) -#define PLD_AUD_DIV0 (1 << 5) -#define PLD_AUD_CLK_SEL1 (1 << 4) -#define PLD_AUD_CLK_SEL0 (1 << 3) -#define PLD_AUD_MIC_PWR (1 << 2) -#define PLD_AUD_MIC_GAIN (1 << 1) -#define PLD_AUD_CODEC_EN (1 << 0) - -#define PLD_CF SYSPLD_REG(u32, 0x000024) -#define PLD_CF2_SLEEP (1 << 5) -#define PLD_CF1_SLEEP (1 << 4) -#define PLD_CF2_nPDREQ (1 << 3) -#define PLD_CF1_nPDREQ (1 << 2) -#define PLD_CF2_nIRQ (1 << 1) -#define PLD_CF1_nIRQ (1 << 0) - -#define PLD_SDC SYSPLD_REG(u32, 0x000028) -#define PLD_SDC_INT_EN (1 << 2) -#define PLD_SDC_WP (1 << 1) -#define PLD_SDC_CD (1 << 0) - -#define PLD_FPGA SYSPLD_REG(u32, 0x00002c) - -#define PLD_CODEC SYSPLD_REG(u32, 0x400000) -#define PLD_CODEC_IRQ3 (1 << 4) -#define PLD_CODEC_IRQ2 (1 << 3) -#define PLD_CODEC_IRQ1 (1 << 2) -#define PLD_CODEC_EN (1 << 0) - -#define PLD_BRITE SYSPLD_REG(u32, 0x400004) -#define PLD_BRITE_UP (1 << 1) -#define PLD_BRITE_DN (1 << 0) - -#define PLD_LCDEN SYSPLD_REG(u32, 0x400008) -#define PLD_LCDEN_EN (1 << 0) - -#define PLD_ID SYSPLD_REG(u32, 0x40000c) - -#define PLD_TCH SYSPLD_REG(u32, 0x400010) -#define PLD_TCH_PENIRQ (1 << 1) -#define PLD_TCH_EN (1 << 0) - -#define PLD_GPIO SYSPLD_REG(u32, 0x400014) -#define PLD_GPIO2 (1 << 2) -#define PLD_GPIO1 (1 << 1) -#define PLD_GPIO0 (1 << 0) - -#endif diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index dd1ffccc75e..63997a1128e 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -5,7 +5,7 @@ # Common objects obj-y := time.o clock.o serial.o psc.o \ - dma.o usb.o common.o sram.o aemif.o + usb.o common.o sram.o aemif.o obj-$(CONFIG_DAVINCI_MUX) += mux.o diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c index ba798370fc9..78ea395d2ac 100644 --- a/arch/arm/mach-davinci/board-tnetv107x-evm.c +++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c @@ -26,12 +26,12 @@ #include <linux/input.h> #include <linux/input/matrix_keypad.h> #include <linux/spi/spi.h> +#include <linux/platform_data/edma.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> #include <mach/irqs.h> -#include <mach/edma.h> #include <mach/mux.h> #include <mach/cp_intc.h> #include <mach/tnetv107x.h> diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h index 1ab3df423da..a883043d082 100644 --- a/arch/arm/mach-davinci/davinci.h +++ b/arch/arm/mach-davinci/davinci.h @@ -23,9 +23,9 @@ #include <linux/platform_device.h> #include <linux/spi/spi.h> #include <linux/platform_data/davinci_asp.h> +#include <linux/platform_data/edma.h> #include <linux/platform_data/keyscan-davinci.h> #include <mach/hardware.h> -#include <mach/edma.h> #include <media/davinci/vpfe_capture.h> #include <media/davinci/vpif_types.h> @@ -77,32 +77,32 @@ void davinci_map_sysmod(void); #define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000 /* DM355 function declarations */ -void __init dm355_init(void); +void dm355_init(void); void dm355_init_spi0(unsigned chipselect_mask, const struct spi_board_info *info, unsigned len); -void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata); +void dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata); int dm355_init_video(struct vpfe_config *, struct vpbe_config *); /* DM365 function declarations */ -void __init dm365_init(void); -void __init dm365_init_asp(struct snd_platform_data *pdata); -void __init dm365_init_vc(struct snd_platform_data *pdata); -void __init dm365_init_ks(struct davinci_ks_platform_data *pdata); -void __init dm365_init_rtc(void); +void dm365_init(void); +void dm365_init_asp(struct snd_platform_data *pdata); +void dm365_init_vc(struct snd_platform_data *pdata); +void dm365_init_ks(struct davinci_ks_platform_data *pdata); +void dm365_init_rtc(void); void dm365_init_spi0(unsigned chipselect_mask, const struct spi_board_info *info, unsigned len); int dm365_init_video(struct vpfe_config *, struct vpbe_config *); /* DM644x function declarations */ -void __init dm644x_init(void); -void __init dm644x_init_asp(struct snd_platform_data *pdata); -int __init dm644x_init_video(struct vpfe_config *, struct vpbe_config *); +void dm644x_init(void); +void dm644x_init_asp(struct snd_platform_data *pdata); +int dm644x_init_video(struct vpfe_config *, struct vpbe_config *); /* DM646x function declarations */ -void __init dm646x_init(void); -void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); -void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); -int __init dm646x_init_edma(struct edma_rsv_info *rsv); +void dm646x_init(void); +void dm646x_init_mcasp0(struct snd_platform_data *pdata); +void dm646x_init_mcasp1(struct snd_platform_data *pdata); +int dm646x_init_edma(struct edma_rsv_info *rsv); void dm646x_video_init(void); void dm646x_setup_vpif(struct vpif_display_config *, struct vpif_capture_config *); diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c index cfb194df18e..612a0856e9c 100644 --- a/arch/arm/mach-davinci/devices-tnetv107x.c +++ b/arch/arm/mach-davinci/devices-tnetv107x.c @@ -18,10 +18,10 @@ #include <linux/dma-mapping.h> #include <linux/clk.h> #include <linux/slab.h> +#include <linux/platform_data/edma.h> #include <mach/common.h> #include <mach/irqs.h> -#include <mach/edma.h> #include <mach/tnetv107x.h> #include "clock.h" diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index a7068a3aa9d..90b83d00fe2 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -19,9 +19,10 @@ #include <mach/irqs.h> #include <mach/cputype.h> #include <mach/mux.h> -#include <mach/edma.h> #include <linux/platform_data/mmc-davinci.h> #include <mach/time.h> +#include <linux/platform_data/edma.h> + #include "davinci.h" #include "clock.h" @@ -34,6 +35,9 @@ #define DM365_MMCSD0_BASE 0x01D11000 #define DM365_MMCSD1_BASE 0x01D00000 +#define DAVINCI_DMA_MMCRXEVT 26 +#define DAVINCI_DMA_MMCTXEVT 27 + void __iomem *davinci_sysmod_base; void davinci_map_sysmod(void) diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index a11034a358f..526cf7d06d0 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -19,7 +19,6 @@ #include <asm/mach/map.h> #include <mach/cputype.h> -#include <mach/edma.h> #include <mach/psc.h> #include <mach/mux.h> #include <mach/irqs.h> @@ -28,6 +27,7 @@ #include <mach/common.h> #include <linux/platform_data/spi-davinci.h> #include <mach/gpio-davinci.h> +#include <linux/platform_data/edma.h> #include "davinci.h" #include "clock.h" diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 40fa4fee933..c4b741173c0 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -18,11 +18,11 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> #include <linux/spi/spi.h> +#include <linux/platform_data/edma.h> #include <asm/mach/map.h> #include <mach/cputype.h> -#include <mach/edma.h> #include <mach/psc.h> #include <mach/mux.h> #include <mach/irqs.h> diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 4d37d3e2a19..dd156d58fe6 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -12,11 +12,11 @@ #include <linux/clk.h> #include <linux/serial_8250.h> #include <linux/platform_device.h> +#include <linux/platform_data/edma.h> #include <asm/mach/map.h> #include <mach/cputype.h> -#include <mach/edma.h> #include <mach/irqs.h> #include <mach/psc.h> #include <mach/mux.h> diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index ac7b431c4c8..6d52a321a8c 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -13,11 +13,11 @@ #include <linux/clk.h> #include <linux/serial_8250.h> #include <linux/platform_device.h> +#include <linux/platform_data/edma.h> #include <asm/mach/map.h> #include <mach/cputype.h> -#include <mach/edma.h> #include <mach/irqs.h> #include <mach/psc.h> #include <mach/mux.h> diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h index d13d8dfa2b0..827bbe9baed 100644 --- a/arch/arm/mach-davinci/include/mach/cp_intc.h +++ b/arch/arm/mach-davinci/include/mach/cp_intc.h @@ -51,7 +51,7 @@ #define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2)) #define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2)) -void __init cp_intc_init(void); -int __init cp_intc_of_init(struct device_node *, struct device_node *); +void cp_intc_init(void); +int cp_intc_of_init(struct device_node *, struct device_node *); #endif /* __ASM_HARDWARE_CP_INTC_H */ diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 2e1c9eae0a5..3c797e2272f 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -20,8 +20,8 @@ #include <linux/videodev2.h> #include <mach/serial.h> -#include <mach/edma.h> #include <mach/pm.h> +#include <linux/platform_data/edma.h> #include <linux/platform_data/i2c-davinci.h> #include <linux/platform_data/mmc-davinci.h> #include <linux/platform_data/usb-davinci.h> @@ -79,8 +79,8 @@ extern unsigned int da850_max_speed; #define DA8XX_SHARED_RAM_BASE 0x80000000 #define DA8XX_ARM_RAM_BASE 0xffff0000 -void __init da830_init(void); -void __init da850_init(void); +void da830_init(void); +void da850_init(void); int da830_register_edma(struct edma_rsv_info *rsv); int da850_register_edma(struct edma_rsv_info *rsv[2]); @@ -94,17 +94,17 @@ int da8xx_register_uio_pruss(void); int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata); int da8xx_register_mmcsd0(struct davinci_mmc_config *config); int da850_register_mmcsd1(struct davinci_mmc_config *config); -void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata); +void da8xx_register_mcasp(int id, struct snd_platform_data *pdata); int da8xx_register_rtc(void); int da850_register_cpufreq(char *async_clk); int da8xx_register_cpuidle(void); -void __iomem * __init da8xx_get_mem_ctlr(void); +void __iomem *da8xx_get_mem_ctlr(void); int da850_register_pm(struct platform_device *pdev); -int __init da850_register_sata(unsigned long refclkpn); -int __init da850_register_vpif(void); -int __init da850_register_vpif_display +int da850_register_sata(unsigned long refclkpn); +int da850_register_vpif(void); +int da850_register_vpif_display (struct vpif_display_config *display_config); -int __init da850_register_vpif_capture +int da850_register_vpif_capture (struct vpif_capture_config *capture_config); void da8xx_restart(char mode, const char *cmd); void da8xx_rproc_reserve_cma(void); diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h deleted file mode 100644 index 7e84c906cef..00000000000 --- a/arch/arm/mach-davinci/include/mach/edma.h +++ /dev/null @@ -1,267 +0,0 @@ -/* - * TI DAVINCI dma definitions - * - * Copyright (C) 2006-2009 Texas Instruments. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -/* - * This EDMA3 programming framework exposes two basic kinds of resource: - * - * Channel Triggers transfers, usually from a hardware event but - * also manually or by "chaining" from DMA completions. - * Each channel is coupled to a Parameter RAM (PaRAM) slot. - * - * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM - * "set"), source and destination addresses, a link to a - * next PaRAM slot (if any), options for the transfer, and - * instructions for updating those addresses. There are - * more than twice as many slots as event channels. - * - * Each PaRAM set describes a sequence of transfers, either for one large - * buffer or for several discontiguous smaller buffers. An EDMA transfer - * is driven only from a channel, which performs the transfers specified - * in its PaRAM slot until there are no more transfers. When that last - * transfer completes, the "link" field may be used to reload the channel's - * PaRAM slot with a new transfer descriptor. - * - * The EDMA Channel Controller (CC) maps requests from channels into physical - * Transfer Controller (TC) requests when the channel triggers (by hardware - * or software events, or by chaining). The two physical DMA channels provided - * by the TCs are thus shared by many logical channels. - * - * DaVinci hardware also has a "QDMA" mechanism which is not currently - * supported through this interface. (DSP firmware uses it though.) - */ - -#ifndef EDMA_H_ -#define EDMA_H_ - -/* PaRAM slots are laid out like this */ -struct edmacc_param { - unsigned int opt; - unsigned int src; - unsigned int a_b_cnt; - unsigned int dst; - unsigned int src_dst_bidx; - unsigned int link_bcntrld; - unsigned int src_dst_cidx; - unsigned int ccnt; -}; - -#define CCINT0_INTERRUPT 16 -#define CCERRINT_INTERRUPT 17 -#define TCERRINT0_INTERRUPT 18 -#define TCERRINT1_INTERRUPT 19 - -/* fields in edmacc_param.opt */ -#define SAM BIT(0) -#define DAM BIT(1) -#define SYNCDIM BIT(2) -#define STATIC BIT(3) -#define EDMA_FWID (0x07 << 8) -#define TCCMODE BIT(11) -#define EDMA_TCC(t) ((t) << 12) -#define TCINTEN BIT(20) -#define ITCINTEN BIT(21) -#define TCCHEN BIT(22) -#define ITCCHEN BIT(23) - -#define TRWORD (0x7<<2) -#define PAENTRY (0x1ff<<5) - -/* Drivers should avoid using these symbolic names for dm644x - * channels, and use platform_device IORESOURCE_DMA resources - * instead. (Other DaVinci chips have different peripherals - * and thus have different DMA channel mappings.) - */ -#define DAVINCI_DMA_MCBSP_TX 2 -#define DAVINCI_DMA_MCBSP_RX 3 -#define DAVINCI_DMA_VPSS_HIST 4 -#define DAVINCI_DMA_VPSS_H3A 5 -#define DAVINCI_DMA_VPSS_PRVU 6 -#define DAVINCI_DMA_VPSS_RSZ 7 -#define DAVINCI_DMA_IMCOP_IMXINT 8 -#define DAVINCI_DMA_IMCOP_VLCDINT 9 -#define DAVINCI_DMA_IMCO_PASQINT 10 -#define DAVINCI_DMA_IMCOP_DSQINT 11 -#define DAVINCI_DMA_SPI_SPIX 16 -#define DAVINCI_DMA_SPI_SPIR 17 -#define DAVINCI_DMA_UART0_URXEVT0 18 -#define DAVINCI_DMA_UART0_UTXEVT0 19 -#define DAVINCI_DMA_UART1_URXEVT1 20 -#define DAVINCI_DMA_UART1_UTXEVT1 21 -#define DAVINCI_DMA_UART2_URXEVT2 22 -#define DAVINCI_DMA_UART2_UTXEVT2 23 -#define DAVINCI_DMA_MEMSTK_MSEVT 24 -#define DAVINCI_DMA_MMCRXEVT 26 -#define DAVINCI_DMA_MMCTXEVT 27 -#define DAVINCI_DMA_I2C_ICREVT 28 -#define DAVINCI_DMA_I2C_ICXEVT 29 -#define DAVINCI_DMA_GPIO_GPINT0 32 -#define DAVINCI_DMA_GPIO_GPINT1 33 -#define DAVINCI_DMA_GPIO_GPINT2 34 -#define DAVINCI_DMA_GPIO_GPINT3 35 -#define DAVINCI_DMA_GPIO_GPINT4 36 -#define DAVINCI_DMA_GPIO_GPINT5 37 -#define DAVINCI_DMA_GPIO_GPINT6 38 -#define DAVINCI_DMA_GPIO_GPINT7 39 -#define DAVINCI_DMA_GPIO_GPBNKINT0 40 -#define DAVINCI_DMA_GPIO_GPBNKINT1 41 -#define DAVINCI_DMA_GPIO_GPBNKINT2 42 -#define DAVINCI_DMA_GPIO_GPBNKINT3 43 -#define DAVINCI_DMA_GPIO_GPBNKINT4 44 -#define DAVINCI_DMA_TIMER0_TINT0 48 -#define DAVINCI_DMA_TIMER1_TINT1 49 -#define DAVINCI_DMA_TIMER2_TINT2 50 -#define DAVINCI_DMA_TIMER3_TINT3 51 -#define DAVINCI_DMA_PWM0 52 -#define DAVINCI_DMA_PWM1 53 -#define DAVINCI_DMA_PWM2 54 - -/* DA830 specific EDMA3 information */ -#define EDMA_DA830_NUM_DMACH 32 -#define EDMA_DA830_NUM_TCC 32 -#define EDMA_DA830_NUM_PARAMENTRY 128 -#define EDMA_DA830_NUM_EVQUE 2 -#define EDMA_DA830_NUM_TC 2 -#define EDMA_DA830_CHMAP_EXIST 0 -#define EDMA_DA830_NUM_REGIONS 4 -#define DA830_DMACH2EVENT_MAP0 0x000FC03Fu -#define DA830_DMACH2EVENT_MAP1 0x00000000u -#define DA830_EDMA_ARM_OWN 0x30FFCCFFu - -/*ch_status paramater of callback function possible values*/ -#define DMA_COMPLETE 1 -#define DMA_CC_ERROR 2 -#define DMA_TC1_ERROR 3 -#define DMA_TC2_ERROR 4 - -enum address_mode { - INCR = 0, - FIFO = 1 -}; - -enum fifo_width { - W8BIT = 0, - W16BIT = 1, - W32BIT = 2, - W64BIT = 3, - W128BIT = 4, - W256BIT = 5 -}; - -enum dma_event_q { - EVENTQ_0 = 0, - EVENTQ_1 = 1, - EVENTQ_2 = 2, - EVENTQ_3 = 3, - EVENTQ_DEFAULT = -1 -}; - -enum sync_dimension { - ASYNC = 0, - ABSYNC = 1 -}; - -#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) -#define EDMA_CTLR(i) ((i) >> 16) -#define EDMA_CHAN_SLOT(i) ((i) & 0xffff) - -#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ -#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ -#define EDMA_CONT_PARAMS_ANY 1001 -#define EDMA_CONT_PARAMS_FIXED_EXACT 1002 -#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 - -#define EDMA_MAX_CC 2 - -/* alloc/free DMA channels and their dedicated parameter RAM slots */ -int edma_alloc_channel(int channel, - void (*callback)(unsigned channel, u16 ch_status, void *data), - void *data, enum dma_event_q); -void edma_free_channel(unsigned channel); - -/* alloc/free parameter RAM slots */ -int edma_alloc_slot(unsigned ctlr, int slot); -void edma_free_slot(unsigned slot); - -/* alloc/free a set of contiguous parameter RAM slots */ -int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count); -int edma_free_cont_slots(unsigned slot, int count); - -/* calls that operate on part of a parameter RAM slot */ -void edma_set_src(unsigned slot, dma_addr_t src_port, - enum address_mode mode, enum fifo_width); -void edma_set_dest(unsigned slot, dma_addr_t dest_port, - enum address_mode mode, enum fifo_width); -void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst); -void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx); -void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx); -void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt, - u16 bcnt_rld, enum sync_dimension sync_mode); -void edma_link(unsigned from, unsigned to); -void edma_unlink(unsigned from); - -/* calls that operate on an entire parameter RAM slot */ -void edma_write_slot(unsigned slot, const struct edmacc_param *params); -void edma_read_slot(unsigned slot, struct edmacc_param *params); - -/* channel control operations */ -int edma_start(unsigned channel); -void edma_stop(unsigned channel); -void edma_clean_channel(unsigned channel); -void edma_clear_event(unsigned channel); -void edma_pause(unsigned channel); -void edma_resume(unsigned channel); - -struct edma_rsv_info { - - const s16 (*rsv_chans)[2]; - const s16 (*rsv_slots)[2]; -}; - -/* platform_data for EDMA driver */ -struct edma_soc_info { - - /* how many dma resources of each type */ - unsigned n_channel; - unsigned n_region; - unsigned n_slot; - unsigned n_tc; - unsigned n_cc; - /* - * Default queue is expected to be a low-priority queue. - * This way, long transfers on the default queue started - * by the codec engine will not cause audio defects. - */ - enum dma_event_q default_queue; - - /* Resource reservation for other cores */ - struct edma_rsv_info *rsv; - - const s8 (*queue_tc_mapping)[2]; - const s8 (*queue_priority_mapping)[2]; -}; - -#endif diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h index 1656a02e3ed..366e975effa 100644 --- a/arch/arm/mach-davinci/include/mach/tnetv107x.h +++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h @@ -51,9 +51,9 @@ struct tnetv107x_device_info { extern struct platform_device tnetv107x_wdt_device; extern struct platform_device tnetv107x_serial_device; -extern void __init tnetv107x_init(void); -extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *); -extern void __init tnetv107x_irq_init(void); +extern void tnetv107x_init(void); +extern void tnetv107x_devices_init(struct tnetv107x_device_info *); +extern void tnetv107x_irq_init(void); void tnetv107x_restart(char mode, const char *cmd); #endif diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig index 36469d81395..dff7b2fd4e2 100644 --- a/arch/arm/mach-dove/Kconfig +++ b/arch/arm/mach-dove/Kconfig @@ -22,8 +22,7 @@ config MACH_CM_A510 config MACH_DOVE_DT bool "Marvell Dove Flattened Device Tree" - select MVEBU_CLK_CORE - select MVEBU_CLK_GATING + select DOVE_CLK select REGULATOR select REGULATOR_FIXED_VOLTAGE select USE_OF diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c index 0b142803b2e..f3755ac8114 100644 --- a/arch/arm/mach-dove/board-dt.c +++ b/arch/arm/mach-dove/board-dt.c @@ -10,7 +10,6 @@ #include <linux/init.h> #include <linux/clk-provider.h> -#include <linux/clk/mvebu.h> #include <linux/of.h> #include <linux/of_platform.h> #include <linux/platform_data/usb-ehci-orion.h> @@ -49,7 +48,7 @@ static void __init dove_legacy_clk_init(void) static void __init dove_of_clk_init(void) { - mvebu_clocks_init(); + of_clk_init(NULL); dove_legacy_clk_init(); } diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index e2b5da031f9..2a9443d04d9 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -9,7 +9,6 @@ */ #include <linux/clk-provider.h> -#include <linux/clk/mvebu.h> #include <linux/dma-mapping.h> #include <linux/init.h> #include <linux/of.h> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index d19edff0ea6..1e0e3999c17 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -14,9 +14,11 @@ menu "SAMSUNG EXYNOS SoCs Support" config ARCH_EXYNOS4 bool "SAMSUNG EXYNOS4" default y + select GIC_NON_BANKED select HAVE_ARM_SCU if SMP select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 + select PINCTRL help Samsung EXYNOS4 SoCs based systems @@ -24,6 +26,7 @@ config ARCH_EXYNOS5 bool "SAMSUNG EXYNOS5" select HAVE_ARM_SCU if SMP select HAVE_SMP + select PINCTRL help Samsung EXYNOS5 (Cortex-A15) SoC based systems @@ -34,6 +37,7 @@ config CPU_EXYNOS4210 default y depends on ARCH_EXYNOS4 select ARM_CPU_SUSPEND if PM + select PINCTRL_EXYNOS select PM_GENERIC_DOMAINS select S5P_PM if PM select S5P_SLEEP if PM @@ -45,6 +49,7 @@ config SOC_EXYNOS4212 bool "SAMSUNG EXYNOS4212" default y depends on ARCH_EXYNOS4 + select PINCTRL_EXYNOS select S5P_PM if PM select S5P_SLEEP if PM select SAMSUNG_DMADEV @@ -55,6 +60,7 @@ config SOC_EXYNOS4412 bool "SAMSUNG EXYNOS4412" default y depends on ARCH_EXYNOS4 + select PINCTRL_EXYNOS select SAMSUNG_DMADEV help Enable EXYNOS4412 SoC support @@ -63,6 +69,7 @@ config SOC_EXYNOS5250 bool "SAMSUNG EXYNOS5250" default y depends on ARCH_EXYNOS5 + select PINCTRL_EXYNOS select PM_GENERIC_DOMAINS if PM select S5P_PM if PM select S5P_SLEEP if PM @@ -78,344 +85,23 @@ config SOC_EXYNOS5440 select ARCH_HAS_OPP select ARM_ARCH_TIMER select AUTO_ZRELADDR - select PINCTRL select PINCTRL_EXYNOS5440 select PM_OPP help Enable EXYNOS5440 SoC support -config EXYNOS_ATAGS - bool "ATAGS based boot for EXYNOS (deprecated)" - depends on !ARCH_MULTIPLATFORM - depends on ATAGS - default y - help - The EXYNOS platform is moving towards being completely probed - through device tree. This enables support for board files using - the traditional ATAGS boot format. - Note that this option is not available for multiplatform builds. - -if EXYNOS_ATAGS - -config EXYNOS_DEV_DMA - bool - help - Compile in amba device definitions for DMA controller - -config EXYNOS4_DEV_AHCI - bool - help - Compile in platform device definitions for AHCI - -config EXYNOS4_SETUP_FIMD0 - bool - help - Common setup code for FIMD0. - -config EXYNOS4_DEV_USB_OHCI - bool - help - Compile in platform device definition for USB OHCI - -config EXYNOS4_SETUP_I2C1 - bool - help - Common setup code for i2c bus 1. - -config EXYNOS4_SETUP_I2C2 - bool - help - Common setup code for i2c bus 2. - -config EXYNOS4_SETUP_I2C3 - bool - help - Common setup code for i2c bus 3. - -config EXYNOS4_SETUP_I2C4 - bool - help - Common setup code for i2c bus 4. - -config EXYNOS4_SETUP_I2C5 - bool - help - Common setup code for i2c bus 5. - -config EXYNOS4_SETUP_I2C6 - bool - help - Common setup code for i2c bus 6. - -config EXYNOS4_SETUP_I2C7 - bool - help - Common setup code for i2c bus 7. - -config EXYNOS4_SETUP_KEYPAD - bool - help - Common setup code for keypad. - -config EXYNOS4_SETUP_SDHCI - bool - select EXYNOS4_SETUP_SDHCI_GPIO - help - Internal helper functions for EXYNOS4 based SDHCI systems. - -config EXYNOS4_SETUP_SDHCI_GPIO - bool - help - Common setup code for SDHCI gpio. - -config EXYNOS4_SETUP_FIMC - bool - help - Common setup code for the camera interfaces. - -config EXYNOS4_SETUP_USB_PHY - bool - help - Common setup code for USB PHY controller - -config EXYNOS_SETUP_SPI - bool - help - Common setup code for SPI GPIO configurations. - -# machine support - -if ARCH_EXYNOS4 - -comment "EXYNOS4210 Boards" - -config MACH_SMDKC210 - bool "SMDKC210" - select MACH_SMDKV310 - help - Machine support for Samsung SMDKC210 - -config MACH_SMDKV310 - bool "SMDKV310" - select CPU_EXYNOS4210 - select EXYNOS4_DEV_AHCI - select EXYNOS4_DEV_USB_OHCI - select EXYNOS4_SETUP_FIMD0 - select EXYNOS4_SETUP_I2C1 - select EXYNOS4_SETUP_KEYPAD - select EXYNOS4_SETUP_SDHCI - select EXYNOS4_SETUP_USB_PHY - select EXYNOS_DEV_DMA - select EXYNOS_DEV_SYSMMU - select S3C24XX_PWM - select S3C_DEV_HSMMC - select S3C_DEV_HSMMC1 - select S3C_DEV_HSMMC2 - select S3C_DEV_HSMMC3 - select S3C_DEV_I2C1 - select S3C_DEV_RTC - select S3C_DEV_USB_HSOTG - select S3C_DEV_WDT - select S5P_DEV_FIMC0 - select S5P_DEV_FIMC1 - select S5P_DEV_FIMC2 - select S5P_DEV_FIMC3 - select S5P_DEV_FIMD0 - select S5P_DEV_G2D - select S5P_DEV_I2C_HDMIPHY - select S5P_DEV_JPEG - select S5P_DEV_MFC - select S5P_DEV_TV - select S5P_DEV_USB_EHCI - select SAMSUNG_DEV_BACKLIGHT - select SAMSUNG_DEV_KEYPAD - select SAMSUNG_DEV_PWM - help - Machine support for Samsung SMDKV310 - -config MACH_ARMLEX4210 - bool "ARMLEX4210" - select CPU_EXYNOS4210 - select EXYNOS4_DEV_AHCI - select EXYNOS4_SETUP_SDHCI - select EXYNOS_DEV_DMA - select S3C_DEV_HSMMC - select S3C_DEV_HSMMC2 - select S3C_DEV_HSMMC3 - select S3C_DEV_RTC - select S3C_DEV_WDT - help - Machine support for Samsung ARMLEX4210 based on EXYNOS4210 - -config MACH_UNIVERSAL_C210 - bool "Mobile UNIVERSAL_C210 Board" - select CLKSRC_MMIO - select CPU_EXYNOS4210 - select EXYNOS4_SETUP_FIMC - select EXYNOS4_SETUP_FIMD0 - select EXYNOS4_SETUP_I2C1 - select EXYNOS4_SETUP_I2C3 - select EXYNOS4_SETUP_I2C5 - select EXYNOS4_SETUP_SDHCI - select EXYNOS4_SETUP_USB_PHY - select EXYNOS_DEV_DMA - select EXYNOS_DEV_SYSMMU - select S3C_DEV_HSMMC - select S3C_DEV_HSMMC2 - select S3C_DEV_HSMMC3 - select S3C_DEV_I2C1 - select S3C_DEV_I2C3 - select S3C_DEV_I2C5 - select S3C_DEV_USB_HSOTG - select S5P_DEV_CSIS0 - select S5P_DEV_FIMC0 - select S5P_DEV_FIMC1 - select S5P_DEV_FIMC2 - select S5P_DEV_FIMC3 - select S5P_DEV_FIMD0 - select S5P_DEV_G2D - select S5P_DEV_I2C_HDMIPHY - select S5P_DEV_JPEG - select S5P_DEV_MFC - select S5P_DEV_ONENAND - select S5P_DEV_TV - select S5P_GPIO_INT - select S5P_SETUP_MIPIPHY - select SAMSUNG_HRT - help - Machine support for Samsung Mobile Universal S5PC210 Reference - Board. - -config MACH_NURI - bool "Mobile NURI Board" - select CPU_EXYNOS4210 - select EXYNOS4_SETUP_FIMC - select EXYNOS4_SETUP_FIMD0 - select EXYNOS4_SETUP_I2C1 - select EXYNOS4_SETUP_I2C3 - select EXYNOS4_SETUP_I2C5 - select EXYNOS4_SETUP_I2C6 - select EXYNOS4_SETUP_SDHCI - select EXYNOS4_SETUP_USB_PHY - select EXYNOS_DEV_DMA - select S3C_DEV_HSMMC - select S3C_DEV_HSMMC2 - select S3C_DEV_HSMMC3 - select S3C_DEV_I2C1 - select S3C_DEV_I2C3 - select S3C_DEV_I2C5 - select S3C_DEV_I2C6 - select S3C_DEV_RTC - select S3C_DEV_USB_HSOTG - select S3C_DEV_WDT - select S5P_DEV_CSIS0 - select S5P_DEV_FIMC0 - select S5P_DEV_FIMC1 - select S5P_DEV_FIMC2 - select S5P_DEV_FIMC3 - select S5P_DEV_FIMD0 - select S5P_DEV_G2D - select S5P_DEV_JPEG - select S5P_DEV_MFC - select S5P_DEV_USB_EHCI - select S5P_GPIO_INT - select S5P_SETUP_MIPIPHY - select SAMSUNG_DEV_ADC - select SAMSUNG_DEV_PWM - help - Machine support for Samsung Mobile NURI Board. - -config MACH_ORIGEN - bool "ORIGEN" - select CPU_EXYNOS4210 - select EXYNOS4_DEV_USB_OHCI - select EXYNOS4_SETUP_FIMD0 - select EXYNOS4_SETUP_SDHCI - select EXYNOS4_SETUP_USB_PHY - select EXYNOS_DEV_DMA - select EXYNOS_DEV_SYSMMU - select S3C24XX_PWM - select S3C_DEV_HSMMC - select S3C_DEV_HSMMC2 - select S3C_DEV_RTC - select S3C_DEV_USB_HSOTG - select S3C_DEV_WDT - select S5P_DEV_FIMC0 - select S5P_DEV_FIMC1 - select S5P_DEV_FIMC2 - select S5P_DEV_FIMC3 - select S5P_DEV_FIMD0 - select S5P_DEV_G2D - select S5P_DEV_I2C_HDMIPHY - select S5P_DEV_JPEG - select S5P_DEV_MFC - select S5P_DEV_TV - select S5P_DEV_USB_EHCI - select SAMSUNG_DEV_BACKLIGHT - select SAMSUNG_DEV_PWM - help - Machine support for ORIGEN based on Samsung EXYNOS4210 - -comment "EXYNOS4212 Boards" - -config MACH_SMDK4212 - bool "SMDK4212" - select EXYNOS4_SETUP_FIMD0 - select EXYNOS4_SETUP_I2C1 - select EXYNOS4_SETUP_I2C3 - select EXYNOS4_SETUP_I2C7 - select EXYNOS4_SETUP_KEYPAD - select EXYNOS4_SETUP_SDHCI - select EXYNOS4_SETUP_USB_PHY - select EXYNOS_DEV_DMA - select EXYNOS_DEV_SYSMMU - select S3C24XX_PWM - select S3C_DEV_HSMMC2 - select S3C_DEV_HSMMC3 - select S3C_DEV_I2C1 - select S3C_DEV_I2C3 - select S3C_DEV_I2C7 - select S3C_DEV_RTC - select S3C_DEV_USB_HSOTG - select S3C_DEV_WDT - select S5P_DEV_FIMC0 - select S5P_DEV_FIMC1 - select S5P_DEV_FIMC2 - select S5P_DEV_FIMC3 - select S5P_DEV_FIMD0 - select S5P_DEV_MFC - select SAMSUNG_DEV_BACKLIGHT - select SAMSUNG_DEV_KEYPAD - select SAMSUNG_DEV_PWM - select SOC_EXYNOS4212 - help - Machine support for Samsung SMDK4212 - -comment "EXYNOS4412 Boards" - -config MACH_SMDK4412 - bool "SMDK4412" - select MACH_SMDK4212 - select SOC_EXYNOS4412 - help - Machine support for Samsung SMDK4412 -endif - -endif - comment "Flattened Device Tree based board for EXYNOS SoCs" config MACH_EXYNOS4_DT bool "Samsung Exynos4 Machine using device tree" + default y depends on ARCH_EXYNOS4 select ARM_AMBA select CLKSRC_OF + select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210 select CPU_EXYNOS4210 select KEYBOARD_SAMSUNG if INPUT_KEYBOARD - select PINCTRL - select PINCTRL_EXYNOS select S5P_DEV_MFC - select USE_OF help Machine support for Samsung Exynos4 machine with device tree enabled. Select this if a fdt blob is available for the Exynos4 SoC based board. @@ -428,28 +114,11 @@ config MACH_EXYNOS5_DT depends on ARCH_EXYNOS5 select ARM_AMBA select CLKSRC_OF - select USE_OF + select USB_ARCH_HAS_XHCI help Machine support for Samsung EXYNOS5 machine with device tree enabled. Select this if a fdt blob is available for the EXYNOS5 SoC based board. -if ARCH_EXYNOS4 - -comment "Configuration for HSMMC 8-bit bus width" - -config EXYNOS4_SDHCI_CH0_8BIT - bool "Channel 0 with 8-bit bus" - help - Support HSMMC Channel 0 8-bit bus. - If selected, Channel 1 is disabled. - -config EXYNOS4_SDHCI_CH2_8BIT - bool "Channel 2 with 8-bit bus" - help - Support HSMMC Channel 2 8-bit bus. - If selected, Channel 3 is disabled. -endif - endmenu endif diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index b09b027178f..e970a7a4e27 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -32,38 +32,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec) # machine support -obj-$(CONFIG_MACH_SMDKC210) += mach-smdkv310.o -obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o -obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o -obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o -obj-$(CONFIG_MACH_NURI) += mach-nuri.o -obj-$(CONFIG_MACH_ORIGEN) += mach-origen.o - -obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o -obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o - obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o - -# device support - -obj-y += dev-uart.o -obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o -obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o -obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o -obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o - -obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o -obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o -obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o -obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o -obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o -obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o -obj-$(CONFIG_EXYNOS4_SETUP_I2C4) += setup-i2c4.o -obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o -obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o -obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o -obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o -obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o -obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o -obj-$(CONFIG_EXYNOS_SETUP_SPI) += setup-spi.o diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 745e304ad0d..81e6320ca09 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -10,12 +10,14 @@ */ #include <linux/kernel.h> +#include <linux/bitops.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/irqchip.h> #include <linux/io.h> #include <linux/device.h> #include <linux/gpio.h> +#include <clocksource/samsung_pwm.h> #include <linux/sched.h> #include <linux/serial_core.h> #include <linux/of.h> @@ -38,20 +40,9 @@ #include <mach/regs-irq.h> #include <mach/regs-pmu.h> -#include <mach/regs-gpio.h> -#include <mach/irqs.h> #include <plat/cpu.h> -#include <plat/devs.h> #include <plat/pm.h> -#include <plat/sdhci.h> -#include <plat/gpio-cfg.h> -#include <plat/adc-core.h> -#include <plat/fb-core.h> -#include <plat/fimc-core.h> -#include <plat/iic-core.h> -#include <plat/tv-core.h> -#include <plat/spi-core.h> #include <plat/regs-serial.h> #include "common.h" @@ -67,31 +58,25 @@ static const char name_exynos5440[] = "EXYNOS5440"; static void exynos4_map_io(void); static void exynos5_map_io(void); static void exynos5440_map_io(void); -static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no); static int exynos_init(void); -unsigned long xxti_f = 0, xusbxti_f = 0; - static struct cpu_table cpu_ids[] __initdata = { { .idcode = EXYNOS4210_CPU_ID, .idmask = EXYNOS4_CPU_MASK, .map_io = exynos4_map_io, - .init_uarts = exynos4_init_uarts, .init = exynos_init, .name = name_exynos4210, }, { .idcode = EXYNOS4212_CPU_ID, .idmask = EXYNOS4_CPU_MASK, .map_io = exynos4_map_io, - .init_uarts = exynos4_init_uarts, .init = exynos_init, .name = name_exynos4212, }, { .idcode = EXYNOS4412_CPU_ID, .idmask = EXYNOS4_CPU_MASK, .map_io = exynos4_map_io, - .init_uarts = exynos4_init_uarts, .init = exynos_init, .name = name_exynos4412, }, { @@ -111,15 +96,6 @@ static struct cpu_table cpu_ids[] __initdata = { /* Initial IO mappings */ -static struct map_desc exynos_iodesc[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_CHIPID, - .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - static struct map_desc exynos4_iodesc[] __initdata = { { .virtual = (unsigned long)S3C_VA_SYS, @@ -317,9 +293,16 @@ void exynos5_restart(char mode, const char *cmd) val = 0x1; addr = EXYNOS_SWRESET; } else if (of_machine_is_compatible("samsung,exynos5440")) { + u32 status; np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock"); + + addr = of_iomap(np, 0) + 0xbc; + status = __raw_readl(addr); + addr = of_iomap(np, 0) + 0xcc; - val = (0xfff << 20) | (0x1 << 16); + val = __raw_readl(addr); + + val = (val & 0xffff0000) | (status & 0xffff); } else { pr_err("%s: cannot support non-DT\n", __func__); return; @@ -337,8 +320,7 @@ void __init exynos_init_late(void) exynos_pm_late_initcall(); } -#ifdef CONFIG_OF -int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, +static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, int depth, void *data) { struct map_desc iodesc; @@ -360,7 +342,6 @@ int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, iotable_init(&iodesc, 1); return 1; } -#endif /* * exynos_map_io @@ -368,17 +349,11 @@ int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, * register the standard cpu IO areas */ -void __init exynos_init_io(struct map_desc *mach_desc, int size) +void __init exynos_init_io(void) { -#ifdef CONFIG_OF - if (initial_boot_params) - of_scan_flat_dt(exynos_fdt_map_chipid, NULL); - else -#endif - iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc)); + debug_ll_io_init(); - if (mach_desc) - iotable_init(mach_desc, size); + of_scan_flat_dt(exynos_fdt_map_chipid, NULL); /* detect cpu id and rev. */ s5p_init_cpu(S5P_VA_CHIPID); @@ -399,34 +374,6 @@ static void __init exynos4_map_io(void) iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc)); if (soc_is_exynos4212() || soc_is_exynos4412()) iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc)); - - /* initialize device information early */ - exynos4_default_sdhci0(); - exynos4_default_sdhci1(); - exynos4_default_sdhci2(); - exynos4_default_sdhci3(); - - s3c_adc_setname("samsung-adc-v3"); - - s3c_fimc_setname(0, "exynos4-fimc"); - s3c_fimc_setname(1, "exynos4-fimc"); - s3c_fimc_setname(2, "exynos4-fimc"); - s3c_fimc_setname(3, "exynos4-fimc"); - - s3c_sdhci_setname(0, "exynos4-sdhci"); - s3c_sdhci_setname(1, "exynos4-sdhci"); - s3c_sdhci_setname(2, "exynos4-sdhci"); - s3c_sdhci_setname(3, "exynos4-sdhci"); - - /* The I2C bus controllers are directly compatible with s3c2440 */ - s3c_i2c0_setname("s3c2440-i2c"); - s3c_i2c1_setname("s3c2440-i2c"); - s3c_i2c2_setname("s3c2440-i2c"); - - s5p_fb_setname(0, "exynos4-fb"); - s5p_hdmi_setname("exynos4-hdmi"); - - s3c64xx_spi_setname("exynos4210-spi"); } static void __init exynos5_map_io(void) @@ -444,60 +391,8 @@ static void __init exynos5440_map_io(void) void __init exynos_init_time(void) { - if (of_have_populated_dt()) { -#ifdef CONFIG_OF - of_clk_init(NULL); - clocksource_of_init(); -#endif - } else { - /* todo: remove after migrating legacy E4 platforms to dt */ -#ifdef CONFIG_ARCH_EXYNOS4 - exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1); - exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f); -#endif - mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0, EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1); - } -} - -static unsigned int max_combiner_nr(void) -{ - if (soc_is_exynos5250()) - return EXYNOS5_MAX_COMBINER_NR; - else if (soc_is_exynos4412()) - return EXYNOS4412_MAX_COMBINER_NR; - else if (soc_is_exynos4212()) - return EXYNOS4212_MAX_COMBINER_NR; - else - return EXYNOS4210_MAX_COMBINER_NR; -} - - -void __init exynos4_init_irq(void) -{ - unsigned int gic_bank_offset; - - gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; - - if (!of_have_populated_dt()) - gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL); -#ifdef CONFIG_OF - else - irqchip_init(); -#endif - - if (!of_have_populated_dt()) - combiner_init(S5P_VA_COMBINER_BASE, NULL, - max_combiner_nr(), COMBINER_IRQ(0, 0)); - - gic_arch_extn.irq_set_wake = s3c_irq_wake; -} - -void __init exynos5_init_irq(void) -{ -#ifdef CONFIG_OF - irqchip_init(); -#endif - gic_arch_extn.irq_set_wake = s3c_irq_wake; + of_clk_init(NULL); + clocksource_of_init(); } struct bus_type exynos_subsys = { @@ -515,59 +410,19 @@ static int __init exynos_core_init(void) } core_initcall(exynos_core_init); -#ifdef CONFIG_CACHE_L2X0 static int __init exynos4_l2x0_cache_init(void) { int ret; - if (soc_is_exynos5250() || soc_is_exynos5440()) - return 0; - ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); - if (!ret) { - l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); - clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); - return 0; - } - - if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) { - l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC; - /* TAG, Data Latency Control: 2 cycles */ - l2x0_saved_regs.tag_latency = 0x110; - - if (soc_is_exynos4212() || soc_is_exynos4412()) - l2x0_saved_regs.data_latency = 0x120; - else - l2x0_saved_regs.data_latency = 0x110; - - l2x0_saved_regs.prefetch_ctrl = 0x30000007; - l2x0_saved_regs.pwr_ctrl = - (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN); - - l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); - - __raw_writel(l2x0_saved_regs.tag_latency, - S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); - __raw_writel(l2x0_saved_regs.data_latency, - S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); - - /* L2X0 Prefetch Control */ - __raw_writel(l2x0_saved_regs.prefetch_ctrl, - S5P_VA_L2CC + L2X0_PREFETCH_CTRL); + if (ret) + return ret; - /* L2X0 Power Control */ - __raw_writel(l2x0_saved_regs.pwr_ctrl, - S5P_VA_L2CC + L2X0_POWER_CTRL); - - clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); - clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs)); - } - - l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK); + l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); + clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); return 0; } early_initcall(exynos4_l2x0_cache_init); -#endif static int __init exynos_init(void) { @@ -575,350 +430,3 @@ static int __init exynos_init(void) return device_register(&exynos4_dev); } - -/* uart registration process */ - -static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no) -{ - struct s3c2410_uartcfg *tcfg = cfg; - u32 ucnt; - - for (ucnt = 0; ucnt < no; ucnt++, tcfg++) - tcfg->has_fracval = 1; - - s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no); -} - -static void __iomem *exynos_eint_base; - -static DEFINE_SPINLOCK(eint_lock); - -static unsigned int eint0_15_data[16]; - -static inline int exynos4_irq_to_gpio(unsigned int irq) -{ - if (irq < IRQ_EINT(0)) - return -EINVAL; - - irq -= IRQ_EINT(0); - if (irq < 8) - return EXYNOS4_GPX0(irq); - - irq -= 8; - if (irq < 8) - return EXYNOS4_GPX1(irq); - - irq -= 8; - if (irq < 8) - return EXYNOS4_GPX2(irq); - - irq -= 8; - if (irq < 8) - return EXYNOS4_GPX3(irq); - - return -EINVAL; -} - -static inline int exynos5_irq_to_gpio(unsigned int irq) -{ - if (irq < IRQ_EINT(0)) - return -EINVAL; - - irq -= IRQ_EINT(0); - if (irq < 8) - return EXYNOS5_GPX0(irq); - - irq -= 8; - if (irq < 8) - return EXYNOS5_GPX1(irq); - - irq -= 8; - if (irq < 8) - return EXYNOS5_GPX2(irq); - - irq -= 8; - if (irq < 8) - return EXYNOS5_GPX3(irq); - - return -EINVAL; -} - -static unsigned int exynos4_eint0_15_src_int[16] = { - EXYNOS4_IRQ_EINT0, - EXYNOS4_IRQ_EINT1, - EXYNOS4_IRQ_EINT2, - EXYNOS4_IRQ_EINT3, - EXYNOS4_IRQ_EINT4, - EXYNOS4_IRQ_EINT5, - EXYNOS4_IRQ_EINT6, - EXYNOS4_IRQ_EINT7, - EXYNOS4_IRQ_EINT8, - EXYNOS4_IRQ_EINT9, - EXYNOS4_IRQ_EINT10, - EXYNOS4_IRQ_EINT11, - EXYNOS4_IRQ_EINT12, - EXYNOS4_IRQ_EINT13, - EXYNOS4_IRQ_EINT14, - EXYNOS4_IRQ_EINT15, -}; - -static unsigned int exynos5_eint0_15_src_int[16] = { - EXYNOS5_IRQ_EINT0, - EXYNOS5_IRQ_EINT1, - EXYNOS5_IRQ_EINT2, - EXYNOS5_IRQ_EINT3, - EXYNOS5_IRQ_EINT4, - EXYNOS5_IRQ_EINT5, - EXYNOS5_IRQ_EINT6, - EXYNOS5_IRQ_EINT7, - EXYNOS5_IRQ_EINT8, - EXYNOS5_IRQ_EINT9, - EXYNOS5_IRQ_EINT10, - EXYNOS5_IRQ_EINT11, - EXYNOS5_IRQ_EINT12, - EXYNOS5_IRQ_EINT13, - EXYNOS5_IRQ_EINT14, - EXYNOS5_IRQ_EINT15, -}; -static inline void exynos_irq_eint_mask(struct irq_data *data) -{ - u32 mask; - - spin_lock(&eint_lock); - mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq)); - mask |= EINT_OFFSET_BIT(data->irq); - __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq)); - spin_unlock(&eint_lock); -} - -static void exynos_irq_eint_unmask(struct irq_data *data) -{ - u32 mask; - - spin_lock(&eint_lock); - mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq)); - mask &= ~(EINT_OFFSET_BIT(data->irq)); - __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq)); - spin_unlock(&eint_lock); -} - -static inline void exynos_irq_eint_ack(struct irq_data *data) -{ - __raw_writel(EINT_OFFSET_BIT(data->irq), - EINT_PEND(exynos_eint_base, data->irq)); -} - -static void exynos_irq_eint_maskack(struct irq_data *data) -{ - exynos_irq_eint_mask(data); - exynos_irq_eint_ack(data); -} - -static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type) -{ - int offs = EINT_OFFSET(data->irq); - int shift; - u32 ctrl, mask; - u32 newvalue = 0; - - switch (type) { - case IRQ_TYPE_EDGE_RISING: - newvalue = S5P_IRQ_TYPE_EDGE_RISING; - break; - - case IRQ_TYPE_EDGE_FALLING: - newvalue = S5P_IRQ_TYPE_EDGE_FALLING; - break; - - case IRQ_TYPE_EDGE_BOTH: - newvalue = S5P_IRQ_TYPE_EDGE_BOTH; - break; - - case IRQ_TYPE_LEVEL_LOW: - newvalue = S5P_IRQ_TYPE_LEVEL_LOW; - break; - - case IRQ_TYPE_LEVEL_HIGH: - newvalue = S5P_IRQ_TYPE_LEVEL_HIGH; - break; - - default: - printk(KERN_ERR "No such irq type %d", type); - return -EINVAL; - } - - shift = (offs & 0x7) * 4; - mask = 0x7 << shift; - - spin_lock(&eint_lock); - ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq)); - ctrl &= ~mask; - ctrl |= newvalue << shift; - __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq)); - spin_unlock(&eint_lock); - - if (soc_is_exynos5250()) - s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf)); - else - s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf)); - - return 0; -} - -static struct irq_chip exynos_irq_eint = { - .name = "exynos-eint", - .irq_mask = exynos_irq_eint_mask, - .irq_unmask = exynos_irq_eint_unmask, - .irq_mask_ack = exynos_irq_eint_maskack, - .irq_ack = exynos_irq_eint_ack, - .irq_set_type = exynos_irq_eint_set_type, -#ifdef CONFIG_PM - .irq_set_wake = s3c_irqext_wake, -#endif -}; - -/* - * exynos4_irq_demux_eint - * - * This function demuxes the IRQ from from EINTs 16 to 31. - * It is designed to be inlined into the specific handler - * s5p_irq_demux_eintX_Y. - * - * Each EINT pend/mask registers handle eight of them. - */ -static inline void exynos_irq_demux_eint(unsigned int start) -{ - unsigned int irq; - - u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start)); - u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start)); - - status &= ~mask; - status &= 0xff; - - while (status) { - irq = fls(status) - 1; - generic_handle_irq(irq + start); - status &= ~(1 << irq); - } -} - -static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) -{ - struct irq_chip *chip = irq_get_chip(irq); - chained_irq_enter(chip, desc); - exynos_irq_demux_eint(IRQ_EINT(16)); - exynos_irq_demux_eint(IRQ_EINT(24)); - chained_irq_exit(chip, desc); -} - -static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc) -{ - u32 *irq_data = irq_get_handler_data(irq); - struct irq_chip *chip = irq_get_chip(irq); - - chained_irq_enter(chip, desc); - generic_handle_irq(*irq_data); - chained_irq_exit(chip, desc); -} - -static int __init exynos_init_irq_eint(void) -{ - int irq; - -#ifdef CONFIG_PINCTRL_SAMSUNG - /* - * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf - * functionality along with support for external gpio and wakeup - * interrupts. If the samsung pinctrl driver is enabled and includes - * the wakeup interrupt support, then the setting up external wakeup - * interrupts here can be skipped. This check here is temporary to - * allow exynos4 platforms that do not use Samsung pinctrl driver to - * co-exist with platforms that do. When all of the Samsung Exynos4 - * platforms switch over to using the pinctrl driver, the wakeup - * interrupt support code here can be completely removed. - */ - static const struct of_device_id exynos_pinctrl_ids[] = { - { .compatible = "samsung,exynos4210-pinctrl", }, - { .compatible = "samsung,exynos4x12-pinctrl", }, - { .compatible = "samsung,exynos5250-pinctrl", }, - }; - struct device_node *pctrl_np, *wkup_np; - const char *wkup_compat = "samsung,exynos4210-wakeup-eint"; - - for_each_matching_node(pctrl_np, exynos_pinctrl_ids) { - if (of_device_is_available(pctrl_np)) { - wkup_np = of_find_compatible_node(pctrl_np, NULL, - wkup_compat); - if (wkup_np) - return -ENODEV; - } - } -#endif - if (soc_is_exynos5440()) - return 0; - - if (soc_is_exynos5250()) - exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K); - else - exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K); - - if (exynos_eint_base == NULL) { - pr_err("unable to ioremap for EINT base address\n"); - return -ENOMEM; - } - - for (irq = 0 ; irq <= 31 ; irq++) { - irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint, - handle_level_irq); - set_irq_flags(IRQ_EINT(irq), IRQF_VALID); - } - - irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31); - - for (irq = 0 ; irq <= 15 ; irq++) { - eint0_15_data[irq] = IRQ_EINT(irq); - - if (soc_is_exynos5250()) { - irq_set_handler_data(exynos5_eint0_15_src_int[irq], - &eint0_15_data[irq]); - irq_set_chained_handler(exynos5_eint0_15_src_int[irq], - exynos_irq_eint0_15); - } else { - irq_set_handler_data(exynos4_eint0_15_src_int[irq], - &eint0_15_data[irq]); - irq_set_chained_handler(exynos4_eint0_15_src_int[irq], - exynos_irq_eint0_15); - } - } - - return 0; -} -arch_initcall(exynos_init_irq_eint); - -static struct resource exynos4_pmu_resource[] = { - DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU), - DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1), -#if defined(CONFIG_SOC_EXYNOS4412) - DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2), - DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3), -#endif -}; - -static struct platform_device exynos4_device_pmu = { - .name = "arm-pmu", - .num_resources = ARRAY_SIZE(exynos4_pmu_resource), - .resource = exynos4_pmu_resource, -}; - -static int __init exynos_armpmu_init(void) -{ - if (!of_have_populated_dt()) { - if (soc_is_exynos4210() || soc_is_exynos4212()) - exynos4_device_pmu.num_resources = 2; - platform_device_register(&exynos4_device_pmu); - } - - return 0; -} -arch_initcall(exynos_armpmu_init); diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 60dd35cc01a..38d45fd23be 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -19,9 +19,7 @@ void exynos_init_time(void); extern unsigned long xxti_f, xusbxti_f; struct map_desc; -void exynos_init_io(struct map_desc *mach_desc, int size); -void exynos4_init_irq(void); -void exynos5_init_irq(void); +void exynos_init_io(void); void exynos4_restart(char mode, const char *cmd); void exynos5_restart(char mode, const char *cmd); void exynos_init_late(void); @@ -32,6 +30,8 @@ void exynos4_clk_register_fixed_ext(unsigned long, unsigned long); void exynos_firmware_init(void); +void exynos_set_timer_source(u8 channels); + #ifdef CONFIG_PM_GENERIC_DOMAINS int exynos_pm_late_initcall(void); #else diff --git a/arch/arm/mach-exynos/dev-ahci.c b/arch/arm/mach-exynos/dev-ahci.c deleted file mode 100644 index ce1aad3eeeb..00000000000 --- a/arch/arm/mach-exynos/dev-ahci.c +++ /dev/null @@ -1,255 +0,0 @@ -/* linux/arch/arm/mach-exynos4/dev-ahci.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 - AHCI support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/dma-mapping.h> -#include <linux/platform_device.h> -#include <linux/ahci_platform.h> - -#include <plat/cpu.h> - -#include <mach/irqs.h> -#include <mach/map.h> -#include <mach/regs-pmu.h> - -/* PHY Control Register */ -#define SATA_CTRL0 0x0 -/* PHY Link Control Register */ -#define SATA_CTRL1 0x4 -/* PHY Status Register */ -#define SATA_PHY_STATUS 0x8 - -#define SATA_CTRL0_RX_DATA_VALID(x) (x << 27) -#define SATA_CTRL0_SPEED_MODE (1 << 26) -#define SATA_CTRL0_M_PHY_CAL (1 << 19) -#define SATA_CTRL0_PHY_CMU_RST_N (1 << 10) -#define SATA_CTRL0_M_PHY_LN_RST_N (1 << 9) -#define SATA_CTRL0_PHY_POR_N (1 << 8) - -#define SATA_CTRL1_RST_PMALIVE_N (1 << 8) -#define SATA_CTRL1_RST_RXOOB_N (1 << 7) -#define SATA_CTRL1_RST_RX_N (1 << 6) -#define SATA_CTRL1_RST_TX_N (1 << 5) - -#define SATA_PHY_STATUS_CMU_OK (1 << 18) -#define SATA_PHY_STATUS_LANE_OK (1 << 16) - -#define LANE0 0x200 -#define COM_LANE 0xA00 - -#define HOST_PORTS_IMPL 0xC -#define SCLK_SATA_FREQ (67 * MHZ) - -static void __iomem *phy_base, *phy_ctrl; - -struct phy_reg { - u8 reg; - u8 val; -}; - -/* SATA PHY setup */ -static const struct phy_reg exynos4_sataphy_cmu[] = { - { 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 }, - { 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 }, - { 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 }, - { 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 }, - { 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 }, - { 0x6b, 0xc8 }, { 0x6c, 0x06 }, -}; - -static const struct phy_reg exynos4_sataphy_lane[] = { - { 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 }, - { 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 }, - { 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e }, - { 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 }, - { 0x51, 0x0f }, -}; - -static const struct phy_reg exynos4_sataphy_comlane[] = { - { 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d }, - { 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 }, - { 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 }, - { 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 }, - { 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 }, - { 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 }, - { 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 }, - { 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d }, - { 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 }, - { 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 }, - { 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 }, - { 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff }, - { 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 }, - { 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 }, -}; - -static int wait_for_phy_ready(void __iomem *reg, unsigned long bit) -{ - unsigned long timeout; - - /* wait for maximum of 3 sec */ - timeout = jiffies + msecs_to_jiffies(3000); - while (!(__raw_readl(reg) & bit)) { - if (time_after(jiffies, timeout)) - return -1; - cpu_relax(); - } - return 0; -} - -static int ahci_phy_init(void __iomem *mmio) -{ - int i, ctrl0; - - for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++) - __raw_writeb(exynos4_sataphy_cmu[i].val, - phy_base + (exynos4_sataphy_cmu[i].reg * 4)); - - for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++) - __raw_writeb(exynos4_sataphy_lane[i].val, - phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4); - - for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++) - __raw_writeb(exynos4_sataphy_comlane[i].val, - phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4); - - __raw_writeb(0x07, phy_base); - - ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0); - ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N; - __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0); - - if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS, - SATA_PHY_STATUS_CMU_OK) < 0) { - printk(KERN_ERR "PHY CMU not ready\n"); - return -EBUSY; - } - - __raw_writeb(0x03, phy_base + (COM_LANE * 4)); - - ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0); - ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N; - __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0); - - if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS, - SATA_PHY_STATUS_LANE_OK) < 0) { - printk(KERN_ERR "PHY LANE not ready\n"); - return -EBUSY; - } - - ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0); - ctrl0 |= SATA_CTRL0_M_PHY_CAL; - __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0); - - return 0; -} - -static int exynos4_ahci_init(struct device *dev, void __iomem *mmio) -{ - struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata; - int val, ret; - - phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K); - if (!phy_base) { - dev_err(dev, "failed to allocate memory for SATA PHY\n"); - return -ENOMEM; - } - - phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16); - if (!phy_ctrl) { - dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n"); - ret = -ENOMEM; - goto err1; - } - - clk_sata = clk_get(dev, "sata"); - if (IS_ERR(clk_sata)) { - dev_err(dev, "failed to get sata clock\n"); - ret = PTR_ERR(clk_sata); - clk_sata = NULL; - goto err2; - - } - clk_enable(clk_sata); - - clk_sataphy = clk_get(dev, "sataphy"); - if (IS_ERR(clk_sataphy)) { - dev_err(dev, "failed to get sataphy clock\n"); - ret = PTR_ERR(clk_sataphy); - clk_sataphy = NULL; - goto err3; - } - clk_enable(clk_sataphy); - - clk_sclk_sata = clk_get(dev, "sclk_sata"); - if (IS_ERR(clk_sclk_sata)) { - dev_err(dev, "failed to get sclk_sata\n"); - ret = PTR_ERR(clk_sclk_sata); - clk_sclk_sata = NULL; - goto err4; - } - clk_enable(clk_sclk_sata); - clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ); - - __raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL); - - /* Enable PHY link control */ - val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N | - SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N; - __raw_writel(val, phy_ctrl + SATA_CTRL1); - - /* Set communication speed as 3Gbps and enable PHY power */ - val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE | - SATA_CTRL0_PHY_POR_N; - __raw_writel(val, phy_ctrl + SATA_CTRL0); - - /* Port0 is available */ - __raw_writel(0x1, mmio + HOST_PORTS_IMPL); - - return ahci_phy_init(mmio); - -err4: - clk_disable(clk_sataphy); - clk_put(clk_sataphy); -err3: - clk_disable(clk_sata); - clk_put(clk_sata); -err2: - iounmap(phy_ctrl); -err1: - iounmap(phy_base); - - return ret; -} - -static struct ahci_platform_data exynos4_ahci_pdata = { - .init = exynos4_ahci_init, -}; - -static struct resource exynos4_ahci_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_SATA, SZ_64K), - [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_SATA), -}; - -static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32); - -struct platform_device exynos4_device_ahci = { - .name = "ahci", - .id = -1, - .resource = exynos4_ahci_resource, - .num_resources = ARRAY_SIZE(exynos4_ahci_resource), - .dev = { - .platform_data = &exynos4_ahci_pdata, - .dma_mask = &exynos4_ahci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c deleted file mode 100644 index c662c89794b..00000000000 --- a/arch/arm/mach-exynos/dev-audio.c +++ /dev/null @@ -1,254 +0,0 @@ -/* linux/arch/arm/mach-exynos4/dev-audio.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Copyright (c) 2010 Samsung Electronics Co. Ltd - * Jaswinder Singh <jassi.brar@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <linux/gpio.h> -#include <linux/platform_data/asoc-s3c.h> - -#include <plat/gpio-cfg.h> - -#include <mach/map.h> -#include <mach/dma.h> -#include <mach/irqs.h> - -#define EXYNOS4_AUDSS_INT_MEM (0x03000000) - -static int exynos4_cfg_i2s(struct platform_device *pdev) -{ - /* configure GPIO for i2s port */ - switch (pdev->id) { - case 0: - s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2)); - break; - case 1: - s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2)); - break; - case 2: - s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4)); - break; - default: - printk(KERN_ERR "Invalid Device %d\n", pdev->id); - return -EINVAL; - } - - return 0; -} - -static struct s3c_audio_pdata i2sv5_pdata = { - .cfg_gpio = exynos4_cfg_i2s, - .type = { - .i2s = { - .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI - | QUIRK_NEED_RSTCLR, - .idma_addr = EXYNOS4_AUDSS_INT_MEM, - }, - }, -}; - -static struct resource exynos4_i2s0_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S0, SZ_256), - [1] = DEFINE_RES_DMA(DMACH_I2S0_TX), - [2] = DEFINE_RES_DMA(DMACH_I2S0_RX), - [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX), -}; - -struct platform_device exynos4_device_i2s0 = { - .name = "samsung-i2s", - .id = 0, - .num_resources = ARRAY_SIZE(exynos4_i2s0_resource), - .resource = exynos4_i2s0_resource, - .dev = { - .platform_data = &i2sv5_pdata, - }, -}; - -static struct s3c_audio_pdata i2sv3_pdata = { - .cfg_gpio = exynos4_cfg_i2s, - .type = { - .i2s = { - .quirks = QUIRK_NO_MUXPSR, - }, - }, -}; - -static struct resource exynos4_i2s1_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S1, SZ_256), - [1] = DEFINE_RES_DMA(DMACH_I2S1_TX), - [2] = DEFINE_RES_DMA(DMACH_I2S1_RX), -}; - -struct platform_device exynos4_device_i2s1 = { - .name = "samsung-i2s", - .id = 1, - .num_resources = ARRAY_SIZE(exynos4_i2s1_resource), - .resource = exynos4_i2s1_resource, - .dev = { - .platform_data = &i2sv3_pdata, - }, -}; - -static struct resource exynos4_i2s2_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S2, SZ_256), - [1] = DEFINE_RES_DMA(DMACH_I2S2_TX), - [2] = DEFINE_RES_DMA(DMACH_I2S2_RX), -}; - -struct platform_device exynos4_device_i2s2 = { - .name = "samsung-i2s", - .id = 2, - .num_resources = ARRAY_SIZE(exynos4_i2s2_resource), - .resource = exynos4_i2s2_resource, - .dev = { - .platform_data = &i2sv3_pdata, - }, -}; - -/* PCM Controller platform_devices */ - -static int exynos4_pcm_cfg_gpio(struct platform_device *pdev) -{ - switch (pdev->id) { - case 0: - s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3)); - break; - case 1: - s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3)); - break; - case 2: - s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3)); - break; - default: - printk(KERN_DEBUG "Invalid PCM Controller number!"); - return -EINVAL; - } - - return 0; -} - -static struct s3c_audio_pdata s3c_pcm_pdata = { - .cfg_gpio = exynos4_pcm_cfg_gpio, -}; - -static struct resource exynos4_pcm0_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM0, SZ_256), - [1] = DEFINE_RES_DMA(DMACH_PCM0_TX), - [2] = DEFINE_RES_DMA(DMACH_PCM0_RX), -}; - -struct platform_device exynos4_device_pcm0 = { - .name = "samsung-pcm", - .id = 0, - .num_resources = ARRAY_SIZE(exynos4_pcm0_resource), - .resource = exynos4_pcm0_resource, - .dev = { - .platform_data = &s3c_pcm_pdata, - }, -}; - -static struct resource exynos4_pcm1_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM1, SZ_256), - [1] = DEFINE_RES_DMA(DMACH_PCM1_TX), - [2] = DEFINE_RES_DMA(DMACH_PCM1_RX), -}; - -struct platform_device exynos4_device_pcm1 = { - .name = "samsung-pcm", - .id = 1, - .num_resources = ARRAY_SIZE(exynos4_pcm1_resource), - .resource = exynos4_pcm1_resource, - .dev = { - .platform_data = &s3c_pcm_pdata, - }, -}; - -static struct resource exynos4_pcm2_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM2, SZ_256), - [1] = DEFINE_RES_DMA(DMACH_PCM2_TX), - [2] = DEFINE_RES_DMA(DMACH_PCM2_RX), -}; - -struct platform_device exynos4_device_pcm2 = { - .name = "samsung-pcm", - .id = 2, - .num_resources = ARRAY_SIZE(exynos4_pcm2_resource), - .resource = exynos4_pcm2_resource, - .dev = { - .platform_data = &s3c_pcm_pdata, - }, -}; - -/* AC97 Controller platform devices */ - -static int exynos4_ac97_cfg_gpio(struct platform_device *pdev) -{ - return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4)); -} - -static struct resource exynos4_ac97_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_AC97, SZ_256), - [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT), - [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN), - [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN), - [4] = DEFINE_RES_IRQ(EXYNOS4_IRQ_AC97), -}; - -static struct s3c_audio_pdata s3c_ac97_pdata = { - .cfg_gpio = exynos4_ac97_cfg_gpio, -}; - -static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32); - -struct platform_device exynos4_device_ac97 = { - .name = "samsung-ac97", - .id = -1, - .num_resources = ARRAY_SIZE(exynos4_ac97_resource), - .resource = exynos4_ac97_resource, - .dev = { - .platform_data = &s3c_ac97_pdata, - .dma_mask = &exynos4_ac97_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -/* S/PDIF Controller platform_device */ - -static int exynos4_spdif_cfg_gpio(struct platform_device *pdev) -{ - s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4)); - - return 0; -} - -static struct resource exynos4_spdif_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_SPDIF, SZ_256), - [1] = DEFINE_RES_DMA(DMACH_SPDIF), -}; - -static struct s3c_audio_pdata samsung_spdif_pdata = { - .cfg_gpio = exynos4_spdif_cfg_gpio, -}; - -static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32); - -struct platform_device exynos4_device_spdif = { - .name = "samsung-spdif", - .id = -1, - .num_resources = ARRAY_SIZE(exynos4_spdif_resource), - .resource = exynos4_spdif_resource, - .dev = { - .platform_data = &samsung_spdif_pdata, - .dma_mask = &exynos4_spdif_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; diff --git a/arch/arm/mach-exynos/dev-ohci.c b/arch/arm/mach-exynos/dev-ohci.c deleted file mode 100644 index d5bc129e6bb..00000000000 --- a/arch/arm/mach-exynos/dev-ohci.c +++ /dev/null @@ -1,52 +0,0 @@ -/* linux/arch/arm/mach-exynos/dev-ohci.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS - OHCI support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/dma-mapping.h> -#include <linux/platform_device.h> -#include <linux/platform_data/usb-ohci-exynos.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/devs.h> -#include <plat/usb-phy.h> - -static struct resource exynos4_ohci_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_OHCI, SZ_256), - [1] = DEFINE_RES_IRQ(IRQ_USB_HOST), -}; - -static u64 exynos4_ohci_dma_mask = DMA_BIT_MASK(32); - -struct platform_device exynos4_device_ohci = { - .name = "exynos-ohci", - .id = -1, - .num_resources = ARRAY_SIZE(exynos4_ohci_resource), - .resource = exynos4_ohci_resource, - .dev = { - .dma_mask = &exynos4_ohci_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - } -}; - -void __init exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd) -{ - struct exynos4_ohci_platdata *npd; - - npd = s3c_set_platdata(pd, sizeof(struct exynos4_ohci_platdata), - &exynos4_device_ohci); - - if (!npd->phy_init) - npd->phy_init = s5p_usb_phy_init; - if (!npd->phy_exit) - npd->phy_exit = s5p_usb_phy_exit; -} diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c deleted file mode 100644 index c48aff02c78..00000000000 --- a/arch/arm/mach-exynos/dev-uart.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Base EXYNOS UART resource and device definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/ioport.h> -#include <linux/platform_device.h> - -#include <asm/mach/arch.h> -#include <asm/mach/irq.h> -#include <mach/hardware.h> -#include <mach/map.h> -#include <mach/irqs.h> - -#include <plat/devs.h> - -#define EXYNOS_UART_RESOURCE(_series, _nr) \ -static struct resource exynos##_series##_uart##_nr##_resource[] = { \ - [0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART), \ - [1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr), \ -}; - -EXYNOS_UART_RESOURCE(4, 0) -EXYNOS_UART_RESOURCE(4, 1) -EXYNOS_UART_RESOURCE(4, 2) -EXYNOS_UART_RESOURCE(4, 3) - -struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = { - [0] = { - .resources = exynos4_uart0_resource, - .nr_resources = ARRAY_SIZE(exynos4_uart0_resource), - }, - [1] = { - .resources = exynos4_uart1_resource, - .nr_resources = ARRAY_SIZE(exynos4_uart1_resource), - }, - [2] = { - .resources = exynos4_uart2_resource, - .nr_resources = ARRAY_SIZE(exynos4_uart2_resource), - }, - [3] = { - .resources = exynos4_uart3_resource, - .nr_resources = ARRAY_SIZE(exynos4_uart3_resource), - }, -}; diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c deleted file mode 100644 index 87e07d6fc61..00000000000 --- a/arch/arm/mach-exynos/dma.c +++ /dev/null @@ -1,322 +0,0 @@ -/* linux/arch/arm/mach-exynos4/dma.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Copyright (C) 2010 Samsung Electronics Co. Ltd. - * Jaswinder Singh <jassi.brar@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <linux/dma-mapping.h> -#include <linux/amba/bus.h> -#include <linux/amba/pl330.h> -#include <linux/of.h> - -#include <asm/irq.h> -#include <plat/devs.h> -#include <plat/irqs.h> -#include <plat/cpu.h> - -#include <mach/map.h> -#include <mach/irqs.h> -#include <mach/dma.h> - -static u8 exynos4210_pdma0_peri[] = { - DMACH_PCM0_RX, - DMACH_PCM0_TX, - DMACH_PCM2_RX, - DMACH_PCM2_TX, - DMACH_MSM_REQ0, - DMACH_MSM_REQ2, - DMACH_SPI0_RX, - DMACH_SPI0_TX, - DMACH_SPI2_RX, - DMACH_SPI2_TX, - DMACH_I2S0S_TX, - DMACH_I2S0_RX, - DMACH_I2S0_TX, - DMACH_I2S2_RX, - DMACH_I2S2_TX, - DMACH_UART0_RX, - DMACH_UART0_TX, - DMACH_UART2_RX, - DMACH_UART2_TX, - DMACH_UART4_RX, - DMACH_UART4_TX, - DMACH_SLIMBUS0_RX, - DMACH_SLIMBUS0_TX, - DMACH_SLIMBUS2_RX, - DMACH_SLIMBUS2_TX, - DMACH_SLIMBUS4_RX, - DMACH_SLIMBUS4_TX, - DMACH_AC97_MICIN, - DMACH_AC97_PCMIN, - DMACH_AC97_PCMOUT, -}; - -static u8 exynos4212_pdma0_peri[] = { - DMACH_PCM0_RX, - DMACH_PCM0_TX, - DMACH_PCM2_RX, - DMACH_PCM2_TX, - DMACH_MIPI_HSI0, - DMACH_MIPI_HSI1, - DMACH_SPI0_RX, - DMACH_SPI0_TX, - DMACH_SPI2_RX, - DMACH_SPI2_TX, - DMACH_I2S0S_TX, - DMACH_I2S0_RX, - DMACH_I2S0_TX, - DMACH_I2S2_RX, - DMACH_I2S2_TX, - DMACH_UART0_RX, - DMACH_UART0_TX, - DMACH_UART2_RX, - DMACH_UART2_TX, - DMACH_UART4_RX, - DMACH_UART4_TX, - DMACH_SLIMBUS0_RX, - DMACH_SLIMBUS0_TX, - DMACH_SLIMBUS2_RX, - DMACH_SLIMBUS2_TX, - DMACH_SLIMBUS4_RX, - DMACH_SLIMBUS4_TX, - DMACH_AC97_MICIN, - DMACH_AC97_PCMIN, - DMACH_AC97_PCMOUT, - DMACH_MIPI_HSI4, - DMACH_MIPI_HSI5, -}; - -static u8 exynos5250_pdma0_peri[] = { - DMACH_PCM0_RX, - DMACH_PCM0_TX, - DMACH_PCM2_RX, - DMACH_PCM2_TX, - DMACH_SPI0_RX, - DMACH_SPI0_TX, - DMACH_SPI2_RX, - DMACH_SPI2_TX, - DMACH_I2S0S_TX, - DMACH_I2S0_RX, - DMACH_I2S0_TX, - DMACH_I2S2_RX, - DMACH_I2S2_TX, - DMACH_UART0_RX, - DMACH_UART0_TX, - DMACH_UART2_RX, - DMACH_UART2_TX, - DMACH_UART4_RX, - DMACH_UART4_TX, - DMACH_SLIMBUS0_RX, - DMACH_SLIMBUS0_TX, - DMACH_SLIMBUS2_RX, - DMACH_SLIMBUS2_TX, - DMACH_SLIMBUS4_RX, - DMACH_SLIMBUS4_TX, - DMACH_AC97_MICIN, - DMACH_AC97_PCMIN, - DMACH_AC97_PCMOUT, - DMACH_MIPI_HSI0, - DMACH_MIPI_HSI2, - DMACH_MIPI_HSI4, - DMACH_MIPI_HSI6, -}; - -static struct dma_pl330_platdata exynos_pdma0_pdata; - -static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330, - EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata); - -static u8 exynos4210_pdma1_peri[] = { - DMACH_PCM0_RX, - DMACH_PCM0_TX, - DMACH_PCM1_RX, - DMACH_PCM1_TX, - DMACH_MSM_REQ1, - DMACH_MSM_REQ3, - DMACH_SPI1_RX, - DMACH_SPI1_TX, - DMACH_I2S0S_TX, - DMACH_I2S0_RX, - DMACH_I2S0_TX, - DMACH_I2S1_RX, - DMACH_I2S1_TX, - DMACH_UART0_RX, - DMACH_UART0_TX, - DMACH_UART1_RX, - DMACH_UART1_TX, - DMACH_UART3_RX, - DMACH_UART3_TX, - DMACH_SLIMBUS1_RX, - DMACH_SLIMBUS1_TX, - DMACH_SLIMBUS3_RX, - DMACH_SLIMBUS3_TX, - DMACH_SLIMBUS5_RX, - DMACH_SLIMBUS5_TX, -}; - -static u8 exynos4212_pdma1_peri[] = { - DMACH_PCM0_RX, - DMACH_PCM0_TX, - DMACH_PCM1_RX, - DMACH_PCM1_TX, - DMACH_MIPI_HSI2, - DMACH_MIPI_HSI3, - DMACH_SPI1_RX, - DMACH_SPI1_TX, - DMACH_I2S0S_TX, - DMACH_I2S0_RX, - DMACH_I2S0_TX, - DMACH_I2S1_RX, - DMACH_I2S1_TX, - DMACH_UART0_RX, - DMACH_UART0_TX, - DMACH_UART1_RX, - DMACH_UART1_TX, - DMACH_UART3_RX, - DMACH_UART3_TX, - DMACH_SLIMBUS1_RX, - DMACH_SLIMBUS1_TX, - DMACH_SLIMBUS3_RX, - DMACH_SLIMBUS3_TX, - DMACH_SLIMBUS5_RX, - DMACH_SLIMBUS5_TX, - DMACH_SLIMBUS0AUX_RX, - DMACH_SLIMBUS0AUX_TX, - DMACH_SPDIF, - DMACH_MIPI_HSI6, - DMACH_MIPI_HSI7, -}; - -static u8 exynos5250_pdma1_peri[] = { - DMACH_PCM0_RX, - DMACH_PCM0_TX, - DMACH_PCM1_RX, - DMACH_PCM1_TX, - DMACH_SPI1_RX, - DMACH_SPI1_TX, - DMACH_PWM, - DMACH_SPDIF, - DMACH_I2S0S_TX, - DMACH_I2S0_RX, - DMACH_I2S0_TX, - DMACH_I2S1_RX, - DMACH_I2S1_TX, - DMACH_UART0_RX, - DMACH_UART0_TX, - DMACH_UART1_RX, - DMACH_UART1_TX, - DMACH_UART3_RX, - DMACH_UART3_TX, - DMACH_SLIMBUS1_RX, - DMACH_SLIMBUS1_TX, - DMACH_SLIMBUS3_RX, - DMACH_SLIMBUS3_TX, - DMACH_SLIMBUS5_RX, - DMACH_SLIMBUS5_TX, - DMACH_SLIMBUS0AUX_RX, - DMACH_SLIMBUS0AUX_TX, - DMACH_DISP1, - DMACH_MIPI_HSI1, - DMACH_MIPI_HSI3, - DMACH_MIPI_HSI5, - DMACH_MIPI_HSI7, -}; - -static struct dma_pl330_platdata exynos_pdma1_pdata; - -static AMBA_AHB_DEVICE(exynos_pdma1, "dma-pl330.1", 0x00041330, - EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata); - -static u8 mdma_peri[] = { - DMACH_MTOM_0, - DMACH_MTOM_1, - DMACH_MTOM_2, - DMACH_MTOM_3, - DMACH_MTOM_4, - DMACH_MTOM_5, - DMACH_MTOM_6, - DMACH_MTOM_7, -}; - -static struct dma_pl330_platdata exynos_mdma1_pdata = { - .nr_valid_peri = ARRAY_SIZE(mdma_peri), - .peri_id = mdma_peri, -}; - -static AMBA_AHB_DEVICE(exynos_mdma1, "dma-pl330.2", 0x00041330, - EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata); - -static int __init exynos_dma_init(void) -{ - if (of_have_populated_dt()) - return 0; - - if (soc_is_exynos4210()) { - exynos_pdma0_pdata.nr_valid_peri = - ARRAY_SIZE(exynos4210_pdma0_peri); - exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri; - exynos_pdma1_pdata.nr_valid_peri = - ARRAY_SIZE(exynos4210_pdma1_peri); - exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri; - - if (samsung_rev() == EXYNOS4210_REV_0) - exynos_mdma1_device.res.start = EXYNOS4_PA_S_MDMA1; - } else if (soc_is_exynos4212() || soc_is_exynos4412()) { - exynos_pdma0_pdata.nr_valid_peri = - ARRAY_SIZE(exynos4212_pdma0_peri); - exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri; - exynos_pdma1_pdata.nr_valid_peri = - ARRAY_SIZE(exynos4212_pdma1_peri); - exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri; - } else if (soc_is_exynos5250()) { - exynos_pdma0_pdata.nr_valid_peri = - ARRAY_SIZE(exynos5250_pdma0_peri); - exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri; - exynos_pdma1_pdata.nr_valid_peri = - ARRAY_SIZE(exynos5250_pdma1_peri); - exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri; - - exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0; - exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K; - exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0; - exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1; - exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K; - exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1; - exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1; - exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K; - exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1; - } - - dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask); - dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask); - dma_cap_set(DMA_PRIVATE, exynos_pdma0_pdata.cap_mask); - amba_device_register(&exynos_pdma0_device, &iomem_resource); - - dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask); - dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask); - dma_cap_set(DMA_PRIVATE, exynos_pdma1_pdata.cap_mask); - amba_device_register(&exynos_pdma1_device, &iomem_resource); - - dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask); - amba_device_register(&exynos_mdma1_device, &iomem_resource); - - return 0; -} -arch_initcall(exynos_dma_init); diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index ed11f100d47..932129ef26c 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -48,20 +48,18 @@ static const struct firmware_ops exynos_firmware_ops = { void __init exynos_firmware_init(void) { - if (of_have_populated_dt()) { - struct device_node *nd; - const __be32 *addr; + struct device_node *nd; + const __be32 *addr; - nd = of_find_compatible_node(NULL, NULL, - "samsung,secure-firmware"); - if (!nd) - return; + nd = of_find_compatible_node(NULL, NULL, + "samsung,secure-firmware"); + if (!nd) + return; - addr = of_get_address(nd, 0, NULL, NULL); - if (!addr) { - pr_err("%s: No address specified.\n", __func__); - return; - } + addr = of_get_address(nd, 0, NULL, NULL); + if (!addr) { + pr_err("%s: No address specified.\n", __func__); + return; } pr_info("Running under secure firmware.\n"); diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h deleted file mode 100644 index eb24f1eb8e3..00000000000 --- a/arch/arm/mach-exynos/include/mach/gpio.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS - GPIO lib support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_GPIO_H -#define __ASM_ARCH_GPIO_H __FILE__ - -/* Macro for EXYNOS GPIO numbering */ - -#define EXYNOS_GPIO_NEXT(__gpio) \ - ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) - -/* EXYNOS4 GPIO bank sizes */ - -#define EXYNOS4_GPIO_A0_NR (8) -#define EXYNOS4_GPIO_A1_NR (6) -#define EXYNOS4_GPIO_B_NR (8) -#define EXYNOS4_GPIO_C0_NR (5) -#define EXYNOS4_GPIO_C1_NR (5) -#define EXYNOS4_GPIO_D0_NR (4) -#define EXYNOS4_GPIO_D1_NR (4) -#define EXYNOS4_GPIO_E0_NR (5) -#define EXYNOS4_GPIO_E1_NR (8) -#define EXYNOS4_GPIO_E2_NR (6) -#define EXYNOS4_GPIO_E3_NR (8) -#define EXYNOS4_GPIO_E4_NR (8) -#define EXYNOS4_GPIO_F0_NR (8) -#define EXYNOS4_GPIO_F1_NR (8) -#define EXYNOS4_GPIO_F2_NR (8) -#define EXYNOS4_GPIO_F3_NR (6) -#define EXYNOS4_GPIO_J0_NR (8) -#define EXYNOS4_GPIO_J1_NR (5) -#define EXYNOS4_GPIO_K0_NR (7) -#define EXYNOS4_GPIO_K1_NR (7) -#define EXYNOS4_GPIO_K2_NR (7) -#define EXYNOS4_GPIO_K3_NR (7) -#define EXYNOS4_GPIO_L0_NR (8) -#define EXYNOS4_GPIO_L1_NR (3) -#define EXYNOS4_GPIO_L2_NR (8) -#define EXYNOS4_GPIO_X0_NR (8) -#define EXYNOS4_GPIO_X1_NR (8) -#define EXYNOS4_GPIO_X2_NR (8) -#define EXYNOS4_GPIO_X3_NR (8) -#define EXYNOS4_GPIO_Y0_NR (6) -#define EXYNOS4_GPIO_Y1_NR (4) -#define EXYNOS4_GPIO_Y2_NR (6) -#define EXYNOS4_GPIO_Y3_NR (8) -#define EXYNOS4_GPIO_Y4_NR (8) -#define EXYNOS4_GPIO_Y5_NR (8) -#define EXYNOS4_GPIO_Y6_NR (8) -#define EXYNOS4_GPIO_Z_NR (7) - -/* EXYNOS4 GPIO bank numbers */ - -enum exynos4_gpio_number { - EXYNOS4_GPIO_A0_START = 0, - EXYNOS4_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A0), - EXYNOS4_GPIO_B_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A1), - EXYNOS4_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_B), - EXYNOS4_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0), - EXYNOS4_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1), - EXYNOS4_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0), - EXYNOS4_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1), - EXYNOS4_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0), - EXYNOS4_GPIO_E2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1), - EXYNOS4_GPIO_E3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2), - EXYNOS4_GPIO_E4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3), - EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4), - EXYNOS4_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0), - EXYNOS4_GPIO_F2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1), - EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2), - EXYNOS4_GPIO_J0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F3), - EXYNOS4_GPIO_J1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J0), - EXYNOS4_GPIO_K0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J1), - EXYNOS4_GPIO_K1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K0), - EXYNOS4_GPIO_K2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K1), - EXYNOS4_GPIO_K3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K2), - EXYNOS4_GPIO_L0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K3), - EXYNOS4_GPIO_L1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L0), - EXYNOS4_GPIO_L2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L1), - EXYNOS4_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L2), - EXYNOS4_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X0), - EXYNOS4_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X1), - EXYNOS4_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X2), - EXYNOS4_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X3), - EXYNOS4_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y0), - EXYNOS4_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y1), - EXYNOS4_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y2), - EXYNOS4_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y3), - EXYNOS4_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y4), - EXYNOS4_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y5), - EXYNOS4_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6), -}; - -/* EXYNOS4 GPIO number definitions */ - -#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr)) -#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr)) -#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr)) -#define EXYNOS4_GPC0(_nr) (EXYNOS4_GPIO_C0_START + (_nr)) -#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr)) -#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr)) -#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr)) -#define EXYNOS4_GPE0(_nr) (EXYNOS4_GPIO_E0_START + (_nr)) -#define EXYNOS4_GPE1(_nr) (EXYNOS4_GPIO_E1_START + (_nr)) -#define EXYNOS4_GPE2(_nr) (EXYNOS4_GPIO_E2_START + (_nr)) -#define EXYNOS4_GPE3(_nr) (EXYNOS4_GPIO_E3_START + (_nr)) -#define EXYNOS4_GPE4(_nr) (EXYNOS4_GPIO_E4_START + (_nr)) -#define EXYNOS4_GPF0(_nr) (EXYNOS4_GPIO_F0_START + (_nr)) -#define EXYNOS4_GPF1(_nr) (EXYNOS4_GPIO_F1_START + (_nr)) -#define EXYNOS4_GPF2(_nr) (EXYNOS4_GPIO_F2_START + (_nr)) -#define EXYNOS4_GPF3(_nr) (EXYNOS4_GPIO_F3_START + (_nr)) -#define EXYNOS4_GPJ0(_nr) (EXYNOS4_GPIO_J0_START + (_nr)) -#define EXYNOS4_GPJ1(_nr) (EXYNOS4_GPIO_J1_START + (_nr)) -#define EXYNOS4_GPK0(_nr) (EXYNOS4_GPIO_K0_START + (_nr)) -#define EXYNOS4_GPK1(_nr) (EXYNOS4_GPIO_K1_START + (_nr)) -#define EXYNOS4_GPK2(_nr) (EXYNOS4_GPIO_K2_START + (_nr)) -#define EXYNOS4_GPK3(_nr) (EXYNOS4_GPIO_K3_START + (_nr)) -#define EXYNOS4_GPL0(_nr) (EXYNOS4_GPIO_L0_START + (_nr)) -#define EXYNOS4_GPL1(_nr) (EXYNOS4_GPIO_L1_START + (_nr)) -#define EXYNOS4_GPL2(_nr) (EXYNOS4_GPIO_L2_START + (_nr)) -#define EXYNOS4_GPX0(_nr) (EXYNOS4_GPIO_X0_START + (_nr)) -#define EXYNOS4_GPX1(_nr) (EXYNOS4_GPIO_X1_START + (_nr)) -#define EXYNOS4_GPX2(_nr) (EXYNOS4_GPIO_X2_START + (_nr)) -#define EXYNOS4_GPX3(_nr) (EXYNOS4_GPIO_X3_START + (_nr)) -#define EXYNOS4_GPY0(_nr) (EXYNOS4_GPIO_Y0_START + (_nr)) -#define EXYNOS4_GPY1(_nr) (EXYNOS4_GPIO_Y1_START + (_nr)) -#define EXYNOS4_GPY2(_nr) (EXYNOS4_GPIO_Y2_START + (_nr)) -#define EXYNOS4_GPY3(_nr) (EXYNOS4_GPIO_Y3_START + (_nr)) -#define EXYNOS4_GPY4(_nr) (EXYNOS4_GPIO_Y4_START + (_nr)) -#define EXYNOS4_GPY5(_nr) (EXYNOS4_GPIO_Y5_START + (_nr)) -#define EXYNOS4_GPY6(_nr) (EXYNOS4_GPIO_Y6_START + (_nr)) -#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr)) - -/* the end of the EXYNOS4 specific gpios */ - -#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1) - -/* EXYNOS5 GPIO bank sizes */ - -#define EXYNOS5_GPIO_A0_NR (8) -#define EXYNOS5_GPIO_A1_NR (6) -#define EXYNOS5_GPIO_A2_NR (8) -#define EXYNOS5_GPIO_B0_NR (5) -#define EXYNOS5_GPIO_B1_NR (5) -#define EXYNOS5_GPIO_B2_NR (4) -#define EXYNOS5_GPIO_B3_NR (4) -#define EXYNOS5_GPIO_C0_NR (7) -#define EXYNOS5_GPIO_C1_NR (4) -#define EXYNOS5_GPIO_C2_NR (7) -#define EXYNOS5_GPIO_C3_NR (7) -#define EXYNOS5_GPIO_C4_NR (7) -#define EXYNOS5_GPIO_D0_NR (4) -#define EXYNOS5_GPIO_D1_NR (8) -#define EXYNOS5_GPIO_Y0_NR (6) -#define EXYNOS5_GPIO_Y1_NR (4) -#define EXYNOS5_GPIO_Y2_NR (6) -#define EXYNOS5_GPIO_Y3_NR (8) -#define EXYNOS5_GPIO_Y4_NR (8) -#define EXYNOS5_GPIO_Y5_NR (8) -#define EXYNOS5_GPIO_Y6_NR (8) -#define EXYNOS5_GPIO_X0_NR (8) -#define EXYNOS5_GPIO_X1_NR (8) -#define EXYNOS5_GPIO_X2_NR (8) -#define EXYNOS5_GPIO_X3_NR (8) -#define EXYNOS5_GPIO_E0_NR (8) -#define EXYNOS5_GPIO_E1_NR (2) -#define EXYNOS5_GPIO_F0_NR (4) -#define EXYNOS5_GPIO_F1_NR (4) -#define EXYNOS5_GPIO_G0_NR (8) -#define EXYNOS5_GPIO_G1_NR (8) -#define EXYNOS5_GPIO_G2_NR (2) -#define EXYNOS5_GPIO_H0_NR (4) -#define EXYNOS5_GPIO_H1_NR (8) -#define EXYNOS5_GPIO_V0_NR (8) -#define EXYNOS5_GPIO_V1_NR (8) -#define EXYNOS5_GPIO_V2_NR (8) -#define EXYNOS5_GPIO_V3_NR (8) -#define EXYNOS5_GPIO_V4_NR (2) -#define EXYNOS5_GPIO_Z_NR (7) - -/* EXYNOS5 GPIO bank numbers */ - -enum exynos5_gpio_number { - EXYNOS5_GPIO_A0_START = 0, - EXYNOS5_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A0), - EXYNOS5_GPIO_A2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A1), - EXYNOS5_GPIO_B0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A2), - EXYNOS5_GPIO_B1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B0), - EXYNOS5_GPIO_B2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B1), - EXYNOS5_GPIO_B3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B2), - EXYNOS5_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B3), - EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0), - EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1), - EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2), - EXYNOS5_GPIO_C4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3), - EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4), - EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0), - EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1), - EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0), - EXYNOS5_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y1), - EXYNOS5_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y2), - EXYNOS5_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y3), - EXYNOS5_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y4), - EXYNOS5_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y5), - EXYNOS5_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y6), - EXYNOS5_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X0), - EXYNOS5_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X1), - EXYNOS5_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X2), - EXYNOS5_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X3), - EXYNOS5_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E0), - EXYNOS5_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E1), - EXYNOS5_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F0), - EXYNOS5_GPIO_G0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F1), - EXYNOS5_GPIO_G1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G0), - EXYNOS5_GPIO_G2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G1), - EXYNOS5_GPIO_H0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G2), - EXYNOS5_GPIO_H1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H0), - EXYNOS5_GPIO_V0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H1), - EXYNOS5_GPIO_V1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V0), - EXYNOS5_GPIO_V2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V1), - EXYNOS5_GPIO_V3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V2), - EXYNOS5_GPIO_V4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V3), - EXYNOS5_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V4), -}; - -/* EXYNOS5 GPIO number definitions */ - -#define EXYNOS5_GPA0(_nr) (EXYNOS5_GPIO_A0_START + (_nr)) -#define EXYNOS5_GPA1(_nr) (EXYNOS5_GPIO_A1_START + (_nr)) -#define EXYNOS5_GPA2(_nr) (EXYNOS5_GPIO_A2_START + (_nr)) -#define EXYNOS5_GPB0(_nr) (EXYNOS5_GPIO_B0_START + (_nr)) -#define EXYNOS5_GPB1(_nr) (EXYNOS5_GPIO_B1_START + (_nr)) -#define EXYNOS5_GPB2(_nr) (EXYNOS5_GPIO_B2_START + (_nr)) -#define EXYNOS5_GPB3(_nr) (EXYNOS5_GPIO_B3_START + (_nr)) -#define EXYNOS5_GPC0(_nr) (EXYNOS5_GPIO_C0_START + (_nr)) -#define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr)) -#define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr)) -#define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr)) -#define EXYNOS5_GPC4(_nr) (EXYNOS5_GPIO_C4_START + (_nr)) -#define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr)) -#define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr)) -#define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr)) -#define EXYNOS5_GPY1(_nr) (EXYNOS5_GPIO_Y1_START + (_nr)) -#define EXYNOS5_GPY2(_nr) (EXYNOS5_GPIO_Y2_START + (_nr)) -#define EXYNOS5_GPY3(_nr) (EXYNOS5_GPIO_Y3_START + (_nr)) -#define EXYNOS5_GPY4(_nr) (EXYNOS5_GPIO_Y4_START + (_nr)) -#define EXYNOS5_GPY5(_nr) (EXYNOS5_GPIO_Y5_START + (_nr)) -#define EXYNOS5_GPY6(_nr) (EXYNOS5_GPIO_Y6_START + (_nr)) -#define EXYNOS5_GPX0(_nr) (EXYNOS5_GPIO_X0_START + (_nr)) -#define EXYNOS5_GPX1(_nr) (EXYNOS5_GPIO_X1_START + (_nr)) -#define EXYNOS5_GPX2(_nr) (EXYNOS5_GPIO_X2_START + (_nr)) -#define EXYNOS5_GPX3(_nr) (EXYNOS5_GPIO_X3_START + (_nr)) -#define EXYNOS5_GPE0(_nr) (EXYNOS5_GPIO_E0_START + (_nr)) -#define EXYNOS5_GPE1(_nr) (EXYNOS5_GPIO_E1_START + (_nr)) -#define EXYNOS5_GPF0(_nr) (EXYNOS5_GPIO_F0_START + (_nr)) -#define EXYNOS5_GPF1(_nr) (EXYNOS5_GPIO_F1_START + (_nr)) -#define EXYNOS5_GPG0(_nr) (EXYNOS5_GPIO_G0_START + (_nr)) -#define EXYNOS5_GPG1(_nr) (EXYNOS5_GPIO_G1_START + (_nr)) -#define EXYNOS5_GPG2(_nr) (EXYNOS5_GPIO_G2_START + (_nr)) -#define EXYNOS5_GPH0(_nr) (EXYNOS5_GPIO_H0_START + (_nr)) -#define EXYNOS5_GPH1(_nr) (EXYNOS5_GPIO_H1_START + (_nr)) -#define EXYNOS5_GPV0(_nr) (EXYNOS5_GPIO_V0_START + (_nr)) -#define EXYNOS5_GPV1(_nr) (EXYNOS5_GPIO_V1_START + (_nr)) -#define EXYNOS5_GPV2(_nr) (EXYNOS5_GPIO_V2_START + (_nr)) -#define EXYNOS5_GPV3(_nr) (EXYNOS5_GPIO_V3_START + (_nr)) -#define EXYNOS5_GPV4(_nr) (EXYNOS5_GPIO_V4_START + (_nr)) -#define EXYNOS5_GPZ(_nr) (EXYNOS5_GPIO_Z_START + (_nr)) - -/* the end of the EXYNOS5 specific gpios */ - -#define EXYNOS5_GPIO_END (EXYNOS5_GPZ(EXYNOS5_GPIO_Z_NR) + 1) - -/* actually, EXYNOS5_GPIO_END is bigger than EXYNOS4 */ - -#define S3C_GPIO_END (EXYNOS5_GPIO_END) - -/* define the number of gpios */ - -#define ARCH_NR_GPIOS (CONFIG_SAMSUNG_GPIO_EXTRA + S3C_GPIO_END) - -#endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h deleted file mode 100644 index c72f59d91fc..00000000000 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ /dev/null @@ -1,476 +0,0 @@ -/* - * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS - IRQ definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H __FILE__ - -#include <plat/irqs.h> - -/* PPI: Private Peripheral Interrupt */ - -#define IRQ_PPI(x) (x + 16) - -/* SPI: Shared Peripheral Interrupt */ - -#define IRQ_SPI(x) (x + 32) - -/* COMBINER */ - -#define MAX_IRQ_IN_COMBINER 8 -#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128)) -#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y) - -/* For EXYNOS4 and EXYNOS5 */ - -#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32) - -/* For EXYNOS4 SoCs */ - -#define EXYNOS4_IRQ_EINT0 IRQ_SPI(16) -#define EXYNOS4_IRQ_EINT1 IRQ_SPI(17) -#define EXYNOS4_IRQ_EINT2 IRQ_SPI(18) -#define EXYNOS4_IRQ_EINT3 IRQ_SPI(19) -#define EXYNOS4_IRQ_EINT4 IRQ_SPI(20) -#define EXYNOS4_IRQ_EINT5 IRQ_SPI(21) -#define EXYNOS4_IRQ_EINT6 IRQ_SPI(22) -#define EXYNOS4_IRQ_EINT7 IRQ_SPI(23) -#define EXYNOS4_IRQ_EINT8 IRQ_SPI(24) -#define EXYNOS4_IRQ_EINT9 IRQ_SPI(25) -#define EXYNOS4_IRQ_EINT10 IRQ_SPI(26) -#define EXYNOS4_IRQ_EINT11 IRQ_SPI(27) -#define EXYNOS4_IRQ_EINT12 IRQ_SPI(28) -#define EXYNOS4_IRQ_EINT13 IRQ_SPI(29) -#define EXYNOS4_IRQ_EINT14 IRQ_SPI(30) -#define EXYNOS4_IRQ_EINT15 IRQ_SPI(31) - -#define EXYNOS4_IRQ_MDMA0 IRQ_SPI(33) -#define EXYNOS4_IRQ_MDMA1 IRQ_SPI(34) -#define EXYNOS4_IRQ_PDMA0 IRQ_SPI(35) -#define EXYNOS4_IRQ_PDMA1 IRQ_SPI(36) -#define EXYNOS4_IRQ_TIMER0_VIC IRQ_SPI(37) -#define EXYNOS4_IRQ_TIMER1_VIC IRQ_SPI(38) -#define EXYNOS4_IRQ_TIMER2_VIC IRQ_SPI(39) -#define EXYNOS4_IRQ_TIMER3_VIC IRQ_SPI(40) -#define EXYNOS4_IRQ_TIMER4_VIC IRQ_SPI(41) -#define EXYNOS4_IRQ_MCT_L0 IRQ_SPI(42) -#define EXYNOS4_IRQ_WDT IRQ_SPI(43) -#define EXYNOS4_IRQ_RTC_ALARM IRQ_SPI(44) -#define EXYNOS4_IRQ_RTC_TIC IRQ_SPI(45) -#define EXYNOS4_IRQ_GPIO_XB IRQ_SPI(46) -#define EXYNOS4_IRQ_GPIO_XA IRQ_SPI(47) -#define EXYNOS4_IRQ_MCT_L1 IRQ_SPI(48) - -#define EXYNOS4_IRQ_UART0 IRQ_SPI(52) -#define EXYNOS4_IRQ_UART1 IRQ_SPI(53) -#define EXYNOS4_IRQ_UART2 IRQ_SPI(54) -#define EXYNOS4_IRQ_UART3 IRQ_SPI(55) -#define EXYNOS4_IRQ_UART4 IRQ_SPI(56) -#define EXYNOS4_IRQ_MCT_G0 IRQ_SPI(57) -#define EXYNOS4_IRQ_IIC IRQ_SPI(58) -#define EXYNOS4_IRQ_IIC1 IRQ_SPI(59) -#define EXYNOS4_IRQ_IIC2 IRQ_SPI(60) -#define EXYNOS4_IRQ_IIC3 IRQ_SPI(61) -#define EXYNOS4_IRQ_IIC4 IRQ_SPI(62) -#define EXYNOS4_IRQ_IIC5 IRQ_SPI(63) -#define EXYNOS4_IRQ_IIC6 IRQ_SPI(64) -#define EXYNOS4_IRQ_IIC7 IRQ_SPI(65) -#define EXYNOS4_IRQ_SPI0 IRQ_SPI(66) -#define EXYNOS4_IRQ_SPI1 IRQ_SPI(67) -#define EXYNOS4_IRQ_SPI2 IRQ_SPI(68) - -#define EXYNOS4_IRQ_USB_HOST IRQ_SPI(70) -#define EXYNOS4_IRQ_USB_HSOTG IRQ_SPI(71) -#define EXYNOS4_IRQ_MODEM_IF IRQ_SPI(72) -#define EXYNOS4_IRQ_HSMMC0 IRQ_SPI(73) -#define EXYNOS4_IRQ_HSMMC1 IRQ_SPI(74) -#define EXYNOS4_IRQ_HSMMC2 IRQ_SPI(75) -#define EXYNOS4_IRQ_HSMMC3 IRQ_SPI(76) -#define EXYNOS4_IRQ_DWMCI IRQ_SPI(77) - -#define EXYNOS4_IRQ_MIPI_CSIS0 IRQ_SPI(78) -#define EXYNOS4_IRQ_MIPI_CSIS1 IRQ_SPI(80) - -#define EXYNOS4_IRQ_ONENAND_AUDI IRQ_SPI(82) -#define EXYNOS4_IRQ_ROTATOR IRQ_SPI(83) -#define EXYNOS4_IRQ_FIMC0 IRQ_SPI(84) -#define EXYNOS4_IRQ_FIMC1 IRQ_SPI(85) -#define EXYNOS4_IRQ_FIMC2 IRQ_SPI(86) -#define EXYNOS4_IRQ_FIMC3 IRQ_SPI(87) -#define EXYNOS4_IRQ_JPEG IRQ_SPI(88) -#define EXYNOS4_IRQ_2D IRQ_SPI(89) -#define EXYNOS4_IRQ_PCIE IRQ_SPI(90) - -#define EXYNOS4_IRQ_MIXER IRQ_SPI(91) -#define EXYNOS4_IRQ_HDMI IRQ_SPI(92) -#define EXYNOS4_IRQ_IIC_HDMIPHY IRQ_SPI(93) -#define EXYNOS4_IRQ_MFC IRQ_SPI(94) -#define EXYNOS4_IRQ_SDO IRQ_SPI(95) - -#define EXYNOS4_IRQ_AUDIO_SS IRQ_SPI(96) -#define EXYNOS4_IRQ_I2S0 IRQ_SPI(97) -#define EXYNOS4_IRQ_I2S1 IRQ_SPI(98) -#define EXYNOS4_IRQ_I2S2 IRQ_SPI(99) -#define EXYNOS4_IRQ_AC97 IRQ_SPI(100) - -#define EXYNOS4_IRQ_SPDIF IRQ_SPI(104) -#define EXYNOS4_IRQ_ADC0 IRQ_SPI(105) -#define EXYNOS4_IRQ_PEN0 IRQ_SPI(106) -#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107) -#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108) -#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109) -#define EXYNOS4_IRQ_POWER_PMU IRQ_SPI(110) -#define EXYNOS4_IRQ_GPS IRQ_SPI(111) -#define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112) -#define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113) - -#define EXYNOS4_IRQ_TSI IRQ_SPI(115) -#define EXYNOS4_IRQ_SATA IRQ_SPI(116) - -#define EXYNOS4_IRQ_PMU COMBINER_IRQ(2, 2) -#define EXYNOS4_IRQ_PMU_CPU1 COMBINER_IRQ(3, 2) -#define EXYNOS4_IRQ_PMU_CPU2 COMBINER_IRQ(18, 2) -#define EXYNOS4_IRQ_PMU_CPU3 COMBINER_IRQ(19, 2) - -#define EXYNOS4_IRQ_TMU_TRIG0 COMBINER_IRQ(2, 4) -#define EXYNOS4_IRQ_TMU_TRIG1 COMBINER_IRQ(3, 4) - -#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0) -#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1) -#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2) -#define EXYNOS4_IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3) -#define EXYNOS4_IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4) -#define EXYNOS4_IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5) -#define EXYNOS4_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6) -#define EXYNOS4_IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7) - -#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0) -#define EXYNOS4_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1) -#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2) -#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3) -#define EXYNOS4_IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4) -#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5) -#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6) -#define EXYNOS4_IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7) - -#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0 COMBINER_IRQ(16, 0) -#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0 COMBINER_IRQ(16, 1) -#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0 COMBINER_IRQ(16, 2) -#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0 COMBINER_IRQ(16, 3) -#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0 COMBINER_IRQ(16, 4) -#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0 COMBINER_IRQ(16, 5) - -#define EXYNOS4_IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0) -#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1) -#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2) - -#define EXYNOS4210_MAX_COMBINER_NR 16 -#define EXYNOS4212_MAX_COMBINER_NR 18 -#define EXYNOS4412_MAX_COMBINER_NR 20 -#define EXYNOS4_MAX_COMBINER_NR EXYNOS4412_MAX_COMBINER_NR - -#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16 -#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9 - -/* - * For Compatibility: - * the default is for EXYNOS4, and - * for exynos5, should be re-mapped at function - */ - -#define IRQ_TIMER0_VIC EXYNOS4_IRQ_TIMER0_VIC -#define IRQ_TIMER1_VIC EXYNOS4_IRQ_TIMER1_VIC -#define IRQ_TIMER2_VIC EXYNOS4_IRQ_TIMER2_VIC -#define IRQ_TIMER3_VIC EXYNOS4_IRQ_TIMER3_VIC -#define IRQ_TIMER4_VIC EXYNOS4_IRQ_TIMER4_VIC - -#define IRQ_WDT EXYNOS4_IRQ_WDT -#define IRQ_RTC_ALARM EXYNOS4_IRQ_RTC_ALARM -#define IRQ_RTC_TIC EXYNOS4_IRQ_RTC_TIC -#define IRQ_GPIO_XB EXYNOS4_IRQ_GPIO_XB -#define IRQ_GPIO_XA EXYNOS4_IRQ_GPIO_XA - -#define IRQ_IIC EXYNOS4_IRQ_IIC -#define IRQ_IIC1 EXYNOS4_IRQ_IIC1 -#define IRQ_IIC3 EXYNOS4_IRQ_IIC3 -#define IRQ_IIC5 EXYNOS4_IRQ_IIC5 -#define IRQ_IIC6 EXYNOS4_IRQ_IIC6 -#define IRQ_IIC7 EXYNOS4_IRQ_IIC7 - -#define IRQ_SPI0 EXYNOS4_IRQ_SPI0 -#define IRQ_SPI1 EXYNOS4_IRQ_SPI1 -#define IRQ_SPI2 EXYNOS4_IRQ_SPI2 - -#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST -#define IRQ_OTG EXYNOS4_IRQ_USB_HSOTG - -#define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0 -#define IRQ_HSMMC1 EXYNOS4_IRQ_HSMMC1 -#define IRQ_HSMMC2 EXYNOS4_IRQ_HSMMC2 -#define IRQ_HSMMC3 EXYNOS4_IRQ_HSMMC3 - -#define IRQ_MIPI_CSIS0 EXYNOS4_IRQ_MIPI_CSIS0 - -#define IRQ_ONENAND_AUDI EXYNOS4_IRQ_ONENAND_AUDI - -#define IRQ_FIMC0 EXYNOS4_IRQ_FIMC0 -#define IRQ_FIMC1 EXYNOS4_IRQ_FIMC1 -#define IRQ_FIMC2 EXYNOS4_IRQ_FIMC2 -#define IRQ_FIMC3 EXYNOS4_IRQ_FIMC3 -#define IRQ_JPEG EXYNOS4_IRQ_JPEG -#define IRQ_2D EXYNOS4_IRQ_2D - -#define IRQ_MIXER EXYNOS4_IRQ_MIXER -#define IRQ_HDMI EXYNOS4_IRQ_HDMI -#define IRQ_IIC_HDMIPHY EXYNOS4_IRQ_IIC_HDMIPHY -#define IRQ_MFC EXYNOS4_IRQ_MFC -#define IRQ_SDO EXYNOS4_IRQ_SDO - -#define IRQ_I2S0 EXYNOS4_IRQ_I2S0 - -#define IRQ_ADC EXYNOS4_IRQ_ADC0 -#define IRQ_TC EXYNOS4_IRQ_PEN0 - -#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD - -#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO -#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC -#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM - -#define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS -#define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS - -/* For EXYNOS5 SoCs */ - -#define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33) -#define EXYNOS5_IRQ_PDMA0 IRQ_SPI(34) -#define EXYNOS5_IRQ_PDMA1 IRQ_SPI(35) -#define EXYNOS5_IRQ_TIMER0_VIC IRQ_SPI(36) -#define EXYNOS5_IRQ_TIMER1_VIC IRQ_SPI(37) -#define EXYNOS5_IRQ_TIMER2_VIC IRQ_SPI(38) -#define EXYNOS5_IRQ_TIMER3_VIC IRQ_SPI(39) -#define EXYNOS5_IRQ_TIMER4_VIC IRQ_SPI(40) -#define EXYNOS5_IRQ_RTIC IRQ_SPI(41) -#define EXYNOS5_IRQ_WDT IRQ_SPI(42) -#define EXYNOS5_IRQ_RTC_ALARM IRQ_SPI(43) -#define EXYNOS5_IRQ_RTC_TIC IRQ_SPI(44) -#define EXYNOS5_IRQ_GPIO_XB IRQ_SPI(45) -#define EXYNOS5_IRQ_GPIO_XA IRQ_SPI(46) -#define EXYNOS5_IRQ_GPIO IRQ_SPI(47) -#define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48) -#define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49) -#define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50) -#define EXYNOS5_IRQ_IIC IRQ_SPI(56) -#define EXYNOS5_IRQ_IIC1 IRQ_SPI(57) -#define EXYNOS5_IRQ_IIC2 IRQ_SPI(58) -#define EXYNOS5_IRQ_IIC3 IRQ_SPI(59) -#define EXYNOS5_IRQ_IIC4 IRQ_SPI(60) -#define EXYNOS5_IRQ_IIC5 IRQ_SPI(61) -#define EXYNOS5_IRQ_IIC6 IRQ_SPI(62) -#define EXYNOS5_IRQ_IIC7 IRQ_SPI(63) -#define EXYNOS5_IRQ_IIC_HDMIPHY IRQ_SPI(64) -#define EXYNOS5_IRQ_TMU IRQ_SPI(65) -#define EXYNOS5_IRQ_FIQ_0 IRQ_SPI(66) -#define EXYNOS5_IRQ_FIQ_1 IRQ_SPI(67) -#define EXYNOS5_IRQ_SPI0 IRQ_SPI(68) -#define EXYNOS5_IRQ_SPI1 IRQ_SPI(69) -#define EXYNOS5_IRQ_SPI2 IRQ_SPI(70) -#define EXYNOS5_IRQ_USB_HOST IRQ_SPI(71) -#define EXYNOS5_IRQ_USB3_DRD IRQ_SPI(72) -#define EXYNOS5_IRQ_MIPI_HSI IRQ_SPI(73) -#define EXYNOS5_IRQ_USB_HSOTG IRQ_SPI(74) -#define EXYNOS5_IRQ_HSMMC0 IRQ_SPI(75) -#define EXYNOS5_IRQ_HSMMC1 IRQ_SPI(76) -#define EXYNOS5_IRQ_HSMMC2 IRQ_SPI(77) -#define EXYNOS5_IRQ_HSMMC3 IRQ_SPI(78) -#define EXYNOS5_IRQ_MIPICSI0 IRQ_SPI(79) -#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80) -#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81) -#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82) -#define EXYNOS5_IRQ_WDT_IOP IRQ_SPI(83) -#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84) -#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85) -#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86) -#define EXYNOS5_IRQ_GSC2 IRQ_SPI(87) -#define EXYNOS5_IRQ_GSC3 IRQ_SPI(88) -#define EXYNOS5_IRQ_JPEG IRQ_SPI(89) -#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90) -#define EXYNOS5_IRQ_2D IRQ_SPI(91) -#define EXYNOS5_IRQ_EFNFCON_0 IRQ_SPI(92) -#define EXYNOS5_IRQ_EFNFCON_1 IRQ_SPI(93) -#define EXYNOS5_IRQ_MIXER IRQ_SPI(94) -#define EXYNOS5_IRQ_HDMI IRQ_SPI(95) -#define EXYNOS5_IRQ_MFC IRQ_SPI(96) -#define EXYNOS5_IRQ_AUDIO_SS IRQ_SPI(97) -#define EXYNOS5_IRQ_I2S0 IRQ_SPI(98) -#define EXYNOS5_IRQ_I2S1 IRQ_SPI(99) -#define EXYNOS5_IRQ_I2S2 IRQ_SPI(100) -#define EXYNOS5_IRQ_AC97 IRQ_SPI(101) -#define EXYNOS5_IRQ_PCM0 IRQ_SPI(102) -#define EXYNOS5_IRQ_PCM1 IRQ_SPI(103) -#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104) -#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105) -#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106) -#define EXYNOS5_IRQ_ADC1 IRQ_SPI(107) -#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108) -#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109) -#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110) -#define EXYNOS5_IRQ_EAGLE_PMU IRQ_SPI(111) -#define EXYNOS5_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112) -#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113) -#define EXYNOS5_IRQ_CEC IRQ_SPI(114) -#define EXYNOS5_IRQ_SATA IRQ_SPI(115) - -#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123) -#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124) -#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125) -#define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126) -#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127) - -/* EXYNOS5440 */ - -#define EXYNOS5440_IRQ_UART0 IRQ_SPI(2) -#define EXYNOS5440_IRQ_UART1 IRQ_SPI(3) - -#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2) - -#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0) -#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1) -#define EXYNOS5_IRQ_SYSMMU_GSC1_0 COMBINER_IRQ(2, 2) -#define EXYNOS5_IRQ_SYSMMU_GSC1_1 COMBINER_IRQ(2, 3) -#define EXYNOS5_IRQ_SYSMMU_GSC2_0 COMBINER_IRQ(2, 4) -#define EXYNOS5_IRQ_SYSMMU_GSC2_1 COMBINER_IRQ(2, 5) -#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6) -#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7) - -#define EXYNOS5_IRQ_SYSMMU_LITE2_0 COMBINER_IRQ(3, 0) -#define EXYNOS5_IRQ_SYSMMU_LITE2_1 COMBINER_IRQ(3, 1) -#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2) -#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3) -#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4) -#define EXYNOS5_IRQ_SYSMMU_LITE0_1 COMBINER_IRQ(3, 5) -#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6) -#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7) - -#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(4, 0) -#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1 COMBINER_IRQ(4, 1) -#define EXYNOS5_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 2) -#define EXYNOS5_IRQ_SYSMMU_JPEG_1 COMBINER_IRQ(4, 3) - -#define EXYNOS5_IRQ_SYSMMU_FD_0 COMBINER_IRQ(5, 0) -#define EXYNOS5_IRQ_SYSMMU_FD_1 COMBINER_IRQ(5, 1) -#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2) -#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3) -#define EXYNOS5_IRQ_SYSMMU_MCUISP_0 COMBINER_IRQ(5, 4) -#define EXYNOS5_IRQ_SYSMMU_MCUISP_1 COMBINER_IRQ(5, 5) -#define EXYNOS5_IRQ_SYSMMU_3DNR_0 COMBINER_IRQ(5, 6) -#define EXYNOS5_IRQ_SYSMMU_3DNR_1 COMBINER_IRQ(5, 7) - -#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0) -#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1) -#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(6, 2) -#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(6, 3) -#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4) -#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5) -#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6) -#define EXYNOS5_IRQ_SYSMMU_SSS_1 COMBINER_IRQ(6, 7) - -#define EXYNOS5_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(7, 0) -#define EXYNOS5_IRQ_SYSMMU_MDMA0_1 COMBINER_IRQ(7, 1) -#define EXYNOS5_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(7, 2) -#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3) -#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4) -#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5) - -#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(8, 5) -#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(8, 6) - -#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4) -#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5) - -#define EXYNOS5_IRQ_DP COMBINER_IRQ(10, 3) -#define EXYNOS5_IRQ_SYSMMU_DIS0_0 COMBINER_IRQ(10, 4) -#define EXYNOS5_IRQ_SYSMMU_DIS0_1 COMBINER_IRQ(10, 5) -#define EXYNOS5_IRQ_SYSMMU_ISP_0 COMBINER_IRQ(10, 6) -#define EXYNOS5_IRQ_SYSMMU_ISP_1 COMBINER_IRQ(10, 7) - -#define EXYNOS5_IRQ_SYSMMU_ODC_0 COMBINER_IRQ(11, 0) -#define EXYNOS5_IRQ_SYSMMU_ODC_1 COMBINER_IRQ(11, 1) -#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6) -#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7) - -#define EXYNOS5_IRQ_MDMA1_ABORT COMBINER_IRQ(13, 1) - -#define EXYNOS5_IRQ_MDMA0_ABORT COMBINER_IRQ(15, 3) - -#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4) -#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5) -#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6) - -#define EXYNOS5_IRQ_ARMIOP_GIC COMBINER_IRQ(19, 0) -#define EXYNOS5_IRQ_ARMISP_GIC COMBINER_IRQ(19, 1) -#define EXYNOS5_IRQ_IOP_GIC COMBINER_IRQ(19, 3) -#define EXYNOS5_IRQ_ISP_GIC COMBINER_IRQ(19, 4) - -#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4) - -#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0) - -#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0) -#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1) -#define EXYNOS5_IRQ_SYSMMU_LITE1_1 COMBINER_IRQ(24, 2) -#define EXYNOS5_IRQ_SYSMMU_2D_0 COMBINER_IRQ(24, 5) -#define EXYNOS5_IRQ_SYSMMU_2D_1 COMBINER_IRQ(24, 6) - -#define EXYNOS5_IRQ_EINT2 COMBINER_IRQ(25, 0) -#define EXYNOS5_IRQ_EINT3 COMBINER_IRQ(25, 1) - -#define EXYNOS5_IRQ_EINT4 COMBINER_IRQ(26, 0) -#define EXYNOS5_IRQ_EINT5 COMBINER_IRQ(26, 1) - -#define EXYNOS5_IRQ_EINT6 COMBINER_IRQ(27, 0) -#define EXYNOS5_IRQ_EINT7 COMBINER_IRQ(27, 1) - -#define EXYNOS5_IRQ_EINT8 COMBINER_IRQ(28, 0) -#define EXYNOS5_IRQ_EINT9 COMBINER_IRQ(28, 1) - -#define EXYNOS5_IRQ_EINT10 COMBINER_IRQ(29, 0) -#define EXYNOS5_IRQ_EINT11 COMBINER_IRQ(29, 1) - -#define EXYNOS5_IRQ_EINT12 COMBINER_IRQ(30, 0) -#define EXYNOS5_IRQ_EINT13 COMBINER_IRQ(30, 1) - -#define EXYNOS5_IRQ_EINT14 COMBINER_IRQ(31, 0) -#define EXYNOS5_IRQ_EINT15 COMBINER_IRQ(31, 1) - -#define EXYNOS5_MAX_COMBINER_NR 32 - -#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 14 -#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9 -#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5 -#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1 - -#define MAX_COMBINER_NR (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \ - EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR) - -#define S5P_EINT_BASE1 COMBINER_IRQ(MAX_COMBINER_NR, 0) -#define S5P_EINT_BASE2 (S5P_EINT_BASE1 + 16) -#define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32) -#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) -#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64) - -/* Set the default NR_IRQS */ -#define EXYNOS_NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT) - -#ifndef CONFIG_SPARSE_IRQ -#define NR_IRQS EXYNOS_NR_IRQS -#endif - -#endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 92b29bb583c..7b046b59d9e 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -30,31 +30,6 @@ #define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000 #define EXYNOS5250_PA_SYSRAM_NS 0x0204F000 -#define EXYNOS4_PA_FIMC0 0x11800000 -#define EXYNOS4_PA_FIMC1 0x11810000 -#define EXYNOS4_PA_FIMC2 0x11820000 -#define EXYNOS4_PA_FIMC3 0x11830000 - -#define EXYNOS4_PA_JPEG 0x11840000 - -/* x = 0...1 */ -#define EXYNOS4_PA_FIMC_LITE(x) (0x12390000 + ((x) * 0x10000)) - -#define EXYNOS4_PA_G2D 0x12800000 - -#define EXYNOS4_PA_I2S0 0x03830000 -#define EXYNOS4_PA_I2S1 0xE3100000 -#define EXYNOS4_PA_I2S2 0xE2A00000 - -#define EXYNOS4_PA_PCM0 0x03840000 -#define EXYNOS4_PA_PCM1 0x13980000 -#define EXYNOS4_PA_PCM2 0x13990000 - -#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000)) - -#define EXYNOS4_PA_ONENAND 0x0C000000 -#define EXYNOS4_PA_ONENAND_DMA 0x0C600000 - #define EXYNOS_PA_CHIPID 0x10000000 #define EXYNOS4_PA_SYSCON 0x10010000 @@ -71,10 +46,6 @@ #define EXYNOS4_PA_WATCHDOG 0x10060000 #define EXYNOS5_PA_WATCHDOG 0x101D0000 -#define EXYNOS4_PA_RTC 0x10070000 - -#define EXYNOS4_PA_KEYPAD 0x100A0000 - #define EXYNOS4_PA_DMC0 0x10400000 #define EXYNOS4_PA_DMC1 0x10410000 @@ -87,207 +58,22 @@ #define EXYNOS5_PA_GIC_DIST 0x10481000 #define EXYNOS4_PA_COREPERI 0x10500000 -#define EXYNOS4_PA_TWD 0x10500600 #define EXYNOS4_PA_L2CC 0x10502000 -#define EXYNOS4_PA_TMU 0x100C0000 - -#define EXYNOS4_PA_MDMA0 0x10810000 -#define EXYNOS4_PA_MDMA1 0x12850000 -#define EXYNOS4_PA_S_MDMA1 0x12840000 -#define EXYNOS4_PA_PDMA0 0x12680000 -#define EXYNOS4_PA_PDMA1 0x12690000 -#define EXYNOS5_PA_MDMA0 0x10800000 -#define EXYNOS5_PA_MDMA1 0x11C10000 -#define EXYNOS5_PA_PDMA0 0x121A0000 -#define EXYNOS5_PA_PDMA1 0x121B0000 - -#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000 -#define EXYNOS4_PA_SYSMMU_2D_ACP 0x10A40000 -#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000 -#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000 -#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000 -#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000 -#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000 -#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000 -#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000 -#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000 -#define EXYNOS4_PA_SYSMMU_FIMC_ISP 0x12260000 -#define EXYNOS4_PA_SYSMMU_FIMC_DRC 0x12270000 -#define EXYNOS4_PA_SYSMMU_FIMC_FD 0x122A0000 -#define EXYNOS4_PA_SYSMMU_ISPCPU 0x122B0000 -#define EXYNOS4_PA_SYSMMU_FIMC_LITE0 0x123B0000 -#define EXYNOS4_PA_SYSMMU_FIMC_LITE1 0x123C0000 -#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000 -#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000 -#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000 -#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000 -#define EXYNOS4_PA_SYSMMU_TV 0x12E20000 -#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000 -#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000 - -#define EXYNOS5_PA_GSC0 0x13E00000 -#define EXYNOS5_PA_GSC1 0x13E10000 -#define EXYNOS5_PA_GSC2 0x13E20000 -#define EXYNOS5_PA_GSC3 0x13E30000 - -#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000 -#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000 -#define EXYNOS5_PA_SYSMMU_2D 0x10A60000 -#define EXYNOS5_PA_SYSMMU_MFC_L 0x11200000 -#define EXYNOS5_PA_SYSMMU_MFC_R 0x11210000 -#define EXYNOS5_PA_SYSMMU_ROTATOR 0x11D40000 -#define EXYNOS5_PA_SYSMMU_MDMA2 0x11D50000 -#define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000 -#define EXYNOS5_PA_SYSMMU_IOP 0x12360000 -#define EXYNOS5_PA_SYSMMU_RTIC 0x12370000 -#define EXYNOS5_PA_SYSMMU_ISP 0x13260000 -#define EXYNOS5_PA_SYSMMU_DRC 0x12370000 -#define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000 -#define EXYNOS5_PA_SYSMMU_SCALERP 0x13290000 -#define EXYNOS5_PA_SYSMMU_FD 0x132A0000 -#define EXYNOS5_PA_SYSMMU_ISPCPU 0x132B0000 -#define EXYNOS5_PA_SYSMMU_ODC 0x132C0000 -#define EXYNOS5_PA_SYSMMU_DIS0 0x132D0000 -#define EXYNOS5_PA_SYSMMU_DIS1 0x132E0000 -#define EXYNOS5_PA_SYSMMU_3DNR 0x132F0000 -#define EXYNOS5_PA_SYSMMU_LITE0 0x13C40000 -#define EXYNOS5_PA_SYSMMU_LITE1 0x13C50000 -#define EXYNOS5_PA_SYSMMU_GSC0 0x13E80000 -#define EXYNOS5_PA_SYSMMU_GSC1 0x13E90000 -#define EXYNOS5_PA_SYSMMU_GSC2 0x13EA0000 -#define EXYNOS5_PA_SYSMMU_GSC3 0x13EB0000 -#define EXYNOS5_PA_SYSMMU_FIMD1 0x14640000 -#define EXYNOS5_PA_SYSMMU_TV 0x14650000 - -#define EXYNOS4_PA_SPI0 0x13920000 -#define EXYNOS4_PA_SPI1 0x13930000 -#define EXYNOS4_PA_SPI2 0x13940000 -#define EXYNOS5_PA_SPI0 0x12D20000 -#define EXYNOS5_PA_SPI1 0x12D30000 -#define EXYNOS5_PA_SPI2 0x12D40000 - -#define EXYNOS4_PA_GPIO1 0x11400000 -#define EXYNOS4_PA_GPIO2 0x11000000 -#define EXYNOS4_PA_GPIO3 0x03860000 -#define EXYNOS5_PA_GPIO1 0x11400000 -#define EXYNOS5_PA_GPIO2 0x13400000 -#define EXYNOS5_PA_GPIO3 0x10D10000 -#define EXYNOS5_PA_GPIO4 0x03860000 - -#define EXYNOS4_PA_MIPI_CSIS0 0x11880000 -#define EXYNOS4_PA_MIPI_CSIS1 0x11890000 - -#define EXYNOS4_PA_FIMD0 0x11C00000 - -#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) -#define EXYNOS4_PA_DWMCI 0x12550000 -#define EXYNOS5_PA_DWMCI0 0x12200000 -#define EXYNOS5_PA_DWMCI1 0x12210000 -#define EXYNOS5_PA_DWMCI2 0x12220000 -#define EXYNOS5_PA_DWMCI3 0x12230000 - -#define EXYNOS4_PA_HSOTG 0x12480000 -#define EXYNOS4_PA_USB_HSPHY 0x125B0000 - -#define EXYNOS4_PA_SATA 0x12560000 -#define EXYNOS4_PA_SATAPHY 0x125D0000 -#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000 - #define EXYNOS4_PA_SROMC 0x12570000 #define EXYNOS5_PA_SROMC 0x12250000 -#define EXYNOS4_PA_EHCI 0x12580000 -#define EXYNOS4_PA_OHCI 0x12590000 #define EXYNOS4_PA_HSPHY 0x125B0000 -#define EXYNOS4_PA_MFC 0x13400000 #define EXYNOS4_PA_UART 0x13800000 #define EXYNOS5_PA_UART 0x12C00000 -#define EXYNOS4_PA_VP 0x12C00000 -#define EXYNOS4_PA_MIXER 0x12C10000 -#define EXYNOS4_PA_SDO 0x12C20000 -#define EXYNOS4_PA_HDMI 0x12D00000 -#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000 - -#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) -#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000)) - -#define EXYNOS4_PA_ADC 0x13910000 -#define EXYNOS4_PA_ADC1 0x13911000 - -#define EXYNOS4_PA_AC97 0x139A0000 - -#define EXYNOS4_PA_SPDIF 0x139B0000 - #define EXYNOS4_PA_TIMER 0x139D0000 #define EXYNOS5_PA_TIMER 0x12DD0000 -#define EXYNOS4_PA_SDRAM 0x40000000 -#define EXYNOS5_PA_SDRAM 0x40000000 - -/* Compatibiltiy Defines */ - -#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0) -#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1) -#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2) -#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3) -#define S3C_PA_IIC EXYNOS4_PA_IIC(0) -#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1) -#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2) -#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3) -#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4) -#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5) -#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6) -#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7) -#define S3C_PA_RTC EXYNOS4_PA_RTC -#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG -#define S3C_PA_SPI0 EXYNOS4_PA_SPI0 -#define S3C_PA_SPI1 EXYNOS4_PA_SPI1 -#define S3C_PA_SPI2 EXYNOS4_PA_SPI2 -#define S3C_PA_USB_HSOTG EXYNOS4_PA_HSOTG - -#define S5P_PA_EHCI EXYNOS4_PA_EHCI -#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0 -#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1 -#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2 -#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3 -#define S5P_PA_JPEG EXYNOS4_PA_JPEG -#define S5P_PA_G2D EXYNOS4_PA_G2D -#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0 -#define S5P_PA_HDMI EXYNOS4_PA_HDMI -#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY -#define S5P_PA_MFC EXYNOS4_PA_MFC -#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0 -#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1 -#define S5P_PA_MIXER EXYNOS4_PA_MIXER -#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND -#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA -#define S5P_PA_SDO EXYNOS4_PA_SDO -#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM -#define S5P_PA_VP EXYNOS4_PA_VP - -#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC -#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1 -#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD - /* Compatibility UART */ -#define EXYNOS4_PA_UART0 0x13800000 -#define EXYNOS4_PA_UART1 0x13810000 -#define EXYNOS4_PA_UART2 0x13820000 -#define EXYNOS4_PA_UART3 0x13830000 -#define EXYNOS4_SZ_UART SZ_256 - -#define EXYNOS5_PA_UART0 0x12C00000 -#define EXYNOS5_PA_UART1 0x12C10000 -#define EXYNOS5_PA_UART2 0x12C20000 -#define EXYNOS5_PA_UART3 0x12C30000 - #define EXYNOS5440_PA_UART0 0x000B0000 -#define EXYNOS5440_PA_UART1 0x000C0000 -#define EXYNOS5440_SZ_UART SZ_256 #define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h index 7dbbfec13ea..2b00833b664 100644 --- a/arch/arm/mach-exynos/include/mach/pm-core.h +++ b/arch/arm/mach-exynos/include/mach/pm-core.h @@ -18,8 +18,15 @@ #ifndef __ASM_ARCH_PM_CORE_H #define __ASM_ARCH_PM_CORE_H __FILE__ +#include <linux/of.h> #include <mach/regs-pmu.h> +#ifdef CONFIG_PINCTRL_EXYNOS +extern u32 exynos_get_eint_wake_mask(void); +#else +static inline u32 exynos_get_eint_wake_mask(void) { return 0xffffffff; } +#endif + static inline void s3c_pm_debug_init_uart(void) { /* nothing here yet */ @@ -27,7 +34,7 @@ static inline void s3c_pm_debug_init_uart(void) static inline void s3c_pm_arch_prepare_irqs(void) { - __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK); + __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); } @@ -57,4 +64,9 @@ static inline void samsung_pm_saved_gpios(void) /* nothing here yet */ } +/* Compatibility definitions to make plat-samsung/pm.c compile */ +#define IRQ_EINT_BIT(x) 1 +#define s3c_irqwake_intallow 0 +#define s3c_irqwake_eintallow 0 + #endif /* __ASM_ARCH_PM_CORE_H */ diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h deleted file mode 100644 index e4b5b60dcb8..00000000000 --- a/arch/arm/mach-exynos/include/mach/regs-gpio.h +++ /dev/null @@ -1,40 +0,0 @@ -/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 - GPIO (including EINT) register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_REGS_GPIO_H -#define __ASM_ARCH_REGS_GPIO_H __FILE__ - -#include <mach/map.h> -#include <mach/irqs.h> - -#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3) -#define EINT_CON(b, x) (b + 0xE00 + (EINT_REG_NR(x) * 4)) -#define EINT_FLTCON(b, x) (b + 0xE80 + (EINT_REG_NR(x) * 4)) -#define EINT_MASK(b, x) (b + 0xF00 + (EINT_REG_NR(x) * 4)) -#define EINT_PEND(b, x) (b + 0xF40 + (EINT_REG_NR(x) * 4)) - -#define EINT_OFFSET_BIT(x) (1 << (EINT_OFFSET(x) & 0x7)) - -/* compatibility for plat-s5p/irq-pm.c */ -#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00) -#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4)) - -#define EXYNOS4_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80) -#define S5P_EINT_FLTCON(x) (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4)) - -#define EXYNOS4_EINT40MASK (S5P_VA_GPIO2 + 0xF00) -#define S5P_EINT_MASK(x) (EXYNOS4_EINT40MASK + ((x) * 0x4)) - -#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40) -#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4)) - -#endif /* __ASM_ARCH_REGS_GPIO_H */ diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h deleted file mode 100644 index 07277735252..00000000000 --- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics Co.Ltd - * Author: Joonyoung Shim <jy0922.shim@samsung.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __PLAT_S5P_REGS_USB_PHY_H -#define __PLAT_S5P_REGS_USB_PHY_H - -#define EXYNOS4_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY) - -#define EXYNOS4_PHYPWR EXYNOS4_HSOTG_PHYREG(0x00) -#define PHY1_HSIC_NORMAL_MASK (0xf << 9) -#define PHY1_HSIC1_SLEEP (1 << 12) -#define PHY1_HSIC1_FORCE_SUSPEND (1 << 11) -#define PHY1_HSIC0_SLEEP (1 << 10) -#define PHY1_HSIC0_FORCE_SUSPEND (1 << 9) - -#define PHY1_STD_NORMAL_MASK (0x7 << 6) -#define PHY1_STD_SLEEP (1 << 8) -#define PHY1_STD_ANALOG_POWERDOWN (1 << 7) -#define PHY1_STD_FORCE_SUSPEND (1 << 6) - -#define PHY0_NORMAL_MASK (0x39 << 0) -#define PHY0_SLEEP (1 << 5) -#define PHY0_OTG_DISABLE (1 << 4) -#define PHY0_ANALOG_POWERDOWN (1 << 3) -#define PHY0_FORCE_SUSPEND (1 << 0) - -#define EXYNOS4_PHYCLK EXYNOS4_HSOTG_PHYREG(0x04) -#define PHY1_COMMON_ON_N (1 << 7) -#define PHY0_COMMON_ON_N (1 << 4) -#define PHY0_ID_PULLUP (1 << 2) - -#define EXYNOS4_CLKSEL_SHIFT (0) - -#define EXYNOS4210_CLKSEL_MASK (0x3 << 0) -#define EXYNOS4210_CLKSEL_48M (0x0 << 0) -#define EXYNOS4210_CLKSEL_12M (0x2 << 0) -#define EXYNOS4210_CLKSEL_24M (0x3 << 0) - -#define EXYNOS4X12_CLKSEL_MASK (0x7 << 0) -#define EXYNOS4X12_CLKSEL_9600K (0x0 << 0) -#define EXYNOS4X12_CLKSEL_10M (0x1 << 0) -#define EXYNOS4X12_CLKSEL_12M (0x2 << 0) -#define EXYNOS4X12_CLKSEL_19200K (0x3 << 0) -#define EXYNOS4X12_CLKSEL_20M (0x4 << 0) -#define EXYNOS4X12_CLKSEL_24M (0x5 << 0) - -#define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08) -#define HOST_LINK_PORT_SWRST_MASK (0xf << 6) -#define HOST_LINK_PORT2_SWRST (1 << 9) -#define HOST_LINK_PORT1_SWRST (1 << 8) -#define HOST_LINK_PORT0_SWRST (1 << 7) -#define HOST_LINK_ALL_SWRST (1 << 6) - -#define PHY1_SWRST_MASK (0x7 << 3) -#define PHY1_HSIC_SWRST (1 << 5) -#define PHY1_STD_SWRST (1 << 4) -#define PHY1_ALL_SWRST (1 << 3) - -#define PHY0_SWRST_MASK (0x7 << 0) -#define PHY0_PHYLINK_SWRST (1 << 2) -#define PHY0_HLINK_SWRST (1 << 1) -#define PHY0_SWRST (1 << 0) - -#define EXYNOS4_PHY1CON EXYNOS4_HSOTG_PHYREG(0x34) -#define FPENABLEN (1 << 0) - -#endif /* __PLAT_S5P_REGS_USB_PHY_H */ diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c deleted file mode 100644 index 5f0f5570137..00000000000 --- a/arch/arm/mach-exynos/mach-armlex4210.c +++ /dev/null @@ -1,207 +0,0 @@ -/* linux/arch/arm/mach-exynos4/mach-armlex4210.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/gpio.h> -#include <linux/io.h> -#include <linux/mmc/host.h> -#include <linux/platform_device.h> -#include <linux/serial_core.h> -#include <linux/smsc911x.h> - -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/gpio-cfg.h> -#include <plat/regs-serial.h> -#include <plat/regs-srom.h> -#include <plat/sdhci.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include "common.h" - -/* Following are default values for UCON, ULCON and UFCON UART registers */ -#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ - S3C2410_UCON_RXILEVEL | \ - S3C2410_UCON_TXIRQMODE | \ - S3C2410_UCON_RXIRQMODE | \ - S3C2410_UCON_RXFIFO_TOI | \ - S3C2443_UCON_RXERR_IRQEN) - -#define ARMLEX4210_ULCON_DEFAULT S3C2410_LCON_CS8 - -#define ARMLEX4210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG4 | \ - S5PV210_UFCON_RXTRIG4) - -static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = ARMLEX4210_UCON_DEFAULT, - .ulcon = ARMLEX4210_ULCON_DEFAULT, - .ufcon = ARMLEX4210_UFCON_DEFAULT, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = ARMLEX4210_UCON_DEFAULT, - .ulcon = ARMLEX4210_ULCON_DEFAULT, - .ufcon = ARMLEX4210_UFCON_DEFAULT, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = ARMLEX4210_UCON_DEFAULT, - .ulcon = ARMLEX4210_ULCON_DEFAULT, - .ufcon = ARMLEX4210_UFCON_DEFAULT, - }, - [3] = { - .hwport = 3, - .flags = 0, - .ucon = ARMLEX4210_UCON_DEFAULT, - .ulcon = ARMLEX4210_ULCON_DEFAULT, - .ufcon = ARMLEX4210_UFCON_DEFAULT, - }, -}; - -static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_PERMANENT, -#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT - .max_width = 8, - .host_caps = MMC_CAP_8_BIT_DATA, -#endif -}; - -static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_GPIO, - .ext_cd_gpio = EXYNOS4_GPX2(5), - .ext_cd_gpio_invert = 1, - .max_width = 4, -}; - -static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_PERMANENT, - .max_width = 4, -}; - -static void __init armlex4210_sdhci_init(void) -{ - s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata); - s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata); - s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata); -} - -static void __init armlex4210_wlan_init(void) -{ - /* enable */ - s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf)); - s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP); - - /* reset */ - s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf)); - s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP); - - /* wakeup */ - s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf)); - s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP); -} - -static struct resource armlex4210_smsc911x_resources[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(3), SZ_64K), - [1] = DEFINE_RES_NAMED(IRQ_EINT(27), 1, NULL, IORESOURCE_IRQ \ - | IRQF_TRIGGER_HIGH), -}; - -static struct smsc911x_platform_config smsc9215_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, - .phy_interface = PHY_INTERFACE_MODE_MII, - .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67}, -}; - -static struct platform_device armlex4210_smsc911x = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(armlex4210_smsc911x_resources), - .resource = armlex4210_smsc911x_resources, - .dev = { - .platform_data = &smsc9215_config, - }, -}; - -static struct platform_device *armlex4210_devices[] __initdata = { - &s3c_device_hsmmc0, - &s3c_device_hsmmc2, - &s3c_device_hsmmc3, - &s3c_device_rtc, - &s3c_device_wdt, - &armlex4210_smsc911x, - &exynos4_device_ahci, -}; - -static void __init armlex4210_smsc911x_init(void) -{ - u32 cs1; - - /* configure nCS1 width to 16 bits */ - cs1 = __raw_readl(S5P_SROM_BW) & - ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT); - cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) | - (0 << S5P_SROM_BW__WAITENABLE__SHIFT) | - (1 << S5P_SROM_BW__ADDRMODE__SHIFT) | - (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << - S5P_SROM_BW__NCS1__SHIFT; - __raw_writel(cs1, S5P_SROM_BW); - - /* set timing for nCS1 suitable for ethernet chip */ - __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) | - (0x9 << S5P_SROM_BCX__TACP__SHIFT) | - (0xc << S5P_SROM_BCX__TCAH__SHIFT) | - (0x1 << S5P_SROM_BCX__TCOH__SHIFT) | - (0x6 << S5P_SROM_BCX__TACC__SHIFT) | - (0x1 << S5P_SROM_BCX__TCOS__SHIFT) | - (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1); -} - -static void __init armlex4210_map_io(void) -{ - exynos_init_io(NULL, 0); - s3c24xx_init_uarts(armlex4210_uartcfgs, - ARRAY_SIZE(armlex4210_uartcfgs)); -} - -static void __init armlex4210_machine_init(void) -{ - armlex4210_smsc911x_init(); - - armlex4210_sdhci_init(); - - armlex4210_wlan_init(); - - platform_add_devices(armlex4210_devices, - ARRAY_SIZE(armlex4210_devices)); -} - -MACHINE_START(ARMLEX4210, "ARMLEX4210") - /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */ - .atag_offset = 0x100, - .smp = smp_ops(exynos_smp_ops), - .init_irq = exynos4_init_irq, - .map_io = armlex4210_map_io, - .init_machine = armlex4210_machine_init, - .init_late = exynos_init_late, - .init_time = exynos_init_time, - .restart = exynos4_restart, -MACHINE_END diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c index b9ed834a7ee..0099c6c13bb 100644 --- a/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c @@ -23,11 +23,6 @@ #include "common.h" -static void __init exynos4_dt_map_io(void) -{ - exynos_init_io(NULL, 0); -} - static void __init exynos4_dt_machine_init(void) { of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); @@ -55,8 +50,7 @@ static void __init exynos4_reserve(void) DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */ .smp = smp_ops(exynos_smp_ops), - .init_irq = exynos4_init_irq, - .map_io = exynos4_dt_map_io, + .map_io = exynos_init_io, .init_early = exynos_firmware_init, .init_machine = exynos4_dt_machine_init, .init_late = exynos_init_late, diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 753b94f3fca..d5c8afdeaa3 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -23,11 +23,6 @@ #include "common.h" -static void __init exynos5_dt_map_io(void) -{ - exynos_init_io(NULL, 0); -} - static void __init exynos5_dt_machine_init(void) { struct device_node *i2c_np; @@ -76,9 +71,8 @@ static void __init exynos5_reserve(void) DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)") /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ - .init_irq = exynos5_init_irq, .smp = smp_ops(exynos_smp_ops), - .map_io = exynos5_dt_map_io, + .map_io = exynos_init_io, .init_machine = exynos5_dt_machine_init, .init_late = exynos_init_late, .init_time = exynos_init_time, diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c deleted file mode 100644 index 5c8b2878dbb..00000000000 --- a/arch/arm/mach-exynos/mach-nuri.c +++ /dev/null @@ -1,1388 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/mach-nuri.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/platform_device.h> -#include <linux/serial_core.h> -#include <linux/input.h> -#include <linux/i2c.h> -#include <linux/i2c/atmel_mxt_ts.h> -#include <linux/i2c-gpio.h> -#include <linux/gpio_keys.h> -#include <linux/gpio.h> -#include <linux/power/max8903_charger.h> -#include <linux/power/max17042_battery.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> -#include <linux/mfd/max8997.h> -#include <linux/mfd/max8997-private.h> -#include <linux/mmc/host.h> -#include <linux/fb.h> -#include <linux/pwm_backlight.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <linux/platform_data/mipi-csis.h> -#include <linux/platform_data/s3c-hsotg.h> -#include <linux/platform_data/usb-ehci-s5p.h> -#include <drm/exynos_drm.h> - -#include <video/platform_lcd.h> -#include <video/samsung_fimd.h> -#include <media/m5mols.h> -#include <media/s5k6aa.h> -#include <media/s5p_fimc.h> -#include <media/v4l2-mediabus.h> - -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <plat/adc.h> -#include <plat/regs-serial.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/fb.h> -#include <plat/sdhci.h> -#include <plat/clock.h> -#include <plat/gpio-cfg.h> -#include <plat/mfc.h> -#include <plat/fimc-core.h> -#include <plat/camport.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include "common.h" - -/* Following are default values for UCON, ULCON and UFCON UART registers */ -#define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ - S3C2410_UCON_RXILEVEL | \ - S3C2410_UCON_TXIRQMODE | \ - S3C2410_UCON_RXIRQMODE | \ - S3C2410_UCON_RXFIFO_TOI | \ - S3C2443_UCON_RXERR_IRQEN) - -#define NURI_ULCON_DEFAULT S3C2410_LCON_CS8 - -#define NURI_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG256 | \ - S5PV210_UFCON_RXTRIG256) - -enum fixed_regulator_id { - FIXED_REG_ID_MMC = 0, - FIXED_REG_ID_MAX8903, - FIXED_REG_ID_CAM_A28V, - FIXED_REG_ID_CAM_12V, - FIXED_REG_ID_CAM_VT_15V, -}; - -static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = { - { - .hwport = 0, - .ucon = NURI_UCON_DEFAULT, - .ulcon = NURI_ULCON_DEFAULT, - .ufcon = NURI_UFCON_DEFAULT, - }, - { - .hwport = 1, - .ucon = NURI_UCON_DEFAULT, - .ulcon = NURI_ULCON_DEFAULT, - .ufcon = NURI_UFCON_DEFAULT, - }, - { - .hwport = 2, - .ucon = NURI_UCON_DEFAULT, - .ulcon = NURI_ULCON_DEFAULT, - .ufcon = NURI_UFCON_DEFAULT, - }, - { - .hwport = 3, - .ucon = NURI_UCON_DEFAULT, - .ulcon = NURI_ULCON_DEFAULT, - .ufcon = NURI_UFCON_DEFAULT, - }, -}; - -/* eMMC */ -static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = { - .max_width = 8, - .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | - MMC_CAP_ERASE), - .cd_type = S3C_SDHCI_CD_PERMANENT, -}; - -static struct regulator_consumer_supply emmc_supplies[] = { - REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"), - REGULATOR_SUPPLY("vmmc", "dw_mmc"), -}; - -static struct regulator_init_data emmc_fixed_voltage_init_data = { - .constraints = { - .name = "VMEM_VDD_2.8V", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(emmc_supplies), - .consumer_supplies = emmc_supplies, -}; - -static struct fixed_voltage_config emmc_fixed_voltage_config = { - .supply_name = "MASSMEMORY_EN (inverted)", - .microvolts = 2800000, - .gpio = EXYNOS4_GPL1(1), - .enable_high = false, - .init_data = &emmc_fixed_voltage_init_data, -}; - -static struct platform_device emmc_fixed_voltage = { - .name = "reg-fixed-voltage", - .id = FIXED_REG_ID_MMC, - .dev = { - .platform_data = &emmc_fixed_voltage_config, - }, -}; - -/* SD */ -static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = { - .max_width = 4, - .host_caps = MMC_CAP_4_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, - .ext_cd_gpio = EXYNOS4_GPX3(3), /* XEINT_27 */ - .ext_cd_gpio_invert = 1, - .cd_type = S3C_SDHCI_CD_GPIO, -}; - -/* WLAN */ -static struct s3c_sdhci_platdata nuri_hsmmc3_data __initdata = { - .max_width = 4, - .host_caps = MMC_CAP_4_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, - .cd_type = S3C_SDHCI_CD_EXTERNAL, -}; - -static void __init nuri_sdhci_init(void) -{ - s3c_sdhci0_set_platdata(&nuri_hsmmc0_data); - s3c_sdhci2_set_platdata(&nuri_hsmmc2_data); - s3c_sdhci3_set_platdata(&nuri_hsmmc3_data); -} - -/* GPIO KEYS */ -static struct gpio_keys_button nuri_gpio_keys_tables[] = { - { - .code = KEY_VOLUMEUP, - .gpio = EXYNOS4_GPX2(0), /* XEINT16 */ - .desc = "gpio-keys: KEY_VOLUMEUP", - .type = EV_KEY, - .active_low = 1, - .debounce_interval = 1, - }, { - .code = KEY_VOLUMEDOWN, - .gpio = EXYNOS4_GPX2(1), /* XEINT17 */ - .desc = "gpio-keys: KEY_VOLUMEDOWN", - .type = EV_KEY, - .active_low = 1, - .debounce_interval = 1, - }, { - .code = KEY_POWER, - .gpio = EXYNOS4_GPX2(7), /* XEINT23 */ - .desc = "gpio-keys: KEY_POWER", - .type = EV_KEY, - .active_low = 1, - .wakeup = 1, - .debounce_interval = 1, - }, -}; - -static struct gpio_keys_platform_data nuri_gpio_keys_data = { - .buttons = nuri_gpio_keys_tables, - .nbuttons = ARRAY_SIZE(nuri_gpio_keys_tables), -}; - -static struct platform_device nuri_gpio_keys = { - .name = "gpio-keys", - .dev = { - .platform_data = &nuri_gpio_keys_data, - }, -}; - -#ifdef CONFIG_DRM_EXYNOS -static struct exynos_drm_fimd_pdata drm_fimd_pdata = { - .panel = { - .timing = { - .xres = 1024, - .yres = 600, - .hsync_len = 40, - .left_margin = 79, - .right_margin = 200, - .vsync_len = 10, - .upper_margin = 10, - .lower_margin = 11, - .refresh = 60, - }, - }, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB | - VIDCON0_CLKSEL_LCD, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, - .default_win = 3, - .bpp = 32, -}; - -#else -/* Frame Buffer */ -static struct s3c_fb_pd_win nuri_fb_win0 = { - .max_bpp = 24, - .default_bpp = 16, - .xres = 1024, - .yres = 600, - .virtual_x = 1024, - .virtual_y = 2 * 600, -}; - -static struct fb_videomode nuri_lcd_timing = { - .left_margin = 64, - .right_margin = 16, - .upper_margin = 64, - .lower_margin = 1, - .hsync_len = 48, - .vsync_len = 3, - .xres = 1024, - .yres = 600, - .refresh = 60, -}; - -static struct s3c_fb_platdata nuri_fb_pdata __initdata = { - .win[0] = &nuri_fb_win0, - .vtiming = &nuri_lcd_timing, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB | - VIDCON0_CLKSEL_LCD, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, - .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, -}; -#endif - -static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power) -{ - int gpio = EXYNOS4_GPE1(5); - - gpio_request(gpio, "LVDS_nSHDN"); - gpio_direction_output(gpio, power); - gpio_free(gpio); -} - -static int nuri_bl_init(struct device *dev) -{ - return gpio_request_one(EXYNOS4_GPE2(3), GPIOF_OUT_INIT_LOW, - "LCD_LD0_EN"); -} - -static int nuri_bl_notify(struct device *dev, int brightness) -{ - if (brightness < 1) - brightness = 0; - - gpio_set_value(EXYNOS4_GPE2(3), 1); - - return brightness; -} - -static void nuri_bl_exit(struct device *dev) -{ - gpio_free(EXYNOS4_GPE2(3)); -} - -/* nuri pwm backlight */ -static struct platform_pwm_backlight_data nuri_backlight_data = { - .pwm_id = 0, - .pwm_period_ns = 30000, - .max_brightness = 100, - .dft_brightness = 50, - .init = nuri_bl_init, - .notify = nuri_bl_notify, - .exit = nuri_bl_exit, -}; - -static struct platform_device nuri_backlight_device = { - .name = "pwm-backlight", - .id = -1, - .dev = { - .parent = &s3c_device_timer[0].dev, - .platform_data = &nuri_backlight_data, - }, -}; - -static struct plat_lcd_data nuri_lcd_platform_data = { - .set_power = nuri_lcd_power_on, -}; - -static struct platform_device nuri_lcd_device = { - .name = "platform-lcd", - .id = -1, - .dev = { - .platform_data = &nuri_lcd_platform_data, - }, -}; - -/* I2C1 */ -static struct i2c_board_info i2c1_devs[] __initdata = { - /* Gyro, To be updated */ -}; - -/* TSP */ -static struct mxt_platform_data mxt_platform_data = { - .x_line = 18, - .y_line = 11, - .x_size = 1024, - .y_size = 600, - .blen = 0x1, - .threshold = 0x28, - .voltage = 2800000, /* 2.8V */ - .orient = MXT_DIAGONAL_COUNTER, - .irqflags = IRQF_TRIGGER_FALLING, -}; - -static struct s3c2410_platform_i2c i2c3_data __initdata = { - .flags = 0, - .bus_num = 3, - .slave_addr = 0x10, - .frequency = 400 * 1000, - .sda_delay = 100, -}; - -static struct i2c_board_info i2c3_devs[] __initdata = { - { - I2C_BOARD_INFO("atmel_mxt_ts", 0x4a), - .platform_data = &mxt_platform_data, - .irq = IRQ_EINT(4), - }, -}; - -static void __init nuri_tsp_init(void) -{ - int gpio; - - /* TOUCH_INT: XEINT_4 */ - gpio = EXYNOS4_GPX0(4); - gpio_request(gpio, "TOUCH_INT"); - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); -} - -static struct regulator_consumer_supply __initdata max8997_ldo1_[] = { - REGULATOR_SUPPLY("vdd", "s5p-adc"), /* Used by CPU's ADC drv */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo3_[] = { - REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* USB */ - REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo4_[] = { - REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo5_[] = { - REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */ -}; -static struct regulator_consumer_supply nuri_max8997_ldo6_consumer[] = { - REGULATOR_SUPPLY("vdd_reg", "6-003c"), /* S5K6AA camera */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo7_[] = { - REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo8_[] = { - REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), /* USB */ - REGULATOR_SUPPLY("vdac", NULL), /* Used by CPU */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo11_[] = { - REGULATOR_SUPPLY("vcc", "platform-lcd"), /* U804 LVDS */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo12_[] = { - REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo13_[] = { - REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.2"), /* TFLASH */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo14_[] = { - REGULATOR_SUPPLY("inmotor", "max8997-haptic"), -}; -static struct regulator_consumer_supply __initdata max8997_ldo15_[] = { - REGULATOR_SUPPLY("avdd", "3-004a"), /* Touch Screen */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo16_[] = { - REGULATOR_SUPPLY("d_sensor", "0-001f"), /* HDC803 */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo18_[] = { - REGULATOR_SUPPLY("vdd", "3-004a"), /* Touch Screen */ -}; -static struct regulator_consumer_supply __initdata max8997_buck1_[] = { - REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */ -}; -static struct regulator_consumer_supply __initdata max8997_buck2_[] = { - REGULATOR_SUPPLY("vdd_int", "exynos4210-busfreq.0"), /* CPUFREQ */ -}; -static struct regulator_consumer_supply __initdata max8997_buck3_[] = { - REGULATOR_SUPPLY("vdd", "mali_dev.0"), /* G3D of Exynos 4 */ -}; -static struct regulator_consumer_supply __initdata max8997_buck4_[] = { - REGULATOR_SUPPLY("core", "0-001f"), /* HDC803 */ -}; -static struct regulator_consumer_supply __initdata max8997_buck6_[] = { - REGULATOR_SUPPLY("dig_28", "0-001f"), /* pin "7" of HDC803 */ -}; -static struct regulator_consumer_supply __initdata max8997_esafeout1_[] = { - REGULATOR_SUPPLY("usb_vbus", NULL), /* CPU's USB OTG */ -}; -static struct regulator_consumer_supply __initdata max8997_esafeout2_[] = { - REGULATOR_SUPPLY("usb_vbus", "modemctl"), /* VBUS of Modem */ -}; - -static struct regulator_consumer_supply __initdata max8997_charger_[] = { - REGULATOR_SUPPLY("vinchg1", "charger-manager.0"), -}; -static struct regulator_consumer_supply __initdata max8997_chg_toff_[] = { - REGULATOR_SUPPLY("vinchg_stop", NULL), /* for jack interrupt handlers */ -}; - -static struct regulator_consumer_supply __initdata max8997_32khz_ap_[] = { - REGULATOR_SUPPLY("gps_clk", "bcm4751"), - REGULATOR_SUPPLY("bt_clk", "bcm4330-b1"), - REGULATOR_SUPPLY("wifi_clk", "bcm433-b1"), -}; - -static struct regulator_init_data __initdata max8997_ldo1_data = { - .constraints = { - .name = "VADC_3.3V_C210", - .min_uV = 3300000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo1_), - .consumer_supplies = max8997_ldo1_, -}; - -static struct regulator_init_data __initdata max8997_ldo2_data = { - .constraints = { - .name = "VALIVE_1.1V_C210", - .min_uV = 1100000, - .max_uV = 1100000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_ldo3_data = { - .constraints = { - .name = "VUSB_1.1V_C210", - .min_uV = 1100000, - .max_uV = 1100000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo3_), - .consumer_supplies = max8997_ldo3_, -}; - -static struct regulator_init_data __initdata max8997_ldo4_data = { - .constraints = { - .name = "VMIPI_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo4_), - .consumer_supplies = max8997_ldo4_, -}; - -static struct regulator_init_data __initdata max8997_ldo5_data = { - .constraints = { - .name = "VHSIC_1.2V_C210", - .min_uV = 1200000, - .max_uV = 1200000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo5_), - .consumer_supplies = max8997_ldo5_, -}; - -static struct regulator_init_data __initdata max8997_ldo6_data = { - .constraints = { - .name = "VCC_1.8V_PDA", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(nuri_max8997_ldo6_consumer), - .consumer_supplies = nuri_max8997_ldo6_consumer, -}; - -static struct regulator_init_data __initdata max8997_ldo7_data = { - .constraints = { - .name = "CAM_ISP_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo7_), - .consumer_supplies = max8997_ldo7_, -}; - -static struct regulator_init_data __initdata max8997_ldo8_data = { - .constraints = { - .name = "VUSB+VDAC_3.3V_C210", - .min_uV = 3300000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo8_), - .consumer_supplies = max8997_ldo8_, -}; - -static struct regulator_init_data __initdata max8997_ldo9_data = { - .constraints = { - .name = "VCC_2.8V_PDA", - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_ldo10_data = { - .constraints = { - .name = "VPLL_1.1V_C210", - .min_uV = 1100000, - .max_uV = 1100000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_ldo11_data = { - .constraints = { - .name = "LVDS_VDD3.3V", - .min_uV = 3300000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .boot_on = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo11_), - .consumer_supplies = max8997_ldo11_, -}; - -static struct regulator_init_data __initdata max8997_ldo12_data = { - .constraints = { - .name = "VT_CAM_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo12_), - .consumer_supplies = max8997_ldo12_, -}; - -static struct regulator_init_data __initdata max8997_ldo13_data = { - .constraints = { - .name = "VTF_2.8V", - .min_uV = 2800000, - .max_uV = 2800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo13_), - .consumer_supplies = max8997_ldo13_, -}; - -static struct regulator_init_data __initdata max8997_ldo14_data = { - .constraints = { - .name = "VCC_3.0V_MOTOR", - .min_uV = 3000000, - .max_uV = 3000000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo14_), - .consumer_supplies = max8997_ldo14_, -}; - -static struct regulator_init_data __initdata max8997_ldo15_data = { - .constraints = { - .name = "VTOUCH_ADVV2.8V", - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo15_), - .consumer_supplies = max8997_ldo15_, -}; - -static struct regulator_init_data __initdata max8997_ldo16_data = { - .constraints = { - .name = "CAM_SENSOR_IO_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo16_), - .consumer_supplies = max8997_ldo16_, -}; - -static struct regulator_init_data __initdata max8997_ldo18_data = { - .constraints = { - .name = "VTOUCH_VDD2.8V", - .min_uV = 2800000, - .max_uV = 2800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo18_), - .consumer_supplies = max8997_ldo18_, -}; - -static struct regulator_init_data __initdata max8997_ldo21_data = { - .constraints = { - .name = "VDDQ_M1M2_1.2V", - .min_uV = 1200000, - .max_uV = 1200000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_buck1_data = { - .constraints = { - .name = "VARM_1.2V_C210", - .min_uV = 900000, - .max_uV = 1350000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .always_on = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_buck1_), - .consumer_supplies = max8997_buck1_, -}; - -static struct regulator_init_data __initdata max8997_buck2_data = { - .constraints = { - .name = "VINT_1.1V_C210", - .min_uV = 900000, - .max_uV = 1200000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .always_on = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_buck2_), - .consumer_supplies = max8997_buck2_, -}; - -static struct regulator_init_data __initdata max8997_buck3_data = { - .constraints = { - .name = "VG3D_1.1V_C210", - .min_uV = 900000, - .max_uV = 1100000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_buck3_), - .consumer_supplies = max8997_buck3_, -}; - -static struct regulator_init_data __initdata max8997_buck4_data = { - .constraints = { - .name = "CAM_ISP_CORE_1.2V", - .min_uV = 1200000, - .max_uV = 1200000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_buck4_), - .consumer_supplies = max8997_buck4_, -}; - -static struct regulator_init_data __initdata max8997_buck5_data = { - .constraints = { - .name = "VMEM_1.2V_C210", - .min_uV = 1200000, - .max_uV = 1200000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_buck6_data = { - .constraints = { - .name = "CAM_AF_2.8V", - .min_uV = 2800000, - .max_uV = 2800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_buck6_), - .consumer_supplies = max8997_buck6_, -}; - -static struct regulator_init_data __initdata max8997_buck7_data = { - .constraints = { - .name = "VCC_SUB_2.0V", - .min_uV = 2000000, - .max_uV = 2000000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_32khz_ap_data = { - .constraints = { - .name = "32KHz AP", - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_32khz_ap_), - .consumer_supplies = max8997_32khz_ap_, -}; - -static struct regulator_init_data __initdata max8997_32khz_cp_data = { - .constraints = { - .name = "32KHz CP", - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_vichg_data = { - .constraints = { - .name = "VICHG", - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_esafeout1_data = { - .constraints = { - .name = "SAFEOUT1", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .always_on = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_esafeout1_), - .consumer_supplies = max8997_esafeout1_, -}; - -static struct regulator_init_data __initdata max8997_esafeout2_data = { - .constraints = { - .name = "SAFEOUT2", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_esafeout2_), - .consumer_supplies = max8997_esafeout2_, -}; - -static struct regulator_init_data __initdata max8997_charger_cv_data = { - .constraints = { - .name = "CHARGER_CV", - .min_uV = 4200000, - .max_uV = 4200000, - .apply_uV = 1, - }, -}; - -static struct regulator_init_data __initdata max8997_charger_data = { - .constraints = { - .name = "CHARGER", - .min_uA = 200000, - .max_uA = 950000, - .boot_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | - REGULATOR_CHANGE_CURRENT, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_charger_), - .consumer_supplies = max8997_charger_, -}; - -static struct regulator_init_data __initdata max8997_charger_topoff_data = { - .constraints = { - .name = "CHARGER TOPOFF", - .min_uA = 50000, - .max_uA = 200000, - .valid_ops_mask = REGULATOR_CHANGE_CURRENT, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_chg_toff_), - .consumer_supplies = max8997_chg_toff_, -}; - -static struct max8997_regulator_data __initdata nuri_max8997_regulators[] = { - { MAX8997_LDO1, &max8997_ldo1_data }, - { MAX8997_LDO2, &max8997_ldo2_data }, - { MAX8997_LDO3, &max8997_ldo3_data }, - { MAX8997_LDO4, &max8997_ldo4_data }, - { MAX8997_LDO5, &max8997_ldo5_data }, - { MAX8997_LDO6, &max8997_ldo6_data }, - { MAX8997_LDO7, &max8997_ldo7_data }, - { MAX8997_LDO8, &max8997_ldo8_data }, - { MAX8997_LDO9, &max8997_ldo9_data }, - { MAX8997_LDO10, &max8997_ldo10_data }, - { MAX8997_LDO11, &max8997_ldo11_data }, - { MAX8997_LDO12, &max8997_ldo12_data }, - { MAX8997_LDO13, &max8997_ldo13_data }, - { MAX8997_LDO14, &max8997_ldo14_data }, - { MAX8997_LDO15, &max8997_ldo15_data }, - { MAX8997_LDO16, &max8997_ldo16_data }, - - { MAX8997_LDO18, &max8997_ldo18_data }, - { MAX8997_LDO21, &max8997_ldo21_data }, - - { MAX8997_BUCK1, &max8997_buck1_data }, - { MAX8997_BUCK2, &max8997_buck2_data }, - { MAX8997_BUCK3, &max8997_buck3_data }, - { MAX8997_BUCK4, &max8997_buck4_data }, - { MAX8997_BUCK5, &max8997_buck5_data }, - { MAX8997_BUCK6, &max8997_buck6_data }, - { MAX8997_BUCK7, &max8997_buck7_data }, - - { MAX8997_EN32KHZ_AP, &max8997_32khz_ap_data }, - { MAX8997_EN32KHZ_CP, &max8997_32khz_cp_data }, - - { MAX8997_ENVICHG, &max8997_vichg_data }, - { MAX8997_ESAFEOUT1, &max8997_esafeout1_data }, - { MAX8997_ESAFEOUT2, &max8997_esafeout2_data }, - { MAX8997_CHARGER_CV, &max8997_charger_cv_data }, - { MAX8997_CHARGER, &max8997_charger_data }, - { MAX8997_CHARGER_TOPOFF, &max8997_charger_topoff_data }, -}; - -static struct max8997_platform_data __initdata nuri_max8997_pdata = { - .wakeup = 1, - - .num_regulators = ARRAY_SIZE(nuri_max8997_regulators), - .regulators = nuri_max8997_regulators, - - .buck125_gpios = { EXYNOS4_GPX0(5), EXYNOS4_GPX0(6), EXYNOS4_GPL0(0) }, - - .buck1_voltage[0] = 1350000, /* 1.35V */ - .buck1_voltage[1] = 1300000, /* 1.3V */ - .buck1_voltage[2] = 1250000, /* 1.25V */ - .buck1_voltage[3] = 1200000, /* 1.2V */ - .buck1_voltage[4] = 1150000, /* 1.15V */ - .buck1_voltage[5] = 1100000, /* 1.1V */ - .buck1_voltage[6] = 1000000, /* 1.0V */ - .buck1_voltage[7] = 950000, /* 0.95V */ - - .buck2_voltage[0] = 1100000, /* 1.1V */ - .buck2_voltage[1] = 1000000, /* 1.0V */ - .buck2_voltage[2] = 950000, /* 0.95V */ - .buck2_voltage[3] = 900000, /* 0.9V */ - .buck2_voltage[4] = 1100000, /* 1.1V */ - .buck2_voltage[5] = 1000000, /* 1.0V */ - .buck2_voltage[6] = 950000, /* 0.95V */ - .buck2_voltage[7] = 900000, /* 0.9V */ - - .buck5_voltage[0] = 1200000, /* 1.2V */ - .buck5_voltage[1] = 1200000, /* 1.2V */ - .buck5_voltage[2] = 1200000, /* 1.2V */ - .buck5_voltage[3] = 1200000, /* 1.2V */ - .buck5_voltage[4] = 1200000, /* 1.2V */ - .buck5_voltage[5] = 1200000, /* 1.2V */ - .buck5_voltage[6] = 1200000, /* 1.2V */ - .buck5_voltage[7] = 1200000, /* 1.2V */ -}; - -/* GPIO I2C 5 (PMIC) */ -enum { I2C5_MAX8997 }; -static struct i2c_board_info i2c5_devs[] __initdata = { - [I2C5_MAX8997] = { - I2C_BOARD_INFO("max8997", 0xCC >> 1), - .platform_data = &nuri_max8997_pdata, - }, -}; - -static struct max17042_platform_data nuri_battery_platform_data = { -}; - -/* GPIO I2C 9 (Fuel Gauge) */ -static struct i2c_gpio_platform_data i2c9_gpio_data = { - .sda_pin = EXYNOS4_GPY4(0), /* XM0ADDR_8 */ - .scl_pin = EXYNOS4_GPY4(1), /* XM0ADDR_9 */ -}; -static struct platform_device i2c9_gpio = { - .name = "i2c-gpio", - .id = 9, - .dev = { - .platform_data = &i2c9_gpio_data, - }, -}; -enum { I2C9_MAX17042}; -static struct i2c_board_info i2c9_devs[] __initdata = { - [I2C9_MAX17042] = { - I2C_BOARD_INFO("max17042", 0x36), - .platform_data = &nuri_battery_platform_data, - }, -}; - -/* MAX8903 Secondary Charger */ -static struct regulator_consumer_supply supplies_max8903[] = { - REGULATOR_SUPPLY("vinchg2", "charger-manager.0"), -}; - -static struct regulator_init_data max8903_charger_en_data = { - .constraints = { - .name = "VOUT_CHARGER", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(supplies_max8903), - .consumer_supplies = supplies_max8903, -}; - -static struct fixed_voltage_config max8903_charger_en = { - .supply_name = "VOUT_CHARGER", - .microvolts = 5000000, /* Assume 5VDC */ - .gpio = EXYNOS4_GPY4(5), /* TA_EN negaged */ - .enable_high = 0, /* Enable = Low */ - .enabled_at_boot = 1, - .init_data = &max8903_charger_en_data, -}; - -static struct platform_device max8903_fixed_reg_dev = { - .name = "reg-fixed-voltage", - .id = FIXED_REG_ID_MAX8903, - .dev = { .platform_data = &max8903_charger_en }, -}; - -static struct max8903_pdata nuri_max8903 = { - /* - * cen: don't control with the driver, let it be - * controlled by regulator above - */ - .dok = EXYNOS4_GPX1(4), /* TA_nCONNECTED */ - /* uok, usus: not connected */ - .chg = EXYNOS4_GPE2(0), /* TA_nCHG */ - /* flt: vcc_1.8V_pda */ - .dcm = EXYNOS4_GPL0(1), /* CURR_ADJ */ - - .dc_valid = true, - .usb_valid = false, /* USB is not wired to MAX8903 */ -}; - -static struct platform_device nuri_max8903_device = { - .name = "max8903-charger", - .dev = { - .platform_data = &nuri_max8903, - }, -}; - -static void __init nuri_power_init(void) -{ - int gpio; - int ta_en = 0; - - gpio = EXYNOS4_GPX0(7); - gpio_request(gpio, "AP_PMIC_IRQ"); - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - - gpio = EXYNOS4_GPX2(3); - gpio_request(gpio, "FUEL_ALERT"); - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - - gpio = nuri_max8903.dok; - gpio_request(gpio, "TA_nCONNECTED"); - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - ta_en = gpio_get_value(gpio) ? 0 : 1; - - gpio = nuri_max8903.chg; - gpio_request(gpio, "TA_nCHG"); - gpio_direction_input(gpio); - - gpio = nuri_max8903.dcm; - gpio_request(gpio, "CURR_ADJ"); - gpio_direction_output(gpio, ta_en); -} - -/* USB EHCI */ -static struct s5p_ehci_platdata nuri_ehci_pdata; - -static void __init nuri_ehci_init(void) -{ - struct s5p_ehci_platdata *pdata = &nuri_ehci_pdata; - - s5p_ehci_set_platdata(pdata); -} - -/* USB OTG */ -static struct s3c_hsotg_plat nuri_hsotg_pdata; - -/* CAMERA */ -static struct regulator_consumer_supply cam_vt_cam15_supply = - REGULATOR_SUPPLY("vdd_core", "6-003c"); - -static struct regulator_init_data cam_vt_cam15_reg_init_data = { - .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS }, - .num_consumer_supplies = 1, - .consumer_supplies = &cam_vt_cam15_supply, -}; - -static struct fixed_voltage_config cam_vt_cam15_fixed_voltage_cfg = { - .supply_name = "VT_CAM_1.5V", - .microvolts = 1500000, - .gpio = EXYNOS4_GPE2(2), /* VT_CAM_1.5V_EN */ - .enable_high = 1, - .init_data = &cam_vt_cam15_reg_init_data, -}; - -static struct platform_device cam_vt_cam15_fixed_rdev = { - .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_15V, - .dev = { .platform_data = &cam_vt_cam15_fixed_voltage_cfg }, -}; - -static struct regulator_consumer_supply cam_vdda_supply[] = { - REGULATOR_SUPPLY("vdda", "6-003c"), - REGULATOR_SUPPLY("a_sensor", "0-001f"), -}; - -static struct regulator_init_data cam_vdda_reg_init_data = { - .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS }, - .num_consumer_supplies = ARRAY_SIZE(cam_vdda_supply), - .consumer_supplies = cam_vdda_supply, -}; - -static struct fixed_voltage_config cam_vdda_fixed_voltage_cfg = { - .supply_name = "CAM_IO_EN", - .microvolts = 2800000, - .gpio = EXYNOS4_GPE2(1), /* CAM_IO_EN */ - .enable_high = 1, - .init_data = &cam_vdda_reg_init_data, -}; - -static struct platform_device cam_vdda_fixed_rdev = { - .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_A28V, - .dev = { .platform_data = &cam_vdda_fixed_voltage_cfg }, -}; - -static struct regulator_consumer_supply camera_8m_12v_supply = - REGULATOR_SUPPLY("dig_12", "0-001f"); - -static struct regulator_init_data cam_8m_12v_reg_init_data = { - .num_consumer_supplies = 1, - .consumer_supplies = &camera_8m_12v_supply, - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS - }, -}; - -static struct fixed_voltage_config cam_8m_12v_fixed_voltage_cfg = { - .supply_name = "8M_1.2V", - .microvolts = 1200000, - .gpio = EXYNOS4_GPE2(5), /* 8M_1.2V_EN */ - .enable_high = 1, - .init_data = &cam_8m_12v_reg_init_data, -}; - -static struct platform_device cam_8m_12v_fixed_rdev = { - .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_12V, - .dev = { .platform_data = &cam_8m_12v_fixed_voltage_cfg }, -}; - -static struct s5p_platform_mipi_csis mipi_csis_platdata = { - .clk_rate = 166000000UL, - .lanes = 2, - .hs_settle = 12, -}; - -#define GPIO_CAM_MEGA_RST EXYNOS4_GPY3(7) /* ISP_RESET */ -#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPL2(5) -#define GPIO_CAM_VT_NSTBY EXYNOS4_GPL2(0) -#define GPIO_CAM_VT_NRST EXYNOS4_GPL2(1) - -static struct s5k6aa_platform_data s5k6aa_pldata = { - .mclk_frequency = 24000000UL, - .gpio_reset = { GPIO_CAM_VT_NRST, 0 }, - .gpio_stby = { GPIO_CAM_VT_NSTBY, 0 }, - .bus_type = V4L2_MBUS_PARALLEL, - .horiz_flip = 1, -}; - -static struct i2c_board_info s5k6aa_board_info = { - I2C_BOARD_INFO("S5K6AA", 0x3c), - .platform_data = &s5k6aa_pldata, -}; - -static struct m5mols_platform_data m5mols_platdata = { - .gpio_reset = GPIO_CAM_MEGA_RST, -}; - -static struct i2c_board_info m5mols_board_info = { - I2C_BOARD_INFO("M5MOLS", 0x1F), - .platform_data = &m5mols_platdata, -}; - -static struct fimc_source_info nuri_camera_sensors[] = { - { - .flags = V4L2_MBUS_PCLK_SAMPLE_RISING | - V4L2_MBUS_VSYNC_ACTIVE_LOW, - .fimc_bus_type = FIMC_BUS_TYPE_ITU_601, - .board_info = &s5k6aa_board_info, - .clk_frequency = 24000000UL, - .i2c_bus_num = 6, - }, { - .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING | - V4L2_MBUS_VSYNC_ACTIVE_LOW, - .fimc_bus_type = FIMC_BUS_TYPE_MIPI_CSI2, - .board_info = &m5mols_board_info, - .clk_frequency = 24000000UL, - }, -}; - -static struct s5p_platform_fimc fimc_md_platdata = { - .source_info = nuri_camera_sensors, - .num_clients = ARRAY_SIZE(nuri_camera_sensors), -}; - -static struct gpio nuri_camera_gpios[] = { - { GPIO_CAM_VT_NSTBY, GPIOF_OUT_INIT_LOW, "CAM_VGA_NSTBY" }, - { GPIO_CAM_VT_NRST, GPIOF_OUT_INIT_LOW, "CAM_VGA_NRST" }, - { GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" }, - { GPIO_CAM_MEGA_RST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" }, -}; - -static void __init nuri_camera_init(void) -{ - s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata), - &s5p_device_mipi_csis0); - s3c_set_platdata(&fimc_md_platdata, sizeof(fimc_md_platdata), - &s5p_device_fimc_md); - - if (gpio_request_array(nuri_camera_gpios, - ARRAY_SIZE(nuri_camera_gpios))) { - pr_err("%s: GPIO request failed\n", __func__); - return; - } - - m5mols_board_info.irq = s5p_register_gpio_interrupt(GPIO_CAM_8M_ISP_INT); - if (m5mols_board_info.irq >= 0) - s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xF)); - else - pr_err("%s: Failed to configure 8M_ISP_INT GPIO\n", __func__); - - /* Free GPIOs controlled directly by the sensor drivers. */ - gpio_free(GPIO_CAM_VT_NRST); - gpio_free(GPIO_CAM_VT_NSTBY); - gpio_free(GPIO_CAM_MEGA_RST); - - if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) { - pr_err("%s: Camera port A setup failed\n", __func__); - return; - } - /* Increase drive strength of the sensor clock output */ - s5p_gpio_set_drvstr(EXYNOS4_GPJ1(3), S5P_GPIO_DRVSTR_LV4); -} - -static struct s3c2410_platform_i2c nuri_i2c6_platdata __initdata = { - .frequency = 400000U, - .sda_delay = 200, - .bus_num = 6, -}; - -static struct s3c2410_platform_i2c nuri_i2c0_platdata __initdata = { - .frequency = 400000U, - .sda_delay = 200, -}; - -/* DEVFREQ controlling memory/bus */ -static struct platform_device exynos4_bus_devfreq = { - .name = "exynos4210-busfreq", -}; - -static struct platform_device *nuri_devices[] __initdata = { - /* Samsung Platform Devices */ - &s3c_device_i2c5, /* PMIC should initialize first */ - &s3c_device_i2c0, - &s3c_device_i2c6, - &emmc_fixed_voltage, - &s5p_device_mipi_csis0, - &s5p_device_fimc0, - &s5p_device_fimc1, - &s5p_device_fimc2, - &s5p_device_fimc3, - &s5p_device_fimd0, - &s3c_device_hsmmc0, - &s3c_device_hsmmc2, - &s3c_device_hsmmc3, - &s3c_device_wdt, - &s3c_device_timer[0], - &s5p_device_ehci, - &s3c_device_i2c3, - &i2c9_gpio, - &s3c_device_adc, - &s5p_device_g2d, - &s5p_device_jpeg, - &s3c_device_rtc, - &s5p_device_mfc, - &s5p_device_mfc_l, - &s5p_device_mfc_r, - &s5p_device_fimc_md, - &s3c_device_usb_hsotg, - - /* NURI Devices */ - &nuri_gpio_keys, - &nuri_lcd_device, - &nuri_backlight_device, - &max8903_fixed_reg_dev, - &nuri_max8903_device, - &cam_vt_cam15_fixed_rdev, - &cam_vdda_fixed_rdev, - &cam_8m_12v_fixed_rdev, - &exynos4_bus_devfreq, -}; - -static void __init nuri_map_io(void) -{ - exynos_init_io(NULL, 0); - s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs)); - xxti_f = 0; - xusbxti_f = 24000000; -} - -static void __init nuri_reserve(void) -{ - s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); -} - -static void __init nuri_machine_init(void) -{ - nuri_sdhci_init(); - nuri_tsp_init(); - nuri_power_init(); - - s3c_i2c0_set_platdata(&nuri_i2c0_platdata); - i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); - s3c_i2c3_set_platdata(&i2c3_data); - i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs)); - s3c_i2c5_set_platdata(NULL); - i2c5_devs[I2C5_MAX8997].irq = gpio_to_irq(EXYNOS4_GPX0(7)); - i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs)); - i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3)); - i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs)); - s3c_i2c6_set_platdata(&nuri_i2c6_platdata); - -#ifdef CONFIG_DRM_EXYNOS - s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; - exynos4_fimd0_gpio_setup_24bpp(); -#else - s5p_fimd0_set_platdata(&nuri_fb_pdata); -#endif - - nuri_camera_init(); - - nuri_ehci_init(); - s3c_hsotg_set_platdata(&nuri_hsotg_pdata); - - /* Last */ - platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices)); -} - -MACHINE_START(NURI, "NURI") - /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */ - .atag_offset = 0x100, - .smp = smp_ops(exynos_smp_ops), - .init_irq = exynos4_init_irq, - .map_io = nuri_map_io, - .init_machine = nuri_machine_init, - .init_late = exynos_init_late, - .init_time = exynos_init_time, - .reserve = &nuri_reserve, - .restart = exynos4_restart, -MACHINE_END diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c deleted file mode 100644 index 27f03ed5d06..00000000000 --- a/arch/arm/mach-exynos/mach-origen.c +++ /dev/null @@ -1,823 +0,0 @@ -/* linux/arch/arm/mach-exynos4/mach-origen.c - * - * Copyright (c) 2011 Insignal Co., Ltd. - * http://www.insignal.co.kr/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/serial_core.h> -#include <linux/leds.h> -#include <linux/gpio.h> -#include <linux/mmc/host.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/input.h> -#include <linux/pwm.h> -#include <linux/pwm_backlight.h> -#include <linux/gpio_keys.h> -#include <linux/i2c.h> -#include <linux/regulator/machine.h> -#include <linux/mfd/max8997.h> -#include <linux/lcd.h> -#include <linux/rfkill-gpio.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <linux/platform_data/s3c-hsotg.h> -#include <linux/platform_data/usb-ehci-s5p.h> -#include <linux/platform_data/usb-ohci-exynos.h> - -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <video/platform_lcd.h> -#include <video/samsung_fimd.h> - -#include <plat/regs-serial.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/sdhci.h> -#include <plat/clock.h> -#include <plat/gpio-cfg.h> -#include <plat/backlight.h> -#include <plat/fb.h> -#include <plat/mfc.h> -#include <plat/hdmi.h> - -#include <mach/map.h> -#include <mach/irqs.h> - -#include <drm/exynos_drm.h> -#include "common.h" - -/* Following are default values for UCON, ULCON and UFCON UART registers */ -#define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ - S3C2410_UCON_RXILEVEL | \ - S3C2410_UCON_TXIRQMODE | \ - S3C2410_UCON_RXIRQMODE | \ - S3C2410_UCON_RXFIFO_TOI | \ - S3C2443_UCON_RXERR_IRQEN) - -#define ORIGEN_ULCON_DEFAULT S3C2410_LCON_CS8 - -#define ORIGEN_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG4 | \ - S5PV210_UFCON_RXTRIG4) - -static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = ORIGEN_UCON_DEFAULT, - .ulcon = ORIGEN_ULCON_DEFAULT, - .ufcon = ORIGEN_UFCON_DEFAULT, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = ORIGEN_UCON_DEFAULT, - .ulcon = ORIGEN_ULCON_DEFAULT, - .ufcon = ORIGEN_UFCON_DEFAULT, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = ORIGEN_UCON_DEFAULT, - .ulcon = ORIGEN_ULCON_DEFAULT, - .ufcon = ORIGEN_UFCON_DEFAULT, - }, - [3] = { - .hwport = 3, - .flags = 0, - .ucon = ORIGEN_UCON_DEFAULT, - .ulcon = ORIGEN_ULCON_DEFAULT, - .ufcon = ORIGEN_UFCON_DEFAULT, - }, -}; - -static struct regulator_consumer_supply __initdata ldo3_consumer[] = { - REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */ - REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */ - REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */ - REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), /* OTG */ -}; -static struct regulator_consumer_supply __initdata ldo6_consumer[] = { - REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */ -}; -static struct regulator_consumer_supply __initdata ldo7_consumer[] = { - REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */ -}; -static struct regulator_consumer_supply __initdata ldo8_consumer[] = { - REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */ - REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), /* HDMI */ - REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* OTG */ -}; -static struct regulator_consumer_supply __initdata ldo9_consumer[] = { - REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */ -}; -static struct regulator_consumer_supply __initdata ldo11_consumer[] = { - REGULATOR_SUPPLY("dvdd", "alc5625"), /* Realtek ALC5625 */ -}; -static struct regulator_consumer_supply __initdata ldo14_consumer[] = { - REGULATOR_SUPPLY("avdd18", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */ -}; -static struct regulator_consumer_supply __initdata ldo17_consumer[] = { - REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */ -}; -static struct regulator_consumer_supply __initdata buck1_consumer[] = { - REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */ -}; -static struct regulator_consumer_supply __initdata buck2_consumer[] = { - REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */ -}; -static struct regulator_consumer_supply __initdata buck3_consumer[] = { - REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */ -}; -static struct regulator_consumer_supply __initdata buck7_consumer[] = { - REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */ -}; - -static struct regulator_init_data __initdata max8997_ldo1_data = { - .constraints = { - .name = "VDD_ABB_3.3V", - .min_uV = 3300000, - .max_uV = 3300000, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_ldo2_data = { - .constraints = { - .name = "VDD_ALIVE_1.1V", - .min_uV = 1100000, - .max_uV = 1100000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_ldo3_data = { - .constraints = { - .name = "VMIPI_1.1V", - .min_uV = 1100000, - .max_uV = 1100000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo3_consumer), - .consumer_supplies = ldo3_consumer, -}; - -static struct regulator_init_data __initdata max8997_ldo4_data = { - .constraints = { - .name = "VDD_RTC_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_ldo6_data = { - .constraints = { - .name = "VMIPI_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo6_consumer), - .consumer_supplies = ldo6_consumer, -}; - -static struct regulator_init_data __initdata max8997_ldo7_data = { - .constraints = { - .name = "VDD_AUD_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo7_consumer), - .consumer_supplies = ldo7_consumer, -}; - -static struct regulator_init_data __initdata max8997_ldo8_data = { - .constraints = { - .name = "VADC_3.3V", - .min_uV = 3300000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo8_consumer), - .consumer_supplies = ldo8_consumer, -}; - -static struct regulator_init_data __initdata max8997_ldo9_data = { - .constraints = { - .name = "DVDD_SWB_2.8V", - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo9_consumer), - .consumer_supplies = ldo9_consumer, -}; - -static struct regulator_init_data __initdata max8997_ldo10_data = { - .constraints = { - .name = "VDD_PLL_1.1V", - .min_uV = 1100000, - .max_uV = 1100000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_ldo11_data = { - .constraints = { - .name = "VDD_AUD_3V", - .min_uV = 3000000, - .max_uV = 3000000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo11_consumer), - .consumer_supplies = ldo11_consumer, -}; - -static struct regulator_init_data __initdata max8997_ldo14_data = { - .constraints = { - .name = "AVDD18_SWB_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo14_consumer), - .consumer_supplies = ldo14_consumer, -}; - -static struct regulator_init_data __initdata max8997_ldo17_data = { - .constraints = { - .name = "VDD_SWB_3.3V", - .min_uV = 3300000, - .max_uV = 3300000, - .apply_uV = 1, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo17_consumer), - .consumer_supplies = ldo17_consumer, -}; - -static struct regulator_init_data __initdata max8997_ldo21_data = { - .constraints = { - .name = "VDD_MIF_1.2V", - .min_uV = 1200000, - .max_uV = 1200000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_buck1_data = { - .constraints = { - .name = "VDD_ARM_1.2V", - .min_uV = 950000, - .max_uV = 1350000, - .always_on = 1, - .boot_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(buck1_consumer), - .consumer_supplies = buck1_consumer, -}; - -static struct regulator_init_data __initdata max8997_buck2_data = { - .constraints = { - .name = "VDD_INT_1.1V", - .min_uV = 900000, - .max_uV = 1100000, - .always_on = 1, - .boot_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(buck2_consumer), - .consumer_supplies = buck2_consumer, -}; - -static struct regulator_init_data __initdata max8997_buck3_data = { - .constraints = { - .name = "VDD_G3D_1.1V", - .min_uV = 900000, - .max_uV = 1100000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(buck3_consumer), - .consumer_supplies = buck3_consumer, -}; - -static struct regulator_init_data __initdata max8997_buck5_data = { - .constraints = { - .name = "VDDQ_M1M2_1.2V", - .min_uV = 1200000, - .max_uV = 1200000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_buck7_data = { - .constraints = { - .name = "VDD_LCD_3.3V", - .min_uV = 3300000, - .max_uV = 3300000, - .boot_on = 1, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1 - }, - }, - .num_consumer_supplies = ARRAY_SIZE(buck7_consumer), - .consumer_supplies = buck7_consumer, -}; - -static struct max8997_regulator_data __initdata origen_max8997_regulators[] = { - { MAX8997_LDO1, &max8997_ldo1_data }, - { MAX8997_LDO2, &max8997_ldo2_data }, - { MAX8997_LDO3, &max8997_ldo3_data }, - { MAX8997_LDO4, &max8997_ldo4_data }, - { MAX8997_LDO6, &max8997_ldo6_data }, - { MAX8997_LDO7, &max8997_ldo7_data }, - { MAX8997_LDO8, &max8997_ldo8_data }, - { MAX8997_LDO9, &max8997_ldo9_data }, - { MAX8997_LDO10, &max8997_ldo10_data }, - { MAX8997_LDO11, &max8997_ldo11_data }, - { MAX8997_LDO14, &max8997_ldo14_data }, - { MAX8997_LDO17, &max8997_ldo17_data }, - { MAX8997_LDO21, &max8997_ldo21_data }, - { MAX8997_BUCK1, &max8997_buck1_data }, - { MAX8997_BUCK2, &max8997_buck2_data }, - { MAX8997_BUCK3, &max8997_buck3_data }, - { MAX8997_BUCK5, &max8997_buck5_data }, - { MAX8997_BUCK7, &max8997_buck7_data }, -}; - -static struct max8997_platform_data __initdata origen_max8997_pdata = { - .num_regulators = ARRAY_SIZE(origen_max8997_regulators), - .regulators = origen_max8997_regulators, - - .wakeup = true, - .buck1_gpiodvs = false, - .buck2_gpiodvs = false, - .buck5_gpiodvs = false, - - .ignore_gpiodvs_side_effect = true, - .buck125_default_idx = 0x0, - - .buck125_gpios[0] = EXYNOS4_GPX0(0), - .buck125_gpios[1] = EXYNOS4_GPX0(1), - .buck125_gpios[2] = EXYNOS4_GPX0(2), - - .buck1_voltage[0] = 1350000, - .buck1_voltage[1] = 1300000, - .buck1_voltage[2] = 1250000, - .buck1_voltage[3] = 1200000, - .buck1_voltage[4] = 1150000, - .buck1_voltage[5] = 1100000, - .buck1_voltage[6] = 1000000, - .buck1_voltage[7] = 950000, - - .buck2_voltage[0] = 1100000, - .buck2_voltage[1] = 1100000, - .buck2_voltage[2] = 1100000, - .buck2_voltage[3] = 1100000, - .buck2_voltage[4] = 1000000, - .buck2_voltage[5] = 1000000, - .buck2_voltage[6] = 1000000, - .buck2_voltage[7] = 1000000, - - .buck5_voltage[0] = 1200000, - .buck5_voltage[1] = 1200000, - .buck5_voltage[2] = 1200000, - .buck5_voltage[3] = 1200000, - .buck5_voltage[4] = 1200000, - .buck5_voltage[5] = 1200000, - .buck5_voltage[6] = 1200000, - .buck5_voltage[7] = 1200000, -}; - -/* I2C0 */ -static struct i2c_board_info i2c0_devs[] __initdata = { - { - I2C_BOARD_INFO("max8997", (0xCC >> 1)), - .platform_data = &origen_max8997_pdata, - .irq = IRQ_EINT(4), - }, -}; - -static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_INTERNAL, -}; - -static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_INTERNAL, -}; - -/* USB EHCI */ -static struct s5p_ehci_platdata origen_ehci_pdata; - -static void __init origen_ehci_init(void) -{ - struct s5p_ehci_platdata *pdata = &origen_ehci_pdata; - - s5p_ehci_set_platdata(pdata); -} - -/* USB OHCI */ -static struct exynos4_ohci_platdata origen_ohci_pdata; - -static void __init origen_ohci_init(void) -{ - struct exynos4_ohci_platdata *pdata = &origen_ohci_pdata; - - exynos4_ohci_set_platdata(pdata); -} - -/* USB OTG */ -static struct s3c_hsotg_plat origen_hsotg_pdata; - -static struct gpio_led origen_gpio_leds[] = { - { - .name = "origen::status1", - .default_trigger = "heartbeat", - .gpio = EXYNOS4_GPX1(3), - .active_low = 1, - }, - { - .name = "origen::status2", - .default_trigger = "mmc0", - .gpio = EXYNOS4_GPX1(4), - .active_low = 1, - }, -}; - -static struct gpio_led_platform_data origen_gpio_led_info = { - .leds = origen_gpio_leds, - .num_leds = ARRAY_SIZE(origen_gpio_leds), -}; - -static struct platform_device origen_leds_gpio = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &origen_gpio_led_info, - }, -}; - -static struct gpio_keys_button origen_gpio_keys_table[] = { - { - .code = KEY_MENU, - .gpio = EXYNOS4_GPX1(5), - .desc = "gpio-keys: KEY_MENU", - .type = EV_KEY, - .active_low = 1, - .wakeup = 1, - .debounce_interval = 1, - }, { - .code = KEY_HOME, - .gpio = EXYNOS4_GPX1(6), - .desc = "gpio-keys: KEY_HOME", - .type = EV_KEY, - .active_low = 1, - .wakeup = 1, - .debounce_interval = 1, - }, { - .code = KEY_BACK, - .gpio = EXYNOS4_GPX1(7), - .desc = "gpio-keys: KEY_BACK", - .type = EV_KEY, - .active_low = 1, - .wakeup = 1, - .debounce_interval = 1, - }, { - .code = KEY_UP, - .gpio = EXYNOS4_GPX2(0), - .desc = "gpio-keys: KEY_UP", - .type = EV_KEY, - .active_low = 1, - .wakeup = 1, - .debounce_interval = 1, - }, { - .code = KEY_DOWN, - .gpio = EXYNOS4_GPX2(1), - .desc = "gpio-keys: KEY_DOWN", - .type = EV_KEY, - .active_low = 1, - .wakeup = 1, - .debounce_interval = 1, - }, -}; - -static struct gpio_keys_platform_data origen_gpio_keys_data = { - .buttons = origen_gpio_keys_table, - .nbuttons = ARRAY_SIZE(origen_gpio_keys_table), -}; - -static struct platform_device origen_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &origen_gpio_keys_data, - }, -}; - -static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power) -{ - int ret; - - if (power) - ret = gpio_request_one(EXYNOS4_GPE3(4), - GPIOF_OUT_INIT_HIGH, "GPE3_4"); - else - ret = gpio_request_one(EXYNOS4_GPE3(4), - GPIOF_OUT_INIT_LOW, "GPE3_4"); - - gpio_free(EXYNOS4_GPE3(4)); - - if (ret) - pr_err("failed to request gpio for LCD power: %d\n", ret); -} - -static struct plat_lcd_data origen_lcd_hv070wsa_data = { - .set_power = lcd_hv070wsa_set_power, -}; - -static struct platform_device origen_lcd_hv070wsa = { - .name = "platform-lcd", - .dev.parent = &s5p_device_fimd0.dev, - .dev.platform_data = &origen_lcd_hv070wsa_data, -}; - -static struct pwm_lookup origen_pwm_lookup[] = { - PWM_LOOKUP("s3c24xx-pwm.0", 0, "pwm-backlight.0", NULL), -}; - -#ifdef CONFIG_DRM_EXYNOS_FIMD -static struct exynos_drm_fimd_pdata drm_fimd_pdata = { - .panel = { - .timing = { - .left_margin = 64, - .right_margin = 16, - .upper_margin = 64, - .lower_margin = 16, - .hsync_len = 48, - .vsync_len = 3, - .xres = 1024, - .yres = 600, - }, - }, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | - VIDCON1_INV_VCLK, - .default_win = 0, - .bpp = 32, -}; -#else -static struct s3c_fb_pd_win origen_fb_win0 = { - .xres = 1024, - .yres = 600, - .max_bpp = 32, - .default_bpp = 24, - .virtual_x = 1024, - .virtual_y = 2 * 600, -}; - -static struct fb_videomode origen_lcd_timing = { - .left_margin = 64, - .right_margin = 16, - .upper_margin = 64, - .lower_margin = 16, - .hsync_len = 48, - .vsync_len = 3, - .xres = 1024, - .yres = 600, -}; - -static struct s3c_fb_platdata origen_lcd_pdata __initdata = { - .win[0] = &origen_fb_win0, - .vtiming = &origen_lcd_timing, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | - VIDCON1_INV_VCLK, - .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, -}; -#endif - -/* Bluetooth rfkill gpio platform data */ -static struct rfkill_gpio_platform_data origen_bt_pdata = { - .reset_gpio = EXYNOS4_GPX2(2), - .shutdown_gpio = -1, - .type = RFKILL_TYPE_BLUETOOTH, - .name = "origen-bt", -}; - -/* Bluetooth Platform device */ -static struct platform_device origen_device_bluetooth = { - .name = "rfkill_gpio", - .id = -1, - .dev = { - .platform_data = &origen_bt_pdata, - }, -}; - -static struct platform_device *origen_devices[] __initdata = { - &s3c_device_hsmmc2, - &s3c_device_hsmmc0, - &s3c_device_i2c0, - &s3c_device_rtc, - &s3c_device_usb_hsotg, - &s3c_device_wdt, - &s5p_device_ehci, - &s5p_device_fimc0, - &s5p_device_fimc1, - &s5p_device_fimc2, - &s5p_device_fimc3, - &s5p_device_fimc_md, - &s5p_device_fimd0, - &s5p_device_g2d, - &s5p_device_hdmi, - &s5p_device_i2c_hdmiphy, - &s5p_device_jpeg, - &s5p_device_mfc, - &s5p_device_mfc_l, - &s5p_device_mfc_r, - &s5p_device_mixer, - &exynos4_device_ohci, - &origen_device_gpiokeys, - &origen_lcd_hv070wsa, - &origen_leds_gpio, - &origen_device_bluetooth, -}; - -/* LCD Backlight data */ -static struct samsung_bl_gpio_info origen_bl_gpio_info = { - .no = EXYNOS4_GPD0(0), - .func = S3C_GPIO_SFN(2), -}; - -static struct platform_pwm_backlight_data origen_bl_data = { - .pwm_id = 0, - .pwm_period_ns = 1000, -}; - -static void __init origen_bt_setup(void) -{ - gpio_request(EXYNOS4_GPA0(0), "GPIO BT_UART"); - /* 4 UART Pins configuration */ - s3c_gpio_cfgrange_nopull(EXYNOS4_GPA0(0), 4, S3C_GPIO_SFN(2)); - /* Setup BT Reset, this gpio will be requesed by rfkill-gpio */ - s3c_gpio_cfgpin(EXYNOS4_GPX2(2), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE); -} - -/* I2C module and id for HDMIPHY */ -static struct i2c_board_info hdmiphy_info = { - I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38), -}; - -static void s5p_tv_setup(void) -{ - /* Direct HPD to HDMI chip */ - gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"); - s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); - s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); -} - -static void __init origen_map_io(void) -{ - exynos_init_io(NULL, 0); - s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); - xxti_f = 0; - xusbxti_f = 24000000; -} - -static void __init origen_power_init(void) -{ - gpio_request(EXYNOS4_GPX0(4), "PMIC_IRQ"); - s3c_gpio_cfgpin(EXYNOS4_GPX0(4), S3C_GPIO_SFN(0xf)); - s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE); -} - -static void __init origen_reserve(void) -{ - s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); -} - -static void __init origen_machine_init(void) -{ - origen_power_init(); - - s3c_i2c0_set_platdata(NULL); - i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); - - /* - * Since sdhci instance 2 can contain a bootable media, - * sdhci instance 0 is registered after instance 2. - */ - s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata); - s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata); - - origen_ehci_init(); - origen_ohci_init(); - s3c_hsotg_set_platdata(&origen_hsotg_pdata); - - s5p_tv_setup(); - s5p_i2c_hdmiphy_set_platdata(NULL); - s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0); - -#ifdef CONFIG_DRM_EXYNOS_FIMD - s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; - exynos4_fimd0_gpio_setup_24bpp(); -#else - s5p_fimd0_set_platdata(&origen_lcd_pdata); -#endif - - platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices)); - - pwm_add_table(origen_pwm_lookup, ARRAY_SIZE(origen_pwm_lookup)); - samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data); - - origen_bt_setup(); -} - -MACHINE_START(ORIGEN, "ORIGEN") - /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */ - .atag_offset = 0x100, - .smp = smp_ops(exynos_smp_ops), - .init_irq = exynos4_init_irq, - .map_io = origen_map_io, - .init_machine = origen_machine_init, - .init_late = exynos_init_late, - .init_time = exynos_init_time, - .reserve = &origen_reserve, - .restart = exynos4_restart, -MACHINE_END diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c deleted file mode 100644 index 2c8af961792..00000000000 --- a/arch/arm/mach-exynos/mach-smdk4x12.c +++ /dev/null @@ -1,396 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/mach-smdk4x12.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/gpio.h> -#include <linux/i2c.h> -#include <linux/input.h> -#include <linux/io.h> -#include <linux/lcd.h> -#include <linux/mfd/max8997.h> -#include <linux/mmc/host.h> -#include <linux/platform_device.h> -#include <linux/pwm.h> -#include <linux/pwm_backlight.h> -#include <linux/regulator/machine.h> -#include <linux/serial_core.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <linux/platform_data/s3c-hsotg.h> - -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <video/samsung_fimd.h> -#include <plat/backlight.h> -#include <plat/clock.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/fb.h> -#include <plat/gpio-cfg.h> -#include <plat/keypad.h> -#include <plat/mfc.h> -#include <plat/regs-serial.h> -#include <plat/sdhci.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <drm/exynos_drm.h> -#include "common.h" - -/* Following are default values for UCON, ULCON and UFCON UART registers */ -#define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ - S3C2410_UCON_RXILEVEL | \ - S3C2410_UCON_TXIRQMODE | \ - S3C2410_UCON_RXIRQMODE | \ - S3C2410_UCON_RXFIFO_TOI | \ - S3C2443_UCON_RXERR_IRQEN) - -#define SMDK4X12_ULCON_DEFAULT S3C2410_LCON_CS8 - -#define SMDK4X12_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG4 | \ - S5PV210_UFCON_RXTRIG4) - -static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = SMDK4X12_UCON_DEFAULT, - .ulcon = SMDK4X12_ULCON_DEFAULT, - .ufcon = SMDK4X12_UFCON_DEFAULT, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = SMDK4X12_UCON_DEFAULT, - .ulcon = SMDK4X12_ULCON_DEFAULT, - .ufcon = SMDK4X12_UFCON_DEFAULT, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = SMDK4X12_UCON_DEFAULT, - .ulcon = SMDK4X12_ULCON_DEFAULT, - .ufcon = SMDK4X12_UFCON_DEFAULT, - }, - [3] = { - .hwport = 3, - .flags = 0, - .ucon = SMDK4X12_UCON_DEFAULT, - .ulcon = SMDK4X12_ULCON_DEFAULT, - .ufcon = SMDK4X12_UFCON_DEFAULT, - }, -}; - -static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_INTERNAL, -#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT - .max_width = 8, - .host_caps = MMC_CAP_8_BIT_DATA, -#endif -}; - -static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_INTERNAL, -}; - -static struct regulator_consumer_supply max8997_buck1 = - REGULATOR_SUPPLY("vdd_arm", NULL); - -static struct regulator_consumer_supply max8997_buck2 = - REGULATOR_SUPPLY("vdd_int", NULL); - -static struct regulator_consumer_supply max8997_buck3 = - REGULATOR_SUPPLY("vdd_g3d", NULL); - -static struct regulator_init_data max8997_buck1_data = { - .constraints = { - .name = "VDD_ARM_SMDK4X12", - .min_uV = 925000, - .max_uV = 1350000, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max8997_buck1, -}; - -static struct regulator_init_data max8997_buck2_data = { - .constraints = { - .name = "VDD_INT_SMDK4X12", - .min_uV = 950000, - .max_uV = 1150000, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max8997_buck2, -}; - -static struct regulator_init_data max8997_buck3_data = { - .constraints = { - .name = "VDD_G3D_SMDK4X12", - .min_uV = 950000, - .max_uV = 1150000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max8997_buck3, -}; - -static struct max8997_regulator_data smdk4x12_max8997_regulators[] = { - { MAX8997_BUCK1, &max8997_buck1_data }, - { MAX8997_BUCK2, &max8997_buck2_data }, - { MAX8997_BUCK3, &max8997_buck3_data }, -}; - -static struct max8997_platform_data smdk4x12_max8997_pdata = { - .num_regulators = ARRAY_SIZE(smdk4x12_max8997_regulators), - .regulators = smdk4x12_max8997_regulators, - - .buck1_voltage[0] = 1100000, /* 1.1V */ - .buck1_voltage[1] = 1100000, /* 1.1V */ - .buck1_voltage[2] = 1100000, /* 1.1V */ - .buck1_voltage[3] = 1100000, /* 1.1V */ - .buck1_voltage[4] = 1100000, /* 1.1V */ - .buck1_voltage[5] = 1100000, /* 1.1V */ - .buck1_voltage[6] = 1000000, /* 1.0V */ - .buck1_voltage[7] = 950000, /* 0.95V */ - - .buck2_voltage[0] = 1100000, /* 1.1V */ - .buck2_voltage[1] = 1000000, /* 1.0V */ - .buck2_voltage[2] = 950000, /* 0.95V */ - .buck2_voltage[3] = 900000, /* 0.9V */ - .buck2_voltage[4] = 1100000, /* 1.1V */ - .buck2_voltage[5] = 1000000, /* 1.0V */ - .buck2_voltage[6] = 950000, /* 0.95V */ - .buck2_voltage[7] = 900000, /* 0.9V */ - - .buck5_voltage[0] = 1100000, /* 1.1V */ - .buck5_voltage[1] = 1100000, /* 1.1V */ - .buck5_voltage[2] = 1100000, /* 1.1V */ - .buck5_voltage[3] = 1100000, /* 1.1V */ - .buck5_voltage[4] = 1100000, /* 1.1V */ - .buck5_voltage[5] = 1100000, /* 1.1V */ - .buck5_voltage[6] = 1100000, /* 1.1V */ - .buck5_voltage[7] = 1100000, /* 1.1V */ -}; - -static struct i2c_board_info smdk4x12_i2c_devs0[] __initdata = { - { - I2C_BOARD_INFO("max8997", 0x66), - .platform_data = &smdk4x12_max8997_pdata, - } -}; - -static struct i2c_board_info smdk4x12_i2c_devs1[] __initdata = { - { I2C_BOARD_INFO("wm8994", 0x1a), } -}; - -static struct i2c_board_info smdk4x12_i2c_devs3[] __initdata = { - /* nothing here yet */ -}; - -static struct i2c_board_info smdk4x12_i2c_devs7[] __initdata = { - /* nothing here yet */ -}; - -static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = { - .no = EXYNOS4_GPD0(1), - .func = S3C_GPIO_SFN(2), -}; - -static struct platform_pwm_backlight_data smdk4x12_bl_data = { - .pwm_id = 1, - .pwm_period_ns = 1000, -}; - -static struct pwm_lookup smdk4x12_pwm_lookup[] = { - PWM_LOOKUP("s3c24xx-pwm.1", 0, "pwm-backlight.0", NULL), -}; - -static uint32_t smdk4x12_keymap[] __initdata = { - /* KEY(row, col, keycode) */ - KEY(1, 3, KEY_1), KEY(1, 4, KEY_2), KEY(1, 5, KEY_3), - KEY(1, 6, KEY_4), KEY(1, 7, KEY_5), - KEY(2, 5, KEY_D), KEY(2, 6, KEY_A), KEY(2, 7, KEY_B), - KEY(0, 7, KEY_E), KEY(0, 5, KEY_C) -}; - -static struct matrix_keymap_data smdk4x12_keymap_data __initdata = { - .keymap = smdk4x12_keymap, - .keymap_size = ARRAY_SIZE(smdk4x12_keymap), -}; - -static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = { - .keymap_data = &smdk4x12_keymap_data, - .rows = 3, - .cols = 8, -}; - -#ifdef CONFIG_DRM_EXYNOS_FIMD -static struct exynos_drm_fimd_pdata drm_fimd_pdata = { - .panel = { - .timing = { - .left_margin = 8, - .right_margin = 8, - .upper_margin = 6, - .lower_margin = 6, - .hsync_len = 6, - .vsync_len = 4, - .xres = 480, - .yres = 800, - }, - }, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, - .default_win = 0, - .bpp = 32, -}; -#else -static struct s3c_fb_pd_win smdk4x12_fb_win0 = { - .xres = 480, - .yres = 800, - .virtual_x = 480, - .virtual_y = 800 * 2, - .max_bpp = 32, - .default_bpp = 24, -}; - -static struct fb_videomode smdk4x12_lcd_timing = { - .left_margin = 8, - .right_margin = 8, - .upper_margin = 6, - .lower_margin = 6, - .hsync_len = 6, - .vsync_len = 4, - .xres = 480, - .yres = 800, -}; - -static struct s3c_fb_platdata smdk4x12_lcd_pdata __initdata = { - .win[0] = &smdk4x12_fb_win0, - .vtiming = &smdk4x12_lcd_timing, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, - .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, -}; -#endif - -/* USB OTG */ -static struct s3c_hsotg_plat smdk4x12_hsotg_pdata; - -static struct platform_device *smdk4x12_devices[] __initdata = { - &s3c_device_hsmmc2, - &s3c_device_hsmmc3, - &s3c_device_i2c0, - &s3c_device_i2c1, - &s3c_device_i2c3, - &s3c_device_i2c7, - &s3c_device_rtc, - &s3c_device_usb_hsotg, - &s3c_device_wdt, - &s5p_device_fimc0, - &s5p_device_fimc1, - &s5p_device_fimc2, - &s5p_device_fimc3, - &s5p_device_fimc_md, - &s5p_device_fimd0, - &s5p_device_mfc, - &s5p_device_mfc_l, - &s5p_device_mfc_r, - &samsung_device_keypad, -}; - -static void __init smdk4x12_map_io(void) -{ - exynos_init_io(NULL, 0); - s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs)); -} - -static void __init smdk4x12_reserve(void) -{ - s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); -} - -static void __init smdk4x12_machine_init(void) -{ - s3c_i2c0_set_platdata(NULL); - i2c_register_board_info(0, smdk4x12_i2c_devs0, - ARRAY_SIZE(smdk4x12_i2c_devs0)); - - s3c_i2c1_set_platdata(NULL); - i2c_register_board_info(1, smdk4x12_i2c_devs1, - ARRAY_SIZE(smdk4x12_i2c_devs1)); - - s3c_i2c3_set_platdata(NULL); - i2c_register_board_info(3, smdk4x12_i2c_devs3, - ARRAY_SIZE(smdk4x12_i2c_devs3)); - - s3c_i2c7_set_platdata(NULL); - i2c_register_board_info(7, smdk4x12_i2c_devs7, - ARRAY_SIZE(smdk4x12_i2c_devs7)); - - samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data); - pwm_add_table(smdk4x12_pwm_lookup, ARRAY_SIZE(smdk4x12_pwm_lookup)); - - samsung_keypad_set_platdata(&smdk4x12_keypad_data); - - s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata); - s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata); - - s3c_hsotg_set_platdata(&smdk4x12_hsotg_pdata); - -#ifdef CONFIG_DRM_EXYNOS_FIMD - s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; - exynos4_fimd0_gpio_setup_24bpp(); -#else - s5p_fimd0_set_platdata(&smdk4x12_lcd_pdata); -#endif - - platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices)); -} - -MACHINE_START(SMDK4212, "SMDK4212") - /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ - .atag_offset = 0x100, - .smp = smp_ops(exynos_smp_ops), - .init_irq = exynos4_init_irq, - .map_io = smdk4x12_map_io, - .init_machine = smdk4x12_machine_init, - .init_time = exynos_init_time, - .restart = exynos4_restart, - .reserve = &smdk4x12_reserve, -MACHINE_END - -MACHINE_START(SMDK4412, "SMDK4412") - /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ - /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */ - .atag_offset = 0x100, - .smp = smp_ops(exynos_smp_ops), - .init_irq = exynos4_init_irq, - .map_io = smdk4x12_map_io, - .init_machine = smdk4x12_machine_init, - .init_late = exynos_init_late, - .init_time = exynos_init_time, - .restart = exynos4_restart, - .reserve = &smdk4x12_reserve, -MACHINE_END diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c deleted file mode 100644 index d95b8cf8525..00000000000 --- a/arch/arm/mach-exynos/mach-smdkv310.c +++ /dev/null @@ -1,444 +0,0 @@ -/* linux/arch/arm/mach-exynos4/mach-smdkv310.c - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/serial_core.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/lcd.h> -#include <linux/mmc/host.h> -#include <linux/platform_device.h> -#include <linux/smsc911x.h> -#include <linux/io.h> -#include <linux/i2c.h> -#include <linux/input.h> -#include <linux/pwm.h> -#include <linux/pwm_backlight.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <linux/platform_data/s3c-hsotg.h> -#include <linux/platform_data/usb-ehci-s5p.h> -#include <linux/platform_data/usb-ohci-exynos.h> - -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <video/platform_lcd.h> -#include <video/samsung_fimd.h> -#include <plat/regs-serial.h> -#include <plat/regs-srom.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/fb.h> -#include <plat/keypad.h> -#include <plat/sdhci.h> -#include <plat/gpio-cfg.h> -#include <plat/backlight.h> -#include <plat/mfc.h> -#include <plat/clock.h> -#include <plat/hdmi.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <drm/exynos_drm.h> -#include "common.h" - -/* Following are default values for UCON, ULCON and UFCON UART registers */ -#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ - S3C2410_UCON_RXILEVEL | \ - S3C2410_UCON_TXIRQMODE | \ - S3C2410_UCON_RXIRQMODE | \ - S3C2410_UCON_RXFIFO_TOI | \ - S3C2443_UCON_RXERR_IRQEN) - -#define SMDKV310_ULCON_DEFAULT S3C2410_LCON_CS8 - -#define SMDKV310_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG4 | \ - S5PV210_UFCON_RXTRIG4) - -static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = SMDKV310_UCON_DEFAULT, - .ulcon = SMDKV310_ULCON_DEFAULT, - .ufcon = SMDKV310_UFCON_DEFAULT, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = SMDKV310_UCON_DEFAULT, - .ulcon = SMDKV310_ULCON_DEFAULT, - .ufcon = SMDKV310_UFCON_DEFAULT, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = SMDKV310_UCON_DEFAULT, - .ulcon = SMDKV310_ULCON_DEFAULT, - .ufcon = SMDKV310_UFCON_DEFAULT, - }, - [3] = { - .hwport = 3, - .flags = 0, - .ucon = SMDKV310_UCON_DEFAULT, - .ulcon = SMDKV310_ULCON_DEFAULT, - .ufcon = SMDKV310_UFCON_DEFAULT, - }, -}; - -static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_INTERNAL, -#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT - .max_width = 8, - .host_caps = MMC_CAP_8_BIT_DATA, -#endif -}; - -static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_GPIO, - .ext_cd_gpio = EXYNOS4_GPK0(2), - .ext_cd_gpio_invert = 1, -}; - -static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_INTERNAL, -#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT - .max_width = 8, - .host_caps = MMC_CAP_8_BIT_DATA, -#endif -}; - -static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_GPIO, - .ext_cd_gpio = EXYNOS4_GPK2(2), - .ext_cd_gpio_invert = 1, -}; - -static void lcd_lte480wv_set_power(struct plat_lcd_data *pd, - unsigned int power) -{ - if (power) { -#if !defined(CONFIG_BACKLIGHT_PWM) - gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0"); - gpio_free(EXYNOS4_GPD0(1)); -#endif - /* fire nRESET on power up */ - gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0"); - mdelay(100); - - gpio_set_value(EXYNOS4_GPX0(6), 0); - mdelay(10); - - gpio_set_value(EXYNOS4_GPX0(6), 1); - mdelay(10); - - gpio_free(EXYNOS4_GPX0(6)); - } else { -#if !defined(CONFIG_BACKLIGHT_PWM) - gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0"); - gpio_free(EXYNOS4_GPD0(1)); -#endif - } -} - -static struct plat_lcd_data smdkv310_lcd_lte480wv_data = { - .set_power = lcd_lte480wv_set_power, -}; - -static struct platform_device smdkv310_lcd_lte480wv = { - .name = "platform-lcd", - .dev.parent = &s5p_device_fimd0.dev, - .dev.platform_data = &smdkv310_lcd_lte480wv_data, -}; - -#ifdef CONFIG_DRM_EXYNOS_FIMD -static struct exynos_drm_fimd_pdata drm_fimd_pdata = { - .panel = { - .timing = { - .left_margin = 13, - .right_margin = 8, - .upper_margin = 7, - .lower_margin = 5, - .hsync_len = 3, - .vsync_len = 1, - .xres = 800, - .yres = 480, - }, - }, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, - .default_win = 0, - .bpp = 32, -}; -#else -static struct s3c_fb_pd_win smdkv310_fb_win0 = { - .max_bpp = 32, - .default_bpp = 24, - .xres = 800, - .yres = 480, -}; - -static struct fb_videomode smdkv310_lcd_timing = { - .left_margin = 13, - .right_margin = 8, - .upper_margin = 7, - .lower_margin = 5, - .hsync_len = 3, - .vsync_len = 1, - .xres = 800, - .yres = 480, -}; - -static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = { - .win[0] = &smdkv310_fb_win0, - .vtiming = &smdkv310_lcd_timing, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, - .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, -}; -#endif - -static struct resource smdkv310_smsc911x_resources[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(1), SZ_64K), - [1] = DEFINE_RES_NAMED(IRQ_EINT(5), 1, NULL, IORESOURCE_IRQ \ - | IRQF_TRIGGER_LOW), -}; - -static struct smsc911x_platform_config smsc9215_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, - .phy_interface = PHY_INTERFACE_MODE_MII, - .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67}, -}; - -static struct platform_device smdkv310_smsc911x = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smdkv310_smsc911x_resources), - .resource = smdkv310_smsc911x_resources, - .dev = { - .platform_data = &smsc9215_config, - }, -}; - -static uint32_t smdkv310_keymap[] __initdata = { - /* KEY(row, col, keycode) */ - KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3), - KEY(0, 6, KEY_4), KEY(0, 7, KEY_5), - KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C), - KEY(1, 6, KEY_D), KEY(1, 7, KEY_E) -}; - -static struct matrix_keymap_data smdkv310_keymap_data __initdata = { - .keymap = smdkv310_keymap, - .keymap_size = ARRAY_SIZE(smdkv310_keymap), -}; - -static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = { - .keymap_data = &smdkv310_keymap_data, - .rows = 2, - .cols = 8, -}; - -static struct i2c_board_info i2c_devs1[] __initdata = { - {I2C_BOARD_INFO("wm8994", 0x1a),}, -}; - -/* USB EHCI */ -static struct s5p_ehci_platdata smdkv310_ehci_pdata; - -static void __init smdkv310_ehci_init(void) -{ - struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata; - - s5p_ehci_set_platdata(pdata); -} - -/* USB OHCI */ -static struct exynos4_ohci_platdata smdkv310_ohci_pdata; - -static void __init smdkv310_ohci_init(void) -{ - struct exynos4_ohci_platdata *pdata = &smdkv310_ohci_pdata; - - exynos4_ohci_set_platdata(pdata); -} - -/* USB OTG */ -static struct s3c_hsotg_plat smdkv310_hsotg_pdata; - -/* Audio device */ -static struct platform_device smdkv310_device_audio = { - .name = "smdk-audio", - .id = -1, -}; - -static struct platform_device *smdkv310_devices[] __initdata = { - &s3c_device_hsmmc0, - &s3c_device_hsmmc1, - &s3c_device_hsmmc2, - &s3c_device_hsmmc3, - &s3c_device_i2c1, - &s5p_device_i2c_hdmiphy, - &s3c_device_rtc, - &s3c_device_usb_hsotg, - &s3c_device_wdt, - &s5p_device_ehci, - &s5p_device_fimc0, - &s5p_device_fimc1, - &s5p_device_fimc2, - &s5p_device_fimc3, - &s5p_device_fimc_md, - &s5p_device_g2d, - &s5p_device_jpeg, - &exynos4_device_ac97, - &exynos4_device_i2s0, - &exynos4_device_ohci, - &samsung_device_keypad, - &s5p_device_mfc, - &s5p_device_mfc_l, - &s5p_device_mfc_r, - &exynos4_device_spdif, - &samsung_asoc_idma, - &s5p_device_fimd0, - &smdkv310_device_audio, - &smdkv310_lcd_lte480wv, - &smdkv310_smsc911x, - &exynos4_device_ahci, - &s5p_device_hdmi, - &s5p_device_mixer, -}; - -static void __init smdkv310_smsc911x_init(void) -{ - u32 cs1; - - /* configure nCS1 width to 16 bits */ - cs1 = __raw_readl(S5P_SROM_BW) & - ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT); - cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) | - (1 << S5P_SROM_BW__WAITENABLE__SHIFT) | - (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << - S5P_SROM_BW__NCS1__SHIFT; - __raw_writel(cs1, S5P_SROM_BW); - - /* set timing for nCS1 suitable for ethernet chip */ - __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) | - (0x9 << S5P_SROM_BCX__TACP__SHIFT) | - (0xc << S5P_SROM_BCX__TCAH__SHIFT) | - (0x1 << S5P_SROM_BCX__TCOH__SHIFT) | - (0x6 << S5P_SROM_BCX__TACC__SHIFT) | - (0x1 << S5P_SROM_BCX__TCOS__SHIFT) | - (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1); -} - -/* LCD Backlight data */ -static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = { - .no = EXYNOS4_GPD0(1), - .func = S3C_GPIO_SFN(2), -}; - -static struct platform_pwm_backlight_data smdkv310_bl_data = { - .pwm_id = 1, - .pwm_period_ns = 1000, -}; - -/* I2C module and id for HDMIPHY */ -static struct i2c_board_info hdmiphy_info = { - I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38), -}; - -static struct pwm_lookup smdkv310_pwm_lookup[] = { - PWM_LOOKUP("s3c24xx-pwm.1", 0, "pwm-backlight.0", NULL), -}; - -static void s5p_tv_setup(void) -{ - /* direct HPD to HDMI chip */ - WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug")); - s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); - s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); -} - -static void __init smdkv310_map_io(void) -{ - exynos_init_io(NULL, 0); - s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs)); - xxti_f = 12000000; - xusbxti_f = 24000000; -} - -static void __init smdkv310_reserve(void) -{ - s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); -} - -static void __init smdkv310_machine_init(void) -{ - s3c_i2c1_set_platdata(NULL); - i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); - - smdkv310_smsc911x_init(); - - s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata); - s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata); - s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata); - s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata); - - s5p_tv_setup(); - s5p_i2c_hdmiphy_set_platdata(NULL); - s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0); - - samsung_keypad_set_platdata(&smdkv310_keypad_data); - - samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data); - pwm_add_table(smdkv310_pwm_lookup, ARRAY_SIZE(smdkv310_pwm_lookup)); - -#ifdef CONFIG_DRM_EXYNOS_FIMD - s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; - exynos4_fimd0_gpio_setup_24bpp(); -#else - s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata); -#endif - - smdkv310_ehci_init(); - smdkv310_ohci_init(); - s3c_hsotg_set_platdata(&smdkv310_hsotg_pdata); - - platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices)); -} - -MACHINE_START(SMDKV310, "SMDKV310") - /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ - /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */ - .atag_offset = 0x100, - .smp = smp_ops(exynos_smp_ops), - .init_irq = exynos4_init_irq, - .map_io = smdkv310_map_io, - .init_machine = smdkv310_machine_init, - .init_time = exynos_init_time, - .reserve = &smdkv310_reserve, - .restart = exynos4_restart, -MACHINE_END - -MACHINE_START(SMDKC210, "SMDKC210") - /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ - .atag_offset = 0x100, - .smp = smp_ops(exynos_smp_ops), - .init_irq = exynos4_init_irq, - .map_io = smdkv310_map_io, - .init_machine = smdkv310_machine_init, - .init_late = exynos_init_late, - .init_time = exynos_init_time, - .reserve = &smdkv310_reserve, - .restart = exynos4_restart, -MACHINE_END diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c deleted file mode 100644 index 327d50d4681..00000000000 --- a/arch/arm/mach-exynos/mach-universal_c210.c +++ /dev/null @@ -1,1160 +0,0 @@ -/* linux/arch/arm/mach-exynos4/mach-universal_c210.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/platform_device.h> -#include <linux/serial_core.h> -#include <linux/input.h> -#include <linux/i2c.h> -#include <linux/gpio_keys.h> -#include <linux/gpio.h> -#include <linux/interrupt.h> -#include <linux/fb.h> -#include <linux/mfd/max8998.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> -#include <linux/regulator/max8952.h> -#include <linux/mmc/host.h> -#include <linux/i2c-gpio.h> -#include <linux/i2c/mcs.h> -#include <linux/i2c/atmel_mxt_ts.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <linux/platform_data/mipi-csis.h> -#include <linux/platform_data/s3c-hsotg.h> -#include <drm/exynos_drm.h> - -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <video/samsung_fimd.h> -#include <plat/regs-serial.h> -#include <plat/clock.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/gpio-cfg.h> -#include <plat/fb.h> -#include <plat/mfc.h> -#include <plat/sdhci.h> -#include <plat/fimc-core.h> -#include <plat/samsung-time.h> -#include <plat/camport.h> - -#include <mach/map.h> - -#include <media/v4l2-mediabus.h> -#include <media/s5p_fimc.h> -#include <media/m5mols.h> -#include <media/s5k6aa.h> - -#include "common.h" - -/* Following are default values for UCON, ULCON and UFCON UART registers */ -#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ - S3C2410_UCON_RXILEVEL | \ - S3C2410_UCON_TXIRQMODE | \ - S3C2410_UCON_RXIRQMODE | \ - S3C2410_UCON_RXFIFO_TOI | \ - S3C2443_UCON_RXERR_IRQEN) - -#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8 - -#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG256 | \ - S5PV210_UFCON_RXTRIG256) - -static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .ucon = UNIVERSAL_UCON_DEFAULT, - .ulcon = UNIVERSAL_ULCON_DEFAULT, - .ufcon = UNIVERSAL_UFCON_DEFAULT, - }, - [1] = { - .hwport = 1, - .ucon = UNIVERSAL_UCON_DEFAULT, - .ulcon = UNIVERSAL_ULCON_DEFAULT, - .ufcon = UNIVERSAL_UFCON_DEFAULT, - }, - [2] = { - .hwport = 2, - .ucon = UNIVERSAL_UCON_DEFAULT, - .ulcon = UNIVERSAL_ULCON_DEFAULT, - .ufcon = UNIVERSAL_UFCON_DEFAULT, - }, - [3] = { - .hwport = 3, - .ucon = UNIVERSAL_UCON_DEFAULT, - .ulcon = UNIVERSAL_ULCON_DEFAULT, - .ufcon = UNIVERSAL_UFCON_DEFAULT, - }, -}; - -static struct regulator_consumer_supply max8952_consumer = - REGULATOR_SUPPLY("vdd_arm", NULL); - -static struct regulator_init_data universal_max8952_reg_data = { - .constraints = { - .name = "VARM_1.2V", - .min_uV = 770000, - .max_uV = 1400000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .always_on = 1, - .boot_on = 1, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max8952_consumer, -}; - -static struct max8952_platform_data universal_max8952_pdata __initdata = { - .gpio_vid0 = EXYNOS4_GPX0(3), - .gpio_vid1 = EXYNOS4_GPX0(4), - .gpio_en = -1, /* Not controllable, set "Always High" */ - .default_mode = 0, /* vid0 = 0, vid1 = 0 */ - .dvs_mode = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */ - .sync_freq = 0, /* default: fastest */ - .ramp_speed = 0, /* default: fastest */ - .reg_data = &universal_max8952_reg_data, -}; - -static struct regulator_consumer_supply lp3974_buck1_consumer = - REGULATOR_SUPPLY("vdd_int", NULL); - -static struct regulator_consumer_supply lp3974_buck2_consumer = - REGULATOR_SUPPLY("vddg3d", NULL); - -static struct regulator_consumer_supply lp3974_buck3_consumer[] = { - REGULATOR_SUPPLY("vdet", "s5p-sdo"), - REGULATOR_SUPPLY("vdd_reg", "0-003c"), -}; - -static struct regulator_init_data lp3974_buck1_data = { - .constraints = { - .name = "VINT_1.1V", - .min_uV = 750000, - .max_uV = 1500000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &lp3974_buck1_consumer, -}; - -static struct regulator_init_data lp3974_buck2_data = { - .constraints = { - .name = "VG3D_1.1V", - .min_uV = 750000, - .max_uV = 1500000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &lp3974_buck2_consumer, -}; - -static struct regulator_init_data lp3974_buck3_data = { - .constraints = { - .name = "VCC_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(lp3974_buck3_consumer), - .consumer_supplies = lp3974_buck3_consumer, -}; - -static struct regulator_init_data lp3974_buck4_data = { - .constraints = { - .name = "VMEM_1.2V", - .min_uV = 1200000, - .max_uV = 1200000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data lp3974_ldo2_data = { - .constraints = { - .name = "VALIVE_1.2V", - .min_uV = 1200000, - .max_uV = 1200000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, -}; - -static struct regulator_consumer_supply lp3974_ldo3_consumer[] = { - REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), - REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), - REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), - REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), -}; - -static struct regulator_init_data lp3974_ldo3_data = { - .constraints = { - .name = "VUSB+MIPI_1.1V", - .min_uV = 1100000, - .max_uV = 1100000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo3_consumer), - .consumer_supplies = lp3974_ldo3_consumer, -}; - -static struct regulator_consumer_supply lp3974_ldo4_consumer[] = { - REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), -}; - -static struct regulator_init_data lp3974_ldo4_data = { - .constraints = { - .name = "VADC_3.3V", - .min_uV = 3300000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo4_consumer), - .consumer_supplies = lp3974_ldo4_consumer, -}; - -static struct regulator_init_data lp3974_ldo5_data = { - .constraints = { - .name = "VTF_2.8V", - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data lp3974_ldo6_data = { - .constraints = { - .name = "LDO6", - .min_uV = 2000000, - .max_uV = 2000000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_consumer_supply lp3974_ldo7_consumer[] = { - REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), -}; - -static struct regulator_init_data lp3974_ldo7_data = { - .constraints = { - .name = "VLCD+VMIPI_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo7_consumer), - .consumer_supplies = lp3974_ldo7_consumer, -}; - -static struct regulator_consumer_supply lp3974_ldo8_consumer[] = { - REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), - REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"), -}; - -static struct regulator_init_data lp3974_ldo8_data = { - .constraints = { - .name = "VUSB+VDAC_3.3V", - .min_uV = 3300000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo8_consumer), - .consumer_supplies = lp3974_ldo8_consumer, -}; - -static struct regulator_consumer_supply lp3974_ldo9_consumer = - REGULATOR_SUPPLY("vddio", "0-003c"); - -static struct regulator_init_data lp3974_ldo9_data = { - .constraints = { - .name = "VCC_2.8V", - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &lp3974_ldo9_consumer, -}; - -static struct regulator_init_data lp3974_ldo10_data = { - .constraints = { - .name = "VPLL_1.1V", - .min_uV = 1100000, - .max_uV = 1100000, - .boot_on = 1, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_consumer_supply lp3974_ldo11_consumer = - REGULATOR_SUPPLY("dig_28", "0-001f"); - -static struct regulator_init_data lp3974_ldo11_data = { - .constraints = { - .name = "CAM_AF_3.3V", - .min_uV = 3300000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &lp3974_ldo11_consumer, -}; - -static struct regulator_init_data lp3974_ldo12_data = { - .constraints = { - .name = "PS_2.8V", - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data lp3974_ldo13_data = { - .constraints = { - .name = "VHIC_1.2V", - .min_uV = 1200000, - .max_uV = 1200000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_consumer_supply lp3974_ldo14_consumer = - REGULATOR_SUPPLY("dig_18", "0-001f"); - -static struct regulator_init_data lp3974_ldo14_data = { - .constraints = { - .name = "CAM_I_HOST_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &lp3974_ldo14_consumer, -}; - - -static struct regulator_consumer_supply lp3974_ldo15_consumer = - REGULATOR_SUPPLY("dig_12", "0-001f"); - -static struct regulator_init_data lp3974_ldo15_data = { - .constraints = { - .name = "CAM_S_DIG+FM33_CORE_1.2V", - .min_uV = 1200000, - .max_uV = 1200000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &lp3974_ldo15_consumer, -}; - -static struct regulator_consumer_supply lp3974_ldo16_consumer[] = { - REGULATOR_SUPPLY("vdda", "0-003c"), - REGULATOR_SUPPLY("a_sensor", "0-001f"), -}; - -static struct regulator_init_data lp3974_ldo16_data = { - .constraints = { - .name = "CAM_S_ANA_2.8V", - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo16_consumer), - .consumer_supplies = lp3974_ldo16_consumer, -}; - -static struct regulator_init_data lp3974_ldo17_data = { - .constraints = { - .name = "VCC_3.0V_LCD", - .min_uV = 3000000, - .max_uV = 3000000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data lp3974_32khz_ap_data = { - .constraints = { - .name = "32KHz AP", - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, -}; - -static struct regulator_init_data lp3974_32khz_cp_data = { - .constraints = { - .name = "32KHz CP", - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data lp3974_vichg_data = { - .constraints = { - .name = "VICHG", - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data lp3974_esafeout1_data = { - .constraints = { - .name = "SAFEOUT1", - .min_uV = 4800000, - .max_uV = 4800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, -}; - -static struct regulator_init_data lp3974_esafeout2_data = { - .constraints = { - .name = "SAFEOUT2", - .boot_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .enabled = 1, - }, - }, -}; - -static struct max8998_regulator_data lp3974_regulators[] = { - { MAX8998_LDO2, &lp3974_ldo2_data }, - { MAX8998_LDO3, &lp3974_ldo3_data }, - { MAX8998_LDO4, &lp3974_ldo4_data }, - { MAX8998_LDO5, &lp3974_ldo5_data }, - { MAX8998_LDO6, &lp3974_ldo6_data }, - { MAX8998_LDO7, &lp3974_ldo7_data }, - { MAX8998_LDO8, &lp3974_ldo8_data }, - { MAX8998_LDO9, &lp3974_ldo9_data }, - { MAX8998_LDO10, &lp3974_ldo10_data }, - { MAX8998_LDO11, &lp3974_ldo11_data }, - { MAX8998_LDO12, &lp3974_ldo12_data }, - { MAX8998_LDO13, &lp3974_ldo13_data }, - { MAX8998_LDO14, &lp3974_ldo14_data }, - { MAX8998_LDO15, &lp3974_ldo15_data }, - { MAX8998_LDO16, &lp3974_ldo16_data }, - { MAX8998_LDO17, &lp3974_ldo17_data }, - { MAX8998_BUCK1, &lp3974_buck1_data }, - { MAX8998_BUCK2, &lp3974_buck2_data }, - { MAX8998_BUCK3, &lp3974_buck3_data }, - { MAX8998_BUCK4, &lp3974_buck4_data }, - { MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data }, - { MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data }, - { MAX8998_ENVICHG, &lp3974_vichg_data }, - { MAX8998_ESAFEOUT1, &lp3974_esafeout1_data }, - { MAX8998_ESAFEOUT2, &lp3974_esafeout2_data }, -}; - -static struct max8998_platform_data universal_lp3974_pdata = { - .num_regulators = ARRAY_SIZE(lp3974_regulators), - .regulators = lp3974_regulators, - .buck1_voltage1 = 1100000, /* INT */ - .buck1_voltage2 = 1000000, - .buck1_voltage3 = 1100000, - .buck1_voltage4 = 1000000, - .buck1_set1 = EXYNOS4_GPX0(5), - .buck1_set2 = EXYNOS4_GPX0(6), - .buck2_voltage1 = 1200000, /* G3D */ - .buck2_voltage2 = 1100000, - .buck1_default_idx = 0, - .buck2_set3 = EXYNOS4_GPE2(0), - .buck2_default_idx = 0, - .wakeup = true, -}; - - -enum fixed_regulator_id { - FIXED_REG_ID_MMC0, - FIXED_REG_ID_HDMI_5V, - FIXED_REG_ID_CAM_S_IF, - FIXED_REG_ID_CAM_I_CORE, - FIXED_REG_ID_CAM_VT_DIO, -}; - -static struct regulator_consumer_supply hdmi_fixed_consumer = - REGULATOR_SUPPLY("hdmi-en", "exynos4-hdmi"); - -static struct regulator_init_data hdmi_fixed_voltage_init_data = { - .constraints = { - .name = "HDMI_5V", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &hdmi_fixed_consumer, -}; - -static struct fixed_voltage_config hdmi_fixed_voltage_config = { - .supply_name = "HDMI_EN1", - .microvolts = 5000000, - .gpio = EXYNOS4_GPE0(1), - .enable_high = true, - .init_data = &hdmi_fixed_voltage_init_data, -}; - -static struct platform_device hdmi_fixed_voltage = { - .name = "reg-fixed-voltage", - .id = FIXED_REG_ID_HDMI_5V, - .dev = { - .platform_data = &hdmi_fixed_voltage_config, - }, -}; - -/* GPIO I2C 5 (PMIC) */ -static struct i2c_board_info i2c5_devs[] __initdata = { - { - I2C_BOARD_INFO("max8952", 0xC0 >> 1), - .platform_data = &universal_max8952_pdata, - }, { - I2C_BOARD_INFO("lp3974", 0xCC >> 1), - .platform_data = &universal_lp3974_pdata, - }, -}; - -/* I2C3 (TSP) */ -static struct mxt_platform_data qt602240_platform_data = { - .x_line = 19, - .y_line = 11, - .x_size = 800, - .y_size = 480, - .blen = 0x11, - .threshold = 0x28, - .voltage = 2800000, /* 2.8V */ - .orient = MXT_DIAGONAL, - .irqflags = IRQF_TRIGGER_FALLING, -}; - -static struct i2c_board_info i2c3_devs[] __initdata = { - { - I2C_BOARD_INFO("qt602240_ts", 0x4a), - .platform_data = &qt602240_platform_data, - }, -}; - -static void __init universal_tsp_init(void) -{ - int gpio; - - /* TSP_LDO_ON: XMDMADDR_11 */ - gpio = EXYNOS4_GPE2(3); - gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON"); - gpio_export(gpio, 0); - - /* TSP_INT: XMDMADDR_7 */ - gpio = EXYNOS4_GPE1(7); - gpio_request(gpio, "TSP_INT"); - - s5p_register_gpio_interrupt(gpio); - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - i2c3_devs[0].irq = gpio_to_irq(gpio); -} - - -/* GPIO I2C 12 (3 Touchkey) */ -static uint32_t touchkey_keymap[] = { - /* MCS_KEY_MAP(value, keycode) */ - MCS_KEY_MAP(0, KEY_MENU), /* KEY_SEND */ - MCS_KEY_MAP(1, KEY_BACK), /* KEY_END */ -}; - -static struct mcs_platform_data touchkey_data = { - .keymap = touchkey_keymap, - .keymap_size = ARRAY_SIZE(touchkey_keymap), - .key_maxval = 2, -}; - -/* GPIO I2C 3_TOUCH 2.8V */ -#define I2C_GPIO_BUS_12 12 -static struct i2c_gpio_platform_data i2c_gpio12_data = { - .sda_pin = EXYNOS4_GPE4(0), /* XMDMDATA_8 */ - .scl_pin = EXYNOS4_GPE4(1), /* XMDMDATA_9 */ -}; - -static struct platform_device i2c_gpio12 = { - .name = "i2c-gpio", - .id = I2C_GPIO_BUS_12, - .dev = { - .platform_data = &i2c_gpio12_data, - }, -}; - -static struct i2c_board_info i2c_gpio12_devs[] __initdata = { - { - I2C_BOARD_INFO("mcs5080_touchkey", 0x20), - .platform_data = &touchkey_data, - }, -}; - -static void __init universal_touchkey_init(void) -{ - int gpio; - - gpio = EXYNOS4_GPE3(7); /* XMDMDATA_7 */ - gpio_request(gpio, "3_TOUCH_INT"); - s5p_register_gpio_interrupt(gpio); - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); - i2c_gpio12_devs[0].irq = gpio_to_irq(gpio); - - gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */ - gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "3_TOUCH_EN"); -} - -static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = { - .frequency = 300 * 1000, - .sda_delay = 200, -}; - -/* GPIO KEYS */ -static struct gpio_keys_button universal_gpio_keys_tables[] = { - { - .code = KEY_VOLUMEUP, - .gpio = EXYNOS4_GPX2(0), /* XEINT16 */ - .desc = "gpio-keys: KEY_VOLUMEUP", - .type = EV_KEY, - .active_low = 1, - .debounce_interval = 1, - }, { - .code = KEY_VOLUMEDOWN, - .gpio = EXYNOS4_GPX2(1), /* XEINT17 */ - .desc = "gpio-keys: KEY_VOLUMEDOWN", - .type = EV_KEY, - .active_low = 1, - .debounce_interval = 1, - }, { - .code = KEY_CONFIG, - .gpio = EXYNOS4_GPX2(2), /* XEINT18 */ - .desc = "gpio-keys: KEY_CONFIG", - .type = EV_KEY, - .active_low = 1, - .debounce_interval = 1, - }, { - .code = KEY_CAMERA, - .gpio = EXYNOS4_GPX2(3), /* XEINT19 */ - .desc = "gpio-keys: KEY_CAMERA", - .type = EV_KEY, - .active_low = 1, - .debounce_interval = 1, - }, { - .code = KEY_OK, - .gpio = EXYNOS4_GPX3(5), /* XEINT29 */ - .desc = "gpio-keys: KEY_OK", - .type = EV_KEY, - .active_low = 1, - .debounce_interval = 1, - }, -}; - -static struct gpio_keys_platform_data universal_gpio_keys_data = { - .buttons = universal_gpio_keys_tables, - .nbuttons = ARRAY_SIZE(universal_gpio_keys_tables), -}; - -static struct platform_device universal_gpio_keys = { - .name = "gpio-keys", - .dev = { - .platform_data = &universal_gpio_keys_data, - }, -}; - -/* eMMC */ -static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = { - .max_width = 8, - .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), - .cd_type = S3C_SDHCI_CD_PERMANENT, -}; - -static struct regulator_consumer_supply mmc0_supplies[] = { - REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"), -}; - -static struct regulator_init_data mmc0_fixed_voltage_init_data = { - .constraints = { - .name = "VMEM_VDD_2.8V", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(mmc0_supplies), - .consumer_supplies = mmc0_supplies, -}; - -static struct fixed_voltage_config mmc0_fixed_voltage_config = { - .supply_name = "MASSMEMORY_EN", - .microvolts = 2800000, - .gpio = EXYNOS4_GPE1(3), - .enable_high = true, - .init_data = &mmc0_fixed_voltage_init_data, -}; - -static struct platform_device mmc0_fixed_voltage = { - .name = "reg-fixed-voltage", - .id = FIXED_REG_ID_MMC0, - .dev = { - .platform_data = &mmc0_fixed_voltage_config, - }, -}; - -/* SD */ -static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = { - .max_width = 4, - .host_caps = MMC_CAP_4_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, - .ext_cd_gpio = EXYNOS4_GPX3(4), /* XEINT_28 */ - .ext_cd_gpio_invert = 1, - .cd_type = S3C_SDHCI_CD_GPIO, -}; - -/* WiFi */ -static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = { - .max_width = 4, - .host_caps = MMC_CAP_4_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, - .cd_type = S3C_SDHCI_CD_EXTERNAL, -}; - -static void __init universal_sdhci_init(void) -{ - s3c_sdhci0_set_platdata(&universal_hsmmc0_data); - s3c_sdhci2_set_platdata(&universal_hsmmc2_data); - s3c_sdhci3_set_platdata(&universal_hsmmc3_data); -} - -/* I2C1 */ -static struct i2c_board_info i2c1_devs[] __initdata = { - /* Gyro, To be updated */ -}; - -#ifdef CONFIG_DRM_EXYNOS -static struct exynos_drm_fimd_pdata drm_fimd_pdata = { - .panel = { - .timing = { - .left_margin = 16, - .right_margin = 16, - .upper_margin = 2, - .lower_margin = 28, - .hsync_len = 2, - .vsync_len = 1, - .xres = 480, - .yres = 800, - .refresh = 55, - }, - }, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB | - VIDCON0_CLKSEL_LCD, - .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN - | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, - .default_win = 3, - .bpp = 32, -}; -#else -/* Frame Buffer */ -static struct s3c_fb_pd_win universal_fb_win0 = { - .max_bpp = 32, - .default_bpp = 16, - .xres = 480, - .yres = 800, - .virtual_x = 480, - .virtual_y = 2 * 800, -}; - -static struct fb_videomode universal_lcd_timing = { - .left_margin = 16, - .right_margin = 16, - .upper_margin = 2, - .lower_margin = 28, - .hsync_len = 2, - .vsync_len = 1, - .xres = 480, - .yres = 800, - .refresh = 55, -}; - -static struct s3c_fb_platdata universal_lcd_pdata __initdata = { - .win[0] = &universal_fb_win0, - .vtiming = &universal_lcd_timing, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB | - VIDCON0_CLKSEL_LCD, - .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN - | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, - .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, -}; -#endif - -static struct regulator_consumer_supply cam_vt_dio_supply = - REGULATOR_SUPPLY("vdd_core", "0-003c"); - -static struct regulator_init_data cam_vt_dio_reg_init_data = { - .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS }, - .num_consumer_supplies = 1, - .consumer_supplies = &cam_vt_dio_supply, -}; - -static struct fixed_voltage_config cam_vt_dio_fixed_voltage_cfg = { - .supply_name = "CAM_VT_D_IO", - .microvolts = 2800000, - .gpio = EXYNOS4_GPE2(1), /* CAM_PWR_EN2 */ - .enable_high = 1, - .init_data = &cam_vt_dio_reg_init_data, -}; - -static struct platform_device cam_vt_dio_fixed_reg_dev = { - .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_DIO, - .dev = { .platform_data = &cam_vt_dio_fixed_voltage_cfg }, -}; - -static struct regulator_consumer_supply cam_i_core_supply = - REGULATOR_SUPPLY("core", "0-001f"); - -static struct regulator_init_data cam_i_core_reg_init_data = { - .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS }, - .num_consumer_supplies = 1, - .consumer_supplies = &cam_i_core_supply, -}; - -static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = { - .supply_name = "CAM_I_CORE_1.2V", - .microvolts = 1200000, - .gpio = EXYNOS4_GPE2(2), /* CAM_8M_CORE_EN */ - .enable_high = 1, - .init_data = &cam_i_core_reg_init_data, -}; - -static struct platform_device cam_i_core_fixed_reg_dev = { - .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_I_CORE, - .dev = { .platform_data = &cam_i_core_fixed_voltage_cfg }, -}; - -static struct regulator_consumer_supply cam_s_if_supply = - REGULATOR_SUPPLY("d_sensor", "0-001f"); - -static struct regulator_init_data cam_s_if_reg_init_data = { - .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS }, - .num_consumer_supplies = 1, - .consumer_supplies = &cam_s_if_supply, -}; - -static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = { - .supply_name = "CAM_S_IF_1.8V", - .microvolts = 1800000, - .gpio = EXYNOS4_GPE3(0), /* CAM_PWR_EN1 */ - .enable_high = 1, - .init_data = &cam_s_if_reg_init_data, -}; - -static struct platform_device cam_s_if_fixed_reg_dev = { - .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_S_IF, - .dev = { .platform_data = &cam_s_if_fixed_voltage_cfg }, -}; - -static struct s5p_platform_mipi_csis mipi_csis_platdata = { - .clk_rate = 166000000UL, - .lanes = 2, - .hs_settle = 12, -}; - -#define GPIO_CAM_LEVEL_EN(n) EXYNOS4_GPE4(n + 3) -#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPX1(5) /* XEINT_13 */ -#define GPIO_CAM_MEGA_nRST EXYNOS4_GPE2(5) -#define GPIO_CAM_VGA_NRST EXYNOS4_GPE4(7) -#define GPIO_CAM_VGA_NSTBY EXYNOS4_GPE4(6) - -static int s5k6aa_set_power(int on) -{ - gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on); - return 0; -} - -static struct s5k6aa_platform_data s5k6aa_platdata = { - .mclk_frequency = 21600000UL, - .gpio_reset = { GPIO_CAM_VGA_NRST, 0 }, - .gpio_stby = { GPIO_CAM_VGA_NSTBY, 0 }, - .bus_type = V4L2_MBUS_PARALLEL, - .horiz_flip = 1, - .set_power = s5k6aa_set_power, -}; - -static struct i2c_board_info s5k6aa_board_info = { - I2C_BOARD_INFO("S5K6AA", 0x3C), - .platform_data = &s5k6aa_platdata, -}; - -static int m5mols_set_power(struct device *dev, int on) -{ - gpio_set_value(GPIO_CAM_LEVEL_EN(1), !on); - gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on); - return 0; -} - -static struct m5mols_platform_data m5mols_platdata = { - .gpio_reset = GPIO_CAM_MEGA_nRST, - .reset_polarity = 0, - .set_power = m5mols_set_power, -}; - -static struct i2c_board_info m5mols_board_info = { - I2C_BOARD_INFO("M5MOLS", 0x1F), - .platform_data = &m5mols_platdata, -}; - -static struct fimc_source_info universal_camera_sensors[] = { - { - .mux_id = 0, - .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING | - V4L2_MBUS_VSYNC_ACTIVE_LOW, - .fimc_bus_type = FIMC_BUS_TYPE_ITU_601, - .board_info = &s5k6aa_board_info, - .i2c_bus_num = 0, - .clk_frequency = 24000000UL, - }, { - .mux_id = 0, - .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING | - V4L2_MBUS_VSYNC_ACTIVE_LOW, - .fimc_bus_type = FIMC_BUS_TYPE_MIPI_CSI2, - .board_info = &m5mols_board_info, - .i2c_bus_num = 0, - .clk_frequency = 24000000UL, - }, -}; - -static struct s5p_platform_fimc fimc_md_platdata = { - .source_info = universal_camera_sensors, - .num_clients = ARRAY_SIZE(universal_camera_sensors), -}; - -static struct gpio universal_camera_gpios[] = { - { GPIO_CAM_LEVEL_EN(1), GPIOF_OUT_INIT_HIGH, "CAM_LVL_EN1" }, - { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW, "CAM_LVL_EN2" }, - { GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" }, - { GPIO_CAM_MEGA_nRST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" }, - { GPIO_CAM_VGA_NRST, GPIOF_OUT_INIT_LOW, "CAM_VGA_NRST" }, - { GPIO_CAM_VGA_NSTBY, GPIOF_OUT_INIT_LOW, "CAM_VGA_NSTBY" }, -}; - -/* USB OTG */ -static struct s3c_hsotg_plat universal_hsotg_pdata; - -static void __init universal_camera_init(void) -{ - s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata), - &s5p_device_mipi_csis0); - s3c_set_platdata(&fimc_md_platdata, sizeof(fimc_md_platdata), - &s5p_device_fimc_md); - - if (gpio_request_array(universal_camera_gpios, - ARRAY_SIZE(universal_camera_gpios))) { - pr_err("%s: GPIO request failed\n", __func__); - return; - } - - if (!s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xf))) - m5mols_board_info.irq = gpio_to_irq(GPIO_CAM_8M_ISP_INT); - else - pr_err("Failed to configure 8M_ISP_INT GPIO\n"); - - /* Free GPIOs controlled directly by the sensor drivers. */ - gpio_free(GPIO_CAM_MEGA_nRST); - gpio_free(GPIO_CAM_8M_ISP_INT); - gpio_free(GPIO_CAM_VGA_NRST); - gpio_free(GPIO_CAM_VGA_NSTBY); - - if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) - pr_err("Camera port A setup failed\n"); -} - -static struct platform_device *universal_devices[] __initdata = { - /* Samsung Platform Devices */ - &s5p_device_mipi_csis0, - &s5p_device_fimc0, - &s5p_device_fimc1, - &s5p_device_fimc2, - &s5p_device_fimc3, - &s5p_device_g2d, - &mmc0_fixed_voltage, - &s3c_device_hsmmc0, - &s3c_device_hsmmc2, - &s3c_device_hsmmc3, - &s3c_device_i2c0, - &s3c_device_i2c3, - &s3c_device_i2c5, - &s5p_device_i2c_hdmiphy, - &hdmi_fixed_voltage, - &s5p_device_hdmi, - &s5p_device_sdo, - &s5p_device_mixer, - - /* Universal Devices */ - &i2c_gpio12, - &universal_gpio_keys, - &s5p_device_onenand, - &s5p_device_fimd0, - &s5p_device_jpeg, - &s3c_device_usb_hsotg, - &s5p_device_mfc, - &s5p_device_mfc_l, - &s5p_device_mfc_r, - &cam_vt_dio_fixed_reg_dev, - &cam_i_core_fixed_reg_dev, - &cam_s_if_fixed_reg_dev, - &s5p_device_fimc_md, -}; - -static void __init universal_map_io(void) -{ - exynos_init_io(NULL, 0); - s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4); - xxti_f = 0; - xusbxti_f = 24000000; -} - -static void s5p_tv_setup(void) -{ - /* direct HPD to HDMI chip */ - gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"); - s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); - s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); -} - -static void __init universal_reserve(void) -{ - s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); -} - -static void __init universal_machine_init(void) -{ - universal_sdhci_init(); - s5p_tv_setup(); - - s3c_i2c0_set_platdata(&universal_i2c0_platdata); - i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); - - universal_tsp_init(); - s3c_i2c3_set_platdata(NULL); - i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs)); - - s3c_i2c5_set_platdata(NULL); - s5p_i2c_hdmiphy_set_platdata(NULL); - i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs)); - -#ifdef CONFIG_DRM_EXYNOS - s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; - exynos4_fimd0_gpio_setup_24bpp(); -#else - s5p_fimd0_set_platdata(&universal_lcd_pdata); -#endif - - universal_touchkey_init(); - i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs, - ARRAY_SIZE(i2c_gpio12_devs)); - - s3c_hsotg_set_platdata(&universal_hsotg_pdata); - universal_camera_init(); - - /* Last */ - platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices)); -} - -MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") - /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */ - .atag_offset = 0x100, - .smp = smp_ops(exynos_smp_ops), - .init_irq = exynos4_init_irq, - .map_io = universal_map_io, - .init_machine = universal_machine_init, - .init_late = exynos_init_late, - .init_time = samsung_timer_init, - .reserve = &universal_reserve, - .restart = exynos4_restart, -MACHINE_END diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index a0e8ff7758a..d9c6d0ab6a0 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -200,7 +200,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) { int i; - if (!(soc_is_exynos5250() || soc_is_exynos5440())) + if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9) scu_enable(scu_base_addr()); /* diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index e3faaa81201..41c20692a13 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -30,7 +30,6 @@ #include <plat/regs-srom.h> #include <mach/regs-irq.h> -#include <mach/regs-gpio.h> #include <mach/regs-clock.h> #include <mach/regs-pmu.h> #include <mach/pm-core.h> diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index 9f1351de52f..1703593e366 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -74,17 +74,6 @@ static int exynos_pd_power_off(struct generic_pm_domain *domain) return exynos_pd_power(domain, false); } -#define EXYNOS_GPD(PD, BASE, NAME) \ -static struct exynos_pm_domain PD = { \ - .base = (void __iomem *)BASE, \ - .name = NAME, \ - .pd = { \ - .power_off = exynos_pd_power_off, \ - .power_on = exynos_pd_power_on, \ - }, \ -} - -#ifdef CONFIG_OF static void exynos_add_device_to_domain(struct exynos_pm_domain *pd, struct device *dev) { @@ -157,7 +146,7 @@ static struct notifier_block platform_nb = { .notifier_call = exynos_pm_notifier_call, }; -static __init int exynos_pm_dt_parse_domains(void) +static __init int exynos4_pm_init_power_domain(void) { struct platform_device *pdev; struct device_node *np; @@ -193,94 +182,6 @@ static __init int exynos_pm_dt_parse_domains(void) return 0; } -#else -static __init int exynos_pm_dt_parse_domains(void) -{ - return 0; -} -#endif /* CONFIG_OF */ - -static __init __maybe_unused void exynos_pm_add_dev_to_genpd(struct platform_device *pdev, - struct exynos_pm_domain *pd) -{ - if (pdev->dev.bus) { - if (!pm_genpd_add_device(&pd->pd, &pdev->dev)) - pm_genpd_dev_need_restore(&pdev->dev, true); - else - pr_info("%s: error in adding %s device to %s power" - "domain\n", __func__, dev_name(&pdev->dev), - pd->name); - } -} - -EXYNOS_GPD(exynos4_pd_mfc, S5P_PMU_MFC_CONF, "pd-mfc"); -EXYNOS_GPD(exynos4_pd_g3d, S5P_PMU_G3D_CONF, "pd-g3d"); -EXYNOS_GPD(exynos4_pd_lcd0, S5P_PMU_LCD0_CONF, "pd-lcd0"); -EXYNOS_GPD(exynos4_pd_lcd1, S5P_PMU_LCD1_CONF, "pd-lcd1"); -EXYNOS_GPD(exynos4_pd_tv, S5P_PMU_TV_CONF, "pd-tv"); -EXYNOS_GPD(exynos4_pd_cam, S5P_PMU_CAM_CONF, "pd-cam"); -EXYNOS_GPD(exynos4_pd_gps, S5P_PMU_GPS_CONF, "pd-gps"); - -static struct exynos_pm_domain *exynos4_pm_domains[] = { - &exynos4_pd_mfc, - &exynos4_pd_g3d, - &exynos4_pd_lcd0, - &exynos4_pd_lcd1, - &exynos4_pd_tv, - &exynos4_pd_cam, - &exynos4_pd_gps, -}; - -static __init int exynos4_pm_init_power_domain(void) -{ - int idx; - - if (of_have_populated_dt()) - return exynos_pm_dt_parse_domains(); - - for (idx = 0; idx < ARRAY_SIZE(exynos4_pm_domains); idx++) { - struct exynos_pm_domain *pd = exynos4_pm_domains[idx]; - int on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN; - - pm_genpd_init(&pd->pd, NULL, !on); - } - -#ifdef CONFIG_S5P_DEV_FIMD0 - exynos_pm_add_dev_to_genpd(&s5p_device_fimd0, &exynos4_pd_lcd0); -#endif -#ifdef CONFIG_S5P_DEV_TV - exynos_pm_add_dev_to_genpd(&s5p_device_hdmi, &exynos4_pd_tv); - exynos_pm_add_dev_to_genpd(&s5p_device_mixer, &exynos4_pd_tv); -#endif -#ifdef CONFIG_S5P_DEV_MFC - exynos_pm_add_dev_to_genpd(&s5p_device_mfc, &exynos4_pd_mfc); -#endif -#ifdef CONFIG_S5P_DEV_FIMC0 - exynos_pm_add_dev_to_genpd(&s5p_device_fimc0, &exynos4_pd_cam); -#endif -#ifdef CONFIG_S5P_DEV_FIMC1 - exynos_pm_add_dev_to_genpd(&s5p_device_fimc1, &exynos4_pd_cam); -#endif -#ifdef CONFIG_S5P_DEV_FIMC2 - exynos_pm_add_dev_to_genpd(&s5p_device_fimc2, &exynos4_pd_cam); -#endif -#ifdef CONFIG_S5P_DEV_FIMC3 - exynos_pm_add_dev_to_genpd(&s5p_device_fimc3, &exynos4_pd_cam); -#endif -#ifdef CONFIG_S5P_DEV_CSIS0 - exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis0, &exynos4_pd_cam); -#endif -#ifdef CONFIG_S5P_DEV_CSIS1 - exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis1, &exynos4_pd_cam); -#endif -#ifdef CONFIG_S5P_DEV_G2D - exynos_pm_add_dev_to_genpd(&s5p_device_g2d, &exynos4_pd_lcd0); -#endif -#ifdef CONFIG_S5P_DEV_JPEG - exynos_pm_add_dev_to_genpd(&s5p_device_jpeg, &exynos4_pd_cam); -#endif - return 0; -} arch_initcall(exynos4_pm_init_power_domain); int __init exynos_pm_late_initcall(void) diff --git a/arch/arm/mach-exynos/setup-fimc.c b/arch/arm/mach-exynos/setup-fimc.c deleted file mode 100644 index 6a45078d9d1..00000000000 --- a/arch/arm/mach-exynos/setup-fimc.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics Co., Ltd. - * - * Exynos4 camera interface GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/gpio.h> -#include <plat/gpio-cfg.h> -#include <plat/camport.h> - -int exynos4_fimc_setup_gpio(enum s5p_camport_id id) -{ - u32 gpio8, gpio5; - u32 sfn; - int ret; - - switch (id) { - case S5P_CAMPORT_A: - gpio8 = EXYNOS4_GPJ0(0); /* PCLK, VSYNC, HREF, DATA[0:4] */ - gpio5 = EXYNOS4_GPJ1(0); /* DATA[5:7], CLKOUT, FIELD */ - sfn = S3C_GPIO_SFN(2); - break; - - case S5P_CAMPORT_B: - gpio8 = EXYNOS4_GPE0(0); /* DATA[0:7] */ - gpio5 = EXYNOS4_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */ - sfn = S3C_GPIO_SFN(3); - break; - - default: - WARN(1, "Wrong camport id: %d\n", id); - return -EINVAL; - } - - ret = s3c_gpio_cfgall_range(gpio8, 8, sfn, S3C_GPIO_PULL_UP); - if (ret) - return ret; - - return s3c_gpio_cfgall_range(gpio5, 5, sfn, S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-exynos/setup-fimd0.c b/arch/arm/mach-exynos/setup-fimd0.c deleted file mode 100644 index 5665bb4e980..00000000000 --- a/arch/arm/mach-exynos/setup-fimd0.c +++ /dev/null @@ -1,43 +0,0 @@ -/* linux/arch/arm/mach-exynos4/setup-fimd0.c - * - * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Base Exynos4 FIMD 0 configuration - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/fb.h> -#include <linux/gpio.h> - -#include <video/samsung_fimd.h> -#include <plat/gpio-cfg.h> - -#include <mach/map.h> - -void exynos4_fimd0_gpio_setup_24bpp(void) -{ - unsigned int reg; - - s3c_gpio_cfgrange_nopull(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2)); - s3c_gpio_cfgrange_nopull(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2)); - s3c_gpio_cfgrange_nopull(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2)); - s3c_gpio_cfgrange_nopull(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2)); - - /* - * Set DISPLAY_CONTROL register for Display path selection. - * - * DISPLAY_CONTROL[1:0] - * --------------------- - * 00 | MIE - * 01 | MDINE - * 10 | FIMD : selected - * 11 | FIMD - */ - reg = __raw_readl(S3C_VA_SYS + 0x0210); - reg |= (1 << 1); - __raw_writel(reg, S3C_VA_SYS + 0x0210); -} diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c deleted file mode 100644 index e2d9dfbf102..00000000000 --- a/arch/arm/mach-exynos/setup-i2c0.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2009-2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * I2C0 GPIO configuration. - * - * Based on plat-s3c64xx/setup-i2c0.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include <linux/gpio.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> -#include <plat/cpu.h> - -void s3c_i2c0_cfg_gpio(struct platform_device *dev) -{ - if (soc_is_exynos5250() || soc_is_exynos5440()) - /* will be implemented with gpio function */ - return; - - s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-exynos/setup-i2c1.c b/arch/arm/mach-exynos/setup-i2c1.c deleted file mode 100644 index 8d2279cc85d..00000000000 --- a/arch/arm/mach-exynos/setup-i2c1.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/setup-i2c1.c - * - * Copyright (C) 2010 Samsung Electronics Co., Ltd. - * - * I2C1 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include <linux/gpio.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> - -void s3c_i2c1_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(EXYNOS4_GPD1(2), 2, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-exynos/setup-i2c2.c b/arch/arm/mach-exynos/setup-i2c2.c deleted file mode 100644 index 0ed62fc42a7..00000000000 --- a/arch/arm/mach-exynos/setup-i2c2.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/setup-i2c2.c - * - * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. - * - * I2C2 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include <linux/gpio.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> - -void s3c_i2c2_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(EXYNOS4_GPA0(6), 2, - S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-exynos/setup-i2c3.c b/arch/arm/mach-exynos/setup-i2c3.c deleted file mode 100644 index 7787fd26076..00000000000 --- a/arch/arm/mach-exynos/setup-i2c3.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/setup-i2c3.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * - * I2C3 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include <linux/gpio.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> - -void s3c_i2c3_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(EXYNOS4_GPA1(2), 2, - S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-exynos/setup-i2c4.c b/arch/arm/mach-exynos/setup-i2c4.c deleted file mode 100644 index edc847f8982..00000000000 --- a/arch/arm/mach-exynos/setup-i2c4.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/setup-i2c4.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * - * I2C4 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include <linux/gpio.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> - -void s3c_i2c4_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2, - S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-exynos/setup-i2c5.c b/arch/arm/mach-exynos/setup-i2c5.c deleted file mode 100644 index d88af7f7595..00000000000 --- a/arch/arm/mach-exynos/setup-i2c5.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/setup-i2c5.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * - * I2C5 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include <linux/gpio.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> - -void s3c_i2c5_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2, - S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-exynos/setup-i2c6.c b/arch/arm/mach-exynos/setup-i2c6.c deleted file mode 100644 index c590286c9d3..00000000000 --- a/arch/arm/mach-exynos/setup-i2c6.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/setup-i2c6.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * - * I2C6 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include <linux/gpio.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> - -void s3c_i2c6_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2, - S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-exynos/setup-i2c7.c b/arch/arm/mach-exynos/setup-i2c7.c deleted file mode 100644 index 1bba75568a5..00000000000 --- a/arch/arm/mach-exynos/setup-i2c7.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/setup-i2c7.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * - * I2C7 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include <linux/gpio.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> - -void s3c_i2c7_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2, - S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-exynos/setup-keypad.c b/arch/arm/mach-exynos/setup-keypad.c deleted file mode 100644 index 7862bfb5933..00000000000 --- a/arch/arm/mach-exynos/setup-keypad.c +++ /dev/null @@ -1,36 +0,0 @@ -/* linux/arch/arm/mach-exynos4/setup-keypad.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * GPIO configuration for Exynos4 KeyPad device - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/gpio.h> -#include <plat/gpio-cfg.h> - -void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) -{ - /* Keypads can be of various combinations, Just making sure */ - - if (rows > 8) { - /* Set all the necessary GPX2 pins: KP_ROW[0~7] */ - s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3), - S3C_GPIO_PULL_UP); - - /* Set all the necessary GPX3 pins: KP_ROW[8~] */ - s3c_gpio_cfgall_range(EXYNOS4_GPX3(0), (rows - 8), - S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); - } else { - /* Set all the necessary GPX2 pins: KP_ROW[x] */ - s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), rows, S3C_GPIO_SFN(3), - S3C_GPIO_PULL_UP); - } - - /* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */ - s3c_gpio_cfgrange_nopull(EXYNOS4_GPX1(0), cols, S3C_GPIO_SFN(3)); -} diff --git a/arch/arm/mach-exynos/setup-sdhci-gpio.c b/arch/arm/mach-exynos/setup-sdhci-gpio.c deleted file mode 100644 index d5b98c86673..00000000000 --- a/arch/arm/mach-exynos/setup-sdhci-gpio.c +++ /dev/null @@ -1,152 +0,0 @@ -/* linux/arch/arm/mach-exynos4/setup-sdhci-gpio.c - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <linux/mmc/host.h> -#include <linux/mmc/card.h> - -#include <mach/gpio.h> -#include <plat/gpio-cfg.h> -#include <plat/sdhci.h> - -void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) -{ - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - unsigned int gpio; - - /* Set all the necessary GPK0[0:1] pins to special-function 2 */ - for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - - switch (width) { - case 8: - for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) { - /* Data pin GPK1[3:6] to special-function 3 */ - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - case 4: - for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) { - /* Data pin GPK0[3:6] to special-function 2 */ - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - default: - break; - } - - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_cfgpin(EXYNOS4_GPK0(2), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(EXYNOS4_GPK0(2), S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } -} - -void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) -{ - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - unsigned int gpio; - - /* Set all the necessary GPK1[0:1] pins to special-function 2 */ - for (gpio = EXYNOS4_GPK1(0); gpio < EXYNOS4_GPK1(2); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - - for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) { - /* Data pin GPK1[3:6] to special-function 2 */ - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_cfgpin(EXYNOS4_GPK1(2), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(EXYNOS4_GPK1(2), S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } -} - -void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) -{ - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - unsigned int gpio; - - /* Set all the necessary GPK2[0:1] pins to special-function 2 */ - for (gpio = EXYNOS4_GPK2(0); gpio < EXYNOS4_GPK2(2); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - - switch (width) { - case 8: - for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) { - /* Data pin GPK3[3:6] to special-function 3 */ - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - case 4: - for (gpio = EXYNOS4_GPK2(3); gpio <= EXYNOS4_GPK2(6); gpio++) { - /* Data pin GPK2[3:6] to special-function 2 */ - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - default: - break; - } - - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_cfgpin(EXYNOS4_GPK2(2), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(EXYNOS4_GPK2(2), S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } -} - -void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width) -{ - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - unsigned int gpio; - - /* Set all the necessary GPK3[0:1] pins to special-function 2 */ - for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - - for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) { - /* Data pin GPK3[3:6] to special-function 2 */ - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_cfgpin(EXYNOS4_GPK3(2), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(EXYNOS4_GPK3(2), S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } -} diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c deleted file mode 100644 index 4999829d1c6..00000000000 --- a/arch/arm/mach-exynos/setup-spi.c +++ /dev/null @@ -1,45 +0,0 @@ -/* linux/arch/arm/mach-exynos4/setup-spi.c - * - * Copyright (C) 2011 Samsung Electronics Ltd. - * http://www.samsung.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/gpio.h> -#include <plat/gpio-cfg.h> - -#ifdef CONFIG_S3C64XX_DEV_SPI0 -int s3c64xx_spi0_cfg_gpio(void) -{ - s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP); - s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); - return 0; -} -#endif - -#ifdef CONFIG_S3C64XX_DEV_SPI1 -int s3c64xx_spi1_cfg_gpio(void) -{ - s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP); - s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); - return 0; -} -#endif - -#ifdef CONFIG_S3C64XX_DEV_SPI2 -int s3c64xx_spi2_cfg_gpio(void) -{ - s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5)); - s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP); - s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2, - S3C_GPIO_SFN(5), S3C_GPIO_PULL_UP); - return 0; -} -#endif diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c deleted file mode 100644 index 6af40662a44..00000000000 --- a/arch/arm/mach-exynos/setup-usb-phy.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics Co.Ltd - * Author: Joonyoung Shim <jy0922.shim@samsung.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/platform_device.h> -#include <mach/regs-pmu.h> -#include <mach/regs-usb-phy.h> -#include <plat/cpu.h> -#include <plat/usb-phy.h> - -static atomic_t host_usage; - -static int exynos4_usb_host_phy_is_on(void) -{ - return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1; -} - -static void exynos4210_usb_phy_clkset(struct platform_device *pdev) -{ - struct clk *xusbxti_clk; - u32 phyclk; - - xusbxti_clk = clk_get(&pdev->dev, "xusbxti"); - if (xusbxti_clk && !IS_ERR(xusbxti_clk)) { - if (soc_is_exynos4210()) { - /* set clock frequency for PLL */ - phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK; - - switch (clk_get_rate(xusbxti_clk)) { - case 12 * MHZ: - phyclk |= EXYNOS4210_CLKSEL_12M; - break; - case 48 * MHZ: - phyclk |= EXYNOS4210_CLKSEL_48M; - break; - default: - case 24 * MHZ: - phyclk |= EXYNOS4210_CLKSEL_24M; - break; - } - writel(phyclk, EXYNOS4_PHYCLK); - } else if (soc_is_exynos4212() || soc_is_exynos4412()) { - /* set clock frequency for PLL */ - phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK; - - switch (clk_get_rate(xusbxti_clk)) { - case 9600 * KHZ: - phyclk |= EXYNOS4X12_CLKSEL_9600K; - break; - case 10 * MHZ: - phyclk |= EXYNOS4X12_CLKSEL_10M; - break; - case 12 * MHZ: - phyclk |= EXYNOS4X12_CLKSEL_12M; - break; - case 19200 * KHZ: - phyclk |= EXYNOS4X12_CLKSEL_19200K; - break; - case 20 * MHZ: - phyclk |= EXYNOS4X12_CLKSEL_20M; - break; - default: - case 24 * MHZ: - /* default reference clock */ - phyclk |= EXYNOS4X12_CLKSEL_24M; - break; - } - writel(phyclk, EXYNOS4_PHYCLK); - } - clk_put(xusbxti_clk); - } -} - -static int exynos4210_usb_phy0_init(struct platform_device *pdev) -{ - u32 rstcon; - - writel(readl(S5P_USBDEVICE_PHY_CONTROL) | S5P_USBDEVICE_PHY_ENABLE, - S5P_USBDEVICE_PHY_CONTROL); - - exynos4210_usb_phy_clkset(pdev); - - /* set to normal PHY0 */ - writel((readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK), EXYNOS4_PHYPWR); - - /* reset PHY0 and Link */ - rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK; - writel(rstcon, EXYNOS4_RSTCON); - udelay(10); - - rstcon &= ~PHY0_SWRST_MASK; - writel(rstcon, EXYNOS4_RSTCON); - - return 0; -} - -static int exynos4210_usb_phy0_exit(struct platform_device *pdev) -{ - writel((readl(EXYNOS4_PHYPWR) | PHY0_ANALOG_POWERDOWN | - PHY0_OTG_DISABLE), EXYNOS4_PHYPWR); - - writel(readl(S5P_USBDEVICE_PHY_CONTROL) & ~S5P_USBDEVICE_PHY_ENABLE, - S5P_USBDEVICE_PHY_CONTROL); - - return 0; -} - -static int exynos4210_usb_phy1_init(struct platform_device *pdev) -{ - struct clk *otg_clk; - u32 rstcon; - int err; - - atomic_inc(&host_usage); - - otg_clk = clk_get(&pdev->dev, "otg"); - if (IS_ERR(otg_clk)) { - dev_err(&pdev->dev, "Failed to get otg clock\n"); - return PTR_ERR(otg_clk); - } - - err = clk_enable(otg_clk); - if (err) { - clk_put(otg_clk); - return err; - } - - if (exynos4_usb_host_phy_is_on()) - return 0; - - writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE, - S5P_USBHOST_PHY_CONTROL); - - exynos4210_usb_phy_clkset(pdev); - - /* floating prevention logic: disable */ - writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON); - - /* set to normal HSIC 0 and 1 of PHY1 */ - writel((readl(EXYNOS4_PHYPWR) & ~PHY1_HSIC_NORMAL_MASK), - EXYNOS4_PHYPWR); - - /* set to normal standard USB of PHY1 */ - writel((readl(EXYNOS4_PHYPWR) & ~PHY1_STD_NORMAL_MASK), EXYNOS4_PHYPWR); - - /* reset all ports of both PHY and Link */ - rstcon = readl(EXYNOS4_RSTCON) | HOST_LINK_PORT_SWRST_MASK | - PHY1_SWRST_MASK; - writel(rstcon, EXYNOS4_RSTCON); - udelay(10); - - rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK); - writel(rstcon, EXYNOS4_RSTCON); - udelay(80); - - clk_disable(otg_clk); - clk_put(otg_clk); - - return 0; -} - -static int exynos4210_usb_phy1_exit(struct platform_device *pdev) -{ - struct clk *otg_clk; - int err; - - if (atomic_dec_return(&host_usage) > 0) - return 0; - - otg_clk = clk_get(&pdev->dev, "otg"); - if (IS_ERR(otg_clk)) { - dev_err(&pdev->dev, "Failed to get otg clock\n"); - return PTR_ERR(otg_clk); - } - - err = clk_enable(otg_clk); - if (err) { - clk_put(otg_clk); - return err; - } - - writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN), - EXYNOS4_PHYPWR); - - writel(readl(S5P_USBHOST_PHY_CONTROL) & ~S5P_USBHOST_PHY_ENABLE, - S5P_USBHOST_PHY_CONTROL); - - clk_disable(otg_clk); - clk_put(otg_clk); - - return 0; -} - -int s5p_usb_phy_init(struct platform_device *pdev, int type) -{ - if (type == USB_PHY_TYPE_DEVICE) - return exynos4210_usb_phy0_init(pdev); - else if (type == USB_PHY_TYPE_HOST) - return exynos4210_usb_phy1_init(pdev); - - return -EINVAL; -} - -int s5p_usb_phy_exit(struct platform_device *pdev, int type) -{ - if (type == USB_PHY_TYPE_DEVICE) - return exynos4210_usb_phy0_exit(pdev); - else if (type == USB_PHY_TYPE_HOST) - return exynos4210_usb_phy1_exit(pdev); - - return -EINVAL; -} diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index ba44328464f..f25cf888f3d 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -56,9 +56,6 @@ config MXC_USE_EPIT uses the same clocks as the GPT. Anyway, on some systems the GPT may be in use for other purposes. -config MXC_ULPI - bool - config ARCH_HAS_RNGA bool @@ -233,7 +230,7 @@ config MACH_EUKREA_CPUIMX25SD select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select MXC_ULPI if USB_ULPI + select USB_ULPI_VIEWPORT if USB_ULPI select SOC_IMX25 choice @@ -284,7 +281,7 @@ config MACH_PCM038 select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_MXC_W1 select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_ULPI if USB_ULPI + select USB_ULPI_VIEWPORT if USB_ULPI select SOC_IMX27 help Include support for phyCORE-i.MX27 (aka pcm038) platform. This @@ -314,7 +311,7 @@ config MACH_CPUIMX27 select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_MXC_W1 - select MXC_ULPI if USB_ULPI + select USB_ULPI_VIEWPORT if USB_ULPI select SOC_IMX27 help Include support for Eukrea CPUIMX27 platform. This includes @@ -369,7 +366,7 @@ config MACH_MX27_3DS select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_SPI_IMX select MXC_DEBUG_BOARD - select MXC_ULPI if USB_ULPI + select USB_ULPI_VIEWPORT if USB_ULPI select SOC_IMX27 help Include support for MX27PDK platform. This includes specific @@ -414,7 +411,7 @@ config MACH_PCA100 select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_MXC_W1 select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_ULPI if USB_ULPI + select USB_ULPI_VIEWPORT if USB_ULPI select SOC_IMX27 help Include support for phyCARD-s (aka pca100) platform. This @@ -481,7 +478,7 @@ config MACH_MX31LILLY select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_ULPI if USB_ULPI + select USB_ULPI_VIEWPORT if USB_ULPI select SOC_IMX31 help Include support for mx31 based LILLY1131 modules. This includes @@ -497,7 +494,7 @@ config MACH_MX31LITE select IMX_HAVE_PLATFORM_MXC_RTC select IMX_HAVE_PLATFORM_SPI_IMX select LEDS_GPIO_REGISTER - select MXC_ULPI if USB_ULPI + select USB_ULPI_VIEWPORT if USB_ULPI select SOC_IMX31 help Include support for MX31 LITEKIT platform. This includes specific @@ -514,7 +511,7 @@ config MACH_PCM037 select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_MXC_W1 - select MXC_ULPI if USB_ULPI + select USB_ULPI_VIEWPORT if USB_ULPI select SOC_IMX31 help Include support for Phytec pcm037 platform. This includes @@ -544,7 +541,7 @@ config MACH_MX31_3DS select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SPI_IMX select MXC_DEBUG_BOARD - select MXC_ULPI if USB_ULPI + select USB_ULPI_VIEWPORT if USB_ULPI select SOC_IMX31 help Include support for MX31PDK (3DS) platform. This includes specific @@ -571,7 +568,7 @@ config MACH_MX31MOBOARD select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_SPI_IMX select LEDS_GPIO_REGISTER - select MXC_ULPI if USB_ULPI + select USB_ULPI_VIEWPORT if USB_ULPI select SOC_IMX31 help Include support for mx31moboard platform. This includes specific @@ -595,7 +592,7 @@ config MACH_ARMADILLO5X0 select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND - select MXC_ULPI if USB_ULPI + select USB_ULPI_VIEWPORT if USB_ULPI select SOC_IMX31 help Include support for Atmark Armadillo-500 platform. This includes @@ -639,7 +636,7 @@ config MACH_PCM043 select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select MXC_ULPI if USB_ULPI + select USB_ULPI_VIEWPORT if USB_ULPI select SOC_IMX35 help Include support for Phytec pcm043 platform. This includes @@ -673,7 +670,7 @@ config MACH_EUKREA_CPUIMX35SD select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select MXC_ULPI if USB_ULPI + select USB_ULPI_VIEWPORT if USB_ULPI select SOC_IMX35 help Include support for Eukrea CPUIMX35 platform. This includes @@ -816,6 +813,40 @@ config SOC_IMX6Q help This enables support for Freescale i.MX6 Quad processor. +config SOC_IMX6SL + bool "i.MX6 SoloLite support" + select ARM_ERRATA_754322 + select ARM_ERRATA_775420 + select ARM_GIC + select CPU_V7 + select HAVE_IMX_ANATOP + select HAVE_IMX_GPC + select HAVE_IMX_MMDC + select HAVE_IMX_SRC + select PINCTRL + select PINCTRL_IMX6SL + select PL310_ERRATA_588369 if CACHE_PL310 + select PL310_ERRATA_727915 if CACHE_PL310 + select PL310_ERRATA_769419 if CACHE_PL310 + + help + This enables support for Freescale i.MX6 SoloLite processor. + +config SOC_VF610 + bool "Vybrid Family VF610 support" + select CPU_V7 + select ARM_GIC + select CLKSRC_OF + select PINCTRL + select PINCTRL_VF610 + select VF_PIT_TIMER + select PL310_ERRATA_588369 if CACHE_PL310 + select PL310_ERRATA_727915 if CACHE_PL310 + select PL310_ERRATA_769419 if CACHE_PL310 + + help + This enable support for Freescale Vybrid VF610 processor. + endif source "arch/arm/mach-imx/devices/Kconfig" diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 70ae7c490ac..e20f22d58fd 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -23,7 +23,6 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o obj-$(CONFIG_MXC_TZIC) += tzic.o obj-$(CONFIG_MXC_AVIC) += avic.o -obj-$(CONFIG_MXC_ULPI) += ulpi.o obj-$(CONFIG_MXC_USE_EPIT) += epit.o obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o @@ -98,6 +97,7 @@ AFLAGS_headsmp.o :=-Wa,-march=armv7-a obj-$(CONFIG_SMP) += headsmp.o platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o +obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o ifeq ($(CONFIG_PM),y) obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o @@ -111,4 +111,6 @@ obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o obj-$(CONFIG_SOC_IMX53) += mach-imx53.o +obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o + obj-y += devices/ diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 6fc486b6a3c..04b1bad6835 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -73,6 +73,12 @@ static const char *mx53_cko2_sel[] = { "tve_sel", "lp_apm", "uart_root", "dummy"/* spdif0_clk_root */, "dummy", "dummy", }; +static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", }; +static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", }; +static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", }; +static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", }; +static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", }; + enum imx5_clks { dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred, @@ -110,7 +116,9 @@ enum imx5_clks { owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate, cko1_sel, cko1_podf, cko1, cko2_sel, cko2_podf, cko2, - srtc_gate, pata_gate, + srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel, + spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf, + spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate, clk_max }; @@ -123,11 +131,13 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, { int i; + of_clk_init(NULL); + clk[dummy] = imx_clk_fixed("dummy", 0); - clk[ckil] = imx_clk_fixed("ckil", rate_ckil); - clk[osc] = imx_clk_fixed("osc", rate_osc); - clk[ckih1] = imx_clk_fixed("ckih1", rate_ckih1); - clk[ckih2] = imx_clk_fixed("ckih2", rate_ckih2); + clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil); + clk[osc] = imx_obtain_fixed_clock("osc", rate_osc); + clk[ckih1] = imx_obtain_fixed_clock("ckih1", rate_ckih1); + clk[ckih2] = imx_obtain_fixed_clock("ckih2", rate_ckih2); clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1, lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); @@ -267,6 +277,13 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22); clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28); clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0); + clk[spdif0_sel] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel)); + clk[spdif0_pred] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3); + clk[spdif0_podf] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6); + clk[spdif0_com_s] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1, + spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT); + clk[spdif0_gate] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26); + clk[spdif_ipg_gate] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30); for (i = 0; i < ARRAY_SIZE(clk); i++) if (IS_ERR(clk[i])) @@ -378,6 +395,15 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8); clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10); clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12); + clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, + mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel)); + clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2, + spdif_sel, ARRAY_SIZE(spdif_sel)); + clk[spdif1_pred] = imx_clk_divider("spdif1_podf", "spdif1_sel", MXC_CCM_CDCDR, 16, 3); + clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6); + clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1, + mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel)); + clk[spdif1_gate] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28); for (i = 0; i < ARRAY_SIZE(clk); i++) if (IS_ERR(clk[i])) @@ -485,6 +511,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); + clk[sata_gate] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2); clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4, mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel)); @@ -495,6 +522,8 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel)); clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); + clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, + mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel)); for (i = 0; i < ARRAY_SIZE(clk); i++) if (IS_ERR(clk[i])) @@ -542,42 +571,12 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, return 0; } -#ifdef CONFIG_OF -static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc, - unsigned long *ckih1, unsigned long *ckih2) -{ - struct device_node *np; - - /* retrieve the freqency of fixed clocks from device tree */ - for_each_compatible_node(np, NULL, "fixed-clock") { - u32 rate; - if (of_property_read_u32(np, "clock-frequency", &rate)) - continue; - - if (of_device_is_compatible(np, "fsl,imx-ckil")) - *ckil = rate; - else if (of_device_is_compatible(np, "fsl,imx-osc")) - *osc = rate; - else if (of_device_is_compatible(np, "fsl,imx-ckih1")) - *ckih1 = rate; - else if (of_device_is_compatible(np, "fsl,imx-ckih2")) - *ckih2 = rate; - } -} - int __init mx51_clocks_init_dt(void) { - unsigned long ckil, osc, ckih1, ckih2; - - clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2); - return mx51_clocks_init(ckil, osc, ckih1, ckih2); + return mx51_clocks_init(0, 0, 0, 0); } int __init mx53_clocks_init_dt(void) { - unsigned long ckil, osc, ckih1, ckih2; - - clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2); - return mx53_clocks_init(ckil, osc, ckih1, ckih2); + return mx53_clocks_init(0, 0, 0, 0); } -#endif diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 15125900308..4282e99f5ca 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -177,17 +177,18 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; -static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", }; +static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; +static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; -static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", }; +static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; static const char *gpu_axi_sels[] = { "axi", "ahb", }; static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; -static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", }; +static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", }; static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; -static const char *ldb_di_sels[] = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; +static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; @@ -237,7 +238,7 @@ enum mx6q_clks { pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, - usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max + usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, clk_max }; static struct clk *clk[clk_max]; @@ -269,27 +270,16 @@ static struct clk_div_table video_div_table[] = { { } }; -int __init mx6q_clocks_init(void) +static void __init imx6q_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *base; int i, irq; clk[dummy] = imx_clk_fixed("dummy", 0); - - /* retrieve the freqency of fixed clocks from device tree */ - for_each_compatible_node(np, NULL, "fixed-clock") { - u32 rate; - if (of_property_read_u32(np, "clock-frequency", &rate)) - continue; - - if (of_device_is_compatible(np, "fsl,imx-ckil")) - clk[ckil] = imx_clk_fixed("ckil", rate); - else if (of_device_is_compatible(np, "fsl,imx-ckih1")) - clk[ckih] = imx_clk_fixed("ckih", rate); - else if (of_device_is_compatible(np, "fsl,imx-osc")) - clk[osc] = imx_clk_fixed("osc", rate); - } + clk[ckil] = imx_obtain_fixed_clock("ckil", 0); + clk[ckih] = imx_obtain_fixed_clock("ckih1", 0); + clk[osc] = imx_obtain_fixed_clock("osc", 0); np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); base = of_iomap(np, 0); @@ -311,7 +301,6 @@ int __init mx6q_clocks_init(void) clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3); - clk[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0); /* * Bit 20 is the reserved and read-only bit, we do this only for: @@ -359,7 +348,7 @@ int __init mx6q_clocks_init(void) clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); - np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm"); + np = ccm_node; base = of_iomap(np, 0); WARN_ON(!base); ccm_base = base; @@ -369,8 +358,8 @@ int __init mx6q_clocks_init(void) clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); - clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); - clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); + clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); + clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); @@ -480,7 +469,14 @@ int __init mx6q_clocks_init(void) clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16); clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); - clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); + if (cpu_is_imx6dl()) + /* + * The multiplexer and divider of imx6q clock gpu3d_shader get + * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl. + */ + clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24); + else + clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4); @@ -498,7 +494,14 @@ int __init mx6q_clocks_init(void) clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16); - clk[mlb] = imx_clk_gate2("mlb", "pll8_mlb", base + 0x74, 18); + if (cpu_is_imx6dl()) + /* + * The multiplexer and divider of the imx6q clock gpu2d get + * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl. + */ + clk[mlb] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18); + else + clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); @@ -527,6 +530,7 @@ int __init mx6q_clocks_init(void) clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); + clk[eim_slow] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10); clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); @@ -546,6 +550,8 @@ int __init mx6q_clocks_init(void) clk_register_clkdev(clk[ahb], "ahb", NULL); clk_register_clkdev(clk[cko1], "cko1", NULL); clk_register_clkdev(clk[arm], NULL, "cpu0"); + clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL); + clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL); if (imx6q_revision() != IMX_CHIP_REVISION_1_0) { clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); @@ -575,6 +581,5 @@ int __init mx6q_clocks_init(void) WARN_ON(!base); irq = irq_of_parse_and_map(np, 0); mxc_timer_init(base, irq); - - return 0; } +CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init); diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c new file mode 100644 index 00000000000..a307ac22dff --- /dev/null +++ b/arch/arm/mach-imx/clk-imx6sl.c @@ -0,0 +1,267 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/err.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <dt-bindings/clock/imx6sl-clock.h> + +#include "clk.h" +#include "common.h" + +static const char const *step_sels[] = { "osc", "pll2_pfd2", }; +static const char const *pll1_sw_sels[] = { "pll1_sys", "step", }; +static const char const *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", }; +static const char const *ocram_sels[] = { "periph", "ocram_alt_sels", }; +static const char const *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", }; +static const char const *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; +static const char const *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; +static const char const *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", }; +static const char const *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", }; +static const char const *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", }; +static const char const *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", }; +static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_post_div", "dummy", }; +static const char const *perclk_sels[] = { "ipg", "osc", }; +static const char const *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", }; +static const char const *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", }; +static const char const *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", }; +static const char const *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", }; +static const char const *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", }; +static const char const *audio_sels[] = { "pll4_post_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", }; +static const char const *ecspi_sels[] = { "pll3_60m", "osc", }; +static const char const *uart_sels[] = { "pll3_80m", "osc", }; + +static struct clk_div_table clk_enet_ref_table[] = { + { .val = 0, .div = 20, }, + { .val = 1, .div = 10, }, + { .val = 2, .div = 5, }, + { .val = 3, .div = 4, }, + { } +}; + +static struct clk_div_table post_div_table[] = { + { .val = 2, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 0, .div = 4, }, + { } +}; + +static struct clk_div_table video_div_table[] = { + { .val = 0, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 2, .div = 1, }, + { .val = 3, .div = 4, }, + { } +}; + +static struct clk *clks[IMX6SL_CLK_CLK_END]; +static struct clk_onecell_data clk_data; + +static void __init imx6sl_clocks_init(struct device_node *ccm_node) +{ + struct device_node *np; + void __iomem *base; + int irq; + int i; + + clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); + clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); + clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop"); + base = of_iomap(np, 0); + WARN_ON(!base); + + /* type name parent base div_mask */ + clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); + clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); + clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); + clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); + clks[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); + clks[IMX6SL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); + clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3); + + /* + * usbphy1 and usbphy2 are implemented as dummy gates using reserve + * bit 20. They are used by phy driver to keep the refcount of + * parent PLL correct. usbphy1_gate and usbphy2_gate only needs to be + * turned on during boot, and software will not need to control it + * anymore after that. + */ + clks[IMX6SL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); + clks[IMX6SL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); + clks[IMX6SL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); + clks[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); + + /* dev name parent_name flags reg shift width div: flags, div_table lock */ + clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); + clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); + clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); + clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); + + /* name parent_name reg idx */ + clks[IMX6SL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0", "pll2_bus", base + 0x100, 0); + clks[IMX6SL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus", base + 0x100, 1); + clks[IMX6SL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus", base + 0x100, 2); + clks[IMX6SL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0", "pll3_usb_otg", base + 0xf0, 0); + clks[IMX6SL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", base + 0xf0, 1); + clks[IMX6SL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", base + 0xf0, 2); + clks[IMX6SL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", base + 0xf0, 3); + + /* name parent_name mult div */ + clks[IMX6SL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2", 1, 2); + clks[IMX6SL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); + clks[IMX6SL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); + clks[IMX6SL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); + + np = ccm_node; + base = of_iomap(np, 0); + WARN_ON(!base); + + /* name reg shift width parent_names num_parents */ + clks[IMX6SL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); + clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); + clks[IMX6SL_CLK_OCRAM_ALT_SEL] = imx_clk_mux("ocram_alt_sel", base + 0x14, 7, 1, ocram_alt_sels, ARRAY_SIZE(ocram_alt_sels)); + clks[IMX6SL_CLK_OCRAM_SEL] = imx_clk_mux("ocram_sel", base + 0x14, 6, 1, ocram_sels, ARRAY_SIZE(ocram_sels)); + clks[IMX6SL_CLK_PRE_PERIPH2_SEL] = imx_clk_mux("pre_periph2_sel", base + 0x18, 21, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); + clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); + clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); + clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); + clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); + clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); + clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); + clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); + clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); + clks[IMX6SL_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); + clks[IMX6SL_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); + clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); + clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); + clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); + clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); + clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); + clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels)); + clks[IMX6SL_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels)); + clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels)); + clks[IMX6SL_CLK_EPDC_PIX_SEL] = imx_clk_mux("epdc_pix_sel", base + 0x38, 15, 3, epdc_pix_sels, ARRAY_SIZE(epdc_pix_sels)); + clks[IMX6SL_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); + clks[IMX6SL_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); + clks[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); + clks[IMX6SL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); + clks[IMX6SL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); + + /* name reg shift width busy: reg, shift parent_names num_parents */ + clks[IMX6SL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); + clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); + + /* name parent_name reg shift width */ + clks[IMX6SL_CLK_OCRAM_PODF] = imx_clk_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3); + clks[IMX6SL_CLK_PERIPH_CLK2_PODF] = imx_clk_divider("periph_clk2_podf", "periph_clk2_sel", base + 0x14, 27, 3); + clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel", base + 0x14, 0, 3); + clks[IMX6SL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); + clks[IMX6SL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3); + clks[IMX6SL_CLK_LCDIF_AXI_PODF] = imx_clk_divider("lcdif_axi_podf", "lcdif_axi_sel", base + 0x3c, 16, 3); + clks[IMX6SL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); + clks[IMX6SL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); + clks[IMX6SL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); + clks[IMX6SL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); + clks[IMX6SL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); + clks[IMX6SL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); + clks[IMX6SL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); + clks[IMX6SL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); + clks[IMX6SL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); + clks[IMX6SL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); + clks[IMX6SL_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6); + clks[IMX6SL_CLK_PXP_AXI_PODF] = imx_clk_divider("pxp_axi_podf", "pxp_axi_sel", base + 0x34, 3, 3); + clks[IMX6SL_CLK_EPDC_AXI_PODF] = imx_clk_divider("epdc_axi_podf", "epdc_axi_sel", base + 0x34, 12, 3); + clks[IMX6SL_CLK_GPU2D_OVG_PODF] = imx_clk_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3); + clks[IMX6SL_CLK_GPU2D_PODF] = imx_clk_divider("gpu2d_podf", "gpu2d_sel", base + 0x18, 29, 3); + clks[IMX6SL_CLK_LCDIF_PIX_PRED] = imx_clk_divider("lcdif_pix_pred", "lcdif_pix_sel", base + 0x38, 3, 3); + clks[IMX6SL_CLK_EPDC_PIX_PRED] = imx_clk_divider("epdc_pix_pred", "epdc_pix_sel", base + 0x38, 12, 3); + clks[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3); + clks[IMX6SL_CLK_EPDC_PIX_PODF] = imx_clk_divider("epdc_pix_podf", "epdc_pix_pred", base + 0x18, 23, 3); + clks[IMX6SL_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", base + 0x30, 25, 3); + clks[IMX6SL_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", base + 0x30, 22, 3); + clks[IMX6SL_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", base + 0x30, 12, 3); + clks[IMX6SL_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", base + 0x30, 9, 3); + clks[IMX6SL_CLK_EXTERN_AUDIO_PRED] = imx_clk_divider("extern_audio_pred", "extern_audio_sel", base + 0x28, 9, 3); + clks[IMX6SL_CLK_EXTERN_AUDIO_PODF] = imx_clk_divider("extern_audio_podf", "extern_audio_pred", base + 0x28, 25, 3); + clks[IMX6SL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6); + clks[IMX6SL_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_sel", base + 0x24, 0, 6); + + /* name parent_name reg shift width busy: reg, shift */ + clks[IMX6SL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); + clks[IMX6SL_CLK_MMDC_ROOT] = imx_clk_busy_divider("mmdc", "periph2", base + 0x14, 3, 3, base + 0x48, 2); + clks[IMX6SL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); + + /* name parent_name reg shift */ + clks[IMX6SL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); + clks[IMX6SL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); + clks[IMX6SL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); + clks[IMX6SL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); + clks[IMX6SL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12); + clks[IMX6SL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14); + clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16); + clks[IMX6SL_CLK_GPT] = imx_clk_gate2("gpt", "perclk", base + 0x6c, 20); + clks[IMX6SL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x6c, 22); + clks[IMX6SL_CLK_GPU2D_OVG] = imx_clk_gate2("gpu2d_ovg", "gpu2d_ovg_podf", base + 0x6c, 26); + clks[IMX6SL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6); + clks[IMX6SL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8); + clks[IMX6SL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10); + clks[IMX6SL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12); + clks[IMX6SL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x74, 0); + clks[IMX6SL_CLK_PXP_AXI] = imx_clk_gate2("pxp_axi", "pxp_axi_podf", base + 0x74, 2); + clks[IMX6SL_CLK_EPDC_AXI] = imx_clk_gate2("epdc_axi", "epdc_axi_podf", base + 0x74, 4); + clks[IMX6SL_CLK_LCDIF_AXI] = imx_clk_gate2("lcdif_axi", "lcdif_axi_podf", base + 0x74, 6); + clks[IMX6SL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_pix_podf", base + 0x74, 8); + clks[IMX6SL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_pix_podf", base + 0x74, 10); + clks[IMX6SL_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28); + clks[IMX6SL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16); + clks[IMX6SL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18); + clks[IMX6SL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20); + clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22); + clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6); + clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14); + clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18); + clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20); + clks[IMX6SL_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22); + clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24); + clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26); + clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); + clks[IMX6SL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); + clks[IMX6SL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); + clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); + clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); + + for (i = 0; i < ARRAY_SIZE(clks); i++) + if (IS_ERR(clks[i])) + pr_err("i.MX6SL clk %d: register failed with %ld\n", + i, PTR_ERR(clks[i])); + + clk_data.clks = clks; + clk_data.clk_num = ARRAY_SIZE(clks); + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + + clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0"); + clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0"); + + if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { + clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]); + clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); + } + + np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt"); + base = of_iomap(np, 0); + WARN_ON(!base); + irq = irq_of_parse_and_map(np, 0); + mxc_timer_init(base, irq); +} +CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init); diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c index d09bc3df9a7..a9fad5f8d34 100644 --- a/arch/arm/mach-imx/clk-pllv3.c +++ b/arch/arm/mach-imx/clk-pllv3.c @@ -296,13 +296,6 @@ static const struct clk_ops clk_pllv3_enet_ops = { .recalc_rate = clk_pllv3_enet_recalc_rate, }; -static const struct clk_ops clk_pllv3_mlb_ops = { - .prepare = clk_pllv3_prepare, - .unprepare = clk_pllv3_unprepare, - .enable = clk_pllv3_enable, - .disable = clk_pllv3_disable, -}; - struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask) @@ -330,9 +323,6 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, case IMX_PLLV3_ENET: ops = &clk_pllv3_enet_ops; break; - case IMX_PLLV3_MLB: - ops = &clk_pllv3_mlb_ops; - break; default: ops = &clk_pllv3_ops; } diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c new file mode 100644 index 00000000000..d617c0b7c80 --- /dev/null +++ b/arch/arm/mach-imx/clk-vf610.c @@ -0,0 +1,319 @@ +/* + * Copyright 2012-2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#include <linux/of_address.h> +#include <linux/clk.h> +#include <dt-bindings/clock/vf610-clock.h> + +#include "clk.h" + +#define CCM_CCR (ccm_base + 0x00) +#define CCM_CSR (ccm_base + 0x04) +#define CCM_CCSR (ccm_base + 0x08) +#define CCM_CACRR (ccm_base + 0x0c) +#define CCM_CSCMR1 (ccm_base + 0x10) +#define CCM_CSCDR1 (ccm_base + 0x14) +#define CCM_CSCDR2 (ccm_base + 0x18) +#define CCM_CSCDR3 (ccm_base + 0x1c) +#define CCM_CSCMR2 (ccm_base + 0x20) +#define CCM_CSCDR4 (ccm_base + 0x24) +#define CCM_CLPCR (ccm_base + 0x2c) +#define CCM_CISR (ccm_base + 0x30) +#define CCM_CIMR (ccm_base + 0x34) +#define CCM_CGPR (ccm_base + 0x3c) +#define CCM_CCGR0 (ccm_base + 0x40) +#define CCM_CCGR1 (ccm_base + 0x44) +#define CCM_CCGR2 (ccm_base + 0x48) +#define CCM_CCGR3 (ccm_base + 0x4c) +#define CCM_CCGR4 (ccm_base + 0x50) +#define CCM_CCGR5 (ccm_base + 0x54) +#define CCM_CCGR6 (ccm_base + 0x58) +#define CCM_CCGR7 (ccm_base + 0x5c) +#define CCM_CCGR8 (ccm_base + 0x60) +#define CCM_CCGR9 (ccm_base + 0x64) +#define CCM_CCGR10 (ccm_base + 0x68) +#define CCM_CCGR11 (ccm_base + 0x6c) +#define CCM_CMEOR0 (ccm_base + 0x70) +#define CCM_CMEOR1 (ccm_base + 0x74) +#define CCM_CMEOR2 (ccm_base + 0x78) +#define CCM_CMEOR3 (ccm_base + 0x7c) +#define CCM_CMEOR4 (ccm_base + 0x80) +#define CCM_CMEOR5 (ccm_base + 0x84) +#define CCM_CPPDSR (ccm_base + 0x88) +#define CCM_CCOWR (ccm_base + 0x8c) +#define CCM_CCPGR0 (ccm_base + 0x90) +#define CCM_CCPGR1 (ccm_base + 0x94) +#define CCM_CCPGR2 (ccm_base + 0x98) +#define CCM_CCPGR3 (ccm_base + 0x9c) + +#define CCM_CCGRx_CGn(n) ((n) * 2) + +#define PFD_PLL1_BASE (anatop_base + 0x2b0) +#define PFD_PLL2_BASE (anatop_base + 0x100) +#define PFD_PLL3_BASE (anatop_base + 0xf0) + +static void __iomem *anatop_base; +static void __iomem *ccm_base; + +/* sources for multiplexer clocks, this is used multiple times */ +static const char const *fast_sels[] = { "firc", "fxosc", }; +static const char const *slow_sels[] = { "sirc_32k", "sxosc", }; +static const char const *pll1_sels[] = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", }; +static const char const *pll2_sels[] = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", }; +static const char const *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", }; +static const char const *ddr_sels[] = { "pll2_pfd2", "sys_sel", }; +static const char const *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", }; +static const char const *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", }; +static const char const *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; +static const char const *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; +static const char const *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", }; +static const char const *qspi_sels[] = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", }; +static const char const *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", }; +static const char const *dcu_sels[] = { "pll1_pfd2", "pll3_main", }; +static const char const *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", }; +static const char const *vadc_sels[] = { "pll6_main_div", "pll3_main_div", "pll3_main", }; +/* FTM counter clock source, not module clock */ +static const char const *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", }; +static const char const *ftm_fix_sels[] = { "sxosc", "ipg_bus", }; + +static struct clk_div_table pll4_main_div_table[] = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 6 }, + { .val = 3, .div = 8 }, + { .val = 4, .div = 10 }, + { .val = 5, .div = 12 }, + { .val = 6, .div = 14 }, + { .val = 7, .div = 16 }, + { } +}; + +static struct clk *clk[VF610_CLK_END]; +static struct clk_onecell_data clk_data; + +static void __init vf610_clocks_init(struct device_node *ccm_node) +{ + struct device_node *np; + + clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0); + clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000); + clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000); + clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000); + + clk[VF610_CLK_SXOSC] = imx_obtain_fixed_clock("sxosc", 0); + clk[VF610_CLK_FXOSC] = imx_obtain_fixed_clock("fxosc", 0); + clk[VF610_CLK_AUDIO_EXT] = imx_obtain_fixed_clock("audio_ext", 0); + clk[VF610_CLK_ENET_EXT] = imx_obtain_fixed_clock("enet_ext", 0); + + clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2); + + np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop"); + anatop_base = of_iomap(np, 0); + BUG_ON(!anatop_base); + + np = ccm_node; + ccm_base = of_iomap(np, 0); + BUG_ON(!ccm_base); + + clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels)); + clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels)); + + clk[VF610_CLK_PLL1_MAIN] = imx_clk_fixed_factor("pll1_main", "fast_clk_sel", 22, 1); + clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_PLL1_BASE, 0); + clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_PLL1_BASE, 1); + clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_PLL1_BASE, 2); + clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_PLL1_BASE, 3); + + clk[VF610_CLK_PLL2_MAIN] = imx_clk_fixed_factor("pll2_main", "fast_clk_sel", 22, 1); + clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_PLL2_BASE, 0); + clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_PLL2_BASE, 1); + clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_PLL2_BASE, 2); + clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_PLL2_BASE, 3); + + clk[VF610_CLK_PLL3_MAIN] = imx_clk_fixed_factor("pll3_main", "fast_clk_sel", 20, 1); + clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_main", PFD_PLL3_BASE, 0); + clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_main", PFD_PLL3_BASE, 1); + clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_main", PFD_PLL3_BASE, 2); + clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_main", PFD_PLL3_BASE, 3); + + clk[VF610_CLK_PLL4_MAIN] = imx_clk_fixed_factor("pll4_main", "fast_clk_sel", 25, 1); + /* Enet pll: fixed 50Mhz */ + clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6); + /* pll6: default 960Mhz */ + clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1); + clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5); + clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5); + clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels)); + clk[VF610_CLK_DDR_SEL] = imx_clk_mux("ddr_sel", CCM_CCSR, 6, 1, ddr_sels, ARRAY_SIZE(ddr_sels)); + clk[VF610_CLK_SYS_BUS] = imx_clk_divider("sys_bus", "sys_sel", CCM_CACRR, 0, 3); + clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3); + clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2); + + clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1); + clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock); + clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1); + + clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4)); + clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4)); + + clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4); + clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4); + clk[VF610_CLK_QSPI0_X4_DIV] = imx_clk_divider("qspi0_x4", "qspi0_en", CCM_CSCDR3, 0, 2); + clk[VF610_CLK_QSPI0_X2_DIV] = imx_clk_divider("qspi0_x2", "qspi0_x4", CCM_CSCDR3, 2, 1); + clk[VF610_CLK_QSPI0_X1_DIV] = imx_clk_divider("qspi0_x1", "qspi0_x2", CCM_CSCDR3, 3, 1); + clk[VF610_CLK_QSPI0] = imx_clk_gate2("qspi0", "qspi0_x1", CCM_CCGR2, CCM_CCGRx_CGn(4)); + + clk[VF610_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", CCM_CSCMR1, 24, 2, qspi_sels, 4); + clk[VF610_CLK_QSPI1_EN] = imx_clk_gate("qspi1_en", "qspi1_sel", CCM_CSCDR3, 12); + clk[VF610_CLK_QSPI1_X4_DIV] = imx_clk_divider("qspi1_x4", "qspi1_en", CCM_CSCDR3, 8, 2); + clk[VF610_CLK_QSPI1_X2_DIV] = imx_clk_divider("qspi1_x2", "qspi1_x4", CCM_CSCDR3, 10, 1); + clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1); + clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4)); + + clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10); + clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20); + clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4); + clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7); + clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24); + clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23); + + clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7)); + + clk[VF610_CLK_UART0] = imx_clk_gate2("uart0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7)); + clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8)); + clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9)); + clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10)); + + clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6)); + clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7)); + + clk[VF610_CLK_DSPI0] = imx_clk_gate2("dspi0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(12)); + clk[VF610_CLK_DSPI1] = imx_clk_gate2("dspi1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(13)); + clk[VF610_CLK_DSPI2] = imx_clk_gate2("dspi2", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12)); + clk[VF610_CLK_DSPI3] = imx_clk_gate2("dspi3", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13)); + + clk[VF610_CLK_WDT] = imx_clk_gate2("wdt", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14)); + + clk[VF610_CLK_ESDHC0_SEL] = imx_clk_mux("esdhc0_sel", CCM_CSCMR1, 16, 2, esdhc_sels, 4); + clk[VF610_CLK_ESDHC0_EN] = imx_clk_gate("esdhc0_en", "esdhc0_sel", CCM_CSCDR2, 28); + clk[VF610_CLK_ESDHC0_DIV] = imx_clk_divider("esdhc0_div", "esdhc0_en", CCM_CSCDR2, 16, 4); + clk[VF610_CLK_ESDHC0] = imx_clk_gate2("eshc0", "esdhc0_div", CCM_CCGR7, CCM_CCGRx_CGn(1)); + + clk[VF610_CLK_ESDHC1_SEL] = imx_clk_mux("esdhc1_sel", CCM_CSCMR1, 18, 2, esdhc_sels, 4); + clk[VF610_CLK_ESDHC1_EN] = imx_clk_gate("esdhc1_en", "esdhc1_sel", CCM_CSCDR2, 29); + clk[VF610_CLK_ESDHC1_DIV] = imx_clk_divider("esdhc1_div", "esdhc1_en", CCM_CSCDR2, 20, 4); + clk[VF610_CLK_ESDHC1] = imx_clk_gate2("eshc1", "esdhc1_div", CCM_CCGR7, CCM_CCGRx_CGn(2)); + + /* + * ftm_ext_clk and ftm_fix_clk are FTM timer counter's + * selectable clock sources, both use a common enable bit + * in CCM_CSCDR1, selecting "dummy" clock as parent of + * "ftm0_ext_fix" make it serve only for enable/disable. + */ + clk[VF610_CLK_FTM0_EXT_SEL] = imx_clk_mux("ftm0_ext_sel", CCM_CSCMR2, 6, 2, ftm_ext_sels, 4); + clk[VF610_CLK_FTM0_FIX_SEL] = imx_clk_mux("ftm0_fix_sel", CCM_CSCMR2, 14, 1, ftm_fix_sels, 2); + clk[VF610_CLK_FTM0_EXT_FIX_EN] = imx_clk_gate("ftm0_ext_fix_en", "dummy", CCM_CSCDR1, 25); + clk[VF610_CLK_FTM1_EXT_SEL] = imx_clk_mux("ftm1_ext_sel", CCM_CSCMR2, 8, 2, ftm_ext_sels, 4); + clk[VF610_CLK_FTM1_FIX_SEL] = imx_clk_mux("ftm1_fix_sel", CCM_CSCMR2, 15, 1, ftm_fix_sels, 2); + clk[VF610_CLK_FTM1_EXT_FIX_EN] = imx_clk_gate("ftm1_ext_fix_en", "dummy", CCM_CSCDR1, 26); + clk[VF610_CLK_FTM2_EXT_SEL] = imx_clk_mux("ftm2_ext_sel", CCM_CSCMR2, 10, 2, ftm_ext_sels, 4); + clk[VF610_CLK_FTM2_FIX_SEL] = imx_clk_mux("ftm2_fix_sel", CCM_CSCMR2, 16, 1, ftm_fix_sels, 2); + clk[VF610_CLK_FTM2_EXT_FIX_EN] = imx_clk_gate("ftm2_ext_fix_en", "dummy", CCM_CSCDR1, 27); + clk[VF610_CLK_FTM3_EXT_SEL] = imx_clk_mux("ftm3_ext_sel", CCM_CSCMR2, 12, 2, ftm_ext_sels, 4); + clk[VF610_CLK_FTM3_FIX_SEL] = imx_clk_mux("ftm3_fix_sel", CCM_CSCMR2, 17, 1, ftm_fix_sels, 2); + clk[VF610_CLK_FTM3_EXT_FIX_EN] = imx_clk_gate("ftm3_ext_fix_en", "dummy", CCM_CSCDR1, 28); + + /* ftm(n)_clk are FTM module operation clock */ + clk[VF610_CLK_FTM0] = imx_clk_gate2("ftm0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(8)); + clk[VF610_CLK_FTM1] = imx_clk_gate2("ftm1", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(9)); + clk[VF610_CLK_FTM2] = imx_clk_gate2("ftm2", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(8)); + clk[VF610_CLK_FTM3] = imx_clk_gate2("ftm3", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(9)); + + clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2); + clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19); + clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3); + clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8)); + clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2); + clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23); + clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3); + clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8)); + + clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4); + clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30); + clk[VF610_CLK_ESAI_DIV] = imx_clk_divider("esai_div", "esai_en", CCM_CSCDR2, 24, 4); + clk[VF610_CLK_ESAI] = imx_clk_gate2("esai", "esai_div", CCM_CCGR4, CCM_CCGRx_CGn(2)); + + clk[VF610_CLK_SAI0_SEL] = imx_clk_mux("sai0_sel", CCM_CSCMR1, 0, 2, sai_sels, 4); + clk[VF610_CLK_SAI0_EN] = imx_clk_gate("sai0_en", "sai0_sel", CCM_CSCDR1, 16); + clk[VF610_CLK_SAI0_DIV] = imx_clk_divider("sai0_div", "sai0_en", CCM_CSCDR1, 0, 4); + clk[VF610_CLK_SAI0] = imx_clk_gate2("sai0", "sai0_div", CCM_CCGR0, CCM_CCGRx_CGn(15)); + + clk[VF610_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", CCM_CSCMR1, 2, 2, sai_sels, 4); + clk[VF610_CLK_SAI1_EN] = imx_clk_gate("sai1_en", "sai1_sel", CCM_CSCDR1, 17); + clk[VF610_CLK_SAI1_DIV] = imx_clk_divider("sai1_div", "sai1_en", CCM_CSCDR1, 4, 4); + clk[VF610_CLK_SAI1] = imx_clk_gate2("sai1", "sai1_div", CCM_CCGR1, CCM_CCGRx_CGn(0)); + + clk[VF610_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", CCM_CSCMR1, 4, 2, sai_sels, 4); + clk[VF610_CLK_SAI2_EN] = imx_clk_gate("sai2_en", "sai2_sel", CCM_CSCDR1, 18); + clk[VF610_CLK_SAI2_DIV] = imx_clk_divider("sai2_div", "sai2_en", CCM_CSCDR1, 8, 4); + clk[VF610_CLK_SAI2] = imx_clk_gate2("sai2", "sai2_div", CCM_CCGR1, CCM_CCGRx_CGn(1)); + + clk[VF610_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", CCM_CSCMR1, 6, 2, sai_sels, 4); + clk[VF610_CLK_SAI3_EN] = imx_clk_gate("sai3_en", "sai3_sel", CCM_CSCDR1, 19); + clk[VF610_CLK_SAI3_DIV] = imx_clk_divider("sai3_div", "sai3_en", CCM_CSCDR1, 12, 4); + clk[VF610_CLK_SAI3] = imx_clk_gate2("sai3", "sai3_div", CCM_CCGR1, CCM_CCGRx_CGn(2)); + + clk[VF610_CLK_NFC_SEL] = imx_clk_mux("nfc_sel", CCM_CSCMR1, 12, 2, nfc_sels, 4); + clk[VF610_CLK_NFC_EN] = imx_clk_gate("nfc_en", "nfc_sel", CCM_CSCDR2, 9); + clk[VF610_CLK_NFC_PRE_DIV] = imx_clk_divider("nfc_pre_div", "nfc_en", CCM_CSCDR3, 13, 3); + clk[VF610_CLK_NFC_FRAC_DIV] = imx_clk_divider("nfc_frac_div", "nfc_pre_div", CCM_CSCDR2, 4, 4); + clk[VF610_CLK_NFC] = imx_clk_gate2("nfc", "nfc_frac_div", CCM_CCGR10, CCM_CCGRx_CGn(0)); + + clk[VF610_CLK_GPU_SEL] = imx_clk_mux("gpu_sel", CCM_CSCMR1, 14, 1, gpu_sels, 2); + clk[VF610_CLK_GPU_EN] = imx_clk_gate("gpu_en", "gpu_sel", CCM_CSCDR2, 10); + clk[VF610_CLK_GPU2D] = imx_clk_gate2("gpu", "gpu_en", CCM_CCGR8, CCM_CCGRx_CGn(15)); + + clk[VF610_CLK_VADC_SEL] = imx_clk_mux("vadc_sel", CCM_CSCMR1, 8, 2, vadc_sels, 3); + clk[VF610_CLK_VADC_EN] = imx_clk_gate("vadc_en", "vadc_sel", CCM_CSCDR1, 22); + clk[VF610_CLK_VADC_DIV] = imx_clk_divider("vadc_div", "vadc_en", CCM_CSCDR1, 20, 2); + clk[VF610_CLK_VADC_DIV_HALF] = imx_clk_fixed_factor("vadc_div_half", "vadc_div", 1, 2); + clk[VF610_CLK_VADC] = imx_clk_gate2("vadc", "vadc_div", CCM_CCGR8, CCM_CCGRx_CGn(7)); + + clk[VF610_CLK_ADC0] = imx_clk_gate2("adc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(11)); + clk[VF610_CLK_ADC1] = imx_clk_gate2("adc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(11)); + clk[VF610_CLK_DAC0] = imx_clk_gate2("dac0", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(12)); + clk[VF610_CLK_DAC1] = imx_clk_gate2("dac1", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(13)); + + clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1)); + + clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0)); + clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4)); + + clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); + clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); + clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); + clk_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2); + + clk_set_parent(clk[VF610_CLK_QSPI1_SEL], clk[VF610_CLK_PLL1_PFD4]); + clk_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2); + clk_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2); + clk_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2); + + clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]); + clk_set_parent(clk[VF610_CLK_SAI1_SEL], clk[VF610_CLK_AUDIO_EXT]); + clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]); + clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]); + + /* Add the clocks to provider list */ + clk_data.clks = clk; + clk_data.clk_num = ARRAY_SIZE(clk); + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); +} +CLK_OF_DECLARE(vf610, "fsl,vf610-ccm", vf610_clocks_init); diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c index 37e884ed1cd..55bc80a0066 100644 --- a/arch/arm/mach-imx/clk.c +++ b/arch/arm/mach-imx/clk.c @@ -1,4 +1,39 @@ +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/of.h> +#include <linux/slab.h> #include <linux/spinlock.h> #include "clk.h" DEFINE_SPINLOCK(imx_ccm_lock); + +static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) +{ + struct of_phandle_args phandle; + struct clk *clk = ERR_PTR(-ENODEV); + char *path; + + path = kasprintf(GFP_KERNEL, "/clocks/%s", name); + if (!path) + return ERR_PTR(-ENOMEM); + + phandle.np = of_find_node_by_path(path); + kfree(path); + + if (phandle.np) { + clk = of_clk_get_from_provider(&phandle); + of_node_put(phandle.np); + } + return clk; +} + +struct clk * __init imx_obtain_fixed_clock( + const char *name, unsigned long rate) +{ + struct clk *clk; + + clk = imx_obtain_fixed_clock_from_dt(name); + if (IS_ERR(clk)) + clk = imx_clk_fixed(name, rate); + return clk; +} diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h index d9d9d9c66df..0e4e8bb261b 100644 --- a/arch/arm/mach-imx/clk.h +++ b/arch/arm/mach-imx/clk.h @@ -18,7 +18,6 @@ enum imx_pllv3_type { IMX_PLLV3_USB, IMX_PLLV3_AV, IMX_PLLV3_ENET, - IMX_PLLV3_MLB, }; struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, @@ -29,6 +28,9 @@ struct clk *clk_register_gate2(struct device *dev, const char *name, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock); +struct clk * imx_obtain_fixed_clock( + const char *name, unsigned long rate); + static inline struct clk *imx_clk_gate2(const char *name, const char *parent, void __iomem *reg, u8 shift) { diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index c08ae3f99ce..ee78847abf4 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -68,12 +68,12 @@ extern int mx27_clocks_init_dt(void); extern int mx31_clocks_init_dt(void); extern int mx51_clocks_init_dt(void); extern int mx53_clocks_init_dt(void); -extern int mx6q_clocks_init(void); extern struct platform_device *mxc_register_gpio(char *name, int id, resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); extern void mxc_set_cpu_type(unsigned int type); extern void mxc_restart(char, const char *); extern void mxc_arch_reset_init(void __iomem *); +extern void mxc_arch_reset_init_dt(void); extern int mx53_revision(void); extern int imx6q_revision(void); extern int mx53_display_revision(void); diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h index 356131f7b59..a3b0b04b45c 100644 --- a/arch/arm/mach-imx/hardware.h +++ b/arch/arm/mach-imx/hardware.h @@ -20,6 +20,7 @@ #ifndef __ASM_ARCH_MXC_HARDWARE_H__ #define __ASM_ARCH_MXC_HARDWARE_H__ +#include <asm/io.h> #include <asm/sizes.h> #define addr_in_module(addr, mod) \ diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S index 67b9c48dcaf..627f16f0e9d 100644 --- a/arch/arm/mach-imx/headsmp.S +++ b/arch/arm/mach-imx/headsmp.S @@ -18,8 +18,20 @@ .section ".text.head", "ax" #ifdef CONFIG_SMP +diag_reg_offset: + .word g_diag_reg - . + + .macro set_diag_reg + adr r0, diag_reg_offset + ldr r1, [r0] + add r1, r1, r0 @ r1 = physical &g_diag_reg + ldr r0, [r1] + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register + .endm + ENTRY(v7_secondary_startup) bl v7_invalidate_l1 + set_diag_reg b secondary_startup ENDPROC(v7_secondary_startup) #endif diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c index 82348391582..3e1ec5ffe63 100644 --- a/arch/arm/mach-imx/imx25-dt.c +++ b/arch/arm/mach-imx/imx25-dt.c @@ -19,6 +19,8 @@ static void __init imx25_dt_init(void) { + mxc_arch_reset_init_dt(); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c index 4aaead0a77f..4e235ecb402 100644 --- a/arch/arm/mach-imx/imx27-dt.c +++ b/arch/arm/mach-imx/imx27-dt.c @@ -22,6 +22,8 @@ static void __init imx27_dt_init(void) { struct platform_device_info devinfo = { .name = "cpufreq-cpu0", }; + mxc_arch_reset_init_dt(); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); platform_device_register_full(&devinfo); diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c index 67de611e29a..818a1cc2fe4 100644 --- a/arch/arm/mach-imx/imx31-dt.c +++ b/arch/arm/mach-imx/imx31-dt.c @@ -20,6 +20,8 @@ static void __init imx31_dt_init(void) { + mxc_arch_reset_init_dt(); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c index ab24cc32211..53e43e579dd 100644 --- a/arch/arm/mach-imx/imx51-dt.c +++ b/arch/arm/mach-imx/imx51-dt.c @@ -23,6 +23,8 @@ static void __init imx51_dt_init(void) { struct platform_device_info devinfo = { .name = "cpufreq-cpu0", }; + mxc_arch_reset_init_dt(); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); platform_device_register_full(&devinfo); } diff --git a/arch/arm/mach-imx/irq-common.c b/arch/arm/mach-imx/irq-common.c index 4b34f52dc46..0a920d18486 100644 --- a/arch/arm/mach-imx/irq-common.c +++ b/arch/arm/mach-imx/irq-common.c @@ -18,6 +18,7 @@ #include <linux/module.h> #include <linux/irq.h> +#include <linux/platform_data/asoc-imx-ssi.h> #include "irq-common.h" diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c index f579c616fee..74e7b94c22e 100644 --- a/arch/arm/mach-imx/mach-imx53.c +++ b/arch/arm/mach-imx/mach-imx53.c @@ -21,6 +21,7 @@ #include <asm/mach/time.h> #include "common.h" +#include "hardware.h" #include "mx53.h" static void __init imx53_qsb_init(void) @@ -38,6 +39,8 @@ static void __init imx53_qsb_init(void) static void __init imx53_dt_init(void) { + mxc_arch_reset_init_dt(); + if (of_machine_is_compatible("fsl,imx53-qsb")) imx53_qsb_init(); diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 5536fd81379..f5965220a4d 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -11,6 +11,7 @@ */ #include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/clocksource.h> #include <linux/cpu.h> @@ -145,6 +146,45 @@ static void __init imx6q_sabrelite_init(void) imx6q_sabrelite_cko1_setup(); } +static void __init imx6q_sabresd_cko1_setup(void) +{ + struct clk *cko1_sel, *pll4, *pll4_post, *cko1; + unsigned long rate; + + cko1_sel = clk_get_sys(NULL, "cko1_sel"); + pll4 = clk_get_sys(NULL, "pll4_audio"); + pll4_post = clk_get_sys(NULL, "pll4_post_div"); + cko1 = clk_get_sys(NULL, "cko1"); + if (IS_ERR(cko1_sel) || IS_ERR(pll4) + || IS_ERR(pll4_post) || IS_ERR(cko1)) { + pr_err("cko1 setup failed!\n"); + goto put_clk; + } + /* + * Setting pll4 at 768MHz (24MHz * 32) + * So its child clock can get 24MHz easily + */ + clk_set_rate(pll4, 768000000); + + clk_set_parent(cko1_sel, pll4_post); + rate = clk_round_rate(cko1, 24000000); + clk_set_rate(cko1, rate); +put_clk: + if (!IS_ERR(cko1_sel)) + clk_put(cko1_sel); + if (!IS_ERR(pll4_post)) + clk_put(pll4_post); + if (!IS_ERR(pll4)) + clk_put(pll4); + if (!IS_ERR(cko1)) + clk_put(cko1); +} + +static void __init imx6q_sabresd_init(void) +{ + imx6q_sabresd_cko1_setup(); +} + static void __init imx6q_1588_init(void) { struct regmap *gpr; @@ -165,6 +205,9 @@ static void __init imx6q_init_machine(void) { if (of_machine_is_compatible("fsl,imx6q-sabrelite")) imx6q_sabrelite_init(); + else if (of_machine_is_compatible("fsl,imx6q-sabresd") || + of_machine_is_compatible("fsl,imx6dl-sabresd")) + imx6q_sabresd_init(); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); @@ -253,10 +296,44 @@ static void __init imx6q_map_io(void) imx_scu_map_io(); } +#ifdef CONFIG_CACHE_L2X0 +static void __init imx6q_init_l2cache(void) +{ + void __iomem *l2x0_base; + struct device_node *np; + unsigned int val; + + np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); + if (!np) + goto out; + + l2x0_base = of_iomap(np, 0); + if (!l2x0_base) { + of_node_put(np); + goto out; + } + + /* Configure the L2 PREFETCH and POWER registers */ + val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); + val |= 0x70800000; + writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL); + val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN; + writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL); + + iounmap(l2x0_base); + of_node_put(np); + +out: + l2x0_of_init(0, ~0UL); +} +#else +static inline void imx6q_init_l2cache(void) {} +#endif + static void __init imx6q_init_irq(void) { imx6q_init_revision(); - l2x0_of_init(0, ~0UL); + imx6q_init_l2cache(); imx_src_init(); imx_gpc_init(); irqchip_init(); @@ -264,7 +341,7 @@ static void __init imx6q_init_irq(void) static void __init imx6q_timer_init(void) { - mx6q_clocks_init(); + of_clk_init(NULL); clocksource_of_init(); imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", imx6q_revision()); diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c new file mode 100644 index 00000000000..132db260950 --- /dev/null +++ b/arch/arm/mach-imx/mach-imx6sl.c @@ -0,0 +1,52 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/clk-provider.h> +#include <linux/irqchip.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <asm/hardware/cache-l2x0.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include "common.h" + +static void __init imx6sl_init_machine(void) +{ + mxc_arch_reset_init_dt(); + + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static void __init imx6sl_init_irq(void) +{ + l2x0_of_init(0, ~0UL); + imx_src_init(); + imx_gpc_init(); + irqchip_init(); +} + +static void __init imx6sl_timer_init(void) +{ + of_clk_init(NULL); +} + +static const char *imx6sl_dt_compat[] __initdata = { + "fsl,imx6sl", + NULL, +}; + +DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)") + .map_io = debug_ll_io_init, + .init_irq = imx6sl_init_irq, + .init_time = imx6sl_timer_init, + .init_machine = imx6sl_init_machine, + .dt_compat = imx6sl_dt_compat, + .restart = mxc_restart, +MACHINE_END diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index b8b15bb1ffd..19bb6441a7d 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -398,8 +398,8 @@ static void __init pca100_init(void) imx27_add_fsl_usb2_udc(&otg_device_pdata); } - usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); + usbh2_pdata.otg = imx_otg_ulpi_create( + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); if (usbh2_pdata.otg) imx27_add_mxc_ehci_hs(2, &usbh2_pdata); diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c new file mode 100644 index 00000000000..816991deb9b --- /dev/null +++ b/arch/arm/mach-imx/mach-vf610.c @@ -0,0 +1,48 @@ +/* + * Copyright 2012-2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/of_platform.h> +#include <linux/clocksource.h> +#include <linux/irqchip.h> +#include <linux/clk-provider.h> +#include <asm/mach/arch.h> +#include <asm/hardware/cache-l2x0.h> + +#include "common.h" + +static void __init vf610_init_machine(void) +{ + mxc_arch_reset_init_dt(); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static void __init vf610_init_irq(void) +{ + l2x0_of_init(0, ~0UL); + irqchip_init(); +} + +static void __init vf610_init_time(void) +{ + of_clk_init(NULL); + clocksource_of_init(); +} + +static const char *vf610_dt_compat[] __initdata = { + "fsl,vf610", + NULL, +}; + +DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)") + .init_irq = vf610_init_irq, + .init_time = vf610_init_time, + .init_machine = vf610_init_machine, + .dt_compat = vf610_dt_compat, + .restart = mxc_restart, +MACHINE_END diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c index 3c609c52d3e..e065fedb3ad 100644 --- a/arch/arm/mach-imx/mm-imx1.c +++ b/arch/arm/mach-imx/mm-imx1.c @@ -39,7 +39,6 @@ void __init mx1_map_io(void) void __init imx1_init_early(void) { mxc_set_cpu_type(MXC_CPU_MX1); - mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR)); imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR), MX1_NUM_GPIO_PORT); } @@ -51,6 +50,7 @@ void __init mx1_init_irq(void) void __init imx1_soc_init(void) { + mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR)); mxc_device_init(); mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256, diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c index d8ccd3a8ec5..2e91ab2ca37 100644 --- a/arch/arm/mach-imx/mm-imx21.c +++ b/arch/arm/mach-imx/mm-imx21.c @@ -66,7 +66,6 @@ void __init mx21_map_io(void) void __init imx21_init_early(void) { mxc_set_cpu_type(MXC_CPU_MX21); - mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR)); imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR), MX21_NUM_GPIO_PORT); } @@ -82,6 +81,7 @@ static const struct resource imx21_audmux_res[] __initconst = { void __init imx21_soc_init(void) { + mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR)); mxc_device_init(); mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c index 9357707bb7a..e065c117f5a 100644 --- a/arch/arm/mach-imx/mm-imx25.c +++ b/arch/arm/mach-imx/mm-imx25.c @@ -54,7 +54,6 @@ void __init imx25_init_early(void) { mxc_set_cpu_type(MXC_CPU_MX25); mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR)); - mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR)); } void __init mx25_init_irq(void) @@ -89,6 +88,7 @@ static const struct resource imx25_audmux_res[] __initconst = { void __init imx25_soc_init(void) { + mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR)); mxc_device_init(); /* i.mx25 has the i.mx35 type gpio */ diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c index 4f1be65a7b5..7d82a5a5b16 100644 --- a/arch/arm/mach-imx/mm-imx27.c +++ b/arch/arm/mach-imx/mm-imx27.c @@ -66,7 +66,6 @@ void __init mx27_map_io(void) void __init imx27_init_early(void) { mxc_set_cpu_type(MXC_CPU_MX27); - mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR)); imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR), MX27_NUM_GPIO_PORT); } @@ -82,6 +81,7 @@ static const struct resource imx27_audmux_res[] __initconst = { void __init imx27_soc_init(void) { + mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR)); mxc_device_init(); /* i.mx27 has the i.mx21 type gpio */ diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c index e0e69a68217..8f0f60697f5 100644 --- a/arch/arm/mach-imx/mm-imx3.c +++ b/arch/arm/mach-imx/mm-imx3.c @@ -138,7 +138,6 @@ void __init mx31_map_io(void) void __init imx31_init_early(void) { mxc_set_cpu_type(MXC_CPU_MX31); - mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); arch_ioremap_caller = imx3_ioremap_caller; arm_pm_idle = imx3_idle; mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR); @@ -174,6 +173,7 @@ void __init imx31_soc_init(void) imx3_init_l2x0(); + mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); mxc_device_init(); mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); @@ -216,7 +216,6 @@ void __init imx35_init_early(void) { mxc_set_cpu_type(MXC_CPU_MX35); mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); - mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); arm_pm_idle = imx3_idle; arch_ioremap_caller = imx3_ioremap_caller; mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR); @@ -272,6 +271,7 @@ void __init imx35_soc_init(void) imx3_init_l2x0(); + mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); mxc_device_init(); mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index b7c4e70e508..cf193d87274 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c @@ -83,7 +83,6 @@ void __init imx51_init_early(void) imx51_ipu_mipi_setup(); mxc_set_cpu_type(MXC_CPU_MX51); mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); - mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); imx_src_init(); } @@ -91,7 +90,6 @@ void __init imx53_init_early(void) { mxc_set_cpu_type(MXC_CPU_MX53); mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); - mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR)); imx_src_init(); } @@ -129,6 +127,7 @@ static const struct resource imx51_audmux_res[] __initconst = { void __init imx51_soc_init(void) { + mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); mxc_device_init(); /* i.mx51 has the i.mx35 type gpio */ diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c index 4a69305db65..c6e1ab54488 100644 --- a/arch/arm/mach-imx/platsmp.c +++ b/arch/arm/mach-imx/platsmp.c @@ -12,6 +12,7 @@ #include <linux/init.h> #include <linux/smp.h> +#include <asm/cacheflush.h> #include <asm/page.h> #include <asm/smp_scu.h> #include <asm/mach/map.h> @@ -21,6 +22,7 @@ #define SCU_STANDBY_ENABLE (1 << 5) +u32 g_diag_reg; static void __iomem *scu_base; static struct map_desc scu_io_desc __initdata = { @@ -80,6 +82,18 @@ void imx_smp_prepare(void) static void __init imx_smp_prepare_cpus(unsigned int max_cpus) { imx_smp_prepare(); + + /* + * The diagnostic register holds the errata bits. Mostly bootloader + * does not bring up secondary cores, so that when errata bits are set + * in bootloader, they are set only for boot cpu. But on a SMP + * configuration, it should be equally done on every single core. + * Read the register from boot cpu here, and will replicate it into + * secondary cores when booting them. + */ + asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (g_diag_reg) : : "cc"); + __cpuc_flush_dcache_area(&g_diag_reg, sizeof(g_diag_reg)); + outer_clean_range(__pa(&g_diag_reg), __pa(&g_diag_reg + 1)); } struct smp_operations imx_smp_ops __initdata = { diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 695e0d73bf8..7cdc79a9657 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -21,6 +21,8 @@ #include <linux/io.h> #include <linux/err.h> #include <linux/delay.h> +#include <linux/of.h> +#include <linux/of_address.h> #include <asm/system_misc.h> #include <asm/proc-fns.h> @@ -30,6 +32,7 @@ #include "hardware.h" static void __iomem *wdog_base; +static struct clk *wdog_clk; /* * Reset the system. It is called by machine_restart(). @@ -38,16 +41,13 @@ void mxc_restart(char mode, const char *cmd) { unsigned int wcr_enable; - if (cpu_is_mx1()) { - wcr_enable = (1 << 0); - } else { - struct clk *clk; + if (wdog_clk) + clk_enable(wdog_clk); - clk = clk_get_sys("imx2-wdt.0", NULL); - if (!IS_ERR(clk)) - clk_prepare_enable(clk); + if (cpu_is_mx1()) + wcr_enable = (1 << 0); + else wcr_enable = (1 << 2); - } /* Assert SRS signal */ __raw_writew(wcr_enable, wdog_base); @@ -55,7 +55,7 @@ void mxc_restart(char mode, const char *cmd) /* wait for reset to assert... */ mdelay(500); - printk(KERN_ERR "Watchdog reset failed to assert reset\n"); + pr_err("%s: Watchdog reset failed to assert reset\n", __func__); /* delay to allow the serial port to show the message */ mdelay(50); @@ -64,7 +64,34 @@ void mxc_restart(char mode, const char *cmd) soft_restart(0); } -void mxc_arch_reset_init(void __iomem *base) +void __init mxc_arch_reset_init(void __iomem *base) { wdog_base = base; + + wdog_clk = clk_get_sys("imx2-wdt.0", NULL); + if (IS_ERR(wdog_clk)) { + pr_warn("%s: failed to get wdog clock\n", __func__); + wdog_clk = NULL; + return; + } + + clk_prepare(wdog_clk); +} + +void __init mxc_arch_reset_init_dt(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt"); + wdog_base = of_iomap(np, 0); + WARN_ON(!wdog_base); + + wdog_clk = of_clk_get(np, 0); + if (IS_ERR(wdog_clk)) { + pr_warn("%s: failed to get wdog clock\n", __func__); + wdog_clk = NULL; + return; + } + + clk_prepare(wdog_clk); } diff --git a/arch/arm/mach-imx/ulpi.c b/arch/arm/mach-imx/ulpi.c deleted file mode 100644 index 0f051957d10..00000000000 --- a/arch/arm/mach-imx/ulpi.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> - * Copyright 2009 Daniel Mack <daniel@caiaq.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/delay.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> - -#include "ulpi.h" - -/* ULPIVIEW register bits */ -#define ULPIVW_WU (1 << 31) /* Wakeup */ -#define ULPIVW_RUN (1 << 30) /* read/write run */ -#define ULPIVW_WRITE (1 << 29) /* 0 = read 1 = write */ -#define ULPIVW_SS (1 << 27) /* SyncState */ -#define ULPIVW_PORT_MASK 0x07 /* Port field */ -#define ULPIVW_PORT_SHIFT 24 -#define ULPIVW_ADDR_MASK 0xff /* data address field */ -#define ULPIVW_ADDR_SHIFT 16 -#define ULPIVW_RDATA_MASK 0xff /* read data field */ -#define ULPIVW_RDATA_SHIFT 8 -#define ULPIVW_WDATA_MASK 0xff /* write data field */ -#define ULPIVW_WDATA_SHIFT 0 - -static int ulpi_poll(void __iomem *view, u32 bit) -{ - int timeout = 10000; - - while (timeout--) { - u32 data = __raw_readl(view); - - if (!(data & bit)) - return 0; - - cpu_relax(); - }; - - printk(KERN_WARNING "timeout polling for ULPI device\n"); - - return -ETIMEDOUT; -} - -static int ulpi_read(struct usb_phy *otg, u32 reg) -{ - int ret; - void __iomem *view = otg->io_priv; - - /* make sure interface is running */ - if (!(__raw_readl(view) & ULPIVW_SS)) { - __raw_writel(ULPIVW_WU, view); - - /* wait for wakeup */ - ret = ulpi_poll(view, ULPIVW_WU); - if (ret) - return ret; - } - - /* read the register */ - __raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view); - - /* wait for completion */ - ret = ulpi_poll(view, ULPIVW_RUN); - if (ret) - return ret; - - return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK; -} - -static int ulpi_write(struct usb_phy *otg, u32 val, u32 reg) -{ - int ret; - void __iomem *view = otg->io_priv; - - /* make sure the interface is running */ - if (!(__raw_readl(view) & ULPIVW_SS)) { - __raw_writel(ULPIVW_WU, view); - /* wait for wakeup */ - ret = ulpi_poll(view, ULPIVW_WU); - if (ret) - return ret; - } - - __raw_writel((ULPIVW_RUN | ULPIVW_WRITE | - (reg << ULPIVW_ADDR_SHIFT) | - ((val & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), view); - - /* wait for completion */ - return ulpi_poll(view, ULPIVW_RUN); -} - -struct usb_phy_io_ops mxc_ulpi_access_ops = { - .read = ulpi_read, - .write = ulpi_write, -}; -EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops); - -struct usb_phy *imx_otg_ulpi_create(unsigned int flags) -{ - return otg_ulpi_create(&mxc_ulpi_access_ops, flags); -} diff --git a/arch/arm/mach-imx/ulpi.h b/arch/arm/mach-imx/ulpi.h index 42bdaca6d7d..23f5c0349e8 100644 --- a/arch/arm/mach-imx/ulpi.h +++ b/arch/arm/mach-imx/ulpi.h @@ -1,8 +1,13 @@ #ifndef __MACH_ULPI_H #define __MACH_ULPI_H -#ifdef CONFIG_USB_ULPI -struct usb_phy *imx_otg_ulpi_create(unsigned int flags); +#include <linux/usb/ulpi.h> + +#ifdef CONFIG_USB_ULPI_VIEWPORT +static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags) +{ + return otg_ulpi_create(&ulpi_viewport_access_ops, flags); +} #else static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags) { @@ -10,7 +15,5 @@ static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags) } #endif -extern struct usb_phy_io_ops mxc_ulpi_access_ops; - #endif /* __MACH_ULPI_H */ diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile index d14d6b76f4c..ec759ded7b6 100644 --- a/arch/arm/mach-integrator/Makefile +++ b/arch/arm/mach-integrator/Makefile @@ -8,5 +8,5 @@ obj-y := core.o lm.o leds.o obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o -obj-$(CONFIG_PCI) += pci_v3.o pci.o +obj-$(CONFIG_PCI) += pci_v3.o obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h index be5859efe10..306d025d973 100644 --- a/arch/arm/mach-integrator/include/mach/platform.h +++ b/arch/arm/mach-integrator/include/mach/platform.h @@ -305,29 +305,6 @@ /* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */ /* ------------------------------------------------------------------------ - * Where in the memory map does PCI live? - * ------------------------------------------------------------------------ - * This represents a fairly liberal usage of address space. Even though - * the V3 only has two windows (therefore we need to map stuff on the fly), - * we maintain the same addresses, even if they're not mapped. - * - */ -#define PHYS_PCI_MEM_BASE 0x40000000 /* 512M to xxx */ -/* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? - */ -#define PHYS_PCI_IO_BASE 0x60000000 /* 16M to xxx */ -/* unused (128-16)M from B1000000-B7FFFFFF - */ -#define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */ -/* unused ((128-16)M - 64K) from XXX - */ -#define PHYS_PCI_V3_BASE 0x62000000 - -#define PCI_MEMORY_VADDR IOMEM(0xe8000000) -#define PCI_CONFIG_VADDR IOMEM(0xec000000) -#define PCI_V3_VADDR IOMEM(0xed000000) - -/* ------------------------------------------------------------------------ * Integrator Interrupt Controllers * ------------------------------------------------------------------------ * diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index b23c8e4f28e..a5b15c4e8de 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -41,7 +41,6 @@ #include <linux/stat.h> #include <linux/sys_soc.h> #include <linux/termios.h> -#include <video/vga.h> #include <mach/hardware.h> #include <mach/platform.h> @@ -57,10 +56,10 @@ #include <asm/mach/arch.h> #include <asm/mach/irq.h> #include <asm/mach/map.h> -#include <asm/mach/pci.h> #include <asm/mach/time.h> #include "common.h" +#include "pci_v3.h" /* Base address to the AP system controller */ void __iomem *ap_syscon_base; @@ -78,10 +77,6 @@ void __iomem *ap_syscon_base; /* * Logical Physical - * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M) - * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M) - * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k) - * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) * ef000000 Cache flush * f1000000 10000000 Core module registers * f1100000 11000000 System controller registers @@ -130,29 +125,13 @@ static struct map_desc ap_io_desc[] __initdata __maybe_unused = { .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE), .length = SZ_4K, .type = MT_DEVICE - }, { - .virtual = (unsigned long)PCI_MEMORY_VADDR, - .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE), - .length = SZ_16M, - .type = MT_DEVICE - }, { - .virtual = (unsigned long)PCI_CONFIG_VADDR, - .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE), - .length = SZ_16M, - .type = MT_DEVICE - }, { - .virtual = (unsigned long)PCI_V3_VADDR, - .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE), - .length = SZ_64K, - .type = MT_DEVICE } }; static void __init ap_map_io(void) { iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); - vga_base = (unsigned long)PCI_MEMORY_VADDR; - pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE)); + pci_v3_early_init(); } #ifdef CONFIG_PM @@ -615,6 +594,11 @@ static void __init ap_map_io_atag(void) * for eventual deletion. */ +static struct platform_device pci_v3_device = { + .name = "pci-v3", + .id = 0, +}; + static struct resource cfi_flash_resource = { .start = INTEGRATOR_FLASH_BASE, .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1, @@ -672,6 +656,7 @@ static void __init ap_init(void) unsigned long sc_dec; int i; + platform_device_register(&pci_v3_device); platform_device_register(&cfi_flash_device); ap_syscon_base = __io_address(INTEGRATOR_SC_BASE); diff --git a/arch/arm/mach-integrator/pci.c b/arch/arm/mach-integrator/pci.c deleted file mode 100644 index 6c1667e728f..00000000000 --- a/arch/arm/mach-integrator/pci.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * linux/arch/arm/mach-integrator/pci-integrator.c - * - * Copyright (C) 1999 ARM Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * - * PCI functions for Integrator - */ -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/interrupt.h> -#include <linux/init.h> - -#include <asm/mach/pci.h> -#include <asm/mach-types.h> - -#include <mach/irqs.h> - -/* - * A small note about bridges and interrupts. The DECchip 21050 (and - * later) adheres to the PCI-PCI bridge specification. This says that - * the interrupts on the other side of a bridge are swizzled in the - * following manner: - * - * Dev Interrupt Interrupt - * Pin on Pin on - * Device Connector - * - * 4 A A - * B B - * C C - * D D - * - * 5 A B - * B C - * C D - * D A - * - * 6 A C - * B D - * C A - * D B - * - * 7 A D - * B A - * C B - * D C - * - * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A. - * Thus, each swizzle is ((pin-1) + (device#-4)) % 4 - */ - -/* - * This routine handles multiple bridges. - */ -static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp) -{ - if (*pinp == 0) - *pinp = 1; - - return pci_common_swizzle(dev, pinp); -} - -static int irq_tab[4] __initdata = { - IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3 -}; - -/* - * map the specified device/slot/pin to an IRQ. This works out such - * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1. - */ -static int __init integrator_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int intnr = ((slot - 9) + (pin - 1)) & 3; - - return irq_tab[intnr]; -} - -extern void pci_v3_init(void *); - -static struct hw_pci integrator_pci __initdata = { - .swizzle = integrator_swizzle, - .map_irq = integrator_map_irq, - .setup = pci_v3_setup, - .nr_controllers = 1, - .ops = &pci_v3_ops, - .preinit = pci_v3_preinit, - .postinit = pci_v3_postinit, -}; - -static int __init integrator_pci_init(void) -{ - if (machine_is_integrator()) - pci_common_init(&integrator_pci); - return 0; -} - -subsys_initcall(integrator_pci_init); diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index e7fcea7f330..a0e069d37e1 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -27,16 +27,198 @@ #include <linux/spinlock.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/of_pci.h> +#include <video/vga.h> #include <mach/hardware.h> #include <mach/platform.h> #include <mach/irqs.h> +#include <asm/mach/map.h> #include <asm/signal.h> #include <asm/mach/pci.h> #include <asm/irq_regs.h> -#include <asm/hardware/pci_v3.h> +#include "pci_v3.h" + +/* + * Where in the memory map does PCI live? + * + * This represents a fairly liberal usage of address space. Even though + * the V3 only has two windows (therefore we need to map stuff on the fly), + * we maintain the same addresses, even if they're not mapped. + */ +#define PHYS_PCI_MEM_BASE 0x40000000 /* 512M */ +#define PHYS_PCI_IO_BASE 0x60000000 /* 16M */ +#define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M */ +#define PHYS_PCI_V3_BASE 0x62000000 /* 64K */ + +#define PCI_MEMORY_VADDR IOMEM(0xe8000000) +#define PCI_CONFIG_VADDR IOMEM(0xec000000) + +/* + * V3 Local Bus to PCI Bridge definitions + * + * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04 + * All V3 register names are prefaced by V3_ to avoid clashing with any other + * PCI definitions. Their names match the user's manual. + * + * I'm assuming that I20 is disabled. + * + */ +#define V3_PCI_VENDOR 0x00000000 +#define V3_PCI_DEVICE 0x00000002 +#define V3_PCI_CMD 0x00000004 +#define V3_PCI_STAT 0x00000006 +#define V3_PCI_CC_REV 0x00000008 +#define V3_PCI_HDR_CFG 0x0000000C +#define V3_PCI_IO_BASE 0x00000010 +#define V3_PCI_BASE0 0x00000014 +#define V3_PCI_BASE1 0x00000018 +#define V3_PCI_SUB_VENDOR 0x0000002C +#define V3_PCI_SUB_ID 0x0000002E +#define V3_PCI_ROM 0x00000030 +#define V3_PCI_BPARAM 0x0000003C +#define V3_PCI_MAP0 0x00000040 +#define V3_PCI_MAP1 0x00000044 +#define V3_PCI_INT_STAT 0x00000048 +#define V3_PCI_INT_CFG 0x0000004C +#define V3_LB_BASE0 0x00000054 +#define V3_LB_BASE1 0x00000058 +#define V3_LB_MAP0 0x0000005E +#define V3_LB_MAP1 0x00000062 +#define V3_LB_BASE2 0x00000064 +#define V3_LB_MAP2 0x00000066 +#define V3_LB_SIZE 0x00000068 +#define V3_LB_IO_BASE 0x0000006E +#define V3_FIFO_CFG 0x00000070 +#define V3_FIFO_PRIORITY 0x00000072 +#define V3_FIFO_STAT 0x00000074 +#define V3_LB_ISTAT 0x00000076 +#define V3_LB_IMASK 0x00000077 +#define V3_SYSTEM 0x00000078 +#define V3_LB_CFG 0x0000007A +#define V3_PCI_CFG 0x0000007C +#define V3_DMA_PCI_ADR0 0x00000080 +#define V3_DMA_PCI_ADR1 0x00000090 +#define V3_DMA_LOCAL_ADR0 0x00000084 +#define V3_DMA_LOCAL_ADR1 0x00000094 +#define V3_DMA_LENGTH0 0x00000088 +#define V3_DMA_LENGTH1 0x00000098 +#define V3_DMA_CSR0 0x0000008B +#define V3_DMA_CSR1 0x0000009B +#define V3_DMA_CTLB_ADR0 0x0000008C +#define V3_DMA_CTLB_ADR1 0x0000009C +#define V3_DMA_DELAY 0x000000E0 +#define V3_MAIL_DATA 0x000000C0 +#define V3_PCI_MAIL_IEWR 0x000000D0 +#define V3_PCI_MAIL_IERD 0x000000D2 +#define V3_LB_MAIL_IEWR 0x000000D4 +#define V3_LB_MAIL_IERD 0x000000D6 +#define V3_MAIL_WR_STAT 0x000000D8 +#define V3_MAIL_RD_STAT 0x000000DA +#define V3_QBA_MAP 0x000000DC + +/* PCI COMMAND REGISTER bits + */ +#define V3_COMMAND_M_FBB_EN (1 << 9) +#define V3_COMMAND_M_SERR_EN (1 << 8) +#define V3_COMMAND_M_PAR_EN (1 << 6) +#define V3_COMMAND_M_MASTER_EN (1 << 2) +#define V3_COMMAND_M_MEM_EN (1 << 1) +#define V3_COMMAND_M_IO_EN (1 << 0) + +/* SYSTEM REGISTER bits + */ +#define V3_SYSTEM_M_RST_OUT (1 << 15) +#define V3_SYSTEM_M_LOCK (1 << 14) + +/* PCI_CFG bits + */ +#define V3_PCI_CFG_M_I2O_EN (1 << 15) +#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14) +#define V3_PCI_CFG_M_IO_DIS (1 << 13) +#define V3_PCI_CFG_M_EN3V (1 << 12) +#define V3_PCI_CFG_M_RETRY_EN (1 << 10) +#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) +#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) + +/* PCI_BASE register bits (PCI -> Local Bus) + */ +#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000 +#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00 +#define V3_PCI_BASE_M_PREFETCH (1 << 3) +#define V3_PCI_BASE_M_TYPE (3 << 1) +#define V3_PCI_BASE_M_IO (1 << 0) + +/* PCI MAP register bits (PCI -> Local bus) + */ +#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 +#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) +#define V3_PCI_MAP_M_ROM_SIZE (3 << 10) +#define V3_PCI_MAP_M_SWAP (3 << 8) +#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 +#define V3_PCI_MAP_M_REG_EN (1 << 1) +#define V3_PCI_MAP_M_ENABLE (1 << 0) + +/* + * LB_BASE0,1 register bits (Local bus -> PCI) + */ +#define V3_LB_BASE_ADR_BASE 0xfff00000 +#define V3_LB_BASE_SWAP (3 << 8) +#define V3_LB_BASE_ADR_SIZE (15 << 4) +#define V3_LB_BASE_PREFETCH (1 << 3) +#define V3_LB_BASE_ENABLE (1 << 0) + +#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) +#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) +#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) +#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) +#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) +#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) +#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) +#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) +#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) +#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) +#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) +#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) + +#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) + +/* + * LB_MAP0,1 register bits (Local bus -> PCI) + */ +#define V3_LB_MAP_MAP_ADR 0xfff0 +#define V3_LB_MAP_TYPE (7 << 1) +#define V3_LB_MAP_AD_LOW_EN (1 << 0) + +#define V3_LB_MAP_TYPE_IACK (0 << 1) +#define V3_LB_MAP_TYPE_IO (1 << 1) +#define V3_LB_MAP_TYPE_MEM (3 << 1) +#define V3_LB_MAP_TYPE_CONFIG (5 << 1) +#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) + +#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) + +/* + * LB_BASE2 register bits (Local bus -> PCI IO) + */ +#define V3_LB_BASE2_ADR_BASE 0xff00 +#define V3_LB_BASE2_SWAP (3 << 6) +#define V3_LB_BASE2_ENABLE (1 << 0) + +#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) + +/* + * LB_MAP2 register bits (Local bus -> PCI IO) + */ +#define V3_LB_MAP2_MAP_ADR 0xff00 + +#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) /* * The V3 PCI interface chip in Integrator provides several windows from @@ -101,15 +283,22 @@ * the mappings into PCI memory. */ +/* Filled in by probe */ +static void __iomem *pci_v3_base; +static struct resource conf_mem; /* FIXME: remap this instead of static map */ +static struct resource io_mem; +static struct resource non_mem; +static struct resource pre_mem; + // V3 access routines -#define v3_writeb(o,v) __raw_writeb(v, PCI_V3_VADDR + (unsigned int)(o)) -#define v3_readb(o) (__raw_readb(PCI_V3_VADDR + (unsigned int)(o))) +#define v3_writeb(o,v) __raw_writeb(v, pci_v3_base + (unsigned int)(o)) +#define v3_readb(o) (__raw_readb(pci_v3_base + (unsigned int)(o))) -#define v3_writew(o,v) __raw_writew(v, PCI_V3_VADDR + (unsigned int)(o)) -#define v3_readw(o) (__raw_readw(PCI_V3_VADDR + (unsigned int)(o))) +#define v3_writew(o,v) __raw_writew(v, pci_v3_base + (unsigned int)(o)) +#define v3_readw(o) (__raw_readw(pci_v3_base + (unsigned int)(o))) -#define v3_writel(o,v) __raw_writel(v, PCI_V3_VADDR + (unsigned int)(o)) -#define v3_readl(o) (__raw_readl(PCI_V3_VADDR + (unsigned int)(o))) +#define v3_writel(o,v) __raw_writel(v, pci_v3_base + (unsigned int)(o)) +#define v3_readl(o) (__raw_readl(pci_v3_base + (unsigned int)(o))) /*============================================================================ * @@ -243,13 +432,13 @@ static void __iomem *v3_open_config_window(struct pci_bus *bus, * prefetchable), this frees up base1 for re-use by * configuration memory */ - v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | + v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) | V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE); /* * Set up base1/map1 to point into configuration space. */ - v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) | + v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(conf_mem.start) | V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE); v3_writew(V3_LB_MAP1, mapaddress); @@ -261,7 +450,7 @@ static void v3_close_config_window(void) /* * Reassign base1 for use by prefetchable PCI memory */ - v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | + v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | V3_LB_BASE_ENABLE); v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | @@ -270,7 +459,7 @@ static void v3_close_config_window(void) /* * And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */ - v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | + v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); } @@ -337,25 +526,11 @@ static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where, return PCIBIOS_SUCCESSFUL; } -struct pci_ops pci_v3_ops = { +static struct pci_ops pci_v3_ops = { .read = v3_read_config, .write = v3_write_config, }; -static struct resource non_mem = { - .name = "PCI non-prefetchable", - .start = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START, - .end = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static struct resource pre_mem = { - .name = "PCI prefetchable", - .start = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START, - .end = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START + PCI_BUS_PREMEM_SIZE - 1, - .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, -}; - static int __init pci_v3_setup_resources(struct pci_sys_data *sys) { if (request_resource(&iomem_resource, &non_mem)) { @@ -471,7 +646,7 @@ static irqreturn_t v3_irq(int dummy, void *devid) return IRQ_HANDLED; } -int __init pci_v3_setup(int nr, struct pci_sys_data *sys) +static int __init pci_v3_setup(int nr, struct pci_sys_data *sys) { int ret = 0; @@ -479,7 +654,7 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys) return -EINVAL; if (nr == 0) { - sys->mem_offset = PHYS_PCI_MEM_BASE; + sys->mem_offset = non_mem.start; ret = pci_v3_setup_resources(sys); } @@ -490,18 +665,10 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys) * V3_LB_BASE? - local bus address * V3_LB_MAP? - pci bus address */ -void __init pci_v3_preinit(void) +static void __init pci_v3_preinit(void) { unsigned long flags; unsigned int temp; - int ret; - - /* Remap the Integrator system controller */ - ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100); - if (!ap_syscon_base) { - pr_err("unable to remap the AP syscon for PCIv3\n"); - return; - } pcibios_min_mem = 0x00100000; @@ -525,7 +692,7 @@ void __init pci_v3_preinit(void) * Setup window 0 - PCI non-prefetchable memory * Local: 0x40000000 Bus: 0x00000000 Size: 256MB */ - v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | + v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | V3_LB_MAP_TYPE_MEM); @@ -534,7 +701,7 @@ void __init pci_v3_preinit(void) * Setup window 1 - PCI prefetchable memory * Local: 0x50000000 Bus: 0x10000000 Size: 256MB */ - v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | + v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | V3_LB_BASE_ENABLE); v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | @@ -543,7 +710,7 @@ void __init pci_v3_preinit(void) /* * Setup window 2 - PCI IO */ - v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(PHYS_PCI_IO_BASE) | + v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_mem.start) | V3_LB_BASE_ENABLE); v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0)); @@ -578,18 +745,10 @@ void __init pci_v3_preinit(void) v3_writeb(V3_LB_IMASK, 0x28); __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET); - /* - * Grab the PCI error interrupt. - */ - ret = request_irq(IRQ_AP_V3INT, v3_irq, 0, "V3", NULL); - if (ret) - printk(KERN_ERR "PCI: unable to grab PCI error " - "interrupt: %d\n", ret); - raw_spin_unlock_irqrestore(&v3_lock, flags); } -void __init pci_v3_postinit(void) +static void __init pci_v3_postinit(void) { unsigned int pci_cmd; @@ -608,5 +767,278 @@ void __init pci_v3_postinit(void) "interrupt: %d\n", ret); #endif - register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0); + register_isa_ports(non_mem.start, io_mem.start, 0); +} + +/* + * A small note about bridges and interrupts. The DECchip 21050 (and + * later) adheres to the PCI-PCI bridge specification. This says that + * the interrupts on the other side of a bridge are swizzled in the + * following manner: + * + * Dev Interrupt Interrupt + * Pin on Pin on + * Device Connector + * + * 4 A A + * B B + * C C + * D D + * + * 5 A B + * B C + * C D + * D A + * + * 6 A C + * B D + * C A + * D B + * + * 7 A D + * B A + * C B + * D C + * + * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A. + * Thus, each swizzle is ((pin-1) + (device#-4)) % 4 + */ + +/* + * This routine handles multiple bridges. + */ +static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp) +{ + if (*pinp == 0) + *pinp = 1; + + return pci_common_swizzle(dev, pinp); +} + +static int irq_tab[4] __initdata = { + IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3 +}; + +/* + * map the specified device/slot/pin to an IRQ. This works out such + * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1. + */ +static int __init pci_v3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + int intnr = ((slot - 9) + (pin - 1)) & 3; + + return irq_tab[intnr]; +} + +static struct hw_pci pci_v3 __initdata = { + .swizzle = pci_v3_swizzle, + .setup = pci_v3_setup, + .nr_controllers = 1, + .ops = &pci_v3_ops, + .preinit = pci_v3_preinit, + .postinit = pci_v3_postinit, +}; + +#ifdef CONFIG_OF + +static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin) +{ + struct of_irq oirq; + int ret; + + ret = of_irq_map_pci(dev, &oirq); + if (ret) { + dev_err(&dev->dev, "of_irq_map_pci() %d\n", ret); + /* Proper return code 0 == NO_IRQ */ + return 0; + } + + return irq_create_of_mapping(oirq.controller, oirq.specifier, + oirq.size); +} + +static int __init pci_v3_dtprobe(struct platform_device *pdev, + struct device_node *np) +{ + struct of_pci_range_parser parser; + struct of_pci_range range; + struct resource *res; + int irq, ret; + + if (of_pci_range_parser_init(&parser, np)) + return -EINVAL; + + /* Get base for bridge registers */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "unable to obtain PCIv3 base\n"); + return -ENODEV; + } + pci_v3_base = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (!pci_v3_base) { + dev_err(&pdev->dev, "unable to remap PCIv3 base\n"); + return -ENODEV; + } + + /* Get and request error IRQ resource */ + irq = platform_get_irq(pdev, 0); + if (irq <= 0) { + dev_err(&pdev->dev, "unable to obtain PCIv3 error IRQ\n"); + return -ENODEV; + } + ret = devm_request_irq(&pdev->dev, irq, v3_irq, 0, + "PCIv3 error", NULL); + if (ret < 0) { + dev_err(&pdev->dev, "unable to request PCIv3 error IRQ %d (%d)\n", irq, ret); + return ret; + } + + for_each_of_pci_range(&parser, &range) { + if (!range.flags) { + of_pci_range_to_resource(&range, np, &conf_mem); + conf_mem.name = "PCIv3 config"; + } + if (range.flags & IORESOURCE_IO) { + of_pci_range_to_resource(&range, np, &io_mem); + io_mem.name = "PCIv3 I/O"; + } + if ((range.flags & IORESOURCE_MEM) && + !(range.flags & IORESOURCE_PREFETCH)) { + of_pci_range_to_resource(&range, np, &non_mem); + non_mem.name = "PCIv3 non-prefetched mem"; + } + if ((range.flags & IORESOURCE_MEM) && + (range.flags & IORESOURCE_PREFETCH)) { + of_pci_range_to_resource(&range, np, &pre_mem); + pre_mem.name = "PCIv3 prefetched mem"; + } + } + + if (!conf_mem.start || !io_mem.start || + !non_mem.start || !pre_mem.start) { + dev_err(&pdev->dev, "missing ranges in device node\n"); + return -EINVAL; + } + + pci_v3.map_irq = pci_v3_map_irq_dt; + pci_common_init_dev(&pdev->dev, &pci_v3); + + return 0; +} + +#else + +static inline int pci_v3_dtprobe(struct platform_device *pdev, + struct device_node *np) +{ + return -EINVAL; +} + +#endif + +static int __init pci_v3_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + int ret; + + /* Remap the Integrator system controller */ + ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100); + if (!ap_syscon_base) { + dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n"); + return -ENODEV; + } + + /* Device tree probe path */ + if (np) + return pci_v3_dtprobe(pdev, np); + + pci_v3_base = devm_ioremap(&pdev->dev, PHYS_PCI_V3_BASE, SZ_64K); + if (!pci_v3_base) { + dev_err(&pdev->dev, "unable to remap PCIv3 base\n"); + return -ENODEV; + } + + ret = devm_request_irq(&pdev->dev, IRQ_AP_V3INT, v3_irq, 0, "V3", NULL); + if (ret) { + dev_err(&pdev->dev, "unable to grab PCI error interrupt: %d\n", + ret); + return -ENODEV; + } + + conf_mem.name = "PCIv3 config"; + conf_mem.start = PHYS_PCI_CONFIG_BASE; + conf_mem.end = PHYS_PCI_CONFIG_BASE + SZ_16M - 1; + conf_mem.flags = IORESOURCE_MEM; + + io_mem.name = "PCIv3 I/O"; + io_mem.start = PHYS_PCI_IO_BASE; + io_mem.end = PHYS_PCI_IO_BASE + SZ_16M - 1; + io_mem.flags = IORESOURCE_MEM; + + non_mem.name = "PCIv3 non-prefetched mem"; + non_mem.start = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START; + non_mem.end = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START + + PCI_BUS_NONMEM_SIZE - 1; + non_mem.flags = IORESOURCE_MEM; + + pre_mem.name = "PCIv3 prefetched mem"; + pre_mem.start = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START; + pre_mem.end = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START + + PCI_BUS_PREMEM_SIZE - 1; + pre_mem.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + + pci_v3.map_irq = pci_v3_map_irq; + + pci_common_init_dev(&pdev->dev, &pci_v3); + + return 0; +} + +static const struct of_device_id pci_ids[] = { + { .compatible = "v3,v360epc-pci", }, + {}, +}; + +static struct platform_driver pci_v3_driver = { + .driver = { + .name = "pci-v3", + .of_match_table = pci_ids, + }, +}; + +static int __init pci_v3_init(void) +{ + return platform_driver_probe(&pci_v3_driver, pci_v3_probe); +} + +subsys_initcall(pci_v3_init); + +/* + * Static mappings for the PCIv3 bridge + * + * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M) + * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M) + * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) + */ +static struct map_desc pci_v3_io_desc[] __initdata __maybe_unused = { + { + .virtual = (unsigned long)PCI_MEMORY_VADDR, + .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, { + .virtual = (unsigned long)PCI_CONFIG_VADDR, + .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE), + .length = SZ_16M, + .type = MT_DEVICE + } +}; + +int __init pci_v3_early_init(void) +{ + iotable_init(pci_v3_io_desc, ARRAY_SIZE(pci_v3_io_desc)); + vga_base = (unsigned long)PCI_MEMORY_VADDR; + pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE)); + return 0; } diff --git a/arch/arm/mach-integrator/pci_v3.h b/arch/arm/mach-integrator/pci_v3.h new file mode 100644 index 00000000000..755fd29fed4 --- /dev/null +++ b/arch/arm/mach-integrator/pci_v3.h @@ -0,0 +1,2 @@ +/* Simple oneliner include to the PCIv3 early init */ +extern int pci_v3_early_init(void); diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig new file mode 100644 index 00000000000..2dbd4ce3653 --- /dev/null +++ b/arch/arm/mach-keystone/Kconfig @@ -0,0 +1,15 @@ +config ARCH_KEYSTONE + bool "Texas Instruments Keystone Devices" + depends on ARCH_MULTI_V7 + select CPU_V7 + select ARM_GIC + select HAVE_ARM_ARCH_TIMER + select HAVE_SMP + select CLKSRC_MMIO + select GENERIC_CLOCKEVENTS + select HAVE_SCHED_CLOCK + select ARCH_WANT_OPTIONAL_GPIOLIB + select ARM_ERRATA_798181 + help + Support for boards based on the Texas Instruments Keystone family of + SoCs. diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile new file mode 100644 index 00000000000..3f6b8ab8223 --- /dev/null +++ b/arch/arm/mach-keystone/Makefile @@ -0,0 +1,2 @@ +obj-y := keystone.o +obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-keystone/Makefile.boot b/arch/arm/mach-keystone/Makefile.boot new file mode 100644 index 00000000000..f3835c43af6 --- /dev/null +++ b/arch/arm/mach-keystone/Makefile.boot @@ -0,0 +1 @@ +zreladdr-y := 0x80008000 diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c new file mode 100644 index 00000000000..fe4d9ff93a7 --- /dev/null +++ b/arch/arm/mach-keystone/keystone.c @@ -0,0 +1,75 @@ +/* + * Keystone2 based boards and SOC related code. + * + * Copyright 2013 Texas Instruments, Inc. + * Cyril Chemparathy <cyril@ti.com> + * Santosh Shilimkar <santosh.shillimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ +#include <linux/io.h> +#include <linux/of.h> +#include <linux/init.h> +#include <linux/of_platform.h> +#include <linux/of_address.h> + +#include <asm/setup.h> +#include <asm/mach/map.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/smp_plat.h> + +#include "keystone.h" + +#define PLL_RESET_WRITE_KEY_MASK 0xffff0000 +#define PLL_RESET_WRITE_KEY 0x5a69 +#define PLL_RESET BIT(16) + +static void __iomem *keystone_rstctrl; + +static void __init keystone_init(void) +{ + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "ti,keystone-reset"); + if (WARN_ON(!node)) + pr_warn("ti,keystone-reset node undefined\n"); + + keystone_rstctrl = of_iomap(node, 0); + if (WARN_ON(!keystone_rstctrl)) + pr_warn("ti,keystone-reset iomap error\n"); + + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char *keystone_match[] __initconst = { + "ti,keystone-evm", + NULL, +}; + +void keystone_restart(char mode, const char *cmd) +{ + u32 val; + + BUG_ON(!keystone_rstctrl); + + /* Enable write access to RSTCTRL */ + val = readl(keystone_rstctrl); + val &= PLL_RESET_WRITE_KEY_MASK; + val |= PLL_RESET_WRITE_KEY; + writel(val, keystone_rstctrl); + + /* Reset the SOC */ + val = readl(keystone_rstctrl); + val &= ~PLL_RESET; + writel(val, keystone_rstctrl); +} + +DT_MACHINE_START(KEYSTONE, "Keystone") + .smp = smp_ops(keystone_smp_ops), + .init_machine = keystone_init, + .dt_compat = keystone_match, + .restart = keystone_restart, +MACHINE_END diff --git a/arch/arm/mach-keystone/keystone.h b/arch/arm/mach-keystone/keystone.h new file mode 100644 index 00000000000..43a1b4789a6 --- /dev/null +++ b/arch/arm/mach-keystone/keystone.h @@ -0,0 +1,17 @@ +/* + * Copyright 2013 Texas Instruments, Inc. + * Cyril Chemparathy <cyril@ti.com> + * Santosh Shilimkar <santosh.shillimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ + +#ifndef __KEYSTONE_H__ +#define __KEYSTONE_H__ + +extern struct smp_operations keystone_smp_ops; +extern void secondary_startup(void); + +#endif /* __KEYSTONE_H__ */ diff --git a/arch/arm/mach-keystone/platsmp.c b/arch/arm/mach-keystone/platsmp.c new file mode 100644 index 00000000000..630ab3bd5f7 --- /dev/null +++ b/arch/arm/mach-keystone/platsmp.c @@ -0,0 +1,52 @@ +/* + * Keystone SOC SMP platform code + * + * Copyright 2013 Texas Instruments, Inc. + * Cyril Chemparathy <cyril@ti.com> + * Santosh Shilimkar <santosh.shillimkar@ti.com> + * + * Based on platsmp.c, Copyright (C) 2002 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/smp.h> +#include <linux/io.h> + +#include <asm/smp_plat.h> +#include <asm/prom.h> + +#include "keystone.h" + +static int __cpuinit keystone_smp_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + unsigned long start = virt_to_phys(&secondary_startup); + int error; + + pr_debug("keystone-smp: booting cpu %d, vector %08lx\n", + cpu, start); + + asm volatile ( + "mov r0, #0\n" /* power on cmd */ + "mov r1, %1\n" /* cpu */ + "mov r2, %2\n" /* start */ + ".inst 0xe1600070\n" /* smc #0 */ + "mov %0, r0\n" + : "=r" (error) + : "r"(cpu), "r"(start) + : "cc", "r0", "r1", "r2", "memory" + ); + + pr_debug("keystone-smp: monitor returned %d\n", error); + + return error; +} + +struct smp_operations keystone_smp_ops __initdata = { + .smp_init_cpus = arm_dt_init_cpu_maps, + .smp_boot_secondary = keystone_smp_boot_secondary, +}; diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 7509a89af96..e610e137aa3 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -8,12 +8,6 @@ config MACH_D2NET_V2 Say 'Y' here if you want your kernel to support the LaCie d2 Network v2 NAS. -config MACH_DB88F6281_BP - bool "Marvell DB-88F6281-BP Development Board" - help - Say 'Y' here if you want your kernel to support the - Marvell DB-88F6281-BP Development Board. - config MACH_DOCKSTAR bool "Seagate FreeAgent DockStar" help @@ -134,13 +128,12 @@ comment "Device tree entries" config ARCH_KIRKWOOD_DT bool "Marvell Kirkwood Flattened Device Tree" + select KIRKWOOD_CLK select POWER_SUPPLY select POWER_RESET select POWER_RESET_GPIO select REGULATOR select REGULATOR_FIXED_VOLTAGE - select MVEBU_CLK_CORE - select MVEBU_CLK_GATING select USE_OF help Say 'Y' here if you want your kernel to support the @@ -153,6 +146,13 @@ config MACH_CLOUDBOX_DT Say 'Y' here if you want your kernel to support the LaCie CloudBox NAS, using Flattened Device Tree. +config MACH_DB88F628X_BP_DT + bool "Marvell DB-88F628x-BP Development Board (Flattened Device Tree)" + help + Say 'Y' here if you want your kernel to support the Marvell + DB-88F6281-BP and DB-88F6282-BP Development Board (Flattened + Device Tree). + config MACH_DLINK_KIRKWOOD_DT bool "D-Link Kirkwood-based NAS (Flattened Device Tree)" select ARCH_KIRKWOOD_DT @@ -272,14 +272,6 @@ config MACH_NETSPACE_V2_DT Say 'Y' here if you want your kernel to support the LaCie Network Space v2 NAS, using Flattened Device Tree. -config MACH_NSA310_DT - bool "ZyXEL NSA-310 (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - select ARM_ATAG_DTB_COMPAT - help - Say 'Y' here if you want your kernel to support the - ZyXEL NSA-310 board (Flattened Device Tree). - config MACH_OPENBLOCKS_A6_DT bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)" select ARCH_KIRKWOOD_DT diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index e1f3735d341..2fdc3a7ad22 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -1,7 +1,6 @@ obj-y += common.o irq.o pcie.o mpp.o obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o -obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o obj-$(CONFIG_MACH_DOCKSTAR) += dockstar-setup.o obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG) += sheevaplug-setup.o obj-$(CONFIG_MACH_GURUPLUG) += guruplug-setup.o @@ -21,6 +20,7 @@ obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o obj-$(CONFIG_MACH_CLOUDBOX_DT) += board-ns2.o +obj-$(CONFIG_MACH_DB88F628X_BP_DT) += board-db88f628x-bp.o obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += board-dnskw.o obj-$(CONFIG_MACH_DOCKSTAR_DT) += board-dockstar.o obj-$(CONFIG_MACH_DREAMPLUG_DT) += board-dreamplug.o @@ -37,7 +37,6 @@ obj-$(CONFIG_MACH_NETSPACE_LITE_V2_DT) += board-ns2.o obj-$(CONFIG_MACH_NETSPACE_MAX_V2_DT) += board-ns2.o obj-$(CONFIG_MACH_NETSPACE_MINI_V2_DT) += board-ns2.o obj-$(CONFIG_MACH_NETSPACE_V2_DT) += board-ns2.o -obj-$(CONFIG_MACH_NSA310_DT) += board-nsa310.o obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT) += board-openblocks_a6.o obj-$(CONFIG_MACH_READYNAS_DT) += board-readynas.o obj-$(CONFIG_MACH_TOPKICK_DT) += board-usi_topkick.o diff --git a/arch/arm/mach-kirkwood/board-db88f628x-bp.c b/arch/arm/mach-kirkwood/board-db88f628x-bp.c new file mode 100644 index 00000000000..2f574bc8ed4 --- /dev/null +++ b/arch/arm/mach-kirkwood/board-db88f628x-bp.c @@ -0,0 +1,24 @@ +/* + * Saeed Bishara <saeed@marvell.com> + * + * Marvell DB-88F628{1,2}-BP Development Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/of.h> +#include <linux/mv643xx_eth.h> +#include "common.h" + +static struct mv643xx_eth_platform_data db88f628x_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(8), +}; + +void __init db88f628x_init(void) +{ + kirkwood_ge00_init(&db88f628x_ge00_data); +} diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index e9647b80cb5..cee5dc71cb6 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -15,7 +15,6 @@ #include <linux/of.h> #include <linux/of_platform.h> #include <linux/clk-provider.h> -#include <linux/clk/mvebu.h> #include <linux/kexec.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -25,11 +24,6 @@ #include <plat/common.h> #include "common.h" -static struct of_device_id kirkwood_dt_match_table[] __initdata = { - { .compatible = "simple-bus", }, - { } -}; - /* * There are still devices that doesn't know about DT yet. Get clock * gates here and add a clock lookup alias, so that old platform @@ -77,7 +71,7 @@ static void __init kirkwood_legacy_clk_init(void) static void __init kirkwood_of_clk_init(void) { - mvebu_clocks_init(); + of_clk_init(NULL); kirkwood_legacy_clk_init(); } @@ -97,6 +91,8 @@ static void __init kirkwood_dt_init(void) kirkwood_l2_init(); + kirkwood_cpufreq_init(); + /* Setup root of clk tree */ kirkwood_of_clk_init(); @@ -147,6 +143,10 @@ static void __init kirkwood_dt_init(void) of_machine_is_compatible("lacie,netspace_v2")) ns2_init(); + if (of_machine_is_compatible("marvell,db-88f6281-bp") || + of_machine_is_compatible("marvell,db-88f6282-bp")) + db88f628x_init(); + if (of_machine_is_compatible("mpl,cec4")) mplcec4_init(); @@ -159,7 +159,7 @@ static void __init kirkwood_dt_init(void) if (of_machine_is_compatible("usi,topkick")) usi_topkick_init(); - of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static const char * const kirkwood_dt_board_compat[] = { @@ -181,6 +181,8 @@ static const char * const kirkwood_dt_board_compat[] = { "lacie,netspace_max_v2", "lacie,netspace_mini_v2", "lacie,netspace_v2", + "marvell,db-88f6281-bp", + "marvell,db-88f6282-bp", "mpl,cec4", "netgear,readynas-duo-v2", "plathome,openblocks-a6", diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c index c8ebde4919e..98b5ad1bba9 100644 --- a/arch/arm/mach-kirkwood/board-iconnect.c +++ b/arch/arm/mach-kirkwood/board-iconnect.c @@ -22,11 +22,3 @@ void __init iconnect_init(void) { kirkwood_ge00_init(&iconnect_ge00_data); } - -static int __init iconnect_pci_init(void) -{ - if (of_machine_is_compatible("iom,iconnect")) - kirkwood_pcie_init(KW_PCIE0); - return 0; -} -subsys_initcall(iconnect_pci_init); diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c index 7d6dc669e17..938712e248f 100644 --- a/arch/arm/mach-kirkwood/board-mplcec4.c +++ b/arch/arm/mach-kirkwood/board-mplcec4.c @@ -29,7 +29,6 @@ void __init mplcec4_init(void) */ kirkwood_ge00_init(&mplcec4_ge00_data); kirkwood_ge01_init(&mplcec4_ge01_data); - kirkwood_pcie_init(KW_PCIE0); } diff --git a/arch/arm/mach-kirkwood/board-nsa310.c b/arch/arm/mach-kirkwood/board-nsa310.c deleted file mode 100644 index 55ade93b93b..00000000000 --- a/arch/arm/mach-kirkwood/board-nsa310.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * arch/arm/mach-kirkwood/nsa-310-setup.c - * - * ZyXEL NSA-310 Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <mach/kirkwood.h> -#include <linux/of.h> -#include "common.h" - -static int __init nsa310_pci_init(void) -{ - if (of_machine_is_compatible("zyxel,nsa310")) - kirkwood_pcie_init(KW_PCIE0); - - return 0; -} - -subsys_initcall(nsa310_pci_init); diff --git a/arch/arm/mach-kirkwood/board-readynas.c b/arch/arm/mach-kirkwood/board-readynas.c index fb42c20e273..341b82d9cad 100644 --- a/arch/arm/mach-kirkwood/board-readynas.c +++ b/arch/arm/mach-kirkwood/board-readynas.c @@ -24,5 +24,4 @@ static struct mv643xx_eth_platform_data netgear_readynas_ge00_data = { void __init netgear_readynas_init(void) { kirkwood_ge00_init(&netgear_readynas_ge00_data); - kirkwood_pcie_init(KW_PCIE0); } diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c index acb0187c7ee..4695d5f35fc 100644 --- a/arch/arm/mach-kirkwood/board-ts219.c +++ b/arch/arm/mach-kirkwood/board-ts219.c @@ -41,13 +41,3 @@ void __init qnap_dt_ts219_init(void) pm_power_off = qnap_tsx1x_power_off; } - -/* FIXME: Will not work with DT. Maybe use MPP40_GPIO? */ -static int __init ts219_pci_init(void) -{ - if (machine_is_ts219()) - kirkwood_pcie_init(KW_PCIE0); - - return 0; -} -subsys_initcall(ts219_pci_init); diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index c2cae69e6d2..7c72c725b71 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -528,12 +528,6 @@ void __init kirkwood_init_early(void) { orion_time_set_base(TIMER_VIRT_BASE); - /* - * Some Kirkwood devices allocate their coherent buffers from atomic - * context. Increase size of atomic coherent pool to make sure such - * the allocations won't fail. - */ - init_dma_coherent_pool_size(SZ_1M); mvebu_mbus_init("marvell,kirkwood-mbus", BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ); @@ -604,6 +598,29 @@ void __init kirkwood_audio_init(void) } /***************************************************************************** + * CPU Frequency + ****************************************************************************/ +static struct resource kirkwood_cpufreq_resources[] = { + [0] = { + .start = CPU_CONTROL_PHYS, + .end = CPU_CONTROL_PHYS + 3, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device kirkwood_cpufreq_device = { + .name = "kirkwood-cpufreq", + .id = -1, + .num_resources = ARRAY_SIZE(kirkwood_cpufreq_resources), + .resource = kirkwood_cpufreq_resources, +}; + +void __init kirkwood_cpufreq_init(void) +{ + platform_device_register(&kirkwood_cpufreq_device); +} + +/***************************************************************************** * General ****************************************************************************/ /* @@ -654,30 +671,6 @@ char * __init kirkwood_id(void) void __init kirkwood_setup_wins(void) { - /* - * The PCIe windows will no longer be statically allocated - * here once Kirkwood is migrated to the pci-mvebu driver. - */ - mvebu_mbus_add_window_remap_flags("pcie0.0", - KIRKWOOD_PCIE_IO_PHYS_BASE, - KIRKWOOD_PCIE_IO_SIZE, - KIRKWOOD_PCIE_IO_BUS_BASE, - MVEBU_MBUS_PCI_IO); - mvebu_mbus_add_window_remap_flags("pcie0.0", - KIRKWOOD_PCIE_MEM_PHYS_BASE, - KIRKWOOD_PCIE_MEM_SIZE, - MVEBU_MBUS_NO_REMAP, - MVEBU_MBUS_PCI_MEM); - mvebu_mbus_add_window_remap_flags("pcie1.0", - KIRKWOOD_PCIE1_IO_PHYS_BASE, - KIRKWOOD_PCIE1_IO_SIZE, - KIRKWOOD_PCIE1_IO_BUS_BASE, - MVEBU_MBUS_PCI_IO); - mvebu_mbus_add_window_remap_flags("pcie1.0", - KIRKWOOD_PCIE1_MEM_PHYS_BASE, - KIRKWOOD_PCIE1_MEM_SIZE, - MVEBU_MBUS_NO_REMAP, - MVEBU_MBUS_PCI_MEM); mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE); mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE, diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 21da3b1ebd7..e2e19b302c2 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -51,6 +51,8 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev_ready)(struct mtd_info *)); void kirkwood_audio_init(void); void kirkwood_cpuidle_init(void); +void kirkwood_cpufreq_init(void); + void kirkwood_restart(char, const char *); void kirkwood_clk_init(void); @@ -119,6 +121,12 @@ void km_kirkwood_init(void); static inline void km_kirkwood_init(void) {}; #endif +#ifdef CONFIG_MACH_DB88F628X_BP_DT +void db88f628x_init(void); +#else +static inline void db88f628x_init(void) {}; +#endif + #ifdef CONFIG_MACH_MPLCEC4_DT void mplcec4_init(void); #else diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c deleted file mode 100644 index 5a369fe7475..00000000000 --- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * arch/arm/mach-kirkwood/db88f6281-bp-setup.c - * - * Marvell DB-88F6281-BP Development Board Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/sizes.h> -#include <linux/platform_device.h> -#include <linux/mtd/partitions.h> -#include <linux/ata_platform.h> -#include <linux/mv643xx_eth.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <mach/kirkwood.h> -#include <linux/platform_data/mmc-mvsdio.h> -#include "common.h" -#include "mpp.h" - -static struct mtd_partition db88f6281_nand_parts[] = { - { - .name = "u-boot", - .offset = 0, - .size = SZ_1M - }, { - .name = "uImage", - .offset = MTDPART_OFS_NXTBLK, - .size = SZ_4M - }, { - .name = "root", - .offset = MTDPART_OFS_NXTBLK, - .size = MTDPART_SIZ_FULL - }, -}; - -static struct mv643xx_eth_platform_data db88f6281_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -static struct mv_sata_platform_data db88f6281_sata_data = { - .n_ports = 2, -}; - -static struct mvsdio_platform_data db88f6281_mvsdio_data = { - .gpio_write_protect = 37, - .gpio_card_detect = 38, -}; - -static unsigned int db88f6281_mpp_config[] __initdata = { - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP37_GPIO, - MPP38_GPIO, - 0 -}; - -static void __init db88f6281_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_init(); - kirkwood_mpp_conf(db88f6281_mpp_config); - - kirkwood_nand_init(ARRAY_AND_SIZE(db88f6281_nand_parts), 25); - kirkwood_ehci_init(); - kirkwood_ge00_init(&db88f6281_ge00_data); - kirkwood_sata_init(&db88f6281_sata_data); - kirkwood_uart0_init(); - kirkwood_sdio_init(&db88f6281_mvsdio_data); -} - -static int __init db88f6281_pci_init(void) -{ - if (machine_is_db88f6281_bp()) { - u32 dev, rev; - - kirkwood_pcie_id(&dev, &rev); - if (dev == MV88F6282_DEV_ID) - kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0); - else - kirkwood_pcie_init(KW_PCIE0); - } - return 0; -} -subsys_initcall(db88f6281_pci_init); - -MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board") - /* Maintainer: Saeed Bishara <saeed@marvell.com> */ - .atag_offset = 0x100, - .init_machine = db88f6281_init, - .map_io = kirkwood_map_io, - .init_early = kirkwood_init_early, - .init_irq = kirkwood_init_irq, - .init_time = kirkwood_timer_init, - .restart = kirkwood_restart, -MACHINE_END diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h index 5c82b7dce4e..d4cbe5e81bb 100644 --- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h +++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h @@ -17,6 +17,7 @@ #define CPU_CONFIG_ERROR_PROP 0x00000004 #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) +#define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104) #define CPU_RESET 0x00000002 #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) @@ -69,6 +70,7 @@ #define CGC_RUNIT (1 << 7) #define CGC_XOR0 (1 << 8) #define CGC_AUDIO (1 << 9) +#define CGC_POWERSAVE (1 << 11) #define CGC_SATA0 (1 << 14) #define CGC_SATA1 (1 << 15) #define CGC_XOR1 (1 << 16) diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c index 827cde42414..e96fd71abd7 100644 --- a/arch/arm/mach-kirkwood/mpp.c +++ b/arch/arm/mach-kirkwood/mpp.c @@ -22,9 +22,10 @@ static unsigned int __init kirkwood_variant(void) kirkwood_pcie_id(&dev, &rev); - if ((dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) || - (dev == MV88F6282_DEV_ID)) + if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) return MPP_F6281_MASK; + if (dev == MV88F6282_DEV_ID) + return MPP_F6282_MASK; if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0) return MPP_F6192_MASK; if (dev == MV88F6180_DEV_ID) diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index 7f43e6c2f8c..ddcb09f5bdd 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -12,6 +12,7 @@ #include <linux/pci.h> #include <linux/slab.h> #include <linux/clk.h> +#include <linux/mbus.h> #include <video/vga.h> #include <asm/irq.h> #include <asm/mach/pci.h> @@ -253,6 +254,27 @@ static void __init add_pcie_port(int index, void __iomem *base) void __init kirkwood_pcie_init(unsigned int portmask) { + mvebu_mbus_add_window_remap_flags("pcie0.0", + KIRKWOOD_PCIE_IO_PHYS_BASE, + KIRKWOOD_PCIE_IO_SIZE, + KIRKWOOD_PCIE_IO_BUS_BASE, + MVEBU_MBUS_PCI_IO); + mvebu_mbus_add_window_remap_flags("pcie0.0", + KIRKWOOD_PCIE_MEM_PHYS_BASE, + KIRKWOOD_PCIE_MEM_SIZE, + MVEBU_MBUS_NO_REMAP, + MVEBU_MBUS_PCI_MEM); + mvebu_mbus_add_window_remap_flags("pcie1.0", + KIRKWOOD_PCIE1_IO_PHYS_BASE, + KIRKWOOD_PCIE1_IO_SIZE, + KIRKWOOD_PCIE1_IO_BUS_BASE, + MVEBU_MBUS_PCI_IO); + mvebu_mbus_add_window_remap_flags("pcie1.0", + KIRKWOOD_PCIE1_MEM_PHYS_BASE, + KIRKWOOD_PCIE1_MEM_SIZE, + MVEBU_MBUS_NO_REMAP, + MVEBU_MBUS_PCI_MEM); + vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE; if (portmask & KW_PCIE0) diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c index 283abff9022..e1267d6b468 100644 --- a/arch/arm/mach-kirkwood/ts219-setup.c +++ b/arch/arm/mach-kirkwood/ts219-setup.c @@ -124,7 +124,7 @@ static void __init qnap_ts219_init(void) static int __init ts219_pci_init(void) { if (machine_is_ts219()) - kirkwood_pcie_init(KW_PCIE0); + kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0); return 0; } diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index e11acbb0a46..9eb63d72460 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -10,11 +10,11 @@ config ARCH_MVEBU select PLAT_ORION select SPARSE_IRQ select CLKDEV_LOOKUP - select MVEBU_CLK_CORE - select MVEBU_CLK_CPU - select MVEBU_CLK_GATING select MVEBU_MBUS select ZONE_DMA if ARM_LPAE + select ARCH_REQUIRE_GPIOLIB + select MIGHT_HAVE_PCI + select PCI_QUIRKS if PCI if ARCH_MVEBU @@ -29,6 +29,7 @@ config MACH_ARMADA_370_XP config MACH_ARMADA_370 bool "Marvell Armada 370 boards" + select ARMADA_370_CLK select MACH_ARMADA_370_XP select PINCTRL_ARMADA_370 help @@ -37,6 +38,7 @@ config MACH_ARMADA_370 config MACH_ARMADA_XP bool "Marvell Armada XP boards" + select ARMADA_XP_CLK select MACH_ARMADA_370_XP select PINCTRL_ARMADA_XP help diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index 42a4cb3087e..97cbb802191 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -14,13 +14,13 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <linux/clk-provider.h> +#include <linux/of_address.h> #include <linux/of_platform.h> #include <linux/io.h> #include <linux/time-armada-370-xp.h> -#include <linux/clk/mvebu.h> #include <linux/dma-mapping.h> #include <linux/mbus.h> -#include <linux/irqchip.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -29,52 +29,49 @@ #include "common.h" #include "coherency.h" -static struct map_desc armada_370_xp_io_desc[] __initdata = { - { - .virtual = (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE, - .pfn = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE), - .length = ARMADA_370_XP_REGS_SIZE, - .type = MT_DEVICE, - }, -}; - -void __init armada_370_xp_map_io(void) +static void __init armada_370_xp_map_io(void) { - iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc)); + debug_ll_io_init(); } -void __init armada_370_xp_timer_and_clk_init(void) -{ - mvebu_clocks_init(); - armada_370_xp_timer_init(); -} +/* + * This initialization will be replaced by a DT-based + * initialization once the mvebu-mbus driver gains DT support. + */ + +#define ARMADA_370_XP_MBUS_WINS_OFFS 0x20000 +#define ARMADA_370_XP_MBUS_WINS_SIZE 0x100 +#define ARMADA_370_XP_SDRAM_WINS_OFFS 0x20180 +#define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20 -void __init armada_370_xp_init_early(void) +static void __init armada_370_xp_mbus_init(void) { char *mbus_soc_name; + struct device_node *dn; + const __be32 mbus_wins_offs = cpu_to_be32(ARMADA_370_XP_MBUS_WINS_OFFS); + const __be32 sdram_wins_offs = cpu_to_be32(ARMADA_370_XP_SDRAM_WINS_OFFS); - /* - * Some Armada 370/XP devices allocate their coherent buffers - * from atomic context. Increase size of atomic coherent pool - * to make sure such the allocations won't fail. - */ - init_dma_coherent_pool_size(SZ_1M); - - /* - * This initialization will be replaced by a DT-based - * initialization once the mvebu-mbus driver gains DT support. - */ if (of_machine_is_compatible("marvell,armada370")) mbus_soc_name = "marvell,armada370-mbus"; else mbus_soc_name = "marvell,armadaxp-mbus"; + dn = of_find_node_by_name(NULL, "internal-regs"); + BUG_ON(!dn); + mvebu_mbus_init(mbus_soc_name, - ARMADA_370_XP_MBUS_WINS_BASE, + of_translate_address(dn, &mbus_wins_offs), ARMADA_370_XP_MBUS_WINS_SIZE, - ARMADA_370_XP_SDRAM_WINS_BASE, + of_translate_address(dn, &sdram_wins_offs), ARMADA_370_XP_SDRAM_WINS_SIZE); +} +static void __init armada_370_xp_timer_and_clk_init(void) +{ + of_clk_init(NULL); + armada_370_xp_timer_init(); + coherency_init(); + armada_370_xp_mbus_init(); #ifdef CONFIG_CACHE_L2X0 l2x0_of_init(0, ~0UL); #endif @@ -83,7 +80,6 @@ void __init armada_370_xp_init_early(void) static void __init armada_370_xp_dt_init(void) { of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - coherency_init(); } static const char * const armada_370_xp_dt_compat[] = { @@ -95,8 +91,6 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)") .smp = smp_ops(armada_xp_smp_ops), .init_machine = armada_370_xp_dt_init, .map_io = armada_370_xp_map_io, - .init_early = armada_370_xp_init_early, - .init_irq = irqchip_init, .init_time = armada_370_xp_timer_and_clk_init, .restart = mvebu_restart, .dt_compat = armada_370_xp_dt_compat, diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h index 2070e1b4f34..c612b2c4ed6 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.h +++ b/arch/arm/mach-mvebu/armada-370-xp.h @@ -15,16 +15,6 @@ #ifndef __MACH_ARMADA_370_XP_H #define __MACH_ARMADA_370_XP_H -#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 -#define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfec00000) -#define ARMADA_370_XP_REGS_SIZE SZ_1M - -/* These defines can go away once mvebu-mbus has a DT binding */ -#define ARMADA_370_XP_MBUS_WINS_BASE (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000) -#define ARMADA_370_XP_MBUS_WINS_SIZE 0x100 -#define ARMADA_370_XP_SDRAM_WINS_BASE (ARMADA_370_XP_REGS_PHYS_BASE + 0x20180) -#define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20 - #ifdef CONFIG_SMP #include <linux/cpumask.h> diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c index 8278960066c..32fcf69f420 100644 --- a/arch/arm/mach-mvebu/coherency.c +++ b/arch/arm/mach-mvebu/coherency.c @@ -25,16 +25,11 @@ #include <linux/dma-mapping.h> #include <linux/platform_device.h> #include <asm/smp_plat.h> +#include <asm/cacheflush.h> #include "armada-370-xp.h" -/* - * Some functions in this file are called very early during SMP - * initialization. At that time the device tree framework is not yet - * ready, and it is not possible to get the register address to - * ioremap it. That's why the pointer below is given with an initial - * value matching its virtual mapping - */ -static void __iomem *coherency_base = ARMADA_370_XP_REGS_VIRT_BASE + 0x20200; +unsigned long __cpuinitdata coherency_phys_base; +static void __iomem *coherency_base; static void __iomem *coherency_cpu_base; /* Coherency fabric registers */ @@ -47,18 +42,6 @@ static struct of_device_id of_coherency_table[] = { { /* end of list */ }, }; -#ifdef CONFIG_SMP -int coherency_get_cpu_count(void) -{ - int reg, cnt; - - reg = readl(coherency_base + COHERENCY_FABRIC_CFG_OFFSET); - cnt = (reg & 0xF) + 1; - - return cnt; -} -#endif - /* Function defined in coherency_ll.S */ int ll_set_cpu_coherent(void __iomem *base_addr, unsigned int hw_cpu_id); @@ -143,13 +126,30 @@ int __init coherency_init(void) np = of_find_matching_node(NULL, of_coherency_table); if (np) { + struct resource res; pr_info("Initializing Coherency fabric\n"); + of_address_to_resource(np, 0, &res); + coherency_phys_base = res.start; + /* + * Ensure secondary CPUs will see the updated value, + * which they read before they join the coherency + * fabric, and therefore before they are coherent with + * the boot CPU cache. + */ + sync_cache_w(&coherency_phys_base); coherency_base = of_iomap(np, 0); coherency_cpu_base = of_iomap(np, 1); set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); - bus_register_notifier(&platform_bus_type, - &mvebu_hwcc_platform_nb); } return 0; } + +static int __init coherency_late_init(void) +{ + bus_register_notifier(&platform_bus_type, + &mvebu_hwcc_platform_nb); + return 0; +} + +postcore_initcall(coherency_late_init); diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h index 2f428137f6f..df33ad8a6c0 100644 --- a/arch/arm/mach-mvebu/coherency.h +++ b/arch/arm/mach-mvebu/coherency.h @@ -14,10 +14,6 @@ #ifndef __MACH_370_XP_COHERENCY_H #define __MACH_370_XP_COHERENCY_H -#ifdef CONFIG_SMP -int coherency_get_cpu_count(void); -#endif - int set_cpu_coherent(int cpu_id, int smp_group_id); int coherency_init(void); diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S index 53e8391192c..5476669ba90 100644 --- a/arch/arm/mach-mvebu/coherency_ll.S +++ b/arch/arm/mach-mvebu/coherency_ll.S @@ -32,15 +32,21 @@ ENTRY(ll_set_cpu_coherent) /* Add CPU to SMP group - Atomic */ add r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET - ldr r2, [r3] +1: + ldrex r2, [r3] orr r2, r2, r1 - str r2, [r3] + strex r0, r2, [r3] + cmp r0, #0 + bne 1b /* Enable coherency on CPU - Atomic */ - add r3, r0, #ARMADA_XP_CFB_CFG_REG_OFFSET - ldr r2, [r3] + add r3, r3, #ARMADA_XP_CFB_CFG_REG_OFFSET +1: + ldrex r2, [r3] orr r2, r2, r1 - str r2, [r3] + strex r0, r2, [r3] + cmp r0, #0 + bne 1b dsb diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h index aa27bc2ffb6..98defd5e92c 100644 --- a/arch/arm/mach-mvebu/common.h +++ b/arch/arm/mach-mvebu/common.h @@ -15,6 +15,8 @@ #ifndef __ARCH_MVEBU_COMMON_H #define __ARCH_MVEBU_COMMON_H +#define ARMADA_XP_MAX_CPUS 4 + void mvebu_restart(char mode, const char *cmd); void armada_370_xp_init_irq(void); diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S index a06e0ede8c0..7147300c8af 100644 --- a/arch/arm/mach-mvebu/headsmp.S +++ b/arch/arm/mach-mvebu/headsmp.S @@ -21,12 +21,6 @@ #include <linux/linkage.h> #include <linux/init.h> -/* - * At this stage the secondary CPUs don't have acces yet to the MMU, so - * we have to provide physical addresses - */ -#define ARMADA_XP_CFB_BASE 0xD0020200 - __CPUINIT /* @@ -35,15 +29,21 @@ * startup */ ENTRY(armada_xp_secondary_startup) + /* Get coherency fabric base physical address */ + adr r0, 1f + ldr r1, [r0] + ldr r0, [r0, r1] /* Read CPU id */ mrc p15, 0, r1, c0, c0, 5 and r1, r1, #0xF /* Add CPU to coherency fabric */ - ldr r0, =ARMADA_XP_CFB_BASE - bl ll_set_cpu_coherent b secondary_startup ENDPROC(armada_xp_secondary_startup) + + .align 2 +1: + .long coherency_phys_base - . diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c index 875ea748391..93f2f3ab45f 100644 --- a/arch/arm/mach-mvebu/platsmp.c +++ b/arch/arm/mach-mvebu/platsmp.c @@ -88,8 +88,16 @@ static int __cpuinit armada_xp_boot_secondary(unsigned int cpu, static void __init armada_xp_smp_init_cpus(void) { + struct device_node *np; unsigned int i, ncores; - ncores = coherency_get_cpu_count(); + + np = of_find_node_by_name(NULL, "cpus"); + if (!np) + panic("No 'cpus' node found\n"); + + ncores = of_get_child_count(np); + if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS) + panic("Invalid number of CPUs in DT\n"); /* Limit possible CPUs to defconfig */ if (ncores > nr_cpu_ids) { diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c index 68ab858e27b..a94b3a718d1 100644 --- a/arch/arm/mach-omap1/dma.c +++ b/arch/arm/mach-omap1/dma.c @@ -345,6 +345,7 @@ static int __init omap1_system_dma_init(void) dev_err(&pdev->dev, "%s: Memory allocation failed for d->chan!\n", __func__); + ret = -ENOMEM; goto exit_release_d; } diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index f49cd51e162..1bfe9ee0331 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -149,6 +149,14 @@ config SOC_AM33XX select MULTI_IRQ_HANDLER select COMMON_CLK +config SOC_AM43XX + bool "TI AM43x" + select CPU_V7 + select MULTI_IRQ_HANDLER + select ARM_GIC + select COMMON_CLK + select MACH_OMAP_GENERIC + config OMAP_PACKAGE_ZAF bool diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 55a9d677768..ec2e128074d 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) +obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) obj-y += mcbsp.o @@ -38,6 +39,7 @@ omap-4-5-common = omap4-common.o omap-wakeupgen.o \ sleep44xx.o obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) +obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common) plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) @@ -58,6 +60,8 @@ obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o +obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o +obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o # Pin multiplexing obj-$(CONFIG_SOC_OMAP2420) += mux2420.o @@ -110,6 +114,7 @@ obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o +obj-$(CONFIG_SOC_AM43XX) += prm33xx.o cm33xx.o omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ prcm_mpu44xx.o prminst44xx.o \ vc44xx_data.o vp44xx_data.o @@ -125,8 +130,9 @@ obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common) -obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o +obj-$(CONFIG_SOC_AM43XX) += $(voltagedomain-common) obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common) +obj-$(CONFIG_SOC_OMAP5) += voltagedomains54xx_data.o # OMAP powerdomain framework powerdomain-common += powerdomain.o powerdomain-common.o @@ -140,7 +146,9 @@ obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o +obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common) obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) +obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o # PRCM clockdomain control clockdomain-common += clockdomain.o @@ -155,7 +163,9 @@ obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o +obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common) obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) +obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o # Clock framework obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o @@ -198,6 +208,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o +obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o # EMU peripherals obj-$(CONFIG_OMAP3_EMU) += emu.o diff --git a/arch/arm/mach-omap2/am33xx.h b/arch/arm/mach-omap2/am33xx.h index 43296c1af9e..5eef093e673 100644 --- a/arch/arm/mach-omap2/am33xx.h +++ b/arch/arm/mach-omap2/am33xx.h @@ -21,6 +21,7 @@ #define AM33XX_SCM_BASE 0x44E10000 #define AM33XX_CTRL_BASE AM33XX_SCM_BASE #define AM33XX_PRCM_BASE 0x44E00000 +#define AM43XX_PRCM_BASE 0x44DF0000 #define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + 0x3FC) #endif /* __ASM_ARCH_AM33XX_H */ diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 88aa6b1835c..e5fbfed69aa 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -185,3 +185,19 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)") .restart = omap44xx_restart, MACHINE_END #endif + +#ifdef CONFIG_SOC_AM43XX +static const char *am43_boards_compat[] __initdata = { + "ti,am43", + NULL, +}; + +DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)") + .map_io = am33xx_map_io, + .init_early = am43xx_init_early, + .init_irq = omap_gic_of_init, + .init_machine = omap_generic_init, + .init_time = omap3_sync32k_timer_init, + .dt_compat = am43_boards_compat, +MACHINE_END +#endif diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index 6ebc7803bc3..0346de56436 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c @@ -454,9 +454,29 @@ DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0, */ DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732); -DEFINE_CLK_GATE(clkdiv32k_ick, "clkdiv32k_ck", &clkdiv32k_ck, 0x0, - AM33XX_CM_PER_CLKDIV32K_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, - 0x0, NULL); +static struct clk clkdiv32k_ick; + +static const char *clkdiv32k_ick_parent_names[] = { + "clkdiv32k_ck", +}; + +static const struct clk_ops clkdiv32k_ick_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .init = &omap2_init_clk_clkdm, +}; + +static struct clk_hw_omap clkdiv32k_ick_hw = { + .hw = { + .clk = &clkdiv32k_ick, + }, + .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL, + .enable_bit = AM33XX_MODULEMODE_SWCTRL_SHIFT, + .clkdm_name = "clk_24mhz_clkdm", +}; + +DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops); /* "usbotg_fck" is an additional clock and not really a modulemode */ DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0, @@ -842,6 +862,33 @@ static struct clk_hw_omap wdt1_fck_hw = { DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops); +static const char *pwmss_clk_parents[] = { + "dpll_per_m2_ck", +}; + +static const struct clk_ops ehrpwm_tbclk_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, +}; + +DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm", + NULL, NULL, 0, + AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), + AM33XX_PWMSS0_TBCLKEN_SHIFT, + NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); + +DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm", + NULL, NULL, 0, + AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), + AM33XX_PWMSS1_TBCLKEN_SHIFT, + NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); + +DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm", + NULL, NULL, 0, + AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), + AM33XX_PWMSS2_TBCLKEN_SHIFT, + NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); + /* * clkdev */ @@ -922,6 +969,9 @@ static struct omap_clk am33xx_clks[] = { CLK(NULL, "clkout2_div_ck", &clkout2_div_ck), CLK(NULL, "timer_32k_ck", &clkdiv32k_ick), CLK(NULL, "timer_sys_ck", &sys_clkin_ck), + CLK("48300200.ehrpwm", "tbclk", &ehrpwm0_tbclk), + CLK("48302200.ehrpwm", "tbclk", &ehrpwm1_tbclk), + CLK("48304200.ehrpwm", "tbclk", &ehrpwm2_tbclk), }; diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c index 45cd26430d1..334b7674590 100644 --- a/arch/arm/mach-omap2/cclock3xxx_data.c +++ b/arch/arm/mach-omap2/cclock3xxx_data.c @@ -3329,11 +3329,7 @@ static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = { CLK(NULL, "cpefuse_fck", &cpefuse_fck), CLK(NULL, "ts_fck", &ts_fck), CLK(NULL, "usbtll_fck", &usbtll_fck), - CLK("usbhs_omap", "usbtll_fck", &usbtll_fck), - CLK("usbhs_tll", "usbtll_fck", &usbtll_fck), CLK(NULL, "usbtll_ick", &usbtll_ick), - CLK("usbhs_omap", "usbtll_ick", &usbtll_ick), - CLK("usbhs_tll", "usbtll_ick", &usbtll_ick), CLK("omap_hsmmc.2", "ick", &mmchs3_ick), CLK(NULL, "mmchs3_ick", &mmchs3_ick), CLK(NULL, "mmchs3_fck", &mmchs3_fck), @@ -3343,7 +3339,6 @@ static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = { CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck), CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck), CLK(NULL, "usbhost_ick", &usbhost_ick), - CLK("usbhs_omap", "usbhost_ick", &usbhost_ick), }; /* @@ -3463,12 +3458,6 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "utmi_p2_gfclk", &dummy_ck), CLK(NULL, "xclk60mhsp1_ck", &dummy_ck), CLK(NULL, "xclk60mhsp2_ck", &dummy_ck), - CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck), - CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck), - CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck), - CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck), - CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck), - CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck), CLK(NULL, "init_60m_fclk", &dummy_ck), CLK(NULL, "gpt1_fck", &gpt1_fck), CLK(NULL, "aes2_ick", &aes2_ick), diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c index 8f3bf4e5090..bbd6a3f717e 100644 --- a/arch/arm/mach-omap2/clock36xx.c +++ b/arch/arm/mach-omap2/clock36xx.c @@ -20,11 +20,12 @@ #include <linux/kernel.h> #include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/io.h> #include "clock.h" #include "clock36xx.h" - +#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) /** * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering @@ -39,29 +40,28 @@ */ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) { - struct clk_hw_omap *parent; + struct clk_divider *parent; struct clk_hw *parent_hw; - u32 dummy_v, orig_v, clksel_shift; + u32 dummy_v, orig_v; int ret; /* Clear PWRDN bit of HSDIVIDER */ ret = omap2_dflt_clk_enable(clk); parent_hw = __clk_get_hw(__clk_get_parent(clk->clk)); - parent = to_clk_hw_omap(parent_hw); + parent = to_clk_divider(parent_hw); /* Restore the dividers */ if (!ret) { - clksel_shift = __ffs(parent->clksel_mask); - orig_v = __raw_readl(parent->clksel_reg); + orig_v = __raw_readl(parent->reg); dummy_v = orig_v; /* Write any other value different from the Read value */ - dummy_v ^= (1 << clksel_shift); - __raw_writel(dummy_v, parent->clksel_reg); + dummy_v ^= (1 << parent->shift); + __raw_writel(dummy_v, parent->reg); /* Write the original divider */ - __raw_writel(orig_v, parent->clksel_reg); + __raw_writel(orig_v, parent->reg); } return ret; diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 2da37656a69..daeecf1b89f 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -216,6 +216,7 @@ extern void __init omap243x_clockdomains_init(void); extern void __init omap3xxx_clockdomains_init(void); extern void __init am33xx_clockdomains_init(void); extern void __init omap44xx_clockdomains_init(void); +extern void __init omap54xx_clockdomains_init(void); extern void clkdm_add_autodeps(struct clockdomain *clkdm); extern void clkdm_del_autodeps(struct clockdomain *clkdm); diff --git a/arch/arm/mach-omap2/clockdomains54xx_data.c b/arch/arm/mach-omap2/clockdomains54xx_data.c new file mode 100644 index 00000000000..1a3c69d2e14 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomains54xx_data.c @@ -0,0 +1,464 @@ +/* + * OMAP54XX Clock domains framework + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Abhijit Pagare (abhijitpagare@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * Paul Walmsley (paul@pwsan.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/io.h> + +#include "clockdomain.h" +#include "cm1_54xx.h" +#include "cm2_54xx.h" + +#include "cm-regbits-54xx.h" +#include "prm54xx.h" +#include "prcm44xx.h" +#include "prcm_mpu54xx.h" + +/* Static Dependencies for OMAP4 Clock Domains */ + +static struct clkdm_dep c2c_wkup_sleep_deps[] = { + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3init_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { .clkdm_name = "l3main2_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep cam_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep dma_wkup_sleep_deps[] = { + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "dss_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "ipu_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3init_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { .clkdm_name = "l4sec_clkdm" }, + { .clkdm_name = "wkupaon_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep dsp_wkup_sleep_deps[] = { + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3init_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { .clkdm_name = "l3main2_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { .clkdm_name = "wkupaon_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep dss_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3main2_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep gpu_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep ipu_wkup_sleep_deps[] = { + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "dsp_clkdm" }, + { .clkdm_name = "dss_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "gpu_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3init_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { .clkdm_name = "l3main2_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { .clkdm_name = "l4sec_clkdm" }, + { .clkdm_name = "wkupaon_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep iva_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep l3init_wkup_sleep_deps[] = { + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { .clkdm_name = "l4sec_clkdm" }, + { .clkdm_name = "wkupaon_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep l4sec_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep mipiext_wkup_sleep_deps[] = { + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3init_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { .clkdm_name = "l3main2_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep mpu_wkup_sleep_deps[] = { + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "dsp_clkdm" }, + { .clkdm_name = "dss_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "gpu_clkdm" }, + { .clkdm_name = "ipu_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3init_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { .clkdm_name = "l3main2_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { .clkdm_name = "l4sec_clkdm" }, + { .clkdm_name = "wkupaon_clkdm" }, + { NULL }, +}; + +static struct clockdomain l4sec_54xx_clkdm = { + .name = "l4sec_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS, + .dep_bit = OMAP54XX_L4SEC_STATDEP_SHIFT, + .wkdep_srcs = l4sec_wkup_sleep_deps, + .sleepdep_srcs = l4sec_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain iva_54xx_clkdm = { + .name = "iva_clkdm", + .pwrdm = { .name = "iva_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_IVA_INST, + .clkdm_offs = OMAP54XX_CM_CORE_IVA_IVA_CDOFFS, + .dep_bit = OMAP54XX_IVA_STATDEP_SHIFT, + .wkdep_srcs = iva_wkup_sleep_deps, + .sleepdep_srcs = iva_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain mipiext_54xx_clkdm = { + .name = "mipiext_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS, + .wkdep_srcs = mipiext_wkup_sleep_deps, + .sleepdep_srcs = mipiext_wkup_sleep_deps, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain l3main2_54xx_clkdm = { + .name = "l3main2_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS, + .dep_bit = OMAP54XX_L3MAIN2_STATDEP_SHIFT, + .flags = CLKDM_CAN_HWSUP, +}; + +static struct clockdomain l3main1_54xx_clkdm = { + .name = "l3main1_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS, + .dep_bit = OMAP54XX_L3MAIN1_STATDEP_SHIFT, + .flags = CLKDM_CAN_HWSUP, +}; + +static struct clockdomain custefuse_54xx_clkdm = { + .name = "custefuse_clkdm", + .pwrdm = { .name = "custefuse_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CUSTEFUSE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain ipu_54xx_clkdm = { + .name = "ipu_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_IPU_CDOFFS, + .dep_bit = OMAP54XX_IPU_STATDEP_SHIFT, + .wkdep_srcs = ipu_wkup_sleep_deps, + .sleepdep_srcs = ipu_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain l4cfg_54xx_clkdm = { + .name = "l4cfg_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS, + .dep_bit = OMAP54XX_L4CFG_STATDEP_SHIFT, + .flags = CLKDM_CAN_HWSUP, +}; + +static struct clockdomain abe_54xx_clkdm = { + .name = "abe_clkdm", + .pwrdm = { .name = "abe_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_AON_ABE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS, + .dep_bit = OMAP54XX_ABE_STATDEP_SHIFT, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain dss_54xx_clkdm = { + .name = "dss_clkdm", + .pwrdm = { .name = "dss_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_DSS_INST, + .clkdm_offs = OMAP54XX_CM_CORE_DSS_DSS_CDOFFS, + .dep_bit = OMAP54XX_DSS_STATDEP_SHIFT, + .wkdep_srcs = dss_wkup_sleep_deps, + .sleepdep_srcs = dss_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain dsp_54xx_clkdm = { + .name = "dsp_clkdm", + .pwrdm = { .name = "dsp_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_AON_DSP_INST, + .clkdm_offs = OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS, + .dep_bit = OMAP54XX_DSP_STATDEP_SHIFT, + .wkdep_srcs = dsp_wkup_sleep_deps, + .sleepdep_srcs = dsp_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain c2c_54xx_clkdm = { + .name = "c2c_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_C2C_CDOFFS, + .wkdep_srcs = c2c_wkup_sleep_deps, + .sleepdep_srcs = c2c_wkup_sleep_deps, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain l4per_54xx_clkdm = { + .name = "l4per_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS, + .dep_bit = OMAP54XX_L4PER_STATDEP_SHIFT, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain gpu_54xx_clkdm = { + .name = "gpu_clkdm", + .pwrdm = { .name = "gpu_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_GPU_INST, + .clkdm_offs = OMAP54XX_CM_CORE_GPU_GPU_CDOFFS, + .dep_bit = OMAP54XX_GPU_STATDEP_SHIFT, + .wkdep_srcs = gpu_wkup_sleep_deps, + .sleepdep_srcs = gpu_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain wkupaon_54xx_clkdm = { + .name = "wkupaon_clkdm", + .pwrdm = { .name = "wkupaon_pwrdm" }, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .cm_inst = OMAP54XX_PRM_WKUPAON_CM_INST, + .clkdm_offs = OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS, + .dep_bit = OMAP54XX_WKUPAON_STATDEP_SHIFT, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain mpu0_54xx_clkdm = { + .name = "mpu0_clkdm", + .pwrdm = { .name = "cpu0_pwrdm" }, + .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, + .cm_inst = OMAP54XX_PRCM_MPU_CM_C0_INST, + .clkdm_offs = OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain mpu1_54xx_clkdm = { + .name = "mpu1_clkdm", + .pwrdm = { .name = "cpu1_pwrdm" }, + .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, + .cm_inst = OMAP54XX_PRCM_MPU_CM_C1_INST, + .clkdm_offs = OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain coreaon_54xx_clkdm = { + .name = "coreaon_clkdm", + .pwrdm = { .name = "coreaon_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_COREAON_INST, + .clkdm_offs = OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain mpu_54xx_clkdm = { + .name = "mpu_clkdm", + .pwrdm = { .name = "mpu_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_AON_MPU_INST, + .clkdm_offs = OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS, + .wkdep_srcs = mpu_wkup_sleep_deps, + .sleepdep_srcs = mpu_wkup_sleep_deps, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain l3init_54xx_clkdm = { + .name = "l3init_clkdm", + .pwrdm = { .name = "l3init_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_L3INIT_INST, + .clkdm_offs = OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS, + .dep_bit = OMAP54XX_L3INIT_STATDEP_SHIFT, + .wkdep_srcs = l3init_wkup_sleep_deps, + .sleepdep_srcs = l3init_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain dma_54xx_clkdm = { + .name = "dma_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_DMA_CDOFFS, + .wkdep_srcs = dma_wkup_sleep_deps, + .sleepdep_srcs = dma_wkup_sleep_deps, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain l3instr_54xx_clkdm = { + .name = "l3instr_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS, +}; + +static struct clockdomain emif_54xx_clkdm = { + .name = "emif_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS, + .dep_bit = OMAP54XX_EMIF_STATDEP_SHIFT, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain emu_54xx_clkdm = { + .name = "emu_clkdm", + .pwrdm = { .name = "emu_pwrdm" }, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .cm_inst = OMAP54XX_PRM_EMU_CM_INST, + .clkdm_offs = OMAP54XX_PRM_EMU_CM_EMU_CDOFFS, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain cam_54xx_clkdm = { + .name = "cam_clkdm", + .pwrdm = { .name = "cam_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CAM_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CAM_CAM_CDOFFS, + .wkdep_srcs = cam_wkup_sleep_deps, + .sleepdep_srcs = cam_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +/* As clockdomains are added or removed above, this list must also be changed */ +static struct clockdomain *clockdomains_omap54xx[] __initdata = { + &l4sec_54xx_clkdm, + &iva_54xx_clkdm, + &mipiext_54xx_clkdm, + &l3main2_54xx_clkdm, + &l3main1_54xx_clkdm, + &custefuse_54xx_clkdm, + &ipu_54xx_clkdm, + &l4cfg_54xx_clkdm, + &abe_54xx_clkdm, + &dss_54xx_clkdm, + &dsp_54xx_clkdm, + &c2c_54xx_clkdm, + &l4per_54xx_clkdm, + &gpu_54xx_clkdm, + &wkupaon_54xx_clkdm, + &mpu0_54xx_clkdm, + &mpu1_54xx_clkdm, + &coreaon_54xx_clkdm, + &mpu_54xx_clkdm, + &l3init_54xx_clkdm, + &dma_54xx_clkdm, + &l3instr_54xx_clkdm, + &emif_54xx_clkdm, + &emu_54xx_clkdm, + &cam_54xx_clkdm, + NULL +}; + +void __init omap54xx_clockdomains_init(void) +{ + clkdm_register_platform_funcs(&omap4_clkdm_operations); + clkdm_register_clkdms(clockdomains_omap54xx); + clkdm_complete_init(); +} diff --git a/arch/arm/mach-omap2/cm-regbits-54xx.h b/arch/arm/mach-omap2/cm-regbits-54xx.h new file mode 100644 index 00000000000..e83b8e352b6 --- /dev/null +++ b/arch/arm/mach-omap2/cm-regbits-54xx.h @@ -0,0 +1,1737 @@ +/* + * OMAP54xx Clock Management register bits + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H +#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H + +/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_MPU_DYNAMICDEP */ +#define OMAP54XX_ABE_DYNDEP_SHIFT 3 +#define OMAP54XX_ABE_DYNDEP_WIDTH 0x1 +#define OMAP54XX_ABE_DYNDEP_MASK (1 << 3) + +/* + * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, + * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP + */ +#define OMAP54XX_ABE_STATDEP_SHIFT 3 +#define OMAP54XX_ABE_STATDEP_WIDTH 0x1 +#define OMAP54XX_ABE_STATDEP_MASK (1 << 3) + +/* + * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_IVA, + * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO1, + * CM_AUTOIDLE_DPLL_UNIPRO2, CM_AUTOIDLE_DPLL_USB + */ +#define OMAP54XX_AUTO_DPLL_MODE_SHIFT 0 +#define OMAP54XX_AUTO_DPLL_MODE_WIDTH 0x3 +#define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0) + +/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_C2C_DYNDEP_SHIFT 18 +#define OMAP54XX_C2C_DYNDEP_WIDTH 0x1 +#define OMAP54XX_C2C_DYNDEP_MASK (1 << 18) + +/* Used by CM_MPU_STATICDEP */ +#define OMAP54XX_C2C_STATDEP_SHIFT 18 +#define OMAP54XX_C2C_STATDEP_WIDTH 0x1 +#define OMAP54XX_C2C_STATDEP_MASK (1 << 18) + +/* Used by CM_IPU_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_CAM_DYNDEP_SHIFT 9 +#define OMAP54XX_CAM_DYNDEP_WIDTH 0x1 +#define OMAP54XX_CAM_DYNDEP_MASK (1 << 9) + +/* + * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP, + * CM_MPU_STATICDEP + */ +#define OMAP54XX_CAM_STATDEP_SHIFT 9 +#define OMAP54XX_CAM_STATDEP_WIDTH 0x1 +#define OMAP54XX_CAM_STATDEP_MASK (1 << 9) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 +#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_MASK (1 << 12) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_ABE_GICLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_ABE_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_ABE_GICLK_MASK (1 << 9) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_MASK (1 << 11) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) + +/* Used by CM_DSS_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_SHIFT 13 +#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_MASK (1 << 13) + +/* Used by CM_C2C_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_MASK (1 << 9) + +/* Used by CM_C2C_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_C2C_GICLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_C2C_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_C2C_GICLK_MASK (1 << 10) + +/* Used by CM_C2C_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_MASK (1 << 8) + +/* Used by CM_CAM_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_MASK (1 << 11) + +/* Used by CM_CAM_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_CAM_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_CAM_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_CAM_GCLK_MASK (1 << 8) + +/* Used by CM_CAM_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_MASK (1 << 12) + +/* Used by CM_COREAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_MASK (1 << 12) + +/* Used by CM_COREAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_SHIFT 14 +#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_MASK (1 << 14) + +/* Used by CM_COREAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_MASK (1 << 8) + +/* Used by CM_CAM_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_MASK (1 << 9) + +/* Used by CM_CUSTEFUSE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_MASK (1 << 8) + +/* Used by CM_CUSTEFUSE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_MASK (1 << 9) + +/* Used by CM_EMIF_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_DLL_GCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_DLL_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_DLL_GCLK_MASK (1 << 9) + +/* Used by CM_DMA_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_MASK (1 << 8) + +/* Used by CM_DSP_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_DSP_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_DSP_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_DSP_GCLK_MASK (1 << 8) + +/* Used by CM_DSS_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_MASK (1 << 9) + +/* Used by CM_DSS_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_MASK (1 << 8) + +/* Used by CM_DSS_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_MASK (1 << 10) + +/* Used by CM_EMIF_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_MASK (1 << 8) + +/* Used by CM_EMIF_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_MASK (1 << 11) + +/* Used by CM_EMIF_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_MASK (1 << 10) + +/* Used by CM_EMU_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_MASK (1 << 8) + +/* Used by CM_CAM_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_MASK (1 << 10) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) + +/* Used by CM_GPU_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_MASK (1 << 9) + +/* Used by CM_GPU_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_MASK (1 << 10) + +/* Used by CM_GPU_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_MASK (1 << 8) + +/* Used by CM_DSS_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_MASK (1 << 12) + +/* Used by CM_DSS_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_MASK (1 << 11) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 +#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 +#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 +#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 +#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_SHIFT 6 +#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_MASK (1 << 6) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_SHIFT 7 +#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_MASK (1 << 7) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_SHIFT 16 +#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_MASK (1 << 16) + +/* Used by CM_IPU_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_IPU_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_IPU_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_IPU_GCLK_MASK (1 << 8) + +/* Used by CM_IVA_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_IVA_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_IVA_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_IVA_GCLK_MASK (1 << 8) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_MASK (1 << 12) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_SHIFT 28 +#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_MASK (1 << 28) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_SHIFT 29 +#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_MASK (1 << 29) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_MASK (1 << 8) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_MASK (1 << 9) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_MASK (1 << 11) + +/* Used by CM_L3INSTR_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_MASK (1 << 9) + +/* Used by CM_L3INSTR_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_MASK (1 << 8) + +/* Used by CM_L3INSTR_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_MASK (1 << 10) + +/* Used by CM_L3MAIN1_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_MASK (1 << 8) + +/* Used by CM_L3MAIN2_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_MASK (1 << 8) + +/* Used by CM_L4CFG_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_MASK (1 << 8) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_MASK (1 << 8) + +/* Used by CM_L4SEC_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_MASK (1 << 8) + +/* Used by CM_L4SEC_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_MASK (1 << 9) + +/* Used by CM_MIPIEXT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_MASK (1 << 8) + +/* Used by CM_MIPIEXT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_MASK (1 << 11) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_SHIFT 2 +#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_MASK (1 << 2) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_SHIFT 17 +#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_MASK (1 << 17) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_SHIFT 18 +#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_MASK (1 << 18) + +/* Used by CM_MPU_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_MPU_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_MPU_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_MPU_GCLK_MASK (1 << 8) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PAD_CLKS_SHIFT 14 +#define OMAP54XX_CLKACTIVITY_PAD_CLKS_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PAD_CLKS_MASK (1 << 14) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_SHIFT 15 +#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_MASK (1 << 15) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_SHIFT 3 +#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_MASK (1 << 3) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_SHIFT 4 +#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_MASK (1 << 4) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_SHIFT 15 +#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_MASK (1 << 15) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 +#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 +#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 +#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_SHIFT 19 +#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_MASK (1 << 19) + +/* Used by CM_COREAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_MASK (1 << 11) + +/* Used by CM_COREAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_MASK (1 << 10) + +/* Used by CM_COREAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_MASK (1 << 9) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SYS_CLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_SYS_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SYS_CLK_MASK (1 << 8) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_SHIFT 15 +#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_MASK (1 << 15) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_SHIFT 14 +#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_MASK (1 << 14) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_MASK (1 << 9) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_MASK (1 << 10) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_MASK (1 << 11) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_MASK (1 << 12) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_SHIFT 13 +#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_MASK (1 << 13) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_SHIFT 14 +#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_MASK (1 << 14) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 +#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 +#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 +#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) + +/* Used by CM_MIPIEXT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_MASK (1 << 10) + +/* Used by CM_MIPIEXT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_SHIFT 13 +#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_MASK (1 << 13) + +/* Used by CM_MIPIEXT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_MASK (1 << 12) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_MASK (1 << 10) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_SHIFT 13 +#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_MASK (1 << 13) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_SHIFT 5 +#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_MASK (1 << 5) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 +#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 +#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_SHIFT 31 +#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_MASK (1 << 31) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 +#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 +#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_MASK (1 << 11) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_MASK (1 << 12) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_SHIFT 13 +#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_MASK (1 << 13) + +/* Used by CM_COREAON_IO_SRCOMP_CLKCTRL, CM_WKUPAON_IO_SRCOMP_CLKCTRL */ +#define OMAP54XX_CLKEN_SRCOMP_FCLK_SHIFT 8 +#define OMAP54XX_CLKEN_SRCOMP_FCLK_WIDTH 0x1 +#define OMAP54XX_CLKEN_SRCOMP_FCLK_MASK (1 << 8) + +/* + * Used by CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, + * CM_ABE_TIMER8_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, + * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, + * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL + */ +#define OMAP54XX_CLKSEL_SHIFT 24 +#define OMAP54XX_CLKSEL_WIDTH 0x1 +#define OMAP54XX_CLKSEL_MASK (1 << 24) + +/* + * Renamed from CLKSEL Used by CM_CLKSEL_ABE_DSS_SYS, CM_CLKSEL_ABE_PLL_REF, + * CM_CLKSEL_USB_60MHZ, CM_CLKSEL_WKUPAON + */ +#define OMAP54XX_CLKSEL_0_0_SHIFT 0 +#define OMAP54XX_CLKSEL_0_0_WIDTH 0x1 +#define OMAP54XX_CLKSEL_0_0_MASK (1 << 0) + +/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ +#define OMAP54XX_CLKSEL_0_1_SHIFT 0 +#define OMAP54XX_CLKSEL_0_1_WIDTH 0x2 +#define OMAP54XX_CLKSEL_0_1_MASK (0x3 << 0) + +/* Renamed from CLKSEL Used by CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL */ +#define OMAP54XX_CLKSEL_24_25_SHIFT 24 +#define OMAP54XX_CLKSEL_24_25_WIDTH 0x2 +#define OMAP54XX_CLKSEL_24_25_MASK (0x3 << 24) + +/* Used by CM_MPU_MPU_CLKCTRL */ +#define OMAP54XX_CLKSEL_ABE_DIV_MODE_SHIFT 26 +#define OMAP54XX_CLKSEL_ABE_DIV_MODE_WIDTH 0x1 +#define OMAP54XX_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) + +/* Used by CM_ABE_AESS_CLKCTRL */ +#define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24 +#define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1 +#define OMAP54XX_CLKSEL_AESS_FCLK_MASK (1 << 24) + +/* Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL */ +#define OMAP54XX_CLKSEL_DIV_SHIFT 25 +#define OMAP54XX_CLKSEL_DIV_WIDTH 0x1 +#define OMAP54XX_CLKSEL_DIV_MASK (1 << 25) + +/* Used by CM_MPU_MPU_CLKCTRL */ +#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_SHIFT 24 +#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_WIDTH 0x2 +#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_MASK (0x3 << 24) + +/* Used by CM_CAM_FDIF_CLKCTRL */ +#define OMAP54XX_CLKSEL_FCLK_SHIFT 24 +#define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1 +#define OMAP54XX_CLKSEL_FCLK_MASK (1 << 24) + +/* Used by CM_GPU_GPU_CLKCTRL */ +#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24 +#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) + +/* Used by CM_GPU_GPU_CLKCTRL */ +#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25 +#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) + +/* Used by CM_GPU_GPU_CLKCTRL */ +#define OMAP54XX_CLKSEL_GPU_SYS_CLK_SHIFT 26 +#define OMAP54XX_CLKSEL_GPU_SYS_CLK_WIDTH 0x1 +#define OMAP54XX_CLKSEL_GPU_SYS_CLK_MASK (1 << 26) + +/* + * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, + * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL + */ +#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26 +#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2 +#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_MASK (0x3 << 26) + +/* Used by CM_CLKSEL_CORE */ +#define OMAP54XX_CLKSEL_L3_SHIFT 4 +#define OMAP54XX_CLKSEL_L3_WIDTH 0x1 +#define OMAP54XX_CLKSEL_L3_MASK (1 << 4) + +/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ +#define OMAP54XX_CLKSEL_L3_1_1_SHIFT 1 +#define OMAP54XX_CLKSEL_L3_1_1_WIDTH 0x1 +#define OMAP54XX_CLKSEL_L3_1_1_MASK (1 << 1) + +/* Used by CM_CLKSEL_CORE */ +#define OMAP54XX_CLKSEL_L4_SHIFT 8 +#define OMAP54XX_CLKSEL_L4_WIDTH 0x1 +#define OMAP54XX_CLKSEL_L4_MASK (1 << 8) + +/* Used by CM_EMIF_EMIF1_CLKCTRL */ +#define OMAP54XX_CLKSEL_LL_SHIFT 24 +#define OMAP54XX_CLKSEL_LL_WIDTH 0x1 +#define OMAP54XX_CLKSEL_LL_MASK (1 << 24) + +/* Used by CM_CLKSEL_ABE */ +#define OMAP54XX_CLKSEL_OPP_SHIFT 0 +#define OMAP54XX_CLKSEL_OPP_WIDTH 0x2 +#define OMAP54XX_CLKSEL_OPP_MASK (0x3 << 0) + +/* Renamed from CLKSEL_OPP Used by CM_L3INIT_UNIPRO2_CLKCTRL */ +#define OMAP54XX_CLKSEL_OPP_24_24_SHIFT 24 +#define OMAP54XX_CLKSEL_OPP_24_24_WIDTH 0x1 +#define OMAP54XX_CLKSEL_OPP_24_24_MASK (1 << 24) + +/* + * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, + * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL + */ +#define OMAP54XX_CLKSEL_SOURCE_SHIFT 24 +#define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2 +#define OMAP54XX_CLKSEL_SOURCE_MASK (0x3 << 24) + +/* + * Renamed from CLKSEL_SOURCE Used by CM_L3INIT_MMC1_CLKCTRL, + * CM_L3INIT_MMC2_CLKCTRL + */ +#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24 +#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1 +#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_MASK (1 << 24) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24 +#define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1 +#define OMAP54XX_CLKSEL_UTMI_P1_MASK (1 << 24) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25 +#define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1 +#define OMAP54XX_CLKSEL_UTMI_P2_MASK (1 << 25) + +/* + * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER, + * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER, + * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE, + * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE, + * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE, CM_DIV_M2_DPLL_ABE, + * CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, + * CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, CM_DIV_M2_DPLL_USB, + * CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER + */ +#define OMAP54XX_CLKST_SHIFT 9 +#define OMAP54XX_CLKST_WIDTH 0x1 +#define OMAP54XX_CLKST_MASK (1 << 9) + +/* + * Used by CM_ABE_CLKSTCTRL, CM_C2C_CLKSTCTRL, CM_CAM_CLKSTCTRL, + * CM_COREAON_CLKSTCTRL, CM_CUSTEFUSE_CLKSTCTRL, CM_DMA_CLKSTCTRL, + * CM_DSP_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_EMIF_CLKSTCTRL, CM_EMU_CLKSTCTRL, + * CM_GPU_CLKSTCTRL, CM_IPU_CLKSTCTRL, CM_IVA_CLKSTCTRL, CM_L3INIT_CLKSTCTRL, + * CM_L3INSTR_CLKSTCTRL, CM_L3MAIN1_CLKSTCTRL, CM_L3MAIN2_CLKSTCTRL, + * CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL, + * CM_MIPIEXT_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_WKUPAON_CLKSTCTRL + */ +#define OMAP54XX_CLKTRCTRL_SHIFT 0 +#define OMAP54XX_CLKTRCTRL_WIDTH 0x2 +#define OMAP54XX_CLKTRCTRL_MASK (0x3 << 0) + +/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER */ +#define OMAP54XX_CLKX2ST_SHIFT 11 +#define OMAP54XX_CLKX2ST_WIDTH 0x1 +#define OMAP54XX_CLKX2ST_MASK (1 << 11) + +/* Used by CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_COREAON_DYNDEP_SHIFT 16 +#define OMAP54XX_COREAON_DYNDEP_WIDTH 0x1 +#define OMAP54XX_COREAON_DYNDEP_MASK (1 << 16) + +/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_COREAON_STATDEP_SHIFT 16 +#define OMAP54XX_COREAON_STATDEP_WIDTH 0x1 +#define OMAP54XX_COREAON_STATDEP_MASK (1 << 16) + +/* Used by CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_CUSTEFUSE_DYNDEP_SHIFT 17 +#define OMAP54XX_CUSTEFUSE_DYNDEP_WIDTH 0x1 +#define OMAP54XX_CUSTEFUSE_DYNDEP_MASK (1 << 17) + +/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_CUSTEFUSE_STATDEP_SHIFT 17 +#define OMAP54XX_CUSTEFUSE_STATDEP_WIDTH 0x1 +#define OMAP54XX_CUSTEFUSE_STATDEP_MASK (1 << 17) + +/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ +#define OMAP54XX_CUSTOM_SHIFT 6 +#define OMAP54XX_CUSTOM_WIDTH 0x2 +#define OMAP54XX_CUSTOM_MASK (0x3 << 6) + +/* + * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, + * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1, + * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB + */ +#define OMAP54XX_DCC_EN_SHIFT 22 +#define OMAP54XX_DCC_EN_WIDTH 0x1 +#define OMAP54XX_DCC_EN_MASK (1 << 22) + +/* + * Used by CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS, + * CM_CORE_AON_DEBUG_DSS_FD_TRANS, CM_CORE_AON_DEBUG_EMIF_FD_TRANS, + * CM_CORE_AON_DEBUG_L4SEC_FD_TRANS + */ +#define OMAP54XX_CM_DEBUG_OUT_SHIFT 0 +#define OMAP54XX_CM_DEBUG_OUT_WIDTH 0xd +#define OMAP54XX_CM_DEBUG_OUT_MASK (0x1fff << 0) + +/* + * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS, + * CM_CORE_AON_DEBUG_L3INIT_FD_TRANS, CM_CORE_AON_DEBUG_L4PER_FD_TRANS + */ +#define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20 +#define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0) + +/* + * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_C2C_FD_TRANS, + * CM_CORE_AON_DEBUG_COREAON_FD_TRANS, CM_CORE_AON_DEBUG_L4CFG_FD_TRANS + */ +#define OMAP54XX_DEBUG_OUT_0_8_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_8_WIDTH 0x9 +#define OMAP54XX_DEBUG_OUT_0_8_MASK (0x1ff << 0) + +/* + * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS, + * CM_CORE_AON_DEBUG_DMA_FD_TRANS, CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS + */ +#define OMAP54XX_DEBUG_OUT_0_4_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_4_WIDTH 0x5 +#define OMAP54XX_DEBUG_OUT_0_4_MASK (0x1f << 0) + +/* + * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_DSP_FD_TRANS, + * CM_CORE_AON_DEBUG_IPU_FD_TRANS, CM_CORE_AON_DEBUG_MPU_FD_TRANS + */ +#define OMAP54XX_DEBUG_OUT_0_5_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_5_WIDTH 0x6 +#define OMAP54XX_DEBUG_OUT_0_5_MASK (0x3f << 0) + +/* + * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CAM_FD_TRANS, + * CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS + */ +#define OMAP54XX_DEBUG_OUT_0_10_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_10_WIDTH 0xb +#define OMAP54XX_DEBUG_OUT_0_10_MASK (0x7ff << 0) + +/* + * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_IVA_FD_TRANS, + * CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS + */ +#define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7 +#define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0) + +/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS2 */ +#define OMAP54XX_DEBUG_OUT_0_19_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_19_WIDTH 0x14 +#define OMAP54XX_DEBUG_OUT_0_19_MASK (0xfffff << 0) + +/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_GPU_FD_TRANS */ +#define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa +#define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0) + +/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2 */ +#define OMAP54XX_DEBUG_OUT_0_26_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_26_WIDTH 0x1b +#define OMAP54XX_DEBUG_OUT_0_26_MASK (0x7ffffff << 0) + +/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS */ +#define OMAP54XX_DEBUG_OUT_0_13_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_13_WIDTH 0xe +#define OMAP54XX_DEBUG_OUT_0_13_MASK (0x3fff << 0) + +/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L4PER_FD_TRANS2 */ +#define OMAP54XX_DEBUG_OUT_0_21_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_21_WIDTH 0x16 +#define OMAP54XX_DEBUG_OUT_0_21_MASK (0x3fffff << 0) + +/* + * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, + * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU, + * CM_SSC_DELTAMSTEP_DPLL_PER + */ +#define OMAP54XX_DELTAMSTEP_SHIFT 0 +#define OMAP54XX_DELTAMSTEP_WIDTH 0x14 +#define OMAP54XX_DELTAMSTEP_MASK (0xfffff << 0) + +/* + * Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_UNIPRO1, + * CM_SSC_DELTAMSTEP_DPLL_UNIPRO2, CM_SSC_DELTAMSTEP_DPLL_USB + */ +#define OMAP54XX_DELTAMSTEP_0_20_SHIFT 0 +#define OMAP54XX_DELTAMSTEP_0_20_WIDTH 0x15 +#define OMAP54XX_DELTAMSTEP_0_20_MASK (0x1fffff << 0) + +/* + * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER, + * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER, + * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE, + * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE, + * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE + */ +#define OMAP54XX_DIVHS_SHIFT 0 +#define OMAP54XX_DIVHS_WIDTH 0x6 +#define OMAP54XX_DIVHS_MASK (0x3f << 0) + +/* + * Renamed from DIVHS Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, + * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M3_DPLL_ABE, + * CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER + */ +#define OMAP54XX_DIVHS_0_4_SHIFT 0 +#define OMAP54XX_DIVHS_0_4_WIDTH 0x5 +#define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0) + +/* + * Renamed from DIVHS Used by CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, + * CM_DIV_M2_DPLL_USB + */ +#define OMAP54XX_DIVHS_0_6_SHIFT 0 +#define OMAP54XX_DIVHS_0_6_WIDTH 0x7 +#define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0) + +/* Used by CM_DLL_CTRL */ +#define OMAP54XX_DLL_OVERRIDE_SHIFT 0 +#define OMAP54XX_DLL_OVERRIDE_WIDTH 0x1 +#define OMAP54XX_DLL_OVERRIDE_MASK (1 << 0) + +/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */ +#define OMAP54XX_DLL_OVERRIDE_2_2_SHIFT 2 +#define OMAP54XX_DLL_OVERRIDE_2_2_WIDTH 0x1 +#define OMAP54XX_DLL_OVERRIDE_2_2_MASK (1 << 2) + +/* Used by CM_SHADOW_FREQ_CONFIG1 */ +#define OMAP54XX_DLL_RESET_SHIFT 3 +#define OMAP54XX_DLL_RESET_WIDTH 0x1 +#define OMAP54XX_DLL_RESET_MASK (1 << 3) + +/* + * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, + * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1, + * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB + */ +#define OMAP54XX_DPLL_BYP_CLKSEL_SHIFT 23 +#define OMAP54XX_DPLL_BYP_CLKSEL_WIDTH 0x1 +#define OMAP54XX_DPLL_BYP_CLKSEL_MASK (1 << 23) + +/* Used by CM_CLKSEL_DPLL_CORE */ +#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 +#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1 +#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) + +/* Used by CM_SHADOW_FREQ_CONFIG1 */ +#define OMAP54XX_DPLL_CORE_DPLL_EN_SHIFT 8 +#define OMAP54XX_DPLL_CORE_DPLL_EN_WIDTH 0x3 +#define OMAP54XX_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) + +/* Used by CM_SHADOW_FREQ_CONFIG2 */ +#define OMAP54XX_DPLL_CORE_H12_DIV_SHIFT 2 +#define OMAP54XX_DPLL_CORE_H12_DIV_WIDTH 0x6 +#define OMAP54XX_DPLL_CORE_H12_DIV_MASK (0x3f << 2) + +/* Used by CM_SHADOW_FREQ_CONFIG1 */ +#define OMAP54XX_DPLL_CORE_M2_DIV_SHIFT 11 +#define OMAP54XX_DPLL_CORE_M2_DIV_WIDTH 0x5 +#define OMAP54XX_DPLL_CORE_M2_DIV_MASK (0x1f << 11) + +/* + * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, + * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER + */ +#define OMAP54XX_DPLL_DIV_SHIFT 0 +#define OMAP54XX_DPLL_DIV_WIDTH 0x7 +#define OMAP54XX_DPLL_DIV_MASK (0x7f << 0) + +/* + * Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_UNIPRO1, + * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB + */ +#define OMAP54XX_DPLL_DIV_0_7_SHIFT 0 +#define OMAP54XX_DPLL_DIV_0_7_WIDTH 0x8 +#define OMAP54XX_DPLL_DIV_0_7_MASK (0xff << 0) + +/* + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER + */ +#define OMAP54XX_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define OMAP54XX_DPLL_DRIFTGUARD_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) + +/* + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, + * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB + */ +#define OMAP54XX_DPLL_EN_SHIFT 0 +#define OMAP54XX_DPLL_EN_WIDTH 0x3 +#define OMAP54XX_DPLL_EN_MASK (0x7 << 0) + +/* + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER + */ +#define OMAP54XX_DPLL_LPMODE_EN_SHIFT 10 +#define OMAP54XX_DPLL_LPMODE_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10) + +/* + * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, + * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER + */ +#define OMAP54XX_DPLL_MULT_SHIFT 8 +#define OMAP54XX_DPLL_MULT_WIDTH 0xb +#define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8) + +/* + * Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_UNIPRO1, + * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB + */ +#define OMAP54XX_DPLL_MULT_UNIPRO1_SHIFT 8 +#define OMAP54XX_DPLL_MULT_UNIPRO1_WIDTH 0xc +#define OMAP54XX_DPLL_MULT_UNIPRO1_MASK (0xfff << 8) + +/* + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER + */ +#define OMAP54XX_DPLL_REGM4XEN_SHIFT 11 +#define OMAP54XX_DPLL_REGM4XEN_WIDTH 0x1 +#define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11) + +/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */ +#define OMAP54XX_DPLL_SD_DIV_SHIFT 24 +#define OMAP54XX_DPLL_SD_DIV_WIDTH 0x8 +#define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24) + +/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */ +#define OMAP54XX_DPLL_SELFREQDCO_SHIFT 21 +#define OMAP54XX_DPLL_SELFREQDCO_WIDTH 0x1 +#define OMAP54XX_DPLL_SELFREQDCO_MASK (1 << 21) + +/* + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, + * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB + */ +#define OMAP54XX_DPLL_SSC_ACK_SHIFT 13 +#define OMAP54XX_DPLL_SSC_ACK_WIDTH 0x1 +#define OMAP54XX_DPLL_SSC_ACK_MASK (1 << 13) + +/* + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, + * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB + */ +#define OMAP54XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 +#define OMAP54XX_DPLL_SSC_DOWNSPREAD_WIDTH 0x1 +#define OMAP54XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) + +/* + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, + * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB + */ +#define OMAP54XX_DPLL_SSC_EN_SHIFT 12 +#define OMAP54XX_DPLL_SSC_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_SSC_EN_MASK (1 << 12) + +/* Used by CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_DSP_DYNDEP_SHIFT 1 +#define OMAP54XX_DSP_DYNDEP_WIDTH 0x1 +#define OMAP54XX_DSP_DYNDEP_MASK (1 << 1) + +/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_DSP_STATDEP_SHIFT 1 +#define OMAP54XX_DSP_STATDEP_WIDTH 0x1 +#define OMAP54XX_DSP_STATDEP_MASK (1 << 1) + +/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ +#define OMAP54XX_DSS_DYNDEP_SHIFT 8 +#define OMAP54XX_DSS_DYNDEP_WIDTH 0x1 +#define OMAP54XX_DSS_DYNDEP_MASK (1 << 8) + +/* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_DSS_STATDEP_SHIFT 8 +#define OMAP54XX_DSS_STATDEP_WIDTH 0x1 +#define OMAP54XX_DSS_STATDEP_MASK (1 << 8) + +/* + * Used by CM_C2C_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, + * CM_MIPIEXT_DYNAMICDEP, CM_MPU_DYNAMICDEP + */ +#define OMAP54XX_EMIF_DYNDEP_SHIFT 4 +#define OMAP54XX_EMIF_DYNDEP_WIDTH 0x1 +#define OMAP54XX_EMIF_DYNDEP_MASK (1 << 4) + +/* + * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, + * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, + * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, + * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP + */ +#define OMAP54XX_EMIF_STATDEP_SHIFT 4 +#define OMAP54XX_EMIF_STATDEP_WIDTH 0x1 +#define OMAP54XX_EMIF_STATDEP_MASK (1 << 4) + +/* Used by CM_SHADOW_FREQ_CONFIG1 */ +#define OMAP54XX_FREQ_UPDATE_SHIFT 0 +#define OMAP54XX_FREQ_UPDATE_WIDTH 0x1 +#define OMAP54XX_FREQ_UPDATE_MASK (1 << 0) + +/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ +#define OMAP54XX_FUNC_SHIFT 16 +#define OMAP54XX_FUNC_WIDTH 0xc +#define OMAP54XX_FUNC_MASK (0xfff << 16) + +/* Used by CM_SHADOW_FREQ_CONFIG2 */ +#define OMAP54XX_GPMC_FREQ_UPDATE_SHIFT 0 +#define OMAP54XX_GPMC_FREQ_UPDATE_WIDTH 0x1 +#define OMAP54XX_GPMC_FREQ_UPDATE_MASK (1 << 0) + +/* Used by CM_L3MAIN2_DYNAMICDEP */ +#define OMAP54XX_GPU_DYNDEP_SHIFT 10 +#define OMAP54XX_GPU_DYNDEP_WIDTH 0x1 +#define OMAP54XX_GPU_DYNDEP_MASK (1 << 10) + +/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_GPU_STATDEP_SHIFT 10 +#define OMAP54XX_GPU_STATDEP_WIDTH 0x1 +#define OMAP54XX_GPU_STATDEP_MASK (1 << 10) + +/* + * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL, + * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL, + * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL, + * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, + * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL, + * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL, + * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL, + * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL, + * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL, + * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, + * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, + * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL, + * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, + * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, + * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, + * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, + * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL, + * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL, + * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL, + * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL, + * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL, + * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, + * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL, + * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL, + * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL, + * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, + * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, + * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, + * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, + * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, + * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, + * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, + * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, + * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, + * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, + * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, + * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL, + * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, + * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, + * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, + * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, + * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL, + * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL, + * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL, + * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL, + * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL, + * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL, + * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL + */ +#define OMAP54XX_IDLEST_SHIFT 16 +#define OMAP54XX_IDLEST_WIDTH 0x2 +#define OMAP54XX_IDLEST_MASK (0x3 << 16) + +/* Used by CM_L3MAIN2_DYNAMICDEP */ +#define OMAP54XX_IPU_DYNDEP_SHIFT 0 +#define OMAP54XX_IPU_DYNDEP_WIDTH 0x1 +#define OMAP54XX_IPU_DYNDEP_MASK (1 << 0) + +/* Used by CM_DMA_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_IPU_STATDEP_SHIFT 0 +#define OMAP54XX_IPU_STATDEP_WIDTH 0x1 +#define OMAP54XX_IPU_STATDEP_MASK (1 << 0) + +/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP */ +#define OMAP54XX_IVA_DYNDEP_SHIFT 2 +#define OMAP54XX_IVA_DYNDEP_WIDTH 0x1 +#define OMAP54XX_IVA_DYNDEP_MASK (1 << 2) + +/* + * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, + * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, + * CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP + */ +#define OMAP54XX_IVA_STATDEP_SHIFT 2 +#define OMAP54XX_IVA_STATDEP_WIDTH 0x1 +#define OMAP54XX_IVA_STATDEP_MASK (1 << 2) + +/* Used by CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ +#define OMAP54XX_L3INIT_DYNDEP_SHIFT 7 +#define OMAP54XX_L3INIT_DYNDEP_WIDTH 0x1 +#define OMAP54XX_L3INIT_DYNDEP_MASK (1 << 7) + +/* + * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, + * CM_IPU_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP + */ +#define OMAP54XX_L3INIT_STATDEP_SHIFT 7 +#define OMAP54XX_L3INIT_STATDEP_WIDTH 0x1 +#define OMAP54XX_L3INIT_STATDEP_MASK (1 << 7) + +/* + * Used by CM_DSP_DYNAMICDEP, CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, + * CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP + */ +#define OMAP54XX_L3MAIN1_DYNDEP_SHIFT 5 +#define OMAP54XX_L3MAIN1_DYNDEP_WIDTH 0x1 +#define OMAP54XX_L3MAIN1_DYNDEP_MASK (1 << 5) + +/* + * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, + * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, + * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, + * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP + */ +#define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5 +#define OMAP54XX_L3MAIN1_STATDEP_WIDTH 0x1 +#define OMAP54XX_L3MAIN1_STATDEP_MASK (1 << 5) + +/* + * Used by CM_C2C_DYNAMICDEP, CM_CAM_DYNAMICDEP, CM_DMA_DYNAMICDEP, + * CM_DSS_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GPU_DYNAMICDEP, CM_IPU_DYNAMICDEP, + * CM_IVA_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, + * CM_L4CFG_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP + */ +#define OMAP54XX_L3MAIN2_DYNDEP_SHIFT 6 +#define OMAP54XX_L3MAIN2_DYNDEP_WIDTH 0x1 +#define OMAP54XX_L3MAIN2_DYNDEP_MASK (1 << 6) + +/* + * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, + * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, + * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, + * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP + */ +#define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6 +#define OMAP54XX_L3MAIN2_STATDEP_WIDTH 0x1 +#define OMAP54XX_L3MAIN2_STATDEP_MASK (1 << 6) + +/* Used by CM_L3MAIN1_DYNAMICDEP */ +#define OMAP54XX_L4CFG_DYNDEP_SHIFT 12 +#define OMAP54XX_L4CFG_DYNDEP_WIDTH 0x1 +#define OMAP54XX_L4CFG_DYNDEP_MASK (1 << 12) + +/* + * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, + * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP + */ +#define OMAP54XX_L4CFG_STATDEP_SHIFT 12 +#define OMAP54XX_L4CFG_STATDEP_WIDTH 0x1 +#define OMAP54XX_L4CFG_STATDEP_MASK (1 << 12) + +/* Used by CM_L3MAIN2_DYNAMICDEP */ +#define OMAP54XX_L4PER_DYNDEP_SHIFT 13 +#define OMAP54XX_L4PER_DYNDEP_WIDTH 0x1 +#define OMAP54XX_L4PER_DYNDEP_MASK (1 << 13) + +/* + * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, + * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, + * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP + */ +#define OMAP54XX_L4PER_STATDEP_SHIFT 13 +#define OMAP54XX_L4PER_STATDEP_WIDTH 0x1 +#define OMAP54XX_L4PER_STATDEP_MASK (1 << 13) + +/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ +#define OMAP54XX_L4SEC_DYNDEP_SHIFT 14 +#define OMAP54XX_L4SEC_DYNDEP_WIDTH 0x1 +#define OMAP54XX_L4SEC_DYNDEP_MASK (1 << 14) + +/* + * Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, + * CM_MPU_STATICDEP + */ +#define OMAP54XX_L4SEC_STATDEP_SHIFT 14 +#define OMAP54XX_L4SEC_STATDEP_WIDTH 0x1 +#define OMAP54XX_L4SEC_STATDEP_MASK (1 << 14) + +/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_MIPIEXT_DYNDEP_SHIFT 21 +#define OMAP54XX_MIPIEXT_DYNDEP_WIDTH 0x1 +#define OMAP54XX_MIPIEXT_DYNDEP_MASK (1 << 21) + +/* Used by CM_MPU_STATICDEP */ +#define OMAP54XX_MIPIEXT_STATDEP_SHIFT 21 +#define OMAP54XX_MIPIEXT_STATDEP_WIDTH 0x1 +#define OMAP54XX_MIPIEXT_STATDEP_MASK (1 << 21) + +/* + * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, + * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, + * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1, + * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB + */ +#define OMAP54XX_MODFREQDIV_EXPONENT_SHIFT 8 +#define OMAP54XX_MODFREQDIV_EXPONENT_WIDTH 0x3 +#define OMAP54XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8) + +/* + * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, + * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, + * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1, + * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB + */ +#define OMAP54XX_MODFREQDIV_MANTISSA_SHIFT 0 +#define OMAP54XX_MODFREQDIV_MANTISSA_WIDTH 0x7 +#define OMAP54XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0) + +/* + * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL, + * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL, + * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL, + * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, + * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL, + * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL, + * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL, + * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL, + * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL, + * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, + * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, + * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL, + * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, + * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, + * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, + * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, + * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL, + * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL, + * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL, + * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL, + * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL, + * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, + * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL, + * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL, + * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL, + * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, + * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, + * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, + * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, + * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, + * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, + * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, + * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, + * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, + * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, + * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, + * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL, + * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, + * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, + * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, + * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, + * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL, + * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL, + * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL, + * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL, + * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL, + * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL, + * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL + */ +#define OMAP54XX_MODULEMODE_SHIFT 0 +#define OMAP54XX_MODULEMODE_WIDTH 0x2 +#define OMAP54XX_MODULEMODE_MASK (0x3 << 0) + +/* Used by CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_MPU_DYNDEP_SHIFT 19 +#define OMAP54XX_MPU_DYNDEP_WIDTH 0x1 +#define OMAP54XX_MPU_DYNDEP_MASK (1 << 19) + +/* Used by CM_DSS_DSS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11 +#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_MASK (1 << 11) + +/* Renamed from OPTFCLKEN_32KHZ_CLK Used by CM_L3INIT_MMC1_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_MASK (1 << 8) + +/* Used by CM_DSS_DSS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9 +#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) + +/* Used by CM_COREAON_USB_PHY_CORE_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_CLK32K_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_CLK32K_MASK (1 << 8) + +/* Used by CM_CAM_ISS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_CTRLCLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_CTRLCLK_MASK (1 << 8) + +/* + * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, + * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, + * CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL + */ +#define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_DBCLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_DBCLK_MASK (1 << 8) + +/* Used by CM_EMIF_EMIF_DLL_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_DLL_CLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_DLL_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_DLL_CLK_MASK (1 << 8) + +/* Used by CM_DSS_DSS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_DSSCLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_DSSCLK_MASK (1 << 8) + +/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_FCLK0_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_FCLK0_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_FCLK0_MASK (1 << 8) + +/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_FCLK1_SHIFT 9 +#define OMAP54XX_OPTFCLKEN_FCLK1_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_FCLK1_MASK (1 << 9) + +/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_FCLK2_SHIFT 10 +#define OMAP54XX_OPTFCLKEN_FCLK2_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_FCLK2_MASK (1 << 10) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_SHIFT 15 +#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_MASK (1 << 15) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 +#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 +#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7 +#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_MASK (1 << 7) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 +#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 +#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6 +#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_MASK (1 << 6) + +/* Used by CM_L3INIT_USB_OTG_SS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_REFCLK960M_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_REFCLK960M_MASK (1 << 8) + +/* Used by CM_L3INIT_SATA_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_REF_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_REF_CLK_MASK (1 << 8) + +/* Used by CM_WKUPAON_SCRM_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_SCRM_CORE_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_SCRM_CORE_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_SCRM_CORE_MASK (1 << 8) + +/* Used by CM_WKUPAON_SCRM_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_SCRM_PER_SHIFT 9 +#define OMAP54XX_OPTFCLKEN_SCRM_PER_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_SCRM_PER_MASK (1 << 9) + +/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11 +#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 11) + +/* Used by CM_DSS_DSS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10 +#define OMAP54XX_OPTFCLKEN_SYS_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_SYS_CLK_MASK (1 << 10) + +/* Used by CM_MIPIEXT_LLI_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_MASK (1 << 8) + +/* Used by CM_MIPIEXT_LLI_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9 +#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_MASK (1 << 9) + +/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) + +/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 +#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) + +/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 +#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 +#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 +#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) + +/* Used by CM_CORE_AON_DEBUG_OUT, CM_CORE_DEBUG_OUT */ +#define OMAP54XX_OUTPUT_SHIFT 0 +#define OMAP54XX_OUTPUT_WIDTH 0x20 +#define OMAP54XX_OUTPUT_MASK (0xffffffff << 0) + +/* Used by CM_CLKSEL_ABE */ +#define OMAP54XX_PAD_CLKS_GATE_SHIFT 8 +#define OMAP54XX_PAD_CLKS_GATE_WIDTH 0x1 +#define OMAP54XX_PAD_CLKS_GATE_MASK (1 << 8) + +/* Used by CM_RESTORE_ST */ +#define OMAP54XX_PHASE1_COMPLETED_SHIFT 0 +#define OMAP54XX_PHASE1_COMPLETED_WIDTH 0x1 +#define OMAP54XX_PHASE1_COMPLETED_MASK (1 << 0) + +/* Used by CM_RESTORE_ST */ +#define OMAP54XX_PHASE2A_COMPLETED_SHIFT 1 +#define OMAP54XX_PHASE2A_COMPLETED_WIDTH 0x1 +#define OMAP54XX_PHASE2A_COMPLETED_MASK (1 << 1) + +/* Used by CM_RESTORE_ST */ +#define OMAP54XX_PHASE2B_COMPLETED_SHIFT 2 +#define OMAP54XX_PHASE2B_COMPLETED_WIDTH 0x1 +#define OMAP54XX_PHASE2B_COMPLETED_MASK (1 << 2) + +/* Used by CM_DYN_DEP_PRESCAL */ +#define OMAP54XX_PRESCAL_SHIFT 0 +#define OMAP54XX_PRESCAL_WIDTH 0x6 +#define OMAP54XX_PRESCAL_MASK (0x3f << 0) + +/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ +#define OMAP54XX_R_RTL_SHIFT 11 +#define OMAP54XX_R_RTL_WIDTH 0x5 +#define OMAP54XX_R_RTL_MASK (0x1f << 11) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_TLL_HS_CLKCTRL */ +#define OMAP54XX_SAR_MODE_SHIFT 4 +#define OMAP54XX_SAR_MODE_WIDTH 0x1 +#define OMAP54XX_SAR_MODE_MASK (1 << 4) + +/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ +#define OMAP54XX_SCHEME_SHIFT 30 +#define OMAP54XX_SCHEME_WIDTH 0x2 +#define OMAP54XX_SCHEME_MASK (0x3 << 30) + +/* Used by CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_SDMA_DYNDEP_SHIFT 11 +#define OMAP54XX_SDMA_DYNDEP_WIDTH 0x1 +#define OMAP54XX_SDMA_DYNDEP_MASK (1 << 11) + +/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_SDMA_STATDEP_SHIFT 11 +#define OMAP54XX_SDMA_STATDEP_WIDTH 0x1 +#define OMAP54XX_SDMA_STATDEP_MASK (1 << 11) + +/* Used by CM_CORE_AON_DEBUG_CFG */ +#define OMAP54XX_SEL0_SHIFT 0 +#define OMAP54XX_SEL0_WIDTH 0x7 +#define OMAP54XX_SEL0_MASK (0x7f << 0) + +/* Renamed from SEL0 Used by CM_CORE_DEBUG_CFG */ +#define OMAP54XX_SEL0_0_7_SHIFT 0 +#define OMAP54XX_SEL0_0_7_WIDTH 0x8 +#define OMAP54XX_SEL0_0_7_MASK (0xff << 0) + +/* Used by CM_CORE_AON_DEBUG_CFG */ +#define OMAP54XX_SEL1_SHIFT 8 +#define OMAP54XX_SEL1_WIDTH 0x7 +#define OMAP54XX_SEL1_MASK (0x7f << 8) + +/* Renamed from SEL1 Used by CM_CORE_DEBUG_CFG */ +#define OMAP54XX_SEL1_CORE_DEBUG_CFG_SHIFT 8 +#define OMAP54XX_SEL1_CORE_DEBUG_CFG_WIDTH 0x8 +#define OMAP54XX_SEL1_CORE_DEBUG_CFG_MASK (0xff << 8) + +/* Used by CM_CORE_AON_DEBUG_CFG */ +#define OMAP54XX_SEL2_SHIFT 16 +#define OMAP54XX_SEL2_WIDTH 0x7 +#define OMAP54XX_SEL2_MASK (0x7f << 16) + +/* Renamed from SEL2 Used by CM_CORE_DEBUG_CFG */ +#define OMAP54XX_SEL2_CORE_DEBUG_CFG_SHIFT 16 +#define OMAP54XX_SEL2_CORE_DEBUG_CFG_WIDTH 0x8 +#define OMAP54XX_SEL2_CORE_DEBUG_CFG_MASK (0xff << 16) + +/* Used by CM_CORE_AON_DEBUG_CFG */ +#define OMAP54XX_SEL3_SHIFT 24 +#define OMAP54XX_SEL3_WIDTH 0x7 +#define OMAP54XX_SEL3_MASK (0x7f << 24) + +/* Renamed from SEL3 Used by CM_CORE_DEBUG_CFG */ +#define OMAP54XX_SEL3_CORE_DEBUG_CFG_SHIFT 24 +#define OMAP54XX_SEL3_CORE_DEBUG_CFG_WIDTH 0x8 +#define OMAP54XX_SEL3_CORE_DEBUG_CFG_MASK (0xff << 24) + +/* Used by CM_CLKSEL_ABE */ +#define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10 +#define OMAP54XX_SLIMBUS1_CLK_GATE_WIDTH 0x1 +#define OMAP54XX_SLIMBUS1_CLK_GATE_MASK (1 << 10) + +/* + * Used by CM_ABE_AESS_CLKCTRL, CM_C2C_C2C_CLKCTRL, CM_CAM_FDIF_CLKCTRL, + * CM_CAM_ISS_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, CM_DSP_DSP_CLKCTRL, + * CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, + * CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, CM_IVA_IVA_CLKCTRL, + * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, + * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_SATA_CLKCTRL, + * CM_L3INIT_UNIPRO2_CLKCTRL, CM_L3INIT_USB_HOST_HS_CLKCTRL, + * CM_L3INIT_USB_OTG_SS_CLKCTRL, CM_L4SEC_DMA_CRYPTO_CLKCTRL, + * CM_MIPIEXT_LLI_CLKCTRL, CM_MPU_MPU_CLKCTRL + */ +#define OMAP54XX_STBYST_SHIFT 18 +#define OMAP54XX_STBYST_WIDTH 0x1 +#define OMAP54XX_STBYST_MASK (1 << 18) + +/* + * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, + * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, + * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB + */ +#define OMAP54XX_ST_DPLL_CLK_SHIFT 0 +#define OMAP54XX_ST_DPLL_CLK_WIDTH 0x1 +#define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0) + +/* + * Used by CM_CLKDCOLDO_DPLL_UNIPRO1, CM_CLKDCOLDO_DPLL_UNIPRO2, + * CM_CLKDCOLDO_DPLL_USB + */ +#define OMAP54XX_ST_DPLL_CLKDCOLDO_SHIFT 9 +#define OMAP54XX_ST_DPLL_CLKDCOLDO_WIDTH 0x1 +#define OMAP54XX_ST_DPLL_CLKDCOLDO_MASK (1 << 9) + +/* + * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, + * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, + * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB + */ +#define OMAP54XX_ST_DPLL_INIT_SHIFT 4 +#define OMAP54XX_ST_DPLL_INIT_WIDTH 0x1 +#define OMAP54XX_ST_DPLL_INIT_MASK (1 << 4) + +/* + * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, + * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, + * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB + */ +#define OMAP54XX_ST_DPLL_MODE_SHIFT 1 +#define OMAP54XX_ST_DPLL_MODE_WIDTH 0x3 +#define OMAP54XX_ST_DPLL_MODE_MASK (0x7 << 1) + +/* Used by CM_CLKSEL_SYS */ +#define OMAP54XX_SYS_CLKSEL_SHIFT 0 +#define OMAP54XX_SYS_CLKSEL_WIDTH 0x3 +#define OMAP54XX_SYS_CLKSEL_MASK (0x7 << 0) + +/* + * Used by CM_C2C_DYNAMICDEP, CM_DSP_DYNAMICDEP, CM_EMU_DYNAMICDEP, + * CM_IPU_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, + * CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP, + * CM_MPU_DYNAMICDEP + */ +#define OMAP54XX_WINDOWSIZE_SHIFT 24 +#define OMAP54XX_WINDOWSIZE_WIDTH 0x4 +#define OMAP54XX_WINDOWSIZE_MASK (0xf << 24) + +/* Used by CM_L3MAIN1_DYNAMICDEP */ +#define OMAP54XX_WKUPAON_DYNDEP_SHIFT 15 +#define OMAP54XX_WKUPAON_DYNDEP_WIDTH 0x1 +#define OMAP54XX_WKUPAON_DYNDEP_MASK (1 << 15) + +/* + * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP, + * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP + */ +#define OMAP54XX_WKUPAON_STATDEP_SHIFT 15 +#define OMAP54XX_WKUPAON_STATDEP_WIDTH 0x1 +#define OMAP54XX_WKUPAON_STATDEP_MASK (1 << 15) + +/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ +#define OMAP54XX_X_MAJOR_SHIFT 8 +#define OMAP54XX_X_MAJOR_WIDTH 0x3 +#define OMAP54XX_X_MAJOR_MASK (0x7 << 8) + +/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ +#define OMAP54XX_Y_MINOR_SHIFT 0 +#define OMAP54XX_Y_MINOR_WIDTH 0x6 +#define OMAP54XX_Y_MINOR_MASK (0x3f << 0) +#endif diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h index 1bc00dc4876..5ae8fe39d6e 100644 --- a/arch/arm/mach-omap2/cm1_44xx.h +++ b/arch/arm/mach-omap2/cm1_44xx.h @@ -25,6 +25,8 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H +#include "cm_44xx_54xx.h" + /* CM1 base address */ #define OMAP4430_CM1_BASE 0x4a004000 @@ -217,9 +219,4 @@ #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) -/* Function prototypes */ -extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx); -extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx); -extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); - #endif diff --git a/arch/arm/mach-omap2/cm1_54xx.h b/arch/arm/mach-omap2/cm1_54xx.h new file mode 100644 index 00000000000..90b3348e667 --- /dev/null +++ b/arch/arm/mach-omap2/cm1_54xx.h @@ -0,0 +1,213 @@ +/* + * OMAP54xx CM1 instance offset macros + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H +#define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H + +#include "cm_44xx_54xx.h" + +/* CM1 base address */ +#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000 + +#define OMAP54XX_CM_CORE_AON_REGADDR(inst, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg)) + +/* CM_CORE_AON instances */ +#define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000 +#define OMAP54XX_CM_CORE_AON_CKGEN_INST 0x0100 +#define OMAP54XX_CM_CORE_AON_MPU_INST 0x0300 +#define OMAP54XX_CM_CORE_AON_DSP_INST 0x0400 +#define OMAP54XX_CM_CORE_AON_ABE_INST 0x0500 +#define OMAP54XX_CM_CORE_AON_RESTORE_INST 0x0e00 +#define OMAP54XX_CM_CORE_AON_INSTR_INST 0x0f00 + +/* CM_CORE_AON clockdomain register offsets (from instance start) */ +#define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000 +#define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x0000 +#define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS 0x0000 + +/* CM_CORE_AON */ + +/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */ +#define OMAP54XX_REVISION_CM_CORE_AON_OFFSET 0x0000 +#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040 +#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040) +#define OMAP54XX_CM_CORE_AON_DEBUG_CFG_OFFSET 0x0080 +#define OMAP54XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x0084 +#define OMAP54XX_CM_CORE_AON_DEBUG_MPU_FD_TRANS_OFFSET 0x0090 +#define OMAP54XX_CM_CORE_AON_DEBUG_DSP_FD_TRANS_OFFSET 0x0094 +#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS_OFFSET 0x0098 +#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS2_OFFSET 0x009c +#define OMAP54XX_CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS_OFFSET 0x00a0 +#define OMAP54XX_CM_CORE_AON_DEBUG_C2C_FD_TRANS_OFFSET 0x00a4 +#define OMAP54XX_CM_CORE_AON_DEBUG_CAM_FD_TRANS_OFFSET 0x00a8 +#define OMAP54XX_CM_CORE_AON_DEBUG_COREAON_FD_TRANS_OFFSET 0x00ac +#define OMAP54XX_CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS_OFFSET 0x00b0 +#define OMAP54XX_CM_CORE_AON_DEBUG_DMA_FD_TRANS_OFFSET 0x00b4 +#define OMAP54XX_CM_CORE_AON_DEBUG_DSS_FD_TRANS_OFFSET 0x00b8 +#define OMAP54XX_CM_CORE_AON_DEBUG_EMIF_FD_TRANS_OFFSET 0x00bc +#define OMAP54XX_CM_CORE_AON_DEBUG_GPU_FD_TRANS_OFFSET 0x00c0 +#define OMAP54XX_CM_CORE_AON_DEBUG_IPU_FD_TRANS_OFFSET 0x00c4 +#define OMAP54XX_CM_CORE_AON_DEBUG_IVA_FD_TRANS_OFFSET 0x00c8 +#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS_OFFSET 0x00cc +#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2_OFFSET 0x00d0 +#define OMAP54XX_CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS_OFFSET 0x00d4 +#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS_OFFSET 0x00d8 +#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS_OFFSET 0x00dc +#define OMAP54XX_CM_CORE_AON_DEBUG_L4CFG_FD_TRANS_OFFSET 0x00e0 +#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS_OFFSET 0x00e4 +#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS2_OFFSET 0x00e8 +#define OMAP54XX_CM_CORE_AON_DEBUG_L4SEC_FD_TRANS_OFFSET 0x00ec +#define OMAP54XX_CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS_OFFSET 0x00f0 + +/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */ +#define OMAP54XX_CM_CLKSEL_CORE_OFFSET 0x0000 +#define OMAP54XX_CM_CLKSEL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0000) +#define OMAP54XX_CM_CLKSEL_ABE_OFFSET 0x0008 +#define OMAP54XX_CM_CLKSEL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0008) +#define OMAP54XX_CM_DLL_CTRL_OFFSET 0x0010 +#define OMAP54XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 +#define OMAP54XX_CM_CLKMODE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0020) +#define OMAP54XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 +#define OMAP54XX_CM_IDLEST_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0024) +#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 +#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0028) +#define OMAP54XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c +#define OMAP54XX_CM_CLKSEL_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x002c) +#define OMAP54XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 +#define OMAP54XX_CM_DIV_M2_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0030) +#define OMAP54XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 +#define OMAP54XX_CM_DIV_M3_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0034) +#define OMAP54XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038 +#define OMAP54XX_CM_DIV_H11_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0038) +#define OMAP54XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c +#define OMAP54XX_CM_DIV_H12_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x003c) +#define OMAP54XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040 +#define OMAP54XX_CM_DIV_H13_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0040) +#define OMAP54XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044 +#define OMAP54XX_CM_DIV_H14_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0044) +#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 +#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c +#define OMAP54XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050 +#define OMAP54XX_CM_DIV_H21_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0050) +#define OMAP54XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054 +#define OMAP54XX_CM_DIV_H22_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0054) +#define OMAP54XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058 +#define OMAP54XX_CM_DIV_H23_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0058) +#define OMAP54XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c +#define OMAP54XX_CM_DIV_H24_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x005c) +#define OMAP54XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 +#define OMAP54XX_CM_CLKMODE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0060) +#define OMAP54XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 +#define OMAP54XX_CM_IDLEST_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0064) +#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 +#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0068) +#define OMAP54XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c +#define OMAP54XX_CM_CLKSEL_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x006c) +#define OMAP54XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 +#define OMAP54XX_CM_DIV_M2_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0070) +#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 +#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c +#define OMAP54XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c +#define OMAP54XX_CM_BYPCLK_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x009c) +#define OMAP54XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 +#define OMAP54XX_CM_CLKMODE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a0) +#define OMAP54XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 +#define OMAP54XX_CM_IDLEST_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a4) +#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 +#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a8) +#define OMAP54XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac +#define OMAP54XX_CM_CLKSEL_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ac) +#define OMAP54XX_CM_DIV_H11_DPLL_IVA_OFFSET 0x00b8 +#define OMAP54XX_CM_DIV_H11_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00b8) +#define OMAP54XX_CM_DIV_H12_DPLL_IVA_OFFSET 0x00bc +#define OMAP54XX_CM_DIV_H12_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00bc) +#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 +#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc +#define OMAP54XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc +#define OMAP54XX_CM_BYPCLK_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00dc) +#define OMAP54XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 +#define OMAP54XX_CM_CLKMODE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e0) +#define OMAP54XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 +#define OMAP54XX_CM_IDLEST_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e4) +#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 +#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e8) +#define OMAP54XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec +#define OMAP54XX_CM_CLKSEL_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ec) +#define OMAP54XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 +#define OMAP54XX_CM_DIV_M2_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f0) +#define OMAP54XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 +#define OMAP54XX_CM_DIV_M3_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f4) +#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 +#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c +#define OMAP54XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 +#define OMAP54XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 +#define OMAP54XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 +#define OMAP54XX_CM_RESTORE_ST_OFFSET 0x0180 + +/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */ +#define OMAP54XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_MPU_STATICDEP_OFFSET 0x0004 +#define OMAP54XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008 +#define OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_MPU_MPU_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0020) +#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028 +#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0028) + +/* CM_CORE_AON.DSP_CM_CORE_AON register offsets */ +#define OMAP54XX_CM_DSP_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_DSP_STATICDEP_OFFSET 0x0004 +#define OMAP54XX_CM_DSP_DYNAMICDEP_OFFSET 0x0008 +#define OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_DSP_DSP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_DSP_INST, 0x0020) + +/* CM_CORE_AON.ABE_CM_CORE_AON register offsets */ +#define OMAP54XX_CM_ABE_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0020) +#define OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET 0x0028 +#define OMAP54XX_CM_ABE_AESS_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0028) +#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET 0x0030 +#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0030) +#define OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET 0x0038 +#define OMAP54XX_CM_ABE_DMIC_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0038) +#define OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET 0x0040 +#define OMAP54XX_CM_ABE_MCASP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0040) +#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 +#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0048) +#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 +#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0050) +#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 +#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0058) +#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET 0x0060 +#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0060) +#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 +#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0068) +#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 +#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0070) +#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 +#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0078) +#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 +#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0080) +#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET 0x0088 +#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0088) + +#endif diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h index b9de72da1a8..ee5136d7cdd 100644 --- a/arch/arm/mach-omap2/cm2_44xx.h +++ b/arch/arm/mach-omap2/cm2_44xx.h @@ -25,6 +25,8 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H #define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H +#include "cm_44xx_54xx.h" + /* CM2 base address */ #define OMAP4430_CM2_BASE 0x4a008000 @@ -449,9 +451,4 @@ #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020) -/* Function prototypes */ -extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx); -extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx); -extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); - #endif diff --git a/arch/arm/mach-omap2/cm2_54xx.h b/arch/arm/mach-omap2/cm2_54xx.h new file mode 100644 index 00000000000..2683231b299 --- /dev/null +++ b/arch/arm/mach-omap2/cm2_54xx.h @@ -0,0 +1,389 @@ +/* + * OMAP54xx CM2 instance offset macros + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H +#define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H + +#include "cm_44xx_54xx.h" + +/* CM2 base address */ +#define OMAP54XX_CM_CORE_BASE 0x4a008000 + +#define OMAP54XX_CM_CORE_REGADDR(inst, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg)) + +/* CM_CORE instances */ +#define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000 +#define OMAP54XX_CM_CORE_CKGEN_INST 0x0100 +#define OMAP54XX_CM_CORE_COREAON_INST 0x0600 +#define OMAP54XX_CM_CORE_CORE_INST 0x0700 +#define OMAP54XX_CM_CORE_IVA_INST 0x1200 +#define OMAP54XX_CM_CORE_CAM_INST 0x1300 +#define OMAP54XX_CM_CORE_DSS_INST 0x1400 +#define OMAP54XX_CM_CORE_GPU_INST 0x1500 +#define OMAP54XX_CM_CORE_L3INIT_INST 0x1600 +#define OMAP54XX_CM_CORE_CUSTEFUSE_INST 0x1700 +#define OMAP54XX_CM_CORE_RESTORE_INST 0x1e00 +#define OMAP54XX_CM_CORE_INSTR_INST 0x1f00 + +/* CM_CORE clockdomain register offsets (from instance start) */ +#define OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000 +#define OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000 +#define OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS 0x0100 +#define OMAP54XX_CM_CORE_CORE_IPU_CDOFFS 0x0200 +#define OMAP54XX_CM_CORE_CORE_DMA_CDOFFS 0x0300 +#define OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400 +#define OMAP54XX_CM_CORE_CORE_C2C_CDOFFS 0x0500 +#define OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600 +#define OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700 +#define OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS 0x0800 +#define OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS 0x0900 +#define OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS 0x0a80 +#define OMAP54XX_CM_CORE_IVA_IVA_CDOFFS 0x0000 +#define OMAP54XX_CM_CORE_CAM_CAM_CDOFFS 0x0000 +#define OMAP54XX_CM_CORE_DSS_DSS_CDOFFS 0x0000 +#define OMAP54XX_CM_CORE_GPU_GPU_CDOFFS 0x0000 +#define OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000 +#define OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000 + +/* CM_CORE */ + +/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */ +#define OMAP54XX_REVISION_CM_CORE_OFFSET 0x0000 +#define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040 +#define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_OCP_SOCKET_INST, 0x0040) +#define OMAP54XX_CM_CORE_DEBUG_CFG_OFFSET 0x0080 +#define OMAP54XX_CM_CORE_DEBUG_OUT_OFFSET 0x0084 + +/* CM_CORE.CKGEN_CM_CORE register offsets */ +#define OMAP54XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 +#define OMAP54XX_CM_CLKSEL_USB_60MHZ OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0004) +#define OMAP54XX_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 +#define OMAP54XX_CM_CLKMODE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0040) +#define OMAP54XX_CM_IDLEST_DPLL_PER_OFFSET 0x0044 +#define OMAP54XX_CM_IDLEST_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0044) +#define OMAP54XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 +#define OMAP54XX_CM_AUTOIDLE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0048) +#define OMAP54XX_CM_CLKSEL_DPLL_PER_OFFSET 0x004c +#define OMAP54XX_CM_CLKSEL_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x004c) +#define OMAP54XX_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 +#define OMAP54XX_CM_DIV_M2_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0050) +#define OMAP54XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 +#define OMAP54XX_CM_DIV_M3_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0054) +#define OMAP54XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0058 +#define OMAP54XX_CM_DIV_H11_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0058) +#define OMAP54XX_CM_DIV_H12_DPLL_PER_OFFSET 0x005c +#define OMAP54XX_CM_DIV_H12_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x005c) +#define OMAP54XX_CM_DIV_H13_DPLL_PER_OFFSET 0x0060 +#define OMAP54XX_CM_DIV_H13_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0060) +#define OMAP54XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0064 +#define OMAP54XX_CM_DIV_H14_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0064) +#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 +#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c +#define OMAP54XX_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 +#define OMAP54XX_CM_CLKMODE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0080) +#define OMAP54XX_CM_IDLEST_DPLL_USB_OFFSET 0x0084 +#define OMAP54XX_CM_IDLEST_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0084) +#define OMAP54XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 +#define OMAP54XX_CM_AUTOIDLE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0088) +#define OMAP54XX_CM_CLKSEL_DPLL_USB_OFFSET 0x008c +#define OMAP54XX_CM_CLKSEL_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x008c) +#define OMAP54XX_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 +#define OMAP54XX_CM_DIV_M2_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0090) +#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 +#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac +#define OMAP54XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 +#define OMAP54XX_CM_CLKDCOLDO_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00b4) +#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2_OFFSET 0x00c0 +#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c0) +#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2_OFFSET 0x00c4 +#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c4) +#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2_OFFSET 0x00c8 +#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c8) +#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2_OFFSET 0x00cc +#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00cc) +#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2_OFFSET 0x00d0 +#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00d0) +#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO2_OFFSET 0x00e8 +#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO2_OFFSET 0x00ec +#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2_OFFSET 0x00f4 +#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00f4) +#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1_OFFSET 0x0100 +#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0100) +#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1_OFFSET 0x0104 +#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0104) +#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1_OFFSET 0x0108 +#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0108) +#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1_OFFSET 0x010c +#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x010c) +#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1_OFFSET 0x0110 +#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0110) +#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO1_OFFSET 0x0128 +#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO1_OFFSET 0x012c +#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1_OFFSET 0x0134 +#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0134) + +/* CM_CORE.COREAON_CM_CORE register offsets */ +#define OMAP54XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028 +#define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0028) +#define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET 0x0030 +#define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0030) +#define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038 +#define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0038) +#define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL_OFFSET 0x0040 +#define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0040) +#define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050 +#define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0050) + +/* CM_CORE.CORE_CM_CORE register offsets */ +#define OMAP54XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008 +#define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0020) +#define OMAP54XX_CM_L3MAIN2_CLKSTCTRL_OFFSET 0x0100 +#define OMAP54XX_CM_L3MAIN2_DYNAMICDEP_OFFSET 0x0108 +#define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET 0x0120 +#define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0120) +#define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET 0x0128 +#define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0128) +#define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 +#define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0130) +#define OMAP54XX_CM_IPU_CLKSTCTRL_OFFSET 0x0200 +#define OMAP54XX_CM_IPU_STATICDEP_OFFSET 0x0204 +#define OMAP54XX_CM_IPU_DYNAMICDEP_OFFSET 0x0208 +#define OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET 0x0220 +#define OMAP54XX_CM_IPU_IPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0220) +#define OMAP54XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300 +#define OMAP54XX_CM_DMA_STATICDEP_OFFSET 0x0304 +#define OMAP54XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308 +#define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320 +#define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0320) +#define OMAP54XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400 +#define OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420 +#define OMAP54XX_CM_EMIF_DMM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0420) +#define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428 +#define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0428) +#define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430 +#define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0430) +#define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438 +#define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0438) +#define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440 +#define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0440) +#define OMAP54XX_CM_C2C_CLKSTCTRL_OFFSET 0x0500 +#define OMAP54XX_CM_C2C_STATICDEP_OFFSET 0x0504 +#define OMAP54XX_CM_C2C_DYNAMICDEP_OFFSET 0x0508 +#define OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET 0x0520 +#define OMAP54XX_CM_C2C_C2C_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0520) +#define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL_OFFSET 0x0528 +#define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0528) +#define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL_OFFSET 0x0530 +#define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0530) +#define OMAP54XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 +#define OMAP54XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 +#define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 +#define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0620) +#define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628 +#define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0628) +#define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 +#define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0630) +#define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 +#define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0638) +#define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640 +#define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0640) +#define OMAP54XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 +#define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET 0x0720 +#define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0720) +#define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 +#define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0728) +#define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740 +#define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0740) +#define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748 +#define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0748) +#define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750 +#define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0750) +#define OMAP54XX_CM_MIPIEXT_CLKSTCTRL_OFFSET 0x0800 +#define OMAP54XX_CM_MIPIEXT_STATICDEP_OFFSET 0x0804 +#define OMAP54XX_CM_MIPIEXT_DYNAMICDEP_OFFSET 0x0808 +#define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL_OFFSET 0x0820 +#define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0820) +#define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL_OFFSET 0x0828 +#define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0828) +#define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL_OFFSET 0x0830 +#define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0830) +#define OMAP54XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0900 +#define OMAP54XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0908 +#define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0928 +#define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0928) +#define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0930 +#define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0930) +#define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0938 +#define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0938) +#define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0940 +#define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0940) +#define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0948 +#define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0948) +#define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0950 +#define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0950) +#define OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0958 +#define OMAP54XX_CM_L4PER_ELM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0958) +#define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0960 +#define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0960) +#define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0968 +#define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0968) +#define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0970 +#define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0970) +#define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0978 +#define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0978) +#define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0980 +#define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0980) +#define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0988 +#define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0988) +#define OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x09a0 +#define OMAP54XX_CM_L4PER_I2C1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a0) +#define OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x09a8 +#define OMAP54XX_CM_L4PER_I2C2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a8) +#define OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x09b0 +#define OMAP54XX_CM_L4PER_I2C3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b0) +#define OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x09b8 +#define OMAP54XX_CM_L4PER_I2C4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b8) +#define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET 0x09c0 +#define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09c0) +#define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x09f0 +#define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f0) +#define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x09f8 +#define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f8) +#define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0a00 +#define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a00) +#define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0a08 +#define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a08) +#define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0a10 +#define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a10) +#define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0a18 +#define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a18) +#define OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0a20 +#define OMAP54XX_CM_L4PER_MMC3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a20) +#define OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0a28 +#define OMAP54XX_CM_L4PER_MMC4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a28) +#define OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0a40 +#define OMAP54XX_CM_L4PER_UART1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a40) +#define OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0a48 +#define OMAP54XX_CM_L4PER_UART2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a48) +#define OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0a50 +#define OMAP54XX_CM_L4PER_UART3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a50) +#define OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0a58 +#define OMAP54XX_CM_L4PER_UART4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a58) +#define OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET 0x0a60 +#define OMAP54XX_CM_L4PER_MMC5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a60) +#define OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0a68 +#define OMAP54XX_CM_L4PER_I2C5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a68) +#define OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0a70 +#define OMAP54XX_CM_L4PER_UART5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a70) +#define OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET 0x0a78 +#define OMAP54XX_CM_L4PER_UART6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a78) +#define OMAP54XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0a80 +#define OMAP54XX_CM_L4SEC_STATICDEP_OFFSET 0x0a84 +#define OMAP54XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0a88 +#define OMAP54XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x0aa0 +#define OMAP54XX_CM_L4SEC_AES1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa0) +#define OMAP54XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x0aa8 +#define OMAP54XX_CM_L4SEC_AES2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa8) +#define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x0ab0 +#define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab0) +#define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x0ab8 +#define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab8) +#define OMAP54XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x0ac0 +#define OMAP54XX_CM_L4SEC_RNG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac0) +#define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL_OFFSET 0x0ac8 +#define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac8) +#define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x0ad8 +#define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ad8) + +/* CM_CORE.IVA_CM_CORE register offsets */ +#define OMAP54XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_IVA_STATICDEP_OFFSET 0x0004 +#define OMAP54XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008 +#define OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_IVA_IVA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0020) +#define OMAP54XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028 +#define OMAP54XX_CM_IVA_SL2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0028) + +/* CM_CORE.CAM_CM_CORE register offsets */ +#define OMAP54XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_CAM_STATICDEP_OFFSET 0x0004 +#define OMAP54XX_CM_CAM_DYNAMICDEP_OFFSET 0x0008 +#define OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_CAM_ISS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0020) +#define OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 +#define OMAP54XX_CM_CAM_FDIF_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0028) +#define OMAP54XX_CM_CAM_CAL_CLKCTRL_OFFSET 0x0030 +#define OMAP54XX_CM_CAM_CAL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0030) + +/* CM_CORE.DSS_CM_CORE register offsets */ +#define OMAP54XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_DSS_STATICDEP_OFFSET 0x0004 +#define OMAP54XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008 +#define OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_DSS_DSS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0020) +#define OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030 +#define OMAP54XX_CM_DSS_BB2D_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0030) + +/* CM_CORE.GPU_CM_CORE register offsets */ +#define OMAP54XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_GPU_STATICDEP_OFFSET 0x0004 +#define OMAP54XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008 +#define OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_GPU_GPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_GPU_INST, 0x0020) + +/* CM_CORE.L3INIT_CM_CORE register offsets */ +#define OMAP54XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_L3INIT_STATICDEP_OFFSET 0x0004 +#define OMAP54XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 +#define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 +#define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0028) +#define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 +#define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0030) +#define OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 +#define OMAP54XX_CM_L3INIT_HSI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0038) +#define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL_OFFSET 0x0040 +#define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0040) +#define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL_OFFSET 0x0048 +#define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0048) +#define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET 0x0058 +#define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0058) +#define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET 0x0068 +#define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0068) +#define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078 +#define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0078) +#define OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 +#define OMAP54XX_CM_L3INIT_SATA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0088) +#define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0 +#define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e0) +#define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8 +#define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e8) +#define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET 0x00f0 +#define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00f0) + +/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */ +#define OMAP54XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CUSTEFUSE_INST, 0x0020) + +#endif diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h index 64f4bafe7bd..9d1f4fcdebb 100644 --- a/arch/arm/mach-omap2/cm33xx.h +++ b/arch/arm/mach-omap2/cm33xx.h @@ -383,7 +383,7 @@ extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs); extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs); extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs); -#ifdef CONFIG_SOC_AM33XX +#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs); extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, diff --git a/arch/arm/mach-omap2/cm_44xx_54xx.h b/arch/arm/mach-omap2/cm_44xx_54xx.h new file mode 100644 index 00000000000..cbb21169032 --- /dev/null +++ b/arch/arm/mach-omap2/cm_44xx_54xx.h @@ -0,0 +1,36 @@ +/* + * OMAP44xx and OMAP54xx CM1/CM2 function prototypes + * + * Copyright (C) 2009-2013 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CM_44XX_54XX_H +#define __ARCH_ARM_MACH_OMAP2_CM_44XX_55XX_H + +/* CM1 Function prototypes */ +extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx); +extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx); +extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); + +/* CM2 Function prototypes */ +extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx); +extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx); +extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); + +#endif diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index d555cf2459e..72cab3f4f16 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -96,6 +96,7 @@ void am33xx_init_early(void); void am35xx_init_early(void); void ti81xx_init_early(void); void am33xx_init_early(void); +void am43xx_init_early(void); void omap4430_init_early(void); void omap5_init_early(void); void omap3_init_late(void); /* Do not use this one */ @@ -237,8 +238,8 @@ extern void omap_do_wfi(void); #ifdef CONFIG_SMP /* Needed for secondary core boot */ -extern void omap_secondary_startup(void); -extern void omap_secondary_startup_4460(void); +extern void omap4_secondary_startup(void); +extern void omap4460_secondary_startup(void); extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); extern void omap_auxcoreboot_addr(u32 cpu_addr); extern u32 omap_read_auxcoreboot0(void); diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index e6c328128a0..f7d7c2ef1b4 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -358,6 +358,18 @@ #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) +/* AM33XX PWMSS Control register */ +#define AM33XX_PWMSS_TBCLK_CLKCTRL 0x664 + +/* AM33XX PWMSS Control bitfields */ +#define AM33XX_PWMSS0_TBCLKEN_SHIFT 0 +#define AM33XX_PWMSS1_TBCLKEN_SHIFT 1 +#define AM33XX_PWMSS2_TBCLKEN_SHIFT 2 + +/* DEV Feature register to identify AM33XX features */ +#define AM33XX_DEV_FEATURE 0x604 +#define AM33XX_SGX_MASK BIT(29) + /* CONTROL OMAP STATUS register to identify OMAP3 features */ #define OMAP3_CONTROL_OMAP_STATUS 0x044c diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 1272c41d474..7335eb2bf3f 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -55,7 +55,7 @@ int omap_type(void) if (cpu_is_omap24xx()) { val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); - } else if (soc_is_am33xx()) { + } else if (soc_is_am33xx() || soc_is_am43xx()) { val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); } else if (cpu_is_omap34xx()) { val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); @@ -209,6 +209,8 @@ static void __init omap3_cpuinfo(void) cpu_name = "TI816X"; } else if (soc_is_am335x()) { cpu_name = "AM335X"; + } else if (soc_is_am437x()) { + cpu_name = "AM437x"; } else if (cpu_is_ti814x()) { cpu_name = "TI814X"; } else if (omap3_has_iva() && omap3_has_sgx()) { @@ -302,6 +304,19 @@ void __init ti81xx_check_features(void) omap3_cpuinfo(); } +void __init am33xx_check_features(void) +{ + u32 status; + + omap_features = OMAP3_HAS_NEON; + + status = omap_ctrl_readl(AM33XX_DEV_FEATURE); + if (status & AM33XX_SGX_MASK) + omap_features |= OMAP3_HAS_SGX; + + omap3_cpuinfo(); +} + void __init omap3xxx_check_revision(void) { const char *cpu_rev; @@ -405,11 +420,18 @@ void __init omap3xxx_check_revision(void) cpu_rev = "1.0"; break; case 1: - /* FALLTHROUGH */ - default: omap_revision = TI8168_REV_ES1_1; cpu_rev = "1.1"; break; + case 2: + omap_revision = TI8168_REV_ES2_0; + cpu_rev = "2.0"; + break; + case 3: + /* FALLTHROUGH */ + default: + omap_revision = TI8168_REV_ES2_1; + cpu_rev = "2.1"; } break; case 0xb944: @@ -430,6 +452,10 @@ void __init omap3xxx_check_revision(void) break; } break; + case 0xb98c: + omap_revision = AM437X_REV_ES1_0; + cpu_rev = "1.0"; + break; case 0xb8f2: switch (rev) { case 0: diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 09abf99e9e5..fe3253a100e 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -202,7 +202,7 @@ static struct map_desc omapti81xx_io_desc[] __initdata = { }; #endif -#ifdef CONFIG_SOC_AM33XX +#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) static struct map_desc omapam33xx_io_desc[] __initdata = { { .virtual = L4_34XX_VIRT, @@ -318,7 +318,7 @@ void __init ti81xx_map_io(void) } #endif -#ifdef CONFIG_SOC_AM33XX +#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) void __init am33xx_map_io(void) { iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); @@ -576,8 +576,7 @@ void __init am33xx_init_early(void) omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE)); omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL); omap3xxx_check_revision(); - ti81xx_check_features(); - am33xx_voltagedomains_init(); + am33xx_check_features(); am33xx_powerdomains_init(); am33xx_clockdomains_init(); am33xx_hwmod_init(); @@ -586,6 +585,19 @@ void __init am33xx_init_early(void) } #endif +#ifdef CONFIG_SOC_AM43XX +void __init am43xx_init_early(void) +{ + omap2_set_globals_tap(AM335X_CLASS, + AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); + omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), + NULL); + omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE)); + omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL); + omap3xxx_check_revision(); +} +#endif + #ifdef CONFIG_ARCH_OMAP4 void __init omap4430_init_early(void) { @@ -631,7 +643,13 @@ void __init omap5_init_early(void) omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); omap_prm_base_init(); omap_cm_base_init(); + omap44xx_prm_init(); omap5xxx_check_revision(); + omap54xx_voltagedomains_init(); + omap54xx_powerdomains_init(); + omap54xx_clockdomains_init(); + omap54xx_hwmod_init(); + omap_hwmod_init_postsetup(); } #endif diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 0ea09faf327..4ea30811416 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -49,7 +49,7 @@ END(omap5_secondary_startup) * The primary core will update this flag using a hardware * register AuxCoreBoot0. */ -ENTRY(omap_secondary_startup) +ENTRY(omap4_secondary_startup) hold: ldr r12,=0x103 dsb smc #0 @ read from AuxCoreBoot0 @@ -64,9 +64,9 @@ hold: ldr r12,=0x103 * should now contain the SVC stack for this core */ b secondary_startup -ENDPROC(omap_secondary_startup) +ENDPROC(omap4_secondary_startup) -ENTRY(omap_secondary_startup_4460) +ENTRY(omap4460_secondary_startup) hold_2: ldr r12,=0x103 dsb smc #0 @ read from AuxCoreBoot0 @@ -101,4 +101,4 @@ hold_2: ldr r12,=0x103 * should now contain the SVC stack for this core */ b secondary_startup -ENDPROC(omap_secondary_startup_4460) +ENDPROC(omap4460_secondary_startup) diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c index e80327b6c81..f993a418870 100644 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c @@ -71,10 +71,43 @@ struct omap4_cpu_pm_info { void (*secondary_startup)(void); }; +/** + * struct cpu_pm_ops - CPU pm operations + * @finish_suspend: CPU suspend finisher function pointer + * @resume: CPU resume function pointer + * @scu_prepare: CPU Snoop Control program function pointer + * + * Structure holds functions pointer for CPU low power operations like + * suspend, resume and scu programming. + */ +struct cpu_pm_ops { + int (*finish_suspend)(unsigned long cpu_state); + void (*resume)(void); + void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state); +}; + static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info); static struct powerdomain *mpuss_pd; static void __iomem *sar_base; +static int default_finish_suspend(unsigned long cpu_state) +{ + omap_do_wfi(); + return 0; +} + +static void dummy_cpu_resume(void) +{} + +static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state) +{} + +struct cpu_pm_ops omap_pm_ops = { + .finish_suspend = default_finish_suspend, + .resume = dummy_cpu_resume, + .scu_prepare = dummy_scu_prepare, +}; + /* * Program the wakeup routine address for the CPU0 and CPU1 * used for OFF or DORMANT wakeup. @@ -158,11 +191,12 @@ static void save_l2x0_context(void) { u32 val; void __iomem *l2x0_base = omap4_get_l2cache_base(); - - val = __raw_readl(l2x0_base + L2X0_AUX_CTRL); - __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET); - val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL); - __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET); + if (l2x0_base) { + val = __raw_readl(l2x0_base + L2X0_AUX_CTRL); + __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET); + val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL); + __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET); + } } #else static void save_l2x0_context(void) @@ -225,14 +259,17 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) cpu_clear_prev_logic_pwrst(cpu); pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); - set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume)); - scu_pwrst_prepare(cpu, power_state); + set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume)); + omap_pm_ops.scu_prepare(cpu, power_state); l2x0_pwrst_prepare(cpu, save_state); /* * Call low level function with targeted low power state. */ - cpu_suspend(save_state, omap4_finish_suspend); + if (save_state) + cpu_suspend(save_state, omap_pm_ops.finish_suspend); + else + omap_pm_ops.finish_suspend(save_state); /* * Restore the CPUx power state to ON otherwise CPUx @@ -268,14 +305,14 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup)); - scu_pwrst_prepare(cpu, power_state); + omap_pm_ops.scu_prepare(cpu, power_state); /* * CPU never retuns back if targeted power state is OFF mode. * CPU ONLINE follows normal CPU ONLINE ptah via - * omap_secondary_startup(). + * omap4_secondary_startup(). */ - omap4_finish_suspend(cpu_state); + omap_pm_ops.finish_suspend(cpu_state); pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); return 0; @@ -319,9 +356,9 @@ int __init omap4_mpuss_init(void) pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET; pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1; if (cpu_is_omap446x()) - pm_info->secondary_startup = omap_secondary_startup_4460; + pm_info->secondary_startup = omap4460_secondary_startup; else - pm_info->secondary_startup = omap_secondary_startup; + pm_info->secondary_startup = omap4_secondary_startup; pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm"); if (!pm_info->pwrdm) { @@ -352,6 +389,12 @@ int __init omap4_mpuss_init(void) save_l2x0_context(); + if (cpu_is_omap44xx()) { + omap_pm_ops.finish_suspend = omap4_finish_suspend; + omap_pm_ops.resume = omap4_cpu_resume; + omap_pm_ops.scu_prepare = scu_pwrst_prepare; + } + return 0; } diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 2a551f997ae..98a11463a84 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -87,7 +87,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * /* * Update the AuxCoreBoot0 with boot state for secondary core. - * omap_secondary_startup() routine will hold the secondary core till + * omap4_secondary_startup() routine will hold the secondary core till * the AuxCoreBoot1 register is updated with cpu state * A barrier is added to ensure that write buffer is drained */ @@ -200,7 +200,7 @@ static void __init omap4_smp_init_cpus(void) static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) { - void *startup_addr = omap_secondary_startup; + void *startup_addr = omap4_secondary_startup; void __iomem *base = omap_get_wakeupgen_base(); /* @@ -211,7 +211,7 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) scu_enable(scu_base); if (cpu_is_omap446x()) { - startup_addr = omap_secondary_startup_4460; + startup_addr = omap4460_secondary_startup; pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; } diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 13b27ffaf45..38cd3a69cff 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -339,19 +339,3 @@ int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) return 0; } #endif - -/** - * omap44xx_restart - trigger a software restart of the SoC - * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c - * @cmd: passed from the userspace program rebooting the system (if provided) - * - * Resets the SoC. For @cmd, see the 'reboot' syscall in - * kernel/sys.c. No return value. - */ -void omap44xx_restart(char mode, const char *cmd) -{ - /* XXX Should save 'cmd' into scratchpad for use after reboot */ - omap4_prminst_global_warm_sw_reset(); /* never returns */ - while (1); -} - diff --git a/arch/arm/mach-omap2/omap4-restart.c b/arch/arm/mach-omap2/omap4-restart.c new file mode 100644 index 00000000000..f90e02e1189 --- /dev/null +++ b/arch/arm/mach-omap2/omap4-restart.c @@ -0,0 +1,27 @@ +/* + * omap4-restart.c - Common to OMAP4 and OMAP5 + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/types.h> +#include "prminst44xx.h" + +/** + * omap44xx_restart - trigger a software restart of the SoC + * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c + * @cmd: passed from the userspace program rebooting the system (if provided) + * + * Resets the SoC. For @cmd, see the 'reboot' syscall in + * kernel/sys.c. No return value. + */ +void omap44xx_restart(char mode, const char *cmd) +{ + /* XXX Should save 'cmd' into scratchpad for use after reboot */ + omap4_prminst_global_warm_sw_reset(); /* never returns */ + while (1) + ; +} diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index d25a95fe992..7341eff63f5 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1356,13 +1356,27 @@ static void _enable_sysc(struct omap_hwmod *oh) clkdm = _get_clkdm(oh); if (sf & SYSC_HAS_SIDLEMODE) { + if (oh->flags & HWMOD_SWSUP_SIDLE || + oh->flags & HWMOD_SWSUP_SIDLE_ACT) { + idlemode = HWMOD_IDLEMODE_NO; + } else { + if (sf & SYSC_HAS_ENAWAKEUP) + _enable_wakeup(oh, &v); + if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) + idlemode = HWMOD_IDLEMODE_SMART_WKUP; + else + idlemode = HWMOD_IDLEMODE_SMART; + } + + /* + * This is special handling for some IPs like + * 32k sync timer. Force them to idle! + */ clkdm_act = (clkdm && clkdm->flags & CLKDM_ACTIVE_WITH_MPU); if (clkdm_act && !(oh->class->sysc->idlemodes & (SIDLE_SMART | SIDLE_SMART_WKUP))) idlemode = HWMOD_IDLEMODE_FORCE; - else - idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? - HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; + _set_slave_idlemode(oh, idlemode, &v); } @@ -1391,10 +1405,6 @@ static void _enable_sysc(struct omap_hwmod *oh) (sf & SYSC_HAS_CLOCKACTIVITY)) _set_clockactivity(oh, oh->class->sysc->clockact, &v); - /* If slave is in SMARTIDLE, also enable wakeup */ - if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) - _enable_wakeup(oh, &v); - _write_sysconfig(v, oh); /* @@ -1430,13 +1440,16 @@ static void _idle_sysc(struct omap_hwmod *oh) sf = oh->class->sysc->sysc_flags; if (sf & SYSC_HAS_SIDLEMODE) { - /* XXX What about HWMOD_IDLEMODE_SMART_WKUP? */ - if (oh->flags & HWMOD_SWSUP_SIDLE || - !(oh->class->sysc->idlemodes & - (SIDLE_SMART | SIDLE_SMART_WKUP))) + if (oh->flags & HWMOD_SWSUP_SIDLE) { idlemode = HWMOD_IDLEMODE_FORCE; - else - idlemode = HWMOD_IDLEMODE_SMART; + } else { + if (sf & SYSC_HAS_ENAWAKEUP) + _enable_wakeup(oh, &v); + if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) + idlemode = HWMOD_IDLEMODE_SMART_WKUP; + else + idlemode = HWMOD_IDLEMODE_SMART; + } _set_slave_idlemode(oh, idlemode, &v); } @@ -1455,10 +1468,6 @@ static void _idle_sysc(struct omap_hwmod *oh) _set_master_standbymode(oh, idlemode, &v); } - /* If slave is in SMARTIDLE, also enable wakeup */ - if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) - _enable_wakeup(oh, &v); - _write_sysconfig(v, oh); } @@ -2065,7 +2074,7 @@ static int _omap4_get_context_lost(struct omap_hwmod *oh) * do so is present in the hwmod data, then call it and pass along the * return value; otherwise, return 0. */ -static int __init _enable_preprogram(struct omap_hwmod *oh) +static int _enable_preprogram(struct omap_hwmod *oh) { if (!oh->class->enable_preprogram) return 0; @@ -2246,42 +2255,6 @@ static int _idle(struct omap_hwmod *oh) } /** - * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit - * @oh: struct omap_hwmod * - * @autoidle: desired AUTOIDLE bitfield value (0 or 1) - * - * Sets the IP block's OCP autoidle bit in hardware, and updates our - * local copy. Intended to be used by drivers that require - * direct manipulation of the AUTOIDLE bits. - * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes - * along the return value from _set_module_autoidle(). - * - * Any users of this function should be scrutinized carefully. - */ -int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle) -{ - u32 v; - int retval = 0; - unsigned long flags; - - if (!oh || oh->_state != _HWMOD_STATE_ENABLED) - return -EINVAL; - - spin_lock_irqsave(&oh->_lock, flags); - - v = oh->_sysc_cache; - - retval = _set_module_autoidle(oh, autoidle, &v); - - if (!retval) - _write_sysconfig(v, oh); - - spin_unlock_irqrestore(&oh->_lock, flags); - - return retval; -} - -/** * _shutdown - shutdown an omap_hwmod * @oh: struct omap_hwmod * * @@ -3180,38 +3153,6 @@ error: } /** - * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode - * @oh: struct omap_hwmod * - * @idlemode: SIDLEMODE field bits (shifted to bit 0) - * - * Sets the IP block's OCP slave idlemode in hardware, and updates our - * local copy. Intended to be used by drivers that have some erratum - * that requires direct manipulation of the SIDLEMODE bits. Returns - * -EINVAL if @oh is null, or passes along the return value from - * _set_slave_idlemode(). - * - * XXX Does this function have any current users? If not, we should - * remove it; it is better to let the rest of the hwmod code handle this. - * Any users of this function should be scrutinized carefully. - */ -int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) -{ - u32 v; - int retval = 0; - - if (!oh) - return -EINVAL; - - v = oh->_sysc_cache; - - retval = _set_slave_idlemode(oh, idlemode, &v); - if (!retval) - _write_sysconfig(v, oh); - - return retval; -} - -/** * omap_hwmod_lookup - look up a registered omap_hwmod by name * @name: name of the omap_hwmod to look up * diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index fe5962921f0..aab33fd814c 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -463,6 +463,9 @@ struct omap_hwmod_omap4_prcm { * is kept in force-standby mode. Failing to do so causes PM problems * with musb on OMAP3630 at least. Note that musb has a dedicated register * to control MSTANDBY signal when MIDLEMODE is set to force-standby. + * HWMOD_SWSUP_SIDLE_ACT: omap_hwmod code should manually bring the module + * out of idle, but rely on smart-idle to the put it back in idle, + * so the wakeups are still functional (Only known case for now is UART) */ #define HWMOD_SWSUP_SIDLE (1 << 0) #define HWMOD_SWSUP_MSTANDBY (1 << 1) @@ -476,6 +479,7 @@ struct omap_hwmod_omap4_prcm { #define HWMOD_EXT_OPT_MAIN_CLK (1 << 9) #define HWMOD_BLOCK_WFI (1 << 10) #define HWMOD_FORCE_MSTANDBY (1 << 11) +#define HWMOD_SWSUP_SIDLE_ACT (1 << 12) /* * omap_hwmod._int_flags definitions @@ -641,9 +645,6 @@ int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name); int omap_hwmod_enable_clocks(struct omap_hwmod *oh); int omap_hwmod_disable_clocks(struct omap_hwmod *oh); -int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode); -int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle); - int omap_hwmod_reset(struct omap_hwmod *oh); void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); @@ -698,6 +699,7 @@ extern int omap2420_hwmod_init(void); extern int omap2430_hwmod_init(void); extern int omap3xxx_hwmod_init(void); extern int omap44xx_hwmod_init(void); +extern int omap54xx_hwmod_init(void); extern int am33xx_hwmod_init(void); extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index c8c64b3e1ac..d05fc7b5456 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -512,6 +512,7 @@ struct omap_hwmod omap2xxx_uart1_hwmod = { .mpu_irqs = omap2_uart1_mpu_irqs, .sdma_reqs = omap2_uart1_sdma_reqs, .main_clk = "uart1_fck", + .flags = HWMOD_SWSUP_SIDLE_ACT, .prcm = { .omap2 = { .module_offs = CORE_MOD, @@ -531,6 +532,7 @@ struct omap_hwmod omap2xxx_uart2_hwmod = { .mpu_irqs = omap2_uart2_mpu_irqs, .sdma_reqs = omap2_uart2_sdma_reqs, .main_clk = "uart2_fck", + .flags = HWMOD_SWSUP_SIDLE_ACT, .prcm = { .omap2 = { .module_offs = CORE_MOD, @@ -550,6 +552,7 @@ struct omap_hwmod omap2xxx_uart3_hwmod = { .mpu_irqs = omap2_uart3_mpu_irqs, .sdma_reqs = omap2_uart3_sdma_reqs, .main_clk = "uart3_fck", + .flags = HWMOD_SWSUP_SIDLE_ACT, .prcm = { .omap2 = { .module_offs = CORE_MOD, diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 01d8f324450..0c9a183131e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -329,7 +329,7 @@ static struct omap_hwmod_class am33xx_gfx_hwmod_class = { }; static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { - { .name = "gfx", .rst_shift = 0 }, + { .name = "gfx", .rst_shift = 0, .st_shift = 0}, }; static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = { @@ -347,6 +347,7 @@ static struct omap_hwmod am33xx_gfx_hwmod = { .omap4 = { .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET, .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET, + .rstst_offs = AM33XX_RM_GFX_RSTST_OFFSET, .modulemode = MODULEMODE_SWCTRL, }, }, @@ -1995,6 +1996,7 @@ static struct omap_hwmod am33xx_uart1_hwmod = { .name = "uart1", .class = &uart_class, .clkdm_name = "l4_wkup_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = am33xx_uart1_irqs, .sdma_reqs = uart1_edma_reqs, .main_clk = "dpll_per_m2_div4_wkupdm_ck", @@ -2006,6 +2008,13 @@ static struct omap_hwmod am33xx_uart1_hwmod = { }, }; +/* uart2 */ +static struct omap_hwmod_dma_info uart2_edma_reqs[] = { + { .name = "tx", .dma_req = 28, }, + { .name = "rx", .dma_req = 29, }, + { .dma_req = -1 } +}; + static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = { { .irq = 73 + OMAP_INTC_START, }, { .irq = -1 }, @@ -2015,8 +2024,9 @@ static struct omap_hwmod am33xx_uart2_hwmod = { .name = "uart2", .class = &uart_class, .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = am33xx_uart2_irqs, - .sdma_reqs = uart1_edma_reqs, + .sdma_reqs = uart2_edma_reqs, .main_clk = "dpll_per_m2_div4_ck", .prcm = { .omap4 = { @@ -2042,6 +2052,7 @@ static struct omap_hwmod am33xx_uart3_hwmod = { .name = "uart3", .class = &uart_class, .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = am33xx_uart3_irqs, .sdma_reqs = uart3_edma_reqs, .main_clk = "dpll_per_m2_div4_ck", @@ -2062,6 +2073,7 @@ static struct omap_hwmod am33xx_uart4_hwmod = { .name = "uart4", .class = &uart_class, .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = am33xx_uart4_irqs, .sdma_reqs = uart1_edma_reqs, .main_clk = "dpll_per_m2_div4_ck", @@ -2082,6 +2094,7 @@ static struct omap_hwmod am33xx_uart5_hwmod = { .name = "uart5", .class = &uart_class, .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = am33xx_uart5_irqs, .sdma_reqs = uart1_edma_reqs, .main_clk = "dpll_per_m2_div4_ck", @@ -2102,6 +2115,7 @@ static struct omap_hwmod am33xx_uart6_hwmod = { .name = "uart6", .class = &uart_class, .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = am33xx_uart6_irqs, .sdma_reqs = uart1_edma_reqs, .main_clk = "dpll_per_m2_div4_ck", diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 4083606ea1d..31c7126eb3b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -490,6 +490,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = { .mpu_irqs = omap2_uart1_mpu_irqs, .sdma_reqs = omap2_uart1_sdma_reqs, .main_clk = "uart1_fck", + .flags = HWMOD_SWSUP_SIDLE_ACT, .prcm = { .omap2 = { .module_offs = CORE_MOD, @@ -508,6 +509,7 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = { .mpu_irqs = omap2_uart2_mpu_irqs, .sdma_reqs = omap2_uart2_sdma_reqs, .main_clk = "uart2_fck", + .flags = HWMOD_SWSUP_SIDLE_ACT, .prcm = { .omap2 = { .module_offs = CORE_MOD, @@ -526,6 +528,7 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = { .mpu_irqs = omap2_uart3_mpu_irqs, .sdma_reqs = omap2_uart3_sdma_reqs, .main_clk = "uart3_fck", + .flags = HWMOD_SWSUP_SIDLE_ACT, .prcm = { .omap2 = { .module_offs = OMAP3430_PER_MOD, @@ -555,6 +558,7 @@ static struct omap_hwmod omap36xx_uart4_hwmod = { .mpu_irqs = uart4_mpu_irqs, .sdma_reqs = uart4_sdma_reqs, .main_clk = "uart4_fck", + .flags = HWMOD_SWSUP_SIDLE_ACT, .prcm = { .omap2 = { .module_offs = OMAP3430_PER_MOD, diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index eaba9dc91a0..848b6dc6759 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -3434,6 +3434,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = { .name = "uart1", .class = &omap44xx_uart_hwmod_class, .clkdm_name = "l4_per_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = omap44xx_uart1_irqs, .sdma_reqs = omap44xx_uart1_sdma_reqs, .main_clk = "func_48m_fclk", @@ -3462,6 +3463,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = { .name = "uart2", .class = &omap44xx_uart_hwmod_class, .clkdm_name = "l4_per_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = omap44xx_uart2_irqs, .sdma_reqs = omap44xx_uart2_sdma_reqs, .main_clk = "func_48m_fclk", @@ -3490,7 +3492,8 @@ static struct omap_hwmod omap44xx_uart3_hwmod = { .name = "uart3", .class = &omap44xx_uart_hwmod_class, .clkdm_name = "l4_per_clkdm", - .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET | + HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = omap44xx_uart3_irqs, .sdma_reqs = omap44xx_uart3_sdma_reqs, .main_clk = "func_48m_fclk", @@ -3519,6 +3522,7 @@ static struct omap_hwmod omap44xx_uart4_hwmod = { .name = "uart4", .class = &omap44xx_uart_hwmod_class, .clkdm_name = "l4_per_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = omap44xx_uart4_irqs, .sdma_reqs = omap44xx_uart4_sdma_reqs, .main_clk = "func_48m_fclk", diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c new file mode 100644 index 00000000000..f37ae96b70a --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -0,0 +1,2150 @@ +/* + * Hardware modules present on the OMAP54xx chips + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Paul Walmsley + * Benoit Cousson + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/io.h> +#include <linux/platform_data/gpio-omap.h> +#include <linux/power/smartreflex.h> +#include <linux/i2c-omap.h> + +#include <linux/omap-dma.h> +#include <linux/platform_data/spi-omap2-mcspi.h> +#include <linux/platform_data/asoc-ti-mcbsp.h> +#include <plat/dmtimer.h> + +#include "omap_hwmod.h" +#include "omap_hwmod_common_data.h" +#include "cm1_54xx.h" +#include "cm2_54xx.h" +#include "prm54xx.h" +#include "prm-regbits-54xx.h" +#include "i2c.h" +#include "mmc.h" +#include "wd_timer.h" + +/* Base offset for all OMAP5 interrupts external to MPUSS */ +#define OMAP54XX_IRQ_GIC_START 32 + +/* Base offset for all OMAP5 dma requests */ +#define OMAP54XX_DMA_REQ_START 1 + + +/* + * IP blocks + */ + +/* + * 'dmm' class + * instance(s): dmm + */ +static struct omap_hwmod_class omap54xx_dmm_hwmod_class = { + .name = "dmm", +}; + +/* dmm */ +static struct omap_hwmod omap54xx_dmm_hwmod = { + .name = "dmm", + .class = &omap54xx_dmm_hwmod_class, + .clkdm_name = "emif_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET, + }, + }, +}; + +/* + * 'l3' class + * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 + */ +static struct omap_hwmod_class omap54xx_l3_hwmod_class = { + .name = "l3", +}; + +/* l3_instr */ +static struct omap_hwmod omap54xx_l3_instr_hwmod = { + .name = "l3_instr", + .class = &omap54xx_l3_hwmod_class, + .clkdm_name = "l3instr_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* l3_main_1 */ +static struct omap_hwmod omap54xx_l3_main_1_hwmod = { + .name = "l3_main_1", + .class = &omap54xx_l3_hwmod_class, + .clkdm_name = "l3main1_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET, + }, + }, +}; + +/* l3_main_2 */ +static struct omap_hwmod omap54xx_l3_main_2_hwmod = { + .name = "l3_main_2", + .class = &omap54xx_l3_hwmod_class, + .clkdm_name = "l3main2_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET, + }, + }, +}; + +/* l3_main_3 */ +static struct omap_hwmod omap54xx_l3_main_3_hwmod = { + .name = "l3_main_3", + .class = &omap54xx_l3_hwmod_class, + .clkdm_name = "l3instr_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* + * 'l4' class + * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup + */ +static struct omap_hwmod_class omap54xx_l4_hwmod_class = { + .name = "l4", +}; + +/* l4_abe */ +static struct omap_hwmod omap54xx_l4_abe_hwmod = { + .name = "l4_abe", + .class = &omap54xx_l4_hwmod_class, + .clkdm_name = "abe_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET, + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, +}; + +/* l4_cfg */ +static struct omap_hwmod omap54xx_l4_cfg_hwmod = { + .name = "l4_cfg", + .class = &omap54xx_l4_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, + }, + }, +}; + +/* l4_per */ +static struct omap_hwmod omap54xx_l4_per_hwmod = { + .name = "l4_per", + .class = &omap54xx_l4_hwmod_class, + .clkdm_name = "l4per_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET, + }, + }, +}; + +/* l4_wkup */ +static struct omap_hwmod omap54xx_l4_wkup_hwmod = { + .name = "l4_wkup", + .class = &omap54xx_l4_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET, + }, + }, +}; + +/* + * 'mpu_bus' class + * instance(s): mpu_private + */ +static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = { + .name = "mpu_bus", +}; + +/* mpu_private */ +static struct omap_hwmod omap54xx_mpu_private_hwmod = { + .name = "mpu_private", + .class = &omap54xx_mpu_bus_hwmod_class, + .clkdm_name = "mpu_clkdm", + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, +}; + +/* + * 'counter' class + * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock + */ + +static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_counter_hwmod_class = { + .name = "counter", + .sysc = &omap54xx_counter_sysc, +}; + +/* counter_32k */ +static struct omap_hwmod omap54xx_counter_32k_hwmod = { + .name = "counter_32k", + .class = &omap54xx_counter_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .flags = HWMOD_SWSUP_SIDLE, + .main_clk = "wkupaon_iclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET, + }, + }, +}; + +/* + * 'dma' class + * dma controller for data exchange between memory to memory (i.e. internal or + * external memory) and gp peripherals to memory or memory to gp peripherals + */ + +static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x002c, + .syss_offs = 0x0028, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_dma_hwmod_class = { + .name = "dma", + .sysc = &omap54xx_dma_sysc, +}; + +/* dma dev_attr */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, + .lch_count = 32, +}; + +/* dma_system */ +static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = { + { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START }, + { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START }, + { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START }, + { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod omap54xx_dma_system_hwmod = { + .name = "dma_system", + .class = &omap54xx_dma_hwmod_class, + .clkdm_name = "dma_clkdm", + .mpu_irqs = omap54xx_dma_system_irqs, + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET, + }, + }, + .dev_attr = &dma_dev_attr, +}; + +/* + * 'dmic' class + * digital microphone controller + */ + +static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap54xx_dmic_hwmod_class = { + .name = "dmic", + .sysc = &omap54xx_dmic_sysc, +}; + +/* dmic */ +static struct omap_hwmod omap54xx_dmic_hwmod = { + .name = "dmic", + .class = &omap54xx_dmic_hwmod_class, + .clkdm_name = "abe_clkdm", + .main_clk = "dmic_gfclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'emif' class + * external memory interface no1 (wrapper) + */ + +static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = { + .rev_offs = 0x0000, +}; + +static struct omap_hwmod_class omap54xx_emif_hwmod_class = { + .name = "emif", + .sysc = &omap54xx_emif_sysc, +}; + +/* emif1 */ +static struct omap_hwmod omap54xx_emif1_hwmod = { + .name = "emif1", + .class = &omap54xx_emif_hwmod_class, + .clkdm_name = "emif_clkdm", + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, + .main_clk = "dpll_core_h11x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* emif2 */ +static struct omap_hwmod omap54xx_emif2_hwmod = { + .name = "emif2", + .class = &omap54xx_emif_hwmod_class, + .clkdm_name = "emif_clkdm", + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, + .main_clk = "dpll_core_h11x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* + * 'gpio' class + * general purpose io module + */ + +static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0114, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_gpio_hwmod_class = { + .name = "gpio", + .sysc = &omap54xx_gpio_sysc, + .rev = 2, +}; + +/* gpio dev_attr */ +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = true, +}; + +/* gpio1 */ +static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { + { .role = "dbclk", .clk = "gpio1_dbclk" }, +}; + +static struct omap_hwmod omap54xx_gpio1_hwmod = { + .name = "gpio1", + .class = &omap54xx_gpio_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .main_clk = "wkupaon_iclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio2 */ +static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { + { .role = "dbclk", .clk = "gpio2_dbclk" }, +}; + +static struct omap_hwmod omap54xx_gpio2_hwmod = { + .name = "gpio2", + .class = &omap54xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio3 */ +static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { + { .role = "dbclk", .clk = "gpio3_dbclk" }, +}; + +static struct omap_hwmod omap54xx_gpio3_hwmod = { + .name = "gpio3", + .class = &omap54xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio4 */ +static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { + { .role = "dbclk", .clk = "gpio4_dbclk" }, +}; + +static struct omap_hwmod omap54xx_gpio4_hwmod = { + .name = "gpio4", + .class = &omap54xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio4_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio5 */ +static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { + { .role = "dbclk", .clk = "gpio5_dbclk" }, +}; + +static struct omap_hwmod omap54xx_gpio5_hwmod = { + .name = "gpio5", + .class = &omap54xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio5_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio6 */ +static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { + { .role = "dbclk", .clk = "gpio6_dbclk" }, +}; + +static struct omap_hwmod omap54xx_gpio6_hwmod = { + .name = "gpio6", + .class = &omap54xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio6_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio7 */ +static struct omap_hwmod_opt_clk gpio7_opt_clks[] = { + { .role = "dbclk", .clk = "gpio7_dbclk" }, +}; + +static struct omap_hwmod omap54xx_gpio7_hwmod = { + .name = "gpio7", + .class = &omap54xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio7_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio8 */ +static struct omap_hwmod_opt_clk gpio8_opt_clks[] = { + { .role = "dbclk", .clk = "gpio8_dbclk" }, +}; + +static struct omap_hwmod omap54xx_gpio8_hwmod = { + .name = "gpio8", + .class = &omap54xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio8_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* + * 'i2c' class + * multimaster high-speed i2c controller + */ + +static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = { + .sysc_offs = 0x0010, + .syss_offs = 0x0090, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .clockact = CLOCKACT_TEST_ICLK, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_i2c_hwmod_class = { + .name = "i2c", + .sysc = &omap54xx_i2c_sysc, + .reset = &omap_i2c_reset, + .rev = OMAP_I2C_IP_VERSION_2, +}; + +/* i2c dev_attr */ +static struct omap_i2c_dev_attr i2c_dev_attr = { + .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, +}; + +/* i2c1 */ +static struct omap_hwmod omap54xx_i2c1_hwmod = { + .name = "i2c1", + .class = &omap54xx_i2c_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "func_96m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* i2c2 */ +static struct omap_hwmod omap54xx_i2c2_hwmod = { + .name = "i2c2", + .class = &omap54xx_i2c_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "func_96m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* i2c3 */ +static struct omap_hwmod omap54xx_i2c3_hwmod = { + .name = "i2c3", + .class = &omap54xx_i2c_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "func_96m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* i2c4 */ +static struct omap_hwmod omap54xx_i2c4_hwmod = { + .name = "i2c4", + .class = &omap54xx_i2c_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "func_96m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* i2c5 */ +static struct omap_hwmod omap54xx_i2c5_hwmod = { + .name = "i2c5", + .class = &omap54xx_i2c_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "func_96m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* + * 'kbd' class + * keyboard controller + */ + +static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_kbd_hwmod_class = { + .name = "kbd", + .sysc = &omap54xx_kbd_sysc, +}; + +/* kbd */ +static struct omap_hwmod omap54xx_kbd_hwmod = { + .name = "kbd", + .class = &omap54xx_kbd_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .main_clk = "sys_32k_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'mcbsp' class + * multi channel buffered serial port controller + */ + +static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = { + .sysc_offs = 0x008c, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = { + .name = "mcbsp", + .sysc = &omap54xx_mcbsp_sysc, + .rev = MCBSP_CONFIG_TYPE4, +}; + +/* mcbsp1 */ +static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { + { .role = "pad_fck", .clk = "pad_clks_ck" }, + { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" }, +}; + +static struct omap_hwmod omap54xx_mcbsp1_hwmod = { + .name = "mcbsp1", + .class = &omap54xx_mcbsp_hwmod_class, + .clkdm_name = "abe_clkdm", + .main_clk = "mcbsp1_gfclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcbsp1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), +}; + +/* mcbsp2 */ +static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { + { .role = "pad_fck", .clk = "pad_clks_ck" }, + { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" }, +}; + +static struct omap_hwmod omap54xx_mcbsp2_hwmod = { + .name = "mcbsp2", + .class = &omap54xx_mcbsp_hwmod_class, + .clkdm_name = "abe_clkdm", + .main_clk = "mcbsp2_gfclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcbsp2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), +}; + +/* mcbsp3 */ +static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { + { .role = "pad_fck", .clk = "pad_clks_ck" }, + { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" }, +}; + +static struct omap_hwmod omap54xx_mcbsp3_hwmod = { + .name = "mcbsp3", + .class = &omap54xx_mcbsp_hwmod_class, + .clkdm_name = "abe_clkdm", + .main_clk = "mcbsp3_gfclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcbsp3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), +}; + +/* + * 'mcpdm' class + * multi channel pdm controller (proprietary interface with phoenix power + * ic) + */ + +static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = { + .name = "mcpdm", + .sysc = &omap54xx_mcpdm_sysc, +}; + +/* mcpdm */ +static struct omap_hwmod omap54xx_mcpdm_hwmod = { + .name = "mcpdm", + .class = &omap54xx_mcpdm_hwmod_class, + .clkdm_name = "abe_clkdm", + /* + * It's suspected that the McPDM requires an off-chip main + * functional clock, controlled via I2C. This IP block is + * currently reset very early during boot, before I2C is + * available, so it doesn't seem that we have any choice in + * the kernel other than to avoid resetting it. XXX This is + * really a hardware issue workaround: every IP block should + * be able to source its main functional clock from either + * on-chip or off-chip sources. McPDM seems to be the only + * current exception. + */ + + .flags = HWMOD_EXT_OPT_MAIN_CLK, + .main_clk = "pad_clks_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'mcspi' class + * multichannel serial port interface (mcspi) / master/slave synchronous serial + * bus + */ + +static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = { + .name = "mcspi", + .sysc = &omap54xx_mcspi_sysc, + .rev = OMAP4_MCSPI_REV, +}; + +/* mcspi1 */ +/* mcspi1 dev_attr */ +static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { + .num_chipselect = 4, +}; + +static struct omap_hwmod omap54xx_mcspi1_hwmod = { + .name = "mcspi1", + .class = &omap54xx_mcspi_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mcspi1_dev_attr, +}; + +/* mcspi2 */ +/* mcspi2 dev_attr */ +static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { + .num_chipselect = 2, +}; + +static struct omap_hwmod omap54xx_mcspi2_hwmod = { + .name = "mcspi2", + .class = &omap54xx_mcspi_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mcspi2_dev_attr, +}; + +/* mcspi3 */ +/* mcspi3 dev_attr */ +static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { + .num_chipselect = 2, +}; + +static struct omap_hwmod omap54xx_mcspi3_hwmod = { + .name = "mcspi3", + .class = &omap54xx_mcspi_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mcspi3_dev_attr, +}; + +/* mcspi4 */ +/* mcspi4 dev_attr */ +static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { + .num_chipselect = 1, +}; + +static struct omap_hwmod omap54xx_mcspi4_hwmod = { + .name = "mcspi4", + .class = &omap54xx_mcspi_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mcspi4_dev_attr, +}; + +/* + * 'mmc' class + * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller + */ + +static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | + SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap54xx_mmc_hwmod_class = { + .name = "mmc", + .sysc = &omap54xx_mmc_sysc, +}; + +/* mmc1 */ +static struct omap_hwmod_opt_clk mmc1_opt_clks[] = { + { .role = "32khz_clk", .clk = "mmc1_32khz_clk" }, +}; + +/* mmc1 dev_attr */ +static struct omap_mmc_dev_attr mmc1_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; + +static struct omap_hwmod omap54xx_mmc1_hwmod = { + .name = "mmc1", + .class = &omap54xx_mmc_hwmod_class, + .clkdm_name = "l3init_clkdm", + .main_clk = "mmc1_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mmc1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks), + .dev_attr = &mmc1_dev_attr, +}; + +/* mmc2 */ +static struct omap_hwmod omap54xx_mmc2_hwmod = { + .name = "mmc2", + .class = &omap54xx_mmc_hwmod_class, + .clkdm_name = "l3init_clkdm", + .main_clk = "mmc2_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* mmc3 */ +static struct omap_hwmod omap54xx_mmc3_hwmod = { + .name = "mmc3", + .class = &omap54xx_mmc_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* mmc4 */ +static struct omap_hwmod omap54xx_mmc4_hwmod = { + .name = "mmc4", + .class = &omap54xx_mmc_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* mmc5 */ +static struct omap_hwmod omap54xx_mmc5_hwmod = { + .name = "mmc5", + .class = &omap54xx_mmc_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_96m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'mpu' class + * mpu sub-system + */ + +static struct omap_hwmod_class omap54xx_mpu_hwmod_class = { + .name = "mpu", +}; + +/* mpu */ +static struct omap_hwmod omap54xx_mpu_hwmod = { + .name = "mpu", + .class = &omap54xx_mpu_hwmod_class, + .clkdm_name = "mpu_clkdm", + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, + .main_clk = "dpll_mpu_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET, + }, + }, +}; + +/* + * 'timer' class + * general purpose timer module with accurate 1ms tick + * This class contains several variants: ['timer_1ms', 'timer'] + */ + +static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, + .clockact = CLOCKACT_TEST_ICLK, +}; + +static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = { + .name = "timer", + .sysc = &omap54xx_timer_1ms_sysc, +}; + +static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap54xx_timer_hwmod_class = { + .name = "timer", + .sysc = &omap54xx_timer_sysc, +}; + +/* timer1 */ +static struct omap_hwmod omap54xx_timer1_hwmod = { + .name = "timer1", + .class = &omap54xx_timer_1ms_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .main_clk = "timer1_gfclk_mux", + .flags = HWMOD_SET_DEFAULT_CLOCKACT, + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer2 */ +static struct omap_hwmod omap54xx_timer2_hwmod = { + .name = "timer2", + .class = &omap54xx_timer_1ms_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "timer2_gfclk_mux", + .flags = HWMOD_SET_DEFAULT_CLOCKACT, + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer3 */ +static struct omap_hwmod omap54xx_timer3_hwmod = { + .name = "timer3", + .class = &omap54xx_timer_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "timer3_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer4 */ +static struct omap_hwmod omap54xx_timer4_hwmod = { + .name = "timer4", + .class = &omap54xx_timer_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "timer4_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer5 */ +static struct omap_hwmod omap54xx_timer5_hwmod = { + .name = "timer5", + .class = &omap54xx_timer_hwmod_class, + .clkdm_name = "abe_clkdm", + .main_clk = "timer5_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer6 */ +static struct omap_hwmod omap54xx_timer6_hwmod = { + .name = "timer6", + .class = &omap54xx_timer_hwmod_class, + .clkdm_name = "abe_clkdm", + .main_clk = "timer6_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer7 */ +static struct omap_hwmod omap54xx_timer7_hwmod = { + .name = "timer7", + .class = &omap54xx_timer_hwmod_class, + .clkdm_name = "abe_clkdm", + .main_clk = "timer7_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer8 */ +static struct omap_hwmod omap54xx_timer8_hwmod = { + .name = "timer8", + .class = &omap54xx_timer_hwmod_class, + .clkdm_name = "abe_clkdm", + .main_clk = "timer8_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer9 */ +static struct omap_hwmod omap54xx_timer9_hwmod = { + .name = "timer9", + .class = &omap54xx_timer_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "timer9_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer10 */ +static struct omap_hwmod omap54xx_timer10_hwmod = { + .name = "timer10", + .class = &omap54xx_timer_1ms_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "timer10_gfclk_mux", + .flags = HWMOD_SET_DEFAULT_CLOCKACT, + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer11 */ +static struct omap_hwmod omap54xx_timer11_hwmod = { + .name = "timer11", + .class = &omap54xx_timer_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "timer11_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'uart' class + * universal asynchronous receiver/transmitter (uart) + */ + +static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = { + .rev_offs = 0x0050, + .sysc_offs = 0x0054, + .syss_offs = 0x0058, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_uart_hwmod_class = { + .name = "uart", + .sysc = &omap54xx_uart_sysc, +}; + +/* uart1 */ +static struct omap_hwmod omap54xx_uart1_hwmod = { + .name = "uart1", + .class = &omap54xx_uart_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* uart2 */ +static struct omap_hwmod omap54xx_uart2_hwmod = { + .name = "uart2", + .class = &omap54xx_uart_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* uart3 */ +static struct omap_hwmod omap54xx_uart3_hwmod = { + .name = "uart3", + .class = &omap54xx_uart_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* uart4 */ +static struct omap_hwmod omap54xx_uart4_hwmod = { + .name = "uart4", + .class = &omap54xx_uart_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* uart5 */ +static struct omap_hwmod omap54xx_uart5_hwmod = { + .name = "uart5", + .class = &omap54xx_uart_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* uart6 */ +static struct omap_hwmod omap54xx_uart6_hwmod = { + .name = "uart6", + .class = &omap54xx_uart_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'usb_otg_ss' class + * 2.0 super speed (usb_otg_ss) controller + */ + +static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE | + SYSC_HAS_SIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = { + .name = "usb_otg_ss", + .sysc = &omap54xx_usb_otg_ss_sysc, +}; + +/* usb_otg_ss */ +static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = { + { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" }, +}; + +static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = { + .name = "usb_otg_ss", + .class = &omap54xx_usb_otg_ss_hwmod_class, + .clkdm_name = "l3init_clkdm", + .flags = HWMOD_SWSUP_SIDLE, + .main_clk = "dpll_core_h13x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = usb_otg_ss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks), +}; + +/* + * 'wd_timer' class + * 32-bit watchdog upward counter that generates a pulse on the reset pin on + * overflow condition + */ + +static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = { + .name = "wd_timer", + .sysc = &omap54xx_wd_timer_sysc, + .pre_shutdown = &omap2_wd_timer_disable, +}; + +/* wd_timer2 */ +static struct omap_hwmod omap54xx_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap54xx_wd_timer_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .main_clk = "sys_32k_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + + +/* + * Interfaces + */ + +/* l3_main_1 -> dmm */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = { + .master = &omap54xx_l3_main_1_hwmod, + .slave = &omap54xx_dmm_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_SDMA, +}; + +/* l3_main_3 -> l3_instr */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = { + .master = &omap54xx_l3_main_3_hwmod, + .slave = &omap54xx_l3_instr_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = { + .master = &omap54xx_l3_main_2_hwmod, + .slave = &omap54xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = { + .master = &omap54xx_l4_cfg_hwmod, + .slave = &omap54xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = { + .master = &omap54xx_mpu_hwmod, + .slave = &omap54xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU, +}; + +/* l3_main_1 -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = { + .master = &omap54xx_l3_main_1_hwmod, + .slave = &omap54xx_l3_main_2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU, +}; + +/* l4_cfg -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = { + .master = &omap54xx_l4_cfg_hwmod, + .slave = &omap54xx_l3_main_2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = { + .master = &omap54xx_l3_main_1_hwmod, + .slave = &omap54xx_l3_main_3_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU, +}; + +/* l3_main_2 -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = { + .master = &omap54xx_l3_main_2_hwmod, + .slave = &omap54xx_l3_main_3_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = { + .master = &omap54xx_l4_cfg_hwmod, + .slave = &omap54xx_l3_main_3_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l4_abe */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = { + .master = &omap54xx_l3_main_1_hwmod, + .slave = &omap54xx_l4_abe_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> l4_abe */ +static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = { + .master = &omap54xx_mpu_hwmod, + .slave = &omap54xx_l4_abe_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l4_cfg */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = { + .master = &omap54xx_l3_main_1_hwmod, + .slave = &omap54xx_l4_cfg_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> l4_per */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = { + .master = &omap54xx_l3_main_2_hwmod, + .slave = &omap54xx_l4_per_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l4_wkup */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = { + .master = &omap54xx_l3_main_1_hwmod, + .slave = &omap54xx_l4_wkup_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> mpu_private */ +static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = { + .master = &omap54xx_mpu_hwmod, + .slave = &omap54xx_mpu_private_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> counter_32k */ +static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = { + .master = &omap54xx_l4_wkup_hwmod, + .slave = &omap54xx_counter_32k_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = { + { + .pa_start = 0x4a056000, + .pa_end = 0x4a056fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> dma_system */ +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = { + .master = &omap54xx_l4_cfg_hwmod, + .slave = &omap54xx_dma_system_hwmod, + .clk = "l4_root_clk_div", + .addr = omap54xx_dma_system_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_abe -> dmic */ +static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = { + .master = &omap54xx_l4_abe_hwmod, + .slave = &omap54xx_dmic_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU, +}; + +/* mpu -> emif1 */ +static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = { + .master = &omap54xx_mpu_hwmod, + .slave = &omap54xx_emif1_hwmod, + .clk = "dpll_core_h11x2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> emif2 */ +static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = { + .master = &omap54xx_mpu_hwmod, + .slave = &omap54xx_emif2_hwmod, + .clk = "dpll_core_h11x2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = { + .master = &omap54xx_l4_wkup_hwmod, + .slave = &omap54xx_gpio1_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio2 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_gpio2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio3 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_gpio3_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio4 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_gpio4_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio5 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_gpio5_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio6 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_gpio6_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio7 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_gpio7_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio8 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_gpio8_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> i2c1 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_i2c1_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> i2c2 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_i2c2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> i2c3 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_i2c3_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> i2c4 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_i2c4_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> i2c5 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_i2c5_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> kbd */ +static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = { + .master = &omap54xx_l4_wkup_hwmod, + .slave = &omap54xx_kbd_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_abe -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = { + .master = &omap54xx_l4_abe_hwmod, + .slave = &omap54xx_mcbsp1_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU, +}; + +/* l4_abe -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = { + .master = &omap54xx_l4_abe_hwmod, + .slave = &omap54xx_mcbsp2_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU, +}; + +/* l4_abe -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = { + .master = &omap54xx_l4_abe_hwmod, + .slave = &omap54xx_mcbsp3_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU, +}; + +/* l4_abe -> mcpdm */ +static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = { + .master = &omap54xx_l4_abe_hwmod, + .slave = &omap54xx_mcpdm_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU, +}; + +/* l4_per -> mcspi1 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_mcspi1_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> mcspi2 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_mcspi2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> mcspi3 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_mcspi3_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> mcspi4 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_mcspi4_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> mmc1 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_mmc1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> mmc2 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_mmc2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> mmc3 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_mmc3_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> mmc4 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_mmc4_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> mmc5 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_mmc5_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> mpu */ +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = { + .master = &omap54xx_l4_cfg_hwmod, + .slave = &omap54xx_mpu_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = { + .master = &omap54xx_l4_wkup_hwmod, + .slave = &omap54xx_timer1_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> timer2 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_timer2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> timer3 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_timer3_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> timer4 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_timer4_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_abe -> timer5 */ +static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = { + .master = &omap54xx_l4_abe_hwmod, + .slave = &omap54xx_timer5_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU, +}; + +/* l4_abe -> timer6 */ +static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = { + .master = &omap54xx_l4_abe_hwmod, + .slave = &omap54xx_timer6_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU, +}; + +/* l4_abe -> timer7 */ +static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = { + .master = &omap54xx_l4_abe_hwmod, + .slave = &omap54xx_timer7_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU, +}; + +/* l4_abe -> timer8 */ +static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = { + .master = &omap54xx_l4_abe_hwmod, + .slave = &omap54xx_timer8_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU, +}; + +/* l4_per -> timer9 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_timer9_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> timer10 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_timer10_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> timer11 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_timer11_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> uart1 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_uart1_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> uart2 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_uart2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> uart3 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_uart3_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> uart4 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_uart4_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> uart5 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_uart5_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> uart6 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_uart6_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> usb_otg_ss */ +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = { + .master = &omap54xx_l4_cfg_hwmod, + .slave = &omap54xx_usb_otg_ss_hwmod, + .clk = "dpll_core_h13x2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = { + .master = &omap54xx_l4_wkup_hwmod, + .slave = &omap54xx_wd_timer2_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { + &omap54xx_l3_main_1__dmm, + &omap54xx_l3_main_3__l3_instr, + &omap54xx_l3_main_2__l3_main_1, + &omap54xx_l4_cfg__l3_main_1, + &omap54xx_mpu__l3_main_1, + &omap54xx_l3_main_1__l3_main_2, + &omap54xx_l4_cfg__l3_main_2, + &omap54xx_l3_main_1__l3_main_3, + &omap54xx_l3_main_2__l3_main_3, + &omap54xx_l4_cfg__l3_main_3, + &omap54xx_l3_main_1__l4_abe, + &omap54xx_mpu__l4_abe, + &omap54xx_l3_main_1__l4_cfg, + &omap54xx_l3_main_2__l4_per, + &omap54xx_l3_main_1__l4_wkup, + &omap54xx_mpu__mpu_private, + &omap54xx_l4_wkup__counter_32k, + &omap54xx_l4_cfg__dma_system, + &omap54xx_l4_abe__dmic, + &omap54xx_mpu__emif1, + &omap54xx_mpu__emif2, + &omap54xx_l4_wkup__gpio1, + &omap54xx_l4_per__gpio2, + &omap54xx_l4_per__gpio3, + &omap54xx_l4_per__gpio4, + &omap54xx_l4_per__gpio5, + &omap54xx_l4_per__gpio6, + &omap54xx_l4_per__gpio7, + &omap54xx_l4_per__gpio8, + &omap54xx_l4_per__i2c1, + &omap54xx_l4_per__i2c2, + &omap54xx_l4_per__i2c3, + &omap54xx_l4_per__i2c4, + &omap54xx_l4_per__i2c5, + &omap54xx_l4_wkup__kbd, + &omap54xx_l4_abe__mcbsp1, + &omap54xx_l4_abe__mcbsp2, + &omap54xx_l4_abe__mcbsp3, + &omap54xx_l4_abe__mcpdm, + &omap54xx_l4_per__mcspi1, + &omap54xx_l4_per__mcspi2, + &omap54xx_l4_per__mcspi3, + &omap54xx_l4_per__mcspi4, + &omap54xx_l4_per__mmc1, + &omap54xx_l4_per__mmc2, + &omap54xx_l4_per__mmc3, + &omap54xx_l4_per__mmc4, + &omap54xx_l4_per__mmc5, + &omap54xx_l4_cfg__mpu, + &omap54xx_l4_wkup__timer1, + &omap54xx_l4_per__timer2, + &omap54xx_l4_per__timer3, + &omap54xx_l4_per__timer4, + &omap54xx_l4_abe__timer5, + &omap54xx_l4_abe__timer6, + &omap54xx_l4_abe__timer7, + &omap54xx_l4_abe__timer8, + &omap54xx_l4_per__timer9, + &omap54xx_l4_per__timer10, + &omap54xx_l4_per__timer11, + &omap54xx_l4_per__uart1, + &omap54xx_l4_per__uart2, + &omap54xx_l4_per__uart3, + &omap54xx_l4_per__uart4, + &omap54xx_l4_per__uart5, + &omap54xx_l4_per__uart6, + &omap54xx_l4_cfg__usb_otg_ss, + &omap54xx_l4_wkup__wd_timer2, + NULL, +}; + +int __init omap54xx_hwmod_init(void) +{ + omap_hwmod_init(); + return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs); +} diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index c01859398b5..5a2d8034c8d 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -546,8 +546,10 @@ static void __init prcm_setup_regs(void) /* Clear any pending PRCM interrupts */ omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); - if (omap3_has_iva()) - omap3_iva_idle(); + /* + * We need to idle iva2_pwrdm even on am3703 with no iva2. + */ + omap3_iva_idle(); omap3_d2d_idle(); } diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index a251f87fa2a..82f0698933d 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -1,7 +1,7 @@ /* - * OMAP4 Power Management Routines + * OMAP4+ Power Management Routines * - * Copyright (C) 2010-2011 Texas Instruments, Inc. + * Copyright (C) 2010-2013 Texas Instruments, Inc. * Rajendra Nayak <rnayak@ti.com> * Santosh Shilimkar <santosh.shilimkar@ti.com> * @@ -135,16 +135,16 @@ static void omap_default_idle(void) } /** - * omap4_pm_init - Init routine for OMAP4 PM + * omap4_init_static_deps - Add OMAP4 static dependencies * - * Initializes all powerdomain and clockdomain target states - * and all PRCM settings. + * Add needed static clockdomain dependencies on OMAP4 devices. + * Return: 0 on success or 'err' on failures */ -int __init omap4_pm_init(void) +static inline int omap4_init_static_deps(void) { - int ret; struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm; struct clockdomain *ducati_clkdm, *l3_2_clkdm; + int ret = 0; if (omap_rev() == OMAP4430_REV_ES1_0) { WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); @@ -163,7 +163,7 @@ int __init omap4_pm_init(void) ret = pwrdm_for_each(pwrdms_setup, NULL); if (ret) { pr_err("Failed to setup powerdomains\n"); - goto err2; + return ret; } /* @@ -171,6 +171,10 @@ int __init omap4_pm_init(void) * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as * expected. The hardware recommendation is to enable static * dependencies for these to avoid system lock ups or random crashes. + * The L4 wakeup depedency is added to workaround the OCP sync hardware + * BUG with 32K synctimer which lead to incorrect timer value read + * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which + * are part of L4 wakeup clockdomain. */ mpuss_clkdm = clkdm_lookup("mpuss_clkdm"); emif_clkdm = clkdm_lookup("l3_emif_clkdm"); @@ -179,7 +183,7 @@ int __init omap4_pm_init(void) ducati_clkdm = clkdm_lookup("ducati_clkdm"); if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || (!l3_2_clkdm) || (!ducati_clkdm)) - goto err2; + return -EINVAL; ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm); ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm); @@ -188,9 +192,42 @@ int __init omap4_pm_init(void) ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm); if (ret) { pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n"); + return -EINVAL; + } + + return ret; +} + +/** + * omap4_pm_init - Init routine for OMAP4+ devices + * + * Initializes all powerdomain and clockdomain target states + * and all PRCM settings. + * Return: Returns the error code returned by called functions. + */ +int __init omap4_pm_init(void) +{ + int ret = 0; + + if (omap_rev() == OMAP4430_REV_ES1_0) { + WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); + return -ENODEV; + } + + pr_info("Power Management for TI OMAP4+ devices.\n"); + + ret = pwrdm_for_each(pwrdms_setup, NULL); + if (ret) { + pr_err("Failed to setup powerdomains.\n"); goto err2; } + if (cpu_is_omap44xx()) { + ret = omap4_init_static_deps(); + if (ret) + goto err2; + } + ret = omap4_mpuss_init(); if (ret) { pr_err("Failed to initialise OMAP4 MPUSS\n"); @@ -206,7 +243,8 @@ int __init omap4_pm_init(void) /* Overwrite the default cpu_do_idle() */ arm_pm_idle = omap_default_idle; - omap4_idle_init(); + if (cpu_is_omap44xx()) + omap4_idle_init(); err2: return ret; diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 86babd740d4..e233dfcbc18 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -102,6 +102,10 @@ static int _pwrdm_register(struct powerdomain *pwrdm) if (_pwrdm_lookup(pwrdm->name)) return -EEXIST; + if (arch_pwrdm && arch_pwrdm->pwrdm_has_voltdm) + if (!arch_pwrdm->pwrdm_has_voltdm()) + goto skip_voltdm; + voltdm = voltdm_lookup(pwrdm->voltdm.name); if (!voltdm) { pr_err("powerdomain: %s: voltagedomain %s does not exist\n", @@ -111,6 +115,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm) pwrdm->voltdm.ptr = voltdm; INIT_LIST_HEAD(&pwrdm->voltdm_node); voltdm_add_pwrdm(voltdm, pwrdm); +skip_voltdm: spin_lock_init(&pwrdm->_lock); list_add(&pwrdm->node, &pwrdm_list); diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index 140c36074fe..e4d7bd6f94b 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -166,6 +166,7 @@ struct powerdomain { * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep * @pwrdm_wait_transition: Wait for a pd state transition to complete + * @pwrdm_has_voltdm: Check if a voltdm association is needed * * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family * chips, a powerdomain's power state is not allowed to directly @@ -196,6 +197,7 @@ struct pwrdm_ops { int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm); int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm); int (*pwrdm_wait_transition)(struct powerdomain *pwrdm); + int (*pwrdm_has_voltdm)(void); }; int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs); @@ -253,6 +255,7 @@ extern void omap243x_powerdomains_init(void); extern void omap3xxx_powerdomains_init(void); extern void am33xx_powerdomains_init(void); extern void omap44xx_powerdomains_init(void); +extern void omap54xx_powerdomains_init(void); extern struct pwrdm_ops omap2_pwrdm_operations; extern struct pwrdm_ops omap3_pwrdm_operations; diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index f0e14e9efe5..e2d4bd80452 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -336,6 +336,54 @@ static struct powerdomain dpll5_pwrdm = { .voltdm = { .name = "core" }, }; +static struct powerdomain device_81xx_pwrdm = { + .name = "device_pwrdm", + .prcm_offs = TI81XX_PRM_DEVICE_MOD, + .voltdm = { .name = "core" }, +}; + +static struct powerdomain active_816x_pwrdm = { + .name = "active_pwrdm", + .prcm_offs = TI816X_PRM_ACTIVE_MOD, + .pwrsts = PWRSTS_OFF_ON, + .voltdm = { .name = "core" }, +}; + +static struct powerdomain default_816x_pwrdm = { + .name = "default_pwrdm", + .prcm_offs = TI81XX_PRM_DEFAULT_MOD, + .pwrsts = PWRSTS_OFF_ON, + .voltdm = { .name = "core" }, +}; + +static struct powerdomain ivahd0_816x_pwrdm = { + .name = "ivahd0_pwrdm", + .prcm_offs = TI816X_PRM_IVAHD0_MOD, + .pwrsts = PWRSTS_OFF_ON, + .voltdm = { .name = "mpu_iva" }, +}; + +static struct powerdomain ivahd1_816x_pwrdm = { + .name = "ivahd1_pwrdm", + .prcm_offs = TI816X_PRM_IVAHD1_MOD, + .pwrsts = PWRSTS_OFF_ON, + .voltdm = { .name = "mpu_iva" }, +}; + +static struct powerdomain ivahd2_816x_pwrdm = { + .name = "ivahd2_pwrdm", + .prcm_offs = TI816X_PRM_IVAHD2_MOD, + .pwrsts = PWRSTS_OFF_ON, + .voltdm = { .name = "mpu_iva" }, +}; + +static struct powerdomain sgx_816x_pwrdm = { + .name = "sgx_pwrdm", + .prcm_offs = TI816X_PRM_SGX_MOD, + .pwrsts = PWRSTS_OFF_ON, + .voltdm = { .name = "core" }, +}; + /* As powerdomains are added or removed above, this list must also be changed */ static struct powerdomain *powerdomains_omap3430_common[] __initdata = { &wkup_omap2_pwrdm, @@ -393,6 +441,17 @@ static struct powerdomain *powerdomains_am35x[] __initdata = { NULL }; +static struct powerdomain *powerdomains_ti81xx[] __initdata = { + &device_81xx_pwrdm, + &active_816x_pwrdm, + &default_816x_pwrdm, + &ivahd0_816x_pwrdm, + &ivahd1_816x_pwrdm, + &ivahd2_816x_pwrdm, + &sgx_816x_pwrdm, + NULL +}; + void __init omap3xxx_powerdomains_init(void) { unsigned int rev; @@ -406,6 +465,9 @@ void __init omap3xxx_powerdomains_init(void) if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { pwrdm_register_pwrdms(powerdomains_am35x); + } else if (rev == TI8168_REV_ES1_0 || rev == TI8168_REV_ES1_1 + || rev == TI8168_REV_ES2_0 || rev == TI8168_REV_ES2_1) { + pwrdm_register_pwrdms(powerdomains_ti81xx); } else { pwrdm_register_pwrdms(powerdomains_omap3430_common); diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c new file mode 100644 index 00000000000..81f8a7cc26e --- /dev/null +++ b/arch/arm/mach-omap2/powerdomains54xx_data.c @@ -0,0 +1,331 @@ +/* + * OMAP54XX Power domains framework + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Abhijit Pagare (abhijitpagare@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * Paul Walmsley (paul@pwsan.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> + +#include "powerdomain.h" + +#include "prcm-common.h" +#include "prcm44xx.h" +#include "prm-regbits-54xx.h" +#include "prm54xx.h" +#include "prcm_mpu54xx.h" + +/* core_54xx_pwrdm: CORE power domain */ +static struct powerdomain core_54xx_pwrdm = { + .name = "core_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_CORE_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 5, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* core_nret_bank */ + [1] = PWRSTS_OFF_RET, /* core_ocmram */ + [2] = PWRSTS_OFF_RET, /* core_other_bank */ + [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ + [4] = PWRSTS_OFF_RET, /* ipu_unicache */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* core_nret_bank */ + [1] = PWRSTS_OFF_RET, /* core_ocmram */ + [2] = PWRSTS_OFF_RET, /* core_other_bank */ + [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ + [4] = PWRSTS_OFF_RET, /* ipu_unicache */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* abe_54xx_pwrdm: Audio back end power domain */ +static struct powerdomain abe_54xx_pwrdm = { + .name = "abe_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_ABE_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* aessmem */ + [1] = PWRSTS_OFF_RET, /* periphmem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* aessmem */ + [1] = PWRSTS_OFF_RET, /* periphmem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */ +static struct powerdomain coreaon_54xx_pwrdm = { + .name = "coreaon_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_COREAON_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_ON, +}; + +/* dss_54xx_pwrdm: Display subsystem power domain */ +static struct powerdomain dss_54xx_pwrdm = { + .name = "dss_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_DSS_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* dss_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* dss_mem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ +static struct powerdomain cpu0_54xx_pwrdm = { + .name = "cpu0_pwrdm", + .voltdm = { .name = "mpu" }, + .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C0_INST, + .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_ON, /* cpu0_l1 */ + }, +}; + +/* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ +static struct powerdomain cpu1_54xx_pwrdm = { + .name = "cpu1_pwrdm", + .voltdm = { .name = "mpu" }, + .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C1_INST, + .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_ON, /* cpu1_l1 */ + }, +}; + +/* emu_54xx_pwrdm: Emulation power domain */ +static struct powerdomain emu_54xx_pwrdm = { + .name = "emu_pwrdm", + .voltdm = { .name = "wkup" }, + .prcm_offs = OMAP54XX_PRM_EMU_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* emu_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* emu_bank */ + }, +}; + +/* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */ +static struct powerdomain mpu_54xx_pwrdm = { + .name = "mpu_pwrdm", + .voltdm = { .name = "mpu" }, + .prcm_offs = OMAP54XX_PRM_MPU_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* mpu_l2 */ + [1] = PWRSTS_RET, /* mpu_ram */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* mpu_l2 */ + [1] = PWRSTS_OFF_RET, /* mpu_ram */ + }, +}; + +/* custefuse_54xx_pwrdm: Customer efuse controller power domain */ +static struct powerdomain custefuse_54xx_pwrdm = { + .name = "custefuse_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_CUSTEFUSE_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* dsp_54xx_pwrdm: Tesla processor power domain */ +static struct powerdomain dsp_54xx_pwrdm = { + .name = "dsp_pwrdm", + .voltdm = { .name = "mm" }, + .prcm_offs = OMAP54XX_PRM_DSP_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 3, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* dsp_edma */ + [1] = PWRSTS_OFF_RET, /* dsp_l1 */ + [2] = PWRSTS_OFF_RET, /* dsp_l2 */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* dsp_edma */ + [1] = PWRSTS_OFF_RET, /* dsp_l1 */ + [2] = PWRSTS_OFF_RET, /* dsp_l2 */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* cam_54xx_pwrdm: Camera subsystem power domain */ +static struct powerdomain cam_54xx_pwrdm = { + .name = "cam_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_CAM_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* cam_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* cam_mem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* l3init_54xx_pwrdm: L3 initators pheripherals power domain */ +static struct powerdomain l3init_54xx_pwrdm = { + .name = "l3init_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_L3INIT_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* l3init_bank1 */ + [1] = PWRSTS_OFF_RET, /* l3init_bank2 */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* l3init_bank1 */ + [1] = PWRSTS_OFF_RET, /* l3init_bank2 */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* gpu_54xx_pwrdm: 3D accelerator power domain */ +static struct powerdomain gpu_54xx_pwrdm = { + .name = "gpu_pwrdm", + .voltdm = { .name = "mm" }, + .prcm_offs = OMAP54XX_PRM_GPU_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* gpu_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* gpu_mem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* wkupaon_54xx_pwrdm: Wake-up power domain */ +static struct powerdomain wkupaon_54xx_pwrdm = { + .name = "wkupaon_pwrdm", + .voltdm = { .name = "wkup" }, + .prcm_offs = OMAP54XX_PRM_WKUPAON_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_ON, + .banks = 1, + .pwrsts_mem_ret = { + }, + .pwrsts_mem_on = { + [0] = PWRSTS_ON, /* wkup_bank */ + }, +}; + +/* iva_54xx_pwrdm: IVA-HD power domain */ +static struct powerdomain iva_54xx_pwrdm = { + .name = "iva_pwrdm", + .voltdm = { .name = "mm" }, + .prcm_offs = OMAP54XX_PRM_IVA_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF, + .banks = 4, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* hwa_mem */ + [1] = PWRSTS_OFF_RET, /* sl2_mem */ + [2] = PWRSTS_OFF_RET, /* tcm1_mem */ + [3] = PWRSTS_OFF_RET, /* tcm2_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* hwa_mem */ + [1] = PWRSTS_OFF_RET, /* sl2_mem */ + [2] = PWRSTS_OFF_RET, /* tcm1_mem */ + [3] = PWRSTS_OFF_RET, /* tcm2_mem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* + * The following power domains are not under SW control + * + * mpuaon + * mmaon + */ + +/* As powerdomains are added or removed above, this list must also be changed */ +static struct powerdomain *powerdomains_omap54xx[] __initdata = { + &core_54xx_pwrdm, + &abe_54xx_pwrdm, + &coreaon_54xx_pwrdm, + &dss_54xx_pwrdm, + &cpu0_54xx_pwrdm, + &cpu1_54xx_pwrdm, + &emu_54xx_pwrdm, + &mpu_54xx_pwrdm, + &custefuse_54xx_pwrdm, + &dsp_54xx_pwrdm, + &cam_54xx_pwrdm, + &l3init_54xx_pwrdm, + &gpu_54xx_pwrdm, + &wkupaon_54xx_pwrdm, + &iva_54xx_pwrdm, + NULL +}; + +void __init omap54xx_powerdomains_init(void) +{ + pwrdm_register_platform_funcs(&omap4_pwrdm_operations); + pwrdm_register_pwrdms(powerdomains_omap54xx); + pwrdm_complete_init(); +} diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index c7d355fafd2..ff1ac4a82a0 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -48,6 +48,17 @@ #define OMAP3430_NEON_MOD 0xb00 #define OMAP3430ES2_USBHOST_MOD 0xc00 +/* + * TI81XX PRM module offsets + */ +#define TI81XX_PRM_DEVICE_MOD 0x0000 +#define TI816X_PRM_ACTIVE_MOD 0x0a00 +#define TI81XX_PRM_DEFAULT_MOD 0x0b00 +#define TI816X_PRM_IVAHD0_MOD 0x0c00 +#define TI816X_PRM_IVAHD1_MOD 0x0d00 +#define TI816X_PRM_IVAHD2_MOD 0x0e00 +#define TI816X_PRM_SGX_MOD 0x0f00 + /* 24XX register bits shared between CM & PRM registers */ /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h index 7334ffb9d2c..f429cdd5a11 100644 --- a/arch/arm/mach-omap2/prcm44xx.h +++ b/arch/arm/mach-omap2/prcm44xx.h @@ -32,6 +32,12 @@ #define OMAP4430_SCRM_PARTITION 4 #define OMAP4430_PRCM_MPU_PARTITION 5 +#define OMAP54XX_PRM_PARTITION 1 +#define OMAP54XX_CM_CORE_AON_PARTITION 2 +#define OMAP54XX_CM_CORE_PARTITION 3 +#define OMAP54XX_SCRM_PARTITION 4 +#define OMAP54XX_PRCM_MPU_PARTITION 5 + /* * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition * IDs, plus one diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h index 884af7bb4af..059bd4f4903 100644 --- a/arch/arm/mach-omap2/prcm_mpu44xx.h +++ b/arch/arm/mach-omap2/prcm_mpu44xx.h @@ -25,12 +25,9 @@ #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H +#include "prcm_mpu_44xx_54xx.h" #include "common.h" -# ifndef __ASSEMBLER__ -extern void __iomem *prcm_mpu_base; -# endif - #define OMAP4430_PRCM_MPU_BASE 0x48243000 #define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \ @@ -98,13 +95,4 @@ extern void __iomem *prcm_mpu_base; #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018 #define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018) -/* Function prototypes */ -# ifndef __ASSEMBLER__ -extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx); -extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx); -extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, - s16 idx); -extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu); -# endif - #endif diff --git a/arch/arm/mach-omap2/prcm_mpu54xx.h b/arch/arm/mach-omap2/prcm_mpu54xx.h new file mode 100644 index 00000000000..bc2ce328831 --- /dev/null +++ b/arch/arm/mach-omap2/prcm_mpu54xx.h @@ -0,0 +1,87 @@ +/* + * OMAP54xx PRCM MPU instance offset macros + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H +#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H + +#include "prcm_mpu_44xx_54xx.h" +#include "common.h" + +#define OMAP54XX_PRCM_MPU_BASE 0x48243000 + +#define OMAP54XX_PRCM_MPU_REGADDR(inst, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg)) + +/* PRCM_MPU instances */ +#define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST 0x0000 +#define OMAP54XX_PRCM_MPU_DEVICE_INST 0x0200 +#define OMAP54XX_PRCM_MPU_PRM_C0_INST 0x0400 +#define OMAP54XX_PRCM_MPU_CM_C0_INST 0x0600 +#define OMAP54XX_PRCM_MPU_PRM_C1_INST 0x0800 +#define OMAP54XX_PRCM_MPU_CM_C1_INST 0x0a00 + +/* PRCM_MPU clockdomain register offsets (from instance start) */ +#define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000 +#define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000 + + +/* + * PRCM_MPU + * + * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global) + * point of view the PRCM_MPU is a single entity. It shares the same + * programming model as the global PRCM and thus can be assimilate as two new + * MOD inside the PRCM + */ + +/* PRCM_MPU.PRCM_MPU_OCP_SOCKET register offsets */ +#define OMAP54XX_REVISION_PRCM_MPU_OFFSET 0x0000 + +/* PRCM_MPU.PRCM_MPU_DEVICE register offsets */ +#define OMAP54XX_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 +#define OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 +#define OMAP54XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010 +#define OMAP54XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014 + +/* PRCM_MPU.PRCM_MPU_PRM_C0 register offsets */ +#define OMAP54XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_CPU0_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010 +#define OMAP54XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014 +#define OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024 + +/* PRCM_MPU.PRCM_MPU_CM_C0 register offsets */ +#define OMAP54XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C0_INST, 0x0020) + +/* PRCM_MPU.PRCM_MPU_PRM_C1 register offsets */ +#define OMAP54XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_CPU1_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010 +#define OMAP54XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014 +#define OMAP54XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024 + +/* PRCM_MPU.PRCM_MPU_CM_C1 register offsets */ +#define OMAP54XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C1_INST, 0x0020) + +#endif diff --git a/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h new file mode 100644 index 00000000000..ca149e70bed --- /dev/null +++ b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h @@ -0,0 +1,36 @@ +/* + * OMAP44xx and OMAP54xx PRCM MPU function prototypes + * + * Copyright (C) 2010, 2013 Texas Instruments, Inc. + * Copyright (C) 2010 Nokia Corporation + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H +#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H + +#ifndef __ASSEMBLER__ +extern void __iomem *prcm_mpu_base; + +extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx); +extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx); +extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, + s16 idx); +extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu); +#endif + +#endif diff --git a/arch/arm/mach-omap2/prm-regbits-54xx.h b/arch/arm/mach-omap2/prm-regbits-54xx.h new file mode 100644 index 00000000000..be31b21aa9c --- /dev/null +++ b/arch/arm/mach-omap2/prm-regbits-54xx.h @@ -0,0 +1,2701 @@ +/* + * OMAP54xx Power Management register bits + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H +#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ABBOFF_ACT_SHIFT 1 +#define OMAP54XX_ABBOFF_ACT_WIDTH 0x1 +#define OMAP54XX_ABBOFF_ACT_MASK (1 << 1) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ABBOFF_SLEEP_SHIFT 2 +#define OMAP54XX_ABBOFF_SLEEP_WIDTH 0x1 +#define OMAP54XX_ABBOFF_SLEEP_MASK (1 << 2) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_ABB_MM_DONE_EN_SHIFT 31 +#define OMAP54XX_ABB_MM_DONE_EN_WIDTH 0x1 +#define OMAP54XX_ABB_MM_DONE_EN_MASK (1 << 31) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_ABB_MM_DONE_ST_SHIFT 31 +#define OMAP54XX_ABB_MM_DONE_ST_WIDTH 0x1 +#define OMAP54XX_ABB_MM_DONE_ST_MASK (1 << 31) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_ABB_MPU_DONE_EN_SHIFT 7 +#define OMAP54XX_ABB_MPU_DONE_EN_WIDTH 0x1 +#define OMAP54XX_ABB_MPU_DONE_EN_MASK (1 << 7) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_ABB_MPU_DONE_ST_SHIFT 7 +#define OMAP54XX_ABB_MPU_DONE_ST_WIDTH 0x1 +#define OMAP54XX_ABB_MPU_DONE_ST_MASK (1 << 7) + +/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ +#define OMAP54XX_ACTIVE_FBB_SEL_SHIFT 2 +#define OMAP54XX_ACTIVE_FBB_SEL_WIDTH 0x1 +#define OMAP54XX_ACTIVE_FBB_SEL_MASK (1 << 2) + +/* Used by PM_ABE_PWRSTCTRL */ +#define OMAP54XX_AESSMEM_ONSTATE_SHIFT 16 +#define OMAP54XX_AESSMEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_AESSMEM_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_ABE_PWRSTCTRL */ +#define OMAP54XX_AESSMEM_RETSTATE_SHIFT 8 +#define OMAP54XX_AESSMEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_AESSMEM_RETSTATE_MASK (1 << 8) + +/* Used by PM_ABE_PWRSTST */ +#define OMAP54XX_AESSMEM_STATEST_SHIFT 4 +#define OMAP54XX_AESSMEM_STATEST_WIDTH 0x2 +#define OMAP54XX_AESSMEM_STATEST_MASK (0x3 << 4) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_AIPOFF_SHIFT 8 +#define OMAP54XX_AIPOFF_WIDTH 0x1 +#define OMAP54XX_AIPOFF_MASK (1 << 8) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_SHIFT 0 +#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_WIDTH 0x2 +#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_AUTO_CTRL_VDD_MM_L_SHIFT 4 +#define OMAP54XX_AUTO_CTRL_VDD_MM_L_WIDTH 0x2 +#define OMAP54XX_AUTO_CTRL_VDD_MM_L_MASK (0x3 << 4) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_SHIFT 2 +#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_WIDTH 0x2 +#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2) + +/* Used by PRM_VC_BYPASS_ERRST */ +#define OMAP54XX_BYPS_RA_ERR_SHIFT 1 +#define OMAP54XX_BYPS_RA_ERR_WIDTH 0x1 +#define OMAP54XX_BYPS_RA_ERR_MASK (1 << 1) + +/* Used by PRM_VC_BYPASS_ERRST */ +#define OMAP54XX_BYPS_SA_ERR_SHIFT 0 +#define OMAP54XX_BYPS_SA_ERR_WIDTH 0x1 +#define OMAP54XX_BYPS_SA_ERR_MASK (1 << 0) + +/* Used by PRM_VC_BYPASS_ERRST */ +#define OMAP54XX_BYPS_TIMEOUT_ERR_SHIFT 2 +#define OMAP54XX_BYPS_TIMEOUT_ERR_WIDTH 0x1 +#define OMAP54XX_BYPS_TIMEOUT_ERR_MASK (1 << 2) + +/* Used by PRM_RSTST */ +#define OMAP54XX_C2C_RST_SHIFT 10 +#define OMAP54XX_C2C_RST_WIDTH 0x1 +#define OMAP54XX_C2C_RST_MASK (1 << 10) + +/* Used by PM_CAM_PWRSTCTRL */ +#define OMAP54XX_CAM_MEM_ONSTATE_SHIFT 16 +#define OMAP54XX_CAM_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_CAM_MEM_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_CAM_PWRSTST */ +#define OMAP54XX_CAM_MEM_STATEST_SHIFT 4 +#define OMAP54XX_CAM_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_CAM_MEM_STATEST_MASK (0x3 << 4) + +/* Used by PRM_CLKREQCTRL */ +#define OMAP54XX_CLKREQ_COND_SHIFT 0 +#define OMAP54XX_CLKREQ_COND_WIDTH 0x3 +#define OMAP54XX_CLKREQ_COND_MASK (0x7 << 0) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_CMDRA_VDD_CORE_L_SHIFT 16 +#define OMAP54XX_CMDRA_VDD_CORE_L_WIDTH 0x8 +#define OMAP54XX_CMDRA_VDD_CORE_L_MASK (0xff << 16) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_CMDRA_VDD_MM_L_SHIFT 16 +#define OMAP54XX_CMDRA_VDD_MM_L_WIDTH 0x8 +#define OMAP54XX_CMDRA_VDD_MM_L_MASK (0xff << 16) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_CMDRA_VDD_MPU_L_SHIFT 16 +#define OMAP54XX_CMDRA_VDD_MPU_L_WIDTH 0x8 +#define OMAP54XX_CMDRA_VDD_MPU_L_MASK (0xff << 16) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_CMD_VDD_CORE_L_SHIFT 28 +#define OMAP54XX_CMD_VDD_CORE_L_WIDTH 0x1 +#define OMAP54XX_CMD_VDD_CORE_L_MASK (1 << 28) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_CMD_VDD_MM_L_SHIFT 28 +#define OMAP54XX_CMD_VDD_MM_L_WIDTH 0x1 +#define OMAP54XX_CMD_VDD_MM_L_MASK (1 << 28) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_CMD_VDD_MPU_L_SHIFT 28 +#define OMAP54XX_CMD_VDD_MPU_L_WIDTH 0x1 +#define OMAP54XX_CMD_VDD_MPU_L_MASK (1 << 28) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_CORE_OCMRAM_ONSTATE_SHIFT 18 +#define OMAP54XX_CORE_OCMRAM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_CORE_OCMRAM_RETSTATE_SHIFT 9 +#define OMAP54XX_CORE_OCMRAM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_CORE_OCMRAM_RETSTATE_MASK (1 << 9) + +/* Used by PM_CORE_PWRSTST */ +#define OMAP54XX_CORE_OCMRAM_STATEST_SHIFT 6 +#define OMAP54XX_CORE_OCMRAM_STATEST_WIDTH 0x2 +#define OMAP54XX_CORE_OCMRAM_STATEST_MASK (0x3 << 6) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_SHIFT 16 +#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_WIDTH 0x2 +#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_SHIFT 8 +#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_WIDTH 0x1 +#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8) + +/* Used by PM_CORE_PWRSTST */ +#define OMAP54XX_CORE_OTHER_BANK_STATEST_SHIFT 4 +#define OMAP54XX_CORE_OTHER_BANK_STATEST_WIDTH 0x2 +#define OMAP54XX_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4) + +/* Used by REVISION_PRM */ +#define OMAP54XX_CUSTOM_SHIFT 6 +#define OMAP54XX_CUSTOM_WIDTH 0x2 +#define OMAP54XX_CUSTOM_MASK (0x3 << 6) + +/* Used by PRM_VC_VAL_BYPASS */ +#define OMAP54XX_DATA_SHIFT 16 +#define OMAP54XX_DATA_WIDTH 0x8 +#define OMAP54XX_DATA_MASK (0xff << 16) + +/* Used by PRM_DEBUG_CORE_RET_TRANS */ +#define OMAP54XX_PRM_DEBUG_OUT_SHIFT 0 +#define OMAP54XX_PRM_DEBUG_OUT_WIDTH 0x1c +#define OMAP54XX_PRM_DEBUG_OUT_MASK (0xfffffff << 0) + +/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MM_RET_TRANS */ +#define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa +#define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0) + +/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MPU_RET_TRANS */ +#define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7 +#define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0) + +/* Renamed from DEBUG_OUT Used by PRM_DEBUG_OFF_TRANS */ +#define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20 +#define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0) + +/* Renamed from DEBUG_OUT Used by PRM_DEBUG_WKUPAON_FD_TRANS */ +#define OMAP54XX_DEBUG_OUT_0_11_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_11_WIDTH 0xc +#define OMAP54XX_DEBUG_OUT_0_11_MASK (0xfff << 0) + +/* Used by PRM_DEVICE_OFF_CTRL */ +#define OMAP54XX_DEVICE_OFF_ENABLE_SHIFT 0 +#define OMAP54XX_DEVICE_OFF_ENABLE_WIDTH 0x1 +#define OMAP54XX_DEVICE_OFF_ENABLE_MASK (1 << 0) + +/* Used by PRM_VC_CFG_I2C_MODE */ +#define OMAP54XX_DFILTEREN_SHIFT 6 +#define OMAP54XX_DFILTEREN_WIDTH 0x1 +#define OMAP54XX_DFILTEREN_MASK (1 << 6) + +/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_DPLL_ABE_RECAL_EN_SHIFT 4 +#define OMAP54XX_DPLL_ABE_RECAL_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_ABE_RECAL_EN_MASK (1 << 4) + +/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_DPLL_ABE_RECAL_ST_SHIFT 4 +#define OMAP54XX_DPLL_ABE_RECAL_ST_WIDTH 0x1 +#define OMAP54XX_DPLL_ABE_RECAL_ST_MASK (1 << 4) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_DPLL_CORE_RECAL_EN_SHIFT 0 +#define OMAP54XX_DPLL_CORE_RECAL_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_CORE_RECAL_EN_MASK (1 << 0) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_DPLL_CORE_RECAL_ST_SHIFT 0 +#define OMAP54XX_DPLL_CORE_RECAL_ST_WIDTH 0x1 +#define OMAP54XX_DPLL_CORE_RECAL_ST_MASK (1 << 0) + +/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_DPLL_IVA_RECAL_EN_SHIFT 2 +#define OMAP54XX_DPLL_IVA_RECAL_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_IVA_RECAL_EN_MASK (1 << 2) + +/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_DPLL_IVA_RECAL_ST_SHIFT 2 +#define OMAP54XX_DPLL_IVA_RECAL_ST_WIDTH 0x1 +#define OMAP54XX_DPLL_IVA_RECAL_ST_MASK (1 << 2) + +/* Used by PRM_IRQENABLE_MPU */ +#define OMAP54XX_DPLL_MPU_RECAL_EN_SHIFT 1 +#define OMAP54XX_DPLL_MPU_RECAL_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_MPU_RECAL_EN_MASK (1 << 1) + +/* Used by PRM_IRQSTATUS_MPU */ +#define OMAP54XX_DPLL_MPU_RECAL_ST_SHIFT 1 +#define OMAP54XX_DPLL_MPU_RECAL_ST_WIDTH 0x1 +#define OMAP54XX_DPLL_MPU_RECAL_ST_MASK (1 << 1) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_DPLL_PER_RECAL_EN_SHIFT 3 +#define OMAP54XX_DPLL_PER_RECAL_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_PER_RECAL_EN_MASK (1 << 3) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_DPLL_PER_RECAL_ST_SHIFT 3 +#define OMAP54XX_DPLL_PER_RECAL_ST_WIDTH 0x1 +#define OMAP54XX_DPLL_PER_RECAL_ST_MASK (1 << 3) + +/* Used by PM_DSP_PWRSTCTRL */ +#define OMAP54XX_DSP_EDMA_ONSTATE_SHIFT 20 +#define OMAP54XX_DSP_EDMA_ONSTATE_WIDTH 0x2 +#define OMAP54XX_DSP_EDMA_ONSTATE_MASK (0x3 << 20) + +/* Used by PM_DSP_PWRSTCTRL */ +#define OMAP54XX_DSP_EDMA_RETSTATE_SHIFT 10 +#define OMAP54XX_DSP_EDMA_RETSTATE_WIDTH 0x1 +#define OMAP54XX_DSP_EDMA_RETSTATE_MASK (1 << 10) + +/* Used by PM_DSP_PWRSTST */ +#define OMAP54XX_DSP_EDMA_STATEST_SHIFT 8 +#define OMAP54XX_DSP_EDMA_STATEST_WIDTH 0x2 +#define OMAP54XX_DSP_EDMA_STATEST_MASK (0x3 << 8) + +/* Used by PM_DSP_PWRSTCTRL */ +#define OMAP54XX_DSP_L1_ONSTATE_SHIFT 16 +#define OMAP54XX_DSP_L1_ONSTATE_WIDTH 0x2 +#define OMAP54XX_DSP_L1_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_DSP_PWRSTCTRL */ +#define OMAP54XX_DSP_L1_RETSTATE_SHIFT 8 +#define OMAP54XX_DSP_L1_RETSTATE_WIDTH 0x1 +#define OMAP54XX_DSP_L1_RETSTATE_MASK (1 << 8) + +/* Used by PM_DSP_PWRSTST */ +#define OMAP54XX_DSP_L1_STATEST_SHIFT 4 +#define OMAP54XX_DSP_L1_STATEST_WIDTH 0x2 +#define OMAP54XX_DSP_L1_STATEST_MASK (0x3 << 4) + +/* Used by PM_DSP_PWRSTCTRL */ +#define OMAP54XX_DSP_L2_ONSTATE_SHIFT 18 +#define OMAP54XX_DSP_L2_ONSTATE_WIDTH 0x2 +#define OMAP54XX_DSP_L2_ONSTATE_MASK (0x3 << 18) + +/* Used by PM_DSP_PWRSTCTRL */ +#define OMAP54XX_DSP_L2_RETSTATE_SHIFT 9 +#define OMAP54XX_DSP_L2_RETSTATE_WIDTH 0x1 +#define OMAP54XX_DSP_L2_RETSTATE_MASK (1 << 9) + +/* Used by PM_DSP_PWRSTST */ +#define OMAP54XX_DSP_L2_STATEST_SHIFT 6 +#define OMAP54XX_DSP_L2_STATEST_WIDTH 0x2 +#define OMAP54XX_DSP_L2_STATEST_MASK (0x3 << 6) + +/* Used by PM_DSS_PWRSTCTRL */ +#define OMAP54XX_DSS_MEM_ONSTATE_SHIFT 16 +#define OMAP54XX_DSS_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_DSS_MEM_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_DSS_PWRSTCTRL */ +#define OMAP54XX_DSS_MEM_RETSTATE_SHIFT 8 +#define OMAP54XX_DSS_MEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_DSS_MEM_RETSTATE_MASK (1 << 8) + +/* Used by PM_DSS_PWRSTST */ +#define OMAP54XX_DSS_MEM_STATEST_SHIFT 4 +#define OMAP54XX_DSS_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_DSS_MEM_STATEST_MASK (0x3 << 4) + +/* Used by PRM_DEVICE_OFF_CTRL */ +#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_SHIFT 8 +#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_WIDTH 0x1 +#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8) + +/* Used by PRM_DEVICE_OFF_CTRL */ +#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_SHIFT 9 +#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_WIDTH 0x1 +#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9) + +/* Used by PM_EMU_PWRSTCTRL */ +#define OMAP54XX_EMU_BANK_ONSTATE_SHIFT 16 +#define OMAP54XX_EMU_BANK_ONSTATE_WIDTH 0x2 +#define OMAP54XX_EMU_BANK_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_EMU_PWRSTST */ +#define OMAP54XX_EMU_BANK_STATEST_SHIFT 4 +#define OMAP54XX_EMU_BANK_STATEST_WIDTH 0x2 +#define OMAP54XX_EMU_BANK_STATEST_MASK (0x3 << 4) + +/* + * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP, + * PRM_SRAM_WKUP_SETUP + */ +#define OMAP54XX_ENABLE_RTA_SHIFT 0 +#define OMAP54XX_ENABLE_RTA_WIDTH 0x1 +#define OMAP54XX_ENABLE_RTA_MASK (1 << 0) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ENFUNC1_SHIFT 3 +#define OMAP54XX_ENFUNC1_WIDTH 0x1 +#define OMAP54XX_ENFUNC1_MASK (1 << 3) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ENFUNC2_SHIFT 4 +#define OMAP54XX_ENFUNC2_WIDTH 0x1 +#define OMAP54XX_ENFUNC2_MASK (1 << 4) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ENFUNC3_SHIFT 5 +#define OMAP54XX_ENFUNC3_WIDTH 0x1 +#define OMAP54XX_ENFUNC3_MASK (1 << 5) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ENFUNC4_SHIFT 6 +#define OMAP54XX_ENFUNC4_WIDTH 0x1 +#define OMAP54XX_ENFUNC4_MASK (1 << 6) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ENFUNC5_SHIFT 7 +#define OMAP54XX_ENFUNC5_WIDTH 0x1 +#define OMAP54XX_ENFUNC5_MASK (1 << 7) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_ERRORGAIN_SHIFT 16 +#define OMAP54XX_ERRORGAIN_WIDTH 0x8 +#define OMAP54XX_ERRORGAIN_MASK (0xff << 16) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_ERROROFFSET_SHIFT 24 +#define OMAP54XX_ERROROFFSET_WIDTH 0x8 +#define OMAP54XX_ERROROFFSET_MASK (0xff << 24) + +/* Used by PRM_RSTST */ +#define OMAP54XX_EXTERNAL_WARM_RST_SHIFT 5 +#define OMAP54XX_EXTERNAL_WARM_RST_WIDTH 0x1 +#define OMAP54XX_EXTERNAL_WARM_RST_MASK (1 << 5) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_FORCEUPDATE_SHIFT 1 +#define OMAP54XX_FORCEUPDATE_WIDTH 0x1 +#define OMAP54XX_FORCEUPDATE_MASK (1 << 1) + +/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */ +#define OMAP54XX_FORCEUPDATEWAIT_SHIFT 8 +#define OMAP54XX_FORCEUPDATEWAIT_WIDTH 0x18 +#define OMAP54XX_FORCEUPDATEWAIT_MASK (0xffffff << 8) + +/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU */ +#define OMAP54XX_FORCEWKUP_EN_SHIFT 10 +#define OMAP54XX_FORCEWKUP_EN_WIDTH 0x1 +#define OMAP54XX_FORCEWKUP_EN_MASK (1 << 10) + +/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU */ +#define OMAP54XX_FORCEWKUP_ST_SHIFT 10 +#define OMAP54XX_FORCEWKUP_ST_WIDTH 0x1 +#define OMAP54XX_FORCEWKUP_ST_MASK (1 << 10) + +/* Used by REVISION_PRM */ +#define OMAP54XX_FUNC_SHIFT 16 +#define OMAP54XX_FUNC_WIDTH 0xc +#define OMAP54XX_FUNC_MASK (0xfff << 16) + +/* Used by PRM_RSTST */ +#define OMAP54XX_GLOBAL_COLD_RST_SHIFT 0 +#define OMAP54XX_GLOBAL_COLD_RST_WIDTH 0x1 +#define OMAP54XX_GLOBAL_COLD_RST_MASK (1 << 0) + +/* Used by PRM_RSTST */ +#define OMAP54XX_GLOBAL_WARM_SW_RST_SHIFT 1 +#define OMAP54XX_GLOBAL_WARM_SW_RST_WIDTH 0x1 +#define OMAP54XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_GLOBAL_WUEN_SHIFT 16 +#define OMAP54XX_GLOBAL_WUEN_WIDTH 0x1 +#define OMAP54XX_GLOBAL_WUEN_MASK (1 << 16) + +/* Used by PM_GPU_PWRSTCTRL */ +#define OMAP54XX_GPU_MEM_ONSTATE_SHIFT 16 +#define OMAP54XX_GPU_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_GPU_MEM_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_GPU_PWRSTST */ +#define OMAP54XX_GPU_MEM_STATEST_SHIFT 4 +#define OMAP54XX_GPU_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_GPU_MEM_STATEST_MASK (0x3 << 4) + +/* Used by PRM_VC_CFG_I2C_MODE */ +#define OMAP54XX_HSMCODE_SHIFT 0 +#define OMAP54XX_HSMCODE_WIDTH 0x3 +#define OMAP54XX_HSMCODE_MASK (0x7 << 0) + +/* Used by PRM_VC_CFG_I2C_MODE */ +#define OMAP54XX_HSMODEEN_SHIFT 3 +#define OMAP54XX_HSMODEEN_WIDTH 0x1 +#define OMAP54XX_HSMODEEN_MASK (1 << 3) + +/* Used by PRM_VC_CFG_I2C_CLK */ +#define OMAP54XX_HSSCLH_SHIFT 16 +#define OMAP54XX_HSSCLH_WIDTH 0x8 +#define OMAP54XX_HSSCLH_MASK (0xff << 16) + +/* Used by PRM_VC_CFG_I2C_CLK */ +#define OMAP54XX_HSSCLL_SHIFT 24 +#define OMAP54XX_HSSCLL_WIDTH 0x8 +#define OMAP54XX_HSSCLL_MASK (0xff << 24) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_HWA_MEM_ONSTATE_SHIFT 16 +#define OMAP54XX_HWA_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_HWA_MEM_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_HWA_MEM_RETSTATE_SHIFT 8 +#define OMAP54XX_HWA_MEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_HWA_MEM_RETSTATE_MASK (1 << 8) + +/* Used by PM_IVA_PWRSTST */ +#define OMAP54XX_HWA_MEM_STATEST_SHIFT 4 +#define OMAP54XX_HWA_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_HWA_MEM_STATEST_MASK (0x3 << 4) + +/* Used by PRM_RSTST */ +#define OMAP54XX_ICEPICK_RST_SHIFT 9 +#define OMAP54XX_ICEPICK_RST_WIDTH 0x1 +#define OMAP54XX_ICEPICK_RST_MASK (1 << 9) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_INITVDD_SHIFT 2 +#define OMAP54XX_INITVDD_WIDTH 0x1 +#define OMAP54XX_INITVDD_MASK (1 << 2) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_INITVOLTAGE_SHIFT 8 +#define OMAP54XX_INITVOLTAGE_WIDTH 0x8 +#define OMAP54XX_INITVOLTAGE_MASK (0xff << 8) + +/* + * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, + * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, + * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST, + * PRM_VOLTST_MM, PRM_VOLTST_MPU + */ +#define OMAP54XX_INTRANSITION_SHIFT 20 +#define OMAP54XX_INTRANSITION_WIDTH 0x1 +#define OMAP54XX_INTRANSITION_MASK (1 << 20) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_IO_EN_SHIFT 9 +#define OMAP54XX_IO_EN_WIDTH 0x1 +#define OMAP54XX_IO_EN_MASK (1 << 9) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_IO_ON_STATUS_SHIFT 5 +#define OMAP54XX_IO_ON_STATUS_WIDTH 0x1 +#define OMAP54XX_IO_ON_STATUS_MASK (1 << 5) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_IO_ST_SHIFT 9 +#define OMAP54XX_IO_ST_WIDTH 0x1 +#define OMAP54XX_IO_ST_MASK (1 << 9) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_IPU_L2RAM_ONSTATE_SHIFT 20 +#define OMAP54XX_IPU_L2RAM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_IPU_L2RAM_ONSTATE_MASK (0x3 << 20) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_IPU_L2RAM_RETSTATE_SHIFT 10 +#define OMAP54XX_IPU_L2RAM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_IPU_L2RAM_RETSTATE_MASK (1 << 10) + +/* Used by PM_CORE_PWRSTST */ +#define OMAP54XX_IPU_L2RAM_STATEST_SHIFT 8 +#define OMAP54XX_IPU_L2RAM_STATEST_WIDTH 0x2 +#define OMAP54XX_IPU_L2RAM_STATEST_MASK (0x3 << 8) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_IPU_UNICACHE_ONSTATE_SHIFT 22 +#define OMAP54XX_IPU_UNICACHE_ONSTATE_WIDTH 0x2 +#define OMAP54XX_IPU_UNICACHE_ONSTATE_MASK (0x3 << 22) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_IPU_UNICACHE_RETSTATE_SHIFT 11 +#define OMAP54XX_IPU_UNICACHE_RETSTATE_WIDTH 0x1 +#define OMAP54XX_IPU_UNICACHE_RETSTATE_MASK (1 << 11) + +/* Used by PM_CORE_PWRSTST */ +#define OMAP54XX_IPU_UNICACHE_STATEST_SHIFT 10 +#define OMAP54XX_IPU_UNICACHE_STATEST_WIDTH 0x2 +#define OMAP54XX_IPU_UNICACHE_STATEST_MASK (0x3 << 10) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_ISOCLK_OVERRIDE_SHIFT 0 +#define OMAP54XX_ISOCLK_OVERRIDE_WIDTH 0x1 +#define OMAP54XX_ISOCLK_OVERRIDE_MASK (1 << 0) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_ISOCLK_STATUS_SHIFT 1 +#define OMAP54XX_ISOCLK_STATUS_WIDTH 0x1 +#define OMAP54XX_ISOCLK_STATUS_MASK (1 << 1) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_ISOOVR_EXTEND_SHIFT 4 +#define OMAP54XX_ISOOVR_EXTEND_WIDTH 0x1 +#define OMAP54XX_ISOOVR_EXTEND_MASK (1 << 4) + +/* Used by PRM_IO_COUNT */ +#define OMAP54XX_ISO_2_ON_TIME_SHIFT 0 +#define OMAP54XX_ISO_2_ON_TIME_WIDTH 0x8 +#define OMAP54XX_ISO_2_ON_TIME_MASK (0xff << 0) + +/* Used by PM_L3INIT_PWRSTCTRL */ +#define OMAP54XX_L3INIT_BANK1_ONSTATE_SHIFT 16 +#define OMAP54XX_L3INIT_BANK1_ONSTATE_WIDTH 0x2 +#define OMAP54XX_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_L3INIT_PWRSTCTRL */ +#define OMAP54XX_L3INIT_BANK1_RETSTATE_SHIFT 8 +#define OMAP54XX_L3INIT_BANK1_RETSTATE_WIDTH 0x1 +#define OMAP54XX_L3INIT_BANK1_RETSTATE_MASK (1 << 8) + +/* Used by PM_L3INIT_PWRSTST */ +#define OMAP54XX_L3INIT_BANK1_STATEST_SHIFT 4 +#define OMAP54XX_L3INIT_BANK1_STATEST_WIDTH 0x2 +#define OMAP54XX_L3INIT_BANK1_STATEST_MASK (0x3 << 4) + +/* Used by PM_L3INIT_PWRSTCTRL */ +#define OMAP54XX_L3INIT_BANK2_ONSTATE_SHIFT 18 +#define OMAP54XX_L3INIT_BANK2_ONSTATE_WIDTH 0x2 +#define OMAP54XX_L3INIT_BANK2_ONSTATE_MASK (0x3 << 18) + +/* Used by PM_L3INIT_PWRSTCTRL */ +#define OMAP54XX_L3INIT_BANK2_RETSTATE_SHIFT 9 +#define OMAP54XX_L3INIT_BANK2_RETSTATE_WIDTH 0x1 +#define OMAP54XX_L3INIT_BANK2_RETSTATE_MASK (1 << 9) + +/* Used by PM_L3INIT_PWRSTST */ +#define OMAP54XX_L3INIT_BANK2_STATEST_SHIFT 6 +#define OMAP54XX_L3INIT_BANK2_STATEST_WIDTH 0x2 +#define OMAP54XX_L3INIT_BANK2_STATEST_MASK (0x3 << 6) + +/* + * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, + * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, + * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST + */ +#define OMAP54XX_LASTPOWERSTATEENTERED_SHIFT 24 +#define OMAP54XX_LASTPOWERSTATEENTERED_WIDTH 0x2 +#define OMAP54XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) + +/* Used by PRM_RSTST */ +#define OMAP54XX_LLI_RST_SHIFT 14 +#define OMAP54XX_LLI_RST_WIDTH 0x1 +#define OMAP54XX_LLI_RST_MASK (1 << 14) + +/* + * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSP_PWRSTCTRL, + * PM_DSS_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL + */ +#define OMAP54XX_LOGICRETSTATE_SHIFT 2 +#define OMAP54XX_LOGICRETSTATE_WIDTH 0x1 +#define OMAP54XX_LOGICRETSTATE_MASK (1 << 2) + +/* + * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, + * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, + * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST + */ +#define OMAP54XX_LOGICSTATEST_SHIFT 2 +#define OMAP54XX_LOGICSTATEST_WIDTH 0x1 +#define OMAP54XX_LOGICSTATEST_MASK (1 << 2) + +/* + * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, + * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, + * RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT, RM_ABE_TIMER5_CONTEXT, + * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, + * RM_ABE_WD_TIMER3_CONTEXT, RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT, + * RM_CAM_CAL_CONTEXT, RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, + * RM_COREAON_SMARTREFLEX_CORE_CONTEXT, RM_COREAON_SMARTREFLEX_MM_CONTEXT, + * RM_COREAON_SMARTREFLEX_MPU_CONTEXT, RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT, + * RM_DSP_DSP_CONTEXT, RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT, + * RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, RM_EMIF_EMIF2_CONTEXT, + * RM_EMIF_EMIF_DLL_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, + * RM_EMU_DEBUGSS_CONTEXT, RM_GPU_GPU_CONTEXT, RM_IPU_IPU_CONTEXT, + * RM_IVA_IVA_CONTEXT, RM_IVA_SL2_CONTEXT, RM_L3INIT_IEEE1500_2_OCP_CONTEXT, + * RM_L3INIT_OCP2SCP1_CONTEXT, RM_L3INIT_OCP2SCP3_CONTEXT, + * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT, + * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT, + * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT, + * RM_L3MAIN2_L3_MAIN_2_CONTEXT, RM_L3MAIN2_OCMC_RAM_CONTEXT, + * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_OCP2SCP2_CONTEXT, + * RM_L4CFG_SAR_ROM_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT, + * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, + * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, + * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, + * RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT, + * RM_L4PER_TIMER10_CONTEXT, RM_L4PER_TIMER11_CONTEXT, RM_L4PER_TIMER2_CONTEXT, + * RM_L4PER_TIMER3_CONTEXT, RM_L4PER_TIMER4_CONTEXT, RM_L4PER_TIMER9_CONTEXT, + * RM_L4SEC_FPKA_CONTEXT, RM_MIPIEXT_LLI_CONTEXT, + * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT, + * RM_WKUPAON_COUNTER_32K_CONTEXT, RM_WKUPAON_GPIO1_CONTEXT, + * RM_WKUPAON_KBD_CONTEXT, RM_WKUPAON_L4_WKUP_CONTEXT, + * RM_WKUPAON_SAR_RAM_CONTEXT, RM_WKUPAON_TIMER12_CONTEXT, + * RM_WKUPAON_TIMER1_CONTEXT, RM_WKUPAON_WD_TIMER1_CONTEXT, + * RM_WKUPAON_WD_TIMER2_CONTEXT + */ +#define OMAP54XX_LOSTCONTEXT_DFF_SHIFT 0 +#define OMAP54XX_LOSTCONTEXT_DFF_WIDTH 0x1 +#define OMAP54XX_LOSTCONTEXT_DFF_MASK (1 << 0) + +/* + * Used by RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT, + * RM_C2C_MODEM_ICR_CONTEXT, RM_DMA_DMA_SYSTEM_CONTEXT, RM_DSP_DSP_CONTEXT, + * RM_DSS_DSS_CONTEXT, RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, + * RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, RM_IPU_IPU_CONTEXT, + * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, + * RM_L3INIT_USB_HOST_HS_CONTEXT, RM_L3INIT_USB_OTG_SS_CONTEXT, + * RM_L3INIT_USB_TLL_HS_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT, + * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT, + * RM_L3MAIN2_GPMC_CONTEXT, RM_L3MAIN2_L3_MAIN_2_CONTEXT, + * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_MAILBOX_CONTEXT, + * RM_L4CFG_SPINLOCK_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, + * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, + * RM_L4PER_GPIO7_CONTEXT, RM_L4PER_GPIO8_CONTEXT, RM_L4PER_I2C1_CONTEXT, + * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, + * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT, + * RM_L4PER_UART6_CONTEXT, RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, + * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT, RM_L4SEC_RNG_CONTEXT, + * RM_L4SEC_SHA2MD5_CONTEXT, RM_MIPIEXT_LLI_CONTEXT, + * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT + */ +#define OMAP54XX_LOSTCONTEXT_RFF_SHIFT 1 +#define OMAP54XX_LOSTCONTEXT_RFF_WIDTH 0x1 +#define OMAP54XX_LOSTCONTEXT_RFF_MASK (1 << 1) + +/* Used by RM_ABE_AESS_CONTEXT */ +#define OMAP54XX_LOSTMEM_AESSMEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_AESSMEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_AESSMEM_MASK (1 << 8) + +/* Used by RM_CAM_CAL_CONTEXT */ +#define OMAP54XX_LOSTMEM_CAL_MEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_CAL_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_CAL_MEM_MASK (1 << 8) + +/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ +#define OMAP54XX_LOSTMEM_CAM_MEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_CAM_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_CAM_MEM_MASK (1 << 8) + +/* Used by RM_EMIF_DMM_CONTEXT */ +#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_SHIFT 9 +#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_MASK (1 << 9) + +/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_L3INSTR_OCP_WP_NOC_CONTEXT */ +#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_SHIFT 8 +#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_MASK (1 << 8) + +/* Used by RM_L3MAIN2_OCMC_RAM_CONTEXT */ +#define OMAP54XX_LOSTMEM_CORE_OCMRAM_SHIFT 8 +#define OMAP54XX_LOSTMEM_CORE_OCMRAM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_CORE_OCMRAM_MASK (1 << 8) + +/* Used by RM_DMA_DMA_SYSTEM_CONTEXT, RM_EMIF_DMM_CONTEXT */ +#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 +#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8) + +/* Used by RM_DSP_DSP_CONTEXT */ +#define OMAP54XX_LOSTMEM_DSP_EDMA_SHIFT 10 +#define OMAP54XX_LOSTMEM_DSP_EDMA_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_DSP_EDMA_MASK (1 << 10) + +/* Used by RM_DSP_DSP_CONTEXT */ +#define OMAP54XX_LOSTMEM_DSP_L1_SHIFT 8 +#define OMAP54XX_LOSTMEM_DSP_L1_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_DSP_L1_MASK (1 << 8) + +/* Used by RM_DSP_DSP_CONTEXT */ +#define OMAP54XX_LOSTMEM_DSP_L2_SHIFT 9 +#define OMAP54XX_LOSTMEM_DSP_L2_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_DSP_L2_MASK (1 << 9) + +/* Used by RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT */ +#define OMAP54XX_LOSTMEM_DSS_MEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_DSS_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_DSS_MEM_MASK (1 << 8) + +/* Used by RM_EMU_DEBUGSS_CONTEXT */ +#define OMAP54XX_LOSTMEM_EMU_BANK_SHIFT 8 +#define OMAP54XX_LOSTMEM_EMU_BANK_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_EMU_BANK_MASK (1 << 8) + +/* Used by RM_GPU_GPU_CONTEXT */ +#define OMAP54XX_LOSTMEM_GPU_MEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_GPU_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_GPU_MEM_MASK (1 << 8) + +/* Used by RM_IVA_IVA_CONTEXT */ +#define OMAP54XX_LOSTMEM_HWA_MEM_SHIFT 10 +#define OMAP54XX_LOSTMEM_HWA_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_HWA_MEM_MASK (1 << 10) + +/* Used by RM_IPU_IPU_CONTEXT */ +#define OMAP54XX_LOSTMEM_IPU_L2RAM_SHIFT 9 +#define OMAP54XX_LOSTMEM_IPU_L2RAM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_IPU_L2RAM_MASK (1 << 9) + +/* Used by RM_IPU_IPU_CONTEXT */ +#define OMAP54XX_LOSTMEM_IPU_UNICACHE_SHIFT 8 +#define OMAP54XX_LOSTMEM_IPU_UNICACHE_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_IPU_UNICACHE_MASK (1 << 8) + +/* + * Used by RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, + * RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT, + * RM_L3INIT_USB_OTG_SS_CONTEXT + */ +#define OMAP54XX_LOSTMEM_L3INIT_BANK1_SHIFT 8 +#define OMAP54XX_LOSTMEM_L3INIT_BANK1_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_L3INIT_BANK1_MASK (1 << 8) + +/* Used by RM_MPU_MPU_CONTEXT */ +#define OMAP54XX_LOSTMEM_MPU_L2_SHIFT 9 +#define OMAP54XX_LOSTMEM_MPU_L2_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_MPU_L2_MASK (1 << 9) + +/* Used by RM_MPU_MPU_CONTEXT */ +#define OMAP54XX_LOSTMEM_MPU_RAM_SHIFT 10 +#define OMAP54XX_LOSTMEM_MPU_RAM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_MPU_RAM_MASK (1 << 10) + +/* + * Used by RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT, + * RM_L4SEC_FPKA_CONTEXT + */ +#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_SHIFT 8 +#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8) + +/* + * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, + * RM_ABE_MCBSP3_CONTEXT, RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT + */ +#define OMAP54XX_LOSTMEM_PERIHPMEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_PERIHPMEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_PERIHPMEM_MASK (1 << 8) + +/* + * Used by RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, + * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT, + * RM_L4PER_UART6_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT + */ +#define OMAP54XX_LOSTMEM_RETAINED_BANK_SHIFT 8 +#define OMAP54XX_LOSTMEM_RETAINED_BANK_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_RETAINED_BANK_MASK (1 << 8) + +/* Used by RM_IVA_SL2_CONTEXT */ +#define OMAP54XX_LOSTMEM_SL2_MEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_SL2_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_SL2_MEM_MASK (1 << 8) + +/* Used by RM_IVA_IVA_CONTEXT */ +#define OMAP54XX_LOSTMEM_TCM1_MEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_TCM1_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_TCM1_MEM_MASK (1 << 8) + +/* Used by RM_IVA_IVA_CONTEXT */ +#define OMAP54XX_LOSTMEM_TCM2_MEM_SHIFT 9 +#define OMAP54XX_LOSTMEM_TCM2_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_TCM2_MEM_MASK (1 << 9) + +/* Used by RM_WKUPAON_SAR_RAM_CONTEXT */ +#define OMAP54XX_LOSTMEM_WKUP_BANK_SHIFT 8 +#define OMAP54XX_LOSTMEM_WKUP_BANK_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_WKUP_BANK_MASK (1 << 8) + +/* + * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, + * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL, + * PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL + */ +#define OMAP54XX_LOWPOWERSTATECHANGE_SHIFT 4 +#define OMAP54XX_LOWPOWERSTATECHANGE_WIDTH 0x1 +#define OMAP54XX_LOWPOWERSTATECHANGE_MASK (1 << 4) + +/* Used by PRM_DEBUG_TRANS_CFG */ +#define OMAP54XX_MODE_SHIFT 0 +#define OMAP54XX_MODE_WIDTH 0x2 +#define OMAP54XX_MODE_MASK (0x3 << 0) + +/* Used by PRM_MODEM_IF_CTRL */ +#define OMAP54XX_MODEM_SHUTDOWN_IRQ_SHIFT 9 +#define OMAP54XX_MODEM_SHUTDOWN_IRQ_WIDTH 0x1 +#define OMAP54XX_MODEM_SHUTDOWN_IRQ_MASK (1 << 9) + +/* Used by PRM_MODEM_IF_CTRL */ +#define OMAP54XX_MODEM_WAKE_IRQ_SHIFT 8 +#define OMAP54XX_MODEM_WAKE_IRQ_WIDTH 0x1 +#define OMAP54XX_MODEM_WAKE_IRQ_MASK (1 << 8) + +/* Used by PM_MPU_PWRSTCTRL */ +#define OMAP54XX_MPU_L2_ONSTATE_SHIFT 18 +#define OMAP54XX_MPU_L2_ONSTATE_WIDTH 0x2 +#define OMAP54XX_MPU_L2_ONSTATE_MASK (0x3 << 18) + +/* Used by PM_MPU_PWRSTCTRL */ +#define OMAP54XX_MPU_L2_RETSTATE_SHIFT 9 +#define OMAP54XX_MPU_L2_RETSTATE_WIDTH 0x1 +#define OMAP54XX_MPU_L2_RETSTATE_MASK (1 << 9) + +/* Used by PM_MPU_PWRSTST */ +#define OMAP54XX_MPU_L2_STATEST_SHIFT 6 +#define OMAP54XX_MPU_L2_STATEST_WIDTH 0x2 +#define OMAP54XX_MPU_L2_STATEST_MASK (0x3 << 6) + +/* Used by PM_MPU_PWRSTCTRL */ +#define OMAP54XX_MPU_RAM_ONSTATE_SHIFT 20 +#define OMAP54XX_MPU_RAM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_MPU_RAM_ONSTATE_MASK (0x3 << 20) + +/* Used by PM_MPU_PWRSTCTRL */ +#define OMAP54XX_MPU_RAM_RETSTATE_SHIFT 10 +#define OMAP54XX_MPU_RAM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_MPU_RAM_RETSTATE_MASK (1 << 10) + +/* Used by PM_MPU_PWRSTST */ +#define OMAP54XX_MPU_RAM_STATEST_SHIFT 8 +#define OMAP54XX_MPU_RAM_STATEST_WIDTH 0x2 +#define OMAP54XX_MPU_RAM_STATEST_MASK (0x3 << 8) + +/* Used by PRM_RSTST */ +#define OMAP54XX_MPU_SECURITY_VIOL_RST_SHIFT 2 +#define OMAP54XX_MPU_SECURITY_VIOL_RST_WIDTH 0x1 +#define OMAP54XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2) + +/* Used by PRM_RSTST */ +#define OMAP54XX_MPU_WDT_RST_SHIFT 3 +#define OMAP54XX_MPU_WDT_RST_WIDTH 0x1 +#define OMAP54XX_MPU_WDT_RST_MASK (1 << 3) + +/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ +#define OMAP54XX_NOCAP_SHIFT 4 +#define OMAP54XX_NOCAP_WIDTH 0x1 +#define OMAP54XX_NOCAP_MASK (1 << 4) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_OCP_NRET_BANK_ONSTATE_SHIFT 24 +#define OMAP54XX_OCP_NRET_BANK_ONSTATE_WIDTH 0x2 +#define OMAP54XX_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_OCP_NRET_BANK_RETSTATE_SHIFT 12 +#define OMAP54XX_OCP_NRET_BANK_RETSTATE_WIDTH 0x1 +#define OMAP54XX_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) + +/* Used by PM_CORE_PWRSTST */ +#define OMAP54XX_OCP_NRET_BANK_STATEST_SHIFT 12 +#define OMAP54XX_OCP_NRET_BANK_STATEST_WIDTH 0x2 +#define OMAP54XX_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) + +/* + * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, + * PRM_VC_VAL_CMD_VDD_MPU_L + */ +#define OMAP54XX_OFF_SHIFT 0 +#define OMAP54XX_OFF_WIDTH 0x8 +#define OMAP54XX_OFF_MASK (0xff << 0) + +/* + * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, + * PRM_VC_VAL_CMD_VDD_MPU_L + */ +#define OMAP54XX_ON_SHIFT 24 +#define OMAP54XX_ON_WIDTH 0x8 +#define OMAP54XX_ON_MASK (0xff << 24) + +/* + * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, + * PRM_VC_VAL_CMD_VDD_MPU_L + */ +#define OMAP54XX_ONLP_SHIFT 16 +#define OMAP54XX_ONLP_WIDTH 0x8 +#define OMAP54XX_ONLP_MASK (0xff << 16) + +/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ +#define OMAP54XX_OPP_CHANGE_SHIFT 2 +#define OMAP54XX_OPP_CHANGE_WIDTH 0x1 +#define OMAP54XX_OPP_CHANGE_MASK (1 << 2) + +/* Used by PRM_VC_VAL_BYPASS */ +#define OMAP54XX_OPP_CHANGE_EMIF_LVL_SHIFT 25 +#define OMAP54XX_OPP_CHANGE_EMIF_LVL_WIDTH 0x1 +#define OMAP54XX_OPP_CHANGE_EMIF_LVL_MASK (1 << 25) + +/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ +#define OMAP54XX_OPP_SEL_SHIFT 0 +#define OMAP54XX_OPP_SEL_WIDTH 0x2 +#define OMAP54XX_OPP_SEL_MASK (0x3 << 0) + +/* Used by PRM_DEBUG_OUT */ +#define OMAP54XX_OUTPUT_SHIFT 0 +#define OMAP54XX_OUTPUT_WIDTH 0x20 +#define OMAP54XX_OUTPUT_MASK (0xffffffff << 0) + +/* Used by PRM_SRAM_COUNT */ +#define OMAP54XX_PCHARGECNT_VALUE_SHIFT 0 +#define OMAP54XX_PCHARGECNT_VALUE_WIDTH 0x6 +#define OMAP54XX_PCHARGECNT_VALUE_MASK (0x3f << 0) + +/* Used by PRM_PSCON_COUNT */ +#define OMAP54XX_PCHARGE_TIME_SHIFT 0 +#define OMAP54XX_PCHARGE_TIME_WIDTH 0x8 +#define OMAP54XX_PCHARGE_TIME_MASK (0xff << 0) + +/* Used by PM_ABE_PWRSTCTRL */ +#define OMAP54XX_PERIPHMEM_ONSTATE_SHIFT 20 +#define OMAP54XX_PERIPHMEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_PERIPHMEM_ONSTATE_MASK (0x3 << 20) + +/* Used by PM_ABE_PWRSTCTRL */ +#define OMAP54XX_PERIPHMEM_RETSTATE_SHIFT 10 +#define OMAP54XX_PERIPHMEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_PERIPHMEM_RETSTATE_MASK (1 << 10) + +/* Used by PM_ABE_PWRSTST */ +#define OMAP54XX_PERIPHMEM_STATEST_SHIFT 8 +#define OMAP54XX_PERIPHMEM_STATEST_WIDTH 0x2 +#define OMAP54XX_PERIPHMEM_STATEST_MASK (0x3 << 8) + +/* Used by PRM_PHASE1_CNDP */ +#define OMAP54XX_PHASE1_CNDP_SHIFT 0 +#define OMAP54XX_PHASE1_CNDP_WIDTH 0x20 +#define OMAP54XX_PHASE1_CNDP_MASK (0xffffffff << 0) + +/* Used by PRM_PHASE2A_CNDP */ +#define OMAP54XX_PHASE2A_CNDP_SHIFT 0 +#define OMAP54XX_PHASE2A_CNDP_WIDTH 0x20 +#define OMAP54XX_PHASE2A_CNDP_MASK (0xffffffff << 0) + +/* Used by PRM_PHASE2B_CNDP */ +#define OMAP54XX_PHASE2B_CNDP_SHIFT 0 +#define OMAP54XX_PHASE2B_CNDP_WIDTH 0x20 +#define OMAP54XX_PHASE2B_CNDP_MASK (0xffffffff << 0) + +/* Used by PRM_PSCON_COUNT */ +#define OMAP54XX_PONOUT_2_PGOODIN_TIME_SHIFT 8 +#define OMAP54XX_PONOUT_2_PGOODIN_TIME_WIDTH 0x8 +#define OMAP54XX_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8) + +/* + * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, + * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL, + * PM_EMU_PWRSTCTRL, PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, + * PM_MPU_PWRSTCTRL + */ +#define OMAP54XX_POWERSTATE_SHIFT 0 +#define OMAP54XX_POWERSTATE_WIDTH 0x2 +#define OMAP54XX_POWERSTATE_MASK (0x3 << 0) + +/* + * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, + * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, + * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST + */ +#define OMAP54XX_POWERSTATEST_SHIFT 0 +#define OMAP54XX_POWERSTATEST_WIDTH 0x2 +#define OMAP54XX_POWERSTATEST_MASK (0x3 << 0) + +/* Used by PRM_PWRREQCTRL */ +#define OMAP54XX_PWRREQ_COND_SHIFT 0 +#define OMAP54XX_PWRREQ_COND_WIDTH 0x2 +#define OMAP54XX_PWRREQ_COND_MASK (0x3 << 0) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_RACEN_VDD_CORE_L_SHIFT 27 +#define OMAP54XX_RACEN_VDD_CORE_L_WIDTH 0x1 +#define OMAP54XX_RACEN_VDD_CORE_L_MASK (1 << 27) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_RACEN_VDD_MM_L_SHIFT 27 +#define OMAP54XX_RACEN_VDD_MM_L_WIDTH 0x1 +#define OMAP54XX_RACEN_VDD_MM_L_MASK (1 << 27) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_RACEN_VDD_MPU_L_SHIFT 27 +#define OMAP54XX_RACEN_VDD_MPU_L_WIDTH 0x1 +#define OMAP54XX_RACEN_VDD_MPU_L_MASK (1 << 27) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_RAC_VDD_CORE_L_SHIFT 26 +#define OMAP54XX_RAC_VDD_CORE_L_WIDTH 0x1 +#define OMAP54XX_RAC_VDD_CORE_L_MASK (1 << 26) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_RAC_VDD_MM_L_SHIFT 26 +#define OMAP54XX_RAC_VDD_MM_L_WIDTH 0x1 +#define OMAP54XX_RAC_VDD_MM_L_MASK (1 << 26) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_RAC_VDD_MPU_L_SHIFT 26 +#define OMAP54XX_RAC_VDD_MPU_L_WIDTH 0x1 +#define OMAP54XX_RAC_VDD_MPU_L_MASK (1 << 26) + +/* + * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, + * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, + * PRM_VOLTSETUP_MPU_RET_SLEEP + */ +#define OMAP54XX_RAMP_DOWN_COUNT_SHIFT 16 +#define OMAP54XX_RAMP_DOWN_COUNT_WIDTH 0x6 +#define OMAP54XX_RAMP_DOWN_COUNT_MASK (0x3f << 16) + +/* + * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, + * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, + * PRM_VOLTSETUP_MPU_RET_SLEEP + */ +#define OMAP54XX_RAMP_DOWN_PRESCAL_SHIFT 24 +#define OMAP54XX_RAMP_DOWN_PRESCAL_WIDTH 0x2 +#define OMAP54XX_RAMP_DOWN_PRESCAL_MASK (0x3 << 24) + +/* + * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, + * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, + * PRM_VOLTSETUP_MPU_RET_SLEEP + */ +#define OMAP54XX_RAMP_UP_COUNT_SHIFT 0 +#define OMAP54XX_RAMP_UP_COUNT_WIDTH 0x6 +#define OMAP54XX_RAMP_UP_COUNT_MASK (0x3f << 0) + +/* + * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, + * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, + * PRM_VOLTSETUP_MPU_RET_SLEEP + */ +#define OMAP54XX_RAMP_UP_PRESCAL_SHIFT 8 +#define OMAP54XX_RAMP_UP_PRESCAL_WIDTH 0x2 +#define OMAP54XX_RAMP_UP_PRESCAL_MASK (0x3 << 8) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_RAV_VDD_CORE_L_SHIFT 25 +#define OMAP54XX_RAV_VDD_CORE_L_WIDTH 0x1 +#define OMAP54XX_RAV_VDD_CORE_L_MASK (1 << 25) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_RAV_VDD_MM_L_SHIFT 25 +#define OMAP54XX_RAV_VDD_MM_L_WIDTH 0x1 +#define OMAP54XX_RAV_VDD_MM_L_MASK (1 << 25) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_RAV_VDD_MPU_L_SHIFT 25 +#define OMAP54XX_RAV_VDD_MPU_L_WIDTH 0x1 +#define OMAP54XX_RAV_VDD_MPU_L_MASK (1 << 25) + +/* Used by PRM_VC_VAL_BYPASS */ +#define OMAP54XX_REGADDR_SHIFT 8 +#define OMAP54XX_REGADDR_WIDTH 0x8 +#define OMAP54XX_REGADDR_MASK (0xff << 8) + +/* + * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, + * PRM_VC_VAL_CMD_VDD_MPU_L + */ +#define OMAP54XX_RET_SHIFT 8 +#define OMAP54XX_RET_WIDTH 0x8 +#define OMAP54XX_RET_MASK (0xff << 8) + +/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ +#define OMAP54XX_RETMODE_ENABLE_SHIFT 0 +#define OMAP54XX_RETMODE_ENABLE_WIDTH 0x1 +#define OMAP54XX_RETMODE_ENABLE_MASK (1 << 0) + +/* Used by PRM_RSTTIME */ +#define OMAP54XX_RSTTIME1_SHIFT 0 +#define OMAP54XX_RSTTIME1_WIDTH 0xa +#define OMAP54XX_RSTTIME1_MASK (0x3ff << 0) + +/* Used by PRM_RSTTIME */ +#define OMAP54XX_RSTTIME2_SHIFT 10 +#define OMAP54XX_RSTTIME2_WIDTH 0x5 +#define OMAP54XX_RSTTIME2_MASK (0x1f << 10) + +/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ +#define OMAP54XX_RST_CPU0_SHIFT 0 +#define OMAP54XX_RST_CPU0_WIDTH 0x1 +#define OMAP54XX_RST_CPU0_MASK (1 << 0) + +/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ +#define OMAP54XX_RST_CPU1_SHIFT 1 +#define OMAP54XX_RST_CPU1_WIDTH 0x1 +#define OMAP54XX_RST_CPU1_MASK (1 << 1) + +/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */ +#define OMAP54XX_RST_DSP_SHIFT 0 +#define OMAP54XX_RST_DSP_WIDTH 0x1 +#define OMAP54XX_RST_DSP_MASK (1 << 0) + +/* Used by RM_DSP_RSTST */ +#define OMAP54XX_RST_DSP_EMU_SHIFT 2 +#define OMAP54XX_RST_DSP_EMU_WIDTH 0x1 +#define OMAP54XX_RST_DSP_EMU_MASK (1 << 2) + +/* Used by RM_DSP_RSTST */ +#define OMAP54XX_RST_DSP_EMU_REQ_SHIFT 3 +#define OMAP54XX_RST_DSP_EMU_REQ_WIDTH 0x1 +#define OMAP54XX_RST_DSP_EMU_REQ_MASK (1 << 3) + +/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */ +#define OMAP54XX_RST_DSP_MMU_CACHE_SHIFT 1 +#define OMAP54XX_RST_DSP_MMU_CACHE_WIDTH 0x1 +#define OMAP54XX_RST_DSP_MMU_CACHE_MASK (1 << 1) + +/* Used by RM_IPU_RSTST */ +#define OMAP54XX_RST_EMULATION_CPU0_SHIFT 3 +#define OMAP54XX_RST_EMULATION_CPU0_WIDTH 0x1 +#define OMAP54XX_RST_EMULATION_CPU0_MASK (1 << 3) + +/* Used by RM_IPU_RSTST */ +#define OMAP54XX_RST_EMULATION_CPU1_SHIFT 4 +#define OMAP54XX_RST_EMULATION_CPU1_WIDTH 0x1 +#define OMAP54XX_RST_EMULATION_CPU1_MASK (1 << 4) + +/* Used by RM_IVA_RSTST */ +#define OMAP54XX_RST_EMULATION_SEQ1_SHIFT 3 +#define OMAP54XX_RST_EMULATION_SEQ1_WIDTH 0x1 +#define OMAP54XX_RST_EMULATION_SEQ1_MASK (1 << 3) + +/* Used by RM_IVA_RSTST */ +#define OMAP54XX_RST_EMULATION_SEQ2_SHIFT 4 +#define OMAP54XX_RST_EMULATION_SEQ2_WIDTH 0x1 +#define OMAP54XX_RST_EMULATION_SEQ2_MASK (1 << 4) + +/* Used by PRM_RSTCTRL */ +#define OMAP54XX_RST_GLOBAL_COLD_SW_SHIFT 1 +#define OMAP54XX_RST_GLOBAL_COLD_SW_WIDTH 0x1 +#define OMAP54XX_RST_GLOBAL_COLD_SW_MASK (1 << 1) + +/* Used by PRM_RSTCTRL */ +#define OMAP54XX_RST_GLOBAL_WARM_SW_SHIFT 0 +#define OMAP54XX_RST_GLOBAL_WARM_SW_WIDTH 0x1 +#define OMAP54XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) + +/* Used by RM_IPU_RSTST */ +#define OMAP54XX_RST_ICECRUSHER_CPU0_SHIFT 5 +#define OMAP54XX_RST_ICECRUSHER_CPU0_WIDTH 0x1 +#define OMAP54XX_RST_ICECRUSHER_CPU0_MASK (1 << 5) + +/* Used by RM_IPU_RSTST */ +#define OMAP54XX_RST_ICECRUSHER_CPU1_SHIFT 6 +#define OMAP54XX_RST_ICECRUSHER_CPU1_WIDTH 0x1 +#define OMAP54XX_RST_ICECRUSHER_CPU1_MASK (1 << 6) + +/* Used by RM_IVA_RSTST */ +#define OMAP54XX_RST_ICECRUSHER_SEQ1_SHIFT 5 +#define OMAP54XX_RST_ICECRUSHER_SEQ1_WIDTH 0x1 +#define OMAP54XX_RST_ICECRUSHER_SEQ1_MASK (1 << 5) + +/* Used by RM_IVA_RSTST */ +#define OMAP54XX_RST_ICECRUSHER_SEQ2_SHIFT 6 +#define OMAP54XX_RST_ICECRUSHER_SEQ2_WIDTH 0x1 +#define OMAP54XX_RST_ICECRUSHER_SEQ2_MASK (1 << 6) + +/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ +#define OMAP54XX_RST_IPU_MMU_CACHE_SHIFT 2 +#define OMAP54XX_RST_IPU_MMU_CACHE_WIDTH 0x1 +#define OMAP54XX_RST_IPU_MMU_CACHE_MASK (1 << 2) + +/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ +#define OMAP54XX_RST_LOGIC_SHIFT 2 +#define OMAP54XX_RST_LOGIC_WIDTH 0x1 +#define OMAP54XX_RST_LOGIC_MASK (1 << 2) + +/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ +#define OMAP54XX_RST_SEQ1_SHIFT 0 +#define OMAP54XX_RST_SEQ1_WIDTH 0x1 +#define OMAP54XX_RST_SEQ1_MASK (1 << 0) + +/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ +#define OMAP54XX_RST_SEQ2_SHIFT 1 +#define OMAP54XX_RST_SEQ2_WIDTH 0x1 +#define OMAP54XX_RST_SEQ2_MASK (1 << 1) + +/* Used by REVISION_PRM */ +#define OMAP54XX_R_RTL_SHIFT 11 +#define OMAP54XX_R_RTL_WIDTH 0x5 +#define OMAP54XX_R_RTL_MASK (0x1f << 11) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_SA_VDD_CORE_L_SHIFT 0 +#define OMAP54XX_SA_VDD_CORE_L_WIDTH 0x7 +#define OMAP54XX_SA_VDD_CORE_L_MASK (0x7f << 0) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_SA_VDD_MM_L_SHIFT 0 +#define OMAP54XX_SA_VDD_MM_L_WIDTH 0x7 +#define OMAP54XX_SA_VDD_MM_L_MASK (0x7f << 0) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_SA_VDD_MPU_L_SHIFT 0 +#define OMAP54XX_SA_VDD_MPU_L_WIDTH 0x7 +#define OMAP54XX_SA_VDD_MPU_L_MASK (0x7f << 0) + +/* Used by REVISION_PRM */ +#define OMAP54XX_SCHEME_SHIFT 30 +#define OMAP54XX_SCHEME_WIDTH 0x2 +#define OMAP54XX_SCHEME_MASK (0x3 << 30) + +/* Used by PRM_VC_CFG_I2C_CLK */ +#define OMAP54XX_SCLH_SHIFT 0 +#define OMAP54XX_SCLH_WIDTH 0x8 +#define OMAP54XX_SCLH_MASK (0xff << 0) + +/* Used by PRM_VC_CFG_I2C_CLK */ +#define OMAP54XX_SCLL_SHIFT 8 +#define OMAP54XX_SCLL_WIDTH 0x8 +#define OMAP54XX_SCLL_MASK (0xff << 8) + +/* Used by PRM_RSTST */ +#define OMAP54XX_SECURE_WDT_RST_SHIFT 4 +#define OMAP54XX_SECURE_WDT_RST_WIDTH 0x1 +#define OMAP54XX_SECURE_WDT_RST_MASK (1 << 4) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_SEL_SA_VDD_CORE_L_SHIFT 24 +#define OMAP54XX_SEL_SA_VDD_CORE_L_WIDTH 0x1 +#define OMAP54XX_SEL_SA_VDD_CORE_L_MASK (1 << 24) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_SEL_SA_VDD_MM_L_SHIFT 24 +#define OMAP54XX_SEL_SA_VDD_MM_L_WIDTH 0x1 +#define OMAP54XX_SEL_SA_VDD_MM_L_MASK (1 << 24) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_SEL_SA_VDD_MPU_L_SHIFT 24 +#define OMAP54XX_SEL_SA_VDD_MPU_L_WIDTH 0x1 +#define OMAP54XX_SEL_SA_VDD_MPU_L_MASK (1 << 24) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_SL2_MEM_ONSTATE_SHIFT 18 +#define OMAP54XX_SL2_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_SL2_MEM_ONSTATE_MASK (0x3 << 18) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_SL2_MEM_RETSTATE_SHIFT 9 +#define OMAP54XX_SL2_MEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_SL2_MEM_RETSTATE_MASK (1 << 9) + +/* Used by PM_IVA_PWRSTST */ +#define OMAP54XX_SL2_MEM_STATEST_SHIFT 6 +#define OMAP54XX_SL2_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_SL2_MEM_STATEST_MASK (0x3 << 6) + +/* Used by PRM_VC_VAL_BYPASS */ +#define OMAP54XX_SLAVEADDR_SHIFT 0 +#define OMAP54XX_SLAVEADDR_WIDTH 0x7 +#define OMAP54XX_SLAVEADDR_MASK (0x7f << 0) + +/* Used by PRM_SRAM_COUNT */ +#define OMAP54XX_SLPCNT_VALUE_SHIFT 16 +#define OMAP54XX_SLPCNT_VALUE_WIDTH 0x8 +#define OMAP54XX_SLPCNT_VALUE_MASK (0xff << 16) + +/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ +#define OMAP54XX_SMPSWAITTIMEMAX_SHIFT 8 +#define OMAP54XX_SMPSWAITTIMEMAX_WIDTH 0x10 +#define OMAP54XX_SMPSWAITTIMEMAX_MASK (0xffff << 8) + +/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ +#define OMAP54XX_SMPSWAITTIMEMIN_SHIFT 8 +#define OMAP54XX_SMPSWAITTIMEMIN_WIDTH 0x10 +#define OMAP54XX_SMPSWAITTIMEMIN_MASK (0xffff << 8) + +/* Used by PRM_VC_CORE_ERRST */ +#define OMAP54XX_SMPS_RA_ERR_CORE_SHIFT 1 +#define OMAP54XX_SMPS_RA_ERR_CORE_WIDTH 0x1 +#define OMAP54XX_SMPS_RA_ERR_CORE_MASK (1 << 1) + +/* Used by PRM_VC_MM_ERRST */ +#define OMAP54XX_SMPS_RA_ERR_MM_SHIFT 1 +#define OMAP54XX_SMPS_RA_ERR_MM_WIDTH 0x1 +#define OMAP54XX_SMPS_RA_ERR_MM_MASK (1 << 1) + +/* Used by PRM_VC_MPU_ERRST */ +#define OMAP54XX_SMPS_RA_ERR_MPU_SHIFT 1 +#define OMAP54XX_SMPS_RA_ERR_MPU_WIDTH 0x1 +#define OMAP54XX_SMPS_RA_ERR_MPU_MASK (1 << 1) + +/* Used by PRM_VC_CORE_ERRST */ +#define OMAP54XX_SMPS_SA_ERR_CORE_SHIFT 0 +#define OMAP54XX_SMPS_SA_ERR_CORE_WIDTH 0x1 +#define OMAP54XX_SMPS_SA_ERR_CORE_MASK (1 << 0) + +/* Used by PRM_VC_MM_ERRST */ +#define OMAP54XX_SMPS_SA_ERR_MM_SHIFT 0 +#define OMAP54XX_SMPS_SA_ERR_MM_WIDTH 0x1 +#define OMAP54XX_SMPS_SA_ERR_MM_MASK (1 << 0) + +/* Used by PRM_VC_MPU_ERRST */ +#define OMAP54XX_SMPS_SA_ERR_MPU_SHIFT 0 +#define OMAP54XX_SMPS_SA_ERR_MPU_WIDTH 0x1 +#define OMAP54XX_SMPS_SA_ERR_MPU_MASK (1 << 0) + +/* Used by PRM_VC_CORE_ERRST */ +#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_SHIFT 2 +#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_WIDTH 0x1 +#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2) + +/* Used by PRM_VC_MM_ERRST */ +#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_SHIFT 2 +#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_WIDTH 0x1 +#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_MASK (1 << 2) + +/* Used by PRM_VC_MPU_ERRST */ +#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_SHIFT 2 +#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_WIDTH 0x1 +#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 2) + +/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ +#define OMAP54XX_SR2EN_SHIFT 0 +#define OMAP54XX_SR2EN_WIDTH 0x1 +#define OMAP54XX_SR2EN_MASK (1 << 0) + +/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ +#define OMAP54XX_SR2_IN_TRANSITION_SHIFT 6 +#define OMAP54XX_SR2_IN_TRANSITION_WIDTH 0x1 +#define OMAP54XX_SR2_IN_TRANSITION_MASK (1 << 6) + +/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ +#define OMAP54XX_SR2_STATUS_SHIFT 3 +#define OMAP54XX_SR2_STATUS_WIDTH 0x2 +#define OMAP54XX_SR2_STATUS_MASK (0x3 << 3) + +/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ +#define OMAP54XX_SR2_WTCNT_VALUE_SHIFT 8 +#define OMAP54XX_SR2_WTCNT_VALUE_WIDTH 0x8 +#define OMAP54XX_SR2_WTCNT_VALUE_MASK (0xff << 8) + +/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ +#define OMAP54XX_SRAMLDO_STATUS_SHIFT 8 +#define OMAP54XX_SRAMLDO_STATUS_WIDTH 0x1 +#define OMAP54XX_SRAMLDO_STATUS_MASK (1 << 8) + +/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ +#define OMAP54XX_SRAM_IN_TRANSITION_SHIFT 9 +#define OMAP54XX_SRAM_IN_TRANSITION_WIDTH 0x1 +#define OMAP54XX_SRAM_IN_TRANSITION_MASK (1 << 9) + +/* Used by PRM_VC_CFG_I2C_MODE */ +#define OMAP54XX_SRMODEEN_SHIFT 4 +#define OMAP54XX_SRMODEEN_WIDTH 0x1 +#define OMAP54XX_SRMODEEN_MASK (1 << 4) + +/* Used by PRM_VOLTSETUP_WARMRESET */ +#define OMAP54XX_STABLE_COUNT_SHIFT 0 +#define OMAP54XX_STABLE_COUNT_WIDTH 0x6 +#define OMAP54XX_STABLE_COUNT_MASK (0x3f << 0) + +/* Used by PRM_VOLTSETUP_WARMRESET */ +#define OMAP54XX_STABLE_PRESCAL_SHIFT 8 +#define OMAP54XX_STABLE_PRESCAL_WIDTH 0x2 +#define OMAP54XX_STABLE_PRESCAL_MASK (0x3 << 8) + +/* Used by PRM_BANDGAP_SETUP */ +#define OMAP54XX_STARTUP_COUNT_SHIFT 0 +#define OMAP54XX_STARTUP_COUNT_WIDTH 0x8 +#define OMAP54XX_STARTUP_COUNT_MASK (0xff << 0) + +/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */ +#define OMAP54XX_STARTUP_COUNT_24_31_SHIFT 24 +#define OMAP54XX_STARTUP_COUNT_24_31_WIDTH 0x8 +#define OMAP54XX_STARTUP_COUNT_24_31_MASK (0xff << 24) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_TCM1_MEM_ONSTATE_SHIFT 20 +#define OMAP54XX_TCM1_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_TCM1_MEM_ONSTATE_MASK (0x3 << 20) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_TCM1_MEM_RETSTATE_SHIFT 10 +#define OMAP54XX_TCM1_MEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_TCM1_MEM_RETSTATE_MASK (1 << 10) + +/* Used by PM_IVA_PWRSTST */ +#define OMAP54XX_TCM1_MEM_STATEST_SHIFT 8 +#define OMAP54XX_TCM1_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_TCM1_MEM_STATEST_MASK (0x3 << 8) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_TCM2_MEM_ONSTATE_SHIFT 22 +#define OMAP54XX_TCM2_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_TCM2_MEM_ONSTATE_MASK (0x3 << 22) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_TCM2_MEM_RETSTATE_SHIFT 11 +#define OMAP54XX_TCM2_MEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_TCM2_MEM_RETSTATE_MASK (1 << 11) + +/* Used by PM_IVA_PWRSTST */ +#define OMAP54XX_TCM2_MEM_STATEST_SHIFT 10 +#define OMAP54XX_TCM2_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_TCM2_MEM_STATEST_MASK (0x3 << 10) + +/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ +#define OMAP54XX_TIMEOUT_SHIFT 0 +#define OMAP54XX_TIMEOUT_WIDTH 0x10 +#define OMAP54XX_TIMEOUT_MASK (0xffff << 0) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_TIMEOUTEN_SHIFT 3 +#define OMAP54XX_TIMEOUTEN_WIDTH 0x1 +#define OMAP54XX_TIMEOUTEN_MASK (1 << 3) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_TRANSITION_EN_SHIFT 8 +#define OMAP54XX_TRANSITION_EN_WIDTH 0x1 +#define OMAP54XX_TRANSITION_EN_MASK (1 << 8) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_TRANSITION_ST_SHIFT 8 +#define OMAP54XX_TRANSITION_ST_WIDTH 0x1 +#define OMAP54XX_TRANSITION_ST_MASK (1 << 8) + +/* Used by PRM_DEBUG_TRANS_CFG */ +#define OMAP54XX_TRIGGER_CLEAR_SHIFT 2 +#define OMAP54XX_TRIGGER_CLEAR_WIDTH 0x1 +#define OMAP54XX_TRIGGER_CLEAR_MASK (1 << 2) + +/* Used by PRM_RSTST */ +#define OMAP54XX_TSHUT_CORE_RST_SHIFT 13 +#define OMAP54XX_TSHUT_CORE_RST_WIDTH 0x1 +#define OMAP54XX_TSHUT_CORE_RST_MASK (1 << 13) + +/* Used by PRM_RSTST */ +#define OMAP54XX_TSHUT_MM_RST_SHIFT 12 +#define OMAP54XX_TSHUT_MM_RST_WIDTH 0x1 +#define OMAP54XX_TSHUT_MM_RST_MASK (1 << 12) + +/* Used by PRM_RSTST */ +#define OMAP54XX_TSHUT_MPU_RST_SHIFT 11 +#define OMAP54XX_TSHUT_MPU_RST_WIDTH 0x1 +#define OMAP54XX_TSHUT_MPU_RST_MASK (1 << 11) + +/* Used by PRM_VC_VAL_BYPASS */ +#define OMAP54XX_VALID_SHIFT 24 +#define OMAP54XX_VALID_WIDTH 0x1 +#define OMAP54XX_VALID_MASK (1 << 24) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VC_BYPASSACK_EN_SHIFT 14 +#define OMAP54XX_VC_BYPASSACK_EN_WIDTH 0x1 +#define OMAP54XX_VC_BYPASSACK_EN_MASK (1 << 14) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VC_BYPASSACK_ST_SHIFT 14 +#define OMAP54XX_VC_BYPASSACK_ST_WIDTH 0x1 +#define OMAP54XX_VC_BYPASSACK_ST_MASK (1 << 14) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VC_CORE_VPACK_EN_SHIFT 22 +#define OMAP54XX_VC_CORE_VPACK_EN_WIDTH 0x1 +#define OMAP54XX_VC_CORE_VPACK_EN_MASK (1 << 22) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VC_CORE_VPACK_ST_SHIFT 22 +#define OMAP54XX_VC_CORE_VPACK_ST_WIDTH 0x1 +#define OMAP54XX_VC_CORE_VPACK_ST_MASK (1 << 22) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VC_MM_VPACK_EN_SHIFT 30 +#define OMAP54XX_VC_MM_VPACK_EN_WIDTH 0x1 +#define OMAP54XX_VC_MM_VPACK_EN_MASK (1 << 30) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VC_MM_VPACK_ST_SHIFT 30 +#define OMAP54XX_VC_MM_VPACK_ST_WIDTH 0x1 +#define OMAP54XX_VC_MM_VPACK_ST_MASK (1 << 30) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VC_MPU_VPACK_EN_SHIFT 6 +#define OMAP54XX_VC_MPU_VPACK_EN_WIDTH 0x1 +#define OMAP54XX_VC_MPU_VPACK_EN_MASK (1 << 6) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VC_MPU_VPACK_ST_SHIFT 6 +#define OMAP54XX_VC_MPU_VPACK_ST_WIDTH 0x1 +#define OMAP54XX_VC_MPU_VPACK_ST_MASK (1 << 6) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VC_RAERR_EN_SHIFT 12 +#define OMAP54XX_VC_RAERR_EN_WIDTH 0x1 +#define OMAP54XX_VC_RAERR_EN_MASK (1 << 12) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VC_RAERR_ST_SHIFT 12 +#define OMAP54XX_VC_RAERR_ST_WIDTH 0x1 +#define OMAP54XX_VC_RAERR_ST_MASK (1 << 12) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VC_SAERR_EN_SHIFT 11 +#define OMAP54XX_VC_SAERR_EN_WIDTH 0x1 +#define OMAP54XX_VC_SAERR_EN_MASK (1 << 11) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VC_SAERR_ST_SHIFT 11 +#define OMAP54XX_VC_SAERR_ST_WIDTH 0x1 +#define OMAP54XX_VC_SAERR_ST_MASK (1 << 11) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VC_TOERR_EN_SHIFT 13 +#define OMAP54XX_VC_TOERR_EN_WIDTH 0x1 +#define OMAP54XX_VC_TOERR_EN_MASK (1 << 13) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VC_TOERR_ST_SHIFT 13 +#define OMAP54XX_VC_TOERR_ST_WIDTH 0x1 +#define OMAP54XX_VC_TOERR_ST_MASK (1 << 13) + +/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ +#define OMAP54XX_VDDMAX_SHIFT 24 +#define OMAP54XX_VDDMAX_WIDTH 0x8 +#define OMAP54XX_VDDMAX_MASK (0xff << 24) + +/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ +#define OMAP54XX_VDDMIN_SHIFT 16 +#define OMAP54XX_VDDMIN_WIDTH 0x8 +#define OMAP54XX_VDDMIN_MASK (0xff << 16) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_VDD_CORE_I2C_DISABLE_SHIFT 12 +#define OMAP54XX_VDD_CORE_I2C_DISABLE_WIDTH 0x1 +#define OMAP54XX_VDD_CORE_I2C_DISABLE_MASK (1 << 12) + +/* Used by PRM_RSTST */ +#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_SHIFT 8 +#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_WIDTH 0x1 +#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_VDD_MM_I2C_DISABLE_SHIFT 14 +#define OMAP54XX_VDD_MM_I2C_DISABLE_WIDTH 0x1 +#define OMAP54XX_VDD_MM_I2C_DISABLE_MASK (1 << 14) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_VDD_MM_PRESENCE_SHIFT 9 +#define OMAP54XX_VDD_MM_PRESENCE_WIDTH 0x1 +#define OMAP54XX_VDD_MM_PRESENCE_MASK (1 << 9) + +/* Used by PRM_RSTST */ +#define OMAP54XX_VDD_MM_VOLT_MGR_RST_SHIFT 7 +#define OMAP54XX_VDD_MM_VOLT_MGR_RST_WIDTH 0x1 +#define OMAP54XX_VDD_MM_VOLT_MGR_RST_MASK (1 << 7) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_VDD_MPU_I2C_DISABLE_SHIFT 13 +#define OMAP54XX_VDD_MPU_I2C_DISABLE_WIDTH 0x1 +#define OMAP54XX_VDD_MPU_I2C_DISABLE_MASK (1 << 13) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_VDD_MPU_PRESENCE_SHIFT 8 +#define OMAP54XX_VDD_MPU_PRESENCE_WIDTH 0x1 +#define OMAP54XX_VDD_MPU_PRESENCE_MASK (1 << 8) + +/* Used by PRM_RSTST */ +#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_SHIFT 6 +#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_WIDTH 0x1 +#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6) + +/* Used by PRM_VC_CORE_ERRST */ +#define OMAP54XX_VFSM_RA_ERR_CORE_SHIFT 4 +#define OMAP54XX_VFSM_RA_ERR_CORE_WIDTH 0x1 +#define OMAP54XX_VFSM_RA_ERR_CORE_MASK (1 << 4) + +/* Used by PRM_VC_MM_ERRST */ +#define OMAP54XX_VFSM_RA_ERR_MM_SHIFT 4 +#define OMAP54XX_VFSM_RA_ERR_MM_WIDTH 0x1 +#define OMAP54XX_VFSM_RA_ERR_MM_MASK (1 << 4) + +/* Used by PRM_VC_MPU_ERRST */ +#define OMAP54XX_VFSM_RA_ERR_MPU_SHIFT 4 +#define OMAP54XX_VFSM_RA_ERR_MPU_WIDTH 0x1 +#define OMAP54XX_VFSM_RA_ERR_MPU_MASK (1 << 4) + +/* Used by PRM_VC_CORE_ERRST */ +#define OMAP54XX_VFSM_SA_ERR_CORE_SHIFT 3 +#define OMAP54XX_VFSM_SA_ERR_CORE_WIDTH 0x1 +#define OMAP54XX_VFSM_SA_ERR_CORE_MASK (1 << 3) + +/* Used by PRM_VC_MM_ERRST */ +#define OMAP54XX_VFSM_SA_ERR_MM_SHIFT 3 +#define OMAP54XX_VFSM_SA_ERR_MM_WIDTH 0x1 +#define OMAP54XX_VFSM_SA_ERR_MM_MASK (1 << 3) + +/* Used by PRM_VC_MPU_ERRST */ +#define OMAP54XX_VFSM_SA_ERR_MPU_SHIFT 3 +#define OMAP54XX_VFSM_SA_ERR_MPU_WIDTH 0x1 +#define OMAP54XX_VFSM_SA_ERR_MPU_MASK (1 << 3) + +/* Used by PRM_VC_CORE_ERRST */ +#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_SHIFT 5 +#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_WIDTH 0x1 +#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5) + +/* Used by PRM_VC_MM_ERRST */ +#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_SHIFT 5 +#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_WIDTH 0x1 +#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_MASK (1 << 5) + +/* Used by PRM_VC_MPU_ERRST */ +#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_SHIFT 5 +#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_WIDTH 0x1 +#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 5) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_VOLRA_VDD_CORE_L_SHIFT 8 +#define OMAP54XX_VOLRA_VDD_CORE_L_WIDTH 0x8 +#define OMAP54XX_VOLRA_VDD_CORE_L_MASK (0xff << 8) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_VOLRA_VDD_MM_L_SHIFT 8 +#define OMAP54XX_VOLRA_VDD_MM_L_WIDTH 0x8 +#define OMAP54XX_VOLRA_VDD_MM_L_MASK (0xff << 8) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_VOLRA_VDD_MPU_L_SHIFT 8 +#define OMAP54XX_VOLRA_VDD_MPU_L_WIDTH 0x8 +#define OMAP54XX_VOLRA_VDD_MPU_L_MASK (0xff << 8) + +/* Used by PRM_VOLTST_MM, PRM_VOLTST_MPU */ +#define OMAP54XX_VOLTSTATEST_SHIFT 0 +#define OMAP54XX_VOLTSTATEST_WIDTH 0x2 +#define OMAP54XX_VOLTSTATEST_MASK (0x3 << 0) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_VPENABLE_SHIFT 0 +#define OMAP54XX_VPENABLE_WIDTH 0x1 +#define OMAP54XX_VPENABLE_MASK (1 << 0) + +/* Used by PRM_VP_CORE_STATUS, PRM_VP_MM_STATUS, PRM_VP_MPU_STATUS */ +#define OMAP54XX_VPINIDLE_SHIFT 0 +#define OMAP54XX_VPINIDLE_WIDTH 0x1 +#define OMAP54XX_VPINIDLE_MASK (1 << 0) + +/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */ +#define OMAP54XX_VPVOLTAGE_SHIFT 0 +#define OMAP54XX_VPVOLTAGE_WIDTH 0x8 +#define OMAP54XX_VPVOLTAGE_MASK (0xff << 0) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_CORE_EQVALUE_EN_SHIFT 20 +#define OMAP54XX_VP_CORE_EQVALUE_EN_WIDTH 0x1 +#define OMAP54XX_VP_CORE_EQVALUE_EN_MASK (1 << 20) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_CORE_EQVALUE_ST_SHIFT 20 +#define OMAP54XX_VP_CORE_EQVALUE_ST_WIDTH 0x1 +#define OMAP54XX_VP_CORE_EQVALUE_ST_MASK (1 << 20) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_CORE_MAXVDD_EN_SHIFT 18 +#define OMAP54XX_VP_CORE_MAXVDD_EN_WIDTH 0x1 +#define OMAP54XX_VP_CORE_MAXVDD_EN_MASK (1 << 18) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_CORE_MAXVDD_ST_SHIFT 18 +#define OMAP54XX_VP_CORE_MAXVDD_ST_WIDTH 0x1 +#define OMAP54XX_VP_CORE_MAXVDD_ST_MASK (1 << 18) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_CORE_MINVDD_EN_SHIFT 17 +#define OMAP54XX_VP_CORE_MINVDD_EN_WIDTH 0x1 +#define OMAP54XX_VP_CORE_MINVDD_EN_MASK (1 << 17) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_CORE_MINVDD_ST_SHIFT 17 +#define OMAP54XX_VP_CORE_MINVDD_ST_WIDTH 0x1 +#define OMAP54XX_VP_CORE_MINVDD_ST_MASK (1 << 17) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_CORE_NOSMPSACK_EN_SHIFT 19 +#define OMAP54XX_VP_CORE_NOSMPSACK_EN_WIDTH 0x1 +#define OMAP54XX_VP_CORE_NOSMPSACK_EN_MASK (1 << 19) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_CORE_NOSMPSACK_ST_SHIFT 19 +#define OMAP54XX_VP_CORE_NOSMPSACK_ST_WIDTH 0x1 +#define OMAP54XX_VP_CORE_NOSMPSACK_ST_MASK (1 << 19) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 +#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_WIDTH 0x1 +#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 +#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_WIDTH 0x1 +#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_CORE_TRANXDONE_EN_SHIFT 21 +#define OMAP54XX_VP_CORE_TRANXDONE_EN_WIDTH 0x1 +#define OMAP54XX_VP_CORE_TRANXDONE_EN_MASK (1 << 21) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_CORE_TRANXDONE_ST_SHIFT 21 +#define OMAP54XX_VP_CORE_TRANXDONE_ST_WIDTH 0x1 +#define OMAP54XX_VP_CORE_TRANXDONE_ST_MASK (1 << 21) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_MM_EQVALUE_EN_SHIFT 28 +#define OMAP54XX_VP_MM_EQVALUE_EN_WIDTH 0x1 +#define OMAP54XX_VP_MM_EQVALUE_EN_MASK (1 << 28) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_MM_EQVALUE_ST_SHIFT 28 +#define OMAP54XX_VP_MM_EQVALUE_ST_WIDTH 0x1 +#define OMAP54XX_VP_MM_EQVALUE_ST_MASK (1 << 28) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_MM_MAXVDD_EN_SHIFT 26 +#define OMAP54XX_VP_MM_MAXVDD_EN_WIDTH 0x1 +#define OMAP54XX_VP_MM_MAXVDD_EN_MASK (1 << 26) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_MM_MAXVDD_ST_SHIFT 26 +#define OMAP54XX_VP_MM_MAXVDD_ST_WIDTH 0x1 +#define OMAP54XX_VP_MM_MAXVDD_ST_MASK (1 << 26) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_MM_MINVDD_EN_SHIFT 25 +#define OMAP54XX_VP_MM_MINVDD_EN_WIDTH 0x1 +#define OMAP54XX_VP_MM_MINVDD_EN_MASK (1 << 25) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_MM_MINVDD_ST_SHIFT 25 +#define OMAP54XX_VP_MM_MINVDD_ST_WIDTH 0x1 +#define OMAP54XX_VP_MM_MINVDD_ST_MASK (1 << 25) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_MM_NOSMPSACK_EN_SHIFT 27 +#define OMAP54XX_VP_MM_NOSMPSACK_EN_WIDTH 0x1 +#define OMAP54XX_VP_MM_NOSMPSACK_EN_MASK (1 << 27) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_MM_NOSMPSACK_ST_SHIFT 27 +#define OMAP54XX_VP_MM_NOSMPSACK_ST_WIDTH 0x1 +#define OMAP54XX_VP_MM_NOSMPSACK_ST_MASK (1 << 27) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_SHIFT 24 +#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_WIDTH 0x1 +#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_MASK (1 << 24) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_SHIFT 24 +#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_WIDTH 0x1 +#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_MASK (1 << 24) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_MM_TRANXDONE_EN_SHIFT 29 +#define OMAP54XX_VP_MM_TRANXDONE_EN_WIDTH 0x1 +#define OMAP54XX_VP_MM_TRANXDONE_EN_MASK (1 << 29) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_MM_TRANXDONE_ST_SHIFT 29 +#define OMAP54XX_VP_MM_TRANXDONE_ST_WIDTH 0x1 +#define OMAP54XX_VP_MM_TRANXDONE_ST_MASK (1 << 29) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VP_MPU_EQVALUE_EN_SHIFT 4 +#define OMAP54XX_VP_MPU_EQVALUE_EN_WIDTH 0x1 +#define OMAP54XX_VP_MPU_EQVALUE_EN_MASK (1 << 4) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VP_MPU_EQVALUE_ST_SHIFT 4 +#define OMAP54XX_VP_MPU_EQVALUE_ST_WIDTH 0x1 +#define OMAP54XX_VP_MPU_EQVALUE_ST_MASK (1 << 4) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VP_MPU_MAXVDD_EN_SHIFT 2 +#define OMAP54XX_VP_MPU_MAXVDD_EN_WIDTH 0x1 +#define OMAP54XX_VP_MPU_MAXVDD_EN_MASK (1 << 2) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VP_MPU_MAXVDD_ST_SHIFT 2 +#define OMAP54XX_VP_MPU_MAXVDD_ST_WIDTH 0x1 +#define OMAP54XX_VP_MPU_MAXVDD_ST_MASK (1 << 2) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VP_MPU_MINVDD_EN_SHIFT 1 +#define OMAP54XX_VP_MPU_MINVDD_EN_WIDTH 0x1 +#define OMAP54XX_VP_MPU_MINVDD_EN_MASK (1 << 1) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VP_MPU_MINVDD_ST_SHIFT 1 +#define OMAP54XX_VP_MPU_MINVDD_ST_WIDTH 0x1 +#define OMAP54XX_VP_MPU_MINVDD_ST_MASK (1 << 1) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VP_MPU_NOSMPSACK_EN_SHIFT 3 +#define OMAP54XX_VP_MPU_NOSMPSACK_EN_WIDTH 0x1 +#define OMAP54XX_VP_MPU_NOSMPSACK_EN_MASK (1 << 3) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VP_MPU_NOSMPSACK_ST_SHIFT 3 +#define OMAP54XX_VP_MPU_NOSMPSACK_ST_WIDTH 0x1 +#define OMAP54XX_VP_MPU_NOSMPSACK_ST_MASK (1 << 3) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 +#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_WIDTH 0x1 +#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 +#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_WIDTH 0x1 +#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VP_MPU_TRANXDONE_EN_SHIFT 5 +#define OMAP54XX_VP_MPU_TRANXDONE_EN_WIDTH 0x1 +#define OMAP54XX_VP_MPU_TRANXDONE_EN_MASK (1 << 5) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VP_MPU_TRANXDONE_ST_SHIFT 5 +#define OMAP54XX_VP_MPU_TRANXDONE_ST_WIDTH 0x1 +#define OMAP54XX_VP_MPU_TRANXDONE_ST_MASK (1 << 5) + +/* Used by PRM_SRAM_COUNT */ +#define OMAP54XX_VSETUPCNT_VALUE_SHIFT 8 +#define OMAP54XX_VSETUPCNT_VALUE_WIDTH 0x8 +#define OMAP54XX_VSETUPCNT_VALUE_MASK (0xff << 8) + +/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ +#define OMAP54XX_VSTEPMAX_SHIFT 0 +#define OMAP54XX_VSTEPMAX_WIDTH 0x8 +#define OMAP54XX_VSTEPMAX_MASK (0xff << 0) + +/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ +#define OMAP54XX_VSTEPMIN_SHIFT 0 +#define OMAP54XX_VSTEPMIN_WIDTH 0x8 +#define OMAP54XX_VSTEPMIN_MASK (0xff << 0) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DISPC_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_DISPC_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DISPC_DSP_MASK (1 << 2) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DISPC_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_DISPC_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DISPC_IPU_MASK (1 << 1) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DISPC_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_DISPC_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DISPC_MPU_MASK (1 << 0) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DISPC_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_DISPC_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DISPC_SDMA_MASK (1 << 3) + +/* Used by PM_ABE_DMIC_WKDEP */ +#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_MASK (1 << 6) + +/* Used by PM_ABE_DMIC_WKDEP */ +#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_ABE_DMIC_WKDEP */ +#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_MASK (1 << 2) + +/* Used by PM_ABE_DMIC_WKDEP */ +#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_A_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_DSI1_A_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_A_DSP_MASK (1 << 6) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_A_IPU_SHIFT 5 +#define OMAP54XX_WKUPDEP_DSI1_A_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_A_IPU_MASK (1 << 5) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_A_MPU_SHIFT 4 +#define OMAP54XX_WKUPDEP_DSI1_A_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_A_MPU_MASK (1 << 4) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_MASK (1 << 7) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_B_DSP_SHIFT 10 +#define OMAP54XX_WKUPDEP_DSI1_B_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_B_DSP_MASK (1 << 10) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_B_IPU_SHIFT 9 +#define OMAP54XX_WKUPDEP_DSI1_B_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_B_IPU_MASK (1 << 9) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_B_MPU_SHIFT 8 +#define OMAP54XX_WKUPDEP_DSI1_B_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_B_MPU_MASK (1 << 8) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_SHIFT 11 +#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_MASK (1 << 11) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_C_DSP_SHIFT 17 +#define OMAP54XX_WKUPDEP_DSI1_C_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_C_DSP_MASK (1 << 17) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_C_IPU_SHIFT 16 +#define OMAP54XX_WKUPDEP_DSI1_C_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_C_IPU_MASK (1 << 16) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_C_MPU_SHIFT 15 +#define OMAP54XX_WKUPDEP_DSI1_C_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_C_MPU_MASK (1 << 15) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_SHIFT 18 +#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_MASK (1 << 18) + +/* Used by PM_WKUPAON_GPIO1_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_MASK (1 << 1) + +/* Used by PM_WKUPAON_GPIO1_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_WKUPAON_GPIO1_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_MASK (1 << 6) + +/* Used by PM_L4PER_GPIO2_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_GPIO2_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_GPIO2_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_MASK (1 << 6) + +/* Used by PM_L4PER_GPIO3_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_GPIO3_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_MASK (1 << 6) + +/* Used by PM_L4PER_GPIO4_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_GPIO4_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_MASK (1 << 6) + +/* Used by PM_L4PER_GPIO5_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_GPIO5_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_MASK (1 << 6) + +/* Used by PM_L4PER_GPIO6_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_GPIO6_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_MASK (1 << 6) + +/* Used by PM_L4PER_GPIO7_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_GPIO8_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 +#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_SHIFT 14 +#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_MASK (1 << 14) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_SHIFT 13 +#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_MASK (1 << 13) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 +#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12) + +/* Used by PM_L3INIT_HSI_WKDEP */ +#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_MASK (1 << 6) + +/* Used by PM_L3INIT_HSI_WKDEP */ +#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_MASK (1 << 1) + +/* Used by PM_L3INIT_HSI_WKDEP */ +#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_I2C1_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_L4PER_I2C1_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_I2C1_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_I2C2_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_L4PER_I2C2_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_I2C2_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_I2C3_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_L4PER_I2C3_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_I2C3_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_I2C4_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_L4PER_I2C4_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_I2C4_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_I2C5_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_WKUPAON_KBD_WKDEP */ +#define OMAP54XX_WKUPDEP_KBD_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_KBD_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_KBD_MPU_MASK (1 << 0) + +/* Used by PM_ABE_MCASP_WKDEP */ +#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_MASK (1 << 6) + +/* Used by PM_ABE_MCASP_WKDEP */ +#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_ABE_MCASP_WKDEP */ +#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_MASK (1 << 2) + +/* Used by PM_ABE_MCASP_WKDEP */ +#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_ABE_MCBSP1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP1_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MCBSP1_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP1_DSP_MASK (1 << 2) + +/* Used by PM_ABE_MCBSP1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCBSP1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP1_MPU_MASK (1 << 0) + +/* Used by PM_ABE_MCBSP1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3) + +/* Used by PM_ABE_MCBSP2_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP2_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MCBSP2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP2_DSP_MASK (1 << 2) + +/* Used by PM_ABE_MCBSP2_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCBSP2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP2_MPU_MASK (1 << 0) + +/* Used by PM_ABE_MCBSP2_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3) + +/* Used by PM_ABE_MCBSP3_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP3_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MCBSP3_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP3_DSP_MASK (1 << 2) + +/* Used by PM_ABE_MCBSP3_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP3_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCBSP3_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP3_MPU_MASK (1 << 0) + +/* Used by PM_ABE_MCBSP3_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3) + +/* Used by PM_ABE_MCPDM_WKDEP */ +#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_MASK (1 << 6) + +/* Used by PM_ABE_MCPDM_WKDEP */ +#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_ABE_MCPDM_WKDEP */ +#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_MASK (1 << 2) + +/* Used by PM_ABE_MCPDM_WKDEP */ +#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MCSPI1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI1_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MCSPI1_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI1_DSP_MASK (1 << 2) + +/* Used by PM_L4PER_MCSPI1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI1_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_MCSPI1_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI1_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_MCSPI1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCSPI1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MCSPI1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_MCSPI2_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI2_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_MCSPI2_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI2_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_MCSPI2_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCSPI2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI2_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MCSPI2_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_MCSPI3_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI3_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCSPI3_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI3_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MCSPI3_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_MCSPI4_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI4_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCSPI4_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI4_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MCSPI4_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3) + +/* Used by PM_L3INIT_MMC1_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC1_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MMC1_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC1_DSP_MASK (1 << 2) + +/* Used by PM_L3INIT_MMC1_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC1_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_MMC1_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC1_IPU_MASK (1 << 1) + +/* Used by PM_L3INIT_MMC1_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MMC1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC1_MPU_MASK (1 << 0) + +/* Used by PM_L3INIT_MMC1_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC1_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MMC1_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC1_SDMA_MASK (1 << 3) + +/* Used by PM_L3INIT_MMC2_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC2_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MMC2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC2_DSP_MASK (1 << 2) + +/* Used by PM_L3INIT_MMC2_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC2_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_MMC2_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC2_IPU_MASK (1 << 1) + +/* Used by PM_L3INIT_MMC2_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MMC2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC2_MPU_MASK (1 << 0) + +/* Used by PM_L3INIT_MMC2_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC2_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MMC2_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC2_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_MMC3_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC3_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_MMC3_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC3_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_MMC3_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC3_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MMC3_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC3_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MMC3_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC3_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MMC3_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC3_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_MMC4_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC4_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MMC4_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC4_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MMC4_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC4_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MMC4_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC4_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_MMC5_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC5_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MMC5_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC5_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MMC5_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC5_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MMC5_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC5_SDMA_MASK (1 << 3) + +/* Used by PM_L3INIT_SATA_WKDEP */ +#define OMAP54XX_WKUPDEP_SATA_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_SATA_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SATA_MPU_MASK (1 << 0) + +/* Used by PM_ABE_SLIMBUS1_WKDEP */ +#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_MASK (1 << 6) + +/* Used by PM_ABE_SLIMBUS1_WKDEP */ +#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_ABE_SLIMBUS1_WKDEP */ +#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_MASK (1 << 2) + +/* Used by PM_ABE_SLIMBUS1_WKDEP */ +#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */ +#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_MASK (1 << 1) + +/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */ +#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_MASK (1 << 0) + +/* Used by PM_COREAON_SMARTREFLEX_MM_WKDEP */ +#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_MASK (1 << 0) + +/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */ +#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_TIMER10_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER10_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER10_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER10_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_TIMER11_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER11_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_TIMER11_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER11_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_TIMER11_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER11_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER11_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER11_MPU_MASK (1 << 0) + +/* Used by PM_WKUPAON_TIMER12_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER12_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER12_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER12_MPU_MASK (1 << 0) + +/* Used by PM_WKUPAON_TIMER1_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_TIMER2_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER2_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_TIMER3_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER3_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_TIMER3_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER3_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_TIMER3_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER3_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER3_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER3_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_TIMER4_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER4_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_TIMER4_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER4_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_TIMER4_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER4_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER4_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER4_MPU_MASK (1 << 0) + +/* Used by PM_ABE_TIMER5_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER5_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_TIMER5_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER5_DSP_MASK (1 << 2) + +/* Used by PM_ABE_TIMER5_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER5_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER5_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER5_MPU_MASK (1 << 0) + +/* Used by PM_ABE_TIMER6_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER6_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_TIMER6_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER6_DSP_MASK (1 << 2) + +/* Used by PM_ABE_TIMER6_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER6_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER6_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER6_MPU_MASK (1 << 0) + +/* Used by PM_ABE_TIMER7_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER7_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_TIMER7_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER7_DSP_MASK (1 << 2) + +/* Used by PM_ABE_TIMER7_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER7_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER7_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER7_MPU_MASK (1 << 0) + +/* Used by PM_ABE_TIMER8_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER8_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_TIMER8_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER8_DSP_MASK (1 << 2) + +/* Used by PM_ABE_TIMER8_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER8_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER8_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER8_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_TIMER9_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER9_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_TIMER9_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER9_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_TIMER9_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER9_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER9_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER9_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART1_WKDEP */ +#define OMAP54XX_WKUPDEP_UART1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UART1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART1_WKDEP */ +#define OMAP54XX_WKUPDEP_UART1_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_UART1_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART1_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_UART2_WKDEP */ +#define OMAP54XX_WKUPDEP_UART2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UART2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART2_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART2_WKDEP */ +#define OMAP54XX_WKUPDEP_UART2_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_UART2_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART2_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_UART3_WKDEP */ +#define OMAP54XX_WKUPDEP_UART3_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_UART3_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART3_DSP_MASK (1 << 2) + +/* Used by PM_L4PER_UART3_WKDEP */ +#define OMAP54XX_WKUPDEP_UART3_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_UART3_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART3_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_UART3_WKDEP */ +#define OMAP54XX_WKUPDEP_UART3_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UART3_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART3_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART3_WKDEP */ +#define OMAP54XX_WKUPDEP_UART3_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_UART3_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART3_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_UART4_WKDEP */ +#define OMAP54XX_WKUPDEP_UART4_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UART4_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART4_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART4_WKDEP */ +#define OMAP54XX_WKUPDEP_UART4_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_UART4_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART4_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_UART5_WKDEP */ +#define OMAP54XX_WKUPDEP_UART5_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UART5_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART5_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART5_WKDEP */ +#define OMAP54XX_WKUPDEP_UART5_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_UART5_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART5_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_UART6_WKDEP */ +#define OMAP54XX_WKUPDEP_UART6_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UART6_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART6_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART6_WKDEP */ +#define OMAP54XX_WKUPDEP_UART6_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_UART6_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART6_SDMA_MASK (1 << 3) + +/* Used by PM_L3INIT_UNIPRO2_WKDEP */ +#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_MASK (1 << 0) + +/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */ +#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_MASK (1 << 1) + +/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */ +#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_MASK (1 << 0) + +/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */ +#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_MASK (1 << 1) + +/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */ +#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_MASK (1 << 0) + +/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */ +#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_MASK (1 << 1) + +/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */ +#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_MASK (1 << 0) + +/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */ +#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_MASK (1 << 0) + +/* Used by PM_ABE_WD_TIMER3_WKDEP */ +#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_MASK (1 << 0) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_WUCLK_CTRL_SHIFT 8 +#define OMAP54XX_WUCLK_CTRL_WIDTH 0x1 +#define OMAP54XX_WUCLK_CTRL_MASK (1 << 8) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_WUCLK_STATUS_SHIFT 9 +#define OMAP54XX_WUCLK_STATUS_WIDTH 0x1 +#define OMAP54XX_WUCLK_STATUS_MASK (1 << 9) + +/* Used by REVISION_PRM */ +#define OMAP54XX_X_MAJOR_SHIFT 8 +#define OMAP54XX_X_MAJOR_WIDTH 0x3 +#define OMAP54XX_X_MAJOR_MASK (0x7 << 8) + +/* Used by REVISION_PRM */ +#define OMAP54XX_Y_MINOR_SHIFT 0 +#define OMAP54XX_Y_MINOR_WIDTH 0x6 +#define OMAP54XX_Y_MINOR_MASK (0x3f << 0) +#endif diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c index 44c0d7216aa..72044073774 100644 --- a/arch/arm/mach-omap2/prm33xx.c +++ b/arch/arm/mach-omap2/prm33xx.c @@ -320,6 +320,12 @@ static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm) return 0; } +static int am33xx_check_vcvp(void) +{ + /* No VC/VP on am33xx devices */ + return 0; +} + struct pwrdm_ops am33xx_pwrdm_operations = { .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst, .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst, @@ -335,4 +341,5 @@ struct pwrdm_ops am33xx_pwrdm_operations = { .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst, .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst, .pwrdm_wait_transition = am33xx_pwrdm_wait_transition, + .pwrdm_has_voltdm = am33xx_check_vcvp, }; diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index 8ee1fbdec56..7db2422faa1 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h @@ -25,6 +25,7 @@ #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H +#include "prm44xx_54xx.h" #include "prcm-common.h" #include "prm.h" @@ -744,36 +745,4 @@ #define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 #define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8) -/* Function prototypes */ -# ifndef __ASSEMBLER__ - -extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx); -extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx); -extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); - -/* OMAP4-specific VP functions */ -u32 omap4_prm_vp_check_txdone(u8 vp_id); -void omap4_prm_vp_clear_txdone(u8 vp_id); - -/* - * OMAP4 access functions for voltage controller (VC) and - * voltage proccessor (VP) in the PRM. - */ -extern u32 omap4_prm_vcvp_read(u8 offset); -extern void omap4_prm_vcvp_write(u32 val, u8 offset); -extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); - -extern void omap44xx_prm_reconfigure_io_chain(void); - -/* PRM interrupt-related functions */ -extern void omap44xx_prm_read_pending_irqs(unsigned long *events); -extern void omap44xx_prm_ocp_barrier(void); -extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask); -extern void omap44xx_prm_restore_irqen(u32 *saved_mask); - -extern int __init omap44xx_prm_init(void); -extern u32 omap44xx_prm_get_reset_sources(void); - -# endif - #endif diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h new file mode 100644 index 00000000000..7cd22abb8f1 --- /dev/null +++ b/arch/arm/mach-omap2/prm44xx_54xx.h @@ -0,0 +1,58 @@ +/* + * OMAP44xx and 54xx PRM common functions + * + * Copyright (C) 2009-2013 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H +#define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H + +/* Function prototypes */ +#ifndef __ASSEMBLER__ + +extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx); +extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx); +extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); + +/* OMAP4/OMAP5-specific VP functions */ +u32 omap4_prm_vp_check_txdone(u8 vp_id); +void omap4_prm_vp_clear_txdone(u8 vp_id); + +/* + * OMAP4/OMAP5 access functions for voltage controller (VC) and + * voltage proccessor (VP) in the PRM. + */ +extern u32 omap4_prm_vcvp_read(u8 offset); +extern void omap4_prm_vcvp_write(u32 val, u8 offset); +extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); + +extern void omap44xx_prm_reconfigure_io_chain(void); + +/* PRM interrupt-related functions */ +extern void omap44xx_prm_read_pending_irqs(unsigned long *events); +extern void omap44xx_prm_ocp_barrier(void); +extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask); +extern void omap44xx_prm_restore_irqen(u32 *saved_mask); + +extern int __init omap44xx_prm_init(void); +extern u32 omap44xx_prm_get_reset_sources(void); + +#endif + +#endif diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h new file mode 100644 index 00000000000..e4411010309 --- /dev/null +++ b/arch/arm/mach-omap2/prm54xx.h @@ -0,0 +1,421 @@ +/* + * OMAP54xx PRM instance offset macros + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_PRM54XX_H +#define __ARCH_ARM_MACH_OMAP2_PRM54XX_H + +#include "prm44xx_54xx.h" +#include "prcm-common.h" +#include "prm.h" + +#define OMAP54XX_PRM_BASE 0x4ae06000 + +#define OMAP54XX_PRM_REGADDR(inst, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE + (inst) + (reg)) + + +/* PRM instances */ +#define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000 +#define OMAP54XX_PRM_CKGEN_INST 0x0100 +#define OMAP54XX_PRM_MPU_INST 0x0300 +#define OMAP54XX_PRM_DSP_INST 0x0400 +#define OMAP54XX_PRM_ABE_INST 0x0500 +#define OMAP54XX_PRM_COREAON_INST 0x0600 +#define OMAP54XX_PRM_CORE_INST 0x0700 +#define OMAP54XX_PRM_IVA_INST 0x1200 +#define OMAP54XX_PRM_CAM_INST 0x1300 +#define OMAP54XX_PRM_DSS_INST 0x1400 +#define OMAP54XX_PRM_GPU_INST 0x1500 +#define OMAP54XX_PRM_L3INIT_INST 0x1600 +#define OMAP54XX_PRM_CUSTEFUSE_INST 0x1700 +#define OMAP54XX_PRM_WKUPAON_INST 0x1800 +#define OMAP54XX_PRM_WKUPAON_CM_INST 0x1900 +#define OMAP54XX_PRM_EMU_INST 0x1a00 +#define OMAP54XX_PRM_EMU_CM_INST 0x1b00 +#define OMAP54XX_PRM_DEVICE_INST 0x1c00 +#define OMAP54XX_PRM_INSTR_INST 0x1f00 + +/* PRM clockdomain register offsets (from instance start) */ +#define OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000 +#define OMAP54XX_PRM_EMU_CM_EMU_CDOFFS 0x0000 + +/* PRM */ + +/* PRM.OCP_SOCKET_PRM register offsets */ +#define OMAP54XX_REVISION_PRM_OFFSET 0x0000 +#define OMAP54XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010 +#define OMAP54XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 +#define OMAP54XX_PRM_IRQENABLE_MPU_OFFSET 0x0018 +#define OMAP54XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c +#define OMAP54XX_PRM_IRQSTATUS_IPU_OFFSET 0x0020 +#define OMAP54XX_PRM_IRQENABLE_IPU_OFFSET 0x0028 +#define OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET 0x0030 +#define OMAP54XX_PRM_IRQENABLE_DSP_OFFSET 0x0038 +#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 +#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_OCP_SOCKET_INST, 0x0040) +#define OMAP54XX_PRM_DEBUG_OUT_OFFSET 0x0084 +#define OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET 0x0090 +#define OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET 0x0094 +#define OMAP54XX_PRM_DEBUG_CORE_RET_TRANS_OFFSET 0x0098 +#define OMAP54XX_PRM_DEBUG_MPU_RET_TRANS_OFFSET 0x009c +#define OMAP54XX_PRM_DEBUG_MM_RET_TRANS_OFFSET 0x00a0 +#define OMAP54XX_PRM_DEBUG_WKUPAON_FD_TRANS_OFFSET 0x00a4 + +/* PRM.CKGEN_PRM register offsets */ +#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET 0x0000 +#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0000) +#define OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008 +#define OMAP54XX_CM_CLKSEL_WKUPAON OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0008) +#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c +#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x000c) +#define OMAP54XX_CM_CLKSEL_SYS_OFFSET 0x0010 +#define OMAP54XX_CM_CLKSEL_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0010) + +/* PRM.MPU_PRM register offsets */ +#define OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_MPU_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 + +/* PRM.DSP_PRM register offsets */ +#define OMAP54XX_PM_DSP_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_DSP_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_DSP_RSTCTRL_OFFSET 0x0010 +#define OMAP54XX_RM_DSP_RSTST_OFFSET 0x0014 +#define OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET 0x0024 + +/* PRM.ABE_PRM register offsets */ +#define OMAP54XX_PM_ABE_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_ABE_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET 0x002c +#define OMAP54XX_PM_ABE_MCPDM_WKDEP_OFFSET 0x0030 +#define OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET 0x0034 +#define OMAP54XX_PM_ABE_DMIC_WKDEP_OFFSET 0x0038 +#define OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c +#define OMAP54XX_PM_ABE_MCASP_WKDEP_OFFSET 0x0040 +#define OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044 +#define OMAP54XX_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048 +#define OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c +#define OMAP54XX_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050 +#define OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054 +#define OMAP54XX_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058 +#define OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c +#define OMAP54XX_PM_ABE_SLIMBUS1_WKDEP_OFFSET 0x0060 +#define OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET 0x0064 +#define OMAP54XX_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068 +#define OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c +#define OMAP54XX_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070 +#define OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074 +#define OMAP54XX_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078 +#define OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c +#define OMAP54XX_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080 +#define OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084 +#define OMAP54XX_PM_ABE_WD_TIMER3_WKDEP_OFFSET 0x0088 +#define OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET 0x008c + +/* PRM.COREAON_PRM register offsets */ +#define OMAP54XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0028 +#define OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x002c +#define OMAP54XX_PM_COREAON_SMARTREFLEX_MM_WKDEP_OFFSET 0x0030 +#define OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET 0x0034 +#define OMAP54XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0038 +#define OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x003c + +/* PRM.CORE_PRM register offsets */ +#define OMAP54XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_CORE_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024 +#define OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET 0x0124 +#define OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET 0x012c +#define OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET 0x0134 +#define OMAP54XX_RM_IPU_RSTCTRL_OFFSET 0x0210 +#define OMAP54XX_RM_IPU_RSTST_OFFSET 0x0214 +#define OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET 0x0224 +#define OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324 +#define OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424 +#define OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c +#define OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434 +#define OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c +#define OMAP54XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444 +#define OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET 0x0524 +#define OMAP54XX_RM_C2C_MODEM_ICR_CONTEXT_OFFSET 0x052c +#define OMAP54XX_RM_C2C_C2C_OCP_FW_CONTEXT_OFFSET 0x0534 +#define OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 +#define OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c +#define OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634 +#define OMAP54XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c +#define OMAP54XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644 +#define OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET 0x0724 +#define OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c +#define OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744 +#define OMAP54XX_RM_MIPIEXT_LLI_CONTEXT_OFFSET 0x0824 +#define OMAP54XX_RM_MIPIEXT_LLI_OCP_FW_CONTEXT_OFFSET 0x082c +#define OMAP54XX_RM_MIPIEXT_MPHY_CONTEXT_OFFSET 0x0834 +#define OMAP54XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0928 +#define OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x092c +#define OMAP54XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0930 +#define OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0934 +#define OMAP54XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0938 +#define OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x093c +#define OMAP54XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0940 +#define OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0944 +#define OMAP54XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0948 +#define OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x094c +#define OMAP54XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0950 +#define OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0954 +#define OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x095c +#define OMAP54XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0960 +#define OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0964 +#define OMAP54XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0968 +#define OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x096c +#define OMAP54XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0970 +#define OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0974 +#define OMAP54XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0978 +#define OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x097c +#define OMAP54XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0980 +#define OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0984 +#define OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x098c +#define OMAP54XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x09a0 +#define OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x09a4 +#define OMAP54XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x09a8 +#define OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x09ac +#define OMAP54XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x09b0 +#define OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x09b4 +#define OMAP54XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x09b8 +#define OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x09bc +#define OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x09c0 +#define OMAP54XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x09f0 +#define OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x09f4 +#define OMAP54XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x09f8 +#define OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x09fc +#define OMAP54XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0a00 +#define OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0a04 +#define OMAP54XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0a08 +#define OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x0a0c +#define OMAP54XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0a10 +#define OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0a14 +#define OMAP54XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0a18 +#define OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x0a1c +#define OMAP54XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0a20 +#define OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0a24 +#define OMAP54XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0a28 +#define OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x0a2c +#define OMAP54XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0a40 +#define OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0a44 +#define OMAP54XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0a48 +#define OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x0a4c +#define OMAP54XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0a50 +#define OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0a54 +#define OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x0a58 +#define OMAP54XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0a5c +#define OMAP54XX_PM_L4PER_MMC5_WKDEP_OFFSET 0x0a60 +#define OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET 0x0a64 +#define OMAP54XX_PM_L4PER_I2C5_WKDEP_OFFSET 0x0a68 +#define OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET 0x0a6c +#define OMAP54XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0a70 +#define OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0a74 +#define OMAP54XX_PM_L4PER_UART6_WKDEP_OFFSET 0x0a78 +#define OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET 0x0a7c +#define OMAP54XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x0aa4 +#define OMAP54XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x0aac +#define OMAP54XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x0ab4 +#define OMAP54XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x0abc +#define OMAP54XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x0ac4 +#define OMAP54XX_RM_L4SEC_SHA2MD5_CONTEXT_OFFSET 0x0acc +#define OMAP54XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x0adc + +/* PRM.IVA_PRM register offsets */ +#define OMAP54XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_IVA_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_IVA_RSTCTRL_OFFSET 0x0010 +#define OMAP54XX_RM_IVA_RSTST_OFFSET 0x0014 +#define OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024 +#define OMAP54XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c + +/* PRM.CAM_PRM register offsets */ +#define OMAP54XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_CAM_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET 0x0024 +#define OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c +#define OMAP54XX_RM_CAM_CAL_CONTEXT_OFFSET 0x0034 + +/* PRM.DSS_PRM register offsets */ +#define OMAP54XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_DSS_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020 +#define OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 +#define OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034 + +/* PRM.GPU_PRM register offsets */ +#define OMAP54XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_GPU_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024 + +/* PRM.L3INIT_PRM register offsets */ +#define OMAP54XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_L3INIT_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 +#define OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c +#define OMAP54XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 +#define OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 +#define OMAP54XX_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038 +#define OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c +#define OMAP54XX_PM_L3INIT_UNIPRO2_WKDEP_OFFSET 0x0040 +#define OMAP54XX_RM_L3INIT_UNIPRO2_CONTEXT_OFFSET 0x0044 +#define OMAP54XX_PM_L3INIT_USB_HOST_HS_WKDEP_OFFSET 0x0058 +#define OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET 0x005c +#define OMAP54XX_PM_L3INIT_USB_TLL_HS_WKDEP_OFFSET 0x0068 +#define OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET 0x006c +#define OMAP54XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c +#define OMAP54XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 +#define OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c +#define OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4 +#define OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec +#define OMAP54XX_PM_L3INIT_USB_OTG_SS_WKDEP_OFFSET 0x00f0 +#define OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET 0x00f4 + +/* PRM.CUSTEFUSE_PRM register offsets */ +#define OMAP54XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024 + +/* PRM.WKUPAON_PRM register offsets */ +#define OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0024 +#define OMAP54XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x002c +#define OMAP54XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x0030 +#define OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0034 +#define OMAP54XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0038 +#define OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x003c +#define OMAP54XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x0040 +#define OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0044 +#define OMAP54XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0048 +#define OMAP54XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x004c +#define OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0054 +#define OMAP54XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0064 +#define OMAP54XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0078 +#define OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x007c + +/* PRM.WKUPAON_CM register offsets */ +#define OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0020) +#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028 +#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0028) +#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030 +#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0030) +#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038 +#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0038) +#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040 +#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0040) +#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048 +#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0048) +#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050 +#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0050) +#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060 +#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0060) +#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078 +#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0078) +#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090 +#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0090) +#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098 +#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0098) + +/* PRM.EMU_PRM register offsets */ +#define OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_EMU_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 + +/* PRM.EMU_CM register offsets */ +#define OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008 +#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0020) +#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x0028 +#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0028) + +/* PRM.DEVICE_PRM register offsets */ +#define OMAP54XX_PRM_RSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PRM_RSTST_OFFSET 0x0004 +#define OMAP54XX_PRM_RSTTIME_OFFSET 0x0008 +#define OMAP54XX_PRM_CLKREQCTRL_OFFSET 0x000c +#define OMAP54XX_PRM_VOLTCTRL_OFFSET 0x0010 +#define OMAP54XX_PRM_PWRREQCTRL_OFFSET 0x0014 +#define OMAP54XX_PRM_PSCON_COUNT_OFFSET 0x0018 +#define OMAP54XX_PRM_IO_COUNT_OFFSET 0x001c +#define OMAP54XX_PRM_IO_PMCTRL_OFFSET 0x0020 +#define OMAP54XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 +#define OMAP54XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 +#define OMAP54XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c +#define OMAP54XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030 +#define OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 +#define OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 +#define OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c +#define OMAP54XX_PRM_VP_CORE_CONFIG_OFFSET 0x0040 +#define OMAP54XX_PRM_VP_CORE_STATUS_OFFSET 0x0044 +#define OMAP54XX_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048 +#define OMAP54XX_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c +#define OMAP54XX_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050 +#define OMAP54XX_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054 +#define OMAP54XX_PRM_VP_MPU_CONFIG_OFFSET 0x0058 +#define OMAP54XX_PRM_VP_MPU_STATUS_OFFSET 0x005c +#define OMAP54XX_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060 +#define OMAP54XX_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064 +#define OMAP54XX_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068 +#define OMAP54XX_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c +#define OMAP54XX_PRM_VP_MM_CONFIG_OFFSET 0x0070 +#define OMAP54XX_PRM_VP_MM_STATUS_OFFSET 0x0074 +#define OMAP54XX_PRM_VP_MM_VLIMITTO_OFFSET 0x0078 +#define OMAP54XX_PRM_VP_MM_VOLTAGE_OFFSET 0x007c +#define OMAP54XX_PRM_VP_MM_VSTEPMAX_OFFSET 0x0080 +#define OMAP54XX_PRM_VP_MM_VSTEPMIN_OFFSET 0x0084 +#define OMAP54XX_PRM_VC_SMPS_CORE_CONFIG_OFFSET 0x0088 +#define OMAP54XX_PRM_VC_SMPS_MM_CONFIG_OFFSET 0x008c +#define OMAP54XX_PRM_VC_SMPS_MPU_CONFIG_OFFSET 0x0090 +#define OMAP54XX_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094 +#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MM_L_OFFSET 0x0098 +#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x009c +#define OMAP54XX_PRM_VC_VAL_BYPASS_OFFSET 0x00a0 +#define OMAP54XX_PRM_VC_CORE_ERRST_OFFSET 0x00a4 +#define OMAP54XX_PRM_VC_MM_ERRST_OFFSET 0x00a8 +#define OMAP54XX_PRM_VC_MPU_ERRST_OFFSET 0x00ac +#define OMAP54XX_PRM_VC_BYPASS_ERRST_OFFSET 0x00b0 +#define OMAP54XX_PRM_VC_CFG_I2C_MODE_OFFSET 0x00b4 +#define OMAP54XX_PRM_VC_CFG_I2C_CLK_OFFSET 0x00b8 +#define OMAP54XX_PRM_SRAM_COUNT_OFFSET 0x00bc +#define OMAP54XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0 +#define OMAP54XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4 +#define OMAP54XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8 +#define OMAP54XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc +#define OMAP54XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0 +#define OMAP54XX_PRM_SLDO_MM_SETUP_OFFSET 0x00d4 +#define OMAP54XX_PRM_SLDO_MM_CTRL_OFFSET 0x00d8 +#define OMAP54XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc +#define OMAP54XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0 +#define OMAP54XX_PRM_ABBLDO_MM_SETUP_OFFSET 0x00e4 +#define OMAP54XX_PRM_ABBLDO_MM_CTRL_OFFSET 0x00e8 +#define OMAP54XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec +#define OMAP54XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0 +#define OMAP54XX_PRM_PHASE1_CNDP_OFFSET 0x00f4 +#define OMAP54XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8 +#define OMAP54XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc +#define OMAP54XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100 +#define OMAP54XX_PRM_VOLTST_MPU_OFFSET 0x0110 +#define OMAP54XX_PRM_VOLTST_MM_OFFSET 0x0114 + +#endif diff --git a/arch/arm/mach-omap2/scrm54xx.h b/arch/arm/mach-omap2/scrm54xx.h new file mode 100644 index 00000000000..57e86c8f823 --- /dev/null +++ b/arch/arm/mach-omap2/scrm54xx.h @@ -0,0 +1,231 @@ +/* + * OMAP54XX SCRM registers and bitfields + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H +#define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H + +#define OMAP5_SCRM_BASE 0x4ae0a000 + +#define OMAP54XX_SCRM_REGADDR(reg) \ + OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg)) + +/* SCRM */ + +/* SCRM.SCRM register offsets */ +#define OMAP5_SCRM_REVISION_SCRM_OFFSET 0x0000 +#define OMAP5_SCRM_REVISION_SCRM OMAP54XX_SCRM_REGADDR(0x0000) +#define OMAP5_SCRM_CLKSETUPTIME_OFFSET 0x0100 +#define OMAP5_SCRM_CLKSETUPTIME OMAP54XX_SCRM_REGADDR(0x0100) +#define OMAP5_SCRM_PMICSETUPTIME_OFFSET 0x0104 +#define OMAP5_SCRM_PMICSETUPTIME OMAP54XX_SCRM_REGADDR(0x0104) +#define OMAP5_SCRM_ALTCLKSRC_OFFSET 0x0110 +#define OMAP5_SCRM_ALTCLKSRC OMAP54XX_SCRM_REGADDR(0x0110) +#define OMAP5_SCRM_MODEMCLKM_OFFSET 0x0118 +#define OMAP5_SCRM_MODEMCLKM OMAP54XX_SCRM_REGADDR(0x0118) +#define OMAP5_SCRM_D2DCLKM_OFFSET 0x011c +#define OMAP5_SCRM_D2DCLKM OMAP54XX_SCRM_REGADDR(0x011c) +#define OMAP5_SCRM_EXTCLKREQ_OFFSET 0x0200 +#define OMAP5_SCRM_EXTCLKREQ OMAP54XX_SCRM_REGADDR(0x0200) +#define OMAP5_SCRM_ACCCLKREQ_OFFSET 0x0204 +#define OMAP5_SCRM_ACCCLKREQ OMAP54XX_SCRM_REGADDR(0x0204) +#define OMAP5_SCRM_PWRREQ_OFFSET 0x0208 +#define OMAP5_SCRM_PWRREQ OMAP54XX_SCRM_REGADDR(0x0208) +#define OMAP5_SCRM_AUXCLKREQ0_OFFSET 0x0210 +#define OMAP5_SCRM_AUXCLKREQ0 OMAP54XX_SCRM_REGADDR(0x0210) +#define OMAP5_SCRM_AUXCLKREQ1_OFFSET 0x0214 +#define OMAP5_SCRM_AUXCLKREQ1 OMAP54XX_SCRM_REGADDR(0x0214) +#define OMAP5_SCRM_AUXCLKREQ2_OFFSET 0x0218 +#define OMAP5_SCRM_AUXCLKREQ2 OMAP54XX_SCRM_REGADDR(0x0218) +#define OMAP5_SCRM_AUXCLKREQ3_OFFSET 0x021c +#define OMAP5_SCRM_AUXCLKREQ3 OMAP54XX_SCRM_REGADDR(0x021c) +#define OMAP5_SCRM_AUXCLKREQ4_OFFSET 0x0220 +#define OMAP5_SCRM_AUXCLKREQ4 OMAP54XX_SCRM_REGADDR(0x0220) +#define OMAP5_SCRM_AUXCLKREQ5_OFFSET 0x0224 +#define OMAP5_SCRM_AUXCLKREQ5 OMAP54XX_SCRM_REGADDR(0x0224) +#define OMAP5_SCRM_D2DCLKREQ_OFFSET 0x0234 +#define OMAP5_SCRM_D2DCLKREQ OMAP54XX_SCRM_REGADDR(0x0234) +#define OMAP5_SCRM_AUXCLK0_OFFSET 0x0310 +#define OMAP5_SCRM_AUXCLK0 OMAP54XX_SCRM_REGADDR(0x0310) +#define OMAP5_SCRM_AUXCLK1_OFFSET 0x0314 +#define OMAP5_SCRM_AUXCLK1 OMAP54XX_SCRM_REGADDR(0x0314) +#define OMAP5_SCRM_AUXCLK2_OFFSET 0x0318 +#define OMAP5_SCRM_AUXCLK2 OMAP54XX_SCRM_REGADDR(0x0318) +#define OMAP5_SCRM_AUXCLK3_OFFSET 0x031c +#define OMAP5_SCRM_AUXCLK3 OMAP54XX_SCRM_REGADDR(0x031c) +#define OMAP5_SCRM_AUXCLK4_OFFSET 0x0320 +#define OMAP5_SCRM_AUXCLK4 OMAP54XX_SCRM_REGADDR(0x0320) +#define OMAP5_SCRM_AUXCLK5_OFFSET 0x0324 +#define OMAP5_SCRM_AUXCLK5 OMAP54XX_SCRM_REGADDR(0x0324) +#define OMAP5_SCRM_RSTTIME_OFFSET 0x0400 +#define OMAP5_SCRM_RSTTIME OMAP54XX_SCRM_REGADDR(0x0400) +#define OMAP5_SCRM_MODEMRSTCTRL_OFFSET 0x0418 +#define OMAP5_SCRM_MODEMRSTCTRL OMAP54XX_SCRM_REGADDR(0x0418) +#define OMAP5_SCRM_D2DRSTCTRL_OFFSET 0x041c +#define OMAP5_SCRM_D2DRSTCTRL OMAP54XX_SCRM_REGADDR(0x041c) +#define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420 +#define OMAP5_SCRM_EXTPWRONRSTCTRL OMAP54XX_SCRM_REGADDR(0x0420) +#define OMAP5_SCRM_EXTWARMRSTST_OFFSET 0x0510 +#define OMAP5_SCRM_EXTWARMRSTST OMAP54XX_SCRM_REGADDR(0x0510) +#define OMAP5_SCRM_APEWARMRSTST_OFFSET 0x0514 +#define OMAP5_SCRM_APEWARMRSTST OMAP54XX_SCRM_REGADDR(0x0514) +#define OMAP5_SCRM_MODEMWARMRSTST_OFFSET 0x0518 +#define OMAP5_SCRM_MODEMWARMRSTST OMAP54XX_SCRM_REGADDR(0x0518) +#define OMAP5_SCRM_D2DWARMRSTST_OFFSET 0x051c +#define OMAP5_SCRM_D2DWARMRSTST OMAP54XX_SCRM_REGADDR(0x051c) + +/* + * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, + * AUXCLKREQ5, D2DCLKREQ + */ +#define OMAP5_ACCURACY_SHIFT 1 +#define OMAP5_ACCURACY_WIDTH 0x1 +#define OMAP5_ACCURACY_MASK (1 << 1) + +/* Used by APEWARMRSTST */ +#define OMAP5_APEWARMRSTST_SHIFT 1 +#define OMAP5_APEWARMRSTST_WIDTH 0x1 +#define OMAP5_APEWARMRSTST_MASK (1 << 1) + +/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ +#define OMAP5_CLKDIV_SHIFT 16 +#define OMAP5_CLKDIV_WIDTH 0x4 +#define OMAP5_CLKDIV_MASK (0xf << 16) + +/* Used by D2DCLKM, MODEMCLKM */ +#define OMAP5_CLK_32KHZ_SHIFT 0 +#define OMAP5_CLK_32KHZ_WIDTH 0x1 +#define OMAP5_CLK_32KHZ_MASK (1 << 0) + +/* Used by D2DRSTCTRL, MODEMRSTCTRL */ +#define OMAP5_COLDRST_SHIFT 0 +#define OMAP5_COLDRST_WIDTH 0x1 +#define OMAP5_COLDRST_MASK (1 << 0) + +/* Used by D2DWARMRSTST */ +#define OMAP5_D2DWARMRSTST_SHIFT 3 +#define OMAP5_D2DWARMRSTST_WIDTH 0x1 +#define OMAP5_D2DWARMRSTST_MASK (1 << 3) + +/* Used by AUXCLK0 */ +#define OMAP5_DISABLECLK_SHIFT 9 +#define OMAP5_DISABLECLK_WIDTH 0x1 +#define OMAP5_DISABLECLK_MASK (1 << 9) + +/* Used by CLKSETUPTIME */ +#define OMAP5_DOWNTIME_SHIFT 16 +#define OMAP5_DOWNTIME_WIDTH 0x6 +#define OMAP5_DOWNTIME_MASK (0x3f << 16) + +/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ +#define OMAP5_ENABLE_SHIFT 8 +#define OMAP5_ENABLE_WIDTH 0x1 +#define OMAP5_ENABLE_MASK (1 << 8) + +/* Renamed from ENABLE Used by EXTPWRONRSTCTRL */ +#define OMAP5_ENABLE_0_0_SHIFT 0 +#define OMAP5_ENABLE_0_0_WIDTH 0x1 +#define OMAP5_ENABLE_0_0_MASK (1 << 0) + +/* Used by ALTCLKSRC */ +#define OMAP5_ENABLE_EXT_SHIFT 3 +#define OMAP5_ENABLE_EXT_WIDTH 0x1 +#define OMAP5_ENABLE_EXT_MASK (1 << 3) + +/* Used by ALTCLKSRC */ +#define OMAP5_ENABLE_INT_SHIFT 2 +#define OMAP5_ENABLE_INT_WIDTH 0x1 +#define OMAP5_ENABLE_INT_MASK (1 << 2) + +/* Used by EXTWARMRSTST */ +#define OMAP5_EXTWARMRSTST_SHIFT 0 +#define OMAP5_EXTWARMRSTST_WIDTH 0x1 +#define OMAP5_EXTWARMRSTST_MASK (1 << 0) + +/* + * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, + * AUXCLKREQ5 + */ +#define OMAP5_MAPPING_SHIFT 2 +#define OMAP5_MAPPING_WIDTH 0x3 +#define OMAP5_MAPPING_MASK (0x7 << 2) + +/* Used by ALTCLKSRC */ +#define OMAP5_MODE_SHIFT 0 +#define OMAP5_MODE_WIDTH 0x2 +#define OMAP5_MODE_MASK (0x3 << 0) + +/* Used by MODEMWARMRSTST */ +#define OMAP5_MODEMWARMRSTST_SHIFT 2 +#define OMAP5_MODEMWARMRSTST_WIDTH 0x1 +#define OMAP5_MODEMWARMRSTST_MASK (1 << 2) + +/* + * Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5, + * AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5, + * D2DCLKREQ, EXTCLKREQ, PWRREQ + */ +#define OMAP5_POLARITY_SHIFT 0 +#define OMAP5_POLARITY_WIDTH 0x1 +#define OMAP5_POLARITY_MASK (1 << 0) + +/* Used by EXTPWRONRSTCTRL */ +#define OMAP5_PWRONRST_SHIFT 1 +#define OMAP5_PWRONRST_WIDTH 0x1 +#define OMAP5_PWRONRST_MASK (1 << 1) + +/* Used by REVISION_SCRM */ +#define OMAP5_REV_SHIFT 0 +#define OMAP5_REV_WIDTH 0x8 +#define OMAP5_REV_MASK (0xff << 0) + +/* Used by RSTTIME */ +#define OMAP5_RSTTIME_SHIFT 0 +#define OMAP5_RSTTIME_WIDTH 0x4 +#define OMAP5_RSTTIME_MASK (0xf << 0) + +/* Used by CLKSETUPTIME */ +#define OMAP5_SETUPTIME_SHIFT 0 +#define OMAP5_SETUPTIME_WIDTH 0xc +#define OMAP5_SETUPTIME_MASK (0xfff << 0) + +/* Used by PMICSETUPTIME */ +#define OMAP5_SLEEPTIME_SHIFT 0 +#define OMAP5_SLEEPTIME_WIDTH 0x6 +#define OMAP5_SLEEPTIME_MASK (0x3f << 0) + +/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ +#define OMAP5_SRCSELECT_SHIFT 1 +#define OMAP5_SRCSELECT_WIDTH 0x2 +#define OMAP5_SRCSELECT_MASK (0x3 << 1) + +/* Used by D2DCLKM */ +#define OMAP5_SYSCLK_SHIFT 1 +#define OMAP5_SYSCLK_WIDTH 0x1 +#define OMAP5_SYSCLK_MASK (1 << 1) + +/* Used by PMICSETUPTIME */ +#define OMAP5_WAKEUPTIME_SHIFT 16 +#define OMAP5_WAKEUPTIME_WIDTH 0x6 +#define OMAP5_WAKEUPTIME_MASK (0x3f << 16) + +/* Used by D2DRSTCTRL, MODEMRSTCTRL */ +#define OMAP5_WARMRST_SHIFT 1 +#define OMAP5_WARMRST_WIDTH 0x1 +#define OMAP5_WARMRST_MASK (1 << 1) + +#endif diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 8396b5b7e91..f6601563aa6 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -95,38 +95,9 @@ static void omap_uart_enable_wakeup(struct device *dev, bool enable) omap_hwmod_disable_wakeup(od->hwmods[0]); } -/* - * Errata i291: [UART]:Cannot Acknowledge Idle Requests - * in Smartidle Mode When Configured for DMA Operations. - * WA: configure uart in force idle mode. - */ -static void omap_uart_set_noidle(struct device *dev) -{ - struct platform_device *pdev = to_platform_device(dev); - struct omap_device *od = to_omap_device(pdev); - - omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO); -} - -static void omap_uart_set_smartidle(struct device *dev) -{ - struct platform_device *pdev = to_platform_device(dev); - struct omap_device *od = to_omap_device(pdev); - u8 idlemode; - - if (od->hwmods[0]->class->sysc->idlemodes & SIDLE_SMART_WKUP) - idlemode = HWMOD_IDLEMODE_SMART_WKUP; - else - idlemode = HWMOD_IDLEMODE_SMART; - - omap_hwmod_set_slave_idlemode(od->hwmods[0], idlemode); -} - #else static void omap_uart_enable_wakeup(struct device *dev, bool enable) {} -static void omap_uart_set_noidle(struct device *dev) {} -static void omap_uart_set_smartidle(struct device *dev) {} #endif /* CONFIG_PM */ #ifdef CONFIG_OMAP_MUX @@ -299,8 +270,6 @@ void __init omap_serial_init_port(struct omap_board_data *bdata, omap_up.uartclk = OMAP24XX_BASE_BAUD * 16; omap_up.flags = UPF_BOOT_AUTOCONF; omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count; - omap_up.set_forceidle = omap_uart_set_smartidle; - omap_up.set_noidle = omap_uart_set_noidle; omap_up.enable_wakeup = omap_uart_enable_wakeup; omap_up.dma_rx_buf_size = info->dma_rx_buf_size; omap_up.dma_rx_timeout = info->dma_rx_timeout; diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index 197cc16870d..8c616e436bc 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h @@ -96,6 +96,15 @@ # endif #endif +#ifdef CONFIG_SOC_AM43XX +# ifdef OMAP_NAME +# undef MULTI_OMAP2 +# define MULTI_OMAP2 +# else +# define OMAP_NAME am43xx +# endif +#endif + /* * Omap device type i.e. EMU/HS/TST/GP/BAD */ @@ -187,6 +196,7 @@ IS_OMAP_CLASS(44xx, 0x44) IS_AM_CLASS(35xx, 0x35) IS_OMAP_CLASS(54xx, 0x54) IS_AM_CLASS(33xx, 0x33) +IS_AM_CLASS(43xx, 0x43) IS_TI_CLASS(81xx, 0x81) @@ -202,6 +212,7 @@ IS_OMAP_SUBCLASS(543x, 0x543) IS_TI_SUBCLASS(816x, 0x816) IS_TI_SUBCLASS(814x, 0x814) IS_AM_SUBCLASS(335x, 0x335) +IS_AM_SUBCLASS(437x, 0x437) #define cpu_is_omap24xx() 0 #define cpu_is_omap242x() 0 @@ -214,6 +225,8 @@ IS_AM_SUBCLASS(335x, 0x335) #define soc_is_am35xx() 0 #define soc_is_am33xx() 0 #define soc_is_am335x() 0 +#define soc_is_am43xx() 0 +#define soc_is_am437x() 0 #define cpu_is_omap44xx() 0 #define cpu_is_omap443x() 0 #define cpu_is_omap446x() 0 @@ -341,6 +354,13 @@ IS_OMAP_TYPE(3430, 0x3430) # define soc_is_am335x() is_am335x() #endif +#ifdef CONFIG_SOC_AM43XX +# undef soc_is_am43xx +# undef soc_is_am437x +# define soc_is_am43xx() is_am43xx() +# define soc_is_am437x() is_am437x() +#endif + # if defined(CONFIG_ARCH_OMAP4) # undef cpu_is_omap44xx # undef cpu_is_omap443x @@ -383,6 +403,8 @@ IS_OMAP_TYPE(3430, 0x3430) #define TI816X_CLASS 0x81600034 #define TI8168_REV_ES1_0 TI816X_CLASS #define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8)) +#define TI8168_REV_ES2_0 (TI816X_CLASS | (0x2 << 8)) +#define TI8168_REV_ES2_1 (TI816X_CLASS | (0x3 << 8)) #define TI814X_CLASS 0x81400034 #define TI8148_REV_ES1_0 TI814X_CLASS @@ -398,6 +420,9 @@ IS_OMAP_TYPE(3430, 0x3430) #define AM335X_REV_ES2_0 (AM335X_CLASS | (0x1 << 8)) #define AM335X_REV_ES2_1 (AM335X_CLASS | (0x2 << 8)) +#define AM437X_CLASS 0x43700000 +#define AM437X_REV_ES1_0 AM437X_CLASS + #define OMAP443X_CLASS 0x44300044 #define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8)) #define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8)) @@ -424,6 +449,7 @@ void omap4xxx_check_revision(void); void omap5xxx_check_revision(void); void omap3xxx_check_features(void); void ti81xx_check_features(void); +void am33xx_check_features(void); void omap4xxx_check_features(void); /* diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c index 0ff0f068bea..4bd09683623 100644 --- a/arch/arm/mach-omap2/sram.c +++ b/arch/arm/mach-omap2/sram.c @@ -119,6 +119,9 @@ static void __init omap_detect_sram(void) if (soc_is_am33xx()) { omap_sram_start = AM33XX_SRAM_PA; omap_sram_size = 0x10000; /* 64K */ + } else if (soc_is_am43xx()) { + omap_sram_start = AM33XX_SRAM_PA; + omap_sram_size = SZ_256K; } else if (cpu_is_omap34xx()) { omap_sram_start = OMAP3_SRAM_PA; omap_sram_size = 0x10000; /* 64K */ diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index f8b23b8040d..3bdb0fb0202 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -582,7 +582,7 @@ OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon", 2, "timer_sys_ck", NULL); #endif /* CONFIG_ARCH_OMAP2 */ -#ifdef CONFIG_ARCH_OMAP3 +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX) OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon", 2, "timer_sys_ck", NULL); OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure", diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h index a0ce4f10ff1..f7f2879b31b 100644 --- a/arch/arm/mach-omap2/voltage.h +++ b/arch/arm/mach-omap2/voltage.h @@ -169,8 +169,8 @@ int omap_voltage_late_init(void); extern void omap2xxx_voltagedomains_init(void); extern void omap3xxx_voltagedomains_init(void); -extern void am33xx_voltagedomains_init(void); extern void omap44xx_voltagedomains_init(void); +extern void omap54xx_voltagedomains_init(void); struct voltagedomain *voltdm_lookup(const char *name); void voltdm_init(struct voltagedomain **voltdm_list); diff --git a/arch/arm/mach-omap2/voltagedomains33xx_data.c b/arch/arm/mach-omap2/voltagedomains33xx_data.c deleted file mode 100644 index 965458dc0cb..00000000000 --- a/arch/arm/mach-omap2/voltagedomains33xx_data.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * AM33XX voltage domain data - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include "voltage.h" - -static struct voltagedomain am33xx_voltdm_mpu = { - .name = "mpu", -}; - -static struct voltagedomain am33xx_voltdm_core = { - .name = "core", -}; - -static struct voltagedomain am33xx_voltdm_rtc = { - .name = "rtc", -}; - -static struct voltagedomain *voltagedomains_am33xx[] __initdata = { - &am33xx_voltdm_mpu, - &am33xx_voltdm_core, - &am33xx_voltdm_rtc, - NULL, -}; - -void __init am33xx_voltagedomains_init(void) -{ - voltdm_init(voltagedomains_am33xx); -} diff --git a/arch/arm/mach-omap2/voltagedomains54xx_data.c b/arch/arm/mach-omap2/voltagedomains54xx_data.c new file mode 100644 index 00000000000..72b8971b54c --- /dev/null +++ b/arch/arm/mach-omap2/voltagedomains54xx_data.c @@ -0,0 +1,102 @@ +/* + * OMAP5 Voltage Management Routines + * + * Based on voltagedomains44xx_data.c + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/err.h> +#include <linux/init.h> + +#include "common.h" + +#include "prm54xx.h" +#include "voltage.h" +#include "omap_opp_data.h" +#include "vc.h" +#include "vp.h" + +static const struct omap_vfsm_instance omap5_vdd_mpu_vfsm = { + .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET, +}; + +static const struct omap_vfsm_instance omap5_vdd_mm_vfsm = { + .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET, +}; + +static const struct omap_vfsm_instance omap5_vdd_core_vfsm = { + .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET, +}; + +static struct voltagedomain omap5_voltdm_mpu = { + .name = "mpu", + .scalable = true, + .read = omap4_prm_vcvp_read, + .write = omap4_prm_vcvp_write, + .rmw = omap4_prm_vcvp_rmw, + .vc = &omap4_vc_mpu, + .vfsm = &omap5_vdd_mpu_vfsm, + .vp = &omap4_vp_mpu, +}; + +static struct voltagedomain omap5_voltdm_mm = { + .name = "mm", + .scalable = true, + .read = omap4_prm_vcvp_read, + .write = omap4_prm_vcvp_write, + .rmw = omap4_prm_vcvp_rmw, + .vc = &omap4_vc_iva, + .vfsm = &omap5_vdd_mm_vfsm, + .vp = &omap4_vp_iva, +}; + +static struct voltagedomain omap5_voltdm_core = { + .name = "core", + .scalable = true, + .read = omap4_prm_vcvp_read, + .write = omap4_prm_vcvp_write, + .rmw = omap4_prm_vcvp_rmw, + .vc = &omap4_vc_core, + .vfsm = &omap5_vdd_core_vfsm, + .vp = &omap4_vp_core, +}; + +static struct voltagedomain omap5_voltdm_wkup = { + .name = "wkup", +}; + +static struct voltagedomain *voltagedomains_omap5[] __initdata = { + &omap5_voltdm_mpu, + &omap5_voltdm_mm, + &omap5_voltdm_core, + &omap5_voltdm_wkup, + NULL, +}; + +static const char *sys_clk_name __initdata = "sys_clkin"; + +void __init omap54xx_voltagedomains_init(void) +{ + struct voltagedomain *voltdm; + int i; + + /* + * XXX Will depend on the process, validation, and binning + * for the currently-running IC. Use OMAP4 data for time being. + */ +#ifdef CONFIG_PM_OPP + omap5_voltdm_mpu.volt_data = omap446x_vdd_mpu_volt_data; + omap5_voltdm_mm.volt_data = omap446x_vdd_iva_volt_data; + omap5_voltdm_core.volt_data = omap446x_vdd_core_volt_data; +#endif + + for (i = 0; voltdm = voltagedomains_omap5[i], voltdm; i++) + voltdm->sys_clk.name = sys_clk_name; + + voltdm_init(voltagedomains_omap5); +}; diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index b97fd672e89..f8a6db9239b 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -199,13 +199,6 @@ void __init orion5x_init_early(void) orion_time_set_base(TIMER_VIRT_BASE); - /* - * Some Orion5x devices allocate their coherent buffers from atomic - * context. Increase size of atomic coherent pool to make sure such - * the allocations won't fail. - */ - init_dma_coherent_pool_size(SZ_1M); - /* Initialize the MBUS driver */ orion5x_pcie_id(&dev, &rev); if (dev == MV88F5281_DEV_ID) diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig index 13bae78b215..b1022f4315f 100644 --- a/arch/arm/mach-picoxcell/Kconfig +++ b/arch/arm/mach-picoxcell/Kconfig @@ -4,7 +4,6 @@ config ARCH_PICOXCELL select ARM_PATCH_PHYS_VIRT select ARM_VIC select CPU_V6K - select DW_APB_TIMER select DW_APB_TIMER_OF select GENERIC_CLOCKEVENTS select HAVE_TCM diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c index 70b441ad1d1..7cde0424d33 100644 --- a/arch/arm/mach-picoxcell/common.c +++ b/arch/arm/mach-picoxcell/common.c @@ -15,7 +15,6 @@ #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/of_platform.h> -#include <linux/dw_apb_timer.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -88,7 +87,6 @@ DT_MACHINE_START(PICOXCELL, "Picochip picoXcell") .map_io = picoxcell_map_io, .nr_irqs = NR_IRQS_LEGACY, .init_irq = irqchip_init, - .init_time = dw_apb_timer_init, .init_machine = picoxcell_init_machine, .dt_compat = picoxcell_dt_match, .restart = picoxcell_wdt_restart, diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c index 9936c180bf0..8f595c0cc8d 100644 --- a/arch/arm/mach-prima2/pm.c +++ b/arch/arm/mach-prima2/pm.c @@ -101,8 +101,10 @@ static int __init sirfsoc_of_pwrc_init(void) struct device_node *np; np = of_find_matching_node(NULL, pwrc_ids); - if (!np) - panic("unable to find compatible pwrc node in dtb\n"); + if (!np) { + pr_err("unable to find compatible sirf pwrc node in dtb\n"); + return -ENOENT; + } /* * pwrc behind rtciobrg is not located in memory space diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c index 435019ca0a4..d5e0cbc934c 100644 --- a/arch/arm/mach-prima2/rstc.c +++ b/arch/arm/mach-prima2/rstc.c @@ -28,8 +28,10 @@ static int __init sirfsoc_of_rstc_init(void) struct device_node *np; np = of_find_matching_node(NULL, rstc_ids); - if (!np) - panic("unable to find compatible rstc node in dtb\n"); + if (!np) { + pr_err("unable to find compatible sirf rstc node in dtb\n"); + return -ENOENT; + } sirfsoc_rstc_base = of_iomap(np, 0); if (!sirfsoc_rstc_base) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig new file mode 100644 index 00000000000..25ee12b21f0 --- /dev/null +++ b/arch/arm/mach-rockchip/Kconfig @@ -0,0 +1,16 @@ +config ARCH_ROCKCHIP + bool "Rockchip RK2928 and RK3xxx SOCs" if ARCH_MULTI_V7 + select PINCTRL + select PINCTRL_ROCKCHIP + select ARCH_REQUIRE_GPIOLIB + select ARM_GIC + select CACHE_L2X0 + select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_SMP + select LOCAL_TIMERS if SMP + select COMMON_CLK + select GENERIC_CLOCKEVENTS + select DW_APB_TIMER_OF + help + Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs + containing the RK2928, RK30xx and RK31xx series. diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile new file mode 100644 index 00000000000..1547d4fc920 --- /dev/null +++ b/arch/arm/mach-rockchip/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c new file mode 100644 index 00000000000..724d2d81f97 --- /dev/null +++ b/arch/arm/mach-rockchip/rockchip.c @@ -0,0 +1,52 @@ +/* + * Device Tree support for Rockchip SoCs + * + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/of_platform.h> +#include <linux/irqchip.h> +#include <linux/dw_apb_timer.h> +#include <linux/clk-provider.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/hardware/cache-l2x0.h> + +static void __init rockchip_timer_init(void) +{ + of_clk_init(NULL); + clocksource_of_init(); +} + +static void __init rockchip_dt_init(void) +{ + l2x0_of_init(0, ~0UL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char * const rockchip_board_dt_compat[] = { + "rockchip,rk2928", + "rockchip,rk3066a", + "rockchip,rk3066b", + "rockchip,rk3188", + NULL, +}; + +DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)") + .init_machine = rockchip_dt_init, + .init_time = rockchip_timer_init, + .dt_compat = rockchip_board_dt_compat, +MACHINE_END diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c index ab1700ec8e6..b7e09467152 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2412.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c @@ -35,121 +35,95 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = { [DMACH_XD0] = { .name = "xdreq0", .channels = MAP(S3C2412_DMAREQSEL_XDREQ0), - .channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ0), }, [DMACH_XD1] = { .name = "xdreq1", .channels = MAP(S3C2412_DMAREQSEL_XDREQ1), - .channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ1), }, [DMACH_SDI] = { .name = "sdi", .channels = MAP(S3C2412_DMAREQSEL_SDI), - .channels_rx = MAP(S3C2412_DMAREQSEL_SDI), }, - [DMACH_SPI0] = { - .name = "spi0", + [DMACH_SPI0_RX] = { + .name = "spi0-rx", + .channels = MAP(S3C2412_DMAREQSEL_SPI0RX), + }, + [DMACH_SPI0_TX] = { + .name = "spi0-tx", .channels = MAP(S3C2412_DMAREQSEL_SPI0TX), - .channels_rx = MAP(S3C2412_DMAREQSEL_SPI0RX), }, - [DMACH_SPI1] = { - .name = "spi1", + [DMACH_SPI1_RX] = { + .name = "spi1-rx", + .channels = MAP(S3C2412_DMAREQSEL_SPI1RX), + }, + [DMACH_SPI1_TX] = { + .name = "spi1-tx", .channels = MAP(S3C2412_DMAREQSEL_SPI1TX), - .channels_rx = MAP(S3C2412_DMAREQSEL_SPI1RX), }, [DMACH_UART0] = { .name = "uart0", .channels = MAP(S3C2412_DMAREQSEL_UART0_0), - .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_0), }, [DMACH_UART1] = { .name = "uart1", .channels = MAP(S3C2412_DMAREQSEL_UART1_0), - .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_0), }, [DMACH_UART2] = { .name = "uart2", .channels = MAP(S3C2412_DMAREQSEL_UART2_0), - .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_0), }, [DMACH_UART0_SRC2] = { .name = "uart0", .channels = MAP(S3C2412_DMAREQSEL_UART0_1), - .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_1), }, [DMACH_UART1_SRC2] = { .name = "uart1", .channels = MAP(S3C2412_DMAREQSEL_UART1_1), - .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_1), }, [DMACH_UART2_SRC2] = { .name = "uart2", .channels = MAP(S3C2412_DMAREQSEL_UART2_1), - .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_1), }, [DMACH_TIMER] = { .name = "timer", .channels = MAP(S3C2412_DMAREQSEL_TIMER), - .channels_rx = MAP(S3C2412_DMAREQSEL_TIMER), }, [DMACH_I2S_IN] = { .name = "i2s-sdi", .channels = MAP(S3C2412_DMAREQSEL_I2SRX), - .channels_rx = MAP(S3C2412_DMAREQSEL_I2SRX), }, [DMACH_I2S_OUT] = { .name = "i2s-sdo", .channels = MAP(S3C2412_DMAREQSEL_I2STX), - .channels_rx = MAP(S3C2412_DMAREQSEL_I2STX), }, [DMACH_USB_EP1] = { .name = "usb-ep1", .channels = MAP(S3C2412_DMAREQSEL_USBEP1), - .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP1), }, [DMACH_USB_EP2] = { .name = "usb-ep2", .channels = MAP(S3C2412_DMAREQSEL_USBEP2), - .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP2), }, [DMACH_USB_EP3] = { .name = "usb-ep3", .channels = MAP(S3C2412_DMAREQSEL_USBEP3), - .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP3), }, [DMACH_USB_EP4] = { .name = "usb-ep4", .channels = MAP(S3C2412_DMAREQSEL_USBEP4), - .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP4), }, }; -static void s3c2412_dma_direction(struct s3c2410_dma_chan *chan, - struct s3c24xx_dma_map *map, - enum dma_data_direction dir) -{ - unsigned long chsel; - - if (dir == DMA_FROM_DEVICE) - chsel = map->channels_rx[0]; - else - chsel = map->channels[0]; - - chsel &= ~DMA_CH_VALID; - chsel |= S3C2412_DMAREQSEL_HW; - - writel(chsel, chan->regs + S3C2412_DMA_DMAREQSEL); -} - static void s3c2412_dma_select(struct s3c2410_dma_chan *chan, struct s3c24xx_dma_map *map) { - s3c2412_dma_direction(chan, map, chan->source); + unsigned long chsel = map->channels[0] & (~DMA_CH_VALID); + writel(chsel | S3C2412_DMAREQSEL_HW, + chan->regs + S3C2412_DMA_DMAREQSEL); } static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = { .select = s3c2412_dma_select, - .direction = s3c2412_dma_direction, .dcon_mask = 0, .map = s3c2412_dma_mappings, .map_size = ARRAY_SIZE(s3c2412_dma_mappings), diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c index 5fe3539dc2b..95b9f759fe9 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2443.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c @@ -128,7 +128,8 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = { static void s3c2443_dma_select(struct s3c2410_dma_chan *chan, struct s3c24xx_dma_map *map) { - writel(map->channels[0] | S3C2443_DMAREQSEL_HW, + unsigned long chsel = map->channels[0] & (~DMA_CH_VALID); + writel(chsel | S3C2443_DMAREQSEL_HW, chan->regs + S3C2443_DMA_DMAREQSEL); } diff --git a/arch/arm/mach-s3c24xx/dma.c b/arch/arm/mach-s3c24xx/dma.c index aab64909e9a..4a65cba3295 100644 --- a/arch/arm/mach-s3c24xx/dma.c +++ b/arch/arm/mach-s3c24xx/dma.c @@ -1159,9 +1159,6 @@ int s3c2410_dma_devconfig(enum dma_ch channel, return -EINVAL; } - if (dma_sel.direction != NULL) - (dma_sel.direction)(chan, chan->map, source); - return 0; } diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 69a31bc0730..65e1547678b 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -36,11 +36,13 @@ config ARCH_R8A7740 select RENESAS_INTC_IRQPIN config ARCH_R8A7778 - bool "R-Car M1 (R8A77780)" + bool "R-Car M1A (R8A77781)" select ARCH_WANT_OPTIONAL_GPIOLIB select CPU_V7 select SH_CLK_CPG select ARM_GIC + select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI config ARCH_R8A7779 bool "R-Car H1 (R8A77790)" @@ -143,6 +145,8 @@ config MACH_KZM9D config MACH_KZM9G bool "KZM-A9-GT board" depends on ARCH_SH73A0 + select ARCH_HAS_CPUFREQ + select ARCH_HAS_OPP select ARCH_REQUIRE_GPIOLIB select REGULATOR_FIXED_VOLTAGE if REGULATOR select SND_SOC_AK4642 if SND_SIMPLE_CARD diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c index dac4365c515..7ed2401b899 100644 --- a/arch/arm/mach-shmobile/board-bockw.c +++ b/arch/arm/mach-shmobile/board-bockw.c @@ -38,12 +38,18 @@ static struct resource smsc911x_resources[] = { DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */ }; +static struct rcar_phy_platform_data usb_phy_platform_data __initdata; + static const struct pinctrl_map bockw_pinctrl_map[] = { /* SCIF0 */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", "scif0_data_a", "scif0"), PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", "scif0_ctrl", "scif0"), + PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778", + "usb0", "usb0"), + PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778", + "usb1", "usb1"), }; #define IRQ0MR 0x30 @@ -54,6 +60,7 @@ static void __init bockw_init(void) r8a7778_clock_init(); r8a7778_init_irq_extpin(1); r8a7778_add_standard_devices(); + r8a7778_add_usb_phy_device(&usb_phy_platform_data); pinctrl_register_mappings(bockw_pinctrl_map, ARRAY_SIZE(bockw_pinctrl_map)); @@ -91,4 +98,5 @@ DT_MACHINE_START(BOCKW_DT, "bockw") .init_machine = bockw_init, .init_time = shmobile_timer_init, .dt_compat = bockw_boards_compat_dt, + .init_late = r8a7778_init_late, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index fac9e0f8789..b1b41b199f9 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -37,10 +37,6 @@ #include <linux/mmc/host.h> #include <linux/mmc/sh_mobile_sdhi.h> #include <linux/mfd/tmio.h> -#include <linux/usb/otg.h> -#include <linux/usb/ehci_pdriver.h> -#include <linux/usb/ohci_pdriver.h> -#include <linux/pm_runtime.h> #include <mach/hardware.h> #include <mach/r8a7779.h> #include <mach/common.h> @@ -61,6 +57,8 @@ static struct regulator_consumer_supply dummy_supplies[] = { REGULATOR_SUPPLY("vdd33a", "smsc911x"), }; +static struct rcar_phy_platform_data usb_phy_platform_data __initdata; + /* SMSC LAN89218 */ static struct resource smsc911x_resources[] = { [0] = { @@ -150,26 +148,6 @@ static struct platform_device hspi_device = { .num_resources = ARRAY_SIZE(hspi_resources), }; -/* USB PHY */ -static struct resource usb_phy_resources[] = { - [0] = { - .start = 0xffe70000, - .end = 0xffe70900 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 0xfff70000, - .end = 0xfff70900 - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device usb_phy_device = { - .name = "rcar_usb_phy", - .resource = usb_phy_resources, - .num_resources = ARRAY_SIZE(usb_phy_resources), -}; - /* LEDS */ static struct gpio_led marzen_leds[] = { { @@ -205,161 +183,9 @@ static struct platform_device *marzen_devices[] __initdata = { &sdhi0_device, &thermal_device, &hspi_device, - &usb_phy_device, &leds_device, }; -/* USB */ -static struct usb_phy *phy; -static int usb_power_on(struct platform_device *pdev) -{ - if (!phy) - return -EIO; - - pm_runtime_enable(&pdev->dev); - pm_runtime_get_sync(&pdev->dev); - - usb_phy_init(phy); - - return 0; -} - -static void usb_power_off(struct platform_device *pdev) -{ - if (!phy) - return; - - usb_phy_shutdown(phy); - - pm_runtime_put_sync(&pdev->dev); - pm_runtime_disable(&pdev->dev); -} - -static struct usb_ehci_pdata ehcix_pdata = { - .power_on = usb_power_on, - .power_off = usb_power_off, - .power_suspend = usb_power_off, -}; - -static struct resource ehci0_resources[] = { - [0] = { - .start = 0xffe70000, - .end = 0xffe70400 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_iid(0x4c), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device ehci0_device = { - .name = "ehci-platform", - .id = 0, - .dev = { - .dma_mask = &ehci0_device.dev.coherent_dma_mask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &ehcix_pdata, - }, - .num_resources = ARRAY_SIZE(ehci0_resources), - .resource = ehci0_resources, -}; - -static struct resource ehci1_resources[] = { - [0] = { - .start = 0xfff70000, - .end = 0xfff70400 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_iid(0x4d), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device ehci1_device = { - .name = "ehci-platform", - .id = 1, - .dev = { - .dma_mask = &ehci1_device.dev.coherent_dma_mask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &ehcix_pdata, - }, - .num_resources = ARRAY_SIZE(ehci1_resources), - .resource = ehci1_resources, -}; - -static struct usb_ohci_pdata ohcix_pdata = { - .power_on = usb_power_on, - .power_off = usb_power_off, - .power_suspend = usb_power_off, -}; - -static struct resource ohci0_resources[] = { - [0] = { - .start = 0xffe70400, - .end = 0xffe70800 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_iid(0x4c), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device ohci0_device = { - .name = "ohci-platform", - .id = 0, - .dev = { - .dma_mask = &ohci0_device.dev.coherent_dma_mask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &ohcix_pdata, - }, - .num_resources = ARRAY_SIZE(ohci0_resources), - .resource = ohci0_resources, -}; - -static struct resource ohci1_resources[] = { - [0] = { - .start = 0xfff70400, - .end = 0xfff70800 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_iid(0x4d), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device ohci1_device = { - .name = "ohci-platform", - .id = 1, - .dev = { - .dma_mask = &ohci1_device.dev.coherent_dma_mask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &ohcix_pdata, - }, - .num_resources = ARRAY_SIZE(ohci1_resources), - .resource = ohci1_resources, -}; - -static struct platform_device *marzen_late_devices[] __initdata = { - &ehci0_device, - &ehci1_device, - &ohci0_device, - &ohci1_device, -}; - -void __init marzen_init_late(void) -{ - /* get usb phy */ - phy = usb_get_phy(USB_PHY_TYPE_USB2); - - shmobile_init_late(); - platform_add_devices(marzen_late_devices, - ARRAY_SIZE(marzen_late_devices)); -} - static const struct pinctrl_map marzen_pinctrl_map[] = { /* HSPI0 */ PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779", @@ -407,6 +233,7 @@ static void __init marzen_init(void) r8a7779_pinmux_init(); r8a7779_add_standard_devices(); + r8a7779_add_usb_phy_device(&usb_phy_platform_data); platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); } @@ -417,6 +244,6 @@ MACHINE_START(MARZEN, "marzen") .nr_irqs = NR_IRQS_LEGACY, .init_irq = r8a7779_init_irq, .init_machine = marzen_init, - .init_late = marzen_init_late, + .init_late = r8a7779_init_late, .init_time = r8a7779_earlytimer_init, MACHINE_END diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index e710c00c382..5f7fe628b8a 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -22,15 +22,44 @@ #include <linux/kernel.h> #include <linux/sh_clk.h> #include <linux/clkdev.h> +#include <mach/clock.h> #include <mach/common.h> #define CPG_BASE 0xe6150000 #define CPG_LEN 0x270 -#define MPCKCR 0xe6150080 #define SMSTPCR2 0xe6150138 +#define SMSTPCR3 0xe615013c #define SMSTPCR5 0xe6150144 +#define FRQCRA 0xE6150000 +#define FRQCRB 0xE6150004 +#define VCLKCR1 0xE6150008 +#define VCLKCR2 0xE615000C +#define VCLKCR3 0xE615001C +#define VCLKCR4 0xE6150014 +#define VCLKCR5 0xE6150034 +#define ZBCKCR 0xE6150010 +#define SD0CKCR 0xE6150074 +#define SD1CKCR 0xE6150078 +#define SD2CKCR 0xE615007C +#define MMC0CKCR 0xE6150240 +#define MMC1CKCR 0xE6150244 +#define FSIACKCR 0xE6150018 +#define FSIBCKCR 0xE6150090 +#define MPCKCR 0xe6150080 +#define SPUVCKCR 0xE6150094 +#define HSICKCR 0xE615026C +#define M4CKCR 0xE6150098 +#define PLLECR 0xE61500D0 +#define PLL1CR 0xE6150028 +#define PLL2CR 0xE615002C +#define PLL2SCR 0xE61501F4 +#define PLL2HCR 0xE61501E4 +#define CKSCR 0xE61500C0 + +#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base) + static struct clk_mapping cpg_mapping = { .phys = CPG_BASE, .len = CPG_LEN, @@ -51,29 +80,327 @@ static struct clk extal2_clk = { .mapping = &cpg_mapping, }; +static struct sh_clk_ops followparent_clk_ops = { + .recalc = followparent_recalc, +}; + +static struct clk main_clk = { + /* .parent will be set r8a73a4_clock_init */ + .ops = &followparent_clk_ops, +}; + +SH_CLK_RATIO(div2, 1, 2); +SH_CLK_RATIO(div4, 1, 4); + +SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2); +SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2); +SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2); +SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_clk, div4); + +/* External FSIACK/FSIBCK clock */ +static struct clk fsiack_clk = { +}; + +static struct clk fsibck_clk = { +}; + +/* + * PLL clocks + */ +static struct clk *pll_parent_main[] = { + [0] = &main_clk, + [1] = &main_div2_clk +}; + +static struct clk *pll_parent_main_extal[8] = { + [0] = &main_div2_clk, + [1] = &extal2_div2_clk, + [3] = &extal2_div4_clk, + [4] = &main_clk, + [5] = &extal2_clk, +}; + +static unsigned long pll_recalc(struct clk *clk) +{ + unsigned long mult = 1; + + if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit)) + mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1); + + return clk->parent->rate * mult; +} + +static int pll_set_parent(struct clk *clk, struct clk *parent) +{ + u32 val; + int i, ret; + + if (!clk->parent_table || !clk->parent_num) + return -EINVAL; + + /* Search the parent */ + for (i = 0; i < clk->parent_num; i++) + if (clk->parent_table[i] == parent) + break; + + if (i == clk->parent_num) + return -ENODEV; + + ret = clk_reparent(clk, parent); + if (ret < 0) + return ret; + + val = ioread32(clk->mapped_reg) & + ~(((1 << clk->src_width) - 1) << clk->src_shift); + + iowrite32(val | i << clk->src_shift, clk->mapped_reg); + + return 0; +} + +static struct sh_clk_ops pll_clk_ops = { + .recalc = pll_recalc, + .set_parent = pll_set_parent, +}; + +#define PLL_CLOCK(name, p, pt, w, s, reg, e) \ + static struct clk name = { \ + .ops = &pll_clk_ops, \ + .flags = CLK_ENABLE_ON_INIT, \ + .parent = p, \ + .parent_table = pt, \ + .parent_num = ARRAY_SIZE(pt), \ + .src_width = w, \ + .src_shift = s, \ + .enable_reg = (void __iomem *)reg, \ + .enable_bit = e, \ + .mapping = &cpg_mapping, \ + } + +PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1); +PLL_CLOCK(pll2_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR, 2); +PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4); +PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5); + +SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2); + static struct clk *main_clks[] = { &extalr_clk, &extal1_clk, + &extal1_div2_clk, &extal2_clk, + &extal2_div2_clk, + &extal2_div4_clk, + &main_clk, + &main_div2_clk, + &fsiack_clk, + &fsibck_clk, + &pll1_clk, + &pll1_div2_clk, + &pll2_clk, + &pll2s_clk, + &pll2h_clk, +}; + +/* DIV4 */ +static void div4_kick(struct clk *clk) +{ + unsigned long value; + + /* set KICK bit in FRQCRB to update hardware setting */ + value = ioread32(CPG_MAP(FRQCRB)); + value |= (1 << 31); + iowrite32(value, CPG_MAP(FRQCRB)); +} + +static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10}; + +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = divisors, + .nr_divisors = ARRAY_SIZE(divisors), +}; + +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, + .kick = div4_kick, +}; + +enum { + DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, + DIV4_ZX, DIV4_ZS, DIV4_HP, + DIV4_NR }; + +static struct clk div4_clks[DIV4_NR] = { + [DIV4_I] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT), + [DIV4_M3] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT), + [DIV4_B] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 8, 0x0dff, CLK_ENABLE_ON_INIT), + [DIV4_M1] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 4, 0x1dff, 0), + [DIV4_M2] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 0, 0x1dff, 0), + [DIV4_ZX] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0), + [DIV4_ZS] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 8, 0x0dff, 0), + [DIV4_HP] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 4, 0x0dff, 0), }; enum { + DIV6_ZB, + DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, + DIV6_MMC0, DIV6_MMC1, + DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5, + DIV6_FSIA, DIV6_FSIB, + DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV, + DIV6_NR }; + +static struct clk *div6_parents[8] = { + [0] = &pll1_div2_clk, + [1] = &pll2s_clk, + [3] = &extal2_clk, + [4] = &main_div2_clk, + [6] = &extalr_clk, +}; + +static struct clk *fsia_parents[4] = { + [0] = &pll1_div2_clk, + [1] = &pll2s_clk, + [2] = &fsiack_clk, +}; + +static struct clk *fsib_parents[4] = { + [0] = &pll1_div2_clk, + [1] = &pll2s_clk, + [2] = &fsibck_clk, +}; + +static struct clk *mp_parents[4] = { + [0] = &pll1_div2_clk, + [1] = &pll2s_clk, + [2] = &extal2_clk, + [3] = &extal2_clk, +}; + +static struct clk *m4_parents[2] = { + [0] = &pll2s_clk, +}; + +static struct clk *hsi_parents[4] = { + [0] = &pll2h_clk, + [1] = &pll1_div2_clk, + [3] = &pll2s_clk, +}; + +/*** FIXME *** + * SH_CLK_DIV6_EXT() macro doesn't care .mapping + * but, it is necessary on R-Car (= ioremap() base CPG) + * The difference between + * SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT() + * is only .mapping + */ +#define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents, \ + _num_parents, _src_shift, _src_width) \ +{ \ + .enable_reg = (void __iomem *)_reg, \ + .enable_bit = 0, /* unused */ \ + .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \ + .div_mask = SH_CLK_DIV6_MSK, \ + .parent_table = _parents, \ + .parent_num = _num_parents, \ + .src_shift = _src_shift, \ + .src_width = _src_width, \ + .mapping = &cpg_mapping, \ +} + +static struct clk div6_clks[DIV6_NR] = { + [DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT, + div6_parents, 2, 7, 1), + [DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0, + div6_parents, 2, 6, 2), + [DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0, + div6_parents, 2, 6, 2), + [DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0, + div6_parents, 2, 6, 2), + [DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0, + div6_parents, 2, 6, 2), + [DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0, + div6_parents, 2, 6, 2), + [DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0, /* didn't care bit[6-7] */ + div6_parents, ARRAY_SIZE(div6_parents), 12, 3), + [DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0, /* didn't care bit[6-7] */ + div6_parents, ARRAY_SIZE(div6_parents), 12, 3), + [DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0, /* didn't care bit[6-7] */ + div6_parents, ARRAY_SIZE(div6_parents), 12, 3), + [DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0, /* didn't care bit[6-7] */ + div6_parents, ARRAY_SIZE(div6_parents), 12, 3), + [DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0, /* didn't care bit[6-7] */ + div6_parents, ARRAY_SIZE(div6_parents), 12, 3), + [DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0, + fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2), + [DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0, + fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2), + [DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0, /* it needs bit[9-11] control */ + mp_parents, ARRAY_SIZE(mp_parents), 6, 2), + /* pll2s will be selected always for M4 */ + [DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0, /* it needs bit[9] control */ + m4_parents, ARRAY_SIZE(m4_parents), 6, 1), + [DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0, /* it needs bit[9] control */ + hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2), + [DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0, + mp_parents, ARRAY_SIZE(mp_parents), 6, 2), +}; + +/* MSTP */ +enum { MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, + MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP522, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { - [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ - [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ - [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ - [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ - [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ - [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */ + [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 4, 0), /* SCIFA0 */ + [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 3, 0), /* SCIFA1 */ + [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 6, 0), /* SCIFB0 */ + [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */ + [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */ + [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */ + [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */ + [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */ + [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */ + [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */ + [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */ [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */ }; static struct clk_lookup lookups[] = { + /* main clock */ + CLKDEV_CON_ID("extal1", &extal1_clk), + CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk), + CLKDEV_CON_ID("extal2", &extal2_clk), + CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk), + CLKDEV_CON_ID("extal2_div4", &extal2_div4_clk), + CLKDEV_CON_ID("fsiack", &fsiack_clk), + CLKDEV_CON_ID("fsibck", &fsibck_clk), + + /* pll clock */ + CLKDEV_CON_ID("pll1", &pll1_clk), + CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk), + CLKDEV_CON_ID("pll2", &pll2_clk), + CLKDEV_CON_ID("pll2s", &pll2s_clk), + CLKDEV_CON_ID("pll2h", &pll2h_clk), + + /* DIV6 */ + CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]), + CLKDEV_CON_ID("vck1", &div6_clks[DIV6_VCK1]), + CLKDEV_CON_ID("vck2", &div6_clks[DIV6_VCK2]), + CLKDEV_CON_ID("vck3", &div6_clks[DIV6_VCK3]), + CLKDEV_CON_ID("vck4", &div6_clks[DIV6_VCK4]), + CLKDEV_CON_ID("vck5", &div6_clks[DIV6_VCK5]), + CLKDEV_CON_ID("fsia", &div6_clks[DIV6_FSIA]), + CLKDEV_CON_ID("fsib", &div6_clks[DIV6_FSIB]), + CLKDEV_CON_ID("mp", &div6_clks[DIV6_MP]), + CLKDEV_CON_ID("m4", &div6_clks[DIV6_M4]), + CLKDEV_CON_ID("hsi", &div6_clks[DIV6_HSI]), + CLKDEV_CON_ID("spuv", &div6_clks[DIV6_SPUV]), + + /* MSTP */ CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), @@ -81,6 +408,16 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), + CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), + CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), + CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), + CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), + CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), + CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), /* for DT */ CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), @@ -88,22 +425,40 @@ static struct clk_lookup lookups[] = { void __init r8a73a4_clock_init(void) { - void __iomem *cpg_base, *reg; + void __iomem *reg; int k, ret = 0; + u32 ckscr; + + reg = ioremap_nocache(CKSCR, PAGE_SIZE); + BUG_ON(!reg); + ckscr = ioread32(reg); + iounmap(reg); - /* fix MPCLK to EXTAL2 for now. - * this is needed until more detailed clock topology is supported - */ - cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN); - BUG_ON(!cpg_base); - reg = cpg_base + (MPCKCR - CPG_BASE); - iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */ - iounmap(cpg_base); + switch ((ckscr >> 28) & 0x3) { + case 0: + main_clk.parent = &extal1_clk; + break; + case 1: + main_clk.parent = &extal1_div2_clk; + break; + case 2: + main_clk.parent = &extal2_clk; + break; + case 3: + main_clk.parent = &extal2_div2_clk; + break; + } for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); if (!ret) + ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); + + if (!ret) + ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR); + + if (!ret) ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); clkdev_add_table(lookups, ARRAY_SIZE(lookups)); diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index c0d39aa6de5..7fd32d604e3 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c @@ -266,7 +266,7 @@ static struct clk fsiack_clk = { static struct clk fsibck_clk = { }; -struct clk *main_clks[] = { +static struct clk *main_clks[] = { &extalr_clk, &extal1_clk, &extal2_clk, @@ -317,7 +317,7 @@ enum { DIV4_NR }; -struct clk div4_clks[DIV4_NR] = { +static struct clk div4_clks[DIV4_NR] = { [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT), [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT), [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), @@ -461,7 +461,7 @@ enum { MSTP329, MSTP328, MSTP323, MSTP320, MSTP314, MSTP313, MSTP312, - MSTP309, + MSTP309, MSTP304, MSTP416, MSTP415, MSTP407, MSTP406, @@ -499,6 +499,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */ [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */ [MSTP309] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 9, 0), /* GEther */ + [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_CP], SMSTPCR3, 4, 0), /* TPU0 */ [MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 16, 0), /* USBHOST */ [MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */ @@ -551,6 +552,7 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_tmu.4", &mstp_clks[MSTP111]), CLKDEV_DEV_ID("sh_tmu.5", &mstp_clks[MSTP111]), CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), + CLKDEV_DEV_ID("fff20000.i2c", &mstp_clks[MSTP116]), CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), @@ -584,6 +586,7 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), + CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]), @@ -592,6 +595,8 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]), CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]), + CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]), + CLKDEV_DEV_ID("renesas_tpu_pwm", &mstp_clks[MSTP304]), CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c index cd6855290b1..53798e5037d 100644 --- a/arch/arm/mach-shmobile/clock-r8a7778.c +++ b/arch/arm/mach-shmobile/clock-r8a7778.c @@ -23,9 +23,23 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +/* + * MD MD MD MD PLLA PLLB EXTAL clki clkz + * 19 18 12 11 (HMz) (MHz) (MHz) + *---------------------------------------------------------------------------- + * 1 0 0 0 x21 x21 38.00 800 800 + * 1 0 0 1 x24 x24 33.33 800 800 + * 1 0 1 0 x28 x28 28.50 800 800 + * 1 0 1 1 x32 x32 25.00 800 800 + * 1 1 0 1 x24 x21 33.33 800 700 + * 1 1 1 0 x28 x21 28.50 800 600 + * 1 1 1 1 x32 x24 25.00 800 600 + */ + #include <linux/io.h> #include <linux/sh_clk.h> #include <linux/clkdev.h> +#include <mach/clock.h> #include <mach/common.h> #define MSTPCR0 IOMEM(0xffc80030) @@ -37,6 +51,9 @@ #define MSTPCR4 IOMEM(0xffc80050) #define MSTPCR5 IOMEM(0xffc80054) #define MSTPCR6 IOMEM(0xffc80058) +#define MODEMR 0xFFCC0020 + +#define MD(nr) BIT(nr) /* ioremap() through clock mapping mandatory to avoid * collision with ARM coherent DMA virtual memory range. @@ -47,37 +64,94 @@ static struct clk_mapping cpg_mapping = { .len = 0x80, }; -static struct clk clkp = { - .rate = 62500000, /* FIXME: shortcut */ - .flags = CLK_ENABLE_ON_INIT, +static struct clk extal_clk = { + /* .rate will be updated on r8a7778_clock_init() */ .mapping = &cpg_mapping, }; +/* + * clock ratio of these clock will be updated + * on r8a7778_clock_init() + */ +SH_FIXED_RATIO_CLK_SET(plla_clk, extal_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(pllb_clk, extal_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(i_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(s_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(s1_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(s3_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(s4_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(b_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(out_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(p_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(g_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(z_clk, pllb_clk, 1, 1); + static struct clk *main_clks[] = { - &clkp, + &extal_clk, + &plla_clk, + &pllb_clk, + &i_clk, + &s_clk, + &s1_clk, + &s3_clk, + &s4_clk, + &b_clk, + &out_clk, + &p_clk, + &g_clk, + &z_clk, }; enum { + MSTP331, + MSTP323, MSTP322, MSTP321, MSTP114, - MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, + MSTP100, + MSTP030, + MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, MSTP016, MSTP015, + MSTP007, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { - [MSTP114] = SH_CLK_MSTP32(&clkp, MSTPCR1, 14, 0), /* Ether */ - [MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */ - [MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */ - [MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */ - [MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */ - [MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */ - [MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */ - [MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */ - [MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */ + [MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */ + [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */ + [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ + [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */ + [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */ + [MSTP100] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 0, 0), /* USB0/1 */ + [MSTP030] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 30, 0), /* I2C0 */ + [MSTP029] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 29, 0), /* I2C1 */ + [MSTP028] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 28, 0), /* I2C2 */ + [MSTP027] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 27, 0), /* I2C3 */ + [MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */ + [MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */ + [MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */ + [MSTP023] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 23, 0), /* SCIF3 */ + [MSTP022] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 22, 0), /* SCIF4 */ + [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */ + [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */ + [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */ + [MSTP007] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 7, 0), /* HSPI */ }; static struct clk_lookup lookups[] = { + /* main */ + CLKDEV_CON_ID("shyway_clk", &s_clk), + CLKDEV_CON_ID("peripheral_clk", &p_clk), + /* MSTP32 clocks */ + CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */ + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */ + CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ + CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ + CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ + CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ + CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ + CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ @@ -86,12 +160,93 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */ CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */ + CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ + CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ + CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ }; void __init r8a7778_clock_init(void) { + void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE); + u32 mode; int k, ret = 0; + BUG_ON(!modemr); + mode = ioread32(modemr); + iounmap(modemr); + + switch (mode & (MD(19) | MD(18) | MD(12) | MD(11))) { + case MD(19): + extal_clk.rate = 38000000; + SH_CLK_SET_RATIO(&plla_clk_ratio, 21, 1); + SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1); + break; + case MD(19) | MD(11): + extal_clk.rate = 33333333; + SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1); + SH_CLK_SET_RATIO(&pllb_clk_ratio, 24, 1); + break; + case MD(19) | MD(12): + extal_clk.rate = 28500000; + SH_CLK_SET_RATIO(&plla_clk_ratio, 28, 1); + SH_CLK_SET_RATIO(&pllb_clk_ratio, 28, 1); + break; + case MD(19) | MD(12) | MD(11): + extal_clk.rate = 25000000; + SH_CLK_SET_RATIO(&plla_clk_ratio, 32, 1); + SH_CLK_SET_RATIO(&pllb_clk_ratio, 32, 1); + break; + case MD(19) | MD(18) | MD(11): + extal_clk.rate = 33333333; + SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1); + SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1); + break; + case MD(19) | MD(18) | MD(12): + extal_clk.rate = 28500000; + SH_CLK_SET_RATIO(&plla_clk_ratio, 28, 1); + SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1); + break; + case MD(19) | MD(18) | MD(12) | MD(11): + extal_clk.rate = 25000000; + SH_CLK_SET_RATIO(&plla_clk_ratio, 32, 1); + SH_CLK_SET_RATIO(&pllb_clk_ratio, 24, 1); + break; + default: + BUG(); + } + + if (mode & MD(1)) { + SH_CLK_SET_RATIO(&i_clk_ratio, 1, 1); + SH_CLK_SET_RATIO(&s_clk_ratio, 1, 3); + SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 6); + SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4); + SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8); + SH_CLK_SET_RATIO(&p_clk_ratio, 1, 12); + SH_CLK_SET_RATIO(&g_clk_ratio, 1, 12); + if (mode & MD(2)) { + SH_CLK_SET_RATIO(&b_clk_ratio, 1, 18); + SH_CLK_SET_RATIO(&out_clk_ratio, 1, 18); + } else { + SH_CLK_SET_RATIO(&b_clk_ratio, 1, 12); + SH_CLK_SET_RATIO(&out_clk_ratio, 1, 12); + } + } else { + SH_CLK_SET_RATIO(&i_clk_ratio, 1, 1); + SH_CLK_SET_RATIO(&s_clk_ratio, 1, 4); + SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 8); + SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4); + SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8); + SH_CLK_SET_RATIO(&p_clk_ratio, 1, 16); + SH_CLK_SET_RATIO(&g_clk_ratio, 1, 12); + if (mode & MD(2)) { + SH_CLK_SET_RATIO(&b_clk_ratio, 1, 16); + SH_CLK_SET_RATIO(&out_clk_ratio, 1, 16); + } else { + SH_CLK_SET_RATIO(&b_clk_ratio, 1, 12); + SH_CLK_SET_RATIO(&out_clk_ratio, 1, 12); + } + } + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index 31d5cd4d978..9daeb8c3748 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c @@ -112,7 +112,7 @@ static struct clk *main_clks[] = { }; enum { MSTP323, MSTP322, MSTP321, MSTP320, - MSTP115, MSTP114, + MSTP116, MSTP115, MSTP114, MSTP103, MSTP101, MSTP100, MSTP030, MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, @@ -125,6 +125,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */ [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */ [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */ + [MSTP116] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 16, 0), /* PCIe */ [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */ [MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */ [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */ @@ -161,6 +162,7 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("peripheral_clk", &clkp_clk), /* MSTP32 clocks */ + CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */ CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */ CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */ diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index bad9bf2e34d..5d71313df52 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c @@ -22,48 +22,228 @@ #include <linux/kernel.h> #include <linux/sh_clk.h> #include <linux/clkdev.h> +#include <mach/clock.h> #include <mach/common.h> +/* + * MD EXTAL PLL0 PLL1 PLL3 + * 14 13 19 (MHz) *1 *1 + *--------------------------------------------------- + * 0 0 0 15 x 1 x172/2 x208/2 x106 + * 0 0 1 15 x 1 x172/2 x208/2 x88 + * 0 1 0 20 x 1 x130/2 x156/2 x80 + * 0 1 1 20 x 1 x130/2 x156/2 x66 + * 1 0 0 26 / 2 x200/2 x240/2 x122 + * 1 0 1 26 / 2 x200/2 x240/2 x102 + * 1 1 0 30 / 2 x172/2 x208/2 x106 + * 1 1 1 30 / 2 x172/2 x208/2 x88 + * + * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2) + * see "p1 / 2" on R8A7790_CLOCK_ROOT() below + */ + +#define MD(nr) (1 << nr) + #define CPG_BASE 0xe6150000 #define CPG_LEN 0x1000 #define SMSTPCR2 0xe6150138 +#define SMSTPCR3 0xe615013c #define SMSTPCR7 0xe615014c +#define MODEMR 0xE6160060 +#define SDCKCR 0xE6150074 +#define SD2CKCR 0xE6150078 +#define SD3CKCR 0xE615007C +#define MMC0CKCR 0xE6150240 +#define MMC1CKCR 0xE6150244 +#define SSPCKCR 0xE6150248 +#define SSPRSCKCR 0xE615024C + static struct clk_mapping cpg_mapping = { .phys = CPG_BASE, .len = CPG_LEN, }; -static struct clk p_clk = { - .rate = 65000000, /* shortcut for now */ +static struct clk extal_clk = { + /* .rate will be updated on r8a7790_clock_init() */ .mapping = &cpg_mapping, }; -static struct clk mp_clk = { - .rate = 52000000, /* shortcut for now */ - .mapping = &cpg_mapping, +static struct sh_clk_ops followparent_clk_ops = { + .recalc = followparent_recalc, +}; + +static struct clk main_clk = { + /* .parent will be set r8a73a4_clock_init */ + .ops = &followparent_clk_ops, }; +/* + * clock ratio of these clock will be updated + * on r8a7790_clock_init() + */ +SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(lb_clk, pll1_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1); + +/* fixed ratio clock */ +SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2); +SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2); + +SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2); +SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3); +SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3); +SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6); +SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12); +SH_FIXED_RATIO_CLK_SET(i_clk, pll1_clk, 1, 2); +SH_FIXED_RATIO_CLK_SET(b_clk, pll1_clk, 1, 12); +SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24); +SH_FIXED_RATIO_CLK_SET(cl_clk, pll1_clk, 1, 48); +SH_FIXED_RATIO_CLK_SET(m2_clk, pll1_clk, 1, 8); +SH_FIXED_RATIO_CLK_SET(imp_clk, pll1_clk, 1, 4); +SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024)); +SH_FIXED_RATIO_CLK_SET(oscclk_clk, pll1_clk, 1, (12 * 1024)); + +SH_FIXED_RATIO_CLK_SET(zb3_clk, pll3_clk, 1, 4); +SH_FIXED_RATIO_CLK_SET(zb3d2_clk, pll3_clk, 1, 8); +SH_FIXED_RATIO_CLK_SET(ddr_clk, pll3_clk, 1, 8); +SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15); + static struct clk *main_clks[] = { + &extal_clk, + &extal_div2_clk, + &main_clk, + &pll1_clk, + &pll1_div2_clk, + &pll3_clk, + &lb_clk, + &qspi_clk, + &zg_clk, + &zx_clk, + &zs_clk, + &hp_clk, + &i_clk, + &b_clk, &p_clk, + &cl_clk, + &m2_clk, + &imp_clk, + &rclk_clk, + &oscclk_clk, + &zb3_clk, + &zb3d2_clk, + &ddr_clk, &mp_clk, + &cp_clk, +}; + +/* SDHI (DIV4) clock */ +static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 }; + +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = divisors, + .nr_divisors = ARRAY_SIZE(divisors), +}; + +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, +}; + +enum { + DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR +}; + +static struct clk div4_clks[DIV4_NR] = { + [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT), + [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT), + [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT), +}; + +/* DIV6 clocks */ +enum { + DIV6_SD2, DIV6_SD3, + DIV6_MMC0, DIV6_MMC1, + DIV6_SSP, DIV6_SSPRS, + DIV6_NR +}; + +static struct clk div6_clks[DIV6_NR] = { + [DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0), + [DIV6_SD3] = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0), + [DIV6_MMC0] = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0), + [DIV6_MMC1] = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0), + [DIV6_SSP] = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0), + [DIV6_SSPRS] = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0), +}; + +/* MSTP */ +enum { + MSTP721, MSTP720, + MSTP717, MSTP716, + MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, + MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, + MSTP_NR }; -enum { MSTP721, MSTP720, - MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ + [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */ + [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */ + [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */ + [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SD2], SMSTPCR3, 12, 0), /* SDHI2 */ + [MSTP311] = SH_CLK_MSTP32(&div6_clks[DIV6_SD3], SMSTPCR3, 11, 0), /* SDHI3 */ + [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, 0), /* MMC1 */ + [MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */ [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ + [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ + [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */ }; static struct clk_lookup lookups[] = { + + /* main clocks */ + CLKDEV_CON_ID("extal", &extal_clk), + CLKDEV_CON_ID("extal_div2", &extal_div2_clk), + CLKDEV_CON_ID("main", &main_clk), + CLKDEV_CON_ID("pll1", &pll1_clk), + CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk), + CLKDEV_CON_ID("pll3", &pll3_clk), + CLKDEV_CON_ID("zg", &zg_clk), + CLKDEV_CON_ID("zx", &zx_clk), + CLKDEV_CON_ID("zs", &zs_clk), + CLKDEV_CON_ID("hp", &hp_clk), + CLKDEV_CON_ID("i", &i_clk), + CLKDEV_CON_ID("b", &b_clk), + CLKDEV_CON_ID("lb", &lb_clk), + CLKDEV_CON_ID("p", &p_clk), + CLKDEV_CON_ID("cl", &cl_clk), + CLKDEV_CON_ID("m2", &m2_clk), + CLKDEV_CON_ID("imp", &imp_clk), + CLKDEV_CON_ID("rclk", &rclk_clk), + CLKDEV_CON_ID("oscclk", &oscclk_clk), + CLKDEV_CON_ID("zb3", &zb3_clk), + CLKDEV_CON_ID("zb3d2", &zb3d2_clk), + CLKDEV_CON_ID("ddr", &ddr_clk), + CLKDEV_CON_ID("mp", &mp_clk), + CLKDEV_CON_ID("qspi", &qspi_clk), + CLKDEV_CON_ID("cp", &cp_clk), + + /* DIV4 */ + CLKDEV_CON_ID("sdh", &div4_clks[DIV4_SDH]), + + /* DIV6 */ + CLKDEV_CON_ID("ssp", &div6_clks[DIV6_SSP]), + CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]), + + /* MSTP */ CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), @@ -72,16 +252,77 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]), CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]), CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), + CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), + CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), + CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), + CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), + CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), + CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), + CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("ee160000.sdhi", &mstp_clks[MSTP311]), + CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]), + CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), + CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), }; +#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ + extal_clk.rate = e * 1000 * 1000; \ + main_clk.parent = m; \ + SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \ + if (mode & MD(19)) \ + SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \ + else \ + SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1) + + void __init r8a7790_clock_init(void) { + void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE); + u32 mode; int k, ret = 0; + BUG_ON(!modemr); + mode = ioread32(modemr); + iounmap(modemr); + + switch (mode & (MD(14) | MD(13))) { + case 0: + R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88); + break; + case MD(13): + R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66); + break; + case MD(14): + R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102); + break; + case MD(13) | MD(14): + R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88); + break; + } + + if (mode & (MD(18))) + SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36); + else + SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24); + + if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2)) + SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16); + else + SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20); + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); if (!ret) + ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); + + if (!ret) + ret = sh_clk_div6_register(div6_clks, DIV6_NR); + + if (!ret) ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); clkdev_add_table(lookups, ARRAY_SIZE(lookups)); diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index 784fbaa4cc5..d9fd0336b91 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -228,6 +228,11 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, static struct clk div4_clks[DIV4_NR] = { [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT), + /* + * ZG clock is dividing PLL0 frequency to supply SGX. Make sure not to + * exceed maximum frequencies of 201.5MHz for VDD_DVFS=1.175 and + * 239.2MHz for VDD_DVFS=1.315V. + */ [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT), [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT), [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT), @@ -252,6 +257,101 @@ static struct clk twd_clk = { .ops = &twd_clk_ops, }; +static struct sh_clk_ops zclk_ops, kicker_ops; +static const struct sh_clk_ops *div4_clk_ops; + +static int zclk_set_rate(struct clk *clk, unsigned long rate) +{ + int ret; + + if (!clk->parent || !__clk_get(clk->parent)) + return -ENODEV; + + if (readl(FRQCRB) & (1 << 31)) + return -EBUSY; + + if (rate == clk_get_rate(clk->parent)) { + /* 1:1 - switch off divider */ + __raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB); + /* nullify the divider to prepare for the next time */ + ret = div4_clk_ops->set_rate(clk, rate / 2); + if (!ret) + ret = frqcr_kick(); + if (ret > 0) + ret = 0; + } else { + /* Enable the divider */ + __raw_writel(__raw_readl(FRQCRB) | (1 << 28), FRQCRB); + + ret = frqcr_kick(); + if (ret >= 0) + /* + * set the divider - call the DIV4 method, it will kick + * FRQCRB too + */ + ret = div4_clk_ops->set_rate(clk, rate); + if (ret < 0) + goto esetrate; + } + +esetrate: + __clk_put(clk->parent); + return ret; +} + +static long zclk_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long div_freq = div4_clk_ops->round_rate(clk, rate), + parent_freq = clk_get_rate(clk->parent); + + if (rate > div_freq && abs(parent_freq - rate) < rate - div_freq) + return parent_freq; + + return div_freq; +} + +static unsigned long zclk_recalc(struct clk *clk) +{ + /* + * Must recalculate frequencies in case PLL0 has been changed, even if + * the divisor is unused ATM! + */ + unsigned long div_freq = div4_clk_ops->recalc(clk); + + if (__raw_readl(FRQCRB) & (1 << 28)) + return div_freq; + + return clk_get_rate(clk->parent); +} + +static int kicker_set_rate(struct clk *clk, unsigned long rate) +{ + if (__raw_readl(FRQCRB) & (1 << 31)) + return -EBUSY; + + return div4_clk_ops->set_rate(clk, rate); +} + +static void div4_clk_extend(void) +{ + int i; + + div4_clk_ops = div4_clks[0].ops; + + /* Add a kicker-busy check before changing the rate */ + kicker_ops = *div4_clk_ops; + /* We extend the DIV4 clock with a 1:1 pass-through case */ + zclk_ops = *div4_clk_ops; + + kicker_ops.set_rate = kicker_set_rate; + zclk_ops.set_rate = zclk_set_rate; + zclk_ops.round_rate = zclk_round_rate; + zclk_ops.recalc = zclk_recalc; + + for (i = 0; i < DIV4_NR; i++) + div4_clks[i].ops = i == DIV4_Z ? &zclk_ops : &kicker_ops; +} + enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1, DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, DIV6_FSIA, DIV6_FSIB, DIV6_SUB, @@ -450,7 +550,7 @@ static struct clk *late_main_clks[] = { }; enum { MSTP001, - MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100, + MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP112, MSTP100, MSTP219, MSTP218, MSTP217, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322, @@ -471,6 +571,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */ [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */ + [MSTP112] = MSTP(&div4_clks[DIV4_ZG], SMSTPCR1, 12, 0), /* SGX */ [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */ [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */ @@ -513,6 +614,9 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("r_clk", &r_clk), CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */ + /* DIV4 clocks */ + CLKDEV_DEV_ID("cpufreq-cpu0", &div4_clks[DIV4_Z]), + /* DIV6 clocks */ CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]), @@ -604,8 +708,11 @@ void __init sh73a0_clock_init(void) for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); - if (!ret) + if (!ret) { ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); + if (!ret) + div4_clk_extend(); + } if (!ret) ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR); diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h index 76ac61292e4..03e56074928 100644 --- a/arch/arm/mach-shmobile/include/mach/clock.h +++ b/arch/arm/mach-shmobile/include/mach/clock.h @@ -24,16 +24,16 @@ struct clk name = { \ } #define SH_FIXED_RATIO_CLK(name, p, r) \ -static SH_FIXED_RATIO_CLKg(name, p, r); +static SH_FIXED_RATIO_CLKg(name, p, r) #define SH_FIXED_RATIO_CLK_SET(name, p, m, d) \ SH_CLK_RATIO(name, m, d); \ - SH_FIXED_RATIO_CLK(name, p, name); + SH_FIXED_RATIO_CLK(name, p, name) #define SH_CLK_SET_RATIO(p, m, d) \ -{ \ +do { \ (p)->mul = m; \ (p)->div = d; \ -} +} while (0) #endif diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h index 68053fc4d9d..851d027a2f0 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7778.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h @@ -18,16 +18,26 @@ #ifndef __ASM_R8A7778_H__ #define __ASM_R8A7778_H__ +#include <linux/mmc/sh_mmcif.h> +#include <linux/mmc/sh_mobile_sdhi.h> #include <linux/sh_eth.h> +#include <linux/platform_data/usb-rcar-phy.h> extern void r8a7778_add_standard_devices(void); extern void r8a7778_add_standard_devices_dt(void); extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata); +extern void r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata); +extern void r8a7778_add_i2c_device(int id); +extern void r8a7778_add_hspi_device(int id); +extern void r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info); + +extern void r8a7778_init_late(void); extern void r8a7778_init_delay(void); extern void r8a7778_init_irq(void); extern void r8a7778_init_irq_dt(void); extern void r8a7778_clock_init(void); extern void r8a7778_init_irq_extpin(int irlm); extern void r8a7778_pinmux_init(void); +extern void r8a7778_sdhi_init(int id, struct sh_mobile_sdhi_info *info); #endif /* __ASM_R8A7778_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index 188b295938a..fc47073c7ba 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -4,6 +4,7 @@ #include <linux/sh_clk.h> #include <linux/pm_domain.h> #include <linux/sh_eth.h> +#include <linux/platform_data/usb-rcar-phy.h> struct platform_device; @@ -33,6 +34,8 @@ extern void r8a7779_add_early_devices(void); extern void r8a7779_add_standard_devices(void); extern void r8a7779_add_standard_devices_dt(void); extern void r8a7779_add_ether_device(struct sh_eth_plat_data *pdata); +extern void r8a7779_add_usb_phy_device(struct rcar_phy_platform_data *pdata); +extern void r8a7779_init_late(void); extern void r8a7779_clock_init(void); extern void r8a7779_pinmux_init(void); extern void r8a7779_pm_init(void); diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 1f36ecc322a..80c20392ad7 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -30,6 +30,12 @@ #include <linux/irqchip.h> #include <linux/serial_sci.h> #include <linux/sh_timer.h> +#include <linux/pm_runtime.h> +#include <linux/usb/phy.h> +#include <linux/usb/hcd.h> +#include <linux/usb/ehci_pdriver.h> +#include <linux/usb/ohci_pdriver.h> +#include <linux/dma-mapping.h> #include <mach/irqs.h> #include <mach/r8a7778.h> #include <mach/common.h> @@ -81,12 +87,6 @@ static struct sh_timer_config sh_tmu1_platform_data = { .clocksource_rating = 200, }; -/* Ether */ -static struct resource ether_resources[] = { - DEFINE_RES_MEM(0xfde00000, 0x400), - DEFINE_RES_IRQ(gic_iid(0x89)), -}; - #define r8a7778_register_tmu(idx) \ platform_device_register_resndata( \ &platform_bus, "sh_tmu", idx, \ @@ -95,6 +95,113 @@ static struct resource ether_resources[] = { &sh_tmu##idx##_platform_data, \ sizeof(sh_tmu##idx##_platform_data)) +/* USB PHY */ +static struct resource usb_phy_resources[] __initdata = { + DEFINE_RES_MEM(0xffe70800, 0x100), + DEFINE_RES_MEM(0xffe76000, 0x100), +}; + +void __init r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata) +{ + platform_device_register_resndata(&platform_bus, "rcar_usb_phy", -1, + usb_phy_resources, + ARRAY_SIZE(usb_phy_resources), + pdata, sizeof(*pdata)); +} + +/* USB */ +static struct usb_phy *phy; + +static int usb_power_on(struct platform_device *pdev) +{ + if (IS_ERR(phy)) + return PTR_ERR(phy); + + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + + usb_phy_init(phy); + + return 0; +} + +static void usb_power_off(struct platform_device *pdev) +{ + if (IS_ERR(phy)) + return; + + usb_phy_shutdown(phy); + + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); +} + +static int ehci_init_internal_buffer(struct usb_hcd *hcd) +{ + /* + * Below are recommended values from the datasheet; + * see [USB :: Setting of EHCI Internal Buffer]. + */ + /* EHCI IP internal buffer setting */ + iowrite32(0x00ff0040, hcd->regs + 0x0094); + /* EHCI IP internal buffer enable */ + iowrite32(0x00000001, hcd->regs + 0x009C); + + return 0; +} + +static struct usb_ehci_pdata ehci_pdata __initdata = { + .power_on = usb_power_on, + .power_off = usb_power_off, + .power_suspend = usb_power_off, + .pre_setup = ehci_init_internal_buffer, +}; + +static struct resource ehci_resources[] __initdata = { + DEFINE_RES_MEM(0xffe70000, 0x400), + DEFINE_RES_IRQ(gic_iid(0x4c)), +}; + +static struct usb_ohci_pdata ohci_pdata __initdata = { + .power_on = usb_power_on, + .power_off = usb_power_off, + .power_suspend = usb_power_off, +}; + +static struct resource ohci_resources[] __initdata = { + DEFINE_RES_MEM(0xffe70400, 0x400), + DEFINE_RES_IRQ(gic_iid(0x4c)), +}; + +#define USB_PLATFORM_INFO(hci) \ +static struct platform_device_info hci##_info __initdata = { \ + .parent = &platform_bus, \ + .name = #hci "-platform", \ + .id = -1, \ + .res = hci##_resources, \ + .num_res = ARRAY_SIZE(hci##_resources), \ + .data = &hci##_pdata, \ + .size_data = sizeof(hci##_pdata), \ + .dma_mask = DMA_BIT_MASK(32), \ +} + +USB_PLATFORM_INFO(ehci); +USB_PLATFORM_INFO(ohci); + +/* Ether */ +static struct resource ether_resources[] = { + DEFINE_RES_MEM(0xfde00000, 0x400), + DEFINE_RES_IRQ(gic_iid(0x89)), +}; + +void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata) +{ + platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1, + ether_resources, + ARRAY_SIZE(ether_resources), + pdata, sizeof(*pdata)); +} + /* PFC/GPIO */ static struct resource pfc_resources[] = { DEFINE_RES_MEM(0xfffc0000, 0x118), @@ -139,6 +246,91 @@ void __init r8a7778_pinmux_init(void) r8a7778_register_gpio(2); r8a7778_register_gpio(3); r8a7778_register_gpio(4); +}; + +/* SDHI */ +static struct resource sdhi_resources[] = { + /* SDHI0 */ + DEFINE_RES_MEM(0xFFE4C000, 0x100), + DEFINE_RES_IRQ(gic_iid(0x77)), + /* SDHI1 */ + DEFINE_RES_MEM(0xFFE4D000, 0x100), + DEFINE_RES_IRQ(gic_iid(0x78)), + /* SDHI2 */ + DEFINE_RES_MEM(0xFFE4F000, 0x100), + DEFINE_RES_IRQ(gic_iid(0x76)), +}; + +void __init r8a7778_sdhi_init(int id, + struct sh_mobile_sdhi_info *info) +{ + BUG_ON(id < 0 || id > 2); + + platform_device_register_resndata( + &platform_bus, "sh_mobile_sdhi", id, + sdhi_resources + (2 * id), 2, + info, sizeof(*info)); +} + +/* I2C */ +static struct resource i2c_resources[] __initdata = { + /* I2C0 */ + DEFINE_RES_MEM(0xffc70000, 0x1000), + DEFINE_RES_IRQ(gic_iid(0x63)), + /* I2C1 */ + DEFINE_RES_MEM(0xffc71000, 0x1000), + DEFINE_RES_IRQ(gic_iid(0x6e)), + /* I2C2 */ + DEFINE_RES_MEM(0xffc72000, 0x1000), + DEFINE_RES_IRQ(gic_iid(0x6c)), + /* I2C3 */ + DEFINE_RES_MEM(0xffc73000, 0x1000), + DEFINE_RES_IRQ(gic_iid(0x6d)), +}; + +void __init r8a7778_add_i2c_device(int id) +{ + BUG_ON(id < 0 || id > 3); + + platform_device_register_simple( + "i2c-rcar", id, + i2c_resources + (2 * id), 2); +} + +/* HSPI */ +static struct resource hspi_resources[] __initdata = { + /* HSPI0 */ + DEFINE_RES_MEM(0xfffc7000, 0x18), + DEFINE_RES_IRQ(gic_iid(0x5f)), + /* HSPI1 */ + DEFINE_RES_MEM(0xfffc8000, 0x18), + DEFINE_RES_IRQ(gic_iid(0x74)), + /* HSPI2 */ + DEFINE_RES_MEM(0xfffc6000, 0x18), + DEFINE_RES_IRQ(gic_iid(0x75)), +}; + +void __init r8a7778_add_hspi_device(int id) +{ + BUG_ON(id < 0 || id > 2); + + platform_device_register_simple( + "sh-hspi", id, + hspi_resources + (2 * id), 2); +} + +/* MMC */ +static struct resource mmc_resources[] __initdata = { + DEFINE_RES_MEM(0xffe4e000, 0x100), + DEFINE_RES_IRQ(gic_iid(0x5d)), +}; + +void __init r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info) +{ + platform_device_register_resndata( + &platform_bus, "sh_mmcif", -1, + mmc_resources, ARRAY_SIZE(mmc_resources), + info, sizeof(*info)); } void __init r8a7778_add_standard_devices(void) @@ -165,12 +357,12 @@ void __init r8a7778_add_standard_devices(void) r8a7778_register_tmu(1); } -void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata) +void __init r8a7778_init_late(void) { - platform_device_register_resndata(&platform_bus, "sh_eth", -1, - ether_resources, - ARRAY_SIZE(ether_resources), - pdata, sizeof(*pdata)); + phy = usb_get_phy(USB_PHY_TYPE_USB2); + + platform_device_register_full(&ehci_info); + platform_device_register_full(&ohci_info); } static struct renesas_intc_irqpin_config irqpin_platform_data = { @@ -286,6 +478,7 @@ DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") .init_machine = r8a7778_add_standard_devices_dt, .init_time = shmobile_timer_init, .dt_compat = r8a7778_compat_dt, + .init_late = r8a7778_init_late, MACHINE_END #endif /* CONFIG_USE_OF */ diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index dbb13f289e7..398687761f5 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -32,6 +32,11 @@ #include <linux/sh_intc.h> #include <linux/sh_timer.h> #include <linux/dma-mapping.h> +#include <linux/usb/otg.h> +#include <linux/usb/hcd.h> +#include <linux/usb/ehci_pdriver.h> +#include <linux/usb/ohci_pdriver.h> +#include <linux/pm_runtime.h> #include <mach/hardware.h> #include <mach/irqs.h> #include <mach/r8a7779.h> @@ -383,6 +388,165 @@ static struct platform_device sata_device = { }, }; +/* USB PHY */ +static struct resource usb_phy_resources[] __initdata = { + [0] = { + .start = 0xffe70800, + .end = 0xffe70900 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +/* USB */ +static struct usb_phy *phy; + +static int usb_power_on(struct platform_device *pdev) +{ + if (IS_ERR(phy)) + return PTR_ERR(phy); + + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + + usb_phy_init(phy); + + return 0; +} + +static void usb_power_off(struct platform_device *pdev) +{ + if (IS_ERR(phy)) + return; + + usb_phy_shutdown(phy); + + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); +} + +static int ehci_init_internal_buffer(struct usb_hcd *hcd) +{ + /* + * Below are recommended values from the datasheet; + * see [USB :: Setting of EHCI Internal Buffer]. + */ + /* EHCI IP internal buffer setting */ + iowrite32(0x00ff0040, hcd->regs + 0x0094); + /* EHCI IP internal buffer enable */ + iowrite32(0x00000001, hcd->regs + 0x009C); + + return 0; +} + +static struct usb_ehci_pdata ehcix_pdata = { + .power_on = usb_power_on, + .power_off = usb_power_off, + .power_suspend = usb_power_off, + .pre_setup = ehci_init_internal_buffer, +}; + +static struct resource ehci0_resources[] = { + [0] = { + .start = 0xffe70000, + .end = 0xffe70400 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_iid(0x4c), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ehci0_device = { + .name = "ehci-platform", + .id = 0, + .dev = { + .dma_mask = &ehci0_device.dev.coherent_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ehcix_pdata, + }, + .num_resources = ARRAY_SIZE(ehci0_resources), + .resource = ehci0_resources, +}; + +static struct resource ehci1_resources[] = { + [0] = { + .start = 0xfff70000, + .end = 0xfff70400 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_iid(0x4d), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ehci1_device = { + .name = "ehci-platform", + .id = 1, + .dev = { + .dma_mask = &ehci1_device.dev.coherent_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ehcix_pdata, + }, + .num_resources = ARRAY_SIZE(ehci1_resources), + .resource = ehci1_resources, +}; + +static struct usb_ohci_pdata ohcix_pdata = { + .power_on = usb_power_on, + .power_off = usb_power_off, + .power_suspend = usb_power_off, +}; + +static struct resource ohci0_resources[] = { + [0] = { + .start = 0xffe70400, + .end = 0xffe70800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_iid(0x4c), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ohci0_device = { + .name = "ohci-platform", + .id = 0, + .dev = { + .dma_mask = &ohci0_device.dev.coherent_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ohcix_pdata, + }, + .num_resources = ARRAY_SIZE(ohci0_resources), + .resource = ohci0_resources, +}; + +static struct resource ohci1_resources[] = { + [0] = { + .start = 0xfff70400, + .end = 0xfff70800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_iid(0x4d), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ohci1_device = { + .name = "ohci-platform", + .id = 1, + .dev = { + .dma_mask = &ohci1_device.dev.coherent_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ohcix_pdata, + }, + .num_resources = ARRAY_SIZE(ohci1_resources), + .resource = ohci1_resources, +}; + /* Ether */ static struct resource ether_resources[] = { { @@ -406,7 +570,7 @@ static struct platform_device *r8a7779_devices_dt[] __initdata = { &tmu01_device, }; -static struct platform_device *r8a7779_late_devices[] __initdata = { +static struct platform_device *r8a7779_standard_devices[] __initdata = { &i2c0_device, &i2c1_device, &i2c2_device, @@ -426,18 +590,26 @@ void __init r8a7779_add_standard_devices(void) platform_add_devices(r8a7779_devices_dt, ARRAY_SIZE(r8a7779_devices_dt)); - platform_add_devices(r8a7779_late_devices, - ARRAY_SIZE(r8a7779_late_devices)); + platform_add_devices(r8a7779_standard_devices, + ARRAY_SIZE(r8a7779_standard_devices)); } void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata) { - platform_device_register_resndata(&platform_bus, "sh_eth", -1, + platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1, ether_resources, ARRAY_SIZE(ether_resources), pdata, sizeof(*pdata)); } +void __init r8a7779_add_usb_phy_device(struct rcar_phy_platform_data *pdata) +{ + platform_device_register_resndata(&platform_bus, "rcar_usb_phy", -1, + usb_phy_resources, + ARRAY_SIZE(usb_phy_resources), + pdata, sizeof(*pdata)); +} + /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ void __init __weak r8a7779_register_twd(void) { } @@ -470,6 +642,23 @@ void __init r8a7779_add_early_devices(void) */ } +static struct platform_device *r8a7779_late_devices[] __initdata = { + &ehci0_device, + &ehci1_device, + &ohci0_device, + &ohci1_device, +}; + +void __init r8a7779_init_late(void) +{ + /* get USB PHY */ + phy = usb_get_phy(USB_PHY_TYPE_USB2); + + shmobile_init_late(); + platform_add_devices(r8a7779_late_devices, + ARRAY_SIZE(r8a7779_late_devices)); +} + #ifdef CONFIG_USE_OF void __init r8a7779_init_delay(void) { @@ -503,6 +692,7 @@ DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") .init_irq = r8a7779_init_irq_dt, .init_machine = r8a7779_add_standard_devices_dt, .init_time = shmobile_timer_init, + .init_late = r8a7779_init_late, .dt_compat = r8a7779_compat_dt, MACHINE_END #endif /* CONFIG_USE_OF */ diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index 9696f364686..96e7ca1e4e1 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -288,12 +288,7 @@ static struct sh_timer_config tmu00_platform_data = { }; static struct resource tmu00_resources[] = { - [0] = { - .name = "TMU00", - .start = 0xfff60008, - .end = 0xfff60013, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM_NAMED(0xfff60008, 0xc, "TMU00"), [1] = { .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */ .flags = IORESOURCE_IRQ, @@ -318,12 +313,7 @@ static struct sh_timer_config tmu01_platform_data = { }; static struct resource tmu01_resources[] = { - [0] = { - .name = "TMU01", - .start = 0xfff60014, - .end = 0xfff6001f, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM_NAMED(0xfff60014, 0xc, "TMU00"), [1] = { .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */ .flags = IORESOURCE_IRQ, @@ -341,12 +331,7 @@ static struct platform_device tmu01_device = { }; static struct resource i2c0_resources[] = { - [0] = { - .name = "IIC0", - .start = 0xe6820000, - .end = 0xe6820425 - 1, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM_NAMED(0xe6820000, 0x426, "IIC0"), [1] = { .start = gic_spi(167), .end = gic_spi(170), @@ -355,12 +340,7 @@ static struct resource i2c0_resources[] = { }; static struct resource i2c1_resources[] = { - [0] = { - .name = "IIC1", - .start = 0xe6822000, - .end = 0xe6822425 - 1, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM_NAMED(0xe6822000, 0x426, "IIC1"), [1] = { .start = gic_spi(51), .end = gic_spi(54), @@ -369,12 +349,7 @@ static struct resource i2c1_resources[] = { }; static struct resource i2c2_resources[] = { - [0] = { - .name = "IIC2", - .start = 0xe6824000, - .end = 0xe6824425 - 1, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM_NAMED(0xe6824000, 0x426, "IIC2"), [1] = { .start = gic_spi(171), .end = gic_spi(174), @@ -383,12 +358,7 @@ static struct resource i2c2_resources[] = { }; static struct resource i2c3_resources[] = { - [0] = { - .name = "IIC3", - .start = 0xe6826000, - .end = 0xe6826425 - 1, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM_NAMED(0xe6826000, 0x426, "IIC3"), [1] = { .start = gic_spi(183), .end = gic_spi(186), @@ -397,12 +367,7 @@ static struct resource i2c3_resources[] = { }; static struct resource i2c4_resources[] = { - [0] = { - .name = "IIC4", - .start = 0xe6828000, - .end = 0xe6828425 - 1, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM_NAMED(0xe6828000, 0x426, "IIC4"), [1] = { .start = gic_spi(187), .end = gic_spi(190), @@ -623,12 +588,7 @@ static struct sh_dmae_pdata sh73a0_dmae_platform_data = { }; static struct resource sh73a0_dmae_resources[] = { - { - /* Registers including DMAOR and channels including DMARSx */ - .start = 0xfe000020, - .end = 0xfe008a00 - 1, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(0xfe000020, 0x89e0), { .name = "error_irq", .start = gic_spi(129), @@ -727,18 +687,10 @@ static struct sh_dmae_pdata sh73a0_mpdma_platform_data = { /* Resource order important! */ static struct resource sh73a0_mpdma_resources[] = { - { - /* Channel registers and DMAOR */ - .start = 0xec618020, - .end = 0xec61828f, - .flags = IORESOURCE_MEM, - }, - { - /* DMARSx */ - .start = 0xec619000, - .end = 0xec61900b, - .flags = IORESOURCE_MEM, - }, + /* Channel registers and DMAOR */ + DEFINE_RES_MEM(0xec618020, 0x270), + /* DMARSx */ + DEFINE_RES_MEM(0xec619000, 0xc), { .name = "error_irq", .start = gic_spi(181), @@ -785,12 +737,7 @@ static struct platform_device pmu_device = { /* an IPMMU module for ICB */ static struct resource ipmmu_resources[] = { - [0] = { - .name = "IPMMU", - .start = 0xfe951000, - .end = 0xfe9510ff, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM_NAMED(0xfe951000, 0x100, "IPMMU"), }; static const char * const ipmmu_dev_names[] = { @@ -982,11 +929,17 @@ void __init sh73a0_add_standard_devices(void) ARRAY_SIZE(sh73a0_late_devices)); } +void __init sh73a0_init_delay(void) +{ + shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ +} + /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ void __init __weak sh73a0_register_twd(void) { } void __init sh73a0_earlytimer_init(void) { + sh73a0_init_delay(); sh73a0_clock_init(); shmobile_earlytimer_init(); sh73a0_register_twd(); @@ -1005,17 +958,14 @@ void __init sh73a0_add_early_devices(void) #ifdef CONFIG_USE_OF -void __init sh73a0_init_delay(void) -{ - shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ -} - static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = { {}, }; void __init sh73a0_add_standard_devices_dt(void) { + struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, }; + /* clocks are setup late during boot in the case of DT */ sh73a0_clock_init(); @@ -1023,6 +973,9 @@ void __init sh73a0_add_standard_devices_dt(void) ARRAY_SIZE(sh73a0_devices_dt)); of_platform_populate(NULL, of_default_bus_match_table, sh73a0_auxdata_lookup, NULL); + + /* Instantiate cpufreq-cpu0 */ + platform_device_register_full(&devinfo); } static const char *sh73a0_boards_compat_dt[] __initdata = { diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 566e804d403..dd86db46752 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -7,11 +7,11 @@ config ARCH_SOCFPGA select CLKDEV_LOOKUP select COMMON_CLK select CPU_V7 - select DW_APB_TIMER select DW_APB_TIMER_OF select GENERIC_CLOCKEVENTS select GPIO_PL061 if GPIOLIB select HAVE_ARM_SCU select HAVE_SMP + select MFD_SYSCON select SPARSE_IRQ select USE_OF diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 46a051359f0..8ea11b472b9 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -14,7 +14,6 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -#include <linux/dw_apb_timer.h> #include <linux/clk-provider.h> #include <linux/irqchip.h> #include <linux/of_address.h> @@ -120,7 +119,6 @@ DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA") .smp = smp_ops(socfpga_smp_ops), .map_io = socfpga_map_io, .init_irq = socfpga_init_irq, - .init_time = dw_apb_timer_init, .init_machine = socfpga_cyclone5_init, .restart = socfpga_cyclone5_restart, .dt_compat = altera_dt_match, diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index d259c782d74..5b045e302b4 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1,5 +1,6 @@ config ARCH_SUNXI bool "Allwinner A1X SOCs" if ARCH_MULTI_V7 + select ARCH_REQUIRE_GPIOLIB select CLKSRC_MMIO select CLKSRC_OF select COMMON_CLK diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 706ce35396b..a42d8743ba7 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -14,7 +14,6 @@ #include <linux/delay.h> #include <linux/kernel.h> #include <linux/init.h> -#include <linux/irqchip.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/of_platform.h> @@ -110,6 +109,7 @@ static void __init sunxi_dt_init(void) static const char * const sunxi_board_dt_compat[] = { "allwinner,sun4i-a10", + "allwinner,sun5i-a10s", "allwinner,sun5i-a13", NULL, }; @@ -117,7 +117,6 @@ static const char * const sunxi_board_dt_compat[] = { DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") .init_machine = sunxi_dt_init, .map_io = sunxi_map_io, - .init_irq = irqchip_init, .init_time = sunxi_timer_init, .dt_compat = sunxi_board_dt_compat, MACHINE_END diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index d011f0ad49c..98b184efc11 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_TEGRA_PCI) += pcie.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o +obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o endif diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 9f852c6fe5b..ec5836b1e71 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -29,6 +29,7 @@ #include "board.h" #include "common.h" +#include "cpuidle.h" #include "fuse.h" #include "iomap.h" #include "irq.h" @@ -108,5 +109,6 @@ void __init tegra_init_early(void) void __init tegra_init_late(void) { tegra_init_suspend(); + tegra_cpuidle_init(); tegra_powergate_debugfs_init(); } diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h index 5900cc44f78..32f8eb3fe34 100644 --- a/arch/arm/mach-tegra/common.h +++ b/arch/arm/mach-tegra/common.h @@ -2,3 +2,4 @@ extern struct smp_operations tegra_smp_ops; extern int tegra_cpu_kill(unsigned int cpu); extern void tegra_cpu_die(unsigned int cpu); +extern int tegra_cpu_disable(unsigned int cpu); diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index 0cdba8de8c7..706aa4215c3 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -177,7 +177,6 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu; bool entered_lp2 = false; if (tegra_pending_sgi()) @@ -193,16 +192,16 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, local_fiq_disable(); - tegra_set_cpu_in_lp2(cpu); + tegra_set_cpu_in_lp2(); cpu_pm_enter(); - if (cpu == 0) + if (dev->cpu == 0) entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index); else entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index); cpu_pm_exit(); - tegra_clear_cpu_in_lp2(cpu); + tegra_clear_cpu_in_lp2(); local_fiq_enable(); @@ -214,8 +213,5 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, int __init tegra20_cpuidle_init(void) { -#ifdef CONFIG_PM_SLEEP - tegra_tear_down_cpu = tegra20_tear_down_cpu; -#endif return cpuidle_register(&tegra_idle_driver, cpu_possible_mask); } diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c index 3cf9aca5f3e..ed2a2a7bae4 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ b/arch/arm/mach-tegra/cpuidle-tegra30.c @@ -114,16 +114,15 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu; bool entered_lp2 = false; bool last_cpu; local_fiq_disable(); - last_cpu = tegra_set_cpu_in_lp2(cpu); + last_cpu = tegra_set_cpu_in_lp2(); cpu_pm_enter(); - if (cpu == 0) { + if (dev->cpu == 0) { if (last_cpu) entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv, index); @@ -134,7 +133,7 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev, } cpu_pm_exit(); - tegra_clear_cpu_in_lp2(cpu); + tegra_clear_cpu_in_lp2(); local_fiq_enable(); @@ -146,8 +145,5 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev, int __init tegra30_cpuidle_init(void) { -#ifdef CONFIG_PM_SLEEP - tegra_tear_down_cpu = tegra30_tear_down_cpu; -#endif return cpuidle_register(&tegra_idle_driver, NULL); } diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c index 4b744c4661e..e85973cef03 100644 --- a/arch/arm/mach-tegra/cpuidle.c +++ b/arch/arm/mach-tegra/cpuidle.c @@ -27,25 +27,20 @@ #include "fuse.h" #include "cpuidle.h" -static int __init tegra_cpuidle_init(void) +void __init tegra_cpuidle_init(void) { - int ret; - switch (tegra_chip_id) { case TEGRA20: - ret = tegra20_cpuidle_init(); + if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) + tegra20_cpuidle_init(); break; case TEGRA30: - ret = tegra30_cpuidle_init(); + if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC)) + tegra30_cpuidle_init(); break; case TEGRA114: - ret = tegra114_cpuidle_init(); - break; - default: - ret = -ENODEV; + if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) + tegra114_cpuidle_init(); break; } - - return ret; } -device_initcall(tegra_cpuidle_init); diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h index d733f75d020..9ec2c1ab0fa 100644 --- a/arch/arm/mach-tegra/cpuidle.h +++ b/arch/arm/mach-tegra/cpuidle.h @@ -17,22 +17,13 @@ #ifndef __MACH_TEGRA_CPUIDLE_H #define __MACH_TEGRA_CPUIDLE_H -#ifdef CONFIG_ARCH_TEGRA_2x_SOC +#ifdef CONFIG_CPU_IDLE int tegra20_cpuidle_init(void); -#else -static inline int tegra20_cpuidle_init(void) { return -ENODEV; } -#endif - -#ifdef CONFIG_ARCH_TEGRA_3x_SOC int tegra30_cpuidle_init(void); -#else -static inline int tegra30_cpuidle_init(void) { return -ENODEV; } -#endif - -#ifdef CONFIG_ARCH_TEGRA_114_SOC int tegra114_cpuidle_init(void); +void tegra_cpuidle_init(void); #else -static inline int tegra114_cpuidle_init(void) { return -ENODEV; } +static inline void tegra_cpuidle_init(void) {} #endif #endif diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h index 67eab56699b..7a29bae799a 100644 --- a/arch/arm/mach-tegra/flowctrl.h +++ b/arch/arm/mach-tegra/flowctrl.h @@ -25,6 +25,7 @@ #define FLOW_CTRL_WAITEVENT (2 << 29) #define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29) #define FLOW_CTRL_JTAG_RESUME (1 << 28) +#define FLOW_CTRL_SCLK_RESUME (1 << 27) #define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) #define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) #define FLOW_CTRL_CPU0_CSR 0x8 diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h index aacc00d0598..def79683bef 100644 --- a/arch/arm/mach-tegra/fuse.h +++ b/arch/arm/mach-tegra/fuse.h @@ -19,16 +19,6 @@ #ifndef __MACH_TEGRA_FUSE_H #define __MACH_TEGRA_FUSE_H -enum tegra_revision { - TEGRA_REVISION_UNKNOWN = 0, - TEGRA_REVISION_A01, - TEGRA_REVISION_A02, - TEGRA_REVISION_A03, - TEGRA_REVISION_A03p, - TEGRA_REVISION_A04, - TEGRA_REVISION_MAX, -}; - #define SKU_ID_T20 8 #define SKU_ID_T25SE 20 #define SKU_ID_AP25 23 @@ -40,6 +30,17 @@ enum tegra_revision { #define TEGRA30 0x30 #define TEGRA114 0x35 +#ifndef __ASSEMBLY__ +enum tegra_revision { + TEGRA_REVISION_UNKNOWN = 0, + TEGRA_REVISION_A01, + TEGRA_REVISION_A02, + TEGRA_REVISION_A03, + TEGRA_REVISION_A03p, + TEGRA_REVISION_A04, + TEGRA_REVISION_MAX, +}; + extern int tegra_sku_id; extern int tegra_cpu_process_id; extern int tegra_core_process_id; @@ -72,5 +73,6 @@ void tegra114_init_speedo_data(void); #else static inline void tegra114_init_speedo_data(void) {} #endif +#endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c index 184914a68d7..a52c10e0a85 100644 --- a/arch/arm/mach-tegra/hotplug.c +++ b/arch/arm/mach-tegra/hotplug.c @@ -46,6 +46,17 @@ void __ref tegra_cpu_die(unsigned int cpu) BUG(); } +int tegra_cpu_disable(unsigned int cpu) +{ + switch (tegra_chip_id) { + case TEGRA20: + case TEGRA30: + return cpu == 0 ? -EPERM : 0; + default: + return 0; + } +} + void __init tegra_hotplug_init(void) { if (!IS_ENABLED(CONFIG_HOTPLUG_CPU)) @@ -55,4 +66,6 @@ void __init tegra_hotplug_init(void) tegra_hotplug_shutdown = tegra20_hotplug_shutdown; if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30) tegra_hotplug_shutdown = tegra30_hotplug_shutdown; + if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114) + tegra_hotplug_shutdown = tegra30_hotplug_shutdown; } diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index fad4226ef71..24db4ac428a 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -140,8 +140,31 @@ remove_clamps: static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle) { + int ret = 0; + cpu = cpu_logical_map(cpu); - return tegra_pmc_cpu_power_on(cpu); + + if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) { + /* + * Warm boot flow + * The flow controller in charge of the power state and + * control for each CPU. + */ + /* set SCLK as event trigger for flow controller */ + flowctrl_write_cpu_csr(cpu, 1); + flowctrl_write_cpu_halt(cpu, + FLOW_CTRL_WAITEVENT | FLOW_CTRL_SCLK_RESUME); + } else { + /* + * Cold boot flow + * The CPU is powered up by toggling PMC directly. It will + * also initial power state in flow controller. After that, + * the CPU's power state is maintained by flow controller. + */ + ret = tegra_pmc_cpu_power_on(cpu); + } + + return ret; } static int __cpuinit tegra_boot_secondary(unsigned int cpu, @@ -173,5 +196,6 @@ struct smp_operations tegra_smp_ops __initdata = { #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = tegra_cpu_kill, .cpu_die = tegra_cpu_die, + .cpu_disable = tegra_cpu_disable, #endif }; diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 45cf52c7e52..94e69bee3da 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -44,6 +44,20 @@ static DEFINE_SPINLOCK(tegra_lp2_lock); void (*tegra_tear_down_cpu)(void); +static void tegra_tear_down_cpu_init(void) +{ + switch (tegra_chip_id) { + case TEGRA20: + if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) + tegra_tear_down_cpu = tegra20_tear_down_cpu; + break; + case TEGRA30: + if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC)) + tegra_tear_down_cpu = tegra30_tear_down_cpu; + break; + } +} + /* * restore_cpu_complex * @@ -91,8 +105,9 @@ static void suspend_cpu_complex(void) flowctrl_cpu_suspend_enter(cpu); } -void tegra_clear_cpu_in_lp2(int phy_cpu_id) +void tegra_clear_cpu_in_lp2(void) { + int phy_cpu_id = cpu_logical_map(smp_processor_id()); u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; spin_lock(&tegra_lp2_lock); @@ -103,8 +118,9 @@ void tegra_clear_cpu_in_lp2(int phy_cpu_id) spin_unlock(&tegra_lp2_lock); } -bool tegra_set_cpu_in_lp2(int phy_cpu_id) +bool tegra_set_cpu_in_lp2(void) { + int phy_cpu_id = cpu_logical_map(smp_processor_id()); bool last_cpu = false; cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask; u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; @@ -192,7 +208,7 @@ static int __cpuinit tegra_suspend_enter(suspend_state_t state) suspend_cpu_complex(); switch (mode) { case TEGRA_SUSPEND_LP2: - tegra_set_cpu_in_lp2(0); + tegra_set_cpu_in_lp2(); break; default: break; @@ -202,7 +218,7 @@ static int __cpuinit tegra_suspend_enter(suspend_state_t state) switch (mode) { case TEGRA_SUSPEND_LP2: - tegra_clear_cpu_in_lp2(0); + tegra_clear_cpu_in_lp2(); break; default: break; @@ -224,6 +240,7 @@ void __init tegra_init_suspend(void) if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE) return; + tegra_tear_down_cpu_init(); tegra_pmc_suspend_init(); suspend_set_ops(&tegra_suspend_ops); diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 778a4aa7c3f..94c4b9d9077 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -28,8 +28,8 @@ extern unsigned long l2x0_saved_regs_addr; void save_cpu_arch_register(void); void restore_cpu_arch_register(void); -void tegra_clear_cpu_in_lp2(int phy_cpu_id); -bool tegra_set_cpu_in_lp2(int phy_cpu_id); +void tegra_clear_cpu_in_lp2(void); +bool tegra_set_cpu_in_lp2(void); void tegra_idle_lp2_last(void); extern void (*tegra_tear_down_cpu)(void); diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index e6de88a2ea0..39dc9e7834f 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -22,11 +22,11 @@ #include <asm/hardware/cache-l2x0.h> #include "flowctrl.h" +#include "fuse.h" #include "iomap.h" #include "reset.h" #include "sleep.h" -#define APB_MISC_GP_HIDREV 0x804 #define PMC_SCRATCH41 0x140 #define RESET_DATA(x) ((TEGRA_RESET_##x)*4) @@ -38,34 +38,40 @@ * CPU boot vector when restarting the a CPU following * an LP2 transition. Also branched to by LP0 and LP1 resume after * re-enabling sdram. + * + * r6: SoC ID */ ENTRY(tegra_resume) bl v7_invalidate_l1 cpu_id r0 + tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 + cmp r6, #TEGRA114 + beq no_cpu0_chk + cmp r0, #0 @ CPU0? THUMB( it ne ) bne cpu_resume @ no +no_cpu0_chk: -#ifdef CONFIG_ARCH_TEGRA_3x_SOC /* Are we on Tegra20? */ - mov32 r6, TEGRA_APB_MISC_BASE - ldr r0, [r6, #APB_MISC_GP_HIDREV] - and r0, r0, #0xff00 - cmp r0, #(0x20 << 8) + cmp r6, #TEGRA20 beq 1f @ Yes /* Clear the flow controller flags for this CPU. */ - mov32 r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR @ CPU0 CSR - ldr r1, [r2] + cpu_to_csr_reg r1, r0 + mov32 r2, TEGRA_FLOW_CTRL_BASE + ldr r1, [r2, r1] /* Clear event & intr flag */ orr r1, r1, \ #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG - movw r0, #0x0FFD @ enable, cluster_switch, immed, & bitmaps + movw r0, #0x3FFD @ enable, cluster_switch, immed, bitmaps + @ & ext flags for CPU power mgnt bic r1, r1, r0 str r1, [r2] 1: -#endif + check_cpu_part_num 0xc09, r8, r9 + bne not_ca9 #ifdef CONFIG_HAVE_ARM_SCU /* enable SCU */ mov32 r0, TEGRA_ARM_PERIF_BASE @@ -76,6 +82,7 @@ ENTRY(tegra_resume) /* L2 cache resume & re-enable */ l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr +not_ca9: b cpu_resume ENDPROC(tegra_resume) @@ -98,7 +105,7 @@ ENTRY(__tegra_cpu_reset_handler_start) * Register usage within the reset handler: * * Others: scratch - * R6 = SoC ID << 8 + * R6 = SoC ID * R7 = CPU present (to the OS) mask * R8 = CPU in LP1 state mask * R9 = CPU in LP2 state mask @@ -115,12 +122,10 @@ ENTRY(__tegra_cpu_reset_handler) cpsid aif, 0x13 @ SVC mode, interrupts disabled - mov32 r6, TEGRA_APB_MISC_BASE - ldr r6, [r6, #APB_MISC_GP_HIDREV] - and r6, r6, #0xff00 + tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 #ifdef CONFIG_ARCH_TEGRA_2x_SOC t20_check: - cmp r6, #(0x20 << 8) + cmp r6, #TEGRA20 bne after_t20_check t20_errata: # Tegra20 is a Cortex-A9 r1p1 @@ -136,7 +141,7 @@ after_t20_check: #endif #ifdef CONFIG_ARCH_TEGRA_3x_SOC t30_check: - cmp r6, #(0x30 << 8) + cmp r6, #TEGRA30 bne after_t30_check t30_errata: # Tegra30 is a Cortex-A9 r2p9 @@ -163,7 +168,7 @@ after_errata: #ifdef CONFIG_ARCH_TEGRA_2x_SOC /* Are we on Tegra20? */ - cmp r6, #(0x20 << 8) + cmp r6, #TEGRA20 bne 1f /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ mov32 r5, TEGRA_PMC_BASE @@ -186,11 +191,14 @@ __is_not_lp2: #ifdef CONFIG_SMP /* - * Can only be secondary boot (initial or hotplug) but CPU 0 - * cannot be here. + * Can only be secondary boot (initial or hotplug) + * CPU0 can't be here for Tegra20/30 */ + cmp r6, #TEGRA114 + beq __no_cpu0_chk cmp r10, #0 bleq __die @ CPU0 cannot be here +__no_cpu0_chk: ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)] cmp lr, #0 bleq __die @ no secondary startup handler @@ -210,10 +218,7 @@ __die: mov32 r7, TEGRA_CLK_RESET_BASE /* Are we on Tegra20? */ - mov32 r6, TEGRA_APB_MISC_BASE - ldr r0, [r6, #APB_MISC_GP_HIDREV] - and r0, r0, #0xff00 - cmp r0, #(0x20 << 8) + cmp r6, #TEGRA20 bne 1f #ifdef CONFIG_ARCH_TEGRA_2x_SOC diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index d29dfcce948..ada8821b48b 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -19,6 +19,7 @@ #include <asm/assembler.h> #include <asm/asm-offsets.h> +#include "fuse.h" #include "sleep.h" #include "flowctrl.h" @@ -43,14 +44,19 @@ ENDPROC(tegra30_hotplug_shutdown) * * Puts the current CPU in wait-for-event mode on the flow controller * and powergates it -- flags (in R0) indicate the request type. - * Must never be called for CPU 0. * - * corrupts r0-r4, r12 + * r10 = SoC ID + * corrupts r0-r4, r10-r12 */ ENTRY(tegra30_cpu_shutdown) cpu_id r3 + tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10 + cmp r10, #TEGRA30 + bne _no_cpu0_chk @ It's not Tegra30 + cmp r3, #0 moveq pc, lr @ Must never be called for CPU 0 +_no_cpu0_chk: ldr r12, =TEGRA_FLOW_CTRL_VIRT cpu_to_csr_reg r1, r3 @@ -65,7 +71,9 @@ ENTRY(tegra30_cpu_shutdown) movw r12, \ FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \ FLOW_CTRL_CSR_ENABLE - mov r4, #(1 << 4) + cmp r10, #TEGRA30 + moveq r4, #(1 << 4) @ wfe bitmap + movne r4, #(1 << 8) @ wfi bitmap ARM( orr r12, r12, r4, lsl r3 ) THUMB( lsl r4, r4, r3 ) THUMB( orr r12, r12, r4 ) @@ -79,9 +87,20 @@ delay_1: cpsid a @ disable imprecise aborts. ldr r3, [r1] @ read CSR str r3, [r1] @ clear CSR + tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN + beq flow_ctrl_setting_for_lp2 + + /* flow controller set up for hotplug */ + mov r3, #FLOW_CTRL_WAITEVENT @ For hotplug + b flow_ctrl_done +flow_ctrl_setting_for_lp2: + /* flow controller set up for LP2 */ + cmp r10, #TEGRA30 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2 - movne r3, #FLOW_CTRL_WAITEVENT @ For hotplug + movne r3, #FLOW_CTRL_WAITEVENT +flow_ctrl_done: + cmp r10, #TEGRA30 str r3, [r2] ldr r0, [r2] b wfe_war @@ -89,7 +108,8 @@ delay_1: __cpu_reset_again: dsb .align 5 - wfe @ CPU should be power gated here + wfeeq @ CPU should be power gated here + wfine wfe_war: b __cpu_reset_again diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 364d84523fb..9daaef26b0f 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -106,9 +106,11 @@ ENTRY(tegra_shut_off_mmu) isb #ifdef CONFIG_CACHE_L2X0 /* Disable L2 cache */ - mov32 r4, TEGRA_ARM_PERIF_BASE + 0x3000 - mov r5, #0 - str r5, [r4, #L2X0_CTRL] + check_cpu_part_num 0xc09, r9, r10 + movweq r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000) + movteq r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000) + moveq r5, #0 + streq r5, [r4, #L2X0_CTRL] #endif mov pc, r0 ENDPROC(tegra_shut_off_mmu) diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 2080fb12ce2..98b7da698f2 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -25,6 +25,8 @@ + IO_PPSB_VIRT) #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \ + IO_PPSB_VIRT) +#define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \ + + IO_APB_VIRT) #define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT) /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */ @@ -70,19 +72,40 @@ movt \reg, #:upper16:\val .endm +/* Marco to check CPU part num */ +.macro check_cpu_part_num part_num, tmp1, tmp2 + mrc p15, 0, \tmp1, c0, c0, 0 + ubfx \tmp1, \tmp1, #4, #12 + mov32 \tmp2, \part_num + cmp \tmp1, \tmp2 +.endm + /* Macro to exit SMP coherency. */ .macro exit_smp, tmp1, tmp2 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR isb - cpu_id \tmp1 - mov \tmp1, \tmp1, lsl #2 - mov \tmp2, #0xf - mov \tmp2, \tmp2, lsl \tmp1 - mov32 \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC - str \tmp2, [\tmp1] @ invalidate SCU tags for CPU +#ifdef CONFIG_HAVE_ARM_SCU + check_cpu_part_num 0xc09, \tmp1, \tmp2 + mrceq p15, 0, \tmp1, c0, c0, 5 + andeq \tmp1, \tmp1, #0xF + moveq \tmp1, \tmp1, lsl #2 + moveq \tmp2, #0xf + moveq \tmp2, \tmp2, lsl \tmp1 + ldreq \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC) + streq \tmp2, [\tmp1] @ invalidate SCU tags for CPU dsb +#endif +.endm + +/* Macro to check Tegra revision */ +#define APB_MISC_GP_HIDREV 0x804 +.macro tegra_get_soc_id base, tmp1 + mov32 \tmp1, \base + ldr \tmp1, [\tmp1, #APB_MISC_GP_HIDREV] + and \tmp1, \tmp1, #0xff00 + mov \tmp1, \tmp1, lsr #8 .endm /* Macro to resume & re-enable L2 cache */ diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c index 31e69a019bd..3ae4a7f1a2f 100644 --- a/arch/arm/mach-tegra/tegra2_emc.c +++ b/arch/arm/mach-tegra/tegra2_emc.c @@ -183,7 +183,7 @@ static struct device_node *tegra_emc_ramcode_devnode(struct device_node *np) u32 reg; for_each_child_of_node(np, iter) { - if (of_property_read_u32(np, "nvidia,ram-code", ®)) + if (of_property_read_u32(iter, "nvidia,ram-code", ®)) continue; if (reg == tegra_bct_strapping) return of_node_get(iter); diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig index 1f597647d43..a85adcd0088 100644 --- a/arch/arm/mach-u300/Kconfig +++ b/arch/arm/mach-u300/Kconfig @@ -1,24 +1,46 @@ -if ARCH_U300 - menu "ST-Ericsson AB U300/U335 Platform" comment "ST-Ericsson Mobile Platform Products" -config MACH_U300 - bool "U300" +config ARCH_U300 + bool "ST-Ericsson U300 Series" if ARCH_MULTI_V5 + depends on MMU + select ARCH_REQUIRE_GPIOLIB + select ARM_AMBA + select ARM_PATCH_PHYS_VIRT + select ARM_VIC + select CLKDEV_LOOKUP + select CLKSRC_MMIO + select CLKSRC_OF + select COMMON_CLK + select CPU_ARM926T + select GENERIC_CLOCKEVENTS + select HAVE_TCM select PINCTRL select PINCTRL_COH901 select PINCTRL_U300 + select SPARSE_IRQ + select MFD_SYSCON + select USE_OF + help + Support for ST-Ericsson U300 series mobile platforms. comment "ST-Ericsson U300/U335 Feature Selections" +config MACH_U300 + depends on ARCH_U300 + bool "U300" + default y + config U300_DEBUG + depends on ARCH_U300 bool "Debug support for U300" depends on PM help Debug support for U300 in sysfs, procfs etc. config MACH_U300_SPIDUMMY + depends on ARCH_U300 bool "SSP/SPI dummy chip" select SPI select SPI_MASTER @@ -31,5 +53,3 @@ config MACH_U300_SPIDUMMY SPI framework and ARM PL022 support. endmenu - -endif diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile index 5a86c58da39..0f362b64fb8 100644 --- a/arch/arm/mach-u300/Makefile +++ b/arch/arm/mach-u300/Makefile @@ -7,7 +7,5 @@ obj-m := obj-n := obj- := -obj-$(CONFIG_SPI_PL022) += spi.o obj-$(CONFIG_MACH_U300_SPIDUMMY) += dummyspichip.o -obj-$(CONFIG_I2C_STU300) += i2c.o obj-$(CONFIG_REGULATOR_AB3100) += regulator.o diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index a683d17b2ce..4f7ac2a1145 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -9,46 +9,157 @@ * Author: Linus Walleij <linus.walleij@stericsson.com> */ #include <linux/kernel.h> -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/interrupt.h> -#include <linux/bitops.h> -#include <linux/device.h> -#include <linux/mm.h> -#include <linux/termios.h> -#include <linux/dmaengine.h> -#include <linux/amba/bus.h> -#include <linux/amba/mmci.h> -#include <linux/amba/serial.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/mtd/nand.h> -#include <linux/mtd/fsmc.h> #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf-generic.h> -#include <linux/dma-mapping.h> #include <linux/platform_data/clk-u300.h> -#include <linux/platform_data/pinctrl-coh901.h> -#include <linux/platform_data/dma-coh901318.h> -#include <linux/irqchip/arm-vic.h> +#include <linux/irqchip.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> +#include <linux/clocksource.h> +#include <linux/clk.h> -#include <asm/types.h> -#include <asm/setup.h> -#include <asm/memory.h> #include <asm/mach/map.h> -#include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <mach/hardware.h> -#include <mach/syscon.h> -#include <mach/irqs.h> +/* + * These are the large blocks of memory allocated for I/O. + * the defines are used for setting up the I/O memory mapping. + */ + +/* NAND Flash CS0 */ +#define U300_NAND_CS0_PHYS_BASE 0x80000000 +/* NFIF */ +#define U300_NAND_IF_PHYS_BASE 0x9f800000 +/* ALE, CLE offset for FSMC NAND */ +#define PLAT_NAND_CLE (1 << 16) +#define PLAT_NAND_ALE (1 << 17) +/* AHB Peripherals */ +#define U300_AHB_PER_PHYS_BASE 0xa0000000 +#define U300_AHB_PER_VIRT_BASE 0xff010000 +/* FAST Peripherals */ +#define U300_FAST_PER_PHYS_BASE 0xc0000000 +#define U300_FAST_PER_VIRT_BASE 0xff020000 +/* SLOW Peripherals */ +#define U300_SLOW_PER_PHYS_BASE 0xc0010000 +#define U300_SLOW_PER_VIRT_BASE 0xff000000 +/* Boot ROM */ +#define U300_BOOTROM_PHYS_BASE 0xffff0000 +#define U300_BOOTROM_VIRT_BASE 0xffff0000 +/* SEMI config base */ +#define U300_SEMI_CONFIG_BASE 0x2FFE0000 + +/* + * AHB peripherals + */ + +/* AHB Peripherals Bridge Controller */ +#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000) +/* Vectored Interrupt Controller 0, servicing 32 interrupts */ +#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000) +#define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000) +/* Vectored Interrupt Controller 1, servicing 32 interrupts */ +#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000) +#define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000) +/* Memory Stick Pro (MSPRO) controller */ +#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000) +/* EMIF Configuration Area */ +#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000) + +/* + * FAST peripherals + */ + +/* FAST bridge control */ +#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000) +/* MMC/SD controller */ +#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000) +/* PCM I2S0 controller */ +#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000) +/* PCM I2S1 controller */ +#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000) +/* I2C0 controller */ +#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000) +/* I2C1 controller */ +#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000) +/* SPI controller */ +#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000) +/* Fast UART1 on U335 only */ +#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000) + +/* + * SLOW peripherals + */ + +/* SLOW bridge control */ +#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE) +/* SYSCON */ +#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000) +#define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000) +/* Watchdog */ +#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000) +/* UART0 */ +#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000) +/* APP side special timer */ +#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000) +#define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000) +/* Keypad */ +#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000) +/* GPIO */ +#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000) +/* RTC */ +#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000) +/* Bus tracer */ +#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000) +/* Event handler (hardware queue) */ +#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000) +/* Genric Timer */ +#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000) +/* PPM */ +#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000) + +/* + * REST peripherals + */ + +/* ISP (image signal processor) */ +#define U300_ISP_BASE (0xA0008000) +/* DMA Controller base */ +#define U300_DMAC_BASE (0xC0020000) +/* MSL Base */ +#define U300_MSL_BASE (0xc0022000) +/* APEX Base */ +#define U300_APEX_BASE (0xc0030000) +/* Video Encoder Base */ +#define U300_VIDEOENC_BASE (0xc0080000) +/* XGAM Base */ +#define U300_XGAM_BASE (0xd0000000) + +/* + * SYSCON addresses applicable to the core machine. + */ -#include "timer.h" -#include "spi.h" -#include "i2c.h" -#include "u300-gpio.h" +/* Chip ID register 16bit (R/-) */ +#define U300_SYSCON_CIDR (0x400) +/* SMCR */ +#define U300_SYSCON_SMCR (0x4d0) +#define U300_SYSCON_SMCR_FIELD_MASK (0x000e) +#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008) +#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004) +#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002) +/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */ +#define U300_SYSCON_CSDR (0x4f0) +#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001) +/* PRINT_CONTROL Print Control 16bit (R/-) */ +#define U300_SYSCON_PCR (0x4f8) +#define U300_SYSCON_PCR_SERV_IND (0x0001) +/* BOOT_CONTROL 16bit (R/-) */ +#define U300_SYSCON_BCR (0x4fc) +#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400) +#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200) +#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC) +#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003) + +static void __iomem *syscon_base; /* * Static I/O mappings that are needed for booting the U300 platforms. The @@ -82,365 +193,6 @@ static void __init u300_map_io(void) iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc)); } -/* - * Declaration of devices found on the U300 board and - * their respective memory locations. - */ - -static struct amba_pl011_data uart0_plat_data = { -#ifdef CONFIG_COH901318 - .dma_filter = coh901318_filter_id, - .dma_rx_param = (void *) U300_DMA_UART0_RX, - .dma_tx_param = (void *) U300_DMA_UART0_TX, -#endif -}; - -/* Slow device at 0x3000 offset */ -static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE, - { IRQ_U300_UART0 }, &uart0_plat_data); - -/* The U335 have an additional UART1 on the APP CPU */ -static struct amba_pl011_data uart1_plat_data = { -#ifdef CONFIG_COH901318 - .dma_filter = coh901318_filter_id, - .dma_rx_param = (void *) U300_DMA_UART1_RX, - .dma_tx_param = (void *) U300_DMA_UART1_TX, -#endif -}; - -/* Fast device at 0x7000 offset */ -static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE, - { IRQ_U300_UART1 }, &uart1_plat_data); - -/* AHB device at 0x4000 offset */ -static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL); - -/* Fast device at 0x6000 offset */ -static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE, - { IRQ_U300_SPI }, NULL); - -/* Fast device at 0x1000 offset */ -#define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 } - -static struct mmci_platform_data mmcsd_platform_data = { - /* - * Do not set ocr_mask or voltage translation function, - * we have a regulator we can control instead. - */ - .f_max = 24000000, - .gpio_wp = -1, - .gpio_cd = U300_GPIO_PIN_MMC_CD, - .cd_invert = true, - .capabilities = MMC_CAP_MMC_HIGHSPEED | - MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, -#ifdef CONFIG_COH901318 - .dma_filter = coh901318_filter_id, - .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX, - /* Don't specify a TX channel, this RX channel is bidirectional */ -#endif -}; - -static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE, - U300_MMCSD_IRQS, &mmcsd_platform_data); - -/* - * The order of device declaration may be important, since some devices - * have dependencies on other devices being initialized first. - */ -static struct amba_device *amba_devs[] __initdata = { - &uart0_device, - &uart1_device, - &pl022_device, - &pl172_device, - &mmcsd_device, -}; - -/* Here follows a list of all hw resources that the platform devices - * allocate. Note, clock dependencies are not included - */ - -static struct resource gpio_resources[] = { - { - .start = U300_GPIO_BASE, - .end = (U300_GPIO_BASE + SZ_4K - 1), - .flags = IORESOURCE_MEM, - }, - { - .name = "gpio0", - .start = IRQ_U300_GPIO_PORT0, - .end = IRQ_U300_GPIO_PORT0, - .flags = IORESOURCE_IRQ, - }, - { - .name = "gpio1", - .start = IRQ_U300_GPIO_PORT1, - .end = IRQ_U300_GPIO_PORT1, - .flags = IORESOURCE_IRQ, - }, - { - .name = "gpio2", - .start = IRQ_U300_GPIO_PORT2, - .end = IRQ_U300_GPIO_PORT2, - .flags = IORESOURCE_IRQ, - }, - { - .name = "gpio3", - .start = IRQ_U300_GPIO_PORT3, - .end = IRQ_U300_GPIO_PORT3, - .flags = IORESOURCE_IRQ, - }, - { - .name = "gpio4", - .start = IRQ_U300_GPIO_PORT4, - .end = IRQ_U300_GPIO_PORT4, - .flags = IORESOURCE_IRQ, - }, - { - .name = "gpio5", - .start = IRQ_U300_GPIO_PORT5, - .end = IRQ_U300_GPIO_PORT5, - .flags = IORESOURCE_IRQ, - }, - { - .name = "gpio6", - .start = IRQ_U300_GPIO_PORT6, - .end = IRQ_U300_GPIO_PORT6, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource keypad_resources[] = { - { - .start = U300_KEYPAD_BASE, - .end = U300_KEYPAD_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "coh901461-press", - .start = IRQ_U300_KEYPAD_KEYBF, - .end = IRQ_U300_KEYPAD_KEYBF, - .flags = IORESOURCE_IRQ, - }, - { - .name = "coh901461-release", - .start = IRQ_U300_KEYPAD_KEYBR, - .end = IRQ_U300_KEYPAD_KEYBR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource rtc_resources[] = { - { - .start = U300_RTC_BASE, - .end = U300_RTC_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_U300_RTC, - .end = IRQ_U300_RTC, - .flags = IORESOURCE_IRQ, - }, -}; - -/* - * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2) - * but these are not yet used by the driver. - */ -static struct resource fsmc_resources[] = { - { - .name = "nand_addr", - .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE, - .end = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "nand_cmd", - .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE, - .end = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "nand_data", - .start = U300_NAND_CS0_PHYS_BASE, - .end = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "fsmc_regs", - .start = U300_NAND_IF_PHYS_BASE, - .end = U300_NAND_IF_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource i2c0_resources[] = { - { - .start = U300_I2C0_BASE, - .end = U300_I2C0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_U300_I2C0, - .end = IRQ_U300_I2C0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource i2c1_resources[] = { - { - .start = U300_I2C1_BASE, - .end = U300_I2C1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_U300_I2C1, - .end = IRQ_U300_I2C1, - .flags = IORESOURCE_IRQ, - }, - -}; - -static struct resource wdog_resources[] = { - { - .start = U300_WDOG_BASE, - .end = U300_WDOG_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_U300_WDOG, - .end = IRQ_U300_WDOG, - .flags = IORESOURCE_IRQ, - } -}; - -static struct resource dma_resource[] = { - { - .start = U300_DMAC_BASE, - .end = U300_DMAC_BASE + PAGE_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_U300_DMA, - .end = IRQ_U300_DMA, - .flags = IORESOURCE_IRQ, - } -}; - - -static struct resource pinctrl_resources[] = { - { - .start = U300_SYSCON_BASE, - .end = U300_SYSCON_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device wdog_device = { - .name = "coh901327_wdog", - .id = -1, - .num_resources = ARRAY_SIZE(wdog_resources), - .resource = wdog_resources, -}; - -static struct platform_device i2c0_device = { - .name = "stu300", - .id = 0, - .num_resources = ARRAY_SIZE(i2c0_resources), - .resource = i2c0_resources, -}; - -static struct platform_device i2c1_device = { - .name = "stu300", - .id = 1, - .num_resources = ARRAY_SIZE(i2c1_resources), - .resource = i2c1_resources, -}; - -static struct platform_device pinctrl_device = { - .name = "pinctrl-u300", - .id = -1, - .num_resources = ARRAY_SIZE(pinctrl_resources), - .resource = pinctrl_resources, -}; - -/* - * The different variants have a few different versions of the - * GPIO block, with different number of ports. - */ -static struct u300_gpio_platform u300_gpio_plat = { - .ports = 7, - .gpio_base = 0, -}; - -static struct platform_device gpio_device = { - .name = "u300-gpio", - .id = -1, - .num_resources = ARRAY_SIZE(gpio_resources), - .resource = gpio_resources, - .dev = { - .platform_data = &u300_gpio_plat, - }, -}; - -static struct platform_device keypad_device = { - .name = "keypad", - .id = -1, - .num_resources = ARRAY_SIZE(keypad_resources), - .resource = keypad_resources, -}; - -static struct platform_device rtc_device = { - .name = "rtc-coh901331", - .id = -1, - .num_resources = ARRAY_SIZE(rtc_resources), - .resource = rtc_resources, -}; - -static struct mtd_partition u300_partitions[] = { - { - .name = "bootrecords", - .offset = 0, - .size = SZ_128K, - }, - { - .name = "free", - .offset = SZ_128K, - .size = 8064 * SZ_1K, - }, - { - .name = "platform", - .offset = 8192 * SZ_1K, - .size = 253952 * SZ_1K, - }, -}; - -static struct fsmc_nand_platform_data nand_platform_data = { - .partitions = u300_partitions, - .nr_partitions = ARRAY_SIZE(u300_partitions), - .options = NAND_SKIP_BBTSCAN, - .width = FSMC_NAND_BW8, -}; - -static struct platform_device nand_device = { - .name = "fsmc-nand", - .id = -1, - .resource = fsmc_resources, - .num_resources = ARRAY_SIZE(fsmc_resources), - .dev = { - .platform_data = &nand_platform_data, - }, -}; - -static struct platform_device dma_device = { - .name = "coh901318", - .id = -1, - .resource = dma_resource, - .num_resources = ARRAY_SIZE(dma_resource), - .dev = { - .coherent_dma_mask = ~0, - }, -}; - static unsigned long pin_pullup_conf[] = { PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1), }; @@ -467,61 +219,6 @@ static struct pinctrl_map __initdata u300_pinmux_map[] = { pin_highz_conf), }; -/* - * Notice that AMBA devices are initialized before platform devices. - * - */ -static struct platform_device *platform_devs[] __initdata = { - &dma_device, - &i2c0_device, - &i2c1_device, - &keypad_device, - &rtc_device, - &pinctrl_device, - &gpio_device, - &nand_device, - &wdog_device, -}; - -/* - * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected - * together so some interrupts are connected to the first one and some - * to the second one. - */ -static void __init u300_init_irq(void) -{ - u32 mask[2] = {0, 0}; - struct clk *clk; - int i; - - /* initialize clocking early, we want to clock the INTCON */ - u300_clk_init(U300_SYSCON_VBASE); - - /* Bootstrap EMIF and SEMI clocks */ - clk = clk_get_sys("pl172", NULL); - BUG_ON(IS_ERR(clk)); - clk_prepare_enable(clk); - clk = clk_get_sys("semi", NULL); - BUG_ON(IS_ERR(clk)); - clk_prepare_enable(clk); - - /* Clock the interrupt controller */ - clk = clk_get_sys("intcon", NULL); - BUG_ON(IS_ERR(clk)); - clk_prepare_enable(clk); - - for (i = 0; i < U300_VIC_IRQS_END; i++) - set_bit(i, (unsigned long *) &mask[0]); - vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START, - mask[0], mask[0]); - vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START, - mask[1], mask[1]); -} - - -/* - * U300 platforms peripheral handling - */ struct db_chip { u16 chipid; const char *name; @@ -578,7 +275,7 @@ static void __init u300_init_check_chip(void) const char unknown[] = "UNKNOWN"; /* Read out and print chip ID */ - val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR); + val = readw(syscon_base + U300_SYSCON_CIDR); /* This is in funky bigendian order... */ val = (val & 0xFFU) << 8 | (val >> 8); chip = db_chips; @@ -600,74 +297,6 @@ static void __init u300_init_check_chip(void) } } -/* - * Some devices and their resources require reserved physical memory from - * the end of the available RAM. This function traverses the list of devices - * and assigns actual addresses to these. - */ -static void __init u300_assign_physmem(void) -{ - unsigned long curr_start = __pa(high_memory); - int i, j; - - for (i = 0; i < ARRAY_SIZE(platform_devs); i++) { - for (j = 0; j < platform_devs[i]->num_resources; j++) { - struct resource *const res = - &platform_devs[i]->resource[j]; - - if (IORESOURCE_MEM == res->flags && - 0 == res->start) { - res->start = curr_start; - res->end += curr_start; - curr_start += resource_size(res); - - printk(KERN_INFO "core.c: Mapping RAM " \ - "%#x-%#x to device %s:%s\n", - res->start, res->end, - platform_devs[i]->name, res->name); - } - } - } -} - -static void __init u300_init_machine(void) -{ - int i; - u16 val; - - /* Check what platform we run and print some status information */ - u300_init_check_chip(); - - /* Initialize SPI device with some board specifics */ - u300_spi_init(&pl022_device); - - /* Register the AMBA devices in the AMBA bus abstraction layer */ - for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { - struct amba_device *d = amba_devs[i]; - amba_device_register(d, &iomem_resource); - } - - u300_assign_physmem(); - - /* Initialize pinmuxing */ - pinctrl_register_mappings(u300_pinmux_map, - ARRAY_SIZE(u300_pinmux_map)); - - /* Register subdevices on the I2C buses */ - u300_i2c_register_board_devices(); - - /* Register the platform devices */ - platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); - - /* Register subdevices on the SPI bus */ - u300_spi_register_board_devices(); - - /* Enable SEMI self refresh */ - val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) | - U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE; - writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR); -} - /* Forward declare this function from the watchdog */ void coh901327_watchdog_reset(void); @@ -688,13 +317,99 @@ static void u300_restart(char mode, const char *cmd) while (1); } -MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board") - /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */ - .atag_offset = 0x100, +/* These are mostly to get the right device names for the clock lookups */ +static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE, + "pinctrl-u300", NULL), + OF_DEV_AUXDATA("stericsson,gpio-coh901", U300_GPIO_BASE, + "u300-gpio", NULL), + OF_DEV_AUXDATA("stericsson,coh901327", U300_WDOG_BASE, + "coh901327_wdog", NULL), + OF_DEV_AUXDATA("stericsson,coh901331", U300_RTC_BASE, + "rtc-coh901331", NULL), + OF_DEV_AUXDATA("stericsson,coh901318", U300_DMAC_BASE, + "coh901318", NULL), + OF_DEV_AUXDATA("stericsson,fsmc-nand", U300_NAND_IF_PHYS_BASE, + "fsmc-nand", NULL), + OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE, + "uart0", NULL), + OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE, + "uart1", NULL), + OF_DEV_AUXDATA("arm,primecell", U300_SPI_BASE, + "pl022", NULL), + OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE, + "stu300.0", NULL), + OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE, + "stu300.1", NULL), + OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE, + "mmci", NULL), + { /* sentinel */ }, +}; + +static void __init u300_init_irq_dt(void) +{ + struct device_node *syscon; + struct clk *clk; + + syscon = of_find_node_by_path("/syscon@c0011000"); + if (!syscon) { + pr_crit("could not find syscon node\n"); + return; + } + syscon_base = of_iomap(syscon, 0); + if (!syscon_base) { + pr_crit("could not remap syscon\n"); + return; + } + /* initialize clocking early, we want to clock the INTCON */ + u300_clk_init(syscon_base); + + /* Bootstrap EMIF and SEMI clocks */ + clk = clk_get_sys("pl172", NULL); + BUG_ON(IS_ERR(clk)); + clk_prepare_enable(clk); + clk = clk_get_sys("semi", NULL); + BUG_ON(IS_ERR(clk)); + clk_prepare_enable(clk); + + /* Clock the interrupt controller */ + clk = clk_get_sys("intcon", NULL); + BUG_ON(IS_ERR(clk)); + clk_prepare_enable(clk); + + irqchip_init(); +} + +static void __init u300_init_machine_dt(void) +{ + u16 val; + + /* Check what platform we run and print some status information */ + u300_init_check_chip(); + + /* Initialize pinmuxing */ + pinctrl_register_mappings(u300_pinmux_map, + ARRAY_SIZE(u300_pinmux_map)); + + of_platform_populate(NULL, of_default_bus_match_table, + u300_auxdata_lookup, NULL); + + /* Enable SEMI self refresh */ + val = readw(syscon_base + U300_SYSCON_SMCR) | + U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE; + writew(val, syscon_base + U300_SYSCON_SMCR); +} + +static const char * u300_board_compat[] = { + "stericsson,u300", + NULL, +}; + +DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)") .map_io = u300_map_io, - .nr_irqs = 0, - .init_irq = u300_init_irq, - .init_time = u300_timer_init, - .init_machine = u300_init_machine, + .init_irq = u300_init_irq_dt, + .init_time = clocksource_of_init, + .init_machine = u300_init_machine_dt, .restart = u300_restart, + .dt_compat = u300_board_compat, MACHINE_END diff --git a/arch/arm/mach-u300/dummyspichip.c b/arch/arm/mach-u300/dummyspichip.c index 2785cb67b5e..ec0283cf9a3 100644 --- a/arch/arm/mach-u300/dummyspichip.c +++ b/arch/arm/mach-u300/dummyspichip.c @@ -263,28 +263,22 @@ static int pl022_dummy_remove(struct spi_device *spi) return 0; } +static const struct of_device_id pl022_dummy_dt_match[] = { + { .compatible = "arm,pl022-dummy" }, + {}, +}; + static struct spi_driver pl022_dummy_driver = { .driver = { .name = "spi-dummy", .owner = THIS_MODULE, + .of_match_table = pl022_dummy_dt_match, }, .probe = pl022_dummy_probe, .remove = pl022_dummy_remove, }; -static int __init pl022_init_dummy(void) -{ - return spi_register_driver(&pl022_dummy_driver); -} - -static void __exit pl022_exit_dummy(void) -{ - spi_unregister_driver(&pl022_dummy_driver); -} - -module_init(pl022_init_dummy); -module_exit(pl022_exit_dummy); - +module_spi_driver(pl022_dummy_driver); MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); MODULE_DESCRIPTION("PL022 SSP/SPI DUMMY Linux driver"); MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c deleted file mode 100644 index 96800aa1316..00000000000 --- a/arch/arm/mach-u300/i2c.c +++ /dev/null @@ -1,285 +0,0 @@ -/* - * arch/arm/mach-u300/i2c.c - * - * Copyright (C) 2009-2012 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * - * Register board i2c devices - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ -#include <linux/kernel.h> -#include <linux/i2c.h> -#include <linux/mfd/ab3100.h> -#include <linux/regulator/machine.h> -#include <linux/amba/bus.h> -#include <mach/irqs.h> - -/* - * Initial settings of ab3100 registers. - * Common for below LDO regulator settings are that - * bit 7-5 controls voltage. Bit 4 turns regulator ON(1) or OFF(0). - * Bit 3-2 controls sleep enable and bit 1-0 controls sleep mode. - */ - -/* LDO_A 0x16: 2.75V, ON, SLEEP_A, SLEEP OFF GND */ -#define LDO_A_SETTING 0x16 -/* LDO_C 0x10: 2.65V, ON, SLEEP_A or B, SLEEP full power */ -#define LDO_C_SETTING 0x10 -/* LDO_D 0x10: 2.65V, ON, sleep mode not used */ -#define LDO_D_SETTING 0x10 -/* LDO_E 0x10: 1.8V, ON, SLEEP_A or B, SLEEP full power */ -#define LDO_E_SETTING 0x10 -/* LDO_E SLEEP 0x00: 1.8V, not used, SLEEP_A or B, not used */ -#define LDO_E_SLEEP_SETTING 0x00 -/* LDO_F 0xD0: 2.5V, ON, SLEEP_A or B, SLEEP full power */ -#define LDO_F_SETTING 0xD0 -/* LDO_G 0x00: 2.85V, OFF, SLEEP_A or B, SLEEP full power */ -#define LDO_G_SETTING 0x00 -/* LDO_H 0x18: 2.75V, ON, SLEEP_B, SLEEP full power */ -#define LDO_H_SETTING 0x18 -/* LDO_K 0x00: 2.75V, OFF, SLEEP_A or B, SLEEP full power */ -#define LDO_K_SETTING 0x00 -/* LDO_EXT 0x00: Voltage not set, OFF, not used, not used */ -#define LDO_EXT_SETTING 0x00 -/* BUCK 0x7D: 1.2V, ON, SLEEP_A and B, SLEEP low power */ -#define BUCK_SETTING 0x7D -/* BUCK SLEEP 0xAC: 1.05V, Not used, SLEEP_A and B, Not used */ -#define BUCK_SLEEP_SETTING 0xAC - -#ifdef CONFIG_AB3100_CORE -static struct regulator_consumer_supply supply_ldo_c[] = { - { - .dev_name = "ab3100-codec", - .supply = "vaudio", /* Powers the codec */ - }, -}; - -/* - * This one needs to be a supply so we can turn it off - * in order to shut down the system. - */ -static struct regulator_consumer_supply supply_ldo_d[] = { - { - .supply = "vana15", /* Powers the SoC (CPU etc) */ - }, -}; - -static struct regulator_consumer_supply supply_ldo_g[] = { - { - .dev_name = "mmci", - .supply = "vmmc", /* Powers MMC/SD card */ - }, -}; - -static struct regulator_consumer_supply supply_ldo_h[] = { - { - .dev_name = "xgam_pdi", - .supply = "vdisp", /* Powers camera, display etc */ - }, -}; - -static struct regulator_consumer_supply supply_ldo_k[] = { - { - .dev_name = "irda", - .supply = "vir", /* Power IrDA */ - }, -}; - -/* - * This is a placeholder for whoever wish to use the - * external power. - */ -static struct regulator_consumer_supply supply_ldo_ext[] = { - { - .supply = "vext", /* External power */ - }, -}; - -/* Preset (hardware defined) voltages for these regulators */ -#define LDO_A_VOLTAGE 2750000 -#define LDO_C_VOLTAGE 2650000 -#define LDO_D_VOLTAGE 2650000 - -static struct ab3100_platform_data ab3100_plf_data = { - .reg_constraints = { - /* LDO A routing and constraints */ - { - .constraints = { - .name = "vrad", - .min_uV = LDO_A_VOLTAGE, - .max_uV = LDO_A_VOLTAGE, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .always_on = 1, - .boot_on = 1, - }, - }, - /* LDO C routing and constraints */ - { - .constraints = { - .min_uV = LDO_C_VOLTAGE, - .max_uV = LDO_C_VOLTAGE, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - }, - .num_consumer_supplies = ARRAY_SIZE(supply_ldo_c), - .consumer_supplies = supply_ldo_c, - }, - /* LDO D routing and constraints */ - { - .constraints = { - .min_uV = LDO_D_VOLTAGE, - .max_uV = LDO_D_VOLTAGE, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - /* - * Actually this is boot_on but we need - * to reference count it externally to - * be able to shut down the system. - */ - }, - .num_consumer_supplies = ARRAY_SIZE(supply_ldo_d), - .consumer_supplies = supply_ldo_d, - }, - /* LDO E routing and constraints */ - { - .constraints = { - .name = "vio", - .min_uV = 1800000, - .max_uV = 1800000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .always_on = 1, - .boot_on = 1, - }, - }, - /* LDO F routing and constraints */ - { - .constraints = { - .name = "vana25", - .min_uV = 2500000, - .max_uV = 2500000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .always_on = 1, - .boot_on = 1, - }, - }, - /* LDO G routing and constraints */ - { - .constraints = { - .min_uV = 1500000, - .max_uV = 2850000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(supply_ldo_g), - .consumer_supplies = supply_ldo_g, - }, - /* LDO H routing and constraints */ - { - .constraints = { - .min_uV = 1200000, - .max_uV = 2750000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(supply_ldo_h), - .consumer_supplies = supply_ldo_h, - }, - /* LDO K routing and constraints */ - { - .constraints = { - .min_uV = 1800000, - .max_uV = 2750000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(supply_ldo_k), - .consumer_supplies = supply_ldo_k, - }, - /* External regulator interface. No fixed voltage specified. - * If we knew the voltage of the external regulator and it - * was connected on the board, we could add the (fixed) - * voltage for it here. - */ - { - .constraints = { - .min_uV = 0, - .max_uV = 0, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(supply_ldo_ext), - .consumer_supplies = supply_ldo_ext, - }, - /* Buck converter routing and constraints */ - { - .constraints = { - .name = "vcore", - .min_uV = 1200000, - .max_uV = 1800000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE, - .always_on = 1, - .boot_on = 1, - }, - }, - }, - .reg_initvals = { - LDO_A_SETTING, - LDO_C_SETTING, - LDO_E_SETTING, - LDO_E_SLEEP_SETTING, - LDO_F_SETTING, - LDO_G_SETTING, - LDO_H_SETTING, - LDO_K_SETTING, - LDO_EXT_SETTING, - BUCK_SETTING, - BUCK_SLEEP_SETTING, - LDO_D_SETTING, - }, -}; -#endif - -static struct i2c_board_info __initdata bus0_i2c_board_info[] = { -#ifdef CONFIG_AB3100_CORE - { - .type = "ab3100", - .addr = 0x48, - .irq = IRQ_U300_IRQ0_EXT, - .platform_data = &ab3100_plf_data, - }, -#else - { }, -#endif -}; - -static struct i2c_board_info __initdata bus1_i2c_board_info[] = { - { - .type = "fwcam", - .addr = 0x10, - }, - { - .type = "fwcam", - .addr = 0x5d, - }, -}; - -void __init u300_i2c_register_board_devices(void) -{ - i2c_register_board_info(0, bus0_i2c_board_info, - ARRAY_SIZE(bus0_i2c_board_info)); - /* - * This makes the core shut down all unused regulators - * after all the initcalls have completed. - */ - regulator_has_full_constraints(); - i2c_register_board_info(1, bus1_i2c_board_info, - ARRAY_SIZE(bus1_i2c_board_info)); -} diff --git a/arch/arm/mach-u300/i2c.h b/arch/arm/mach-u300/i2c.h deleted file mode 100644 index 485c02e5c06..00000000000 --- a/arch/arm/mach-u300/i2c.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * arch/arm/mach-u300/i2c.h - * - * Copyright (C) 2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * - * Register board i2c devices - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ - -#ifndef MACH_U300_I2C_H -#define MACH_U300_I2C_H - -#ifdef CONFIG_I2C_STU300 -void __init u300_i2c_register_board_devices(void); -#else -/* Compile out this stuff if no I2C adapter is available */ -static inline void __init u300_i2c_register_board_devices(void) -{ -} -#endif - -#endif diff --git a/arch/arm/mach-u300/include/mach/hardware.h b/arch/arm/mach-u300/include/mach/hardware.h deleted file mode 100644 index b99d4ce0ac2..00000000000 --- a/arch/arm/mach-u300/include/mach/hardware.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * arch/arm/mach-u300/include/mach/hardware.h - */ -#include <asm/sizes.h> -#include <mach/u300-regs.h> diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h deleted file mode 100644 index 21d5e76a6cd..00000000000 --- a/arch/arm/mach-u300/include/mach/irqs.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * - * arch/arm/mach-u300/include/mach/irqs.h - * - * - * Copyright (C) 2006-2012 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * IRQ channel definitions for the U300 platforms. - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ - -#ifndef __MACH_IRQS_H -#define __MACH_IRQS_H - -#define IRQ_U300_INTCON0_START 32 -#define IRQ_U300_INTCON1_START 64 -/* These are on INTCON0 - 30 lines */ -#define IRQ_U300_IRQ0_EXT 32 -#define IRQ_U300_IRQ1_EXT 33 -#define IRQ_U300_DMA 34 -#define IRQ_U300_VIDEO_ENC_0 35 -#define IRQ_U300_VIDEO_ENC_1 36 -#define IRQ_U300_AAIF_RX 37 -#define IRQ_U300_AAIF_TX 38 -#define IRQ_U300_AAIF_VGPIO 39 -#define IRQ_U300_AAIF_WAKEUP 40 -#define IRQ_U300_PCM_I2S0_FRAME 41 -#define IRQ_U300_PCM_I2S0_FIFO 42 -#define IRQ_U300_PCM_I2S1_FRAME 43 -#define IRQ_U300_PCM_I2S1_FIFO 44 -#define IRQ_U300_XGAM_GAMCON 45 -#define IRQ_U300_XGAM_CDI 46 -#define IRQ_U300_XGAM_CDICON 47 -#define IRQ_U300_XGAM_PDI 49 -#define IRQ_U300_XGAM_PDICON 50 -#define IRQ_U300_XGAM_GAMEACC 51 -#define IRQ_U300_XGAM_MCIDCT 52 -#define IRQ_U300_APEX 53 -#define IRQ_U300_UART0 54 -#define IRQ_U300_SPI 55 -#define IRQ_U300_TIMER_APP_OS 56 -#define IRQ_U300_TIMER_APP_DD 57 -#define IRQ_U300_TIMER_APP_GP1 58 -#define IRQ_U300_TIMER_APP_GP2 59 -#define IRQ_U300_TIMER_OS 60 -#define IRQ_U300_TIMER_MS 61 -#define IRQ_U300_KEYPAD_KEYBF 62 -#define IRQ_U300_KEYPAD_KEYBR 63 -/* These are on INTCON1 - 32 lines */ -#define IRQ_U300_GPIO_PORT0 64 -#define IRQ_U300_GPIO_PORT1 65 -#define IRQ_U300_GPIO_PORT2 66 - -/* These are for DB3150, DB3200 and DB3350 */ -#define IRQ_U300_WDOG 67 -#define IRQ_U300_EVHIST 68 -#define IRQ_U300_MSPRO 69 -#define IRQ_U300_MMCSD_MCIINTR0 70 -#define IRQ_U300_MMCSD_MCIINTR1 71 -#define IRQ_U300_I2C0 72 -#define IRQ_U300_I2C1 73 -#define IRQ_U300_RTC 74 -#define IRQ_U300_NFIF 75 -#define IRQ_U300_NFIF2 76 - -/* The DB3350-specific interrupt lines */ -#define IRQ_U300_ISP_F0 77 -#define IRQ_U300_ISP_F1 78 -#define IRQ_U300_ISP_F2 79 -#define IRQ_U300_ISP_F3 80 -#define IRQ_U300_ISP_F4 81 -#define IRQ_U300_GPIO_PORT3 82 -#define IRQ_U300_SYSCON_PLL_LOCK 83 -#define IRQ_U300_UART1 84 -#define IRQ_U300_GPIO_PORT4 85 -#define IRQ_U300_GPIO_PORT5 86 -#define IRQ_U300_GPIO_PORT6 87 -#define U300_VIC_IRQS_END 88 - -#endif diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h deleted file mode 100644 index 10bdd0be977..00000000000 --- a/arch/arm/mach-u300/include/mach/syscon.h +++ /dev/null @@ -1,592 +0,0 @@ -/* - * - * arch/arm/mach-u300/include/mach/syscon.h - * - * - * Copyright (C) 2008-2012 ST-Ericsson AB - * - * Author: Rickard Andersson <rickard.andersson@stericsson.com> - */ - -#ifndef __MACH_SYSCON_H -#define __MACH_SYSCON_H - -/* - * All register defines for SYSCON registers that concerns individual - * block clocks and reset lines are registered here. This is because - * we don't want any other file to try to fool around with this stuff. - */ - -/* APP side SYSCON registers */ -/* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */ -/* CLK Control Register 16bit (R/W) */ -#define U300_SYSCON_CCR (0x0000) -#define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040) -#define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020) -#define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00) -/* CLK Status Register 16bit (R/W) */ -#define U300_SYSCON_CSR (0x0004) -#define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002) -#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001) -/* Reset lines for SLOW devices 16bit (R/W) */ -#define U300_SYSCON_RSR (0x0014) -#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200) -#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100) -#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080) -#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040) -#define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020) -#define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010) -#define U300_SYSCON_RSR_EH_RESET_EN (0x0008) -#define U300_SYSCON_RSR_BTR_RESET_EN (0x0004) -#define U300_SYSCON_RSR_UART_RESET_EN (0x0002) -#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001) -/* Reset lines for FAST devices 16bit (R/W) */ -#define U300_SYSCON_RFR (0x0018) -#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080) -#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040) -#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020) -#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010) -#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008) -#define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004) -#define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002) -#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001) -/* Reset lines for the rest of the peripherals 16bit (R/W) */ -#define U300_SYSCON_RRR (0x001c) -#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000) -#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000) -#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000) -#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800) -#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100) -#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080) -#define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040) -#define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020) -#define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010) -#define U300_SYSCON_RRR_CPU_RESET_EN (0x0008) -#define U300_SYSCON_RRR_APEX_RESET_EN (0x0004) -#define U300_SYSCON_RRR_AHB_RESET_EN (0x0002) -#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001) -/* Clock enable for SLOW peripherals 16bit (R/W) */ -#define U300_SYSCON_CESR (0x0020) -#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200) -#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100) -#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080) -#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040) -#define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010) -#define U300_SYSCON_CESR_EH_CLK_EN (0x0008) -#define U300_SYSCON_CESR_BTR_CLK_EN (0x0004) -#define U300_SYSCON_CESR_UART_CLK_EN (0x0002) -#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001) -/* Clock enable for FAST peripherals 16bit (R/W) */ -#define U300_SYSCON_CEFR (0x0024) -#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200) -#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100) -#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080) -#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040) -#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020) -#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010) -#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008) -#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004) -#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002) -#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001) -/* Clock enable for the rest of the peripherals 16bit (R/W) */ -#define U300_SYSCON_CERR (0x0028) -#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000) -#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000) -#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800) -#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400) -#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200) -#define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100) -#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080) -#define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040) -#define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020) -#define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010) -#define U300_SYSCON_CERR_CPU_CLK_EN (0x0008) -#define U300_SYSCON_CERR_APEX_CLK_EN (0x0004) -#define U300_SYSCON_CERR_AHB_CLK_EN (0x0002) -#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001) -/* Single block clock enable 16bit (-/W) */ -#define U300_SYSCON_SBCER (0x002c) -#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009) -#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008) -#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007) -#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006) -#define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004) -#define U300_SYSCON_SBCER_EH_CLK_EN (0x0003) -#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002) -#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001) -#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000) -#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019) -#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018) -#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017) -#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016) -#define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015) -#define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014) -#define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013) -#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012) -#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011) -#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010) -#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D) -#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C) -#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B) -#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A) -#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029) -#define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028) -#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027) -#define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026) -#define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025) -#define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024) -#define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023) -#define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022) -#define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021) -#define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020) -/* Single block clock disable 16bit (-/W) */ -#define U300_SYSCON_SBCDR (0x0030) -/* Same values as above for SBCER */ -/* Clock force SLOW peripherals 16bit (R/W) */ -#define U300_SYSCON_CFSR (0x003c) -#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200) -#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100) -#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080) -#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020) -#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010) -#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008) -#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004) -#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002) -#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001) -/* Clock force FAST peripherals 16bit (R/W) */ -#define U300_SYSCON_CFFR (0x40) -/* Values not defined. Define if you want to use them. */ -/* Clock force the rest of the peripherals 16bit (R/W) */ -#define U300_SYSCON_CFRR (0x44) -#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000) -#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000) -#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800) -#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400) -#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200) -#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100) -#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080) -#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040) -#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020) -#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010) -#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008) -#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004) -#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002) -#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001) -/* PLL208 Frequency Control 16bit (R/W) */ -#define U300_SYSCON_PFCR (0x48) -#define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F) -/* Power Management Control 16bit (R/W) */ -#define U300_SYSCON_PMCR (0x50) -#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002) -#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001) -/* - * All other clocking registers moved to clock.c! - */ -/* Reset Out 16bit (R/W) */ -#define U300_SYSCON_RCR (0x6c) -#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001) -/* EMIF Slew Rate Control 16bit (R/W) */ -#define U300_SYSCON_SRCLR (0x70) -#define U300_SYSCON_SRCLR_MASK (0x03FF) -#define U300_SYSCON_SRCLR_VALUE (0x03FF) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001) -/* EMIF Clock Control Register 16bit (R/W) */ -#define U300_SYSCON_ECCR (0x0078) -#define U300_SYSCON_ECCR_MASK (0x000F) -#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008) -#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004) -#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002) -#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001) -/* Step one for killing the applications system 16bit (-/W) */ -#define U300_SYSCON_KA1R (0x0080) -#define U300_SYSCON_KA1R_MASK (0xFFFF) -#define U300_SYSCON_KA1R_VALUE (0xFFFF) -/* Step two for killing the application system 16bit (-/W) */ -#define U300_SYSCON_KA2R (0x0084) -#define U300_SYSCON_KA2R_MASK (0xFFFF) -#define U300_SYSCON_KA2R_VALUE (0xFFFF) -/* MMC/MSPRO frequency divider register 0 16bit (R/W) */ -#define U300_SYSCON_MMF0R (0x90) -#define U300_SYSCON_MMF0R_MASK (0x00FF) -#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0) -#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F) -/* MMC/MSPRO frequency divider register 1 16bit (R/W) */ -#define U300_SYSCON_MMF1R (0x94) -#define U300_SYSCON_MMF1R_MASK (0x00FF) -#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0) -#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F) -/* AAIF control register 16 bit (R/W) */ -#define U300_SYSCON_AAIFCR (0x98) -#define U300_SYSCON_AAIFCR_MASK (0x0003) -#define U300_SYSCON_AAIFCR_AASW_CTRL_MASK (0x0003) -#define U300_SYSCON_AAIFCR_AASW_CTRL_FUNCTIONAL (0x0000) -#define U300_SYSCON_AAIFCR_AASW_CTRL_MONITORING (0x0001) -#define U300_SYSCON_AAIFCR_AASW_CTRL_ACC_TO_EXT (0x0002) -#define U300_SYSCON_AAIFCR_AASW_CTRL_APP_TO_EXT (0x0003) -/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */ -#define U300_SYSCON_MMCR (0x9C) -#define U300_SYSCON_MMCR_MASK (0x0003) -#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002) -#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001) -/* Pull up/down control (R/W) */ -#define U300_SYSCON_PUCR (0x104) -#define U300_SYSCON_PUCR_EMIF_1_WAIT_N_PU_ENABLE (0x0200) -#define U300_SYSCON_PUCR_EMIF_1_NFIF_READY_PU_ENABLE (0x0100) -#define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE (0x0080) -#define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE (0x0040) -#define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK (0x003F) -/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */ -#define U300_SYSCON_S0CCR (0x120) -#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF) -#define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000) -#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000) -#define U300_SYSCON_S0CCR_CLOCK_INV (0x0200) -#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0) -#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E) -#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001) -#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1) -#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1) -#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1) -#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1) -#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1) -#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1) -#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1) -#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1) -#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1) -/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */ -#define U300_SYSCON_S1CCR (0x124) -#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF) -#define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000) -#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000) -#define U300_SYSCON_S1CCR_CLOCK_INV (0x0200) -#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0) -#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E) -#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001) -#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1) -#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1) -#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1) -#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1) -#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1) -#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1) -#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1) -#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1) -#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1) -/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */ -#define U300_SYSCON_S2CCR (0x128) -#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF) -#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000) -#define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000) -#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000) -#define U300_SYSCON_S2CCR_CLOCK_INV (0x0200) -#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0) -#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E) -#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001) -#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1) -#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1) -#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1) -#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1) -#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1) -#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1) -#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1) -#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1) -#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1) -/* SYS_MISC_CONTROL, miscellaneous 16bit (R/W) */ -#define U300_SYSCON_MCR (0x12c) -#define U300_SYSCON_MCR_FIELD_MASK (0x00FF) -#define U300_SYSCON_MCR_PMGEN_CR_4_MASK (0x00C0) -#define U300_SYSCON_MCR_PMGEN_CR_4_GPIO (0x0000) -#define U300_SYSCON_MCR_PMGEN_CR_4_SPI (0x0040) -#define U300_SYSCON_MCR_PMGEN_CR_4_AAIF (0x00C0) -#define U300_SYSCON_MCR_PMGEN_CR_2_MASK (0x0030) -#define U300_SYSCON_MCR_PMGEN_CR_2_GPIO (0x0000) -#define U300_SYSCON_MCR_PMGEN_CR_2_EMIF_1_STATIC (0x0010) -#define U300_SYSCON_MCR_PMGEN_CR_2_DSP (0x0020) -#define U300_SYSCON_MCR_PMGEN_CR_2_AAIF (0x0030) -#define U300_SYSCON_MCR_PMGEN_CR_0_MASK (0x000C) -#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M1 (0x0000) -#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M2 (0x0004) -#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M3 (0x0008) -#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM (0x000C) -#define U300_SYSCON_MCR_PM1G_MODE_ENABLE (0x0002) -#define U300_SYSCON_MCR_PMTG5_MODE_ENABLE (0x0001) -/* SC_PLL_IRQ_CONTROL 16bit (R/W) */ -#define U300_SYSCON_PICR (0x0130) -#define U300_SYSCON_PICR_MASK (0x00FF) -#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080) -#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040) -#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020) -#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010) -#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008) -#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004) -#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002) -#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001) -/* SC_PLL_IRQ_STATUS 16 bit (R/-) */ -#define U300_SYSCON_PISR (0x0134) -#define U300_SYSCON_PISR_MASK (0x000F) -#define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008) -#define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004) -#define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002) -#define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001) -/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */ -#define U300_SYSCON_PICLR (0x0138) -#define U300_SYSCON_PICLR_MASK (0x000F) -#define U300_SYSCON_PICLR_RWMASK (0x0000) -#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008) -#define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004) -#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002) -#define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001) -/* CAMIF_CONTROL 16 bit (-/W) */ -#define U300_SYSCON_CICR (0x013C) -#define U300_SYSCON_CICR_MASK (0x0FFF) -#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_MASK (0x0F00) -#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT1 (0x0C00) -#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT0 (0x0300) -#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_MASK (0x00F0) -#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT1 (0x00C0) -#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT0 (0x0030) -#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_MASK (0x000F) -#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT1 (0x000C) -#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT0 (0x0003) -/* Clock activity observability register 0 */ -#define U300_SYSCON_C0OAR (0x140) -#define U300_SYSCON_C0OAR_MASK (0xFFFF) -#define U300_SYSCON_C0OAR_VALUE (0xFFFF) -#define U300_SYSCON_C0OAR_BT_H_CLK (0x8000) -#define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000) -#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000) -#define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000) -#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800) -#define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400) -#define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200) -#define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100) -#define U300_SYSCON_C0OAR_APP_52_CLK (0x0080) -#define U300_SYSCON_C0OAR_APP_208_CLK (0x0040) -#define U300_SYSCON_C0OAR_APP_104_CLK (0x0020) -#define U300_SYSCON_C0OAR_APEX_CLK (0x0010) -#define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008) -#define U300_SYSCON_C0OAR_AHB_CLK (0x0004) -#define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002) -#define U300_SYSCON_C0OAR_AAIF_CLK (0x0001) -/* Clock activity observability register 1 */ -#define U300_SYSCON_C1OAR (0x144) -#define U300_SYSCON_C1OAR_MASK (0x3FFE) -#define U300_SYSCON_C1OAR_VALUE (0x3FFE) -#define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000) -#define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000) -#define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800) -#define U300_SYSCON_C1OAR_MMC_CLK (0x0400) -#define U300_SYSCON_C1OAR_KP_P_CLK (0x0200) -#define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100) -#define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080) -#define U300_SYSCON_C1OAR_GPIO_CLK (0x0040) -#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020) -#define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010) -#define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008) -#define U300_SYSCON_C1OAR_PPM_CLK (0x0004) -#define U300_SYSCON_C1OAR_DMA_CLK (0x0002) -/* Clock activity observability register 2 */ -#define U300_SYSCON_C2OAR (0x148) -#define U300_SYSCON_C2OAR_MASK (0x0FFF) -#define U300_SYSCON_C2OAR_VALUE (0x0FFF) -#define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800) -#define U300_SYSCON_C2OAR_XGAM_CLK (0x0400) -#define U300_SYSCON_C2OAR_VC_H_CLK (0x0200) -#define U300_SYSCON_C2OAR_VC_CLK (0x0100) -#define U300_SYSCON_C2OAR_UA_P_CLK (0x0080) -#define U300_SYSCON_C2OAR_TMR1_CLK (0x0040) -#define U300_SYSCON_C2OAR_TMR0_CLK (0x0020) -#define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010) -#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008) -#define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004) -#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002) -#define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001) - -/* Chip ID register 16bit (R/-) */ -#define U300_SYSCON_CIDR (0x400) -/* Video IRQ clear 16bit (R/W) */ -#define U300_SYSCON_VICR (0x404) -#define U300_SYSCON_VICR_VIDEO1_IRQ_CLEAR_ENABLE (0x0002) -#define U300_SYSCON_VICR_VIDEO0_IRQ_CLEAR_ENABLE (0x0001) -/* SMCR */ -#define U300_SYSCON_SMCR (0x4d0) -#define U300_SYSCON_SMCR_FIELD_MASK (0x000e) -#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008) -#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004) -#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002) -/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */ -#define U300_SYSCON_CSDR (0x4f0) -#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001) -/* PRINT_CONTROL Print Control 16bit (R/-) */ -#define U300_SYSCON_PCR (0x4f8) -#define U300_SYSCON_PCR_SERV_IND (0x0001) -/* BOOT_CONTROL 16bit (R/-) */ -#define U300_SYSCON_BCR (0x4fc) -#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400) -#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200) -#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC) -#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003) - - -/* CPU clock defines */ -/** - * CPU high frequency in MHz - */ -#define SYSCON_CPU_CLOCK_HIGH 208 -/** - * CPU medium frequency in MHz - */ -#define SYSCON_CPU_CLOCK_MEDIUM 52 -/** - * CPU low frequency in MHz - */ -#define SYSCON_CPU_CLOCK_LOW 13 - -/* EMIF clock defines */ -/** - * EMIF high frequency in MHz - */ -#define SYSCON_EMIF_CLOCK_HIGH 104 -/** - * EMIF medium frequency in MHz - */ -#define SYSCON_EMIF_CLOCK_MEDIUM 52 -/** - * EMIF low frequency in MHz - */ -#define SYSCON_EMIF_CLOCK_LOW 13 - -/* AHB clock defines */ -/** - * AHB high frequency in MHz - */ -#define SYSCON_AHB_CLOCK_HIGH 52 -/** - * AHB medium frequency in MHz - */ -#define SYSCON_AHB_CLOCK_MEDIUM 26 -/** - * AHB low frequency in MHz - */ -#define SYSCON_AHB_CLOCK_LOW 7 /* i.e 13/2=6.5MHz */ - -enum syscon_busmaster { - SYSCON_BM_DMAC, - SYSCON_BM_XGAM, - SYSCON_BM_VIDEO_ENC -}; - -/* Selectr a resistor or a set of resistors */ -enum syscon_pull_up_down { - SYSCON_PU_KEY_IN_EN, - SYSCON_PU_EMIF_1_8_BIT_EN, - SYSCON_PU_EMIF_1_16_BIT_EN, - SYSCON_PU_EMIF_1_NFIF_READY_EN, - SYSCON_PU_EMIF_1_NFIF_WAIT_N_EN, -}; - -/* - * Note that this array must match the order of the array "clk_reg" - * in syscon.c - */ -enum syscon_clk { - SYSCON_CLKCONTROL_SLOW_BRIDGE, - SYSCON_CLKCONTROL_UART, - SYSCON_CLKCONTROL_BTR, - SYSCON_CLKCONTROL_EH, - SYSCON_CLKCONTROL_GPIO, - SYSCON_CLKCONTROL_KEYPAD, - SYSCON_CLKCONTROL_APP_TIMER, - SYSCON_CLKCONTROL_ACC_TIMER, - SYSCON_CLKCONTROL_FAST_BRIDGE, - SYSCON_CLKCONTROL_I2C0, - SYSCON_CLKCONTROL_I2C1, - SYSCON_CLKCONTROL_I2S0, - SYSCON_CLKCONTROL_I2S1, - SYSCON_CLKCONTROL_MMC, - SYSCON_CLKCONTROL_SPI, - SYSCON_CLKCONTROL_I2S0_CORE, - SYSCON_CLKCONTROL_I2S1_CORE, - SYSCON_CLKCONTROL_UART1, - SYSCON_CLKCONTROL_AAIF, - SYSCON_CLKCONTROL_AHB, - SYSCON_CLKCONTROL_APEX, - SYSCON_CLKCONTROL_CPU, - SYSCON_CLKCONTROL_DMA, - SYSCON_CLKCONTROL_EMIF, - SYSCON_CLKCONTROL_NAND_IF, - SYSCON_CLKCONTROL_VIDEO_ENC, - SYSCON_CLKCONTROL_XGAM, - SYSCON_CLKCONTROL_SEMI, - SYSCON_CLKCONTROL_AHB_SUBSYS, - SYSCON_CLKCONTROL_MSPRO -}; - -enum syscon_sysclk_mode { - SYSCON_SYSCLK_DISABLED, - SYSCON_SYSCLK_M_CLK, - SYSCON_SYSCLK_ACC_FSM, - SYSCON_SYSCLK_PLL60_48, - SYSCON_SYSCLK_PLL60_60, - SYSCON_SYSCLK_ACC_PLL208, - SYSCON_SYSCLK_APP_PLL13, - SYSCON_SYSCLK_APP_FSM, - SYSCON_SYSCLK_RTC, - SYSCON_SYSCLK_APP_PLL208 -}; - -enum syscon_sysclk_req { - SYSCON_SYSCLKREQ_DISABLED, - SYSCON_SYSCLKREQ_ACTIVE_LOW, - SYSCON_SYSCLKREQ_MONITOR -}; - -enum syscon_clk_mode { - SYSCON_CLKMODE_OFF, - SYSCON_CLKMODE_DEFAULT, - SYSCON_CLKMODE_LOW, - SYSCON_CLKMODE_MEDIUM, - SYSCON_CLKMODE_HIGH, - SYSCON_CLKMODE_PERMANENT, - SYSCON_CLKMODE_ON, -}; - -enum syscon_call_mode { - SYSCON_CLKCALL_NOWAIT, - SYSCON_CLKCALL_WAIT, -}; - -int syscon_dc_on(bool keep_power_on); -int syscon_set_busmaster_active_state(enum syscon_busmaster busmaster, - bool active); -bool syscon_get_busmaster_active_state(void); -int syscon_set_sleep_mask(enum syscon_clk, - bool sleep_ctrl); -int syscon_config_sysclk(u32 sysclk, - enum syscon_sysclk_mode sysclkmode, - bool inverse, - u32 divisor, - enum syscon_sysclk_req sysclkreq); -bool syscon_can_turn_off_semi_clock(void); - -/* This function is restricted to core.c */ -int syscon_request_normal_power(bool req); - -/* This function is restricted to be used by platform_speed.c */ -int syscon_speed_request(enum syscon_call_mode wait_mode, - enum syscon_clk_mode req_clk_mode); -#endif /* __MACH_SYSCON_H */ diff --git a/arch/arm/mach-u300/include/mach/timex.h b/arch/arm/mach-u300/include/mach/timex.h deleted file mode 100644 index f233b72633f..00000000000 --- a/arch/arm/mach-u300/include/mach/timex.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * - * arch/arm/mach-u300/include/mach/timex.h - * - * - * Copyright (C) 2006-2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * Platform tick rate definition. - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ -#ifndef __MACH_TIMEX_H -#define __MACH_TIMEX_H - -/* This is for the APP OS GP1 (General Purpose 1) timer */ -#define CLOCK_TICK_RATE 1000000 - -#endif diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h deleted file mode 100644 index 0320495efc4..00000000000 --- a/arch/arm/mach-u300/include/mach/u300-regs.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * - * arch/arm/mach-u300/include/mach/u300-regs.h - * - * - * Copyright (C) 2006-2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * Basic register address definitions in physical memory and - * some block definitions for core devices like the timer. - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ - -#ifndef __MACH_U300_REGS_H -#define __MACH_U300_REGS_H - -/* - * These are the large blocks of memory allocated for I/O. - * the defines are used for setting up the I/O memory mapping. - */ - -/* NAND Flash CS0 */ -#define U300_NAND_CS0_PHYS_BASE 0x80000000 - -/* NFIF */ -#define U300_NAND_IF_PHYS_BASE 0x9f800000 - -/* ALE, CLE offset for FSMC NAND */ -#define PLAT_NAND_CLE (1 << 16) -#define PLAT_NAND_ALE (1 << 17) - -/* AHB Peripherals */ -#define U300_AHB_PER_PHYS_BASE 0xa0000000 -#define U300_AHB_PER_VIRT_BASE 0xff010000 - -/* FAST Peripherals */ -#define U300_FAST_PER_PHYS_BASE 0xc0000000 -#define U300_FAST_PER_VIRT_BASE 0xff020000 - -/* SLOW Peripherals */ -#define U300_SLOW_PER_PHYS_BASE 0xc0010000 -#define U300_SLOW_PER_VIRT_BASE 0xff000000 - -/* Boot ROM */ -#define U300_BOOTROM_PHYS_BASE 0xffff0000 -#define U300_BOOTROM_VIRT_BASE 0xffff0000 - -/* SEMI config base */ -#define U300_SEMI_CONFIG_BASE 0x2FFE0000 - -/* - * AHB peripherals - */ - -/* AHB Peripherals Bridge Controller */ -#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000) - -/* Vectored Interrupt Controller 0, servicing 32 interrupts */ -#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000) -#define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000) - -/* Vectored Interrupt Controller 1, servicing 32 interrupts */ -#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000) -#define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000) - -/* Memory Stick Pro (MSPRO) controller */ -#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000) - -/* EMIF Configuration Area */ -#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000) - - -/* - * FAST peripherals - */ - -/* FAST bridge control */ -#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000) - -/* MMC/SD controller */ -#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000) - -/* PCM I2S0 controller */ -#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000) - -/* PCM I2S1 controller */ -#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000) - -/* I2C0 controller */ -#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000) - -/* I2C1 controller */ -#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000) - -/* SPI controller */ -#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000) - -/* Fast UART1 on U335 only */ -#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000) - -/* - * SLOW peripherals - */ - -/* SLOW bridge control */ -#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE) - -/* SYSCON */ -#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000) -#define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000) - -/* Watchdog */ -#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000) - -/* UART0 */ -#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000) - -/* APP side special timer */ -#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000) -#define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000) - -/* Keypad */ -#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000) - -/* GPIO */ -#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000) - -/* RTC */ -#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000) - -/* Bus tracer */ -#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000) - -/* Event handler (hardware queue) */ -#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000) - -/* Genric Timer */ -#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000) - -/* PPM */ -#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000) - - -/* - * REST peripherals - */ - -/* ISP (image signal processor) */ -#define U300_ISP_BASE (0xA0008000) - -/* DMA Controller base */ -#define U300_DMAC_BASE (0xC0020000) - -/* MSL Base */ -#define U300_MSL_BASE (0xc0022000) - -/* APEX Base */ -#define U300_APEX_BASE (0xc0030000) - -/* Video Encoder Base */ -#define U300_VIDEOENC_BASE (0xc0080000) - -/* XGAM Base */ -#define U300_XGAM_BASE (0xd0000000) - -#endif diff --git a/arch/arm/mach-u300/include/mach/uncompress.h b/arch/arm/mach-u300/include/mach/uncompress.h deleted file mode 100644 index 783e7e60101..00000000000 --- a/arch/arm/mach-u300/include/mach/uncompress.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * arch/arm/mach-u300/include/mach/uncompress.h - * - * Copyright (C) 2003 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define AMBA_UART_DR (*(volatile unsigned char *)0xc0013000) -#define AMBA_UART_LCRH (*(volatile unsigned char *)0xc001302C) -#define AMBA_UART_CR (*(volatile unsigned char *)0xc0013030) -#define AMBA_UART_FR (*(volatile unsigned char *)0xc0013018) - -/* - * This does not append a newline - */ -static inline void putc(int c) -{ - while (AMBA_UART_FR & (1 << 5)) - barrier(); - - AMBA_UART_DR = c; -} - -static inline void flush(void) -{ - while (AMBA_UART_FR & (1 << 3)) - barrier(); -} - -/* - * nothing to do - */ -#define arch_decomp_setup() diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c index 9c53f01c62e..bf40cd478fe 100644 --- a/arch/arm/mach-u300/regulator.c +++ b/arch/arm/mach-u300/regulator.c @@ -10,11 +10,18 @@ #include <linux/device.h> #include <linux/signal.h> #include <linux/err.h> +#include <linux/of.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/regulator/machine.h> #include <linux/regulator/consumer.h> -/* Those are just for writing in syscon */ -#include <linux/io.h> -#include <mach/hardware.h> -#include <mach/syscon.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h> + +/* Power Management Control 16bit (R/W) */ +#define U300_SYSCON_PMCR (0x50) +#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002) +#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001) /* * Regulators that power the board and chip and which are @@ -47,13 +54,28 @@ void u300_pm_poweroff(void) /* * Hog the regulators needed to power up the board. */ -static int __init u300_init_boardpower(void) +static int __init __u300_init_boardpower(struct platform_device *pdev) { + struct device_node *np = pdev->dev.of_node; + struct device_node *syscon_np; + struct regmap *regmap; int err; - u32 val; pr_info("U300: setting up board power\n"); - main_power_15 = regulator_get(NULL, "vana15"); + + syscon_np = of_parse_phandle(np, "syscon", 0); + if (!syscon_np) { + pr_crit("U300: no syscon node\n"); + return -ENODEV; + } + regmap = syscon_node_to_regmap(syscon_np); + if (!regmap) { + pr_crit("U300: could not locate syscon regmap\n"); + return -ENODEV; + } + + main_power_15 = regulator_get(&pdev->dev, "vana15"); + if (IS_ERR(main_power_15)) { pr_err("could not get vana15"); return PTR_ERR(main_power_15); @@ -72,9 +94,8 @@ static int __init u300_init_boardpower(void) * the rest of the U300 power management is implemented. */ pr_info("U300: disable system controller pull-up\n"); - val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR); - val &= ~U300_SYSCON_PMCR_DCON_ENABLE; - writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR); + regmap_update_bits(regmap, U300_SYSCON_PMCR, + U300_SYSCON_PMCR_DCON_ENABLE, 0); /* Register globally exported PM poweroff hook */ pm_power_off = u300_pm_poweroff; @@ -82,7 +103,31 @@ static int __init u300_init_boardpower(void) return 0; } +static int __init s365_board_probe(struct platform_device *pdev) +{ + return __u300_init_boardpower(pdev); +} + +static const struct of_device_id s365_board_match[] = { + { .compatible = "stericsson,s365" }, + {}, +}; + +static struct platform_driver s365_board_driver = { + .driver = { + .name = "s365-board", + .owner = THIS_MODULE, + .of_match_table = s365_board_match, + }, +}; + /* * So at module init time we hog the regulator! */ -module_init(u300_init_boardpower); +static int __init u300_init_boardpower(void) +{ + return platform_driver_probe(&s365_board_driver, + s365_board_probe); +} + +device_initcall(u300_init_boardpower); diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c deleted file mode 100644 index 910698293d6..00000000000 --- a/arch/arm/mach-u300/spi.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * arch/arm/mach-u300/spi.c - * - * Copyright (C) 2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ -#include <linux/device.h> -#include <linux/amba/bus.h> -#include <linux/spi/spi.h> -#include <linux/amba/pl022.h> -#include <linux/platform_data/dma-coh901318.h> -#include <linux/err.h> - -/* - * The following is for the actual devices on the SSP/SPI bus - */ -#ifdef CONFIG_MACH_U300_SPIDUMMY -static void select_dummy_chip(u32 chipselect) -{ - pr_debug("CORE: %s called with CS=0x%x (%s)\n", - __func__, - chipselect, - chipselect ? "unselect chip" : "select chip"); - /* - * Here you would write the chip select value to the GPIO pins if - * this was a real chip (but this is a loopback dummy). - */ -} - -struct pl022_config_chip dummy_chip_info = { - /* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */ - .com_mode = DMA_TRANSFER, - .iface = SSP_INTERFACE_MOTOROLA_SPI, - /* We can only act as master but SSP_SLAVE is possible in theory */ - .hierarchy = SSP_MASTER, - /* 0 = drive TX even as slave, 1 = do not drive TX as slave */ - .slave_tx_disable = 0, - .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM, - .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC, - .ctrl_len = SSP_BITS_12, - .wait_state = SSP_MWIRE_WAIT_ZERO, - .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, - /* - * This is where you insert a call to a function to enable CS - * (usually GPIO) for a certain chip. - */ - .cs_control = select_dummy_chip, -}; -#endif - -static struct spi_board_info u300_spi_devices[] = { -#ifdef CONFIG_MACH_U300_SPIDUMMY - { - /* A dummy chip used for loopback tests */ - .modalias = "spi-dummy", - /* Really dummy, pass in additional chip config here */ - .platform_data = NULL, - /* This defines how the controller shall handle the device */ - .controller_data = &dummy_chip_info, - /* .irq - no external IRQ routed from this device */ - .max_speed_hz = 1000000, - .bus_num = 0, /* Only one bus on this chip */ - .chip_select = 0, - /* Means SPI_CS_HIGH, change if e.g low CS */ - .mode = SPI_MODE_1 | SPI_LOOP, - }, -#endif -}; - -static struct pl022_ssp_controller ssp_platform_data = { - /* If you have several SPI buses this varies, we have only bus 0 */ - .bus_id = 0, - /* - * On the APP CPU GPIO 4, 5 and 6 are connected as generic - * chip selects for SPI. (Same on U330, U335 and U365.) - * TODO: make sure the GPIO driver can select these properly - * and do padmuxing accordingly too. - */ - .num_chipselect = 3, -#ifdef CONFIG_COH901318 - .enable_dma = 1, - .dma_filter = coh901318_filter_id, - .dma_rx_param = (void *) U300_DMA_SPI_RX, - .dma_tx_param = (void *) U300_DMA_SPI_TX, -#else - .enable_dma = 0, -#endif -}; - - -void __init u300_spi_init(struct amba_device *adev) -{ - adev->dev.platform_data = &ssp_platform_data; -} - -void __init u300_spi_register_board_devices(void) -{ - /* Register any SPI devices */ - spi_register_board_info(u300_spi_devices, ARRAY_SIZE(u300_spi_devices)); -} diff --git a/arch/arm/mach-u300/spi.h b/arch/arm/mach-u300/spi.h deleted file mode 100644 index bd3d867e240..00000000000 --- a/arch/arm/mach-u300/spi.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * arch/arm/mach-u300/spi.h - * - * Copyright (C) 2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ -#ifndef SPI_H -#define SPI_H -#include <linux/amba/bus.h> - -#ifdef CONFIG_SPI_PL022 -void __init u300_spi_init(struct amba_device *adev); -void __init u300_spi_register_board_devices(void); -#else -/* Compile out SPI support if PL022 is not selected */ -static inline void __init u300_spi_init(struct amba_device *adev) -{ -} -static inline void __init u300_spi_register_board_devices(void) -{ -} -#endif - -#endif diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c index d9e73209c9b..390ae5feb1d 100644 --- a/arch/arm/mach-u300/timer.c +++ b/arch/arm/mach-u300/timer.c @@ -18,17 +18,15 @@ #include <linux/clk.h> #include <linux/err.h> #include <linux/irq.h> - -#include <mach/hardware.h> -#include <mach/irqs.h> +#include <linux/delay.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> /* Generic stuff */ #include <asm/sched_clock.h> #include <asm/mach/map.h> #include <asm/mach/time.h> -#include "timer.h" - /* * APP side special timer registers * This timer contains four timers which can fire an interrupt each. @@ -189,6 +187,8 @@ #define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ) #define US_PER_TICK ((1000000 + (HZ/2)) / HZ) +static void __iomem *u300_timer_base; + /* * The u300_set_mode() function is always called first, if we * have oneshot timer active, the oneshot scheduling function @@ -201,28 +201,28 @@ static void u300_set_mode(enum clock_event_mode mode, case CLOCK_EVT_MODE_PERIODIC: /* Disable interrupts on GPT1 */ writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Disable GP1 while we're reprogramming it. */ writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); + u300_timer_base + U300_TIMER_APP_DGPT1); /* * Set the periodic mode to a certain number of ticks per * jiffy. */ writel(TICKS_PER_JIFFY, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); + u300_timer_base + U300_TIMER_APP_GPT1TC); /* * Set continuous mode, so the timer keeps triggering * interrupts. */ writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS, - U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); + u300_timer_base + U300_TIMER_APP_SGPT1M); /* Enable timer interrupts */ writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Then enable the OS timer again */ writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); + u300_timer_base + U300_TIMER_APP_EGPT1); break; case CLOCK_EVT_MODE_ONESHOT: /* Just break; here? */ @@ -233,33 +233,33 @@ static void u300_set_mode(enum clock_event_mode mode, */ /* Disable interrupts on GPT1 */ writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Disable GP1 while we're reprogramming it. */ writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); + u300_timer_base + U300_TIMER_APP_DGPT1); /* * Expire far in the future, u300_set_next_event() will be * called soon... */ - writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); + writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC); /* We run one shot per tick here! */ writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, - U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); + u300_timer_base + U300_TIMER_APP_SGPT1M); /* Enable interrupts for this timer */ writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Enable timer */ writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); + u300_timer_base + U300_TIMER_APP_EGPT1); break; case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: /* Disable interrupts on GP1 */ writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Disable GP1 */ writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); + u300_timer_base + U300_TIMER_APP_DGPT1); break; case CLOCK_EVT_MODE_RESUME: /* Ignore this call */ @@ -281,27 +281,27 @@ static int u300_set_next_event(unsigned long cycles, { /* Disable interrupts on GPT1 */ writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Disable GP1 while we're reprogramming it. */ writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); + u300_timer_base + U300_TIMER_APP_DGPT1); /* Reset the General Purpose timer 1. */ writel(U300_TIMER_APP_RGPT1_TIMER_RESET, - U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1); + u300_timer_base + U300_TIMER_APP_RGPT1); /* IRQ in n * cycles */ - writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); + writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC); /* * We run one shot per tick here! (This is necessary to reconfigure, * the timer will tilt if you don't!) */ writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, - U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); + u300_timer_base + U300_TIMER_APP_SGPT1M); /* Enable timer interrupts */ writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Then enable the OS timer again */ writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); + u300_timer_base + U300_TIMER_APP_EGPT1); return 0; } @@ -320,8 +320,9 @@ static irqreturn_t u300_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evt = &clockevent_u300_1mhz; /* ACK/Clear timer IRQ for the APP GPT1 Timer */ + writel(U300_TIMER_APP_GPT1IA_IRQ_ACK, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA); + u300_timer_base + U300_TIMER_APP_GPT1IA); evt->event_handler(evt); return IRQ_HANDLED; } @@ -342,65 +343,88 @@ static struct irqaction u300_timer_irq = { static u32 notrace u300_read_sched_clock(void) { - return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC); + return readl(u300_timer_base + U300_TIMER_APP_GPT2CC); +} + +static unsigned long u300_read_current_timer(void) +{ + return readl(u300_timer_base + U300_TIMER_APP_GPT2CC); } +static struct delay_timer u300_delay_timer; /* * This sets up the system timers, clock source and clock event. */ -void __init u300_timer_init(void) +static void __init u300_timer_init_of(struct device_node *np) { + struct resource irq_res; + int irq; struct clk *clk; unsigned long rate; + u300_timer_base = of_iomap(np, 0); + if (!u300_timer_base) + panic("could not ioremap system timer\n"); + + /* Get the IRQ for the GP1 timer */ + irq = of_irq_to_resource(np, 2, &irq_res); + if (irq <= 0) + panic("no IRQ for system timer\n"); + + pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq); + /* Clock the interrupt controller */ - clk = clk_get_sys("apptimer", NULL); + clk = of_clk_get(np, 0); BUG_ON(IS_ERR(clk)); clk_prepare_enable(clk); rate = clk_get_rate(clk); setup_sched_clock(u300_read_sched_clock, 32, rate); + u300_delay_timer.read_current_timer = &u300_read_current_timer; + u300_delay_timer.freq = rate; + register_current_timer_delay(&u300_delay_timer); + /* * Disable the "OS" and "DD" timers - these are designed for Symbian! * Example usage in cnh1601578 cpu subsystem pd_timer_app.c */ writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC); + u300_timer_base + U300_TIMER_APP_CRC); writel(U300_TIMER_APP_ROST_TIMER_RESET, - U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST); + u300_timer_base + U300_TIMER_APP_ROST); writel(U300_TIMER_APP_DOST_TIMER_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST); + u300_timer_base + U300_TIMER_APP_DOST); writel(U300_TIMER_APP_RDDT_TIMER_RESET, - U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT); + u300_timer_base + U300_TIMER_APP_RDDT); writel(U300_TIMER_APP_DDDT_TIMER_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT); + u300_timer_base + U300_TIMER_APP_DDDT); /* Reset the General Purpose timer 1. */ writel(U300_TIMER_APP_RGPT1_TIMER_RESET, - U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1); + u300_timer_base + U300_TIMER_APP_RGPT1); /* Set up the IRQ handler */ - setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq); + setup_irq(irq, &u300_timer_irq); /* Reset the General Purpose timer 2 */ writel(U300_TIMER_APP_RGPT2_TIMER_RESET, - U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2); + u300_timer_base + U300_TIMER_APP_RGPT2); /* Set this timer to run around forever */ - writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC); + writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC); /* Set continuous mode so it wraps around */ writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS, - U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M); + u300_timer_base + U300_TIMER_APP_SGPT2M); /* Disable timer interrupts */ writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE); + u300_timer_base + U300_TIMER_APP_GPT2IE); /* Then enable the GP2 timer to use as a free running us counter */ writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2); + u300_timer_base + U300_TIMER_APP_EGPT2); /* Use general purpose timer 2 as clock source */ - if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC, + if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC, "GPT2", rate, 300, 32, clocksource_mmio_readl_up)) pr_err("timer: failed to initialize U300 clock source\n"); @@ -413,3 +437,6 @@ void __init u300_timer_init(void) * used by hrtimers! */ } + +CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer", + u300_timer_init_of); diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h deleted file mode 100644 index d34287bc34f..00000000000 --- a/arch/arm/mach-u300/timer.h +++ /dev/null @@ -1 +0,0 @@ -extern void u300_timer_init(void); diff --git a/arch/arm/mach-u300/u300-gpio.h b/arch/arm/mach-u300/u300-gpio.h deleted file mode 100644 index 83f50772e16..00000000000 --- a/arch/arm/mach-u300/u300-gpio.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Individual pin assignments for the B335/S335. - * Notice that the actual usage of these pins depends on the - * PAD MUX settings, that is why the same number can potentially - * appear several times. In the reference design each pin is only - * used for one purpose. These were determined by inspecting the - * S365 schematic. - */ -#define U300_GPIO_PIN_UART_RX 0 -#define U300_GPIO_PIN_UART_TX 1 -#define U300_GPIO_PIN_UART_CTS 2 -#define U300_GPIO_PIN_UART_RTS 3 -#define U300_GPIO_PIN_CAM_MAIN_STANDBY 4 /* Camera MAIN standby */ -#define U300_GPIO_PIN_GPIO05 5 /* Unrouted */ -#define U300_GPIO_PIN_MS_CD 6 /* Memory Stick Card insertion */ -#define U300_GPIO_PIN_GPIO07 7 /* Test point TP2430 */ - -#define U300_GPIO_PIN_GPIO08 8 /* Test point TP2437 */ -#define U300_GPIO_PIN_GPIO09 9 /* Test point TP2431 */ -#define U300_GPIO_PIN_GPIO10 10 /* Test point TP2432 */ -#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */ -#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */ -#define U300_GPIO_PIN_CAM_SUB_STANDBY 13 /* Camera SUB standby */ -#define U300_GPIO_PIN_GPIO14 14 /* Test point TP2436 */ -#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO16 16 /* Test point TP2438 */ -#define U300_GPIO_PIN_PHFSENSE 17 /* Headphone jack sensing */ -#define U300_GPIO_PIN_GPIO18 18 /* Test point TP2439 */ -#define U300_GPIO_PIN_GPIO19 19 /* Routed somewhere */ -#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */ -#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */ -#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */ -#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO24 24 /* Unrouted */ -#define U300_GPIO_PIN_GPIO25 25 /* Unrouted */ -#define U300_GPIO_PIN_GPIO26 26 /* Unrouted */ -#define U300_GPIO_PIN_GPIO27 27 /* Unrouted */ -#define U300_GPIO_PIN_GPIO28 28 /* Unrouted */ -#define U300_GPIO_PIN_GPIO29 29 /* Unrouted */ -#define U300_GPIO_PIN_GPIO30 30 /* Unrouted */ -#define U300_GPIO_PIN_GPIO31 31 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO32 32 /* Unrouted */ -#define U300_GPIO_PIN_GPIO33 33 /* Unrouted */ -#define U300_GPIO_PIN_GPIO34 34 /* Unrouted */ -#define U300_GPIO_PIN_GPIO35 35 /* Unrouted */ -#define U300_GPIO_PIN_GPIO36 36 /* Unrouted */ -#define U300_GPIO_PIN_GPIO37 37 /* Unrouted */ -#define U300_GPIO_PIN_GPIO38 38 /* Unrouted */ -#define U300_GPIO_PIN_GPIO39 39 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO40 40 /* Unrouted */ -#define U300_GPIO_PIN_GPIO41 41 /* Unrouted */ -#define U300_GPIO_PIN_GPIO42 42 /* Unrouted */ -#define U300_GPIO_PIN_GPIO43 43 /* Unrouted */ -#define U300_GPIO_PIN_GPIO44 44 /* Unrouted */ -#define U300_GPIO_PIN_GPIO45 45 /* Unrouted */ -#define U300_GPIO_PIN_GPIO46 46 /* Unrouted */ -#define U300_GPIO_PIN_GPIO47 47 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO48 48 /* Unrouted */ -#define U300_GPIO_PIN_GPIO49 49 /* Unrouted */ -#define U300_GPIO_PIN_GPIO50 50 /* Unrouted */ -#define U300_GPIO_PIN_GPIO51 51 /* Unrouted */ -#define U300_GPIO_PIN_GPIO52 52 /* Unrouted */ -#define U300_GPIO_PIN_GPIO53 53 /* Unrouted */ -#define U300_GPIO_PIN_GPIO54 54 /* Unrouted */ -#define U300_GPIO_PIN_GPIO55 55 /* Unrouted */ diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 6a4387e39df..b19b07204aa 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -51,6 +51,7 @@ config MACH_MOP500 bool "U8500 Development platform, MOP500 versions" select I2C select I2C_NOMADIK + select REGULATOR select REGULATOR_FIXED_VOLTAGE select SOC_BUS select UX500_SOC_DB8500 diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c index 33c353bc1c4..d6b7c8556fa 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.c +++ b/arch/arm/mach-ux500/board-mop500-regulators.c @@ -374,6 +374,7 @@ static struct ab8500_regulator_reg_init ab8500_reg_init[] = { static struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = { /* supplies to the display/camera */ [AB8500_LDO_AUX1] = { + .supply_regulator = "ab8500-ext-supply3", .constraints = { .name = "V-DISPLAY", .min_uV = 2800000, @@ -387,6 +388,7 @@ static struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = { }, /* supplies to the on-board eMMC */ [AB8500_LDO_AUX2] = { + .supply_regulator = "ab8500-ext-supply3", .constraints = { .name = "V-eMMC1", .min_uV = 1100000, @@ -402,6 +404,7 @@ static struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = { }, /* supply for VAUX3, supplies to SDcard slots */ [AB8500_LDO_AUX3] = { + .supply_regulator = "ab8500-ext-supply3", .constraints = { .name = "V-MMC-SD", .min_uV = 1100000, diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 3cd555ac6d0..78389de94dd 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -623,7 +623,7 @@ static void __init mop500_init_machine(void) sdi0_reg_info.gpios[0].gpio = GPIO_SDMMC_1V8_3V_SEL; mop500_pinmaps_init(); - parent = u8500_init_devices(&ab8500_platdata); + parent = u8500_init_devices(); for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) mop500_platform_devs[i]->dev.parent = parent; @@ -660,7 +660,7 @@ static void __init snowball_init_machine(void) sdi0_reg_info.gpios[0].gpio = SNOWBALL_SDMMC_1V8_3V_GPIO; snowball_pinmaps_init(); - parent = u8500_init_devices(&ab8500_platdata); + parent = u8500_init_devices(); for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++) snowball_platform_devs[i]->dev.parent = parent; @@ -698,7 +698,7 @@ static void __init hrefv60_init_machine(void) sdi0_reg_info.gpios[0].gpio = HREFV60_SDMMC_1V8_3V_GPIO; hrefv60_pinmaps_init(); - parent = u8500_init_devices(&ab8500_platdata); + parent = u8500_init_devices(); for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) mop500_platform_devs[i]->dev.parent = parent; diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index e90b5ab23b6..46cca52890b 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -206,7 +206,7 @@ static struct device * __init db8500_soc_device_init(void) /* * This function is called from the board init */ -struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500) +struct device * __init u8500_init_devices(void) { struct device *parent; int i; @@ -220,8 +220,6 @@ struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500) for (i = 0; i < ARRAY_SIZE(platform_devs); i++) platform_devs[i]->dev.parent = parent; - db8500_prcmu_device.dev.platform_data = ab8500; - platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); return parent; @@ -278,7 +276,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu", &db8500_prcmu_pdata), - OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x", NULL), + OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL), /* Requires device name bindings. */ OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE, "pinctrl-db8500", NULL), diff --git a/arch/arm/mach-ux500/cpuidle.c b/arch/arm/mach-ux500/cpuidle.c index 317a2be129f..a45dd09daed 100644 --- a/arch/arm/mach-ux500/cpuidle.c +++ b/arch/arm/mach-ux500/cpuidle.c @@ -21,6 +21,7 @@ #include <asm/proc-fns.h> #include "db8500-regs.h" +#include "id.h" static atomic_t master = ATOMIC_INIT(0); static DEFINE_SPINLOCK(master_lock); @@ -114,6 +115,9 @@ static struct cpuidle_driver ux500_idle_driver = { int __init ux500_idle_init(void) { + if (!(cpu_is_u8500_family() || cpu_is_ux540_family())) + return -ENODEV; + /* Configure wake up reasons */ prcmu_enable_wakeups(PRCMU_WAKEUP(ARM) | PRCMU_WAKEUP(RTC) | PRCMU_WAKEUP(ABB)); diff --git a/arch/arm/mach-ux500/setup.h b/arch/arm/mach-ux500/setup.h index bddce2b4937..cad3ca86c54 100644 --- a/arch/arm/mach-ux500/setup.h +++ b/arch/arm/mach-ux500/setup.h @@ -18,7 +18,7 @@ void __init ux500_map_io(void); extern void __init u8500_map_io(void); -extern struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500); +extern struct device * __init u8500_init_devices(void); extern void __init ux500_init_irq(void); extern void __init ux500_init_late(void); diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index 5907e10c37f..b8bbabec631 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig @@ -57,4 +57,13 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA config ARCH_VEXPRESS_CA9X4 bool "Versatile Express Cortex-A9x4 tile" +config ARCH_VEXPRESS_DCSCB + bool "Dual Cluster System Control Block (DCSCB) support" + depends on MCPM + select ARM_CCI + help + Support for the Dual Cluster System Configuration Block (DCSCB). + This is needed to provide CPU and cluster power management + on RTSM implementing big.LITTLE. + endmenu diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile index 42703e8b4d3..48ba89a8149 100644 --- a/arch/arm/mach-vexpress/Makefile +++ b/arch/arm/mach-vexpress/Makefile @@ -6,5 +6,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ obj-y := v2m.o obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o +obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h index f134cd4a85f..bde4374ab6d 100644 --- a/arch/arm/mach-vexpress/core.h +++ b/arch/arm/mach-vexpress/core.h @@ -6,6 +6,8 @@ void vexpress_dt_smp_map_io(void); +bool vexpress_smp_init_ops(void); + extern struct smp_operations vexpress_smp_ops; extern void vexpress_cpu_die(unsigned int cpu); diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c new file mode 100644 index 00000000000..16d57a8a9d5 --- /dev/null +++ b/arch/arm/mach-vexpress/dcscb.c @@ -0,0 +1,253 @@ +/* + * arch/arm/mach-vexpress/dcscb.c - Dual Cluster System Configuration Block + * + * Created by: Nicolas Pitre, May 2012 + * Copyright: (C) 2012-2013 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/spinlock.h> +#include <linux/errno.h> +#include <linux/of_address.h> +#include <linux/vexpress.h> +#include <linux/arm-cci.h> + +#include <asm/mcpm.h> +#include <asm/proc-fns.h> +#include <asm/cacheflush.h> +#include <asm/cputype.h> +#include <asm/cp15.h> + + +#define RST_HOLD0 0x0 +#define RST_HOLD1 0x4 +#define SYS_SWRESET 0x8 +#define RST_STAT0 0xc +#define RST_STAT1 0x10 +#define EAG_CFG_R 0x20 +#define EAG_CFG_W 0x24 +#define KFC_CFG_R 0x28 +#define KFC_CFG_W 0x2c +#define DCS_CFG_R 0x30 + +/* + * We can't use regular spinlocks. In the switcher case, it is possible + * for an outbound CPU to call power_down() while its inbound counterpart + * is already live using the same logical CPU number which trips lockdep + * debugging. + */ +static arch_spinlock_t dcscb_lock = __ARCH_SPIN_LOCK_UNLOCKED; + +static void __iomem *dcscb_base; +static int dcscb_use_count[4][2]; +static int dcscb_allcpus_mask[2]; + +static int dcscb_power_up(unsigned int cpu, unsigned int cluster) +{ + unsigned int rst_hold, cpumask = (1 << cpu); + unsigned int all_mask = dcscb_allcpus_mask[cluster]; + + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + if (cpu >= 4 || cluster >= 2) + return -EINVAL; + + /* + * Since this is called with IRQs enabled, and no arch_spin_lock_irq + * variant exists, we need to disable IRQs manually here. + */ + local_irq_disable(); + arch_spin_lock(&dcscb_lock); + + dcscb_use_count[cpu][cluster]++; + if (dcscb_use_count[cpu][cluster] == 1) { + rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); + if (rst_hold & (1 << 8)) { + /* remove cluster reset and add individual CPU's reset */ + rst_hold &= ~(1 << 8); + rst_hold |= all_mask; + } + rst_hold &= ~(cpumask | (cpumask << 4)); + writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); + } else if (dcscb_use_count[cpu][cluster] != 2) { + /* + * The only possible values are: + * 0 = CPU down + * 1 = CPU (still) up + * 2 = CPU requested to be up before it had a chance + * to actually make itself down. + * Any other value is a bug. + */ + BUG(); + } + + arch_spin_unlock(&dcscb_lock); + local_irq_enable(); + + return 0; +} + +static void dcscb_power_down(void) +{ + unsigned int mpidr, cpu, cluster, rst_hold, cpumask, all_mask; + bool last_man = false, skip_wfi = false; + + mpidr = read_cpuid_mpidr(); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + cpumask = (1 << cpu); + all_mask = dcscb_allcpus_mask[cluster]; + + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + BUG_ON(cpu >= 4 || cluster >= 2); + + __mcpm_cpu_going_down(cpu, cluster); + + arch_spin_lock(&dcscb_lock); + BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP); + dcscb_use_count[cpu][cluster]--; + if (dcscb_use_count[cpu][cluster] == 0) { + rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); + rst_hold |= cpumask; + if (((rst_hold | (rst_hold >> 4)) & all_mask) == all_mask) { + rst_hold |= (1 << 8); + last_man = true; + } + writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); + } else if (dcscb_use_count[cpu][cluster] == 1) { + /* + * A power_up request went ahead of us. + * Even if we do not want to shut this CPU down, + * the caller expects a certain state as if the WFI + * was aborted. So let's continue with cache cleaning. + */ + skip_wfi = true; + } else + BUG(); + + if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) { + arch_spin_unlock(&dcscb_lock); + + /* + * Flush all cache levels for this cluster. + * + * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need + * a preliminary flush here for those CPUs. At least, that's + * the theory -- without the extra flush, Linux explodes on + * RTSM (to be investigated). + */ + flush_cache_all(); + set_cr(get_cr() & ~CR_C); + flush_cache_all(); + + /* + * This is a harmless no-op. On platforms with a real + * outer cache this might either be needed or not, + * depending on where the outer cache sits. + */ + outer_flush_all(); + + /* Disable local coherency by clearing the ACTLR "SMP" bit: */ + set_auxcr(get_auxcr() & ~(1 << 6)); + + /* + * Disable cluster-level coherency by masking + * incoming snoops and DVM messages: + */ + cci_disable_port_by_cpu(mpidr); + + __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN); + } else { + arch_spin_unlock(&dcscb_lock); + + /* + * Flush the local CPU cache. + * + * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need + * a preliminary flush here for those CPUs. At least, that's + * the theory -- without the extra flush, Linux explodes on + * RTSM (to be investigated). + */ + flush_cache_louis(); + set_cr(get_cr() & ~CR_C); + flush_cache_louis(); + + /* Disable local coherency by clearing the ACTLR "SMP" bit: */ + set_auxcr(get_auxcr() & ~(1 << 6)); + } + + __mcpm_cpu_down(cpu, cluster); + + /* Now we are prepared for power-down, do it: */ + dsb(); + if (!skip_wfi) + wfi(); + + /* Not dead at this point? Let our caller cope. */ +} + +static const struct mcpm_platform_ops dcscb_power_ops = { + .power_up = dcscb_power_up, + .power_down = dcscb_power_down, +}; + +static void __init dcscb_usage_count_init(void) +{ + unsigned int mpidr, cpu, cluster; + + mpidr = read_cpuid_mpidr(); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + BUG_ON(cpu >= 4 || cluster >= 2); + dcscb_use_count[cpu][cluster] = 1; +} + +extern void dcscb_power_up_setup(unsigned int affinity_level); + +static int __init dcscb_init(void) +{ + struct device_node *node; + unsigned int cfg; + int ret; + + if (!cci_probed()) + return -ENODEV; + + node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb"); + if (!node) + return -ENODEV; + dcscb_base = of_iomap(node, 0); + if (!dcscb_base) + return -EADDRNOTAVAIL; + cfg = readl_relaxed(dcscb_base + DCS_CFG_R); + dcscb_allcpus_mask[0] = (1 << (((cfg >> 16) >> (0 << 2)) & 0xf)) - 1; + dcscb_allcpus_mask[1] = (1 << (((cfg >> 16) >> (1 << 2)) & 0xf)) - 1; + dcscb_usage_count_init(); + + ret = mcpm_platform_register(&dcscb_power_ops); + if (!ret) + ret = mcpm_sync_init(dcscb_power_up_setup); + if (ret) { + iounmap(dcscb_base); + return ret; + } + + pr_info("VExpress DCSCB support installed\n"); + + /* + * Future entries into the kernel can now go + * through the cluster entry vectors. + */ + vexpress_flags_set(virt_to_phys(mcpm_entry_point)); + + return 0; +} + +early_initcall(dcscb_init); diff --git a/arch/arm/mach-vexpress/dcscb_setup.S b/arch/arm/mach-vexpress/dcscb_setup.S new file mode 100644 index 00000000000..4bb7fbe0f62 --- /dev/null +++ b/arch/arm/mach-vexpress/dcscb_setup.S @@ -0,0 +1,38 @@ +/* + * arch/arm/include/asm/dcscb_setup.S + * + * Created by: Dave Martin, 2012-06-22 + * Copyright: (C) 2012-2013 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/linkage.h> + + +ENTRY(dcscb_power_up_setup) + + cmp r0, #0 @ check affinity level + beq 2f + +/* + * Enable cluster-level coherency, in preparation for turning on the MMU. + * The ACTLR SMP bit does not need to be set here, because cpu_resume() + * already restores that. + * + * A15/A7 may not require explicit L2 invalidation on reset, dependent + * on hardware integration decisions. + * For now, this code assumes that L2 is either already invalidated, + * or invalidation is not required. + */ + + b cci_enable_port_for_self + +2: @ Implementation-specific local CPU setup operations should go here, + @ if any. In this case, there is nothing to do. + + bx lr + +ENDPROC(dcscb_power_up_setup) diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c index dc1ace55d55..993c9ae5dc5 100644 --- a/arch/arm/mach-vexpress/platsmp.c +++ b/arch/arm/mach-vexpress/platsmp.c @@ -12,9 +12,11 @@ #include <linux/errno.h> #include <linux/smp.h> #include <linux/io.h> +#include <linux/of.h> #include <linux/of_fdt.h> #include <linux/vexpress.h> +#include <asm/mcpm.h> #include <asm/smp_scu.h> #include <asm/mach/map.h> @@ -203,3 +205,21 @@ struct smp_operations __initdata vexpress_smp_ops = { .cpu_die = vexpress_cpu_die, #endif }; + +bool __init vexpress_smp_init_ops(void) +{ +#ifdef CONFIG_MCPM + /* + * The best way to detect a multi-cluster configuration at the moment + * is to look for the presence of a CCI in the system. + * Override the default vexpress_smp_ops if so. + */ + struct device_node *node; + node = of_find_compatible_node(NULL, NULL, "arm,cci-400"); + if (node && of_device_is_available(node)) { + mcpm_smp_set_ops(); + return true; + } +#endif + return false; +} diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index 8802030df98..b0eccf7e06e 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -456,6 +456,7 @@ static const char * const v2m_dt_match[] __initconst = { DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express") .dt_compat = v2m_dt_match, .smp = smp_ops(vexpress_smp_ops), + .smp_init = smp_init_ops(vexpress_smp_init_ops), .map_io = v2m_dt_map_io, .init_early = v2m_dt_init_early, .init_irq = irqchip_init, diff --git a/arch/arm/mach-virt/Makefile b/arch/arm/mach-virt/Makefile index 042afc1f8c4..7ddbfa60227 100644 --- a/arch/arm/mach-virt/Makefile +++ b/arch/arm/mach-virt/Makefile @@ -3,4 +3,3 @@ # obj-y := virt.o -obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-virt/platsmp.c b/arch/arm/mach-virt/platsmp.c deleted file mode 100644 index f4143f5bfa5..00000000000 --- a/arch/arm/mach-virt/platsmp.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Dummy Virtual Machine - does what it says on the tin. - * - * Copyright (C) 2012 ARM Ltd - * Author: Will Deacon <will.deacon@arm.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <linux/init.h> -#include <linux/smp.h> -#include <linux/of.h> - -#include <asm/psci.h> -#include <asm/smp_plat.h> - -extern void secondary_startup(void); - -static void __init virt_smp_init_cpus(void) -{ -} - -static void __init virt_smp_prepare_cpus(unsigned int max_cpus) -{ -} - -static int __cpuinit virt_boot_secondary(unsigned int cpu, - struct task_struct *idle) -{ - if (psci_ops.cpu_on) - return psci_ops.cpu_on(cpu_logical_map(cpu), - __pa(secondary_startup)); - return -ENODEV; -} - -struct smp_operations __initdata virt_smp_ops = { - .smp_init_cpus = virt_smp_init_cpus, - .smp_prepare_cpus = virt_smp_prepare_cpus, - .smp_boot_secondary = virt_boot_secondary, -}; diff --git a/arch/arm/mach-virt/virt.c b/arch/arm/mach-virt/virt.c index 061f283f579..a67d2dd5bb6 100644 --- a/arch/arm/mach-virt/virt.c +++ b/arch/arm/mach-virt/virt.c @@ -36,11 +36,8 @@ static const char *virt_dt_match[] = { NULL }; -extern struct smp_operations virt_smp_ops; - DT_MACHINE_START(VIRT, "Dummy Virtual Machine") .init_irq = irqchip_init, .init_machine = virt_init, - .smp = smp_ops(virt_smp_ops), .dt_compat = virt_dt_match, MACHINE_END diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c index 1dd281efc02..f5c33df7a59 100644 --- a/arch/arm/mach-vt8500/vt8500.c +++ b/arch/arm/mach-vt8500/vt8500.c @@ -173,6 +173,7 @@ static const char * const vt8500_dt_compat[] = { "wm,wm8505", "wm,wm8750", "wm,wm8850", + NULL }; DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)") diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index c70969b9c25..50d008d8f87 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -117,7 +117,7 @@ int __init zynq_slcr_init(void) pr_info("%s mapped to %p\n", np->name, zynq_slcr_base); - xilinx_zynq_clocks_init(zynq_slcr_base); + zynq_clock_init(zynq_slcr_base); of_node_put(np); diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 35955b54944..9e8101ecd63 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -397,6 +397,15 @@ config CPU_V7 select CPU_PABRT_V7 select CPU_TLB_V7 if MMU +# ARMv7M +config CPU_V7M + bool + select CPU_32v7M + select CPU_ABRT_NOMMU + select CPU_CACHE_NOP + select CPU_PABRT_LEGACY + select CPU_THUMBONLY + config CPU_THUMBONLY bool # There are no CPUs available with MMU that don't implement an ARM ISA: @@ -441,6 +450,9 @@ config CPU_32v6K config CPU_32v7 bool +config CPU_32v7M + bool + # The abort model config CPU_ABRT_NOMMU bool @@ -491,6 +503,9 @@ config CPU_CACHE_V6 config CPU_CACHE_V7 bool +config CPU_CACHE_NOP + bool + config CPU_CACHE_VIVT bool @@ -613,7 +628,11 @@ config ARCH_DMA_ADDR_T_64BIT config ARM_THUMB bool "Support Thumb user binaries" if !CPU_THUMBONLY - depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON + depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \ + CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \ + CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ + CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \ + CPU_V7 || CPU_FEROCEON || CPU_V7M default y help Say Y if you want to include kernel support for running user space diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 9e51be96f63..ee558a01f39 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_CPU_CACHE_V4WB) += cache-v4wb.o obj-$(CONFIG_CPU_CACHE_V6) += cache-v6.o obj-$(CONFIG_CPU_CACHE_V7) += cache-v7.o obj-$(CONFIG_CPU_CACHE_FA) += cache-fa.o +obj-$(CONFIG_CPU_CACHE_NOP) += cache-nop.o AFLAGS_cache-v6.o :=-Wa,-march=armv6 AFLAGS_cache-v7.o :=-Wa,-march=armv7-a @@ -87,6 +88,7 @@ obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o obj-$(CONFIG_CPU_V6) += proc-v6.o obj-$(CONFIG_CPU_V6K) += proc-v6.o obj-$(CONFIG_CPU_V7) += proc-v7.o +obj-$(CONFIG_CPU_V7M) += proc-v7m.o AFLAGS_proc-v6.o :=-Wa,-march=armv6 AFLAGS_proc-v7.o :=-Wa,-march=armv7-a diff --git a/arch/arm/mm/cache-nop.S b/arch/arm/mm/cache-nop.S new file mode 100644 index 00000000000..8e12ddca003 --- /dev/null +++ b/arch/arm/mm/cache-nop.S @@ -0,0 +1,50 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <linux/init.h> + +#include "proc-macros.S" + +ENTRY(nop_flush_icache_all) + mov pc, lr +ENDPROC(nop_flush_icache_all) + + .globl nop_flush_kern_cache_all + .equ nop_flush_kern_cache_all, nop_flush_icache_all + + .globl nop_flush_kern_cache_louis + .equ nop_flush_kern_cache_louis, nop_flush_icache_all + + .globl nop_flush_user_cache_all + .equ nop_flush_user_cache_all, nop_flush_icache_all + + .globl nop_flush_user_cache_range + .equ nop_flush_user_cache_range, nop_flush_icache_all + + .globl nop_coherent_kern_range + .equ nop_coherent_kern_range, nop_flush_icache_all + +ENTRY(nop_coherent_user_range) + mov r0, 0 + mov pc, lr +ENDPROC(nop_coherent_user_range) + + .globl nop_flush_kern_dcache_area + .equ nop_flush_kern_dcache_area, nop_flush_icache_all + + .globl nop_dma_flush_range + .equ nop_dma_flush_range, nop_flush_icache_all + + .globl nop_dma_map_area + .equ nop_dma_map_area, nop_flush_icache_all + + .globl nop_dma_unmap_area + .equ nop_dma_unmap_area, nop_flush_icache_all + + __INITDATA + + @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) + define_cache_functions nop diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index d51225f90ae..dd3a6c670f0 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c @@ -20,12 +20,19 @@ void __init arm_mm_memblock_reserve(void) { +#ifndef CONFIG_CPU_V7M /* * Register the exception vector page. * some architectures which the DRAM is the exception vector to trap, * alloc_page breaks with error, although it is not NULL, but "0." */ memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE); +#else /* ifndef CONFIG_CPU_V7M */ + /* + * There is no dedicated vector page on V7-M. So nothing needs to be + * reserved here. + */ +#endif } void __init sanity_check_meminfo(void) diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S new file mode 100644 index 00000000000..0c93588fcb9 --- /dev/null +++ b/arch/arm/mm/proc-v7m.S @@ -0,0 +1,157 @@ +/* + * linux/arch/arm/mm/proc-v7m.S + * + * Copyright (C) 2008 ARM Ltd. + * Copyright (C) 2001 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This is the "shell" of the ARMv7-M processor support. + */ +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/v7m.h> +#include "proc-macros.S" + +ENTRY(cpu_v7m_proc_init) + mov pc, lr +ENDPROC(cpu_v7m_proc_init) + +ENTRY(cpu_v7m_proc_fin) + mov pc, lr +ENDPROC(cpu_v7m_proc_fin) + +/* + * cpu_v7m_reset(loc) + * + * Perform a soft reset of the system. Put the CPU into the + * same state as it would be if it had been reset, and branch + * to what would be the reset vector. + * + * - loc - location to jump to for soft reset + */ + .align 5 +ENTRY(cpu_v7m_reset) + mov pc, r0 +ENDPROC(cpu_v7m_reset) + +/* + * cpu_v7m_do_idle() + * + * Idle the processor (eg, wait for interrupt). + * + * IRQs are already disabled. + */ +ENTRY(cpu_v7m_do_idle) + wfi + mov pc, lr +ENDPROC(cpu_v7m_do_idle) + +ENTRY(cpu_v7m_dcache_clean_area) + mov pc, lr +ENDPROC(cpu_v7m_dcache_clean_area) + +/* + * There is no MMU, so here is nothing to do. + */ +ENTRY(cpu_v7m_switch_mm) + mov pc, lr +ENDPROC(cpu_v7m_switch_mm) + +.globl cpu_v7m_suspend_size +.equ cpu_v7m_suspend_size, 0 + +#ifdef CONFIG_ARM_CPU_SUSPEND +ENTRY(cpu_v7m_do_suspend) + mov pc, lr +ENDPROC(cpu_v7m_do_suspend) + +ENTRY(cpu_v7m_do_resume) + mov pc, lr +ENDPROC(cpu_v7m_do_resume) +#endif + + .section ".text.init", #alloc, #execinstr + +/* + * __v7m_setup + * + * This should be able to cover all ARMv7-M cores. + */ +__v7m_setup: + @ Configure the vector table base address + ldr r0, =BASEADDR_V7M_SCB + ldr r12, =vector_table + str r12, [r0, V7M_SCB_VTOR] + + @ enable UsageFault, BusFault and MemManage fault. + ldr r5, [r0, #V7M_SCB_SHCSR] + orr r5, #(V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA) + str r5, [r0, #V7M_SCB_SHCSR] + + @ Lower the priority of the SVC and PendSV exceptions + mov r5, #0x80000000 + str r5, [r0, V7M_SCB_SHPR2] @ set SVC priority + mov r5, #0x00800000 + str r5, [r0, V7M_SCB_SHPR3] @ set PendSV priority + + @ SVC to run the kernel in this mode + adr r1, BSYM(1f) + ldr r5, [r12, #11 * 4] @ read the SVC vector entry + str r1, [r12, #11 * 4] @ write the temporary SVC vector entry + mov r6, lr @ save LR + mov r7, sp @ save SP + ldr sp, =__v7m_setup_stack_top + cpsie i + svc #0 +1: cpsid i + str r5, [r12, #11 * 4] @ restore the original SVC vector entry + mov lr, r6 @ restore LR + mov sp, r7 @ restore SP + + @ Special-purpose control register + mov r1, #1 + msr control, r1 @ Thread mode has unpriviledged access + + @ Configure the System Control Register to ensure 8-byte stack alignment + @ Note the STKALIGN bit is either RW or RAO. + ldr r12, [r0, V7M_SCB_CCR] @ system control register + orr r12, #V7M_SCB_CCR_STKALIGN + str r12, [r0, V7M_SCB_CCR] + mov pc, lr +ENDPROC(__v7m_setup) + + define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1 + + .section ".rodata" + string cpu_arch_name, "armv7m" + string cpu_elf_name "v7m" + string cpu_v7m_name "ARMv7-M" + + .section ".proc.info.init", #alloc, #execinstr + + /* + * Match any ARMv7-M processor core. + */ + .type __v7m_proc_info, #object +__v7m_proc_info: + .long 0x000f0000 @ Required ID value + .long 0x000f0000 @ Mask for ID + .long 0 @ proc_info_list.__cpu_mm_mmu_flags + .long 0 @ proc_info_list.__cpu_io_mmu_flags + b __v7m_setup @ proc_info_list.__cpu_flush + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT + .long cpu_v7m_name + .long v7m_processor_functions @ proc_info_list.proc + .long 0 @ proc_info_list.tlb + .long 0 @ proc_info_list.user + .long nop_cache_fns @ proc_info_list.cache + .size __v7m_proc_info, . - __v7m_proc_info + +__v7m_setup_stack: + .space 4 * 8 @ 8 registers +__v7m_setup_stack_top: diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 251f827271e..c019b7aaf77 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -383,7 +383,7 @@ static struct resource orion_ge10_shared_resources[] = { static struct platform_device orion_ge10_shared = { .name = MV643XX_ETH_SHARED_NAME, - .id = 1, + .id = 2, .dev = { .platform_data = &orion_ge10_shared_data, }, @@ -398,8 +398,8 @@ static struct resource orion_ge10_resources[] = { static struct platform_device orion_ge10 = { .name = MV643XX_ETH_NAME, - .id = 1, - .num_resources = 2, + .id = 2, + .num_resources = 1, .resource = orion_ge10_resources, .dev = { .coherent_dma_mask = DMA_BIT_MASK(32), @@ -432,7 +432,7 @@ static struct resource orion_ge11_shared_resources[] = { static struct platform_device orion_ge11_shared = { .name = MV643XX_ETH_SHARED_NAME, - .id = 1, + .id = 3, .dev = { .platform_data = &orion_ge11_shared_data, }, @@ -447,8 +447,8 @@ static struct resource orion_ge11_resources[] = { static struct platform_device orion_ge11 = { .name = MV643XX_ETH_NAME, - .id = 1, - .num_resources = 2, + .id = 3, + .num_resources = 1, .resource = orion_ge11_resources, .dev = { .coherent_dma_mask = DMA_BIT_MASK(32), diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index e06fc5fefa1..d9a24f605a2 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -10,6 +10,7 @@ #ifndef __PLAT_COMMON_H #include <linux/mv643xx_eth.h> +#include <linux/platform_data/usb-ehci-orion.h> struct dsa_platform_data; struct mv_sata_platform_data; diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index f8ed2de0a67..ca27cc9ac4b 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -6,7 +6,7 @@ config PLAT_SAMSUNG bool - depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P + depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P || ARCH_EXYNOS default y select GENERIC_IRQ_CHIP select NO_IOPORT @@ -15,12 +15,10 @@ config PLAT_SAMSUNG config PLAT_S5P bool - depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) + depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) default y select ARCH_REQUIRE_GPIOLIB - select ARM_GIC if ARCH_EXYNOS - select ARM_VIC if !ARCH_EXYNOS - select GIC_NON_BANKED if ARCH_EXYNOS4 + select ARM_VIC select NO_IOPORT select PLAT_SAMSUNG select S3C_GPIO_TRACK @@ -60,6 +58,20 @@ config S3C_LOWLEVEL_UART_PORT this configuration should be between zero and two. The port must have been initialised by the boot-loader before use. +config SAMSUNG_ATAGS + def_bool n + depends on !ARCH_MULTIPLATFORM + depends on ATAGS + help + This option enables ATAGS based boot support code for + Samsung platforms, including static platform devices, legacy + clock, timer and interrupt initialization, etc. + + Platforms that support only DT based boot need not to select + this option. + +if SAMSUNG_ATAGS + # timer options config SAMSUNG_HRT @@ -367,11 +379,6 @@ config S5P_DEV_JPEG help Compile in platform device definitions for JPEG codec -config S5P_DEV_MFC - bool - help - Compile in setup memory (init) code for MFC - config S5P_DEV_ONENAND bool help @@ -412,6 +419,21 @@ config S3C_DMA help Internal configuration for S3C DMA core +config S5P_IRQ_PM + bool + default y if S5P_PM + help + Legacy IRQ power management for S5P platforms + +config SAMSUNG_PM_GPIO + bool + default y if GPIO_SAMSUNG && PM + help + Include legacy GPIO power management code for platforms not using + pinctrl-samsung driver. + +endif + config SAMSUNG_DMADEV bool select ARM_AMBA @@ -421,6 +443,11 @@ config SAMSUNG_DMADEV help Use DMA device engine for PL330 DMAC. +config S5P_DEV_MFC + bool + help + Compile in setup memory (init) code for MFC + comment "Power management" config SAMSUNG_PM_DEBUG diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index a23c460299a..6348ae2e3b4 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -31,10 +31,10 @@ obj-$(CONFIG_S3C_ADC) += adc.o # devices -obj-y += platformdata.o +obj-$(CONFIG_SAMSUNG_ATAGS) += platformdata.o -obj-y += devs.o -obj-y += dev-uart.o +obj-$(CONFIG_SAMSUNG_ATAGS) += devs.o +obj-$(CONFIG_SAMSUNG_ATAGS) += dev-uart.o obj-$(CONFIG_S5P_DEV_MFC) += s5p-dev-mfc.o obj-$(CONFIG_S5P_DEV_UART) += s5p-dev-uart.o @@ -52,10 +52,11 @@ obj-$(CONFIG_SAMSUNG_DMADEV) += dma-ops.o # PM support obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_PM) += pm-gpio.o +obj-$(CONFIG_SAMSUNG_PM_GPIO) += pm-gpio.o obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o -obj-$(CONFIG_S5P_PM) += s5p-pm.o s5p-irq-pm.o +obj-$(CONFIG_S5P_PM) += s5p-pm.o +obj-$(CONFIG_S5P_IRQ_PM) += s5p-irq-pm.o obj-$(CONFIG_S5P_SLEEP) += s5p-sleep.o diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 30c2fe243f7..0f9c3f431a5 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -311,9 +311,9 @@ struct platform_device s5p_device_jpeg = { #ifdef CONFIG_S5P_DEV_FIMD0 static struct resource s5p_fimd0_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K), - [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC), - [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO), - [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM), + [1] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_VSYNC, "vsync"), + [2] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_FIFO, "fifo"), + [3] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_SYSTEM, "lcd_sys"), }; struct platform_device s5p_device_fimd0 = { diff --git a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h index d01576318b2..bd3a6db14cb 100644 --- a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h +++ b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h @@ -28,7 +28,6 @@ struct s3c24xx_dma_map { const char *name; unsigned long channels[S3C_DMA_CHANNELS]; - unsigned long channels_rx[S3C_DMA_CHANNELS]; }; struct s3c24xx_dma_selection { @@ -38,10 +37,6 @@ struct s3c24xx_dma_selection { void (*select)(struct s3c2410_dma_chan *chan, struct s3c24xx_dma_map *map); - - void (*direction)(struct s3c2410_dma_chan *chan, - struct s3c24xx_dma_map *map, - enum dma_data_direction dir); }; extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel); diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index f6fcadeee96..5d47ca35cab 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -166,6 +166,7 @@ extern void s3c_pm_check_store(void); */ extern void s3c_pm_configure_extint(void); +#ifdef CONFIG_GPIO_SAMSUNG /** * samsung_pm_restore_gpios() - restore the state of the gpios after sleep. * @@ -181,6 +182,10 @@ extern void samsung_pm_restore_gpios(void); * Save the GPIO states for resotration on resume. See samsung_pm_restore_gpios(). */ extern void samsung_pm_save_gpios(void); +#else +static inline void samsung_pm_restore_gpios(void) {} +static inline void samsung_pm_save_gpios(void) {} +#endif extern void s3c_pm_save_core(void); extern void s3c_pm_restore_core(void); diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h index 438b24846e7..02b66d723d1 100644 --- a/arch/arm/plat-samsung/include/plat/uncompress.h +++ b/arch/arm/plat-samsung/include/plat/uncompress.h @@ -66,6 +66,9 @@ uart_rd(unsigned int reg) static void putc(int ch) { + if (!config_enabled(CONFIG_DEBUG_LL)) + return; + if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) { int level; @@ -118,7 +121,12 @@ static void arch_decomp_error(const char *x) #ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO static inline void arch_enable_uart_fifo(void) { - u32 fifocon = uart_rd(S3C2410_UFCON); + u32 fifocon; + + if (!config_enabled(CONFIG_DEBUG_LL)) + return; + + fifocon = uart_rd(S3C2410_UFCON); if (!(fifocon & S3C2410_UFCON_FIFOMODE)) { fifocon |= S3C2410_UFCON_RESETBOTH; diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c index 79d10fca909..3e5c4619caa 100644 --- a/arch/arm/plat-samsung/init.c +++ b/arch/arm/plat-samsung/init.c @@ -87,7 +87,7 @@ void __init s3c24xx_init_clocks(int xtal) } /* uart management */ - +#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS) static int nr_uarts __initdata = 0; static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS]; @@ -134,11 +134,12 @@ void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) if (cpu == NULL) return; - if (cpu->init_uarts == NULL) { + if (cpu->init_uarts == NULL && IS_ENABLED(CONFIG_SAMSUNG_ATAGS)) { printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n"); } else (cpu->init_uarts)(cfg, no); } +#endif static int __init s3c_arch_init(void) { @@ -152,8 +153,9 @@ static int __init s3c_arch_init(void) ret = (cpu->init)(); if (ret != 0) return ret; - +#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS) ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts); +#endif return ret; } diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c index c2ff92c30bd..a8de3cfe2ee 100644 --- a/arch/arm/plat-samsung/pm-gpio.c +++ b/arch/arm/plat-samsung/pm-gpio.c @@ -192,7 +192,8 @@ struct samsung_gpio_pm samsung_gpio_pm_2bit = { .resume = samsung_gpio_pm_2bit_resume, }; -#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P) +#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P) \ + || defined(CONFIG_ARCH_EXYNOS) static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip) { chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); @@ -302,7 +303,7 @@ struct samsung_gpio_pm samsung_gpio_pm_4bit = { .save = samsung_gpio_pm_4bit_save, .resume = samsung_gpio_pm_4bit_resume, }; -#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */ +#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P || CONFIG_ARCH_EXYNOS */ /** * samsung_pm_save_gpio() - save gpio chip data for suspend diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index 53210ec4e8e..ea361364245 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -16,18 +16,23 @@ #include <linux/suspend.h> #include <linux/errno.h> #include <linux/delay.h> +#include <linux/of.h> #include <linux/serial_core.h> #include <linux/io.h> #include <asm/cacheflush.h> #include <asm/suspend.h> -#include <mach/hardware.h> -#include <mach/map.h> #include <plat/regs-serial.h> + +#ifdef CONFIG_SAMSUNG_ATAGS +#include <mach/hardware.h> +#include <mach/map.h> #include <mach/regs-clock.h> #include <mach/regs-irq.h> #include <mach/irqs.h> +#endif + #include <asm/irq.h> #include <plat/pm.h> @@ -261,7 +266,8 @@ static int s3c_pm_enter(suspend_state_t state) * require a full power-cycle) */ - if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) && + if (!of_have_populated_dt() && + !any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) && !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) { printk(KERN_ERR "%s: No wake-up sources!\n", __func__); printk(KERN_ERR "%s: Aborting sleep\n", __func__); @@ -270,8 +276,11 @@ static int s3c_pm_enter(suspend_state_t state) /* save all necessary core registers not covered by the drivers */ - samsung_pm_save_gpios(); - samsung_pm_saved_gpios(); + if (!of_have_populated_dt()) { + samsung_pm_save_gpios(); + samsung_pm_saved_gpios(); + } + s3c_pm_save_uarts(); s3c_pm_save_core(); @@ -310,8 +319,11 @@ static int s3c_pm_enter(suspend_state_t state) s3c_pm_restore_core(); s3c_pm_restore_uarts(); - samsung_pm_restore_gpios(); - s3c_pm_restored_gpios(); + + if (!of_have_populated_dt()) { + samsung_pm_restore_gpios(); + s3c_pm_restored_gpios(); + } s3c_pm_debug_init(); diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c index a93fb6fb660..ad51f85fbd0 100644 --- a/arch/arm/plat-samsung/s5p-dev-mfc.c +++ b/arch/arm/plat-samsung/s5p-dev-mfc.c @@ -17,10 +17,12 @@ #include <linux/of_fdt.h> #include <linux/of.h> +#include <plat/mfc.h> + +#ifdef CONFIG_SAMSUNG_ATAGS #include <mach/map.h> #include <mach/irqs.h> #include <plat/devs.h> -#include <plat/mfc.h> static struct resource s5p_mfc_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K), @@ -61,6 +63,10 @@ struct platform_device s5p_device_mfc_r = { .coherent_dma_mask = DMA_BIT_MASK(32), }, }; +#else +static struct platform_device s5p_device_mfc_l; +static struct platform_device s5p_device_mfc_r; +#endif struct s5p_mfc_reserved_mem { phys_addr_t base; @@ -70,6 +76,7 @@ struct s5p_mfc_reserved_mem { static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata; + void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize, phys_addr_t lbase, unsigned int lsize) { @@ -93,6 +100,7 @@ void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize, } } +#ifdef CONFIG_SAMSUNG_ATAGS static int __init s5p_mfc_memory_init(void) { int i; @@ -111,6 +119,7 @@ static int __init s5p_mfc_memory_init(void) return 0; } device_initcall(s5p_mfc_memory_init); +#endif #ifdef CONFIG_OF int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname, diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S index 323ce1a62bb..46e17492fd1 100644 --- a/arch/arm/vfp/entry.S +++ b/arch/arm/vfp/entry.S @@ -60,7 +60,7 @@ ENTRY(vfp_testing_entry) str r11, [r10, #TI_PREEMPT] #endif ldr r0, VFP_arch_address - str r5, [r0] @ known non-zero value + str r0, [r0] @ set to non-zero value mov pc, r9 @ we have handled the fault ENDPROC(vfp_testing_entry) diff --git a/arch/arm64/kernel/arm64ksyms.c b/arch/arm64/kernel/arm64ksyms.c index 7df1aad29b6..41b4f626d55 100644 --- a/arch/arm64/kernel/arm64ksyms.c +++ b/arch/arm64/kernel/arm64ksyms.c @@ -34,6 +34,7 @@ EXPORT_SYMBOL(__strnlen_user); EXPORT_SYMBOL(__strncpy_from_user); EXPORT_SYMBOL(copy_page); +EXPORT_SYMBOL(clear_page); EXPORT_SYMBOL(__copy_from_user); EXPORT_SYMBOL(__copy_to_user); diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index c7e047049f2..1d1314280a0 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -390,6 +390,16 @@ el0_sync_compat: b.eq el0_fpsimd_exc cmp x24, #ESR_EL1_EC_UNKNOWN // unknown exception in EL0 b.eq el0_undef + cmp x24, #ESR_EL1_EC_CP15_32 // CP15 MRC/MCR trap + b.eq el0_undef + cmp x24, #ESR_EL1_EC_CP15_64 // CP15 MRRC/MCRR trap + b.eq el0_undef + cmp x24, #ESR_EL1_EC_CP14_MR // CP14 MRC/MCR trap + b.eq el0_undef + cmp x24, #ESR_EL1_EC_CP14_LS // CP14 LDC/STC trap + b.eq el0_undef + cmp x24, #ESR_EL1_EC_CP14_64 // CP14 MRRC/MCRR trap + b.eq el0_undef cmp x24, #ESR_EL1_EC_BREAKPT_EL0 // debug exception in EL0 b.ge el0_dbg b el0_inv diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index 61d7dd29f75..f30852d2859 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -267,7 +267,8 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs) return; #endif - if (show_unhandled_signals) { + if (show_unhandled_signals && unhandled_signal(current, SIGILL) && + printk_ratelimit()) { pr_info("%s[%d]: undefined instruction: pc=%p\n", current->comm, task_pid_nr(current), pc); dump_instr(KERN_INFO, regs); @@ -294,7 +295,7 @@ asmlinkage long do_ni_syscall(struct pt_regs *regs) } #endif - if (show_unhandled_signals) { + if (show_unhandled_signals && printk_ratelimit()) { pr_info("%s[%d]: syscall %d\n", current->comm, task_pid_nr(current), (int)regs->syscallno); dump_instr("", regs); @@ -310,14 +311,20 @@ asmlinkage long do_ni_syscall(struct pt_regs *regs) */ asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr) { + siginfo_t info; + void __user *pc = (void __user *)instruction_pointer(regs); console_verbose(); pr_crit("Bad mode in %s handler detected, code 0x%08x\n", handler[reason], esr); + __show_regs(regs); + + info.si_signo = SIGILL; + info.si_errno = 0; + info.si_code = ILL_ILLOPC; + info.si_addr = pc; - die("Oops - bad mode", regs, 0); - local_irq_disable(); - panic("bad mode"); + arm64_notify_die("Oops - bad mode", regs, &info, 0); } void __pte_error(const char *file, int line, unsigned long val) diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 98af6e760cc..1426468b77f 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -113,7 +113,8 @@ static void __do_user_fault(struct task_struct *tsk, unsigned long addr, { struct siginfo si; - if (show_unhandled_signals) { + if (show_unhandled_signals && unhandled_signal(tsk, sig) && + printk_ratelimit()) { pr_info("%s[%d]: unhandled %s (%d) at 0x%08lx, esr 0x%03x\n", tsk->comm, task_pid_nr(tsk), fault_name(esr), sig, addr, esr); diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig index bdc35589277..549903cfc2c 100644 --- a/arch/avr32/Kconfig +++ b/arch/avr32/Kconfig @@ -205,6 +205,11 @@ config ARCH_DISCONTIGMEM_ENABLE config ARCH_SPARSEMEM_ENABLE def_bool n +config NODES_SHIFT + int + default "2" + depends on NEED_MULTIPLE_NODES + source "mm/Kconfig" config OWNERSHIP_TRACE diff --git a/arch/avr32/include/asm/Kbuild b/arch/avr32/include/asm/Kbuild index 4dd4f78d3dc..d22af851f3f 100644 --- a/arch/avr32/include/asm/Kbuild +++ b/arch/avr32/include/asm/Kbuild @@ -2,3 +2,4 @@ generic-y += clkdev.h generic-y += exec.h generic-y += trace_clock.h +generic-y += param.h diff --git a/arch/avr32/include/asm/numnodes.h b/arch/avr32/include/asm/numnodes.h deleted file mode 100644 index 0b864d7ce33..00000000000 --- a/arch/avr32/include/asm/numnodes.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __ASM_AVR32_NUMNODES_H -#define __ASM_AVR32_NUMNODES_H - -/* Max 4 nodes */ -#define NODES_SHIFT 2 - -#endif /* __ASM_AVR32_NUMNODES_H */ diff --git a/arch/avr32/include/asm/param.h b/arch/avr32/include/asm/param.h deleted file mode 100644 index 009a167aea1..00000000000 --- a/arch/avr32/include/asm/param.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __ASM_AVR32_PARAM_H -#define __ASM_AVR32_PARAM_H - -#include <uapi/asm/param.h> - -# define HZ CONFIG_HZ -# define USER_HZ 100 /* User interfaces are in "ticks" */ -# define CLOCKS_PER_SEC (USER_HZ) /* frequency at which times() counts */ -#endif /* __ASM_AVR32_PARAM_H */ diff --git a/arch/avr32/include/uapi/asm/Kbuild b/arch/avr32/include/uapi/asm/Kbuild index df53e7a4677..3b85eaddf52 100644 --- a/arch/avr32/include/uapi/asm/Kbuild +++ b/arch/avr32/include/uapi/asm/Kbuild @@ -33,3 +33,4 @@ header-y += termbits.h header-y += termios.h header-y += types.h header-y += unistd.h +generic-y += param.h diff --git a/arch/avr32/include/uapi/asm/param.h b/arch/avr32/include/uapi/asm/param.h deleted file mode 100644 index d28aa5ee6d3..00000000000 --- a/arch/avr32/include/uapi/asm/param.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef _UAPI__ASM_AVR32_PARAM_H -#define _UAPI__ASM_AVR32_PARAM_H - - -#ifndef HZ -# define HZ 100 -#endif - -/* TODO: Should be configurable */ -#define EXEC_PAGESIZE 4096 - -#ifndef NOGROUP -# define NOGROUP (-1) -#endif - -#define MAXHOSTNAMELEN 64 - -#endif /* _UAPI__ASM_AVR32_PARAM_H */ diff --git a/arch/avr32/kernel/module.c b/arch/avr32/kernel/module.c index 596f7305d93..2c941290802 100644 --- a/arch/avr32/kernel/module.c +++ b/arch/avr32/kernel/module.c @@ -264,7 +264,7 @@ int apply_relocate_add(Elf32_Shdr *sechdrs, const char *strtab, break; case R_AVR32_GOT18SW: if ((relocation & 0xfffe0003) != 0 - && (relocation & 0xfffc0003) != 0xffff0000) + && (relocation & 0xfffc0000) != 0xfffc0000) return reloc_overflow(module, "R_AVR32_GOT18SW", relocation); relocation >>= 2; diff --git a/arch/ia64/include/asm/tlb.h b/arch/ia64/include/asm/tlb.h index c3ffe3e54ed..ef3a9de0195 100644 --- a/arch/ia64/include/asm/tlb.h +++ b/arch/ia64/include/asm/tlb.h @@ -46,12 +46,6 @@ #include <asm/tlbflush.h> #include <asm/machvec.h> -#ifdef CONFIG_SMP -# define tlb_fast_mode(tlb) ((tlb)->nr == ~0U) -#else -# define tlb_fast_mode(tlb) (1) -#endif - /* * If we can't allocate a page to make a big batch of page pointers * to work on, then just handle a few from the on-stack structure. @@ -60,7 +54,7 @@ struct mmu_gather { struct mm_struct *mm; - unsigned int nr; /* == ~0U => fast mode */ + unsigned int nr; unsigned int max; unsigned char fullmm; /* non-zero means full mm flush */ unsigned char need_flush; /* really unmapped some PTEs? */ @@ -103,6 +97,7 @@ extern struct ia64_tr_entry *ia64_idtrs[NR_CPUS]; static inline void ia64_tlb_flush_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end) { + unsigned long i; unsigned int nr; if (!tlb->need_flush) @@ -141,13 +136,11 @@ ia64_tlb_flush_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long e /* lastly, release the freed pages */ nr = tlb->nr; - if (!tlb_fast_mode(tlb)) { - unsigned long i; - tlb->nr = 0; - tlb->start_addr = ~0UL; - for (i = 0; i < nr; ++i) - free_page_and_swap_cache(tlb->pages[i]); - } + + tlb->nr = 0; + tlb->start_addr = ~0UL; + for (i = 0; i < nr; ++i) + free_page_and_swap_cache(tlb->pages[i]); } static inline void __tlb_alloc_page(struct mmu_gather *tlb) @@ -167,20 +160,7 @@ tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned int full_m tlb->mm = mm; tlb->max = ARRAY_SIZE(tlb->local); tlb->pages = tlb->local; - /* - * Use fast mode if only 1 CPU is online. - * - * It would be tempting to turn on fast-mode for full_mm_flush as well. But this - * doesn't work because of speculative accesses and software prefetching: the page - * table of "mm" may (and usually is) the currently active page table and even - * though the kernel won't do any user-space accesses during the TLB shoot down, a - * compiler might use speculation or lfetch.fault on what happens to be a valid - * user-space address. This in turn could trigger a TLB miss fault (or a VHPT - * walk) and re-insert a TLB entry we just removed. Slow mode avoids such - * problems. (We could make fast-mode work by switching the current task to a - * different "mm" during the shootdown.) --davidm 08/02/2002 - */ - tlb->nr = (num_online_cpus() == 1) ? ~0U : 0; + tlb->nr = 0; tlb->fullmm = full_mm_flush; tlb->start_addr = ~0UL; } @@ -214,11 +194,6 @@ static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page) { tlb->need_flush = 1; - if (tlb_fast_mode(tlb)) { - free_page_and_swap_cache(page); - return 1; /* avoid calling tlb_flush_mmu */ - } - if (!tlb->nr && tlb->pages == tlb->local) __tlb_alloc_page(tlb); diff --git a/arch/m68k/configs/amiga_defconfig b/arch/m68k/configs/amiga_defconfig index 90d3109c82f..19325e117ee 100644 --- a/arch/m68k/configs/amiga_defconfig +++ b/arch/m68k/configs/amiga_defconfig @@ -1,55 +1,78 @@ -CONFIG_EXPERIMENTAL=y CONFIG_LOCALVERSION="-amiga" CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_RELAY=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_AMIGA=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_SUN_PARTITION=y +# CONFIG_EFI_PARTITION is not set +CONFIG_SYSV68_PARTITION=y +CONFIG_IOSCHED_DEADLINE=m CONFIG_M68020=y CONFIG_M68030=y CONFIG_M68040=y CONFIG_M68060=y -CONFIG_BINFMT_AOUT=m -CONFIG_BINFMT_MISC=m +CONFIG_AMIGA=y CONFIG_ZORRO=y CONFIG_AMIGA_PCMCIA=y -CONFIG_HEARTBEAT=y -CONFIG_PROC_HARDWARE=y CONFIG_ZORRO_NAMES=y +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m CONFIG_NET=y CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_XFRM_MIGRATE=y CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set # CONFIG_NF_CT_PROTO_DCCP is not set CONFIG_NF_CT_PROTO_UDPLITE=m CONFIG_NF_CONNTRACK_AMANDA=m @@ -57,25 +80,37 @@ CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m CONFIG_NF_CONNTRACK_IRC=m CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m CONFIG_NF_CONNTRACK_PPTP=m CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m CONFIG_NETFILTER_XT_MATCH_CLUSTER=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m @@ -86,6 +121,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m @@ -99,22 +136,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m +CONFIG_NF_NAT_IPV4=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m @@ -124,7 +170,6 @@ CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -133,18 +178,30 @@ CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m +CONFIG_NF_NAT_IPV6=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m CONFIG_IP_DCCP=m # CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m CONFIG_ATALK=m +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_DAT=y +# CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y # CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FW_LOADER_USER_HELPER is not set CONFIG_CONNECTOR=m CONFIG_PARPORT=m CONFIG_PARPORT_AMIGA=m @@ -154,11 +211,13 @@ CONFIG_AMIGA_FLOPPY=y CONFIG_AMIGA_Z2RAM=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_CDROM_PKTCDVD=m CONFIG_ATA_OVER_ETH=m CONFIG_IDE=y +CONFIG_IDE_GD_ATAPI=y CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_GAYLE=y CONFIG_BLK_DEV_BUDDHA=y @@ -172,57 +231,77 @@ CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=m CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_SAS_LIBSAS=m -# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set -CONFIG_SCSI_SRP_ATTRS=m -CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_SCSI_SAS_ATTRS=m CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m CONFIG_A3000_SCSI=y CONFIG_A2091_SCSI=y CONFIG_GVP11_SCSI=y CONFIG_SCSI_A4000T=y CONFIG_SCSI_ZORRO7XX=y CONFIG_MD=y -CONFIG_BLK_DEV_MD=m CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID456=m CONFIG_BLK_DEV_DM=m CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m CONFIG_DM_UEVENT=y +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m CONFIG_NETDEVICES=y CONFIG_DUMMY=m -CONFIG_MACVLAN=m CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_VXLAN=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_VETH=m -CONFIG_NET_ETHERNET=y -CONFIG_ARIADNE=y +# CONFIG_NET_VENDOR_3COM is not set CONFIG_A2065=y +CONFIG_ARIADNE=y +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FUJITSU is not set +# CONFIG_NET_VENDOR_HP is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set CONFIG_HYDRA=y -CONFIG_ZORRO8390=y CONFIG_APNE=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +CONFIG_ZORRO8390=y +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set CONFIG_PPP=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m CONFIG_SLIP=m CONFIG_SLIP_COMPRESSED=y CONFIG_SLIP_SMART=y CONFIG_SLIP_MODE_SLIP6=y -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m CONFIG_KEYBOARD_AMIGA=y # CONFIG_KEYBOARD_ATKBD is not set # CONFIG_MOUSE_PS2 is not set @@ -233,11 +312,14 @@ CONFIG_INPUT_MISC=y CONFIG_INPUT_M68K_BEEP=m # CONFIG_SERIO is not set CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set # CONFIG_DEVKMEM is not set CONFIG_PRINTER=m # CONFIG_HW_RANDOM is not set -CONFIG_GEN_RTC=m -CONFIG_GEN_RTC_X=y +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_PARPORT=m +CONFIG_PTP_1588_CLOCK=m # CONFIG_HWMON is not set CONFIG_FB=y CONFIG_FB_CIRRUS=y @@ -252,48 +334,64 @@ CONFIG_SOUND=m CONFIG_DMASOUND_PAULA=m CONFIG_HID=m CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set # CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MSM6242=m +CONFIG_RTC_DRV_RP5C01=m +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_HEARTBEAT=y +CONFIG_PROC_HARDWARE=y CONFIG_AMIGA_BUILTIN_SERIAL=y CONFIG_SERIAL_CONSOLE=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set # CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y CONFIG_REISERFS_FS=m CONFIG_JFS_FS=m CONFIG_XFS_FS=m CONFIG_OCFS2_FS=m -# CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m +CONFIG_CUSE=m CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y +CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y CONFIG_HFS_FS=m CONFIG_HFSPLUS_FS=m CONFIG_CRAMFS=m CONFIG_SQUASHFS=m -CONFIG_MINIX_FS=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +CONFIG_ROOT_NFS=y CONFIG_NFSD=m CONFIG_NFSD_V3=y -CONFIG_SMB_FS=m -CONFIG_SMB_NLS_DEFAULT=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set CONFIG_CODA_FS=m CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_737=m @@ -332,10 +430,23 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m CONFIG_DLM=m CONFIG_MAGIC_SYSRQ=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_TEST=m @@ -345,19 +456,16 @@ CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_VMAC=m CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_RMD256=m CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_AES=m CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAMELLIA=m @@ -373,6 +481,14 @@ CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_ZLIB=m CONFIG_CRYPTO_LZO=m # CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m # CONFIG_CRYPTO_HW is not set -CONFIG_CRC16=m CONFIG_CRC_T10DIF=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_TEST=m diff --git a/arch/m68k/configs/apollo_defconfig b/arch/m68k/configs/apollo_defconfig index 8f4f657fdbc..14dc6ccda7f 100644 --- a/arch/m68k/configs/apollo_defconfig +++ b/arch/m68k/configs/apollo_defconfig @@ -1,55 +1,76 @@ -CONFIG_EXPERIMENTAL=y CONFIG_LOCALVERSION="-apollo" CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_RELAY=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_APOLLO=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_SUN_PARTITION=y +# CONFIG_EFI_PARTITION is not set +CONFIG_SYSV68_PARTITION=y +CONFIG_IOSCHED_DEADLINE=m CONFIG_M68020=y CONFIG_M68030=y CONFIG_M68040=y CONFIG_M68060=y +CONFIG_APOLLO=y +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m -CONFIG_HEARTBEAT=y -CONFIG_PROC_HARDWARE=y CONFIG_NET=y CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_XFRM_MIGRATE=y CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set # CONFIG_NF_CT_PROTO_DCCP is not set CONFIG_NF_CT_PROTO_UDPLITE=m CONFIG_NF_CONNTRACK_AMANDA=m @@ -57,25 +78,37 @@ CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m CONFIG_NF_CONNTRACK_IRC=m CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m CONFIG_NF_CONNTRACK_PPTP=m CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m CONFIG_NETFILTER_XT_MATCH_CLUSTER=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m @@ -86,6 +119,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m @@ -99,22 +134,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m +CONFIG_NF_NAT_IPV4=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m @@ -124,7 +168,6 @@ CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -133,21 +176,34 @@ CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m +CONFIG_NF_NAT_IPV6=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m CONFIG_IP_DCCP=m # CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m CONFIG_ATALK=m +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_DAT=y +# CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y # CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FW_LOADER_USER_HELPER is not set CONFIG_CONNECTOR=m CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_CDROM_PKTCDVD=m @@ -162,57 +218,74 @@ CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=m CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_SAS_LIBSAS=m -# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set -CONFIG_SCSI_SRP_ATTRS=m -CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_SCSI_SAS_ATTRS=m CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m CONFIG_MD=y -CONFIG_BLK_DEV_MD=m CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID456=m CONFIG_BLK_DEV_DM=m CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m CONFIG_DM_UEVENT=y +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m CONFIG_NETDEVICES=y CONFIG_DUMMY=m -CONFIG_MACVLAN=m CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_VXLAN=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_VETH=m -CONFIG_NET_ETHERNET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set CONFIG_PPP=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m CONFIG_SLIP=m CONFIG_SLIP_COMPRESSED=y CONFIG_SLIP_SMART=y CONFIG_SLIP_MODE_SLIP6=y -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m # CONFIG_KEYBOARD_ATKBD is not set -CONFIG_MOUSE_PS2=m +# CONFIG_MOUSE_PS2 is not set CONFIG_MOUSE_SERIAL=m CONFIG_SERIO=m -# CONFIG_SERIO_SERPORT is not set CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set # CONFIG_DEVKMEM is not set # CONFIG_HW_RANDOM is not set -CONFIG_GEN_RTC=m -CONFIG_GEN_RTC_X=y +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PTP_1588_CLOCK=m # CONFIG_HWMON is not set CONFIG_FB=y CONFIG_FRAMEBUFFER_CONSOLE=y @@ -221,47 +294,61 @@ CONFIG_LOGO=y # CONFIG_LOGO_LINUX_CLUT224 is not set CONFIG_HID=m CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set # CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_HEARTBEAT=y +CONFIG_PROC_HARDWARE=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set # CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y CONFIG_REISERFS_FS=m CONFIG_JFS_FS=m CONFIG_XFS_FS=m CONFIG_OCFS2_FS=m -# CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m +CONFIG_CUSE=m CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y +CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y CONFIG_HFS_FS=m CONFIG_HFSPLUS_FS=m CONFIG_CRAMFS=m CONFIG_SQUASHFS=m -CONFIG_MINIX_FS=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y CONFIG_ROOT_NFS=y CONFIG_NFSD=m CONFIG_NFSD_V3=y -CONFIG_SMB_FS=m -CONFIG_SMB_NLS_DEFAULT=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set CONFIG_CODA_FS=m CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_737=m @@ -300,10 +387,23 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m CONFIG_DLM=m CONFIG_MAGIC_SYSRQ=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_TEST=m @@ -313,19 +413,16 @@ CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_VMAC=m CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_RMD256=m CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_AES=m CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAMELLIA=m @@ -341,6 +438,14 @@ CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_ZLIB=m CONFIG_CRYPTO_LZO=m # CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m # CONFIG_CRYPTO_HW is not set -CONFIG_CRC16=m CONFIG_CRC_T10DIF=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_TEST=m diff --git a/arch/m68k/configs/atari_defconfig b/arch/m68k/configs/atari_defconfig index 4571d33903f..6d5370c914b 100644 --- a/arch/m68k/configs/atari_defconfig +++ b/arch/m68k/configs/atari_defconfig @@ -1,53 +1,75 @@ -CONFIG_EXPERIMENTAL=y CONFIG_LOCALVERSION="-atari" CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_RELAY=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_ATARI=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_SUN_PARTITION=y +# CONFIG_EFI_PARTITION is not set +CONFIG_SYSV68_PARTITION=y +CONFIG_IOSCHED_DEADLINE=m CONFIG_M68020=y CONFIG_M68030=y CONFIG_M68040=y CONFIG_M68060=y +CONFIG_ATARI=y +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m -CONFIG_STRAM_PROC=y -CONFIG_HEARTBEAT=y -CONFIG_PROC_HARDWARE=y CONFIG_NET=y CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_XFRM_MIGRATE=y CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set # CONFIG_NF_CT_PROTO_DCCP is not set CONFIG_NF_CT_PROTO_UDPLITE=m CONFIG_NF_CONNTRACK_AMANDA=m @@ -55,25 +77,37 @@ CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m CONFIG_NF_CONNTRACK_IRC=m CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m CONFIG_NF_CONNTRACK_PPTP=m CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m CONFIG_NETFILTER_XT_MATCH_CLUSTER=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m @@ -84,6 +118,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m @@ -97,22 +133,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m +CONFIG_NF_NAT_IPV4=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m @@ -122,7 +167,6 @@ CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -131,18 +175,30 @@ CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m +CONFIG_NF_NAT_IPV6=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m CONFIG_IP_DCCP=m # CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m CONFIG_ATALK=m +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_DAT=y +# CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y # CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FW_LOADER_USER_HELPER is not set CONFIG_CONNECTOR=m CONFIG_PARPORT=m CONFIG_PARPORT_ATARI=m @@ -150,11 +206,13 @@ CONFIG_PARPORT_1284=y CONFIG_ATARI_FLOPPY=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_CDROM_PKTCDVD=m CONFIG_ATA_OVER_ETH=m CONFIG_IDE=y +CONFIG_IDE_GD_ATAPI=y CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_FALCON_IDE=y CONFIG_RAID_ATTRS=m @@ -167,63 +225,81 @@ CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=m CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_SAS_LIBSAS=m -# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set -CONFIG_SCSI_SRP_ATTRS=m -CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_SCSI_SAS_ATTRS=m CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m CONFIG_ATARI_SCSI=y CONFIG_MD=y -CONFIG_BLK_DEV_MD=m CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID456=m CONFIG_BLK_DEV_DM=m CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m CONFIG_DM_UEVENT=y +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m CONFIG_NETDEVICES=y CONFIG_DUMMY=m -CONFIG_MACVLAN=m CONFIG_EQUALIZER=m -CONFIG_VETH=m -CONFIG_NET_ETHERNET=y CONFIG_MII=y +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_VXLAN=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_VETH=m CONFIG_ATARILANCE=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set CONFIG_PPP=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m CONFIG_SLIP=m CONFIG_SLIP_COMPRESSED=y CONFIG_SLIP_SMART=y CONFIG_SLIP_MODE_SLIP6=y -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m CONFIG_KEYBOARD_ATARI=y # CONFIG_KEYBOARD_ATKBD is not set -CONFIG_MOUSE_PS2=m +# CONFIG_MOUSE_PS2 is not set CONFIG_MOUSE_ATARI=m CONFIG_INPUT_MISC=y CONFIG_INPUT_M68K_BEEP=m -# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO is not set CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set # CONFIG_DEVKMEM is not set CONFIG_PRINTER=m # CONFIG_HW_RANDOM is not set -CONFIG_GEN_RTC=m -CONFIG_GEN_RTC_X=y +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_PARPORT=m +CONFIG_PTP_1588_CLOCK=m # CONFIG_HWMON is not set CONFIG_FB=y CONFIG_FB_ATARI=y @@ -233,47 +309,64 @@ CONFIG_SOUND=m CONFIG_DMASOUND_ATARI=m CONFIG_HID=m CONFIG_HIDRAW=y -# CONFIG_USB_SUPPORT is not set +CONFIG_UHID=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_HEARTBEAT=y +CONFIG_PROC_HARDWARE=y +CONFIG_NATFEAT=y +CONFIG_NFBLOCK=y +CONFIG_NFCON=y +CONFIG_NFETH=y CONFIG_ATARI_DSP56K=m CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set # CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y CONFIG_REISERFS_FS=m CONFIG_JFS_FS=m CONFIG_XFS_FS=m CONFIG_OCFS2_FS=m -# CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m +CONFIG_CUSE=m CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y +CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y CONFIG_HFS_FS=m CONFIG_HFSPLUS_FS=m CONFIG_CRAMFS=m CONFIG_SQUASHFS=m -CONFIG_MINIX_FS=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +CONFIG_ROOT_NFS=y CONFIG_NFSD=m CONFIG_NFSD_V3=y -CONFIG_SMB_FS=m -CONFIG_SMB_NLS_DEFAULT=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set CONFIG_CODA_FS=m CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_737=m @@ -312,10 +405,23 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m CONFIG_DLM=m CONFIG_MAGIC_SYSRQ=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_TEST=m @@ -325,19 +431,16 @@ CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_VMAC=m CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_RMD256=m CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_AES=m CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAMELLIA=m @@ -353,6 +456,14 @@ CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_ZLIB=m CONFIG_CRYPTO_LZO=m # CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m # CONFIG_CRYPTO_HW is not set -CONFIG_CRC16=y CONFIG_CRC_T10DIF=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_TEST=m diff --git a/arch/m68k/configs/bvme6000_defconfig b/arch/m68k/configs/bvme6000_defconfig index 12f211733ba..c015ddb6fd8 100644 --- a/arch/m68k/configs/bvme6000_defconfig +++ b/arch/m68k/configs/bvme6000_defconfig @@ -1,53 +1,74 @@ -CONFIG_EXPERIMENTAL=y CONFIG_LOCALVERSION="-bvme6000" CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_RELAY=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_VME=y -CONFIG_BVME6000=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_SUN_PARTITION=y +# CONFIG_EFI_PARTITION is not set +CONFIG_IOSCHED_DEADLINE=m CONFIG_M68040=y CONFIG_M68060=y +CONFIG_VME=y +CONFIG_BVME6000=y +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m -CONFIG_PROC_HARDWARE=y CONFIG_NET=y CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_XFRM_MIGRATE=y CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set # CONFIG_NF_CT_PROTO_DCCP is not set CONFIG_NF_CT_PROTO_UDPLITE=m CONFIG_NF_CONNTRACK_AMANDA=m @@ -55,25 +76,37 @@ CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m CONFIG_NF_CONNTRACK_IRC=m CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m CONFIG_NF_CONNTRACK_PPTP=m CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m CONFIG_NETFILTER_XT_MATCH_CLUSTER=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m @@ -84,6 +117,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m @@ -97,22 +132,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m +CONFIG_NF_NAT_IPV4=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m @@ -122,7 +166,6 @@ CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -131,21 +174,34 @@ CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m +CONFIG_NF_NAT_IPV6=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m CONFIG_IP_DCCP=m # CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m CONFIG_ATALK=m +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_DAT=y +# CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y # CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FW_LOADER_USER_HELPER is not set CONFIG_CONNECTOR=m CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_CDROM_PKTCDVD=m @@ -160,103 +216,131 @@ CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=m CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_SAS_LIBSAS=m -# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set -CONFIG_SCSI_SRP_ATTRS=m -CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_SCSI_SAS_ATTRS=m CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m CONFIG_BVME6000_SCSI=y CONFIG_MD=y -CONFIG_BLK_DEV_MD=m CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID456=m CONFIG_BLK_DEV_DM=m CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m CONFIG_DM_UEVENT=y +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m CONFIG_NETDEVICES=y CONFIG_DUMMY=m -CONFIG_MACVLAN=m CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_VXLAN=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_VETH=m -CONFIG_NET_ETHERNET=y +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set CONFIG_BVME6000_NET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set CONFIG_PPP=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m CONFIG_SLIP=m CONFIG_SLIP_COMPRESSED=y CONFIG_SLIP_SMART=y CONFIG_SLIP_MODE_SLIP6=y -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m # CONFIG_KEYBOARD_ATKBD is not set -CONFIG_MOUSE_PS2=m -CONFIG_MOUSE_SERIAL=m -CONFIG_SERIO=m -# CONFIG_SERIO_SERPORT is not set +# CONFIG_MOUSE_PS2 is not set +# CONFIG_SERIO is not set CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set # CONFIG_DEVKMEM is not set # CONFIG_HW_RANDOM is not set -CONFIG_GEN_RTC=m -CONFIG_GEN_RTC_X=y +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PTP_1588_CLOCK=m # CONFIG_HWMON is not set CONFIG_HID=m CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set # CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_PROC_HARDWARE=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set # CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y CONFIG_REISERFS_FS=m CONFIG_JFS_FS=m CONFIG_XFS_FS=m CONFIG_OCFS2_FS=m -# CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m +CONFIG_CUSE=m CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y +CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y CONFIG_HFS_FS=m CONFIG_HFSPLUS_FS=m CONFIG_CRAMFS=m CONFIG_SQUASHFS=m -CONFIG_MINIX_FS=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y CONFIG_ROOT_NFS=y CONFIG_NFSD=m CONFIG_NFSD_V3=y -CONFIG_SMB_FS=m -CONFIG_SMB_NLS_DEFAULT=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set CONFIG_CODA_FS=m CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_737=m @@ -295,10 +379,23 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m CONFIG_DLM=m CONFIG_MAGIC_SYSRQ=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_TEST=m @@ -308,19 +405,16 @@ CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_VMAC=m CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_RMD256=m CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_AES=m CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAMELLIA=m @@ -336,7 +430,14 @@ CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_ZLIB=m CONFIG_CRYPTO_LZO=m # CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m # CONFIG_CRYPTO_HW is not set -CONFIG_CRC16=m CONFIG_CRC_T10DIF=y -CONFIG_CRC32=m +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_TEST=m diff --git a/arch/m68k/configs/hp300_defconfig b/arch/m68k/configs/hp300_defconfig index 215389a5407..ec7382d8aff 100644 --- a/arch/m68k/configs/hp300_defconfig +++ b/arch/m68k/configs/hp300_defconfig @@ -1,54 +1,76 @@ -CONFIG_EXPERIMENTAL=y CONFIG_LOCALVERSION="-hp300" CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_RELAY=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_HP300=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_SUN_PARTITION=y +# CONFIG_EFI_PARTITION is not set +CONFIG_SYSV68_PARTITION=y +CONFIG_IOSCHED_DEADLINE=m CONFIG_M68020=y CONFIG_M68030=y CONFIG_M68040=y CONFIG_M68060=y +CONFIG_HP300=y +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m -CONFIG_PROC_HARDWARE=y CONFIG_NET=y CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_XFRM_MIGRATE=y CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set # CONFIG_NF_CT_PROTO_DCCP is not set CONFIG_NF_CT_PROTO_UDPLITE=m CONFIG_NF_CONNTRACK_AMANDA=m @@ -56,25 +78,37 @@ CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m CONFIG_NF_CONNTRACK_IRC=m CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m CONFIG_NF_CONNTRACK_PPTP=m CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m CONFIG_NETFILTER_XT_MATCH_CLUSTER=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m @@ -85,6 +119,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m @@ -98,22 +134,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m +CONFIG_NF_NAT_IPV4=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m @@ -123,7 +168,6 @@ CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -132,21 +176,34 @@ CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m +CONFIG_NF_NAT_IPV6=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m CONFIG_IP_DCCP=m # CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m CONFIG_ATALK=m +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_DAT=y +# CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y # CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FW_LOADER_USER_HELPER is not set CONFIG_CONNECTOR=m CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_CDROM_PKTCDVD=m @@ -161,59 +218,77 @@ CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=m CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_SAS_LIBSAS=m -# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set -CONFIG_SCSI_SRP_ATTRS=m -CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_SCSI_SAS_ATTRS=m CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m CONFIG_MD=y -CONFIG_BLK_DEV_MD=m CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID456=m CONFIG_BLK_DEV_DM=m CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m CONFIG_DM_UEVENT=y +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m CONFIG_NETDEVICES=y CONFIG_DUMMY=m -CONFIG_MACVLAN=m CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_VXLAN=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_VETH=m -CONFIG_NET_ETHERNET=y CONFIG_HPLANCE=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set CONFIG_PPP=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m CONFIG_SLIP=m CONFIG_SLIP_COMPRESSED=y CONFIG_SLIP_SMART=y CONFIG_SLIP_MODE_SLIP6=y -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m # CONFIG_KEYBOARD_ATKBD is not set -CONFIG_MOUSE_PS2=m +# CONFIG_MOUSE_PS2 is not set CONFIG_MOUSE_SERIAL=m CONFIG_INPUT_MISC=y CONFIG_HP_SDC_RTC=m -# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_SERPORT=m CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set # CONFIG_DEVKMEM is not set # CONFIG_HW_RANDOM is not set -CONFIG_GEN_RTC=m -CONFIG_GEN_RTC_X=y +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PTP_1588_CLOCK=m # CONFIG_HWMON is not set CONFIG_FB=y CONFIG_FRAMEBUFFER_CONSOLE=y @@ -222,47 +297,60 @@ CONFIG_LOGO=y # CONFIG_LOGO_LINUX_VGA16 is not set CONFIG_HID=m CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set # CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_PROC_HARDWARE=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set # CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y CONFIG_REISERFS_FS=m CONFIG_JFS_FS=m CONFIG_XFS_FS=m CONFIG_OCFS2_FS=m -# CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m +CONFIG_CUSE=m CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y +CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y CONFIG_HFS_FS=m CONFIG_HFSPLUS_FS=m CONFIG_CRAMFS=m CONFIG_SQUASHFS=m -CONFIG_MINIX_FS=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y CONFIG_ROOT_NFS=y CONFIG_NFSD=m CONFIG_NFSD_V3=y -CONFIG_SMB_FS=m -CONFIG_SMB_NLS_DEFAULT=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set CONFIG_CODA_FS=m CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_737=m @@ -301,10 +389,23 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m CONFIG_DLM=m CONFIG_MAGIC_SYSRQ=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_TEST=m @@ -314,19 +415,16 @@ CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_VMAC=m CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_RMD256=m CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_AES=m CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAMELLIA=m @@ -342,6 +440,14 @@ CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_ZLIB=m CONFIG_CRYPTO_LZO=m # CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m # CONFIG_CRYPTO_HW is not set -CONFIG_CRC16=m CONFIG_CRC_T10DIF=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_TEST=m diff --git a/arch/m68k/configs/mac_defconfig b/arch/m68k/configs/mac_defconfig index cb9dfb30b67..7d46fbec704 100644 --- a/arch/m68k/configs/mac_defconfig +++ b/arch/m68k/configs/mac_defconfig @@ -1,49 +1,75 @@ -CONFIG_EXPERIMENTAL=y CONFIG_LOCALVERSION="-mac" CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_RELAY=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_MAC=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_SUN_PARTITION=y +# CONFIG_EFI_PARTITION is not set +CONFIG_SYSV68_PARTITION=y +CONFIG_IOSCHED_DEADLINE=m CONFIG_M68020=y CONFIG_M68030=y CONFIG_M68040=y +CONFIG_M68KFPU_EMU=y +CONFIG_MAC=y +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m -CONFIG_PROC_HARDWARE=y CONFIG_NET=y CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_XFRM_MIGRATE=y CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set # CONFIG_NF_CT_PROTO_DCCP is not set CONFIG_NF_CT_PROTO_UDPLITE=m CONFIG_NF_CONNTRACK_AMANDA=m @@ -51,25 +77,37 @@ CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m CONFIG_NF_CONNTRACK_IRC=m CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m CONFIG_NF_CONNTRACK_PPTP=m CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m CONFIG_NETFILTER_XT_MATCH_CLUSTER=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m @@ -80,6 +118,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m @@ -93,22 +133,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m +CONFIG_NF_NAT_IPV4=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m @@ -118,7 +167,6 @@ CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -127,31 +175,45 @@ CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m +CONFIG_NF_NAT_IPV6=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m CONFIG_IP_DCCP=m # CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m CONFIG_ATALK=m CONFIG_DEV_APPLETALK=m CONFIG_IPDDP=m CONFIG_IPDDP_ENCAP=y CONFIG_IPDDP_DECAP=y +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_DAT=y +# CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y # CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FW_LOADER_USER_HELPER is not set CONFIG_CONNECTOR=m -CONFIG_BLK_DEV_SWIM=y +CONFIG_BLK_DEV_SWIM=m CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_CDROM_PKTCDVD=m CONFIG_ATA_OVER_ETH=m CONFIG_IDE=y +CONFIG_IDE_GD_ATAPI=y CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_MAC_IDE=y CONFIG_RAID_ATTRS=m @@ -164,29 +226,30 @@ CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=m CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_SAS_LIBSAS=m -# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set -CONFIG_SCSI_SRP_ATTRS=m -CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_SCSI_SAS_ATTRS=m CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m CONFIG_MAC_SCSI=y CONFIG_SCSI_MAC_ESP=y CONFIG_MD=y -CONFIG_BLK_DEV_MD=m CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID456=m CONFIG_BLK_DEV_DM=m CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m CONFIG_DM_UEVENT=y +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m CONFIG_ADB=y CONFIG_ADB_MACII=y -CONFIG_ADB_MACIISI=y CONFIG_ADB_IOP=y CONFIG_ADB_PMU68K=y CONFIG_ADB_CUDA=y @@ -194,46 +257,61 @@ CONFIG_INPUT_ADBHID=y CONFIG_MAC_EMUMOUSEBTN=y CONFIG_NETDEVICES=y CONFIG_DUMMY=m -CONFIG_MACVLAN=m CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_VXLAN=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_VETH=m -CONFIG_NET_ETHERNET=y -CONFIG_MAC8390=y -CONFIG_MAC89x0=m -CONFIG_MACSONIC=m CONFIG_MACMACE=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +CONFIG_MAC89x0=y +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +CONFIG_MACSONIC=y +CONFIG_MAC8390=y +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set CONFIG_PPP=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m CONFIG_SLIP=m CONFIG_SLIP_COMPRESSED=y CONFIG_SLIP_SMART=y CONFIG_SLIP_MODE_SLIP6=y -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m # CONFIG_KEYBOARD_ATKBD is not set -CONFIG_MOUSE_PS2=m +# CONFIG_MOUSE_PS2 is not set CONFIG_MOUSE_SERIAL=m CONFIG_INPUT_MISC=y CONFIG_INPUT_M68K_BEEP=m CONFIG_SERIO=m -# CONFIG_SERIO_SERPORT is not set CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set # CONFIG_DEVKMEM is not set CONFIG_SERIAL_PMACZILOG=y CONFIG_SERIAL_PMACZILOG_TTYS=y CONFIG_SERIAL_PMACZILOG_CONSOLE=y # CONFIG_HW_RANDOM is not set -CONFIG_GEN_RTC=m -CONFIG_GEN_RTC_X=y +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PTP_1588_CLOCK=m # CONFIG_HWMON is not set CONFIG_FB=y CONFIG_FB_VALKYRIE=y @@ -242,46 +320,60 @@ CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y CONFIG_HID=m CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set # CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_PROC_HARDWARE=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set # CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y CONFIG_REISERFS_FS=m CONFIG_JFS_FS=m CONFIG_XFS_FS=m CONFIG_OCFS2_FS=m -# CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m +CONFIG_CUSE=m CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y +CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_AFFS_FS=m -CONFIG_HFS_FS=y -CONFIG_HFSPLUS_FS=y +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m CONFIG_CRAMFS=m CONFIG_SQUASHFS=m -CONFIG_MINIX_FS=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m CONFIG_SYSV_FS=m CONFIG_UFS_FS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y +CONFIG_NFS_FS=y CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +CONFIG_ROOT_NFS=y CONFIG_NFSD=m CONFIG_NFSD_V3=y -CONFIG_SMB_FS=m -CONFIG_SMB_NLS_DEFAULT=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set CONFIG_CODA_FS=m CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_737=m @@ -320,10 +412,23 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m CONFIG_DLM=m CONFIG_MAGIC_SYSRQ=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_TEST=m @@ -333,19 +438,16 @@ CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_VMAC=m CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_RMD256=m CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_AES=m CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAMELLIA=m @@ -361,6 +463,14 @@ CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_ZLIB=m CONFIG_CRYPTO_LZO=m # CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m # CONFIG_CRYPTO_HW is not set -CONFIG_CRC16=m CONFIG_CRC_T10DIF=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_TEST=m diff --git a/arch/m68k/configs/multi_defconfig b/arch/m68k/configs/multi_defconfig index 8d5def4a31e..0f795d8e65f 100644 --- a/arch/m68k/configs/multi_defconfig +++ b/arch/m68k/configs/multi_defconfig @@ -1,15 +1,29 @@ -CONFIG_EXPERIMENTAL=y CONFIG_LOCALVERSION="-multi" CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_RELAY=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +# CONFIG_EFI_PARTITION is not set +CONFIG_IOSCHED_DEADLINE=m +CONFIG_M68020=y +CONFIG_M68040=y +CONFIG_M68060=y +CONFIG_M68KFPU_EMU=y CONFIG_AMIGA=y CONFIG_ATARI=y CONFIG_MAC=y @@ -21,48 +35,50 @@ CONFIG_BVME6000=y CONFIG_HP300=y CONFIG_SUN3X=y CONFIG_Q40=y -CONFIG_M68020=y -CONFIG_M68040=y -CONFIG_M68060=y -CONFIG_BINFMT_AOUT=m -CONFIG_BINFMT_MISC=m CONFIG_ZORRO=y CONFIG_AMIGA_PCMCIA=y -CONFIG_STRAM_PROC=y -CONFIG_HEARTBEAT=y -CONFIG_PROC_HARDWARE=y CONFIG_ZORRO_NAMES=y +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m CONFIG_NET=y CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_XFRM_MIGRATE=y CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set # CONFIG_NF_CT_PROTO_DCCP is not set CONFIG_NF_CT_PROTO_UDPLITE=m CONFIG_NF_CONNTRACK_AMANDA=m @@ -70,25 +86,37 @@ CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m CONFIG_NF_CONNTRACK_IRC=m CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m CONFIG_NF_CONNTRACK_PPTP=m CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m CONFIG_NETFILTER_XT_MATCH_CLUSTER=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m @@ -99,6 +127,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m @@ -112,22 +142,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m +CONFIG_NF_NAT_IPV4=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m @@ -137,7 +176,6 @@ CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -146,22 +184,34 @@ CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m +CONFIG_NF_NAT_IPV6=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m CONFIG_IP_DCCP=m # CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m CONFIG_ATALK=m CONFIG_DEV_APPLETALK=m CONFIG_IPDDP=m CONFIG_IPDDP_ENCAP=y CONFIG_IPDDP_DECAP=y +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_DAT=y +# CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y # CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FW_LOADER_USER_HELPER is not set CONFIG_CONNECTOR=m CONFIG_PARPORT=m CONFIG_PARPORT_AMIGA=m @@ -170,15 +220,17 @@ CONFIG_PARPORT_ATARI=m CONFIG_PARPORT_1284=y CONFIG_AMIGA_FLOPPY=y CONFIG_ATARI_FLOPPY=y -CONFIG_BLK_DEV_SWIM=y +CONFIG_BLK_DEV_SWIM=m CONFIG_AMIGA_Z2RAM=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_CDROM_PKTCDVD=m CONFIG_ATA_OVER_ETH=m CONFIG_IDE=y +CONFIG_IDE_GD_ATAPI=y CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_GAYLE=y CONFIG_BLK_DEV_BUDDHA=y @@ -195,11 +247,9 @@ CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=m CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_SAS_LIBSAS=m -# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set -CONFIG_SCSI_SRP_ATTRS=m -CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_SCSI_SAS_ATTRS=m CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m CONFIG_A3000_SCSI=y CONFIG_A2091_SCSI=y CONFIG_GVP11_SCSI=y @@ -213,21 +263,24 @@ CONFIG_MVME16x_SCSI=y CONFIG_BVME6000_SCSI=y CONFIG_SUN3X_ESP=y CONFIG_MD=y -CONFIG_BLK_DEV_MD=m CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID456=m CONFIG_BLK_DEV_DM=m CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m CONFIG_DM_UEVENT=y +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m CONFIG_ADB=y CONFIG_ADB_MACII=y -CONFIG_ADB_MACIISI=y CONFIG_ADB_IOP=y CONFIG_ADB_PMU68K=y CONFIG_ADB_CUDA=y @@ -235,49 +288,64 @@ CONFIG_INPUT_ADBHID=y CONFIG_MAC_EMUMOUSEBTN=y CONFIG_NETDEVICES=y CONFIG_DUMMY=m -CONFIG_MACVLAN=m CONFIG_EQUALIZER=m -CONFIG_VETH=m -CONFIG_NET_ETHERNET=y CONFIG_MII=y -CONFIG_ARIADNE=y +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_VXLAN=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_VETH=m +# CONFIG_NET_VENDOR_3COM is not set CONFIG_A2065=y -CONFIG_HYDRA=y -CONFIG_ZORRO8390=y -CONFIG_APNE=y -CONFIG_MAC8390=y -CONFIG_MAC89x0=y -CONFIG_MACSONIC=y -CONFIG_MACMACE=y -CONFIG_MVME147_NET=y -CONFIG_MVME16x_NET=y -CONFIG_BVME6000_NET=y +CONFIG_ARIADNE=y CONFIG_ATARILANCE=y -CONFIG_SUN3LANCE=y CONFIG_HPLANCE=y +CONFIG_MVME147_NET=y +CONFIG_SUN3LANCE=y +CONFIG_MACMACE=y +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +CONFIG_MAC89x0=y +# CONFIG_NET_VENDOR_FUJITSU is not set +# CONFIG_NET_VENDOR_HP is not set +CONFIG_BVME6000_NET=y +CONFIG_MVME16x_NET=y +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +CONFIG_MACSONIC=y +CONFIG_HYDRA=y +CONFIG_MAC8390=y CONFIG_NE2000=m -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +CONFIG_APNE=y +CONFIG_ZORRO8390=y +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set CONFIG_PPP=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m CONFIG_SLIP=m CONFIG_SLIP_COMPRESSED=y CONFIG_SLIP_SMART=y CONFIG_SLIP_MODE_SLIP6=y -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m CONFIG_KEYBOARD_AMIGA=y CONFIG_KEYBOARD_ATARI=y # CONFIG_KEYBOARD_ATKBD is not set CONFIG_KEYBOARD_SUNKBD=y -CONFIG_MOUSE_PS2=m +# CONFIG_MOUSE_PS2 is not set CONFIG_MOUSE_SERIAL=m CONFIG_MOUSE_AMIGA=m CONFIG_MOUSE_ATARI=m @@ -285,18 +353,20 @@ CONFIG_INPUT_JOYSTICK=y CONFIG_JOYSTICK_AMIGA=m CONFIG_INPUT_MISC=y CONFIG_INPUT_M68K_BEEP=m -CONFIG_HP_SDC_RTC=y -# CONFIG_SERIO_SERPORT is not set +CONFIG_HP_SDC_RTC=m CONFIG_SERIO_Q40KBD=y CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set # CONFIG_DEVKMEM is not set CONFIG_SERIAL_PMACZILOG=y CONFIG_SERIAL_PMACZILOG_TTYS=y CONFIG_SERIAL_PMACZILOG_CONSOLE=y CONFIG_PRINTER=m # CONFIG_HW_RANDOM is not set -CONFIG_GEN_RTC=y -CONFIG_GEN_RTC_X=y +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_PARPORT=m +CONFIG_PTP_1588_CLOCK=m # CONFIG_HWMON is not set CONFIG_FB=y CONFIG_FB_CIRRUS=y @@ -316,7 +386,20 @@ CONFIG_DMASOUND_PAULA=m CONFIG_DMASOUND_Q40=m CONFIG_HID=m CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set # CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MSM6242=m +CONFIG_RTC_DRV_RP5C01=m +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_HEARTBEAT=y +CONFIG_PROC_HARDWARE=y +CONFIG_NATFEAT=y +CONFIG_NFBLOCK=y +CONFIG_NFCON=y +CONFIG_NFETH=y CONFIG_ATARI_DSP56K=m CONFIG_AMIGA_BUILTIN_SERIAL=y CONFIG_SERIAL_CONSOLE=y @@ -324,42 +407,49 @@ CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set # CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y CONFIG_REISERFS_FS=m CONFIG_JFS_FS=m CONFIG_XFS_FS=m CONFIG_OCFS2_FS=m -# CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m +CONFIG_CUSE=m CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y +CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_AFFS_FS=m -CONFIG_HFS_FS=y -CONFIG_HFSPLUS_FS=y +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m CONFIG_CRAMFS=m CONFIG_SQUASHFS=m -CONFIG_MINIX_FS=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y CONFIG_ROOT_NFS=y CONFIG_NFSD=m CONFIG_NFSD_V3=y -CONFIG_SMB_FS=m -CONFIG_SMB_NLS_DEFAULT=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set CONFIG_CODA_FS=m CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_737=m @@ -398,10 +488,23 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m CONFIG_DLM=m CONFIG_MAGIC_SYSRQ=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_TEST=m @@ -411,19 +514,16 @@ CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_VMAC=m CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_RMD256=m CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_AES=m CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAMELLIA=m @@ -439,6 +539,14 @@ CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_ZLIB=m CONFIG_CRYPTO_LZO=m # CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m # CONFIG_CRYPTO_HW is not set -CONFIG_CRC16=y CONFIG_CRC_T10DIF=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_TEST=m diff --git a/arch/m68k/configs/mvme147_defconfig b/arch/m68k/configs/mvme147_defconfig index e2af46f530c..5586c6529fc 100644 --- a/arch/m68k/configs/mvme147_defconfig +++ b/arch/m68k/configs/mvme147_defconfig @@ -1,52 +1,73 @@ -CONFIG_EXPERIMENTAL=y CONFIG_LOCALVERSION="-mvme147" CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_RELAY=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_SUN_PARTITION=y +# CONFIG_EFI_PARTITION is not set +CONFIG_IOSCHED_DEADLINE=m +CONFIG_M68030=y CONFIG_VME=y CONFIG_MVME147=y -CONFIG_M68030=y +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m -CONFIG_PROC_HARDWARE=y CONFIG_NET=y CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_XFRM_MIGRATE=y CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set # CONFIG_NF_CT_PROTO_DCCP is not set CONFIG_NF_CT_PROTO_UDPLITE=m CONFIG_NF_CONNTRACK_AMANDA=m @@ -54,25 +75,37 @@ CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m CONFIG_NF_CONNTRACK_IRC=m CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m CONFIG_NF_CONNTRACK_PPTP=m CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m CONFIG_NETFILTER_XT_MATCH_CLUSTER=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m @@ -83,6 +116,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m @@ -96,22 +131,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m +CONFIG_NF_NAT_IPV4=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m @@ -121,7 +165,6 @@ CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -130,21 +173,34 @@ CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m +CONFIG_NF_NAT_IPV6=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m CONFIG_IP_DCCP=m # CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m CONFIG_ATALK=m +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_DAT=y +# CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y # CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FW_LOADER_USER_HELPER is not set CONFIG_CONNECTOR=m CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_CDROM_PKTCDVD=m @@ -159,103 +215,132 @@ CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=m CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_SAS_LIBSAS=m -# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set -CONFIG_SCSI_SRP_ATTRS=m -CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_SCSI_SAS_ATTRS=m CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m CONFIG_MVME147_SCSI=y CONFIG_MD=y -CONFIG_BLK_DEV_MD=m CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID456=m CONFIG_BLK_DEV_DM=m CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m CONFIG_DM_UEVENT=y +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m CONFIG_NETDEVICES=y CONFIG_DUMMY=m -CONFIG_MACVLAN=m CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_VXLAN=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_VETH=m -CONFIG_NET_ETHERNET=y CONFIG_MVME147_NET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set CONFIG_PPP=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m CONFIG_SLIP=m CONFIG_SLIP_COMPRESSED=y CONFIG_SLIP_SMART=y CONFIG_SLIP_MODE_SLIP6=y -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m # CONFIG_KEYBOARD_ATKBD is not set -CONFIG_MOUSE_PS2=m -CONFIG_MOUSE_SERIAL=m -CONFIG_SERIO=m -# CONFIG_SERIO_SERPORT is not set +# CONFIG_MOUSE_PS2 is not set +# CONFIG_SERIO is not set CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set # CONFIG_DEVKMEM is not set # CONFIG_HW_RANDOM is not set -CONFIG_GEN_RTC=m -CONFIG_GEN_RTC_X=y +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PTP_1588_CLOCK=m # CONFIG_HWMON is not set CONFIG_HID=m CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set # CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_PROC_HARDWARE=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set # CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y CONFIG_REISERFS_FS=m CONFIG_JFS_FS=m CONFIG_XFS_FS=m CONFIG_OCFS2_FS=m -# CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m +CONFIG_CUSE=m CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y +CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y CONFIG_HFS_FS=m CONFIG_HFSPLUS_FS=m CONFIG_CRAMFS=m CONFIG_SQUASHFS=m -CONFIG_MINIX_FS=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y CONFIG_ROOT_NFS=y CONFIG_NFSD=m CONFIG_NFSD_V3=y -CONFIG_SMB_FS=m -CONFIG_SMB_NLS_DEFAULT=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set CONFIG_CODA_FS=m CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_737=m @@ -294,10 +379,23 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m CONFIG_DLM=m CONFIG_MAGIC_SYSRQ=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_TEST=m @@ -307,19 +405,16 @@ CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_VMAC=m CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_RMD256=m CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_AES=m CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAMELLIA=m @@ -335,6 +430,14 @@ CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_ZLIB=m CONFIG_CRYPTO_LZO=m # CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m # CONFIG_CRYPTO_HW is not set -CONFIG_CRC16=m CONFIG_CRC_T10DIF=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_TEST=m diff --git a/arch/m68k/configs/mvme16x_defconfig b/arch/m68k/configs/mvme16x_defconfig index 7c9402b2097..e5e8262bbac 100644 --- a/arch/m68k/configs/mvme16x_defconfig +++ b/arch/m68k/configs/mvme16x_defconfig @@ -1,53 +1,74 @@ -CONFIG_EXPERIMENTAL=y CONFIG_LOCALVERSION="-mvme16x" CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_RELAY=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_VME=y -CONFIG_MVME16x=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_SUN_PARTITION=y +# CONFIG_EFI_PARTITION is not set +CONFIG_IOSCHED_DEADLINE=m CONFIG_M68040=y CONFIG_M68060=y +CONFIG_VME=y +CONFIG_MVME16x=y +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m -CONFIG_PROC_HARDWARE=y CONFIG_NET=y CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_XFRM_MIGRATE=y CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set # CONFIG_NF_CT_PROTO_DCCP is not set CONFIG_NF_CT_PROTO_UDPLITE=m CONFIG_NF_CONNTRACK_AMANDA=m @@ -55,25 +76,37 @@ CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m CONFIG_NF_CONNTRACK_IRC=m CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m CONFIG_NF_CONNTRACK_PPTP=m CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m CONFIG_NETFILTER_XT_MATCH_CLUSTER=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m @@ -84,6 +117,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m @@ -97,22 +132,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m +CONFIG_NF_NAT_IPV4=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m @@ -122,7 +166,6 @@ CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -131,21 +174,34 @@ CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m +CONFIG_NF_NAT_IPV6=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m CONFIG_IP_DCCP=m # CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m CONFIG_ATALK=m +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_DAT=y +# CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y # CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FW_LOADER_USER_HELPER is not set CONFIG_CONNECTOR=m CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_CDROM_PKTCDVD=m @@ -160,103 +216,131 @@ CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=m CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_SAS_LIBSAS=m -# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set -CONFIG_SCSI_SRP_ATTRS=m -CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_SCSI_SAS_ATTRS=m CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m CONFIG_MVME16x_SCSI=y CONFIG_MD=y -CONFIG_BLK_DEV_MD=m CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID456=m CONFIG_BLK_DEV_DM=m CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m CONFIG_DM_UEVENT=y +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m CONFIG_NETDEVICES=y CONFIG_DUMMY=m -CONFIG_MACVLAN=m CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_VXLAN=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_VETH=m -CONFIG_NET_ETHERNET=y +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set CONFIG_MVME16x_NET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set CONFIG_PPP=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m CONFIG_SLIP=m CONFIG_SLIP_COMPRESSED=y CONFIG_SLIP_SMART=y CONFIG_SLIP_MODE_SLIP6=y -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m # CONFIG_KEYBOARD_ATKBD is not set -CONFIG_MOUSE_PS2=m -CONFIG_MOUSE_SERIAL=m -CONFIG_SERIO=m -# CONFIG_SERIO_SERPORT is not set +# CONFIG_MOUSE_PS2 is not set +# CONFIG_SERIO is not set CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set # CONFIG_DEVKMEM is not set # CONFIG_HW_RANDOM is not set -CONFIG_GEN_RTC=m -CONFIG_GEN_RTC_X=y +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PTP_1588_CLOCK=m # CONFIG_HWMON is not set CONFIG_HID=m CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set # CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_PROC_HARDWARE=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set # CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y CONFIG_REISERFS_FS=m CONFIG_JFS_FS=m CONFIG_XFS_FS=m CONFIG_OCFS2_FS=m -# CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m +CONFIG_CUSE=m CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y +CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y CONFIG_HFS_FS=m CONFIG_HFSPLUS_FS=m CONFIG_CRAMFS=m CONFIG_SQUASHFS=m -CONFIG_MINIX_FS=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y CONFIG_ROOT_NFS=y CONFIG_NFSD=m CONFIG_NFSD_V3=y -CONFIG_SMB_FS=m -CONFIG_SMB_NLS_DEFAULT=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set CONFIG_CODA_FS=m CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_737=m @@ -295,10 +379,23 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m CONFIG_DLM=m CONFIG_MAGIC_SYSRQ=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_TEST=m @@ -308,19 +405,16 @@ CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_VMAC=m CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_RMD256=m CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_AES=m CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAMELLIA=m @@ -336,6 +430,14 @@ CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_ZLIB=m CONFIG_CRYPTO_LZO=m # CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m # CONFIG_CRYPTO_HW is not set -CONFIG_CRC16=m CONFIG_CRC_T10DIF=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_TEST=m diff --git a/arch/m68k/configs/q40_defconfig b/arch/m68k/configs/q40_defconfig index 19d23db690a..8982370e8b4 100644 --- a/arch/m68k/configs/q40_defconfig +++ b/arch/m68k/configs/q40_defconfig @@ -1,49 +1,74 @@ -CONFIG_EXPERIMENTAL=y CONFIG_LOCALVERSION="-q40" CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_RELAY=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_Q40=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_SUN_PARTITION=y +# CONFIG_EFI_PARTITION is not set +CONFIG_SYSV68_PARTITION=y +CONFIG_IOSCHED_DEADLINE=m CONFIG_M68040=y CONFIG_M68060=y +CONFIG_Q40=y +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m -CONFIG_HEARTBEAT=y -CONFIG_PROC_HARDWARE=y CONFIG_NET=y CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_XFRM_MIGRATE=y CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set # CONFIG_NF_CT_PROTO_DCCP is not set CONFIG_NF_CT_PROTO_UDPLITE=m CONFIG_NF_CONNTRACK_AMANDA=m @@ -51,25 +76,37 @@ CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m CONFIG_NF_CONNTRACK_IRC=m CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m CONFIG_NF_CONNTRACK_PPTP=m CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m CONFIG_NETFILTER_XT_MATCH_CLUSTER=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m @@ -80,6 +117,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m @@ -93,22 +132,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m +CONFIG_NF_NAT_IPV4=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m @@ -118,7 +166,6 @@ CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -127,26 +174,40 @@ CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m +CONFIG_NF_NAT_IPV6=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m CONFIG_IP_DCCP=m # CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m CONFIG_ATALK=m +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_DAT=y +# CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y # CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FW_LOADER_USER_HELPER is not set CONFIG_CONNECTOR=m CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_CDROM_PKTCDVD=m CONFIG_ATA_OVER_ETH=m CONFIG_IDE=y +CONFIG_IDE_GD_ATAPI=y CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_Q40IDE=y CONFIG_RAID_ATTRS=m @@ -159,61 +220,82 @@ CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=m CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_SAS_LIBSAS=m -# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set -CONFIG_SCSI_SRP_ATTRS=m -CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_SCSI_SAS_ATTRS=m CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m CONFIG_MD=y -CONFIG_BLK_DEV_MD=m CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID456=m CONFIG_BLK_DEV_DM=m CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m CONFIG_DM_UEVENT=y +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m CONFIG_NETDEVICES=y CONFIG_DUMMY=m -CONFIG_MACVLAN=m CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_VXLAN=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_VETH=m -CONFIG_NET_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FUJITSU is not set +# CONFIG_NET_VENDOR_HP is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set CONFIG_NE2000=m -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set CONFIG_PPP=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m CONFIG_SLIP=m CONFIG_SLIP_COMPRESSED=y CONFIG_SLIP_SMART=y CONFIG_SLIP_MODE_SLIP6=y -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m # CONFIG_KEYBOARD_ATKBD is not set -CONFIG_MOUSE_PS2=m +# CONFIG_MOUSE_PS2 is not set CONFIG_MOUSE_SERIAL=m CONFIG_INPUT_MISC=y CONFIG_INPUT_M68K_BEEP=m -CONFIG_SERIO=m -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIO_Q40KBD=m +CONFIG_SERIO_Q40KBD=y CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set # CONFIG_DEVKMEM is not set # CONFIG_HW_RANDOM is not set -CONFIG_GEN_RTC=m -CONFIG_GEN_RTC_X=y +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PTP_1588_CLOCK=m # CONFIG_HWMON is not set CONFIG_FB=y CONFIG_FRAMEBUFFER_CONSOLE=y @@ -222,46 +304,61 @@ CONFIG_SOUND=m CONFIG_DMASOUND_Q40=m CONFIG_HID=m CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set # CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_HEARTBEAT=y +CONFIG_PROC_HARDWARE=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set # CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y CONFIG_REISERFS_FS=m CONFIG_JFS_FS=m CONFIG_XFS_FS=m CONFIG_OCFS2_FS=m -# CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m +CONFIG_CUSE=m CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y +CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y CONFIG_HFS_FS=m CONFIG_HFSPLUS_FS=m CONFIG_CRAMFS=m CONFIG_SQUASHFS=m -CONFIG_MINIX_FS=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +CONFIG_ROOT_NFS=y CONFIG_NFSD=m CONFIG_NFSD_V3=y -CONFIG_SMB_FS=m -CONFIG_SMB_NLS_DEFAULT=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set CONFIG_CODA_FS=m CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_737=m @@ -300,10 +397,23 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m CONFIG_DLM=m CONFIG_MAGIC_SYSRQ=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_TEST=m @@ -313,19 +423,16 @@ CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_VMAC=m CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_RMD256=m CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_AES=m CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAMELLIA=m @@ -341,6 +448,14 @@ CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_ZLIB=m CONFIG_CRYPTO_LZO=m # CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m # CONFIG_CRYPTO_HW is not set -CONFIG_CRC16=m CONFIG_CRC_T10DIF=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_TEST=m diff --git a/arch/m68k/configs/sun3_defconfig b/arch/m68k/configs/sun3_defconfig index ca6c0b4cab7..54674d61e00 100644 --- a/arch/m68k/configs/sun3_defconfig +++ b/arch/m68k/configs/sun3_defconfig @@ -1,50 +1,71 @@ -CONFIG_EXPERIMENTAL=y CONFIG_LOCALVERSION="-sun3" CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_RELAY=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +# CONFIG_EFI_PARTITION is not set +CONFIG_SYSV68_PARTITION=y +CONFIG_IOSCHED_DEADLINE=m CONFIG_SUN3=y +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m -CONFIG_PROC_HARDWARE=y CONFIG_NET=y CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_XFRM_MIGRATE=y CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set # CONFIG_NF_CT_PROTO_DCCP is not set CONFIG_NF_CT_PROTO_UDPLITE=m CONFIG_NF_CONNTRACK_AMANDA=m @@ -52,25 +73,37 @@ CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m CONFIG_NF_CONNTRACK_IRC=m CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m CONFIG_NF_CONNTRACK_PPTP=m CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m CONFIG_NETFILTER_XT_MATCH_CLUSTER=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m @@ -81,6 +114,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m @@ -94,22 +129,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m +CONFIG_NF_NAT_IPV4=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m @@ -119,7 +163,6 @@ CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -128,21 +171,34 @@ CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m +CONFIG_NF_NAT_IPV6=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m CONFIG_IP_DCCP=m # CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m CONFIG_ATALK=m +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_DAT=y +# CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y # CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FW_LOADER_USER_HELPER is not set CONFIG_CONNECTOR=m CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_CDROM_PKTCDVD=m @@ -157,107 +213,136 @@ CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=m CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_SAS_LIBSAS=m -# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set -CONFIG_SCSI_SRP_ATTRS=m -CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_SCSI_SAS_ATTRS=m CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m CONFIG_SUN3_SCSI=y CONFIG_MD=y -CONFIG_BLK_DEV_MD=m CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID456=m CONFIG_BLK_DEV_DM=m CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m CONFIG_DM_UEVENT=y +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m CONFIG_NETDEVICES=y CONFIG_DUMMY=m -CONFIG_MACVLAN=m CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_VXLAN=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_VETH=m -CONFIG_NET_ETHERNET=y CONFIG_SUN3LANCE=y +# CONFIG_NET_CADENCE is not set CONFIG_SUN3_82586=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_WIZNET is not set CONFIG_PPP=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m CONFIG_SLIP=m CONFIG_SLIP_COMPRESSED=y CONFIG_SLIP_SMART=y CONFIG_SLIP_MODE_SLIP6=y -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m # CONFIG_KEYBOARD_ATKBD is not set CONFIG_KEYBOARD_SUNKBD=y -CONFIG_MOUSE_PS2=m +# CONFIG_MOUSE_PS2 is not set CONFIG_MOUSE_SERIAL=m -# CONFIG_SERIO_SERPORT is not set CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set # CONFIG_DEVKMEM is not set # CONFIG_HW_RANDOM is not set -CONFIG_GEN_RTC=m -CONFIG_GEN_RTC_X=y +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PTP_1588_CLOCK=m # CONFIG_HWMON is not set CONFIG_FB=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y CONFIG_HID=m CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set # CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_PROC_HARDWARE=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set # CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y CONFIG_REISERFS_FS=m CONFIG_JFS_FS=m CONFIG_XFS_FS=m CONFIG_OCFS2_FS=m -# CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m +CONFIG_CUSE=m CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y +CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y CONFIG_HFS_FS=m CONFIG_HFSPLUS_FS=m CONFIG_CRAMFS=m CONFIG_SQUASHFS=m -CONFIG_MINIX_FS=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y CONFIG_ROOT_NFS=y CONFIG_NFSD=m CONFIG_NFSD_V3=y -CONFIG_SMB_FS=m -CONFIG_SMB_NLS_DEFAULT=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set CONFIG_CODA_FS=m CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_737=m @@ -296,10 +381,23 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m CONFIG_DLM=m CONFIG_MAGIC_SYSRQ=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_TEST=m @@ -309,19 +407,16 @@ CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_VMAC=m CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_RMD256=m CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_AES=m CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAMELLIA=m @@ -337,6 +432,14 @@ CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_ZLIB=m CONFIG_CRYPTO_LZO=m # CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m # CONFIG_CRYPTO_HW is not set -CONFIG_CRC16=m CONFIG_CRC_T10DIF=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_TEST=m diff --git a/arch/m68k/configs/sun3x_defconfig b/arch/m68k/configs/sun3x_defconfig index c80941c7759..832d9539f44 100644 --- a/arch/m68k/configs/sun3x_defconfig +++ b/arch/m68k/configs/sun3x_defconfig @@ -1,50 +1,71 @@ -CONFIG_EXPERIMENTAL=y CONFIG_LOCALVERSION="-sun3x" CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_RELAY=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +# CONFIG_EFI_PARTITION is not set +CONFIG_SYSV68_PARTITION=y +CONFIG_IOSCHED_DEADLINE=m CONFIG_SUN3X=y +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m -CONFIG_PROC_HARDWARE=y CONFIG_NET=y CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_XFRM_MIGRATE=y CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set # CONFIG_NF_CT_PROTO_DCCP is not set CONFIG_NF_CT_PROTO_UDPLITE=m CONFIG_NF_CONNTRACK_AMANDA=m @@ -52,25 +73,37 @@ CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m CONFIG_NF_CONNTRACK_IRC=m CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m CONFIG_NF_CONNTRACK_PPTP=m CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m CONFIG_NETFILTER_XT_MATCH_CLUSTER=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m @@ -81,6 +114,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m @@ -94,22 +129,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m +CONFIG_NF_NAT_IPV4=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m @@ -119,7 +163,6 @@ CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -128,21 +171,34 @@ CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m +CONFIG_NF_NAT_IPV6=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m CONFIG_IP_DCCP=m # CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m CONFIG_ATALK=m +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_DAT=y +# CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y # CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FW_LOADER_USER_HELPER is not set CONFIG_CONNECTOR=m CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_CDROM_PKTCDVD=m @@ -157,106 +213,136 @@ CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=m CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_SAS_LIBSAS=m -# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set -CONFIG_SCSI_SRP_ATTRS=m -CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_SCSI_SAS_ATTRS=m CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m CONFIG_SUN3X_ESP=y CONFIG_MD=y -CONFIG_BLK_DEV_MD=m CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID456=m CONFIG_BLK_DEV_DM=m CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m CONFIG_DM_UEVENT=y +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m CONFIG_NETDEVICES=y CONFIG_DUMMY=m -CONFIG_MACVLAN=m CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_VXLAN=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_VETH=m -CONFIG_NET_ETHERNET=y CONFIG_SUN3LANCE=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set CONFIG_PPP=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m CONFIG_SLIP=m CONFIG_SLIP_COMPRESSED=y CONFIG_SLIP_SMART=y CONFIG_SLIP_MODE_SLIP6=y -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m # CONFIG_KEYBOARD_ATKBD is not set CONFIG_KEYBOARD_SUNKBD=y -CONFIG_MOUSE_PS2=m +# CONFIG_MOUSE_PS2 is not set CONFIG_MOUSE_SERIAL=m -# CONFIG_SERIO_SERPORT is not set CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set # CONFIG_DEVKMEM is not set # CONFIG_HW_RANDOM is not set -CONFIG_GEN_RTC=m -CONFIG_GEN_RTC_X=y +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PTP_1588_CLOCK=m # CONFIG_HWMON is not set CONFIG_FB=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y CONFIG_HID=m CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set # CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_PROC_HARDWARE=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set # CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y CONFIG_REISERFS_FS=m CONFIG_JFS_FS=m CONFIG_XFS_FS=m CONFIG_OCFS2_FS=m -# CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m +CONFIG_CUSE=m CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y +CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y CONFIG_HFS_FS=m CONFIG_HFSPLUS_FS=m CONFIG_CRAMFS=m CONFIG_SQUASHFS=m -CONFIG_MINIX_FS=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y CONFIG_ROOT_NFS=y CONFIG_NFSD=m CONFIG_NFSD_V3=y -CONFIG_SMB_FS=m -CONFIG_SMB_NLS_DEFAULT=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set CONFIG_CODA_FS=m CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_737=m @@ -295,10 +381,23 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m CONFIG_DLM=m CONFIG_MAGIC_SYSRQ=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_TEST=m @@ -308,19 +407,16 @@ CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_VMAC=m CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_RMD256=m CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_AES=m CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAMELLIA=m @@ -336,6 +432,14 @@ CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_ZLIB=m CONFIG_CRYPTO_LZO=m # CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m # CONFIG_CRYPTO_HW is not set -CONFIG_CRC16=m CONFIG_CRC_T10DIF=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_TEST=m diff --git a/arch/m68k/include/asm/Kbuild b/arch/m68k/include/asm/Kbuild index c7933e41f10..09d77a862da 100644 --- a/arch/m68k/include/asm/Kbuild +++ b/arch/m68k/include/asm/Kbuild @@ -6,7 +6,6 @@ generic-y += device.h generic-y += emergency-restart.h generic-y += errno.h generic-y += exec.h -generic-y += futex.h generic-y += hw_irq.h generic-y += ioctl.h generic-y += ipcbuf.h diff --git a/arch/m68k/include/asm/futex.h b/arch/m68k/include/asm/futex.h new file mode 100644 index 00000000000..bc868af10c9 --- /dev/null +++ b/arch/m68k/include/asm/futex.h @@ -0,0 +1,94 @@ +#ifndef _ASM_M68K_FUTEX_H +#define _ASM_M68K_FUTEX_H + +#ifdef __KERNEL__ +#if !defined(CONFIG_MMU) +#include <asm-generic/futex.h> +#else /* CONFIG_MMU */ + +#include <linux/futex.h> +#include <linux/uaccess.h> +#include <asm/errno.h> + +static inline int +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) +{ + u32 val; + + if (unlikely(get_user(val, uaddr) != 0)) + return -EFAULT; + + if (val == oldval && unlikely(put_user(newval, uaddr) != 0)) + return -EFAULT; + + *uval = val; + + return 0; +} + +static inline int +futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr) +{ + int op = (encoded_op >> 28) & 7; + int cmp = (encoded_op >> 24) & 15; + int oparg = (encoded_op << 8) >> 20; + int cmparg = (encoded_op << 20) >> 20; + int oldval, ret; + u32 tmp; + + if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) + oparg = 1 << oparg; + + pagefault_disable(); /* implies preempt_disable() */ + + ret = -EFAULT; + if (unlikely(get_user(oldval, uaddr) != 0)) + goto out_pagefault_enable; + + ret = 0; + tmp = oldval; + + switch (op) { + case FUTEX_OP_SET: + tmp = oparg; + break; + case FUTEX_OP_ADD: + tmp += oparg; + break; + case FUTEX_OP_OR: + tmp |= oparg; + break; + case FUTEX_OP_ANDN: + tmp &= ~oparg; + break; + case FUTEX_OP_XOR: + tmp ^= oparg; + break; + default: + ret = -ENOSYS; + } + + if (ret == 0 && unlikely(put_user(tmp, uaddr) != 0)) + ret = -EFAULT; + +out_pagefault_enable: + pagefault_enable(); /* subsumes preempt_enable() */ + + if (ret == 0) { + switch (cmp) { + case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break; + case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break; + case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break; + case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break; + case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break; + case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break; + default: ret = -ENOSYS; + } + } + return ret; +} + +#endif /* CONFIG_MMU */ +#endif /* __KERNEL__ */ +#endif /* _ASM_M68K_FUTEX_H */ diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h index 8cc83431805..2f6eec1e34b 100644 --- a/arch/m68k/include/asm/gpio.h +++ b/arch/m68k/include/asm/gpio.h @@ -86,6 +86,7 @@ static inline int gpio_cansleep(unsigned gpio) return gpio < MCFGPIO_PIN_MAX ? 0 : __gpio_cansleep(gpio); } +#ifndef CONFIG_GPIOLIB static inline int gpio_request_one(unsigned gpio, unsigned long flags, const char *label) { int err; @@ -105,5 +106,5 @@ static inline int gpio_request_one(unsigned gpio, unsigned long flags, const cha return err; } - +#endif /* !CONFIG_GPIOLIB */ #endif diff --git a/arch/m68k/kernel/head.S b/arch/m68k/kernel/head.S index d197e7ff62c..ac85f16534a 100644 --- a/arch/m68k/kernel/head.S +++ b/arch/m68k/kernel/head.S @@ -2752,11 +2752,9 @@ func_return get_new_page #ifdef CONFIG_MAC L(scc_initable_mac): - .byte 9,12 /* Reset */ .byte 4,0x44 /* x16, 1 stopbit, no parity */ .byte 3,0xc0 /* receiver: 8 bpc */ .byte 5,0xe2 /* transmitter: 8 bpc, assert dtr/rts */ - .byte 9,0 /* no interrupts */ .byte 10,0 /* NRZ */ .byte 11,0x50 /* use baud rate generator */ .byte 12,1,13,0 /* 38400 baud */ @@ -2899,6 +2897,7 @@ func_start serial_init,%d0/%d1/%a0/%a1 is_not_mac(L(serial_init_not_mac)) #ifdef SERIAL_DEBUG + /* You may define either or both of these. */ #define MAC_USE_SCC_A /* Modem port */ #define MAC_USE_SCC_B /* Printer port */ @@ -2908,9 +2907,21 @@ func_start serial_init,%d0/%d1/%a0/%a1 #define mac_scc_cha_b_data_offset 0x4 #define mac_scc_cha_a_data_offset 0x6 +#if defined(MAC_USE_SCC_A) || defined(MAC_USE_SCC_B) + movel %pc@(L(mac_sccbase)),%a0 + /* Reset SCC device */ + moveb #9,%a0@(mac_scc_cha_a_ctrl_offset) + moveb #0xc0,%a0@(mac_scc_cha_a_ctrl_offset) + /* Wait for 5 PCLK cycles, which is about 68 CPU cycles */ + /* 5 / 3.6864 MHz = approx. 1.36 us = 68 / 50 MHz */ + movel #35,%d0 +5: + subq #1,%d0 + jne 5b +#endif + #ifdef MAC_USE_SCC_A /* Initialize channel A */ - movel %pc@(L(mac_sccbase)),%a0 lea %pc@(L(scc_initable_mac)),%a1 5: moveb %a1@+,%d0 jmi 6f @@ -2922,9 +2933,6 @@ func_start serial_init,%d0/%d1/%a0/%a1 #ifdef MAC_USE_SCC_B /* Initialize channel B */ -#ifndef MAC_USE_SCC_A /* Load mac_sccbase only if needed */ - movel %pc@(L(mac_sccbase)),%a0 -#endif /* MAC_USE_SCC_A */ lea %pc@(L(scc_initable_mac)),%a1 7: moveb %a1@+,%d0 jmi 8f @@ -2933,6 +2941,7 @@ func_start serial_init,%d0/%d1/%a0/%a1 jra 7b 8: #endif /* MAC_USE_SCC_B */ + #endif /* SERIAL_DEBUG */ jra L(serial_init_done) @@ -3006,17 +3015,17 @@ func_start serial_putc,%d0/%d1/%a0/%a1 #ifdef SERIAL_DEBUG -#ifdef MAC_USE_SCC_A +#if defined(MAC_USE_SCC_A) || defined(MAC_USE_SCC_B) movel %pc@(L(mac_sccbase)),%a1 +#endif + +#ifdef MAC_USE_SCC_A 3: btst #2,%a1@(mac_scc_cha_a_ctrl_offset) jeq 3b moveb %d0,%a1@(mac_scc_cha_a_data_offset) #endif /* MAC_USE_SCC_A */ #ifdef MAC_USE_SCC_B -#ifndef MAC_USE_SCC_A /* Load mac_sccbase only if needed */ - movel %pc@(L(mac_sccbase)),%a1 -#endif /* MAC_USE_SCC_A */ 4: btst #2,%a1@(mac_scc_cha_b_ctrl_offset) jeq 4b moveb %d0,%a1@(mac_scc_cha_b_data_offset) diff --git a/arch/microblaze/include/asm/cacheflush.h b/arch/microblaze/include/asm/cacheflush.h index 0f553bc009a..ffea82a16d2 100644 --- a/arch/microblaze/include/asm/cacheflush.h +++ b/arch/microblaze/include/asm/cacheflush.h @@ -102,21 +102,23 @@ do { \ #define flush_cache_range(vma, start, len) do { } while (0) -#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ -do { \ - u32 addr = virt_to_phys(dst); \ - memcpy((dst), (src), (len)); \ - if (vma->vm_flags & VM_EXEC) { \ - invalidate_icache_range((unsigned) (addr), \ - (unsigned) (addr) + PAGE_SIZE); \ - flush_dcache_range((unsigned) (addr), \ - (unsigned) (addr) + PAGE_SIZE); \ - } \ -} while (0) - -#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ -do { \ - memcpy((dst), (src), (len)); \ -} while (0) +static inline void copy_to_user_page(struct vm_area_struct *vma, + struct page *page, unsigned long vaddr, + void *dst, void *src, int len) +{ + u32 addr = virt_to_phys(dst); + memcpy(dst, src, len); + if (vma->vm_flags & VM_EXEC) { + invalidate_icache_range(addr, addr + PAGE_SIZE); + flush_dcache_range(addr, addr + PAGE_SIZE); + } +} + +static inline void copy_from_user_page(struct vm_area_struct *vma, + struct page *page, unsigned long vaddr, + void *dst, void *src, int len) +{ + memcpy(dst, src, len); +} #endif /* _ASM_MICROBLAZE_CACHEFLUSH_H */ diff --git a/arch/microblaze/include/asm/futex.h b/arch/microblaze/include/asm/futex.h index ff8cde159d9..01848f056f4 100644 --- a/arch/microblaze/include/asm/futex.h +++ b/arch/microblaze/include/asm/futex.h @@ -105,7 +105,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, __asm__ __volatile__ ("1: lwx %1, %3, r0; \ cmp %2, %1, %4; \ - beqi %2, 3f; \ + bnei %2, 3f; \ 2: swx %5, %3, r0; \ addic %2, r0, 0; \ bnei %2, 1b; \ diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h index 8cb8a8566ed..2565cb94f32 100644 --- a/arch/microblaze/include/asm/io.h +++ b/arch/microblaze/include/asm/io.h @@ -123,11 +123,11 @@ static inline void writel(unsigned int v, volatile void __iomem *addr) * inb_p/inw_p/... * The macros don't do byte-swapping. */ -#define inb(port) readb((u8 *)((port))) +#define inb(port) readb((u8 *)((unsigned long)(port))) #define outb(val, port) writeb((val), (u8 *)((unsigned long)(port))) -#define inw(port) readw((u16 *)((port))) +#define inw(port) readw((u16 *)((unsigned long)(port))) #define outw(val, port) writew((val), (u16 *)((unsigned long)(port))) -#define inl(port) readl((u32 *)((port))) +#define inl(port) readl((u32 *)((unsigned long)(port))) #define outl(val, port) writel((val), (u32 *)((unsigned long)(port))) #define inb_p(port) inb((port)) diff --git a/arch/microblaze/include/asm/uaccess.h b/arch/microblaze/include/asm/uaccess.h index efe59d88178..04e49553bdf 100644 --- a/arch/microblaze/include/asm/uaccess.h +++ b/arch/microblaze/include/asm/uaccess.h @@ -99,13 +99,13 @@ static inline int access_ok(int type, const void __user *addr, if ((get_fs().seg < ((unsigned long)addr)) || (get_fs().seg < ((unsigned long)addr + size - 1))) { pr_debug("ACCESS fail: %s at 0x%08x (size 0x%x), seg 0x%08x\n", - type ? "WRITE" : "READ ", (u32)addr, (u32)size, + type ? "WRITE" : "READ ", (__force u32)addr, (u32)size, (u32)get_fs().seg); return 0; } ok: pr_debug("ACCESS OK: %s at 0x%08x (size 0x%x), seg 0x%08x\n", - type ? "WRITE" : "READ ", (u32)addr, (u32)size, + type ? "WRITE" : "READ ", (__force u32)addr, (u32)size, (u32)get_fs().seg); return 1; } diff --git a/arch/microblaze/kernel/cpu/cache.c b/arch/microblaze/kernel/cpu/cache.c index 4254514b4c8..a6e44410672 100644 --- a/arch/microblaze/kernel/cpu/cache.c +++ b/arch/microblaze/kernel/cpu/cache.c @@ -140,7 +140,7 @@ do { \ /* It is used only first parameter for OP - for wic, wdc */ #define CACHE_RANGE_LOOP_1(start, end, line_length, op) \ do { \ - int volatile temp; \ + int volatile temp = 0; \ int align = ~(line_length - 1); \ end = ((end & align) == end) ? end - line_length : end & align; \ WARN_ON(end - start < 0); \ diff --git a/arch/mips/alchemy/board-gpr.c b/arch/mips/alchemy/board-gpr.c index cb0f6afb738..9edc35ff8cf 100644 --- a/arch/mips/alchemy/board-gpr.c +++ b/arch/mips/alchemy/board-gpr.c @@ -31,6 +31,7 @@ #include <linux/i2c.h> #include <linux/i2c-gpio.h> #include <asm/bootinfo.h> +#include <asm/idle.h> #include <asm/reboot.h> #include <asm/mach-au1x00/au1000.h> #include <prom.h> diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 38afb11ba2c..93fa586d52e 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -36,6 +36,7 @@ #include <linux/interrupt.h> #include <linux/spinlock.h> +#include <asm/idle.h> #include <asm/processor.h> #include <asm/time.h> #include <asm/mach-au1x00/au1000.h> diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index a0233a2c198..8be4e856b8b 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -19,6 +19,7 @@ #include <linux/clk.h> #include <asm/bootinfo.h> +#include <asm/idle.h> #include <asm/time.h> /* for mips_hpt_frequency */ #include <asm/reboot.h> /* for _machine_{restart,halt} */ #include <asm/mips_machine.h> diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index b0baa299f89..01b1b3f94fe 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -428,13 +428,16 @@ static void octeon_restart(char *command) */ static void octeon_kill_core(void *arg) { - mb(); - if (octeon_is_simulation()) { - /* The simulator needs the watchdog to stop for dead cores */ - cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); + if (octeon_is_simulation()) /* A break instruction causes the simulator stop a core */ - asm volatile ("sync\nbreak"); - } + asm volatile ("break" ::: "memory"); + + local_irq_disable(); + /* Disable watchdog on this core. */ + cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); + /* Spin in a low power mode. */ + while (true) + asm volatile ("wait" ::: "memory"); } diff --git a/arch/mips/cobalt/reset.c b/arch/mips/cobalt/reset.c index 516b4428df4..4eedd481dd0 100644 --- a/arch/mips/cobalt/reset.c +++ b/arch/mips/cobalt/reset.c @@ -12,6 +12,7 @@ #include <linux/io.h> #include <linux/leds.h> +#include <asm/idle.h> #include <asm/processor.h> #include <cobalt.h> diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index face9d26e6d..bac26b971c5 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig @@ -228,7 +228,6 @@ CONFIG_HIDRAW=y CONFIG_USB_HID=y CONFIG_USB_SUPPORT=y CONFIG_USB=y -CONFIG_USB_SUSPEND=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y diff --git a/arch/mips/configs/db1235_defconfig b/arch/mips/configs/db1235_defconfig index 14752dde754..e2b4ad55462 100644 --- a/arch/mips/configs/db1235_defconfig +++ b/arch/mips/configs/db1235_defconfig @@ -344,7 +344,6 @@ CONFIG_UHID=y CONFIG_USB_HIDDEV=y CONFIG_USB=y CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_SUSPEND=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD_PLATFORM=y CONFIG_USB_EHCI_ROOT_HUB_TT=y diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig index b6acd2f256b..343bebc4b63 100644 --- a/arch/mips/configs/lemote2f_defconfig +++ b/arch/mips/configs/lemote2f_defconfig @@ -300,7 +300,6 @@ CONFIG_USB=y CONFIG_USB_DEVICEFS=y # CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_SUSPEND=y CONFIG_USB_OTG_WHITELIST=y CONFIG_USB_MON=y CONFIG_USB_EHCI_HCD=y diff --git a/arch/mips/include/asm/clock.h b/arch/mips/include/asm/clock.h index c9456e7a728..778e32d817b 100644 --- a/arch/mips/include/asm/clock.h +++ b/arch/mips/include/asm/clock.h @@ -6,8 +6,6 @@ #include <linux/seq_file.h> #include <linux/clk.h> -extern void (*cpu_wait) (void); - struct clk; struct clk_ops { diff --git a/arch/mips/include/asm/idle.h b/arch/mips/include/asm/idle.h new file mode 100644 index 00000000000..d192158886b --- /dev/null +++ b/arch/mips/include/asm/idle.h @@ -0,0 +1,23 @@ +#ifndef __ASM_IDLE_H +#define __ASM_IDLE_H + +#include <linux/linkage.h> + +extern void (*cpu_wait)(void); +extern void r4k_wait(void); +extern asmlinkage void __r4k_wait(void); +extern void r4k_wait_irqoff(void); +extern void __pastwait(void); + +static inline int using_rollback_handler(void) +{ + return cpu_wait == r4k_wait; +} + +static inline int address_is_in_r4k_wait_irqoff(unsigned long addr) +{ + return addr >= (unsigned long)r4k_wait_irqoff && + addr < (unsigned long)__pastwait; +} + +#endif /* __ASM_IDLE_H */ diff --git a/arch/mips/include/asm/kvm.h b/arch/mips/include/asm/kvm.h deleted file mode 100644 index 85789eacbf1..00000000000 --- a/arch/mips/include/asm/kvm.h +++ /dev/null @@ -1,55 +0,0 @@ -/* -* This file is subject to the terms and conditions of the GNU General Public -* License. See the file "COPYING" in the main directory of this archive -* for more details. -* -* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. -* Authors: Sanjay Lal <sanjayl@kymasys.com> -*/ - -#ifndef __LINUX_KVM_MIPS_H -#define __LINUX_KVM_MIPS_H - -#include <linux/types.h> - -#define __KVM_MIPS - -#define N_MIPS_COPROC_REGS 32 -#define N_MIPS_COPROC_SEL 8 - -/* for KVM_GET_REGS and KVM_SET_REGS */ -struct kvm_regs { - __u32 gprs[32]; - __u32 hi; - __u32 lo; - __u32 pc; - - __u32 cp0reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL]; -}; - -/* for KVM_GET_SREGS and KVM_SET_SREGS */ -struct kvm_sregs { -}; - -/* for KVM_GET_FPU and KVM_SET_FPU */ -struct kvm_fpu { -}; - -struct kvm_debug_exit_arch { -}; - -/* for KVM_SET_GUEST_DEBUG */ -struct kvm_guest_debug_arch { -}; - -struct kvm_mips_interrupt { - /* in */ - __u32 cpu; - __u32 irq; -}; - -/* definition of registers in kvm_run */ -struct kvm_sync_regs { -}; - -#endif /* __LINUX_KVM_MIPS_H */ diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h index 143875c6c95..4d6fa0bf130 100644 --- a/arch/mips/include/asm/kvm_host.h +++ b/arch/mips/include/asm/kvm_host.h @@ -496,10 +496,6 @@ struct kvm_mips_callbacks { uint32_t cause); int (*irq_clear) (struct kvm_vcpu *vcpu, unsigned int priority, uint32_t cause); - int (*vcpu_ioctl_get_regs) (struct kvm_vcpu *vcpu, - struct kvm_regs *regs); - int (*vcpu_ioctl_set_regs) (struct kvm_vcpu *vcpu, - struct kvm_regs *regs); }; extern struct kvm_mips_callbacks *kvm_mips_callbacks; int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks); diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index 820116067c1..516e6e9a559 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -117,7 +117,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) if (! ((asid += ASID_INC) & ASID_MASK) ) { if (cpu_has_vtag_icache) flush_icache_all(); -#ifdef CONFIG_VIRTUALIZATION +#ifdef CONFIG_KVM kvm_local_flush_tlb_all(); /* start new asid cycle */ #else local_flush_tlb_all(); /* start new asid cycle */ diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index ec1ca537fbc..f59552fae91 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h @@ -171,14 +171,13 @@ typedef struct { unsigned long pgprot; } pgprot_t; #ifdef CONFIG_FLATMEM -#define pfn_valid(pfn) \ -({ \ - unsigned long __pfn = (pfn); \ - /* avoid <linux/bootmem.h> include hell */ \ - extern unsigned long min_low_pfn; \ - \ - __pfn >= min_low_pfn && __pfn < max_mapnr; \ -}) +static inline int pfn_valid(unsigned long pfn) +{ + /* avoid <linux/mm.h> include hell */ + extern unsigned long max_mapnr; + + return pfn >= ARCH_PFN_OFFSET && pfn < max_mapnr; +} #elif defined(CONFIG_SPARSEMEM) diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 71686c897de..1470b7b68b0 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -28,7 +28,6 @@ /* * System setup and hardware flags.. */ -extern void (*cpu_wait)(void); extern unsigned int vced_count, vcei_count; diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h index a3186f2bb8a..5e6cd094739 100644 --- a/arch/mips/include/asm/ptrace.h +++ b/arch/mips/include/asm/ptrace.h @@ -16,6 +16,38 @@ #include <asm/isadep.h> #include <uapi/asm/ptrace.h> +/* + * This struct defines the way the registers are stored on the stack during a + * system call/exception. As usual the registers k0/k1 aren't being saved. + */ +struct pt_regs { +#ifdef CONFIG_32BIT + /* Pad bytes for argument save space on the stack. */ + unsigned long pad0[6]; +#endif + + /* Saved main processor registers. */ + unsigned long regs[32]; + + /* Saved special registers. */ + unsigned long cp0_status; + unsigned long hi; + unsigned long lo; +#ifdef CONFIG_CPU_HAS_SMARTMIPS + unsigned long acx; +#endif + unsigned long cp0_badvaddr; + unsigned long cp0_cause; + unsigned long cp0_epc; +#ifdef CONFIG_MIPS_MT_SMTC + unsigned long cp0_tcstatus; +#endif /* CONFIG_MIPS_MT_SMTC */ +#ifdef CONFIG_CPU_CAVIUM_OCTEON + unsigned long long mpl[3]; /* MTM{0,1,2} */ + unsigned long long mtp[3]; /* MTP{0,1,2} */ +#endif +} __aligned(8); + struct task_struct; extern int ptrace_getregs(struct task_struct *child, __s64 __user *data); diff --git a/arch/mips/include/uapi/asm/kvm.h b/arch/mips/include/uapi/asm/kvm.h new file mode 100644 index 00000000000..f09ff5ae205 --- /dev/null +++ b/arch/mips/include/uapi/asm/kvm.h @@ -0,0 +1,135 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2013 Cavium, Inc. + * Authors: Sanjay Lal <sanjayl@kymasys.com> + */ + +#ifndef __LINUX_KVM_MIPS_H +#define __LINUX_KVM_MIPS_H + +#include <linux/types.h> + +/* + * KVM MIPS specific structures and definitions. + * + * Some parts derived from the x86 version of this file. + */ + +/* + * for KVM_GET_REGS and KVM_SET_REGS + * + * If Config[AT] is zero (32-bit CPU), the register contents are + * stored in the lower 32-bits of the struct kvm_regs fields and sign + * extended to 64-bits. + */ +struct kvm_regs { + /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ + __u64 gpr[32]; + __u64 hi; + __u64 lo; + __u64 pc; +}; + +/* + * for KVM_GET_FPU and KVM_SET_FPU + * + * If Status[FR] is zero (32-bit FPU), the upper 32-bits of the FPRs + * are zero filled. + */ +struct kvm_fpu { + __u64 fpr[32]; + __u32 fir; + __u32 fccr; + __u32 fexr; + __u32 fenr; + __u32 fcsr; + __u32 pad; +}; + + +/* + * For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access CP0 + * registers. The id field is broken down as follows: + * + * bits[2..0] - Register 'sel' index. + * bits[7..3] - Register 'rd' index. + * bits[15..8] - Must be zero. + * bits[31..16] - 1 -> CP0 registers. + * bits[51..32] - Must be zero. + * bits[63..52] - As per linux/kvm.h + * + * Other sets registers may be added in the future. Each set would + * have its own identifier in bits[31..16]. + * + * The registers defined in struct kvm_regs are also accessible, the + * id values for these are below. + */ + +#define KVM_REG_MIPS_R0 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0) +#define KVM_REG_MIPS_R1 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 1) +#define KVM_REG_MIPS_R2 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 2) +#define KVM_REG_MIPS_R3 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 3) +#define KVM_REG_MIPS_R4 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 4) +#define KVM_REG_MIPS_R5 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 5) +#define KVM_REG_MIPS_R6 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 6) +#define KVM_REG_MIPS_R7 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 7) +#define KVM_REG_MIPS_R8 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 8) +#define KVM_REG_MIPS_R9 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 9) +#define KVM_REG_MIPS_R10 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 10) +#define KVM_REG_MIPS_R11 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 11) +#define KVM_REG_MIPS_R12 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 12) +#define KVM_REG_MIPS_R13 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 13) +#define KVM_REG_MIPS_R14 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 14) +#define KVM_REG_MIPS_R15 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 15) +#define KVM_REG_MIPS_R16 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 16) +#define KVM_REG_MIPS_R17 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 17) +#define KVM_REG_MIPS_R18 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 18) +#define KVM_REG_MIPS_R19 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 19) +#define KVM_REG_MIPS_R20 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 20) +#define KVM_REG_MIPS_R21 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 21) +#define KVM_REG_MIPS_R22 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 22) +#define KVM_REG_MIPS_R23 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 23) +#define KVM_REG_MIPS_R24 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 24) +#define KVM_REG_MIPS_R25 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 25) +#define KVM_REG_MIPS_R26 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 26) +#define KVM_REG_MIPS_R27 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 27) +#define KVM_REG_MIPS_R28 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 28) +#define KVM_REG_MIPS_R29 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 29) +#define KVM_REG_MIPS_R30 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 30) +#define KVM_REG_MIPS_R31 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 31) + +#define KVM_REG_MIPS_HI (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 32) +#define KVM_REG_MIPS_LO (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 33) +#define KVM_REG_MIPS_PC (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 34) + +/* + * KVM MIPS specific structures and definitions + * + */ +struct kvm_debug_exit_arch { + __u64 epc; +}; + +/* for KVM_SET_GUEST_DEBUG */ +struct kvm_guest_debug_arch { +}; + +/* definition of registers in kvm_run */ +struct kvm_sync_regs { +}; + +/* dummy definition */ +struct kvm_sregs { +}; + +struct kvm_mips_interrupt { + /* in */ + __u32 cpu; + __u32 irq; +}; + +#endif /* __LINUX_KVM_MIPS_H */ diff --git a/arch/mips/include/uapi/asm/ptrace.h b/arch/mips/include/uapi/asm/ptrace.h index 4d58d846870..b26f7e31727 100644 --- a/arch/mips/include/uapi/asm/ptrace.h +++ b/arch/mips/include/uapi/asm/ptrace.h @@ -22,16 +22,12 @@ #define DSP_CONTROL 77 #define ACX 78 +#ifndef __KERNEL__ /* * This struct defines the way the registers are stored on the stack during a * system call/exception. As usual the registers k0/k1 aren't being saved. */ struct pt_regs { -#ifdef CONFIG_32BIT - /* Pad bytes for argument save space on the stack. */ - unsigned long pad0[6]; -#endif - /* Saved main processor registers. */ unsigned long regs[32]; @@ -39,20 +35,11 @@ struct pt_regs { unsigned long cp0_status; unsigned long hi; unsigned long lo; -#ifdef CONFIG_CPU_HAS_SMARTMIPS - unsigned long acx; -#endif unsigned long cp0_badvaddr; unsigned long cp0_cause; unsigned long cp0_epc; -#ifdef CONFIG_MIPS_MT_SMTC - unsigned long cp0_tcstatus; -#endif /* CONFIG_MIPS_MT_SMTC */ -#ifdef CONFIG_CPU_CAVIUM_OCTEON - unsigned long long mpl[3]; /* MTM{0,1,2} */ - unsigned long long mtp[3]; /* MTP{0,1,2} */ -#endif } __attribute__ ((aligned (8))); +#endif /* __KERNEL__ */ /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ #define PTRACE_GETREGS 12 diff --git a/arch/mips/include/uapi/asm/unistd.h b/arch/mips/include/uapi/asm/unistd.h index 16338b84fa7..1dee279f966 100644 --- a/arch/mips/include/uapi/asm/unistd.h +++ b/arch/mips/include/uapi/asm/unistd.h @@ -694,16 +694,17 @@ #define __NR_process_vm_writev (__NR_Linux + 305) #define __NR_kcmp (__NR_Linux + 306) #define __NR_finit_module (__NR_Linux + 307) +#define __NR_getdents64 (__NR_Linux + 308) /* * Offset of the last Linux 64-bit flavoured syscall */ -#define __NR_Linux_syscalls 307 +#define __NR_Linux_syscalls 308 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ #define __NR_64_Linux 5000 -#define __NR_64_Linux_syscalls 307 +#define __NR_64_Linux_syscalls 308 #if _MIPS_SIM == _MIPS_SIM_NABI32 diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 6ad9e04bdf6..423d871a946 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -4,7 +4,7 @@ extra-y := head.o vmlinux.lds -obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \ +obj-y += cpu-probe.o branch.o entry.o genex.o idle.o irq.o process.o \ prom.o ptrace.o reset.o setup.o signal.o syscall.o \ time.o topology.o traps.o unaligned.o watch.o vdso.o diff --git a/arch/mips/kernel/binfmt_elfn32.c b/arch/mips/kernel/binfmt_elfn32.c index e06f777e9c4..1188e00bb12 100644 --- a/arch/mips/kernel/binfmt_elfn32.c +++ b/arch/mips/kernel/binfmt_elfn32.c @@ -119,4 +119,15 @@ MODULE_AUTHOR("Ralf Baechle (ralf@linux-mips.org)"); #undef TASK_SIZE #define TASK_SIZE TASK_SIZE32 +#undef cputime_to_timeval +#define cputime_to_timeval cputime_to_compat_timeval +static __inline__ void +cputime_to_compat_timeval(const cputime_t cputime, struct compat_timeval *value) +{ + unsigned long jiffies = cputime_to_jiffies(cputime); + + value->tv_usec = (jiffies % HZ) * (1000000L / HZ); + value->tv_sec = jiffies / HZ; +} + #include "../../../fs/binfmt_elf.c" diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c index 97c5a1668e5..202e581e609 100644 --- a/arch/mips/kernel/binfmt_elfo32.c +++ b/arch/mips/kernel/binfmt_elfo32.c @@ -162,4 +162,15 @@ MODULE_AUTHOR("Ralf Baechle (ralf@linux-mips.org)"); #undef TASK_SIZE #define TASK_SIZE TASK_SIZE32 +#undef cputime_to_timeval +#define cputime_to_timeval cputime_to_compat_timeval +static __inline__ void +cputime_to_compat_timeval(const cputime_t cputime, struct compat_timeval *value) +{ + unsigned long jiffies = cputime_to_jiffies(cputime); + + value->tv_usec = (jiffies % HZ) * (1000000L / HZ); + value->tv_sec = jiffies / HZ; +} + #include "../../../fs/binfmt_elf.c" diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 4bbffdb9024..c6568bf4b1b 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -27,105 +27,6 @@ #include <asm/spram.h> #include <asm/uaccess.h> -/* - * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, - * the implementation of the "wait" feature differs between CPU families. This - * points to the function that implements CPU specific wait. - * The wait instruction stops the pipeline and reduces the power consumption of - * the CPU very much. - */ -void (*cpu_wait)(void); -EXPORT_SYMBOL(cpu_wait); - -static void r3081_wait(void) -{ - unsigned long cfg = read_c0_conf(); - write_c0_conf(cfg | R30XX_CONF_HALT); -} - -static void r39xx_wait(void) -{ - local_irq_disable(); - if (!need_resched()) - write_c0_conf(read_c0_conf() | TX39_CONF_HALT); - local_irq_enable(); -} - -extern void r4k_wait(void); - -/* - * This variant is preferable as it allows testing need_resched and going to - * sleep depending on the outcome atomically. Unfortunately the "It is - * implementation-dependent whether the pipeline restarts when a non-enabled - * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes - * using this version a gamble. - */ -void r4k_wait_irqoff(void) -{ - local_irq_disable(); - if (!need_resched()) - __asm__(" .set push \n" - " .set mips3 \n" - " wait \n" - " .set pop \n"); - local_irq_enable(); - __asm__(" .globl __pastwait \n" - "__pastwait: \n"); -} - -/* - * The RM7000 variant has to handle erratum 38. The workaround is to not - * have any pending stores when the WAIT instruction is executed. - */ -static void rm7k_wait_irqoff(void) -{ - local_irq_disable(); - if (!need_resched()) - __asm__( - " .set push \n" - " .set mips3 \n" - " .set noat \n" - " mfc0 $1, $12 \n" - " sync \n" - " mtc0 $1, $12 # stalls until W stage \n" - " wait \n" - " mtc0 $1, $12 # stalls until W stage \n" - " .set pop \n"); - local_irq_enable(); -} - -/* - * The Au1xxx wait is available only if using 32khz counter or - * external timer source, but specifically not CP0 Counter. - * alchemy/common/time.c may override cpu_wait! - */ -static void au1k_wait(void) -{ - __asm__(" .set mips3 \n" - " cache 0x14, 0(%0) \n" - " cache 0x14, 32(%0) \n" - " sync \n" - " nop \n" - " wait \n" - " nop \n" - " nop \n" - " nop \n" - " nop \n" - " .set mips0 \n" - : : "r" (au1k_wait)); -} - -static int __initdata nowait; - -static int __init wait_disable(char *s) -{ - nowait = 1; - - return 1; -} - -__setup("nowait", wait_disable); - static int __cpuinitdata mips_fpu_disabled; static int __init fpu_disable(char *s) @@ -150,105 +51,6 @@ static int __init dsp_disable(char *s) __setup("nodsp", dsp_disable); -void __init check_wait(void) -{ - struct cpuinfo_mips *c = ¤t_cpu_data; - - if (nowait) { - printk("Wait instruction disabled.\n"); - return; - } - - switch (c->cputype) { - case CPU_R3081: - case CPU_R3081E: - cpu_wait = r3081_wait; - break; - case CPU_TX3927: - cpu_wait = r39xx_wait; - break; - case CPU_R4200: -/* case CPU_R4300: */ - case CPU_R4600: - case CPU_R4640: - case CPU_R4650: - case CPU_R4700: - case CPU_R5000: - case CPU_R5500: - case CPU_NEVADA: - case CPU_4KC: - case CPU_4KEC: - case CPU_4KSC: - case CPU_5KC: - case CPU_25KF: - case CPU_PR4450: - case CPU_BMIPS3300: - case CPU_BMIPS4350: - case CPU_BMIPS4380: - case CPU_BMIPS5000: - case CPU_CAVIUM_OCTEON: - case CPU_CAVIUM_OCTEON_PLUS: - case CPU_CAVIUM_OCTEON2: - case CPU_JZRISC: - case CPU_LOONGSON1: - case CPU_XLR: - case CPU_XLP: - cpu_wait = r4k_wait; - break; - - case CPU_RM7000: - cpu_wait = rm7k_wait_irqoff; - break; - - case CPU_M14KC: - case CPU_M14KEC: - case CPU_24K: - case CPU_34K: - case CPU_1004K: - cpu_wait = r4k_wait; - if (read_c0_config7() & MIPS_CONF7_WII) - cpu_wait = r4k_wait_irqoff; - break; - - case CPU_74K: - cpu_wait = r4k_wait; - if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) - cpu_wait = r4k_wait_irqoff; - break; - - case CPU_TX49XX: - cpu_wait = r4k_wait_irqoff; - break; - case CPU_ALCHEMY: - cpu_wait = au1k_wait; - break; - case CPU_20KC: - /* - * WAIT on Rev1.0 has E1, E2, E3 and E16. - * WAIT on Rev2.0 and Rev3.0 has E16. - * Rev3.1 WAIT is nop, why bother - */ - if ((c->processor_id & 0xff) <= 0x64) - break; - - /* - * Another rev is incremeting c0_count at a reduced clock - * rate while in WAIT mode. So we basically have the choice - * between using the cp0 timer as clocksource or avoiding - * the WAIT instruction. Until more details are known, - * disable the use of WAIT for 20Kc entirely. - cpu_wait = r4k_wait; - */ - break; - case CPU_RM9000: - if ((c->processor_id & 0x00ff) >= 0x40) - cpu_wait = r4k_wait; - break; - default: - break; - } -} - static inline void check_errata(void) { struct cpuinfo_mips *c = ¤t_cpu_data; diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c index cf5509f13dd..dba90ec0dc3 100644 --- a/arch/mips/kernel/ftrace.c +++ b/arch/mips/kernel/ftrace.c @@ -25,12 +25,16 @@ #define MCOUNT_OFFSET_INSNS 4 #endif +#ifdef CONFIG_DYNAMIC_FTRACE + /* Arch override because MIPS doesn't need to run this from stop_machine() */ void arch_ftrace_update_code(int command) { ftrace_modify_all_code(command); } +#endif + /* * Check if the address is in kernel space * diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 9098829bfcb..31fa856829c 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -122,7 +122,7 @@ handle_vcei: __FINIT .align 5 /* 32 byte rollback region */ -LEAF(r4k_wait) +LEAF(__r4k_wait) .set push .set noreorder /* start of rollback region */ @@ -146,14 +146,14 @@ LEAF(r4k_wait) jr ra nop .set pop - END(r4k_wait) + END(__r4k_wait) .macro BUILD_ROLLBACK_PROLOGUE handler FEXPORT(rollback_\handler) .set push .set noat MFC0 k0, CP0_EPC - PTR_LA k1, r4k_wait + PTR_LA k1, __r4k_wait ori k0, 0x1f /* 32 byte rollback region */ xori k0, 0x1f bne k0, k1, 9f diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c new file mode 100644 index 00000000000..0c655deeea4 --- /dev/null +++ b/arch/mips/kernel/idle.c @@ -0,0 +1,245 @@ +/* + * MIPS idle loop and WAIT instruction support. + * + * Copyright (C) xxxx the Anonymous + * Copyright (C) 1994 - 2006 Ralf Baechle + * Copyright (C) 2003, 2004 Maciej W. Rozycki + * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include <linux/export.h> +#include <linux/init.h> +#include <linux/irqflags.h> +#include <linux/printk.h> +#include <linux/sched.h> +#include <asm/cpu.h> +#include <asm/cpu-info.h> +#include <asm/idle.h> +#include <asm/mipsregs.h> + +/* + * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, + * the implementation of the "wait" feature differs between CPU families. This + * points to the function that implements CPU specific wait. + * The wait instruction stops the pipeline and reduces the power consumption of + * the CPU very much. + */ +void (*cpu_wait)(void); +EXPORT_SYMBOL(cpu_wait); + +static void r3081_wait(void) +{ + unsigned long cfg = read_c0_conf(); + write_c0_conf(cfg | R30XX_CONF_HALT); + local_irq_enable(); +} + +static void r39xx_wait(void) +{ + if (!need_resched()) + write_c0_conf(read_c0_conf() | TX39_CONF_HALT); + local_irq_enable(); +} + +void r4k_wait(void) +{ + local_irq_enable(); + __r4k_wait(); +} + +/* + * This variant is preferable as it allows testing need_resched and going to + * sleep depending on the outcome atomically. Unfortunately the "It is + * implementation-dependent whether the pipeline restarts when a non-enabled + * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes + * using this version a gamble. + */ +void r4k_wait_irqoff(void) +{ + if (!need_resched()) + __asm__( + " .set push \n" + " .set mips3 \n" + " wait \n" + " .set pop \n"); + local_irq_enable(); + __asm__( + " .globl __pastwait \n" + "__pastwait: \n"); +} + +/* + * The RM7000 variant has to handle erratum 38. The workaround is to not + * have any pending stores when the WAIT instruction is executed. + */ +static void rm7k_wait_irqoff(void) +{ + if (!need_resched()) + __asm__( + " .set push \n" + " .set mips3 \n" + " .set noat \n" + " mfc0 $1, $12 \n" + " sync \n" + " mtc0 $1, $12 # stalls until W stage \n" + " wait \n" + " mtc0 $1, $12 # stalls until W stage \n" + " .set pop \n"); + local_irq_enable(); +} + +/* + * Au1 'wait' is only useful when the 32kHz counter is used as timer, + * since coreclock (and the cp0 counter) stops upon executing it. Only an + * interrupt can wake it, so they must be enabled before entering idle modes. + */ +static void au1k_wait(void) +{ + unsigned long c0status = read_c0_status() | 1; /* irqs on */ + + __asm__( + " .set mips3 \n" + " cache 0x14, 0(%0) \n" + " cache 0x14, 32(%0) \n" + " sync \n" + " mtc0 %1, $12 \n" /* wr c0status */ + " wait \n" + " nop \n" + " nop \n" + " nop \n" + " nop \n" + " .set mips0 \n" + : : "r" (au1k_wait), "r" (c0status)); +} + +static int __initdata nowait; + +static int __init wait_disable(char *s) +{ + nowait = 1; + + return 1; +} + +__setup("nowait", wait_disable); + +void __init check_wait(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + + if (nowait) { + printk("Wait instruction disabled.\n"); + return; + } + + switch (c->cputype) { + case CPU_R3081: + case CPU_R3081E: + cpu_wait = r3081_wait; + break; + case CPU_TX3927: + cpu_wait = r39xx_wait; + break; + case CPU_R4200: +/* case CPU_R4300: */ + case CPU_R4600: + case CPU_R4640: + case CPU_R4650: + case CPU_R4700: + case CPU_R5000: + case CPU_R5500: + case CPU_NEVADA: + case CPU_4KC: + case CPU_4KEC: + case CPU_4KSC: + case CPU_5KC: + case CPU_25KF: + case CPU_PR4450: + case CPU_BMIPS3300: + case CPU_BMIPS4350: + case CPU_BMIPS4380: + case CPU_BMIPS5000: + case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: + case CPU_CAVIUM_OCTEON2: + case CPU_JZRISC: + case CPU_LOONGSON1: + case CPU_XLR: + case CPU_XLP: + cpu_wait = r4k_wait; + break; + + case CPU_RM7000: + cpu_wait = rm7k_wait_irqoff; + break; + + case CPU_M14KC: + case CPU_M14KEC: + case CPU_24K: + case CPU_34K: + case CPU_1004K: + cpu_wait = r4k_wait; + if (read_c0_config7() & MIPS_CONF7_WII) + cpu_wait = r4k_wait_irqoff; + break; + + case CPU_74K: + cpu_wait = r4k_wait; + if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) + cpu_wait = r4k_wait_irqoff; + break; + + case CPU_TX49XX: + cpu_wait = r4k_wait_irqoff; + break; + case CPU_ALCHEMY: + cpu_wait = au1k_wait; + break; + case CPU_20KC: + /* + * WAIT on Rev1.0 has E1, E2, E3 and E16. + * WAIT on Rev2.0 and Rev3.0 has E16. + * Rev3.1 WAIT is nop, why bother + */ + if ((c->processor_id & 0xff) <= 0x64) + break; + + /* + * Another rev is incremeting c0_count at a reduced clock + * rate while in WAIT mode. So we basically have the choice + * between using the cp0 timer as clocksource or avoiding + * the WAIT instruction. Until more details are known, + * disable the use of WAIT for 20Kc entirely. + cpu_wait = r4k_wait; + */ + break; + case CPU_RM9000: + if ((c->processor_id & 0x00ff) >= 0x40) + cpu_wait = r4k_wait; + break; + default: + break; + } +} + +static void smtc_idle_hook(void) +{ +#ifdef CONFIG_MIPS_MT_SMTC + void smtc_idle_loop_hook(void); + + smtc_idle_loop_hook(); +#endif +} + +void arch_cpu_idle(void) +{ + smtc_idle_hook(); + if (cpu_wait) + cpu_wait(); + else + local_irq_enable(); +} diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c index 12bc4ebdf55..1f8187ab099 100644 --- a/arch/mips/kernel/kprobes.c +++ b/arch/mips/kernel/kprobes.c @@ -207,7 +207,10 @@ void __kprobes arch_disarm_kprobe(struct kprobe *p) void __kprobes arch_remove_kprobe(struct kprobe *p) { - free_insn_slot(p->ainsn.insn, 0); + if (p->ainsn.insn) { + free_insn_slot(p->ainsn.insn, 0); + p->ainsn.insn = NULL; + } } static void save_previous_kprobe(struct kprobe_ctlblk *kcb) diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index a3e461408b7..acb34373679 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -10,6 +10,7 @@ #include <asm/bootinfo.h> #include <asm/cpu.h> #include <asm/cpu-features.h> +#include <asm/idle.h> #include <asm/mipsregs.h> #include <asm/processor.h> #include <asm/prom.h> diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index a682a87bcc0..c6a041d9d05 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -51,19 +51,6 @@ void arch_cpu_idle_dead(void) } #endif -void arch_cpu_idle(void) -{ -#ifdef CONFIG_MIPS_MT_SMTC - extern void smtc_idle_loop_hook(void); - - smtc_idle_loop_hook(); -#endif - if (cpu_wait) - (*cpu_wait)(); - else - local_irq_enable(); -} - asmlinkage void ret_from_fork(void); asmlinkage void ret_from_kernel_thread(void); diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index 93c070b41b0..6fa198db899 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -40,6 +40,7 @@ #include <asm/processor.h> #include <asm/vpe.h> #include <asm/rtlx.h> +#include <asm/setup.h> static struct rtlx_info *rtlx; static int major; diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index 36cfd4060e1..97a5909a61c 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -423,4 +423,5 @@ sys_call_table: PTR sys_process_vm_writev /* 5305 */ PTR sys_kcmp PTR sys_finit_module + PTR sys_getdents64 .size sys_call_table,.-sys_call_table diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index c17619fe18e..6e7862ab46c 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -37,6 +37,7 @@ #include <linux/atomic.h> #include <asm/cpu.h> #include <asm/processor.h> +#include <asm/idle.h> #include <asm/r4k-timer.h> #include <asm/mmu_context.h> #include <asm/time.h> diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 7186222dc5b..75a4fd70984 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -34,6 +34,7 @@ #include <asm/hardirq.h> #include <asm/hazards.h> #include <asm/irq.h> +#include <asm/idle.h> #include <asm/mmu_context.h> #include <asm/mipsregs.h> #include <asm/cacheflush.h> @@ -858,7 +859,6 @@ void smtc_send_ipi(int cpu, int type, unsigned int action) unsigned long flags; int mtflags; unsigned long tcrestart; - extern void r4k_wait_irqoff(void), __pastwait(void); int set_resched_flag = (type == LINUX_SMP_IPI && action == SMP_RESCHEDULE_YOURSELF); @@ -914,8 +914,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action) */ if (cpu_wait == r4k_wait_irqoff) { tcrestart = read_tc_c0_tcrestart(); - if (tcrestart >= (unsigned long)r4k_wait_irqoff - && tcrestart < (unsigned long)__pastwait) { + if (address_is_in_r4k_wait_irqoff(tcrestart)) { write_tc_c0_tcrestart(__pastwait); tcstatus &= ~TCSTATUS_IXMT; write_tc_c0_tcstatus(tcstatus); diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index cb14db3c576..a75ae40184a 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -41,6 +41,7 @@ #include <asm/dsp.h> #include <asm/fpu.h> #include <asm/fpu_emulator.h> +#include <asm/idle.h> #include <asm/mipsregs.h> #include <asm/mipsmtregs.h> #include <asm/module.h> @@ -57,7 +58,6 @@ #include <asm/uasm.h> extern void check_wait(void); -extern asmlinkage void r4k_wait(void); extern asmlinkage void rollback_handle_int(void); extern asmlinkage void handle_int(void); extern u32 handle_tlbl[]; @@ -897,22 +897,24 @@ out_sigsegv: asmlinkage void do_tr(struct pt_regs *regs) { - unsigned int opcode, tcode = 0; + u32 opcode, tcode = 0; u16 instr[2]; - unsigned long epc = exception_epc(regs); + unsigned long epc = msk_isa16_mode(exception_epc(regs)); - if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc))) || - (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2)))) + if (get_isa16_mode(regs->cp0_epc)) { + if (__get_user(instr[0], (u16 __user *)(epc + 0)) || + __get_user(instr[1], (u16 __user *)(epc + 2))) goto out_sigsegv; - opcode = (instr[0] << 16) | instr[1]; - - /* Immediate versions don't provide a code. */ - if (!(opcode & OPCODE)) { - if (get_isa16_mode(regs->cp0_epc)) - /* microMIPS */ - tcode = (opcode >> 12) & 0x1f; - else - tcode = ((opcode >> 6) & ((1 << 10) - 1)); + opcode = (instr[0] << 16) | instr[1]; + /* Immediate versions don't provide a code. */ + if (!(opcode & OPCODE)) + tcode = (opcode >> 12) & ((1 << 4) - 1); + } else { + if (__get_user(opcode, (u32 __user *)epc)) + goto out_sigsegv; + /* Immediate versions don't provide a code. */ + if (!(opcode & OPCODE)) + tcode = (opcode >> 6) & ((1 << 10) - 1); } do_trap_or_bp(regs, tcode, "Trap"); @@ -1542,7 +1544,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) extern char except_vec_vi, except_vec_vi_lui; extern char except_vec_vi_ori, except_vec_vi_end; extern char rollback_except_vec_vi; - char *vec_start = (cpu_wait == r4k_wait) ? + char *vec_start = using_rollback_handler() ? &rollback_except_vec_vi : &except_vec_vi; #ifdef CONFIG_MIPS_MT_SMTC /* @@ -1812,10 +1814,8 @@ void __init trap_init(void) extern char except_vec4; extern char except_vec3_r4000; unsigned long i; - int rollback; check_wait(); - rollback = (cpu_wait == r4k_wait); #if defined(CONFIG_KGDB) if (kgdb_early_setup) @@ -1892,7 +1892,8 @@ void __init trap_init(void) if (board_be_init) board_be_init(); - set_except_vector(0, rollback ? rollback_handle_int : handle_int); + set_except_vector(0, using_rollback_handler() ? rollback_handle_int + : handle_int); set_except_vector(1, handle_tlbm); set_except_vector(2, handle_tlbl); set_except_vector(3, handle_tlbs); diff --git a/arch/mips/kvm/kvm_mips.c b/arch/mips/kvm/kvm_mips.c index e0dad028979..dd203e59e6f 100644 --- a/arch/mips/kvm/kvm_mips.c +++ b/arch/mips/kvm/kvm_mips.c @@ -195,7 +195,7 @@ void kvm_arch_destroy_vm(struct kvm *kvm) long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) { - return -EINVAL; + return -ENOIOCTLCMD; } void kvm_arch_free_memslot(struct kvm_memory_slot *free, @@ -401,7 +401,7 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) { - return -EINVAL; + return -ENOIOCTLCMD; } int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) @@ -475,14 +475,248 @@ int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, struct kvm_mp_state *mp_state) { - return -EINVAL; + return -ENOIOCTLCMD; } int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, struct kvm_mp_state *mp_state) { - return -EINVAL; + return -ENOIOCTLCMD; +} + +#define MIPS_CP0_32(_R, _S) \ + (KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S))) + +#define MIPS_CP0_64(_R, _S) \ + (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S))) + +#define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) +#define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0) +#define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0) +#define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) +#define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) +#define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) +#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) +#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) +#define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) +#define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) +#define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) +#define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0) +#define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0) +#define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) +#define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) +#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) +#define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) +#define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) +#define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) +#define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) +#define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7) +#define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0) +#define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) + +static u64 kvm_mips_get_one_regs[] = { + KVM_REG_MIPS_R0, + KVM_REG_MIPS_R1, + KVM_REG_MIPS_R2, + KVM_REG_MIPS_R3, + KVM_REG_MIPS_R4, + KVM_REG_MIPS_R5, + KVM_REG_MIPS_R6, + KVM_REG_MIPS_R7, + KVM_REG_MIPS_R8, + KVM_REG_MIPS_R9, + KVM_REG_MIPS_R10, + KVM_REG_MIPS_R11, + KVM_REG_MIPS_R12, + KVM_REG_MIPS_R13, + KVM_REG_MIPS_R14, + KVM_REG_MIPS_R15, + KVM_REG_MIPS_R16, + KVM_REG_MIPS_R17, + KVM_REG_MIPS_R18, + KVM_REG_MIPS_R19, + KVM_REG_MIPS_R20, + KVM_REG_MIPS_R21, + KVM_REG_MIPS_R22, + KVM_REG_MIPS_R23, + KVM_REG_MIPS_R24, + KVM_REG_MIPS_R25, + KVM_REG_MIPS_R26, + KVM_REG_MIPS_R27, + KVM_REG_MIPS_R28, + KVM_REG_MIPS_R29, + KVM_REG_MIPS_R30, + KVM_REG_MIPS_R31, + + KVM_REG_MIPS_HI, + KVM_REG_MIPS_LO, + KVM_REG_MIPS_PC, + + KVM_REG_MIPS_CP0_INDEX, + KVM_REG_MIPS_CP0_CONTEXT, + KVM_REG_MIPS_CP0_PAGEMASK, + KVM_REG_MIPS_CP0_WIRED, + KVM_REG_MIPS_CP0_BADVADDR, + KVM_REG_MIPS_CP0_ENTRYHI, + KVM_REG_MIPS_CP0_STATUS, + KVM_REG_MIPS_CP0_CAUSE, + /* EPC set via kvm_regs, et al. */ + KVM_REG_MIPS_CP0_CONFIG, + KVM_REG_MIPS_CP0_CONFIG1, + KVM_REG_MIPS_CP0_CONFIG2, + KVM_REG_MIPS_CP0_CONFIG3, + KVM_REG_MIPS_CP0_CONFIG7, + KVM_REG_MIPS_CP0_ERROREPC +}; + +static int kvm_mips_get_reg(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) +{ + struct mips_coproc *cop0 = vcpu->arch.cop0; + s64 v; + + switch (reg->id) { + case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31: + v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0]; + break; + case KVM_REG_MIPS_HI: + v = (long)vcpu->arch.hi; + break; + case KVM_REG_MIPS_LO: + v = (long)vcpu->arch.lo; + break; + case KVM_REG_MIPS_PC: + v = (long)vcpu->arch.pc; + break; + + case KVM_REG_MIPS_CP0_INDEX: + v = (long)kvm_read_c0_guest_index(cop0); + break; + case KVM_REG_MIPS_CP0_CONTEXT: + v = (long)kvm_read_c0_guest_context(cop0); + break; + case KVM_REG_MIPS_CP0_PAGEMASK: + v = (long)kvm_read_c0_guest_pagemask(cop0); + break; + case KVM_REG_MIPS_CP0_WIRED: + v = (long)kvm_read_c0_guest_wired(cop0); + break; + case KVM_REG_MIPS_CP0_BADVADDR: + v = (long)kvm_read_c0_guest_badvaddr(cop0); + break; + case KVM_REG_MIPS_CP0_ENTRYHI: + v = (long)kvm_read_c0_guest_entryhi(cop0); + break; + case KVM_REG_MIPS_CP0_STATUS: + v = (long)kvm_read_c0_guest_status(cop0); + break; + case KVM_REG_MIPS_CP0_CAUSE: + v = (long)kvm_read_c0_guest_cause(cop0); + break; + case KVM_REG_MIPS_CP0_ERROREPC: + v = (long)kvm_read_c0_guest_errorepc(cop0); + break; + case KVM_REG_MIPS_CP0_CONFIG: + v = (long)kvm_read_c0_guest_config(cop0); + break; + case KVM_REG_MIPS_CP0_CONFIG1: + v = (long)kvm_read_c0_guest_config1(cop0); + break; + case KVM_REG_MIPS_CP0_CONFIG2: + v = (long)kvm_read_c0_guest_config2(cop0); + break; + case KVM_REG_MIPS_CP0_CONFIG3: + v = (long)kvm_read_c0_guest_config3(cop0); + break; + case KVM_REG_MIPS_CP0_CONFIG7: + v = (long)kvm_read_c0_guest_config7(cop0); + break; + default: + return -EINVAL; + } + if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { + u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; + return put_user(v, uaddr64); + } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { + u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; + u32 v32 = (u32)v; + return put_user(v32, uaddr32); + } else { + return -EINVAL; + } +} + +static int kvm_mips_set_reg(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) +{ + struct mips_coproc *cop0 = vcpu->arch.cop0; + u64 v; + + if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { + u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; + + if (get_user(v, uaddr64) != 0) + return -EFAULT; + } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { + u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; + s32 v32; + + if (get_user(v32, uaddr32) != 0) + return -EFAULT; + v = (s64)v32; + } else { + return -EINVAL; + } + + switch (reg->id) { + case KVM_REG_MIPS_R0: + /* Silently ignore requests to set $0 */ + break; + case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31: + vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v; + break; + case KVM_REG_MIPS_HI: + vcpu->arch.hi = v; + break; + case KVM_REG_MIPS_LO: + vcpu->arch.lo = v; + break; + case KVM_REG_MIPS_PC: + vcpu->arch.pc = v; + break; + + case KVM_REG_MIPS_CP0_INDEX: + kvm_write_c0_guest_index(cop0, v); + break; + case KVM_REG_MIPS_CP0_CONTEXT: + kvm_write_c0_guest_context(cop0, v); + break; + case KVM_REG_MIPS_CP0_PAGEMASK: + kvm_write_c0_guest_pagemask(cop0, v); + break; + case KVM_REG_MIPS_CP0_WIRED: + kvm_write_c0_guest_wired(cop0, v); + break; + case KVM_REG_MIPS_CP0_BADVADDR: + kvm_write_c0_guest_badvaddr(cop0, v); + break; + case KVM_REG_MIPS_CP0_ENTRYHI: + kvm_write_c0_guest_entryhi(cop0, v); + break; + case KVM_REG_MIPS_CP0_STATUS: + kvm_write_c0_guest_status(cop0, v); + break; + case KVM_REG_MIPS_CP0_CAUSE: + kvm_write_c0_guest_cause(cop0, v); + break; + case KVM_REG_MIPS_CP0_ERROREPC: + kvm_write_c0_guest_errorepc(cop0, v); + break; + default: + return -EINVAL; + } + return 0; } long @@ -491,9 +725,38 @@ kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) struct kvm_vcpu *vcpu = filp->private_data; void __user *argp = (void __user *)arg; long r; - int intr; switch (ioctl) { + case KVM_SET_ONE_REG: + case KVM_GET_ONE_REG: { + struct kvm_one_reg reg; + if (copy_from_user(®, argp, sizeof(reg))) + return -EFAULT; + if (ioctl == KVM_SET_ONE_REG) + return kvm_mips_set_reg(vcpu, ®); + else + return kvm_mips_get_reg(vcpu, ®); + } + case KVM_GET_REG_LIST: { + struct kvm_reg_list __user *user_list = argp; + u64 __user *reg_dest; + struct kvm_reg_list reg_list; + unsigned n; + + if (copy_from_user(®_list, user_list, sizeof(reg_list))) + return -EFAULT; + n = reg_list.n; + reg_list.n = ARRAY_SIZE(kvm_mips_get_one_regs); + if (copy_to_user(user_list, ®_list, sizeof(reg_list))) + return -EFAULT; + if (n < reg_list.n) + return -E2BIG; + reg_dest = user_list->reg; + if (copy_to_user(reg_dest, kvm_mips_get_one_regs, + sizeof(kvm_mips_get_one_regs))) + return -EFAULT; + return 0; + } case KVM_NMI: /* Treat the NMI as a CPU reset */ r = kvm_mips_reset_vcpu(vcpu); @@ -505,8 +768,6 @@ kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) if (copy_from_user(&irq, argp, sizeof(irq))) goto out; - intr = (int)irq.irq; - kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__, irq.irq); @@ -514,7 +775,7 @@ kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) break; } default: - r = -EINVAL; + r = -ENOIOCTLCMD; } out: @@ -565,7 +826,7 @@ long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) switch (ioctl) { default: - r = -EINVAL; + r = -ENOIOCTLCMD; } return r; @@ -593,13 +854,13 @@ void kvm_arch_exit(void) int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) { - return -ENOTSUPP; + return -ENOIOCTLCMD; } int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) { - return -ENOTSUPP; + return -ENOIOCTLCMD; } int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) @@ -609,12 +870,12 @@ int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) { - return -ENOTSUPP; + return -ENOIOCTLCMD; } int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) { - return -ENOTSUPP; + return -ENOIOCTLCMD; } int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) @@ -627,6 +888,9 @@ int kvm_dev_ioctl_check_extension(long ext) int r; switch (ext) { + case KVM_CAP_ONE_REG: + r = 1; + break; case KVM_CAP_COALESCED_MMIO: r = KVM_COALESCED_MMIO_PAGE_OFFSET; break; @@ -635,7 +899,6 @@ int kvm_dev_ioctl_check_extension(long ext) break; } return r; - } int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) @@ -677,28 +940,28 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) { int i; - for (i = 0; i < 32; i++) - vcpu->arch.gprs[i] = regs->gprs[i]; - + for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++) + vcpu->arch.gprs[i] = regs->gpr[i]; + vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */ vcpu->arch.hi = regs->hi; vcpu->arch.lo = regs->lo; vcpu->arch.pc = regs->pc; - return kvm_mips_callbacks->vcpu_ioctl_set_regs(vcpu, regs); + return 0; } int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) { int i; - for (i = 0; i < 32; i++) - regs->gprs[i] = vcpu->arch.gprs[i]; + for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++) + regs->gpr[i] = vcpu->arch.gprs[i]; regs->hi = vcpu->arch.hi; regs->lo = vcpu->arch.lo; regs->pc = vcpu->arch.pc; - return kvm_mips_callbacks->vcpu_ioctl_get_regs(vcpu, regs); + return 0; } void kvm_mips_comparecount_func(unsigned long data) diff --git a/arch/mips/kvm/kvm_tlb.c b/arch/mips/kvm/kvm_tlb.c index e3f0d9b8b6c..c777dd36d4a 100644 --- a/arch/mips/kvm/kvm_tlb.c +++ b/arch/mips/kvm/kvm_tlb.c @@ -17,6 +17,8 @@ #include <linux/delay.h> #include <linux/module.h> #include <linux/kvm_host.h> +#include <linux/srcu.h> + #include <asm/cpu.h> #include <asm/bootinfo.h> @@ -169,21 +171,27 @@ void kvm_mips_dump_shadow_tlbs(struct kvm_vcpu *vcpu) } } -static void kvm_mips_map_page(struct kvm *kvm, gfn_t gfn) +static int kvm_mips_map_page(struct kvm *kvm, gfn_t gfn) { + int srcu_idx, err = 0; pfn_t pfn; if (kvm->arch.guest_pmap[gfn] != KVM_INVALID_PAGE) - return; + return 0; + srcu_idx = srcu_read_lock(&kvm->srcu); pfn = kvm_mips_gfn_to_pfn(kvm, gfn); if (kvm_mips_is_error_pfn(pfn)) { - panic("Couldn't get pfn for gfn %#" PRIx64 "!\n", gfn); + kvm_err("Couldn't get pfn for gfn %#" PRIx64 "!\n", gfn); + err = -EFAULT; + goto out; } kvm->arch.guest_pmap[gfn] = pfn; - return; +out: + srcu_read_unlock(&kvm->srcu, srcu_idx); + return err; } /* Translate guest KSEG0 addresses to Host PA */ @@ -207,7 +215,10 @@ unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu, gva); return KVM_INVALID_PAGE; } - kvm_mips_map_page(vcpu->kvm, gfn); + + if (kvm_mips_map_page(vcpu->kvm, gfn) < 0) + return KVM_INVALID_ADDR; + return (kvm->arch.guest_pmap[gfn] << PAGE_SHIFT) + offset; } @@ -310,8 +321,11 @@ int kvm_mips_handle_kseg0_tlb_fault(unsigned long badvaddr, even = !(gfn & 0x1); vaddr = badvaddr & (PAGE_MASK << 1); - kvm_mips_map_page(vcpu->kvm, gfn); - kvm_mips_map_page(vcpu->kvm, gfn ^ 0x1); + if (kvm_mips_map_page(vcpu->kvm, gfn) < 0) + return -1; + + if (kvm_mips_map_page(vcpu->kvm, gfn ^ 0x1) < 0) + return -1; if (even) { pfn0 = kvm->arch.guest_pmap[gfn]; @@ -389,8 +403,11 @@ kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu, pfn0 = 0; pfn1 = 0; } else { - kvm_mips_map_page(kvm, mips3_tlbpfn_to_paddr(tlb->tlb_lo0) >> PAGE_SHIFT); - kvm_mips_map_page(kvm, mips3_tlbpfn_to_paddr(tlb->tlb_lo1) >> PAGE_SHIFT); + if (kvm_mips_map_page(kvm, mips3_tlbpfn_to_paddr(tlb->tlb_lo0) >> PAGE_SHIFT) < 0) + return -1; + + if (kvm_mips_map_page(kvm, mips3_tlbpfn_to_paddr(tlb->tlb_lo1) >> PAGE_SHIFT) < 0) + return -1; pfn0 = kvm->arch.guest_pmap[mips3_tlbpfn_to_paddr(tlb->tlb_lo0) >> PAGE_SHIFT]; pfn1 = kvm->arch.guest_pmap[mips3_tlbpfn_to_paddr(tlb->tlb_lo1) >> PAGE_SHIFT]; diff --git a/arch/mips/kvm/kvm_trap_emul.c b/arch/mips/kvm/kvm_trap_emul.c index 466aeef044b..30d725321db 100644 --- a/arch/mips/kvm/kvm_trap_emul.c +++ b/arch/mips/kvm/kvm_trap_emul.c @@ -345,54 +345,6 @@ static int kvm_trap_emul_handle_break(struct kvm_vcpu *vcpu) return ret; } -static int -kvm_trap_emul_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) -{ - struct mips_coproc *cop0 = vcpu->arch.cop0; - - kvm_write_c0_guest_index(cop0, regs->cp0reg[MIPS_CP0_TLB_INDEX][0]); - kvm_write_c0_guest_context(cop0, regs->cp0reg[MIPS_CP0_TLB_CONTEXT][0]); - kvm_write_c0_guest_badvaddr(cop0, regs->cp0reg[MIPS_CP0_BAD_VADDR][0]); - kvm_write_c0_guest_entryhi(cop0, regs->cp0reg[MIPS_CP0_TLB_HI][0]); - kvm_write_c0_guest_epc(cop0, regs->cp0reg[MIPS_CP0_EXC_PC][0]); - - kvm_write_c0_guest_status(cop0, regs->cp0reg[MIPS_CP0_STATUS][0]); - kvm_write_c0_guest_cause(cop0, regs->cp0reg[MIPS_CP0_CAUSE][0]); - kvm_write_c0_guest_pagemask(cop0, - regs->cp0reg[MIPS_CP0_TLB_PG_MASK][0]); - kvm_write_c0_guest_wired(cop0, regs->cp0reg[MIPS_CP0_TLB_WIRED][0]); - kvm_write_c0_guest_errorepc(cop0, regs->cp0reg[MIPS_CP0_ERROR_PC][0]); - - return 0; -} - -static int -kvm_trap_emul_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) -{ - struct mips_coproc *cop0 = vcpu->arch.cop0; - - regs->cp0reg[MIPS_CP0_TLB_INDEX][0] = kvm_read_c0_guest_index(cop0); - regs->cp0reg[MIPS_CP0_TLB_CONTEXT][0] = kvm_read_c0_guest_context(cop0); - regs->cp0reg[MIPS_CP0_BAD_VADDR][0] = kvm_read_c0_guest_badvaddr(cop0); - regs->cp0reg[MIPS_CP0_TLB_HI][0] = kvm_read_c0_guest_entryhi(cop0); - regs->cp0reg[MIPS_CP0_EXC_PC][0] = kvm_read_c0_guest_epc(cop0); - - regs->cp0reg[MIPS_CP0_STATUS][0] = kvm_read_c0_guest_status(cop0); - regs->cp0reg[MIPS_CP0_CAUSE][0] = kvm_read_c0_guest_cause(cop0); - regs->cp0reg[MIPS_CP0_TLB_PG_MASK][0] = - kvm_read_c0_guest_pagemask(cop0); - regs->cp0reg[MIPS_CP0_TLB_WIRED][0] = kvm_read_c0_guest_wired(cop0); - regs->cp0reg[MIPS_CP0_ERROR_PC][0] = kvm_read_c0_guest_errorepc(cop0); - - regs->cp0reg[MIPS_CP0_CONFIG][0] = kvm_read_c0_guest_config(cop0); - regs->cp0reg[MIPS_CP0_CONFIG][1] = kvm_read_c0_guest_config1(cop0); - regs->cp0reg[MIPS_CP0_CONFIG][2] = kvm_read_c0_guest_config2(cop0); - regs->cp0reg[MIPS_CP0_CONFIG][3] = kvm_read_c0_guest_config3(cop0); - regs->cp0reg[MIPS_CP0_CONFIG][7] = kvm_read_c0_guest_config7(cop0); - - return 0; -} - static int kvm_trap_emul_vm_init(struct kvm *kvm) { return 0; @@ -471,8 +423,6 @@ static struct kvm_mips_callbacks kvm_trap_emul_callbacks = { .dequeue_io_int = kvm_mips_dequeue_io_int_cb, .irq_deliver = kvm_mips_irq_deliver_cb, .irq_clear = kvm_mips_irq_clear_cb, - .vcpu_ioctl_get_regs = kvm_trap_emul_ioctl_get_regs, - .vcpu_ioctl_set_regs = kvm_trap_emul_ioctl_set_regs, }; int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks) diff --git a/arch/mips/loongson/common/reset.c b/arch/mips/loongson/common/reset.c index 35c8c646849..65bfbb5d06f 100644 --- a/arch/mips/loongson/common/reset.c +++ b/arch/mips/loongson/common/reset.c @@ -12,6 +12,7 @@ #include <linux/init.h> #include <linux/pm.h> +#include <asm/idle.h> #include <asm/reboot.h> #include <loongson.h> diff --git a/arch/mips/loongson1/common/reset.c b/arch/mips/loongson1/common/reset.c index d4f610f9604..547f34b69e4 100644 --- a/arch/mips/loongson1/common/reset.c +++ b/arch/mips/loongson1/common/reset.c @@ -9,6 +9,7 @@ #include <linux/io.h> #include <linux/pm.h> +#include <asm/idle.h> #include <asm/reboot.h> #include <loongson1.h> diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index ce9818eef7d..afeef93f81a 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -301,10 +301,6 @@ static u32 tlb_handler[128] __cpuinitdata; static struct uasm_label labels[128] __cpuinitdata; static struct uasm_reloc relocs[128] __cpuinitdata; -#ifdef CONFIG_64BIT -static int check_for_high_segbits __cpuinitdata; -#endif - static int check_for_high_segbits __cpuinitdata; static unsigned int kscratch_used_mask __cpuinitdata; diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c index af319143b59..eaa99d28cb8 100644 --- a/arch/mips/netlogic/xlp/setup.c +++ b/arch/mips/netlogic/xlp/setup.c @@ -37,6 +37,7 @@ #include <linux/pm.h> #include <linux/bootmem.h> +#include <asm/idle.h> #include <asm/reboot.h> #include <asm/time.h> #include <asm/bootinfo.h> diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c index e3e094100e3..89c8c106663 100644 --- a/arch/mips/netlogic/xlr/setup.c +++ b/arch/mips/netlogic/xlr/setup.c @@ -36,6 +36,7 @@ #include <linux/serial_8250.h> #include <linux/pm.h> +#include <asm/idle.h> #include <asm/reboot.h> #include <asm/time.h> #include <asm/bootinfo.h> diff --git a/arch/mips/pmcs-msp71xx/msp_setup.c b/arch/mips/pmcs-msp71xx/msp_setup.c index 1651cfdbfe7..396b2967ad8 100644 --- a/arch/mips/pmcs-msp71xx/msp_setup.c +++ b/arch/mips/pmcs-msp71xx/msp_setup.c @@ -12,6 +12,7 @@ #include <asm/bootinfo.h> #include <asm/cacheflush.h> +#include <asm/idle.h> #include <asm/r4kcache.h> #include <asm/reboot.h> #include <asm/smp-ops.h> diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c index fb1569580de..6b5f3406f41 100644 --- a/arch/mips/ralink/of.c +++ b/arch/mips/ralink/of.c @@ -88,7 +88,7 @@ void __init plat_mem_setup(void) __dt_setup_arch(&__dtb_start); if (soc_info.mem_size) - add_memory_region(soc_info.mem_base, soc_info.mem_size, + add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M, BOOT_MEM_RAM); else detect_memory_region(soc_info.mem_base, diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index 5364aabc210..681e7f86c08 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -26,6 +26,7 @@ #include <linux/slab.h> #include <linux/irq.h> #include <asm/bootinfo.h> +#include <asm/idle.h> #include <asm/time.h> #include <asm/reboot.h> #include <asm/r4kcache.h> diff --git a/arch/mips/vr41xx/common/pmu.c b/arch/mips/vr41xx/common/pmu.c index 70a3f90131d..d7f755833c3 100644 --- a/arch/mips/vr41xx/common/pmu.c +++ b/arch/mips/vr41xx/common/pmu.c @@ -27,6 +27,7 @@ #include <asm/cacheflush.h> #include <asm/cpu.h> +#include <asm/idle.h> #include <asm/io.h> #include <asm/processor.h> #include <asm/reboot.h> diff --git a/arch/mips/wrppmc/reset.c b/arch/mips/wrppmc/reset.c index cc5474b24f0..80beb188ed4 100644 --- a/arch/mips/wrppmc/reset.c +++ b/arch/mips/wrppmc/reset.c @@ -9,6 +9,7 @@ #include <linux/kernel.h> #include <asm/cacheflush.h> +#include <asm/idle.h> #include <asm/mipsregs.h> #include <asm/processor.h> diff --git a/arch/mn10300/include/asm/pci.h b/arch/mn10300/include/asm/pci.h index 8137c25c4e1..6f31cc0f1a8 100644 --- a/arch/mn10300/include/asm/pci.h +++ b/arch/mn10300/include/asm/pci.h @@ -103,4 +103,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) return channel ? 15 : 14; } +#include <asm-generic/pci_iomap.h> + #endif /* _ASM_PCI_H */ diff --git a/arch/mn10300/kernel/entry.S b/arch/mn10300/kernel/entry.S index 68fcab8f8f6..222152a3f75 100644 --- a/arch/mn10300/kernel/entry.S +++ b/arch/mn10300/kernel/entry.S @@ -60,6 +60,7 @@ ENTRY(ret_from_kernel_thread) mov (REG_D0,fp),d0 mov (REG_A0,fp),a0 calls (a0) + GET_THREAD_INFO a2 # A2 must be set on return from sys_exit() clr d0 mov d0,(REG_D0,fp) jmp syscall_exit @@ -107,10 +108,10 @@ syscall_exit_work: and EPSW_nSL,d0 beq resume_kernel # returning to supervisor mode - btst _TIF_SYSCALL_TRACE,d2 - beq work_pending LOCAL_IRQ_ENABLE # could let syscall_trace_exit() call # schedule() instead + btst _TIF_SYSCALL_TRACE,d2 + beq work_pending mov fp,d0 call syscall_trace_exit[],0 # do_syscall_trace(regs) jmp resume_userspace @@ -123,6 +124,7 @@ work_pending: work_resched: call schedule[],0 +resume_userspace: # make sure we don't miss an interrupt setting need_resched or # sigpending between sampling and the rti LOCAL_IRQ_DISABLE @@ -131,6 +133,8 @@ work_resched: mov (TI_flags,a2),d2 btst _TIF_WORK_MASK,d2 beq restore_all + + LOCAL_IRQ_ENABLE btst _TIF_NEED_RESCHED,d2 bne work_resched @@ -169,17 +173,6 @@ ret_from_intr: and EPSW_nSL,d0 beq resume_kernel # returning to supervisor mode -ENTRY(resume_userspace) - # make sure we don't miss an interrupt setting need_resched or - # sigpending between sampling and the rti - LOCAL_IRQ_DISABLE - - # is there any work to be done on int/exception return? - mov (TI_flags,a2),d2 - btst _TIF_WORK_MASK,d2 - bne work_pending - jmp restore_all - #ifdef CONFIG_PREEMPT ENTRY(resume_kernel) LOCAL_IRQ_DISABLE diff --git a/arch/mn10300/unit-asb2305/pci.c b/arch/mn10300/unit-asb2305/pci.c index 1adcf024bb9..e37fac0461f 100644 --- a/arch/mn10300/unit-asb2305/pci.c +++ b/arch/mn10300/unit-asb2305/pci.c @@ -19,6 +19,7 @@ #include <linux/delay.h> #include <linux/irq.h> #include <asm/io.h> +#include <asm/irq.h> #include "pci-asb2305.h" unsigned int pci_probe = 1; diff --git a/arch/parisc/Makefile b/arch/parisc/Makefile index 197690068f8..96ec3982be8 100644 --- a/arch/parisc/Makefile +++ b/arch/parisc/Makefile @@ -66,7 +66,7 @@ KBUILD_CFLAGS_KERNEL += -mlong-calls endif # select which processor to optimise for -cflags-$(CONFIG_PA7100) += -march=1.1 -mschedule=7100 +cflags-$(CONFIG_PA7000) += -march=1.1 -mschedule=7100 cflags-$(CONFIG_PA7200) += -march=1.1 -mschedule=7200 cflags-$(CONFIG_PA7100LC) += -march=1.1 -mschedule=7100LC cflags-$(CONFIG_PA7300LC) += -march=1.1 -mschedule=7300 diff --git a/arch/parisc/include/asm/assembly.h b/arch/parisc/include/asm/assembly.h index 89fb40005e3..0da84823234 100644 --- a/arch/parisc/include/asm/assembly.h +++ b/arch/parisc/include/asm/assembly.h @@ -438,7 +438,6 @@ SAVE_SP (%sr4, PT_SR4 (\regs)) SAVE_SP (%sr5, PT_SR5 (\regs)) SAVE_SP (%sr6, PT_SR6 (\regs)) - SAVE_SP (%sr7, PT_SR7 (\regs)) SAVE_CR (%cr17, PT_IASQ0(\regs)) mtctl %r0, %cr17 diff --git a/arch/parisc/include/asm/hardirq.h b/arch/parisc/include/asm/hardirq.h index c19f7138ba4..241c3451846 100644 --- a/arch/parisc/include/asm/hardirq.h +++ b/arch/parisc/include/asm/hardirq.h @@ -17,17 +17,14 @@ typedef struct { unsigned int __softirq_pending; -#ifdef CONFIG_DEBUG_STACKOVERFLOW unsigned int kernel_stack_usage; -#ifdef CONFIG_IRQSTACKS unsigned int irq_stack_usage; - unsigned int irq_stack_counter; -#endif -#endif #ifdef CONFIG_SMP unsigned int irq_resched_count; unsigned int irq_call_count; #endif + unsigned int irq_unaligned_count; + unsigned int irq_fpassist_count; unsigned int irq_tlb_count; } ____cacheline_aligned irq_cpustat_t; diff --git a/arch/parisc/include/asm/mmzone.h b/arch/parisc/include/asm/mmzone.h index 0e625ab9aae..cc50d33b7b8 100644 --- a/arch/parisc/include/asm/mmzone.h +++ b/arch/parisc/include/asm/mmzone.h @@ -39,17 +39,14 @@ extern unsigned char pfnnid_map[PFNNID_MAP_MAX]; static inline int pfn_to_nid(unsigned long pfn) { unsigned int i; - unsigned char r; if (unlikely(pfn_is_io(pfn))) return 0; i = pfn >> PFNNID_SHIFT; BUG_ON(i >= ARRAY_SIZE(pfnnid_map)); - r = pfnnid_map[i]; - BUG_ON(r == 0xff); - return (int)r; + return (int)pfnnid_map[i]; } static inline int pfn_valid(int pfn) diff --git a/arch/parisc/include/asm/processor.h b/arch/parisc/include/asm/processor.h index cfbc43929cf..cc2290a3cac 100644 --- a/arch/parisc/include/asm/processor.h +++ b/arch/parisc/include/asm/processor.h @@ -17,7 +17,6 @@ #include <asm/ptrace.h> #include <asm/types.h> #include <asm/percpu.h> - #endif /* __ASSEMBLY__ */ /* @@ -59,26 +58,6 @@ #ifndef __ASSEMBLY__ /* - * IRQ STACK - used for irq handler - */ -#ifdef __KERNEL__ - -#include <linux/spinlock_types.h> - -#define IRQ_STACK_SIZE (4096 << 2) /* 16k irq stack size */ - -union irq_stack_union { - unsigned long stack[IRQ_STACK_SIZE/sizeof(unsigned long)]; - raw_spinlock_t lock; -}; - -DECLARE_PER_CPU(union irq_stack_union, irq_stack_union); - -void call_on_stack(unsigned long p1, void *func, unsigned long new_stack); - -#endif /* __KERNEL__ */ - -/* * Data detected about CPUs at boot time which is the same for all CPU's. * HP boxes are SMP - ie identical processors. * diff --git a/arch/parisc/kernel/drivers.c b/arch/parisc/kernel/drivers.c index 5709c5e59be..14285caec71 100644 --- a/arch/parisc/kernel/drivers.c +++ b/arch/parisc/kernel/drivers.c @@ -394,7 +394,7 @@ EXPORT_SYMBOL(print_pci_hwpath); static void setup_bus_id(struct parisc_device *padev) { struct hardware_path path; - char name[20]; + char name[28]; char *output = name; int i; diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S index ae27cb6ce19..e8f07dd2840 100644 --- a/arch/parisc/kernel/entry.S +++ b/arch/parisc/kernel/entry.S @@ -65,15 +65,11 @@ rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */ mtsp %r0, %sr4 mtsp %r0, %sr5 - mfsp %sr7, %r1 - or,= %r0,%r1,%r0 /* Only save sr7 in sr3 if sr7 != 0 */ - mtsp %r1, %sr3 + mtsp %r0, %sr6 tovirt_r1 %r29 load32 KERNEL_PSW, %r1 rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */ - mtsp %r0, %sr6 - mtsp %r0, %sr7 mtctl %r0, %cr17 /* Clear IIASQ tail */ mtctl %r0, %cr17 /* Clear IIASQ head */ mtctl %r1, %ipsw @@ -119,17 +115,20 @@ /* we save the registers in the task struct */ + copy %r30, %r17 mfctl %cr30, %r1 + ldo THREAD_SZ_ALGN(%r1), %r30 + mtsp %r0,%sr7 + mtsp %r16,%sr3 tophys %r1,%r9 LDREG TI_TASK(%r9), %r1 /* thread_info -> task_struct */ tophys %r1,%r9 ldo TASK_REGS(%r9),%r9 - STREG %r30, PT_GR30(%r9) + STREG %r17,PT_GR30(%r9) STREG %r29,PT_GR29(%r9) STREG %r26,PT_GR26(%r9) + STREG %r16,PT_SR7(%r9) copy %r9,%r29 - mfctl %cr30, %r1 - ldo THREAD_SZ_ALGN(%r1), %r30 .endm .macro get_stack_use_r30 @@ -137,10 +136,12 @@ /* we put a struct pt_regs on the stack and save the registers there */ tophys %r30,%r9 - STREG %r30,PT_GR30(%r9) + copy %r30,%r1 ldo PT_SZ_ALGN(%r30),%r30 + STREG %r1,PT_GR30(%r9) STREG %r29,PT_GR29(%r9) STREG %r26,PT_GR26(%r9) + STREG %r16,PT_SR7(%r9) copy %r9,%r29 .endm diff --git a/arch/parisc/kernel/hardware.c b/arch/parisc/kernel/hardware.c index f7752f6af29..9e2d2e40852 100644 --- a/arch/parisc/kernel/hardware.c +++ b/arch/parisc/kernel/hardware.c @@ -222,6 +222,7 @@ static struct hp_hardware hp_hardware_list[] = { {HPHW_NPROC,0x5DD,0x4,0x81,"Duet W2"}, {HPHW_NPROC,0x5DE,0x4,0x81,"Piccolo W+"}, {HPHW_NPROC,0x5DF,0x4,0x81,"Cantata W2"}, + {HPHW_NPROC,0x5DF,0x0,0x00,"Marcato W+? (rp5470)"}, {HPHW_NPROC,0x5E0,0x4,0x91,"Cantata DC- W2"}, {HPHW_NPROC,0x5E1,0x4,0x91,"Crescendo DC- W2"}, {HPHW_NPROC,0x5E2,0x4,0x91,"Crescendo 650 W2"}, diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c index 55237a70e19..2e6443b1e92 100644 --- a/arch/parisc/kernel/irq.c +++ b/arch/parisc/kernel/irq.c @@ -27,11 +27,11 @@ #include <linux/interrupt.h> #include <linux/kernel_stat.h> #include <linux/seq_file.h> -#include <linux/spinlock.h> #include <linux/types.h> #include <asm/io.h> #include <asm/smp.h> +#include <asm/ldcw.h> #undef PARISC_IRQ_CR16_COUNTS @@ -172,10 +172,6 @@ int arch_show_interrupts(struct seq_file *p, int prec) for_each_online_cpu(j) seq_printf(p, "%10u ", irq_stats(j)->irq_stack_usage); seq_puts(p, " Interrupt stack usage\n"); - seq_printf(p, "%*s: ", prec, "ISC"); - for_each_online_cpu(j) - seq_printf(p, "%10u ", irq_stats(j)->irq_stack_counter); - seq_puts(p, " Interrupt stack usage counter\n"); # endif #endif #ifdef CONFIG_SMP @@ -188,6 +184,14 @@ int arch_show_interrupts(struct seq_file *p, int prec) seq_printf(p, "%10u ", irq_stats(j)->irq_call_count); seq_puts(p, " Function call interrupts\n"); #endif + seq_printf(p, "%*s: ", prec, "UAH"); + for_each_online_cpu(j) + seq_printf(p, "%10u ", irq_stats(j)->irq_unaligned_count); + seq_puts(p, " Unaligned access handler traps\n"); + seq_printf(p, "%*s: ", prec, "FPA"); + for_each_online_cpu(j) + seq_printf(p, "%10u ", irq_stats(j)->irq_fpassist_count); + seq_puts(p, " Floating point assist traps\n"); seq_printf(p, "%*s: ", prec, "TLB"); for_each_online_cpu(j) seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count); @@ -376,6 +380,24 @@ static inline int eirr_to_irq(unsigned long eirr) return (BITS_PER_LONG - bit) + TIMER_IRQ; } +#ifdef CONFIG_IRQSTACKS +/* + * IRQ STACK - used for irq handler + */ +#define IRQ_STACK_SIZE (4096 << 2) /* 16k irq stack size */ + +union irq_stack_union { + unsigned long stack[IRQ_STACK_SIZE/sizeof(unsigned long)]; + volatile unsigned int slock[4]; + volatile unsigned int lock[1]; +}; + +DEFINE_PER_CPU(union irq_stack_union, irq_stack_union) = { + .slock = { 1,1,1,1 }, + }; +#endif + + int sysctl_panic_on_stackoverflow = 1; static inline void stack_overflow_check(struct pt_regs *regs) @@ -442,27 +464,26 @@ panic_check: } #ifdef CONFIG_IRQSTACKS -DEFINE_PER_CPU(union irq_stack_union, irq_stack_union) = { - .lock = __RAW_SPIN_LOCK_UNLOCKED((irq_stack_union).lock) - }; +/* in entry.S: */ +void call_on_stack(unsigned long p1, void *func, unsigned long new_stack); static void execute_on_irq_stack(void *func, unsigned long param1) { union irq_stack_union *union_ptr; unsigned long irq_stack; - raw_spinlock_t *irq_stack_in_use; + volatile unsigned int *irq_stack_in_use; union_ptr = &per_cpu(irq_stack_union, smp_processor_id()); irq_stack = (unsigned long) &union_ptr->stack; - irq_stack = ALIGN(irq_stack + sizeof(irq_stack_union.lock), + irq_stack = ALIGN(irq_stack + sizeof(irq_stack_union.slock), 64); /* align for stack frame usage */ /* We may be called recursive. If we are already using the irq stack, * just continue to use it. Use spinlocks to serialize * the irq stack usage. */ - irq_stack_in_use = &union_ptr->lock; - if (!raw_spin_trylock(irq_stack_in_use)) { + irq_stack_in_use = (volatile unsigned int *)__ldcw_align(union_ptr); + if (!__ldcw(irq_stack_in_use)) { void (*direct_call)(unsigned long p1) = func; /* We are using the IRQ stack already. @@ -474,10 +495,8 @@ static void execute_on_irq_stack(void *func, unsigned long param1) /* This is where we switch to the IRQ stack. */ call_on_stack(param1, func, irq_stack); - __inc_irq_stat(irq_stack_counter); - /* free up irq stack usage. */ - do_raw_spin_unlock(irq_stack_in_use); + *irq_stack_in_use = 1; } asmlinkage void do_softirq(void) diff --git a/arch/parisc/kernel/pacache.S b/arch/parisc/kernel/pacache.S index 5e1de6072be..36d7f402e48 100644 --- a/arch/parisc/kernel/pacache.S +++ b/arch/parisc/kernel/pacache.S @@ -605,14 +605,14 @@ ENTRY(copy_user_page_asm) convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */ convert_phys_for_tlb_insert20 %r23 /* convert phys addr to tlb insert format */ depd %r24,63,22, %r28 /* Form aliased virtual address 'to' */ - depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */ + depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */ copy %r28, %r29 depdi 1, 41,1, %r29 /* Form aliased virtual address 'from' */ #else extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */ extrw,u %r23, 24,25, %r23 /* convert phys addr to tlb insert format */ depw %r24, 31,22, %r28 /* Form aliased virtual address 'to' */ - depwi 0, 31,12, %r28 /* Clear any offset bits */ + depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */ copy %r28, %r29 depwi 1, 9,1, %r29 /* Form aliased virtual address 'from' */ #endif @@ -762,7 +762,7 @@ ENTRY(clear_user_page_asm) #else extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */ depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */ - depwi 0, 31,12, %r28 /* Clear any offset bits */ + depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */ #endif /* Purge any old translation */ @@ -846,7 +846,7 @@ ENTRY(flush_dcache_page_asm) #else extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */ depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */ - depwi 0, 31,12, %r28 /* Clear any offset bits */ + depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */ #endif /* Purge any old translation */ @@ -918,11 +918,11 @@ ENTRY(flush_icache_page_asm) #endif convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */ depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */ - depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */ + depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */ #else extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */ depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */ - depwi 0, 31,12, %r28 /* Clear any offset bits */ + depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */ #endif /* Purge any old translation */ diff --git a/arch/parisc/kernel/setup.c b/arch/parisc/kernel/setup.c index 76b63e726a5..1e95b2000ce 100644 --- a/arch/parisc/kernel/setup.c +++ b/arch/parisc/kernel/setup.c @@ -69,7 +69,8 @@ void __init setup_cmdline(char **cmdline_p) /* called from hpux boot loader */ boot_command_line[0] = '\0'; } else { - strcpy(boot_command_line, (char *)__va(boot_args[1])); + strlcpy(boot_command_line, (char *)__va(boot_args[1]), + COMMAND_LINE_SIZE); #ifdef CONFIG_BLK_DEV_INITRD if (boot_args[2] != 0) /* did palo pass us a ramdisk? */ diff --git a/arch/parisc/kernel/traps.c b/arch/parisc/kernel/traps.c index fe41a98043b..04e47c6a456 100644 --- a/arch/parisc/kernel/traps.c +++ b/arch/parisc/kernel/traps.c @@ -646,6 +646,7 @@ void notrace handle_interruption(int code, struct pt_regs *regs) case 14: /* Assist Exception Trap, i.e. floating point exception. */ die_if_kernel("Floating point exception", regs, 0); /* quiet */ + __inc_irq_stat(irq_fpassist_count); handle_fpe(regs); return; diff --git a/arch/parisc/kernel/unaligned.c b/arch/parisc/kernel/unaligned.c index 234e3682cf0..d7c0acb35ec 100644 --- a/arch/parisc/kernel/unaligned.c +++ b/arch/parisc/kernel/unaligned.c @@ -27,6 +27,7 @@ #include <linux/signal.h> #include <linux/ratelimit.h> #include <asm/uaccess.h> +#include <asm/hardirq.h> /* #define DEBUG_UNALIGNED 1 */ @@ -454,6 +455,8 @@ void handle_unaligned(struct pt_regs *regs) struct siginfo si; register int flop=0; /* true if this is a flop */ + __inc_irq_stat(irq_unaligned_count); + /* log a message with pacing */ if (user_mode(regs)) { if (current->thread.flags & PARISC_UAC_SIGBUS) { diff --git a/arch/powerpc/configs/ps3_defconfig b/arch/powerpc/configs/ps3_defconfig index f7919623291..139a8308070 100644 --- a/arch/powerpc/configs/ps3_defconfig +++ b/arch/powerpc/configs/ps3_defconfig @@ -136,7 +136,6 @@ CONFIG_HID_SMARTJOYPLUS=m CONFIG_USB_HIDDEV=y CONFIG_USB=m CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_SUSPEND=y CONFIG_USB_MON=m CONFIG_USB_EHCI_HCD=m # CONFIG_USB_EHCI_HCD_PPC_OF is not set diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index 26807e5aff5..6f3887d884d 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -176,6 +176,7 @@ extern const char *powerpc_base_platform; #define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000) #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000) #define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000) +#define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000) #ifndef __ASSEMBLY__ @@ -394,19 +395,20 @@ extern const char *powerpc_base_platform; CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \ CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \ - CPU_FTR_HVMODE) + CPU_FTR_HVMODE | CPU_FTR_DABRX) #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ CPU_FTR_MMCRA | CPU_FTR_SMT | \ CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \ - CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB) + CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX) #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ CPU_FTR_MMCRA | CPU_FTR_SMT | \ CPU_FTR_COHERENT_ICACHE | \ CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ - CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR) + CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \ + CPU_FTR_DABRX) #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ CPU_FTR_MMCRA | CPU_FTR_SMT | \ @@ -415,7 +417,7 @@ extern const char *powerpc_base_platform; CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \ - CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR) + CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX) #define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ CPU_FTR_MMCRA | CPU_FTR_SMT | \ @@ -430,14 +432,15 @@ extern const char *powerpc_base_platform; CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ - CPU_FTR_UNALIGNED_LD_STD) + CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX) #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \ - CPU_FTR_PURR | CPU_FTR_REAL_LE) + CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX) #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \ - CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX) + CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | \ + CPU_FTR_ICSWX | CPU_FTR_DABRX ) #ifdef __powerpc64__ #ifdef CONFIG_PPC_BOOK3E diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index 8e5fae8beaf..46793b58a76 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -513,7 +513,7 @@ label##_common: \ */ #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \ EXCEPTION_COMMON(trap, label, hdlr, ret_from_except_lite, \ - FINISH_NAP;RUNLATCH_ON;DISABLE_INTS) + FINISH_NAP;DISABLE_INTS;RUNLATCH_ON) /* * When the idle code in power4_idle puts the CPU into NAP mode, diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h index cf4df8e2139..0c7f2bfcf13 100644 --- a/arch/powerpc/include/asm/hvcall.h +++ b/arch/powerpc/include/asm/hvcall.h @@ -264,6 +264,7 @@ #define H_GET_MPP 0x2D4 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC #define H_BEST_ENERGY 0x2F4 +#define H_XIRR_X 0x2FC #define H_RANDOM 0x300 #define H_COP 0x304 #define H_GET_MPP_X 0x314 diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h index b9dd382cb34..851bac7afa4 100644 --- a/arch/powerpc/include/asm/kvm_asm.h +++ b/arch/powerpc/include/asm/kvm_asm.h @@ -54,8 +54,16 @@ #define BOOKE_INTERRUPT_DEBUG 15 /* E500 */ -#define BOOKE_INTERRUPT_SPE_UNAVAIL 32 -#define BOOKE_INTERRUPT_SPE_FP_DATA 33 +#define BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL 32 +#define BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST 33 +/* + * TODO: Unify 32-bit and 64-bit kernel exception handlers to use same defines + */ +#define BOOKE_INTERRUPT_SPE_UNAVAIL BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL +#define BOOKE_INTERRUPT_SPE_FP_DATA BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST +#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL +#define BOOKE_INTERRUPT_ALTIVEC_ASSIST \ + BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST #define BOOKE_INTERRUPT_SPE_FP_ROUND 34 #define BOOKE_INTERRUPT_PERFORMANCE_MONITOR 35 #define BOOKE_INTERRUPT_DOORBELL 36 @@ -67,10 +75,6 @@ #define BOOKE_INTERRUPT_HV_SYSCALL 40 #define BOOKE_INTERRUPT_HV_PRIV 41 -/* altivec */ -#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL 42 -#define BOOKE_INTERRUPT_ALTIVEC_ASSIST 43 - /* book3s */ #define BOOK3S_INTERRUPT_SYSTEM_RESET 0x100 diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h index 8b11b5bd993..2c1d8cb9b26 100644 --- a/arch/powerpc/include/asm/pci-bridge.h +++ b/arch/powerpc/include/asm/pci-bridge.h @@ -174,6 +174,8 @@ struct pci_dn { /* Get the pointer to a device_node's pci_dn */ #define PCI_DN(dn) ((struct pci_dn *) (dn)->data) +extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev); + extern void * update_dn_pci_info(struct device_node *dn, void *data); static inline int pci_device_from_OF_node(struct device_node *np, diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h index cea8496091f..2f1b6c5f817 100644 --- a/arch/powerpc/include/asm/ppc_asm.h +++ b/arch/powerpc/include/asm/ppc_asm.h @@ -523,6 +523,17 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,946) #define PPC440EP_ERR42 #endif +/* The following stops all load and store data streams associated with stream + * ID (ie. streams created explicitly). The embedded and server mnemonics for + * dcbt are different so we use machine "power4" here explicitly. + */ +#define DCBT_STOP_ALL_STREAM_IDS(scratch) \ +.machine push ; \ +.machine "power4" ; \ + lis scratch,0x60000000@h; \ + dcbt r0,scratch,0b01010; \ +.machine pop + /* * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them * keep the address intact to be compatible with code shared with diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index d7e67ca8b4a..14a65836369 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -284,6 +284,12 @@ struct thread_struct { unsigned long ebbrr; unsigned long ebbhr; unsigned long bescr; + unsigned long siar; + unsigned long sdar; + unsigned long sier; + unsigned long mmcr0; + unsigned long mmcr2; + unsigned long mmcra; #endif }; @@ -403,21 +409,16 @@ static inline void prefetchw(const void *x) #endif #ifdef CONFIG_PPC64 -static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32) +static inline unsigned long get_clean_sp(unsigned long sp, int is_32) { - unsigned long sp; - if (is_32) - sp = regs->gpr[1] & 0x0ffffffffUL; - else - sp = regs->gpr[1]; - + return sp & 0x0ffffffffUL; return sp; } #else -static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32) +static inline unsigned long get_clean_sp(unsigned long sp, int is_32) { - return regs->gpr[1]; + return sp; } #endif diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index a6136515c7f..4a9e408644f 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -111,17 +111,6 @@ #define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T) #define MSR_TM_SUSPENDED(x) (((x) & MSR_TS_MASK) == MSR_TS_S) -/* Reason codes describing kernel causes for transaction aborts. By - convention, bit0 is copied to TEXASR[56] (IBM bit 7) which is set if - the failure is persistent. -*/ -#define TM_CAUSE_RESCHED 0xfe -#define TM_CAUSE_TLBI 0xfc -#define TM_CAUSE_FAC_UNAV 0xfa -#define TM_CAUSE_SYSCALL 0xf9 /* Persistent */ -#define TM_CAUSE_MISC 0xf6 -#define TM_CAUSE_SIGNAL 0xf4 - #if defined(CONFIG_PPC_BOOK3S_64) #define MSR_64BIT MSR_SF diff --git a/arch/powerpc/include/asm/signal.h b/arch/powerpc/include/asm/signal.h index fbe66c46389..9322c28aebd 100644 --- a/arch/powerpc/include/asm/signal.h +++ b/arch/powerpc/include/asm/signal.h @@ -3,5 +3,8 @@ #define __ARCH_HAS_SA_RESTORER #include <uapi/asm/signal.h> +#include <uapi/asm/ptrace.h> + +extern unsigned long get_tm_stackpointer(struct pt_regs *regs); #endif /* _ASM_POWERPC_SIGNAL_H */ diff --git a/arch/powerpc/include/asm/tm.h b/arch/powerpc/include/asm/tm.h index 4b4449abf3f..9dfbc34bdbf 100644 --- a/arch/powerpc/include/asm/tm.h +++ b/arch/powerpc/include/asm/tm.h @@ -5,6 +5,8 @@ * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation. */ +#include <uapi/asm/tm.h> + #ifdef CONFIG_PPC_TRANSACTIONAL_MEM extern void do_load_up_transact_fpu(struct thread_struct *thread); extern void do_load_up_transact_altivec(struct thread_struct *thread); diff --git a/arch/powerpc/include/uapi/asm/Kbuild b/arch/powerpc/include/uapi/asm/Kbuild index f7bca637074..5182c8622b5 100644 --- a/arch/powerpc/include/uapi/asm/Kbuild +++ b/arch/powerpc/include/uapi/asm/Kbuild @@ -40,6 +40,7 @@ header-y += statfs.h header-y += swab.h header-y += termbits.h header-y += termios.h +header-y += tm.h header-y += types.h header-y += ucontext.h header-y += unistd.h diff --git a/arch/powerpc/include/uapi/asm/tm.h b/arch/powerpc/include/uapi/asm/tm.h new file mode 100644 index 00000000000..85059a00f56 --- /dev/null +++ b/arch/powerpc/include/uapi/asm/tm.h @@ -0,0 +1,18 @@ +#ifndef _ASM_POWERPC_TM_H +#define _ASM_POWERPC_TM_H + +/* Reason codes describing kernel causes for transaction aborts. By + * convention, bit0 is copied to TEXASR[56] (IBM bit 7) which is set if + * the failure is persistent. PAPR saves 0xff-0xe0 for the hypervisor. + */ +#define TM_CAUSE_PERSISTENT 0x01 +#define TM_CAUSE_RESCHED 0xde +#define TM_CAUSE_TLBI 0xdc +#define TM_CAUSE_FAC_UNAV 0xda +#define TM_CAUSE_SYSCALL 0xd8 /* future use */ +#define TM_CAUSE_MISC 0xd6 /* future use */ +#define TM_CAUSE_SIGNAL 0xd4 +#define TM_CAUSE_ALIGNMENT 0xd2 +#define TM_CAUSE_EMULATE 0xd0 + +#endif diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c index b51a97cfedf..6f16ffafa6f 100644 --- a/arch/powerpc/kernel/asm-offsets.c +++ b/arch/powerpc/kernel/asm-offsets.c @@ -127,6 +127,12 @@ int main(void) DEFINE(THREAD_BESCR, offsetof(struct thread_struct, bescr)); DEFINE(THREAD_EBBHR, offsetof(struct thread_struct, ebbhr)); DEFINE(THREAD_EBBRR, offsetof(struct thread_struct, ebbrr)); + DEFINE(THREAD_SIAR, offsetof(struct thread_struct, siar)); + DEFINE(THREAD_SDAR, offsetof(struct thread_struct, sdar)); + DEFINE(THREAD_SIER, offsetof(struct thread_struct, sier)); + DEFINE(THREAD_MMCR0, offsetof(struct thread_struct, mmcr0)); + DEFINE(THREAD_MMCR2, offsetof(struct thread_struct, mmcr2)); + DEFINE(THREAD_MMCRA, offsetof(struct thread_struct, mmcra)); #endif #ifdef CONFIG_PPC_TRANSACTIONAL_MEM DEFINE(PACATMSCRATCH, offsetof(struct paca_struct, tm_scratch)); diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S index a283b6442b2..18b5b9cf8e3 100644 --- a/arch/powerpc/kernel/cpu_setup_power.S +++ b/arch/powerpc/kernel/cpu_setup_power.S @@ -135,8 +135,12 @@ __init_HFSCR: blr __init_TLB: - /* Clear the TLB */ - li r6,128 + /* + * Clear the TLB using the "IS 3" form of tlbiel instruction + * (invalidate by congruence class). P7 has 128 CCs, P8 has 512 + * so we just always do 512 + */ + li r6,512 mtctr r6 li r7,0xc00 /* IS field = 0b11 */ ptesync diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index c60bbec25c1..2a45d0f0438 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -452,7 +452,7 @@ static struct cpu_spec __initdata cpu_specs[] = { .mmu_features = MMU_FTRS_POWER8, .icache_bsize = 128, .dcache_bsize = 128, - .oprofile_type = PPC_OPROFILE_POWER4, + .oprofile_type = PPC_OPROFILE_INVALID, .oprofile_cpu_type = "ppc64/ibm-compat-v1", .cpu_setup = __setup_cpu_power8, .cpu_restore = __restore_cpu_power8, @@ -482,7 +482,7 @@ static struct cpu_spec __initdata cpu_specs[] = { .cpu_name = "POWER7+ (raw)", .cpu_features = CPU_FTRS_POWER7, .cpu_user_features = COMMON_USER_POWER7, - .cpu_user_features = COMMON_USER2_POWER7, + .cpu_user_features2 = COMMON_USER2_POWER7, .mmu_features = MMU_FTRS_POWER7, .icache_bsize = 128, .dcache_bsize = 128, @@ -507,7 +507,7 @@ static struct cpu_spec __initdata cpu_specs[] = { .num_pmcs = 6, .pmc_type = PPC_PMC_IBM, .oprofile_cpu_type = "ppc64/power8", - .oprofile_type = PPC_OPROFILE_POWER4, + .oprofile_type = PPC_OPROFILE_INVALID, .cpu_setup = __setup_cpu_power8, .cpu_restore = __restore_cpu_power8, .platform = "power8", diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index d22e73e4618..22b45a4955c 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -849,7 +849,7 @@ resume_kernel: /* check current_thread_info, _TIF_EMULATE_STACK_STORE */ CURRENT_THREAD_INFO(r9, r1) lwz r8,TI_FLAGS(r9) - andis. r8,r8,_TIF_EMULATE_STACK_STORE@h + andis. r0,r8,_TIF_EMULATE_STACK_STORE@h beq+ 1f addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */ diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index 51cfb8fc301..8741c854e03 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -487,6 +487,13 @@ BEGIN_FTR_SECTION ldarx r6,0,r1 END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS) +#ifdef CONFIG_PPC_BOOK3S +/* Cancel all explict user streams as they will have no use after context + * switch and will stop the HW from creating streams itself + */ + DCBT_STOP_ALL_STREAM_IDS(r6) +#endif + addi r6,r4,-THREAD /* Convert THREAD to 'current' */ std r6,PACACURRENT(r13) /* Set new 'current' */ diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index e6eba1bf61a..40e4a17c8ba 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -454,38 +454,14 @@ BEGIN_FTR_SECTION xori r10,r10,(MSR_FE0|MSR_FE1) mtmsrd r10 sync - fmr 0,0 - fmr 1,1 - fmr 2,2 - fmr 3,3 - fmr 4,4 - fmr 5,5 - fmr 6,6 - fmr 7,7 - fmr 8,8 - fmr 9,9 - fmr 10,10 - fmr 11,11 - fmr 12,12 - fmr 13,13 - fmr 14,14 - fmr 15,15 - fmr 16,16 - fmr 17,17 - fmr 18,18 - fmr 19,19 - fmr 20,20 - fmr 21,21 - fmr 22,22 - fmr 23,23 - fmr 24,24 - fmr 25,25 - fmr 26,26 - fmr 27,27 - fmr 28,28 - fmr 29,29 - fmr 30,30 - fmr 31,31 + +#define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 +#define FMR4(n) FMR2(n) ; FMR2(n+2) +#define FMR8(n) FMR4(n) ; FMR4(n+4) +#define FMR16(n) FMR8(n) ; FMR8(n+8) +#define FMR32(n) FMR16(n) ; FMR16(n+16) + FMR32(0) + FTR_SECTION_ELSE /* * To denormalise we need to move a copy of the register to itself. @@ -495,39 +471,25 @@ FTR_SECTION_ELSE oris r10,r10,MSR_VSX@h mtmsrd r10 sync - XVCPSGNDP(0,0,0) - XVCPSGNDP(1,1,1) - XVCPSGNDP(2,2,2) - XVCPSGNDP(3,3,3) - XVCPSGNDP(4,4,4) - XVCPSGNDP(5,5,5) - XVCPSGNDP(6,6,6) - XVCPSGNDP(7,7,7) - XVCPSGNDP(8,8,8) - XVCPSGNDP(9,9,9) - XVCPSGNDP(10,10,10) - XVCPSGNDP(11,11,11) - XVCPSGNDP(12,12,12) - XVCPSGNDP(13,13,13) - XVCPSGNDP(14,14,14) - XVCPSGNDP(15,15,15) - XVCPSGNDP(16,16,16) - XVCPSGNDP(17,17,17) - XVCPSGNDP(18,18,18) - XVCPSGNDP(19,19,19) - XVCPSGNDP(20,20,20) - XVCPSGNDP(21,21,21) - XVCPSGNDP(22,22,22) - XVCPSGNDP(23,23,23) - XVCPSGNDP(24,24,24) - XVCPSGNDP(25,25,25) - XVCPSGNDP(26,26,26) - XVCPSGNDP(27,27,27) - XVCPSGNDP(28,28,28) - XVCPSGNDP(29,29,29) - XVCPSGNDP(30,30,30) - XVCPSGNDP(31,31,31) + +#define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) +#define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) +#define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) +#define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) +#define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) + XVCPSGNDP32(0) + ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) + +BEGIN_FTR_SECTION + b denorm_done +END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) +/* + * To denormalise we need to move a copy of the register to itself. + * For POWER8 we need to do that for all 64 VSX registers + */ + XVCPSGNDP32(32) +denorm_done: mtspr SPRN_HSRR0,r11 mtcrf 0x80,r9 ld r9,PACA_EXGEN+EX_R9(r13) @@ -721,7 +683,7 @@ machine_check_common: STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) - STD_EXCEPTION_COMMON(0xe40, emulation_assist, .program_check_exception) + STD_EXCEPTION_COMMON(0xe40, emulation_assist, .emulation_assist_interrupt) STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception) #ifdef CONFIG_PPC_DOORBELL STD_EXCEPTION_COMMON_ASYNC(0xe80, h_doorbell, .doorbell_exception) diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index 5cbcf4d5a80..ea185e0b3ca 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c @@ -162,7 +162,7 @@ notrace unsigned int __check_irq_replay(void) * in case we also had a rollover while hard disabled */ local_paca->irq_happened &= ~PACA_IRQ_DEC; - if (decrementer_check_overflow()) + if ((happened & PACA_IRQ_DEC) || decrementer_check_overflow()) return 0x900; /* Finally check if an external interrupt happened */ diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c index 6053f037ef0..eabeec99101 100644 --- a/arch/powerpc/kernel/pci-common.c +++ b/arch/powerpc/kernel/pci-common.c @@ -657,15 +657,6 @@ void pci_resource_to_user(const struct pci_dev *dev, int bar, * ranges. However, some machines (thanks Apple !) tend to split their * space into lots of small contiguous ranges. So we have to coalesce. * - * - We can only cope with all memory ranges having the same offset - * between CPU addresses and PCI addresses. Unfortunately, some bridges - * are setup for a large 1:1 mapping along with a small "window" which - * maps PCI address 0 to some arbitrary high address of the CPU space in - * order to give access to the ISA memory hole. - * The way out of here that I've chosen for now is to always set the - * offset based on the first resource found, then override it if we - * have a different offset and the previous was set by an ISA hole. - * * - Some busses have IO space not starting at 0, which causes trouble with * the way we do our IO resource renumbering. The code somewhat deals with * it for 64 bits but I would expect problems on 32 bits. @@ -680,10 +671,9 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose, int rlen; int pna = of_n_addr_cells(dev); int np = pna + 5; - int memno = 0, isa_hole = -1; + int memno = 0; u32 pci_space; unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; - unsigned long long isa_mb = 0; struct resource *res; printk(KERN_INFO "PCI host bridge %s %s ranges:\n", @@ -777,8 +767,6 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose, } /* Handles ISA memory hole space here */ if (pci_addr == 0) { - isa_mb = cpu_addr; - isa_hole = memno; if (primary || isa_mem_base == 0) isa_mem_base = cpu_addr; hose->isa_mem_phys = cpu_addr; @@ -839,6 +827,7 @@ static void pcibios_fixup_resources(struct pci_dev *dev) } for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { struct resource *res = dev->resource + i; + struct pci_bus_region reg; if (!res->flags) continue; @@ -847,8 +836,9 @@ static void pcibios_fixup_resources(struct pci_dev *dev) * at 0 as unset as well, except if PCI_PROBE_ONLY is also set * since in that case, we don't want to re-assign anything */ + pcibios_resource_to_bus(dev, ®, res); if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || - (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { + (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { /* Only print message if not re-assigning */ if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] " @@ -1520,9 +1510,10 @@ static void pcibios_setup_phb_resources(struct pci_controller *hose, for (i = 0; i < 3; ++i) { res = &hose->mem_resources[i]; if (!res->flags) { - printk(KERN_ERR "PCI: Memory resource 0 not set for " - "host bridge %s (domain %d)\n", - hose->dn->full_name, hose->global_number); + if (i == 0) + printk(KERN_ERR "PCI: Memory resource 0 not set for " + "host bridge %s (domain %d)\n", + hose->dn->full_name, hose->global_number); continue; } offset = hose->mem_offset[i]; diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c index 873050d2684..2e8629654ca 100644 --- a/arch/powerpc/kernel/pci_64.c +++ b/arch/powerpc/kernel/pci_64.c @@ -266,3 +266,13 @@ int pcibus_to_node(struct pci_bus *bus) } EXPORT_SYMBOL(pcibus_to_node); #endif + +static void quirk_radeon_32bit_msi(struct pci_dev *dev) +{ + struct pci_dn *pdn = pci_get_pdn(dev); + + if (pdn) + pdn->force_32bit_msi = 1; +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x68f2, quirk_radeon_32bit_msi); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0xaa68, quirk_radeon_32bit_msi); diff --git a/arch/powerpc/kernel/pci_dn.c b/arch/powerpc/kernel/pci_dn.c index e7af165f8b9..df038442548 100644 --- a/arch/powerpc/kernel/pci_dn.c +++ b/arch/powerpc/kernel/pci_dn.c @@ -32,6 +32,14 @@ #include <asm/ppc-pci.h> #include <asm/firmware.h> +struct pci_dn *pci_get_pdn(struct pci_dev *pdev) +{ + struct device_node *dn = pci_device_to_OF_node(pdev); + if (!dn) + return NULL; + return PCI_DN(dn); +} + /* * Traverse_func that inits the PCI fields of the device node. * NOTE: this *must* be done before read/write config to the device. diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index a902723fdc6..076d1242507 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -399,7 +399,8 @@ static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) { mtspr(SPRN_DABR, dabr); - mtspr(SPRN_DABRX, dabrx); + if (cpu_has_feature(CPU_FTR_DABRX)) + mtspr(SPRN_DABRX, dabrx); return 0; } #else @@ -1368,7 +1369,7 @@ void show_stack(struct task_struct *tsk, unsigned long *stack) #ifdef CONFIG_PPC64 /* Called with hard IRQs off */ -void __ppc64_runlatch_on(void) +void notrace __ppc64_runlatch_on(void) { struct thread_info *ti = current_thread_info(); unsigned long ctrl; @@ -1381,7 +1382,7 @@ void __ppc64_runlatch_on(void) } /* Called with hard IRQs off */ -void __ppc64_runlatch_off(void) +void notrace __ppc64_runlatch_off(void) { struct thread_info *ti = current_thread_info(); unsigned long ctrl; diff --git a/arch/powerpc/kernel/signal.c b/arch/powerpc/kernel/signal.c index 577a8aa69c6..457e97aa294 100644 --- a/arch/powerpc/kernel/signal.c +++ b/arch/powerpc/kernel/signal.c @@ -18,6 +18,7 @@ #include <asm/uaccess.h> #include <asm/unistd.h> #include <asm/debug.h> +#include <asm/tm.h> #include "signal.h" @@ -30,13 +31,13 @@ int show_unhandled_signals = 1; /* * Allocate space for the signal frame */ -void __user * get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, +void __user * get_sigframe(struct k_sigaction *ka, unsigned long sp, size_t frame_size, int is_32) { unsigned long oldsp, newsp; /* Default to using normal stack */ - oldsp = get_clean_sp(regs, is_32); + oldsp = get_clean_sp(sp, is_32); /* Check for alt stack */ if ((ka->sa.sa_flags & SA_ONSTACK) && @@ -175,3 +176,38 @@ void do_notify_resume(struct pt_regs *regs, unsigned long thread_info_flags) user_enter(); } + +unsigned long get_tm_stackpointer(struct pt_regs *regs) +{ + /* When in an active transaction that takes a signal, we need to be + * careful with the stack. It's possible that the stack has moved back + * up after the tbegin. The obvious case here is when the tbegin is + * called inside a function that returns before a tend. In this case, + * the stack is part of the checkpointed transactional memory state. + * If we write over this non transactionally or in suspend, we are in + * trouble because if we get a tm abort, the program counter and stack + * pointer will be back at the tbegin but our in memory stack won't be + * valid anymore. + * + * To avoid this, when taking a signal in an active transaction, we + * need to use the stack pointer from the checkpointed state, rather + * than the speculated state. This ensures that the signal context + * (written tm suspended) will be written below the stack required for + * the rollback. The transaction is aborted becuase of the treclaim, + * so any memory written between the tbegin and the signal will be + * rolled back anyway. + * + * For signals taken in non-TM or suspended mode, we use the + * normal/non-checkpointed stack pointer. + */ + +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + if (MSR_TM_ACTIVE(regs->msr)) { + tm_enable(); + tm_reclaim(¤t->thread, regs->msr, TM_CAUSE_SIGNAL); + if (MSR_TM_TRANSACTIONAL(regs->msr)) + return current->thread.ckpt_regs.gpr[1]; + } +#endif + return regs->gpr[1]; +} diff --git a/arch/powerpc/kernel/signal.h b/arch/powerpc/kernel/signal.h index ec84c901cea..c69b9aeb9f2 100644 --- a/arch/powerpc/kernel/signal.h +++ b/arch/powerpc/kernel/signal.h @@ -12,7 +12,7 @@ extern void do_notify_resume(struct pt_regs *regs, unsigned long thread_info_flags); -extern void __user * get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, +extern void __user * get_sigframe(struct k_sigaction *ka, unsigned long sp, size_t frame_size, int is_32); extern int handle_signal32(unsigned long sig, struct k_sigaction *ka, diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c index 95068bf569a..201385c3a1a 100644 --- a/arch/powerpc/kernel/signal_32.c +++ b/arch/powerpc/kernel/signal_32.c @@ -503,12 +503,6 @@ static int save_tm_user_regs(struct pt_regs *regs, { unsigned long msr = regs->msr; - /* tm_reclaim rolls back all reg states, updating thread.ckpt_regs, - * thread.transact_fpr[], thread.transact_vr[], etc. - */ - tm_enable(); - tm_reclaim(¤t->thread, msr, TM_CAUSE_SIGNAL); - /* Make sure floating point registers are stored in regs */ flush_fp_to_thread(current); @@ -965,7 +959,7 @@ int handle_rt_signal32(unsigned long sig, struct k_sigaction *ka, /* Set up Signal Frame */ /* Put a Real Time Context onto stack */ - rt_sf = get_sigframe(ka, regs, sizeof(*rt_sf), 1); + rt_sf = get_sigframe(ka, get_tm_stackpointer(regs), sizeof(*rt_sf), 1); addr = rt_sf; if (unlikely(rt_sf == NULL)) goto badframe; @@ -1403,7 +1397,7 @@ int handle_signal32(unsigned long sig, struct k_sigaction *ka, unsigned long tramp; /* Set up Signal Frame */ - frame = get_sigframe(ka, regs, sizeof(*frame), 1); + frame = get_sigframe(ka, get_tm_stackpointer(regs), sizeof(*frame), 1); if (unlikely(frame == NULL)) goto badframe; sc = (struct sigcontext __user *) &frame->sctx; diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c index c1794286098..345947367ec 100644 --- a/arch/powerpc/kernel/signal_64.c +++ b/arch/powerpc/kernel/signal_64.c @@ -154,11 +154,12 @@ static long setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs, * As above, but Transactional Memory is in use, so deliver sigcontexts * containing checkpointed and transactional register states. * - * To do this, we treclaim to gather both sets of registers and set up the - * 'normal' sigcontext registers with rolled-back register values such that a - * simple signal handler sees a correct checkpointed register state. - * If interested, a TM-aware sighandler can examine the transactional registers - * in the 2nd sigcontext to determine the real origin of the signal. + * To do this, we treclaim (done before entering here) to gather both sets of + * registers and set up the 'normal' sigcontext registers with rolled-back + * register values such that a simple signal handler sees a correct + * checkpointed register state. If interested, a TM-aware sighandler can + * examine the transactional registers in the 2nd sigcontext to determine the + * real origin of the signal. */ static long setup_tm_sigcontexts(struct sigcontext __user *sc, struct sigcontext __user *tm_sc, @@ -184,16 +185,6 @@ static long setup_tm_sigcontexts(struct sigcontext __user *sc, BUG_ON(!MSR_TM_ACTIVE(regs->msr)); - /* tm_reclaim rolls back all reg states, saving checkpointed (older) - * GPRs to thread.ckpt_regs and (if used) FPRs to (newer) - * thread.transact_fp and/or VRs to (newer) thread.transact_vr. - * THEN we save out FP/VRs, if necessary, to the checkpointed (older) - * thread.fr[]/vr[]s. The transactional (newer) GPRs are on the - * stack, in *regs. - */ - tm_enable(); - tm_reclaim(¤t->thread, msr, TM_CAUSE_SIGNAL); - flush_fp_to_thread(current); #ifdef CONFIG_ALTIVEC @@ -711,7 +702,7 @@ int handle_rt_signal64(int signr, struct k_sigaction *ka, siginfo_t *info, unsigned long newsp = 0; long err = 0; - frame = get_sigframe(ka, regs, sizeof(*frame), 0); + frame = get_sigframe(ka, get_tm_stackpointer(regs), sizeof(*frame), 0); if (unlikely(frame == NULL)) goto badframe; diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index a7a648f6b75..c0e5caf8ccc 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c @@ -53,6 +53,7 @@ #ifdef CONFIG_PPC64 #include <asm/firmware.h> #include <asm/processor.h> +#include <asm/tm.h> #endif #include <asm/kexec.h> #include <asm/ppc-opcode.h> @@ -932,6 +933,28 @@ static int emulate_isel(struct pt_regs *regs, u32 instword) return 0; } +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM +static inline bool tm_abort_check(struct pt_regs *regs, int cause) +{ + /* If we're emulating a load/store in an active transaction, we cannot + * emulate it as the kernel operates in transaction suspended context. + * We need to abort the transaction. This creates a persistent TM + * abort so tell the user what caused it with a new code. + */ + if (MSR_TM_TRANSACTIONAL(regs->msr)) { + tm_enable(); + tm_abort(cause); + return true; + } + return false; +} +#else +static inline bool tm_abort_check(struct pt_regs *regs, int reason) +{ + return false; +} +#endif + static int emulate_instruction(struct pt_regs *regs) { u32 instword; @@ -971,6 +994,9 @@ static int emulate_instruction(struct pt_regs *regs) /* Emulate load/store string insn. */ if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { + if (tm_abort_check(regs, + TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) + return -EINVAL; PPC_WARN_EMULATED(string, regs); return emulate_string_inst(regs, instword); } @@ -1139,6 +1165,16 @@ bail: exception_exit(prev_state); } +/* + * This occurs when running in hypervisor mode on POWER6 or later + * and an illegal instruction is encountered. + */ +void __kprobes emulation_assist_interrupt(struct pt_regs *regs) +{ + regs->msr |= REASON_ILLEGAL; + program_check_exception(regs); +} + void alignment_exception(struct pt_regs *regs) { enum ctx_state prev_state = exception_enter(); @@ -1148,6 +1184,9 @@ void alignment_exception(struct pt_regs *regs) if (!arch_irq_disabled_regs(regs)) local_irq_enable(); + if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) + goto bail; + /* we don't implement logging of alignment exceptions */ if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) fixed = fix_alignment(regs); diff --git a/arch/powerpc/kvm/44x_tlb.c b/arch/powerpc/kvm/44x_tlb.c index 5dd3ab46997..ed038544814 100644 --- a/arch/powerpc/kvm/44x_tlb.c +++ b/arch/powerpc/kvm/44x_tlb.c @@ -441,6 +441,7 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws) struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu); struct kvmppc_44x_tlbe *tlbe; unsigned int gtlb_index; + int idx; gtlb_index = kvmppc_get_gpr(vcpu, ra); if (gtlb_index >= KVM44x_GUEST_TLB_SIZE) { @@ -473,6 +474,8 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws) return EMULATE_FAIL; } + idx = srcu_read_lock(&vcpu->kvm->srcu); + if (tlbe_is_host_safe(vcpu, tlbe)) { gva_t eaddr; gpa_t gpaddr; @@ -489,6 +492,8 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws) kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index); } + srcu_read_unlock(&vcpu->kvm->srcu, idx); + trace_kvm_gtlb_write(gtlb_index, tlbe->tid, tlbe->word0, tlbe->word1, tlbe->word2); diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index 9de24f8e03c..550f5928b39 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -562,6 +562,8 @@ int kvmppc_pseries_do_hcall(struct kvm_vcpu *vcpu) case H_CPPR: case H_EOI: case H_IPI: + case H_IPOLL: + case H_XIRR_X: if (kvmppc_xics_enabled(vcpu)) { ret = kvmppc_xics_hcall(vcpu, req); break; diff --git a/arch/powerpc/kvm/book3s_pr_papr.c b/arch/powerpc/kvm/book3s_pr_papr.c index b24309c6c2d..da0e0bc268b 100644 --- a/arch/powerpc/kvm/book3s_pr_papr.c +++ b/arch/powerpc/kvm/book3s_pr_papr.c @@ -257,6 +257,8 @@ int kvmppc_h_pr(struct kvm_vcpu *vcpu, unsigned long cmd) case H_CPPR: case H_EOI: case H_IPI: + case H_IPOLL: + case H_XIRR_X: if (kvmppc_xics_enabled(vcpu)) return kvmppc_h_pr_xics_hcall(vcpu, cmd); break; diff --git a/arch/powerpc/kvm/book3s_xics.c b/arch/powerpc/kvm/book3s_xics.c index f7a10375661..94c1dd46b83 100644 --- a/arch/powerpc/kvm/book3s_xics.c +++ b/arch/powerpc/kvm/book3s_xics.c @@ -650,6 +650,23 @@ static noinline int kvmppc_h_ipi(struct kvm_vcpu *vcpu, unsigned long server, return H_SUCCESS; } +static int kvmppc_h_ipoll(struct kvm_vcpu *vcpu, unsigned long server) +{ + union kvmppc_icp_state state; + struct kvmppc_icp *icp; + + icp = vcpu->arch.icp; + if (icp->server_num != server) { + icp = kvmppc_xics_find_server(vcpu->kvm, server); + if (!icp) + return H_PARAMETER; + } + state = ACCESS_ONCE(icp->state); + kvmppc_set_gpr(vcpu, 4, ((u32)state.cppr << 24) | state.xisr); + kvmppc_set_gpr(vcpu, 5, state.mfrr); + return H_SUCCESS; +} + static noinline void kvmppc_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr) { union kvmppc_icp_state old_state, new_state; @@ -787,6 +804,18 @@ int kvmppc_xics_hcall(struct kvm_vcpu *vcpu, u32 req) if (!xics || !vcpu->arch.icp) return H_HARDWARE; + /* These requests don't have real-mode implementations at present */ + switch (req) { + case H_XIRR_X: + res = kvmppc_h_xirr(vcpu); + kvmppc_set_gpr(vcpu, 4, res); + kvmppc_set_gpr(vcpu, 5, get_tb()); + return rc; + case H_IPOLL: + rc = kvmppc_h_ipoll(vcpu, kvmppc_get_gpr(vcpu, 4)); + return rc; + } + /* Check for real mode returning too hard */ if (xics->real_mode) return kvmppc_xics_rm_complete(vcpu, req); diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c index 1020119226d..5cd7ad0c117 100644 --- a/arch/powerpc/kvm/booke.c +++ b/arch/powerpc/kvm/booke.c @@ -832,6 +832,18 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, { int r = RESUME_HOST; int s; + int idx; + +#ifdef CONFIG_PPC64 + WARN_ON(local_paca->irq_happened != 0); +#endif + + /* + * We enter with interrupts disabled in hardware, but + * we need to call hard_irq_disable anyway to ensure that + * the software state is kept in sync. + */ + hard_irq_disable(); /* update before a new last_exit_type is rewritten */ kvmppc_update_timing_stats(vcpu); @@ -1053,6 +1065,8 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, break; } + idx = srcu_read_lock(&vcpu->kvm->srcu); + gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); gfn = gpaddr >> PAGE_SHIFT; @@ -1075,6 +1089,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, kvmppc_account_exit(vcpu, MMIO_EXITS); } + srcu_read_unlock(&vcpu->kvm->srcu, idx); break; } @@ -1098,6 +1113,8 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS); + idx = srcu_read_lock(&vcpu->kvm->srcu); + gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); gfn = gpaddr >> PAGE_SHIFT; @@ -1114,6 +1131,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK); } + srcu_read_unlock(&vcpu->kvm->srcu, idx); break; } diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc/kvm/e500_mmu.c index c41a5a96b55..6d6f153b6c1 100644 --- a/arch/powerpc/kvm/e500_mmu.c +++ b/arch/powerpc/kvm/e500_mmu.c @@ -396,6 +396,7 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu) struct kvm_book3e_206_tlb_entry *gtlbe; int tlbsel, esel; int recal = 0; + int idx; tlbsel = get_tlb_tlbsel(vcpu); esel = get_tlb_esel(vcpu, tlbsel); @@ -430,6 +431,8 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu) kvmppc_set_tlb1map_range(vcpu, gtlbe); } + idx = srcu_read_lock(&vcpu->kvm->srcu); + /* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */ if (tlbe_is_host_safe(vcpu, gtlbe)) { u64 eaddr = get_tlb_eaddr(gtlbe); @@ -444,6 +447,8 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu) kvmppc_mmu_map(vcpu, eaddr, raddr, index_of(tlbsel, esel)); } + srcu_read_unlock(&vcpu->kvm->srcu, idx); + kvmppc_set_exit_type(vcpu, EMULATED_TLBWE_EXITS); return EMULATE_DONE; } diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c index 753cc99eff2..19c8379575f 100644 --- a/arch/powerpc/kvm/e500mc.c +++ b/arch/powerpc/kvm/e500mc.c @@ -177,8 +177,6 @@ int kvmppc_core_check_processor_compat(void) r = 0; else if (strcmp(cur_cpu_spec->cpu_name, "e5500") == 0) r = 0; - else if (strcmp(cur_cpu_spec->cpu_name, "e6500") == 0) - r = 0; else r = -ENOTSUPP; diff --git a/arch/powerpc/lib/copypage_power7.S b/arch/powerpc/lib/copypage_power7.S index 0ef75bf0695..395c594722a 100644 --- a/arch/powerpc/lib/copypage_power7.S +++ b/arch/powerpc/lib/copypage_power7.S @@ -28,13 +28,14 @@ _GLOBAL(copypage_power7) * aligned we don't need to clear the bottom 7 bits of either * address. */ - ori r9,r3,1 /* stream=1 */ + ori r9,r3,1 /* stream=1 => to */ #ifdef CONFIG_PPC_64K_PAGES - lis r7,0x0E01 /* depth=7, units=512 */ + lis r7,0x0E01 /* depth=7 + * units/cachelines=512 */ #else lis r7,0x0E00 /* depth=7 */ - ori r7,r7,0x1000 /* units=32 */ + ori r7,r7,0x1000 /* units/cachelines=32 */ #endif ori r10,r7,1 /* stream=1 */ @@ -43,12 +44,14 @@ _GLOBAL(copypage_power7) .machine push .machine "power4" - dcbt r0,r4,0b01000 - dcbt r0,r7,0b01010 - dcbtst r0,r9,0b01000 - dcbtst r0,r10,0b01010 + /* setup read stream 0 */ + dcbt r0,r4,0b01000 /* addr from */ + dcbt r0,r7,0b01010 /* length and depth from */ + /* setup write stream 1 */ + dcbtst r0,r9,0b01000 /* addr to */ + dcbtst r0,r10,0b01010 /* length and depth to */ eieio - dcbt r0,r8,0b01010 /* GO */ + dcbt r0,r8,0b01010 /* all streams GO */ .machine pop #ifdef CONFIG_ALTIVEC diff --git a/arch/powerpc/lib/copyuser_power7.S b/arch/powerpc/lib/copyuser_power7.S index 0d24ff15f5f..d1f11795a7a 100644 --- a/arch/powerpc/lib/copyuser_power7.S +++ b/arch/powerpc/lib/copyuser_power7.S @@ -318,12 +318,14 @@ err1; stb r0,0(r3) .machine push .machine "power4" - dcbt r0,r6,0b01000 - dcbt r0,r7,0b01010 - dcbtst r0,r9,0b01000 - dcbtst r0,r10,0b01010 + /* setup read stream 0 */ + dcbt r0,r6,0b01000 /* addr from */ + dcbt r0,r7,0b01010 /* length and depth from */ + /* setup write stream 1 */ + dcbtst r0,r9,0b01000 /* addr to */ + dcbtst r0,r10,0b01010 /* length and depth to */ eieio - dcbt r0,r8,0b01010 /* GO */ + dcbt r0,r8,0b01010 /* all streams GO */ .machine pop beq cr1,.Lunwind_stack_nonvmx_copy diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c index 6a2aead5b0e..4c122c3f162 100644 --- a/arch/powerpc/mm/hash_native_64.c +++ b/arch/powerpc/mm/hash_native_64.c @@ -336,11 +336,18 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp, hpte_v = hptep->v; actual_psize = hpte_actual_psize(hptep, psize); + /* + * We need to invalidate the TLB always because hpte_remove doesn't do + * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less + * random entry from it. When we do that we don't invalidate the TLB + * (hpte_remove) because we assume the old translation is still + * technically "valid". + */ if (actual_psize < 0) { - native_unlock_hpte(hptep); - return -1; + actual_psize = psize; + ret = -1; + goto err_out; } - /* Even if we miss, we need to invalidate the TLB */ if (!HPTE_V_COMPARE(hpte_v, want_v)) { DBG_LOW(" -> miss\n"); ret = -1; @@ -350,6 +357,7 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp, hptep->r = (hptep->r & ~(HPTE_R_PP | HPTE_R_N)) | (newpp & (HPTE_R_PP | HPTE_R_N | HPTE_R_C)); } +err_out: native_unlock_hpte(hptep); /* Ensure it is out of the tlb too. */ @@ -409,7 +417,7 @@ static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea, hptep = htab_address + slot; actual_psize = hpte_actual_psize(hptep, psize); if (actual_psize < 0) - return; + actual_psize = psize; /* Update the HPTE */ hptep->r = (hptep->r & ~(HPTE_R_PP | HPTE_R_N)) | @@ -437,21 +445,27 @@ static void native_hpte_invalidate(unsigned long slot, unsigned long vpn, hpte_v = hptep->v; actual_psize = hpte_actual_psize(hptep, psize); + /* + * We need to invalidate the TLB always because hpte_remove doesn't do + * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less + * random entry from it. When we do that we don't invalidate the TLB + * (hpte_remove) because we assume the old translation is still + * technically "valid". + */ if (actual_psize < 0) { + actual_psize = psize; native_unlock_hpte(hptep); - local_irq_restore(flags); - return; + goto err_out; } - /* Even if we miss, we need to invalidate the TLB */ if (!HPTE_V_COMPARE(hpte_v, want_v)) native_unlock_hpte(hptep); else /* Invalidate the hpte. NOTE: this also unlocks it */ hptep->v = 0; +err_out: /* Invalidate the TLB */ tlbie(vpn, psize, actual_psize, ssize, local); - local_irq_restore(flags); } diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 426180b8497..29c6482890c 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -110,7 +110,7 @@ static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} static bool regs_use_siar(struct pt_regs *regs) { - return !!(regs->result & 1); + return !!regs->result; } /* @@ -136,22 +136,30 @@ static inline unsigned long perf_ip_adjust(struct pt_regs *regs) * If we're not doing instruction sampling, give them the SDAR * (sampled data address). If we are doing instruction sampling, then * only give them the SDAR if it corresponds to the instruction - * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC or - * the [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA. + * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the + * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. */ static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { unsigned long mmcra = regs->dsisr; - unsigned long sdsync; + bool sdar_valid; - if (ppmu->flags & PPMU_SIAR_VALID) - sdsync = POWER7P_MMCRA_SDAR_VALID; - else if (ppmu->flags & PPMU_ALT_SIPR) - sdsync = POWER6_MMCRA_SDSYNC; - else - sdsync = MMCRA_SDSYNC; + if (ppmu->flags & PPMU_HAS_SIER) + sdar_valid = regs->dar & SIER_SDAR_VALID; + else { + unsigned long sdsync; + + if (ppmu->flags & PPMU_SIAR_VALID) + sdsync = POWER7P_MMCRA_SDAR_VALID; + else if (ppmu->flags & PPMU_ALT_SIPR) + sdsync = POWER6_MMCRA_SDSYNC; + else + sdsync = MMCRA_SDSYNC; + + sdar_valid = mmcra & sdsync; + } - if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync)) + if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) *addrp = mfspr(SPRN_SDAR); } @@ -181,11 +189,6 @@ static bool regs_sipr(struct pt_regs *regs) return !!(regs->dsisr & sipr); } -static bool regs_no_sipr(struct pt_regs *regs) -{ - return !!(regs->result & 2); -} - static inline u32 perf_flags_from_msr(struct pt_regs *regs) { if (regs->msr & MSR_PR) @@ -208,7 +211,7 @@ static inline u32 perf_get_misc_flags(struct pt_regs *regs) * SIAR which should give slightly more reliable * results */ - if (regs_no_sipr(regs)) { + if (ppmu->flags & PPMU_NO_SIPR) { unsigned long siar = mfspr(SPRN_SIAR); if (siar >= PAGE_OFFSET) return PERF_RECORD_MISC_KERNEL; @@ -239,22 +242,9 @@ static inline void perf_read_regs(struct pt_regs *regs) int use_siar; regs->dsisr = mmcra; - regs->result = 0; - - if (ppmu->flags & PPMU_NO_SIPR) - regs->result |= 2; - - /* - * On power8 if we're in random sampling mode, the SIER is updated. - * If we're in continuous sampling mode, we don't have SIPR. - */ - if (ppmu->flags & PPMU_HAS_SIER) { - if (marked) - regs->dar = mfspr(SPRN_SIER); - else - regs->result |= 2; - } + if (ppmu->flags & PPMU_HAS_SIER) + regs->dar = mfspr(SPRN_SIER); /* * If this isn't a PMU exception (eg a software event) the SIAR is @@ -279,12 +269,12 @@ static inline void perf_read_regs(struct pt_regs *regs) use_siar = 1; else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) use_siar = 0; - else if (!regs_no_sipr(regs) && regs_sipr(regs)) + else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) use_siar = 0; else use_siar = 1; - regs->result |= use_siar; + regs->result = use_siar; } /* @@ -308,8 +298,13 @@ static inline int siar_valid(struct pt_regs *regs) unsigned long mmcra = regs->dsisr; int marked = mmcra & MMCRA_SAMPLE_ENABLE; - if ((ppmu->flags & PPMU_SIAR_VALID) && marked) - return mmcra & POWER7P_MMCRA_SIAR_VALID; + if (marked) { + if (ppmu->flags & PPMU_HAS_SIER) + return regs->dar & SIER_SIAR_VALID; + + if (ppmu->flags & PPMU_SIAR_VALID) + return mmcra & POWER7P_MMCRA_SIAR_VALID; + } return 1; } @@ -1763,7 +1758,7 @@ static void perf_event_interrupt(struct pt_regs *regs) } } } - if ((!found) && printk_ratelimit()) + if (!found && !nmi && printk_ratelimit()) printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); /* diff --git a/arch/powerpc/platforms/powernv/Kconfig b/arch/powerpc/platforms/powernv/Kconfig index d3e840d643a..c24684c818a 100644 --- a/arch/powerpc/platforms/powernv/Kconfig +++ b/arch/powerpc/platforms/powernv/Kconfig @@ -6,6 +6,7 @@ config PPC_POWERNV select PPC_ICP_NATIVE select PPC_P7_NAP select PPC_PCI_CHOICE if EMBEDDED + select EPAPR_BOOT default y config POWERNV_MSI diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index 3937aaae5bc..9c9d15e4cdf 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -68,16 +68,6 @@ define_pe_printk_level(pe_err, KERN_ERR); define_pe_printk_level(pe_warn, KERN_WARNING); define_pe_printk_level(pe_info, KERN_INFO); -static struct pci_dn *pnv_ioda_get_pdn(struct pci_dev *dev) -{ - struct device_node *np; - - np = pci_device_to_OF_node(dev); - if (!np) - return NULL; - return PCI_DN(np); -} - static int pnv_ioda_alloc_pe(struct pnv_phb *phb) { unsigned long pe; @@ -110,7 +100,7 @@ static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) { struct pci_controller *hose = pci_bus_to_host(dev->bus); struct pnv_phb *phb = hose->private_data; - struct pci_dn *pdn = pnv_ioda_get_pdn(dev); + struct pci_dn *pdn = pci_get_pdn(dev); if (!pdn) return NULL; @@ -173,7 +163,7 @@ static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) /* Add to all parents PELT-V */ while (parent) { - struct pci_dn *pdn = pnv_ioda_get_pdn(parent); + struct pci_dn *pdn = pci_get_pdn(parent); if (pdn && pdn->pe_number != IODA_INVALID_PE) { rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); @@ -252,7 +242,7 @@ static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) { struct pci_controller *hose = pci_bus_to_host(dev->bus); struct pnv_phb *phb = hose->private_data; - struct pci_dn *pdn = pnv_ioda_get_pdn(dev); + struct pci_dn *pdn = pci_get_pdn(dev); struct pnv_ioda_pe *pe; int pe_num; @@ -323,7 +313,7 @@ static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) struct pci_dev *dev; list_for_each_entry(dev, &bus->devices, bus_list) { - struct pci_dn *pdn = pnv_ioda_get_pdn(dev); + struct pci_dn *pdn = pci_get_pdn(dev); if (pdn == NULL) { pr_warn("%s: No device node associated with device !\n", @@ -436,7 +426,7 @@ static void pnv_pci_ioda_setup_PEs(void) static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) { - struct pci_dn *pdn = pnv_ioda_get_pdn(pdev); + struct pci_dn *pdn = pci_get_pdn(pdev); struct pnv_ioda_pe *pe; /* @@ -768,6 +758,7 @@ static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, unsigned int is_64, struct msi_msg *msg) { struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); + struct pci_dn *pdn = pci_get_pdn(dev); struct irq_data *idata; struct irq_chip *ichip; unsigned int xive_num = hwirq - phb->msi_base; @@ -783,6 +774,10 @@ static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, if (pe->mve_number < 0) return -ENXIO; + /* Force 32-bit MSI on some broken devices */ + if (pdn && pdn->force_32bit_msi) + is_64 = 0; + /* Assign XIVE to PE */ rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); if (rc) { @@ -1035,7 +1030,7 @@ static int pnv_pci_enable_device_hook(struct pci_dev *dev) if (!phb->initialized) return 0; - pdn = pnv_ioda_get_pdn(dev); + pdn = pci_get_pdn(dev); if (!pdn || pdn->pe_number == IODA_INVALID_PE) return -EINVAL; diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c index 163bd7422f1..277343cc6a3 100644 --- a/arch/powerpc/platforms/powernv/pci.c +++ b/arch/powerpc/platforms/powernv/pci.c @@ -47,6 +47,10 @@ static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type) { struct pci_controller *hose = pci_bus_to_host(pdev->bus); struct pnv_phb *phb = hose->private_data; + struct pci_dn *pdn = pci_get_pdn(pdev); + + if (pdn && pdn->force_32bit_msi && !phb->msi32_support) + return -ENODEV; return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV; } @@ -367,7 +371,7 @@ static void pnv_tce_free(struct iommu_table *tbl, long index, long npages) while (npages--) *(tcep++) = 0; - if (tbl->it_type & TCE_PCI_SWINV_CREATE) + if (tbl->it_type & TCE_PCI_SWINV_FREE) pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1); } diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig index 023b288f895..4459eff7a75 100644 --- a/arch/powerpc/platforms/pseries/Kconfig +++ b/arch/powerpc/platforms/pseries/Kconfig @@ -19,6 +19,8 @@ config PPC_PSERIES select ZLIB_DEFLATE select PPC_DOORBELL select HAVE_CONTEXT_TRACKING + select HOTPLUG if SMP + select HOTPLUG_CPU if SMP default y config PPC_SPLPAR diff --git a/arch/powerpc/platforms/pseries/eeh_pseries.c b/arch/powerpc/platforms/pseries/eeh_pseries.c index 19506f93573..b456b157d33 100644 --- a/arch/powerpc/platforms/pseries/eeh_pseries.c +++ b/arch/powerpc/platforms/pseries/eeh_pseries.c @@ -83,7 +83,11 @@ static int pseries_eeh_init(void) ibm_configure_pe = rtas_token("ibm,configure-pe"); ibm_configure_bridge = rtas_token("ibm,configure-bridge"); - /* necessary sanity check */ + /* + * Necessary sanity check. We needn't check "get-config-addr-info" + * and its variant since the old firmware probably support address + * of domain/bus/slot/function for EEH RTAS operations. + */ if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) { pr_warning("%s: RTAS service <ibm,set-eeh-option> invalid\n", __func__); @@ -102,12 +106,6 @@ static int pseries_eeh_init(void) pr_warning("%s: RTAS service <ibm,slot-error-detail> invalid\n", __func__); return -EINVAL; - } else if (ibm_get_config_addr_info2 == RTAS_UNKNOWN_SERVICE && - ibm_get_config_addr_info == RTAS_UNKNOWN_SERVICE) { - pr_warning("%s: RTAS service <ibm,get-config-addr-info2> and " - "<ibm,get-config-addr-info> invalid\n", - __func__); - return -EINVAL; } else if (ibm_configure_pe == RTAS_UNKNOWN_SERVICE && ibm_configure_bridge == RTAS_UNKNOWN_SERVICE) { pr_warning("%s: RTAS service <ibm,configure-pe> and " diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c index 420524e6f8c..6d2f0abce6f 100644 --- a/arch/powerpc/platforms/pseries/msi.c +++ b/arch/powerpc/platforms/pseries/msi.c @@ -26,26 +26,6 @@ static int query_token, change_token; #define RTAS_CHANGE_MSIX_FN 4 #define RTAS_CHANGE_32MSI_FN 5 -static struct pci_dn *get_pdn(struct pci_dev *pdev) -{ - struct device_node *dn; - struct pci_dn *pdn; - - dn = pci_device_to_OF_node(pdev); - if (!dn) { - dev_dbg(&pdev->dev, "rtas_msi: No OF device node\n"); - return NULL; - } - - pdn = PCI_DN(dn); - if (!pdn) { - dev_dbg(&pdev->dev, "rtas_msi: No PCI DN\n"); - return NULL; - } - - return pdn; -} - /* RTAS Helpers */ static int rtas_change_msi(struct pci_dn *pdn, u32 func, u32 num_irqs) @@ -91,7 +71,7 @@ static void rtas_disable_msi(struct pci_dev *pdev) { struct pci_dn *pdn; - pdn = get_pdn(pdev); + pdn = pci_get_pdn(pdev); if (!pdn) return; @@ -152,7 +132,7 @@ static int check_req(struct pci_dev *pdev, int nvec, char *prop_name) struct pci_dn *pdn; const u32 *req_msi; - pdn = get_pdn(pdev); + pdn = pci_get_pdn(pdev); if (!pdn) return -ENODEV; @@ -394,6 +374,23 @@ static int check_msix_entries(struct pci_dev *pdev) return 0; } +static void rtas_hack_32bit_msi_gen2(struct pci_dev *pdev) +{ + u32 addr_hi, addr_lo; + + /* + * We should only get in here for IODA1 configs. This is based on the + * fact that we using RTAS for MSIs, we don't have the 32 bit MSI RTAS + * support, and we are in a PCIe Gen2 slot. + */ + dev_info(&pdev->dev, + "rtas_msi: No 32 bit MSI firmware support, forcing 32 bit MSI\n"); + pci_read_config_dword(pdev, pdev->msi_cap + PCI_MSI_ADDRESS_HI, &addr_hi); + addr_lo = 0xffff0000 | ((addr_hi >> (48 - 32)) << 4); + pci_write_config_dword(pdev, pdev->msi_cap + PCI_MSI_ADDRESS_LO, addr_lo); + pci_write_config_dword(pdev, pdev->msi_cap + PCI_MSI_ADDRESS_HI, 0); +} + static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec_in, int type) { struct pci_dn *pdn; @@ -401,8 +398,9 @@ static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec_in, int type) struct msi_desc *entry; struct msi_msg msg; int nvec = nvec_in; + int use_32bit_msi_hack = 0; - pdn = get_pdn(pdev); + pdn = pci_get_pdn(pdev); if (!pdn) return -ENODEV; @@ -428,15 +426,31 @@ static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec_in, int type) */ again: if (type == PCI_CAP_ID_MSI) { - if (pdn->force_32bit_msi) + if (pdn->force_32bit_msi) { rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSI_FN, nvec); - else + if (rc < 0) { + /* + * We only want to run the 32 bit MSI hack below if + * the max bus speed is Gen2 speed + */ + if (pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) + return rc; + + use_32bit_msi_hack = 1; + } + } else + rc = -1; + + if (rc < 0) rc = rtas_change_msi(pdn, RTAS_CHANGE_MSI_FN, nvec); - if (rc < 0 && !pdn->force_32bit_msi) { + if (rc < 0) { pr_debug("rtas_msi: trying the old firmware call.\n"); rc = rtas_change_msi(pdn, RTAS_CHANGE_FN, nvec); } + + if (use_32bit_msi_hack && rc > 0) + rtas_hack_32bit_msi_gen2(pdev); } else rc = rtas_change_msi(pdn, RTAS_CHANGE_MSIX_FN, nvec); @@ -518,12 +532,3 @@ static int rtas_msi_init(void) } arch_initcall(rtas_msi_init); -static void quirk_radeon(struct pci_dev *dev) -{ - struct pci_dn *pdn = get_pdn(dev); - - if (pdn) - pdn->force_32bit_msi = 1; -} -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x68f2, quirk_radeon); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0xaa68, quirk_radeon); diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 0a13ecb270c..3cc2f9159ab 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -54,7 +54,7 @@ static DEFINE_RAW_SPINLOCK(mpic_lock); #ifdef CONFIG_PPC32 /* XXX for now */ #ifdef CONFIG_IRQ_ALL_CPUS -#define distribute_irqs (!(mpic->flags & MPIC_SINGLE_DEST_CPU)) +#define distribute_irqs (1) #else #define distribute_irqs (0) #endif @@ -1703,7 +1703,7 @@ void mpic_setup_this_cpu(void) * it differently, then we should make sure we also change the default * values of irq_desc[].affinity in irq.c. */ - if (distribute_irqs) { + if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) { for (i = 0; i < mpic->num_sources ; i++) mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 2c9789da0e2..da183c5a103 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -98,7 +98,6 @@ config S390 select CLONE_BACKWARDS2 select GENERIC_CLOCKEVENTS select GENERIC_CPU_DEVICES if !SMP - select GENERIC_KERNEL_THREAD select GENERIC_SMP_IDLE_THREAD select GENERIC_TIME_VSYSCALL_OLD select HAVE_ALIGNED_STRUCT_PAGE if SLUB diff --git a/arch/s390/appldata/appldata_base.c b/arch/s390/appldata/appldata_base.c index bae0f402bf2..87a22092b68 100644 --- a/arch/s390/appldata/appldata_base.c +++ b/arch/s390/appldata/appldata_base.c @@ -212,7 +212,9 @@ appldata_timer_handler(ctl_table *ctl, int write, return 0; } if (!write) { - len = sprintf(buf, appldata_timer_active ? "1\n" : "0\n"); + strncpy(buf, appldata_timer_active ? "1\n" : "0\n", + ARRAY_SIZE(buf)); + len = strnlen(buf, ARRAY_SIZE(buf)); if (len > *lenp) len = *lenp; if (copy_to_user(buffer, buf, len)) @@ -317,7 +319,8 @@ appldata_generic_handler(ctl_table *ctl, int write, return 0; } if (!write) { - len = sprintf(buf, ops->active ? "1\n" : "0\n"); + strncpy(buf, ops->active ? "1\n" : "0\n", ARRAY_SIZE(buf)); + len = strnlen(buf, ARRAY_SIZE(buf)); if (len > *lenp) len = *lenp; if (copy_to_user(buffer, buf, len)) { diff --git a/arch/s390/include/asm/dma-mapping.h b/arch/s390/include/asm/dma-mapping.h index 9411db653ba..886ac7d4937 100644 --- a/arch/s390/include/asm/dma-mapping.h +++ b/arch/s390/include/asm/dma-mapping.h @@ -71,8 +71,8 @@ static inline void dma_free_coherent(struct device *dev, size_t size, { struct dma_map_ops *dma_ops = get_dma_ops(dev); - dma_ops->free(dev, size, cpu_addr, dma_handle, NULL); debug_dma_free_coherent(dev, size, cpu_addr, dma_handle); + dma_ops->free(dev, size, cpu_addr, dma_handle, NULL); } #endif /* _ASM_S390_DMA_MAPPING_H */ diff --git a/arch/s390/include/asm/ftrace.h b/arch/s390/include/asm/ftrace.h index b7931faaef6..bf246dae136 100644 --- a/arch/s390/include/asm/ftrace.h +++ b/arch/s390/include/asm/ftrace.h @@ -9,11 +9,6 @@ struct dyn_arch_ftrace { }; #define MCOUNT_ADDR ((long)_mcount) -#ifdef CONFIG_64BIT -#define MCOUNT_INSN_SIZE 12 -#else -#define MCOUNT_INSN_SIZE 20 -#endif static inline unsigned long ftrace_call_adjust(unsigned long addr) { @@ -21,4 +16,11 @@ static inline unsigned long ftrace_call_adjust(unsigned long addr) } #endif /* __ASSEMBLY__ */ + +#ifdef CONFIG_64BIT +#define MCOUNT_INSN_SIZE 12 +#else +#define MCOUNT_INSN_SIZE 22 +#endif + #endif /* _ASM_S390_FTRACE_H */ diff --git a/arch/s390/include/asm/io.h b/arch/s390/include/asm/io.h index 379d96e2105..fd9be010f9b 100644 --- a/arch/s390/include/asm/io.h +++ b/arch/s390/include/asm/io.h @@ -36,6 +36,7 @@ static inline void * phys_to_virt(unsigned long address) } void *xlate_dev_mem_ptr(unsigned long phys); +#define xlate_dev_mem_ptr xlate_dev_mem_ptr void unxlate_dev_mem_ptr(unsigned long phys, void *addr); /* diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h index 75ce9b065f9..5d64fb7619c 100644 --- a/arch/s390/include/asm/page.h +++ b/arch/s390/include/asm/page.h @@ -32,7 +32,7 @@ void storage_key_init_range(unsigned long start, unsigned long end); -static unsigned long pfmf(unsigned long function, unsigned long address) +static inline unsigned long pfmf(unsigned long function, unsigned long address) { asm volatile( " .insn rre,0xb9af0000,%[function],%[address]" @@ -44,17 +44,13 @@ static unsigned long pfmf(unsigned long function, unsigned long address) static inline void clear_page(void *page) { - if (MACHINE_HAS_PFMF) { - pfmf(0x10000, (unsigned long)page); - } else { - register unsigned long reg1 asm ("1") = 0; - register void *reg2 asm ("2") = page; - register unsigned long reg3 asm ("3") = 4096; - asm volatile( - " mvcl 2,0" - : "+d" (reg2), "+d" (reg3) : "d" (reg1) - : "memory", "cc"); - } + register unsigned long reg1 asm ("1") = 0; + register void *reg2 asm ("2") = page; + register unsigned long reg3 asm ("3") = 4096; + asm volatile( + " mvcl 2,0" + : "+d" (reg2), "+d" (reg3) : "d" (reg1) + : "memory", "cc"); } static inline void copy_page(void *to, void *from) diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h index 4105b8221fd..e8b6e5b8932 100644 --- a/arch/s390/include/asm/pgtable.h +++ b/arch/s390/include/asm/pgtable.h @@ -306,7 +306,7 @@ extern unsigned long MODULES_END; #define RCP_HC_BIT 0x00200000UL #define RCP_GR_BIT 0x00040000UL #define RCP_GC_BIT 0x00020000UL -#define RCP_IN_BIT 0x00008000UL /* IPTE notify bit */ +#define RCP_IN_BIT 0x00002000UL /* IPTE notify bit */ /* User dirty / referenced bit for KVM's migration feature */ #define KVM_UR_BIT 0x00008000UL @@ -374,7 +374,7 @@ extern unsigned long MODULES_END; #define RCP_HC_BIT 0x0020000000000000UL #define RCP_GR_BIT 0x0004000000000000UL #define RCP_GC_BIT 0x0002000000000000UL -#define RCP_IN_BIT 0x0000800000000000UL /* IPTE notify bit */ +#define RCP_IN_BIT 0x0000200000000000UL /* IPTE notify bit */ /* User dirty / referenced bit for KVM's migration feature */ #define KVM_UR_BIT 0x0000800000000000UL @@ -623,7 +623,7 @@ static inline pgste_t pgste_get_lock(pte_t *ptep) " csg %0,%1,%2\n" " jl 0b\n" : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE]) - : "Q" (ptep[PTRS_PER_PTE]) : "cc"); + : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory"); #endif return __pgste(new); } @@ -635,18 +635,26 @@ static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste) " nihh %1,0xff7f\n" /* clear RCP_PCL_BIT */ " stg %1,%0\n" : "=Q" (ptep[PTRS_PER_PTE]) - : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) : "cc"); + : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) + : "cc", "memory"); preempt_enable(); #endif } +static inline void pgste_set(pte_t *ptep, pgste_t pgste) +{ +#ifdef CONFIG_PGSTE + *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste; +#endif +} + static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste) { #ifdef CONFIG_PGSTE unsigned long address, bits; unsigned char skey; - if (!pte_present(*ptep)) + if (pte_val(*ptep) & _PAGE_INVALID) return pgste; address = pte_val(*ptep) & PAGE_MASK; skey = page_get_storage_key(address); @@ -680,7 +688,7 @@ static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste) #ifdef CONFIG_PGSTE int young; - if (!pte_present(*ptep)) + if (pte_val(*ptep) & _PAGE_INVALID) return pgste; /* Get referenced bit from storage key */ young = page_reset_referenced(pte_val(*ptep) & PAGE_MASK); @@ -704,17 +712,19 @@ static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry) { #ifdef CONFIG_PGSTE unsigned long address; - unsigned long okey, nkey; + unsigned long nkey; - if (!pte_present(entry)) + if (pte_val(entry) & _PAGE_INVALID) return; + VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID)); address = pte_val(entry) & PAGE_MASK; - okey = nkey = page_get_storage_key(address); - nkey &= ~(_PAGE_ACC_BITS | _PAGE_FP_BIT); - /* Set page access key and fetch protection bit from pgste */ - nkey |= (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56; - if (okey != nkey) - page_set_storage_key(address, nkey, 0); + /* + * Set page access key and fetch protection bit from pgste. + * The guest C/R information is still in the PGSTE, set real + * key C/R to 0. + */ + nkey = (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56; + page_set_storage_key(address, nkey, 0); #endif } @@ -1098,6 +1108,11 @@ static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, pte = *ptep; if (!mm_exclusive(mm)) __ptep_ipte(address, ptep); + + if (mm_has_pgste(mm)) { + pgste = pgste_update_all(&pte, pgste); + pgste_set(ptep, pgste); + } return pte; } @@ -1105,9 +1120,13 @@ static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long address, pte_t *ptep, pte_t pte) { + pgste_t pgste; + if (mm_has_pgste(mm)) { + pgste = *(pgste_t *)(ptep + PTRS_PER_PTE); + pgste_set_key(ptep, pgste, pte); pgste_set_pte(ptep, pte); - pgste_set_unlock(ptep, *(pgste_t *)(ptep + PTRS_PER_PTE)); + pgste_set_unlock(ptep, pgste); } else *ptep = pte; } diff --git a/arch/s390/kernel/dis.c b/arch/s390/kernel/dis.c index 7f4a4a8c847..be87d3e05a5 100644 --- a/arch/s390/kernel/dis.c +++ b/arch/s390/kernel/dis.c @@ -1862,6 +1862,8 @@ void print_fn_code(unsigned char *code, unsigned long len) while (len) { ptr = buffer; opsize = insn_length(*code); + if (opsize > len) + break; ptr += sprintf(ptr, "%p: ", code); for (i = 0; i < opsize; i++) ptr += sprintf(ptr, "%02x", code[i]); diff --git a/arch/s390/kernel/dumpstack.c b/arch/s390/kernel/dumpstack.c index 29829747725..87acc38f73c 100644 --- a/arch/s390/kernel/dumpstack.c +++ b/arch/s390/kernel/dumpstack.c @@ -74,6 +74,8 @@ __show_trace(unsigned long sp, unsigned long low, unsigned long high) static void show_trace(struct task_struct *task, unsigned long *stack) { + const unsigned long frame_size = + STACK_FRAME_OVERHEAD + sizeof(struct pt_regs); register unsigned long __r15 asm ("15"); unsigned long sp; @@ -82,11 +84,13 @@ static void show_trace(struct task_struct *task, unsigned long *stack) sp = task ? task->thread.ksp : __r15; printk("Call Trace:\n"); #ifdef CONFIG_CHECK_STACK - sp = __show_trace(sp, S390_lowcore.panic_stack - 4096, - S390_lowcore.panic_stack); + sp = __show_trace(sp, + S390_lowcore.panic_stack + frame_size - 4096, + S390_lowcore.panic_stack + frame_size); #endif - sp = __show_trace(sp, S390_lowcore.async_stack - ASYNC_SIZE, - S390_lowcore.async_stack); + sp = __show_trace(sp, + S390_lowcore.async_stack + frame_size - ASYNC_SIZE, + S390_lowcore.async_stack + frame_size); if (task) __show_trace(sp, (unsigned long) task_stack_page(task), (unsigned long) task_stack_page(task) + THREAD_SIZE); diff --git a/arch/s390/kernel/ftrace.c b/arch/s390/kernel/ftrace.c index 78bdf0e5dff..e3043aef87a 100644 --- a/arch/s390/kernel/ftrace.c +++ b/arch/s390/kernel/ftrace.c @@ -16,12 +16,6 @@ #include <trace/syscall.h> #include <asm/asm-offsets.h> -#ifdef CONFIG_64BIT -#define MCOUNT_OFFSET_RET 12 -#else -#define MCOUNT_OFFSET_RET 22 -#endif - #ifdef CONFIG_DYNAMIC_FTRACE void ftrace_disable_code(void); @@ -155,9 +149,10 @@ unsigned long __kprobes prepare_ftrace_return(unsigned long parent, if (unlikely(atomic_read(¤t->tracing_graph_pause))) goto out; + ip = (ip & PSW_ADDR_INSN) - MCOUNT_INSN_SIZE; if (ftrace_push_return_trace(parent, ip, &trace.depth, 0) == -EBUSY) goto out; - trace.func = (ip & PSW_ADDR_INSN) - MCOUNT_OFFSET_RET; + trace.func = ip; /* Only trace if the calling function expects to. */ if (!ftrace_graph_entry(&trace)) { current->curr_ret_stack--; diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c index f7fb58903f6..408e866ae54 100644 --- a/arch/s390/kernel/irq.c +++ b/arch/s390/kernel/irq.c @@ -311,3 +311,67 @@ void measurement_alert_subclass_unregister(void) spin_unlock(&ma_subclass_lock); } EXPORT_SYMBOL(measurement_alert_subclass_unregister); + +void synchronize_irq(unsigned int irq) +{ + /* + * Not needed, the handler is protected by a lock and IRQs that occur + * after the handler is deleted are just NOPs. + */ +} +EXPORT_SYMBOL_GPL(synchronize_irq); + +#ifndef CONFIG_PCI + +/* Only PCI devices have dynamically-defined IRQ handlers */ + +int request_irq(unsigned int irq, irq_handler_t handler, + unsigned long irqflags, const char *devname, void *dev_id) +{ + return -EINVAL; +} +EXPORT_SYMBOL_GPL(request_irq); + +void free_irq(unsigned int irq, void *dev_id) +{ + WARN_ON(1); +} +EXPORT_SYMBOL_GPL(free_irq); + +void enable_irq(unsigned int irq) +{ + WARN_ON(1); +} +EXPORT_SYMBOL_GPL(enable_irq); + +void disable_irq(unsigned int irq) +{ + WARN_ON(1); +} +EXPORT_SYMBOL_GPL(disable_irq); + +#endif /* !CONFIG_PCI */ + +void disable_irq_nosync(unsigned int irq) +{ + disable_irq(irq); +} +EXPORT_SYMBOL_GPL(disable_irq_nosync); + +unsigned long probe_irq_on(void) +{ + return 0; +} +EXPORT_SYMBOL_GPL(probe_irq_on); + +int probe_irq_off(unsigned long val) +{ + return 0; +} +EXPORT_SYMBOL_GPL(probe_irq_off); + +unsigned int probe_irq_mask(unsigned long val) +{ + return val; +} +EXPORT_SYMBOL_GPL(probe_irq_mask); diff --git a/arch/s390/kernel/mcount.S b/arch/s390/kernel/mcount.S index 4567ce20d90..08dcf21cb8d 100644 --- a/arch/s390/kernel/mcount.S +++ b/arch/s390/kernel/mcount.S @@ -7,6 +7,7 @@ #include <linux/linkage.h> #include <asm/asm-offsets.h> +#include <asm/ftrace.h> .section .kprobes.text, "ax" @@ -33,6 +34,7 @@ ENTRY(ftrace_caller) la %r2,0(%r14) st %r0,__SF_BACKCHAIN(%r15) la %r3,0(%r3) + ahi %r2,-MCOUNT_INSN_SIZE l %r14,0b-0b(%r1) l %r14,0(%r14) basr %r14,%r14 diff --git a/arch/s390/kernel/mcount64.S b/arch/s390/kernel/mcount64.S index 11332193db3..1c52eae3396 100644 --- a/arch/s390/kernel/mcount64.S +++ b/arch/s390/kernel/mcount64.S @@ -7,6 +7,7 @@ #include <linux/linkage.h> #include <asm/asm-offsets.h> +#include <asm/ftrace.h> .section .kprobes.text, "ax" @@ -29,6 +30,7 @@ ENTRY(ftrace_caller) stg %r1,__SF_BACKCHAIN(%r15) lgr %r2,%r14 lg %r3,168(%r15) + aghi %r2,-MCOUNT_INSN_SIZE larl %r14,ftrace_trace_function lg %r14,0(%r14) basr %r14,%r14 diff --git a/arch/s390/kernel/sclp.S b/arch/s390/kernel/sclp.S index b6506ee32a3..29bd7bec417 100644 --- a/arch/s390/kernel/sclp.S +++ b/arch/s390/kernel/sclp.S @@ -225,7 +225,7 @@ _sclp_print: ahi %r2,1 ltr %r0,%r0 # end of string? jz .LfinalizemtoS4 - chi %r0,0x15 # end of line (NL)? + chi %r0,0x0a # end of line (NL)? jz .LfinalizemtoS4 stc %r0,0(%r6,%r7) # copy to mto la %r11,0(%r6,%r7) diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c index 8074cb4b7cb..4f977d0d25c 100644 --- a/arch/s390/kernel/smp.c +++ b/arch/s390/kernel/smp.c @@ -428,34 +428,27 @@ void smp_stop_cpu(void) * This is the main routine where commands issued by other * cpus are handled. */ -static void do_ext_call_interrupt(struct ext_code ext_code, - unsigned int param32, unsigned long param64) +static void smp_handle_ext_call(void) { unsigned long bits; - int cpu; - - cpu = smp_processor_id(); - if (ext_code.code == 0x1202) - inc_irq_stat(IRQEXT_EXC); - else - inc_irq_stat(IRQEXT_EMS); - /* - * handle bit signal external calls - */ - bits = xchg(&pcpu_devices[cpu].ec_mask, 0); + /* handle bit signal external calls */ + bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0); if (test_bit(ec_stop_cpu, &bits)) smp_stop_cpu(); - if (test_bit(ec_schedule, &bits)) scheduler_ipi(); - if (test_bit(ec_call_function, &bits)) generic_smp_call_function_interrupt(); - if (test_bit(ec_call_function_single, &bits)) generic_smp_call_function_single_interrupt(); +} +static void do_ext_call_interrupt(struct ext_code ext_code, + unsigned int param32, unsigned long param64) +{ + inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS); + smp_handle_ext_call(); } void arch_send_call_function_ipi_mask(const struct cpumask *mask) @@ -645,7 +638,7 @@ static int __cpuinit __smp_rescan_cpus(struct sclp_cpu_info *info, continue; pcpu = pcpu_devices + cpu; pcpu->address = info->cpu[i].address; - pcpu->state = (cpu >= info->configured) ? + pcpu->state = (i >= info->configured) ? CPU_STATE_STANDBY : CPU_STATE_CONFIGURED; smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); set_cpu_present(cpu, true); @@ -760,6 +753,8 @@ int __cpu_disable(void) { unsigned long cregs[16]; + /* Handle possible pending IPIs */ + smp_handle_ext_call(); set_cpu_online(smp_processor_id(), false); /* Disable pseudo page faults on this cpu. */ pfault_fini(); diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c index 7805ddca833..a938b548f07 100644 --- a/arch/s390/mm/pgtable.c +++ b/arch/s390/mm/pgtable.c @@ -492,7 +492,7 @@ static int gmap_connect_pgtable(unsigned long address, unsigned long segment, mp = (struct gmap_pgtable *) page->index; rmap->gmap = gmap; rmap->entry = segment_ptr; - rmap->vmaddr = address; + rmap->vmaddr = address & PMD_MASK; spin_lock(&mm->page_table_lock); if (*segment_ptr == segment) { list_add(&rmap->list, &mp->mapper); @@ -677,8 +677,7 @@ int gmap_ipte_notify(struct gmap *gmap, unsigned long start, unsigned long len) break; } /* Get the page mapped */ - if (get_user_pages(current, gmap->mm, addr, 1, 1, 0, - NULL, NULL) != 1) { + if (fixup_user_fault(current, gmap->mm, addr, FAULT_FLAG_WRITE)) { rc = -EFAULT; break; } diff --git a/arch/s390/pci/pci.c b/arch/s390/pci/pci.c index e6f15b5d8b7..f1e5be85d59 100644 --- a/arch/s390/pci/pci.c +++ b/arch/s390/pci/pci.c @@ -302,15 +302,6 @@ static int zpci_cfg_store(struct zpci_dev *zdev, int offset, u32 val, u8 len) return rc; } -void synchronize_irq(unsigned int irq) -{ - /* - * Not needed, the handler is protected by a lock and IRQs that occur - * after the handler is deleted are just NOPs. - */ -} -EXPORT_SYMBOL_GPL(synchronize_irq); - void enable_irq(unsigned int irq) { struct msi_desc *msi = irq_get_msi_desc(irq); @@ -327,30 +318,6 @@ void disable_irq(unsigned int irq) } EXPORT_SYMBOL_GPL(disable_irq); -void disable_irq_nosync(unsigned int irq) -{ - disable_irq(irq); -} -EXPORT_SYMBOL_GPL(disable_irq_nosync); - -unsigned long probe_irq_on(void) -{ - return 0; -} -EXPORT_SYMBOL_GPL(probe_irq_on); - -int probe_irq_off(unsigned long val) -{ - return 0; -} -EXPORT_SYMBOL_GPL(probe_irq_off); - -unsigned int probe_irq_mask(unsigned long val) -{ - return val; -} -EXPORT_SYMBOL_GPL(probe_irq_mask); - void pcibios_fixup_bus(struct pci_bus *bus) { } diff --git a/arch/score/mm/init.c b/arch/score/mm/init.c index d8f988a37d1..0940682ab38 100644 --- a/arch/score/mm/init.c +++ b/arch/score/mm/init.c @@ -41,8 +41,6 @@ unsigned long empty_zero_page; EXPORT_SYMBOL_GPL(empty_zero_page); -static struct kcore_list kcore_mem, kcore_vmalloc; - static void setup_zero_page(void) { struct page *page; diff --git a/arch/sparc/kernel/prom_common.c b/arch/sparc/kernel/prom_common.c index 9f20566b077..79cc0d1a477 100644 --- a/arch/sparc/kernel/prom_common.c +++ b/arch/sparc/kernel/prom_common.c @@ -54,6 +54,7 @@ EXPORT_SYMBOL(of_set_property_mutex); int of_set_property(struct device_node *dp, const char *name, void *val, int len) { struct property **prevp; + unsigned long flags; void *new_val; int err; @@ -64,7 +65,7 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len err = -ENODEV; mutex_lock(&of_set_property_mutex); - raw_spin_lock(&devtree_lock); + raw_spin_lock_irqsave(&devtree_lock, flags); prevp = &dp->properties; while (*prevp) { struct property *prop = *prevp; @@ -91,7 +92,7 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len } prevp = &(*prevp)->next; } - raw_spin_unlock(&devtree_lock); + raw_spin_unlock_irqrestore(&devtree_lock, flags); mutex_unlock(&of_set_property_mutex); /* XXX Upate procfs if necessary... */ diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c index 35ee62fccf9..c205035a6b9 100644 --- a/arch/x86/boot/compressed/eboot.c +++ b/arch/x86/boot/compressed/eboot.c @@ -251,51 +251,6 @@ static void find_bits(unsigned long mask, u8 *pos, u8 *size) *size = len; } -static efi_status_t setup_efi_vars(struct boot_params *params) -{ - struct setup_data *data; - struct efi_var_bootdata *efidata; - u64 store_size, remaining_size, var_size; - efi_status_t status; - - if (sys_table->runtime->hdr.revision < EFI_2_00_SYSTEM_TABLE_REVISION) - return EFI_UNSUPPORTED; - - data = (struct setup_data *)(unsigned long)params->hdr.setup_data; - - while (data && data->next) - data = (struct setup_data *)(unsigned long)data->next; - - status = efi_call_phys4((void *)sys_table->runtime->query_variable_info, - EFI_VARIABLE_NON_VOLATILE | - EFI_VARIABLE_BOOTSERVICE_ACCESS | - EFI_VARIABLE_RUNTIME_ACCESS, &store_size, - &remaining_size, &var_size); - - if (status != EFI_SUCCESS) - return status; - - status = efi_call_phys3(sys_table->boottime->allocate_pool, - EFI_LOADER_DATA, sizeof(*efidata), &efidata); - - if (status != EFI_SUCCESS) - return status; - - efidata->data.type = SETUP_EFI_VARS; - efidata->data.len = sizeof(struct efi_var_bootdata) - - sizeof(struct setup_data); - efidata->data.next = 0; - efidata->store_size = store_size; - efidata->remaining_size = remaining_size; - efidata->max_var_size = var_size; - - if (data) - data->next = (unsigned long)efidata; - else - params->hdr.setup_data = (unsigned long)efidata; - -} - static efi_status_t setup_efi_pci(struct boot_params *params) { efi_pci_io_protocol *pci; @@ -1202,8 +1157,6 @@ struct boot_params *efi_main(void *handle, efi_system_table_t *_table, setup_graphics(boot_params); - setup_efi_vars(boot_params); - setup_efi_pci(boot_params); status = efi_call_phys3(sys_table->boottime->allocate_pool, diff --git a/arch/x86/crypto/crc32-pclmul_asm.S b/arch/x86/crypto/crc32-pclmul_asm.S index 94c27df8a54..f247304299a 100644 --- a/arch/x86/crypto/crc32-pclmul_asm.S +++ b/arch/x86/crypto/crc32-pclmul_asm.S @@ -240,7 +240,7 @@ fold_64: pand %xmm3, %xmm1 PCLMULQDQ 0x00, CONSTANT, %xmm1 pxor %xmm2, %xmm1 - pextrd $0x01, %xmm1, %eax + PEXTRD 0x01, %xmm1, %eax ret ENDPROC(crc32_pclmul_le_16) diff --git a/arch/x86/crypto/sha256-avx-asm.S b/arch/x86/crypto/sha256-avx-asm.S index 56610c4bf31..642f15687a0 100644 --- a/arch/x86/crypto/sha256-avx-asm.S +++ b/arch/x86/crypto/sha256-avx-asm.S @@ -118,7 +118,7 @@ y2 = %r15d _INP_END_SIZE = 8 _INP_SIZE = 8 -_XFER_SIZE = 8 +_XFER_SIZE = 16 _XMM_SAVE_SIZE = 0 _INP_END = 0 diff --git a/arch/x86/crypto/sha256-ssse3-asm.S b/arch/x86/crypto/sha256-ssse3-asm.S index 98d3c391da8..f833b74d902 100644 --- a/arch/x86/crypto/sha256-ssse3-asm.S +++ b/arch/x86/crypto/sha256-ssse3-asm.S @@ -111,7 +111,7 @@ y2 = %r15d _INP_END_SIZE = 8 _INP_SIZE = 8 -_XFER_SIZE = 8 +_XFER_SIZE = 16 _XMM_SAVE_SIZE = 0 _INP_END = 0 diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h index 2fb5d5884e2..60c89f30c72 100644 --- a/arch/x86/include/asm/efi.h +++ b/arch/x86/include/asm/efi.h @@ -102,13 +102,6 @@ extern void efi_call_phys_epilog(void); extern void efi_unmap_memmap(void); extern void efi_memory_uc(u64 addr, unsigned long size); -struct efi_var_bootdata { - struct setup_data data; - u64 store_size; - u64 remaining_size; - u64 max_var_size; -}; - #ifdef CONFIG_EFI static inline bool efi_is_native(void) diff --git a/arch/x86/include/asm/inst.h b/arch/x86/include/asm/inst.h index 280bf7fb6ab..3e115273ed8 100644 --- a/arch/x86/include/asm/inst.h +++ b/arch/x86/include/asm/inst.h @@ -9,12 +9,68 @@ #define REG_NUM_INVALID 100 -#define REG_TYPE_R64 0 -#define REG_TYPE_XMM 1 +#define REG_TYPE_R32 0 +#define REG_TYPE_R64 1 +#define REG_TYPE_XMM 2 #define REG_TYPE_INVALID 100 + .macro R32_NUM opd r32 + \opd = REG_NUM_INVALID + .ifc \r32,%eax + \opd = 0 + .endif + .ifc \r32,%ecx + \opd = 1 + .endif + .ifc \r32,%edx + \opd = 2 + .endif + .ifc \r32,%ebx + \opd = 3 + .endif + .ifc \r32,%esp + \opd = 4 + .endif + .ifc \r32,%ebp + \opd = 5 + .endif + .ifc \r32,%esi + \opd = 6 + .endif + .ifc \r32,%edi + \opd = 7 + .endif +#ifdef CONFIG_X86_64 + .ifc \r32,%r8d + \opd = 8 + .endif + .ifc \r32,%r9d + \opd = 9 + .endif + .ifc \r32,%r10d + \opd = 10 + .endif + .ifc \r32,%r11d + \opd = 11 + .endif + .ifc \r32,%r12d + \opd = 12 + .endif + .ifc \r32,%r13d + \opd = 13 + .endif + .ifc \r32,%r14d + \opd = 14 + .endif + .ifc \r32,%r15d + \opd = 15 + .endif +#endif + .endm + .macro R64_NUM opd r64 \opd = REG_NUM_INVALID +#ifdef CONFIG_X86_64 .ifc \r64,%rax \opd = 0 .endif @@ -63,6 +119,7 @@ .ifc \r64,%r15 \opd = 15 .endif +#endif .endm .macro XMM_NUM opd xmm @@ -118,10 +175,13 @@ .endm .macro REG_TYPE type reg + R32_NUM reg_type_r32 \reg R64_NUM reg_type_r64 \reg XMM_NUM reg_type_xmm \reg .if reg_type_r64 <> REG_NUM_INVALID \type = REG_TYPE_R64 + .elseif reg_type_r32 <> REG_NUM_INVALID + \type = REG_TYPE_R32 .elseif reg_type_xmm <> REG_NUM_INVALID \type = REG_TYPE_XMM .else @@ -162,6 +222,16 @@ .byte \imm8 .endm + .macro PEXTRD imm8 xmm gpr + R32_NUM extrd_opd1 \gpr + XMM_NUM extrd_opd2 \xmm + PFX_OPD_SIZE + PFX_REX extrd_opd1 extrd_opd2 + .byte 0x0f, 0x3a, 0x16 + MODRM 0xc0 extrd_opd1 extrd_opd2 + .byte \imm8 + .endm + .macro AESKEYGENASSIST rcon xmm1 xmm2 XMM_NUM aeskeygen_opd1 \xmm1 XMM_NUM aeskeygen_opd2 \xmm2 diff --git a/arch/x86/include/uapi/asm/bootparam.h b/arch/x86/include/uapi/asm/bootparam.h index 08744242b8d..c15ddaf9071 100644 --- a/arch/x86/include/uapi/asm/bootparam.h +++ b/arch/x86/include/uapi/asm/bootparam.h @@ -6,7 +6,6 @@ #define SETUP_E820_EXT 1 #define SETUP_DTB 2 #define SETUP_PCI 3 -#define SETUP_EFI_VARS 4 /* ram_size flags */ #define RAMDISK_IMAGE_START_MASK 0x07FF diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 08f7e803909..321d65ebaff 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -115,8 +115,10 @@ startup_64: movq %rdi, %rax shrq $PUD_SHIFT, %rax andl $(PTRS_PER_PUD-1), %eax - movq %rdx, (4096+0)(%rbx,%rax,8) - movq %rdx, (4096+8)(%rbx,%rax,8) + movq %rdx, 4096(%rbx,%rax,8) + incl %eax + andl $(PTRS_PER_PUD-1), %eax + movq %rdx, 4096(%rbx,%rax,8) addq $8192, %rbx movq %rdi, %rax diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c index 245a71db401..cb339097b9e 100644 --- a/arch/x86/kernel/i387.c +++ b/arch/x86/kernel/i387.c @@ -22,23 +22,19 @@ /* * Were we in an interrupt that interrupted kernel mode? * - * For now, with eagerfpu we will return interrupted kernel FPU - * state as not-idle. TBD: Ideally we can change the return value - * to something like __thread_has_fpu(current). But we need to - * be careful of doing __thread_clear_has_fpu() before saving - * the FPU etc for supporting nested uses etc. For now, take - * the simple route! - * * On others, we can do a kernel_fpu_begin/end() pair *ONLY* if that * pair does nothing at all: the thread must not have fpu (so * that we don't try to save the FPU state), and TS must * be set (so that the clts/stts pair does nothing that is * visible in the interrupted kernel thread). + * + * Except for the eagerfpu case when we return 1 unless we've already + * been eager and saved the state in kernel_fpu_begin(). */ static inline bool interrupted_kernel_fpu_idle(void) { if (use_eager_fpu()) - return 0; + return __thread_has_fpu(current); return !__thread_has_fpu(current) && (read_cr0() & X86_CR0_TS); @@ -78,8 +74,8 @@ void __kernel_fpu_begin(void) struct task_struct *me = current; if (__thread_has_fpu(me)) { - __save_init_fpu(me); __thread_clear_has_fpu(me); + __save_init_fpu(me); /* We do 'stts()' in __kernel_fpu_end() */ } else if (!use_eager_fpu()) { this_cpu_write(fpu_owner_task, NULL); diff --git a/arch/x86/kernel/relocate_kernel_64.S b/arch/x86/kernel/relocate_kernel_64.S index 7a6f3b3be3c..f2bb9c96720 100644 --- a/arch/x86/kernel/relocate_kernel_64.S +++ b/arch/x86/kernel/relocate_kernel_64.S @@ -160,7 +160,7 @@ identity_mapped: xorq %rbp, %rbp xorq %r8, %r8 xorq %r9, %r9 - xorq %r10, %r9 + xorq %r10, %r10 xorq %r11, %r11 xorq %r12, %r12 xorq %r13, %r13 diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 8db0010ed15..5953dcea752 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -1240,9 +1240,12 @@ static int decode_modrm(struct x86_emulate_ctxt *ctxt, ctxt->modrm_seg = VCPU_SREG_DS; if (ctxt->modrm_mod == 3) { + int highbyte_regs = ctxt->rex_prefix == 0; + op->type = OP_REG; op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; - op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp); + op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, + highbyte_regs && (ctxt->d & ByteOp)); if (ctxt->d & Sse) { op->type = OP_XMM; op->bytes = 16; @@ -3997,7 +4000,8 @@ static const struct opcode twobyte_table[256] = { DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, N, D(ImplicitOps | ModRM), N, N, /* 0x10 - 0x1F */ - N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N, + N, N, N, N, N, N, N, N, + D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM), /* 0x20 - 0x2F */ DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read), DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read), @@ -4836,6 +4840,7 @@ twobyte_insn: case 0x08: /* invd */ case 0x0d: /* GrpP (prefetch) */ case 0x18: /* Grp16 (prefetch/nop) */ + case 0x1f: /* nop */ break; case 0x20: /* mov cr, reg */ ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index e1adbb4aca7..0eee2c8b64d 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -1861,11 +1861,14 @@ void kvm_apic_accept_events(struct kvm_vcpu *vcpu) { struct kvm_lapic *apic = vcpu->arch.apic; unsigned int sipi_vector; + unsigned long pe; - if (!kvm_vcpu_has_lapic(vcpu)) + if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events) return; - if (test_and_clear_bit(KVM_APIC_INIT, &apic->pending_events)) { + pe = xchg(&apic->pending_events, 0); + + if (test_bit(KVM_APIC_INIT, &pe)) { kvm_lapic_reset(vcpu); kvm_vcpu_reset(vcpu); if (kvm_vcpu_is_bsp(apic->vcpu)) @@ -1873,7 +1876,7 @@ void kvm_apic_accept_events(struct kvm_vcpu *vcpu) else vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; } - if (test_and_clear_bit(KVM_APIC_SIPI, &apic->pending_events) && + if (test_bit(KVM_APIC_SIPI, &pe) && vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { /* evaluate pending_events before reading the vector */ smp_rmb(); diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index eaac1743def..1f34e921977 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -277,6 +277,9 @@ static int __meminit split_mem_range(struct map_range *mr, int nr_range, end_pfn = limit_pfn; nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); + if (!after_bootmem) + adjust_range_page_size_mask(mr, nr_range); + /* try to merge same page size and continuous */ for (i = 0; nr_range > 1 && i < nr_range - 1; i++) { unsigned long old_start; @@ -291,9 +294,6 @@ static int __meminit split_mem_range(struct map_range *mr, int nr_range, nr_range--; } - if (!after_bootmem) - adjust_range_page_size_mask(mr, nr_range); - for (i = 0; i < nr_range; i++) printk(KERN_DEBUG " [mem %#010lx-%#010lx] page %s\n", mr[i].start, mr[i].end - 1, diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c index 305c68b8d53..981c2dbd72c 100644 --- a/arch/x86/pci/common.c +++ b/arch/x86/pci/common.c @@ -628,7 +628,9 @@ int pcibios_add_device(struct pci_dev *dev) pa_data = boot_params.hdr.setup_data; while (pa_data) { - data = phys_to_virt(pa_data); + data = ioremap(pa_data, sizeof(*rom)); + if (!data) + return -ENOMEM; if (data->type == SETUP_PCI) { rom = (struct pci_setup_rom *)data; @@ -645,6 +647,7 @@ int pcibios_add_device(struct pci_dev *dev) } } pa_data = data->next; + iounmap(data); } return 0; } diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c index 0e0fabf1734..6eb18c42a28 100644 --- a/arch/x86/pci/mrst.c +++ b/arch/x86/pci/mrst.c @@ -141,11 +141,6 @@ static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn, */ static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg) { - if (bus == 0 && (devfn == PCI_DEVFN(2, 0) - || devfn == PCI_DEVFN(0, 0) - || devfn == PCI_DEVFN(3, 0))) - return 1; - /* This is a workaround for A0 LNC bug where PCI status register does * not have new CAP bit set. can not be written by SW either. * @@ -155,7 +150,10 @@ static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg) */ if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE) return 0; - + if (bus == 0 && (devfn == PCI_DEVFN(2, 0) + || devfn == PCI_DEVFN(0, 0) + || devfn == PCI_DEVFN(3, 0))) + return 1; return 0; /* langwell on others */ } diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c index 55856b2310d..5ae2eb09419 100644 --- a/arch/x86/platform/efi/efi.c +++ b/arch/x86/platform/efi/efi.c @@ -42,7 +42,6 @@ #include <linux/io.h> #include <linux/reboot.h> #include <linux/bcd.h> -#include <linux/ucs2_string.h> #include <asm/setup.h> #include <asm/efi.h> @@ -54,12 +53,12 @@ #define EFI_DEBUG 1 -/* - * There's some additional metadata associated with each - * variable. Intel's reference implementation is 60 bytes - bump that - * to account for potential alignment constraints - */ -#define VAR_METADATA_SIZE 64 +#define EFI_MIN_RESERVE 5120 + +#define EFI_DUMMY_GUID \ + EFI_GUID(0x4424ac57, 0xbe4b, 0x47dd, 0x9e, 0x97, 0xed, 0x50, 0xf0, 0x9f, 0x92, 0xa9) + +static efi_char16_t efi_dummy_name[6] = { 'D', 'U', 'M', 'M', 'Y', 0 }; struct efi __read_mostly efi = { .mps = EFI_INVALID_TABLE_ADDR, @@ -79,13 +78,6 @@ struct efi_memory_map memmap; static struct efi efi_phys __initdata; static efi_system_table_t efi_systab __initdata; -static u64 efi_var_store_size; -static u64 efi_var_remaining_size; -static u64 efi_var_max_var_size; -static u64 boot_used_size; -static u64 boot_var_size; -static u64 active_size; - unsigned long x86_efi_facility; /* @@ -188,53 +180,8 @@ static efi_status_t virt_efi_get_next_variable(unsigned long *name_size, efi_char16_t *name, efi_guid_t *vendor) { - efi_status_t status; - static bool finished = false; - static u64 var_size; - - status = efi_call_virt3(get_next_variable, - name_size, name, vendor); - - if (status == EFI_NOT_FOUND) { - finished = true; - if (var_size < boot_used_size) { - boot_var_size = boot_used_size - var_size; - active_size += boot_var_size; - } else { - printk(KERN_WARNING FW_BUG "efi: Inconsistent initial sizes\n"); - } - } - - if (boot_used_size && !finished) { - unsigned long size; - u32 attr; - efi_status_t s; - void *tmp; - - s = virt_efi_get_variable(name, vendor, &attr, &size, NULL); - - if (s != EFI_BUFFER_TOO_SMALL || !size) - return status; - - tmp = kmalloc(size, GFP_ATOMIC); - - if (!tmp) - return status; - - s = virt_efi_get_variable(name, vendor, &attr, &size, tmp); - - if (s == EFI_SUCCESS && (attr & EFI_VARIABLE_NON_VOLATILE)) { - var_size += size; - var_size += ucs2_strsize(name, 1024); - active_size += size; - active_size += VAR_METADATA_SIZE; - active_size += ucs2_strsize(name, 1024); - } - - kfree(tmp); - } - - return status; + return efi_call_virt3(get_next_variable, + name_size, name, vendor); } static efi_status_t virt_efi_set_variable(efi_char16_t *name, @@ -243,34 +190,9 @@ static efi_status_t virt_efi_set_variable(efi_char16_t *name, unsigned long data_size, void *data) { - efi_status_t status; - u32 orig_attr = 0; - unsigned long orig_size = 0; - - status = virt_efi_get_variable(name, vendor, &orig_attr, &orig_size, - NULL); - - if (status != EFI_BUFFER_TOO_SMALL) - orig_size = 0; - - status = efi_call_virt5(set_variable, - name, vendor, attr, - data_size, data); - - if (status == EFI_SUCCESS) { - if (orig_size) { - active_size -= orig_size; - active_size -= ucs2_strsize(name, 1024); - active_size -= VAR_METADATA_SIZE; - } - if (data_size) { - active_size += data_size; - active_size += ucs2_strsize(name, 1024); - active_size += VAR_METADATA_SIZE; - } - } - - return status; + return efi_call_virt5(set_variable, + name, vendor, attr, + data_size, data); } static efi_status_t virt_efi_query_variable_info(u32 attr, @@ -786,9 +708,6 @@ void __init efi_init(void) char vendor[100] = "unknown"; int i = 0; void *tmp; - struct setup_data *data; - struct efi_var_bootdata *efi_var_data; - u64 pa_data; #ifdef CONFIG_X86_32 if (boot_params.efi_info.efi_systab_hi || @@ -806,22 +725,6 @@ void __init efi_init(void) if (efi_systab_init(efi_phys.systab)) return; - pa_data = boot_params.hdr.setup_data; - while (pa_data) { - data = early_ioremap(pa_data, sizeof(*efi_var_data)); - if (data->type == SETUP_EFI_VARS) { - efi_var_data = (struct efi_var_bootdata *)data; - - efi_var_store_size = efi_var_data->store_size; - efi_var_remaining_size = efi_var_data->remaining_size; - efi_var_max_var_size = efi_var_data->max_var_size; - } - pa_data = data->next; - early_iounmap(data, sizeof(*efi_var_data)); - } - - boot_used_size = efi_var_store_size - efi_var_remaining_size; - set_bit(EFI_SYSTEM_TABLES, &x86_efi_facility); /* @@ -1085,6 +988,13 @@ void __init efi_enter_virtual_mode(void) runtime_code_page_mkexec(); kfree(new_memmap); + + /* clean DUMMY object */ + efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID, + EFI_VARIABLE_NON_VOLATILE | + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS, + 0, NULL); } /* @@ -1136,33 +1046,65 @@ efi_status_t efi_query_variable_store(u32 attributes, unsigned long size) efi_status_t status; u64 storage_size, remaining_size, max_size; + if (!(attributes & EFI_VARIABLE_NON_VOLATILE)) + return 0; + status = efi.query_variable_info(attributes, &storage_size, &remaining_size, &max_size); if (status != EFI_SUCCESS) return status; - if (!max_size && remaining_size > size) - printk_once(KERN_ERR FW_BUG "Broken EFI implementation" - " is returning MaxVariableSize=0\n"); /* * Some firmware implementations refuse to boot if there's insufficient * space in the variable store. We account for that by refusing the * write if permitting it would reduce the available space to under - * 50%. However, some firmware won't reclaim variable space until - * after the used (not merely the actively used) space drops below - * a threshold. We can approximate that case with the value calculated - * above. If both the firmware and our calculations indicate that the - * available space would drop below 50%, refuse the write. + * 5KB. This figure was provided by Samsung, so should be safe. */ + if ((remaining_size - size < EFI_MIN_RESERVE) && + !efi_no_storage_paranoia) { + + /* + * Triggering garbage collection may require that the firmware + * generate a real EFI_OUT_OF_RESOURCES error. We can force + * that by attempting to use more space than is available. + */ + unsigned long dummy_size = remaining_size + 1024; + void *dummy = kmalloc(dummy_size, GFP_ATOMIC); + + status = efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID, + EFI_VARIABLE_NON_VOLATILE | + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS, + dummy_size, dummy); + + if (status == EFI_SUCCESS) { + /* + * This should have failed, so if it didn't make sure + * that we delete it... + */ + efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID, + EFI_VARIABLE_NON_VOLATILE | + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS, + 0, dummy); + } - if (!storage_size || size > remaining_size || - (max_size && size > max_size)) - return EFI_OUT_OF_RESOURCES; + /* + * The runtime code may now have triggered a garbage collection + * run, so check the variable info again + */ + status = efi.query_variable_info(attributes, &storage_size, + &remaining_size, &max_size); - if (!efi_no_storage_paranoia && - ((active_size + size + VAR_METADATA_SIZE > storage_size / 2) && - (remaining_size - size < storage_size / 2))) - return EFI_OUT_OF_RESOURCES; + if (status != EFI_SUCCESS) + return status; + + /* + * There still isn't enough room, so return an error + */ + if (remaining_size - size < EFI_MIN_RESERVE) + return EFI_OUT_OF_RESOURCES; + } return EFI_SUCCESS; } diff --git a/arch/x86/tools/relocs.c b/arch/x86/tools/relocs.c index 590be109089..f7bab68a4b8 100644 --- a/arch/x86/tools/relocs.c +++ b/arch/x86/tools/relocs.c @@ -42,9 +42,6 @@ static const char * const sym_regex_kernel[S_NSYMTYPES] = { "^(xen_irq_disable_direct_reloc$|" "xen_save_fl_direct_reloc$|" "VDSO|" -#if ELF_BITS == 64 - "__vvar_page|" -#endif "__crc_)", /* @@ -72,6 +69,7 @@ static const char * const sym_regex_kernel[S_NSYMTYPES] = { "__per_cpu_load|" "init_per_cpu__.*|" "__end_rodata_hpage_align|" + "__vvar_page|" #endif "_end)$" }; diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c index 8ff37995d54..d99cae8147d 100644 --- a/arch/x86/xen/smp.c +++ b/arch/x86/xen/smp.c @@ -17,6 +17,7 @@ #include <linux/slab.h> #include <linux/smp.h> #include <linux/irq_work.h> +#include <linux/tick.h> #include <asm/paravirt.h> #include <asm/desc.h> @@ -447,6 +448,13 @@ static void __cpuinit xen_play_dead(void) /* used only with HOTPLUG_CPU */ play_dead_common(); HYPERVISOR_vcpu_op(VCPUOP_down, smp_processor_id(), NULL); cpu_bringup(); + /* + * commit 4b0c0f294 (tick: Cleanup NOHZ per cpu data on cpu down) + * clears certain data that the cpu_idle loop (which called us + * and that we return from) expects. The only way to get that + * data back is to call: + */ + tick_nohz_idle_enter(); } #else /* !CONFIG_HOTPLUG_CPU */ @@ -576,24 +584,22 @@ void xen_send_IPI_mask_allbutself(const struct cpumask *mask, { unsigned cpu; unsigned int this_cpu = smp_processor_id(); + int xen_vector = xen_map_vector(vector); - if (!(num_online_cpus() > 1)) + if (!(num_online_cpus() > 1) || (xen_vector < 0)) return; for_each_cpu_and(cpu, mask, cpu_online_mask) { if (this_cpu == cpu) continue; - xen_smp_send_call_function_single_ipi(cpu); + xen_send_IPI_one(cpu, xen_vector); } } void xen_send_IPI_allbutself(int vector) { - int xen_vector = xen_map_vector(vector); - - if (xen_vector >= 0) - xen_send_IPI_mask_allbutself(cpu_online_mask, xen_vector); + xen_send_IPI_mask_allbutself(cpu_online_mask, vector); } static irqreturn_t xen_call_function_interrupt(int irq, void *dev_id) diff --git a/arch/x86/xen/smp.h b/arch/x86/xen/smp.h index 8981a76d081..c7c2d89efd7 100644 --- a/arch/x86/xen/smp.h +++ b/arch/x86/xen/smp.h @@ -5,7 +5,6 @@ extern void xen_send_IPI_mask(const struct cpumask *mask, extern void xen_send_IPI_mask_allbutself(const struct cpumask *mask, int vector); extern void xen_send_IPI_allbutself(int vector); -extern void physflat_send_IPI_allbutself(int vector); extern void xen_send_IPI_all(int vector); extern void xen_send_IPI_self(int vector); |