diff options
Diffstat (limited to 'arch')
1722 files changed, 24033 insertions, 22073 deletions
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index cc31bec2e31..9808998cc07 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -11,7 +11,7 @@ config ALPHA select HAVE_GENERIC_HARDIRQS select GENERIC_IRQ_PROBE select AUTO_IRQ_AFFINITY if SMP - select GENERIC_HARDIRQS_NO_DEPRECATED + select GENERIC_IRQ_SHOW help The Alpha is a 64-bit general-purpose processor designed and marketed by the Digital Equipment Corporation of blessed memory, diff --git a/arch/alpha/include/asm/bitops.h b/arch/alpha/include/asm/bitops.h index adfab8a21df..85b81521577 100644 --- a/arch/alpha/include/asm/bitops.h +++ b/arch/alpha/include/asm/bitops.h @@ -454,13 +454,11 @@ sched_find_first_bit(const unsigned long b[2]) return __ffs(tmp) + ofs; } -#include <asm-generic/bitops/ext2-non-atomic.h> +#include <asm-generic/bitops/le.h> #define ext2_set_bit_atomic(l,n,a) test_and_set_bit(n,a) #define ext2_clear_bit_atomic(l,n,a) test_and_clear_bit(n,a) -#include <asm-generic/bitops/minix.h> - #endif /* __KERNEL__ */ #endif /* _ALPHA_BITOPS_H */ diff --git a/arch/alpha/include/asm/elf.h b/arch/alpha/include/asm/elf.h index 9baae8afe8a..da5449e2217 100644 --- a/arch/alpha/include/asm/elf.h +++ b/arch/alpha/include/asm/elf.h @@ -101,7 +101,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; #define ELF_PLAT_INIT(_r, load_addr) _r->r0 = 0 -/* The registers are layed out in pt_regs for PAL and syscall +/* The registers are laid out in pt_regs for PAL and syscall convenience. Re-order them for the linear elf_gregset_t. */ struct pt_regs; diff --git a/arch/alpha/include/asm/types.h b/arch/alpha/include/asm/types.h index bd621ecd1eb..881544339c2 100644 --- a/arch/alpha/include/asm/types.h +++ b/arch/alpha/include/asm/types.h @@ -20,16 +20,4 @@ typedef unsigned int umode_t; #endif /* __ASSEMBLY__ */ - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ -#ifndef __ASSEMBLY__ - -typedef u64 dma_addr_t; -typedef u64 dma64_addr_t; - -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL__ */ #endif /* _ALPHA_TYPES_H */ diff --git a/arch/alpha/include/asm/unistd.h b/arch/alpha/include/asm/unistd.h index 058937bf5a7..b1834166922 100644 --- a/arch/alpha/include/asm/unistd.h +++ b/arch/alpha/include/asm/unistd.h @@ -452,10 +452,14 @@ #define __NR_fanotify_init 494 #define __NR_fanotify_mark 495 #define __NR_prlimit64 496 +#define __NR_name_to_handle_at 497 +#define __NR_open_by_handle_at 498 +#define __NR_clock_adjtime 499 +#define __NR_syncfs 500 #ifdef __KERNEL__ -#define NR_SYSCALLS 497 +#define NR_SYSCALLS 501 #define __ARCH_WANT_IPC_PARSE_VERSION #define __ARCH_WANT_OLD_READDIR diff --git a/arch/alpha/kernel/Makefile b/arch/alpha/kernel/Makefile index 9bb7b858ed2..7a6d908bb86 100644 --- a/arch/alpha/kernel/Makefile +++ b/arch/alpha/kernel/Makefile @@ -4,7 +4,7 @@ extra-y := head.o vmlinux.lds asflags-y := $(KBUILD_CFLAGS) -ccflags-y := -Werror -Wno-sign-compare +ccflags-y := -Wno-sign-compare obj-y := entry.o traps.o process.o init_task.o osf_sys.o irq.o \ irq_alpha.o signal.o setup.o ptrace.o time.o \ diff --git a/arch/alpha/kernel/core_lca.c b/arch/alpha/kernel/core_lca.c index 4843f6ec9f3..cb2801cfd3d 100644 --- a/arch/alpha/kernel/core_lca.c +++ b/arch/alpha/kernel/core_lca.c @@ -133,7 +133,7 @@ conf_read(unsigned long addr) local_irq_save(flags); - /* Reset status register to avoid loosing errors. */ + /* Reset status register to avoid losing errors. */ stat0 = *(vulp)LCA_IOC_STAT0; *(vulp)LCA_IOC_STAT0 = stat0; mb(); @@ -170,7 +170,7 @@ conf_write(unsigned long addr, unsigned int value) local_irq_save(flags); /* avoid getting hit by machine check */ - /* Reset status register to avoid loosing errors. */ + /* Reset status register to avoid losing errors. */ stat0 = *(vulp)LCA_IOC_STAT0; *(vulp)LCA_IOC_STAT0 = stat0; mb(); diff --git a/arch/alpha/kernel/core_mcpcia.c b/arch/alpha/kernel/core_mcpcia.c index 381fec0af52..da7bcc372f1 100644 --- a/arch/alpha/kernel/core_mcpcia.c +++ b/arch/alpha/kernel/core_mcpcia.c @@ -88,7 +88,7 @@ conf_read(unsigned long addr, unsigned char type1, { unsigned long flags; unsigned long mid = MCPCIA_HOSE2MID(hose->index); - unsigned int stat0, value, temp, cpu; + unsigned int stat0, value, cpu; cpu = smp_processor_id(); @@ -101,7 +101,7 @@ conf_read(unsigned long addr, unsigned char type1, stat0 = *(vuip)MCPCIA_CAP_ERR(mid); *(vuip)MCPCIA_CAP_ERR(mid) = stat0; mb(); - temp = *(vuip)MCPCIA_CAP_ERR(mid); + *(vuip)MCPCIA_CAP_ERR(mid); DBG_CFG(("conf_read: MCPCIA_CAP_ERR(%d) was 0x%x\n", mid, stat0)); mb(); @@ -136,7 +136,7 @@ conf_write(unsigned long addr, unsigned int value, unsigned char type1, { unsigned long flags; unsigned long mid = MCPCIA_HOSE2MID(hose->index); - unsigned int stat0, temp, cpu; + unsigned int stat0, cpu; cpu = smp_processor_id(); @@ -145,7 +145,7 @@ conf_write(unsigned long addr, unsigned int value, unsigned char type1, /* Reset status register to avoid losing errors. */ stat0 = *(vuip)MCPCIA_CAP_ERR(mid); *(vuip)MCPCIA_CAP_ERR(mid) = stat0; mb(); - temp = *(vuip)MCPCIA_CAP_ERR(mid); + *(vuip)MCPCIA_CAP_ERR(mid); DBG_CFG(("conf_write: MCPCIA CAP_ERR(%d) was 0x%x\n", mid, stat0)); draina(); @@ -157,7 +157,7 @@ conf_write(unsigned long addr, unsigned int value, unsigned char type1, *((vuip)addr) = value; mb(); mb(); /* magic */ - temp = *(vuip)MCPCIA_CAP_ERR(mid); /* read to force the write */ + *(vuip)MCPCIA_CAP_ERR(mid); /* read to force the write */ mcheck_expected(cpu) = 0; mb(); @@ -572,12 +572,10 @@ mcpcia_print_system_area(unsigned long la_ptr) void mcpcia_machine_check(unsigned long vector, unsigned long la_ptr) { - struct el_common *mchk_header; struct el_MCPCIA_uncorrected_frame_mcheck *mchk_logout; unsigned int cpu = smp_processor_id(); int expected; - mchk_header = (struct el_common *)la_ptr; mchk_logout = (struct el_MCPCIA_uncorrected_frame_mcheck *)la_ptr; expected = mcheck_expected(cpu); diff --git a/arch/alpha/kernel/err_marvel.c b/arch/alpha/kernel/err_marvel.c index 648ae88aeb8..ae54ad91e18 100644 --- a/arch/alpha/kernel/err_marvel.c +++ b/arch/alpha/kernel/err_marvel.c @@ -1027,7 +1027,7 @@ marvel_process_logout_frame(struct ev7_lf_subpackets *lf_subpackets, int print) * normal operation, dismiss them. * * Dismiss if: - * C_STAT = 0x14 (Error Reponse) + * C_STAT = 0x14 (Error Response) * C_STS<3> = 0 (C_ADDR valid) * C_ADDR<42> = 1 (I/O) * C_ADDR<31:22> = 111110xxb (PCI Config space) diff --git a/arch/alpha/kernel/err_titan.c b/arch/alpha/kernel/err_titan.c index c3b3781a03d..14b26c466c8 100644 --- a/arch/alpha/kernel/err_titan.c +++ b/arch/alpha/kernel/err_titan.c @@ -533,8 +533,6 @@ static struct el_subpacket_annotation el_titan_annotations[] = { static struct el_subpacket * el_process_regatta_subpacket(struct el_subpacket *header) { - int status; - if (header->class != EL_CLASS__REGATTA_FAMILY) { printk("%s ** Unexpected header CLASS %d TYPE %d, aborting\n", err_print_prefix, @@ -551,7 +549,7 @@ el_process_regatta_subpacket(struct el_subpacket *header) printk("%s ** Occurred on CPU %d:\n", err_print_prefix, (int)header->by_type.regatta_frame.cpuid); - status = privateer_process_logout_frame((struct el_common *) + privateer_process_logout_frame((struct el_common *) header->by_type.regatta_frame.data_start, 1); break; default: diff --git a/arch/alpha/kernel/irq.c b/arch/alpha/kernel/irq.c index a19d6008229..381431a2d6d 100644 --- a/arch/alpha/kernel/irq.c +++ b/arch/alpha/kernel/irq.c @@ -67,68 +67,21 @@ int irq_select_affinity(unsigned int irq) } #endif /* CONFIG_SMP */ -int -show_interrupts(struct seq_file *p, void *v) +int arch_show_interrupts(struct seq_file *p, int prec) { int j; - int irq = *(loff_t *) v; - struct irqaction * action; - struct irq_desc *desc; - unsigned long flags; #ifdef CONFIG_SMP - if (irq == 0) { - seq_puts(p, " "); - for_each_online_cpu(j) - seq_printf(p, "CPU%d ", j); - seq_putc(p, '\n'); - } -#endif - - if (irq < ACTUAL_NR_IRQS) { - desc = irq_to_desc(irq); - - if (!desc) - return 0; - - raw_spin_lock_irqsave(&desc->lock, flags); - action = desc->action; - if (!action) - goto unlock; - seq_printf(p, "%3d: ", irq); -#ifndef CONFIG_SMP - seq_printf(p, "%10u ", kstat_irqs(irq)); -#else - for_each_online_cpu(j) - seq_printf(p, "%10u ", kstat_irqs_cpu(irq, j)); + seq_puts(p, "IPI: "); + for_each_online_cpu(j) + seq_printf(p, "%10lu ", cpu_data[j].ipi_count); + seq_putc(p, '\n'); #endif - seq_printf(p, " %14s", get_irq_desc_chip(desc)->name); - seq_printf(p, " %c%s", - (action->flags & IRQF_DISABLED)?'+':' ', - action->name); - - for (action=action->next; action; action = action->next) { - seq_printf(p, ", %c%s", - (action->flags & IRQF_DISABLED)?'+':' ', - action->name); - } - - seq_putc(p, '\n'); -unlock: - raw_spin_unlock_irqrestore(&desc->lock, flags); - } else if (irq == ACTUAL_NR_IRQS) { -#ifdef CONFIG_SMP - seq_puts(p, "IPI: "); - for_each_online_cpu(j) - seq_printf(p, "%10lu ", cpu_data[j].ipi_count); - seq_putc(p, '\n'); -#endif - seq_puts(p, "PMI: "); - for_each_online_cpu(j) - seq_printf(p, "%10lu ", per_cpu(irq_pmi_count, j)); - seq_puts(p, " Performance Monitoring\n"); - seq_printf(p, "ERR: %10lu\n", irq_err_count); - } + seq_puts(p, "PMI: "); + for_each_online_cpu(j) + seq_printf(p, "%10lu ", per_cpu(irq_pmi_count, j)); + seq_puts(p, " Performance Monitoring\n"); + seq_printf(p, "ERR: %10lu\n", irq_err_count); return 0; } diff --git a/arch/alpha/kernel/irq_alpha.c b/arch/alpha/kernel/irq_alpha.c index 411ca11d0a1..51b7fbd9e4c 100644 --- a/arch/alpha/kernel/irq_alpha.c +++ b/arch/alpha/kernel/irq_alpha.c @@ -228,7 +228,7 @@ struct irqaction timer_irqaction = { void __init init_rtc_irq(void) { - set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip, + irq_set_chip_and_handler_name(RTC_IRQ, &dummy_irq_chip, handle_simple_irq, "RTC"); setup_irq(RTC_IRQ, &timer_irqaction); } diff --git a/arch/alpha/kernel/irq_i8259.c b/arch/alpha/kernel/irq_i8259.c index c7cc9813e45..e1861c77dab 100644 --- a/arch/alpha/kernel/irq_i8259.c +++ b/arch/alpha/kernel/irq_i8259.c @@ -92,7 +92,7 @@ init_i8259a_irqs(void) outb(0xff, 0xA1); /* mask all of 8259A-2 */ for (i = 0; i < 16; i++) { - set_irq_chip_and_handler(i, &i8259a_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &i8259a_irq_type, handle_level_irq); } setup_irq(2, &cascade); diff --git a/arch/alpha/kernel/irq_pyxis.c b/arch/alpha/kernel/irq_pyxis.c index b30227fa7f5..13c97a5b31e 100644 --- a/arch/alpha/kernel/irq_pyxis.c +++ b/arch/alpha/kernel/irq_pyxis.c @@ -102,7 +102,7 @@ init_pyxis_irqs(unsigned long ignore_mask) for (i = 16; i < 48; ++i) { if ((ignore_mask >> i) & 1) continue; - set_irq_chip_and_handler(i, &pyxis_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &pyxis_irq_type, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } diff --git a/arch/alpha/kernel/irq_srm.c b/arch/alpha/kernel/irq_srm.c index 82a47bba41c..a79fa30e755 100644 --- a/arch/alpha/kernel/irq_srm.c +++ b/arch/alpha/kernel/irq_srm.c @@ -51,7 +51,7 @@ init_srm_irqs(long max, unsigned long ignore_mask) for (i = 16; i < max; ++i) { if (i < 64 && ((ignore_mask >> i) & 1)) continue; - set_irq_chip_and_handler(i, &srm_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &srm_irq_type, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } } diff --git a/arch/alpha/kernel/setup.c b/arch/alpha/kernel/setup.c index d2634e4476b..edbddcbd5bc 100644 --- a/arch/alpha/kernel/setup.c +++ b/arch/alpha/kernel/setup.c @@ -1404,8 +1404,6 @@ determine_cpu_caches (unsigned int cpu_type) case PCA56_CPU: case PCA57_CPU: { - unsigned long cbox_config, size; - if (cpu_type == PCA56_CPU) { L1I = CSHAPE(16*1024, 6, 1); L1D = CSHAPE(8*1024, 5, 1); @@ -1415,10 +1413,12 @@ determine_cpu_caches (unsigned int cpu_type) } L3 = -1; +#if 0 + unsigned long cbox_config, size; + cbox_config = *(vulp) phys_to_virt (0xfffff00008UL); size = 512*1024 * (1 << ((cbox_config >> 12) & 3)); -#if 0 L2 = ((cbox_config >> 31) & 1 ? CSHAPE (size, 6, 1) : -1); #else L2 = external_cache_probe(512*1024, 6); diff --git a/arch/alpha/kernel/smc37c93x.c b/arch/alpha/kernel/smc37c93x.c index 3e6a2893af9..6886b834f48 100644 --- a/arch/alpha/kernel/smc37c93x.c +++ b/arch/alpha/kernel/smc37c93x.c @@ -79,7 +79,6 @@ static unsigned long __init SMCConfigState(unsigned long baseAddr) { unsigned char devId; - unsigned char devRev; unsigned long configPort; unsigned long indexPort; @@ -100,7 +99,7 @@ static unsigned long __init SMCConfigState(unsigned long baseAddr) devId = inb(dataPort); if (devId == VALID_DEVICE_ID) { outb(DEVICE_REV, indexPort); - devRev = inb(dataPort); + /* unsigned char devRev = */ inb(dataPort); break; } else diff --git a/arch/alpha/kernel/sys_alcor.c b/arch/alpha/kernel/sys_alcor.c index 88d95e872f5..0e1439904cd 100644 --- a/arch/alpha/kernel/sys_alcor.c +++ b/arch/alpha/kernel/sys_alcor.c @@ -125,7 +125,7 @@ alcor_init_irq(void) on while IRQ probing. */ if (i >= 16+20 && i <= 16+30) continue; - set_irq_chip_and_handler(i, &alcor_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &alcor_irq_type, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } i8259a_irq_type.irq_ack = alcor_isa_mask_and_ack_irq; diff --git a/arch/alpha/kernel/sys_cabriolet.c b/arch/alpha/kernel/sys_cabriolet.c index 57eb6307bc2..c8c112d5158 100644 --- a/arch/alpha/kernel/sys_cabriolet.c +++ b/arch/alpha/kernel/sys_cabriolet.c @@ -105,8 +105,8 @@ common_init_irq(void (*srm_dev_int)(unsigned long v)) outb(0xff, 0x806); for (i = 16; i < 35; ++i) { - set_irq_chip_and_handler(i, &cabriolet_irq_type, - handle_level_irq); + irq_set_chip_and_handler(i, &cabriolet_irq_type, + handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } } diff --git a/arch/alpha/kernel/sys_dp264.c b/arch/alpha/kernel/sys_dp264.c index 481df4ecb65..5ac00fd4cd0 100644 --- a/arch/alpha/kernel/sys_dp264.c +++ b/arch/alpha/kernel/sys_dp264.c @@ -270,7 +270,7 @@ init_tsunami_irqs(struct irq_chip * ops, int imin, int imax) { long i; for (i = imin; i <= imax; ++i) { - set_irq_chip_and_handler(i, ops, handle_level_irq); + irq_set_chip_and_handler(i, ops, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } } diff --git a/arch/alpha/kernel/sys_eb64p.c b/arch/alpha/kernel/sys_eb64p.c index 402e908ffb3..a7a23b40eec 100644 --- a/arch/alpha/kernel/sys_eb64p.c +++ b/arch/alpha/kernel/sys_eb64p.c @@ -118,7 +118,7 @@ eb64p_init_irq(void) init_i8259a_irqs(); for (i = 16; i < 32; ++i) { - set_irq_chip_and_handler(i, &eb64p_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &eb64p_irq_type, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } diff --git a/arch/alpha/kernel/sys_eiger.c b/arch/alpha/kernel/sys_eiger.c index 0b44a54c152..a60cd5b2621 100644 --- a/arch/alpha/kernel/sys_eiger.c +++ b/arch/alpha/kernel/sys_eiger.c @@ -138,7 +138,7 @@ eiger_init_irq(void) init_i8259a_irqs(); for (i = 16; i < 128; ++i) { - set_irq_chip_and_handler(i, &eiger_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &eiger_irq_type, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } } diff --git a/arch/alpha/kernel/sys_jensen.c b/arch/alpha/kernel/sys_jensen.c index 00341b75c8b..7f1a87f176e 100644 --- a/arch/alpha/kernel/sys_jensen.c +++ b/arch/alpha/kernel/sys_jensen.c @@ -171,11 +171,11 @@ jensen_init_irq(void) { init_i8259a_irqs(); - set_irq_chip_and_handler(1, &jensen_local_irq_type, handle_level_irq); - set_irq_chip_and_handler(4, &jensen_local_irq_type, handle_level_irq); - set_irq_chip_and_handler(3, &jensen_local_irq_type, handle_level_irq); - set_irq_chip_and_handler(7, &jensen_local_irq_type, handle_level_irq); - set_irq_chip_and_handler(9, &jensen_local_irq_type, handle_level_irq); + irq_set_chip_and_handler(1, &jensen_local_irq_type, handle_level_irq); + irq_set_chip_and_handler(4, &jensen_local_irq_type, handle_level_irq); + irq_set_chip_and_handler(3, &jensen_local_irq_type, handle_level_irq); + irq_set_chip_and_handler(7, &jensen_local_irq_type, handle_level_irq); + irq_set_chip_and_handler(9, &jensen_local_irq_type, handle_level_irq); common_init_isa_dma(); } diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c index e61910734e4..388b99d1779 100644 --- a/arch/alpha/kernel/sys_marvel.c +++ b/arch/alpha/kernel/sys_marvel.c @@ -276,7 +276,7 @@ init_io7_irqs(struct io7 *io7, /* Set up the lsi irqs. */ for (i = 0; i < 128; ++i) { - set_irq_chip_and_handler(base + i, lsi_ops, handle_level_irq); + irq_set_chip_and_handler(base + i, lsi_ops, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } @@ -290,7 +290,7 @@ init_io7_irqs(struct io7 *io7, /* Set up the msi irqs. */ for (i = 128; i < (128 + 512); ++i) { - set_irq_chip_and_handler(base + i, msi_ops, handle_level_irq); + irq_set_chip_and_handler(base + i, msi_ops, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } @@ -308,8 +308,8 @@ marvel_init_irq(void) /* Reserve the legacy irqs. */ for (i = 0; i < 16; ++i) { - set_irq_chip_and_handler(i, &marvel_legacy_irq_type, - handle_level_irq); + irq_set_chip_and_handler(i, &marvel_legacy_irq_type, + handle_level_irq); } /* Init the io7 irqs. */ diff --git a/arch/alpha/kernel/sys_mikasa.c b/arch/alpha/kernel/sys_mikasa.c index cf7f43dd314..0e6e4697a02 100644 --- a/arch/alpha/kernel/sys_mikasa.c +++ b/arch/alpha/kernel/sys_mikasa.c @@ -98,7 +98,8 @@ mikasa_init_irq(void) mikasa_update_irq_hw(0); for (i = 16; i < 32; ++i) { - set_irq_chip_and_handler(i, &mikasa_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &mikasa_irq_type, + handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } diff --git a/arch/alpha/kernel/sys_noritake.c b/arch/alpha/kernel/sys_noritake.c index 92bc188e94a..a00ac708716 100644 --- a/arch/alpha/kernel/sys_noritake.c +++ b/arch/alpha/kernel/sys_noritake.c @@ -127,7 +127,8 @@ noritake_init_irq(void) outw(0, 0x54c); for (i = 16; i < 48; ++i) { - set_irq_chip_and_handler(i, &noritake_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &noritake_irq_type, + handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } diff --git a/arch/alpha/kernel/sys_rawhide.c b/arch/alpha/kernel/sys_rawhide.c index 936d4140ed5..7f52161f3d8 100644 --- a/arch/alpha/kernel/sys_rawhide.c +++ b/arch/alpha/kernel/sys_rawhide.c @@ -180,7 +180,8 @@ rawhide_init_irq(void) } for (i = 16; i < 128; ++i) { - set_irq_chip_and_handler(i, &rawhide_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &rawhide_irq_type, + handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } diff --git a/arch/alpha/kernel/sys_rx164.c b/arch/alpha/kernel/sys_rx164.c index cea22a62913..216d94d9c0c 100644 --- a/arch/alpha/kernel/sys_rx164.c +++ b/arch/alpha/kernel/sys_rx164.c @@ -99,7 +99,7 @@ rx164_init_irq(void) rx164_update_irq_hw(0); for (i = 16; i < 40; ++i) { - set_irq_chip_and_handler(i, &rx164_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &rx164_irq_type, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } diff --git a/arch/alpha/kernel/sys_sable.c b/arch/alpha/kernel/sys_sable.c index a349538aabc..da714e427c5 100644 --- a/arch/alpha/kernel/sys_sable.c +++ b/arch/alpha/kernel/sys_sable.c @@ -518,8 +518,8 @@ sable_lynx_init_irq(int nr_of_irqs) long i; for (i = 0; i < nr_of_irqs; ++i) { - set_irq_chip_and_handler(i, &sable_lynx_irq_type, - handle_level_irq); + irq_set_chip_and_handler(i, &sable_lynx_irq_type, + handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } diff --git a/arch/alpha/kernel/sys_takara.c b/arch/alpha/kernel/sys_takara.c index 42a5331f13c..a31f8cd9bd6 100644 --- a/arch/alpha/kernel/sys_takara.c +++ b/arch/alpha/kernel/sys_takara.c @@ -138,7 +138,8 @@ takara_init_irq(void) takara_update_irq_hw(i, -1); for (i = 16; i < 128; ++i) { - set_irq_chip_and_handler(i, &takara_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &takara_irq_type, + handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } diff --git a/arch/alpha/kernel/sys_titan.c b/arch/alpha/kernel/sys_titan.c index 8c13a0c7783..fea0e462099 100644 --- a/arch/alpha/kernel/sys_titan.c +++ b/arch/alpha/kernel/sys_titan.c @@ -179,7 +179,7 @@ init_titan_irqs(struct irq_chip * ops, int imin, int imax) { long i; for (i = imin; i <= imax; ++i) { - set_irq_chip_and_handler(i, ops, handle_level_irq); + irq_set_chip_and_handler(i, ops, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } } diff --git a/arch/alpha/kernel/sys_wildfire.c b/arch/alpha/kernel/sys_wildfire.c index ca60a387ef0..d92cdc715c6 100644 --- a/arch/alpha/kernel/sys_wildfire.c +++ b/arch/alpha/kernel/sys_wildfire.c @@ -156,7 +156,6 @@ static void __init wildfire_init_irq_per_pca(int qbbno, int pcano) { int i, irq_bias; - unsigned long io_bias; static struct irqaction isa_enable = { .handler = no_action, .name = "isa_enable", @@ -165,10 +164,12 @@ wildfire_init_irq_per_pca(int qbbno, int pcano) irq_bias = qbbno * (WILDFIRE_PCA_PER_QBB * WILDFIRE_IRQ_PER_PCA) + pcano * WILDFIRE_IRQ_PER_PCA; +#if 0 + unsigned long io_bias; + /* Only need the following for first PCI bus per PCA. */ io_bias = WILDFIRE_IO(qbbno, pcano<<1) - WILDFIRE_IO_BIAS; -#if 0 outb(0, DMA1_RESET_REG + io_bias); outb(0, DMA2_RESET_REG + io_bias); outb(DMA_MODE_CASCADE, DMA2_MODE_REG + io_bias); @@ -183,17 +184,17 @@ wildfire_init_irq_per_pca(int qbbno, int pcano) for (i = 0; i < 16; ++i) { if (i == 2) continue; - set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type, - handle_level_irq); + irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type, + handle_level_irq); irq_set_status_flags(i + irq_bias, IRQ_LEVEL); } - set_irq_chip_and_handler(36+irq_bias, &wildfire_irq_type, - handle_level_irq); + irq_set_chip_and_handler(36 + irq_bias, &wildfire_irq_type, + handle_level_irq); irq_set_status_flags(36 + irq_bias, IRQ_LEVEL); for (i = 40; i < 64; ++i) { - set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type, - handle_level_irq); + irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type, + handle_level_irq); irq_set_status_flags(i + irq_bias, IRQ_LEVEL); } diff --git a/arch/alpha/kernel/systbls.S b/arch/alpha/kernel/systbls.S index a6a1de9db16..15f999d41c7 100644 --- a/arch/alpha/kernel/systbls.S +++ b/arch/alpha/kernel/systbls.S @@ -498,23 +498,27 @@ sys_call_table: .quad sys_ni_syscall /* sys_timerfd */ .quad sys_eventfd .quad sys_recvmmsg - .quad sys_fallocate /* 480 */ + .quad sys_fallocate /* 480 */ .quad sys_timerfd_create .quad sys_timerfd_settime .quad sys_timerfd_gettime .quad sys_signalfd4 - .quad sys_eventfd2 /* 485 */ + .quad sys_eventfd2 /* 485 */ .quad sys_epoll_create1 .quad sys_dup3 .quad sys_pipe2 .quad sys_inotify_init1 - .quad sys_preadv /* 490 */ + .quad sys_preadv /* 490 */ .quad sys_pwritev .quad sys_rt_tgsigqueueinfo .quad sys_perf_event_open .quad sys_fanotify_init - .quad sys_fanotify_mark /* 495 */ + .quad sys_fanotify_mark /* 495 */ .quad sys_prlimit64 + .quad sys_name_to_handle_at + .quad sys_open_by_handle_at + .quad sys_clock_adjtime + .quad sys_syncfs /* 500 */ .size sys_call_table, . - sys_call_table .type sys_call_table, @object diff --git a/arch/alpha/kernel/time.c b/arch/alpha/kernel/time.c index a58e84f1a63..818e74ed45d 100644 --- a/arch/alpha/kernel/time.c +++ b/arch/alpha/kernel/time.c @@ -153,6 +153,7 @@ void read_persistent_clock(struct timespec *ts) year += 100; ts->tv_sec = mktime(year, mon, day, hour, min, sec); + ts->tv_nsec = 0; } @@ -374,8 +375,7 @@ static struct clocksource clocksource_rpcc = { static inline void register_rpcc_clocksource(long cycle_freq) { - clocksource_calc_mult_shift(&clocksource_rpcc, cycle_freq, 4); - clocksource_register(&clocksource_rpcc); + clocksource_register_hz(&clocksource_rpcc, cycle_freq); } #else /* !CONFIG_SMP */ static inline void register_rpcc_clocksource(long cycle_freq) diff --git a/arch/alpha/lib/ev67-strrchr.S b/arch/alpha/lib/ev67-strrchr.S index 3fd8bf414c7..dd0d8c6b9f5 100644 --- a/arch/alpha/lib/ev67-strrchr.S +++ b/arch/alpha/lib/ev67-strrchr.S @@ -82,7 +82,7 @@ $loop: $eos: negq t1, t4 # E : isolate first null byte match and t1, t4, t4 # E : - subq t4, 1, t5 # E : build a mask of the bytes upto... + subq t4, 1, t5 # E : build a mask of the bytes up to... or t4, t5, t4 # E : ... and including the null and t3, t4, t3 # E : mask out char matches after null diff --git a/arch/alpha/lib/fls.c b/arch/alpha/lib/fls.c index 32afaa3fa68..ddd048c0d82 100644 --- a/arch/alpha/lib/fls.c +++ b/arch/alpha/lib/fls.c @@ -6,7 +6,7 @@ #include <linux/bitops.h> /* This is fls(x)-1, except zero is held to zero. This allows most - efficent input into extbl, plus it allows easy handling of fls(0)=0. */ + efficient input into extbl, plus it allows easy handling of fls(0)=0. */ const unsigned char __flsm1_tab[256] = { diff --git a/arch/alpha/lib/strrchr.S b/arch/alpha/lib/strrchr.S index 82cfd0ac907..1970dc07cfd 100644 --- a/arch/alpha/lib/strrchr.S +++ b/arch/alpha/lib/strrchr.S @@ -54,7 +54,7 @@ $loop: $eos: negq t1, t4 # e0 : isolate first null byte match and t1, t4, t4 # e1 : - subq t4, 1, t5 # e0 : build a mask of the bytes upto... + subq t4, 1, t5 # e0 : build a mask of the bytes up to... or t4, t5, t4 # e1 : ... and including the null and t3, t4, t3 # e0 : mask out char matches after null diff --git a/arch/alpha/oprofile/op_model_ev67.c b/arch/alpha/oprofile/op_model_ev67.c index 70302086283..5b9d178e022 100644 --- a/arch/alpha/oprofile/op_model_ev67.c +++ b/arch/alpha/oprofile/op_model_ev67.c @@ -192,7 +192,7 @@ ev67_handle_interrupt(unsigned long which, struct pt_regs *regs, case TRAP_INVALID1: case TRAP_INVALID2: case TRAP_INVALID3: - /* Pipeline redirection ocurred. PMPC points + /* Pipeline redirection occurred. PMPC points to PALcode. Recognize ITB miss by PALcode offset address, and get actual PC from EXC_ADDR. */ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 599e1634840..377a7a595b0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -28,6 +28,7 @@ config ARM select HAVE_C_RECORDMCOUNT select HAVE_GENERIC_HARDIRQS select HAVE_SPARSE_IRQ + select GENERIC_IRQ_SHOW help The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and @@ -235,6 +236,7 @@ config ARCH_INTEGRATOR select ICST select GENERIC_CLOCKEVENTS select PLAT_VERSATILE + select PLAT_VERSATILE_FPGA_IRQ help Support for ARM's Integrator platform. @@ -242,11 +244,11 @@ config ARCH_REALVIEW bool "ARM Ltd. RealView family" select ARM_AMBA select CLKDEV_LOOKUP - select HAVE_SCHED_CLOCK select ICST select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB select PLAT_VERSATILE + select PLAT_VERSATILE_CLCD select ARM_TIMER_SP804 select GPIO_PL061 if GPIOLIB help @@ -257,11 +259,12 @@ config ARCH_VERSATILE select ARM_AMBA select ARM_VIC select CLKDEV_LOOKUP - select HAVE_SCHED_CLOCK select ICST select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB select PLAT_VERSATILE + select PLAT_VERSATILE_CLCD + select PLAT_VERSATILE_FPGA_IRQ select ARM_TIMER_SP804 help This enables support for ARM Ltd Versatile board. @@ -274,9 +277,10 @@ config ARCH_VEXPRESS select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS select HAVE_CLK - select HAVE_SCHED_CLOCK + select HAVE_PATA_PLATFORM select ICST select PLAT_VERSATILE + select PLAT_VERSATILE_CLCD help This enables support for the ARM Ltd Versatile Express boards. @@ -362,6 +366,7 @@ config ARCH_MXC select GENERIC_CLOCKEVENTS select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP + select HAVE_SCHED_CLOCK help Support for Freescale MXC/iMX-based family of processors @@ -689,7 +694,7 @@ config ARCH_S3C2410 the Samsung SMDK2410 development board (and derivatives). Note, the S3C2416 and the S3C2450 are so close that they even share - the same SoC ID code. This means that there is no seperate machine + the same SoC ID code. This means that there is no separate machine directory (no arch/arm/mach-s3c2450) as the S3C2416 was first. config ARCH_S3C64XX @@ -1011,6 +1016,7 @@ source "arch/arm/mach-ux500/Kconfig" source "arch/arm/mach-versatile/Kconfig" source "arch/arm/mach-vexpress/Kconfig" +source "arch/arm/plat-versatile/Kconfig" source "arch/arm/mach-vt8500/Kconfig" @@ -1534,7 +1540,6 @@ config HIGHMEM config HIGHPTE bool "Allocate 2nd-level pagetables from highmem" depends on HIGHMEM - depends on !OUTER_CACHE config HW_PERF_EVENTS bool "Enable hardware performance counter support for perf events" @@ -2005,6 +2010,9 @@ menu "Power management options" source "kernel/power/Kconfig" config ARCH_SUSPEND_POSSIBLE + depends on !ARCH_S5P64X0 && !ARCH_S5P6442 + depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ + CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE def_bool y endmenu diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu index 901e6dff843..2cef8e13f9f 100644 --- a/arch/arm/Kconfig-nommu +++ b/arch/arm/Kconfig-nommu @@ -34,7 +34,7 @@ config PROCESSOR_ID used instead of the auto-probing which utilizes the register. config REMAP_VECTORS_TO_RAM - bool 'Install vectors to the begining of RAM' if DRAM_BASE + bool 'Install vectors to the beginning of RAM' if DRAM_BASE depends on DRAM_BASE help The kernel needs to change the hardware exception vectors. diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 494224a9b45..03d01d783e3 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -63,17 +63,6 @@ config DEBUG_USER 8 - SIGSEGV faults 16 - SIGBUS faults -config DEBUG_ERRORS - bool "Verbose kernel error messages" - depends on DEBUG_KERNEL - help - This option controls verbose debugging information which can be - printed when the kernel detects an internal error. This debugging - information is useful to kernel hackers when tracking down problems, - but mostly meaningless to other people. It's safe to say Y unless - you are concerned with the code size or don't want to see these - messages. - config DEBUG_STACK_USAGE bool "Enable stack utilization instrumentation" depends on DEBUG_KERNEL diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index f9f77c65dff..0c6852d9350 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -74,7 +74,7 @@ ZTEXTADDR := $(CONFIG_ZBOOT_ROM_TEXT) ZBSSADDR := $(CONFIG_ZBOOT_ROM_BSS) else ZTEXTADDR := 0 -ZBSSADDR := ALIGN(4) +ZBSSADDR := ALIGN(8) endif SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/ @@ -95,8 +95,8 @@ ORIG_CFLAGS := $(KBUILD_CFLAGS) KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) endif -EXTRA_CFLAGS := -fpic -fno-builtin -EXTRA_AFLAGS := -Wa,-march=all +ccflags-y := -fpic -fno-builtin +asflags-y := -Wa,-march=all # Provide size of uncompressed kernel to the decompressor via a linker symbol. LDFLAGS_vmlinux = --defsym _image_size=$(shell stat -c "%s" $(obj)/../Image) diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 84ac4d65631..49f5b2eaaa8 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -21,20 +21,12 @@ #if defined(CONFIG_DEBUG_ICEDCC) -#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) .macro loadsp, rb, tmp .endm .macro writeb, ch, rb mcr p14, 0, \ch, c0, c5, 0 .endm -#elif defined(CONFIG_CPU_V7) - .macro loadsp, rb, tmp - .endm - .macro writeb, ch, rb -wait: mrc p14, 0, pc, c0, c1, 0 - bcs wait - mcr p14, 0, \ch, c0, c5, 0 - .endm #elif defined(CONFIG_CPU_XSCALE) .macro loadsp, rb, tmp .endm @@ -187,15 +179,14 @@ not_angel: bl cache_on restart: adr r0, LC0 - ldmia r0, {r1, r2, r3, r5, r6, r9, r11, r12} - ldr sp, [r0, #32] + ldmia r0, {r1, r2, r3, r6, r9, r11, r12} + ldr sp, [r0, #28] /* * We might be running at a different address. We need * to fix up various pointers. */ sub r0, r0, r1 @ calculate the delta offset - add r5, r5, r0 @ _start add r6, r6, r0 @ _edata #ifndef CONFIG_ZBOOT_ROM @@ -214,31 +205,40 @@ restart: adr r0, LC0 /* * Check to see if we will overwrite ourselves. * r4 = final kernel address - * r5 = start of this image * r9 = size of decompressed image * r10 = end of this image, including bss/stack/malloc space if non XIP * We basically want: - * r4 >= r10 -> OK - * r4 + image length <= r5 -> OK + * r4 - 16k page directory >= r10 -> OK + * r4 + image length <= current position (pc) -> OK */ + add r10, r10, #16384 cmp r4, r10 bhs wont_overwrite add r10, r4, r9 - cmp r10, r5 + ARM( cmp r10, pc ) + THUMB( mov lr, pc ) + THUMB( cmp r10, lr ) bls wont_overwrite /* * Relocate ourselves past the end of the decompressed kernel. - * r5 = start of this image * r6 = _edata * r10 = end of the decompressed kernel * Because we always copy ahead, we need to do it from the end and go * backward in case the source and destination overlap. */ - /* Round up to next 256-byte boundary. */ - add r10, r10, #256 + /* + * Bump to the next 256-byte boundary with the size of + * the relocation code added. This avoids overwriting + * ourself when the offset is small. + */ + add r10, r10, #((reloc_code_end - restart + 256) & ~255) bic r10, r10, #255 + /* Get start of code we want to copy and align it down. */ + adr r5, restart + bic r5, r5, #31 + sub r9, r6, r5 @ size to copy add r9, r9, #31 @ rounded up to a multiple bic r9, r9, #31 @ ... of 32 bytes @@ -253,6 +253,11 @@ restart: adr r0, LC0 /* Preserve offset to relocated code. */ sub r6, r9, r6 +#ifndef CONFIG_ZBOOT_ROM + /* cache_clean_flush may use the stack, so relocate it */ + add sp, sp, r6 +#endif + bl cache_clean_flush adr r0, BSYM(restart) @@ -341,7 +346,6 @@ not_relocated: mov r0, #0 LC0: .word LC0 @ r1 .word __bss_start @ r2 .word _end @ r3 - .word _start @ r5 .word _edata @ r6 .word _image_size @ r9 .word _got_start @ r11 @@ -1070,6 +1074,7 @@ memdump: mov r12, r0 #endif .ltorg +reloc_code_end: .align .section ".stack", "aw", %nobits diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c index 4657e877bf8..2df38263124 100644 --- a/arch/arm/boot/compressed/misc.c +++ b/arch/arm/boot/compressed/misc.c @@ -36,7 +36,7 @@ extern void error(char *x); #ifdef CONFIG_DEBUG_ICEDCC -#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) static void icedcc_putc(int ch) { @@ -52,16 +52,6 @@ static void icedcc_putc(int ch) asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch)); } -#elif defined(CONFIG_CPU_V7) - -static void icedcc_putc(int ch) -{ - asm( - "wait: mrc p14, 0, pc, c0, c1, 0 \n\ - bcs wait \n\ - mcr p14, 0, %0, c0, c5, 0 " - : : "r" (ch)); -} #elif defined(CONFIG_CPU_XSCALE) diff --git a/arch/arm/boot/compressed/mmcif-sh7372.c b/arch/arm/boot/compressed/mmcif-sh7372.c index e6180af241f..7453c8337b8 100644 --- a/arch/arm/boot/compressed/mmcif-sh7372.c +++ b/arch/arm/boot/compressed/mmcif-sh7372.c @@ -10,7 +10,8 @@ */ #include <linux/mmc/sh_mmcif.h> -#include <mach/mmcif.h> +#include <linux/mmc/boot.h> +#include <mach/mmc.h> #define MMCIF_BASE (void __iomem *)0xe6bd0000 @@ -41,8 +42,8 @@ */ asmlinkage void mmcif_loader(unsigned char *buf, unsigned long len) { - mmcif_init_progress(); - mmcif_update_progress(MMCIF_PROGRESS_ENTER); + mmc_init_progress(); + mmc_update_progress(MMC_PROGRESS_ENTER); /* Initialise MMC * registers: PORT84CR-PORT92CR @@ -68,12 +69,12 @@ asmlinkage void mmcif_loader(unsigned char *buf, unsigned long len) /* Enable clock to MMC hardware block */ __raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 12), SMSTPCR3); - mmcif_update_progress(MMCIF_PROGRESS_INIT); + mmc_update_progress(MMC_PROGRESS_INIT); /* setup MMCIF hardware */ sh_mmcif_boot_init(MMCIF_BASE); - mmcif_update_progress(MMCIF_PROGRESS_LOAD); + mmc_update_progress(MMC_PROGRESS_LOAD); /* load kernel via MMCIF interface */ sh_mmcif_boot_do_read(MMCIF_BASE, 2, /* Kernel is at block 2 */ @@ -83,5 +84,5 @@ asmlinkage void mmcif_loader(unsigned char *buf, unsigned long len) /* Disable clock to MMC hardware block */ __raw_writel(__raw_readl(SMSTPCR3) & (1 << 12), SMSTPCR3); - mmcif_update_progress(MMCIF_PROGRESS_DONE); + mmc_update_progress(MMC_PROGRESS_DONE); } diff --git a/arch/arm/boot/compressed/vmlinux.lds.in b/arch/arm/boot/compressed/vmlinux.lds.in index 5309909d728..ea80abe7884 100644 --- a/arch/arm/boot/compressed/vmlinux.lds.in +++ b/arch/arm/boot/compressed/vmlinux.lds.in @@ -54,6 +54,7 @@ SECTIONS .bss : { *(.bss) } _end = .; + . = ALIGN(8); /* the stack must be 64-bit aligned */ .stack : { *(.stack) } .stab 0 : { *(.stab) } diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index e7521bca2c3..6ea9b6f3607 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -16,5 +16,4 @@ obj-$(CONFIG_SHARP_SCOOP) += scoop.o obj-$(CONFIG_ARCH_IXP2000) += uengine.o obj-$(CONFIG_ARCH_IXP23XX) += uengine.o obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o -obj-$(CONFIG_COMMON_CLKDEV) += clkdev.o obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index cb6b041c39d..f70ec7dadeb 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -213,8 +213,8 @@ static int gic_set_wake(struct irq_data *d, unsigned int on) static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) { - struct gic_chip_data *chip_data = get_irq_data(irq); - struct irq_chip *chip = get_irq_chip(irq); + struct gic_chip_data *chip_data = irq_get_handler_data(irq); + struct irq_chip *chip = irq_get_chip(irq); unsigned int cascade_irq, gic_irq; unsigned long status; @@ -257,9 +257,9 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) { if (gic_nr >= MAX_GIC_NR) BUG(); - if (set_irq_data(irq, &gic_data[gic_nr]) != 0) + if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0) BUG(); - set_irq_chained_handler(irq, gic_handle_cascade_irq); + irq_set_chained_handler(irq, gic_handle_cascade_irq); } static void __init gic_dist_init(struct gic_chip_data *gic, @@ -319,9 +319,8 @@ static void __init gic_dist_init(struct gic_chip_data *gic, * Setup the Linux IRQ subsystem. */ for (i = irq_start; i < irq_limit; i++) { - set_irq_chip(i, &gic_chip); - set_irq_chip_data(i, gic); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &gic_chip, handle_level_irq); + irq_set_chip_data(i, gic); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } @@ -382,7 +381,7 @@ void __cpuinit gic_enable_ppi(unsigned int irq) unsigned long flags; local_irq_save(flags); - irq_to_desc(irq)->status |= IRQ_NOPROBE; + irq_set_status_flags(irq, IRQ_NOPROBE); gic_unmask_irq(irq_get_irq_data(irq)); local_irq_restore(flags); } diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c index fcddd48fe9d..7a21927c52e 100644 --- a/arch/arm/common/it8152.c +++ b/arch/arm/common/it8152.c @@ -88,8 +88,8 @@ void it8152_init_irq(void) __raw_writel((0), IT8152_INTC_LDCNIRR); for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) { - set_irq_chip(irq, &it8152_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &it8152_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index a026a6bf489..b55c3625d7e 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c @@ -140,7 +140,7 @@ static struct locomo_dev_info locomo_devices[] = { static void locomo_handler(unsigned int irq, struct irq_desc *desc) { - struct locomo *lchip = get_irq_chip_data(irq); + struct locomo *lchip = irq_get_chip_data(irq); int req, i; /* Acknowledge the parent IRQ */ @@ -197,15 +197,14 @@ static void locomo_setup_irq(struct locomo *lchip) /* * Install handler for IRQ_LOCOMO_HW. */ - set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING); - set_irq_chip_data(lchip->irq, lchip); - set_irq_chained_handler(lchip->irq, locomo_handler); + irq_set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING); + irq_set_chip_data(lchip->irq, lchip); + irq_set_chained_handler(lchip->irq, locomo_handler); /* Install handlers for IRQ_LOCOMO_* */ for ( ; irq <= lchip->irq_base + 3; irq++) { - set_irq_chip(irq, &locomo_chip); - set_irq_chip_data(irq, lchip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &locomo_chip, handle_level_irq); + irq_set_chip_data(irq, lchip); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } @@ -476,8 +475,8 @@ static void __locomo_remove(struct locomo *lchip) device_for_each_child(lchip->dev, NULL, locomo_remove_child); if (lchip->irq != NO_IRQ) { - set_irq_chained_handler(lchip->irq, NULL); - set_irq_data(lchip->irq, NULL); + irq_set_chained_handler(lchip->irq, NULL); + irq_set_handler_data(lchip->irq, NULL); } iounmap(lchip->base); diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c index 8f0f86db360..97912fa4878 100644 --- a/arch/arm/common/pl330.c +++ b/arch/arm/common/pl330.c @@ -1045,7 +1045,7 @@ static inline int _loop(unsigned dry_run, u8 buf[], unsigned lcnt0, lcnt1, ljmp0, ljmp1; struct _arg_LPEND lpend; - /* Max iterations possibile in DMALP is 256 */ + /* Max iterations possible in DMALP is 256 */ if (*bursts >= 256*256) { lcnt1 = 256; lcnt0 = 256; @@ -1446,7 +1446,7 @@ int pl330_update(const struct pl330_info *pi) } for (ev = 0; ev < pi->pcfg.num_events; ev++) { - if (val & (1 << ev)) { /* Event occured */ + if (val & (1 << ev)) { /* Event occurred */ struct pl330_thread *thrd; u32 inten = readl(regs + INTEN); int active; diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index eb9796b0dab..a12b33c0dc4 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -202,7 +202,7 @@ static void sa1111_irq_handler(unsigned int irq, struct irq_desc *desc) { unsigned int stat0, stat1, i; - struct sa1111 *sachip = get_irq_data(irq); + struct sa1111 *sachip = irq_get_handler_data(irq); void __iomem *mapbase = sachip->base + SA1111_INTC; stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0); @@ -472,25 +472,25 @@ static void sa1111_setup_irq(struct sa1111 *sachip) sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1); for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) { - set_irq_chip(irq, &sa1111_low_chip); - set_irq_chip_data(irq, sachip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &sa1111_low_chip, + handle_edge_irq); + irq_set_chip_data(irq, sachip); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) { - set_irq_chip(irq, &sa1111_high_chip); - set_irq_chip_data(irq, sachip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &sa1111_high_chip, + handle_edge_irq); + irq_set_chip_data(irq, sachip); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } /* * Register SA1111 interrupt */ - set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); - set_irq_data(sachip->irq, sachip); - set_irq_chained_handler(sachip->irq, sa1111_irq_handler); + irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); + irq_set_handler_data(sachip->irq, sachip); + irq_set_chained_handler(sachip->irq, sa1111_irq_handler); } /* @@ -815,8 +815,8 @@ static void __sa1111_remove(struct sa1111 *sachip) clk_disable(sachip->clk); if (sachip->irq != NO_IRQ) { - set_irq_chained_handler(sachip->irq, NULL); - set_irq_data(sachip->irq, NULL); + irq_set_chained_handler(sachip->irq, NULL); + irq_set_handler_data(sachip->irq, NULL); release_mem_region(sachip->phys + SA1111_INTC, 512); } diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index ae5fe7292e0..113085a7712 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -305,9 +305,9 @@ static void __init vic_set_irq_sources(void __iomem *base, if (vic_sources & (1 << i)) { unsigned int irq = irq_start + i; - set_irq_chip(irq, &vic_chip); - set_irq_chip_data(irq, base); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &vic_chip, + handle_level_irq); + irq_set_chip_data(irq, base); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/configs/at91x40_defconfig b/arch/arm/configs/at91x40_defconfig new file mode 100644 index 00000000000..c55e9212fcb --- /dev/null +++ b/arch/arm/configs/at91x40_defconfig @@ -0,0 +1,48 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_EMBEDDED=y +# CONFIG_HOTPLUG is not set +# CONFIG_ELF_CORE is not set +# CONFIG_FUTEX is not set +# CONFIG_TIMERFD is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_MMU is not set +CONFIG_ARCH_AT91=y +CONFIG_ARCH_AT91X40=y +CONFIG_MACH_AT91EB01=y +CONFIG_AT91_EARLY_USART0=y +CONFIG_CPU_ARM7TDMI=y +CONFIG_SET_MEM_PARAM=y +CONFIG_DRAM_BASE=0x01000000 +CONFIG_DRAM_SIZE=0x00400000 +CONFIG_FLASH_MEM_BASE=0x01400000 +CONFIG_PROCESSOR_ID=0x14000040 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_BINFMT_FLAT=y +# CONFIG_SUSPEND is not set +# CONFIG_FW_LOADER is not set +CONFIG_MTD=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_RAM=y +CONFIG_MTD_ROM=y +CONFIG_BLK_DEV_RAM=y +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_DEVKMEM is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_EXT2_FS=y +# CONFIG_DNOTIFY is not set +CONFIG_ROMFS_FS=y +# CONFIG_ENABLE_MUST_CHECK is not set diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 019fb7c67dc..076db52ff67 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -193,6 +193,17 @@ CONFIG_FIRMWARE_EDID=y CONFIG_FB_MODE_HELPERS=y CONFIG_FB_TILEBLITTING=y CONFIG_FB_OMAP_LCD_VGA=y +CONFIG_OMAP2_DSS=m +CONFIG_OMAP2_DSS_RFBI=y +CONFIG_OMAP2_DSS_SDI=y +CONFIG_OMAP2_DSS_DSI=y +CONFIG_FB_OMAP2=m +CONFIG_PANEL_GENERIC_DPI=m +CONFIG_PANEL_SHARP_LS037V7DW01=m +CONFIG_PANEL_NEC_NL8048HL11_01B=m +CONFIG_PANEL_TAAL=m +CONFIG_PANEL_TPO_TD043MTEA1=m +CONFIG_PANEL_ACX565AKM=m CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 7a9267e5da5..8845f1c9925 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -21,6 +21,10 @@ CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_IOSCHED_CFQ is not set CONFIG_ARCH_TEGRA=y CONFIG_MACH_HARMONY=y +CONFIG_MACH_KAEN=y +CONFIG_MACH_PAZ00=y +CONFIG_MACH_TRIMSLICE=y +CONFIG_MACH_WARIO=y CONFIG_TEGRA_DEBUG_UARTD=y CONFIG_ARM_ERRATA_742230=y CONFIG_NO_HZ=y @@ -40,6 +44,10 @@ CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y CONFIG_INET_ESP=y # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set @@ -66,7 +74,7 @@ CONFIG_APDS9802ALS=y CONFIG_ISL29003=y CONFIG_NETDEVICES=y CONFIG_DUMMY=y -# CONFIG_NETDEV_1000 is not set +CONFIG_R8169=y # CONFIG_NETDEV_10000 is not set # CONFIG_WLAN is not set # CONFIG_INPUT is not set @@ -78,12 +86,23 @@ CONFIG_SERIAL_8250_CONSOLE=y # CONFIG_LEGACY_PTYS is not set # CONFIG_HW_RANDOM is not set CONFIG_I2C=y -# CONFIG_HWMON is not set -# CONFIG_MFD_SUPPORT is not set +# CONFIG_I2C_COMPAT is not set +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_TEGRA=y +CONFIG_SENSORS_LM90=y +CONFIG_MFD_TPS6586X=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_TPS6586X=y # CONFIG_USB_SUPPORT is not set CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_TEGRA=y +CONFIG_STAGING=y +# CONFIG_STAGING_EXCLUDE_BUILD is not set +CONFIG_IIO=y +CONFIG_SENSORS_ISL29018=y +CONFIG_SENSORS_AK8975=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y @@ -95,6 +114,10 @@ CONFIG_EXT3_FS_SECURITY=y # CONFIG_DNOTIFY is not set CONFIG_VFAT_FS=y CONFIG_TMPFS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y CONFIG_PRINTK_TIME=y diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index af54ed102f5..6b7403fd8f5 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -287,41 +287,63 @@ static inline int fls(int x) #include <asm-generic/bitops/hweight.h> #include <asm-generic/bitops/lock.h> -/* - * Ext2 is defined to use little-endian byte ordering. - * These do not need to be atomic. - */ -#define ext2_set_bit(nr,p) \ - __test_and_set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) -#define ext2_set_bit_atomic(lock,nr,p) \ - test_and_set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) -#define ext2_clear_bit(nr,p) \ - __test_and_clear_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) -#define ext2_clear_bit_atomic(lock,nr,p) \ - test_and_clear_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) -#define ext2_test_bit(nr,p) \ - test_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) -#define ext2_find_first_zero_bit(p,sz) \ - _find_first_zero_bit_le(p,sz) -#define ext2_find_next_zero_bit(p,sz,off) \ - _find_next_zero_bit_le(p,sz,off) -#define ext2_find_next_bit(p, sz, off) \ - _find_next_bit_le(p, sz, off) +static inline void __set_bit_le(int nr, void *addr) +{ + __set_bit(WORD_BITOFF_TO_LE(nr), addr); +} + +static inline void __clear_bit_le(int nr, void *addr) +{ + __clear_bit(WORD_BITOFF_TO_LE(nr), addr); +} + +static inline int __test_and_set_bit_le(int nr, void *addr) +{ + return __test_and_set_bit(WORD_BITOFF_TO_LE(nr), addr); +} + +static inline int test_and_set_bit_le(int nr, void *addr) +{ + return test_and_set_bit(WORD_BITOFF_TO_LE(nr), addr); +} + +static inline int __test_and_clear_bit_le(int nr, void *addr) +{ + return __test_and_clear_bit(WORD_BITOFF_TO_LE(nr), addr); +} + +static inline int test_and_clear_bit_le(int nr, void *addr) +{ + return test_and_clear_bit(WORD_BITOFF_TO_LE(nr), addr); +} + +static inline int test_bit_le(int nr, const void *addr) +{ + return test_bit(WORD_BITOFF_TO_LE(nr), addr); +} + +static inline int find_first_zero_bit_le(const void *p, unsigned size) +{ + return _find_first_zero_bit_le(p, size); +} + +static inline int find_next_zero_bit_le(const void *p, int size, int offset) +{ + return _find_next_zero_bit_le(p, size, offset); +} + +static inline int find_next_bit_le(const void *p, int size, int offset) +{ + return _find_next_bit_le(p, size, offset); +} /* - * Minix is defined to use little-endian byte ordering. - * These do not need to be atomic. + * Ext2 is defined to use little-endian byte ordering. */ -#define minix_set_bit(nr,p) \ - __set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) -#define minix_test_bit(nr,p) \ - test_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) -#define minix_test_and_set_bit(nr,p) \ - __test_and_set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) -#define minix_test_and_clear_bit(nr,p) \ - __test_and_clear_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) -#define minix_find_first_zero_bit(p,sz) \ - _find_first_zero_bit_le(p,sz) +#define ext2_set_bit_atomic(lock, nr, p) \ + test_and_set_bit_le(nr, p) +#define ext2_clear_bit_atomic(lock, nr, p) \ + test_and_clear_bit_le(nr, p) #endif /* __KERNEL__ */ diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index ed5bc9e05a4..cd4458f6417 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -2,6 +2,7 @@ #define __ASM_ARM_CPUTYPE_H #include <linux/stringify.h> +#include <linux/kernel.h> #define CPUID_ID 0 #define CPUID_CACHETYPE 1 diff --git a/arch/arm/include/asm/fpstate.h b/arch/arm/include/asm/fpstate.h index ee5e03efc1b..3ad4c10d0d8 100644 --- a/arch/arm/include/asm/fpstate.h +++ b/arch/arm/include/asm/fpstate.h @@ -18,7 +18,7 @@ * VFP storage area has: * - FPEXC, FPSCR, FPINST and FPINST2. * - 16 or 32 double precision data registers - * - an implementation-dependant word of state for FLDMX/FSTMX (pre-ARMv6) + * - an implementation-dependent word of state for FLDMX/FSTMX (pre-ARMv6) * * FPEXC will always be non-zero once the VFP has been used in this process. */ diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h index c7afbc552c7..7e30874377e 100644 --- a/arch/arm/include/asm/glue-cache.h +++ b/arch/arm/include/asm/glue-cache.h @@ -126,7 +126,7 @@ #endif #if !defined(_CACHE) && !defined(MULTI_CACHE) -#error Unknown cache maintainence model +#error Unknown cache maintenance model #endif #ifndef MULTI_CACHE diff --git a/arch/arm/include/asm/glue.h b/arch/arm/include/asm/glue.h index 0ec35d1698a..fbf71d75ec8 100644 --- a/arch/arm/include/asm/glue.h +++ b/arch/arm/include/asm/glue.h @@ -10,8 +10,8 @@ * * This file provides the glue to stick the processor-specific bits * into the kernel in an efficient manner. The idea is to use branches - * when we're only targetting one class of TLB, or indirect calls - * when we're targetting multiple classes of TLBs. + * when we're only targeting one class of TLB, or indirect calls + * when we're targeting multiple classes of TLBs. */ #ifdef __KERNEL__ diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h index f35b86e68dd..e4a04e4e562 100644 --- a/arch/arm/include/asm/hardware/pl080.h +++ b/arch/arm/include/asm/hardware/pl080.h @@ -16,7 +16,7 @@ * make it not entierly compatible with the PL080 specification from * ARM. When in doubt, check the Samsung documentation first. * - * The Samsung defines are PL080S, and add an extra controll register, + * The Samsung defines are PL080S, and add an extra control register, * the ability to move more than 2^11 counts of data and some extra * OneNAND features. */ diff --git a/arch/arm/include/asm/hw_irq.h b/arch/arm/include/asm/hw_irq.h index 5586b7c8ef6..a71b417b185 100644 --- a/arch/arm/include/asm/hw_irq.h +++ b/arch/arm/include/asm/hw_irq.h @@ -10,14 +10,6 @@ static inline void ack_bad_irq(int irq) irq_err_count++; } -/* - * Obsolete inline function for calling irq descriptor handlers. - */ -static inline void desc_handle_irq(unsigned int irq, struct irq_desc *desc) -{ - desc->handle_irq(irq, desc); -} - void set_irq_flags(unsigned int irq, unsigned int flags); #define IRQF_VALID (1 << 0) diff --git a/arch/arm/include/asm/kprobes.h b/arch/arm/include/asm/kprobes.h index bb8a19bd582..e46bdd0097e 100644 --- a/arch/arm/include/asm/kprobes.h +++ b/arch/arm/include/asm/kprobes.h @@ -39,10 +39,13 @@ typedef u32 kprobe_opcode_t; struct kprobe; typedef void (kprobe_insn_handler_t)(struct kprobe *, struct pt_regs *); +typedef unsigned long (kprobe_check_cc)(unsigned long); + /* Architecture specific copy of original instruction. */ struct arch_specific_insn { kprobe_opcode_t *insn; kprobe_insn_handler_t *insn_handler; + kprobe_check_cc *insn_check_cc; }; struct prev_kprobe { diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h index 6bc63ab498c..080d74f8128 100644 --- a/arch/arm/include/asm/localtimer.h +++ b/arch/arm/include/asm/localtimer.h @@ -44,8 +44,14 @@ int local_timer_ack(void); /* * Setup a local timer interrupt for a CPU. */ -void local_timer_setup(struct clock_event_device *); +int local_timer_setup(struct clock_event_device *); +#else + +static inline int local_timer_setup(struct clock_event_device *evt) +{ + return -ENXIO; +} #endif #endif diff --git a/arch/arm/include/asm/mach/udc_pxa2xx.h b/arch/arm/include/asm/mach/udc_pxa2xx.h index 833306ee9e7..ea297ac70bc 100644 --- a/arch/arm/include/asm/mach/udc_pxa2xx.h +++ b/arch/arm/include/asm/mach/udc_pxa2xx.h @@ -20,8 +20,6 @@ struct pxa2xx_udc_mach_info { * VBUS IRQ and omit the methods above. Store the GPIO number * here. Note that sometimes the signals go through inverters... */ - bool gpio_vbus_inverted; - int gpio_vbus; /* high == vbus present */ bool gpio_pullup_inverted; int gpio_pullup; /* high == pullup activated */ }; diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h index 348d513afa9..d8387437ec5 100644 --- a/arch/arm/include/asm/outercache.h +++ b/arch/arm/include/asm/outercache.h @@ -21,6 +21,8 @@ #ifndef __ASM_OUTERCACHE_H #define __ASM_OUTERCACHE_H +#include <linux/types.h> + struct outer_cache_fns { void (*inv_range)(unsigned long, unsigned long); void (*clean_range)(unsigned long, unsigned long); @@ -38,17 +40,17 @@ struct outer_cache_fns { extern struct outer_cache_fns outer_cache; -static inline void outer_inv_range(unsigned long start, unsigned long end) +static inline void outer_inv_range(phys_addr_t start, phys_addr_t end) { if (outer_cache.inv_range) outer_cache.inv_range(start, end); } -static inline void outer_clean_range(unsigned long start, unsigned long end) +static inline void outer_clean_range(phys_addr_t start, phys_addr_t end) { if (outer_cache.clean_range) outer_cache.clean_range(start, end); } -static inline void outer_flush_range(unsigned long start, unsigned long end) +static inline void outer_flush_range(phys_addr_t start, phys_addr_t end) { if (outer_cache.flush_range) outer_cache.flush_range(start, end); @@ -74,11 +76,11 @@ static inline void outer_disable(void) #else -static inline void outer_inv_range(unsigned long start, unsigned long end) +static inline void outer_inv_range(phys_addr_t start, phys_addr_t end) { } -static inline void outer_clean_range(unsigned long start, unsigned long end) +static inline void outer_clean_range(phys_addr_t start, phys_addr_t end) { } -static inline void outer_flush_range(unsigned long start, unsigned long end) +static inline void outer_flush_range(phys_addr_t start, phys_addr_t end) { } static inline void outer_flush_all(void) { } static inline void outer_inv_all(void) { } diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index ebcb6432f45..5750704e027 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -301,6 +301,7 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; #define pgd_present(pgd) (1) #define pgd_clear(pgdp) do { } while (0) #define set_pgd(pgd,pgdp) do { } while (0) +#define set_pud(pud,pudp) do { } while (0) /* Find an entry in the second-level page table.. */ @@ -351,7 +352,7 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd) #define pte_unmap(pte) __pte_unmap(pte) #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) -#define pfn_pte(pfn,prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) +#define pfn_pte(pfn,prot) __pte(__pfn_to_phys(pfn) | pgprot_val(prot)) #define pte_page(pte) pfn_to_page(pte_pfn(pte)) #define mk_pte(page,prot) pfn_pte(page_to_pfn(page), prot) diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index da8b52ec49c..95176af3df8 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -195,7 +195,7 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn } #define NR_BANKS 8 struct membank { - unsigned long start; + phys_addr_t start; unsigned long size; unsigned int highmem; }; diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 9a87823642d..832888d0c20 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -159,7 +159,7 @@ extern unsigned int user_debug; #include <mach/barriers.h> #elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP) #define mb() do { dsb(); outer_sync(); } while (0) -#define rmb() dmb() +#define rmb() dsb() #define wmb() mb() #else #include <asm/memory.h> @@ -249,7 +249,7 @@ do { \ * cache totally. This means that the cache becomes inconsistent, and, * since we use normal loads/stores as well, this is really bad. * Typically, this causes oopsen in filp_close, but could have other, - * more disasterous effects. There are two work-arounds: + * more disastrous effects. There are two work-arounds: * 1. Disable interrupts and emulate the atomic swap * 2. Clean the cache, perform atomic swap, flush the cache * diff --git a/arch/arm/include/asm/thread_notify.h b/arch/arm/include/asm/thread_notify.h index c4391ba2035..1dc98067589 100644 --- a/arch/arm/include/asm/thread_notify.h +++ b/arch/arm/include/asm/thread_notify.h @@ -43,6 +43,7 @@ static inline void thread_notify(unsigned long rc, struct thread_info *thread) #define THREAD_NOTIFY_FLUSH 0 #define THREAD_NOTIFY_EXIT 1 #define THREAD_NOTIFY_SWITCH 2 +#define THREAD_NOTIFY_COPY 3 #endif #endif diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h index 345df01534a..48192ac3a23 100644 --- a/arch/arm/include/asm/types.h +++ b/arch/arm/include/asm/types.h @@ -16,15 +16,6 @@ typedef unsigned short umode_t; #define BITS_PER_LONG 32 -#ifndef __ASSEMBLY__ - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; -typedef u32 dma64_addr_t; - -#endif /* __ASSEMBLY__ */ - #endif /* __KERNEL__ */ #endif diff --git a/arch/arm/include/asm/ucontext.h b/arch/arm/include/asm/ucontext.h index 47f023aa849..14749aec94b 100644 --- a/arch/arm/include/asm/ucontext.h +++ b/arch/arm/include/asm/ucontext.h @@ -47,7 +47,7 @@ struct crunch_sigframe { #endif #ifdef CONFIG_IWMMXT -/* iwmmxt_area is 0x98 bytes long, preceeded by 8 bytes of signature */ +/* iwmmxt_area is 0x98 bytes long, preceded by 8 bytes of signature */ #define IWMMXT_MAGIC 0x12ef842a #define IWMMXT_STORAGE_SIZE (IWMMXT_SIZE + 8) diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h index c891eb76c0e..87dbe3e2197 100644 --- a/arch/arm/include/asm/unistd.h +++ b/arch/arm/include/asm/unistd.h @@ -396,6 +396,10 @@ #define __NR_fanotify_init (__NR_SYSCALL_BASE+367) #define __NR_fanotify_mark (__NR_SYSCALL_BASE+368) #define __NR_prlimit64 (__NR_SYSCALL_BASE+369) +#define __NR_name_to_handle_at (__NR_SYSCALL_BASE+370) +#define __NR_open_by_handle_at (__NR_SYSCALL_BASE+371) +#define __NR_clock_adjtime (__NR_SYSCALL_BASE+372) +#define __NR_syncfs (__NR_SYSCALL_BASE+373) /* * The following SWIs are ARM private. diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 74554f1742d..8d95446150a 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -29,7 +29,7 @@ obj-$(CONFIG_MODULES) += armksyms.o module.o obj-$(CONFIG_ARTHUR) += arthur.o obj-$(CONFIG_ISA_DMA) += dma-isa.o obj-$(CONFIG_PCI) += bios32.o isa.o -obj-$(CONFIG_PM) += sleep.o +obj-$(CONFIG_PM_SLEEP) += sleep.o obj-$(CONFIG_HAVE_SCHED_CLOCK) += sched_clock.o obj-$(CONFIG_SMP) += smp.o smp_tlb.o obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index d86fcd44b22..e4ee050aad7 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -159,31 +159,6 @@ static void __devinit pci_fixup_dec21285(struct pci_dev *dev) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285); /* - * Same as above. The PrPMC800 carrier board for the PrPMC1100 - * card maps the host-bridge @ 00:01:00 for some reason and it - * ends up getting scanned. Note that we only want to do this - * fixup when we find the IXP4xx on a PrPMC system, which is why - * we check the machine type. We could be running on a board - * with an IXP4xx target device and we don't want to kill the - * resources in that case. - */ -static void __devinit pci_fixup_prpmc1100(struct pci_dev *dev) -{ - int i; - - if (machine_is_prpmc1100()) { - dev->class &= 0xff; - dev->class |= PCI_CLASS_BRIDGE_HOST << 8; - for (i = 0; i < PCI_NUM_RESOURCES; i++) { - dev->resource[i].start = 0; - dev->resource[i].end = 0; - dev->resource[i].flags = 0; - } - } -} -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP4XX, pci_fixup_prpmc1100); - -/* * PCI IDE controllers use non-standard I/O port decoding, respect it. */ static void __devinit pci_fixup_ide_bases(struct pci_dev *dev) diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index 5c26eccef99..7fbf28c35bb 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S @@ -379,6 +379,10 @@ CALL(sys_fanotify_init) CALL(sys_fanotify_mark) CALL(sys_prlimit64) +/* 370 */ CALL(sys_name_to_handle_at) + CALL(sys_open_by_handle_at) + CALL(sys_clock_adjtime) + CALL(sys_syncfs) #ifndef syscalls_counted .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls #define syscalls_counted diff --git a/arch/arm/kernel/crash_dump.c b/arch/arm/kernel/crash_dump.c index cd3b853a8a6..90c50d4b43f 100644 --- a/arch/arm/kernel/crash_dump.c +++ b/arch/arm/kernel/crash_dump.c @@ -18,9 +18,6 @@ #include <linux/uaccess.h> #include <linux/io.h> -/* stores the physical address of elf header of crash image */ -unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX; - /** * copy_oldmem_page() - copy one page from old kernel memory * @pfn: page frame number to be copied diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S index d2d983be096..bcd66e00bdb 100644 --- a/arch/arm/kernel/debug.S +++ b/arch/arm/kernel/debug.S @@ -25,7 +25,7 @@ .macro addruart, rp, rv .endm -#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) .macro senduart, rd, rx mcr p14, 0, \rd, c0, c5, 0 @@ -49,23 +49,6 @@ 1002: .endm -#elif defined(CONFIG_CPU_V7) - - .macro senduart, rd, rx - mcr p14, 0, \rd, c0, c5, 0 - .endm - - .macro busyuart, rd, rx -busy: mrc p14, 0, pc, c0, c1, 0 - bcs busy - .endm - - .macro waituart, rd, rx -wait: mrc p14, 0, pc, c0, c1, 0 - bcs wait - - .endm - #elif defined(CONFIG_CPU_XSCALE) .macro senduart, rd, rx diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c index 2ad62df3773..d16500110ee 100644 --- a/arch/arm/kernel/ecard.c +++ b/arch/arm/kernel/ecard.c @@ -1043,8 +1043,8 @@ ecard_probe(int slot, card_type_t type) */ if (slot < 8) { ec->irq = 32 + slot; - set_irq_chip(ec->irq, &ecard_chip); - set_irq_handler(ec->irq, handle_level_irq); + irq_set_chip_and_handler(ec->irq, &ecard_chip, + handle_level_irq); set_irq_flags(ec->irq, IRQF_VALID); } @@ -1103,7 +1103,7 @@ static int __init ecard_init(void) irqhw = ecard_probeirqhw(); - set_irq_chained_handler(IRQ_EXPANSIONCARD, + irq_set_chained_handler(IRQ_EXPANSIONCARD, irqhw ? ecard_irqexp_handler : ecard_irq_handler); ecard_proc_init(); diff --git a/arch/arm/kernel/elf.c b/arch/arm/kernel/elf.c index d4a0da1e48f..9b05c6a0dce 100644 --- a/arch/arm/kernel/elf.c +++ b/arch/arm/kernel/elf.c @@ -40,15 +40,22 @@ EXPORT_SYMBOL(elf_check_arch); void elf_set_personality(const struct elf32_hdr *x) { unsigned int eflags = x->e_flags; - unsigned int personality = PER_LINUX_32BIT; + unsigned int personality = current->personality & ~PER_MASK; + + /* + * We only support Linux ELF executables, so always set the + * personality to LINUX. + */ + personality |= PER_LINUX; /* * APCS-26 is only valid for OABI executables */ - if ((eflags & EF_ARM_EABI_MASK) == EF_ARM_EABI_UNKNOWN) { - if (eflags & EF_ARM_APCS_26) - personality = PER_LINUX; - } + if ((eflags & EF_ARM_EABI_MASK) == EF_ARM_EABI_UNKNOWN && + (eflags & EF_ARM_APCS_26)) + personality &= ~ADDR_LIMIT_32BIT; + else + personality |= ADDR_LIMIT_32BIT; set_personality(personality); diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c index 052b509e2d5..1bec8b5f22f 100644 --- a/arch/arm/kernel/etm.c +++ b/arch/arm/kernel/etm.c @@ -338,7 +338,7 @@ static struct miscdevice etb_miscdev = { .fops = &etb_fops, }; -static int __init etb_probe(struct amba_device *dev, const struct amba_id *id) +static int __devinit etb_probe(struct amba_device *dev, const struct amba_id *id) { struct tracectx *t = &tracer; int ret = 0; @@ -530,7 +530,7 @@ static ssize_t trace_mode_store(struct kobject *kobj, static struct kobj_attribute trace_mode_attr = __ATTR(trace_mode, 0644, trace_mode_show, trace_mode_store); -static int __init etm_probe(struct amba_device *dev, const struct amba_id *id) +static int __devinit etm_probe(struct amba_device *dev, const struct amba_id *id) { struct tracectx *t = &tracer; int ret = 0; diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 44b84fe6e1b..87acc25d7a3 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -238,8 +238,8 @@ static int enable_monitor_mode(void) ARM_DBG_READ(c1, 0, dscr); /* Ensure that halting mode is disabled. */ - if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN, "halting debug mode enabled." - "Unable to access hardware resources.")) { + if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN, + "halting debug mode enabled. Unable to access hardware resources.\n")) { ret = -EPERM; goto out; } @@ -377,7 +377,7 @@ int arch_install_hw_breakpoint(struct perf_event *bp) } } - if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot")) { + if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot\n")) { ret = -EBUSY; goto out; } @@ -423,7 +423,7 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp) } } - if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot")) + if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot\n")) return; /* Reset the control register. */ @@ -635,7 +635,7 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp) if (WARN_ONCE(!bp->overflow_handler && (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_brps() || !bp->hw.bp_target), - "overflow handler required but none found")) { + "overflow handler required but none found\n")) { ret = -EINVAL; } out: @@ -868,6 +868,13 @@ static void reset_ctrl_regs(void *info) */ asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0)); isb(); + + /* + * Clear any configured vector-catch events before + * enabling monitor mode. + */ + asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0)); + isb(); } if (enable_monitor_mode()) @@ -936,8 +943,8 @@ static int __init arch_hw_breakpoint_init(void) ARM_DBG_READ(c1, 0, dscr); if (dscr & ARM_DSCR_HDBGEN) { max_watchpoint_len = 4; - pr_warning("halting debug mode enabled. Assuming maximum " - "watchpoint size of %u bytes.", max_watchpoint_len); + pr_warning("halting debug mode enabled. Assuming maximum watchpoint size of %u bytes.\n", + max_watchpoint_len); } else { /* Work out the maximum supported watchpoint length. */ max_watchpoint_len = get_max_wp_len(); diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 3535d3793e6..83bbad03fcc 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -51,63 +51,18 @@ unsigned long irq_err_count; -int show_interrupts(struct seq_file *p, void *v) +int arch_show_interrupts(struct seq_file *p, int prec) { - int i = *(loff_t *) v, cpu; - struct irq_desc *desc; - struct irqaction * action; - unsigned long flags; - int prec, n; - - for (prec = 3, n = 1000; prec < 10 && n <= nr_irqs; prec++) - n *= 10; - -#ifdef CONFIG_SMP - if (prec < 4) - prec = 4; -#endif - - if (i == 0) { - char cpuname[12]; - - seq_printf(p, "%*s ", prec, ""); - for_each_present_cpu(cpu) { - sprintf(cpuname, "CPU%d", cpu); - seq_printf(p, " %10s", cpuname); - } - seq_putc(p, '\n'); - } - - if (i < nr_irqs) { - desc = irq_to_desc(i); - raw_spin_lock_irqsave(&desc->lock, flags); - action = desc->action; - if (!action) - goto unlock; - - seq_printf(p, "%*d: ", prec, i); - for_each_present_cpu(cpu) - seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); - seq_printf(p, " %10s", desc->irq_data.chip->name ? : "-"); - seq_printf(p, " %s", action->name); - for (action = action->next; action; action = action->next) - seq_printf(p, ", %s", action->name); - - seq_putc(p, '\n'); -unlock: - raw_spin_unlock_irqrestore(&desc->lock, flags); - } else if (i == nr_irqs) { #ifdef CONFIG_FIQ - show_fiq_list(p, prec); + show_fiq_list(p, prec); #endif #ifdef CONFIG_SMP - show_ipi_list(p, prec); + show_ipi_list(p, prec); #endif #ifdef CONFIG_LOCAL_TIMERS - show_local_irqs(p, prec); + show_local_irqs(p, prec); #endif - seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count); - } + seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count); return 0; } @@ -144,24 +99,21 @@ asm_do_IRQ(unsigned int irq, struct pt_regs *regs) void set_irq_flags(unsigned int irq, unsigned int iflags) { - struct irq_desc *desc; - unsigned long flags; + unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; if (irq >= nr_irqs) { printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq); return; } - desc = irq_to_desc(irq); - raw_spin_lock_irqsave(&desc->lock, flags); - desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; if (iflags & IRQF_VALID) - desc->status &= ~IRQ_NOREQUEST; + clr |= IRQ_NOREQUEST; if (iflags & IRQF_PROBE) - desc->status &= ~IRQ_NOPROBE; + clr |= IRQ_NOPROBE; if (!(iflags & IRQF_NOAUTOEN)) - desc->status &= ~IRQ_NOAUTOEN; - raw_spin_unlock_irqrestore(&desc->lock, flags); + clr |= IRQ_NOAUTOEN; + /* Order is clear bits in "clr" then set bits in "set" */ + irq_modify_status(irq, clr, set & ~clr); } void __init init_IRQ(void) diff --git a/arch/arm/kernel/kprobes-decode.c b/arch/arm/kernel/kprobes-decode.c index 8f6ed43861f..15eeff6aea0 100644 --- a/arch/arm/kernel/kprobes-decode.c +++ b/arch/arm/kernel/kprobes-decode.c @@ -34,9 +34,6 @@ * * *) If the PC is written to by the instruction, the * instruction must be fully simulated in software. - * If it is a conditional instruction, the handler - * will use insn[0] to copy its condition code to - * set r0 to 1 and insn[1] to "mov pc, lr" to return. * * *) Otherwise, a modified form of the instruction is * directly executed. Its handler calls the @@ -68,13 +65,17 @@ #define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25) +#define is_r15(insn, bitpos) (((insn) & (0xf << bitpos)) == (0xf << bitpos)) + +/* + * Test if load/store instructions writeback the address register. + * if P (bit 24) == 0 or W (bit 21) == 1 + */ +#define is_writeback(insn) ((insn ^ 0x01000000) & 0x01200000) + #define PSR_fs (PSR_f|PSR_s) #define KPROBE_RETURN_INSTRUCTION 0xe1a0f00e /* mov pc, lr */ -#define SET_R0_TRUE_INSTRUCTION 0xe3a00001 /* mov r0, #1 */ - -#define truecc_insn(insn) (((insn) & 0xf0000000) | \ - (SET_R0_TRUE_INSTRUCTION & 0x0fffffff)) typedef long (insn_0arg_fn_t)(void); typedef long (insn_1arg_fn_t)(long); @@ -419,14 +420,10 @@ insnslot_llret_4arg_rwflags(long r0, long r1, long r2, long r3, long *cpsr, static void __kprobes simulate_bbl(struct kprobe *p, struct pt_regs *regs) { - insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0]; kprobe_opcode_t insn = p->opcode; long iaddr = (long)p->addr; int disp = branch_displacement(insn); - if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn)) - return; - if (insn & (1 << 24)) regs->ARM_lr = iaddr + 4; @@ -446,14 +443,10 @@ static void __kprobes simulate_blx1(struct kprobe *p, struct pt_regs *regs) static void __kprobes simulate_blx2bx(struct kprobe *p, struct pt_regs *regs) { - insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0]; kprobe_opcode_t insn = p->opcode; int rm = insn & 0xf; long rmv = regs->uregs[rm]; - if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn)) - return; - if (insn & (1 << 5)) regs->ARM_lr = (long)p->addr + 4; @@ -463,9 +456,16 @@ static void __kprobes simulate_blx2bx(struct kprobe *p, struct pt_regs *regs) regs->ARM_cpsr |= PSR_T_BIT; } +static void __kprobes simulate_mrs(struct kprobe *p, struct pt_regs *regs) +{ + kprobe_opcode_t insn = p->opcode; + int rd = (insn >> 12) & 0xf; + unsigned long mask = 0xf8ff03df; /* Mask out execution state */ + regs->uregs[rd] = regs->ARM_cpsr & mask; +} + static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs) { - insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0]; kprobe_opcode_t insn = p->opcode; int rn = (insn >> 16) & 0xf; int lbit = insn & (1 << 20); @@ -476,9 +476,6 @@ static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs) int reg_bit_vector; int reg_count; - if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn)) - return; - reg_count = 0; reg_bit_vector = insn & 0xffff; while (reg_bit_vector) { @@ -510,11 +507,6 @@ static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs) static void __kprobes simulate_stm1_pc(struct kprobe *p, struct pt_regs *regs) { - insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0]; - - if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn)) - return; - regs->ARM_pc = (long)p->addr + str_pc_offset; simulate_ldm1stm1(p, regs); regs->ARM_pc = (long)p->addr + 4; @@ -525,24 +517,16 @@ static void __kprobes simulate_mov_ipsp(struct kprobe *p, struct pt_regs *regs) regs->uregs[12] = regs->uregs[13]; } -static void __kprobes emulate_ldcstc(struct kprobe *p, struct pt_regs *regs) -{ - insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0]; - kprobe_opcode_t insn = p->opcode; - int rn = (insn >> 16) & 0xf; - long rnv = regs->uregs[rn]; - - /* Save Rn in case of writeback. */ - regs->uregs[rn] = insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn); -} - static void __kprobes emulate_ldrd(struct kprobe *p, struct pt_regs *regs) { insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0]; kprobe_opcode_t insn = p->opcode; + long ppc = (long)p->addr + 8; int rd = (insn >> 12) & 0xf; int rn = (insn >> 16) & 0xf; int rm = insn & 0xf; /* rm may be invalid, don't care. */ + long rmv = (rm == 15) ? ppc : regs->uregs[rm]; + long rnv = (rn == 15) ? ppc : regs->uregs[rn]; /* Not following the C calling convention here, so need asm(). */ __asm__ __volatile__ ( @@ -554,29 +538,36 @@ static void __kprobes emulate_ldrd(struct kprobe *p, struct pt_regs *regs) "str r0, %[rn] \n\t" /* in case of writeback */ "str r2, %[rd0] \n\t" "str r3, %[rd1] \n\t" - : [rn] "+m" (regs->uregs[rn]), + : [rn] "+m" (rnv), [rd0] "=m" (regs->uregs[rd]), [rd1] "=m" (regs->uregs[rd+1]) - : [rm] "m" (regs->uregs[rm]), + : [rm] "m" (rmv), [cpsr] "r" (regs->ARM_cpsr), [i_fn] "r" (i_fn) : "r0", "r1", "r2", "r3", "lr", "cc" ); + if (is_writeback(insn)) + regs->uregs[rn] = rnv; } static void __kprobes emulate_strd(struct kprobe *p, struct pt_regs *regs) { insn_4arg_fn_t *i_fn = (insn_4arg_fn_t *)&p->ainsn.insn[0]; kprobe_opcode_t insn = p->opcode; + long ppc = (long)p->addr + 8; int rd = (insn >> 12) & 0xf; int rn = (insn >> 16) & 0xf; int rm = insn & 0xf; - long rnv = regs->uregs[rn]; - long rmv = regs->uregs[rm]; /* rm/rmv may be invalid, don't care. */ + long rnv = (rn == 15) ? ppc : regs->uregs[rn]; + /* rm/rmv may be invalid, don't care. */ + long rmv = (rm == 15) ? ppc : regs->uregs[rm]; + long rnv_wb; - regs->uregs[rn] = insnslot_4arg_rflags(rnv, rmv, regs->uregs[rd], + rnv_wb = insnslot_4arg_rflags(rnv, rmv, regs->uregs[rd], regs->uregs[rd+1], regs->ARM_cpsr, i_fn); + if (is_writeback(insn)) + regs->uregs[rn] = rnv_wb; } static void __kprobes emulate_ldr(struct kprobe *p, struct pt_regs *regs) @@ -594,7 +585,8 @@ static void __kprobes emulate_ldr(struct kprobe *p, struct pt_regs *regs) long cpsr = regs->ARM_cpsr; fnr.dr = insnslot_llret_3arg_rflags(rnv, 0, rmv, cpsr, i_fn); - regs->uregs[rn] = fnr.r0; /* Save Rn in case of writeback. */ + if (rn != 15) + regs->uregs[rn] = fnr.r0; /* Save Rn in case of writeback. */ rdv = fnr.r1; if (rd == 15) { @@ -622,35 +614,11 @@ static void __kprobes emulate_str(struct kprobe *p, struct pt_regs *regs) long rdv = (rd == 15) ? iaddr + str_pc_offset : regs->uregs[rd]; long rnv = (rn == 15) ? iaddr + 8 : regs->uregs[rn]; long rmv = regs->uregs[rm]; /* rm/rmv may be invalid, don't care. */ + long rnv_wb; - /* Save Rn in case of writeback. */ - regs->uregs[rn] = - insnslot_3arg_rflags(rnv, rdv, rmv, regs->ARM_cpsr, i_fn); -} - -static void __kprobes emulate_mrrc(struct kprobe *p, struct pt_regs *regs) -{ - insn_llret_0arg_fn_t *i_fn = (insn_llret_0arg_fn_t *)&p->ainsn.insn[0]; - kprobe_opcode_t insn = p->opcode; - union reg_pair fnr; - int rd = (insn >> 12) & 0xf; - int rn = (insn >> 16) & 0xf; - - fnr.dr = insnslot_llret_0arg_rflags(regs->ARM_cpsr, i_fn); - regs->uregs[rn] = fnr.r0; - regs->uregs[rd] = fnr.r1; -} - -static void __kprobes emulate_mcrr(struct kprobe *p, struct pt_regs *regs) -{ - insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0]; - kprobe_opcode_t insn = p->opcode; - int rd = (insn >> 12) & 0xf; - int rn = (insn >> 16) & 0xf; - long rnv = regs->uregs[rn]; - long rdv = regs->uregs[rd]; - - insnslot_2arg_rflags(rnv, rdv, regs->ARM_cpsr, i_fn); + rnv_wb = insnslot_3arg_rflags(rnv, rdv, rmv, regs->ARM_cpsr, i_fn); + if (rn != 15) + regs->uregs[rn] = rnv_wb; /* Save Rn in case of writeback. */ } static void __kprobes emulate_sat(struct kprobe *p, struct pt_regs *regs) @@ -686,32 +654,32 @@ static void __kprobes emulate_none(struct kprobe *p, struct pt_regs *regs) insnslot_0arg_rflags(regs->ARM_cpsr, i_fn); } -static void __kprobes emulate_rd12(struct kprobe *p, struct pt_regs *regs) +static void __kprobes emulate_nop(struct kprobe *p, struct pt_regs *regs) { - insn_0arg_fn_t *i_fn = (insn_0arg_fn_t *)&p->ainsn.insn[0]; - kprobe_opcode_t insn = p->opcode; - int rd = (insn >> 12) & 0xf; - - regs->uregs[rd] = insnslot_0arg_rflags(regs->ARM_cpsr, i_fn); } -static void __kprobes emulate_ird12(struct kprobe *p, struct pt_regs *regs) +static void __kprobes +emulate_rd12_modify(struct kprobe *p, struct pt_regs *regs) { insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0]; kprobe_opcode_t insn = p->opcode; - int ird = (insn >> 12) & 0xf; + int rd = (insn >> 12) & 0xf; + long rdv = regs->uregs[rd]; - insnslot_1arg_rflags(regs->uregs[ird], regs->ARM_cpsr, i_fn); + regs->uregs[rd] = insnslot_1arg_rflags(rdv, regs->ARM_cpsr, i_fn); } -static void __kprobes emulate_rn16(struct kprobe *p, struct pt_regs *regs) +static void __kprobes +emulate_rd12rn0_modify(struct kprobe *p, struct pt_regs *regs) { - insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0]; + insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0]; kprobe_opcode_t insn = p->opcode; - int rn = (insn >> 16) & 0xf; + int rd = (insn >> 12) & 0xf; + int rn = insn & 0xf; + long rdv = regs->uregs[rd]; long rnv = regs->uregs[rn]; - insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn); + regs->uregs[rd] = insnslot_2arg_rflags(rdv, rnv, regs->ARM_cpsr, i_fn); } static void __kprobes emulate_rd12rm0(struct kprobe *p, struct pt_regs *regs) @@ -817,6 +785,17 @@ emulate_alu_imm_rwflags(struct kprobe *p, struct pt_regs *regs) } static void __kprobes +emulate_alu_tests_imm(struct kprobe *p, struct pt_regs *regs) +{ + insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0]; + kprobe_opcode_t insn = p->opcode; + int rn = (insn >> 16) & 0xf; + long rnv = (rn == 15) ? (long)p->addr + 8 : regs->uregs[rn]; + + insnslot_1arg_rwflags(rnv, ®s->ARM_cpsr, i_fn); +} + +static void __kprobes emulate_alu_rflags(struct kprobe *p, struct pt_regs *regs) { insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0]; @@ -852,14 +831,34 @@ emulate_alu_rwflags(struct kprobe *p, struct pt_regs *regs) insnslot_3arg_rwflags(rnv, rmv, rsv, ®s->ARM_cpsr, i_fn); } +static void __kprobes +emulate_alu_tests(struct kprobe *p, struct pt_regs *regs) +{ + insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0]; + kprobe_opcode_t insn = p->opcode; + long ppc = (long)p->addr + 8; + int rn = (insn >> 16) & 0xf; + int rs = (insn >> 8) & 0xf; /* rs/rsv may be invalid, don't care. */ + int rm = insn & 0xf; + long rnv = (rn == 15) ? ppc : regs->uregs[rn]; + long rmv = (rm == 15) ? ppc : regs->uregs[rm]; + long rsv = regs->uregs[rs]; + + insnslot_3arg_rwflags(rnv, rmv, rsv, ®s->ARM_cpsr, i_fn); +} + static enum kprobe_insn __kprobes prep_emulate_ldr_str(kprobe_opcode_t insn, struct arch_specific_insn *asi) { - int ibit = (insn & (1 << 26)) ? 25 : 22; + int not_imm = (insn & (1 << 26)) ? (insn & (1 << 25)) + : (~insn & (1 << 22)); + + if (is_writeback(insn) && is_r15(insn, 16)) + return INSN_REJECTED; /* Writeback to PC */ insn &= 0xfff00fff; insn |= 0x00001000; /* Rn = r0, Rd = r1 */ - if (insn & (1 << ibit)) { + if (not_imm) { insn &= ~0xf; insn |= 2; /* Rm = r2 */ } @@ -869,20 +868,40 @@ prep_emulate_ldr_str(kprobe_opcode_t insn, struct arch_specific_insn *asi) } static enum kprobe_insn __kprobes -prep_emulate_rd12rm0(kprobe_opcode_t insn, struct arch_specific_insn *asi) +prep_emulate_rd12_modify(kprobe_opcode_t insn, struct arch_specific_insn *asi) { - insn &= 0xffff0ff0; /* Rd = r0, Rm = r0 */ + if (is_r15(insn, 12)) + return INSN_REJECTED; /* Rd is PC */ + + insn &= 0xffff0fff; /* Rd = r0 */ asi->insn[0] = insn; - asi->insn_handler = emulate_rd12rm0; + asi->insn_handler = emulate_rd12_modify; return INSN_GOOD; } static enum kprobe_insn __kprobes -prep_emulate_rd12(kprobe_opcode_t insn, struct arch_specific_insn *asi) +prep_emulate_rd12rn0_modify(kprobe_opcode_t insn, + struct arch_specific_insn *asi) { - insn &= 0xffff0fff; /* Rd = r0 */ + if (is_r15(insn, 12)) + return INSN_REJECTED; /* Rd is PC */ + + insn &= 0xffff0ff0; /* Rd = r0 */ + insn |= 0x00000001; /* Rn = r1 */ + asi->insn[0] = insn; + asi->insn_handler = emulate_rd12rn0_modify; + return INSN_GOOD; +} + +static enum kprobe_insn __kprobes +prep_emulate_rd12rm0(kprobe_opcode_t insn, struct arch_specific_insn *asi) +{ + if (is_r15(insn, 12)) + return INSN_REJECTED; /* Rd is PC */ + + insn &= 0xffff0ff0; /* Rd = r0, Rm = r0 */ asi->insn[0] = insn; - asi->insn_handler = emulate_rd12; + asi->insn_handler = emulate_rd12rm0; return INSN_GOOD; } @@ -890,6 +909,9 @@ static enum kprobe_insn __kprobes prep_emulate_rd12rn16rm0_wflags(kprobe_opcode_t insn, struct arch_specific_insn *asi) { + if (is_r15(insn, 12)) + return INSN_REJECTED; /* Rd is PC */ + insn &= 0xfff00ff0; /* Rd = r0, Rn = r0 */ insn |= 0x00000001; /* Rm = r1 */ asi->insn[0] = insn; @@ -901,6 +923,9 @@ static enum kprobe_insn __kprobes prep_emulate_rd16rs8rm0_wflags(kprobe_opcode_t insn, struct arch_specific_insn *asi) { + if (is_r15(insn, 16)) + return INSN_REJECTED; /* Rd is PC */ + insn &= 0xfff0f0f0; /* Rd = r0, Rs = r0 */ insn |= 0x00000001; /* Rm = r1 */ asi->insn[0] = insn; @@ -912,6 +937,9 @@ static enum kprobe_insn __kprobes prep_emulate_rd16rn12rs8rm0_wflags(kprobe_opcode_t insn, struct arch_specific_insn *asi) { + if (is_r15(insn, 16)) + return INSN_REJECTED; /* Rd is PC */ + insn &= 0xfff000f0; /* Rd = r0, Rn = r0 */ insn |= 0x00000102; /* Rs = r1, Rm = r2 */ asi->insn[0] = insn; @@ -923,6 +951,9 @@ static enum kprobe_insn __kprobes prep_emulate_rdhi16rdlo12rs8rm0_wflags(kprobe_opcode_t insn, struct arch_specific_insn *asi) { + if (is_r15(insn, 16) || is_r15(insn, 12)) + return INSN_REJECTED; /* RdHi or RdLo is PC */ + insn &= 0xfff000f0; /* RdHi = r0, RdLo = r1 */ insn |= 0x00001203; /* Rs = r2, Rm = r3 */ asi->insn[0] = insn; @@ -943,20 +974,13 @@ prep_emulate_rdhi16rdlo12rs8rm0_wflags(kprobe_opcode_t insn, static enum kprobe_insn __kprobes space_1111(kprobe_opcode_t insn, struct arch_specific_insn *asi) { - /* CPS mmod == 1 : 1111 0001 0000 xx10 xxxx xxxx xx0x xxxx */ - /* RFE : 1111 100x x0x1 xxxx xxxx 1010 xxxx xxxx */ - /* SRS : 1111 100x x1x0 1101 xxxx 0101 xxxx xxxx */ - if ((insn & 0xfff30020) == 0xf1020000 || - (insn & 0xfe500f00) == 0xf8100a00 || - (insn & 0xfe5f0f00) == 0xf84d0500) - return INSN_REJECTED; - - /* PLD : 1111 01x1 x101 xxxx xxxx xxxx xxxx xxxx : */ - if ((insn & 0xfd700000) == 0xf4500000) { - insn &= 0xfff0ffff; /* Rn = r0 */ - asi->insn[0] = insn; - asi->insn_handler = emulate_rn16; - return INSN_GOOD; + /* memory hint : 1111 0100 x001 xxxx xxxx xxxx xxxx xxxx : */ + /* PLDI : 1111 0100 x101 xxxx xxxx xxxx xxxx xxxx : */ + /* PLDW : 1111 0101 x001 xxxx xxxx xxxx xxxx xxxx : */ + /* PLD : 1111 0101 x101 xxxx xxxx xxxx xxxx xxxx : */ + if ((insn & 0xfe300000) == 0xf4100000) { + asi->insn_handler = emulate_nop; + return INSN_GOOD_NO_SLOT; } /* BLX(1) : 1111 101x xxxx xxxx xxxx xxxx xxxx xxxx : */ @@ -965,41 +989,22 @@ space_1111(kprobe_opcode_t insn, struct arch_specific_insn *asi) return INSN_GOOD_NO_SLOT; } - /* SETEND : 1111 0001 0000 0001 xxxx xxxx 0000 xxxx */ - /* CDP2 : 1111 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */ - if ((insn & 0xffff00f0) == 0xf1010000 || - (insn & 0xff000010) == 0xfe000000) { - asi->insn[0] = insn; - asi->insn_handler = emulate_none; - return INSN_GOOD; - } + /* CPS : 1111 0001 0000 xxx0 xxxx xxxx xx0x xxxx */ + /* SETEND: 1111 0001 0000 0001 xxxx xxxx 0000 xxxx */ + + /* SRS : 1111 100x x1x0 xxxx xxxx xxxx xxxx xxxx */ + /* RFE : 1111 100x x0x1 xxxx xxxx xxxx xxxx xxxx */ + /* Coprocessor instructions... */ /* MCRR2 : 1111 1100 0100 xxxx xxxx xxxx xxxx xxxx : (Rd != Rn) */ /* MRRC2 : 1111 1100 0101 xxxx xxxx xxxx xxxx xxxx : (Rd != Rn) */ - if ((insn & 0xffe00000) == 0xfc400000) { - insn &= 0xfff00fff; /* Rn = r0 */ - insn |= 0x00001000; /* Rd = r1 */ - asi->insn[0] = insn; - asi->insn_handler = - (insn & (1 << 20)) ? emulate_mrrc : emulate_mcrr; - return INSN_GOOD; - } + /* LDC2 : 1111 110x xxx1 xxxx xxxx xxxx xxxx xxxx */ + /* STC2 : 1111 110x xxx0 xxxx xxxx xxxx xxxx xxxx */ + /* CDP2 : 1111 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */ + /* MCR2 : 1111 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */ + /* MRC2 : 1111 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */ - /* LDC2 : 1111 110x xxx1 xxxx xxxx xxxx xxxx xxxx */ - /* STC2 : 1111 110x xxx0 xxxx xxxx xxxx xxxx xxxx */ - if ((insn & 0xfe000000) == 0xfc000000) { - insn &= 0xfff0ffff; /* Rn = r0 */ - asi->insn[0] = insn; - asi->insn_handler = emulate_ldcstc; - return INSN_GOOD; - } - - /* MCR2 : 1111 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */ - /* MRC2 : 1111 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */ - insn &= 0xffff0fff; /* Rd = r0 */ - asi->insn[0] = insn; - asi->insn_handler = (insn & (1 << 20)) ? emulate_rd12 : emulate_ird12; - return INSN_GOOD; + return INSN_REJECTED; } static enum kprobe_insn __kprobes @@ -1008,19 +1013,18 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi) /* cccc 0001 0xx0 xxxx xxxx xxxx xxxx xxx0 xxxx */ if ((insn & 0x0f900010) == 0x01000000) { - /* BXJ : cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */ - /* MSR : cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */ - if ((insn & 0x0ff000f0) == 0x01200020 || - (insn & 0x0fb000f0) == 0x01200000) - return INSN_REJECTED; - - /* MRS : cccc 0001 0x00 xxxx xxxx xxxx 0000 xxxx */ - if ((insn & 0x0fb00010) == 0x01000000) - return prep_emulate_rd12(insn, asi); + /* MRS cpsr : cccc 0001 0000 xxxx xxxx xxxx 0000 xxxx */ + if ((insn & 0x0ff000f0) == 0x01000000) { + if (is_r15(insn, 12)) + return INSN_REJECTED; /* Rd is PC */ + asi->insn_handler = simulate_mrs; + return INSN_GOOD_NO_SLOT; + } /* SMLALxy : cccc 0001 0100 xxxx xxxx xxxx 1xx0 xxxx */ if ((insn & 0x0ff00090) == 0x01400080) - return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi); + return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, + asi); /* SMULWy : cccc 0001 0010 xxxx xxxx xxxx 1x10 xxxx */ /* SMULxy : cccc 0001 0110 xxxx xxxx xxxx 1xx0 xxxx */ @@ -1029,24 +1033,29 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi) return prep_emulate_rd16rs8rm0_wflags(insn, asi); /* SMLAxy : cccc 0001 0000 xxxx xxxx xxxx 1xx0 xxxx : Q */ - /* SMLAWy : cccc 0001 0010 xxxx xxxx xxxx 0x00 xxxx : Q */ - return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi); + /* SMLAWy : cccc 0001 0010 xxxx xxxx xxxx 1x00 xxxx : Q */ + if ((insn & 0x0ff00090) == 0x01000080 || + (insn & 0x0ff000b0) == 0x01200080) + return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi); + /* BXJ : cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */ + /* MSR : cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */ + /* MRS spsr : cccc 0001 0100 xxxx xxxx xxxx 0000 xxxx */ + + /* Other instruction encodings aren't yet defined */ + return INSN_REJECTED; } /* cccc 0001 0xx0 xxxx xxxx xxxx xxxx 0xx1 xxxx */ else if ((insn & 0x0f900090) == 0x01000010) { - /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */ - if ((insn & 0xfff000f0) == 0xe1200070) - return INSN_REJECTED; - /* BLX(2) : cccc 0001 0010 xxxx xxxx xxxx 0011 xxxx */ /* BX : cccc 0001 0010 xxxx xxxx xxxx 0001 xxxx */ if ((insn & 0x0ff000d0) == 0x01200010) { - asi->insn[0] = truecc_insn(insn); + if ((insn & 0x0ff000ff) == 0x0120003f) + return INSN_REJECTED; /* BLX pc */ asi->insn_handler = simulate_blx2bx; - return INSN_GOOD; + return INSN_GOOD_NO_SLOT; } /* CLZ : cccc 0001 0110 xxxx xxxx xxxx 0001 xxxx */ @@ -1057,17 +1066,27 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi) /* QSUB : cccc 0001 0010 xxxx xxxx xxxx 0101 xxxx :Q */ /* QDADD : cccc 0001 0100 xxxx xxxx xxxx 0101 xxxx :Q */ /* QDSUB : cccc 0001 0110 xxxx xxxx xxxx 0101 xxxx :Q */ - return prep_emulate_rd12rn16rm0_wflags(insn, asi); + if ((insn & 0x0f9000f0) == 0x01000050) + return prep_emulate_rd12rn16rm0_wflags(insn, asi); + + /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */ + /* SMC : cccc 0001 0110 xxxx xxxx xxxx 0111 xxxx */ + + /* Other instruction encodings aren't yet defined */ + return INSN_REJECTED; } /* cccc 0000 xxxx xxxx xxxx xxxx xxxx 1001 xxxx */ - else if ((insn & 0x0f000090) == 0x00000090) { + else if ((insn & 0x0f0000f0) == 0x00000090) { /* MUL : cccc 0000 0000 xxxx xxxx xxxx 1001 xxxx : */ /* MULS : cccc 0000 0001 xxxx xxxx xxxx 1001 xxxx :cc */ /* MLA : cccc 0000 0010 xxxx xxxx xxxx 1001 xxxx : */ /* MLAS : cccc 0000 0011 xxxx xxxx xxxx 1001 xxxx :cc */ /* UMAAL : cccc 0000 0100 xxxx xxxx xxxx 1001 xxxx : */ + /* undef : cccc 0000 0101 xxxx xxxx xxxx 1001 xxxx : */ + /* MLS : cccc 0000 0110 xxxx xxxx xxxx 1001 xxxx : */ + /* undef : cccc 0000 0111 xxxx xxxx xxxx 1001 xxxx : */ /* UMULL : cccc 0000 1000 xxxx xxxx xxxx 1001 xxxx : */ /* UMULLS : cccc 0000 1001 xxxx xxxx xxxx 1001 xxxx :cc */ /* UMLAL : cccc 0000 1010 xxxx xxxx xxxx 1001 xxxx : */ @@ -1076,13 +1095,15 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi) /* SMULLS : cccc 0000 1101 xxxx xxxx xxxx 1001 xxxx :cc */ /* SMLAL : cccc 0000 1110 xxxx xxxx xxxx 1001 xxxx : */ /* SMLALS : cccc 0000 1111 xxxx xxxx xxxx 1001 xxxx :cc */ - if ((insn & 0x0fe000f0) == 0x00000090) { - return prep_emulate_rd16rs8rm0_wflags(insn, asi); - } else if ((insn & 0x0fe000f0) == 0x00200090) { - return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi); - } else { - return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi); - } + if ((insn & 0x00d00000) == 0x00500000) + return INSN_REJECTED; + else if ((insn & 0x00e00000) == 0x00000000) + return prep_emulate_rd16rs8rm0_wflags(insn, asi); + else if ((insn & 0x00a00000) == 0x00200000) + return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi); + else + return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, + asi); } /* cccc 000x xxxx xxxx xxxx xxxx xxxx 1xx1 xxxx */ @@ -1090,23 +1111,45 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi) /* SWP : cccc 0001 0000 xxxx xxxx xxxx 1001 xxxx */ /* SWPB : cccc 0001 0100 xxxx xxxx xxxx 1001 xxxx */ - /* LDRD : cccc 000x xxx0 xxxx xxxx xxxx 1101 xxxx */ - /* STRD : cccc 000x xxx0 xxxx xxxx xxxx 1111 xxxx */ + /* ??? : cccc 0001 0x01 xxxx xxxx xxxx 1001 xxxx */ + /* ??? : cccc 0001 0x10 xxxx xxxx xxxx 1001 xxxx */ + /* ??? : cccc 0001 0x11 xxxx xxxx xxxx 1001 xxxx */ /* STREX : cccc 0001 1000 xxxx xxxx xxxx 1001 xxxx */ /* LDREX : cccc 0001 1001 xxxx xxxx xxxx 1001 xxxx */ + /* STREXD: cccc 0001 1010 xxxx xxxx xxxx 1001 xxxx */ + /* LDREXD: cccc 0001 1011 xxxx xxxx xxxx 1001 xxxx */ + /* STREXB: cccc 0001 1100 xxxx xxxx xxxx 1001 xxxx */ + /* LDREXB: cccc 0001 1101 xxxx xxxx xxxx 1001 xxxx */ + /* STREXH: cccc 0001 1110 xxxx xxxx xxxx 1001 xxxx */ + /* LDREXH: cccc 0001 1111 xxxx xxxx xxxx 1001 xxxx */ + + /* LDRD : cccc 000x xxx0 xxxx xxxx xxxx 1101 xxxx */ + /* STRD : cccc 000x xxx0 xxxx xxxx xxxx 1111 xxxx */ /* LDRH : cccc 000x xxx1 xxxx xxxx xxxx 1011 xxxx */ /* STRH : cccc 000x xxx0 xxxx xxxx xxxx 1011 xxxx */ /* LDRSB : cccc 000x xxx1 xxxx xxxx xxxx 1101 xxxx */ /* LDRSH : cccc 000x xxx1 xxxx xxxx xxxx 1111 xxxx */ - if ((insn & 0x0fb000f0) == 0x01000090) { - /* SWP/SWPB */ - return prep_emulate_rd12rn16rm0_wflags(insn, asi); + if ((insn & 0x0f0000f0) == 0x01000090) { + if ((insn & 0x0fb000f0) == 0x01000090) { + /* SWP/SWPB */ + return prep_emulate_rd12rn16rm0_wflags(insn, + asi); + } else { + /* STREX/LDREX variants and unallocaed space */ + return INSN_REJECTED; + } + } else if ((insn & 0x0e1000d0) == 0x00000d0) { /* STRD/LDRD */ + if ((insn & 0x0000e000) == 0x0000e000) + return INSN_REJECTED; /* Rd is LR or PC */ + if (is_writeback(insn) && is_r15(insn, 16)) + return INSN_REJECTED; /* Writeback to PC */ + insn &= 0xfff00fff; insn |= 0x00002000; /* Rn = r0, Rd = r2 */ - if (insn & (1 << 22)) { - /* I bit */ + if (!(insn & (1 << 22))) { + /* Register index */ insn &= ~0xf; insn |= 1; /* Rm = r1 */ } @@ -1116,6 +1159,9 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi) return INSN_GOOD; } + /* LDRH/STRH/LDRSB/LDRSH */ + if (is_r15(insn, 12)) + return INSN_REJECTED; /* Rd is PC */ return prep_emulate_ldr_str(insn, asi); } @@ -1123,7 +1169,7 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi) /* * ALU op with S bit and Rd == 15 : - * cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx + * cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx */ if ((insn & 0x0e10f000) == 0x0010f000) return INSN_REJECTED; @@ -1152,22 +1198,61 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi) insn |= 0x00000200; /* Rs = r2 */ } asi->insn[0] = insn; - asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */ + + if ((insn & 0x0f900000) == 0x01100000) { + /* + * TST : cccc 0001 0001 xxxx xxxx xxxx xxxx xxxx + * TEQ : cccc 0001 0011 xxxx xxxx xxxx xxxx xxxx + * CMP : cccc 0001 0101 xxxx xxxx xxxx xxxx xxxx + * CMN : cccc 0001 0111 xxxx xxxx xxxx xxxx xxxx + */ + asi->insn_handler = emulate_alu_tests; + } else { + /* ALU ops which write to Rd */ + asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */ emulate_alu_rwflags : emulate_alu_rflags; + } return INSN_GOOD; } static enum kprobe_insn __kprobes space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi) { + /* MOVW : cccc 0011 0000 xxxx xxxx xxxx xxxx xxxx */ + /* MOVT : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx */ + if ((insn & 0x0fb00000) == 0x03000000) + return prep_emulate_rd12_modify(insn, asi); + + /* hints : cccc 0011 0010 0000 xxxx xxxx xxxx xxxx */ + if ((insn & 0x0fff0000) == 0x03200000) { + unsigned op2 = insn & 0x000000ff; + if (op2 == 0x01 || op2 == 0x04) { + /* YIELD : cccc 0011 0010 0000 xxxx xxxx 0000 0001 */ + /* SEV : cccc 0011 0010 0000 xxxx xxxx 0000 0100 */ + asi->insn[0] = insn; + asi->insn_handler = emulate_none; + return INSN_GOOD; + } else if (op2 <= 0x03) { + /* NOP : cccc 0011 0010 0000 xxxx xxxx 0000 0000 */ + /* WFE : cccc 0011 0010 0000 xxxx xxxx 0000 0010 */ + /* WFI : cccc 0011 0010 0000 xxxx xxxx 0000 0011 */ + /* + * We make WFE and WFI true NOPs to avoid stalls due + * to missing events whilst processing the probe. + */ + asi->insn_handler = emulate_nop; + return INSN_GOOD_NO_SLOT; + } + /* For DBG and unallocated hints it's safest to reject them */ + return INSN_REJECTED; + } + /* * MSR : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx - * Undef : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx * ALU op with S bit and Rd == 15 : * cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx */ if ((insn & 0x0fb00000) == 0x03200000 || /* MSR */ - (insn & 0x0ff00000) == 0x03400000 || /* Undef */ (insn & 0x0e10f000) == 0x0210f000) /* ALU s-bit, R15 */ return INSN_REJECTED; @@ -1178,10 +1263,22 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi) * *S (bit 20) updates condition codes * ADC/SBC/RSC reads the C flag */ - insn &= 0xffff0fff; /* Rd = r0 */ + insn &= 0xfff00fff; /* Rn = r0 and Rd = r0 */ asi->insn[0] = insn; - asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */ + + if ((insn & 0x0f900000) == 0x03100000) { + /* + * TST : cccc 0011 0001 xxxx xxxx xxxx xxxx xxxx + * TEQ : cccc 0011 0011 xxxx xxxx xxxx xxxx xxxx + * CMP : cccc 0011 0101 xxxx xxxx xxxx xxxx xxxx + * CMN : cccc 0011 0111 xxxx xxxx xxxx xxxx xxxx + */ + asi->insn_handler = emulate_alu_tests_imm; + } else { + /* ALU ops which write to Rd */ + asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */ emulate_alu_imm_rwflags : emulate_alu_imm_rflags; + } return INSN_GOOD; } @@ -1190,6 +1287,8 @@ space_cccc_0110__1(kprobe_opcode_t insn, struct arch_specific_insn *asi) { /* SEL : cccc 0110 1000 xxxx xxxx xxxx 1011 xxxx GE: !!! */ if ((insn & 0x0ff000f0) == 0x068000b0) { + if (is_r15(insn, 12)) + return INSN_REJECTED; /* Rd is PC */ insn &= 0xfff00ff0; /* Rd = r0, Rn = r0 */ insn |= 0x00000001; /* Rm = r1 */ asi->insn[0] = insn; @@ -1203,6 +1302,8 @@ space_cccc_0110__1(kprobe_opcode_t insn, struct arch_specific_insn *asi) /* USAT16 : cccc 0110 1110 xxxx xxxx xxxx 0011 xxxx :Q */ if ((insn & 0x0fa00030) == 0x06a00010 || (insn & 0x0fb000f0) == 0x06a00030) { + if (is_r15(insn, 12)) + return INSN_REJECTED; /* Rd is PC */ insn &= 0xffff0ff0; /* Rd = r0, Rm = r0 */ asi->insn[0] = insn; asi->insn_handler = emulate_sat; @@ -1211,57 +1312,101 @@ space_cccc_0110__1(kprobe_opcode_t insn, struct arch_specific_insn *asi) /* REV : cccc 0110 1011 xxxx xxxx xxxx 0011 xxxx */ /* REV16 : cccc 0110 1011 xxxx xxxx xxxx 1011 xxxx */ + /* RBIT : cccc 0110 1111 xxxx xxxx xxxx 0011 xxxx */ /* REVSH : cccc 0110 1111 xxxx xxxx xxxx 1011 xxxx */ if ((insn & 0x0ff00070) == 0x06b00030 || - (insn & 0x0ff000f0) == 0x06f000b0) + (insn & 0x0ff00070) == 0x06f00030) return prep_emulate_rd12rm0(insn, asi); + /* ??? : cccc 0110 0000 xxxx xxxx xxxx xxx1 xxxx : */ /* SADD16 : cccc 0110 0001 xxxx xxxx xxxx 0001 xxxx :GE */ /* SADDSUBX : cccc 0110 0001 xxxx xxxx xxxx 0011 xxxx :GE */ /* SSUBADDX : cccc 0110 0001 xxxx xxxx xxxx 0101 xxxx :GE */ /* SSUB16 : cccc 0110 0001 xxxx xxxx xxxx 0111 xxxx :GE */ /* SADD8 : cccc 0110 0001 xxxx xxxx xxxx 1001 xxxx :GE */ + /* ??? : cccc 0110 0001 xxxx xxxx xxxx 1011 xxxx : */ + /* ??? : cccc 0110 0001 xxxx xxxx xxxx 1101 xxxx : */ /* SSUB8 : cccc 0110 0001 xxxx xxxx xxxx 1111 xxxx :GE */ /* QADD16 : cccc 0110 0010 xxxx xxxx xxxx 0001 xxxx : */ /* QADDSUBX : cccc 0110 0010 xxxx xxxx xxxx 0011 xxxx : */ /* QSUBADDX : cccc 0110 0010 xxxx xxxx xxxx 0101 xxxx : */ /* QSUB16 : cccc 0110 0010 xxxx xxxx xxxx 0111 xxxx : */ /* QADD8 : cccc 0110 0010 xxxx xxxx xxxx 1001 xxxx : */ + /* ??? : cccc 0110 0010 xxxx xxxx xxxx 1011 xxxx : */ + /* ??? : cccc 0110 0010 xxxx xxxx xxxx 1101 xxxx : */ /* QSUB8 : cccc 0110 0010 xxxx xxxx xxxx 1111 xxxx : */ /* SHADD16 : cccc 0110 0011 xxxx xxxx xxxx 0001 xxxx : */ /* SHADDSUBX : cccc 0110 0011 xxxx xxxx xxxx 0011 xxxx : */ /* SHSUBADDX : cccc 0110 0011 xxxx xxxx xxxx 0101 xxxx : */ /* SHSUB16 : cccc 0110 0011 xxxx xxxx xxxx 0111 xxxx : */ /* SHADD8 : cccc 0110 0011 xxxx xxxx xxxx 1001 xxxx : */ + /* ??? : cccc 0110 0011 xxxx xxxx xxxx 1011 xxxx : */ + /* ??? : cccc 0110 0011 xxxx xxxx xxxx 1101 xxxx : */ /* SHSUB8 : cccc 0110 0011 xxxx xxxx xxxx 1111 xxxx : */ + /* ??? : cccc 0110 0100 xxxx xxxx xxxx xxx1 xxxx : */ /* UADD16 : cccc 0110 0101 xxxx xxxx xxxx 0001 xxxx :GE */ /* UADDSUBX : cccc 0110 0101 xxxx xxxx xxxx 0011 xxxx :GE */ /* USUBADDX : cccc 0110 0101 xxxx xxxx xxxx 0101 xxxx :GE */ /* USUB16 : cccc 0110 0101 xxxx xxxx xxxx 0111 xxxx :GE */ /* UADD8 : cccc 0110 0101 xxxx xxxx xxxx 1001 xxxx :GE */ + /* ??? : cccc 0110 0101 xxxx xxxx xxxx 1011 xxxx : */ + /* ??? : cccc 0110 0101 xxxx xxxx xxxx 1101 xxxx : */ /* USUB8 : cccc 0110 0101 xxxx xxxx xxxx 1111 xxxx :GE */ /* UQADD16 : cccc 0110 0110 xxxx xxxx xxxx 0001 xxxx : */ /* UQADDSUBX : cccc 0110 0110 xxxx xxxx xxxx 0011 xxxx : */ /* UQSUBADDX : cccc 0110 0110 xxxx xxxx xxxx 0101 xxxx : */ /* UQSUB16 : cccc 0110 0110 xxxx xxxx xxxx 0111 xxxx : */ /* UQADD8 : cccc 0110 0110 xxxx xxxx xxxx 1001 xxxx : */ + /* ??? : cccc 0110 0110 xxxx xxxx xxxx 1011 xxxx : */ + /* ??? : cccc 0110 0110 xxxx xxxx xxxx 1101 xxxx : */ /* UQSUB8 : cccc 0110 0110 xxxx xxxx xxxx 1111 xxxx : */ /* UHADD16 : cccc 0110 0111 xxxx xxxx xxxx 0001 xxxx : */ /* UHADDSUBX : cccc 0110 0111 xxxx xxxx xxxx 0011 xxxx : */ /* UHSUBADDX : cccc 0110 0111 xxxx xxxx xxxx 0101 xxxx : */ /* UHSUB16 : cccc 0110 0111 xxxx xxxx xxxx 0111 xxxx : */ /* UHADD8 : cccc 0110 0111 xxxx xxxx xxxx 1001 xxxx : */ + /* ??? : cccc 0110 0111 xxxx xxxx xxxx 1011 xxxx : */ + /* ??? : cccc 0110 0111 xxxx xxxx xxxx 1101 xxxx : */ /* UHSUB8 : cccc 0110 0111 xxxx xxxx xxxx 1111 xxxx : */ + if ((insn & 0x0f800010) == 0x06000010) { + if ((insn & 0x00300000) == 0x00000000 || + (insn & 0x000000e0) == 0x000000a0 || + (insn & 0x000000e0) == 0x000000c0) + return INSN_REJECTED; /* Unallocated space */ + return prep_emulate_rd12rn16rm0_wflags(insn, asi); + } + /* PKHBT : cccc 0110 1000 xxxx xxxx xxxx x001 xxxx : */ /* PKHTB : cccc 0110 1000 xxxx xxxx xxxx x101 xxxx : */ + if ((insn & 0x0ff00030) == 0x06800010) + return prep_emulate_rd12rn16rm0_wflags(insn, asi); + /* SXTAB16 : cccc 0110 1000 xxxx xxxx xxxx 0111 xxxx : */ - /* SXTB : cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx : */ + /* SXTB16 : cccc 0110 1000 1111 xxxx xxxx 0111 xxxx : */ + /* ??? : cccc 0110 1001 xxxx xxxx xxxx 0111 xxxx : */ /* SXTAB : cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx : */ + /* SXTB : cccc 0110 1010 1111 xxxx xxxx 0111 xxxx : */ /* SXTAH : cccc 0110 1011 xxxx xxxx xxxx 0111 xxxx : */ + /* SXTH : cccc 0110 1011 1111 xxxx xxxx 0111 xxxx : */ /* UXTAB16 : cccc 0110 1100 xxxx xxxx xxxx 0111 xxxx : */ + /* UXTB16 : cccc 0110 1100 1111 xxxx xxxx 0111 xxxx : */ + /* ??? : cccc 0110 1101 xxxx xxxx xxxx 0111 xxxx : */ /* UXTAB : cccc 0110 1110 xxxx xxxx xxxx 0111 xxxx : */ + /* UXTB : cccc 0110 1110 1111 xxxx xxxx 0111 xxxx : */ /* UXTAH : cccc 0110 1111 xxxx xxxx xxxx 0111 xxxx : */ - return prep_emulate_rd12rn16rm0_wflags(insn, asi); + /* UXTH : cccc 0110 1111 1111 xxxx xxxx 0111 xxxx : */ + if ((insn & 0x0f8000f0) == 0x06800070) { + if ((insn & 0x00300000) == 0x00100000) + return INSN_REJECTED; /* Unallocated space */ + + if ((insn & 0x000f0000) == 0x000f0000) + return prep_emulate_rd12rm0(insn, asi); + else + return prep_emulate_rd12rn16rm0_wflags(insn, asi); + } + + /* Other instruction encodings aren't yet defined */ + return INSN_REJECTED; } static enum kprobe_insn __kprobes @@ -1271,29 +1416,49 @@ space_cccc_0111__1(kprobe_opcode_t insn, struct arch_specific_insn *asi) if ((insn & 0x0ff000f0) == 0x03f000f0) return INSN_REJECTED; - /* USADA8 : cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx */ - /* USAD8 : cccc 0111 1000 xxxx 1111 xxxx 0001 xxxx */ - if ((insn & 0x0ff000f0) == 0x07800010) - return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi); - /* SMLALD : cccc 0111 0100 xxxx xxxx xxxx 00x1 xxxx */ /* SMLSLD : cccc 0111 0100 xxxx xxxx xxxx 01x1 xxxx */ if ((insn & 0x0ff00090) == 0x07400010) return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi); /* SMLAD : cccc 0111 0000 xxxx xxxx xxxx 00x1 xxxx :Q */ + /* SMUAD : cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx :Q */ /* SMLSD : cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx :Q */ + /* SMUSD : cccc 0111 0000 xxxx 1111 xxxx 01x1 xxxx : */ /* SMMLA : cccc 0111 0101 xxxx xxxx xxxx 00x1 xxxx : */ - /* SMMLS : cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx : */ + /* SMMUL : cccc 0111 0101 xxxx 1111 xxxx 00x1 xxxx : */ + /* USADA8 : cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx : */ + /* USAD8 : cccc 0111 1000 xxxx 1111 xxxx 0001 xxxx : */ if ((insn & 0x0ff00090) == 0x07000010 || (insn & 0x0ff000d0) == 0x07500010 || - (insn & 0x0ff000d0) == 0x075000d0) + (insn & 0x0ff000f0) == 0x07800010) { + + if ((insn & 0x0000f000) == 0x0000f000) + return prep_emulate_rd16rs8rm0_wflags(insn, asi); + else + return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi); + } + + /* SMMLS : cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx : */ + if ((insn & 0x0ff000d0) == 0x075000d0) return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi); - /* SMUSD : cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx : */ - /* SMUAD : cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx :Q */ - /* SMMUL : cccc 0111 0101 xxxx 1111 xxxx 00x1 xxxx : */ - return prep_emulate_rd16rs8rm0_wflags(insn, asi); + /* SBFX : cccc 0111 101x xxxx xxxx xxxx x101 xxxx : */ + /* UBFX : cccc 0111 111x xxxx xxxx xxxx x101 xxxx : */ + if ((insn & 0x0fa00070) == 0x07a00050) + return prep_emulate_rd12rm0(insn, asi); + + /* BFI : cccc 0111 110x xxxx xxxx xxxx x001 xxxx : */ + /* BFC : cccc 0111 110x xxxx xxxx xxxx x001 1111 : */ + if ((insn & 0x0fe00070) == 0x07c00010) { + + if ((insn & 0x0000000f) == 0x0000000f) + return prep_emulate_rd12_modify(insn, asi); + else + return prep_emulate_rd12rn0_modify(insn, asi); + } + + return INSN_REJECTED; } static enum kprobe_insn __kprobes @@ -1307,6 +1472,10 @@ space_cccc_01xx(kprobe_opcode_t insn, struct arch_specific_insn *asi) /* STRB : cccc 01xx x1x0 xxxx xxxx xxxx xxxx xxxx */ /* STRBT : cccc 01x0 x110 xxxx xxxx xxxx xxxx xxxx */ /* STRT : cccc 01x0 x010 xxxx xxxx xxxx xxxx xxxx */ + + if ((insn & 0x00500000) == 0x00500000 && is_r15(insn, 12)) + return INSN_REJECTED; /* LDRB into PC */ + return prep_emulate_ldr_str(insn, asi); } @@ -1321,10 +1490,9 @@ space_cccc_100x(kprobe_opcode_t insn, struct arch_specific_insn *asi) /* LDM(1) : cccc 100x x0x1 xxxx xxxx xxxx xxxx xxxx */ /* STM(1) : cccc 100x x0x0 xxxx xxxx xxxx xxxx xxxx */ - asi->insn[0] = truecc_insn(insn); asi->insn_handler = ((insn & 0x108000) == 0x008000) ? /* STM & R15 */ simulate_stm1_pc : simulate_ldm1stm1; - return INSN_GOOD; + return INSN_GOOD_NO_SLOT; } static enum kprobe_insn __kprobes @@ -1332,58 +1500,117 @@ space_cccc_101x(kprobe_opcode_t insn, struct arch_specific_insn *asi) { /* B : cccc 1010 xxxx xxxx xxxx xxxx xxxx xxxx */ /* BL : cccc 1011 xxxx xxxx xxxx xxxx xxxx xxxx */ - asi->insn[0] = truecc_insn(insn); asi->insn_handler = simulate_bbl; - return INSN_GOOD; + return INSN_GOOD_NO_SLOT; } static enum kprobe_insn __kprobes -space_cccc_1100_010x(kprobe_opcode_t insn, struct arch_specific_insn *asi) +space_cccc_11xx(kprobe_opcode_t insn, struct arch_specific_insn *asi) { + /* Coprocessor instructions... */ /* MCRR : cccc 1100 0100 xxxx xxxx xxxx xxxx xxxx : (Rd!=Rn) */ /* MRRC : cccc 1100 0101 xxxx xxxx xxxx xxxx xxxx : (Rd!=Rn) */ - insn &= 0xfff00fff; - insn |= 0x00001000; /* Rn = r0, Rd = r1 */ - asi->insn[0] = insn; - asi->insn_handler = (insn & (1 << 20)) ? emulate_mrrc : emulate_mcrr; - return INSN_GOOD; + /* LDC : cccc 110x xxx1 xxxx xxxx xxxx xxxx xxxx */ + /* STC : cccc 110x xxx0 xxxx xxxx xxxx xxxx xxxx */ + /* CDP : cccc 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */ + /* MCR : cccc 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */ + /* MRC : cccc 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */ + + /* SVC : cccc 1111 xxxx xxxx xxxx xxxx xxxx xxxx */ + + return INSN_REJECTED; } -static enum kprobe_insn __kprobes -space_cccc_110x(kprobe_opcode_t insn, struct arch_specific_insn *asi) +static unsigned long __kprobes __check_eq(unsigned long cpsr) { - /* LDC : cccc 110x xxx1 xxxx xxxx xxxx xxxx xxxx */ - /* STC : cccc 110x xxx0 xxxx xxxx xxxx xxxx xxxx */ - insn &= 0xfff0ffff; /* Rn = r0 */ - asi->insn[0] = insn; - asi->insn_handler = emulate_ldcstc; - return INSN_GOOD; + return cpsr & PSR_Z_BIT; } -static enum kprobe_insn __kprobes -space_cccc_111x(kprobe_opcode_t insn, struct arch_specific_insn *asi) +static unsigned long __kprobes __check_ne(unsigned long cpsr) { - /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */ - /* SWI : cccc 1111 xxxx xxxx xxxx xxxx xxxx xxxx */ - if ((insn & 0xfff000f0) == 0xe1200070 || - (insn & 0x0f000000) == 0x0f000000) - return INSN_REJECTED; + return (~cpsr) & PSR_Z_BIT; +} - /* CDP : cccc 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */ - if ((insn & 0x0f000010) == 0x0e000000) { - asi->insn[0] = insn; - asi->insn_handler = emulate_none; - return INSN_GOOD; - } +static unsigned long __kprobes __check_cs(unsigned long cpsr) +{ + return cpsr & PSR_C_BIT; +} - /* MCR : cccc 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */ - /* MRC : cccc 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */ - insn &= 0xffff0fff; /* Rd = r0 */ - asi->insn[0] = insn; - asi->insn_handler = (insn & (1 << 20)) ? emulate_rd12 : emulate_ird12; - return INSN_GOOD; +static unsigned long __kprobes __check_cc(unsigned long cpsr) +{ + return (~cpsr) & PSR_C_BIT; } +static unsigned long __kprobes __check_mi(unsigned long cpsr) +{ + return cpsr & PSR_N_BIT; +} + +static unsigned long __kprobes __check_pl(unsigned long cpsr) +{ + return (~cpsr) & PSR_N_BIT; +} + +static unsigned long __kprobes __check_vs(unsigned long cpsr) +{ + return cpsr & PSR_V_BIT; +} + +static unsigned long __kprobes __check_vc(unsigned long cpsr) +{ + return (~cpsr) & PSR_V_BIT; +} + +static unsigned long __kprobes __check_hi(unsigned long cpsr) +{ + cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ + return cpsr & PSR_C_BIT; +} + +static unsigned long __kprobes __check_ls(unsigned long cpsr) +{ + cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ + return (~cpsr) & PSR_C_BIT; +} + +static unsigned long __kprobes __check_ge(unsigned long cpsr) +{ + cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ + return (~cpsr) & PSR_N_BIT; +} + +static unsigned long __kprobes __check_lt(unsigned long cpsr) +{ + cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ + return cpsr & PSR_N_BIT; +} + +static unsigned long __kprobes __check_gt(unsigned long cpsr) +{ + unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ + temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */ + return (~temp) & PSR_N_BIT; +} + +static unsigned long __kprobes __check_le(unsigned long cpsr) +{ + unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ + temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */ + return temp & PSR_N_BIT; +} + +static unsigned long __kprobes __check_al(unsigned long cpsr) +{ + return true; +} + +static kprobe_check_cc * const condition_checks[16] = { + &__check_eq, &__check_ne, &__check_cs, &__check_cc, + &__check_mi, &__check_pl, &__check_vs, &__check_vc, + &__check_hi, &__check_ls, &__check_ge, &__check_lt, + &__check_gt, &__check_le, &__check_al, &__check_al +}; + /* Return: * INSN_REJECTED If instruction is one not allowed to kprobe, * INSN_GOOD If instruction is supported and uses instruction slot, @@ -1399,133 +1626,45 @@ space_cccc_111x(kprobe_opcode_t insn, struct arch_specific_insn *asi) enum kprobe_insn __kprobes arm_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi) { + asi->insn_check_cc = condition_checks[insn>>28]; asi->insn[1] = KPROBE_RETURN_INSTRUCTION; - if ((insn & 0xf0000000) == 0xf0000000) { + if ((insn & 0xf0000000) == 0xf0000000) return space_1111(insn, asi); - } else if ((insn & 0x0e000000) == 0x00000000) { + else if ((insn & 0x0e000000) == 0x00000000) return space_cccc_000x(insn, asi); - } else if ((insn & 0x0e000000) == 0x02000000) { + else if ((insn & 0x0e000000) == 0x02000000) return space_cccc_001x(insn, asi); - } else if ((insn & 0x0f000010) == 0x06000010) { + else if ((insn & 0x0f000010) == 0x06000010) return space_cccc_0110__1(insn, asi); - } else if ((insn & 0x0f000010) == 0x07000010) { + else if ((insn & 0x0f000010) == 0x07000010) return space_cccc_0111__1(insn, asi); - } else if ((insn & 0x0c000000) == 0x04000000) { + else if ((insn & 0x0c000000) == 0x04000000) return space_cccc_01xx(insn, asi); - } else if ((insn & 0x0e000000) == 0x08000000) { + else if ((insn & 0x0e000000) == 0x08000000) return space_cccc_100x(insn, asi); - } else if ((insn & 0x0e000000) == 0x0a000000) { + else if ((insn & 0x0e000000) == 0x0a000000) return space_cccc_101x(insn, asi); - } else if ((insn & 0x0fe00000) == 0x0c400000) { - - return space_cccc_1100_010x(insn, asi); - - } else if ((insn & 0x0e000000) == 0x0c000000) { - - return space_cccc_110x(insn, asi); - - } - - return space_cccc_111x(insn, asi); + return space_cccc_11xx(insn, asi); } void __init arm_kprobe_decode_init(void) { find_str_pc_offset(); } - - -/* - * All ARM instructions listed below. - * - * Instructions and their general purpose registers are given. - * If a particular register may not use R15, it is prefixed with a "!". - * If marked with a "*" means the value returned by reading R15 - * is implementation defined. - * - * ADC/ADD/AND/BIC/CMN/CMP/EOR/MOV/MVN/ORR/RSB/RSC/SBC/SUB/TEQ - * TST: Rd, Rn, Rm, !Rs - * BX: Rm - * BLX(2): !Rm - * BX: Rm (R15 legal, but discouraged) - * BXJ: !Rm, - * CLZ: !Rd, !Rm - * CPY: Rd, Rm - * LDC/2,STC/2 immediate offset & unindex: Rn - * LDC/2,STC/2 immediate pre/post-indexed: !Rn - * LDM(1/3): !Rn, register_list - * LDM(2): !Rn, !register_list - * LDR,STR,PLD immediate offset: Rd, Rn - * LDR,STR,PLD register offset: Rd, Rn, !Rm - * LDR,STR,PLD scaled register offset: Rd, !Rn, !Rm - * LDR,STR immediate pre/post-indexed: Rd, !Rn - * LDR,STR register pre/post-indexed: Rd, !Rn, !Rm - * LDR,STR scaled register pre/post-indexed: Rd, !Rn, !Rm - * LDRB,STRB immediate offset: !Rd, Rn - * LDRB,STRB register offset: !Rd, Rn, !Rm - * LDRB,STRB scaled register offset: !Rd, !Rn, !Rm - * LDRB,STRB immediate pre/post-indexed: !Rd, !Rn - * LDRB,STRB register pre/post-indexed: !Rd, !Rn, !Rm - * LDRB,STRB scaled register pre/post-indexed: !Rd, !Rn, !Rm - * LDRT,LDRBT,STRBT immediate pre/post-indexed: !Rd, !Rn - * LDRT,LDRBT,STRBT register pre/post-indexed: !Rd, !Rn, !Rm - * LDRT,LDRBT,STRBT scaled register pre/post-indexed: !Rd, !Rn, !Rm - * LDRH/SH/SB/D,STRH/SH/SB/D immediate offset: !Rd, Rn - * LDRH/SH/SB/D,STRH/SH/SB/D register offset: !Rd, Rn, !Rm - * LDRH/SH/SB/D,STRH/SH/SB/D immediate pre/post-indexed: !Rd, !Rn - * LDRH/SH/SB/D,STRH/SH/SB/D register pre/post-indexed: !Rd, !Rn, !Rm - * LDREX: !Rd, !Rn - * MCR/2: !Rd - * MCRR/2,MRRC/2: !Rd, !Rn - * MLA: !Rd, !Rn, !Rm, !Rs - * MOV: Rd - * MRC/2: !Rd (if Rd==15, only changes cond codes, not the register) - * MRS,MSR: !Rd - * MUL: !Rd, !Rm, !Rs - * PKH{BT,TB}: !Rd, !Rn, !Rm - * QDADD,[U]QADD/16/8/SUBX: !Rd, !Rm, !Rn - * QDSUB,[U]QSUB/16/8/ADDX: !Rd, !Rm, !Rn - * REV/16/SH: !Rd, !Rm - * RFE: !Rn - * {S,U}[H]ADD{16,8,SUBX},{S,U}[H]SUB{16,8,ADDX}: !Rd, !Rn, !Rm - * SEL: !Rd, !Rn, !Rm - * SMLA<x><y>,SMLA{D,W<y>},SMLSD,SMML{A,S}: !Rd, !Rn, !Rm, !Rs - * SMLAL<x><y>,SMLA{D,LD},SMLSLD,SMMULL,SMULW<y>: !RdHi, !RdLo, !Rm, !Rs - * SMMUL,SMUAD,SMUL<x><y>,SMUSD: !Rd, !Rm, !Rs - * SSAT/16: !Rd, !Rm - * STM(1/2): !Rn, register_list* (R15 in reg list not recommended) - * STRT immediate pre/post-indexed: Rd*, !Rn - * STRT register pre/post-indexed: Rd*, !Rn, !Rm - * STRT scaled register pre/post-indexed: Rd*, !Rn, !Rm - * STREX: !Rd, !Rn, !Rm - * SWP/B: !Rd, !Rn, !Rm - * {S,U}XTA{B,B16,H}: !Rd, !Rn, !Rm - * {S,U}XT{B,B16,H}: !Rd, !Rm - * UM{AA,LA,UL}L: !RdHi, !RdLo, !Rm, !Rs - * USA{D8,A8,T,T16}: !Rd, !Rm, !Rs - * - * May transfer control by writing R15 (possible mode changes or alternate - * mode accesses marked by "*"): - * ALU op (* with s-bit), B, BL, BKPT, BLX(1/2), BX, BXJ, CPS*, CPY, - * LDM(1), LDM(2/3)*, LDR, MOV, RFE*, SWI* - * - * Instructions that do not take general registers, nor transfer control: - * CDP/2, SETEND, SRS* - */ diff --git a/arch/arm/kernel/kprobes.c b/arch/arm/kernel/kprobes.c index 2ba7deb3072..1656c87501c 100644 --- a/arch/arm/kernel/kprobes.c +++ b/arch/arm/kernel/kprobes.c @@ -134,7 +134,8 @@ static void __kprobes singlestep(struct kprobe *p, struct pt_regs *regs, struct kprobe_ctlblk *kcb) { regs->ARM_pc += 4; - p->ainsn.insn_handler(p, regs); + if (p->ainsn.insn_check_cc(regs->ARM_cpsr)) + p->ainsn.insn_handler(p, regs); } /* diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index 22e194eb853..139e3c82736 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -79,6 +79,7 @@ struct arm_pmu { void (*write_counter)(int idx, u32 val); void (*start)(void); void (*stop)(void); + void (*reset)(void *); const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX]; @@ -204,11 +205,9 @@ armpmu_event_set_period(struct perf_event *event, static u64 armpmu_event_update(struct perf_event *event, struct hw_perf_event *hwc, - int idx) + int idx, int overflow) { - int shift = 64 - 32; - s64 prev_raw_count, new_raw_count; - u64 delta; + u64 delta, prev_raw_count, new_raw_count; again: prev_raw_count = local64_read(&hwc->prev_count); @@ -218,8 +217,13 @@ again: new_raw_count) != prev_raw_count) goto again; - delta = (new_raw_count << shift) - (prev_raw_count << shift); - delta >>= shift; + new_raw_count &= armpmu->max_period; + prev_raw_count &= armpmu->max_period; + + if (overflow) + delta = armpmu->max_period - prev_raw_count + new_raw_count + 1; + else + delta = new_raw_count - prev_raw_count; local64_add(delta, &event->count); local64_sub(delta, &hwc->period_left); @@ -236,7 +240,7 @@ armpmu_read(struct perf_event *event) if (hwc->idx < 0) return; - armpmu_event_update(event, hwc, hwc->idx); + armpmu_event_update(event, hwc, hwc->idx, 0); } static void @@ -254,7 +258,7 @@ armpmu_stop(struct perf_event *event, int flags) if (!(hwc->state & PERF_HES_STOPPED)) { armpmu->disable(hwc, hwc->idx); barrier(); /* why? */ - armpmu_event_update(event, hwc, hwc->idx); + armpmu_event_update(event, hwc, hwc->idx, 0); hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; } } @@ -624,6 +628,19 @@ static struct pmu pmu = { #include "perf_event_v6.c" #include "perf_event_v7.c" +/* + * Ensure the PMU has sane values out of reset. + * This requires SMP to be available, so exists as a separate initcall. + */ +static int __init +armpmu_reset(void) +{ + if (armpmu && armpmu->reset) + return on_each_cpu(armpmu->reset, NULL, 1); + return 0; +} +arch_initcall(armpmu_reset); + static int __init init_hw_perf_events(void) { @@ -729,7 +746,8 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) tail = (struct frame_tail __user *)regs->ARM_fp - 1; - while (tail && !((unsigned long)tail & 0x3)) + while ((entry->nr < PERF_MAX_STACK_DEPTH) && + tail && !((unsigned long)tail & 0x3)) tail = user_backtrace(tail, entry); } diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c index 6fc2d228db5..f1e8dd94afe 100644 --- a/arch/arm/kernel/perf_event_v6.c +++ b/arch/arm/kernel/perf_event_v6.c @@ -474,7 +474,7 @@ armv6pmu_handle_irq(int irq_num, continue; hwc = &event->hw; - armpmu_event_update(event, hwc, idx); + armpmu_event_update(event, hwc, idx, 1); data.period = event->hw.last_period; if (!armpmu_event_set_period(event, hwc, idx)) continue; diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index 2e1402556fa..4960686afb5 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c @@ -466,6 +466,7 @@ static inline unsigned long armv7_pmnc_read(void) static inline void armv7_pmnc_write(unsigned long val) { val &= ARMV7_PMNC_MASK; + isb(); asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); } @@ -502,6 +503,7 @@ static inline int armv7_pmnc_select_counter(unsigned int idx) val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK; asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val)); + isb(); return idx; } @@ -780,7 +782,7 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev) continue; hwc = &event->hw; - armpmu_event_update(event, hwc, idx); + armpmu_event_update(event, hwc, idx, 1); data.period = event->hw.last_period; if (!armpmu_event_set_period(event, hwc, idx)) continue; @@ -847,6 +849,18 @@ static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc, } } +static void armv7pmu_reset(void *info) +{ + u32 idx, nb_cnt = armpmu->num_events; + + /* The counter and interrupt enable registers are unknown at reset. */ + for (idx = 1; idx < nb_cnt; ++idx) + armv7pmu_disable_event(NULL, idx); + + /* Initialize & Reset PMNC: C and P bits */ + armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C); +} + static struct arm_pmu armv7pmu = { .handle_irq = armv7pmu_handle_irq, .enable = armv7pmu_enable_event, @@ -856,17 +870,15 @@ static struct arm_pmu armv7pmu = { .get_event_idx = armv7pmu_get_event_idx, .start = armv7pmu_start, .stop = armv7pmu_stop, + .reset = armv7pmu_reset, .raw_event_mask = 0xFF, .max_period = (1LLU << 32) - 1, }; -static u32 __init armv7_reset_read_pmnc(void) +static u32 __init armv7_read_num_pmnc_events(void) { u32 nb_cnt; - /* Initialize & Reset PMNC: C and P bits */ - armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C); - /* Read the nb of CNTx counters supported from PMNC */ nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK; @@ -880,7 +892,7 @@ static const struct arm_pmu *__init armv7_a8_pmu_init(void) armv7pmu.name = "ARMv7 Cortex-A8"; armv7pmu.cache_map = &armv7_a8_perf_cache_map; armv7pmu.event_map = &armv7_a8_perf_map; - armv7pmu.num_events = armv7_reset_read_pmnc(); + armv7pmu.num_events = armv7_read_num_pmnc_events(); return &armv7pmu; } @@ -890,7 +902,7 @@ static const struct arm_pmu *__init armv7_a9_pmu_init(void) armv7pmu.name = "ARMv7 Cortex-A9"; armv7pmu.cache_map = &armv7_a9_perf_cache_map; armv7pmu.event_map = &armv7_a9_perf_map; - armv7pmu.num_events = armv7_reset_read_pmnc(); + armv7pmu.num_events = armv7_read_num_pmnc_events(); return &armv7pmu; } #else diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c index 28cd3b025bc..39affbe4fdb 100644 --- a/arch/arm/kernel/perf_event_xscale.c +++ b/arch/arm/kernel/perf_event_xscale.c @@ -246,7 +246,7 @@ xscale1pmu_handle_irq(int irq_num, void *dev) continue; hwc = &event->hw; - armpmu_event_update(event, hwc, idx); + armpmu_event_update(event, hwc, idx, 1); data.period = event->hw.last_period; if (!armpmu_event_set_period(event, hwc, idx)) continue; @@ -578,7 +578,7 @@ xscale2pmu_handle_irq(int irq_num, void *dev) continue; hwc = &event->hw; - armpmu_event_update(event, hwc, idx); + armpmu_event_update(event, hwc, idx, 1); data.period = event->hw.last_period; if (!armpmu_event_set_period(event, hwc, idx)) continue; diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 94bbedbed63..5e1e5419722 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -372,6 +372,8 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start, if (clone_flags & CLONE_SETTLS) thread->tp_value = regs->ARM_r3; + thread_notify(THREAD_NOTIFY_COPY, thread); + return 0; } diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index 2bf27f364d0..8182f45ca49 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -767,12 +767,20 @@ long arch_ptrace(struct task_struct *child, long request, #ifdef CONFIG_HAVE_HW_BREAKPOINT case PTRACE_GETHBPREGS: + if (ptrace_get_breakpoints(child) < 0) + return -ESRCH; + ret = ptrace_gethbpregs(child, addr, (unsigned long __user *)data); + ptrace_put_breakpoints(child); break; case PTRACE_SETHBPREGS: + if (ptrace_get_breakpoints(child) < 0) + return -ESRCH; + ret = ptrace_sethbpregs(child, addr, (unsigned long __user *)data); + ptrace_put_breakpoints(child); break; #endif diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index d1da9217427..006c1e884ea 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -466,13 +466,13 @@ static struct machine_desc * __init setup_machine(unsigned int nr) /* can't use cpu_relax() here as it may require MMU setup */; } -static int __init arm_add_memory(unsigned long start, unsigned long size) +static int __init arm_add_memory(phys_addr_t start, unsigned long size) { struct membank *bank = &meminfo.bank[meminfo.nr_banks]; if (meminfo.nr_banks >= NR_BANKS) { printk(KERN_CRIT "NR_BANKS too low, " - "ignoring memory at %#lx\n", start); + "ignoring memory at 0x%08llx\n", (long long)start); return -EINVAL; } @@ -502,7 +502,8 @@ static int __init arm_add_memory(unsigned long start, unsigned long size) static int __init early_mem(char *p) { static int usermem __initdata = 0; - unsigned long size, start; + unsigned long size; + phys_addr_t start; char *endp; /* @@ -788,30 +789,6 @@ static void __init reserve_crashkernel(void) static inline void reserve_crashkernel(void) {} #endif /* CONFIG_KEXEC */ -/* - * Note: elfcorehdr_addr is not just limited to vmcore. It is also used by - * is_kdump_kernel() to determine if we are booting after a panic. Hence - * ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE. - */ - -#ifdef CONFIG_CRASH_DUMP -/* - * elfcorehdr= specifies the location of elf core header stored by the crashed - * kernel. This option will be passed by kexec loader to the capture kernel. - */ -static int __init setup_elfcorehdr(char *arg) -{ - char *end; - - if (!arg) - return -EINVAL; - - elfcorehdr_addr = memparse(arg, &end); - return end > arg ? 0 : -EINVAL; -} -early_param("elfcorehdr", setup_elfcorehdr); -#endif /* CONFIG_CRASH_DUMP */ - static void __init squash_mem_tags(struct tag *tag) { for (; tag->hdr.size; tag = tag_next(tag)) diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index cb839831764..0340224cf73 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -597,19 +597,13 @@ setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info, return err; } -static inline void setup_syscall_restart(struct pt_regs *regs) -{ - regs->ARM_r0 = regs->ARM_ORIG_r0; - regs->ARM_pc -= thumb_mode(regs) ? 2 : 4; -} - /* * OK, we're invoking a handler */ static int handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info, sigset_t *oldset, - struct pt_regs * regs, int syscall) + struct pt_regs * regs) { struct thread_info *thread = current_thread_info(); struct task_struct *tsk = current; @@ -617,26 +611,6 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, int ret; /* - * If we were from a system call, check for system call restarting... - */ - if (syscall) { - switch (regs->ARM_r0) { - case -ERESTART_RESTARTBLOCK: - case -ERESTARTNOHAND: - regs->ARM_r0 = -EINTR; - break; - case -ERESTARTSYS: - if (!(ka->sa.sa_flags & SA_RESTART)) { - regs->ARM_r0 = -EINTR; - break; - } - /* fallthrough */ - case -ERESTARTNOINTR: - setup_syscall_restart(regs); - } - } - - /* * translate the signal */ if (usig < 32 && thread->exec_domain && thread->exec_domain->signal_invmap) @@ -685,6 +659,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, */ static void do_signal(struct pt_regs *regs, int syscall) { + unsigned int retval = 0, continue_addr = 0, restart_addr = 0; struct k_sigaction ka; siginfo_t info; int signr; @@ -698,18 +673,61 @@ static void do_signal(struct pt_regs *regs, int syscall) if (!user_mode(regs)) return; + /* + * If we were from a system call, check for system call restarting... + */ + if (syscall) { + continue_addr = regs->ARM_pc; + restart_addr = continue_addr - (thumb_mode(regs) ? 2 : 4); + retval = regs->ARM_r0; + + /* + * Prepare for system call restart. We do this here so that a + * debugger will see the already changed PSW. + */ + switch (retval) { + case -ERESTARTNOHAND: + case -ERESTARTSYS: + case -ERESTARTNOINTR: + regs->ARM_r0 = regs->ARM_ORIG_r0; + regs->ARM_pc = restart_addr; + break; + case -ERESTART_RESTARTBLOCK: + regs->ARM_r0 = -EINTR; + break; + } + } + if (try_to_freeze()) goto no_signal; + /* + * Get the signal to deliver. When running under ptrace, at this + * point the debugger may change all our registers ... + */ signr = get_signal_to_deliver(&info, &ka, regs, NULL); if (signr > 0) { sigset_t *oldset; + /* + * Depending on the signal settings we may need to revert the + * decision to restart the system call. But skip this if a + * debugger has chosen to restart at a different PC. + */ + if (regs->ARM_pc == restart_addr) { + if (retval == -ERESTARTNOHAND + || (retval == -ERESTARTSYS + && !(ka.sa.sa_flags & SA_RESTART))) { + regs->ARM_r0 = -EINTR; + regs->ARM_pc = continue_addr; + } + } + if (test_thread_flag(TIF_RESTORE_SIGMASK)) oldset = ¤t->saved_sigmask; else oldset = ¤t->blocked; - if (handle_signal(signr, &ka, &info, oldset, regs, syscall) == 0) { + if (handle_signal(signr, &ka, &info, oldset, regs) == 0) { /* * A signal was successfully delivered; the saved * sigmask will have been stored in the signal frame, @@ -723,11 +741,14 @@ static void do_signal(struct pt_regs *regs, int syscall) } no_signal: - /* - * No signal to deliver to the process - restart the syscall. - */ if (syscall) { - if (regs->ARM_r0 == -ERESTART_RESTARTBLOCK) { + /* + * Handle restarting a different system call. As above, + * if a debugger has chosen to restart at a different PC, + * ignore the restart. + */ + if (retval == -ERESTART_RESTARTBLOCK + && regs->ARM_pc == continue_addr) { if (thumb_mode(regs)) { regs->ARM_r7 = __NR_restart_syscall - __NR_SYSCALL_BASE; regs->ARM_pc -= 2; @@ -750,11 +771,6 @@ static void do_signal(struct pt_regs *regs, int syscall) #endif } } - if (regs->ARM_r0 == -ERESTARTNOHAND || - regs->ARM_r0 == -ERESTARTSYS || - regs->ARM_r0 == -ERESTARTNOINTR) { - setup_syscall_restart(regs); - } /* If there's no signal to deliver, we just put the saved sigmask * back. diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S index bfad698a02e..6398ead9d1c 100644 --- a/arch/arm/kernel/sleep.S +++ b/arch/arm/kernel/sleep.S @@ -119,11 +119,19 @@ ENTRY(cpu_resume) #else ldr r0, sleep_save_sp @ stack phys addr #endif - msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off + setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off #ifdef MULTI_CPU - ldmia r0!, {r1, sp, lr, pc} @ load v:p, stack, return fn, resume fn + @ load v:p, stack, return fn, resume fn + ARM( ldmia r0!, {r1, sp, lr, pc} ) +THUMB( ldmia r0!, {r1, r2, r3, r4} ) +THUMB( mov sp, r2 ) +THUMB( mov lr, r3 ) +THUMB( bx r4 ) #else - ldmia r0!, {r1, sp, lr} @ load v:p, stack, return fn + @ load v:p, stack, return fn + ARM( ldmia r0!, {r1, sp, lr} ) +THUMB( ldmia r0!, {r1, r2, lr} ) +THUMB( mov sp, r2 ) b cpu_do_resume #endif ENDPROC(cpu_resume) diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 4539ebcb089..f29b8a29b17 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -474,13 +474,12 @@ static void smp_timer_broadcast(const struct cpumask *mask) #define smp_timer_broadcast NULL #endif -#ifndef CONFIG_LOCAL_TIMERS static void broadcast_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { } -static void local_timer_setup(struct clock_event_device *evt) +static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt) { evt->name = "dummy_timer"; evt->features = CLOCK_EVT_FEAT_ONESHOT | @@ -492,7 +491,6 @@ static void local_timer_setup(struct clock_event_device *evt) clockevents_register_device(evt); } -#endif void __cpuinit percpu_timer_setup(void) { @@ -502,7 +500,8 @@ void __cpuinit percpu_timer_setup(void) evt->cpumask = cpumask_of(cpu); evt->broadcast = smp_timer_broadcast; - local_timer_setup(evt); + if (local_timer_setup(evt)) + broadcast_timer_setup(evt); } #ifdef CONFIG_HOTPLUG_CPU diff --git a/arch/arm/kernel/swp_emulate.c b/arch/arm/kernel/swp_emulate.c index 7a576092291..40ee7e5045e 100644 --- a/arch/arm/kernel/swp_emulate.c +++ b/arch/arm/kernel/swp_emulate.c @@ -158,7 +158,7 @@ static int emulate_swpX(unsigned int address, unsigned int *data, if (res == 0) { /* - * Barrier also required between aquiring a lock for a + * Barrier also required between acquiring a lock for a * protected resource and accessing the resource. Inserted for * same reason as above. */ diff --git a/arch/arm/kernel/sys_oabi-compat.c b/arch/arm/kernel/sys_oabi-compat.c index 4ad8da15ef2..af0aaebf4de 100644 --- a/arch/arm/kernel/sys_oabi-compat.c +++ b/arch/arm/kernel/sys_oabi-compat.c @@ -311,7 +311,7 @@ asmlinkage long sys_oabi_semtimedop(int semid, long err; int i; - if (nsops < 1) + if (nsops < 1 || nsops > SEMOPM) return -EINVAL; sops = kmalloc(sizeof(*sops) * nsops, GFP_KERNEL); if (!sops) diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 21ac43f1c2d..3b54ad19d48 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -410,8 +410,7 @@ static int bad_syscall(int n, struct pt_regs *regs) struct thread_info *thread = current_thread_info(); siginfo_t info; - if (current->personality != PER_LINUX && - current->personality != PER_LINUX_32BIT && + if ((current->personality & PER_MASK) != PER_LINUX && thread->exec_domain->handler) { thread->exec_domain->handler(n, regs); return regs->ARM_r0; @@ -712,17 +711,17 @@ EXPORT_SYMBOL(__readwrite_bug); void __pte_error(const char *file, int line, pte_t pte) { - printk("%s:%d: bad pte %08lx.\n", file, line, pte_val(pte)); + printk("%s:%d: bad pte %08llx.\n", file, line, (long long)pte_val(pte)); } void __pmd_error(const char *file, int line, pmd_t pmd) { - printk("%s:%d: bad pmd %08lx.\n", file, line, pmd_val(pmd)); + printk("%s:%d: bad pmd %08llx.\n", file, line, (long long)pmd_val(pmd)); } void __pgd_error(const char *file, int line, pgd_t pgd) { - printk("%s:%d: bad pgd %08lx.\n", file, line, pgd_val(pgd)); + printk("%s:%d: bad pgd %08llx.\n", file, line, (long long)pgd_val(pgd)); } asmlinkage void __div0(void) diff --git a/arch/arm/lib/uaccess_with_memcpy.c b/arch/arm/lib/uaccess_with_memcpy.c index e2d2f2cd0c4..8b9b13649f8 100644 --- a/arch/arm/lib/uaccess_with_memcpy.c +++ b/arch/arm/lib/uaccess_with_memcpy.c @@ -27,13 +27,18 @@ pin_page_for_write(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp) pgd_t *pgd; pmd_t *pmd; pte_t *pte; + pud_t *pud; spinlock_t *ptl; pgd = pgd_offset(current->mm, addr); if (unlikely(pgd_none(*pgd) || pgd_bad(*pgd))) return 0; - pmd = pmd_offset(pgd, addr); + pud = pud_offset(pgd, addr); + if (unlikely(pud_none(*pud) || pud_bad(*pud))) + return 0; + + pmd = pmd_offset(pud, addr); if (unlikely(pmd_none(*pmd) || pmd_bad(*pmd))) return 0; diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 19390231a0e..2d299bf5d72 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -83,6 +83,7 @@ config ARCH_AT91CAP9 select CPU_ARM926T select GENERIC_CLOCKEVENTS select HAVE_FB_ATMEL + select HAVE_NET_MACB config ARCH_AT572D940HF bool "AT572D940HF" diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c index d1f775e8635..9ffbf3a2dfe 100644 --- a/arch/arm/mach-at91/at91cap9_devices.c +++ b/arch/arm/mach-at91/at91cap9_devices.c @@ -72,7 +72,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) return; if (cpu_is_at91cap9_revB()) - set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH); + irq_set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH); /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { @@ -157,7 +157,7 @@ static struct platform_device at91_usba_udc_device = { void __init at91_add_device_usba(struct usba_platform_data *data) { if (cpu_is_at91cap9_revB()) { - set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH); + irq_set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH); at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS | AT91_MATRIX_UDPHS_BYPASS_LOCK); } @@ -861,7 +861,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) return; if (cpu_is_at91cap9_revB()) - set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH); + irq_set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH); at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c index 2e74a19874d..295e1e77fa6 100644 --- a/arch/arm/mach-at91/board-carmeva.c +++ b/arch/arm/mach-at91/board-carmeva.c @@ -76,7 +76,7 @@ static struct at91_udc_data __initdata carmeva_udc_data = { .pullup_pin = AT91_PIN_PD9, }; -/* FIXME: user dependant */ +/* FIXME: user dependent */ // static struct at91_cf_data __initdata carmeva_cf_data = { // .det_pin = AT91_PIN_PB0, // .rst_pin = AT91_PIN_PC5, diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c index 1f9d3cb64c5..d8df59a3426 100644 --- a/arch/arm/mach-at91/board-eb01.c +++ b/arch/arm/mach-at91/board-eb01.c @@ -30,6 +30,11 @@ #include <mach/board.h> #include "generic.h" +static void __init at91eb01_init_irq(void) +{ + at91x40_init_interrupts(NULL); +} + static void __init at91eb01_map_io(void) { at91x40_initialize(40000000); @@ -38,7 +43,7 @@ static void __init at91eb01_map_io(void) MACHINE_START(AT91EB01, "Atmel AT91 EB01") /* Maintainer: Greg Ungerer <gerg@snapgear.com> */ .timer = &at91x40_timer, - .init_irq = at91x40_init_interrupts, + .init_irq = at91eb01_init_irq, .map_io = at91eb01_map_io, MACHINE_END diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c index af818a21587..4615528205c 100644 --- a/arch/arm/mach-at91/gpio.c +++ b/arch/arm/mach-at91/gpio.c @@ -287,7 +287,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state) else wakeups[bank] &= ~mask; - set_irq_wake(gpio_chip[bank].bank->id, state); + irq_set_irq_wake(gpio_chip[bank].bank->id, state); return 0; } @@ -375,6 +375,7 @@ static int gpio_irq_type(struct irq_data *d, unsigned type) static struct irq_chip gpio_irqchip = { .name = "GPIO", + .irq_disable = gpio_irq_mask, .irq_mask = gpio_irq_mask, .irq_unmask = gpio_irq_unmask, .irq_set_type = gpio_irq_type, @@ -384,16 +385,14 @@ static struct irq_chip gpio_irqchip = { static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) { unsigned pin; - struct irq_desc *gpio; - struct at91_gpio_chip *at91_gpio; - void __iomem *pio; + struct irq_data *idata = irq_desc_get_irq_data(desc); + struct irq_chip *chip = irq_data_get_irq_chip(idata); + struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); + void __iomem *pio = at91_gpio->regbase; u32 isr; - at91_gpio = get_irq_chip_data(irq); - pio = at91_gpio->regbase; - /* temporarily mask (level sensitive) parent IRQ */ - desc->irq_data.chip->irq_ack(&desc->irq_data); + chip->irq_ack(idata); for (;;) { /* Reading ISR acks pending (edge triggered) GPIO interrupts. * When there none are pending, we're finished unless we need @@ -409,27 +408,15 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) } pin = at91_gpio->chip.base; - gpio = &irq_desc[pin]; while (isr) { - if (isr & 1) { - if (unlikely(gpio->depth)) { - /* - * The core ARM interrupt handler lazily disables IRQs so - * another IRQ must be generated before it actually gets - * here to be disabled on the GPIO controller. - */ - gpio_irq_mask(irq_get_irq_data(pin)); - } - else - generic_handle_irq(pin); - } + if (isr & 1) + generic_handle_irq(pin); pin++; - gpio++; isr >>= 1; } } - desc->irq_data.chip->irq_unmask(&desc->irq_data); + chip->irq_unmask(idata); /* now it may re-trigger */ } @@ -518,14 +505,14 @@ void __init at91_gpio_irq_setup(void) __raw_writel(~0, this->regbase + PIO_IDR); for (i = 0, pin = this->chip.base; i < 32; i++, pin++) { - lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class); + irq_set_lockdep_class(pin, &gpio_lock_class); /* * Can use the "simple" and not "edge" handler since it's * shorter, and the AIC handles interrupts sanely. */ - set_irq_chip(pin, &gpio_irqchip); - set_irq_handler(pin, handle_simple_irq); + irq_set_chip_and_handler(pin, &gpio_irqchip, + handle_simple_irq); set_irq_flags(pin, IRQF_VALID); } @@ -536,8 +523,8 @@ void __init at91_gpio_irq_setup(void) if (prev && prev->next == this) continue; - set_irq_chip_data(id, this); - set_irq_chained_handler(id, gpio_irq_handler); + irq_set_chip_data(id, this); + irq_set_chained_handler(id, gpio_irq_handler); } pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); } diff --git a/arch/arm/mach-at91/include/mach/at572d940hf.h b/arch/arm/mach-at91/include/mach/at572d940hf.h index 2d9b0af9c4d..be510cfc56b 100644 --- a/arch/arm/mach-at91/include/mach/at572d940hf.h +++ b/arch/arm/mach-at91/include/mach/at572d940hf.h @@ -89,7 +89,7 @@ /* * System Peripherals (offset from AT91_BASE_SYS) */ -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) +#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) diff --git a/arch/arm/mach-at91/include/mach/at91_mci.h b/arch/arm/mach-at91/include/mach/at91_mci.h index 27ac6f550fe..02182c16a02 100644 --- a/arch/arm/mach-at91/include/mach/at91_mci.h +++ b/arch/arm/mach-at91/include/mach/at91_mci.h @@ -102,7 +102,7 @@ #define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */ #define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */ #define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */ -#define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */ +#define AT91_MCI_RTOE (1 << 20) /* Response Time-out Error */ #define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */ #define AT91_MCI_DTOE (1 << 22) /* Data Time-out Error */ #define AT91_MCI_OVRE (1 << 30) /* Overrun */ diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index 3bef931d0b1..0700f212530 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h @@ -27,6 +27,7 @@ #define ARCH_ID_AT91SAM9G45 0x819b05a0 #define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */ #define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */ +#define ARCH_ID_AT91SAM9X5 0x819a05a0 #define ARCH_ID_AT91CAP9 0x039A03A0 #define ARCH_ID_AT91SAM9XE128 0x329973a0 @@ -55,6 +56,12 @@ static inline unsigned long at91_cpu_fully_identify(void) #define ARCH_EXID_AT91SAM9G46 0x00000003 #define ARCH_EXID_AT91SAM9G45 0x00000004 +#define ARCH_EXID_AT91SAM9G15 0x00000000 +#define ARCH_EXID_AT91SAM9G35 0x00000001 +#define ARCH_EXID_AT91SAM9X35 0x00000002 +#define ARCH_EXID_AT91SAM9G25 0x00000003 +#define ARCH_EXID_AT91SAM9X25 0x00000004 + static inline unsigned long at91_exid_identify(void) { return at91_sys_read(AT91_DBGU_EXID); @@ -143,6 +150,27 @@ static inline unsigned long at91cap9_rev_identify(void) #define cpu_is_at91sam9m11() (0) #endif +#ifdef CONFIG_ARCH_AT91SAM9X5 +#define cpu_is_at91sam9x5() (at91_cpu_identify() == ARCH_ID_AT91SAM9X5) +#define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \ + (at91_exid_identify() == ARCH_EXID_AT91SAM9G15)) +#define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \ + (at91_exid_identify() == ARCH_EXID_AT91SAM9G35)) +#define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \ + (at91_exid_identify() == ARCH_EXID_AT91SAM9X35)) +#define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \ + (at91_exid_identify() == ARCH_EXID_AT91SAM9G25)) +#define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \ + (at91_exid_identify() == ARCH_EXID_AT91SAM9X25)) +#else +#define cpu_is_at91sam9x5() (0) +#define cpu_is_at91sam9g15() (0) +#define cpu_is_at91sam9g35() (0) +#define cpu_is_at91sam9x35() (0) +#define cpu_is_at91sam9g25() (0) +#define cpu_is_at91sam9x25() (0) +#endif + #ifdef CONFIG_ARCH_AT91CAP9 #define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9) #define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B) diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index ddeb6453675..056dc6674b6 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -208,7 +208,7 @@ extern void at91_gpio_resume(void); /*-------------------------------------------------------------------------*/ -/* wrappers for "new style" GPIO calls. the old AT91-specfic ones should +/* wrappers for "new style" GPIO calls. the old AT91-specific ones should * eventually be removed (along with this errno.h inclusion), and the * gpio request/free calls should probably be implemented. */ diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c index b56d6b3a408..9665265ec75 100644 --- a/arch/arm/mach-at91/irq.c +++ b/arch/arm/mach-at91/irq.c @@ -143,8 +143,7 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) /* Active Low interrupt, with the specified priority */ at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); - set_irq_chip(i, &at91_aic_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c index 77f84b40dda..a1f328357aa 100644 --- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c +++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c @@ -551,7 +551,7 @@ int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig, /* [ IN ] Config /****************************************************************************/ /** -* @brief Check the existance of pending descriptor +* @brief Check the existence of pending descriptor * * This function confirmes if there is any pending descriptor in the chain * to program the channel @@ -775,7 +775,7 @@ int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle, /* [ IN ] DMA Cha /** * @brief Read data DMAed to memory * -* This function will read data that has been DMAed to memory while transfering from: +* This function will read data that has been DMAed to memory while transferring from: * - Memory to memory * - Peripheral to memory * @@ -941,7 +941,7 @@ int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configurat /** * @brief Sets channel specific user data * -* This function associates user data to a specif DMA channel +* This function associates user data to a specific DMA channel * */ /****************************************************************************/ diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c index 8d1baf3f468..d87ad30dda3 100644 --- a/arch/arm/mach-bcmring/dma.c +++ b/arch/arm/mach-bcmring/dma.c @@ -629,7 +629,7 @@ EXPORT_SYMBOL(dma_get_device_descriptor_ring); * Configures a DMA channel. * * @return -* >= 0 - Initialization was successfull. +* >= 0 - Initialization was successful. * * -EBUSY - Device is currently being used. * -ENODEV - Device handed in is invalid. @@ -673,7 +673,7 @@ static int ConfigChannel(DMA_Handle_t handle) /** * Initializes all of the data structures associated with the DMA. * @return -* >= 0 - Initialization was successfull. +* >= 0 - Initialization was successful. * * -EBUSY - Device is currently being used. * -ENODEV - Device handed in is invalid. diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/csp/dmacHw.h index 6c8da2b9fc1..e6a1dc484ca 100644 --- a/arch/arm/mach-bcmring/include/csp/dmacHw.h +++ b/arch/arm/mach-bcmring/include/csp/dmacHw.h @@ -362,7 +362,7 @@ int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configurati /** * @brief Read data DMA transferred to memory * -* This function will read data that has been DMAed to memory while transfering from: +* This function will read data that has been DMAed to memory while transferring from: * - Memory to memory * - Peripheral to memory * @@ -446,7 +446,7 @@ void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle * /****************************************************************************/ /** -* @brief Check the existance of pending descriptor +* @brief Check the existence of pending descriptor * * This function confirmes if there is any pending descriptor in the chain * to program the channel @@ -542,7 +542,7 @@ dmacHw_HANDLE_t dmacHw_getInterruptSource(void); /** * @brief Sets channel specific user data * -* This function associates user data to a specif DMA channel +* This function associates user data to a specific DMA channel * */ /****************************************************************************/ diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h index 70eaea866cf..161973385fa 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h +++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h @@ -180,7 +180,7 @@ typedef enum { #define chipcHw_XTAL_FREQ_Hz 25000000 /* Reference clock frequency in Hz */ -/* Programable pin defines */ +/* Programmable pin defines */ #define chipcHw_PIN_GPIO(n) ((((n) >= 0) && ((n) < (chipcHw_GPIO_COUNT))) ? (n) : 0xFFFFFFFF) /* GPIO pin 0 - 60 */ #define chipcHw_PIN_UARTTXD (chipcHw_GPIO_COUNT + 0) /* UART Transmit */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h index c78833acb37..03238c29900 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h +++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h @@ -832,7 +832,7 @@ static inline void chipcHw_setUsbDevice(void) /****************************************************************************/ /** -* @brief Lower layer funtion to enable/disable a clock of a certain device +* @brief Lower layer function to enable/disable a clock of a certain device * * This function enables/disables a core clock * diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h index e01fc4607c9..0aeb6a6fe7f 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h @@ -109,9 +109,9 @@ #define INTCHW_INTC0_DMA0C0 (1<<INTCHW_INTC0_DMA0C0_BITNUM) /* INTC1 - interrupt controller 1 */ -#define INTCHW_INTC1_DDRVPMP_BITNUM 27 /* DDR and VPM PLL clock phase relationship interupt (Not for A0) */ +#define INTCHW_INTC1_DDRVPMP_BITNUM 27 /* DDR and VPM PLL clock phase relationship interrupt (Not for A0) */ #define INTCHW_INTC1_DDRVPMT_BITNUM 26 /* DDR and VPM HW phase align timeout interrupt (Not for A0) */ -#define INTCHW_INTC1_DDRP_BITNUM 26 /* DDR and PLL clock phase relationship interupt (For A0 only)) */ +#define INTCHW_INTC1_DDRP_BITNUM 26 /* DDR and PLL clock phase relationship interrupt (For A0 only)) */ #define INTCHW_INTC1_RTC2_BITNUM 25 /* Real time clock tamper interrupt */ #define INTCHW_INTC1_VDEC_BITNUM 24 /* Hantro Video Decoder interrupt */ /* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */ diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h b/arch/arm/mach-bcmring/include/mach/reg_umi.h index 06a355481ea..0992842caa7 100644 --- a/arch/arm/mach-bcmring/include/mach/reg_umi.h +++ b/arch/arm/mach-bcmring/include/mach/reg_umi.h @@ -88,7 +88,7 @@ /* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */ /* Enable wait pin during burst write or read */ #define REG_UMI_TCR_WAITEN 0x80000000 -/* Enable mem ctrlr to work iwth ext mem of lower freq than AHB clk */ +/* Enable mem ctrlr to work with ext mem of lower freq than AHB clk */ #define REG_UMI_TCR_LOWFREQ 0x40000000 /* 1=synch write, 0=async write */ #define REG_UMI_TCR_MEMTYPE_SYNCWRITE 0x20000000 diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c index 84dcda0d1d9..c48feaf4e8e 100644 --- a/arch/arm/mach-bcmring/irq.c +++ b/arch/arm/mach-bcmring/irq.c @@ -93,11 +93,11 @@ static void vic_init(void __iomem *base, struct irq_chip *chip, unsigned int i; for (i = 0; i < 32; i++) { unsigned int irq = irq_start + i; - set_irq_chip(irq, chip); - set_irq_chip_data(irq, base); + irq_set_chip(irq, chip); + irq_set_chip_data(irq, base); if (vic_sources & (1 << i)) { - set_irq_handler(irq, handle_level_irq); + irq_set_handler(irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } @@ -119,9 +119,9 @@ void __init bcmring_init_irq(void) /* special cases */ if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) { - set_irq_handler(IRQ_GPIO0, handle_simple_irq); + irq_set_handler(IRQ_GPIO0, handle_simple_irq); } if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) { - set_irq_handler(IRQ_GPIO1, handle_simple_irq); + irq_set_handler(IRQ_GPIO1, handle_simple_irq); } } diff --git a/arch/arm/mach-clps711x/irq.c b/arch/arm/mach-clps711x/irq.c index 86da7a1b2bb..c2eceee645e 100644 --- a/arch/arm/mach-clps711x/irq.c +++ b/arch/arm/mach-clps711x/irq.c @@ -112,13 +112,13 @@ void __init clps711x_init_irq(void) for (i = 0; i < NR_IRQS; i++) { if (INT1_IRQS & (1 << i)) { - set_irq_handler(i, handle_level_irq); - set_irq_chip(i, &int1_chip); + irq_set_chip_and_handler(i, &int1_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } if (INT2_IRQS & (1 << i)) { - set_irq_handler(i, handle_level_irq); - set_irq_chip(i, &int2_chip); + irq_set_chip_and_handler(i, &int2_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 32f147998cd..c0deacae778 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -63,6 +63,7 @@ config MACH_DAVINCI_EVM depends on ARCH_DAVINCI_DM644x select MISC_DEVICES select EEPROM_AT24 + select I2C help Configure this option to specify the whether the board used for development is a DM644x EVM @@ -72,6 +73,7 @@ config MACH_SFFSDR depends on ARCH_DAVINCI_DM644x select MISC_DEVICES select EEPROM_AT24 + select I2C help Say Y here to select the Lyrtech Small Form Factor Software Defined Radio (SFFSDR) board. @@ -105,6 +107,7 @@ config MACH_DAVINCI_DM6467_EVM select MACH_DAVINCI_DM6467TEVM select MISC_DEVICES select EEPROM_AT24 + select I2C help Configure this option to specify the whether the board used for development is a DM6467 EVM @@ -118,6 +121,7 @@ config MACH_DAVINCI_DM365_EVM depends on ARCH_DAVINCI_DM365 select MISC_DEVICES select EEPROM_AT24 + select I2C help Configure this option to specify whether the board used for development is a DM365 EVM @@ -129,6 +133,7 @@ config MACH_DAVINCI_DA830_EVM select GPIO_PCF857X select MISC_DEVICES select EEPROM_AT24 + select I2C help Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module. @@ -205,6 +210,7 @@ config MACH_MITYOMAPL138 depends on ARCH_DAVINCI_DA850 select MISC_DEVICES select EEPROM_AT24 + select I2C help Say Y here to select the Critical Link MityDSP-L138/MityARM-1808 System on Module. Information on this SoM may be found at diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c index 2aa79c54f98..606a6f27ed6 100644 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -29,7 +29,7 @@ #include <mach/mux.h> #include <mach/spi.h> -#define MITYOMAPL138_PHY_ID "0:03" +#define MITYOMAPL138_PHY_ID "" #define FACTORY_CONFIG_MAGIC 0x012C0138 #define FACTORY_CONFIG_VERSION 0x00010001 @@ -414,7 +414,7 @@ static struct resource mityomapl138_nandflash_resource[] = { static struct platform_device mityomapl138_nandflash_device = { .name = "davinci_nand", - .id = 0, + .id = 1, .dev = { .platform_data = &mityomapl138_nandflash_data, }, diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c index 6c389ff1020..3e7be2de96d 100644 --- a/arch/arm/mach-davinci/board-neuros-osd2.c +++ b/arch/arm/mach-davinci/board-neuros-osd2.c @@ -11,7 +11,7 @@ * DM644X-EVM board. It has: * DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC, * USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video. - * Additionaly realtime clock, IR remote control receiver, + * Additionally realtime clock, IR remote control receiver, * IR Blaster based on MSP430 (firmware although is different * from used in DM644X-EVM), internal ATA-6 3.5” HDD drive * with PATA interface, two muxed red-green leds. diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c index 9abc80a86a2..f83152d643c 100644 --- a/arch/arm/mach-davinci/cp_intc.c +++ b/arch/arm/mach-davinci/cp_intc.c @@ -167,9 +167,9 @@ void __init cp_intc_init(void) /* Set up genirq dispatching for cp_intc */ for (i = 0; i < num_irq; i++) { - set_irq_chip(i, &cp_intc_irq_chip); + irq_set_chip(i, &cp_intc_irq_chip); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - set_irq_handler(i, handle_edge_irq); + irq_set_handler(i, handle_edge_irq); } /* Enable global interrupt */ diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c index 4a68c2b1ec1..0a95be1512b 100644 --- a/arch/arm/mach-davinci/cpufreq.c +++ b/arch/arm/mach-davinci/cpufreq.c @@ -167,7 +167,7 @@ static int davinci_cpu_init(struct cpufreq_policy *policy) /* * Time measurement across the target() function yields ~1500-1800us * time taken with no drivers on notification list. - * Setting the latency to 2000 us to accomodate addition of drivers + * Setting the latency to 2000 us to accommodate addition of drivers * to pre/post change notification list. */ policy->cpuinfo.transition_latency = 2000 * 1000; diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 68fe4c289d7..b95b9196dee 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -1123,7 +1123,7 @@ void __init da850_init(void) * This helps keeping the peripherals on this domain insulated * from CPU frequency changes caused by DVFS. The firmware sets * both PLL0 and PLL1 to the same frequency so, there should not - * be any noticible change even in non-DVFS use cases. + * be any noticeable change even in non-DVFS use cases. */ da850_set_async3_src(1); diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 625d4b66718..58a02dc7b15 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -39,7 +39,8 @@ #define DA8XX_GPIO_BASE 0x01e26000 #define DA8XX_I2C1_BASE 0x01e28000 #define DA8XX_SPI0_BASE 0x01c41000 -#define DA8XX_SPI1_BASE 0x01f0e000 +#define DA830_SPI1_BASE 0x01e12000 +#define DA850_SPI1_BASE 0x01f0e000 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 @@ -762,8 +763,8 @@ static struct resource da8xx_spi0_resources[] = { static struct resource da8xx_spi1_resources[] = { [0] = { - .start = DA8XX_SPI1_BASE, - .end = DA8XX_SPI1_BASE + SZ_4K - 1, + .start = DA830_SPI1_BASE, + .end = DA830_SPI1_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -832,5 +833,10 @@ int __init da8xx_register_spi(int instance, struct spi_board_info *info, da8xx_spi_pdata[instance].num_chipselect = len; + if (instance == 1 && cpu_is_davinci_da850()) { + da8xx_spi1_resources[0].start = DA850_SPI1_BASE; + da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1; + } + return platform_device_register(&da8xx_spi_device[instance]); } diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 76364d1345d..a3a94e9c937 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -314,7 +314,7 @@ static struct clk timer2_clk = { .name = "timer2", .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_TIMER2, - .usecount = 1, /* REVISIT: why cant' this be disabled? */ + .usecount = 1, /* REVISIT: why can't this be disabled? */ }; static struct clk timer3_clk = { diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 9a2376b3137..4c82c271629 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -274,7 +274,7 @@ static struct clk timer2_clk = { .name = "timer2", .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_TIMER2, - .usecount = 1, /* REVISIT: why cant' this be disabled? */ + .usecount = 1, /* REVISIT: why can't this be disabled? */ }; static struct clk_lookup dm644x_clks[] = { diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index 20d66e5e466..a0b838894ac 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c @@ -62,7 +62,7 @@ static inline struct davinci_gpio_regs __iomem *irq2regs(int irq) { struct davinci_gpio_regs __iomem *g; - g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq); + g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq); return g; } @@ -208,7 +208,7 @@ pure_initcall(davinci_gpio_setup); static void gpio_irq_disable(struct irq_data *d) { struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); - u32 mask = (u32) irq_data_get_irq_data(d); + u32 mask = (u32) irq_data_get_irq_handler_data(d); __raw_writel(mask, &g->clr_falling); __raw_writel(mask, &g->clr_rising); @@ -217,8 +217,8 @@ static void gpio_irq_disable(struct irq_data *d) static void gpio_irq_enable(struct irq_data *d) { struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); - u32 mask = (u32) irq_data_get_irq_data(d); - unsigned status = irq_desc[d->irq].status; + u32 mask = (u32) irq_data_get_irq_handler_data(d); + unsigned status = irqd_get_trigger_type(d); status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; if (!status) @@ -233,21 +233,11 @@ static void gpio_irq_enable(struct irq_data *d) static int gpio_irq_type(struct irq_data *d, unsigned trigger) { struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); - u32 mask = (u32) irq_data_get_irq_data(d); + u32 mask = (u32) irq_data_get_irq_handler_data(d); if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) return -EINVAL; - irq_desc[d->irq].status &= ~IRQ_TYPE_SENSE_MASK; - irq_desc[d->irq].status |= trigger; - - /* don't enable the IRQ if it's currently disabled */ - if (irq_desc[d->irq].depth == 0) { - __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) - ? &g->set_falling : &g->clr_falling); - __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) - ? &g->set_rising : &g->clr_rising); - } return 0; } @@ -256,6 +246,7 @@ static struct irq_chip gpio_irqchip = { .irq_enable = gpio_irq_enable, .irq_disable = gpio_irq_disable, .irq_set_type = gpio_irq_type, + .flags = IRQCHIP_SET_TYPE_MASKED, }; static void @@ -285,7 +276,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) status >>= 16; /* now demux them to the right lowlevel handler */ - n = (int)get_irq_data(irq); + n = (int)irq_get_handler_data(irq); while (status) { res = ffs(status); n += res; @@ -323,7 +314,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger) { struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); - u32 mask = (u32) irq_data_get_irq_data(d); + u32 mask = (u32) irq_data_get_irq_handler_data(d); if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) return -EINVAL; @@ -395,7 +386,7 @@ static int __init davinci_gpio_irq_setup(void) /* AINTC handles mask/unmask; GPIO handles triggering */ irq = bank_irq; - gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq)); + gpio_irqchip_unbanked = *irq_get_chip(irq); gpio_irqchip_unbanked.name = "GPIO-AINTC"; gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked; @@ -406,10 +397,10 @@ static int __init davinci_gpio_irq_setup(void) /* set the direct IRQs up to use that irqchip */ for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { - set_irq_chip(irq, &gpio_irqchip_unbanked); - set_irq_data(irq, (void *) __gpio_mask(gpio)); - set_irq_chip_data(irq, (__force void *) g); - irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH; + irq_set_chip(irq, &gpio_irqchip_unbanked); + irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); + irq_set_chip_data(irq, (__force void *)g); + irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); } goto done; @@ -430,15 +421,15 @@ static int __init davinci_gpio_irq_setup(void) __raw_writel(~0, &g->clr_rising); /* set up all irqs in this bank */ - set_irq_chained_handler(bank_irq, gpio_irq_handler); - set_irq_chip_data(bank_irq, (__force void *) g); - set_irq_data(bank_irq, (void *) irq); + irq_set_chained_handler(bank_irq, gpio_irq_handler); + irq_set_chip_data(bank_irq, (__force void *)g); + irq_set_handler_data(bank_irq, (void *)irq); for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { - set_irq_chip(irq, &gpio_irqchip); - set_irq_chip_data(irq, (__force void *) g); - set_irq_data(irq, (void *) __gpio_mask(gpio)); - set_irq_handler(irq, handle_simple_irq); + irq_set_chip(irq, &gpio_irqchip); + irq_set_chip_data(irq, (__force void *)g); + irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); + irq_set_handler(irq, handle_simple_irq); set_irq_flags(irq, IRQF_VALID); } diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h index cea6b897204..957fb87e832 100644 --- a/arch/arm/mach-davinci/include/mach/cputype.h +++ b/arch/arm/mach-davinci/include/mach/cputype.h @@ -4,7 +4,7 @@ * Author: Kevin Hilman, Deep Root Systems, LLC * * Defines the cpu_is_*() macros for runtime detection of DaVinci - * device type. In addtion, if support for a given device is not + * device type. In addition, if support for a given device is not * compiled in to the kernel, the macros return 0 so that * resulting code can be optimized out. * diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S index 9f1befc5ac3..f8b7ea4f623 100644 --- a/arch/arm/mach-davinci/include/mach/debug-macro.S +++ b/arch/arm/mach-davinci/include/mach/debug-macro.S @@ -24,6 +24,9 @@ #define UART_SHIFT 2 +#define davinci_uart_v2p(x) ((x) - PAGE_OFFSET + PLAT_PHYS_OFFSET) +#define davinci_uart_p2v(x) ((x) - PLAT_PHYS_OFFSET + PAGE_OFFSET) + .pushsection .data davinci_uart_phys: .word 0 davinci_uart_virt: .word 0 @@ -34,7 +37,7 @@ davinci_uart_virt: .word 0 /* Use davinci_uart_phys/virt if already configured */ 10: mrc p15, 0, \rp, c1, c0 tst \rp, #1 @ MMU enabled? - ldreq \rp, =__virt_to_phys(davinci_uart_phys) + ldreq \rp, =davinci_uart_v2p(davinci_uart_phys) ldrne \rp, =davinci_uart_phys add \rv, \rp, #4 @ davinci_uart_virt ldr \rp, [\rp, #0] @@ -48,18 +51,18 @@ davinci_uart_virt: .word 0 tst \rp, #1 @ MMU enabled? /* Copy uart phys address from decompressor uart info */ - ldreq \rv, =__virt_to_phys(davinci_uart_phys) + ldreq \rv, =davinci_uart_v2p(davinci_uart_phys) ldrne \rv, =davinci_uart_phys ldreq \rp, =DAVINCI_UART_INFO - ldrne \rp, =__phys_to_virt(DAVINCI_UART_INFO) + ldrne \rp, =davinci_uart_p2v(DAVINCI_UART_INFO) ldr \rp, [\rp, #0] str \rp, [\rv] /* Copy uart virt address from decompressor uart info */ - ldreq \rv, =__virt_to_phys(davinci_uart_virt) + ldreq \rv, =davinci_uart_v2p(davinci_uart_virt) ldrne \rv, =davinci_uart_virt ldreq \rp, =DAVINCI_UART_INFO - ldrne \rp, =__phys_to_virt(DAVINCI_UART_INFO) + ldrne \rp, =davinci_uart_p2v(DAVINCI_UART_INFO) ldr \rp, [\rp, #4] str \rp, [\rv] diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h index 8051110b8ac..c9e6ce185a6 100644 --- a/arch/arm/mach-davinci/include/mach/serial.h +++ b/arch/arm/mach-davinci/include/mach/serial.h @@ -22,7 +22,7 @@ * * This area sits just below the page tables (see arch/arm/kernel/head.S). */ -#define DAVINCI_UART_INFO (PHYS_OFFSET + 0x3ff8) +#define DAVINCI_UART_INFO (PLAT_PHYS_OFFSET + 0x3ff8) #define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c index 5e05c9b64e1..e6269a6e001 100644 --- a/arch/arm/mach-davinci/irq.c +++ b/arch/arm/mach-davinci/irq.c @@ -154,11 +154,11 @@ void __init davinci_irq_init(void) /* set up genirq dispatch for ARM INTC */ for (i = 0; i < davinci_soc_info.intc_irq_num; i++) { - set_irq_chip(i, &davinci_irq_chip_0); + irq_set_chip(i, &davinci_irq_chip_0); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); if (i != IRQ_TINT1_TINT34) - set_irq_handler(i, handle_edge_irq); + irq_set_handler(i, handle_edge_irq); else - set_irq_handler(i, handle_level_irq); + irq_set_handler(i, handle_level_irq); } } diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h index e5fcdd3f5bf..b20ec9af788 100644 --- a/arch/arm/mach-dove/include/mach/dove.h +++ b/arch/arm/mach-dove/include/mach/dove.h @@ -136,7 +136,7 @@ #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) #define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) #define DOVE_NAND_GPIO_EN (1 << 0) -#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_VIRT_BASE + 0x40) +#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) #define DOVE_SPI_GPIO_SEL (1 << 5) #define DOVE_UART1_GPIO_SEL (1 << 4) #define DOVE_AU1_GPIO_SEL (1 << 3) diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c index 101707fa2e2..f07fd16e0c9 100644 --- a/arch/arm/mach-dove/irq.c +++ b/arch/arm/mach-dove/irq.c @@ -86,8 +86,7 @@ static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc) if (!(cause & (1 << irq))) continue; irq = pmu_to_irq(irq); - desc = irq_desc + irq; - desc_handle_irq(irq, desc); + generic_handle_irq(irq); } } @@ -103,14 +102,14 @@ void __init dove_init_irq(void) */ orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, IRQ_DOVE_GPIO_START); - set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler); - set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler); - set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler); - set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler); + irq_set_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler); + irq_set_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler); + irq_set_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler); + irq_set_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler); orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 32); - set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler); + irq_set_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler); orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 64); @@ -122,10 +121,9 @@ void __init dove_init_irq(void) writel(0, PMU_INTERRUPT_CAUSE); for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { - set_irq_chip(i, &pmu_irq_chip); - set_irq_handler(i, handle_level_irq); - irq_desc[i].status |= IRQ_LEVEL; + irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq); + irq_set_status_flags(i, IRQ_LEVEL); set_irq_flags(i, IRQF_VALID); } - set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); + irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); } diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c index 71db2bdf2f2..c66c7634690 100644 --- a/arch/arm/mach-dove/mpp.c +++ b/arch/arm/mach-dove/mpp.c @@ -147,9 +147,6 @@ void __init dove_mpp_conf(unsigned int *mpp_list) u32 pmu_sig_ctrl[PMU_SIG_REGS]; int i; - /* Initialize gpiolib. */ - orion_gpio_init(); - for (i = 0; i < MPP_NR_REGS; i++) mpp_ctrl[i] = readl(MPP_CTRL(i)); diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c index 7df083f37fa..087bc771ac2 100644 --- a/arch/arm/mach-ebsa110/core.c +++ b/arch/arm/mach-ebsa110/core.c @@ -66,8 +66,8 @@ static void __init ebsa110_init_irq(void) local_irq_restore(flags); for (irq = 0; irq < NR_IRQS; irq++) { - set_irq_chip(irq, &ebsa110_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ebsa110_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c index a889fa7c3ba..a5a9ff70b19 100644 --- a/arch/arm/mach-ep93xx/gpio.c +++ b/arch/arm/mach-ep93xx/gpio.c @@ -101,7 +101,7 @@ static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc) static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc) { /* - * map discontiguous hw irq range to continous sw irq range: + * map discontiguous hw irq range to continuous sw irq range: * * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7}) */ @@ -117,7 +117,7 @@ static void ep93xx_gpio_irq_ack(struct irq_data *d) int port = line >> 3; int port_mask = 1 << (line & 7); - if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { + if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { gpio_int_type2[port] ^= port_mask; /* switch edge direction */ ep93xx_gpio_update_int_params(port); } @@ -131,7 +131,7 @@ static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) int port = line >> 3; int port_mask = 1 << (line & 7); - if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) + if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) gpio_int_type2[port] ^= port_mask; /* switch edge direction */ gpio_int_unmasked[port] &= ~port_mask; @@ -165,10 +165,10 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d) */ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) { - struct irq_desc *desc = irq_desc + d->irq; const int gpio = irq_to_gpio(d->irq); const int port = gpio >> 3; const int port_mask = 1 << (gpio & 7); + irq_flow_handler_t handler; gpio_direction_input(gpio); @@ -176,22 +176,22 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) case IRQ_TYPE_EDGE_RISING: gpio_int_type1[port] |= port_mask; gpio_int_type2[port] |= port_mask; - desc->handle_irq = handle_edge_irq; + handler = handle_edge_irq; break; case IRQ_TYPE_EDGE_FALLING: gpio_int_type1[port] |= port_mask; gpio_int_type2[port] &= ~port_mask; - desc->handle_irq = handle_edge_irq; + handler = handle_edge_irq; break; case IRQ_TYPE_LEVEL_HIGH: gpio_int_type1[port] &= ~port_mask; gpio_int_type2[port] |= port_mask; - desc->handle_irq = handle_level_irq; + handler = handle_level_irq; break; case IRQ_TYPE_LEVEL_LOW: gpio_int_type1[port] &= ~port_mask; gpio_int_type2[port] &= ~port_mask; - desc->handle_irq = handle_level_irq; + handler = handle_level_irq; break; case IRQ_TYPE_EDGE_BOTH: gpio_int_type1[port] |= port_mask; @@ -200,17 +200,16 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) gpio_int_type2[port] &= ~port_mask; /* falling */ else gpio_int_type2[port] |= port_mask; /* rising */ - desc->handle_irq = handle_edge_irq; + handler = handle_edge_irq; break; default: pr_err("failed to set irq type %d for gpio %d\n", type, gpio); return -EINVAL; } - gpio_int_enabled[port] |= port_mask; + __irq_set_handler_locked(d->irq, handler); - desc->status &= ~IRQ_TYPE_SENSE_MASK; - desc->status |= type & IRQ_TYPE_SENSE_MASK; + gpio_int_enabled[port] |= port_mask; ep93xx_gpio_update_int_params(port); @@ -232,20 +231,29 @@ void __init ep93xx_gpio_init_irq(void) for (gpio_irq = gpio_to_irq(0); gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { - set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip); - set_irq_handler(gpio_irq, handle_level_irq); + irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, + handle_level_irq); set_irq_flags(gpio_irq, IRQF_VALID); } - set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO_AB, + ep93xx_gpio_ab_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX, + ep93xx_gpio_f_irq_handler); } @@ -360,52 +368,14 @@ static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) gpio = ep93xx_chip->chip.base; for (i = 0; i < chip->ngpio; i++, gpio++) { int is_out = data_dir_reg & (1 << i); + int irq = gpio_to_irq(gpio); - seq_printf(s, " %s%d gpio-%-3d (%-12s) %s %s", + seq_printf(s, " %s%d gpio-%-3d (%-12s) %s %s %s\n", chip->label, i, gpio, gpiochip_is_requested(chip, i) ? : "", is_out ? "out" : "in ", - (data_reg & (1 << i)) ? "hi" : "lo"); - - if (!is_out) { - int irq = gpio_to_irq(gpio); - struct irq_desc *desc = irq_desc + irq; - - if (irq >= 0 && desc->action) { - char *trigger; - - switch (desc->status & IRQ_TYPE_SENSE_MASK) { - case IRQ_TYPE_NONE: - trigger = "(default)"; - break; - case IRQ_TYPE_EDGE_FALLING: - trigger = "edge-falling"; - break; - case IRQ_TYPE_EDGE_RISING: - trigger = "edge-rising"; - break; - case IRQ_TYPE_EDGE_BOTH: - trigger = "edge-both"; - break; - case IRQ_TYPE_LEVEL_HIGH: - trigger = "level-high"; - break; - case IRQ_TYPE_LEVEL_LOW: - trigger = "level-low"; - break; - default: - trigger = "?trigger?"; - break; - } - - seq_printf(s, " irq-%d %s%s", - irq, trigger, - (desc->status & IRQ_WAKEUP) - ? " wakeup" : ""); - } - } - - seq_printf(s, "\n"); + (data_reg & (1<< i)) ? "hi" : "lo", + (!is_out && irq>= 0) ? "(interrupt)" : ""); } } diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig index a021b5240bb..e849f67be47 100644 --- a/arch/arm/mach-exynos4/Kconfig +++ b/arch/arm/mach-exynos4/Kconfig @@ -20,6 +20,11 @@ config EXYNOS4_MCT help Use MCT (Multi Core Timer) as kernel timers +config EXYNOS4_DEV_AHCI + bool + help + Compile in platform device definitions for AHCI + config EXYNOS4_DEV_PD bool help @@ -134,9 +139,9 @@ config MACH_ARMLEX4210 select S3C_DEV_HSMMC select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC3 + select EXYNOS4_DEV_AHCI select EXYNOS4_DEV_SYSMMU select EXYNOS4_SETUP_SDHCI - select SATA_AHCI_PLATFORM help Machine support for Samsung ARMLEX4210 based on EXYNOS4210 diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile index b8f0e7d82d7..9be104f63c0 100644 --- a/arch/arm/mach-exynos4/Makefile +++ b/arch/arm/mach-exynos4/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_MACH_NURI) += mach-nuri.o # device support obj-y += dev-audio.o +obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o @@ -53,4 +54,3 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o -obj-$(CONFIG_SATA_AHCI_PLATFORM) += dev-ahci.o diff --git a/arch/arm/mach-exynos4/include/mach/debug-macro.S b/arch/arm/mach-exynos4/include/mach/debug-macro.S index 58bbd049a6c..a442ef86116 100644 --- a/arch/arm/mach-exynos4/include/mach/debug-macro.S +++ b/arch/arm/mach-exynos4/include/mach/debug-macro.S @@ -21,8 +21,8 @@ */ .macro addruart, rp, rv - ldreq \rp, = S3C_PA_UART - ldrne \rv, = S3C_VA_UART + ldr \rp, = S3C_PA_UART + ldr \rv, = S3C_VA_UART #if CONFIG_DEBUG_S3C_UART != 0 add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART) add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART) diff --git a/arch/arm/mach-exynos4/include/mach/gpio.h b/arch/arm/mach-exynos4/include/mach/gpio.h index 939728b38d4..be9266b10fd 100644 --- a/arch/arm/mach-exynos4/include/mach/gpio.h +++ b/arch/arm/mach-exynos4/include/mach/gpio.h @@ -18,7 +18,7 @@ #define gpio_cansleep __gpio_cansleep #define gpio_to_irq __gpio_to_irq -/* Practically, GPIO banks upto GPZ are the configurable gpio banks */ +/* Practically, GPIO banks up to GPZ are the configurable gpio banks */ /* GPIO bank sizes */ #define EXYNOS4_GPIO_A0_NR (8) diff --git a/arch/arm/mach-exynos4/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c index 31618d91ce1..f488b66d680 100644 --- a/arch/arm/mach-exynos4/irq-combiner.c +++ b/arch/arm/mach-exynos4/irq-combiner.c @@ -54,8 +54,8 @@ static void combiner_unmask_irq(struct irq_data *data) static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) { - struct combiner_chip_data *chip_data = get_irq_data(irq); - struct irq_chip *chip = get_irq_chip(irq); + struct combiner_chip_data *chip_data = irq_get_handler_data(irq); + struct irq_chip *chip = irq_get_chip(irq); unsigned int cascade_irq, combiner_irq; unsigned long status; @@ -93,9 +93,9 @@ void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) { if (combiner_nr >= MAX_COMBINER_NR) BUG(); - if (set_irq_data(irq, &combiner_data[combiner_nr]) != 0) + if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0) BUG(); - set_irq_chained_handler(irq, combiner_handle_cascade_irq); + irq_set_chained_handler(irq, combiner_handle_cascade_irq); } void __init combiner_init(unsigned int combiner_nr, void __iomem *base, @@ -119,9 +119,8 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base, for (i = irq_start; i < combiner_data[combiner_nr].irq_offset + MAX_IRQ_IN_COMBINER; i++) { - set_irq_chip(i, &combiner_chip); - set_irq_chip_data(i, &combiner_data[combiner_nr]); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq); + irq_set_chip_data(i, &combiner_data[combiner_nr]); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/mach-exynos4/irq-eint.c b/arch/arm/mach-exynos4/irq-eint.c index 4f7ad4a796e..9d87d2ac7f6 100644 --- a/arch/arm/mach-exynos4/irq-eint.c +++ b/arch/arm/mach-exynos4/irq-eint.c @@ -190,8 +190,8 @@ static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc) { - u32 *irq_data = get_irq_data(irq); - struct irq_chip *chip = get_irq_chip(irq); + u32 *irq_data = irq_get_handler_data(irq); + struct irq_chip *chip = irq_get_chip(irq); chip->irq_mask(&desc->irq_data); @@ -208,18 +208,19 @@ int __init exynos4_init_irq_eint(void) int irq; for (irq = 0 ; irq <= 31 ; irq++) { - set_irq_chip(IRQ_EINT(irq), &exynos4_irq_eint); - set_irq_handler(IRQ_EINT(irq), handle_level_irq); + irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint, + handle_level_irq); set_irq_flags(IRQ_EINT(irq), IRQF_VALID); } - set_irq_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31); + irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31); for (irq = 0 ; irq <= 15 ; irq++) { eint0_15_data[irq] = IRQ_EINT(irq); - set_irq_data(exynos4_get_irq_nr(irq), &eint0_15_data[irq]); - set_irq_chained_handler(exynos4_get_irq_nr(irq), + irq_set_handler_data(exynos4_get_irq_nr(irq), + &eint0_15_data[irq]); + irq_set_chained_handler(exynos4_get_irq_nr(irq), exynos4_irq_eint0_15); } diff --git a/arch/arm/mach-exynos4/localtimer.c b/arch/arm/mach-exynos4/localtimer.c index 2a2993ae8d8..6bf3d0ab962 100644 --- a/arch/arm/mach-exynos4/localtimer.c +++ b/arch/arm/mach-exynos4/localtimer.c @@ -18,8 +18,9 @@ /* * Setup the local clock events for a CPU. */ -void __cpuinit local_timer_setup(struct clock_event_device *evt) +int __cpuinit local_timer_setup(struct clock_event_device *evt) { evt->irq = IRQ_LOCALTIMER; twd_timer_setup(evt); + return 0; } diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c index 25a25681812..e645f7a955f 100644 --- a/arch/arm/mach-exynos4/mach-smdkc210.c +++ b/arch/arm/mach-exynos4/mach-smdkc210.c @@ -125,7 +125,7 @@ static struct resource smdkc210_smsc911x_resources[] = { }; static struct smsc911x_platform_config smsc9215_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, .phy_interface = PHY_INTERFACE_MODE_MII, diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c index 88e0275143b..152676471b6 100644 --- a/arch/arm/mach-exynos4/mach-smdkv310.c +++ b/arch/arm/mach-exynos4/mach-smdkv310.c @@ -127,7 +127,7 @@ static struct resource smdkv310_smsc911x_resources[] = { }; static struct smsc911x_platform_config smsc9215_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, .phy_interface = PHY_INTERFACE_MODE_MII, diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c index af82a8fbb68..14ac10b7ec0 100644 --- a/arch/arm/mach-exynos4/mct.c +++ b/arch/arm/mach-exynos4/mct.c @@ -276,7 +276,7 @@ static void exynos4_mct_tick_start(unsigned long cycles, /* update interrupt count buffer */ exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET); - /* enable MCT tick interupt */ + /* enable MCT tick interrupt */ exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET); tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET); diff --git a/arch/arm/mach-exynos4/setup-sdhci-gpio.c b/arch/arm/mach-exynos4/setup-sdhci-gpio.c index 1b3d3a2de95..e8d08bf8965 100644 --- a/arch/arm/mach-exynos4/setup-sdhci-gpio.c +++ b/arch/arm/mach-exynos4/setup-sdhci-gpio.c @@ -38,14 +38,14 @@ void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) switch (width) { case 8: for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) { - /* Data pin GPK1[3:6] to special-funtion 3 */ + /* Data pin GPK1[3:6] to special-function 3 */ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); } case 4: for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) { - /* Data pin GPK0[3:6] to special-funtion 2 */ + /* Data pin GPK0[3:6] to special-function 2 */ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); diff --git a/arch/arm/mach-exynos4/setup-sdhci.c b/arch/arm/mach-exynos4/setup-sdhci.c index 85f9433d483..1e83f8cf236 100644 --- a/arch/arm/mach-exynos4/setup-sdhci.c +++ b/arch/arm/mach-exynos4/setup-sdhci.c @@ -35,7 +35,7 @@ void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r, { u32 ctrl2, ctrl3; - /* don't need to alter anything acording to card-type */ + /* don't need to alter anything according to card-type */ ctrl2 = readl(r + S3C_SDHCI_CONTROL2); diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c index 84c5f258f2d..38a44f9b9da 100644 --- a/arch/arm/mach-footbridge/common.c +++ b/arch/arm/mach-footbridge/common.c @@ -102,8 +102,7 @@ static void __init __fb_init_irq(void) *CSR_FIQ_DISABLE = -1; for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) { - set_irq_chip(irq, &fb_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c index a921fe92b85..5f1f9867fc7 100644 --- a/arch/arm/mach-footbridge/dc21285-timer.c +++ b/arch/arm/mach-footbridge/dc21285-timer.c @@ -30,7 +30,7 @@ static int cksrc_dc21285_enable(struct clocksource *cs) return 0; } -static int cksrc_dc21285_disable(struct clocksource *cs) +static void cksrc_dc21285_disable(struct clocksource *cs) { *CSR_TIMER2_CNTL = 0; } diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c index de7a5cb5dbe..c3a0abbc904 100644 --- a/arch/arm/mach-footbridge/isa-irq.c +++ b/arch/arm/mach-footbridge/isa-irq.c @@ -151,14 +151,14 @@ void __init isa_init_irq(unsigned int host_irq) if (host_irq != (unsigned int)-1) { for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) { - set_irq_chip(irq, &isa_lo_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &isa_lo_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) { - set_irq_chip(irq, &isa_hi_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &isa_hi_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } @@ -166,7 +166,7 @@ void __init isa_init_irq(unsigned int host_irq) request_resource(&ioport_resource, &pic2_resource); setup_irq(IRQ_ISA_CASCADE, &irq_cascade); - set_irq_chained_handler(host_irq, isa_irq_handler); + irq_set_chained_handler(host_irq, isa_irq_handler); /* * On the NetWinder, don't automatically diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c index fa3d333f21e..fdc7ef1391d 100644 --- a/arch/arm/mach-gemini/gpio.c +++ b/arch/arm/mach-gemini/gpio.c @@ -127,8 +127,8 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type) static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { + unsigned int port = (unsigned int)irq_desc_get_handler_data(desc); unsigned int gpio_irq_no, irq_stat; - unsigned int port = (unsigned int)get_irq_data(irq); irq_stat = __raw_readl(GPIO_BASE(port) + GPIO_INT_STAT); @@ -138,9 +138,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) if ((irq_stat & 1) == 0) continue; - BUG_ON(!(irq_desc[gpio_irq_no].handle_irq)); - irq_desc[gpio_irq_no].handle_irq(gpio_irq_no, - &irq_desc[gpio_irq_no]); + generic_handle_irq(gpio_irq_no); } } @@ -219,13 +217,13 @@ void __init gemini_gpio_init(void) for (j = GPIO_IRQ_BASE + i * 32; j < GPIO_IRQ_BASE + (i + 1) * 32; j++) { - set_irq_chip(j, &gpio_irq_chip); - set_irq_handler(j, handle_edge_irq); + irq_set_chip_and_handler(j, &gpio_irq_chip, + handle_edge_irq); set_irq_flags(j, IRQF_VALID); } - set_irq_chained_handler(IRQ_GPIO(i), gpio_irq_handler); - set_irq_data(IRQ_GPIO(i), (void *)i); + irq_set_chained_handler(IRQ_GPIO(i), gpio_irq_handler); + irq_set_handler_data(IRQ_GPIO(i), (void *)i); } BUG_ON(gpiochip_add(&gemini_gpio_chip)); diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c index 96bc227dd84..9485a8fdf85 100644 --- a/arch/arm/mach-gemini/irq.c +++ b/arch/arm/mach-gemini/irq.c @@ -81,13 +81,13 @@ void __init gemini_init_irq(void) request_resource(&iomem_resource, &irq_resource); for (i = 0; i < NR_IRQS; i++) { - set_irq_chip(i, &gemini_irq_chip); + irq_set_chip(i, &gemini_irq_chip); if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) { - set_irq_handler(i, handle_edge_irq); + irq_set_handler(i, handle_edge_irq); mode |= 1 << i; level |= 1 << i; } else { - set_irq_handler(i, handle_level_irq); + irq_set_handler(i, handle_level_irq); } set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c index 1f28c90932c..51d4e44ab97 100644 --- a/arch/arm/mach-h720x/common.c +++ b/arch/arm/mach-h720x/common.c @@ -199,29 +199,29 @@ void __init h720x_init_irq (void) /* Initialize global IRQ's, fast path */ for (irq = 0; irq < NR_GLBL_IRQS; irq++) { - set_irq_chip(irq, &h720x_global_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &h720x_global_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } /* Initialize multiplexed IRQ's, slow path */ for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) { - set_irq_chip(irq, &h720x_gpio_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &h720x_gpio_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID ); } - set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); - set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler); - set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler); - set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler); + irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); + irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler); + irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler); + irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler); #ifdef CONFIG_CPU_H7202 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) { - set_irq_chip(irq, &h720x_gpio_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &h720x_gpio_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID ); } - set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); + irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); #endif /* Enable multiplexed irq's */ diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c index ac3f9144237..c37d570b852 100644 --- a/arch/arm/mach-h720x/cpu-h7202.c +++ b/arch/arm/mach-h720x/cpu-h7202.c @@ -141,13 +141,18 @@ h7202_timer_interrupt(int irq, void *dev_id) /* * mask multiplexed timer IRQs */ -static void inline mask_timerx_irq(struct irq_data *d) +static void inline __mask_timerx_irq(unsigned int irq) { unsigned int bit; - bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1)); + bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1)); CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit; } +static void inline mask_timerx_irq(struct irq_data *d) +{ + __mask_timerx_irq(d->irq); +} + /* * unmask multiplexed timer IRQs */ @@ -196,12 +201,12 @@ void __init h7202_init_irq (void) for (irq = IRQ_TIMER1; irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) { - mask_timerx_irq(irq); - set_irq_chip(irq, &h7202_timerx_chip); - set_irq_handler(irq, handle_edge_irq); + __mask_timerx_irq(irq); + irq_set_chip_and_handler(irq, &h7202_timerx_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID ); } - set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler); + irq_set_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler); h720x_init_irq(); } diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 5eec099e0c7..56b930a1344 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -255,6 +255,7 @@ config MACH_IMX27_VISSTRIM_M10 bool "Vista Silicon i.MX27 Visstrim_m10" select SOC_IMX27 select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_EHCI diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c index cb705c28de0..6269053505f 100644 --- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c @@ -34,6 +34,7 @@ #include <mach/mx25.h> #include <mach/imx-uart.h> #include <mach/audmux.h> +#include <mach/esdhc.h> #include "devices-imx25.h" @@ -242,6 +243,11 @@ struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = { .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, }; +static struct esdhc_platform_data sd1_pdata = { + .cd_gpio = GPIO_SD1CD, + .wp_gpio = -EINVAL, +}; + /* * system init for baseboard usage. Will be called by cpuimx25 init. * @@ -275,7 +281,7 @@ void __init eukrea_mbimxsd25_baseboard_init(void) imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); imx25_add_flexcan1(NULL); - imx25_add_sdhci_esdhc_imx(0, NULL); + imx25_add_sdhci_esdhc_imx(0, &sd1_pdata); gpio_request(GPIO_LED1, "LED1"); gpio_direction_output(GPIO_LED1, 1); diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index 614b3c00c4a..6e1accf93f8 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c @@ -232,10 +232,13 @@ static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = { }; /* MC13783 */ -static struct mc13xxx_platform_data mc13783_pdata __initdata = { - .regulators = mx27_3ds_regulators, - .num_regulators = ARRAY_SIZE(mx27_3ds_regulators), - .flags = MC13XXX_USE_REGULATOR, +static struct mc13xxx_platform_data mc13783_pdata = { + .regulators = { + .regulators = mx27_3ds_regulators, + .num_regulators = ARRAY_SIZE(mx27_3ds_regulators), + + }, + .flags = MC13783_USE_REGULATOR, }; /* SPI */ diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index 38c77084b61..4cbce6d0fef 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c @@ -263,10 +263,12 @@ static struct mc13xxx_regulator_init_data pcm038_regulators[] = { }; static struct mc13xxx_platform_data pcm038_pmic = { - .regulators = pcm038_regulators, - .num_regulators = ARRAY_SIZE(pcm038_regulators), - .flags = MC13XXX_USE_ADC | MC13XXX_USE_REGULATOR | - MC13XXX_USE_TOUCHSCREEN, + .regulators = { + .regulators = pcm038_regulators, + .num_regulators = ARRAY_SIZE(pcm038_regulators), + }, + .flags = MC13783_USE_ADC | MC13783_USE_REGULATOR | + MC13783_USE_TOUCHSCREEN, }; static struct spi_board_info pcm038_spi_board_info[] __initdata = { diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig index 769b0f10c83..d701d32a07f 100644 --- a/arch/arm/mach-integrator/Kconfig +++ b/arch/arm/mach-integrator/Kconfig @@ -13,6 +13,7 @@ config ARCH_INTEGRATOR_CP bool "Support Integrator/CP platform" select ARCH_CINTEGRATOR select ARM_TIMER_SP804 + select PLAT_VERSATILE_CLCD help Include support for the ARM(R) Integrator CP platform. diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h index 5f96e1518aa..a08f9b0299d 100644 --- a/arch/arm/mach-integrator/common.h +++ b/arch/arm/mach-integrator/common.h @@ -1 +1,2 @@ +void integrator_init_early(void); void integrator_reserve(void); diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c index b8e884b450d..77315b99568 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c @@ -144,12 +144,15 @@ static struct clk_lookup lookups[] = { } }; +void __init integrator_init_early(void) +{ + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); +} + static int __init integrator_init(void) { int i; - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { struct amba_device *d = amba_devs[i]; amba_device_register(d, &iomem_resource); diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c index 5db574f8ae3..8cbb75a96bd 100644 --- a/arch/arm/mach-integrator/impd1.c +++ b/arch/arm/mach-integrator/impd1.c @@ -121,6 +121,7 @@ static struct clcd_panel vga = { .height = -1, .tim2 = TIM2_BCD | TIM2_IPC, .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), + .caps = CLCD_CAP_5551, .connector = IMPD1_CTRL_DISP_VGA, .bpp = 16, .grayscale = 0, @@ -149,6 +150,7 @@ static struct clcd_panel svga = { .tim2 = TIM2_BCD, .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), .connector = IMPD1_CTRL_DISP_VGA, + .caps = CLCD_CAP_5551, .bpp = 16, .grayscale = 0, }; @@ -175,6 +177,7 @@ static struct clcd_panel prospector = { .height = -1, .tim2 = TIM2_BCD, .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), + .caps = CLCD_CAP_5551, .fixedtimings = 1, .connector = IMPD1_CTRL_DISP_LCD, .bpp = 16, @@ -206,6 +209,7 @@ static struct clcd_panel ltm10c209 = { .height = -1, .tim2 = TIM2_BCD, .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), + .caps = CLCD_CAP_5551, .fixedtimings = 1, .connector = IMPD1_CTRL_DISP_LCD, .bpp = 16, @@ -279,6 +283,7 @@ static void impd1fb_clcd_remove(struct clcd_fb *fb) static struct clcd_board impd1_clcd_data = { .name = "IM-PD/1", + .caps = CLCD_CAP_5551 | CLCD_CAP_888, .check = clcdfb_check, .decode = clcdfb_decode, .disable = impd1fb_clcd_disable, diff --git a/arch/arm/mach-integrator/include/mach/cm.h b/arch/arm/mach-integrator/include/mach/cm.h index 1ab353e2359..445d57adb04 100644 --- a/arch/arm/mach-integrator/include/mach/cm.h +++ b/arch/arm/mach-integrator/include/mach/cm.h @@ -24,9 +24,9 @@ void cm_control(u32, u32); #define CM_CTRL_LCDBIASDN (1 << 10) #define CM_CTRL_LCDMUXSEL_MASK (7 << 11) #define CM_CTRL_LCDMUXSEL_GENLCD (1 << 11) -#define CM_CTRL_LCDMUXSEL_VGA_16BPP (2 << 11) +#define CM_CTRL_LCDMUXSEL_VGA565_TFT555 (2 << 11) #define CM_CTRL_LCDMUXSEL_SHARPLCD (3 << 11) -#define CM_CTRL_LCDMUXSEL_VGA_8421BPP (4 << 11) +#define CM_CTRL_LCDMUXSEL_VGA555_TFT555 (4 << 11) #define CM_CTRL_LCDEN0 (1 << 14) #define CM_CTRL_LCDEN1 (1 << 15) #define CM_CTRL_STATIC1 (1 << 16) diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index b666443b5cb..980803ff348 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -48,6 +48,8 @@ #include <asm/mach/map.h> #include <asm/mach/time.h> +#include <plat/fpga-irq.h> + #include "common.h" /* @@ -57,10 +59,10 @@ * Setup a VA for the Integrator interrupt controller (for header #0, * just for now). */ -#define VA_IC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE) -#define VA_SC_BASE IO_ADDRESS(INTEGRATOR_SC_BASE) -#define VA_EBI_BASE IO_ADDRESS(INTEGRATOR_EBI_BASE) -#define VA_CMIC_BASE IO_ADDRESS(INTEGRATOR_HDR_IC) +#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE) +#define VA_SC_BASE __io_address(INTEGRATOR_SC_BASE) +#define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE) +#define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC) /* * Logical Physical @@ -156,27 +158,14 @@ static void __init ap_map_io(void) #define INTEGRATOR_SC_VALID_INT 0x003fffff -static void sc_mask_irq(struct irq_data *d) -{ - writel(1 << d->irq, VA_IC_BASE + IRQ_ENABLE_CLEAR); -} - -static void sc_unmask_irq(struct irq_data *d) -{ - writel(1 << d->irq, VA_IC_BASE + IRQ_ENABLE_SET); -} - -static struct irq_chip sc_chip = { - .name = "SC", - .irq_ack = sc_mask_irq, - .irq_mask = sc_mask_irq, - .irq_unmask = sc_unmask_irq, +static struct fpga_irq_data sc_irq_data = { + .base = VA_IC_BASE, + .irq_start = 0, + .chip.name = "SC", }; static void __init ap_init_irq(void) { - unsigned int i; - /* Disable all interrupts initially. */ /* Do the core module ones */ writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); @@ -185,13 +174,7 @@ static void __init ap_init_irq(void) writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); - for (i = 0; i < NR_IRQS; i++) { - if (((1 << i) & INTEGRATOR_SC_VALID_INT) != 0) { - set_irq_chip(i, &sc_chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - } - } + fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data); } #ifdef CONFIG_PM @@ -282,7 +265,7 @@ static void ap_flash_exit(void) static void ap_flash_set_vpp(int on) { - unsigned long reg = on ? SC_CTRLS : SC_CTRLC; + void __iomem *reg = on ? SC_CTRLS : SC_CTRLC; writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg); } @@ -499,8 +482,9 @@ static struct sys_timer ap_timer = { MACHINE_START(INTEGRATOR, "ARM-Integrator") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ .boot_params = 0x00000100, - .map_io = ap_map_io, .reserve = integrator_reserve, + .map_io = ap_map_io, + .init_early = integrator_init_early, .init_irq = ap_init_irq, .timer = &ap_timer, .init_machine = ap_init, diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index e9327da1382..9e3ce26023e 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -42,6 +42,10 @@ #include <asm/hardware/timer-sp.h> +#include <plat/clcd.h> +#include <plat/fpga-irq.h> +#include <plat/sched_clock.h> + #include "common.h" #define INTCP_PA_FLASH_BASE 0x24000000 @@ -49,9 +53,9 @@ #define INTCP_PA_CLCD_BASE 0xc0000000 -#define INTCP_VA_CIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x40) -#define INTCP_VA_PIC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE) -#define INTCP_VA_SIC_BASE IO_ADDRESS(INTEGRATOR_CP_SIC_BASE) +#define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40) +#define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE) +#define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE) #define INTCP_ETH_SIZE 0x10 @@ -139,129 +143,48 @@ static void __init intcp_map_io(void) iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc)); } -#define cic_writel __raw_writel -#define cic_readl __raw_readl -#define pic_writel __raw_writel -#define pic_readl __raw_readl -#define sic_writel __raw_writel -#define sic_readl __raw_readl - -static void cic_mask_irq(struct irq_data *d) -{ - unsigned int irq = d->irq - IRQ_CIC_START; - cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR); -} - -static void cic_unmask_irq(struct irq_data *d) -{ - unsigned int irq = d->irq - IRQ_CIC_START; - cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET); -} - -static struct irq_chip cic_chip = { - .name = "CIC", - .irq_ack = cic_mask_irq, - .irq_mask = cic_mask_irq, - .irq_unmask = cic_unmask_irq, +static struct fpga_irq_data cic_irq_data = { + .base = INTCP_VA_CIC_BASE, + .irq_start = IRQ_CIC_START, + .chip.name = "CIC", }; -static void pic_mask_irq(struct irq_data *d) -{ - unsigned int irq = d->irq - IRQ_PIC_START; - pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR); -} - -static void pic_unmask_irq(struct irq_data *d) -{ - unsigned int irq = d->irq - IRQ_PIC_START; - pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET); -} - -static struct irq_chip pic_chip = { - .name = "PIC", - .irq_ack = pic_mask_irq, - .irq_mask = pic_mask_irq, - .irq_unmask = pic_unmask_irq, +static struct fpga_irq_data pic_irq_data = { + .base = INTCP_VA_PIC_BASE, + .irq_start = IRQ_PIC_START, + .chip.name = "PIC", }; -static void sic_mask_irq(struct irq_data *d) -{ - unsigned int irq = d->irq - IRQ_SIC_START; - sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); -} - -static void sic_unmask_irq(struct irq_data *d) -{ - unsigned int irq = d->irq - IRQ_SIC_START; - sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET); -} - -static struct irq_chip sic_chip = { - .name = "SIC", - .irq_ack = sic_mask_irq, - .irq_mask = sic_mask_irq, - .irq_unmask = sic_unmask_irq, +static struct fpga_irq_data sic_irq_data = { + .base = INTCP_VA_SIC_BASE, + .irq_start = IRQ_SIC_START, + .chip.name = "SIC", }; -static void -sic_handle_irq(unsigned int irq, struct irq_desc *desc) -{ - unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS); - - if (status == 0) { - do_bad_IRQ(irq, desc); - return; - } - - do { - irq = ffs(status) - 1; - status &= ~(1 << irq); - - irq += IRQ_SIC_START; - - generic_handle_irq(irq); - } while (status); -} - static void __init intcp_init_irq(void) { - unsigned int i; + u32 pic_mask, sic_mask; + + pic_mask = ~((~0u) << (11 - IRQ_PIC_START)); + pic_mask |= (~((~0u) << (29 - 22))) << 22; + sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START)); /* * Disable all interrupt sources */ - pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR); - pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR); - - for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) { - if (i == 11) - i = 22; - if (i == 29) - break; - set_irq_chip(i, &pic_chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - } + writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR); + writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR); + writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR); + writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR); + writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); + writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR); - cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR); - cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR); + fpga_irq_init(-1, pic_mask, &pic_irq_data); - for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) { - set_irq_chip(i, &cic_chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } - - sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); - sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR); - - for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) { - set_irq_chip(i, &sic_chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - } + fpga_irq_init(-1, ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)), + &cic_irq_data); - set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq); + fpga_irq_init(IRQ_CP_CPPLDINT, sic_mask, &sic_irq_data); } /* @@ -449,43 +372,21 @@ static struct amba_device aaci_device = { /* * CLCD support */ -static struct clcd_panel vga = { - .mode = { - .name = "VGA", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 39721, - .left_margin = 40, - .right_margin = 24, - .upper_margin = 32, - .lower_margin = 11, - .hsync_len = 96, - .vsync_len = 2, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_BCD | TIM2_IPC, - .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), - .bpp = 16, - .grayscale = 0, -}; - /* * Ensure VGA is selected. */ static void cp_clcd_enable(struct clcd_fb *fb) { - u32 val; + struct fb_var_screeninfo *var = &fb->fb.var; + u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2; - if (fb->fb.var.bits_per_pixel <= 8) - val = CM_CTRL_LCDMUXSEL_VGA_8421BPP; + if (var->bits_per_pixel <= 8 || + (var->bits_per_pixel == 16 && var->green.length == 5)) + /* Pseudocolor, RGB555, BGR555 */ + val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555; else if (fb->fb.var.bits_per_pixel <= 16) - val = CM_CTRL_LCDMUXSEL_VGA_16BPP - | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1 - | CM_CTRL_STATIC1 | CM_CTRL_STATIC2; + /* truecolor RGB565 */ + val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555; else val = 0; /* no idea for this, don't trust the docs */ @@ -498,49 +399,24 @@ static void cp_clcd_enable(struct clcd_fb *fb) CM_CTRL_n24BITEN, val); } -static unsigned long framesize = SZ_1M; - static int cp_clcd_setup(struct clcd_fb *fb) { - dma_addr_t dma; - - fb->panel = &vga; - - fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, - &dma, GFP_KERNEL); - if (!fb->fb.screen_base) { - printk(KERN_ERR "CLCD: unable to map framebuffer\n"); - return -ENOMEM; - } - - fb->fb.fix.smem_start = dma; - fb->fb.fix.smem_len = framesize; - - return 0; -} - -static int cp_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) -{ - return dma_mmap_writecombine(&fb->dev->dev, vma, - fb->fb.screen_base, - fb->fb.fix.smem_start, - fb->fb.fix.smem_len); -} + fb->panel = versatile_clcd_get_panel("VGA"); + if (!fb->panel) + return -EINVAL; -static void cp_clcd_remove(struct clcd_fb *fb) -{ - dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, - fb->fb.screen_base, fb->fb.fix.smem_start); + return versatile_clcd_setup_dma(fb, SZ_1M); } static struct clcd_board clcd_data = { .name = "Integrator/CP", + .caps = CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888, .check = clcdfb_check, .decode = clcdfb_decode, .enable = cp_clcd_enable, .setup = cp_clcd_setup, - .mmap = cp_clcd_mmap, - .remove = cp_clcd_remove, + .mmap = versatile_clcd_mmap_dma, + .remove = versatile_clcd_remove_dma, }; static struct amba_device clcd_device = { @@ -565,11 +441,23 @@ static struct amba_device *amba_devs[] __initdata = { &clcd_device, }; +#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28) + +static void __init intcp_init_early(void) +{ + clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups)); + + integrator_init_early(); + +#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK + versatile_sched_clock_init(REFCOUNTER, 24000000); +#endif +} + static void __init intcp_init(void) { int i; - clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups)); platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs)); for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { @@ -599,8 +487,9 @@ static struct sys_timer cp_timer = { MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ .boot_params = 0x00000100, - .map_io = intcp_map_io, .reserve = integrator_reserve, + .map_io = intcp_map_io, + .init_early = intcp_init_early, .init_irq = intcp_init_irq, .timer = &cp_timer, .init_machine = intcp_init, diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c index a233470dd10..bc739701c30 100644 --- a/arch/arm/mach-iop13xx/irq.c +++ b/arch/arm/mach-iop13xx/irq.c @@ -224,15 +224,15 @@ void __init iop13xx_init_irq(void) for(i = 0; i <= IRQ_IOP13XX_HPI; i++) { if (i < 32) - set_irq_chip(i, &iop13xx_irqchip1); + irq_set_chip(i, &iop13xx_irqchip1); else if (i < 64) - set_irq_chip(i, &iop13xx_irqchip2); + irq_set_chip(i, &iop13xx_irqchip2); else if (i < 96) - set_irq_chip(i, &iop13xx_irqchip3); + irq_set_chip(i, &iop13xx_irqchip3); else - set_irq_chip(i, &iop13xx_irqchip4); + irq_set_chip(i, &iop13xx_irqchip4); - set_irq_handler(i, handle_level_irq); + irq_set_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c index c9c02e3698b..560d5b2dec2 100644 --- a/arch/arm/mach-iop13xx/msi.c +++ b/arch/arm/mach-iop13xx/msi.c @@ -118,7 +118,7 @@ static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc) void __init iop13xx_msi_init(void) { - set_irq_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); + irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); } /* @@ -178,7 +178,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) if (irq < 0) return irq; - set_irq_msi(irq, desc); + irq_set_msi_desc(irq, desc); msg.address_hi = 0x0; msg.address_lo = IOP13XX_MU_MIMR_PCI; @@ -187,7 +187,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f); write_msi_msg(irq, &msg); - set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); + irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); return 0; } diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index 773ea0c95b9..ba3dae352a2 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c @@ -225,7 +225,7 @@ static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where) /* This routine checks the status of the last configuration cycle. If an error * was detected it returns >0, else it returns a 0. The errors being checked * are parity, master abort, target abort (master and target). These types of - * errors occure during a config cycle where there is no device, like during + * errors occur during a config cycle where there is no device, like during * the discovery stage. */ static int iop13xx_atux_pci_status(int clear) @@ -332,7 +332,7 @@ static struct pci_ops iop13xx_atux_ops = { /* This routine checks the status of the last configuration cycle. If an error * was detected it returns >0, else it returns a 0. The errors being checked * are parity, master abort, target abort (master and target). These types of - * errors occure during a config cycle where there is no device, like during + * errors occur during a config cycle where there is no device, like during * the discovery stage. */ static int iop13xx_atue_pci_status(int clear) diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index d3426a12059..d7ee2789d89 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -68,8 +68,7 @@ void __init iop32x_init_irq(void) *IOP3XX_PCIIRSR = 0x0f; for (i = 0; i < NR_IRQS; i++) { - set_irq_chip(i, &ext_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &ext_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index 0ff2f74363a..f7f5d3e451c 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c @@ -110,8 +110,9 @@ void __init iop33x_init_irq(void) *IOP3XX_PCIIRSR = 0x0f; for (i = 0; i < NR_IRQS; i++) { - set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, + (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2, + handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c index 5fc4e064b65..4068166c899 100644 --- a/arch/arm/mach-ixp2000/core.c +++ b/arch/arm/mach-ixp2000/core.c @@ -476,8 +476,8 @@ void __init ixp2000_init_irq(void) */ for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) { if ((1 << irq) & IXP2000_VALID_IRQ_MASK) { - set_irq_chip(irq, &ixp2000_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixp2000_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } else set_irq_flags(irq, 0); } @@ -485,21 +485,21 @@ void __init ixp2000_init_irq(void) for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) { if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) & IXP2000_VALID_ERR_IRQ_MASK) { - set_irq_chip(irq, &ixp2000_err_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } else set_irq_flags(irq, 0); } - set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler); + irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler); for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) { - set_irq_chip(irq, &ixp2000_GPIO_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } - set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); + irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); /* * Enable PCI irqs. The actual PCI[AB] decoding is done in @@ -508,8 +508,8 @@ void __init ixp2000_init_irq(void) */ ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI)); for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) { - set_irq_chip(irq, &ixp2000_pci_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } } diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c index 7d90d3f13ee..235638f800e 100644 --- a/arch/arm/mach-ixp2000/ixdp2x00.c +++ b/arch/arm/mach-ixp2000/ixdp2x00.c @@ -158,13 +158,13 @@ void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigne *board_irq_mask = 0xffffffff; for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) { - set_irq_chip(irq, &ixdp2x00_cpld_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixdp2x00_cpld_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } /* Hook into PCI interrupt */ - set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler); + irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler); } /************************************************************************* diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c index 34b1b2af37c..84835b20955 100644 --- a/arch/arm/mach-ixp2000/ixdp2x01.c +++ b/arch/arm/mach-ixp2000/ixdp2x01.c @@ -115,8 +115,8 @@ void __init ixdp2x01_init_irq(void) for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) { if (irq & valid_irq_mask) { - set_irq_chip(irq, &ixdp2x01_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixdp2x01_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } else { set_irq_flags(irq, 0); @@ -124,7 +124,7 @@ void __init ixdp2x01_init_irq(void) } /* Hook into PCI interrupts */ - set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler); + irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler); } diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c index 9c8a3390321..a1bee33d183 100644 --- a/arch/arm/mach-ixp23xx/core.c +++ b/arch/arm/mach-ixp23xx/core.c @@ -289,12 +289,12 @@ static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type) { switch (type) { case IXP23XX_IRQ_LEVEL: - set_irq_chip(irq, &ixp23xx_irq_level_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixp23xx_irq_level_chip, + handle_level_irq); break; case IXP23XX_IRQ_EDGE: - set_irq_chip(irq, &ixp23xx_irq_edge_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &ixp23xx_irq_edge_chip, + handle_edge_irq); break; } set_irq_flags(irq, IRQF_VALID); @@ -324,12 +324,12 @@ void __init ixp23xx_init_irq(void) } for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) { - set_irq_chip(irq, &ixp23xx_pci_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixp23xx_pci_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } - set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler); + irq_set_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler); } diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c index 181116aa659..8dcba17c81e 100644 --- a/arch/arm/mach-ixp23xx/ixdp2351.c +++ b/arch/arm/mach-ixp23xx/ixdp2351.c @@ -136,8 +136,8 @@ void __init ixdp2351_init_irq(void) irq++) { if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) { set_irq_flags(irq, IRQF_VALID); - set_irq_handler(irq, handle_level_irq); - set_irq_chip(irq, &ixdp2351_inta_chip); + irq_set_chip_and_handler(irq, &ixdp2351_inta_chip, + handle_level_irq); } } @@ -147,13 +147,13 @@ void __init ixdp2351_init_irq(void) irq++) { if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) { set_irq_flags(irq, IRQF_VALID); - set_irq_handler(irq, handle_level_irq); - set_irq_chip(irq, &ixdp2351_intb_chip); + irq_set_chip_and_handler(irq, &ixdp2351_intb_chip, + handle_level_irq); } } - set_irq_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler); - set_irq_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler); + irq_set_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler); + irq_set_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler); } /* diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c index 76c61ba7321..8fe0c627326 100644 --- a/arch/arm/mach-ixp23xx/roadrunner.c +++ b/arch/arm/mach-ixp23xx/roadrunner.c @@ -110,8 +110,8 @@ static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) static void __init roadrunner_pci_preinit(void) { - set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW); ixp23xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c index 845e1b50054..162043ff29f 100644 --- a/arch/arm/mach-ixp4xx/avila-pci.c +++ b/arch/arm/mach-ixp4xx/avila-pci.c @@ -39,10 +39,10 @@ void __init avila_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 9fd894271d5..ed19bc31431 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -252,8 +252,8 @@ void __init ixp4xx_init_irq(void) /* Default to all level triggered */ for(i = 0; i < NR_IRQS; i++) { - set_irq_chip(i, &ixp4xx_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &ixp4xx_irq_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } } diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c index b978ea8bd6f..37fda7d6e83 100644 --- a/arch/arm/mach-ixp4xx/coyote-pci.c +++ b/arch/arm/mach-ixp4xx/coyote-pci.c @@ -32,8 +32,8 @@ void __init coyote_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c index fa70fed462b..c7612010b3f 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-pci.c +++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c @@ -35,12 +35,12 @@ void __init dsmg600_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c index 5a810c93062..44ccde9d487 100644 --- a/arch/arm/mach-ixp4xx/fsg-pci.c +++ b/arch/arm/mach-ixp4xx/fsg-pci.c @@ -32,9 +32,9 @@ void __init fsg_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/gateway7001-pci.c b/arch/arm/mach-ixp4xx/gateway7001-pci.c index 7e93a0975c4..fc112416887 100644 --- a/arch/arm/mach-ixp4xx/gateway7001-pci.c +++ b/arch/arm/mach-ixp4xx/gateway7001-pci.c @@ -29,8 +29,8 @@ void __init gateway7001_pci_preinit(void) { - set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c index d0e4861ac03..3e8c0e33b59 100644 --- a/arch/arm/mach-ixp4xx/goramo_mlr.c +++ b/arch/arm/mach-ixp4xx/goramo_mlr.c @@ -420,8 +420,8 @@ static void __init gmlr_init(void) gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); + irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); + irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); set_control(CONTROL_HSS0_DTR_N, 1); set_control(CONTROL_HSS1_DTR_N, 1); @@ -441,10 +441,10 @@ static void __init gmlr_init(void) #ifdef CONFIG_PCI static void __init gmlr_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c index 25d2c333c20..38cc0725dbd 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c @@ -43,8 +43,8 @@ */ void __init gtwx5715_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c index 1ba165a6eda..58f400417ea 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c @@ -36,10 +36,10 @@ void __init ixdp425_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c index 4ed7ac61492..e64f6d04148 100644 --- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c @@ -25,8 +25,8 @@ void __init ixdpg425_pci_preinit(void) { - set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c index d0cea34cf61..428d1202b79 100644 --- a/arch/arm/mach-ixp4xx/nas100d-pci.c +++ b/arch/arm/mach-ixp4xx/nas100d-pci.c @@ -33,11 +33,11 @@ void __init nas100d_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c index 1eb5a90470b..2e85f76b950 100644 --- a/arch/arm/mach-ixp4xx/nslu2-pci.c +++ b/arch/arm/mach-ixp4xx/nslu2-pci.c @@ -32,9 +32,9 @@ void __init nslu2_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/vulcan-pci.c b/arch/arm/mach-ixp4xx/vulcan-pci.c index f3111c6840e..03bdec5140a 100644 --- a/arch/arm/mach-ixp4xx/vulcan-pci.c +++ b/arch/arm/mach-ixp4xx/vulcan-pci.c @@ -38,8 +38,8 @@ void __init vulcan_pci_preinit(void) pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n", (int)(pci_cardbus_mem_size >> 20)); #endif - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/wg302v2-pci.c b/arch/arm/mach-ixp4xx/wg302v2-pci.c index 9b59ed03b15..17f3cf59a31 100644 --- a/arch/arm/mach-ixp4xx/wg302v2-pci.c +++ b/arch/arm/mach-ixp4xx/wg302v2-pci.c @@ -29,8 +29,8 @@ void __init wg302v2_pci_preinit(void) { - set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c index cbdb5863d13..05d193a25b2 100644 --- a/arch/arm/mach-kirkwood/irq.c +++ b/arch/arm/mach-kirkwood/irq.c @@ -35,14 +35,15 @@ void __init kirkwood_init_irq(void) */ orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0, IRQ_KIRKWOOD_GPIO_START); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler); orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0, IRQ_KIRKWOOD_GPIO_START + 32); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, + gpio_irq_handler); } diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c index 0a95063f6d3..17de0bf53c0 100644 --- a/arch/arm/mach-kirkwood/sheevaplug-setup.c +++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c @@ -58,6 +58,12 @@ static struct mvsdio_platform_data sheeva_esata_mvsdio_data = { static struct gpio_led sheevaplug_led_pins[] = { { + .name = "plug:red:misc", + .default_trigger = "none", + .gpio = 46, + .active_low = 1, + }, + { .name = "plug:green:health", .default_trigger = "default-on", .gpio = 49, @@ -80,6 +86,7 @@ static struct platform_device sheevaplug_leds = { static unsigned int sheevaplug_mpp_config[] __initdata = { MPP29_GPIO, /* USB Power Enable */ + MPP46_GPIO, /* LED Red */ MPP49_GPIO, /* LED */ 0 }; diff --git a/arch/arm/mach-kirkwood/tsx1x-common.c b/arch/arm/mach-kirkwood/tsx1x-common.c index f781164e623..24294b2bc46 100644 --- a/arch/arm/mach-kirkwood/tsx1x-common.c +++ b/arch/arm/mach-kirkwood/tsx1x-common.c @@ -15,7 +15,7 @@ /**************************************************************************** * 16 MiB NOR flash. The struct mtd_partition is not in the same order as the - * partitions on the device because we want to keep compatability with + * partitions on the device because we want to keep compatibility with * the QNAP firmware. * Layout as used by QNAP: * 0x00000000-0x00080000 : "U-Boot" diff --git a/arch/arm/mach-ks8695/gpio.c b/arch/arm/mach-ks8695/gpio.c index 55fbf7111a5..31e456508a6 100644 --- a/arch/arm/mach-ks8695/gpio.c +++ b/arch/arm/mach-ks8695/gpio.c @@ -80,7 +80,7 @@ int ks8695_gpio_interrupt(unsigned int pin, unsigned int type) local_irq_restore(flags); /* Set IRQ triggering type */ - set_irq_type(gpio_irq[pin], type); + irq_set_irq_type(gpio_irq[pin], type); /* enable interrupt mode */ ks8695_gpio_mode(pin, 0); diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c index 7998ccaa633..a78092dcd6f 100644 --- a/arch/arm/mach-ks8695/irq.c +++ b/arch/arm/mach-ks8695/irq.c @@ -115,12 +115,12 @@ static int ks8695_irq_set_type(struct irq_data *d, unsigned int type) } if (level_triggered) { - set_irq_chip(d->irq, &ks8695_irq_level_chip); - set_irq_handler(d->irq, handle_level_irq); + irq_set_chip_and_handler(d->irq, &ks8695_irq_level_chip, + handle_level_irq); } else { - set_irq_chip(d->irq, &ks8695_irq_edge_chip); - set_irq_handler(d->irq, handle_edge_irq); + irq_set_chip_and_handler(d->irq, &ks8695_irq_edge_chip, + handle_edge_irq); } __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC); @@ -158,16 +158,18 @@ void __init ks8695_init_irq(void) case KS8695_IRQ_UART_RX: case KS8695_IRQ_COMM_TX: case KS8695_IRQ_COMM_RX: - set_irq_chip(irq, &ks8695_irq_level_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, + &ks8695_irq_level_chip, + handle_level_irq); break; /* Edge-triggered interrupts */ default: /* clear pending bit */ ks8695_irq_ack(irq_get_irq_data(irq)); - set_irq_chip(irq, &ks8695_irq_edge_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, + &ks8695_irq_edge_chip, + handle_edge_irq); } set_irq_flags(irq, IRQF_VALID); diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c index 316ecbf6c58..4eae566dfdc 100644 --- a/arch/arm/mach-lpc32xx/irq.c +++ b/arch/arm/mach-lpc32xx/irq.c @@ -290,7 +290,7 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type) } /* Ok to use the level handler for all types */ - set_irq_handler(d->irq, handle_level_irq); + irq_set_handler(d->irq, handle_level_irq); return 0; } @@ -390,8 +390,8 @@ void __init lpc32xx_init_irq(void) /* Configure supported IRQ's */ for (i = 0; i < NR_IRQS; i++) { - set_irq_chip(i, &lpc32xx_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &lpc32xx_irq_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } @@ -406,8 +406,8 @@ void __init lpc32xx_init_irq(void) __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); /* MIC SUBIRQx interrupts will route handling to the chain handlers */ - set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler); - set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler); + irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler); + irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler); /* Initially disable all wake events */ __raw_writel(0, LPC32XX_CLKPWR_P01_ER); diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c index e76d41bb705..b9c80597b7b 100644 --- a/arch/arm/mach-lpc32xx/pm.c +++ b/arch/arm/mach-lpc32xx/pm.c @@ -41,7 +41,7 @@ * DRAM clocking and refresh are slightly different for systems with DDR * DRAM or regular SDRAM devices. If SDRAM is used in the system, the * SDRAM will still be accessible in direct-run mode. In DDR based systems, - * a transistion to direct-run mode will stop all DDR accesses (no clocks). + * a transition to direct-run mode will stop all DDR accesses (no clocks). * Because of this, the code to switch power modes and the code to enter * and exit DRAM self-refresh modes must not be executed in DRAM. A small * section of IRAM is used instead for this. diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h index ee8b02ed801..7bfb827f3fe 100644 --- a/arch/arm/mach-mmp/include/mach/gpio.h +++ b/arch/arm/mach-mmp/include/mach/gpio.h @@ -10,7 +10,7 @@ #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) #define GPIO_REG(x) (*((volatile u32 *)(GPIO_REGS_VIRT + (x)))) -#define NR_BUILTIN_GPIO (192) +#define NR_BUILTIN_GPIO IRQ_GPIO_NUM #define gpio_to_bank(gpio) ((gpio) >> 5) #define gpio_to_irq(gpio) (IRQ_GPIO_START + (gpio)) diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h index 4621067c772..713be155a44 100644 --- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h @@ -8,6 +8,15 @@ #define MFP_DRIVE_MEDIUM (0x2 << 13) #define MFP_DRIVE_FAST (0x3 << 13) +#undef MFP_CFG +#undef MFP_CFG_DRV + +#define MFP_CFG(pin, af) \ + (MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM) + +#define MFP_CFG_DRV(pin, af, drv) \ + (MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv) + /* GPIO */ #define GPIO0_GPIO MFP_CFG(GPIO0, AF5) #define GPIO1_GPIO MFP_CFG(GPIO1, AF5) diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h index 4aec493640b..2cbf6df09b8 100644 --- a/arch/arm/mach-mmp/include/mach/mmp2.h +++ b/arch/arm/mach-mmp/include/mach/mmp2.h @@ -11,8 +11,8 @@ extern void __init mmp2_init_irq(void); extern void mmp2_clear_pmic_int(void); #include <linux/i2c.h> +#include <linux/i2c/pxa-i2c.h> #include <mach/devices.h> -#include <plat/i2c.h> extern struct pxa_device_desc mmp2_device_uart1; extern struct pxa_device_desc mmp2_device_uart2; diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h index 1801e420623..a52b3d2f325 100644 --- a/arch/arm/mach-mmp/include/mach/pxa168.h +++ b/arch/arm/mach-mmp/include/mach/pxa168.h @@ -8,8 +8,8 @@ extern void __init pxa168_init_irq(void); extern void pxa168_clear_keypad_wakeup(void); #include <linux/i2c.h> +#include <linux/i2c/pxa-i2c.h> #include <mach/devices.h> -#include <plat/i2c.h> #include <plat/pxa3xx_nand.h> #include <video/pxa168fb.h> #include <plat/pxa27x_keypad.h> diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h index f13c49d6f8d..91be7559139 100644 --- a/arch/arm/mach-mmp/include/mach/pxa910.h +++ b/arch/arm/mach-mmp/include/mach/pxa910.h @@ -7,8 +7,8 @@ extern struct sys_timer pxa910_timer; extern void __init pxa910_init_irq(void); #include <linux/i2c.h> +#include <linux/i2c/pxa-i2c.h> #include <mach/devices.h> -#include <plat/i2c.h> #include <plat/pxa3xx_nand.h> extern struct pxa_device_desc pxa910_device_uart1; diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c index fa037038e7b..d21c5441a3d 100644 --- a/arch/arm/mach-mmp/irq-mmp2.c +++ b/arch/arm/mach-mmp/irq-mmp2.c @@ -110,9 +110,9 @@ static void init_mux_irq(struct irq_chip *chip, int start, int num) if (chip->irq_ack) chip->irq_ack(d); - set_irq_chip(irq, chip); + irq_set_chip(irq, chip); set_irq_flags(irq, IRQF_VALID); - set_irq_handler(irq, handle_level_irq); + irq_set_handler(irq, handle_level_irq); } } @@ -122,7 +122,7 @@ void __init mmp2_init_icu(void) for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) { icu_mask_irq(irq_get_irq_data(irq)); - set_irq_chip(irq, &icu_irq_chip); + irq_set_chip(irq, &icu_irq_chip); set_irq_flags(irq, IRQF_VALID); switch (irq) { @@ -133,7 +133,7 @@ void __init mmp2_init_icu(void) case IRQ_MMP2_SSP_MUX: break; default: - set_irq_handler(irq, handle_level_irq); + irq_set_handler(irq, handle_level_irq); break; } } @@ -149,9 +149,9 @@ void __init mmp2_init_icu(void) init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15); init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2); - set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux); - set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux); - set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux); - set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux); - set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux); + irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux); + irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux); + irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux); + irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux); + irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux); } diff --git a/arch/arm/mach-mmp/irq-pxa168.c b/arch/arm/mach-mmp/irq-pxa168.c index f86b450cb93..89706a0d08f 100644 --- a/arch/arm/mach-mmp/irq-pxa168.c +++ b/arch/arm/mach-mmp/irq-pxa168.c @@ -48,8 +48,7 @@ void __init icu_init_irq(void) for (irq = 0; irq < 64; irq++) { icu_mask_irq(irq_get_irq_data(irq)); - set_irq_chip(irq, &icu_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } } diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index aeb9ae23e6c..99833b9485c 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -9,7 +9,7 @@ * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com> * 2008-10-08: Bin Yang <bin.yang@marvell.com> * - * The timers module actually includes three timers, each timer with upto + * The timers module actually includes three timers, each timer with up to * three match comparators. Timer #0 is used here in free-running mode as * the clock source, and match comparator #1 used as clock event device. * diff --git a/arch/arm/mach-msm/acpuclock-arm11.c b/arch/arm/mach-msm/acpuclock-arm11.c index 7ffbd987eb5..805d4ee53f7 100644 --- a/arch/arm/mach-msm/acpuclock-arm11.c +++ b/arch/arm/mach-msm/acpuclock-arm11.c @@ -343,7 +343,7 @@ int acpuclk_set_rate(unsigned long rate, int for_power_collapse) } } - /* Set wait states for CPU inbetween frequency changes */ + /* Set wait states for CPU between frequency changes */ reg_clkctl = readl(A11S_CLK_CNTL_ADDR); reg_clkctl |= (100 << 16); /* set WT_ST_CNT */ writel(reg_clkctl, A11S_CLK_CNTL_ADDR); diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c index 1993721d472..35c7ceeb3f2 100644 --- a/arch/arm/mach-msm/board-msm8960.c +++ b/arch/arm/mach-msm/board-msm8960.c @@ -53,7 +53,7 @@ static void __init msm8960_init_irq(void) */ for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) - set_irq_handler(i, handle_percpu_irq); + irq_set_handler(i, handle_percpu_irq); } } diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index b3c55f138fc..1163b6fd05d 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c @@ -56,7 +56,7 @@ static void __init msm8x60_init_irq(void) */ for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) - set_irq_handler(i, handle_percpu_irq); + irq_set_handler(i, handle_percpu_irq); } } diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index 7f568611547..6a96911b0ad 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -160,10 +160,7 @@ static struct msm_mmc_platform_data qsd8x50_sdc1_data = { static void __init qsd8x50_init_mmc(void) { - if (machine_is_qsd8x50_ffa() || machine_is_qsd8x50a_ffa()) - vreg_mmc = vreg_get(NULL, "gp6"); - else - vreg_mmc = vreg_get(NULL, "gp5"); + vreg_mmc = vreg_get(NULL, "gp5"); if (IS_ERR(vreg_mmc)) { pr_err("vreg get for vreg_mmc failed (%ld)\n", diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c index 31117a4499c..87e1d01edec 100644 --- a/arch/arm/mach-msm/board-trout-gpio.c +++ b/arch/arm/mach-msm/board-trout-gpio.c @@ -214,17 +214,17 @@ int __init trout_init_gpio(void) { int i; for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) { - set_irq_chip(i, &trout_gpio_irq_chip); - set_irq_handler(i, handle_edge_irq); + irq_set_chip_and_handler(i, &trout_gpio_irq_chip, + handle_edge_irq); set_irq_flags(i, IRQF_VALID); } for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++) gpiochip_add(&msm_gpio_banks[i].chip); - set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH); - set_irq_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler); - set_irq_wake(MSM_GPIO_TO_INT(17), 1); + irq_set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH); + irq_set_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler); + irq_set_irq_wake(MSM_GPIO_TO_INT(17), 1); return 0; } diff --git a/arch/arm/mach-msm/board-trout-mmc.c b/arch/arm/mach-msm/board-trout-mmc.c index 44be8464657..f7a9724788b 100644 --- a/arch/arm/mach-msm/board-trout-mmc.c +++ b/arch/arm/mach-msm/board-trout-mmc.c @@ -174,7 +174,7 @@ int __init trout_init_mmc(unsigned int sys_rev) if (IS_ERR(vreg_sdslot)) return PTR_ERR(vreg_sdslot); - set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1); + irq_set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1); if (!opt_disable_sdcard) msm_add_sdcc(2, &trout_sdslot_data, diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c index 0de19ec74e3..56a964e52ad 100644 --- a/arch/arm/mach-msm/gpio-v2.c +++ b/arch/arm/mach-msm/gpio-v2.c @@ -230,18 +230,18 @@ static void msm_gpio_update_dual_edge_pos(unsigned gpio) val, val2); } -static void msm_gpio_irq_ack(unsigned int irq) +static void msm_gpio_irq_ack(struct irq_data *d) { - int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio)); if (test_bit(gpio, msm_gpio.dual_edge_irqs)) msm_gpio_update_dual_edge_pos(gpio); } -static void msm_gpio_irq_mask(unsigned int irq) +static void msm_gpio_irq_mask(struct irq_data *d) { - int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); unsigned long irq_flags; spin_lock_irqsave(&tlmm_lock, irq_flags); @@ -251,9 +251,9 @@ static void msm_gpio_irq_mask(unsigned int irq) spin_unlock_irqrestore(&tlmm_lock, irq_flags); } -static void msm_gpio_irq_unmask(unsigned int irq) +static void msm_gpio_irq_unmask(struct irq_data *d) { - int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); unsigned long irq_flags; spin_lock_irqsave(&tlmm_lock, irq_flags); @@ -263,9 +263,9 @@ static void msm_gpio_irq_unmask(unsigned int irq) spin_unlock_irqrestore(&tlmm_lock, irq_flags); } -static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) +static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type) { - int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); unsigned long irq_flags; uint32_t bits; @@ -275,14 +275,14 @@ static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) if (flow_type & IRQ_TYPE_EDGE_BOTH) { bits |= BIT(INTR_DECT_CTL); - irq_desc[irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(d->irq, handle_edge_irq); if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) __set_bit(gpio, msm_gpio.dual_edge_irqs); else __clear_bit(gpio, msm_gpio.dual_edge_irqs); } else { bits &= ~BIT(INTR_DECT_CTL); - irq_desc[irq].handle_irq = handle_level_irq; + __irq_set_handler_locked(d->irq, handle_level_irq); __clear_bit(gpio, msm_gpio.dual_edge_irqs); } @@ -309,6 +309,7 @@ static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) */ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) { + struct irq_data *data = irq_desc_get_irq_data(desc); unsigned long i; for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS); @@ -318,21 +319,21 @@ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip, i)); } - desc->chip->ack(irq); + data->chip->irq_ack(data); } -static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) +static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) { - int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); if (on) { if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) - set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); + irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); set_bit(gpio, msm_gpio.wake_irqs); } else { clear_bit(gpio, msm_gpio.wake_irqs); if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) - set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); + irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); } return 0; @@ -340,11 +341,11 @@ static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) static struct irq_chip msm_gpio_irq_chip = { .name = "msmgpio", - .mask = msm_gpio_irq_mask, - .unmask = msm_gpio_irq_unmask, - .ack = msm_gpio_irq_ack, - .set_type = msm_gpio_irq_set_type, - .set_wake = msm_gpio_irq_set_wake, + .irq_mask = msm_gpio_irq_mask, + .irq_unmask = msm_gpio_irq_unmask, + .irq_ack = msm_gpio_irq_ack, + .irq_set_type = msm_gpio_irq_set_type, + .irq_set_wake = msm_gpio_irq_set_wake, }; static int __devinit msm_gpio_probe(struct platform_device *dev) @@ -361,12 +362,12 @@ static int __devinit msm_gpio_probe(struct platform_device *dev) for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) { irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i); - set_irq_chip(irq, &msm_gpio_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } - set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ, + irq_set_chained_handler(TLMM_SCSS_SUMMARY_IRQ, msm_summary_irq_handler); return 0; } @@ -378,7 +379,7 @@ static int __devexit msm_gpio_remove(struct platform_device *dev) if (ret < 0) return ret; - set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); + irq_set_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); return 0; } diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c index 176af9dcb8e..5ea273b00da 100644 --- a/arch/arm/mach-msm/gpio.c +++ b/arch/arm/mach-msm/gpio.c @@ -293,10 +293,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type) val = readl(msm_chip->regs.int_edge); if (flow_type & IRQ_TYPE_EDGE_BOTH) { writel(val | mask, msm_chip->regs.int_edge); - irq_desc[d->irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(d->irq, handle_edge_irq); } else { writel(val & ~mask, msm_chip->regs.int_edge); - irq_desc[d->irq].handle_irq = handle_level_irq; + __irq_set_handler_locked(d->irq, handle_level_irq); } if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { msm_chip->both_edge_detect |= mask; @@ -354,9 +354,9 @@ static int __init msm_init_gpio(void) msm_gpio_chips[j].chip.base + msm_gpio_chips[j].chip.ngpio) j++; - set_irq_chip_data(i, &msm_gpio_chips[j]); - set_irq_chip(i, &msm_gpio_irq_chip); - set_irq_handler(i, handle_edge_irq); + irq_set_chip_data(i, &msm_gpio_chips[j]); + irq_set_chip_and_handler(i, &msm_gpio_irq_chip, + handle_edge_irq); set_irq_flags(i, IRQF_VALID); } @@ -366,10 +366,10 @@ static int __init msm_init_gpio(void) gpiochip_add(&msm_gpio_chips[i].chip); } - set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); - set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); - set_irq_wake(INT_GPIO_GROUP1, 1); - set_irq_wake(INT_GPIO_GROUP2, 2); + irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); + irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); + irq_set_irq_wake(INT_GPIO_GROUP1, 1); + irq_set_irq_wake(INT_GPIO_GROUP2, 2); return 0; } diff --git a/arch/arm/mach-msm/irq-vic.c b/arch/arm/mach-msm/irq-vic.c index 68c28bbdc96..1b54f807c2d 100644 --- a/arch/arm/mach-msm/irq-vic.c +++ b/arch/arm/mach-msm/irq-vic.c @@ -313,11 +313,11 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type) type = msm_irq_shadow_reg[index].int_type; if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { type |= b; - irq_desc[d->irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(d->irq, handle_edge_irq); } if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { type &= ~b; - irq_desc[d->irq].handle_irq = handle_level_irq; + __irq_set_handler_locked(d->irq, handle_level_irq); } writel(type, treg); msm_irq_shadow_reg[index].int_type = type; @@ -357,8 +357,7 @@ void __init msm_init_irq(void) writel(3, VIC_INT_MASTEREN); for (n = 0; n < NR_MSM_IRQS; n++) { - set_irq_chip(n, &msm_irq_chip); - set_irq_handler(n, handle_level_irq); + irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq); set_irq_flags(n, IRQF_VALID); } } diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c index 0b27d899f40..ea514be390c 100644 --- a/arch/arm/mach-msm/irq.c +++ b/arch/arm/mach-msm/irq.c @@ -100,11 +100,11 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type) if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { writel(readl(treg) | b, treg); - irq_desc[d->irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(d->irq, handle_edge_irq); } if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { writel(readl(treg) & (~b), treg); - irq_desc[d->irq].handle_irq = handle_level_irq; + __irq_set_handler_locked(d->irq, handle_level_irq); } return 0; } @@ -145,8 +145,7 @@ void __init msm_init_irq(void) writel(1, VIC_INT_MASTEREN); for (n = 0; n < NR_MSM_IRQS; n++) { - set_irq_chip(n, &msm_irq_chip); - set_irq_handler(n, handle_level_irq); + irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq); set_irq_flags(n, IRQF_VALID); } } diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-msm/scm.c index cfa808dd489..232f97a0450 100644 --- a/arch/arm/mach-msm/scm.c +++ b/arch/arm/mach-msm/scm.c @@ -46,7 +46,7 @@ static DEFINE_MUTEX(scm_lock); * @id: command to be executed * @buf: buffer returned from scm_get_command_buffer() * - * An SCM command is layed out in memory as follows: + * An SCM command is laid out in memory as follows: * * ------------------- <--- struct scm_command * | command header | diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c index 11b54c7aeb0..689e78c95f3 100644 --- a/arch/arm/mach-msm/sirc.c +++ b/arch/arm/mach-msm/sirc.c @@ -105,10 +105,10 @@ static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type) val = readl(sirc_regs.int_type); if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { val |= mask; - irq_desc[d->irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(d->irq, handle_edge_irq); } else { val &= ~mask; - irq_desc[d->irq].handle_irq = handle_level_irq; + __irq_set_handler_locked(d->irq, handle_level_irq); } writel(val, sirc_regs.int_type); @@ -158,15 +158,14 @@ void __init msm_init_sirc(void) wake_enable = 0; for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) { - set_irq_chip(i, &sirc_irq_chip); - set_irq_handler(i, handle_edge_irq); + irq_set_chip_and_handler(i, &sirc_irq_chip, handle_edge_irq); set_irq_flags(i, IRQF_VALID); } for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) { - set_irq_chained_handler(sirc_reg_table[i].cascade_irq, + irq_set_chained_handler(sirc_reg_table[i].cascade_irq, sirc_irq_handler); - set_irq_wake(sirc_reg_table[i].cascade_irq, 1); + irq_set_irq_wake(sirc_reg_table[i].cascade_irq, 1); } return; } diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index e7f8e5a4d48..38b95e949d1 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -263,13 +263,13 @@ static void __init msm_timer_init(void) } #ifdef CONFIG_SMP -void __cpuinit local_timer_setup(struct clock_event_device *evt) +int __cpuinit local_timer_setup(struct clock_event_device *evt) { struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER]; /* Use existing clock_event for cpu 0 */ if (!smp_processor_id()) - return; + return 0; writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); @@ -295,6 +295,7 @@ void __cpuinit local_timer_setup(struct clock_event_device *evt) gic_enable_ppi(clock->irq.irq); clockevents_register_device(evt); + return 0; } inline int local_timer_ack(void) diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index 08da497c39c..3e24431bb5e 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c @@ -38,8 +38,8 @@ void __init mv78xx0_init_irq(void) orion_gpio_init(0, 32, GPIO_VIRT_BASE, mv78xx0_core_index() ? 0x18 : 0, IRQ_MV78XX0_GPIO_START); - set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); - set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); - set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); - set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler); + irq_set_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); + irq_set_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); + irq_set_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); + irq_set_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler); } diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c index 80761474c0f..2e288b38b4a 100644 --- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c @@ -43,6 +43,7 @@ #include <mach/ipu.h> #include <mach/mx3fb.h> #include <mach/audmux.h> +#include <mach/esdhc.h> #include "devices-imx35.h" #include "devices.h" @@ -163,11 +164,14 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { MX35_PAD_SD1_DATA1__ESDHC1_DAT1, MX35_PAD_SD1_DATA2__ESDHC1_DAT2, MX35_PAD_SD1_DATA3__ESDHC1_DAT3, + /* SD1 CD */ + MX35_PAD_LD18__GPIO3_24, }; #define GPIO_LED1 IMX_GPIO_NR(3, 29) #define GPIO_SWITCH1 IMX_GPIO_NR(3, 25) -#define GPIO_LCDPWR (4) +#define GPIO_LCDPWR IMX_GPIO_NR(1, 4) +#define GPIO_SD1CD IMX_GPIO_NR(3, 24) static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd, unsigned int power) @@ -254,6 +258,11 @@ struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = { .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, }; +static struct esdhc_platform_data sd1_pdata = { + .cd_gpio = GPIO_SD1CD, + .wp_gpio = -EINVAL, +}; + /* * system init for baseboard usage. Will be called by cpuimx35 init. * @@ -289,7 +298,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void) imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); imx35_add_flexcan1(NULL); - imx35_add_sdhci_esdhc_imx(0, NULL); + imx35_add_sdhci_esdhc_imx(0, &sd1_pdata); gpio_request(GPIO_LED1, "LED1"); gpio_direction_output(GPIO_LED1, 1); @@ -301,7 +310,6 @@ void __init eukrea_mbimxsd35_baseboard_init(void) gpio_request(GPIO_LCDPWR, "LCDPWR"); gpio_direction_output(GPIO_LCDPWR, 1); - gpio_free(GPIO_LCDPWR); i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices, ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index 544d3e414f5..034be624d35 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -488,10 +488,12 @@ static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = { }; /* MC13783 */ -static struct mc13xxx_platform_data mc13783_pdata __initdata = { - .regulators = mx31_3ds_regulators, - .num_regulators = ARRAY_SIZE(mx31_3ds_regulators), - .flags = MC13XXX_USE_REGULATOR | MC13XXX_USE_TOUCHSCREEN +static struct mc13xxx_platform_data mc13783_pdata = { + .regulators = { + .regulators = mx31_3ds_regulators, + .num_regulators = ARRAY_SIZE(mx31_3ds_regulators), + }, + .flags = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN, }; /* SPI */ diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index 4e4b780c481..3d095d69bc6 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c @@ -199,12 +199,11 @@ static void __init mx31ads_init_expio(void) __raw_writew(0xFFFF, PBC_INTSTATUS_REG); for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) { - set_irq_chip(i, &expio_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID); } - set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH); - set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler); + irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH); + irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler); } #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index 6f3692bccb8..3a021b01161 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c @@ -268,8 +268,10 @@ static struct mc13783_leds_platform_data moboard_leds = { }; static struct mc13xxx_platform_data moboard_pmic = { - .regulators = moboard_regulators, - .num_regulators = ARRAY_SIZE(moboard_regulators), + .regulators = { + .regulators = moboard_regulators, + .num_regulators = ARRAY_SIZE(moboard_regulators), + }, .leds = &moboard_leds, .flags = MC13XXX_USE_REGULATOR | MC13XXX_USE_RTC | MC13XXX_USE_ADC | MC13XXX_USE_LED, diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index b3ecfb22d24..036ba1a4704 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -40,6 +40,7 @@ #include <mach/mx3fb.h> #include <mach/ulpi.h> #include <mach/audmux.h> +#include <mach/esdhc.h> #include "devices-imx35.h" #include "devices.h" @@ -217,11 +218,15 @@ static iomux_v3_cfg_t pcm043_pads[] = { MX35_PAD_SD1_DATA1__ESDHC1_DAT1, MX35_PAD_SD1_DATA2__ESDHC1_DAT2, MX35_PAD_SD1_DATA3__ESDHC1_DAT3, + MX35_PAD_ATA_DATA10__GPIO2_23, /* WriteProtect */ + MX35_PAD_ATA_DATA11__GPIO2_24, /* CardDetect */ }; #define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31) #define AC97_GPIO_TXD IMX_GPIO_NR(2, 28) #define AC97_GPIO_RESET IMX_GPIO_NR(2, 0) +#define SD1_GPIO_WP IMX_GPIO_NR(2, 23) +#define SD1_GPIO_CD IMX_GPIO_NR(2, 24) static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) { @@ -346,6 +351,11 @@ static int __init pcm043_otg_mode(char *options) } __setup("otg_mode=", pcm043_otg_mode); +static struct esdhc_platform_data sd1_pdata = { + .wp_gpio = SD1_GPIO_WP, + .cd_gpio = SD1_GPIO_CD, +}; + /* * Board specific initialization. */ @@ -395,7 +405,7 @@ static void __init pcm043_init(void) imx35_add_fsl_usb2_udc(&otg_device_pdata); imx35_add_flexcan1(NULL); - imx35_add_sdhci_esdhc_imx(0, NULL); + imx35_add_sdhci_esdhc_imx(0, &sd1_pdata); } static void __init pcm043_timer_init(void) diff --git a/arch/arm/mach-mx3/mach-vpr200.c b/arch/arm/mach-mx3/mach-vpr200.c index 2cf390fbd98..47a69cbc31a 100644 --- a/arch/arm/mach-mx3/mach-vpr200.c +++ b/arch/arm/mach-mx3/mach-vpr200.c @@ -257,11 +257,16 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .workaround = FLS_USB2_WORKAROUND_ENGCM09152, }; +static int vpr200_usbh_init(struct platform_device *pdev) +{ + return mx35_initialize_usb_hw(pdev->id, + MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY); +} + /* USB HOST config */ static const struct mxc_usbh_platform_data usb_host_pdata __initconst = { - .portsc = MXC_EHCI_MODE_SERIAL, - .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | - MXC_EHCI_INTERNAL_PHY, + .init = vpr200_usbh_init, + .portsc = MXC_EHCI_MODE_SERIAL, }; static struct platform_device *devices[] __initdata = { diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 83ee08847d4..159340da919 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -165,6 +165,7 @@ config MACH_MX53_LOCO select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select IMX_HAVE_PLATFORM_GPIO_KEYS help Include support for MX53 LOCO platform. This includes specific configurations for the board and its peripherals. diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 4f63048be3c..0b9338cec51 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -3,7 +3,7 @@ # # Object file lists. -obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o +obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o system.o obj-$(CONFIG_SOC_IMX50) += mm-mx50.o obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index b2ecd194e76..bea4e4135f9 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -228,13 +228,12 @@ static inline void babbage_fec_reset(void) int ret; /* reset FEC PHY */ - ret = gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset"); + ret = gpio_request_one(BABBAGE_FEC_PHY_RESET, + GPIOF_OUT_INIT_LOW, "fec-phy-reset"); if (ret) { printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); return; } - gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0); - gpio_set_value(BABBAGE_FEC_PHY_RESET, 0); msleep(1); gpio_set_value(BABBAGE_FEC_PHY_RESET, 1); } diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c index 7b5735c5ea5..2af3f43f74d 100644 --- a/arch/arm/mach-mx5/board-mx53_evk.c +++ b/arch/arm/mach-mx5/board-mx53_evk.c @@ -34,7 +34,7 @@ #include <mach/imx-uart.h> #include <mach/iomux-mx53.h> -#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) +#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6) #define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30) #define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) @@ -82,15 +82,14 @@ static inline void mx53_evk_fec_reset(void) int ret; /* reset FEC PHY */ - ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset"); + ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW, + "fec-phy-reset"); if (ret) { printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); return; } - gpio_direction_output(SMD_FEC_PHY_RST, 0); - gpio_set_value(SMD_FEC_PHY_RST, 0); msleep(1); - gpio_set_value(SMD_FEC_PHY_RST, 1); + gpio_set_value(MX53_EVK_FEC_PHY_RST, 1); } static struct fec_platform_data mx53_evk_fec_pdata = { diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c index 0a18f8d23eb..6206b1191fe 100644 --- a/arch/arm/mach-mx5/board-mx53_loco.c +++ b/arch/arm/mach-mx5/board-mx53_loco.c @@ -36,6 +36,9 @@ #include "crm_regs.h" #include "devices-imx53.h" +#define MX53_LOCO_POWER IMX_GPIO_NR(1, 8) +#define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14) +#define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15) #define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) static iomux_v3_cfg_t mx53_loco_pads[] = { @@ -180,6 +183,27 @@ static iomux_v3_cfg_t mx53_loco_pads[] = { MX53_PAD_GPIO_8__GPIO1_8, }; +#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ +{ \ + .gpio = gpio_num, \ + .type = EV_KEY, \ + .code = ev_code, \ + .active_low = act_low, \ + .desc = "btn " descr, \ + .wakeup = wake, \ +} + +static struct gpio_keys_button loco_buttons[] = { + GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0), + GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0), + GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0), +}; + +static const struct gpio_keys_platform_data loco_button_data __initconst = { + .buttons = loco_buttons, + .nbuttons = ARRAY_SIZE(loco_buttons), +}; + static inline void mx53_loco_fec_reset(void) { int ret; @@ -215,6 +239,7 @@ static void __init mx53_loco_board_init(void) imx53_add_imx_i2c(1, &mx53_loco_i2c_data); imx53_add_sdhci_esdhc_imx(0, NULL); imx53_add_sdhci_esdhc_imx(2, NULL); + imx_add_gpio_keys(&loco_button_data); } static void __init mx53_loco_timer_init(void) diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index 652ace41382..fdbc05ed551 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -865,6 +865,13 @@ static struct clk aips_tz2_clk = { .disable = _clk_ccgr_disable_inwait, }; +static struct clk gpc_dvfs_clk = { + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable, +}; + static struct clk gpt_32k_clk = { .id = 0, .parent = &ckil_clk, @@ -1448,6 +1455,7 @@ static struct clk_lookup mx51_lookups[] = { _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk) _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk) _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk) + _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk) }; static struct clk_lookup mx53_lookups[] = { @@ -1511,6 +1519,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, clk_enable(&iim_clk); mx51_revision(); clk_disable(&iim_clk); + mx51_display_revision(); /* move usb_phy_clk to 24MHz */ clk_set_parent(&usb_phy1_clk, &osc_clk); diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index df46b5e6085..472bdfab2e5 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c @@ -21,6 +21,7 @@ static int cpu_silicon_rev = -1; #define IIM_SREV 0x24 +#define MX50_HW_ADADIG_DIGPROG 0xB0 static int get_mx51_srev(void) { @@ -51,6 +52,26 @@ int mx51_revision(void) } EXPORT_SYMBOL(mx51_revision); +void mx51_display_revision(void) +{ + int rev; + char *srev; + rev = mx51_revision(); + + switch (rev) { + case IMX_CHIP_REVISION_2_0: + srev = IMX_CHIP_REVISION_2_0_STRING; + break; + case IMX_CHIP_REVISION_3_0: + srev = IMX_CHIP_REVISION_3_0_STRING; + break; + default: + srev = IMX_CHIP_REVISION_UNKNOWN_STRING; + } + printk(KERN_INFO "CPU identified as i.MX51, silicon rev %s\n", srev); +} +EXPORT_SYMBOL(mx51_display_revision); + #ifdef CONFIG_NEON /* @@ -107,6 +128,44 @@ int mx53_revision(void) } EXPORT_SYMBOL(mx53_revision); +static int get_mx50_srev(void) +{ + void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K); + u32 rev; + + if (!anatop) { + cpu_silicon_rev = -EINVAL; + return 0; + } + + rev = readl(anatop + MX50_HW_ADADIG_DIGPROG); + rev &= 0xff; + + iounmap(anatop); + if (rev == 0x0) + return IMX_CHIP_REVISION_1_0; + else if (rev == 0x1) + return IMX_CHIP_REVISION_1_1; + return 0; +} + +/* + * Returns: + * the silicon revision of the cpu + * -EINVAL - not a mx50 + */ +int mx50_revision(void) +{ + if (!cpu_is_mx50()) + return -EINVAL; + + if (cpu_silicon_rev == -1) + cpu_silicon_rev = get_mx50_srev(); + + return cpu_silicon_rev; +} +EXPORT_SYMBOL(mx50_revision); + static int __init post_cpu_init(void) { unsigned int reg; diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c index e83ffadb65f..4a8550529b0 100644 --- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c @@ -212,7 +212,7 @@ void __init eukrea_mbimx51_baseboard_init(void) gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq"); gpio_direction_input(MBIMX51_TSC2007_GPIO); - set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING); + irq_set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING); i2c_register_board_info(1, mbimx51_i2c_devices, ARRAY_SIZE(mbimx51_i2c_devices)); diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c index c372a437369..e6c1119c20a 100644 --- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c @@ -67,6 +67,10 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { MX51_PAD_SD1_DATA1__SD1_DATA1, MX51_PAD_SD1_DATA2__SD1_DATA2, MX51_PAD_SD1_DATA3__SD1_DATA3, + /* SD1 CD */ + _MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | + PAD_CTL_PKE | PAD_CTL_SRE_FAST | + PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), }; #define GPIO_LED1 IMX_GPIO_NR(3, 30) diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c index 51a67fc7f0e..d0c7075937c 100644 --- a/arch/arm/mach-mx5/mx51_efika.c +++ b/arch/arm/mach-mx5/mx51_efika.c @@ -42,7 +42,6 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> -#include <asm/mach-types.h> #include "devices-imx51.h" #include "devices.h" @@ -572,8 +571,10 @@ static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = { static struct mc13xxx_platform_data mx51_efika_mc13892_data = { .flags = MC13XXX_USE_RTC | MC13XXX_USE_REGULATOR, - .num_regulators = ARRAY_SIZE(mx51_efika_regulators), - .regulators = mx51_efika_regulators, + .regulators = { + .num_regulators = ARRAY_SIZE(mx51_efika_regulators), + .regulators = mx51_efika_regulators, + }, }; static struct spi_board_info mx51_efika_spi_board_info[] __initdata = { diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c new file mode 100644 index 00000000000..76ae8dc33e0 --- /dev/null +++ b/arch/arm/mach-mx5/system.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <linux/platform_device.h> +#include <linux/io.h> +#include <mach/hardware.h> +#include "crm_regs.h" + +/* set cpu low power mode before WFI instruction. This function is called + * mx5 because it can be used for mx50, mx51, and mx53.*/ +void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) +{ + u32 plat_lpc, arm_srpgcr, ccm_clpcr; + u32 empgc0, empgc1; + int stop_mode = 0; + + /* always allow platform to issue a deep sleep mode request */ + plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) & + ~(MXC_CORTEXA8_PLAT_LPC_DSM); + ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); + arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR); + empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR); + empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR); + + switch (mode) { + case WAIT_CLOCKED: + break; + case WAIT_UNCLOCKED: + ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; + break; + case WAIT_UNCLOCKED_POWER_OFF: + case STOP_POWER_OFF: + plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM + | MXC_CORTEXA8_PLAT_LPC_DBG_DSM; + if (mode == WAIT_UNCLOCKED_POWER_OFF) { + ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; + ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY; + ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS; + stop_mode = 0; + } else { + ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; + ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET; + ccm_clpcr |= MXC_CCM_CLPCR_VSTBY; + ccm_clpcr |= MXC_CCM_CLPCR_SBYOS; + stop_mode = 1; + } + arm_srpgcr |= MXC_SRPGCR_PCR; + + if (tzic_enable_wake(1) != 0) + return; + break; + case STOP_POWER_ON: + ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; + break; + default: + printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode); + return; + } + + __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC); + __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); + __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); + + /* Enable NEON SRPG for all but MX50TO1.0. */ + if (mx50_revision() != IMX_CHIP_REVISION_1_0) + __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); + + if (stop_mode) { + empgc0 |= MXC_SRPGCR_PCR; + empgc1 |= MXC_SRPGCR_PCR; + + __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR); + __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR); + } +} diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 4f6f174af6c..4522fbb235d 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -22,6 +22,7 @@ config MACH_MX23EVK select SOC_IMX23 select MXS_HAVE_AMBA_DUART select MXS_HAVE_PLATFORM_AUART + select MXS_HAVE_PLATFORM_MXS_MMC select MXS_HAVE_PLATFORM_MXSFB default y help @@ -35,6 +36,7 @@ config MACH_MX28EVK select MXS_HAVE_PLATFORM_AUART select MXS_HAVE_PLATFORM_FEC select MXS_HAVE_PLATFORM_FLEXCAN + select MXS_HAVE_PLATFORM_MXS_MMC select MXS_HAVE_PLATFORM_MXSFB select MXS_OCOTP default y diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c index d133c7f3094..c3577ea789a 100644 --- a/arch/arm/mach-mxs/clock-mx23.c +++ b/arch/arm/mach-mxs/clock-mx23.c @@ -521,6 +521,15 @@ static int clk_misc_init(void) __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET); + /* + * 480 MHz seems too high to be ssp clock source directly, + * so set frac to get a 288 MHz ref_io. + */ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC); + reg &= ~BM_CLKCTRL_FRAC_IOFRAC; + reg |= 30 << BP_CLKCTRL_FRAC_IOFRAC; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC); + return 0; } @@ -528,6 +537,12 @@ int __init mx23_clocks_init(void) { clk_misc_init(); + /* + * source ssp clock from ref_io than ref_xtal, + * as ref_xtal only provides 24 MHz as maximum. + */ + clk_set_parent(&ssp_clk, &ref_io_clk); + clk_enable(&cpu_clk); clk_enable(&hbus_clk); clk_enable(&xbus_clk); diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 5e489a2b202..5dcc59d5b9e 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -295,11 +295,11 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \ unsigned long diff, parent_rate, calc_rate; \ int i; \ \ - parent_rate = clk_get_rate(clk->parent); \ div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \ bm_busy = BM_CLKCTRL_##dr##_BUSY; \ \ if (clk->parent == &ref_xtal_clk) { \ + parent_rate = clk_get_rate(clk->parent); \ div = DIV_ROUND_UP(parent_rate, rate); \ if (clk == &cpu_clk) { \ div_max = BM_CLKCTRL_CPU_DIV_XTAL >> \ @@ -309,6 +309,11 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \ if (div == 0 || div > div_max) \ return -EINVAL; \ } else { \ + /* \ + * hack alert: this block modifies clk->parent, too, \ + * so the base to use it the grand parent. \ + */ \ + parent_rate = clk_get_rate(clk->parent->parent); \ rate >>= PARENT_RATE_SHIFT; \ parent_rate >>= PARENT_RATE_SHIFT; \ diff = parent_rate; \ @@ -618,6 +623,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("pll2", NULL, pll2_clk) _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk) _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk) + _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp0_clk) + _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp1_clk) _REGISTER_CLOCK("flexcan.0", NULL, can0_clk) _REGISTER_CLOCK("flexcan.1", NULL, can1_clk) _REGISTER_CLOCK(NULL, "usb0", usb0_clk) @@ -737,6 +744,15 @@ static int clk_misc_init(void) reg |= BM_CLKCTRL_ENET_CLK_OUT_EN; __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); + /* + * 480 MHz seems too high to be ssp clock source directly, + * so set frac0 to get a 288 MHz ref_io0. + */ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0); + reg &= ~BM_CLKCTRL_FRAC0_IO0FRAC; + reg |= 30 << BP_CLKCTRL_FRAC0_IO0FRAC; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0); + return 0; } @@ -744,6 +760,13 @@ int __init mx28_clocks_init(void) { clk_misc_init(); + /* + * source ssp clock from ref_io0 than ref_xtal, + * as ref_xtal only provides 24 MHz as maximum. + */ + clk_set_parent(&ssp0_clk, &ref_io0_clk); + clk_set_parent(&ssp1_clk, &ref_io0_clk); + clk_enable(&cpu_clk); clk_enable(&hbus_clk); clk_enable(&xbus_clk); diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h index c7e14f4e366..c6f345febd3 100644 --- a/arch/arm/mach-mxs/devices-mx23.h +++ b/arch/arm/mach-mxs/devices-mx23.h @@ -21,6 +21,10 @@ extern const struct mxs_auart_data mx23_auart_data[] __initconst; #define mx23_add_auart0() mx23_add_auart(0) #define mx23_add_auart1() mx23_add_auart(1) +extern const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst; +#define mx23_add_mxs_mmc(id, pdata) \ + mxs_add_mxs_mmc(&mx23_mxs_mmc_data[id], pdata) + #define mx23_add_mxs_pwm(id) mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id) struct platform_device *__init mx23_add_mxsfb( diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h index 9d08555c4cf..c473eddce8c 100644 --- a/arch/arm/mach-mxs/devices-mx28.h +++ b/arch/arm/mach-mxs/devices-mx28.h @@ -37,6 +37,10 @@ extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst; extern const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst; #define mx28_add_mxs_i2c(id) mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id]) +extern const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst; +#define mx28_add_mxs_mmc(id, pdata) \ + mxs_add_mxs_mmc(&mx28_mxs_mmc_data[id], pdata) + #define mx28_add_mxs_pwm(id) mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id) struct platform_device *__init mx28_add_mxsfb( diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig index 1451ad060d8..acf9eea124c 100644 --- a/arch/arm/mach-mxs/devices/Kconfig +++ b/arch/arm/mach-mxs/devices/Kconfig @@ -15,6 +15,9 @@ config MXS_HAVE_PLATFORM_FLEXCAN config MXS_HAVE_PLATFORM_MXS_I2C bool +config MXS_HAVE_PLATFORM_MXS_MMC + bool + config MXS_HAVE_PLATFORM_MXS_PWM bool diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile index 0d9bea30b0a..324f2824d38 100644 --- a/arch/arm/mach-mxs/devices/Makefile +++ b/arch/arm/mach-mxs/devices/Makefile @@ -4,5 +4,6 @@ obj-y += platform-dma.o obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o +obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_MMC) += platform-mxs-mmc.o obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o diff --git a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c new file mode 100644 index 00000000000..382dacbeca2 --- /dev/null +++ b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ + +#include <linux/compiler.h> +#include <linux/err.h> +#include <linux/init.h> + +#include <mach/mx23.h> +#include <mach/mx28.h> +#include <mach/devices-common.h> + +#define mxs_mxs_mmc_data_entry_single(soc, _id, hwid) \ + { \ + .id = _id, \ + .iobase = soc ## _SSP ## hwid ## _BASE_ADDR, \ + .dma = soc ## _DMA_SSP ## hwid, \ + .irq_err = soc ## _INT_SSP ## hwid ## _ERROR, \ + .irq_dma = soc ## _INT_SSP ## hwid ## _DMA, \ + } + +#define mxs_mxs_mmc_data_entry(soc, _id, hwid) \ + [_id] = mxs_mxs_mmc_data_entry_single(soc, _id, hwid) + + +#ifdef CONFIG_SOC_IMX23 +const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst = { + mxs_mxs_mmc_data_entry(MX23, 0, 1), + mxs_mxs_mmc_data_entry(MX23, 1, 2), +}; +#endif + +#ifdef CONFIG_SOC_IMX28 +const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst = { + mxs_mxs_mmc_data_entry(MX28, 0, 0), + mxs_mxs_mmc_data_entry(MX28, 1, 1), +}; +#endif + +struct platform_device *__init mxs_add_mxs_mmc( + const struct mxs_mxs_mmc_data *data, + const struct mxs_mmc_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->dma, + .end = data->dma, + .flags = IORESOURCE_DMA, + }, { + .start = data->irq_err, + .end = data->irq_err, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq_dma, + .end = data->irq_dma, + .flags = IORESOURCE_IRQ, + }, + }; + + return mxs_add_platform_device("mxs-mmc", data->id, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c index 56fa2ed1522..2c950fef71a 100644 --- a/arch/arm/mach-mxs/gpio.c +++ b/arch/arm/mach-mxs/gpio.c @@ -136,7 +136,7 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type) static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc) { u32 irq_stat; - struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq); + struct mxs_gpio_port *port = (struct mxs_gpio_port *)irq_get_handler_data(irq); u32 gpio_irq_no_base = port->virtual_irq_start; desc->irq_data.chip->irq_ack(&desc->irq_data); @@ -265,14 +265,14 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt) for (j = port[i].virtual_irq_start; j < port[i].virtual_irq_start + 32; j++) { - set_irq_chip(j, &gpio_irq_chip); - set_irq_handler(j, handle_level_irq); + irq_set_chip_and_handler(j, &gpio_irq_chip, + handle_level_irq); set_irq_flags(j, IRQF_VALID); } /* setup one handler for each entry */ - set_irq_chained_handler(port[i].irq, mxs_gpio_irq_handler); - set_irq_data(port[i].irq, &port[i]); + irq_set_chained_handler(port[i].irq, mxs_gpio_irq_handler); + irq_set_handler_data(port[i].irq, &port[i]); /* register gpio chip */ port[i].chip.direction_input = mxs_gpio_direction_input; diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c index 0f4c120fc16..23ca9d083b2 100644 --- a/arch/arm/mach-mxs/icoll.c +++ b/arch/arm/mach-mxs/icoll.c @@ -74,8 +74,7 @@ void __init icoll_init_irq(void) mxs_reset_block(icoll_base + HW_ICOLL_CTRL); for (i = 0; i < MXS_INTERNAL_IRQS; i++) { - set_irq_chip(i, &mxs_icoll_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &mxs_icoll_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID); } } diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h index 71f24484b04..c5137f14c36 100644 --- a/arch/arm/mach-mxs/include/mach/devices-common.h +++ b/arch/arm/mach-mxs/include/mach/devices-common.h @@ -73,6 +73,19 @@ struct mxs_i2c_data { }; struct platform_device * __init mxs_add_mxs_i2c(const struct mxs_i2c_data *data); +/* mmc */ +#include <mach/mmc.h> +struct mxs_mxs_mmc_data { + int id; + resource_size_t iobase; + resource_size_t dma; + resource_size_t irq_err; + resource_size_t irq_dma; +}; +struct platform_device *__init mxs_add_mxs_mmc( + const struct mxs_mxs_mmc_data *data, + const struct mxs_mmc_platform_data *pdata); + /* pwm */ struct platform_device *__init mxs_add_mxs_pwm( resource_size_t iobase, int id); diff --git a/arch/arm/mach-mxs/include/mach/dma.h b/arch/arm/mach-mxs/include/mach/dma.h new file mode 100644 index 00000000000..7f4aeeaba8d --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/dma.h @@ -0,0 +1,26 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_MXS_DMA_H__ +#define __MACH_MXS_DMA_H__ + +struct mxs_dma_data { + int chan_irq; +}; + +static inline int mxs_dma_is_apbh(struct dma_chan *chan) +{ + return !strcmp(dev_name(chan->device->dev), "mxs-dma-apbh"); +} + +static inline int mxs_dma_is_apbx(struct dma_chan *chan) +{ + return !strcmp(dev_name(chan->device->dev), "mxs-dma-apbx"); +} + +#endif /* __MACH_MXS_DMA_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/mmc.h b/arch/arm/mach-mxs/include/mach/mmc.h new file mode 100644 index 00000000000..211547a0556 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/mmc.h @@ -0,0 +1,18 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_MXS_MMC_H__ +#define __MACH_MXS_MMC_H__ + +struct mxs_mmc_platform_data { + int wp_gpio; /* write protect pin */ + unsigned int flags; +#define SLOTF_4_BIT_CAPABLE (1 << 0) +#define SLOTF_8_BIT_CAPABLE (1 << 1) +}; +#endif /* __MACH_MXS_MMC_H__ */ diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c index a66994f0518..214e5b641bb 100644 --- a/arch/arm/mach-mxs/mach-mx23evk.c +++ b/arch/arm/mach-mxs/mach-mx23evk.c @@ -28,6 +28,8 @@ #define MX23EVK_LCD_ENABLE MXS_GPIO_NR(1, 18) #define MX23EVK_BL_ENABLE MXS_GPIO_NR(1, 28) +#define MX23EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(1, 30) +#define MX23EVK_MMC0_SLOT_POWER MXS_GPIO_NR(1, 29) static const iomux_cfg_t mx23evk_pads[] __initconst = { /* duart */ @@ -73,6 +75,36 @@ static const iomux_cfg_t mx23evk_pads[] __initconst = { MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL, /* backlight control */ MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL, + + /* mmc */ + MX23_PAD_SSP1_DATA0__SSP1_DATA0 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DATA1__SSP1_DATA1 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DATA2__SSP1_DATA2 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DATA3__SSP1_DATA3 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_GPMI_D08__SSP1_DATA4 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_GPMI_D09__SSP1_DATA5 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_GPMI_D10__SSP1_DATA6 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_GPMI_D11__SSP1_DATA7 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_CMD__SSP1_CMD | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DETECT__SSP1_DETECT | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX23_PAD_SSP1_SCK__SSP1_SCK | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* write protect */ + MX23_PAD_PWM4__GPIO_1_30 | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* slot power enable */ + MX23_PAD_PWM3__GPIO_1_29 | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), }; /* mxsfb (lcdif) */ @@ -101,6 +133,11 @@ static const struct mxsfb_platform_data mx23evk_mxsfb_pdata __initconst = { .ld_intf_width = STMLCDIF_24BIT, }; +static struct mxs_mmc_platform_data mx23evk_mmc_pdata __initdata = { + .wp_gpio = MX23EVK_MMC0_WRITE_PROTECT, + .flags = SLOTF_8_BIT_CAPABLE, +}; + static void __init mx23evk_init(void) { int ret; @@ -110,6 +147,13 @@ static void __init mx23evk_init(void) mx23_add_duart(); mx23_add_auart0(); + /* power on mmc slot by writing 0 to the gpio */ + ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_DIR_OUT, + "mmc0-slot-power"); + if (ret) + pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret); + mx23_add_mxs_mmc(0, &mx23evk_mmc_pdata); + ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable"); if (ret) pr_warn("failed to request gpio lcd-enable: %d\n", ret); diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c index 08002d02267..bb329b9a260 100644 --- a/arch/arm/mach-mxs/mach-mx28evk.c +++ b/arch/arm/mach-mxs/mach-mx28evk.c @@ -34,6 +34,11 @@ #define MX28EVK_LCD_ENABLE MXS_GPIO_NR(3, 30) #define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13) +#define MX28EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(2, 12) +#define MX28EVK_MMC1_WRITE_PROTECT MXS_GPIO_NR(0, 28) +#define MX28EVK_MMC0_SLOT_POWER MXS_GPIO_NR(3, 28) +#define MX28EVK_MMC1_SLOT_POWER MXS_GPIO_NR(3, 29) + static const iomux_cfg_t mx28evk_pads[] __initconst = { /* duart */ MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, @@ -115,6 +120,65 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = { MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL, /* backlight control */ MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL, + /* mmc0 */ + MX28_PAD_SSP0_DATA0__SSP0_D0 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA1__SSP0_D1 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA2__SSP0_D2 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA3__SSP0_D3 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA4__SSP0_D4 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA5__SSP0_D5 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA6__SSP0_D6 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA7__SSP0_D7 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_CMD__SSP0_CMD | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_SSP0_SCK__SSP0_SCK | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* write protect */ + MX28_PAD_SSP1_SCK__GPIO_2_12 | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* slot power enable */ + MX28_PAD_PWM3__GPIO_3_28 | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + + /* mmc1 */ + MX28_PAD_GPMI_D00__SSP1_D0 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D01__SSP1_D1 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D02__SSP1_D2 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D03__SSP1_D3 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D04__SSP1_D4 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D05__SSP1_D5 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D06__SSP1_D6 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D07__SSP1_D7 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_RDY1__SSP1_CMD | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_GPMI_WRN__SSP1_SCK | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* write protect */ + MX28_PAD_GPMI_RESETN__GPIO_0_28 | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* slot power enable */ + MX28_PAD_PWM4__GPIO_3_29 | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), }; /* fec */ @@ -258,6 +322,18 @@ static const struct mxsfb_platform_data mx28evk_mxsfb_pdata __initconst = { .ld_intf_width = STMLCDIF_24BIT, }; +static struct mxs_mmc_platform_data mx28evk_mmc_pdata[] __initdata = { + { + /* mmc0 */ + .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT, + .flags = SLOTF_8_BIT_CAPABLE, + }, { + /* mmc1 */ + .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT, + .flags = SLOTF_8_BIT_CAPABLE, + }, +}; + static void __init mx28evk_init(void) { int ret; @@ -297,6 +373,19 @@ static void __init mx28evk_init(void) gpio_set_value(MX28EVK_BL_ENABLE, 1); mx28_add_mxsfb(&mx28evk_mxsfb_pdata); + + /* power on mmc slot by writing 0 to the gpio */ + ret = gpio_request_one(MX28EVK_MMC0_SLOT_POWER, GPIOF_DIR_OUT, + "mmc0-slot-power"); + if (ret) + pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret); + mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]); + + ret = gpio_request_one(MX28EVK_MMC1_SLOT_POWER, GPIOF_DIR_OUT, + "mmc1-slot-power"); + if (ret) + pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret); + mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]); } static void __init mx28evk_timer_init(void) diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c index fa0b154da67..0fcff47009c 100644 --- a/arch/arm/mach-mxs/module-tx28.c +++ b/arch/arm/mach-mxs/module-tx28.c @@ -45,7 +45,7 @@ static const iomux_cfg_t tx28_fec_gpio_pads[] __initconst = { }; #define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3) -static const iomux_cfg_t tx28_fec_pads[] __initconst = { +static const iomux_cfg_t tx28_fec0_pads[] __initconst = { MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE, MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE, MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE, @@ -57,7 +57,20 @@ static const iomux_cfg_t tx28_fec_pads[] __initconst = { MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE, }; -static const struct fec_platform_data tx28_fec_data __initconst = { +static const iomux_cfg_t tx28_fec1_pads[] __initconst = { + MX28_PAD_ENET0_RXD2__ENET1_RXD0, + MX28_PAD_ENET0_RXD3__ENET1_RXD1, + MX28_PAD_ENET0_TXD2__ENET1_TXD0, + MX28_PAD_ENET0_TXD3__ENET1_TXD1, + MX28_PAD_ENET0_COL__ENET1_TX_EN, + MX28_PAD_ENET0_CRS__ENET1_RX_EN, +}; + +static struct fec_platform_data tx28_fec0_data = { + .phy = PHY_INTERFACE_MODE_RMII, +}; + +static struct fec_platform_data tx28_fec1_data = { .phy = PHY_INTERFACE_MODE_RMII, }; @@ -108,15 +121,15 @@ int __init tx28_add_fec0(void) pr_debug("%s: Deasserting FEC PHY RESET\n", __func__); gpio_set_value(TX28_FEC_PHY_RESET, 1); - ret = mxs_iomux_setup_multiple_pads(tx28_fec_pads, - ARRAY_SIZE(tx28_fec_pads)); + ret = mxs_iomux_setup_multiple_pads(tx28_fec0_pads, + ARRAY_SIZE(tx28_fec0_pads)); if (ret) { pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n", __func__, ret); goto free_gpios; } - pr_debug("%s: Registering FEC device\n", __func__); - mx28_add_fec(0, &tx28_fec_data); + pr_debug("%s: Registering FEC0 device\n", __func__); + mx28_add_fec(0, &tx28_fec0_data); return 0; free_gpios: @@ -129,3 +142,19 @@ free_gpios: return ret; } + +int __init tx28_add_fec1(void) +{ + int ret; + + ret = mxs_iomux_setup_multiple_pads(tx28_fec1_pads, + ARRAY_SIZE(tx28_fec1_pads)); + if (ret) { + pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n", + __func__, ret); + return ret; + } + pr_debug("%s: Registering FEC1 device\n", __func__); + mx28_add_fec(1, &tx28_fec1_data); + return 0; +} diff --git a/arch/arm/mach-mxs/module-tx28.h b/arch/arm/mach-mxs/module-tx28.h index df9e1b6e81b..8ed425457d3 100644 --- a/arch/arm/mach-mxs/module-tx28.h +++ b/arch/arm/mach-mxs/module-tx28.h @@ -7,3 +7,4 @@ * Free Software Foundation. */ int __init tx28_add_fec0(void); +int __init tx28_add_fec1(void); diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c index 29ffa750fbe..00023b5cf12 100644 --- a/arch/arm/mach-netx/generic.c +++ b/arch/arm/mach-netx/generic.c @@ -171,13 +171,13 @@ void __init netx_init_irq(void) vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0); for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { - set_irq_chip(irq, &netx_hif_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &netx_hif_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN); - set_irq_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler); + irq_set_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler); } static int __init netx_init(void) diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c index 0c0d5248c36..e27687d5350 100644 --- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c +++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c @@ -107,8 +107,8 @@ void __init board_a9m9750dev_init_irq(void) __func__); for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { - set_irq_chip(i, &a9m9750dev_fpga_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &a9m9750dev_fpga_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } @@ -118,8 +118,8 @@ void __init board_a9m9750dev_init_irq(void) REGSET(eic, SYS_EIC, LVEDG, LEVEL); __raw_writel(eic, SYS_EIC(2)); - set_irq_chained_handler(IRQ_NS9XXX_EXT2, - a9m9750dev_fpga_demux_handler); + irq_set_chained_handler(IRQ_NS9XXX_EXT2, + a9m9750dev_fpga_demux_handler); } void __init board_a9m9750dev_init_machine(void) diff --git a/arch/arm/mach-ns9xxx/include/mach/board.h b/arch/arm/mach-ns9xxx/include/mach/board.h index f7e9196eb9a..19ca6de46a4 100644 --- a/arch/arm/mach-ns9xxx/include/mach/board.h +++ b/arch/arm/mach-ns9xxx/include/mach/board.h @@ -14,12 +14,10 @@ #include <asm/mach-types.h> #define board_is_a9m9750dev() (0 \ - || machine_is_cc9p9360dev() \ || machine_is_cc9p9750dev() \ ) #define board_is_a9mvali() (0 \ - || machine_is_cc9p9360val() \ || machine_is_cc9p9750val() \ ) diff --git a/arch/arm/mach-ns9xxx/include/mach/module.h b/arch/arm/mach-ns9xxx/include/mach/module.h index f851a6b7da6..628e9752589 100644 --- a/arch/arm/mach-ns9xxx/include/mach/module.h +++ b/arch/arm/mach-ns9xxx/include/mach/module.h @@ -18,7 +18,6 @@ ) #define module_is_cc9c() (0 \ - || machine_is_cc9c() \ ) #define module_is_cc9p9210() (0 \ @@ -32,21 +31,17 @@ ) #define module_is_cc9p9360() (0 \ - || machine_is_a9m9360() \ || machine_is_cc9p9360dev() \ || machine_is_cc9p9360js() \ - || machine_is_cc9p9360val() \ ) #define module_is_cc9p9750() (0 \ || machine_is_a9m9750() \ - || machine_is_cc9p9750dev() \ || machine_is_cc9p9750js() \ || machine_is_cc9p9750val() \ ) #define module_is_ccw9c() (0 \ - || machine_is_ccw9c() \ ) #define module_is_inc20otter() (0 \ diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c index 389fa5c669d..37ab0a2b83a 100644 --- a/arch/arm/mach-ns9xxx/irq.c +++ b/arch/arm/mach-ns9xxx/irq.c @@ -31,17 +31,11 @@ static void ns9xxx_mask_irq(struct irq_data *d) __raw_writel(ic, SYS_IC(prio / 4)); } -static void ns9xxx_ack_irq(struct irq_data *d) +static void ns9xxx_eoi_irq(struct irq_data *d) { __raw_writel(0, SYS_ISRADDR); } -static void ns9xxx_maskack_irq(struct irq_data *d) -{ - ns9xxx_mask_irq(d); - ns9xxx_ack_irq(d); -} - static void ns9xxx_unmask_irq(struct irq_data *d) { /* XXX: better use cpp symbols */ @@ -52,56 +46,11 @@ static void ns9xxx_unmask_irq(struct irq_data *d) } static struct irq_chip ns9xxx_chip = { - .irq_ack = ns9xxx_ack_irq, + .irq_eoi = ns9xxx_eoi_irq, .irq_mask = ns9xxx_mask_irq, - .irq_mask_ack = ns9xxx_maskack_irq, .irq_unmask = ns9xxx_unmask_irq, }; -#if 0 -#define handle_irq handle_level_irq -#else -static void handle_prio_irq(unsigned int irq, struct irq_desc *desc) -{ - struct irqaction *action; - irqreturn_t action_ret; - - raw_spin_lock(&desc->lock); - - BUG_ON(desc->status & IRQ_INPROGRESS); - - desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); - kstat_incr_irqs_this_cpu(irq, desc); - - action = desc->action; - if (unlikely(!action || (desc->status & IRQ_DISABLED))) - goto out_mask; - - desc->status |= IRQ_INPROGRESS; - raw_spin_unlock(&desc->lock); - - action_ret = handle_IRQ_event(irq, action); - - /* XXX: There is no direct way to access noirqdebug, so check - * unconditionally for spurious irqs... - * Maybe this function should go to kernel/irq/chip.c? */ - note_interrupt(irq, desc, action_ret); - - raw_spin_lock(&desc->lock); - desc->status &= ~IRQ_INPROGRESS; - - if (desc->status & IRQ_DISABLED) -out_mask: - desc->irq_data.chip->irq_mask(&desc->irq_data); - - /* ack unconditionally to unmask lower prio irqs */ - desc->irq_data.chip->irq_ack(&desc->irq_data); - - raw_spin_unlock(&desc->lock); -} -#define handle_irq handle_prio_irq -#endif - void __init ns9xxx_init_irq(void) { int i; @@ -118,8 +67,8 @@ void __init ns9xxx_init_irq(void) __raw_writel(prio2irq(i), SYS_IVA(i)); for (i = 0; i <= 31; ++i) { - set_irq_chip(i, &ns9xxx_chip); - set_irq_handler(i, handle_irq); + irq_set_chip_and_handler(i, &ns9xxx_chip, handle_fasteoi_irq); set_irq_flags(i, IRQF_VALID); + irq_set_status_flags(i, IRQ_LEVEL); } } diff --git a/arch/arm/mach-nuc93x/irq.c b/arch/arm/mach-nuc93x/irq.c index 1f8a05a2283..aa279f23e34 100644 --- a/arch/arm/mach-nuc93x/irq.c +++ b/arch/arm/mach-nuc93x/irq.c @@ -59,8 +59,8 @@ void __init nuc93x_init_irq(void) __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) { - set_irq_chip(irqno, &nuc93x_irq_chip); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &nuc93x_irq_chip, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } } diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S index 927d5a18176..c1c5fb6a5b4 100644 --- a/arch/arm/mach-omap1/ams-delta-fiq-handler.S +++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S @@ -79,7 +79,7 @@ /* - * Register useage + * Register usage * r8 - temporary * r9 - the driver buffer * r10 - temporary diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 7c5e2112c77..e68dfde1918 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -276,7 +276,7 @@ static void __init osk_init_cf(void) return; } /* the CF I/O IRQ is really active-low */ - set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING); + irq_set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING); } static void __init osk_init_irq(void) @@ -482,7 +482,7 @@ static void __init osk_mistral_init(void) omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */ gpio_request(4, "ts_int"); gpio_direction_input(4); - set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING); + irq_set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING); spi_register_board_info(mistral_boardinfo, ARRAY_SIZE(mistral_boardinfo)); @@ -500,7 +500,7 @@ static void __init osk_mistral_init(void) int irq = gpio_to_irq(OMAP_MPUIO(2)); gpio_direction_input(OMAP_MPUIO(2)); - set_irq_type(irq, IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); #ifdef CONFIG_PM /* share the IRQ in case someone wants to use the * button for more than wakeup from system sleep. diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index d7bbbe721a7..45f01d2c3a7 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -256,12 +256,12 @@ palmz71_powercable(int irq, void *dev_id) { if (gpio_get_value(PALMZ71_USBDETECT_GPIO)) { printk(KERN_INFO "PM: Power cable connected\n"); - set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), - IRQ_TYPE_EDGE_FALLING); + irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), + IRQ_TYPE_EDGE_FALLING); } else { printk(KERN_INFO "PM: Power cable disconnected\n"); - set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), - IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), + IRQ_TYPE_EDGE_RISING); } return IRQ_HANDLED; } diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index d41fe2d0616..0ad781db4e6 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c @@ -399,7 +399,7 @@ static void __init omap_sx1_init(void) sx1_mmc_init(); /* turn on USB power */ - /* sx1_setusbpower(1); cant do it here because i2c is not ready */ + /* sx1_setusbpower(1); can't do it here because i2c is not ready */ gpio_request(1, "A_IRDA_OFF"); gpio_request(11, "A_SWITCH"); gpio_request(15, "A_USB_ON"); diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index bdc0ac8dc21..65d24204937 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -279,10 +279,10 @@ static void __init voiceblue_init(void) gpio_request(13, "16C554 irq"); gpio_request(14, "16C554 irq"); gpio_request(15, "16C554 irq"); - set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); omap_board_config = voiceblue_config; diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index b0f4c231595..36f26c3fa25 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -281,7 +281,7 @@ static inline void omap_init_audio(void) {} * Claiming GPIOs, and setting their direction and initial values, is the * responsibility of the device drivers. So is responding to probe(). * - * Board-specific knowlege like creating devices or pin setup is to be + * Board-specific knowledge like creating devices or pin setup is to be * kept out of drivers as much as possible. In particular, pin setup * may be handled by the boot loader, and drivers should expect it will * normally have been done by the time they're probed. diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c index 0ace7998aaa..cddbf8b089c 100644 --- a/arch/arm/mach-omap1/fpga.c +++ b/arch/arm/mach-omap1/fpga.c @@ -156,17 +156,17 @@ void omap1510_fpga_init_irq(void) * The touchscreen interrupt is level-sensitive, so * we'll use the regular mask_ack routine for it. */ - set_irq_chip(i, &omap_fpga_irq_ack); + irq_set_chip(i, &omap_fpga_irq_ack); } else { /* * All FPGA interrupts except the touchscreen are * edge-sensitive, so we won't mask them. */ - set_irq_chip(i, &omap_fpga_irq); + irq_set_chip(i, &omap_fpga_irq); } - set_irq_handler(i, handle_edge_irq); + irq_set_handler(i, handle_edge_irq); set_irq_flags(i, IRQF_VALID); } @@ -183,6 +183,6 @@ void omap1510_fpga_init_irq(void) return; } gpio_direction_input(13); - set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); - set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); + irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); + irq_set_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); } diff --git a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h index 7a2df29400c..23eed0035ed 100644 --- a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h +++ b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h @@ -31,7 +31,7 @@ #endif /* - * These are the offsets from the begining of the fiq_buffer. They are put here + * These are the offsets from the beginning of the fiq_buffer. They are put here * since the buffer and header need to be accessed by drivers servicing devices * which generate GPIO interrupts - e.g. keyboard, modem, hook switch. */ diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c index 731dd33bff5..5d3da7a63af 100644 --- a/arch/arm/mach-omap1/irq.c +++ b/arch/arm/mach-omap1/irq.c @@ -230,8 +230,8 @@ void __init omap_init_irq(void) irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); omap_irq_set_cfg(j, 0, 0, irq_trigger); - set_irq_chip(j, &omap_irq_chip); - set_irq_handler(j, handle_level_irq); + irq_set_chip_and_handler(j, &omap_irq_chip, + handle_level_irq); set_irq_flags(j, IRQF_VALID); } } diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index eeab35dea07..b997a35830f 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -44,6 +44,7 @@ config ARCH_OMAP4 depends on ARCH_OMAP2PLUS select CPU_V7 select ARM_GIC + select LOCAL_TIMERS if SMP select PL310_ERRATA_588369 select PL310_ERRATA_727915 select ARM_ERRATA_720789 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index a45cd640968..512b1520445 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -68,7 +68,7 @@ obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o AFLAGS_sleep24xx.o :=-Wa,-march=armv6 -AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a +AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec) ifeq ($(CONFIG_PM_VERBOSE),y) CFLAGS_pm_bus.o += -DDEBUG diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index c06eb423c4e..9afd087cc29 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -307,9 +307,6 @@ static struct omap_dss_board_info sdp3430_dss_data = { .default_device = &sdp3430_lcd_device, }; -static struct regulator_consumer_supply sdp3430_vdda_dac_supply = - REGULATOR_SUPPLY("vdda_dac", "omapdss"); - static struct omap_board_config_kernel sdp3430_config[] __initdata = { }; @@ -398,12 +395,13 @@ static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = { }; static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = { - REGULATOR_SUPPLY("vdda_dac", "omapdss"), + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"), }; /* VPLL2 for digital video outputs */ static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = { REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), }; static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = { diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 333ceb2c8fb..56702c5e577 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -36,6 +36,7 @@ #include <plat/usb.h> #include <plat/mmc.h> #include <plat/omap4-keypad.h> +#include <plat/display.h> #include "mux.h" #include "hsmmc.h" @@ -47,6 +48,8 @@ #define ETH_KS8851_QUART 138 #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 #define OMAP4_SFH7741_ENABLE_GPIO 188 +#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */ +#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ static const int sdp4430_keymap[] = { KEY(0, 0, KEY_E), @@ -547,6 +550,12 @@ static struct regulator_init_data sdp4430_vusb = { }, }; +static struct regulator_init_data sdp4430_clk32kg = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, +}; + static struct twl4030_platform_data sdp4430_twldata = { .irq_base = TWL6030_IRQ_BASE, .irq_end = TWL6030_IRQ_END, @@ -562,6 +571,7 @@ static struct twl4030_platform_data sdp4430_twldata = { .vaux1 = &sdp4430_vaux1, .vaux2 = &sdp4430_vaux2, .vaux3 = &sdp4430_vaux3, + .clk32kg = &sdp4430_clk32kg, .usb = &omap4_usbphy_data }; @@ -621,6 +631,76 @@ static void __init omap_sfh7741prox_init(void) } } +static void sdp4430_hdmi_mux_init(void) +{ + /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */ + omap_mux_init_signal("hdmi_hpd", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("hdmi_cec", + OMAP_PIN_INPUT_PULLUP); + /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */ + omap_mux_init_signal("hdmi_ddc_scl", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("hdmi_ddc_sda", + OMAP_PIN_INPUT_PULLUP); +} + +static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev) +{ + int status; + + status = gpio_request_one(HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, + "hdmi_gpio_hpd"); + if (status) { + pr_err("Cannot request GPIO %d\n", HDMI_GPIO_HPD); + return status; + } + status = gpio_request_one(HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, + "hdmi_gpio_ls_oe"); + if (status) { + pr_err("Cannot request GPIO %d\n", HDMI_GPIO_LS_OE); + goto error1; + } + + return 0; + +error1: + gpio_free(HDMI_GPIO_HPD); + + return status; +} + +static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev) +{ + gpio_free(HDMI_GPIO_LS_OE); + gpio_free(HDMI_GPIO_HPD); +} + +static struct omap_dss_device sdp4430_hdmi_device = { + .name = "hdmi", + .driver_name = "hdmi_panel", + .type = OMAP_DISPLAY_TYPE_HDMI, + .platform_enable = sdp4430_panel_enable_hdmi, + .platform_disable = sdp4430_panel_disable_hdmi, + .channel = OMAP_DSS_CHANNEL_DIGIT, +}; + +static struct omap_dss_device *sdp4430_dss_devices[] = { + &sdp4430_hdmi_device, +}; + +static struct omap_dss_board_info sdp4430_dss_data = { + .num_devices = ARRAY_SIZE(sdp4430_dss_devices), + .devices = sdp4430_dss_devices, + .default_device = &sdp4430_hdmi_device, +}; + +void omap_4430sdp_display_init(void) +{ + sdp4430_hdmi_mux_init(); + omap_display_init(&sdp4430_dss_data); +} + #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { OMAP4_MUX(USBB2_ULPITLL_CLK, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), @@ -729,6 +809,8 @@ static void __init omap_4430sdp_init(void) status = omap4_keyboard_init(&sdp4430_keypad_data); if (status) pr_err("Keypad initialization failed: %d\n", status); + + omap_4430sdp_display_init(); } static void __init omap_4430sdp_map_io(void) diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 7b5647954c1..02a12b41c0f 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -488,7 +488,7 @@ static struct regulator_consumer_supply cm_t35_vsim_supply = { }; static struct regulator_consumer_supply cm_t35_vdac_supply = - REGULATOR_SUPPLY("vdda_dac", "omapdss"); + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); static struct regulator_consumer_supply cm_t35_vdvi_supply = REGULATOR_SUPPLY("vdvi", "omapdss"); diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index aa27483c493..65f9fde2c56 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -196,7 +196,7 @@ static struct omap_dss_board_info devkit8000_dss_data = { }; static struct regulator_consumer_supply devkit8000_vdda_dac_supply = - REGULATOR_SUPPLY("vdda_dac", "omapdss"); + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); static uint32_t board_keymap[] = { KEY(0, 0, KEY_1), @@ -277,8 +277,10 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = { .setup = devkit8000_twl_gpio_setup, }; -static struct regulator_consumer_supply devkit8000_vpll1_supply = - REGULATOR_SUPPLY("vdds_dsi", "omapdss"); +static struct regulator_consumer_supply devkit8000_vpll1_supplies[] = { + REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), +}; /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ static struct regulator_init_data devkit8000_vmmc1 = { @@ -319,8 +321,8 @@ static struct regulator_init_data devkit8000_vpll1 = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 1, - .consumer_supplies = &devkit8000_vpll1_supply, + .num_consumer_supplies = ARRAY_SIZE(devkit8000_vpll1_supplies), + .consumer_supplies = devkit8000_vpll1_supplies, }; /* VAUX4 for ads7846 and nubs */ diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index d3199b4ecdb..34cf982b967 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -485,8 +485,10 @@ static struct omap_dss_board_info igep2_dss_data = { .default_device = &igep2_dvi_device, }; -static struct regulator_consumer_supply igep2_vpll2_supply = - REGULATOR_SUPPLY("vdds_dsi", "omapdss"); +static struct regulator_consumer_supply igep2_vpll2_supplies[] = { + REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), +}; static struct regulator_init_data igep2_vpll2 = { .constraints = { @@ -499,8 +501,8 @@ static struct regulator_init_data igep2_vpll2 = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 1, - .consumer_supplies = &igep2_vpll2_supply, + .num_consumer_supplies = ARRAY_SIZE(igep2_vpll2_supplies), + .consumer_supplies = igep2_vpll2_supplies, }; static void __init igep2_display_init(void) @@ -694,7 +696,7 @@ static void __init igep2_init(void) igep2_init_smsc911x(); /* - * WLAN-BT combo module from MuRata wich has a Marvell WLAN + * WLAN-BT combo module from MuRata which has a Marvell WLAN * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface. */ igep2_wlan_bt_init(); diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c index b10db0e6ee6..2cf86c3cb1a 100644 --- a/arch/arm/mach-omap2/board-igep0030.c +++ b/arch/arm/mach-omap2/board-igep0030.c @@ -440,7 +440,7 @@ static void __init igep3_init(void) igep3_leds_init(); /* - * WLAN-BT combo module from MuRata wich has a Marvell WLAN + * WLAN-BT combo module from MuRata which has a Marvell WLAN * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface. */ igep3_wifi_bt_init(); diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 7640c054f43..33007fd4a08 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -232,10 +232,12 @@ static struct omap_dss_board_info beagle_dss_data = { }; static struct regulator_consumer_supply beagle_vdac_supply = - REGULATOR_SUPPLY("vdda_dac", "omapdss"); + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); -static struct regulator_consumer_supply beagle_vdvi_supply = - REGULATOR_SUPPLY("vdds_dsi", "omapdss"); +static struct regulator_consumer_supply beagle_vdvi_supplies[] = { + REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), +}; static void __init beagle_display_init(void) { @@ -422,8 +424,8 @@ static struct regulator_init_data beagle_vpll2 = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 1, - .consumer_supplies = &beagle_vdvi_supply, + .num_consumer_supplies = ARRAY_SIZE(beagle_vdvi_supplies), + .consumer_supplies = beagle_vdvi_supplies, }; static struct twl4030_usb_data beagle_usb_data = { diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 0fa2c7b208b..5a1a916e5cc 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -542,7 +542,7 @@ static struct twl4030_codec_data omap3evm_codec_data = { }; static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = - REGULATOR_SUPPLY("vdda_dac", "omapdss"); + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); /* VDAC for DSS driving S-Video */ static struct regulator_init_data omap3_evm_vdac = { @@ -560,8 +560,10 @@ static struct regulator_init_data omap3_evm_vdac = { }; /* VPLL2 for digital video outputs */ -static struct regulator_consumer_supply omap3_evm_vpll2_supply = - REGULATOR_SUPPLY("vdds_dsi", "omapdss"); +static struct regulator_consumer_supply omap3_evm_vpll2_supplies[] = { + REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), +}; static struct regulator_init_data omap3_evm_vpll2 = { .constraints = { @@ -573,8 +575,8 @@ static struct regulator_init_data omap3_evm_vpll2 = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 1, - .consumer_supplies = &omap3_evm_vpll2_supply, + .num_consumer_supplies = ARRAY_SIZE(omap3_evm_vpll2_supplies), + .consumer_supplies = omap3_evm_vpll2_supplies, }; /* ads7846 on SPI */ diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 2e5dc21e347..07dba888f45 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -342,11 +342,12 @@ static struct regulator_consumer_supply pandora_vmmc3_supply = REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"); static struct regulator_consumer_supply pandora_vdda_dac_supply = - REGULATOR_SUPPLY("vdda_dac", "omapdss"); + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); static struct regulator_consumer_supply pandora_vdds_supplies[] = { REGULATOR_SUPPLY("vdds_sdi", "omapdss"), REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), }; static struct regulator_consumer_supply pandora_vcc_lcd_supply = diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index 8ebdbc38b9d..a6e0b9161c9 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -439,7 +439,7 @@ static struct twl4030_codec_data omap3stalker_codec_data = { }; static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply = - REGULATOR_SUPPLY("vdda_dac", "omapdss"); + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); /* VDAC for DSS driving S-Video */ static struct regulator_init_data omap3_stalker_vdac = { @@ -457,8 +457,10 @@ static struct regulator_init_data omap3_stalker_vdac = { }; /* VPLL2 for digital video outputs */ -static struct regulator_consumer_supply omap3_stalker_vpll2_supply = - REGULATOR_SUPPLY("vdds_dsi", "omapdss"); +static struct regulator_consumer_supply omap3_stalker_vpll2_supplies[] = { + REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), +}; static struct regulator_init_data omap3_stalker_vpll2 = { .constraints = { @@ -471,8 +473,8 @@ static struct regulator_init_data omap3_stalker_vpll2 = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 1, - .consumer_supplies = &omap3_stalker_vpll2_supply, + .num_consumer_supplies = ARRAY_SIZE(omap3_stalker_vpll2_supplies), + .consumer_supplies = omap3_stalker_vpll2_supplies, }; static struct twl4030_platform_data omap3stalker_twldata = { diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 0f4d8a762a7..f3a7b101191 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -34,11 +34,13 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> +#include <plat/display.h> #include <plat/board.h> #include <plat/common.h> #include <plat/usb.h> #include <plat/mmc.h> +#include <plat/panel-generic-dpi.h> #include "timer-gp.h" #include "hsmmc.h" @@ -49,6 +51,8 @@ #define GPIO_HUB_NRESET 62 #define GPIO_WIFI_PMENA 43 #define GPIO_WIFI_IRQ 53 +#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */ +#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ /* wl127x BT, FM, GPS connectivity chip */ static int wl1271_gpios[] = {46, -1, -1}; @@ -281,19 +285,6 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) return 0; } -static struct regulator_init_data omap4_panda_vaux1 = { - .constraints = { - .min_uV = 1000000, - .max_uV = 3000000, - .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -}; - static struct regulator_init_data omap4_panda_vaux2 = { .constraints = { .min_uV = 1200000, @@ -349,19 +340,6 @@ static struct regulator_init_data omap4_panda_vpp = { }, }; -static struct regulator_init_data omap4_panda_vusim = { - .constraints = { - .min_uV = 1200000, - .max_uV = 2900000, - .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -}; - static struct regulator_init_data omap4_panda_vana = { .constraints = { .min_uV = 2100000, @@ -407,6 +385,12 @@ static struct regulator_init_data omap4_panda_vusb = { }, }; +static struct regulator_init_data omap4_panda_clk32kg = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, +}; + static struct twl4030_platform_data omap4_panda_twldata = { .irq_base = TWL6030_IRQ_BASE, .irq_end = TWL6030_IRQ_END, @@ -414,14 +398,13 @@ static struct twl4030_platform_data omap4_panda_twldata = { /* Regulators */ .vmmc = &omap4_panda_vmmc, .vpp = &omap4_panda_vpp, - .vusim = &omap4_panda_vusim, .vana = &omap4_panda_vana, .vcxio = &omap4_panda_vcxio, .vdac = &omap4_panda_vdac, .vusb = &omap4_panda_vusb, - .vaux1 = &omap4_panda_vaux1, .vaux2 = &omap4_panda_vaux2, .vaux3 = &omap4_panda_vaux3, + .clk32kg = &omap4_panda_clk32kg, .usb = &omap4_usbphy_data, }; @@ -433,6 +416,17 @@ static struct i2c_board_info __initdata omap4_panda_i2c_boardinfo[] = { .platform_data = &omap4_panda_twldata, }, }; + +/* + * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM + * is connected as I2C slave device, and can be accessed at address 0x50 + */ +static struct i2c_board_info __initdata panda_i2c_eeprom[] = { + { + I2C_BOARD_INFO("eeprom", 0x50), + }, +}; + static int __init omap4_panda_i2c_init(void) { /* @@ -442,7 +436,12 @@ static int __init omap4_panda_i2c_init(void) omap_register_i2c_bus(1, 400, omap4_panda_i2c_boardinfo, ARRAY_SIZE(omap4_panda_i2c_boardinfo)); omap_register_i2c_bus(2, 400, NULL, 0); - omap_register_i2c_bus(3, 400, NULL, 0); + /* + * Bus 3 is attached to the DVI port where devices like the pico DLP + * projector don't work reliably with 400kHz + */ + omap_register_i2c_bus(3, 100, panda_i2c_eeprom, + ARRAY_SIZE(panda_i2c_eeprom)); omap_register_i2c_bus(4, 400, NULL, 0); return 0; } @@ -462,6 +461,64 @@ static struct omap_board_mux board_mux[] __initdata = { OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + /* gpio 0 - TFP410 PD */ + OMAP4_MUX(KPD_COL1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE3), + /* dispc2_data23 */ + OMAP4_MUX(USBB2_ULPITLL_STP, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data22 */ + OMAP4_MUX(USBB2_ULPITLL_DIR, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data21 */ + OMAP4_MUX(USBB2_ULPITLL_NXT, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data20 */ + OMAP4_MUX(USBB2_ULPITLL_DAT0, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data19 */ + OMAP4_MUX(USBB2_ULPITLL_DAT1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data18 */ + OMAP4_MUX(USBB2_ULPITLL_DAT2, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data15 */ + OMAP4_MUX(USBB2_ULPITLL_DAT3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data14 */ + OMAP4_MUX(USBB2_ULPITLL_DAT4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data13 */ + OMAP4_MUX(USBB2_ULPITLL_DAT5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data12 */ + OMAP4_MUX(USBB2_ULPITLL_DAT6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data11 */ + OMAP4_MUX(USBB2_ULPITLL_DAT7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data10 */ + OMAP4_MUX(DPM_EMU3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data9 */ + OMAP4_MUX(DPM_EMU4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data16 */ + OMAP4_MUX(DPM_EMU5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data17 */ + OMAP4_MUX(DPM_EMU6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_hsync */ + OMAP4_MUX(DPM_EMU7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_pclk */ + OMAP4_MUX(DPM_EMU8, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_vsync */ + OMAP4_MUX(DPM_EMU9, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_de */ + OMAP4_MUX(DPM_EMU10, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data8 */ + OMAP4_MUX(DPM_EMU11, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data7 */ + OMAP4_MUX(DPM_EMU12, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data6 */ + OMAP4_MUX(DPM_EMU13, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data5 */ + OMAP4_MUX(DPM_EMU14, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data4 */ + OMAP4_MUX(DPM_EMU15, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data3 */ + OMAP4_MUX(DPM_EMU16, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data2 */ + OMAP4_MUX(DPM_EMU17, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data1 */ + OMAP4_MUX(DPM_EMU18, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data0 */ + OMAP4_MUX(DPM_EMU19, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), { .reg_offset = OMAP_MUX_TERMINATOR }, }; @@ -535,6 +592,128 @@ static inline void board_serial_init(void) } #endif +/* Display DVI */ +#define PANDA_DVI_TFP410_POWER_DOWN_GPIO 0 + +static int omap4_panda_enable_dvi(struct omap_dss_device *dssdev) +{ + gpio_set_value(dssdev->reset_gpio, 1); + return 0; +} + +static void omap4_panda_disable_dvi(struct omap_dss_device *dssdev) +{ + gpio_set_value(dssdev->reset_gpio, 0); +} + +/* Using generic display panel */ +static struct panel_generic_dpi_data omap4_dvi_panel = { + .name = "generic", + .platform_enable = omap4_panda_enable_dvi, + .platform_disable = omap4_panda_disable_dvi, +}; + +struct omap_dss_device omap4_panda_dvi_device = { + .type = OMAP_DISPLAY_TYPE_DPI, + .name = "dvi", + .driver_name = "generic_dpi_panel", + .data = &omap4_dvi_panel, + .phy.dpi.data_lines = 24, + .reset_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO, + .channel = OMAP_DSS_CHANNEL_LCD2, +}; + +int __init omap4_panda_dvi_init(void) +{ + int r; + + /* Requesting TFP410 DVI GPIO and disabling it, at bootup */ + r = gpio_request_one(omap4_panda_dvi_device.reset_gpio, + GPIOF_OUT_INIT_LOW, "DVI PD"); + if (r) + pr_err("Failed to get DVI powerdown GPIO\n"); + + return r; +} + + +static void omap4_panda_hdmi_mux_init(void) +{ + /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */ + omap_mux_init_signal("hdmi_hpd", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("hdmi_cec", + OMAP_PIN_INPUT_PULLUP); + /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */ + omap_mux_init_signal("hdmi_ddc_scl", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("hdmi_ddc_sda", + OMAP_PIN_INPUT_PULLUP); +} + +static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev) +{ + int status; + + status = gpio_request_one(HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, + "hdmi_gpio_hpd"); + if (status) { + pr_err("Cannot request GPIO %d\n", HDMI_GPIO_HPD); + return status; + } + status = gpio_request_one(HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, + "hdmi_gpio_ls_oe"); + if (status) { + pr_err("Cannot request GPIO %d\n", HDMI_GPIO_LS_OE); + goto error1; + } + + return 0; + +error1: + gpio_free(HDMI_GPIO_HPD); + + return status; +} + +static void omap4_panda_panel_disable_hdmi(struct omap_dss_device *dssdev) +{ + gpio_free(HDMI_GPIO_LS_OE); + gpio_free(HDMI_GPIO_HPD); +} + +static struct omap_dss_device omap4_panda_hdmi_device = { + .name = "hdmi", + .driver_name = "hdmi_panel", + .type = OMAP_DISPLAY_TYPE_HDMI, + .platform_enable = omap4_panda_panel_enable_hdmi, + .platform_disable = omap4_panda_panel_disable_hdmi, + .channel = OMAP_DSS_CHANNEL_DIGIT, +}; + +static struct omap_dss_device *omap4_panda_dss_devices[] = { + &omap4_panda_dvi_device, + &omap4_panda_hdmi_device, +}; + +static struct omap_dss_board_info omap4_panda_dss_data = { + .num_devices = ARRAY_SIZE(omap4_panda_dss_devices), + .devices = omap4_panda_dss_devices, + .default_device = &omap4_panda_dvi_device, +}; + +void omap4_panda_display_init(void) +{ + int r; + + r = omap4_panda_dvi_init(); + if (r) + pr_err("error initializing panda DVI\n"); + + omap4_panda_hdmi_mux_init(); + omap_display_init(&omap4_panda_dss_data); +} + static void __init omap4_panda_init(void) { int package = OMAP_PACKAGE_CBS; @@ -553,6 +732,7 @@ static void __init omap4_panda_init(void) omap4_twl6030_hsmmc_init(mmc); omap4_ehci_init(); usb_musb_init(&musb_board_data); + omap4_panda_display_init(); } static void __init omap4_panda_map_io(void) diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index d0961945c65..59ca33326b8 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -28,6 +28,8 @@ #include <linux/platform_device.h> #include <linux/i2c/twl.h> #include <linux/regulator/machine.h> +#include <linux/regulator/fixed.h> +#include <linux/spi/spi.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> @@ -41,10 +43,14 @@ #include <plat/board.h> #include <plat/common.h> +#include <plat/display.h> +#include <plat/panel-generic-dpi.h> #include <mach/gpio.h> #include <plat/gpmc.h> #include <mach/hardware.h> #include <plat/nand.h> +#include <plat/mcspi.h> +#include <plat/mux.h> #include <plat/usb.h> #include "mux.h" @@ -68,8 +74,6 @@ #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) -#include <plat/mcspi.h> -#include <linux/spi/spi.h> #include <linux/spi/ads7846.h> static struct omap2_mcspi_device_config ads7846_mcspi_config = { @@ -94,16 +98,32 @@ static struct ads7846_platform_data ads7846_config = { .keep_vref_on = 1, }; -static struct spi_board_info overo_spi_board_info[] __initdata = { - { - .modalias = "ads7846", - .bus_num = 1, - .chip_select = 0, - .max_speed_hz = 1500000, - .controller_data = &ads7846_mcspi_config, - .irq = OMAP_GPIO_IRQ(OVERO_GPIO_PENDOWN), - .platform_data = &ads7846_config, - } +/* fixed regulator for ads7846 */ +static struct regulator_consumer_supply ads7846_supply = + REGULATOR_SUPPLY("vcc", "spi1.0"); + +static struct regulator_init_data vads7846_regulator = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &ads7846_supply, +}; + +static struct fixed_voltage_config vads7846 = { + .supply_name = "vads7846", + .microvolts = 3300000, /* 3.3V */ + .gpio = -EINVAL, + .startup_delay = 0, + .init_data = &vads7846_regulator, +}; + +static struct platform_device vads7846_device = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &vads7846, + }, }; static void __init overo_ads7846_init(void) @@ -116,8 +136,7 @@ static void __init overo_ads7846_init(void) return; } - spi_register_board_info(overo_spi_board_info, - ARRAY_SIZE(overo_spi_board_info)); + platform_device_register(&vads7846_device); } #else @@ -233,6 +252,137 @@ static inline void __init overo_init_smsc911x(void) static inline void __init overo_init_smsc911x(void) { return; } #endif +/* DSS */ +static int lcd_enabled; +static int dvi_enabled; + +#define OVERO_GPIO_LCD_EN 144 +#define OVERO_GPIO_LCD_BL 145 + +static void __init overo_display_init(void) +{ + if ((gpio_request(OVERO_GPIO_LCD_EN, "OVERO_GPIO_LCD_EN") == 0) && + (gpio_direction_output(OVERO_GPIO_LCD_EN, 1) == 0)) + gpio_export(OVERO_GPIO_LCD_EN, 0); + else + printk(KERN_ERR "could not obtain gpio for " + "OVERO_GPIO_LCD_EN\n"); + + if ((gpio_request(OVERO_GPIO_LCD_BL, "OVERO_GPIO_LCD_BL") == 0) && + (gpio_direction_output(OVERO_GPIO_LCD_BL, 1) == 0)) + gpio_export(OVERO_GPIO_LCD_BL, 0); + else + printk(KERN_ERR "could not obtain gpio for " + "OVERO_GPIO_LCD_BL\n"); +} + +static int overo_panel_enable_dvi(struct omap_dss_device *dssdev) +{ + if (lcd_enabled) { + printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); + return -EINVAL; + } + dvi_enabled = 1; + + return 0; +} + +static void overo_panel_disable_dvi(struct omap_dss_device *dssdev) +{ + dvi_enabled = 0; +} + +static struct panel_generic_dpi_data dvi_panel = { + .name = "generic", + .platform_enable = overo_panel_enable_dvi, + .platform_disable = overo_panel_disable_dvi, +}; + +static struct omap_dss_device overo_dvi_device = { + .name = "dvi", + .type = OMAP_DISPLAY_TYPE_DPI, + .driver_name = "generic_dpi_panel", + .data = &dvi_panel, + .phy.dpi.data_lines = 24, +}; + +static struct omap_dss_device overo_tv_device = { + .name = "tv", + .driver_name = "venc", + .type = OMAP_DISPLAY_TYPE_VENC, + .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +}; + +static int overo_panel_enable_lcd(struct omap_dss_device *dssdev) +{ + if (dvi_enabled) { + printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); + return -EINVAL; + } + + gpio_set_value(OVERO_GPIO_LCD_EN, 1); + gpio_set_value(OVERO_GPIO_LCD_BL, 1); + lcd_enabled = 1; + return 0; +} + +static void overo_panel_disable_lcd(struct omap_dss_device *dssdev) +{ + gpio_set_value(OVERO_GPIO_LCD_EN, 0); + gpio_set_value(OVERO_GPIO_LCD_BL, 0); + lcd_enabled = 0; +} + +static struct panel_generic_dpi_data lcd43_panel = { + .name = "samsung_lte430wq_f0c", + .platform_enable = overo_panel_enable_lcd, + .platform_disable = overo_panel_disable_lcd, +}; + +static struct omap_dss_device overo_lcd43_device = { + .name = "lcd43", + .type = OMAP_DISPLAY_TYPE_DPI, + .driver_name = "generic_dpi_panel", + .data = &lcd43_panel, + .phy.dpi.data_lines = 24, +}; + +#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ + defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) +static struct omap_dss_device overo_lcd35_device = { + .type = OMAP_DISPLAY_TYPE_DPI, + .name = "lcd35", + .driver_name = "lgphilips_lb035q02_panel", + .phy.dpi.data_lines = 24, + .platform_enable = overo_panel_enable_lcd, + .platform_disable = overo_panel_disable_lcd, +}; +#endif + +static struct omap_dss_device *overo_dss_devices[] = { + &overo_dvi_device, + &overo_tv_device, +#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ + defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) + &overo_lcd35_device, +#endif + &overo_lcd43_device, +}; + +static struct omap_dss_board_info overo_dss_data = { + .num_devices = ARRAY_SIZE(overo_dss_devices), + .devices = overo_dss_devices, + .default_device = &overo_dvi_device, +}; + +static struct regulator_consumer_supply overo_vdda_dac_supply = + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); + +static struct regulator_consumer_supply overo_vdds_dsi_supply[] = { + REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), +}; + static struct mtd_partition overo_nand_partitions[] = { { .name = "xloader", @@ -323,6 +473,93 @@ static struct regulator_consumer_supply overo_vmmc1_supply = { .supply = "vmmc", }; +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) +#include <linux/leds.h> + +static struct gpio_led gpio_leds[] = { + { + .name = "overo:red:gpio21", + .default_trigger = "heartbeat", + .gpio = 21, + .active_low = true, + }, + { + .name = "overo:blue:gpio22", + .default_trigger = "none", + .gpio = 22, + .active_low = true, + }, + { + .name = "overo:blue:COM", + .default_trigger = "mmc0", + .gpio = -EINVAL, /* gets replaced */ + .active_low = true, + }, +}; + +static struct gpio_led_platform_data gpio_leds_pdata = { + .leds = gpio_leds, + .num_leds = ARRAY_SIZE(gpio_leds), +}; + +static struct platform_device gpio_leds_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &gpio_leds_pdata, + }, +}; + +static void __init overo_init_led(void) +{ + platform_device_register(&gpio_leds_device); +} + +#else +static inline void __init overo_init_led(void) { return; } +#endif + +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +#include <linux/input.h> +#include <linux/gpio_keys.h> + +static struct gpio_keys_button gpio_buttons[] = { + { + .code = BTN_0, + .gpio = 23, + .desc = "button0", + .wakeup = 1, + }, + { + .code = BTN_1, + .gpio = 14, + .desc = "button1", + .wakeup = 1, + }, +}; + +static struct gpio_keys_platform_data gpio_keys_pdata = { + .buttons = gpio_buttons, + .nbuttons = ARRAY_SIZE(gpio_buttons), +}; + +static struct platform_device gpio_keys_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &gpio_keys_pdata, + }, +}; + +static void __init overo_init_keys(void) +{ + platform_device_register(&gpio_keys_device); +} + +#else +static inline void __init overo_init_keys(void) { return; } +#endif + static int overo_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { @@ -330,6 +567,11 @@ static int overo_twl_gpio_setup(struct device *dev, overo_vmmc1_supply.dev = mmc[0].dev; +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) + /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */ + gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; +#endif + return 0; } @@ -337,6 +579,7 @@ static struct twl4030_gpio_platform_data overo_gpio_data = { .gpio_base = OMAP_MAX_GPIO_LINES, .irq_base = TWL4030_GPIO_IRQ_BASE, .irq_end = TWL4030_GPIO_IRQ_END, + .use_leds = true, .setup = overo_twl_gpio_setup, }; @@ -358,6 +601,35 @@ static struct regulator_init_data overo_vmmc1 = { .consumer_supplies = &overo_vmmc1_supply, }; +/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ +static struct regulator_init_data overo_vdac = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &overo_vdda_dac_supply, +}; + +/* VPLL2 for digital video outputs */ +static struct regulator_init_data overo_vpll2 = { + .constraints = { + .name = "VDVI", + .min_uV = 1800000, + .max_uV = 1800000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(overo_vdds_dsi_supply), + .consumer_supplies = overo_vdds_dsi_supply, +}; + static struct twl4030_codec_audio_data overo_audio_data; static struct twl4030_codec_data overo_codec_data = { @@ -365,8 +637,6 @@ static struct twl4030_codec_data overo_codec_data = { .audio = &overo_audio_data, }; -/* mmc2 (WLAN) and Bluetooth don't use twl4030 regulators */ - static struct twl4030_platform_data overo_twldata = { .irq_base = TWL4030_IRQ_BASE, .irq_end = TWL4030_IRQ_END, @@ -374,6 +644,8 @@ static struct twl4030_platform_data overo_twldata = { .usb = &overo_usb_data, .codec = &overo_codec_data, .vmmc1 = &overo_vmmc1, + .vdac = &overo_vdac, + .vpll2 = &overo_vpll2, }; static struct i2c_board_info __initdata overo_i2c_boardinfo[] = { @@ -394,18 +666,38 @@ static int __init overo_i2c_init(void) return 0; } -static struct platform_device overo_lcd_device = { - .name = "overo_lcd", - .id = -1, -}; - -static struct omap_lcd_config overo_lcd_config __initdata = { - .ctrl_name = "internal", +static struct spi_board_info overo_spi_board_info[] __initdata = { +#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ + defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) + { + .modalias = "ads7846", + .bus_num = 1, + .chip_select = 0, + .max_speed_hz = 1500000, + .controller_data = &ads7846_mcspi_config, + .irq = OMAP_GPIO_IRQ(OVERO_GPIO_PENDOWN), + .platform_data = &ads7846_config, + }, +#endif +#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ + defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) + { + .modalias = "lgphilips_lb035q02_panel-spi", + .bus_num = 1, + .chip_select = 1, + .max_speed_hz = 500000, + .mode = SPI_MODE_3, + }, +#endif }; -static struct omap_board_config_kernel overo_config[] __initdata = { - { OMAP_TAG_LCD, &overo_lcd_config }, -}; +static int __init overo_spi_init(void) +{ + overo_ads7846_init(); + spi_register_board_info(overo_spi_board_info, + ARRAY_SIZE(overo_spi_board_info)); + return 0; +} static void __init overo_init_early(void) { @@ -414,15 +706,10 @@ static void __init overo_init_early(void) mt46h32m32lf6_sdrc_params); } -static struct platform_device *overo_devices[] __initdata = { - &overo_lcd_device, -}; - static const struct usbhs_omap_board_data usbhs_bdata __initconst = { .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, - .phy_reset = true, .reset_gpio_port[0] = -EINVAL, .reset_gpio_port[1] = OVERO_GPIO_USBH_NRESET, @@ -444,16 +731,18 @@ static struct omap_musb_board_data musb_board_data = { static void __init overo_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap_board_config = overo_config; - omap_board_config_size = ARRAY_SIZE(overo_config); overo_i2c_init(); - platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices)); + omap_display_init(&overo_dss_data); omap_serial_init(); overo_flash_init(); usb_musb_init(&musb_board_data); usbhs_init(&usbhs_bdata); + overo_spi_init(); overo_ads7846_init(); overo_init_smsc911x(); + overo_display_init(); + overo_init_led(); + overo_init_keys(); /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 5f1900c532e..bbcb6775a6a 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -372,7 +372,7 @@ static struct regulator_consumer_supply rx51_vaux1_consumers[] = { }; static struct regulator_consumer_supply rx51_vdac_supply[] = { - REGULATOR_SUPPLY("vdda_dac", "omapdss"), + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"), }; static struct regulator_init_data rx51_vaux1 = { diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index e964895b80e..f8ba20a14e6 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -141,14 +141,19 @@ static void __init rx51_init(void) static void __init rx51_map_io(void) { omap2_set_globals_3xxx(); - rx51_video_mem_init(); omap34xx_map_common_io(); } +static void __init rx51_reserve(void) +{ + rx51_video_mem_init(); + omap_reserve(); +} + MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */ .boot_params = 0x80000100, - .reserve = omap_reserve, + .reserve = rx51_reserve, .map_io = rx51_map_io, .init_early = rx51_init_early, .init_irq = omap_init_irq, diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 448ab60195d..8dee7549fbd 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -226,11 +226,13 @@ static struct omap2_hsmmc_info mmc[] = { {} /* Terminator */ }; -static struct regulator_consumer_supply zoom_vpll2_supply = - REGULATOR_SUPPLY("vdds_dsi", "omapdss"); +static struct regulator_consumer_supply zoom_vpll2_supplies[] = { + REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), +}; static struct regulator_consumer_supply zoom_vdda_dac_supply = - REGULATOR_SUPPLY("vdda_dac", "omapdss"); + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); static struct regulator_init_data zoom_vpll2 = { .constraints = { @@ -241,8 +243,8 @@ static struct regulator_init_data zoom_vpll2 = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 1, - .consumer_supplies = &zoom_vpll2_supply, + .num_consumer_supplies = ARRAY_SIZE(zoom_vpll2_supplies), + .consumer_supplies = zoom_vpll2_supplies, }; static struct regulator_init_data zoom_vdac = { diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index b2b1e37bb6b..d6e34dd9e7e 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -115,6 +115,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 0, 0, 0, 0); + clk->rate = rate; return 0; } diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index b6f65d4ac97..2926d028b6e 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -1804,10 +1804,10 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), /* DSS domain clocks */ - CLK("omapdss", "ick", &dss_ick, CK_242X), - CLK("omapdss", "dss1_fck", &dss1_fck, CK_242X), - CLK("omapdss", "dss2_fck", &dss2_fck, CK_242X), - CLK("omapdss", "tv_fck", &dss_54m_fck, CK_242X), + CLK("omapdss_dss", "ick", &dss_ick, CK_242X), + CLK("omapdss_dss", "fck", &dss1_fck, CK_242X), + CLK("omapdss_dss", "sys_clk", &dss2_fck, CK_242X), + CLK("omapdss_dss", "tv_clk", &dss_54m_fck, CK_242X), /* L3 domain clocks */ CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index bba018331a7..0c79d39e302 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -1894,10 +1894,10 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), /* DSS domain clocks */ - CLK("omapdss", "ick", &dss_ick, CK_243X), - CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X), - CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X), - CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X), + CLK("omapdss_dss", "ick", &dss_ick, CK_243X), + CLK("omapdss_dss", "fck", &dss1_fck, CK_243X), + CLK("omapdss_dss", "sys_clk", &dss2_fck, CK_243X), + CLK("omapdss_dss", "tv_clk", &dss_54m_fck, CK_243X), /* L3 domain clocks */ CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index fcb321a64f1..75b119bd9cd 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3356,13 +3356,13 @@ static struct omap_clk omap3xxx_clks[] = { CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX), CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX), CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX), - CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), - CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX), - CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX), - CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX), - CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), - CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es1, CK_3430ES1), + CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("omapdss_dss", "tv_clk", &dss_tv_fck, CK_3XXX), + CLK("omapdss_dss", "video_clk", &dss_96m_fck, CK_3XXX), + CLK("omapdss_dss", "sys_clk", &dss2_alwon_fck, CK_3XXX), + CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1), + CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX), CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX), diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index d32ed979a8d..8c965671b4d 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -3114,11 +3114,11 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), - CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), - CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), - CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), - CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), - CLK(NULL, "dss_fck", &dss_fck, CK_443X), + CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X), + CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X), + CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X), + CLK("omapdss_dss", "fck", &dss_dss_clk, CK_443X), + CLK("omapdss_dss", "ick", &dss_fck, CK_443X), CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index ab878545bd9..6cb6c03293d 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -258,7 +258,7 @@ static void _resolve_clkdm_deps(struct clockdomain *clkdm, * clkdm_init - set up the clockdomain layer * @clkdms: optional pointer to an array of clockdomains to register * @init_autodeps: optional pointer to an array of autodeps to register - * @custom_funcs: func pointers for arch specfic implementations + * @custom_funcs: func pointers for arch specific implementations * * Set up internal state. If a pointer to an array of clockdomains * @clkdms was supplied, loop through the list of clockdomains, diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 85b3dce6564..5823584d9cd 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -125,7 +125,7 @@ struct clockdomain { }; /** - * struct clkdm_ops - Arch specfic function implementations + * struct clkdm_ops - Arch specific function implementations * @clkdm_add_wkdep: Add a wakeup dependency between clk domains * @clkdm_del_wkdep: Delete a wakeup dependency between clk domains * @clkdm_read_wkdep: Read wakeup dependency state between clk domains diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c index 9d0dec806e9..38830d8d478 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c @@ -247,6 +247,7 @@ struct omap3_cm_regs { u32 per_cm_clksel; u32 emu_cm_clksel; u32 emu_cm_clkstctrl; + u32 pll_cm_autoidle; u32 pll_cm_autoidle2; u32 pll_cm_clksel4; u32 pll_cm_clksel5; @@ -319,6 +320,15 @@ void omap3_cm_save_context(void) omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); cm_context.emu_cm_clkstctrl = omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); + /* + * As per erratum i671, ROM code does not respect the PER DPLL + * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1. + * In this case, even though this register has been saved in + * scratchpad contents, we need to restore AUTO_PERIPH_DPLL + * by ourselves. So, we need to save it anyway. + */ + cm_context.pll_cm_autoidle = + omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); cm_context.pll_cm_autoidle2 = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); cm_context.pll_cm_clksel4 = @@ -441,6 +451,13 @@ void omap3_cm_restore_context(void) CM_CLKSEL1); omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); + /* + * As per erratum i671, ROM code does not respect the PER DPLL + * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1. + * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves. + */ + omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD, + CM_AUTOIDLE); omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD, CM_AUTOIDLE2); omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD, diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 69527941902..da53ba3917c 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -316,8 +316,14 @@ void omap3_save_scratchpad_contents(void) omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); prcm_block_contents.cm_clken_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); + /* + * As per erratum i671, ROM code does not respect the PER DPLL + * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1. + * Then, in anycase, clear these bits to avoid extra latencies. + */ prcm_block_contents.cm_autoidle_pll = - omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL); + omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) & + ~OMAP3430_AUTO_PERIPH_DPLL_MASK; prcm_block_contents.cm_clksel1_pll = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); prcm_block_contents.cm_clksel2_pll = diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index a44c5230340..1c240eff391 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -297,8 +297,8 @@ DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); /** * omap3_cpuidle_update_states() - Update the cpuidle states - * @mpu_deepest_state: Enable states upto and including this for mpu domain - * @core_deepest_state: Enable states upto and including this for core domain + * @mpu_deepest_state: Enable states up to and including this for mpu domain + * @core_deepest_state: Enable states up to and including this for core domain * * This goes through the list of states available and enables and disables the * validity of C states based on deepest state that can be achieved for the diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 0d2d6a9c303..7b855856459 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -35,6 +35,7 @@ #include "mux.h" #include "control.h" +#include "devices.h" #define L3_MODULES_MAX_LEN 12 #define L3_MODULES 3 @@ -65,7 +66,7 @@ static int __init omap3_l3_init(void) WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name); - return PTR_ERR(od); + return IS_ERR(od) ? PTR_ERR(od) : 0; } postcore_initcall(omap3_l3_init); @@ -102,7 +103,7 @@ postcore_initcall(omap4_l3_init); #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) -static struct resource cam_resources[] = { +static struct resource omap2cam_resources[] = { { .start = OMAP24XX_CAMERA_BASE, .end = OMAP24XX_CAMERA_BASE + 0xfff, @@ -114,19 +115,13 @@ static struct resource cam_resources[] = { } }; -static struct platform_device omap_cam_device = { +static struct platform_device omap2cam_device = { .name = "omap24xxcam", .id = -1, - .num_resources = ARRAY_SIZE(cam_resources), - .resource = cam_resources, + .num_resources = ARRAY_SIZE(omap2cam_resources), + .resource = omap2cam_resources, }; - -static inline void omap_init_camera(void) -{ - platform_device_register(&omap_cam_device); -} - -#elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) +#endif static struct resource omap3isp_resources[] = { { @@ -135,11 +130,6 @@ static struct resource omap3isp_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = OMAP3430_ISP_CBUFF_BASE, - .end = OMAP3430_ISP_CBUFF_END, - .flags = IORESOURCE_MEM, - }, - { .start = OMAP3430_ISP_CCP2_BASE, .end = OMAP3430_ISP_CCP2_END, .flags = IORESOURCE_MEM, @@ -175,13 +165,33 @@ static struct resource omap3isp_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = OMAP3430_ISP_CSI2A_BASE, - .end = OMAP3430_ISP_CSI2A_END, + .start = OMAP3430_ISP_CSI2A_REGS1_BASE, + .end = OMAP3430_ISP_CSI2A_REGS1_END, .flags = IORESOURCE_MEM, }, { - .start = OMAP3430_ISP_CSI2PHY_BASE, - .end = OMAP3430_ISP_CSI2PHY_END, + .start = OMAP3430_ISP_CSIPHY2_BASE, + .end = OMAP3430_ISP_CSIPHY2_END, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP3630_ISP_CSI2A_REGS2_BASE, + .end = OMAP3630_ISP_CSI2A_REGS2_END, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP3630_ISP_CSI2C_REGS1_BASE, + .end = OMAP3630_ISP_CSI2C_REGS1_END, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP3630_ISP_CSIPHY1_BASE, + .end = OMAP3630_ISP_CSIPHY1_END, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP3630_ISP_CSI2C_REGS2_BASE, + .end = OMAP3630_ISP_CSI2C_REGS2_END, .flags = IORESOURCE_MEM, }, { @@ -197,15 +207,19 @@ static struct platform_device omap3isp_device = { .resource = omap3isp_resources, }; -static inline void omap_init_camera(void) +int omap3_init_camera(struct isp_platform_data *pdata) { - platform_device_register(&omap3isp_device); + omap3isp_device.dev.platform_data = pdata; + return platform_device_register(&omap3isp_device); } -#else + static inline void omap_init_camera(void) { -} +#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) + if (cpu_is_omap24xx()) + platform_device_register(&omap2cam_device); #endif +} struct omap_device_pm_latency omap_keyboard_latency[] = { { @@ -239,7 +253,7 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data ARRAY_SIZE(omap_keyboard_latency), 0); if (IS_ERR(od)) { - WARN(1, "Cant build omap_device for %s:%s.\n", + WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name); return PTR_ERR(od); } @@ -359,7 +373,7 @@ static int omap_mcspi_init(struct omap_hwmod *oh, void *unused) od = omap_device_build(name, spi_num, oh, pdata, sizeof(*pdata), omap_mcspi_latency, ARRAY_SIZE(omap_mcspi_latency), 0); - WARN(IS_ERR(od), "Cant build omap_device for %s:%s\n", + WARN(IS_ERR(od), "Can't build omap_device for %s:%s\n", name, oh->name); kfree(pdata); return 0; @@ -711,7 +725,7 @@ static int __init omap_init_wdt(void) od = omap_device_build(dev_name, id, oh, NULL, 0, omap_wdt_latency, ARRAY_SIZE(omap_wdt_latency), 0); - WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n", + WARN(IS_ERR(od), "Can't build omap_device for %s:%s.\n", dev_name, oh->name); return 0; } diff --git a/arch/arm/mach-omap2/devices.h b/arch/arm/mach-omap2/devices.h new file mode 100644 index 00000000000..f61eb6e5d13 --- /dev/null +++ b/arch/arm/mach-omap2/devices.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-omap2/devices.h + * + * OMAP2 platform device setup/initialization + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __ARCH_ARM_MACH_OMAP_DEVICES_H +#define __ARCH_ARM_MACH_OMAP_DEVICES_H + +struct isp_platform_data; + +int omap3_init_camera(struct isp_platform_data *pdata); + +#endif diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index b18db84b034..256d23fb79a 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -23,6 +23,8 @@ #include <linux/err.h> #include <plat/display.h> +#include <plat/omap_hwmod.h> +#include <plat/omap_device.h> static struct platform_device omap_display_device = { .name = "omapdss", @@ -32,9 +34,87 @@ static struct platform_device omap_display_device = { }, }; +static struct omap_device_pm_latency omap_dss_latency[] = { + [0] = { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, +}; + +/* oh_core is used for getting opt-clocks */ +static struct omap_hwmod *oh_core; + +static bool opt_clock_available(const char *clk_role) +{ + int i; + + for (i = 0; i < oh_core->opt_clks_cnt; i++) { + if (!strcmp(oh_core->opt_clks[i].role, clk_role)) + return true; + } + return false; +} + int __init omap_display_init(struct omap_dss_board_info *board_data) { int r = 0; + struct omap_hwmod *oh; + struct omap_device *od; + int i; + struct omap_display_platform_data pdata; + + /* + * omap: valid DSS hwmod names + * omap2,3,4: dss_core, dss_dispc, dss_rfbi, dss_venc + * omap3,4: dss_dsi1 + * omap4: dss_dsi2, dss_hdmi + */ + char *oh_name[] = { "dss_core", "dss_dispc", "dss_rfbi", "dss_venc", + "dss_dsi1", "dss_dsi2", "dss_hdmi" }; + char *dev_name[] = { "omapdss_dss", "omapdss_dispc", "omapdss_rfbi", + "omapdss_venc", "omapdss_dsi1", "omapdss_dsi2", + "omapdss_hdmi" }; + int oh_count; + + memset(&pdata, 0, sizeof(pdata)); + + if (cpu_is_omap24xx()) + oh_count = ARRAY_SIZE(oh_name) - 3; + /* last 3 hwmod dev in oh_name are not available for omap2 */ + else if (cpu_is_omap44xx()) + oh_count = ARRAY_SIZE(oh_name); + else + oh_count = ARRAY_SIZE(oh_name) - 2; + /* last 2 hwmod dev in oh_name are not available for omap3 */ + + /* opt_clks are always associated with dss hwmod */ + oh_core = omap_hwmod_lookup("dss_core"); + if (!oh_core) { + pr_err("Could not look up dss_core.\n"); + return -ENODEV; + } + + pdata.board_data = board_data; + pdata.board_data->get_last_off_on_transaction_id = NULL; + pdata.opt_clock_available = opt_clock_available; + + for (i = 0; i < oh_count; i++) { + oh = omap_hwmod_lookup(oh_name[i]); + if (!oh) { + pr_err("Could not look up %s\n", oh_name[i]); + return -ENODEV; + } + + od = omap_device_build(dev_name[i], -1, oh, &pdata, + sizeof(struct omap_display_platform_data), + omap_dss_latency, + ARRAY_SIZE(omap_dss_latency), 0); + + if (WARN((IS_ERR(od)), "Could not build omap_device for %s\n", + oh_name[i])) + return -ENODEV; + } omap_display_device.dev.platform_data = board_data; r = platform_device_register(&omap_display_device); diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index 34922b2d2e3..c9ff0e79703 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -262,7 +262,7 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0); kfree(p); if (IS_ERR(od)) { - pr_err("%s: Cant build omap_device for %s:%s.\n", + pr_err("%s: Can't build omap_device for %s:%s.\n", __func__, name, oh->name); return PTR_ERR(od); } diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c index 413de18c1d2..9529842ae05 100644 --- a/arch/arm/mach-omap2/gpio.c +++ b/arch/arm/mach-omap2/gpio.c @@ -82,7 +82,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) kfree(pdata); if (IS_ERR(od)) { - WARN(1, "Cant build omap_device for %s:%s.\n", + WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name); return PTR_ERR(od); } diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 674174365f7..130034bf01d 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -693,6 +693,7 @@ static int __init gpmc_init(void) { u32 l, irq; int cs, ret = -EINVAL; + int gpmc_irq; char *ck = NULL; if (cpu_is_omap24xx()) { @@ -701,12 +702,15 @@ static int __init gpmc_init(void) l = OMAP2420_GPMC_BASE; else l = OMAP34XX_GPMC_BASE; + gpmc_irq = INT_34XX_GPMC_IRQ; } else if (cpu_is_omap34xx()) { ck = "gpmc_fck"; l = OMAP34XX_GPMC_BASE; + gpmc_irq = INT_34XX_GPMC_IRQ; } else if (cpu_is_omap44xx()) { ck = "gpmc_ck"; l = OMAP44XX_GPMC_BASE; + gpmc_irq = OMAP44XX_IRQ_GPMC; } if (WARN_ON(!ck)) @@ -739,16 +743,17 @@ static int __init gpmc_init(void) /* initalize the irq_chained */ irq = OMAP_GPMC_IRQ_BASE; for (cs = 0; cs < GPMC_CS_NUM; cs++) { - set_irq_handler(irq, handle_simple_irq); + irq_set_chip_and_handler(irq, &dummy_irq_chip, + handle_simple_irq); set_irq_flags(irq, IRQF_VALID); irq++; } - ret = request_irq(INT_34XX_GPMC_IRQ, + ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base); if (ret) pr_err("gpmc: irq-%d could not claim: err %d\n", - INT_34XX_GPMC_IRQ, ret); + gpmc_irq, ret); return ret; } postcore_initcall(gpmc_init); @@ -757,8 +762,6 @@ static irqreturn_t gpmc_handle_irq(int irq, void *dev) { u8 cs; - if (irq != INT_34XX_GPMC_IRQ) - return IRQ_HANDLED; /* check cs to invoke the irq */ cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7; if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END) diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 137e1a5f3d8..b2f30bed5a2 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -465,7 +465,7 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data, sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false); if (IS_ERR(od)) { - WARN(1, "Cant build omap_device for %s:%s.\n", name, oh->name); + WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name); kfree(mmc_data->slots[0].name); goto done; } diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index bc524b94fd5..237e4530abf 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -223,8 +223,7 @@ void __init omap_init_irq(void) nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : ""); for (i = 0; i < nr_of_irqs; i++) { - set_irq_chip(i, &omap_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &omap_irq_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID); } } diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 565b9064a32..4a6ef6ab845 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -149,7 +149,7 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused) ARRAY_SIZE(omap2_mcbsp_latency), false); kfree(pdata); if (IS_ERR(od)) { - pr_err("%s: Cant build omap_device for %s:%s.\n", __func__, + pr_err("%s: Can't build omap_device for %s:%s.\n", __func__, name, oh->name); return PTR_ERR(od); } diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index bb043cbb388..a4ab1e36431 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -518,7 +518,7 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused) seq_printf(s, "/* %s */\n", m->muxnames[mode]); /* - * XXX: Might be revisited to support differences accross + * XXX: Might be revisited to support differences across * same OMAP generation. */ seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def); diff --git a/arch/arm/mach-omap2/mux2430.h b/arch/arm/mach-omap2/mux2430.h index adbea0d03e0..9fd93149ebd 100644 --- a/arch/arm/mach-omap2/mux2430.h +++ b/arch/arm/mach-omap2/mux2430.h @@ -22,7 +22,7 @@ * absolute addresses. The name in the macro is the mode-0 name of * the pin. NOTE: These registers are 8-bits wide. * - * Note that these defines use SDMMC instead of MMC for compability + * Note that these defines use SDMMC instead of MMC for compatibility * with signal names used in 3630. */ #define OMAP2430_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x000 diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 62823467163..c4d0ae87d62 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -1168,11 +1168,6 @@ static struct omap_hwmod_class omap2420_dss_hwmod_class = { .sysc = &omap2420_dss_sysc, }; -/* dss */ -static struct omap_hwmod_irq_info omap2420_dss_irqs[] = { - { .irq = 25 }, -}; - static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = { { .name = "dispc", .dma_req = 5 }, }; @@ -1221,8 +1216,6 @@ static struct omap_hwmod omap2420_dss_core_hwmod = { .name = "dss_core", .class = &omap2420_dss_hwmod_class, .main_clk = "dss1_fck", /* instead of dss_fck */ - .mpu_irqs = omap2420_dss_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dss_irqs), .sdma_reqs = omap2420_dss_sdma_chs, .sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs), .prcm = { @@ -1265,6 +1258,10 @@ static struct omap_hwmod_class omap2420_dispc_hwmod_class = { .sysc = &omap2420_dispc_sysc, }; +static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = { + { .irq = 25 }, +}; + static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = { { .pa_start = 0x48050400, @@ -1297,6 +1294,8 @@ static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = { static struct omap_hwmod omap2420_dss_dispc_hwmod = { .name = "dss_dispc", .class = &omap2420_dispc_hwmod_class, + .mpu_irqs = omap2420_dispc_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dispc_irqs), .main_clk = "dss1_fck", .prcm = { .omap2 = { @@ -1640,6 +1639,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { static struct omap_hwmod omap2420_gpio1_hwmod = { .name = "gpio1", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap242x_gpio1_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs), .main_clk = "gpios_fck", @@ -1670,6 +1670,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { static struct omap_hwmod omap2420_gpio2_hwmod = { .name = "gpio2", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap242x_gpio2_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs), .main_clk = "gpios_fck", @@ -1700,6 +1701,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { static struct omap_hwmod omap2420_gpio3_hwmod = { .name = "gpio3", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap242x_gpio3_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs), .main_clk = "gpios_fck", @@ -1730,6 +1732,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { static struct omap_hwmod omap2420_gpio4_hwmod = { .name = "gpio4", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap242x_gpio4_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs), .main_clk = "gpios_fck", @@ -1783,7 +1786,7 @@ static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = { static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = { { .pa_start = 0x48056000, - .pa_end = 0x4a0560ff, + .pa_end = 0x48056fff, .flags = ADDR_TYPE_RT }, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 0fdf2cabfb1..9682dd519f8 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -1268,10 +1268,6 @@ static struct omap_hwmod_class omap2430_dss_hwmod_class = { .sysc = &omap2430_dss_sysc, }; -/* dss */ -static struct omap_hwmod_irq_info omap2430_dss_irqs[] = { - { .irq = 25 }, -}; static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = { { .name = "dispc", .dma_req = 5 }, }; @@ -1314,8 +1310,6 @@ static struct omap_hwmod omap2430_dss_core_hwmod = { .name = "dss_core", .class = &omap2430_dss_hwmod_class, .main_clk = "dss1_fck", /* instead of dss_fck */ - .mpu_irqs = omap2430_dss_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dss_irqs), .sdma_reqs = omap2430_dss_sdma_chs, .sdma_reqs_cnt = ARRAY_SIZE(omap2430_dss_sdma_chs), .prcm = { @@ -1358,6 +1352,10 @@ static struct omap_hwmod_class omap2430_dispc_hwmod_class = { .sysc = &omap2430_dispc_sysc, }; +static struct omap_hwmod_irq_info omap2430_dispc_irqs[] = { + { .irq = 25 }, +}; + static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = { { .pa_start = 0x48050400, @@ -1384,6 +1382,8 @@ static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = { static struct omap_hwmod omap2430_dss_dispc_hwmod = { .name = "dss_dispc", .class = &omap2430_dispc_hwmod_class, + .mpu_irqs = omap2430_dispc_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dispc_irqs), .main_clk = "dss1_fck", .prcm = { .omap2 = { @@ -1559,7 +1559,7 @@ static struct omap_hwmod omap2430_i2c1_hwmod = { * I2CHS IP's do not follow the usual pattern. * prcm_reg_id alone cannot be used to program * the iclk and fclk. Needs to be handled using - * additonal flags when clk handling is moved + * additional flags when clk handling is moved * to hwmod framework. */ .module_offs = CORE_MOD, @@ -1742,6 +1742,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { static struct omap_hwmod omap2430_gpio1_hwmod = { .name = "gpio1", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap243x_gpio1_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs), .main_clk = "gpios_fck", @@ -1772,6 +1773,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { static struct omap_hwmod omap2430_gpio2_hwmod = { .name = "gpio2", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap243x_gpio2_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs), .main_clk = "gpios_fck", @@ -1802,6 +1804,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { static struct omap_hwmod omap2430_gpio3_hwmod = { .name = "gpio3", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap243x_gpio3_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs), .main_clk = "gpios_fck", @@ -1832,6 +1835,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { static struct omap_hwmod omap2430_gpio4_hwmod = { .name = "gpio4", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap243x_gpio4_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs), .main_clk = "gpios_fck", @@ -1862,6 +1866,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { static struct omap_hwmod omap2430_gpio5_hwmod = { .name = "gpio5", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap243x_gpio5_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs), .main_clk = "gpio5_fck", @@ -1915,7 +1920,7 @@ static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = { static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = { { .pa_start = 0x48056000, - .pa_end = 0x4a0560ff, + .pa_end = 0x48056fff, .flags = ADDR_TYPE_RT }, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index c819c306693..909a84de668 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1480,11 +1480,6 @@ static struct omap_hwmod_class omap3xxx_dss_hwmod_class = { .sysc = &omap3xxx_dss_sysc, }; -/* dss */ -static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = { - { .irq = 25 }, -}; - static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { { .name = "dispc", .dma_req = 5 }, { .name = "dsi1", .dma_req = 74 }, @@ -1548,7 +1543,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = { static struct omap_hwmod_opt_clk dss_opt_clks[] = { { .role = "tv_clk", .clk = "dss_tv_fck" }, - { .role = "dssclk", .clk = "dss_96m_fck" }, + { .role = "video_clk", .clk = "dss_96m_fck" }, { .role = "sys_clk", .clk = "dss2_alwon_fck" }, }; @@ -1556,8 +1551,6 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = { .name = "dss_core", .class = &omap3xxx_dss_hwmod_class, .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ - .mpu_irqs = omap3xxx_dss_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs), .sdma_reqs = omap3xxx_dss_sdma_chs, .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs), @@ -1584,8 +1577,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = { .name = "dss_core", .class = &omap3xxx_dss_hwmod_class, .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ - .mpu_irqs = omap3xxx_dss_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs), .sdma_reqs = omap3xxx_dss_sdma_chs, .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs), @@ -1631,6 +1622,10 @@ static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = { .sysc = &omap3xxx_dispc_sysc, }; +static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = { + { .irq = 25 }, +}; + static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = { { .pa_start = 0x48050400, @@ -1664,6 +1659,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = { static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { .name = "dss_dispc", .class = &omap3xxx_dispc_hwmod_class, + .mpu_irqs = omap3xxx_dispc_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dispc_irqs), .main_clk = "dss1_alwon_fck", .prcm = { .omap2 = { @@ -1689,6 +1686,10 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { .name = "dsi", }; +static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { + { .irq = 25 }, +}; + /* dss_dsi1 */ static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { { @@ -1722,6 +1723,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = { static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { .name = "dss_dsi1", .class = &omap3xxx_dsi_hwmod_class, + .mpu_irqs = omap3xxx_dsi1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dsi1_irqs), .main_clk = "dss1_alwon_fck", .prcm = { .omap2 = { @@ -2138,6 +2141,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = { static struct omap_hwmod omap3xxx_gpio1_hwmod = { .name = "gpio1", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap3xxx_gpio1_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs), .main_clk = "gpio1_ick", @@ -2174,6 +2178,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = { static struct omap_hwmod omap3xxx_gpio2_hwmod = { .name = "gpio2", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap3xxx_gpio2_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs), .main_clk = "gpio2_ick", @@ -2210,6 +2215,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = { static struct omap_hwmod omap3xxx_gpio3_hwmod = { .name = "gpio3", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap3xxx_gpio3_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs), .main_clk = "gpio3_ick", @@ -2246,6 +2252,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = { static struct omap_hwmod omap3xxx_gpio4_hwmod = { .name = "gpio4", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap3xxx_gpio4_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs), .main_clk = "gpio4_ick", @@ -2282,6 +2289,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = { static struct omap_hwmod omap3xxx_gpio5_hwmod = { .name = "gpio5", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap3xxx_gpio5_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs), .main_clk = "gpio5_ick", @@ -2318,6 +2326,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = { static struct omap_hwmod omap3xxx_gpio6_hwmod = { .name = "gpio6", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap3xxx_gpio6_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs), .main_clk = "gpio6_ick", @@ -2383,7 +2392,7 @@ static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = { static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { { .pa_start = 0x48056000, - .pa_end = 0x4a0560ff, + .pa_end = 0x48056fff, .flags = ADDR_TYPE_RT }, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 3e88dd3f8ef..abc548a0c98 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -885,7 +885,7 @@ static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = { static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { { .pa_start = 0x4a056000, - .pa_end = 0x4a0560ff, + .pa_end = 0x4a056fff, .flags = ADDR_TYPE_RT }, }; diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c index 265bff3acb9..4321e793892 100644 --- a/arch/arm/mach-omap2/omap_l3_smx.c +++ b/arch/arm/mach-omap2/omap_l3_smx.c @@ -196,11 +196,11 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3) /* No timeout error for debug sources */ } - base = ((l3->rt) + (*(omap3_l3_bases[int_type] + err_source))); - /* identify the error source */ for (err_source = 0; !(status & (1 << err_source)); err_source++) ; + + base = l3->rt + *(omap3_l3_bases[int_type] + err_source); error = omap3_l3_readll(base, L3_ERROR_LOG); if (error) { @@ -226,7 +226,6 @@ static int __init omap3_l3_probe(struct platform_device *pdev) struct omap3_l3 *l3; struct resource *res; int ret; - int irq; l3 = kzalloc(sizeof(*l3), GFP_KERNEL); if (!l3) { @@ -249,18 +248,17 @@ static int __init omap3_l3_probe(struct platform_device *pdev) goto err2; } - irq = platform_get_irq(pdev, 0); - ret = request_irq(irq, omap3_l3_app_irq, + l3->debug_irq = platform_get_irq(pdev, 0); + ret = request_irq(l3->debug_irq, omap3_l3_app_irq, IRQF_DISABLED | IRQF_TRIGGER_RISING, "l3-debug-irq", l3); if (ret) { dev_err(&pdev->dev, "couldn't request debug irq\n"); goto err3; } - l3->debug_irq = irq; - irq = platform_get_irq(pdev, 1); - ret = request_irq(irq, omap3_l3_app_irq, + l3->app_irq = platform_get_irq(pdev, 1); + ret = request_irq(l3->app_irq, omap3_l3_app_irq, IRQF_DISABLED | IRQF_TRIGGER_RISING, "l3-app-irq", l3); @@ -269,7 +267,6 @@ static int __init omap3_l3_probe(struct platform_device *pdev) goto err4; } - l3->app_irq = irq; goto err0; err4: diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c index e2e605fe913..05f6abc96b0 100644 --- a/arch/arm/mach-omap2/omap_phy_internal.c +++ b/arch/arm/mach-omap2/omap_phy_internal.c @@ -112,12 +112,12 @@ int omap4430_phy_power(struct device *dev, int ID, int on) else /* * Enable VBUS Valid, AValid and IDDIG - * high impedence + * high impedance */ __raw_writel(IDDIG | AVALID | VBUSVALID, ctrl_base + USBOTGHS_CONTROL); } else { - /* Enable session END and IDIG to high impedence. */ + /* Enable session END and IDIG to high impedance. */ __raw_writel(SESSEND | IDDIG, ctrl_base + USBOTGHS_CONTROL); } diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c index 0a8e74e3e81..07d6140baa9 100644 --- a/arch/arm/mach-omap2/omap_twl.c +++ b/arch/arm/mach-omap2/omap_twl.c @@ -308,7 +308,7 @@ int __init omap3_twl_init(void) * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages, * in those scenarios this bit is to be cleared (enable = false). * - * Returns 0 on sucess, error is returned if I2C read/write fails. + * Returns 0 on success, error is returned if I2C read/write fails. */ int __init omap3_twl_set_sr_bit(bool enable) { diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 30af3351c2d..49486f522dc 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -89,6 +89,7 @@ static void omap2_init_processor_devices(void) if (cpu_is_omap44xx()) { _init_omap_device("l3_main_1", &l3_dev); _init_omap_device("dsp", &dsp_dev); + _init_omap_device("iva", &iva_dev); } else { _init_omap_device("l3_main", &l3_dev); } diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 49c6513e90d..9af08473bf1 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -196,7 +196,7 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused) /** * pwrdm_init - set up the powerdomain layer * @pwrdm_list: array of struct powerdomain pointers to register - * @custom_funcs: func pointers for arch specfic implementations + * @custom_funcs: func pointers for arch specific implementations * * Loop through the array of powerdomains @pwrdm_list, registering all * that are available on the current CPU. If pwrdm_list is supplied diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index 027f40bd235..d23d979b9c3 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -121,7 +121,7 @@ struct powerdomain { }; /** - * struct pwrdm_ops - Arch specfic function implementations + * struct pwrdm_ops - Arch specific function implementations * @pwrdm_set_next_pwrst: Set the target power state for a pd * @pwrdm_read_next_pwrst: Read the target power state set for a pd * @pwrdm_read_pwrst: Read the current power state of a pd diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index 9c9c113788b..469a920a74d 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -72,7 +72,7 @@ static struct powerdomain mpu_3xxx_pwrdm = { /* * The USBTLL Save-and-Restore mechanism is broken on - * 3430s upto ES3.0 and 3630ES1.0. Hence this feature + * 3430s up to ES3.0 and 3630ES1.0. Hence this feature * needs to be disabled on these chips. * Refer: 3430 errata ID i459 and 3630 errata ID i579 * diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index 8f674c9442b..13e24f913dd 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -247,7 +247,7 @@ static void sr_stop_vddautocomp(struct omap_sr *sr) * driver register and sr device intializtion API's. Only one call * will ultimately succeed. * - * Currenly this function registers interrrupt handler for a particular SR + * Currently this function registers interrrupt handler for a particular SR * if smartreflex class driver is already registered and has * requested for interrupts and the SR interrupt line in present. */ diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c index 954682e6439..31c0ac4cd66 100644 --- a/arch/arm/mach-omap2/timer-mpu.c +++ b/arch/arm/mach-omap2/timer-mpu.c @@ -26,9 +26,14 @@ /* * Setup the local clock events for a CPU. */ -void __cpuinit local_timer_setup(struct clock_event_device *evt) +int __cpuinit local_timer_setup(struct clock_event_device *evt) { + /* Local timers are not supprted on OMAP4430 ES1.0 */ + if (omap_rev() == OMAP4430_REV_ES1_0) + return -ENXIO; + evt->irq = OMAP44XX_IRQ_LOCALTIMER; twd_timer_setup(evt); + return 0; } diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c index c6facf7becf..0c1552d9d99 100644 --- a/arch/arm/mach-omap2/voltage.c +++ b/arch/arm/mach-omap2/voltage.c @@ -114,7 +114,6 @@ static int __init _config_common_vdd_data(struct omap_vdd_info *vdd) sys_clk_speed /= 1000; /* Generic voltage parameters */ - vdd->curr_volt = 1200000; vdd->volt_scale = vp_forceupdate_scale_voltage; vdd->vp_enabled = false; @@ -851,7 +850,7 @@ int omap_voltage_scale_vdd(struct voltagedomain *voltdm, * @voltdm: pointer to the VDD whose voltage is to be reset. * * This API finds out the correct voltage the voltage domain is supposed - * to be at and resets the voltage to that level. Should be used expecially + * to be at and resets the voltage to that level. Should be used especially * while disabling any voltage compensation modules. */ void omap_voltage_reset(struct voltagedomain *voltdm) @@ -912,7 +911,7 @@ void omap_voltage_get_volttable(struct voltagedomain *voltdm, * This API searches only through the non-compensated voltages int the * voltage table. * Returns pointer to the voltage table entry corresponding to volt on - * sucess. Returns -ENODATA if no voltage table exisits for the passed voltage + * success. Returns -ENODATA if no voltage table exisits for the passed voltage * domain or if there is no matching entry. */ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm, diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index 1a5d6a0e260..5ceafdccc45 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c @@ -19,7 +19,7 @@ #include "common.h" /* - * The Orion has fully programable address map. There's a separate address + * The Orion has fully programmable address map. There's a separate address * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIe, USB, * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own * address decode windows that allow it to access any of the Orion resources. diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index c10a1171537..b7d4591214e 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -213,7 +213,7 @@ void __init db88f5281_pci_preinit(void) pin = DB88F5281_PCI_SLOT0_IRQ_PIN; if (gpio_request(pin, "PCI Int1") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "db88f5281_pci_preinit faield to " "set_irq_type pin %d\n", pin); @@ -226,7 +226,7 @@ void __init db88f5281_pci_preinit(void) pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; if (gpio_request(pin, "PCI Int2") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "db88f5281_pci_preinit faield " "to set_irq_type pin %d\n", pin); diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index ed85891f869..43cf8bc9767 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -34,8 +34,8 @@ void __init orion5x_init_irq(void) * Initialize gpiolib for GPIOs 0-31. */ orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START); - set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler); + irq_set_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler); + irq_set_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler); + irq_set_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler); + irq_set_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler); } diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c index 429ecafe9fd..a5930f83958 100644 --- a/arch/arm/mach-orion5x/net2big-setup.c +++ b/arch/arm/mach-orion5x/net2big-setup.c @@ -190,7 +190,7 @@ err_free_1: * The power front LEDs (blue and red) and SATA red LEDs are controlled via a * single GPIO line and are compatible with the leds-gpio driver. * - * The SATA blue LEDs have some hardware blink capabilities which are detailled + * The SATA blue LEDs have some hardware blink capabilities which are detailed * in the following array: * * SATAx blue LED | SATAx activity | LED state diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index 67ec6959b26..4fc46772a08 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -148,7 +148,7 @@ void __init rd88f5182_pci_preinit(void) pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; if (gpio_request(pin, "PCI IntA") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "rd88f5182_pci_preinit faield to " "set_irq_type pin %d\n", pin); @@ -161,7 +161,7 @@ void __init rd88f5182_pci_preinit(void) pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; if (gpio_request(pin, "PCI IntB") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "rd88f5182_pci_preinit faield to " "set_irq_type pin %d\n", pin); diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c index 5653ee6c71d..61600414391 100644 --- a/arch/arm/mach-orion5x/terastation_pro2-setup.c +++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c @@ -88,7 +88,7 @@ void __init tsp2_pci_preinit(void) pin = TSP2_PCI_SLOT0_IRQ_PIN; if (gpio_request(pin, "PCI Int1") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "tsp2_pci_preinit failed " "to set_irq_type pin %d\n", pin); diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index 8bbd27ea673..e6d64494d3d 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -36,7 +36,7 @@ /**************************************************************************** * 8MiB NOR flash. The struct mtd_partition is not in the same order as the - * partitions on the device because we want to keep compatability with + * partitions on the device because we want to keep compatibility with * existing QNAP firmware. * * Layout as used by QNAP: @@ -117,7 +117,7 @@ void __init qnap_ts209_pci_preinit(void) pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN; if (gpio_request(pin, "PCI Int1") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "qnap_ts209_pci_preinit failed to " "set_irq_type pin %d\n", pin); @@ -131,7 +131,7 @@ void __init qnap_ts209_pci_preinit(void) pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN; if (gpio_request(pin, "PCI Int2") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "qnap_ts209_pci_preinit failed " "to set_irq_type pin %d\n", pin); diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c index 92f393f08fa..9eac8192d92 100644 --- a/arch/arm/mach-orion5x/ts409-setup.c +++ b/arch/arm/mach-orion5x/ts409-setup.c @@ -56,7 +56,7 @@ /**************************************************************************** * 8MiB NOR flash. The struct mtd_partition is not in the same order as the - * partitions on the device because we want to keep compatability with + * partitions on the device because we want to keep compatibility with * existing QNAP firmware. * * Layout as used by QNAP: diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c index 8554707d20a..edb1dd2d161 100644 --- a/arch/arm/mach-orion5x/ts78xx-setup.c +++ b/arch/arm/mach-orion5x/ts78xx-setup.c @@ -402,7 +402,7 @@ static void ts78xx_fpga_supports(void) /* enable devices if magic matches */ switch ((ts78xx_fpga.id >> 8) & 0xffffff) { case TS7800_FPGA_MAGIC: - printk(KERN_WARNING "TS-7800 FPGA: unrecognized revision 0x%.2x\n", + pr_warning("TS-7800 FPGA: unrecognized revision 0x%.2x\n", ts78xx_fpga.id & 0xff); ts78xx_fpga.supports.ts_rtc.present = 1; ts78xx_fpga.supports.ts_nand.present = 1; @@ -423,7 +423,7 @@ static int ts78xx_fpga_load_devices(void) if (ts78xx_fpga.supports.ts_rtc.present == 1) { tmp = ts78xx_ts_rtc_load(); if (tmp) { - printk(KERN_INFO "TS-78xx: RTC not registered\n"); + pr_info("TS-78xx: RTC not registered\n"); ts78xx_fpga.supports.ts_rtc.present = 0; } ret |= tmp; @@ -431,7 +431,7 @@ static int ts78xx_fpga_load_devices(void) if (ts78xx_fpga.supports.ts_nand.present == 1) { tmp = ts78xx_ts_nand_load(); if (tmp) { - printk(KERN_INFO "TS-78xx: NAND not registered\n"); + pr_info("TS-78xx: NAND not registered\n"); ts78xx_fpga.supports.ts_nand.present = 0; } ret |= tmp; @@ -439,7 +439,7 @@ static int ts78xx_fpga_load_devices(void) if (ts78xx_fpga.supports.ts_rng.present == 1) { tmp = ts78xx_ts_rng_load(); if (tmp) { - printk(KERN_INFO "TS-78xx: RNG not registered\n"); + pr_info("TS-78xx: RNG not registered\n"); ts78xx_fpga.supports.ts_rng.present = 0; } ret |= tmp; @@ -466,7 +466,7 @@ static int ts78xx_fpga_load(void) { ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE); - printk(KERN_INFO "TS-78xx FPGA: magic=0x%.6x, rev=0x%.2x\n", + pr_info("TS-78xx FPGA: magic=0x%.6x, rev=0x%.2x\n", (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff); @@ -494,7 +494,7 @@ static int ts78xx_fpga_unload(void) * UrJTAG SVN since r1381 can be used to reprogram the FPGA */ if (ts78xx_fpga.id != fpga_id) { - printk(KERN_ERR "TS-78xx FPGA: magic/rev mismatch\n" + pr_err("TS-78xx FPGA: magic/rev mismatch\n" "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n", (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff, (fpga_id >> 8) & 0xffffff, fpga_id & 0xff); @@ -525,7 +525,7 @@ static ssize_t ts78xx_fpga_store(struct kobject *kobj, int value, ret; if (ts78xx_fpga.state < 0) { - printk(KERN_ERR "TS-78xx FPGA: borked, you must powercycle asap\n"); + pr_err("TS-78xx FPGA: borked, you must powercycle asap\n"); return -EBUSY; } @@ -534,7 +534,7 @@ static ssize_t ts78xx_fpga_store(struct kobject *kobj, else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0) value = 0; else { - printk(KERN_ERR "ts78xx_fpga_store: Invalid value\n"); + pr_err("ts78xx_fpga_store: Invalid value\n"); return -EINVAL; } @@ -616,7 +616,7 @@ static void __init ts78xx_init(void) ret = ts78xx_fpga_load(); ret = sysfs_create_file(power_kobj, &ts78xx_fpga_attr.attr); if (ret) - printk(KERN_ERR "sysfs_create_file failed: %d\n", ret); + pr_err("sysfs_create_file failed: %d\n", ret); } MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC") diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c index c69c180aec7..7608c7a288c 100644 --- a/arch/arm/mach-pnx4008/irq.c +++ b/arch/arm/mach-pnx4008/irq.c @@ -58,22 +58,22 @@ static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type) case IRQ_TYPE_EDGE_RISING: __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */ - set_irq_handler(d->irq, handle_edge_irq); + irq_set_handler(d->irq, handle_edge_irq); break; case IRQ_TYPE_EDGE_FALLING: __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */ - set_irq_handler(d->irq, handle_edge_irq); + irq_set_handler(d->irq, handle_edge_irq); break; case IRQ_TYPE_LEVEL_LOW: __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */ - set_irq_handler(d->irq, handle_level_irq); + irq_set_handler(d->irq, handle_level_irq); break; case IRQ_TYPE_LEVEL_HIGH: __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */ - set_irq_handler(d->irq, handle_level_irq); + irq_set_handler(d->irq, handle_level_irq); break; /* IRQ_TYPE_EDGE_BOTH is not supported */ @@ -98,7 +98,7 @@ void __init pnx4008_init_irq(void) /* configure IRQ's */ for (i = 0; i < NR_IRQS; i++) { set_irq_flags(i, IRQF_VALID); - set_irq_chip(i, &pnx4008_irq_chip); + irq_set_chip(i, &pnx4008_irq_chip); pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]); } diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c index 3499fada73a..4cb069fd9af 100644 --- a/arch/arm/mach-pxa/am200epd.c +++ b/arch/arm/mach-pxa/am200epd.c @@ -128,8 +128,8 @@ static int am200_init_gpio_regs(struct metronomefb_par *par) return 0; err_req_gpio: - while (i > 0) - gpio_free(gpios[i--]); + while (--i >= 0) + gpio_free(gpios[i]); return err; } @@ -194,7 +194,7 @@ static struct notifier_block am200_fb_notif = { }; /* this gets called as part of our init. these steps must be done now so - * that we can use set_pxa_fb_info */ + * that we can use pxa_set_fb_info */ static void __init am200_presetup_fb(void) { int fw; @@ -249,7 +249,7 @@ static void __init am200_presetup_fb(void) /* we divide since we told the LCD controller we're 16bpp */ am200_fb_info.modes->xres /= 2; - set_pxa_fb_info(&am200_fb_info); + pxa_set_fb_info(NULL, &am200_fb_info); } diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c index 993d75e6639..fa8bad235d9 100644 --- a/arch/arm/mach-pxa/am300epd.c +++ b/arch/arm/mach-pxa/am300epd.c @@ -125,10 +125,7 @@ static int am300_init_gpio_regs(struct broadsheetfb_par *par) if (err) { dev_err(&am300_device->dev, "failed requesting " "gpio %d, err=%d\n", i, err); - while (i >= DB0_GPIO_PIN) - gpio_free(i--); - i = ARRAY_SIZE(gpios) - 1; - goto err_req_gpio; + goto err_req_gpio2; } } @@ -159,9 +156,13 @@ static int am300_init_gpio_regs(struct broadsheetfb_par *par) return 0; +err_req_gpio2: + while (--i >= DB0_GPIO_PIN) + gpio_free(i); + i = ARRAY_SIZE(gpios); err_req_gpio: - while (i > 0) - gpio_free(gpios[i--]); + while (--i >= 0) + gpio_free(gpios[i]); return err; } diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index e194d928cda..bfbecec6d05 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -27,6 +27,7 @@ #include <linux/mtd/partitions.h> #include <linux/types.h> #include <linux/i2c/pcf857x.h> +#include <linux/i2c/pxa-i2c.h> #include <linux/mtd/nand.h> #include <linux/mtd/physmap.h> #include <linux/regulator/max1586.h> @@ -51,8 +52,6 @@ #include <mach/irda.h> #include <mach/ohci.h> -#include <plat/i2c.h> - #include "generic.h" #include "devices.h" @@ -264,7 +263,7 @@ static void __init balloon3_lcd_init(void) } balloon3_lcd_screen.pxafb_backlight_power = balloon3_backlight_power; - set_pxa_fb_info(&balloon3_lcd_screen); + pxa_set_fb_info(NULL, &balloon3_lcd_screen); return; err2: @@ -528,13 +527,13 @@ static void __init balloon3_init_irq(void) pxa27x_init_irq(); /* setup extra Balloon3 irqs */ for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) { - set_irq_chip(irq, &balloon3_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &balloon3_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } - set_irq_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler); - set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING); + irq_set_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler); + irq_set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING); pr_debug("%s: chained handler installed - irq %d automatically " "enabled\n", __func__, BALLOON3_AUX_NIRQ); diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c index a2380cd76f8..8b1a30959fa 100644 --- a/arch/arm/mach-pxa/cm-x2xx-pci.c +++ b/arch/arm/mach-pxa/cm-x2xx-pci.c @@ -70,9 +70,10 @@ void __cmx2xx_pci_init_irq(int irq_gpio) cmx2xx_it8152_irq_gpio = irq_gpio; - set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING); - set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx2xx_it8152_irq_demux); + irq_set_chained_handler(gpio_to_irq(irq_gpio), + cmx2xx_it8152_irq_demux); } #ifdef CONFIG_PM diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index b734d846816..8225e2e58c6 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c @@ -379,7 +379,7 @@ __setup("monitor=", cmx2xx_set_display); static void __init cmx2xx_init_display(void) { - set_pxa_fb_info(cmx2xx_display); + pxa_set_fb_info(NULL, cmx2xx_display); } #else static inline void cmx2xx_init_display(void) {} diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 7984268508b..b2248e76ec8 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -29,6 +29,7 @@ #include <linux/i2c.h> #include <linux/i2c/pca953x.h> +#include <linux/i2c/pxa-i2c.h> #include <linux/mfd/da903x.h> #include <linux/regulator/machine.h> @@ -48,7 +49,6 @@ #include <mach/pxafb.h> #include <mach/mmc.h> #include <mach/ohci.h> -#include <plat/i2c.h> #include <plat/pxa3xx_nand.h> #include <mach/audio.h> #include <mach/pxa3xx-u2d.h> @@ -296,7 +296,7 @@ static struct pxafb_mach_info cm_x300_lcd = { static void __init cm_x300_init_lcd(void) { - set_pxa_fb_info(&cm_x300_lcd); + pxa_set_fb_info(NULL, &cm_x300_lcd); } #else static inline void cm_x300_init_lcd(void) {} @@ -765,7 +765,7 @@ static void __init cm_x300_init_da9030(void) { pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info); i2c_register_board_info(1, &cm_x300_pmic_info, 1); - set_irq_wake(IRQ_WAKEUP0, 1); + irq_set_irq_wake(IRQ_WAKEUP0, 1); } static void __init cm_x300_init_wi2wi(void) diff --git a/arch/arm/mach-pxa/colibri-evalboard.c b/arch/arm/mach-pxa/colibri-evalboard.c index 28f667e52ef..81c3c433e2d 100644 --- a/arch/arm/mach-pxa/colibri-evalboard.c +++ b/arch/arm/mach-pxa/colibri-evalboard.c @@ -20,6 +20,7 @@ #include <mach/hardware.h> #include <asm/mach/arch.h> #include <linux/i2c.h> +#include <linux/i2c/pxa-i2c.h> #include <mach/pxa27x.h> #include <mach/colibri.h> @@ -27,8 +28,6 @@ #include <mach/ohci.h> #include <mach/pxa27x-udc.h> -#include <plat/i2c.h> - #include "generic.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c index 07b62a096f1..44c1b77ece6 100644 --- a/arch/arm/mach-pxa/colibri-pxa270-income.c +++ b/arch/arm/mach-pxa/colibri-pxa270-income.c @@ -21,6 +21,7 @@ #include <linux/kernel.h> #include <linux/platform_device.h> #include <linux/pwm_backlight.h> +#include <linux/i2c/pxa-i2c.h> #include <linux/sysdev.h> #include <asm/irq.h> @@ -33,8 +34,6 @@ #include <mach/pxa27x-udc.h> #include <mach/pxafb.h> -#include <plat/i2c.h> - #include "devices.h" #include "generic.h" @@ -176,7 +175,7 @@ static struct pxafb_mach_info income_lcd_screen = { static void __init income_lcd_init(void) { - set_pxa_fb_info(&income_lcd_screen); + pxa_set_fb_info(NULL, &income_lcd_screen); } #else static inline void income_lcd_init(void) {} diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c index 96b2d9fbfef..3f9be419959 100644 --- a/arch/arm/mach-pxa/colibri-pxa3xx.c +++ b/arch/arm/mach-pxa/colibri-pxa3xx.c @@ -105,7 +105,7 @@ void __init colibri_pxa3xx_init_lcd(int bl_pin) lcd_bl_pin = bl_pin; gpio_request(bl_pin, "lcd backlight"); gpio_direction_output(bl_pin, 0); - set_pxa_fb_info(&sharp_lq43_info); + pxa_set_fb_info(NULL, &sharp_lq43_info); } #endif diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index a5452a3a276..3a5507e3191 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -24,6 +24,7 @@ #include <linux/gpio.h> #include <linux/backlight.h> #include <linux/i2c.h> +#include <linux/i2c/pxa-i2c.h> #include <linux/io.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> @@ -45,7 +46,6 @@ #include <asm/mach/irq.h> #include <mach/pxa25x.h> -#include <plat/i2c.h> #include <mach/irda.h> #include <mach/mmc.h> #include <mach/udc.h> @@ -462,7 +462,6 @@ static struct pxaficp_platform_data corgi_ficp_platform_data = { * USB Device Controller */ static struct pxa2xx_udc_mach_info udc_info __initdata = { - .gpio_vbus = -1, /* no connect GPIO; corgi can't tell connection status */ .gpio_pullup = CORGI_GPIO_USB_PULLUP, }; diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c index a305424a967..0481c29a70e 100644 --- a/arch/arm/mach-pxa/csb726.c +++ b/arch/arm/mach-pxa/csb726.c @@ -17,12 +17,12 @@ #include <linux/mtd/partitions.h> #include <linux/sm501.h> #include <linux/smsc911x.h> +#include <linux/i2c/pxa-i2c.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <mach/csb726.h> #include <mach/mfp-pxa27x.h> -#include <plat/i2c.h> #include <mach/mmc.h> #include <mach/ohci.h> #include <mach/pxa2xx-regs.h> diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 4c766e3b4af..2e0425404de 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -4,6 +4,7 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> #include <linux/spi/pxa2xx_spi.h> +#include <linux/i2c/pxa-i2c.h> #include <asm/pmu.h> #include <mach/udc.h> @@ -16,7 +17,6 @@ #include <mach/camera.h> #include <mach/audio.h> #include <mach/hardware.h> -#include <plat/i2c.h> #include <plat/pxa3xx_nand.h> #include "devices.h" @@ -90,7 +90,6 @@ void __init pxa_set_mci_info(struct pxamci_platform_data *info) static struct pxa2xx_udc_mach_info pxa_udc_info = { .gpio_pullup = -1, - .gpio_vbus = -1, }; void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info) @@ -188,16 +187,12 @@ struct platform_device pxa_device_fb = { .resource = pxafb_resources, }; -void __init set_pxa_fb_info(struct pxafb_mach_info *info) +void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info) { + pxa_device_fb.dev.parent = parent; pxa_register_device(&pxa_device_fb, info); } -void __init set_pxa_fb_parent(struct device *parent_dev) -{ - pxa_device_fb.dev.parent = parent_dev; -} - static struct resource pxa_resource_ffuart[] = { { .start = 0x40100000, diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index a78bb309773..f8a6e9d79a3 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -31,6 +31,7 @@ #include <linux/apm-emulation.h> #include <linux/i2c.h> #include <linux/i2c/pca953x.h> +#include <linux/i2c/pxa-i2c.h> #include <linux/regulator/userspace-consumer.h> #include <media/soc_camera.h> @@ -45,7 +46,6 @@ #include <mach/ohci.h> #include <mach/mmc.h> #include <plat/pxa27x_keypad.h> -#include <plat/i2c.h> #include <mach/camera.h> #include "generic.h" @@ -689,7 +689,7 @@ static struct pxafb_mach_info em_x270_lcd = { static void __init em_x270_init_lcd(void) { - set_pxa_fb_info(&em_x270_lcd); + pxa_set_fb_info(NULL, &em_x270_lcd); } #else static inline void em_x270_init_lcd(void) {} diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index edca0a04329..2e3970fdde0 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c @@ -20,6 +20,7 @@ #include <linux/mfd/t7l66xb.h> #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> +#include <linux/usb/gpio_vbus.h> #include <video/w100fb.h> @@ -51,12 +52,20 @@ void __init eseries_fixup(struct machine_desc *desc, mi->bank[0].size = (64*1024*1024); } -struct pxa2xx_udc_mach_info e7xx_udc_mach_info = { +struct gpio_vbus_mach_info e7xx_udc_info = { .gpio_vbus = GPIO_E7XX_USB_DISC, .gpio_pullup = GPIO_E7XX_USB_PULLUP, .gpio_pullup_inverted = 1 }; +static struct platform_device e7xx_gpio_vbus = { + .name = "gpio-vbus", + .id = -1, + .dev = { + .platform_data = &e7xx_udc_info, + }, +}; + struct pxaficp_platform_data e7xx_ficp_platform_data = { .gpio_pwdown = GPIO_E7XX_IR_OFF, .transceiver_cap = IR_SIRMODE | IR_OFF, @@ -165,6 +174,7 @@ static struct platform_device e330_tc6387xb_device = { static struct platform_device *e330_devices[] __initdata = { &e330_tc6387xb_device, + &e7xx_gpio_vbus, }; static void __init e330_init(void) @@ -175,7 +185,6 @@ static void __init e330_init(void) eseries_register_clks(); eseries_get_tmio_gpios(); platform_add_devices(ARRAY_AND_SIZE(e330_devices)); - pxa_set_udc_info(&e7xx_udc_mach_info); } MACHINE_START(E330, "Toshiba e330") @@ -214,6 +223,7 @@ static struct platform_device e350_t7l66xb_device = { static struct platform_device *e350_devices[] __initdata = { &e350_t7l66xb_device, + &e7xx_gpio_vbus, }; static void __init e350_init(void) @@ -224,7 +234,6 @@ static void __init e350_init(void) eseries_register_clks(); eseries_get_tmio_gpios(); platform_add_devices(ARRAY_AND_SIZE(e350_devices)); - pxa_set_udc_info(&e7xx_udc_mach_info); } MACHINE_START(E350, "Toshiba e350") @@ -333,6 +342,7 @@ static struct platform_device e400_t7l66xb_device = { static struct platform_device *e400_devices[] __initdata = { &e400_t7l66xb_device, + &e7xx_gpio_vbus, }; static void __init e400_init(void) @@ -344,9 +354,8 @@ static void __init e400_init(void) /* Fixme - e400 may have a switched clock */ eseries_register_clks(); eseries_get_tmio_gpios(); - set_pxa_fb_info(&e400_pxafb_mach_info); + pxa_set_fb_info(NULL, &e400_pxafb_mach_info); platform_add_devices(ARRAY_AND_SIZE(e400_devices)); - pxa_set_udc_info(&e7xx_udc_mach_info); } MACHINE_START(E400, "Toshiba e400") @@ -519,6 +528,7 @@ static struct platform_device e740_t7l66xb_device = { static struct platform_device *e740_devices[] __initdata = { &e740_fb_device, &e740_t7l66xb_device, + &e7xx_gpio_vbus, }; static void __init e740_init(void) @@ -532,7 +542,6 @@ static void __init e740_init(void) "UDCCLK", &pxa25x_device_udc.dev), eseries_get_tmio_gpios(); platform_add_devices(ARRAY_AND_SIZE(e740_devices)); - pxa_set_udc_info(&e7xx_udc_mach_info); pxa_set_ac97_info(NULL); pxa_set_ficp_info(&e7xx_ficp_platform_data); } @@ -711,6 +720,7 @@ static struct platform_device e750_tc6393xb_device = { static struct platform_device *e750_devices[] __initdata = { &e750_fb_device, &e750_tc6393xb_device, + &e7xx_gpio_vbus, }; static void __init e750_init(void) @@ -723,7 +733,6 @@ static void __init e750_init(void) "GPIO11_CLK", NULL), eseries_get_tmio_gpios(); platform_add_devices(ARRAY_AND_SIZE(e750_devices)); - pxa_set_udc_info(&e7xx_udc_mach_info); pxa_set_ac97_info(NULL); pxa_set_ficp_info(&e7xx_ficp_platform_data); } @@ -873,12 +882,21 @@ static struct platform_device e800_fb_device = { /* --------------------------- UDC definitions --------------------------- */ -static struct pxa2xx_udc_mach_info e800_udc_mach_info = { +static struct gpio_vbus_mach_info e800_udc_info = { .gpio_vbus = GPIO_E800_USB_DISC, .gpio_pullup = GPIO_E800_USB_PULLUP, .gpio_pullup_inverted = 1 }; +static struct platform_device e800_gpio_vbus = { + .name = "gpio-vbus", + .id = -1, + .dev = { + .platform_data = &e800_udc_info, + }, +}; + + /* ----------------- e800 tc6393xb parameters ------------------ */ static struct tc6393xb_platform_data e800_tc6393xb_info = { @@ -907,6 +925,7 @@ static struct platform_device e800_tc6393xb_device = { static struct platform_device *e800_devices[] __initdata = { &e800_fb_device, &e800_tc6393xb_device, + &e800_gpio_vbus, }; static void __init e800_init(void) @@ -919,7 +938,6 @@ static void __init e800_init(void) "GPIO11_CLK", NULL), eseries_get_tmio_gpios(); platform_add_devices(ARRAY_AND_SIZE(e800_devices)); - pxa_set_udc_info(&e800_udc_mach_info); pxa_set_ac97_info(NULL); } diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index 87cec0abe5b..d88aed8fbe1 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c @@ -20,6 +20,7 @@ #include <linux/gpio.h> #include <linux/gpio_keys.h> #include <linux/leds-lp3944.h> +#include <linux/i2c/pxa-i2c.h> #include <media/soc_camera.h> @@ -30,7 +31,6 @@ #include <mach/pxa27x.h> #include <mach/pxafb.h> #include <mach/ohci.h> -#include <plat/i2c.h> #include <mach/hardware.h> #include <plat/pxa27x_keypad.h> #include <mach/camera.h> @@ -783,7 +783,7 @@ static void __init a780_init(void) pxa_set_i2c_info(NULL); - set_pxa_fb_info(&ezx_fb_info_1); + pxa_set_fb_info(NULL, &ezx_fb_info_1); pxa_set_keypad_info(&a780_keypad_platform_data); @@ -853,7 +853,7 @@ static void __init e680_init(void) pxa_set_i2c_info(NULL); i2c_register_board_info(0, ARRAY_AND_SIZE(e680_i2c_board_info)); - set_pxa_fb_info(&ezx_fb_info_1); + pxa_set_fb_info(NULL, &ezx_fb_info_1); pxa_set_keypad_info(&e680_keypad_platform_data); @@ -918,7 +918,7 @@ static void __init a1200_init(void) pxa_set_i2c_info(NULL); i2c_register_board_info(0, ARRAY_AND_SIZE(a1200_i2c_board_info)); - set_pxa_fb_info(&ezx_fb_info_2); + pxa_set_fb_info(NULL, &ezx_fb_info_2); pxa_set_keypad_info(&a1200_keypad_platform_data); @@ -1103,7 +1103,7 @@ static void __init a910_init(void) pxa_set_i2c_info(NULL); i2c_register_board_info(0, ARRAY_AND_SIZE(a910_i2c_board_info)); - set_pxa_fb_info(&ezx_fb_info_2); + pxa_set_fb_info(NULL, &ezx_fb_info_2); pxa_set_keypad_info(&a910_keypad_platform_data); @@ -1173,7 +1173,7 @@ static void __init e6_init(void) pxa_set_i2c_info(NULL); i2c_register_board_info(0, ARRAY_AND_SIZE(e6_i2c_board_info)); - set_pxa_fb_info(&ezx_fb_info_2); + pxa_set_fb_info(NULL, &ezx_fb_info_2); pxa_set_keypad_info(&e6_keypad_platform_data); @@ -1212,7 +1212,7 @@ static void __init e2_init(void) pxa_set_i2c_info(NULL); i2c_register_board_info(0, ARRAY_AND_SIZE(e2_i2c_board_info)); - set_pxa_fb_info(&ezx_fb_info_2); + pxa_set_fb_info(NULL, &ezx_fb_info_2); pxa_set_keypad_info(&e2_keypad_platform_data); diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c index 6fd319ea528..d65e4bde9b9 100644 --- a/arch/arm/mach-pxa/gumstix.c +++ b/arch/arm/mach-pxa/gumstix.c @@ -26,6 +26,7 @@ #include <linux/gpio.h> #include <linux/err.h> #include <linux/clk.h> +#include <linux/usb/gpio_vbus.h> #include <asm/setup.h> #include <asm/memory.h> @@ -106,14 +107,22 @@ static void __init gumstix_mmc_init(void) #endif #ifdef CONFIG_USB_GADGET_PXA25X -static struct pxa2xx_udc_mach_info gumstix_udc_info __initdata = { +static struct gpio_vbus_mach_info gumstix_udc_info = { .gpio_vbus = GPIO_GUMSTIX_USB_GPIOn, .gpio_pullup = GPIO_GUMSTIX_USB_GPIOx, }; +static struct platform_device gumstix_gpio_vbus = { + .name = "gpio-vbus", + .id = -1, + .dev = { + .platform_data = &gumstix_udc_info, + }, +}; + static void __init gumstix_udc_init(void) { - pxa_set_udc_info(&gumstix_udc_info); + platform_device_register(&gumstix_gpio_vbus); } #else static void gumstix_udc_init(void) diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index a908e0a5f39..9cdcca59792 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -35,6 +35,7 @@ #include <linux/spi/spi.h> #include <linux/spi/pxa2xx_spi.h> #include <linux/usb/gpio_vbus.h> +#include <linux/i2c/pxa-i2c.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -42,7 +43,6 @@ #include <mach/pxa27x.h> #include <mach/hx4700.h> -#include <plat/i2c.h> #include <mach/irda.h> #include <video/platform_lcd.h> @@ -711,7 +711,7 @@ static struct regulator_consumer_supply bq24022_consumers[] = { static struct regulator_init_data bq24022_init_data = { .constraints = { .max_uA = 500000, - .valid_ops_mask = REGULATOR_CHANGE_CURRENT, + .valid_ops_mask = REGULATOR_CHANGE_CURRENT|REGULATOR_CHANGE_STATUS, }, .num_consumer_supplies = ARRAY_SIZE(bq24022_consumers), .consumer_supplies = bq24022_consumers, diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index dd40e4a9291..f7fb64f11a7 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c @@ -167,7 +167,7 @@ static void __init idp_init(void) platform_device_register(&smc91x_device); //platform_device_register(&mst_audio_device); - set_pxa_fb_info(&sharp_lm8v31); + pxa_set_fb_info(NULL, &sharp_lm8v31); pxa_set_mci_info(&idp_mci_platform_data); } diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h index b024a8b3743..c4639502efc 100644 --- a/arch/arm/mach-pxa/include/mach/gpio.h +++ b/arch/arm/mach-pxa/include/mach/gpio.h @@ -99,11 +99,24 @@ #define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2)) -#define NR_BUILTIN_GPIO 128 +#define NR_BUILTIN_GPIO PXA_GPIO_IRQ_NUM #define gpio_to_bank(gpio) ((gpio) >> 5) #define gpio_to_irq(gpio) IRQ_GPIO(gpio) -#define irq_to_gpio(irq) IRQ_TO_GPIO(irq) + +static inline int irq_to_gpio(unsigned int irq) +{ + int gpio; + + if (irq == IRQ_GPIO0 || irq == IRQ_GPIO1) + return irq - IRQ_GPIO0; + + gpio = irq - PXA_GPIO_IRQ_BASE; + if (gpio >= 2 && gpio < NR_BUILTIN_GPIO) + return gpio; + + return -1; +} #ifdef CONFIG_CPU_PXA26x /* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h index a4285fc0087..038402404e3 100644 --- a/arch/arm/mach-pxa/include/mach/irqs.h +++ b/arch/arm/mach-pxa/include/mach/irqs.h @@ -93,9 +93,6 @@ #define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x)) #define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x)) -#define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE) -#define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i)) - /* * The following interrupts are for board specific purposes. Since * the kernel can only run on one machine at a time, we can re-use diff --git a/arch/arm/mach-pxa/include/mach/palmz72.h b/arch/arm/mach-pxa/include/mach/palmz72.h index 2bbcf70dd93..0d4700a7961 100644 --- a/arch/arm/mach-pxa/include/mach/palmz72.h +++ b/arch/arm/mach-pxa/include/mach/palmz72.h @@ -44,6 +44,11 @@ #define GPIO_NR_PALMZ72_BT_POWER 17 #define GPIO_NR_PALMZ72_BT_RESET 83 +/* Camera */ +#define GPIO_NR_PALMZ72_CAM_PWDN 56 +#define GPIO_NR_PALMZ72_CAM_RESET 57 +#define GPIO_NR_PALMZ72_CAM_POWER 91 + /** Initial values **/ /* Battery */ diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h index e4fb4668c26..207ecb49a61 100644 --- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h @@ -38,7 +38,7 @@ #define PCMD(x) __REG(0x40F50110 + ((x) << 2)) /* - * Slave Power Managment Unit + * Slave Power Management Unit */ #define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */ #define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */ diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h index 160ec83f51a..01a45ac4811 100644 --- a/arch/arm/mach-pxa/include/mach/pxafb.h +++ b/arch/arm/mach-pxa/include/mach/pxafb.h @@ -154,8 +154,8 @@ struct pxafb_mach_info { void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *); void (*smart_update)(struct fb_info *); }; -void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info); -void set_pxa_fb_parent(struct device *parent_dev); + +void pxa_set_fb_info(struct device *, struct pxafb_mach_info *); unsigned long pxafb_get_hsync_time(struct device *dev); extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int); diff --git a/arch/arm/mach-pxa/include/mach/z2.h b/arch/arm/mach-pxa/include/mach/z2.h index 8835c16bc82..7b0f71ef316 100644 --- a/arch/arm/mach-pxa/include/mach/z2.h +++ b/arch/arm/mach-pxa/include/mach/z2.h @@ -25,8 +25,7 @@ #define GPIO98_ZIPITZ2_LID_BUTTON 98 /* Libertas GSPI8686 WiFi */ -#define GPIO14_ZIPITZ2_WIFI_RESET 14 -#define GPIO15_ZIPITZ2_WIFI_POWER 15 +#define GPIO14_ZIPITZ2_WIFI_POWER 14 #define GPIO24_ZIPITZ2_WIFI_CS 24 #define GPIO36_ZIPITZ2_WIFI_IRQ 36 diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h index faa408ab7ad..0641f31a56b 100644 --- a/arch/arm/mach-pxa/include/mach/zeus.h +++ b/arch/arm/mach-pxa/include/mach/zeus.h @@ -64,7 +64,7 @@ /* * CPLD registers: - * Only 4 registers, but spreaded over a 32MB address space. + * Only 4 registers, but spread over a 32MB address space. * Be gentle, and remap that over 32kB... */ diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 2693e3c3776..6251e3f5c62 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -137,9 +137,9 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn) GEDR0 = 0x3; for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { - set_irq_chip(irq, &pxa_low_gpio_chip); - set_irq_chip_data(irq, irq_base(0)); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &pxa_low_gpio_chip, + handle_edge_irq); + irq_set_chip_data(irq, irq_base(0)); set_irq_flags(irq, IRQF_VALID); } @@ -165,9 +165,9 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn) __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); irq = PXA_IRQ(i); - set_irq_chip(irq, &pxa_internal_irq_chip); - set_irq_chip_data(irq, base); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, + handle_level_irq); + irq_set_chip_data(irq, base); set_irq_flags(irq, IRQF_VALID); } } diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index ccb7bfad17c..e5e326d2cdc 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -28,6 +28,7 @@ #include <linux/leds.h> #include <linux/mfd/da903x.h> #include <linux/i2c/max732x.h> +#include <linux/i2c/pxa-i2c.h> #include <asm/types.h> #include <asm/setup.h> @@ -45,7 +46,6 @@ #include <mach/mmc.h> #include <plat/pxa27x_keypad.h> #include <mach/littleton.h> -#include <plat/i2c.h> #include <plat/pxa3xx_nand.h> #include "generic.h" @@ -185,7 +185,7 @@ static struct pxafb_mach_info littleton_lcd_info = { static void littleton_init_lcd(void) { - set_pxa_fb_info(&littleton_lcd_info); + pxa_set_fb_info(NULL, &littleton_lcd_info); } #else static inline void littleton_init_lcd(void) {}; diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index c9a3e775c2d..f5de541725b 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -149,12 +149,12 @@ static void __init lpd270_init_irq(void) /* setup extra LogicPD PXA270 irqs */ for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) { - set_irq_chip(irq, &lpd270_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &lpd270_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } - set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); - set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); + irq_set_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); + irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); } @@ -480,7 +480,7 @@ static void __init lpd270_init(void) pxa_set_ac97_info(NULL); if (lpd270_lcd_to_use != NULL) - set_pxa_fb_info(lpd270_lcd_to_use); + pxa_set_fb_info(NULL, lpd270_lcd_to_use); pxa_set_ohci_info(&lpd270_ohci_platform_data); } diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index dca20de306b..3ede978c83d 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -165,13 +165,13 @@ static void __init lubbock_init_irq(void) /* setup extra lubbock irqs */ for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) { - set_irq_chip(irq, &lubbock_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &lubbock_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } - set_irq_chained_handler(IRQ_GPIO(0), lubbock_irq_handler); - set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); + irq_set_chained_handler(IRQ_GPIO(0), lubbock_irq_handler); + irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); } #ifdef CONFIG_PM @@ -521,7 +521,7 @@ static void __init lubbock_init(void) clk_add_alias("SA1111_CLK", NULL, "GPIO11_CLK", NULL); pxa_set_udc_info(&udc_info); - set_pxa_fb_info(&sharp_lm8v31); + pxa_set_fb_info(NULL, &sharp_lm8v31); pxa_set_mci_info(&lubbock_mci_platform_data); pxa_set_ficp_info(&lubbock_ficp_platform_data); pxa_set_ac97_info(NULL); diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 41198f0dc3a..9984ef70bd7 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -28,6 +28,7 @@ #include <linux/regulator/bq24022.h> #include <linux/regulator/machine.h> #include <linux/usb/gpio_vbus.h> +#include <linux/i2c/pxa-i2c.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -36,7 +37,6 @@ #include <mach/pxa27x.h> #include <mach/magician.h> #include <mach/pxafb.h> -#include <plat/i2c.h> #include <mach/mmc.h> #include <mach/irda.h> #include <mach/ohci.h> @@ -599,7 +599,7 @@ static struct regulator_consumer_supply bq24022_consumers[] = { static struct regulator_init_data bq24022_init_data = { .constraints = { .max_uA = 500000, - .valid_ops_mask = REGULATOR_CHANGE_CURRENT, + .valid_ops_mask = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS, }, .num_consumer_supplies = ARRAY_SIZE(bq24022_consumers), .consumer_supplies = bq24022_consumers, @@ -757,7 +757,7 @@ static void __init magician_init(void) gpio_direction_output(GPIO104_MAGICIAN_LCD_POWER_1, 0); gpio_direction_output(GPIO105_MAGICIAN_LCD_POWER_2, 0); gpio_direction_output(GPIO106_MAGICIAN_LCD_POWER_3, 0); - set_pxa_fb_info(lcd_select ? &samsung_info : &toppoly_info); + pxa_set_fb_info(NULL, lcd_select ? &samsung_info : &toppoly_info); } else pr_err("LCD detection: CPLD mapping failed\n"); } diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index d4b6f2375f2..95163baca29 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -27,6 +27,7 @@ #include <linux/gpio_keys.h> #include <linux/pwm_backlight.h> #include <linux/smc91x.h> +#include <linux/i2c/pxa-i2c.h> #include <asm/types.h> #include <asm/setup.h> @@ -46,7 +47,6 @@ #include <mach/mainstone.h> #include <mach/audio.h> #include <mach/pxafb.h> -#include <plat/i2c.h> #include <mach/mmc.h> #include <mach/irda.h> #include <mach/ohci.h> @@ -166,8 +166,8 @@ static void __init mainstone_init_irq(void) /* setup extra Mainstone irqs */ for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { - set_irq_chip(irq, &mainstone_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &mainstone_irq_chip, + handle_level_irq); if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14)) set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); else @@ -179,8 +179,8 @@ static void __init mainstone_init_irq(void) MST_INTMSKENA = 0; MST_INTSETCLR = 0; - set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler); - set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); + irq_set_chained_handler(IRQ_GPIO(0), mainstone_irq_handler); + irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); } #ifdef CONFIG_PM @@ -592,7 +592,7 @@ static void __init mainstone_init(void) else mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode; - set_pxa_fb_info(&mainstone_pxafb_info); + pxa_set_fb_info(NULL, &mainstone_pxafb_info); mainstone_backlight_register(); pxa_set_mci_info(&mainstone_mci_platform_data); diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index faafea3542f..23925db8ff7 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -39,6 +39,7 @@ #include <linux/usb/gpio_vbus.h> #include <linux/regulator/max1586.h> #include <linux/slab.h> +#include <linux/i2c/pxa-i2c.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -50,7 +51,6 @@ #include <mach/mmc.h> #include <mach/udc.h> #include <mach/pxa27x-udc.h> -#include <plat/i2c.h> #include <mach/camera.h> #include <mach/audio.h> #include <media/soc_camera.h> @@ -458,7 +458,7 @@ static struct platform_device strataflash = { /* * Suspend/Resume bootstrap management * - * MIO A701 reboot sequence is highly ROM dependant. From the one dissassembled, + * MIO A701 reboot sequence is highly ROM dependent. From the one dissassembled, * this sequence is as follows : * - disables interrupts * - initialize SDRAM (self refresh RAM into active RAM) @@ -795,7 +795,7 @@ static void __init mioa701_machine_init(void) pxa_set_stuart_info(NULL); mio_gpio_request(ARRAY_AND_SIZE(global_gpios)); bootstrap_init(); - set_pxa_fb_info(&mioa701_pxafb_info); + pxa_set_fb_info(NULL, &mioa701_pxafb_info); pxa_set_mci_info(&mioa701_mci_info); pxa_set_keypad_info(&mioa701_keypad_info); pxa_set_udc_info(&mioa701_udc_info); diff --git a/arch/arm/mach-pxa/mxm8x10.c b/arch/arm/mach-pxa/mxm8x10.c index cdf7f41e2bb..b5a8fd3fce0 100644 --- a/arch/arm/mach-pxa/mxm8x10.c +++ b/arch/arm/mach-pxa/mxm8x10.c @@ -22,8 +22,8 @@ #include <linux/serial_8250.h> #include <linux/dm9000.h> #include <linux/gpio.h> +#include <linux/i2c/pxa-i2c.h> -#include <plat/i2c.h> #include <plat/pxa3xx_nand.h> #include <mach/pxafb.h> diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c index 35572c427fa..325c245c0a0 100644 --- a/arch/arm/mach-pxa/palm27x.c +++ b/arch/arm/mach-pxa/palm27x.c @@ -1,8 +1,7 @@ /* * Common code for Palm LD, T5, TX, Z72 * - * Copyright (C) 2010 - * Marek Vasut <marek.vasut@gmail.com> + * Copyright (C) 2010-2011 Marek Vasut <marek.vasut@gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -22,6 +21,7 @@ #include <linux/power_supply.h> #include <linux/usb/gpio_vbus.h> #include <linux/regulator/max1586.h> +#include <linux/i2c/pxa-i2c.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -36,8 +36,6 @@ #include <mach/palmasoc.h> #include <mach/palm27x.h> -#include <plat/i2c.h> - #include "generic.h" #include "devices.h" @@ -159,7 +157,7 @@ void __init palm27x_lcd_init(int power, struct pxafb_mode_info *mode) palm27x_lcd_screen.pxafb_lcd_power = palm27x_lcd_ctl; } - set_pxa_fb_info(&palm27x_lcd_screen); + pxa_set_fb_info(NULL, &palm27x_lcd_screen); } #endif diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c index a09a2374697..fb06bd04727 100644 --- a/arch/arm/mach-pxa/palmtc.c +++ b/arch/arm/mach-pxa/palmtc.c @@ -507,7 +507,7 @@ static struct pxafb_mach_info palmtc_lcd_screen = { static void __init palmtc_lcd_init(void) { - set_pxa_fb_info(&palmtc_lcd_screen); + pxa_set_fb_info(NULL, &palmtc_lcd_screen); } #else static inline void palmtc_lcd_init(void) {} diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c index 3f25014a136..726f5b98dcd 100644 --- a/arch/arm/mach-pxa/palmte2.c +++ b/arch/arm/mach-pxa/palmte2.c @@ -136,30 +136,14 @@ static struct platform_device palmte2_pxa_keys = { /****************************************************************************** * Backlight ******************************************************************************/ +static struct gpio palmte_bl_gpios[] = { + { GPIO_NR_PALMTE2_BL_POWER, GPIOF_INIT_LOW, "Backlight power" }, + { GPIO_NR_PALMTE2_LCD_POWER, GPIOF_INIT_LOW, "LCD power" }, +}; + static int palmte2_backlight_init(struct device *dev) { - int ret; - - ret = gpio_request(GPIO_NR_PALMTE2_BL_POWER, "BL POWER"); - if (ret) - goto err; - ret = gpio_direction_output(GPIO_NR_PALMTE2_BL_POWER, 0); - if (ret) - goto err2; - ret = gpio_request(GPIO_NR_PALMTE2_LCD_POWER, "LCD POWER"); - if (ret) - goto err2; - ret = gpio_direction_output(GPIO_NR_PALMTE2_LCD_POWER, 0); - if (ret) - goto err3; - - return 0; -err3: - gpio_free(GPIO_NR_PALMTE2_LCD_POWER); -err2: - gpio_free(GPIO_NR_PALMTE2_BL_POWER); -err: - return ret; + return gpio_request_array(ARRAY_AND_SIZE(palmte_bl_gpios)); } static int palmte2_backlight_notify(struct device *dev, int brightness) @@ -171,8 +155,7 @@ static int palmte2_backlight_notify(struct device *dev, int brightness) static void palmte2_backlight_exit(struct device *dev) { - gpio_free(GPIO_NR_PALMTE2_BL_POWER); - gpio_free(GPIO_NR_PALMTE2_LCD_POWER); + gpio_free_array(ARRAY_AND_SIZE(palmte_bl_gpios)); } static struct platform_pwm_backlight_data palmte2_backlight_data = { @@ -363,7 +346,7 @@ static void __init palmte2_init(void) pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); - set_pxa_fb_info(&palmte2_lcd_screen); + pxa_set_fb_info(NULL, &palmte2_lcd_screen); pxa_set_mci_info(&palmte2_mci_platform_data); palmte2_udc_init(); pxa_set_ac97_info(&palmte2_ac97_pdata); diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index 3010193b081..3b8a4f37dbb 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c @@ -30,6 +30,7 @@ #include <linux/wm97xx.h> #include <linux/power_supply.h> #include <linux/usb/gpio_vbus.h> +#include <linux/i2c-gpio.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -47,6 +48,9 @@ #include <mach/palm27x.h> #include <mach/pm.h> +#include <mach/camera.h> + +#include <media/soc_camera.h> #include "generic.h" #include "devices.h" @@ -103,6 +107,28 @@ static unsigned long palmz72_pin_config[] __initdata = { GPIO22_GPIO, /* LCD border color */ GPIO96_GPIO, /* lcd power */ + /* PXA Camera */ + GPIO81_CIF_DD_0, + GPIO48_CIF_DD_5, + GPIO50_CIF_DD_3, + GPIO51_CIF_DD_2, + GPIO52_CIF_DD_4, + GPIO53_CIF_MCLK, + GPIO54_CIF_PCLK, + GPIO55_CIF_DD_1, + GPIO84_CIF_FV, + GPIO85_CIF_LV, + GPIO93_CIF_DD_6, + GPIO108_CIF_DD_7, + + GPIO56_GPIO, /* OV9640 Powerdown */ + GPIO57_GPIO, /* OV9640 Reset */ + GPIO91_GPIO, /* OV9640 Power */ + + /* I2C */ + GPIO117_GPIO, /* I2C_SCL */ + GPIO118_GPIO, /* I2C_SDA */ + /* Misc. */ GPIO0_GPIO | WAKEUP_ON_LEVEL_HIGH, /* power detect */ GPIO88_GPIO, /* green led */ @@ -254,6 +280,106 @@ device_initcall(palmz72_pm_init); #endif /****************************************************************************** + * SoC Camera + ******************************************************************************/ +#if defined(CONFIG_SOC_CAMERA_OV9640) || \ + defined(CONFIG_SOC_CAMERA_OV9640_MODULE) +static struct pxacamera_platform_data palmz72_pxacamera_platform_data = { + .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | + PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN, + .mclk_10khz = 2600, +}; + +/* Board I2C devices. */ +static struct i2c_board_info palmz72_i2c_device[] = { + { + I2C_BOARD_INFO("ov9640", 0x30), + } +}; + +static int palmz72_camera_power(struct device *dev, int power) +{ + gpio_set_value(GPIO_NR_PALMZ72_CAM_PWDN, !power); + mdelay(50); + return 0; +} + +static int palmz72_camera_reset(struct device *dev) +{ + gpio_set_value(GPIO_NR_PALMZ72_CAM_RESET, 1); + mdelay(50); + gpio_set_value(GPIO_NR_PALMZ72_CAM_RESET, 0); + mdelay(50); + return 0; +} + +static struct soc_camera_link palmz72_iclink = { + .bus_id = 0, /* Match id in pxa27x_device_camera in device.c */ + .board_info = &palmz72_i2c_device[0], + .i2c_adapter_id = 0, + .module_name = "ov96xx", + .power = &palmz72_camera_power, + .reset = &palmz72_camera_reset, + .flags = SOCAM_DATAWIDTH_8, +}; + +static struct i2c_gpio_platform_data palmz72_i2c_bus_data = { + .sda_pin = 118, + .scl_pin = 117, + .udelay = 10, + .timeout = 100, +}; + +static struct platform_device palmz72_i2c_bus_device = { + .name = "i2c-gpio", + .id = 0, /* we use this as a replacement for i2c-pxa */ + .dev = { + .platform_data = &palmz72_i2c_bus_data, + } +}; + +static struct platform_device palmz72_camera = { + .name = "soc-camera-pdrv", + .id = -1, + .dev = { + .platform_data = &palmz72_iclink, + }, +}; + +/* Here we request the camera GPIOs and configure them. We power up the camera + * module, deassert the reset pin, but put it into powerdown (low to no power + * consumption) mode. This allows us to later bring the module up fast. */ +static struct gpio palmz72_camera_gpios[] = { + { GPIO_NR_PALMZ72_CAM_POWER, GPIOF_INIT_HIGH,"Camera DVDD" }, + { GPIO_NR_PALMZ72_CAM_RESET, GPIOF_INIT_LOW, "Camera RESET" }, + { GPIO_NR_PALMZ72_CAM_PWDN, GPIOF_INIT_LOW, "Camera PWDN" }, +}; + +static inline void __init palmz72_cam_gpio_init(void) +{ + int ret; + + ret = gpio_request_array(ARRAY_AND_SIZE(palmz72_camera_gpios)); + if (!ret) + gpio_free_array(ARRAY_AND_SIZE(palmz72_camera_gpios)); + else + printk(KERN_ERR "Camera GPIO init failed!\n"); + + return; +} + +static void __init palmz72_camera_init(void) +{ + palmz72_cam_gpio_init(); + pxa_set_camera_info(&palmz72_pxacamera_platform_data); + platform_device_register(&palmz72_i2c_bus_device); + platform_device_register(&palmz72_camera); +} +#else +static inline void palmz72_camera_init(void) {} +#endif + +/****************************************************************************** * Machine init ******************************************************************************/ static void __init palmz72_init(void) @@ -276,6 +402,7 @@ static void __init palmz72_init(void) palm27x_pmic_init(); palmz72_kpc_init(); palmz72_leds_init(); + palmz72_camera_init(); } MACHINE_START(PALMZ72, "Palm Zire72") diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index 90820faa711..6d5b7e06212 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -23,12 +23,12 @@ #include <linux/irq.h> #include <linux/platform_device.h> #include <linux/i2c.h> +#include <linux/i2c/pxa-i2c.h> #include <linux/pwm_backlight.h> #include <media/soc_camera.h> #include <asm/gpio.h> -#include <plat/i2c.h> #include <mach/camera.h> #include <asm/mach/map.h> #include <mach/pxa27x.h> @@ -281,16 +281,16 @@ static void __init pcm990_init_irq(void) /* setup extra PCM990 irqs */ for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) { - set_irq_chip(irq, &pcm990_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &pcm990_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } PCM990_INTMSKENA = 0x00; /* disable all Interrupts */ PCM990_INTSETCLR = 0xFF; - set_irq_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler); - set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE); + irq_set_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler); + irq_set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE); } static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int, @@ -515,7 +515,7 @@ void __init pcm990_baseboard_init(void) pcm990_init_irq(); #ifndef CONFIG_PCM990_DISPLAY_NONE - set_pxa_fb_info(&pcm990_fbinfo); + pxa_set_fb_info(NULL, &pcm990_fbinfo); #endif platform_device_register(&pcm990_backlight_device); diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 4f0ff1ab623..16d14fd79b4 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -23,6 +23,7 @@ #include <linux/mtd/physmap.h> #include <linux/gpio.h> #include <linux/i2c.h> +#include <linux/i2c/pxa-i2c.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> #include <linux/spi/pxa2xx_spi.h> @@ -44,7 +45,6 @@ #include <mach/irda.h> #include <mach/poodle.h> #include <mach/pxafb.h> -#include <plat/i2c.h> #include <asm/hardware/scoop.h> #include <asm/hardware/locomo.h> @@ -445,8 +445,7 @@ static void __init poodle_init(void) if (ret) pr_warning("poodle: Unable to register LoCoMo device\n"); - set_pxa_fb_parent(&poodle_locomo_device.dev); - set_pxa_fb_info(&poodle_fb_info); + pxa_set_fb_info(&poodle_locomo_device.dev, &poodle_fb_info); pxa_set_udc_info(&udc_info); pxa_set_mci_info(&poodle_mci_platform_data); pxa_set_ficp_info(&poodle_ficp_platform_data); diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 6bde5956358..a4af8c52d7e 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -285,7 +285,7 @@ static inline void pxa25x_init_pm(void) {} static int pxa25x_set_wake(struct irq_data *d, unsigned int on) { - int gpio = IRQ_TO_GPIO(d->irq); + int gpio = irq_to_gpio(d->irq); uint32_t mask = 0; if (gpio >= 0 && gpio < 85) diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 28b11be00b3..909756eaf4b 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -19,6 +19,7 @@ #include <linux/sysdev.h> #include <linux/io.h> #include <linux/irq.h> +#include <linux/i2c/pxa-i2c.h> #include <asm/mach/map.h> #include <mach/hardware.h> @@ -32,8 +33,6 @@ #include <mach/dma.h> #include <mach/smemc.h> -#include <plat/i2c.h> - #include "generic.h" #include "devices.h" #include "clock.h" @@ -346,7 +345,7 @@ static inline void pxa27x_init_pm(void) {} */ static int pxa27x_set_wake(struct irq_data *d, unsigned int on) { - int gpio = IRQ_TO_GPIO(d->irq); + int gpio = irq_to_gpio(d->irq); uint32_t mask; if (gpio >= 0 && gpio < 128) diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 1230343d9c7..8dd10739115 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -21,6 +21,7 @@ #include <linux/irq.h> #include <linux/io.h> #include <linux/sysdev.h> +#include <linux/i2c/pxa-i2c.h> #include <asm/mach/map.h> #include <mach/hardware.h> @@ -32,7 +33,6 @@ #include <mach/dma.h> #include <mach/regs-intc.h> #include <mach/smemc.h> -#include <plat/i2c.h> #include "generic.h" #include "devices.h" @@ -362,8 +362,8 @@ static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) int irq; for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { - set_irq_chip(irq, &pxa_ext_wakeup_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID); } diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c index 437980f7271..23b229bd06e 100644 --- a/arch/arm/mach-pxa/pxa95x.c +++ b/arch/arm/mach-pxa/pxa95x.c @@ -15,6 +15,7 @@ #include <linux/init.h> #include <linux/pm.h> #include <linux/platform_device.h> +#include <linux/i2c/pxa-i2c.h> #include <linux/irq.h> #include <linux/io.h> #include <linux/sysdev.h> @@ -27,7 +28,6 @@ #include <mach/pm.h> #include <mach/dma.h> #include <mach/regs-intc.h> -#include <plat/i2c.h> #include "generic.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c index 8361151be05..cd1861351f7 100644 --- a/arch/arm/mach-pxa/raumfeld.c +++ b/arch/arm/mach-pxa/raumfeld.c @@ -32,6 +32,7 @@ #include <linux/sched.h> #include <linux/pwm_backlight.h> #include <linux/i2c.h> +#include <linux/i2c/pxa-i2c.h> #include <linux/spi/spi.h> #include <linux/spi/spi_gpio.h> #include <linux/lis3lv02d.h> @@ -53,7 +54,6 @@ #include <mach/ohci.h> #include <mach/pxafb.h> #include <mach/mmc.h> -#include <plat/i2c.h> #include <plat/pxa3xx_nand.h> #include "generic.h" @@ -597,7 +597,7 @@ static void __init raumfeld_lcd_init(void) { int ret; - set_pxa_fb_info(&raumfeld_sharp_lcd_info); + pxa_set_fb_info(NULL, &raumfeld_sharp_lcd_info); /* Earlier devices had the backlight regulator controlled * via PWM, later versions use another controller for that */ diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index c1ca8cb467f..fee97a93512 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c @@ -20,6 +20,7 @@ #include <linux/delay.h> #include <linux/fb.h> #include <linux/i2c.h> +#include <linux/i2c/pxa-i2c.h> #include <linux/smc91x.h> #include <linux/mfd/da903x.h> #include <linux/mtd/mtd.h> @@ -31,7 +32,6 @@ #include <asm/mach/flash.h> #include <mach/pxa930.h> -#include <plat/i2c.h> #include <mach/pxafb.h> #include "devices.h" @@ -473,7 +473,7 @@ static struct pxafb_mach_info saar_lcd_info = { static void __init saar_init_lcd(void) { - set_pxa_fb_info(&saar_lcd_info); + pxa_set_fb_info(NULL, &saar_lcd_info); } #else static inline void saar_init_lcd(void) {} diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c index e497922f761..9322fe527c7 100644 --- a/arch/arm/mach-pxa/saarb.c +++ b/arch/arm/mach-pxa/saarb.c @@ -13,6 +13,7 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/i2c.h> +#include <linux/i2c/pxa-i2c.h> #include <linux/mfd/88pm860x.h> #include <asm/mach-types.h> @@ -24,8 +25,6 @@ #include <mach/mfp-pxa930.h> #include <mach/gpio.h> -#include <plat/i2c.h> - #include "generic.h" #define SAARB_NR_IRQS (IRQ_BOARD_START + 40) diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index b49a2c21124..01c576963e9 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -19,6 +19,7 @@ #include <linux/gpio.h> #include <linux/leds.h> #include <linux/i2c.h> +#include <linux/i2c/pxa-i2c.h> #include <linux/i2c/pca953x.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> @@ -47,8 +48,6 @@ #include <mach/sharpsl_pm.h> #include <mach/smemc.h> -#include <plat/i2c.h> - #include "generic.h" #include "devices.h" @@ -725,7 +724,7 @@ static struct pxafb_mach_info spitz_pxafb_info = { static void __init spitz_lcd_init(void) { - set_pxa_fb_info(&spitz_pxafb_info); + pxa_set_fb_info(NULL, &spitz_pxafb_info); } #else static inline void spitz_lcd_init(void) {} diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c index 9a14fdb83c8..cb5611daf5f 100644 --- a/arch/arm/mach-pxa/stargate2.c +++ b/arch/arm/mach-pxa/stargate2.c @@ -25,6 +25,7 @@ #include <linux/mtd/plat-ram.h> #include <linux/mtd/partitions.h> +#include <linux/i2c/pxa-i2c.h> #include <linux/i2c/pcf857x.h> #include <linux/i2c/at24.h> #include <linux/smc91x.h> @@ -43,7 +44,6 @@ #include <asm/mach/flash.h> #include <mach/pxa27x.h> -#include <plat/i2c.h> #include <mach/mmc.h> #include <mach/udc.h> #include <mach/pxa27x-udc.h> diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c index 9cecf8366db..53d4a472b69 100644 --- a/arch/arm/mach-pxa/tavorevb.c +++ b/arch/arm/mach-pxa/tavorevb.c @@ -466,7 +466,7 @@ static void __init tavorevb_init_lcd(void) { platform_device_register(&tavorevb_backlight_devices[0]); platform_device_register(&tavorevb_backlight_devices[1]); - set_pxa_fb_info(&tavorevb_lcd_info); + pxa_set_fb_info(NULL, &tavorevb_lcd_info); } #else static inline void tavorevb_init_lcd(void) {} diff --git a/arch/arm/mach-pxa/tavorevb3.c b/arch/arm/mach-pxa/tavorevb3.c index 70191a9450e..79f4422f12f 100644 --- a/arch/arm/mach-pxa/tavorevb3.c +++ b/arch/arm/mach-pxa/tavorevb3.c @@ -15,6 +15,7 @@ #include <linux/platform_device.h> #include <linux/interrupt.h> #include <linux/i2c.h> +#include <linux/i2c/pxa-i2c.h> #include <linux/gpio.h> #include <linux/mfd/88pm860x.h> @@ -23,8 +24,6 @@ #include <mach/pxa930.h> -#include <plat/i2c.h> - #include "devices.h" #include "generic.h" diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index e7f64d9b4f2..428da3ff33a 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c @@ -100,7 +100,6 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev) static struct clock_event_device ckevt_pxa_osmr0 = { .name = "osmr0", .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .rating = 200, .set_next_event = pxa_osmr0_set_next_event, .set_mode = pxa_osmr0_set_mode, @@ -135,8 +134,8 @@ static void __init pxa_timer_init(void) init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate); - ckevt_pxa_osmr0.mult = - div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift); + clocksource_calc_mult_shift(&cksrc_pxa_oscr0, clock_tick_rate, 4); + clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4); ckevt_pxa_osmr0.max_delta_ns = clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); ckevt_pxa_osmr0.min_delta_ns = diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index f2582ec300d..5fa145778e7 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -34,6 +34,8 @@ #include <linux/spi/spi.h> #include <linux/spi/pxa2xx_spi.h> #include <linux/input/matrix_keypad.h> +#include <linux/i2c/pxa-i2c.h> +#include <linux/usb/gpio_vbus.h> #include <asm/setup.h> #include <asm/mach-types.h> @@ -41,7 +43,6 @@ #include <mach/pxa25x.h> #include <mach/reset.h> #include <mach/irda.h> -#include <plat/i2c.h> #include <mach/mmc.h> #include <mach/udc.h> #include <mach/tosa_bt.h> @@ -240,12 +241,20 @@ static struct scoop_pcmcia_config tosa_pcmcia_config = { /* * USB Device Controller */ -static struct pxa2xx_udc_mach_info udc_info __initdata = { +static struct gpio_vbus_mach_info tosa_udc_info = { .gpio_pullup = TOSA_GPIO_USB_PULLUP, .gpio_vbus = TOSA_GPIO_USB_IN, .gpio_vbus_inverted = 1, }; +static struct platform_device tosa_gpio_vbus = { + .name = "gpio-vbus", + .id = -1, + .dev = { + .platform_data = &tosa_udc_info, + }, +}; + /* * MMC/SD Device */ @@ -891,6 +900,7 @@ static struct platform_device *devices[] __initdata = { &tosa_bt_device, &sharpsl_rom_device, &wm9712_device, + &tosa_gpio_vbus, }; static void tosa_poweroff(void) @@ -937,7 +947,6 @@ static void __init tosa_init(void) dummy = gpiochip_reserve(TOSA_TC6393XB_GPIO_BASE, 16); pxa_set_mci_info(&tosa_mci_platform_data); - pxa_set_udc_info(&udc_info); pxa_set_ficp_info(&tosa_ficp_platform_data); pxa_set_i2c_info(NULL); pxa_set_ac97_info(NULL); diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index 423261d63d0..b9cfbebdfe9 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -26,6 +26,7 @@ #include <linux/dm9000.h> #include <linux/mtd/physmap.h> #include <linux/mtd/partitions.h> +#include <linux/i2c/pxa-i2c.h> #include <asm/types.h> #include <asm/setup.h> @@ -47,7 +48,6 @@ #include <mach/irda.h> #include <mach/ohci.h> #include <mach/smemc.h> -#include <plat/i2c.h> #include "generic.h" #include "devices.h" @@ -516,9 +516,9 @@ static void __init trizeps4_init(void) pxa_set_stuart_info(NULL); if (0) /* dont know how to determine LCD */ - set_pxa_fb_info(&sharp_lcd); + pxa_set_fb_info(NULL, &sharp_lcd); else - set_pxa_fb_info(&toshiba_lcd); + pxa_set_fb_info(NULL, &toshiba_lcd); pxa_set_mci_info(&trizeps4_mci_platform_data); #ifndef STATUS_LEDS_ON_STUART_PINS diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index 49eeeab2368..b523f119e0f 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -36,6 +36,7 @@ #include <linux/gpio.h> #include <linux/jiffies.h> #include <linux/i2c-gpio.h> +#include <linux/i2c/pxa-i2c.h> #include <linux/serial_8250.h> #include <linux/smc91x.h> #include <linux/pwm_backlight.h> @@ -47,7 +48,6 @@ #include <mach/pxa25x.h> #include <mach/audio.h> #include <mach/pxafb.h> -#include <plat/i2c.h> #include <mach/regs-uart.h> #include <mach/arcom-pcmcia.h> #include <mach/viper.h> @@ -310,14 +310,14 @@ static void __init viper_init_irq(void) /* setup ISA IRQs */ for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) { isa_irq = viper_bit_to_irq(level); - set_irq_chip(isa_irq, &viper_irq_chip); - set_irq_handler(isa_irq, handle_edge_irq); + irq_set_chip_and_handler(isa_irq, &viper_irq_chip, + handle_edge_irq); set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); } - set_irq_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO), + irq_set_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO), viper_irq_handler); - set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH); + irq_set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH); } /* Flat Panel */ @@ -932,7 +932,7 @@ static void __init viper_init(void) /* Wake-up serial console */ viper_init_serial_gpio(); - set_pxa_fb_info(&fb_info); + pxa_set_fb_info(NULL, &fb_info); /* v1 hardware cannot use the datacs line */ version = viper_hw_version(); diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c index b9b579715ff..f71d377c864 100644 --- a/arch/arm/mach-pxa/vpac270.c +++ b/arch/arm/mach-pxa/vpac270.c @@ -26,6 +26,7 @@ #include <linux/ucb1400.h> #include <linux/ata_platform.h> #include <linux/regulator/max1586.h> +#include <linux/i2c/pxa-i2c.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -40,8 +41,6 @@ #include <mach/udc.h> #include <mach/pata_pxa.h> -#include <plat/i2c.h> - #include "generic.h" #include "devices.h" @@ -573,7 +572,7 @@ static void __init vpac270_lcd_init(void) } vpac270_lcd_screen.pxafb_lcd_power = vpac270_lcd_power; - set_pxa_fb_info(&vpac270_lcd_screen); + pxa_set_fb_info(NULL, &vpac270_lcd_screen); return; err2: diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c index 51c0281c6e0..f55f8f2e0db 100644 --- a/arch/arm/mach-pxa/xcep.c +++ b/arch/arm/mach-pxa/xcep.c @@ -16,6 +16,7 @@ #include <linux/platform_device.h> #include <linux/i2c.h> +#include <linux/i2c/pxa-i2c.h> #include <linux/smc91x.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> @@ -26,8 +27,6 @@ #include <asm/mach/irq.h> #include <asm/mach/map.h> -#include <plat/i2c.h> - #include <mach/hardware.h> #include <mach/pxa2xx-regs.h> #include <mach/mfp-pxa25x.h> diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c index a323e076129..fbe9e02e2f9 100644 --- a/arch/arm/mach-pxa/z2.c +++ b/arch/arm/mach-pxa/z2.c @@ -29,6 +29,7 @@ #include <linux/gpio_keys.h> #include <linux/delay.h> #include <linux/regulator/machine.h> +#include <linux/i2c/pxa-i2c.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -40,8 +41,6 @@ #include <mach/mmc.h> #include <plat/pxa27x_keypad.h> -#include <plat/i2c.h> - #include "generic.h" #include "devices.h" @@ -92,13 +91,13 @@ static unsigned long z2_pin_config[] = { GPIO47_STUART_TXD, /* Keypad */ - GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, - GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH, - GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH, - GPIO34_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH, - GPIO38_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH, - GPIO16_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH, - GPIO17_KP_MKIN_6 | WAKEUP_ON_LEVEL_HIGH, + GPIO100_KP_MKIN_0, + GPIO101_KP_MKIN_1, + GPIO102_KP_MKIN_2, + GPIO34_KP_MKIN_3, + GPIO38_KP_MKIN_4, + GPIO16_KP_MKIN_5, + GPIO17_KP_MKIN_6, GPIO103_KP_MKOUT_0, GPIO104_KP_MKOUT_1, GPIO105_KP_MKOUT_2, @@ -139,8 +138,7 @@ static unsigned long z2_pin_config[] = { GPIO1_GPIO, /* Power button */ GPIO37_GPIO, /* Headphone detect */ GPIO98_GPIO, /* Lid switch */ - GPIO14_GPIO, /* WiFi Reset */ - GPIO15_GPIO, /* WiFi Power */ + GPIO14_GPIO, /* WiFi Power */ GPIO24_GPIO, /* WiFi CS */ GPIO36_GPIO, /* WiFi IRQ */ GPIO88_GPIO, /* LCD CS */ @@ -205,7 +203,7 @@ static struct platform_pwm_backlight_data z2_backlight_data[] = { /* Keypad Backlight */ .pwm_id = 1, .max_brightness = 1023, - .dft_brightness = 512, + .dft_brightness = 0, .pwm_period_ns = 1260320, }, [1] = { @@ -272,7 +270,7 @@ static struct pxafb_mach_info z2_lcd_screen = { static void __init z2_lcd_init(void) { - set_pxa_fb_info(&z2_lcd_screen); + pxa_set_fb_info(NULL, &z2_lcd_screen); } #else static inline void z2_lcd_init(void) {} @@ -310,12 +308,12 @@ struct gpio_led z2_gpio_leds[] = { .active_low = 1, }, { .name = "z2:green:charged", - .default_trigger = "none", + .default_trigger = "mmc0", .gpio = GPIO85_ZIPITZ2_LED_CHARGED, .active_low = 1, }, { .name = "z2:amber:charging", - .default_trigger = "none", + .default_trigger = "Z2-charging-or-full", .gpio = GPIO83_ZIPITZ2_LED_CHARGING, .active_low = 1, }, @@ -428,8 +426,22 @@ static inline void z2_mkp_init(void) {} ******************************************************************************/ #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) static struct gpio_keys_button z2_pxa_buttons[] = { - {KEY_POWER, GPIO1_ZIPITZ2_POWER_BUTTON, 0, "Power Button" }, - {KEY_CLOSE, GPIO98_ZIPITZ2_LID_BUTTON, 0, "Lid Button" }, + { + .code = KEY_POWER, + .gpio = GPIO1_ZIPITZ2_POWER_BUTTON, + .active_low = 0, + .desc = "Power Button", + .wakeup = 1, + .type = EV_KEY, + }, + { + .code = SW_LID, + .gpio = GPIO98_ZIPITZ2_LID_BUTTON, + .active_low = 1, + .desc = "Lid Switch", + .wakeup = 0, + .type = EV_SW, + }, }; static struct gpio_keys_platform_data z2_pxa_keys_data = { @@ -462,9 +474,9 @@ static struct z2_battery_info batt_chip_info = { .batt_I2C_addr = 0x55, .batt_I2C_reg = 2, .charge_gpio = GPIO0_ZIPITZ2_AC_DETECT, - .min_voltage = 2400000, - .max_voltage = 3700000, - .batt_div = 69, + .min_voltage = 3475000, + .max_voltage = 4190000, + .batt_div = 59, .batt_mult = 1000000, .batt_tech = POWER_SUPPLY_TECHNOLOGY_LION, .batt_name = "Z2", @@ -498,26 +510,16 @@ static int z2_lbs_spi_setup(struct spi_device *spi) { int ret = 0; - ret = gpio_request(GPIO15_ZIPITZ2_WIFI_POWER, "WiFi Power"); + ret = gpio_request(GPIO14_ZIPITZ2_WIFI_POWER, "WiFi Power"); if (ret) goto err; - ret = gpio_direction_output(GPIO15_ZIPITZ2_WIFI_POWER, 1); + ret = gpio_direction_output(GPIO14_ZIPITZ2_WIFI_POWER, 1); if (ret) goto err2; - ret = gpio_request(GPIO14_ZIPITZ2_WIFI_RESET, "WiFi Reset"); - if (ret) - goto err2; - - ret = gpio_direction_output(GPIO14_ZIPITZ2_WIFI_RESET, 0); - if (ret) - goto err3; - - /* Reset the card */ + /* Wait until card is powered on */ mdelay(180); - gpio_set_value(GPIO14_ZIPITZ2_WIFI_RESET, 1); - mdelay(20); spi->bits_per_word = 16; spi->mode = SPI_MODE_2, @@ -526,22 +528,18 @@ static int z2_lbs_spi_setup(struct spi_device *spi) return 0; -err3: - gpio_free(GPIO14_ZIPITZ2_WIFI_RESET); err2: - gpio_free(GPIO15_ZIPITZ2_WIFI_POWER); + gpio_free(GPIO14_ZIPITZ2_WIFI_POWER); err: return ret; }; static int z2_lbs_spi_teardown(struct spi_device *spi) { - gpio_set_value(GPIO14_ZIPITZ2_WIFI_RESET, 0); - gpio_set_value(GPIO15_ZIPITZ2_WIFI_POWER, 0); - gpio_free(GPIO14_ZIPITZ2_WIFI_RESET); - gpio_free(GPIO15_ZIPITZ2_WIFI_POWER); - return 0; + gpio_set_value(GPIO14_ZIPITZ2_WIFI_POWER, 0); + gpio_free(GPIO14_ZIPITZ2_WIFI_POWER); + return 0; }; static struct pxa2xx_spi_chip z2_lbs_chip_info = { diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index b92aa3b8c4f..00363c7ac18 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -25,6 +25,7 @@ #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> #include <linux/i2c.h> +#include <linux/i2c/pxa-i2c.h> #include <linux/i2c/pca953x.h> #include <linux/apm-emulation.h> #include <linux/can/platform/mcp251x.h> @@ -33,8 +34,6 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/i2c.h> - #include <mach/pxa2xx-regs.h> #include <mach/regs-uart.h> #include <mach/ohci.h> @@ -137,22 +136,23 @@ static void __init zeus_init_irq(void) /* Peripheral IRQs. It would be nice to move those inside driver configuration, but it is not supported at the moment. */ - set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), IRQ_TYPE_EDGE_FALLING); - set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING); + irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), + IRQ_TYPE_EDGE_FALLING); + irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING); /* Setup ISA IRQs */ for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) { isa_irq = zeus_bit_to_irq(level); - set_irq_chip(isa_irq, &zeus_irq_chip); - set_irq_handler(isa_irq, handle_edge_irq); + irq_set_chip_and_handler(isa_irq, &zeus_irq_chip, + handle_edge_irq); set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); } - set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING); - set_irq_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler); + irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING); + irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler); } @@ -847,7 +847,7 @@ static void __init zeus_init(void) if (zeus_setup_fb_gpios()) pr_err("Failed to setup fb gpios\n"); else - set_pxa_fb_info(&zeus_fb_info); + pxa_set_fb_info(NULL, &zeus_fb_info); pxa_set_mci_info(&zeus_mci_platform_data); pxa_set_udc_info(&zeus_udc_info); diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index a4c784aab76..5821185f77a 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -208,7 +208,7 @@ static void __init zylonite_init_lcd(void) platform_device_register(&zylonite_backlight_device); if (lcd_id & 0x20) { - set_pxa_fb_info(&zylonite_sharp_lcd_info); + pxa_set_fb_info(NULL, &zylonite_sharp_lcd_info); return; } @@ -220,7 +220,7 @@ static void __init zylonite_init_lcd(void) else zylonite_toshiba_lcd_info.modes = &toshiba_ltm04c380k_mode; - set_pxa_fb_info(&zylonite_toshiba_lcd_info); + pxa_set_fb_info(NULL, &zylonite_toshiba_lcd_info); } #else static inline void zylonite_init_lcd(void) {} diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c index 3aa73b3e33f..93c64d8d7de 100644 --- a/arch/arm/mach-pxa/zylonite_pxa300.c +++ b/arch/arm/mach-pxa/zylonite_pxa300.c @@ -17,11 +17,11 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/i2c.h> +#include <linux/i2c/pxa-i2c.h> #include <linux/i2c/pca953x.h> #include <linux/gpio.h> #include <mach/pxa300.h> -#include <plat/i2c.h> #include <mach/zylonite.h> #include "generic.h" diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile index a01b76b7c95..541fa4c109e 100644 --- a/arch/arm/mach-realview/Makefile +++ b/arch/arm/mach-realview/Makefile @@ -8,6 +8,5 @@ obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o obj-$(CONFIG_MACH_REALVIEW_PBA8) += realview_pba8.o obj-$(CONFIG_MACH_REALVIEW_PBX) += realview_pbx.o -obj-$(CONFIG_SMP) += platsmp.o headsmp.o +obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 1c6602cf50e..75dbc8791d0 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -51,6 +51,7 @@ #include <mach/irqs.h> #include <asm/hardware/timer-sp.h> +#include <plat/clcd.h> #include <plat/sched_clock.h> #include "core.h" @@ -359,18 +360,19 @@ static struct clk_lookup lookups[] = { } }; -static int __init clk_init(void) +void __init realview_init_early(void) { + void __iomem *sys = __io_address(REALVIEW_SYS_BASE); + if (machine_is_realview_pb1176()) - oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET; + oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC0_OFFSET; else - oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET; + oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC4_OFFSET; clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - return 0; + versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000); } -core_initcall(clk_init); /* * CLCD support. @@ -385,157 +387,6 @@ core_initcall(clk_init); #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8) #define SYS_CLCD_ID_VGA (0x1f << 8) -static struct clcd_panel vga = { - .mode = { - .name = "VGA", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 39721, - .left_margin = 40, - .right_margin = 24, - .upper_margin = 32, - .lower_margin = 11, - .hsync_len = 96, - .vsync_len = 2, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_BCD | TIM2_IPC, - .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), - .bpp = 16, -}; - -static struct clcd_panel xvga = { - .mode = { - .name = "XVGA", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15748, - .left_margin = 152, - .right_margin = 48, - .upper_margin = 23, - .lower_margin = 3, - .hsync_len = 104, - .vsync_len = 4, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_BCD | TIM2_IPC, - .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), - .bpp = 16, -}; - -static struct clcd_panel sanyo_3_8_in = { - .mode = { - .name = "Sanyo QVGA", - .refresh = 116, - .xres = 320, - .yres = 240, - .pixclock = 100000, - .left_margin = 6, - .right_margin = 6, - .upper_margin = 5, - .lower_margin = 5, - .hsync_len = 6, - .vsync_len = 6, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_BCD, - .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), - .bpp = 16, -}; - -static struct clcd_panel sanyo_2_5_in = { - .mode = { - .name = "Sanyo QVGA Portrait", - .refresh = 116, - .xres = 240, - .yres = 320, - .pixclock = 100000, - .left_margin = 20, - .right_margin = 10, - .upper_margin = 2, - .lower_margin = 2, - .hsync_len = 10, - .vsync_len = 2, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC, - .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), - .bpp = 16, -}; - -static struct clcd_panel epson_2_2_in = { - .mode = { - .name = "Epson QCIF", - .refresh = 390, - .xres = 176, - .yres = 220, - .pixclock = 62500, - .left_margin = 3, - .right_margin = 2, - .upper_margin = 1, - .lower_margin = 0, - .hsync_len = 3, - .vsync_len = 2, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_BCD | TIM2_IPC, - .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), - .bpp = 16, -}; - -/* - * Detect which LCD panel is connected, and return the appropriate - * clcd_panel structure. Note: we do not have any information on - * the required timings for the 8.4in panel, so we presently assume - * VGA timings. - */ -static struct clcd_panel *realview_clcd_panel(void) -{ - void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; - struct clcd_panel *vga_panel; - struct clcd_panel *panel; - u32 val; - - if (machine_is_realview_eb()) - vga_panel = &vga; - else - vga_panel = &xvga; - - val = readl(sys_clcd) & SYS_CLCD_ID_MASK; - if (val == SYS_CLCD_ID_SANYO_3_8) - panel = &sanyo_3_8_in; - else if (val == SYS_CLCD_ID_SANYO_2_5) - panel = &sanyo_2_5_in; - else if (val == SYS_CLCD_ID_EPSON_2_2) - panel = &epson_2_2_in; - else if (val == SYS_CLCD_ID_VGA) - panel = vga_panel; - else { - printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n", - val); - panel = vga_panel; - } - - return panel; -} - /* * Disable all display connectors on the interface module. */ @@ -565,56 +416,60 @@ static void realview_clcd_enable(struct clcd_fb *fb) writel(val, sys_clcd); } +/* + * Detect which LCD panel is connected, and return the appropriate + * clcd_panel structure. Note: we do not have any information on + * the required timings for the 8.4in panel, so we presently assume + * VGA timings. + */ static int realview_clcd_setup(struct clcd_fb *fb) { + void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; + const char *panel_name, *vga_panel_name; unsigned long framesize; - dma_addr_t dma; + u32 val; - if (machine_is_realview_eb()) + if (machine_is_realview_eb()) { /* VGA, 16bpp */ framesize = 640 * 480 * 2; - else + vga_panel_name = "VGA"; + } else { /* XVGA, 16bpp */ framesize = 1024 * 768 * 2; - - fb->panel = realview_clcd_panel(); - - fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, - &dma, GFP_KERNEL | GFP_DMA); - if (!fb->fb.screen_base) { - printk(KERN_ERR "CLCD: unable to map framebuffer\n"); - return -ENOMEM; + vga_panel_name = "XVGA"; } - fb->fb.fix.smem_start = dma; - fb->fb.fix.smem_len = framesize; - - return 0; -} + val = readl(sys_clcd) & SYS_CLCD_ID_MASK; + if (val == SYS_CLCD_ID_SANYO_3_8) + panel_name = "Sanyo TM38QV67A02A"; + else if (val == SYS_CLCD_ID_SANYO_2_5) + panel_name = "Sanyo QVGA Portrait"; + else if (val == SYS_CLCD_ID_EPSON_2_2) + panel_name = "Epson L2F50113T00"; + else if (val == SYS_CLCD_ID_VGA) + panel_name = vga_panel_name; + else { + pr_err("CLCD: unknown LCD panel ID 0x%08x, using VGA\n", val); + panel_name = vga_panel_name; + } -static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) -{ - return dma_mmap_writecombine(&fb->dev->dev, vma, - fb->fb.screen_base, - fb->fb.fix.smem_start, - fb->fb.fix.smem_len); -} + fb->panel = versatile_clcd_get_panel(panel_name); + if (!fb->panel) + return -EINVAL; -static void realview_clcd_remove(struct clcd_fb *fb) -{ - dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, - fb->fb.screen_base, fb->fb.fix.smem_start); + return versatile_clcd_setup_dma(fb, framesize); } struct clcd_board clcd_plat_data = { .name = "RealView", + .caps = CLCD_CAP_ALL, .check = clcdfb_check, .decode = clcdfb_decode, .disable = realview_clcd_disable, .enable = realview_clcd_enable, .setup = realview_clcd_setup, - .mmap = realview_clcd_mmap, - .remove = realview_clcd_remove, + .mmap = versatile_clcd_mmap_dma, + .remove = versatile_clcd_remove_dma, }; #ifdef CONFIG_LEDS @@ -656,12 +511,6 @@ void realview_leds_event(led_event_t ledevt) #endif /* CONFIG_LEDS */ /* - * The sched_clock counter - */ -#define REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + \ - REALVIEW_SYS_24MHz_OFFSET) - -/* * Where is the timer (VA)? */ void __iomem *timer0_va_base; @@ -676,8 +525,6 @@ void __init realview_timer_init(unsigned int timer_irq) { u32 val; - versatile_sched_clock_init(REFCOUNTER, 24000000); - /* * set clock frequency: * REALVIEW_REFCLK is 32KHz diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h index 693239ddc39..5c83d1e87a0 100644 --- a/arch/arm/mach-realview/core.h +++ b/arch/arm/mach-realview/core.h @@ -42,7 +42,6 @@ static struct amba_device name##_device = { \ }, \ .dma_mask = ~0, \ .irq = base##_IRQ, \ - /* .dma = base##_DMA,*/ \ } struct machine_desc; @@ -63,6 +62,7 @@ extern void realview_timer_init(unsigned int timer_irq); extern int realview_flash_register(struct resource *res, u32 num); extern int realview_eth_register(const char *name, struct resource *res); extern int realview_usb_register(struct resource *res); +extern void realview_init_early(void); extern void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from, struct meminfo *meminfo); extern void (*realview_reset)(char); diff --git a/arch/arm/mach-realview/headsmp.S b/arch/arm/mach-realview/headsmp.S deleted file mode 100644 index b34be4554d4..00000000000 --- a/arch/arm/mach-realview/headsmp.S +++ /dev/null @@ -1,40 +0,0 @@ -/* - * linux/arch/arm/mach-realview/headsmp.S - * - * Copyright (c) 2003 ARM Limited - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/linkage.h> -#include <linux/init.h> - - __INIT - -/* - * Realview specific entry point for secondary CPUs. This provides - * a "holding pen" into which all secondary cores are held until we're - * ready for them to initialise. - */ -ENTRY(realview_secondary_startup) - mrc p15, 0, r0, c0, c0, 5 - and r0, r0, #15 - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - add r6, r6, r4 -pen: ldr r7, [r6] - cmp r7, r0 - bne pen - - /* - * we've been released from the holding pen: secondary_stack - * should now contain the SVC stack for this core - */ - b secondary_startup - - .align -1: .long . - .long pen_release diff --git a/arch/arm/mach-realview/include/mach/barriers.h b/arch/arm/mach-realview/include/mach/barriers.h index 0c5d749d7b5..9a732195aa1 100644 --- a/arch/arm/mach-realview/include/mach/barriers.h +++ b/arch/arm/mach-realview/include/mach/barriers.h @@ -4,5 +4,5 @@ * operation to deadlock the system. */ #define mb() dsb() -#define rmb() dmb() +#define rmb() dsb() #define wmb() mb() diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c deleted file mode 100644 index 60b4e111f45..00000000000 --- a/arch/arm/mach-realview/localtimer.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * linux/arch/arm/mach-realview/localtimer.c - * - * Copyright (C) 2002 ARM Ltd. - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/init.h> -#include <linux/smp.h> -#include <linux/clockchips.h> - -#include <asm/irq.h> -#include <asm/smp_twd.h> -#include <asm/localtimer.h> - -/* - * Setup the local clock events for a CPU. - */ -void __cpuinit local_timer_setup(struct clock_event_device *evt) -{ - evt->irq = IRQ_LOCALTIMER; - twd_timer_setup(evt); -} diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index 6959d13d908..23919229e12 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -10,44 +10,21 @@ */ #include <linux/init.h> #include <linux/errno.h> -#include <linux/delay.h> -#include <linux/device.h> -#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <asm/cacheflush.h> #include <mach/hardware.h> #include <asm/mach-types.h> +#include <asm/smp_scu.h> #include <asm/unified.h> #include <mach/board-eb.h> #include <mach/board-pb11mp.h> #include <mach/board-pbx.h> -#include <asm/smp_scu.h> #include "core.h" -extern void realview_secondary_startup(void); - -/* - * control for which core is the next to come out of the secondary - * boot "holding pen" - */ -volatile int __cpuinitdata pen_release = -1; - -/* - * Write pen_release in a way that is guaranteed to be visible to all - * observers, irrespective of whether they're taking part in coherency - * or not. This is necessary for the hotplug code to work reliably. - */ -static void __cpuinit write_pen_release(int val) -{ - pen_release = val; - smp_wmb(); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); -} +extern void versatile_secondary_startup(void); static void __iomem *scu_base_addr(void) { @@ -62,75 +39,6 @@ static void __iomem *scu_base_addr(void) return (void __iomem *)0; } -static DEFINE_SPINLOCK(boot_lock); - -void __cpuinit platform_secondary_init(unsigned int cpu) -{ - /* - * if any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - gic_secondary_init(0); - - /* - * let the primary processor know we're out of the - * pen, then head off into the C entry point - */ - write_pen_release(-1); - - /* - * Synchronise with the boot thread. - */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); -} - -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - unsigned long timeout; - - /* - * set synchronisation state between this boot processor - * and the secondary one - */ - spin_lock(&boot_lock); - - /* - * The secondary processor is waiting to be released from - * the holding pen - release it, then wait for it to flag - * that it has been released by resetting pen_release. - * - * Note that "pen_release" is the hardware CPU ID, whereas - * "cpu" is Linux's internal ID. - */ - write_pen_release(cpu); - - /* - * Send the secondary CPU a soft interrupt, thereby causing - * the boot monitor to read the system wide flags register, - * and branch to the address found there. - */ - smp_cross_call(cpumask_of(cpu), 1); - - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) { - smp_rmb(); - if (pen_release == -1) - break; - - udelay(10); - } - - /* - * now the secondary core is starting up let it run its - * calibrations, then wait for it to finish - */ - spin_unlock(&boot_lock); - - return pen_release != -1 ? -ENOSYS : 0; -} - /* * Initialise the CPU possible map early - this describes the CPUs * which may be present or become present in the system. @@ -174,6 +82,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) * until it receives a soft interrupt, and then the * secondary CPU branches to this address. */ - __raw_writel(BSYM(virt_to_phys(realview_secondary_startup)), + __raw_writel(BSYM(virt_to_phys(versatile_secondary_startup)), __io_address(REALVIEW_SYS_FLAGSSET)); } diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 8ede983b861..10e75faba4c 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -144,60 +144,39 @@ static struct pl022_ssp_controller ssp0_plat_data = { * These devices are connected via the core APB bridge */ #define GPIO2_IRQ { IRQ_EB_GPIO2, NO_IRQ } -#define GPIO2_DMA { 0, 0 } #define GPIO3_IRQ { IRQ_EB_GPIO3, NO_IRQ } -#define GPIO3_DMA { 0, 0 } #define AACI_IRQ { IRQ_EB_AACI, NO_IRQ } -#define AACI_DMA { 0x80, 0x81 } #define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B } -#define MMCI0_DMA { 0x84, 0 } #define KMI0_IRQ { IRQ_EB_KMI0, NO_IRQ } -#define KMI0_DMA { 0, 0 } #define KMI1_IRQ { IRQ_EB_KMI1, NO_IRQ } -#define KMI1_DMA { 0, 0 } /* * These devices are connected directly to the multi-layer AHB switch */ #define EB_SMC_IRQ { NO_IRQ, NO_IRQ } -#define EB_SMC_DMA { 0, 0 } #define MPMC_IRQ { NO_IRQ, NO_IRQ } -#define MPMC_DMA { 0, 0 } #define EB_CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ } -#define EB_CLCD_DMA { 0, 0 } #define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ } -#define DMAC_DMA { 0, 0 } /* * These devices are connected via the core APB bridge */ #define SCTL_IRQ { NO_IRQ, NO_IRQ } -#define SCTL_DMA { 0, 0 } #define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ } -#define EB_WATCHDOG_DMA { 0, 0 } #define EB_GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ } -#define EB_GPIO0_DMA { 0, 0 } #define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ } -#define GPIO1_DMA { 0, 0 } #define EB_RTC_IRQ { IRQ_EB_RTC, NO_IRQ } -#define EB_RTC_DMA { 0, 0 } /* * These devices are connected via the DMA APB bridge */ #define SCI_IRQ { IRQ_EB_SCI, NO_IRQ } -#define SCI_DMA { 7, 6 } #define EB_UART0_IRQ { IRQ_EB_UART0, NO_IRQ } -#define EB_UART0_DMA { 15, 14 } #define EB_UART1_IRQ { IRQ_EB_UART1, NO_IRQ } -#define EB_UART1_DMA { 13, 12 } #define EB_UART2_IRQ { IRQ_EB_UART2, NO_IRQ } -#define EB_UART2_DMA { 11, 10 } #define EB_UART3_IRQ { IRQ_EB_UART3, NO_IRQ } -#define EB_UART3_DMA { 0x86, 0x87 } #define EB_SSP_IRQ { IRQ_EB_SSP, NO_IRQ } -#define EB_SSP_DMA { 9, 8 } /* FPGA Primecells */ AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); @@ -369,7 +348,7 @@ static void __init gic_init_irq(void) #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB /* board GIC, secondary */ - gic_init(1, 64, __io_address(REALVIEW_EB_GIC_DIST_BASE), + gic_init(1, 96, __io_address(REALVIEW_EB_GIC_DIST_BASE), __io_address(REALVIEW_EB_GIC_CPU_BASE)); gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); #endif @@ -487,6 +466,7 @@ MACHINE_START(REALVIEW_EB, "ARM-RealView EB") .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_fixup, .map_io = realview_eb_map_io, + .init_early = realview_init_early, .init_irq = gic_init_irq, .timer = &realview_eb_timer, .init_machine = realview_eb_init, diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index 9f26369555c..eab6070f66d 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c @@ -134,47 +134,26 @@ static struct pl022_ssp_controller ssp0_plat_data = { * RealView PB1176 AMBA devices */ #define GPIO2_IRQ { IRQ_PB1176_GPIO2, NO_IRQ } -#define GPIO2_DMA { 0, 0 } #define GPIO3_IRQ { IRQ_PB1176_GPIO3, NO_IRQ } -#define GPIO3_DMA { 0, 0 } #define AACI_IRQ { IRQ_PB1176_AACI, NO_IRQ } -#define AACI_DMA { 0x80, 0x81 } #define MMCI0_IRQ { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B } -#define MMCI0_DMA { 0x84, 0 } #define KMI0_IRQ { IRQ_PB1176_KMI0, NO_IRQ } -#define KMI0_DMA { 0, 0 } #define KMI1_IRQ { IRQ_PB1176_KMI1, NO_IRQ } -#define KMI1_DMA { 0, 0 } #define PB1176_SMC_IRQ { NO_IRQ, NO_IRQ } -#define PB1176_SMC_DMA { 0, 0 } #define MPMC_IRQ { NO_IRQ, NO_IRQ } -#define MPMC_DMA { 0, 0 } #define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ } -#define PB1176_CLCD_DMA { 0, 0 } #define SCTL_IRQ { NO_IRQ, NO_IRQ } -#define SCTL_DMA { 0, 0 } #define PB1176_WATCHDOG_IRQ { IRQ_DC1176_WATCHDOG, NO_IRQ } -#define PB1176_WATCHDOG_DMA { 0, 0 } #define PB1176_GPIO0_IRQ { IRQ_PB1176_GPIO0, NO_IRQ } -#define PB1176_GPIO0_DMA { 0, 0 } #define GPIO1_IRQ { IRQ_PB1176_GPIO1, NO_IRQ } -#define GPIO1_DMA { 0, 0 } #define PB1176_RTC_IRQ { IRQ_DC1176_RTC, NO_IRQ } -#define PB1176_RTC_DMA { 0, 0 } #define SCI_IRQ { IRQ_PB1176_SCI, NO_IRQ } -#define SCI_DMA { 7, 6 } #define PB1176_UART0_IRQ { IRQ_DC1176_UART0, NO_IRQ } -#define PB1176_UART0_DMA { 15, 14 } #define PB1176_UART1_IRQ { IRQ_DC1176_UART1, NO_IRQ } -#define PB1176_UART1_DMA { 13, 12 } #define PB1176_UART2_IRQ { IRQ_DC1176_UART2, NO_IRQ } -#define PB1176_UART2_DMA { 11, 10 } #define PB1176_UART3_IRQ { IRQ_DC1176_UART3, NO_IRQ } -#define PB1176_UART3_DMA { 0x86, 0x87 } #define PB1176_UART4_IRQ { IRQ_PB1176_UART4, NO_IRQ } -#define PB1176_UART4_DMA { 0, 0 } #define PB1176_SSP_IRQ { IRQ_DC1176_SSP, NO_IRQ } -#define PB1176_SSP_DMA { 9, 8 } /* FPGA Primecells */ AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); @@ -382,6 +361,7 @@ MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176") .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_pb1176_fixup, .map_io = realview_pb1176_map_io, + .init_early = realview_init_early, .init_irq = gic_init_irq, .timer = &realview_pb1176_timer, .init_machine = realview_pb1176_init, diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index dea06b2da3a..b2985fc7cd4 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c @@ -136,47 +136,26 @@ static struct pl022_ssp_controller ssp0_plat_data = { */ #define GPIO2_IRQ { IRQ_PB11MP_GPIO2, NO_IRQ } -#define GPIO2_DMA { 0, 0 } #define GPIO3_IRQ { IRQ_PB11MP_GPIO3, NO_IRQ } -#define GPIO3_DMA { 0, 0 } #define AACI_IRQ { IRQ_TC11MP_AACI, NO_IRQ } -#define AACI_DMA { 0x80, 0x81 } #define MMCI0_IRQ { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B } -#define MMCI0_DMA { 0x84, 0 } #define KMI0_IRQ { IRQ_TC11MP_KMI0, NO_IRQ } -#define KMI0_DMA { 0, 0 } #define KMI1_IRQ { IRQ_TC11MP_KMI1, NO_IRQ } -#define KMI1_DMA { 0, 0 } #define PB11MP_SMC_IRQ { NO_IRQ, NO_IRQ } -#define PB11MP_SMC_DMA { 0, 0 } #define MPMC_IRQ { NO_IRQ, NO_IRQ } -#define MPMC_DMA { 0, 0 } #define PB11MP_CLCD_IRQ { IRQ_PB11MP_CLCD, NO_IRQ } -#define PB11MP_CLCD_DMA { 0, 0 } #define DMAC_IRQ { IRQ_PB11MP_DMAC, NO_IRQ } -#define DMAC_DMA { 0, 0 } #define SCTL_IRQ { NO_IRQ, NO_IRQ } -#define SCTL_DMA { 0, 0 } #define PB11MP_WATCHDOG_IRQ { IRQ_PB11MP_WATCHDOG, NO_IRQ } -#define PB11MP_WATCHDOG_DMA { 0, 0 } #define PB11MP_GPIO0_IRQ { IRQ_PB11MP_GPIO0, NO_IRQ } -#define PB11MP_GPIO0_DMA { 0, 0 } #define GPIO1_IRQ { IRQ_PB11MP_GPIO1, NO_IRQ } -#define GPIO1_DMA { 0, 0 } #define PB11MP_RTC_IRQ { IRQ_TC11MP_RTC, NO_IRQ } -#define PB11MP_RTC_DMA { 0, 0 } #define SCI_IRQ { IRQ_PB11MP_SCI, NO_IRQ } -#define SCI_DMA { 7, 6 } #define PB11MP_UART0_IRQ { IRQ_TC11MP_UART0, NO_IRQ } -#define PB11MP_UART0_DMA { 15, 14 } #define PB11MP_UART1_IRQ { IRQ_TC11MP_UART1, NO_IRQ } -#define PB11MP_UART1_DMA { 13, 12 } #define PB11MP_UART2_IRQ { IRQ_PB11MP_UART2, NO_IRQ } -#define PB11MP_UART2_DMA { 11, 10 } #define PB11MP_UART3_IRQ { IRQ_PB11MP_UART3, NO_IRQ } -#define PB11MP_UART3_DMA { 0x86, 0x87 } #define PB11MP_SSP_IRQ { IRQ_PB11MP_SSP, NO_IRQ } -#define PB11MP_SSP_DMA { 9, 8 } /* FPGA Primecells */ AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); @@ -384,6 +363,7 @@ MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore") .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_fixup, .map_io = realview_pb11mp_map_io, + .init_early = realview_init_early, .init_irq = gic_init_irq, .timer = &realview_pb11mp_timer, .init_machine = realview_pb11mp_init, diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c index 7d0f1734a21..fb686655876 100644 --- a/arch/arm/mach-realview/realview_pba8.c +++ b/arch/arm/mach-realview/realview_pba8.c @@ -126,47 +126,26 @@ static struct pl022_ssp_controller ssp0_plat_data = { */ #define GPIO2_IRQ { IRQ_PBA8_GPIO2, NO_IRQ } -#define GPIO2_DMA { 0, 0 } #define GPIO3_IRQ { IRQ_PBA8_GPIO3, NO_IRQ } -#define GPIO3_DMA { 0, 0 } #define AACI_IRQ { IRQ_PBA8_AACI, NO_IRQ } -#define AACI_DMA { 0x80, 0x81 } #define MMCI0_IRQ { IRQ_PBA8_MMCI0A, IRQ_PBA8_MMCI0B } -#define MMCI0_DMA { 0x84, 0 } #define KMI0_IRQ { IRQ_PBA8_KMI0, NO_IRQ } -#define KMI0_DMA { 0, 0 } #define KMI1_IRQ { IRQ_PBA8_KMI1, NO_IRQ } -#define KMI1_DMA { 0, 0 } #define PBA8_SMC_IRQ { NO_IRQ, NO_IRQ } -#define PBA8_SMC_DMA { 0, 0 } #define MPMC_IRQ { NO_IRQ, NO_IRQ } -#define MPMC_DMA { 0, 0 } #define PBA8_CLCD_IRQ { IRQ_PBA8_CLCD, NO_IRQ } -#define PBA8_CLCD_DMA { 0, 0 } #define DMAC_IRQ { IRQ_PBA8_DMAC, NO_IRQ } -#define DMAC_DMA { 0, 0 } #define SCTL_IRQ { NO_IRQ, NO_IRQ } -#define SCTL_DMA { 0, 0 } #define PBA8_WATCHDOG_IRQ { IRQ_PBA8_WATCHDOG, NO_IRQ } -#define PBA8_WATCHDOG_DMA { 0, 0 } #define PBA8_GPIO0_IRQ { IRQ_PBA8_GPIO0, NO_IRQ } -#define PBA8_GPIO0_DMA { 0, 0 } #define GPIO1_IRQ { IRQ_PBA8_GPIO1, NO_IRQ } -#define GPIO1_DMA { 0, 0 } #define PBA8_RTC_IRQ { IRQ_PBA8_RTC, NO_IRQ } -#define PBA8_RTC_DMA { 0, 0 } #define SCI_IRQ { IRQ_PBA8_SCI, NO_IRQ } -#define SCI_DMA { 7, 6 } #define PBA8_UART0_IRQ { IRQ_PBA8_UART0, NO_IRQ } -#define PBA8_UART0_DMA { 15, 14 } #define PBA8_UART1_IRQ { IRQ_PBA8_UART1, NO_IRQ } -#define PBA8_UART1_DMA { 13, 12 } #define PBA8_UART2_IRQ { IRQ_PBA8_UART2, NO_IRQ } -#define PBA8_UART2_DMA { 11, 10 } #define PBA8_UART3_IRQ { IRQ_PBA8_UART3, NO_IRQ } -#define PBA8_UART3_DMA { 0x86, 0x87 } #define PBA8_SSP_IRQ { IRQ_PBA8_SSP, NO_IRQ } -#define PBA8_SSP_DMA { 9, 8 } /* FPGA Primecells */ AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); @@ -334,6 +313,7 @@ MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8") .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_fixup, .map_io = realview_pba8_map_io, + .init_early = realview_init_early, .init_irq = gic_init_irq, .timer = &realview_pba8_timer, .init_machine = realview_pba8_init, diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index b89e28f8853..92ace2cf2b2 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c @@ -148,47 +148,26 @@ static struct pl022_ssp_controller ssp0_plat_data = { */ #define GPIO2_IRQ { IRQ_PBX_GPIO2, NO_IRQ } -#define GPIO2_DMA { 0, 0 } #define GPIO3_IRQ { IRQ_PBX_GPIO3, NO_IRQ } -#define GPIO3_DMA { 0, 0 } #define AACI_IRQ { IRQ_PBX_AACI, NO_IRQ } -#define AACI_DMA { 0x80, 0x81 } #define MMCI0_IRQ { IRQ_PBX_MMCI0A, IRQ_PBX_MMCI0B } -#define MMCI0_DMA { 0x84, 0 } #define KMI0_IRQ { IRQ_PBX_KMI0, NO_IRQ } -#define KMI0_DMA { 0, 0 } #define KMI1_IRQ { IRQ_PBX_KMI1, NO_IRQ } -#define KMI1_DMA { 0, 0 } #define PBX_SMC_IRQ { NO_IRQ, NO_IRQ } -#define PBX_SMC_DMA { 0, 0 } #define MPMC_IRQ { NO_IRQ, NO_IRQ } -#define MPMC_DMA { 0, 0 } #define PBX_CLCD_IRQ { IRQ_PBX_CLCD, NO_IRQ } -#define PBX_CLCD_DMA { 0, 0 } #define DMAC_IRQ { IRQ_PBX_DMAC, NO_IRQ } -#define DMAC_DMA { 0, 0 } #define SCTL_IRQ { NO_IRQ, NO_IRQ } -#define SCTL_DMA { 0, 0 } #define PBX_WATCHDOG_IRQ { IRQ_PBX_WATCHDOG, NO_IRQ } -#define PBX_WATCHDOG_DMA { 0, 0 } #define PBX_GPIO0_IRQ { IRQ_PBX_GPIO0, NO_IRQ } -#define PBX_GPIO0_DMA { 0, 0 } #define GPIO1_IRQ { IRQ_PBX_GPIO1, NO_IRQ } -#define GPIO1_DMA { 0, 0 } #define PBX_RTC_IRQ { IRQ_PBX_RTC, NO_IRQ } -#define PBX_RTC_DMA { 0, 0 } #define SCI_IRQ { IRQ_PBX_SCI, NO_IRQ } -#define SCI_DMA { 7, 6 } #define PBX_UART0_IRQ { IRQ_PBX_UART0, NO_IRQ } -#define PBX_UART0_DMA { 15, 14 } #define PBX_UART1_IRQ { IRQ_PBX_UART1, NO_IRQ } -#define PBX_UART1_DMA { 13, 12 } #define PBX_UART2_IRQ { IRQ_PBX_UART2, NO_IRQ } -#define PBX_UART2_DMA { 11, 10 } #define PBX_UART3_IRQ { IRQ_PBX_UART3, NO_IRQ } -#define PBX_UART3_DMA { 0x86, 0x87 } #define PBX_SSP_IRQ { IRQ_PBX_SSP, NO_IRQ } -#define PBX_SSP_DMA { 9, 8 } /* FPGA Primecells */ AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); @@ -417,6 +396,7 @@ MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX") .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_pbx_fixup, .map_io = realview_pbx_map_io, + .init_early = realview_init_early, .init_irq = gic_init_irq, .timer = &realview_pbx_timer, .init_machine = realview_pbx_init, diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c index d29cd9b737f..2e1b5309fba 100644 --- a/arch/arm/mach-rpc/irq.c +++ b/arch/arm/mach-rpc/irq.c @@ -133,25 +133,25 @@ void __init rpc_init_irq(void) switch (irq) { case 0 ... 7: - set_irq_chip(irq, &iomd_a_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &iomd_a_chip, + handle_level_irq); set_irq_flags(irq, flags); break; case 8 ... 15: - set_irq_chip(irq, &iomd_b_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &iomd_b_chip, + handle_level_irq); set_irq_flags(irq, flags); break; case 16 ... 21: - set_irq_chip(irq, &iomd_dma_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &iomd_dma_chip, + handle_level_irq); set_irq_flags(irq, flags); break; case 64 ... 71: - set_irq_chip(irq, &iomd_fiq_chip); + irq_set_chip(irq, &iomd_fiq_chip); set_irq_flags(irq, IRQF_VALID); break; } diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c index 606cb6b1cc4..bc53d2d16d1 100644 --- a/arch/arm/mach-s3c2410/bast-irq.c +++ b/arch/arm/mach-s3c2410/bast-irq.c @@ -147,15 +147,15 @@ static __init int bast_irq_init(void) __raw_writeb(0x0, BAST_VA_PC104_IRQMASK); - set_irq_chained_handler(IRQ_ISA, bast_irq_pc104_demux); + irq_set_chained_handler(IRQ_ISA, bast_irq_pc104_demux); /* register our IRQs */ for (i = 0; i < 4; i++) { unsigned int irqno = bast_pc104_irqs[i]; - set_irq_chip(irqno, &bast_pc104_chip); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &bast_pc104_chip, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } } diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c index 6b86a722a7d..2c126bbca08 100644 --- a/arch/arm/mach-s3c2410/h1940-bluetooth.c +++ b/arch/arm/mach-s3c2410/h1940-bluetooth.c @@ -18,12 +18,14 @@ #include <linux/leds.h> #include <linux/gpio.h> #include <linux/rfkill.h> +#include <linux/leds.h> #include <mach/regs-gpio.h> #include <mach/hardware.h> #include <mach/h1940-latch.h> +#include <mach/h1940.h> -#define DRV_NAME "h1940-bt" +#define DRV_NAME "h1940-bt" /* Bluetooth control */ static void h1940bt_enable(int on) @@ -37,6 +39,8 @@ static void h1940bt_enable(int on) gpio_set_value(S3C2410_GPH(1), 1); mdelay(10); gpio_set_value(S3C2410_GPH(1), 0); + + h1940_led_blink_set(-EINVAL, GPIO_LED_BLINK, NULL, NULL); } else { gpio_set_value(S3C2410_GPH(1), 1); @@ -44,6 +48,8 @@ static void h1940bt_enable(int on) gpio_set_value(S3C2410_GPH(1), 0); mdelay(10); gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 0); + + h1940_led_blink_set(-EINVAL, GPIO_LED_NO_BLINK_LOW, NULL, NULL); } } @@ -85,7 +91,6 @@ static int __devinit h1940bt_probe(struct platform_device *pdev) s3c_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0); s3c_gpio_setpull(S3C2410_GPH(3), S3C_GPIO_PULL_NONE); - rfk = rfkill_alloc(DRV_NAME, &pdev->dev, RFKILL_TYPE_BLUETOOTH, &h1940bt_rfkill_ops, NULL); if (!rfk) { @@ -93,8 +98,6 @@ static int __devinit h1940bt_probe(struct platform_device *pdev) goto err_rfk_alloc; } - rfkill_set_led_trigger_name(rfk, "h1940-bluetooth"); - ret = rfkill_register(rfk); if (ret) goto err_rfkill; diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h index cf68136cc66..b2b2a5bb275 100644 --- a/arch/arm/mach-s3c2410/include/mach/dma.h +++ b/arch/arm/mach-s3c2410/include/mach/dma.h @@ -19,7 +19,7 @@ #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ /* We use `virtual` dma channels to hide the fact we have only a limited - * number of DMA channels, and not of all of them (dependant on the device) + * number of DMA channels, and not of all of them (dependent on the device) * can be attached to any DMA source. We therefore let the DMA core handle * the allocation of hardware channels to clients. */ diff --git a/arch/arm/mach-s3c2410/include/mach/h1940.h b/arch/arm/mach-s3c2410/include/mach/h1940.h index 4559784129c..2aa683c8d3d 100644 --- a/arch/arm/mach-s3c2410/include/mach/h1940.h +++ b/arch/arm/mach-s3c2410/include/mach/h1940.h @@ -17,5 +17,8 @@ #define H1940_SUSPEND_CHECK (0x30080000) extern void h1940_pm_return(void); +extern int h1940_led_blink_set(unsigned gpio, int state, + unsigned long *delay_on, unsigned long *delay_off); + #endif /* __ASM_ARCH_H1940_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-mem.h index 7f7c5294796..988a6863e54 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-mem.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-mem.h @@ -101,7 +101,7 @@ #define S3C2410_BANKCON_PMC16 (0x03) /* bank configurations for banks 0..7, note banks - * 6 and 7 have differnt configurations depending on + * 6 and 7 have different configurations depending on * the memory type bits */ #define S3C2410_BANKCON_Tacp2 (0x0 << 2) diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 1e93f176c1d..2a2fa062013 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -23,8 +23,15 @@ #include <linux/platform_device.h> #include <linux/io.h> #include <linux/gpio.h> +#include <linux/input.h> +#include <linux/gpio_keys.h> #include <linux/pwm_backlight.h> #include <linux/i2c.h> +#include <linux/leds.h> +#include <linux/pda_power.h> +#include <linux/s3c_adc_battery.h> +#include <linux/delay.h> + #include <video/platform_lcd.h> #include <linux/mmc/host.h> @@ -203,20 +210,239 @@ static struct s3c2410fb_mach_info h1940_fb_info __initdata = { .num_displays = 1, .default_display = 0, - .lpcsel= 0x02, - .gpccon= 0xaa940659, - .gpccon_mask= 0xffffffff, - .gpcup= 0x0000ffff, - .gpcup_mask= 0xffffffff, - .gpdcon= 0xaa84aaa0, - .gpdcon_mask= 0xffffffff, - .gpdup= 0x0000faff, - .gpdup_mask= 0xffffffff, + .lpcsel = 0x02, + .gpccon = 0xaa940659, + .gpccon_mask = 0xffffc0f0, + .gpcup = 0x0000ffff, + .gpcup_mask = 0xffffffff, + .gpdcon = 0xaa84aaa0, + .gpdcon_mask = 0xffffffff, + .gpdup = 0x0000faff, + .gpdup_mask = 0xffffffff, }; -static struct platform_device h1940_device_leds = { - .name = "h1940-leds", +static int power_supply_init(struct device *dev) +{ + return gpio_request(S3C2410_GPF(2), "cable plugged"); +} + +static int h1940_is_ac_online(void) +{ + return !gpio_get_value(S3C2410_GPF(2)); +} + +static void power_supply_exit(struct device *dev) +{ + gpio_free(S3C2410_GPF(2)); +} + +static char *h1940_supplicants[] = { + "main-battery", + "backup-battery", +}; + +static struct pda_power_pdata power_supply_info = { + .init = power_supply_init, + .is_ac_online = h1940_is_ac_online, + .exit = power_supply_exit, + .supplied_to = h1940_supplicants, + .num_supplicants = ARRAY_SIZE(h1940_supplicants), +}; + +static struct resource power_supply_resources[] = { + [0] = { + .name = "ac", + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE | + IORESOURCE_IRQ_HIGHEDGE, + .start = IRQ_EINT2, + .end = IRQ_EINT2, + }, +}; + +static struct platform_device power_supply = { + .name = "pda-power", + .id = -1, + .dev = { + .platform_data = + &power_supply_info, + }, + .resource = power_supply_resources, + .num_resources = ARRAY_SIZE(power_supply_resources), +}; + +static const struct s3c_adc_bat_thresh bat_lut_noac[] = { + { .volt = 4070, .cur = 162, .level = 100}, + { .volt = 4040, .cur = 165, .level = 95}, + { .volt = 4016, .cur = 164, .level = 90}, + { .volt = 3996, .cur = 166, .level = 85}, + { .volt = 3971, .cur = 168, .level = 80}, + { .volt = 3951, .cur = 168, .level = 75}, + { .volt = 3931, .cur = 170, .level = 70}, + { .volt = 3903, .cur = 172, .level = 65}, + { .volt = 3886, .cur = 172, .level = 60}, + { .volt = 3858, .cur = 176, .level = 55}, + { .volt = 3842, .cur = 176, .level = 50}, + { .volt = 3818, .cur = 176, .level = 45}, + { .volt = 3789, .cur = 180, .level = 40}, + { .volt = 3769, .cur = 180, .level = 35}, + { .volt = 3749, .cur = 184, .level = 30}, + { .volt = 3732, .cur = 184, .level = 25}, + { .volt = 3716, .cur = 184, .level = 20}, + { .volt = 3708, .cur = 184, .level = 15}, + { .volt = 3716, .cur = 96, .level = 10}, + { .volt = 3700, .cur = 96, .level = 5}, + { .volt = 3684, .cur = 96, .level = 0}, +}; + +static const struct s3c_adc_bat_thresh bat_lut_acin[] = { + { .volt = 4130, .cur = 0, .level = 100}, + { .volt = 3982, .cur = 0, .level = 50}, + { .volt = 3854, .cur = 0, .level = 10}, + { .volt = 3841, .cur = 0, .level = 0}, +}; + +int h1940_bat_init(void) +{ + int ret; + + ret = gpio_request(H1940_LATCH_SM803_ENABLE, "h1940-charger-enable"); + if (ret) + return ret; + gpio_direction_output(H1940_LATCH_SM803_ENABLE, 0); + + return 0; + +} + +void h1940_bat_exit(void) +{ + gpio_free(H1940_LATCH_SM803_ENABLE); +} + +void h1940_enable_charger(void) +{ + gpio_set_value(H1940_LATCH_SM803_ENABLE, 1); +} + +void h1940_disable_charger(void) +{ + gpio_set_value(H1940_LATCH_SM803_ENABLE, 0); +} + +static struct s3c_adc_bat_pdata h1940_bat_cfg = { + .init = h1940_bat_init, + .exit = h1940_bat_exit, + .enable_charger = h1940_enable_charger, + .disable_charger = h1940_disable_charger, + .gpio_charge_finished = S3C2410_GPF(3), + .gpio_inverted = 1, + .lut_noac = bat_lut_noac, + .lut_noac_cnt = ARRAY_SIZE(bat_lut_noac), + .lut_acin = bat_lut_acin, + .lut_acin_cnt = ARRAY_SIZE(bat_lut_acin), + .volt_channel = 0, + .current_channel = 1, + .volt_mult = 4056, + .current_mult = 1893, + .internal_impedance = 200, + .backup_volt_channel = 3, + /* TODO Check backup volt multiplier */ + .backup_volt_mult = 4056, + .backup_volt_min = 0, + .backup_volt_max = 4149288 +}; + +static struct platform_device h1940_battery = { + .name = "s3c-adc-battery", .id = -1, + .dev = { + .parent = &s3c_device_adc.dev, + .platform_data = &h1940_bat_cfg, + }, +}; + +DEFINE_SPINLOCK(h1940_blink_spin); + +int h1940_led_blink_set(unsigned gpio, int state, + unsigned long *delay_on, unsigned long *delay_off) +{ + int blink_gpio, check_gpio1, check_gpio2; + + switch (gpio) { + case H1940_LATCH_LED_GREEN: + blink_gpio = S3C2410_GPA(7); + check_gpio1 = S3C2410_GPA(1); + check_gpio2 = S3C2410_GPA(3); + break; + case H1940_LATCH_LED_RED: + blink_gpio = S3C2410_GPA(1); + check_gpio1 = S3C2410_GPA(7); + check_gpio2 = S3C2410_GPA(3); + break; + default: + blink_gpio = S3C2410_GPA(3); + check_gpio1 = S3C2410_GPA(1); + check_gpio1 = S3C2410_GPA(7); + break; + } + + if (delay_on && delay_off && !*delay_on && !*delay_off) + *delay_on = *delay_off = 500; + + spin_lock(&h1940_blink_spin); + + switch (state) { + case GPIO_LED_NO_BLINK_LOW: + case GPIO_LED_NO_BLINK_HIGH: + if (!gpio_get_value(check_gpio1) && + !gpio_get_value(check_gpio2)) + gpio_set_value(H1940_LATCH_LED_FLASH, 0); + gpio_set_value(blink_gpio, 0); + if (gpio_is_valid(gpio)) + gpio_set_value(gpio, state); + break; + case GPIO_LED_BLINK: + if (gpio_is_valid(gpio)) + gpio_set_value(gpio, 0); + gpio_set_value(H1940_LATCH_LED_FLASH, 1); + gpio_set_value(blink_gpio, 1); + break; + } + + spin_unlock(&h1940_blink_spin); + + return 0; +} +EXPORT_SYMBOL(h1940_led_blink_set); + +static struct gpio_led h1940_leds_desc[] = { + { + .name = "Green", + .default_trigger = "main-battery-full", + .gpio = H1940_LATCH_LED_GREEN, + .retain_state_suspended = 1, + }, + { + .name = "Red", + .default_trigger + = "main-battery-charging-blink-full-solid", + .gpio = H1940_LATCH_LED_RED, + .retain_state_suspended = 1, + }, +}; + +static struct gpio_led_platform_data h1940_leds_pdata = { + .num_leds = ARRAY_SIZE(h1940_leds_desc), + .leds = h1940_leds_desc, + .gpio_blink_set = h1940_led_blink_set, +}; + +static struct platform_device h1940_device_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &h1940_leds_pdata, + }, }; static struct platform_device h1940_device_bluetooth = { @@ -302,14 +528,14 @@ static struct platform_device h1940_backlight = { static void h1940_lcd_power_set(struct plat_lcd_data *pd, unsigned int power) { - int value; + int value, retries = 100; if (!power) { gpio_set_value(S3C2410_GPC(0), 0); /* wait for 3ac */ do { value = gpio_get_value(S3C2410_GPC(6)); - } while (value); + } while (value && retries--); gpio_set_value(H1940_LATCH_LCD_P2, 0); gpio_set_value(H1940_LATCH_LCD_P3, 0); @@ -327,6 +553,9 @@ static void h1940_lcd_power_set(struct plat_lcd_data *pd, gpio_set_value(H1940_LATCH_LCD_P0, 1); gpio_set_value(H1940_LATCH_LCD_P1, 1); + gpio_direction_input(S3C2410_GPC(1)); + gpio_direction_input(S3C2410_GPC(4)); + mdelay(10); s3c_gpio_cfgpin(S3C2410_GPC(1), S3C_GPIO_SFN(2)); s3c_gpio_cfgpin(S3C2410_GPC(4), S3C_GPIO_SFN(2)); @@ -362,7 +591,44 @@ static struct i2c_board_info h1940_i2c_devices[] = { }, }; +#define DECLARE_BUTTON(p, k, n, w) \ + { \ + .gpio = p, \ + .code = k, \ + .desc = n, \ + .wakeup = w, \ + .active_low = 1, \ + } + +static struct gpio_keys_button h1940_buttons[] = { + DECLARE_BUTTON(S3C2410_GPF(0), KEY_POWER, "Power", 1), + DECLARE_BUTTON(S3C2410_GPF(6), KEY_ENTER, "Select", 1), + DECLARE_BUTTON(S3C2410_GPF(7), KEY_RECORD, "Record", 0), + DECLARE_BUTTON(S3C2410_GPG(0), KEY_F11, "Calendar", 0), + DECLARE_BUTTON(S3C2410_GPG(2), KEY_F12, "Contacts", 0), + DECLARE_BUTTON(S3C2410_GPG(3), KEY_MAIL, "Mail", 0), + DECLARE_BUTTON(S3C2410_GPG(6), KEY_LEFT, "Left_arrow", 0), + DECLARE_BUTTON(S3C2410_GPG(7), KEY_HOMEPAGE, "Home", 0), + DECLARE_BUTTON(S3C2410_GPG(8), KEY_RIGHT, "Right_arrow", 0), + DECLARE_BUTTON(S3C2410_GPG(9), KEY_UP, "Up_arrow", 0), + DECLARE_BUTTON(S3C2410_GPG(10), KEY_DOWN, "Down_arrow", 0), +}; + +static struct gpio_keys_platform_data h1940_buttons_data = { + .buttons = h1940_buttons, + .nbuttons = ARRAY_SIZE(h1940_buttons), +}; + +static struct platform_device h1940_dev_buttons = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &h1940_buttons_data, + } +}; + static struct platform_device *h1940_devices[] __initdata = { + &h1940_dev_buttons, &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, @@ -379,6 +645,8 @@ static struct platform_device *h1940_devices[] __initdata = { &h1940_lcd_powerdev, &s3c_device_adc, &s3c_device_ts, + &power_supply, + &h1940_battery, }; static void __init h1940_map_io(void) @@ -461,6 +729,15 @@ static void __init h1940_init(void) platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices)); + gpio_request(S3C2410_GPA(1), "Red LED blink"); + gpio_request(S3C2410_GPA(3), "Blue LED blink"); + gpio_request(S3C2410_GPA(7), "Green LED blink"); + gpio_request(H1940_LATCH_LED_FLASH, "LED blink"); + gpio_direction_output(S3C2410_GPA(1), 0); + gpio_direction_output(S3C2410_GPA(3), 0); + gpio_direction_output(S3C2410_GPA(7), 0); + gpio_direction_output(H1940_LATCH_LED_FLASH, 0); + i2c_register_board_info(0, h1940_i2c_devices, ARRAY_SIZE(h1940_i2c_devices)); } diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c index 66f44440d5d..079dcaa602d 100644 --- a/arch/arm/mach-s3c2410/mach-n30.c +++ b/arch/arm/mach-s3c2410/mach-n30.c @@ -252,7 +252,7 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = { .def_trigger = "", }; -/* This is the blue LED on the device. Originaly used to indicate GPS activity +/* This is the blue LED on the device. Originally used to indicate GPS activity * by flashing. */ static struct s3c24xx_led_platdata n35_blue_led_pdata = { .name = "blue_led", diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c index eddb52ba5b6..f3355d2ec63 100644 --- a/arch/arm/mach-s3c2412/irq.c +++ b/arch/arm/mach-s3c2412/irq.c @@ -175,18 +175,18 @@ static int s3c2412_irq_add(struct sys_device *sysdev) unsigned int irqno; for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { - set_irq_chip(irqno, &s3c2412_irq_eint0t4); - set_irq_handler(irqno, handle_edge_irq); + irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4, + handle_edge_irq); set_irq_flags(irqno, IRQF_VALID); } /* add demux support for CF/SDI */ - set_irq_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi); + irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi); for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) { - set_irq_chip(irqno, &s3c2412_irq_cfsdi); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } @@ -195,7 +195,7 @@ static int s3c2412_irq_add(struct sys_device *sysdev) s3c2412_irq_rtc_chip = s3c_irq_chip; s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake; - set_irq_chip(IRQ_RTC, &s3c2412_irq_rtc_chip); + irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip); return 0; } diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c index 680fe386aca..77b38f2381c 100644 --- a/arch/arm/mach-s3c2416/irq.c +++ b/arch/arm/mach-s3c2416/irq.c @@ -202,13 +202,11 @@ static int __init s3c2416_add_sub(unsigned int base, { unsigned int irqno; - set_irq_chip(base, &s3c_irq_level_chip); - set_irq_handler(base, handle_level_irq); - set_irq_chained_handler(base, demux); + irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq); + irq_set_chained_handler(base, demux); for (irqno = start; irqno <= end; irqno++) { - set_irq_chip(irqno, chip); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, chip, handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c index acad4428bef..eb1cc0f0705 100644 --- a/arch/arm/mach-s3c2440/irq.c +++ b/arch/arm/mach-s3c2440/irq.c @@ -100,13 +100,13 @@ static int s3c2440_irq_add(struct sys_device *sysdev) /* add new chained handler for wdt, ac7 */ - set_irq_chip(IRQ_WDT, &s3c_irq_level_chip); - set_irq_handler(IRQ_WDT, handle_level_irq); - set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); + irq_set_chip_and_handler(IRQ_WDT, &s3c_irq_level_chip, + handle_level_irq); + irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { - set_irq_chip(irqno, &s3c_irq_wdtac97); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_wdtac97, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c index 0db2411ef4b..716662008ce 100644 --- a/arch/arm/mach-s3c2440/mach-gta02.c +++ b/arch/arm/mach-s3c2440/mach-gta02.c @@ -409,6 +409,10 @@ struct platform_device s3c24xx_pwm_device = { .num_resources = 0, }; +static struct platform_device gta02_dfbmcs320_device = { + .name = "dfbmcs320", +}; + static struct i2c_board_info gta02_i2c_devs[] __initdata = { { I2C_BOARD_INFO("pcf50633", 0x73), @@ -523,6 +527,7 @@ static struct platform_device *gta02_devices[] __initdata = { &s3c_device_iis, &samsung_asoc_dma, &s3c_device_i2c0, + >a02_dfbmcs320_device, >a02_buttons_device, &s3c_device_adc, &s3c_device_ts, diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c index d80f129bca9..dd3120df09f 100644 --- a/arch/arm/mach-s3c2440/mach-mini2440.c +++ b/arch/arm/mach-s3c2440/mach-mini2440.c @@ -155,7 +155,7 @@ static struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = { * the same timings, however, anything smaller than 1024x768 * will only be displayed in the top left corner of a 1024x768 * XGA output unless you add optional dip switches to the shield. - * Therefore timings for other resolutions have been ommited here. + * Therefore timings for other resolutions have been omitted here. */ [2] = { _LCD_DECLARE( @@ -488,6 +488,11 @@ static struct i2c_board_info mini2440_i2c_devs[] __initdata = { }, }; +static struct platform_device uda1340_codec = { + .name = "uda134x-codec", + .id = -1, +}; + static struct platform_device *mini2440_devices[] __initdata = { &s3c_device_ohci, &s3c_device_wdt, @@ -503,7 +508,9 @@ static struct platform_device *mini2440_devices[] __initdata = { &s3c_device_nand, &s3c_device_sdi, &s3c_device_iis, + &uda1340_codec, &mini2440_audio, + &samsung_asoc_dma, }; static void __init mini2440_map_io(void) diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c index 86bbc233b31..27ea95096fe 100644 --- a/arch/arm/mach-s3c2440/mach-rx1950.c +++ b/arch/arm/mach-s3c2440/mach-rx1950.c @@ -263,27 +263,78 @@ void rx1950_disable_charger(void) gpio_direction_output(S3C2410_GPJ(3), 0); } +DEFINE_SPINLOCK(rx1950_blink_spin); + +static int rx1950_led_blink_set(unsigned gpio, int state, + unsigned long *delay_on, unsigned long *delay_off) +{ + int blink_gpio, check_gpio; + + switch (gpio) { + case S3C2410_GPA(6): + blink_gpio = S3C2410_GPA(4); + check_gpio = S3C2410_GPA(3); + break; + case S3C2410_GPA(7): + blink_gpio = S3C2410_GPA(3); + check_gpio = S3C2410_GPA(4); + break; + default: + return -EINVAL; + break; + } + + if (delay_on && delay_off && !*delay_on && !*delay_off) + *delay_on = *delay_off = 500; + + spin_lock(&rx1950_blink_spin); + + switch (state) { + case GPIO_LED_NO_BLINK_LOW: + case GPIO_LED_NO_BLINK_HIGH: + if (!gpio_get_value(check_gpio)) + gpio_set_value(S3C2410_GPJ(6), 0); + gpio_set_value(blink_gpio, 0); + gpio_set_value(gpio, state); + break; + case GPIO_LED_BLINK: + gpio_set_value(gpio, 0); + gpio_set_value(S3C2410_GPJ(6), 1); + gpio_set_value(blink_gpio, 1); + break; + } + + spin_unlock(&rx1950_blink_spin); + + return 0; +} + static struct gpio_led rx1950_leds_desc[] = { { - .name = "Green", - .default_trigger = "main-battery-charging-or-full", - .gpio = S3C2410_GPA(6), + .name = "Green", + .default_trigger = "main-battery-full", + .gpio = S3C2410_GPA(6), + .retain_state_suspended = 1, }, { - .name = "Red", - .default_trigger = "main-battery-full", - .gpio = S3C2410_GPA(7), + .name = "Red", + .default_trigger + = "main-battery-charging-blink-full-solid", + .gpio = S3C2410_GPA(7), + .retain_state_suspended = 1, }, { - .name = "Blue", + .name = "Blue", .default_trigger = "rx1950-acx-mem", - .gpio = S3C2410_GPA(11), + .gpio = S3C2410_GPA(11), + .retain_state_suspended = 1, }, }; static struct gpio_led_platform_data rx1950_leds_pdata = { .num_leds = ARRAY_SIZE(rx1950_leds_desc), .leds = rx1950_leds_desc, + .gpio_blink_set = rx1950_led_blink_set, }; static struct platform_device rx1950_leds = { @@ -752,6 +803,13 @@ static void __init rx1950_init_machine(void) WARN_ON(gpio_request(S3C2410_GPB(1), "LCD power")); + WARN_ON(gpio_request(S3C2410_GPA(3), "Red blink")); + WARN_ON(gpio_request(S3C2410_GPA(4), "Green blink")); + WARN_ON(gpio_request(S3C2410_GPJ(6), "LED blink")); + gpio_direction_output(S3C2410_GPA(3), 0); + gpio_direction_output(S3C2410_GPA(4), 0); + gpio_direction_output(S3C2410_GPJ(6), 0); + platform_add_devices(rx1950_devices, ARRAY_SIZE(rx1950_devices)); i2c_register_board_info(0, rx1950_i2c_devices, diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c index 83daf4ece76..de07c2feaa3 100644 --- a/arch/arm/mach-s3c2440/s3c244x-irq.c +++ b/arch/arm/mach-s3c2440/s3c244x-irq.c @@ -95,19 +95,19 @@ static int s3c244x_irq_add(struct sys_device *sysdev) { unsigned int irqno; - set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip); - set_irq_handler(IRQ_NFCON, handle_level_irq); + irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip, + handle_level_irq); set_irq_flags(IRQ_NFCON, IRQF_VALID); /* add chained handler for camera */ - set_irq_chip(IRQ_CAM, &s3c_irq_level_chip); - set_irq_handler(IRQ_CAM, handle_level_irq); - set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam); + irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip, + handle_level_irq); + irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam); for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { - set_irq_chip(irqno, &s3c_irq_cam); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_cam, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c index c7820f9c135..83ecb1173fb 100644 --- a/arch/arm/mach-s3c2443/irq.c +++ b/arch/arm/mach-s3c2443/irq.c @@ -230,13 +230,11 @@ static int __init s3c2443_add_sub(unsigned int base, { unsigned int irqno; - set_irq_chip(base, &s3c_irq_level_chip); - set_irq_handler(base, handle_level_irq); - set_irq_chained_handler(base, demux); + irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq); + irq_set_chained_handler(base, demux); for (irqno = start; irqno <= end; irqno++) { - set_irq_chip(irqno, chip); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, chip, handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c index c35585cf8c4..b197171e7d0 100644 --- a/arch/arm/mach-s3c64xx/dma.c +++ b/arch/arm/mach-s3c64xx/dma.c @@ -315,7 +315,7 @@ int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op) case S3C2410_DMAOP_FLUSH: return s3c64xx_dma_flush(chan); - /* belive PAUSE/RESUME are no-ops */ + /* believe PAUSE/RESUME are no-ops */ case S3C2410_DMAOP_PAUSE: case S3C2410_DMAOP_RESUME: case S3C2410_DMAOP_STARTED: diff --git a/arch/arm/mach-s3c64xx/irq-eint.c b/arch/arm/mach-s3c64xx/irq-eint.c index 2ead8189da7..4d203be1f4c 100644 --- a/arch/arm/mach-s3c64xx/irq-eint.c +++ b/arch/arm/mach-s3c64xx/irq-eint.c @@ -197,16 +197,15 @@ static int __init s3c64xx_init_irq_eint(void) int irq; for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { - set_irq_chip(irq, &s3c_irq_eint); - set_irq_chip_data(irq, (void *)eint_irq_to_bit(irq)); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq); + irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq)); set_irq_flags(irq, IRQF_VALID); } - set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); - set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11); - set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19); - set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27); + irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); + irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11); + irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19); + irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27); return 0; } diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c index b8d02eb4cf3..a5c00952ea3 100644 --- a/arch/arm/mach-s5p64x0/cpu.c +++ b/arch/arm/mach-s5p64x0/cpu.c @@ -119,7 +119,7 @@ void __init s5p6450_map_io(void) s3c_adc_setname("s3c64xx-adc"); iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc)); - iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6440_iodesc)); + iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc)); } /* diff --git a/arch/arm/mach-s5pc100/include/mach/regs-fb.h b/arch/arm/mach-s5pc100/include/mach/regs-fb.h index 4be4cc9abf7..07aa4d6054f 100644 --- a/arch/arm/mach-s5pc100/include/mach/regs-fb.h +++ b/arch/arm/mach-s5pc100/include/mach/regs-fb.h @@ -29,7 +29,7 @@ #define WPALCON_H (0x19c) #define WPALCON_L (0x1a0) -/* Pallete contro for WPAL0 and WPAL1 is the same as in S3C64xx, but +/* Palette control for WPAL0 and WPAL1 is the same as in S3C64xx, but * different for WPAL2-4 */ /* In WPALCON_L (aka WPALCON) */ diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c index f16946e456e..be25879bb2e 100644 --- a/arch/arm/mach-s5pc100/setup-sdhci.c +++ b/arch/arm/mach-s5pc100/setup-sdhci.c @@ -40,7 +40,7 @@ void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev, { u32 ctrl2, ctrl3; - /* don't need to alter anything acording to card-type */ + /* don't need to alter anything according to card-type */ writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio.h index 1f4b595534c..a5a1e331f8e 100644 --- a/arch/arm/mach-s5pv210/include/mach/gpio.h +++ b/arch/arm/mach-s5pv210/include/mach/gpio.h @@ -18,7 +18,7 @@ #define gpio_cansleep __gpio_cansleep #define gpio_to_irq __gpio_to_irq -/* Practically, GPIO banks upto MP03 are the configurable gpio banks */ +/* Practically, GPIO banks up to MP03 are the configurable gpio banks */ /* GPIO bank sizes */ #define S5PV210_GPIO_A0_NR (8) diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h index 26710b35ef8..b9f9ec33384 100644 --- a/arch/arm/mach-s5pv210/include/mach/irqs.h +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h @@ -99,9 +99,9 @@ #define IRQ_TC IRQ_PENDN #define IRQ_KEYPAD S5P_IRQ_VIC2(25) #define IRQ_CG S5P_IRQ_VIC2(26) -#define IRQ_SEC S5P_IRQ_VIC2(27) -#define IRQ_SECRX S5P_IRQ_VIC2(28) -#define IRQ_SECTX S5P_IRQ_VIC2(29) +#define IRQ_SSS_INT S5P_IRQ_VIC2(27) +#define IRQ_SSS_HASH S5P_IRQ_VIC2(28) +#define IRQ_PCM2 S5P_IRQ_VIC2(29) #define IRQ_SDMIRQ S5P_IRQ_VIC2(30) #define IRQ_SDMFIQ S5P_IRQ_VIC2(31) diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c index 243291722c6..31d5aa76975 100644 --- a/arch/arm/mach-s5pv210/mach-goni.c +++ b/arch/arm/mach-s5pv210/mach-goni.c @@ -15,7 +15,7 @@ #include <linux/fb.h> #include <linux/i2c.h> #include <linux/i2c-gpio.h> -#include <linux/i2c/qt602240_ts.h> +#include <linux/i2c/atmel_mxt_ts.h> #include <linux/mfd/max8998.h> #include <linux/mfd/wm8994/pdata.h> #include <linux/regulator/fixed.h> @@ -25,6 +25,7 @@ #include <linux/gpio_keys.h> #include <linux/input.h> #include <linux/gpio.h> +#include <linux/interrupt.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -225,7 +226,7 @@ static void __init goni_radio_init(void) } /* TSP */ -static struct qt602240_platform_data qt602240_platform_data = { +static struct mxt_platform_data qt602240_platform_data = { .x_line = 17, .y_line = 11, .x_size = 800, @@ -233,7 +234,8 @@ static struct qt602240_platform_data qt602240_platform_data = { .blen = 0x21, .threshold = 0x28, .voltage = 2800000, /* 2.8V */ - .orient = QT602240_DIAGONAL, + .orient = MXT_DIAGONAL, + .irqflags = IRQF_TRIGGER_FALLING, }; static struct s3c2410_platform_i2c i2c2_data __initdata = { diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index bc08ac42e7c..c6a9e86c2d5 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -44,7 +44,6 @@ #include <plat/keypad.h> #include <plat/pm.h> #include <plat/fb.h> -#include <plat/gpio-cfg.h> #include <plat/s5p-time.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c index 746777d56df..3e3ac05bb7b 100644 --- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c +++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c @@ -32,10 +32,10 @@ void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) switch (width) { case 8: - /* GPG1[3:6] special-funtion 3 */ + /* GPG1[3:6] special-function 3 */ s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(3)); case 4: - /* GPG0[3:6] special-funtion 2 */ + /* GPG0[3:6] special-function 2 */ s3c_gpio_cfgrange_nopull(S5PV210_GPG0(3), 4, S3C_GPIO_SFN(2)); default: break; diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c index c32e202731c..a83b6c909f6 100644 --- a/arch/arm/mach-s5pv210/setup-sdhci.c +++ b/arch/arm/mach-s5pv210/setup-sdhci.c @@ -38,7 +38,7 @@ void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev, { u32 ctrl2, ctrl3; - /* don't need to alter anything acording to card-type */ + /* don't need to alter anything according to card-type */ writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile index e697691eed2..41252d22e65 100644 --- a/arch/arm/mach-sa1100/Makefile +++ b/arch/arm/mach-sa1100/Makefile @@ -50,7 +50,7 @@ led-$(CONFIG_SA1100_SIMPAD) += leds-simpad.o # LEDs support obj-$(CONFIG_LEDS) += $(led-y) -# Miscelaneous functions +# Miscellaneous functions obj-$(CONFIG_PM) += pm.o sleep.o obj-$(CONFIG_SA1100_SSP) += ssp.o diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c index 98d780608c7..7f3da4b11ec 100644 --- a/arch/arm/mach-sa1100/cerf.c +++ b/arch/arm/mach-sa1100/cerf.c @@ -96,7 +96,7 @@ static struct resource cerf_flash_resource = { static void __init cerf_init_irq(void) { sa1100_init_irq(); - set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING); } static struct map_desc cerf_io_desc[] __initdata = { diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c index 07d4e8ba371..aaa8acf76b7 100644 --- a/arch/arm/mach-sa1100/cpu-sa1100.c +++ b/arch/arm/mach-sa1100/cpu-sa1100.c @@ -68,7 +68,7 @@ * clock change in ROM and jump to that code from the kernel. The main * disadvantage is that the ROM has to be modified, which is not * possible on all SA-1100 platforms. Another disadvantage is that - * jumping to ROM makes clock switching unecessary complicated. + * jumping to ROM makes clock switching unnecessary complicated. * * The idea behind this driver is that the memory configuration can be * changed while running from DRAM (even with interrupts turned on!) diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h index 4f7ea012e1e..bae8296f5db 100644 --- a/arch/arm/mach-sa1100/include/mach/SA-1100.h +++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h @@ -1794,7 +1794,7 @@ (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR))) -#define DCSR_RUN 0x00000001 /* DMA RUNing */ +#define DCSR_RUN 0x00000001 /* DMA running */ #define DCSR_IE 0x00000002 /* DMA Interrupt Enable */ #define DCSR_ERROR 0x00000004 /* DMA ERROR */ #define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */ diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index 3d85dfad9c1..423ddb3d65e 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c @@ -323,28 +323,28 @@ void __init sa1100_init_irq(void) ICCR = 1; for (irq = 0; irq <= 10; irq++) { - set_irq_chip(irq, &sa1100_low_gpio_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } for (irq = 12; irq <= 31; irq++) { - set_irq_chip(irq, &sa1100_normal_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &sa1100_normal_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } for (irq = 32; irq <= 48; irq++) { - set_irq_chip(irq, &sa1100_high_gpio_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } /* * Install handler for GPIO 11-27 edge detect interrupts */ - set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip); - set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); + irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip); + irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); sa1100_init_gpio(); } diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c index 9d490c66891..f50b00bd18a 100644 --- a/arch/arm/mach-sa1100/jornada720_ssp.c +++ b/arch/arm/mach-sa1100/jornada720_ssp.c @@ -29,7 +29,7 @@ static unsigned long jornada_ssp_flags; /** * jornada_ssp_reverse - reverses input byte * - * we need to reverse all data we recieve from the mcu due to its physical location + * we need to reverse all data we receive from the mcu due to its physical location * returns : 01110111 -> 11101110 */ u8 inline jornada_ssp_reverse(u8 byte) @@ -179,7 +179,7 @@ static int __devinit jornada_ssp_probe(struct platform_device *dev) static int jornada_ssp_remove(struct platform_device *dev) { - /* Note that this doesnt actually remove the driver, since theres nothing to remove + /* Note that this doesn't actually remove the driver, since theres nothing to remove * It just makes sure everything is turned off */ GPSR = GPIO_GPIO25; ssp_exit(); diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index 4aad01f7366..b4fa53a1427 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c @@ -145,8 +145,8 @@ static int __devinit neponset_probe(struct platform_device *dev) /* * Install handler for GPIO25. */ - set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING); - set_irq_chained_handler(IRQ_GPIO25, neponset_irq_handler); + irq_set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING); + irq_set_chained_handler(IRQ_GPIO25, neponset_irq_handler); /* * We would set IRQ_GPIO25 to be a wake-up IRQ, but @@ -161,9 +161,9 @@ static int __devinit neponset_probe(struct platform_device *dev) * Setup other Neponset IRQs. SA1111 will be done by the * generic SA1111 code. */ - set_irq_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq); + irq_set_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq); set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE); - set_irq_handler(IRQ_NEPONSET_USAR, handle_simple_irq); + irq_set_handler(IRQ_NEPONSET_USAR, handle_simple_irq); set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE); /* diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c index 42b80400c10..65161f2bea2 100644 --- a/arch/arm/mach-sa1100/pleb.c +++ b/arch/arm/mach-sa1100/pleb.c @@ -142,7 +142,7 @@ static void __init pleb_map_io(void) GPDR &= ~GPIO_ETH0_IRQ; - set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING); + irq_set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING); } MACHINE_START(PLEB, "PLEB") diff --git a/arch/arm/mach-shark/irq.c b/arch/arm/mach-shark/irq.c index 831fc66dfa4..5dce13e429f 100644 --- a/arch/arm/mach-shark/irq.c +++ b/arch/arm/mach-shark/irq.c @@ -80,8 +80,7 @@ void __init shark_init_irq(void) int irq; for (irq = 0; irq < NR_IRQS; irq++) { - set_irq_chip(irq, &fb_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &fb_chip, handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 1a8118c929b..1e35fa976d6 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -24,9 +24,9 @@ #include <linux/irq.h> #include <linux/platform_device.h> #include <linux/delay.h> -#include <linux/mfd/sh_mobile_sdhi.h> #include <linux/mfd/tmio.h> #include <linux/mmc/host.h> +#include <linux/mmc/sh_mobile_sdhi.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> @@ -312,7 +312,7 @@ static struct resource sdhi0_resources[] = { [0] = { .name = "SDHI0", .start = 0xe6850000, - .end = 0xe68501ff, + .end = 0xe68500ff, .flags = IORESOURCE_MEM, }, [1] = { @@ -345,7 +345,7 @@ static struct resource sdhi1_resources[] = { [0] = { .name = "SDHI1", .start = 0xe6860000, - .end = 0xe68601ff, + .end = 0xe68600ff, .flags = IORESOURCE_MEM, }, [1] = { @@ -923,7 +923,8 @@ static struct platform_device ceu_device = { .num_resources = ARRAY_SIZE(ceu_resources), .resource = ceu_resources, .dev = { - .platform_data = &sh_mobile_ceu_info, + .platform_data = &sh_mobile_ceu_info, + .coherent_dma_mask = 0xffffffff, }, }; @@ -946,7 +947,7 @@ static struct platform_device *ap4evb_devices[] __initdata = { &ap4evb_camera, }; -static int __init hdmi_init_pm_clock(void) +static void __init hdmi_init_pm_clock(void) { struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick"); int ret; @@ -987,20 +988,15 @@ static int __init hdmi_init_pm_clock(void) pr_debug("PLLC2 set frequency %lu\n", rate); ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk); - if (ret < 0) { + if (ret < 0) pr_err("Cannot set HDMI parent: %d\n", ret); - goto out; - } out: if (!IS_ERR(hdmi_ick)) clk_put(hdmi_ick); - return ret; } -device_initcall(hdmi_init_pm_clock); - -static int __init fsi_init_pm_clock(void) +static void __init fsi_init_pm_clock(void) { struct clk *fsia_ick; int ret; @@ -1009,7 +1005,7 @@ static int __init fsi_init_pm_clock(void) if (IS_ERR(fsia_ick)) { ret = PTR_ERR(fsia_ick); pr_err("Cannot get FSI ICK: %d\n", ret); - return ret; + return; } ret = clk_set_parent(fsia_ick, &sh7372_fsiack_clk); @@ -1017,10 +1013,7 @@ static int __init fsi_init_pm_clock(void) pr_err("Cannot set FSI-A parent: %d\n", ret); clk_put(fsia_ick); - - return ret; } -device_initcall(fsi_init_pm_clock); /* * FIXME !! @@ -1254,7 +1247,7 @@ static void __init ap4evb_init(void) gpio_request(GPIO_FN_KEYIN4, NULL); /* enable TouchScreen */ - set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW); tsc_device.irq = IRQ28; i2c_register_board_info(1, &tsc_device, 1); @@ -1310,7 +1303,7 @@ static void __init ap4evb_init(void) lcdc_info.ch[0].lcd_size_cfg.height = 91; /* enable TouchScreen */ - set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); tsc_device.irq = IRQ7; i2c_register_board_info(0, &tsc_device, 1); @@ -1347,6 +1340,9 @@ static void __init ap4evb_init(void) __raw_writel(srcr4 & ~(1 << 13), SRCR4); platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); + + hdmi_init_pm_clock(); + fsi_init_pm_clock(); } static void __init ap4evb_timer_init(void) diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c index dee3e9231fb..c87a7b7c583 100644 --- a/arch/arm/mach-shmobile/board-g4evm.c +++ b/arch/arm/mach-shmobile/board-g4evm.c @@ -31,7 +31,7 @@ #include <linux/input.h> #include <linux/input/sh_keysc.h> #include <linux/mmc/host.h> -#include <linux/mfd/sh_mobile_sdhi.h> +#include <linux/mmc/sh_mobile_sdhi.h> #include <linux/gpio.h> #include <mach/sh7377.h> #include <mach/common.h> @@ -205,7 +205,7 @@ static struct resource sdhi0_resources[] = { [0] = { .name = "SDHI0", .start = 0xe6d50000, - .end = 0xe6d501ff, + .end = 0xe6d50nff, .flags = IORESOURCE_MEM, }, [1] = { @@ -232,7 +232,7 @@ static struct resource sdhi1_resources[] = { [0] = { .name = "SDHI1", .start = 0xe6d60000, - .end = 0xe6d601ff, + .end = 0xe6d600ff, .flags = IORESOURCE_MEM, }, [1] = { diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index 1a63c213e45..7da2ca24229 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -32,10 +32,10 @@ #include <linux/io.h> #include <linux/i2c.h> #include <linux/leds.h> -#include <linux/mfd/sh_mobile_sdhi.h> #include <linux/mfd/tmio.h> #include <linux/mmc/host.h> #include <linux/mmc/sh_mmcif.h> +#include <linux/mmc/sh_mobile_sdhi.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> @@ -295,6 +295,18 @@ static struct fb_videomode mackerel_lcdc_modes[] = { }, }; +static int mackerel_set_brightness(void *board_data, int brightness) +{ + gpio_set_value(GPIO_PORT31, brightness); + + return 0; +} + +static int mackerel_get_brightness(void *board_data) +{ + return gpio_get_value(GPIO_PORT31); +} + static struct sh_mobile_lcdc_info lcdc_info = { .clock_source = LCDC_CLK_BUS, .ch[0] = { @@ -307,6 +319,14 @@ static struct sh_mobile_lcdc_info lcdc_info = { .flags = 0, .lcd_size_cfg.width = 152, .lcd_size_cfg.height = 91, + .board_cfg = { + .set_brightness = mackerel_set_brightness, + .get_brightness = mackerel_get_brightness, + }, + .bl_info = { + .name = "sh_mobile_lcdc_bl", + .max_brightness = 1, + }, } }; @@ -403,7 +423,7 @@ static struct platform_device fsi_hdmi_device = { .name = "sh_fsi2_b_hdmi", }; -static int __init hdmi_init_pm_clock(void) +static void __init hdmi_init_pm_clock(void) { struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick"); int ret; @@ -447,17 +467,13 @@ static int __init hdmi_init_pm_clock(void) pr_debug("PLLC2 set frequency %lu\n", rate); ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk); - if (ret < 0) { + if (ret < 0) pr_err("Cannot set HDMI parent: %d\n", ret); - goto out; - } out: if (!IS_ERR(hdmi_ick)) clk_put(hdmi_ick); - return ret; } -device_initcall(hdmi_init_pm_clock); /* USB1 (Host) */ static void usb1_host_port_power(int port, int power) @@ -670,7 +686,7 @@ static struct resource sdhi0_resources[] = { [0] = { .name = "SDHI0", .start = 0xe6850000, - .end = 0xe68501ff, + .end = 0xe68500ff, .flags = IORESOURCE_MEM, }, [1] = { @@ -705,7 +721,7 @@ static struct resource sdhi1_resources[] = { [0] = { .name = "SDHI1", .start = 0xe6860000, - .end = 0xe68601ff, + .end = 0xe68600ff, .flags = IORESOURCE_MEM, }, [1] = { @@ -748,7 +764,7 @@ static struct resource sdhi2_resources[] = { [0] = { .name = "SDHI2", .start = 0xe6870000, - .end = 0xe68701ff, + .end = 0xe68700ff, .flags = IORESOURCE_MEM, }, [1] = { @@ -901,7 +917,8 @@ static struct platform_device ceu_device = { .num_resources = ARRAY_SIZE(ceu_resources), .resource = ceu_resources, .dev = { - .platform_data = &sh_mobile_ceu_info, + .platform_data = &sh_mobile_ceu_info, + .coherent_dma_mask = 0xffffffff, }, }; @@ -1059,7 +1076,7 @@ static void __init mackerel_init(void) gpio_request(GPIO_FN_LCDDCK, NULL); gpio_request(GPIO_PORT31, NULL); /* backlight */ - gpio_direction_output(GPIO_PORT31, 1); + gpio_direction_output(GPIO_PORT31, 0); /* off by default */ gpio_request(GPIO_PORT151, NULL); /* LCDDON */ gpio_direction_output(GPIO_PORT151, 1); @@ -1103,15 +1120,15 @@ static void __init mackerel_init(void) /* enable Keypad */ gpio_request(GPIO_FN_IRQ9_42, NULL); - set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH); + irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH); /* enable Touchscreen */ gpio_request(GPIO_FN_IRQ7_40, NULL); - set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); /* enable Accelerometer */ gpio_request(GPIO_FN_IRQ21, NULL); - set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); + irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); /* enable SDHI0 */ gpio_request(GPIO_FN_SDHICD0, NULL); @@ -1197,6 +1214,8 @@ static void __init mackerel_init(void) sh7372_add_standard_devices(); platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices)); + + hdmi_init_pm_clock(); } static void __init mackerel_timer_init(void) diff --git a/arch/arm/mach-shmobile/include/mach/mmcif-ap4eb.h b/arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h index a8d02be8d2b..db59fdbda86 100644 --- a/arch/arm/mach-shmobile/include/mach/mmcif-ap4eb.h +++ b/arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h @@ -1,5 +1,5 @@ -#ifndef MMCIF_AP4EB_H -#define MMCIF_AP4EB_H +#ifndef MMC_AP4EB_H +#define MMC_AP4EB_H #define PORT185CR (void __iomem *)0xe60520b9 #define PORT186CR (void __iomem *)0xe60520ba @@ -8,7 +8,7 @@ #define PORTR191_160DR (void __iomem *)0xe6056014 -static inline void mmcif_init_progress(void) +static inline void mmc_init_progress(void) { /* Initialise LEDS1-4 * registers: PORT185CR-PORT188CR (LED1-LED4 Control) @@ -20,10 +20,10 @@ static inline void mmcif_init_progress(void) __raw_writeb(0x10, PORT188CR); } -static inline void mmcif_update_progress(int n) +static inline void mmc_update_progress(int n) { __raw_writel((__raw_readl(PORTR191_160DR) & ~(0xf << 25)) | (1 << (25 + n)), PORTR191_160DR); } -#endif /* MMCIF_AP4EB_H */ +#endif /* MMC_AP4EB_H */ diff --git a/arch/arm/mach-shmobile/include/mach/mmcif-mackerel.h b/arch/arm/mach-shmobile/include/mach/mmc-mackerel.h index 4b4f6949a86..15d3a9efdec 100644 --- a/arch/arm/mach-shmobile/include/mach/mmcif-mackerel.h +++ b/arch/arm/mach-shmobile/include/mach/mmc-mackerel.h @@ -1,5 +1,5 @@ -#ifndef MMCIF_MACKEREL_H -#define MMCIF_MACKEREL_H +#ifndef MMC_MACKEREL_H +#define MMC_MACKEREL_H #define PORT0CR (void __iomem *)0xe6051000 #define PORT1CR (void __iomem *)0xe6051001 @@ -9,7 +9,7 @@ #define PORTR031_000DR (void __iomem *)0xe6055000 #define PORTL159_128DR (void __iomem *)0xe6054010 -static inline void mmcif_init_progress(void) +static inline void mmc_init_progress(void) { /* Initialise LEDS0-3 * registers: PORT0CR-PORT2CR,PORT159CR (LED0-LED3 Control) @@ -21,7 +21,7 @@ static inline void mmcif_init_progress(void) __raw_writeb(0x10, PORT159CR); } -static inline void mmcif_update_progress(int n) +static inline void mmc_update_progress(int n) { unsigned a = 0, b = 0; @@ -35,5 +35,4 @@ static inline void mmcif_update_progress(int n) __raw_writel((__raw_readl(PORTL159_128DR) & ~(1 << 31)) | b, PORTL159_128DR); } - -#endif /* MMCIF_MACKEREL_H */ +#endif /* MMC_MACKEREL_H */ diff --git a/arch/arm/mach-shmobile/include/mach/mmcif.h b/arch/arm/mach-shmobile/include/mach/mmc.h index f4dc3279cf0..21a59db638b 100644 --- a/arch/arm/mach-shmobile/include/mach/mmcif.h +++ b/arch/arm/mach-shmobile/include/mach/mmc.h @@ -1,5 +1,5 @@ -#ifndef MMCIF_H -#define MMCIF_H +#ifndef MMC_H +#define MMC_H /************************************************** * @@ -8,11 +8,11 @@ **************************************************/ #ifdef CONFIG_MACH_AP4EVB -#include "mach/mmcif-ap4eb.h" -#elif CONFIG_MACH_MACKEREL -#include "mach/mmcif-mackerel.h" +#include "mach/mmc-ap4eb.h" +#elif defined(CONFIG_MACH_MACKEREL) +#include "mach/mmc-mackerel.h" #else #error "unsupported board." #endif -#endif /* MMCIF_H */ +#endif /* MMC_H */ diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h index 6d6a205bcf9..9320aff0a20 100644 --- a/arch/arm/mach-shmobile/include/mach/zboot.h +++ b/arch/arm/mach-shmobile/include/mach/zboot.h @@ -13,7 +13,7 @@ #ifdef CONFIG_MACH_AP4EVB #define MACH_TYPE MACH_TYPE_AP4EVB #include "mach/head-ap4evb.txt" -#elif CONFIG_MACH_MACKEREL +#elif defined(CONFIG_MACH_MACKEREL) #define MACH_TYPE MACH_TYPE_MACKEREL #include "mach/head-mackerel.txt" #else diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c index 2fe9704d5ea..cc442d198cd 100644 --- a/arch/arm/mach-shmobile/intc-sh7367.c +++ b/arch/arm/mach-shmobile/intc-sh7367.c @@ -421,7 +421,7 @@ static struct intc_desc intcs_desc __initdata = { static void intcs_demux(unsigned int irq, struct irq_desc *desc) { - void __iomem *reg = (void *)get_irq_data(irq); + void __iomem *reg = (void *)irq_get_handler_data(irq); unsigned int evtcodeas = ioread32(reg); generic_handle_irq(intcs_evt2irq(evtcodeas)); @@ -435,6 +435,6 @@ void __init sh7367_init_irq(void) register_intc_controller(&intcs_desc); /* demux using INTEVTSA */ - set_irq_data(evt2irq(0xf80), (void *)intevtsa); - set_irq_chained_handler(evt2irq(0xf80), intcs_demux); + irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); + irq_set_chained_handler(evt2irq(0xf80), intcs_demux); } diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c index ca5f9d17b39..7a4960f9c1e 100644 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ b/arch/arm/mach-shmobile/intc-sh7372.c @@ -601,7 +601,7 @@ static struct intc_desc intcs_desc __initdata = { static void intcs_demux(unsigned int irq, struct irq_desc *desc) { - void __iomem *reg = (void *)get_irq_data(irq); + void __iomem *reg = (void *)irq_get_handler_data(irq); unsigned int evtcodeas = ioread32(reg); generic_handle_irq(intcs_evt2irq(evtcodeas)); @@ -615,6 +615,6 @@ void __init sh7372_init_irq(void) register_intc_controller(&intcs_desc); /* demux using INTEVTSA */ - set_irq_data(evt2irq(0xf80), (void *)intevtsa); - set_irq_chained_handler(evt2irq(0xf80), intcs_demux); + irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); + irq_set_chained_handler(evt2irq(0xf80), intcs_demux); } diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c index dd568382cc9..fe45154ce66 100644 --- a/arch/arm/mach-shmobile/intc-sh7377.c +++ b/arch/arm/mach-shmobile/intc-sh7377.c @@ -626,7 +626,7 @@ static struct intc_desc intcs_desc __initdata = { static void intcs_demux(unsigned int irq, struct irq_desc *desc) { - void __iomem *reg = (void *)get_irq_data(irq); + void __iomem *reg = (void *)irq_get_handler_data(irq); unsigned int evtcodeas = ioread32(reg); generic_handle_irq(intcs_evt2irq(evtcodeas)); @@ -641,6 +641,6 @@ void __init sh7377_init_irq(void) register_intc_controller(&intcs_desc); /* demux using INTEVTSA */ - set_irq_data(evt2irq(INTCS_INTVECT), (void *)intevtsa); - set_irq_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux); + irq_set_handler_data(evt2irq(INTCS_INTVECT), (void *)intevtsa); + irq_set_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux); } diff --git a/arch/arm/mach-shmobile/localtimer.c b/arch/arm/mach-shmobile/localtimer.c index 2111c28b724..ad9ccc9900c 100644 --- a/arch/arm/mach-shmobile/localtimer.c +++ b/arch/arm/mach-shmobile/localtimer.c @@ -18,8 +18,9 @@ /* * Setup the local clock events for a CPU. */ -void __cpuinit local_timer_setup(struct clock_event_device *evt) +int __cpuinit local_timer_setup(struct clock_event_device *evt) { evt->irq = 29; twd_timer_setup(evt); + return 0; } diff --git a/arch/arm/mach-tcc8k/irq.c b/arch/arm/mach-tcc8k/irq.c index aa9231f4fc6..209fa5c65d4 100644 --- a/arch/arm/mach-tcc8k/irq.c +++ b/arch/arm/mach-tcc8k/irq.c @@ -102,10 +102,10 @@ void __init tcc8k_init_irq(void) for (irqno = 0; irqno < NR_IRQS; irqno++) { if (irqno < 32) - set_irq_chip(irqno, &tcc8000_irq_chip0); + irq_set_chip(irqno, &tcc8000_irq_chip0); else - set_irq_chip(irqno, &tcc8000_irq_chip1); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip(irqno, &tcc8000_irq_chip1); + irq_set_handler(irqno, handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } } diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 622a9ec1ff0..3cdeffc97b4 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -36,6 +36,11 @@ config MACH_KAEN help Support for the Kaen version of Seaboard +config MACH_PAZ00 + bool "Paz00 board" + help + Support for the Toshiba AC100/Dynabook AZ netbook + config MACH_SEABOARD bool "Seaboard board" help diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 9f7a7e1e0c3..1afe05038c2 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -22,6 +22,10 @@ obj-$(CONFIG_USB_SUPPORT) += usb_phy.o obj-${CONFIG_MACH_HARMONY} += board-harmony.o obj-${CONFIG_MACH_HARMONY} += board-harmony-pinmux.o obj-${CONFIG_MACH_HARMONY} += board-harmony-pcie.o +obj-${CONFIG_MACH_HARMONY} += board-harmony-power.o + +obj-${CONFIG_MACH_PAZ00} += board-paz00.o +obj-${CONFIG_MACH_PAZ00} += board-paz00-pinmux.o obj-${CONFIG_MACH_SEABOARD} += board-seaboard.o obj-${CONFIG_MACH_SEABOARD} += board-seaboard-pinmux.o diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c index f7e7d4514b6..9c27b95b8d8 100644 --- a/arch/arm/mach-tegra/board-harmony-pcie.c +++ b/arch/arm/mach-tegra/board-harmony-pcie.c @@ -27,13 +27,29 @@ #ifdef CONFIG_TEGRA_PCI +/* GPIO 3 of the PMIC */ +#define EN_VDD_1V05_GPIO (TEGRA_NR_GPIOS + 2) + static int __init harmony_pcie_init(void) { + struct regulator *regulator = NULL; int err; if (!machine_is_harmony()) return 0; + err = gpio_request(EN_VDD_1V05_GPIO, "EN_VDD_1V05"); + if (err) + return err; + + gpio_direction_output(EN_VDD_1V05_GPIO, 1); + + regulator = regulator_get(NULL, "pex_clk"); + if (IS_ERR_OR_NULL(regulator)) + goto err_reg; + + regulator_enable(regulator); + tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_NORMAL); tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_NORMAL); tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_NORMAL); @@ -49,9 +65,15 @@ err_pcie: tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_TRISTATE); tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_TRISTATE); + regulator_disable(regulator); + regulator_put(regulator); +err_reg: + gpio_free(EN_VDD_1V05_GPIO); + return err; } -subsys_initcall(harmony_pcie_init); +/* PCI should be initialized after I2C, mfd and regulators */ +subsys_initcall_sync(harmony_pcie_init); #endif diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c index 98368d947be..4d63e2e97a8 100644 --- a/arch/arm/mach-tegra/board-harmony-pinmux.c +++ b/arch/arm/mach-tegra/board-harmony-pinmux.c @@ -27,11 +27,11 @@ static struct tegra_pingroup_config harmony_pinmux[] = { {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, - {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_OSC, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, - {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, @@ -114,13 +114,13 @@ static struct tegra_pingroup_config harmony_pinmux[] = { {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, - {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, - {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, - {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, - {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, @@ -141,12 +141,16 @@ static struct tegra_pingroup_config harmony_pinmux[] = { }; static struct tegra_gpio_table gpio_table[] = { - { .gpio = TEGRA_GPIO_PI5, .enable = true }, /* mmc2 cd */ - { .gpio = TEGRA_GPIO_PH1, .enable = true }, /* mmc2 wp */ - { .gpio = TEGRA_GPIO_PT3, .enable = true }, /* mmc2 pwr */ - { .gpio = TEGRA_GPIO_PH2, .enable = true }, /* mmc4 cd */ - { .gpio = TEGRA_GPIO_PH3, .enable = true }, /* mmc4 wp */ - { .gpio = TEGRA_GPIO_PI6, .enable = true }, /* mmc4 pwr */ + { .gpio = TEGRA_GPIO_SD2_CD, .enable = true }, + { .gpio = TEGRA_GPIO_SD2_WP, .enable = true }, + { .gpio = TEGRA_GPIO_SD2_POWER, .enable = true }, + { .gpio = TEGRA_GPIO_SD4_CD, .enable = true }, + { .gpio = TEGRA_GPIO_SD4_WP, .enable = true }, + { .gpio = TEGRA_GPIO_SD4_POWER, .enable = true }, + { .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true }, + { .gpio = TEGRA_GPIO_HP_DET, .enable = true }, + { .gpio = TEGRA_GPIO_INT_MIC_EN, .enable = true }, + { .gpio = TEGRA_GPIO_EXT_MIC_EN, .enable = true }, }; void harmony_pinmux_init(void) diff --git a/arch/arm/mach-tegra/board-harmony-power.c b/arch/arm/mach-tegra/board-harmony-power.c new file mode 100644 index 00000000000..c84442cabe0 --- /dev/null +++ b/arch/arm/mach-tegra/board-harmony-power.c @@ -0,0 +1,117 @@ +/* + * Copyright (C) 2010 NVIDIA, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ +#include <linux/i2c.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> + +#include <linux/regulator/machine.h> +#include <linux/mfd/tps6586x.h> + +#include <mach/irqs.h> + +#define PMC_CTRL 0x0 +#define PMC_CTRL_INTR_LOW (1 << 17) + +static struct regulator_consumer_supply tps658621_ldo0_supply[] = { + REGULATOR_SUPPLY("pex_clk", NULL), +}; + +static struct regulator_init_data ldo0_data = { + .constraints = { + .min_uV = 1250 * 1000, + .max_uV = 3300 * 1000, + .valid_modes_mask = (REGULATOR_MODE_NORMAL | + REGULATOR_MODE_STANDBY), + .valid_ops_mask = (REGULATOR_CHANGE_MODE | + REGULATOR_CHANGE_STATUS | + REGULATOR_CHANGE_VOLTAGE), + }, + .num_consumer_supplies = ARRAY_SIZE(tps658621_ldo0_supply), + .consumer_supplies = tps658621_ldo0_supply, +}; + +#define HARMONY_REGULATOR_INIT(_id, _minmv, _maxmv) \ + static struct regulator_init_data _id##_data = { \ + .constraints = { \ + .min_uV = (_minmv)*1000, \ + .max_uV = (_maxmv)*1000, \ + .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ + REGULATOR_MODE_STANDBY), \ + .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ + REGULATOR_CHANGE_STATUS | \ + REGULATOR_CHANGE_VOLTAGE), \ + }, \ + } + +HARMONY_REGULATOR_INIT(sm0, 725, 1500); +HARMONY_REGULATOR_INIT(sm1, 725, 1500); +HARMONY_REGULATOR_INIT(sm2, 3000, 4550); +HARMONY_REGULATOR_INIT(ldo1, 725, 1500); +HARMONY_REGULATOR_INIT(ldo2, 725, 1500); +HARMONY_REGULATOR_INIT(ldo3, 1250, 3300); +HARMONY_REGULATOR_INIT(ldo4, 1700, 2475); +HARMONY_REGULATOR_INIT(ldo5, 1250, 3300); +HARMONY_REGULATOR_INIT(ldo6, 1250, 3300); +HARMONY_REGULATOR_INIT(ldo7, 1250, 3300); +HARMONY_REGULATOR_INIT(ldo8, 1250, 3300); +HARMONY_REGULATOR_INIT(ldo9, 1250, 3300); + +#define TPS_REG(_id, _data) \ + { \ + .id = TPS6586X_ID_##_id, \ + .name = "tps6586x-regulator", \ + .platform_data = _data, \ + } + +static struct tps6586x_subdev_info tps_devs[] = { + TPS_REG(SM_0, &sm0_data), + TPS_REG(SM_1, &sm1_data), + TPS_REG(SM_2, &sm2_data), + TPS_REG(LDO_0, &ldo0_data), + TPS_REG(LDO_1, &ldo1_data), + TPS_REG(LDO_2, &ldo2_data), + TPS_REG(LDO_3, &ldo3_data), + TPS_REG(LDO_4, &ldo4_data), + TPS_REG(LDO_5, &ldo5_data), + TPS_REG(LDO_6, &ldo6_data), + TPS_REG(LDO_7, &ldo7_data), + TPS_REG(LDO_8, &ldo8_data), + TPS_REG(LDO_9, &ldo9_data), +}; + +static struct tps6586x_platform_data tps_platform = { + .irq_base = TEGRA_NR_IRQS, + .num_subdevs = ARRAY_SIZE(tps_devs), + .subdevs = tps_devs, + .gpio_base = TEGRA_NR_GPIOS, +}; + +static struct i2c_board_info __initdata harmony_regulators[] = { + { + I2C_BOARD_INFO("tps6586x", 0x34), + .irq = INT_EXTERNAL_PMU, + .platform_data = &tps_platform, + }, +}; + +int __init harmony_regulator_init(void) +{ + i2c_register_board_info(3, harmony_regulators, 1); + + return 0; +} diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c index 49224e936eb..75c918a86a3 100644 --- a/arch/arm/mach-tegra/board-harmony.c +++ b/arch/arm/mach-tegra/board-harmony.c @@ -2,6 +2,7 @@ * arch/arm/mach-tegra/board-harmony.c * * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2011 NVIDIA, Inc. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -22,12 +23,18 @@ #include <linux/dma-mapping.h> #include <linux/pda_power.h> #include <linux/io.h> +#include <linux/gpio.h> +#include <linux/i2c.h> +#include <linux/i2c-tegra.h> + +#include <sound/wm8903.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/setup.h> +#include <mach/harmony_audio.h> #include <mach/iomap.h> #include <mach/irqs.h> #include <mach/sdhci.h> @@ -60,11 +67,81 @@ static struct platform_device debug_uart = { }, }; +static struct harmony_audio_platform_data harmony_audio_pdata = { + .gpio_spkr_en = TEGRA_GPIO_SPKR_EN, + .gpio_hp_det = TEGRA_GPIO_HP_DET, + .gpio_int_mic_en = TEGRA_GPIO_INT_MIC_EN, + .gpio_ext_mic_en = TEGRA_GPIO_EXT_MIC_EN, +}; + +static struct platform_device harmony_audio_device = { + .name = "tegra-snd-harmony", + .id = 0, + .dev = { + .platform_data = &harmony_audio_pdata, + }, +}; + +static struct tegra_i2c_platform_data harmony_i2c1_platform_data = { + .bus_clk_rate = 400000, +}; + +static struct tegra_i2c_platform_data harmony_i2c2_platform_data = { + .bus_clk_rate = 400000, +}; + +static struct tegra_i2c_platform_data harmony_i2c3_platform_data = { + .bus_clk_rate = 400000, +}; + +static struct tegra_i2c_platform_data harmony_dvc_platform_data = { + .bus_clk_rate = 400000, +}; + +static struct wm8903_platform_data harmony_wm8903_pdata = { + .irq_active_low = 0, + .micdet_cfg = 0, + .micdet_delay = 100, + .gpio_base = HARMONY_GPIO_WM8903(0), + .gpio_cfg = { + WM8903_GPIO_NO_CONFIG, + WM8903_GPIO_NO_CONFIG, + 0, + WM8903_GPIO_NO_CONFIG, + WM8903_GPIO_NO_CONFIG, + }, +}; + +static struct i2c_board_info __initdata wm8903_board_info = { + I2C_BOARD_INFO("wm8903", 0x1a), + .platform_data = &harmony_wm8903_pdata, + .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ), +}; + +static void __init harmony_i2c_init(void) +{ + tegra_i2c_device1.dev.platform_data = &harmony_i2c1_platform_data; + tegra_i2c_device2.dev.platform_data = &harmony_i2c2_platform_data; + tegra_i2c_device3.dev.platform_data = &harmony_i2c3_platform_data; + tegra_i2c_device4.dev.platform_data = &harmony_dvc_platform_data; + + platform_device_register(&tegra_i2c_device1); + platform_device_register(&tegra_i2c_device2); + platform_device_register(&tegra_i2c_device3); + platform_device_register(&tegra_i2c_device4); + + i2c_register_board_info(0, &wm8903_board_info, 1); +} + static struct platform_device *harmony_devices[] __initdata = { &debug_uart, &tegra_sdhci_device1, &tegra_sdhci_device2, &tegra_sdhci_device4, + &tegra_i2s_device1, + &tegra_das_device, + &tegra_pcm_device, + &harmony_audio_device, }; static void __init tegra_harmony_fixup(struct machine_desc *desc, @@ -80,6 +157,10 @@ static void __init tegra_harmony_fixup(struct machine_desc *desc, static __initdata struct tegra_clk_init_table harmony_clk_init_table[] = { /* name parent rate enabled */ { "uartd", "pll_p", 216000000, true }, + { "pll_a", "pll_p_out1", 56448000, true }, + { "pll_a_out0", "pll_a", 11289600, true }, + { "cdev1", NULL, 0, true }, + { "i2s1", "pll_a_out0", 11289600, false}, { NULL, NULL, 0, 0}, }; @@ -91,15 +172,15 @@ static struct tegra_sdhci_platform_data sdhci_pdata1 = { }; static struct tegra_sdhci_platform_data sdhci_pdata2 = { - .cd_gpio = TEGRA_GPIO_PI5, - .wp_gpio = TEGRA_GPIO_PH1, - .power_gpio = TEGRA_GPIO_PT3, + .cd_gpio = TEGRA_GPIO_SD2_CD, + .wp_gpio = TEGRA_GPIO_SD2_WP, + .power_gpio = TEGRA_GPIO_SD2_POWER, }; static struct tegra_sdhci_platform_data sdhci_pdata4 = { - .cd_gpio = TEGRA_GPIO_PH2, - .wp_gpio = TEGRA_GPIO_PH3, - .power_gpio = TEGRA_GPIO_PI6, + .cd_gpio = TEGRA_GPIO_SD4_CD, + .wp_gpio = TEGRA_GPIO_SD4_WP, + .power_gpio = TEGRA_GPIO_SD4_POWER, .is_8bit = 1, }; @@ -114,6 +195,8 @@ static void __init tegra_harmony_init(void) tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4; platform_add_devices(harmony_devices, ARRAY_SIZE(harmony_devices)); + harmony_i2c_init(); + harmony_regulator_init(); } MACHINE_START(HARMONY, "harmony") diff --git a/arch/arm/mach-tegra/board-harmony.h b/arch/arm/mach-tegra/board-harmony.h index 09ca7755dd5..1e57b071f52 100644 --- a/arch/arm/mach-tegra/board-harmony.h +++ b/arch/arm/mach-tegra/board-harmony.h @@ -17,6 +17,21 @@ #ifndef _MACH_TEGRA_BOARD_HARMONY_H #define _MACH_TEGRA_BOARD_HARMONY_H +#define HARMONY_GPIO_WM8903(_x_) (TEGRA_NR_GPIOS + (_x_)) + +#define TEGRA_GPIO_SD2_CD TEGRA_GPIO_PI5 +#define TEGRA_GPIO_SD2_WP TEGRA_GPIO_PH1 +#define TEGRA_GPIO_SD2_POWER TEGRA_GPIO_PT3 +#define TEGRA_GPIO_SD4_CD TEGRA_GPIO_PH2 +#define TEGRA_GPIO_SD4_WP TEGRA_GPIO_PH3 +#define TEGRA_GPIO_SD4_POWER TEGRA_GPIO_PI6 +#define TEGRA_GPIO_CDC_IRQ TEGRA_GPIO_PX3 +#define TEGRA_GPIO_SPKR_EN HARMONY_GPIO_WM8903(2) +#define TEGRA_GPIO_HP_DET TEGRA_GPIO_PW2 +#define TEGRA_GPIO_INT_MIC_EN TEGRA_GPIO_PX0 +#define TEGRA_GPIO_EXT_MIC_EN TEGRA_GPIO_PX1 + void harmony_pinmux_init(void); +int harmony_regulator_init(void); #endif diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c new file mode 100644 index 00000000000..2643d1bd568 --- /dev/null +++ b/arch/arm/mach-tegra/board-paz00-pinmux.c @@ -0,0 +1,157 @@ +/* + * arch/arm/mach-tegra/board-paz00-pinmux.c + * + * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <mach/pinmux.h> + +#include "gpio-names.h" +#include "board-paz00.h" + +static struct tegra_pingroup_config paz00_pinmux[] = { + {TEGRA_PINGROUP_ATA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CSUS, TEGRA_MUX_PLLC_OUT1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DAP2, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTA, TEGRA_MUX_RSVD1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTD, TEGRA_MUX_RSVD1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCB, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_OWC, TEGRA_MUX_OWR, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SDC, TEGRA_MUX_TWC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPID, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIE, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIF, TEGRA_MUX_RSVD4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UAD, TEGRA_MUX_SPDIF, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +}; + +static struct tegra_gpio_table gpio_table[] = { + { .gpio = TEGRA_GPIO_SD1_CD, .enable = true }, + { .gpio = TEGRA_GPIO_SD1_WP, .enable = true }, + { .gpio = TEGRA_GPIO_SD1_POWER, .enable = true }, + { .gpio = TEGRA_GPIO_SD4_CD, .enable = true }, + { .gpio = TEGRA_GPIO_SD4_WP, .enable = true }, + { .gpio = TEGRA_GPIO_SD4_POWER, .enable = true }, +}; + +void paz00_pinmux_init(void) +{ + tegra_pinmux_config_table(paz00_pinmux, ARRAY_SIZE(paz00_pinmux)); + + tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c new file mode 100644 index 00000000000..57e50a823ee --- /dev/null +++ b/arch/arm/mach-tegra/board-paz00.c @@ -0,0 +1,128 @@ +/* + * arch/arm/mach-tegra/board-paz00.c + * + * Copyright (C) 2011 Marc Dietrich <marvin24@gmx.de> + * + * Based on board-harmony.c + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <linux/clk.h> +#include <linux/dma-mapping.h> +#include <linux/pda_power.h> +#include <linux/io.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/setup.h> + +#include <mach/iomap.h> +#include <mach/irqs.h> +#include <mach/sdhci.h> + +#include "board.h" +#include "board-paz00.h" +#include "clock.h" +#include "devices.h" +#include "gpio-names.h" + +static struct plat_serial8250_port debug_uart_platform_data[] = { + { + .membase = IO_ADDRESS(TEGRA_UARTD_BASE), + .mapbase = TEGRA_UARTD_BASE, + .irq = INT_UARTD, + .flags = UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 216000000, + }, { + .flags = 0 + } +}; + +static struct platform_device debug_uart = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = debug_uart_platform_data, + }, +}; + +static struct platform_device *paz00_devices[] __initdata = { + &debug_uart, + &tegra_sdhci_device1, + &tegra_sdhci_device2, + &tegra_sdhci_device4, +}; + +static void __init tegra_paz00_fixup(struct machine_desc *desc, + struct tag *tags, char **cmdline, struct meminfo *mi) +{ + mi->nr_banks = 1; + mi->bank[0].start = PHYS_OFFSET; + mi->bank[0].size = 448 * SZ_1M; +} + +static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { + /* name parent rate enabled */ + { "uartd", "pll_p", 216000000, true }, + { NULL, NULL, 0, 0}, +}; + + +static struct tegra_sdhci_platform_data sdhci_pdata1 = { + .cd_gpio = TEGRA_GPIO_SD1_CD, + .wp_gpio = TEGRA_GPIO_SD1_WP, + .power_gpio = TEGRA_GPIO_SD1_POWER, +}; + +static struct tegra_sdhci_platform_data sdhci_pdata2 = { + .cd_gpio = -1, + .wp_gpio = -1, + .power_gpio = -1, +}; + +static struct tegra_sdhci_platform_data sdhci_pdata4 = { + .cd_gpio = TEGRA_GPIO_SD4_CD, + .wp_gpio = TEGRA_GPIO_SD4_WP, + .power_gpio = TEGRA_GPIO_SD4_POWER, + .is_8bit = 1, +}; + +static void __init tegra_paz00_init(void) +{ + tegra_clk_init_from_table(paz00_clk_init_table); + + paz00_pinmux_init(); + + tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1; + tegra_sdhci_device2.dev.platform_data = &sdhci_pdata2; + tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4; + + platform_add_devices(paz00_devices, ARRAY_SIZE(paz00_devices)); +} + +MACHINE_START(PAZ00, "paz00") + .boot_params = 0x00000100, + .fixup = tegra_paz00_fixup, + .map_io = tegra_map_common_io, + .init_early = tegra_init_early, + .init_irq = tegra_init_irq, + .timer = &tegra_timer, + .init_machine = tegra_paz00_init, +MACHINE_END diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h new file mode 100644 index 00000000000..da193ca76d3 --- /dev/null +++ b/arch/arm/mach-tegra/board-paz00.h @@ -0,0 +1,29 @@ +/* + * arch/arm/mach-tegra/board-paz00.h + * + * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _MACH_TEGRA_BOARD_PAZ00_H +#define _MACH_TEGRA_BOARD_PAZ00_H + +#define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5 +#define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1 +#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PT3 +#define TEGRA_GPIO_SD4_CD TEGRA_GPIO_PH2 +#define TEGRA_GPIO_SD4_WP TEGRA_GPIO_PH3 +#define TEGRA_GPIO_SD4_POWER TEGRA_GPIO_PI6 + +void paz00_pinmux_init(void); + +#endif diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c index 2d6ad83ed4b..0bda495e974 100644 --- a/arch/arm/mach-tegra/board-seaboard-pinmux.c +++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c @@ -161,11 +161,12 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = { static struct tegra_gpio_table gpio_table[] = { - { .gpio = TEGRA_GPIO_PI5, .enable = true }, /* mmc2 cd */ - { .gpio = TEGRA_GPIO_PH1, .enable = true }, /* mmc2 wp */ - { .gpio = TEGRA_GPIO_PI6, .enable = true }, /* mmc2 pwr */ - { .gpio = TEGRA_GPIO_LIDSWITCH, .enable = true }, /* lid switch */ - { .gpio = TEGRA_GPIO_POWERKEY, .enable = true }, /* power key */ + { .gpio = TEGRA_GPIO_SD2_CD, .enable = true }, + { .gpio = TEGRA_GPIO_SD2_WP, .enable = true }, + { .gpio = TEGRA_GPIO_SD2_POWER, .enable = true }, + { .gpio = TEGRA_GPIO_LIDSWITCH, .enable = true }, + { .gpio = TEGRA_GPIO_POWERKEY, .enable = true }, + { .gpio = TEGRA_GPIO_ISL29018_IRQ, .enable = true }, }; void __init seaboard_pinmux_init(void) diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c index 6ca9e61f6cd..a8d7ace9f95 100644 --- a/arch/arm/mach-tegra/board-seaboard.c +++ b/arch/arm/mach-tegra/board-seaboard.c @@ -18,9 +18,12 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/serial_8250.h> +#include <linux/i2c.h> +#include <linux/i2c-tegra.h> #include <linux/delay.h> #include <linux/input.h> #include <linux/io.h> +#include <linux/gpio.h> #include <linux/gpio_keys.h> #include <mach/iomap.h> @@ -63,6 +66,22 @@ static __initdata struct tegra_clk_init_table seaboard_clk_init_table[] = { { NULL, NULL, 0, 0}, }; +static struct tegra_i2c_platform_data seaboard_i2c1_platform_data = { + .bus_clk_rate = 400000. +}; + +static struct tegra_i2c_platform_data seaboard_i2c2_platform_data = { + .bus_clk_rate = 400000, +}; + +static struct tegra_i2c_platform_data seaboard_i2c3_platform_data = { + .bus_clk_rate = 400000, +}; + +static struct tegra_i2c_platform_data seaboard_dvc_platform_data = { + .bus_clk_rate = 400000, +}; + static struct gpio_keys_button seaboard_gpio_keys_buttons[] = { { .code = SW_LID, @@ -103,9 +122,9 @@ static struct tegra_sdhci_platform_data sdhci_pdata1 = { }; static struct tegra_sdhci_platform_data sdhci_pdata3 = { - .cd_gpio = TEGRA_GPIO_PI5, - .wp_gpio = TEGRA_GPIO_PH1, - .power_gpio = TEGRA_GPIO_PI6, + .cd_gpio = TEGRA_GPIO_SD2_CD, + .wp_gpio = TEGRA_GPIO_SD2_WP, + .power_gpio = TEGRA_GPIO_SD2_POWER, }; static struct tegra_sdhci_platform_data sdhci_pdata4 = { @@ -124,7 +143,36 @@ static struct platform_device *seaboard_devices[] __initdata = { &seaboard_gpio_keys_device, }; -static void __init __tegra_seaboard_init(void) +static struct i2c_board_info __initdata isl29018_device = { + I2C_BOARD_INFO("isl29018", 0x44), + .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_ISL29018_IRQ), +}; + +static struct i2c_board_info __initdata adt7461_device = { + I2C_BOARD_INFO("adt7461", 0x4c), +}; + +static void __init seaboard_i2c_init(void) +{ + gpio_request(TEGRA_GPIO_ISL29018_IRQ, "isl29018"); + gpio_direction_input(TEGRA_GPIO_ISL29018_IRQ); + + i2c_register_board_info(0, &isl29018_device, 1); + + i2c_register_board_info(4, &adt7461_device, 1); + + tegra_i2c_device1.dev.platform_data = &seaboard_i2c1_platform_data; + tegra_i2c_device2.dev.platform_data = &seaboard_i2c2_platform_data; + tegra_i2c_device3.dev.platform_data = &seaboard_i2c3_platform_data; + tegra_i2c_device4.dev.platform_data = &seaboard_dvc_platform_data; + + platform_device_register(&tegra_i2c_device1); + platform_device_register(&tegra_i2c_device2); + platform_device_register(&tegra_i2c_device3); + platform_device_register(&tegra_i2c_device4); +} + +static void __init seaboard_common_init(void) { seaboard_pinmux_init(); @@ -144,7 +192,9 @@ static void __init tegra_seaboard_init(void) debug_uart_platform_data[0].mapbase = TEGRA_UARTD_BASE; debug_uart_platform_data[0].irq = INT_UARTD; - __tegra_seaboard_init(); + seaboard_common_init(); + + seaboard_i2c_init(); } static void __init tegra_kaen_init(void) @@ -154,7 +204,9 @@ static void __init tegra_kaen_init(void) debug_uart_platform_data[0].mapbase = TEGRA_UARTB_BASE; debug_uart_platform_data[0].irq = INT_UARTB; - __tegra_seaboard_init(); + seaboard_common_init(); + + seaboard_i2c_init(); } static void __init tegra_wario_init(void) @@ -164,7 +216,9 @@ static void __init tegra_wario_init(void) debug_uart_platform_data[0].mapbase = TEGRA_UARTB_BASE; debug_uart_platform_data[0].irq = INT_UARTB; - __tegra_seaboard_init(); + seaboard_common_init(); + + seaboard_i2c_init(); } diff --git a/arch/arm/mach-tegra/board-seaboard.h b/arch/arm/mach-tegra/board-seaboard.h index a098e359973..d8415e1a843 100644 --- a/arch/arm/mach-tegra/board-seaboard.h +++ b/arch/arm/mach-tegra/board-seaboard.h @@ -17,6 +17,9 @@ #ifndef _MACH_TEGRA_BOARD_SEABOARD_H #define _MACH_TEGRA_BOARD_SEABOARD_H +#define TEGRA_GPIO_SD2_CD TEGRA_GPIO_PI5 +#define TEGRA_GPIO_SD2_WP TEGRA_GPIO_PH1 +#define TEGRA_GPIO_SD2_POWER TEGRA_GPIO_PI6 #define TEGRA_GPIO_LIDSWITCH TEGRA_GPIO_PC7 #define TEGRA_GPIO_USB1 TEGRA_GPIO_PD0 #define TEGRA_GPIO_POWERKEY TEGRA_GPIO_PV2 diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c index 6d4fc9f7f1f..13534fa08ab 100644 --- a/arch/arm/mach-tegra/board-trimslice-pinmux.c +++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c @@ -16,8 +16,11 @@ #include <linux/kernel.h> #include <linux/init.h> + #include <mach/pinmux.h> +#include <mach/gpio.h> +#include "gpio-names.h" #include "board-trimslice.h" static __initdata struct tegra_pingroup_config trimslice_pinmux[] = { @@ -139,7 +142,13 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = { {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, }; +static struct tegra_gpio_table gpio_table[] = { + { .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true }, /* mmc4 cd */ + { .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true }, /* mmc4 wp */ +}; + void __init trimslice_pinmux_init(void) { tegra_pinmux_config_table(trimslice_pinmux, ARRAY_SIZE(trimslice_pinmux)); + tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table)); } diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c index 7be7d4acd02..cda4cfd78e8 100644 --- a/arch/arm/mach-tegra/board-trimslice.c +++ b/arch/arm/mach-tegra/board-trimslice.c @@ -29,9 +29,12 @@ #include <asm/setup.h> #include <mach/iomap.h> +#include <mach/sdhci.h> #include "board.h" #include "clock.h" +#include "devices.h" +#include "gpio-names.h" #include "board-trimslice.h" @@ -56,9 +59,22 @@ static struct platform_device debug_uart = { .platform_data = debug_uart_platform_data, }, }; +static struct tegra_sdhci_platform_data sdhci_pdata1 = { + .cd_gpio = -1, + .wp_gpio = -1, + .power_gpio = -1, +}; + +static struct tegra_sdhci_platform_data sdhci_pdata4 = { + .cd_gpio = TRIMSLICE_GPIO_SD4_CD, + .wp_gpio = TRIMSLICE_GPIO_SD4_WP, + .power_gpio = -1, +}; static struct platform_device *trimslice_devices[] __initdata = { &debug_uart, + &tegra_sdhci_device1, + &tegra_sdhci_device4, }; static void __init tegra_trimslice_fixup(struct machine_desc *desc, @@ -92,6 +108,9 @@ static void __init tegra_trimslice_init(void) trimslice_pinmux_init(); + tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1; + tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4; + platform_add_devices(trimslice_devices, ARRAY_SIZE(trimslice_devices)); } diff --git a/arch/arm/mach-tegra/board-trimslice.h b/arch/arm/mach-tegra/board-trimslice.h index 16ec0f0d3bb..e8ef6291c6f 100644 --- a/arch/arm/mach-tegra/board-trimslice.h +++ b/arch/arm/mach-tegra/board-trimslice.h @@ -17,6 +17,9 @@ #ifndef _MACH_TEGRA_BOARD_TRIMSLICE_H #define _MACH_TEGRA_BOARD_TRIMSLICE_H +#define TRIMSLICE_GPIO_SD4_CD TEGRA_GPIO_PP1 /* mmc4 cd */ +#define TRIMSLICE_GPIO_SD4_WP TEGRA_GPIO_PP2 /* mmc4 wp */ + void trimslice_pinmux_init(void); #endif diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c index 682e6d33108..1528f9daef1 100644 --- a/arch/arm/mach-tegra/devices.c +++ b/arch/arm/mach-tegra/devices.c @@ -503,3 +503,73 @@ struct platform_device tegra_uarte_device = { .coherent_dma_mask = DMA_BIT_MASK(32), }, }; + +static struct resource i2s_resource1[] = { + [0] = { + .start = INT_I2S1, + .end = INT_I2S1, + .flags = IORESOURCE_IRQ + }, + [1] = { + .start = TEGRA_DMA_REQ_SEL_I2S_1, + .end = TEGRA_DMA_REQ_SEL_I2S_1, + .flags = IORESOURCE_DMA + }, + [2] = { + .start = TEGRA_I2S1_BASE, + .end = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1, + .flags = IORESOURCE_MEM + } +}; + +static struct resource i2s_resource2[] = { + [0] = { + .start = INT_I2S2, + .end = INT_I2S2, + .flags = IORESOURCE_IRQ + }, + [1] = { + .start = TEGRA_DMA_REQ_SEL_I2S2_1, + .end = TEGRA_DMA_REQ_SEL_I2S2_1, + .flags = IORESOURCE_DMA + }, + [2] = { + .start = TEGRA_I2S2_BASE, + .end = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1, + .flags = IORESOURCE_MEM + } +}; + +struct platform_device tegra_i2s_device1 = { + .name = "tegra-i2s", + .id = 0, + .resource = i2s_resource1, + .num_resources = ARRAY_SIZE(i2s_resource1), +}; + +struct platform_device tegra_i2s_device2 = { + .name = "tegra-i2s", + .id = 1, + .resource = i2s_resource2, + .num_resources = ARRAY_SIZE(i2s_resource2), +}; + +static struct resource tegra_das_resources[] = { + [0] = { + .start = TEGRA_APB_MISC_DAS_BASE, + .end = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device tegra_das_device = { + .name = "tegra-das", + .id = -1, + .num_resources = ARRAY_SIZE(tegra_das_resources), + .resource = tegra_das_resources, +}; + +struct platform_device tegra_pcm_device = { + .name = "tegra-pcm-audio", + .id = -1, +}; diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h index 888810c37ee..4a7dc0a097d 100644 --- a/arch/arm/mach-tegra/devices.h +++ b/arch/arm/mach-tegra/devices.h @@ -42,5 +42,9 @@ extern struct platform_device tegra_uartc_device; extern struct platform_device tegra_uartd_device; extern struct platform_device tegra_uarte_device; extern struct platform_device tegra_pmu_device; +extern struct platform_device tegra_i2s_device1; +extern struct platform_device tegra_i2s_device2; +extern struct platform_device tegra_das_device; +extern struct platform_device tegra_pcm_device; #endif diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c index e945ae28ee7..f4ef5eb317b 100644 --- a/arch/arm/mach-tegra/dma.c +++ b/arch/arm/mach-tegra/dma.c @@ -223,7 +223,7 @@ int tegra_dma_dequeue_req(struct tegra_dma_channel *ch, * - Change the source selector to invalid to stop the DMA from * FIFO to memory. * - Read the status register to know the number of pending - * bytes to be transfered. + * bytes to be transferred. * - Finally stop or program the DMA to the next buffer in the * list. */ @@ -244,7 +244,7 @@ int tegra_dma_dequeue_req(struct tegra_dma_channel *ch, if (status & STA_BUSY) req->bytes_transferred -= to_transfer; - /* In continous transfer mode, DMA only tracks the count of the + /* In continuous transfer mode, DMA only tracks the count of the * half DMA buffer. So, if the DMA already finished half the DMA * then add the half buffer to the completed count. * diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c index 12090a2cf3e..65a1aba6823 100644 --- a/arch/arm/mach-tegra/gpio.c +++ b/arch/arm/mach-tegra/gpio.c @@ -208,9 +208,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) spin_unlock_irqrestore(&bank->lvl_lock[port], flags); if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) - __set_irq_handler_unlocked(d->irq, handle_level_irq); + __irq_set_handler_locked(d->irq, handle_level_irq); else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) - __set_irq_handler_unlocked(d->irq, handle_edge_irq); + __irq_set_handler_locked(d->irq, handle_edge_irq); return 0; } @@ -224,7 +224,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) desc->irq_data.chip->irq_ack(&desc->irq_data); - bank = get_irq_data(irq); + bank = irq_get_handler_data(irq); for (port = 0; port < 4; port++) { int gpio = tegra_gpio_compose(bank->bank, port, 0); @@ -257,7 +257,8 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) void tegra_gpio_resume(void) { unsigned long flags; - int b, p, i; + int b; + int p; local_irq_save(flags); @@ -275,31 +276,13 @@ void tegra_gpio_resume(void) } local_irq_restore(flags); - - for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { - struct irq_desc *desc = irq_to_desc(i); - if (!desc || (desc->status & IRQ_WAKEUP)) - continue; - enable_irq(i); - } } void tegra_gpio_suspend(void) { unsigned long flags; - int b, p, i; - - for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { - struct irq_desc *desc = irq_to_desc(i); - if (!desc) - continue; - if (desc->status & IRQ_WAKEUP) { - int gpio = i - INT_GPIO_BASE; - pr_debug("gpio %d.%d is wakeup\n", gpio/8, gpio&7); - continue; - } - disable_irq(i); - } + int b; + int p; local_irq_save(flags); for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) { @@ -320,7 +303,7 @@ void tegra_gpio_suspend(void) static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable) { struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); - return set_irq_wake(bank->irq, enable); + return irq_set_irq_wake(bank->irq, enable); } #endif @@ -359,18 +342,18 @@ static int __init tegra_gpio_init(void) for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))]; - lockdep_set_class(&irq_desc[i].lock, &gpio_lock_class); - set_irq_chip_data(i, bank); - set_irq_chip(i, &tegra_gpio_irq_chip); - set_irq_handler(i, handle_simple_irq); + irq_set_lockdep_class(i, &gpio_lock_class); + irq_set_chip_data(i, bank); + irq_set_chip_and_handler(i, &tegra_gpio_irq_chip, + handle_simple_irq); set_irq_flags(i, IRQF_VALID); } for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) { bank = &tegra_gpio_banks[i]; - set_irq_chained_handler(bank->irq, tegra_gpio_irq_handler); - set_irq_data(bank->irq, bank); + irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler); + irq_set_handler_data(bank->irq, bank); for (j = 0; j < 4; j++) spin_lock_init(&bank->lvl_lock[j]); diff --git a/arch/arm/mach-tegra/include/mach/barriers.h b/arch/arm/mach-tegra/include/mach/barriers.h index cc115174899..425b42e91ef 100644 --- a/arch/arm/mach-tegra/include/mach/barriers.h +++ b/arch/arm/mach-tegra/include/mach/barriers.h @@ -23,7 +23,7 @@ #include <asm/outercache.h> -#define rmb() dmb() +#define rmb() dsb() #define wmb() do { dsb(); outer_sync(); } while (0) #define mb() wmb() diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h index 39011bd9a92..d0132e8031a 100644 --- a/arch/arm/mach-tegra/include/mach/dma.h +++ b/arch/arm/mach-tegra/include/mach/dma.h @@ -92,11 +92,11 @@ struct tegra_dma_req { /* This is a called from the DMA ISR context when the DMA is still in * progress and is actively filling same buffer. * - * In case of continous mode receive, this threshold is 1/2 the buffer + * In case of continuous mode receive, this threshold is 1/2 the buffer * size. In other cases, this will not even be called as there is no * hardware support for it. * - * In the case of continous mode receive, if there is next req already + * In the case of continuous mode receive, if there is next req already * queued, DMA programs the HW to use that req when this req is * completed. If there is no "next req" queued, then DMA ISR doesn't do * anything before calling this callback. diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h index 691cdabd69c..19dec3ac085 100644 --- a/arch/arm/mach-tegra/include/mach/iomap.h +++ b/arch/arm/mach-tegra/include/mach/iomap.h @@ -122,6 +122,9 @@ #define TEGRA_APB_MISC_BASE 0x70000000 #define TEGRA_APB_MISC_SIZE SZ_4K +#define TEGRA_APB_MISC_DAS_BASE 0x70000c00 +#define TEGRA_APB_MISC_DAS_SIZE SZ_128 + #define TEGRA_AC97_BASE 0x70002000 #define TEGRA_AC97_SIZE SZ_512 diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index dfbc219ea49..4330d8995b2 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -144,7 +144,7 @@ void __init tegra_init_irq(void) gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); - gic = get_irq_chip(29); + gic = irq_get_chip(29); tegra_gic_unmask_irq = gic->irq_unmask; tegra_gic_mask_irq = gic->irq_mask; tegra_gic_ack_irq = gic->irq_ack; @@ -154,8 +154,7 @@ void __init tegra_init_irq(void) for (i = 0; i < INT_MAIN_NR; i++) { irq = INT_PRI_BASE + i; - set_irq_chip(irq, &tegra_irq); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &tegra_irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } } diff --git a/arch/arm/mach-tegra/localtimer.c b/arch/arm/mach-tegra/localtimer.c index f81ca7cbbc1..e91d681d45a 100644 --- a/arch/arm/mach-tegra/localtimer.c +++ b/arch/arm/mach-tegra/localtimer.c @@ -18,8 +18,9 @@ /* * Setup the local clock events for a CPU. */ -void __cpuinit local_timer_setup(struct clock_event_device *evt) +int __cpuinit local_timer_setup(struct clock_event_device *evt) { evt->irq = IRQ_LOCALTIMER; twd_timer_setup(evt); + return 0; } diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 6d7c4eea4dc..4459470c052 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -1362,14 +1362,15 @@ static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate) { unsigned long flags; int ret; + long new_rate = rate; - rate = clk_round_rate(c->parent, rate); - if (rate < 0) - return rate; + new_rate = clk_round_rate(c->parent, new_rate); + if (new_rate < 0) + return new_rate; spin_lock_irqsave(&c->parent->spinlock, flags); - c->u.shared_bus_user.rate = rate; + c->u.shared_bus_user.rate = new_rate; ret = tegra_clk_shared_bus_update(c->parent); spin_unlock_irqrestore(&c->parent->spinlock, flags); diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c index fabcc49abe8..5535dd0a78c 100644 --- a/arch/arm/mach-u300/clock.c +++ b/arch/arm/mach-u300/clock.c @@ -263,7 +263,7 @@ static void disable_i2s0_vcxo(void) val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); val &= ~U300_SYSCON_CCR_I2S0_USE_VCXO; writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); - /* Deactivate VCXO if noone else is using VCXO */ + /* Deactivate VCXO if no one else is using VCXO */ if (!(val & U300_SYSCON_CCR_I2S1_USE_VCXO)) val &= ~U300_SYSCON_CCR_TURN_VCXO_ON; writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); @@ -283,7 +283,7 @@ static void disable_i2s1_vcxo(void) val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); val &= ~U300_SYSCON_CCR_I2S1_USE_VCXO; writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); - /* Deactivate VCXO if noone else is using VCXO */ + /* Deactivate VCXO if no one else is using VCXO */ if (!(val & U300_SYSCON_CCR_I2S0_USE_VCXO)) val &= ~U300_SYSCON_CCR_TURN_VCXO_ON; writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); @@ -649,7 +649,7 @@ static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate) */ long clk_round_rate(struct clk *clk, unsigned long rate) { - /* TODO: get apropriate switches for EMIFCLK, AHBCLK and MCLK */ + /* TODO: get appropriate switches for EMIFCLK, AHBCLK and MCLK */ /* Else default to fixed value */ if (clk->round_rate) { diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 203b986280f..58626013aa3 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -23,6 +23,7 @@ menu "Ux500 target platform" config MACH_U8500 bool "U8500 Development platform" depends on UX500_SOC_DB8500 + select TPS6105X help Include support for the mop500 development platform. diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c index 875c91b2f8a..9ed0f90cfe2 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.c +++ b/arch/arm/mach-ux500/board-mop500-regulators.c @@ -13,6 +13,30 @@ #include <linux/regulator/ab8500.h> #include "board-mop500-regulators.h" +/* + * TPS61052 regulator + */ +static struct regulator_consumer_supply tps61052_vaudio_consumers[] = { + /* + * Boost converter supply to raise voltage on audio speaker, this + * is actually connected to three pins, VInVhfL (left amplifier) + * VInVhfR (right amplifier) and VIntDClassInt - all three must + * be connected to the same voltage. + */ + REGULATOR_SUPPLY("vintdclassint", "ab8500-codec.0"), +}; + +struct regulator_init_data tps61052_regulator = { + .constraints = { + .name = "vaudio-hf", + .min_uV = 4500000, + .max_uV = 4500000, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(tps61052_vaudio_consumers), + .consumer_supplies = tps61052_vaudio_consumers, +}; + static struct regulator_consumer_supply ab8500_vaux1_consumers[] = { /* External displays, connector on board 2v5 power supply */ REGULATOR_SUPPLY("vaux12v5", "mcde.0"), @@ -62,6 +86,182 @@ static struct regulator_consumer_supply ab8500_vana_consumers[] = { REGULATOR_SUPPLY("vsmps2", "mcde.0"), }; +/* ab8500 regulator register initialization */ +struct ab8500_regulator_reg_init +ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS] = { + /* + * VanaRequestCtrl = HP/LP depending on VxRequest + * VextSupply1RequestCtrl = HP/LP depending on VxRequest + */ + INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL2, 0x00), + /* + * VextSupply2RequestCtrl = HP/LP depending on VxRequest + * VextSupply3RequestCtrl = HP/LP depending on VxRequest + * Vaux1RequestCtrl = HP/LP depending on VxRequest + * Vaux2RequestCtrl = HP/LP depending on VxRequest + */ + INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL3, 0x00), + /* + * Vaux3RequestCtrl = HP/LP depending on VxRequest + * SwHPReq = Control through SWValid disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL4, 0x00), + /* + * VanaSysClkReq1HPValid = disabled + * Vaux1SysClkReq1HPValid = disabled + * Vaux2SysClkReq1HPValid = disabled + * Vaux3SysClkReq1HPValid = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID1, 0x00), + /* + * VextSupply1SysClkReq1HPValid = disabled + * VextSupply2SysClkReq1HPValid = disabled + * VextSupply3SysClkReq1HPValid = SysClkReq1 controlled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID2, 0x40), + /* + * VanaHwHPReq1Valid = disabled + * Vaux1HwHPreq1Valid = disabled + * Vaux2HwHPReq1Valid = disabled + * Vaux3HwHPReqValid = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID1, 0x00), + /* + * VextSupply1HwHPReq1Valid = disabled + * VextSupply2HwHPReq1Valid = disabled + * VextSupply3HwHPReq1Valid = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID2, 0x00), + /* + * VanaHwHPReq2Valid = disabled + * Vaux1HwHPReq2Valid = disabled + * Vaux2HwHPReq2Valid = disabled + * Vaux3HwHPReq2Valid = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID1, 0x00), + /* + * VextSupply1HwHPReq2Valid = disabled + * VextSupply2HwHPReq2Valid = disabled + * VextSupply3HwHPReq2Valid = HWReq2 controlled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID2, 0x04), + /* + * VanaSwHPReqValid = disabled + * Vaux1SwHPReqValid = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID1, 0x00), + /* + * Vaux2SwHPReqValid = disabled + * Vaux3SwHPReqValid = disabled + * VextSupply1SwHPReqValid = disabled + * VextSupply2SwHPReqValid = disabled + * VextSupply3SwHPReqValid = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID2, 0x00), + /* + * SysClkReq2Valid1 = SysClkReq2 controlled + * SysClkReq3Valid1 = disabled + * SysClkReq4Valid1 = SysClkReq4 controlled + * SysClkReq5Valid1 = disabled + * SysClkReq6Valid1 = SysClkReq6 controlled + * SysClkReq7Valid1 = disabled + * SysClkReq8Valid1 = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID1, 0x2a), + /* + * SysClkReq2Valid2 = disabled + * SysClkReq3Valid2 = disabled + * SysClkReq4Valid2 = disabled + * SysClkReq5Valid2 = disabled + * SysClkReq6Valid2 = SysClkReq6 controlled + * SysClkReq7Valid2 = disabled + * SysClkReq8Valid2 = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID2, 0x20), + /* + * VTVoutEna = disabled + * Vintcore12Ena = disabled + * Vintcore12Sel = 1.25 V + * Vintcore12LP = inactive (HP) + * VTVoutLP = inactive (HP) + */ + INIT_REGULATOR_REGISTER(AB8500_REGUMISC1, 0x10), + /* + * VaudioEna = disabled + * VdmicEna = disabled + * Vamic1Ena = disabled + * Vamic2Ena = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_VAUDIOSUPPLY, 0x00), + /* + * Vamic1_dzout = high-Z when Vamic1 is disabled + * Vamic2_dzout = high-Z when Vamic2 is disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUCTRL1VAMIC, 0x00), + /* + * VPll = Hw controlled + * VanaRegu = force off + */ + INIT_REGULATOR_REGISTER(AB8500_VPLLVANAREGU, 0x02), + /* + * VrefDDREna = disabled + * VrefDDRSleepMode = inactive (no pulldown) + */ + INIT_REGULATOR_REGISTER(AB8500_VREFDDR, 0x00), + /* + * VextSupply1Regu = HW control + * VextSupply2Regu = HW control + * VextSupply3Regu = HW control + * ExtSupply2Bypass = ExtSupply12LPn ball is 0 when Ena is 0 + * ExtSupply3Bypass = ExtSupply3LPn ball is 0 when Ena is 0 + */ + INIT_REGULATOR_REGISTER(AB8500_EXTSUPPLYREGU, 0x2a), + /* + * Vaux1Regu = force HP + * Vaux2Regu = force off + */ + INIT_REGULATOR_REGISTER(AB8500_VAUX12REGU, 0x01), + /* + * Vaux3regu = force off + */ + INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3REGU, 0x00), + /* + * Vsmps1 = 1.15V + */ + INIT_REGULATOR_REGISTER(AB8500_VSMPS1SEL1, 0x24), + /* + * Vaux1Sel = 2.5 V + */ + INIT_REGULATOR_REGISTER(AB8500_VAUX1SEL, 0x08), + /* + * Vaux2Sel = 2.9 V + */ + INIT_REGULATOR_REGISTER(AB8500_VAUX2SEL, 0x0d), + /* + * Vaux3Sel = 2.91 V + */ + INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3SEL, 0x07), + /* + * VextSupply12LP = disabled (no LP) + */ + INIT_REGULATOR_REGISTER(AB8500_REGUCTRL2SPARE, 0x00), + /* + * Vaux1Disch = short discharge time + * Vaux2Disch = short discharge time + * Vaux3Disch = short discharge time + * Vintcore12Disch = short discharge time + * VTVoutDisch = short discharge time + * VaudioDisch = short discharge time + */ + INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH, 0x00), + /* + * VanaDisch = short discharge time + * VdmicPullDownEna = pulldown disabled when Vdmic is disabled + * VdmicDisch = short discharge time + */ + INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH2, 0x00), +}; + /* AB8500 regulators */ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = { /* supplies to the display/camera */ @@ -72,6 +272,7 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = { .max_uV = 2900000, .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, + .boot_on = 1, /* must be on for display */ }, .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers), .consumer_supplies = ab8500_vaux1_consumers, diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h index 2675fae5253..94992158d96 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.h +++ b/arch/arm/mach-ux500/board-mop500-regulators.h @@ -14,6 +14,9 @@ #include <linux/regulator/machine.h> #include <linux/regulator/ab8500.h> +extern struct ab8500_regulator_reg_init +ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS]; extern struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS]; +extern struct regulator_init_data tps61052_regulator; #endif diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 8790d984cac..6e1907fa94f 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -20,7 +20,10 @@ #include <linux/amba/serial.h> #include <linux/spi/spi.h> #include <linux/mfd/ab8500.h> +#include <linux/regulator/ab8500.h> #include <linux/mfd/tc3589x.h> +#include <linux/mfd/tps6105x.h> +#include <linux/mfd/ab8500/gpio.h> #include <linux/leds-lp5521.h> #include <linux/input.h> #include <linux/gpio_keys.h> @@ -41,10 +44,35 @@ #include "board-mop500.h" #include "board-mop500-regulators.h" +static struct ab8500_gpio_platform_data ab8500_gpio_pdata = { + .gpio_base = MOP500_AB8500_GPIO(0), + .irq_base = MOP500_AB8500_VIR_GPIO_IRQ_BASE, + /* config_reg is the initial configuration of ab8500 pins. + * The pins can be configured as GPIO or alt functions based + * on value present in GpioSel1 to GpioSel6 and AlternatFunction + * register. This is the array of 7 configuration settings. + * One has to compile time decide these settings. Below is the + * explanation of these setting + * GpioSel1 = 0x00 => Pins GPIO1 to GPIO8 are not used as GPIO + * GpioSel2 = 0x1E => Pins GPIO10 to GPIO13 are configured as GPIO + * GpioSel3 = 0x80 => Pin GPIO24 is configured as GPIO + * GpioSel4 = 0x01 => Pin GPIo25 is configured as GPIO + * GpioSel5 = 0x7A => Pins GPIO34, GPIO36 to GPIO39 are conf as GPIO + * GpioSel6 = 0x00 => Pins GPIO41 & GPIo42 are not configured as GPIO + * AlternaFunction = 0x00 => If Pins GPIO10 to 13 are not configured + * as GPIO then this register selectes the alternate fucntions + */ + .config_reg = {0x00, 0x1E, 0x80, 0x01, + 0x7A, 0x00, 0x00}, +}; + static struct ab8500_platform_data ab8500_platdata = { .irq_base = MOP500_AB8500_IRQ_BASE, + .regulator_reg_init = ab8500_regulator_reg_init, + .num_regulator_reg_init = ARRAY_SIZE(ab8500_regulator_reg_init), .regulator = ab8500_regulators, .num_regulator = ARRAY_SIZE(ab8500_regulators), + .gpio = &ab8500_gpio_pdata, }; static struct resource ab8500_resources[] = { @@ -66,6 +94,15 @@ struct platform_device ab8500_device = { }; /* + * TPS61052 + */ + +static struct tps6105x_platform_data mop500_tps61052_data = { + .mode = TPS6105X_MODE_VOLTAGE, + .regulator_data = &tps61052_regulator, +}; + +/* * TC35892 */ @@ -135,14 +172,21 @@ static struct lp5521_platform_data __initdata lp5521_sec_data = { .clock_mode = LP5521_CLOCK_EXT, }; -static struct i2c_board_info mop500_i2c0_devices[] = { +static struct i2c_board_info __initdata mop500_i2c0_devices[] = { { I2C_BOARD_INFO("tc3589x", 0x42), .irq = NOMADIK_GPIO_TO_IRQ(217), .platform_data = &mop500_tc35892_data, }, + /* I2C0 devices only available prior to HREFv60 */ + { + I2C_BOARD_INFO("tps61052", 0x33), + .platform_data = &mop500_tps61052_data, + }, }; +#define NUM_PRE_V60_I2C0_DEVICES 1 + static struct i2c_board_info __initdata mop500_i2c2_devices[] = { { /* lp5521 LED driver, 1st device */ @@ -380,6 +424,8 @@ static void __init mop500_uart_init(void) static void __init mop500_init_machine(void) { + int i2c0_devs; + /* * The HREFv60 board removed a GPIO expander and routed * all these GPIO pins to the internal GPIO controller @@ -403,8 +449,11 @@ static void __init mop500_init_machine(void) platform_device_register(&ab8500_device); - i2c_register_board_info(0, mop500_i2c0_devices, - ARRAY_SIZE(mop500_i2c0_devices)); + i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); + if (machine_is_hrefv60()) + i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES; + + i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); i2c_register_board_info(2, mop500_i2c2_devices, ARRAY_SIZE(mop500_i2c2_devices)); } diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index 56722f4be71..03a31cc9b08 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -27,6 +27,10 @@ #define GPIO_BU21013_CS MOP500_EGPIO(13) #define GPIO_SDMMC_EN MOP500_EGPIO(17) #define GPIO_SDMMC_1V8_3V_SEL MOP500_EGPIO(18) +#define MOP500_EGPIO_END MOP500_EGPIO(24) + +/* GPIOs on the AB8500 mixed-signals circuit */ +#define MOP500_AB8500_GPIO(x) (MOP500_EGPIO_END + (x)) struct i2c_board_info; diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h index 0fefb34c11e..16647b25537 100644 --- a/arch/arm/mach-ux500/include/mach/db8500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h @@ -58,7 +58,7 @@ #define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000) #define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000) -/* per7 base addressess */ +/* per7 base addresses */ #define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000) #define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000) #define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000) @@ -68,7 +68,7 @@ #define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) #define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) -/* per6 base addressess */ +/* per6 base addresses */ #define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000) #define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000) #define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000) @@ -79,11 +79,11 @@ #define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000) #define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) -/* per5 base addressess */ +/* per5 base addresses */ #define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000) #define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) -/* per4 base addressess */ +/* per4 base addresses */ #define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000) #define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000) #define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000) @@ -106,7 +106,7 @@ #define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000) #define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) -/* per2 base addressess */ +/* per2 base addresses */ #define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000) #define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000) #define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000) diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h index 7cdeb2af0eb..97ef55f8493 100644 --- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h +++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h @@ -35,9 +35,20 @@ #define MOP500_STMPE1601_IRQBASE MOP500_EGPIO_IRQ_END #define MOP500_STMPE1601_IRQ(x) (MOP500_STMPE1601_IRQBASE + (x)) -#define MOP500_NR_IRQS MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS) +#define MOP500_STMPE1601_IRQ_END \ + MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS) -#define MOP500_IRQ_END MOP500_NR_IRQS +/* AB8500 virtual gpio IRQ */ +#define AB8500_VIR_GPIO_NR_IRQS 16 + +#define MOP500_AB8500_VIR_GPIO_IRQ_BASE \ + MOP500_STMPE1601_IRQ_END +#define MOP500_AB8500_VIR_GPIO_IRQ_END \ + (MOP500_AB8500_VIR_GPIO_IRQ_BASE + AB8500_VIR_GPIO_NR_IRQS) + +#define MOP500_NR_IRQS MOP500_AB8500_VIR_GPIO_IRQ_END + +#define MOP500_IRQ_END MOP500_NR_IRQS #if MOP500_IRQ_END > IRQ_BOARD_END #undef IRQ_BOARD_END diff --git a/arch/arm/mach-ux500/localtimer.c b/arch/arm/mach-ux500/localtimer.c index 2288f6a7c51..5ba113309a0 100644 --- a/arch/arm/mach-ux500/localtimer.c +++ b/arch/arm/mach-ux500/localtimer.c @@ -21,8 +21,9 @@ /* * Setup the local clock events for a CPU. */ -void __cpuinit local_timer_setup(struct clock_event_device *evt) +int __cpuinit local_timer_setup(struct clock_event_device *evt) { evt->irq = IRQ_LOCALTIMER; twd_timer_setup(evt); + return 0; } diff --git a/arch/arm/mach-ux500/modem-irq-db5500.c b/arch/arm/mach-ux500/modem-irq-db5500.c index e1296a7447c..6b86416c94c 100644 --- a/arch/arm/mach-ux500/modem-irq-db5500.c +++ b/arch/arm/mach-ux500/modem-irq-db5500.c @@ -90,8 +90,7 @@ static irqreturn_t modem_cpu_irq_handler(int irq, void *data) static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip) { - set_irq_chip(irq, modem_irq_chip); - set_irq_handler(irq, handle_simple_irq); + irq_set_chip_and_handler(irq, modem_irq_chip, handle_simple_irq); set_irq_flags(irq, IRQF_VALID); pr_debug("modem_irq: Created virtual IRQ %d\n", irq); diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 136c32e7ed8..eb7ffa0ee8b 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -50,6 +50,8 @@ #include <mach/platform.h> #include <asm/hardware/timer-sp.h> +#include <plat/clcd.h> +#include <plat/fpga-irq.h> #include <plat/sched_clock.h> #include "core.h" @@ -63,47 +65,12 @@ #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE) #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE) -static void sic_mask_irq(struct irq_data *d) -{ - unsigned int irq = d->irq - IRQ_SIC_START; - - writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); -} - -static void sic_unmask_irq(struct irq_data *d) -{ - unsigned int irq = d->irq - IRQ_SIC_START; - - writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET); -} - -static struct irq_chip sic_chip = { - .name = "SIC", - .irq_ack = sic_mask_irq, - .irq_mask = sic_mask_irq, - .irq_unmask = sic_unmask_irq, +static struct fpga_irq_data sic_irq = { + .base = VA_SIC_BASE, + .irq_start = IRQ_SIC_START, + .chip.name = "SIC", }; -static void -sic_handle_irq(unsigned int irq, struct irq_desc *desc) -{ - unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS); - - if (status == 0) { - do_bad_IRQ(irq, desc); - return; - } - - do { - irq = ffs(status) - 1; - status &= ~(1 << irq); - - irq += IRQ_SIC_START; - - generic_handle_irq(irq); - } while (status); -} - #if 1 #define IRQ_MMCI0A IRQ_VICSOURCE22 #define IRQ_AACI IRQ_VICSOURCE24 @@ -118,22 +85,11 @@ sic_handle_irq(unsigned int irq, struct irq_desc *desc) void __init versatile_init_irq(void) { - unsigned int i; - vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0); - set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq); - - /* Do second interrupt controller */ writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); - for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) { - if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) { - set_irq_chip(i, &sic_chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - } - } + fpga_irq_init(IRQ_VICSOURCE31, ~PIC_MASK, &sic_irq); /* * Interrupts on secondary controller from 0 to 8 are routed to @@ -476,127 +432,7 @@ static struct clk_lookup lookups[] = { #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8) #define SYS_CLCD_ID_VGA (0x1f << 8) -static struct clcd_panel vga = { - .mode = { - .name = "VGA", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 39721, - .left_margin = 40, - .right_margin = 24, - .upper_margin = 32, - .lower_margin = 11, - .hsync_len = 96, - .vsync_len = 2, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_BCD | TIM2_IPC, - .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), - .bpp = 16, -}; - -static struct clcd_panel sanyo_3_8_in = { - .mode = { - .name = "Sanyo QVGA", - .refresh = 116, - .xres = 320, - .yres = 240, - .pixclock = 100000, - .left_margin = 6, - .right_margin = 6, - .upper_margin = 5, - .lower_margin = 5, - .hsync_len = 6, - .vsync_len = 6, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_BCD, - .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), - .bpp = 16, -}; - -static struct clcd_panel sanyo_2_5_in = { - .mode = { - .name = "Sanyo QVGA Portrait", - .refresh = 116, - .xres = 240, - .yres = 320, - .pixclock = 100000, - .left_margin = 20, - .right_margin = 10, - .upper_margin = 2, - .lower_margin = 2, - .hsync_len = 10, - .vsync_len = 2, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC, - .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), - .bpp = 16, -}; - -static struct clcd_panel epson_2_2_in = { - .mode = { - .name = "Epson QCIF", - .refresh = 390, - .xres = 176, - .yres = 220, - .pixclock = 62500, - .left_margin = 3, - .right_margin = 2, - .upper_margin = 1, - .lower_margin = 0, - .hsync_len = 3, - .vsync_len = 2, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_BCD | TIM2_IPC, - .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), - .bpp = 16, -}; - -/* - * Detect which LCD panel is connected, and return the appropriate - * clcd_panel structure. Note: we do not have any information on - * the required timings for the 8.4in panel, so we presently assume - * VGA timings. - */ -static struct clcd_panel *versatile_clcd_panel(void) -{ - void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET; - struct clcd_panel *panel = &vga; - u32 val; - - val = readl(sys_clcd) & SYS_CLCD_ID_MASK; - if (val == SYS_CLCD_ID_SANYO_3_8) - panel = &sanyo_3_8_in; - else if (val == SYS_CLCD_ID_SANYO_2_5) - panel = &sanyo_2_5_in; - else if (val == SYS_CLCD_ID_EPSON_2_2) - panel = &epson_2_2_in; - else if (val == SYS_CLCD_ID_VGA) - panel = &vga; - else { - printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n", - val); - panel = &vga; - } - - return panel; -} +static bool is_sanyo_2_5_lcd; /* * Disable all display connectors on the interface module. @@ -614,7 +450,7 @@ static void versatile_clcd_disable(struct clcd_fb *fb) /* * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off */ - if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) { + if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) { void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL); unsigned long ctrl; @@ -630,18 +466,22 @@ static void versatile_clcd_disable(struct clcd_fb *fb) */ static void versatile_clcd_enable(struct clcd_fb *fb) { + struct fb_var_screeninfo *var = &fb->fb.var; void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET; u32 val; val = readl(sys_clcd); val &= ~SYS_CLCD_MODE_MASK; - switch (fb->fb.var.green.length) { + switch (var->green.length) { case 5: val |= SYS_CLCD_MODE_5551; break; case 6: - val |= SYS_CLCD_MODE_565_RLSB; + if (var->red.offset == 0) + val |= SYS_CLCD_MODE_565_RLSB; + else + val |= SYS_CLCD_MODE_565_BLSB; break; case 8: val |= SYS_CLCD_MODE_888; @@ -663,7 +503,7 @@ static void versatile_clcd_enable(struct clcd_fb *fb) /* * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on */ - if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) { + if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) { void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL); unsigned long ctrl; @@ -674,50 +514,62 @@ static void versatile_clcd_enable(struct clcd_fb *fb) #endif } -static unsigned long framesize = SZ_1M; - +/* + * Detect which LCD panel is connected, and return the appropriate + * clcd_panel structure. Note: we do not have any information on + * the required timings for the 8.4in panel, so we presently assume + * VGA timings. + */ static int versatile_clcd_setup(struct clcd_fb *fb) { - dma_addr_t dma; + void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET; + const char *panel_name; + u32 val; - fb->panel = versatile_clcd_panel(); + is_sanyo_2_5_lcd = false; - fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, - &dma, GFP_KERNEL); - if (!fb->fb.screen_base) { - printk(KERN_ERR "CLCD: unable to map framebuffer\n"); - return -ENOMEM; + val = readl(sys_clcd) & SYS_CLCD_ID_MASK; + if (val == SYS_CLCD_ID_SANYO_3_8) + panel_name = "Sanyo TM38QV67A02A"; + else if (val == SYS_CLCD_ID_SANYO_2_5) { + panel_name = "Sanyo QVGA Portrait"; + is_sanyo_2_5_lcd = true; + } else if (val == SYS_CLCD_ID_EPSON_2_2) + panel_name = "Epson L2F50113T00"; + else if (val == SYS_CLCD_ID_VGA) + panel_name = "VGA"; + else { + printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n", + val); + panel_name = "VGA"; } - fb->fb.fix.smem_start = dma; - fb->fb.fix.smem_len = framesize; + fb->panel = versatile_clcd_get_panel(panel_name); + if (!fb->panel) + return -EINVAL; - return 0; + return versatile_clcd_setup_dma(fb, SZ_1M); } -static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) +static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs) { - return dma_mmap_writecombine(&fb->dev->dev, vma, - fb->fb.screen_base, - fb->fb.fix.smem_start, - fb->fb.fix.smem_len); -} + clcdfb_decode(fb, regs); -static void versatile_clcd_remove(struct clcd_fb *fb) -{ - dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, - fb->fb.screen_base, fb->fb.fix.smem_start); + /* Always clear BGR for RGB565: we do the routing externally */ + if (fb->fb.var.green.length == 6) + regs->cntl &= ~CNTL_BGR; } static struct clcd_board clcd_plat_data = { .name = "Versatile", + .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888, .check = clcdfb_check, - .decode = clcdfb_decode, + .decode = versatile_clcd_decode, .disable = versatile_clcd_disable, .enable = versatile_clcd_enable, .setup = versatile_clcd_setup, - .mmap = versatile_clcd_mmap, - .remove = versatile_clcd_remove, + .mmap = versatile_clcd_mmap_dma, + .remove = versatile_clcd_remove_dma, }; static struct pl061_platform_data gpio0_plat_data = { @@ -737,53 +589,35 @@ static struct pl022_ssp_controller ssp0_plat_data = { }; #define AACI_IRQ { IRQ_AACI, NO_IRQ } -#define AACI_DMA { 0x80, 0x81 } #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B } -#define MMCI0_DMA { 0x84, 0 } #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ } -#define KMI0_DMA { 0, 0 } #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ } -#define KMI1_DMA { 0, 0 } /* * These devices are connected directly to the multi-layer AHB switch */ #define SMC_IRQ { NO_IRQ, NO_IRQ } -#define SMC_DMA { 0, 0 } #define MPMC_IRQ { NO_IRQ, NO_IRQ } -#define MPMC_DMA { 0, 0 } #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ } -#define CLCD_DMA { 0, 0 } #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ } -#define DMAC_DMA { 0, 0 } /* * These devices are connected via the core APB bridge */ #define SCTL_IRQ { NO_IRQ, NO_IRQ } -#define SCTL_DMA { 0, 0 } #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ } -#define WATCHDOG_DMA { 0, 0 } #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ } -#define GPIO0_DMA { 0, 0 } #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ } -#define GPIO1_DMA { 0, 0 } #define RTC_IRQ { IRQ_RTCINT, NO_IRQ } -#define RTC_DMA { 0, 0 } /* * These devices are connected via the DMA APB bridge */ #define SCI_IRQ { IRQ_SCIINT, NO_IRQ } -#define SCI_DMA { 7, 6 } #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ } -#define UART0_DMA { 15, 14 } #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ } -#define UART1_DMA { 13, 12 } #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ } -#define UART2_DMA { 11, 10 } #define SSP_IRQ { IRQ_SSPINT, NO_IRQ } -#define SSP_DMA { 9, 8 } /* FPGA Primecells */ AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); @@ -865,14 +699,21 @@ static void versatile_leds_event(led_event_t ledevt) } #endif /* CONFIG_LEDS */ -void __init versatile_init(void) +/* Early initializations */ +void __init versatile_init_early(void) { - int i; - - osc4_clk.vcoreg = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSCCLCD_OFFSET; + void __iomem *sys = __io_address(VERSATILE_SYS_BASE); + osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET; clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000); +} + +void __init versatile_init(void) +{ + int i; + platform_device_register(&versatile_flash_device); platform_device_register(&versatile_i2c_device); platform_device_register(&smc91x_device); @@ -889,12 +730,6 @@ void __init versatile_init(void) } /* - * The sched_clock counter - */ -#define REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + \ - VERSATILE_SYS_24MHz_OFFSET) - -/* * Where is the timer (VA)? */ #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE) @@ -909,8 +744,6 @@ static void __init versatile_timer_init(void) { u32 val; - versatile_sched_clock_init(REFCOUNTER, 24000000); - /* * set clock frequency: * VERSATILE_REFCLK is 32KHz diff --git a/arch/arm/mach-versatile/core.h b/arch/arm/mach-versatile/core.h index 9d39886a835..fd6404e5d78 100644 --- a/arch/arm/mach-versatile/core.h +++ b/arch/arm/mach-versatile/core.h @@ -25,6 +25,7 @@ #include <linux/amba/bus.h> extern void __init versatile_init(void); +extern void __init versatile_init_early(void); extern void __init versatile_init_irq(void); extern void __init versatile_map_io(void); extern struct sys_timer versatile_timer; @@ -44,7 +45,6 @@ static struct amba_device name##_device = { \ }, \ .dma_mask = ~0, \ .irq = base##_IRQ, \ - /* .dma = base##_DMA,*/ \ } #endif diff --git a/arch/arm/mach-versatile/include/mach/hardware.h b/arch/arm/mach-versatile/include/mach/hardware.h index b5e75bb4496..6911e1f5f15 100644 --- a/arch/arm/mach-versatile/include/mach/hardware.h +++ b/arch/arm/mach-versatile/include/mach/hardware.h @@ -39,6 +39,6 @@ /* macro to get at IO space when running virtually */ #define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) -#define __io_address(n) __io(IO_ADDRESS(n)) +#define __io_address(n) ((void __iomem __force *)IO_ADDRESS(n)) #endif diff --git a/arch/arm/mach-versatile/versatile_ab.c b/arch/arm/mach-versatile/versatile_ab.c index aa9730fb13b..f8ae64b3eed 100644 --- a/arch/arm/mach-versatile/versatile_ab.c +++ b/arch/arm/mach-versatile/versatile_ab.c @@ -37,6 +37,7 @@ MACHINE_START(VERSATILE_AB, "ARM-Versatile AB") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ .boot_params = 0x00000100, .map_io = versatile_map_io, + .init_early = versatile_init_early, .init_irq = versatile_init_irq, .timer = &versatile_timer, .init_machine = versatile_init, diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c index bf469642a3f..37c23dfeefb 100644 --- a/arch/arm/mach-versatile/versatile_pb.c +++ b/arch/arm/mach-versatile/versatile_pb.c @@ -59,19 +59,14 @@ static struct pl061_platform_data gpio3_plat_data = { }; #define UART3_IRQ { IRQ_SIC_UART3, NO_IRQ } -#define UART3_DMA { 0x86, 0x87 } #define SCI1_IRQ { IRQ_SIC_SCI3, NO_IRQ } -#define SCI1_DMA { 0x88, 0x89 } #define MMCI1_IRQ { IRQ_MMCI1A, IRQ_SIC_MMCI1B } -#define MMCI1_DMA { 0x85, 0 } /* * These devices are connected via the core APB bridge */ #define GPIO2_IRQ { IRQ_GPIOINT2, NO_IRQ } -#define GPIO2_DMA { 0, 0 } #define GPIO3_IRQ { IRQ_GPIOINT3, NO_IRQ } -#define GPIO3_DMA { 0, 0 } /* * These devices are connected via the DMA APB bridge @@ -110,6 +105,7 @@ MACHINE_START(VERSATILE_PB, "ARM-Versatile PB") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ .boot_params = 0x00000100, .map_io = versatile_map_io, + .init_early = versatile_init_early, .init_irq = versatile_init_irq, .timer = &versatile_timer, .init_machine = versatile_pb_init, diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index 3f19b660a16..931148487f0 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig @@ -5,5 +5,8 @@ config ARCH_VEXPRESS_CA9X4 bool "Versatile Express Cortex-A9x4 tile" select CPU_V7 select ARM_GIC + select ARM_ERRATA_720789 + select ARM_ERRATA_751472 + select ARM_ERRATA_753970 endmenu diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile index 2c0ac7de281..90551b9780a 100644 --- a/arch/arm/mach-vexpress/Makefile +++ b/arch/arm/mach-vexpress/Makefile @@ -4,6 +4,5 @@ obj-y := v2m.o obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o -obj-$(CONFIG_SMP) += platsmp.o headsmp.o +obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h index 362780d868d..f4397159c17 100644 --- a/arch/arm/mach-vexpress/core.h +++ b/arch/arm/mach-vexpress/core.h @@ -17,8 +17,3 @@ struct amba_device name##_device = { \ .irq = IRQ_##base, \ /* .dma = DMA_##base,*/ \ } - -struct map_desc; - -void v2m_map_io(struct map_desc *tile, size_t num); -extern struct sys_timer v2m_timer; diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c index e9bccc5230c..ebc22e75932 100644 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c @@ -10,19 +10,17 @@ #include <linux/amba/clcd.h> #include <linux/clkdev.h> -#include <asm/pgtable.h> #include <asm/hardware/arm_timer.h> #include <asm/hardware/cache-l2x0.h> #include <asm/hardware/gic.h> -#include <asm/mach-types.h> #include <asm/pmu.h> +#include <asm/smp_scu.h> #include <asm/smp_twd.h> #include <mach/ct-ca9x4.h> #include <asm/hardware/timer-sp.h> -#include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/time.h> @@ -30,6 +28,8 @@ #include <mach/motherboard.h> +#include <plat/clcd.h> + #define V2M_PA_CS7 0x10000000 static struct map_desc ct_ca9x4_io_desc[] __initdata = { @@ -56,7 +56,7 @@ static void __init ct_ca9x4_map_io(void) #ifdef CONFIG_LOCAL_TIMERS twd_base = MMIO_P2V(A9_MPCORE_TWD); #endif - v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc)); + iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc)); } static void __init ct_ca9x4_init_irq(void) @@ -80,29 +80,6 @@ static struct sys_timer ct_ca9x4_timer = { }; #endif -static struct clcd_panel xvga_panel = { - .mode = { - .name = "XVGA", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15384, - .left_margin = 168, - .right_margin = 8, - .upper_margin = 29, - .lower_margin = 3, - .hsync_len = 144, - .vsync_len = 6, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_BCD | TIM2_IPC, - .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), - .bpp = 16, -}; - static void ct_ca9x4_clcd_enable(struct clcd_fb *fb) { v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0); @@ -112,42 +89,23 @@ static void ct_ca9x4_clcd_enable(struct clcd_fb *fb) static int ct_ca9x4_clcd_setup(struct clcd_fb *fb) { unsigned long framesize = 1024 * 768 * 2; - dma_addr_t dma; - fb->panel = &xvga_panel; + fb->panel = versatile_clcd_get_panel("XVGA"); + if (!fb->panel) + return -EINVAL; - fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, - &dma, GFP_KERNEL); - if (!fb->fb.screen_base) { - printk(KERN_ERR "CLCD: unable to map frame buffer\n"); - return -ENOMEM; - } - fb->fb.fix.smem_start = dma; - fb->fb.fix.smem_len = framesize; - - return 0; -} - -static int ct_ca9x4_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) -{ - return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base, - fb->fb.fix.smem_start, fb->fb.fix.smem_len); -} - -static void ct_ca9x4_clcd_remove(struct clcd_fb *fb) -{ - dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, - fb->fb.screen_base, fb->fb.fix.smem_start); + return versatile_clcd_setup_dma(fb, framesize); } static struct clcd_board ct_ca9x4_clcd_data = { .name = "CT-CA9X4", + .caps = CLCD_CAP_5551 | CLCD_CAP_565, .check = clcdfb_check, .decode = clcdfb_decode, .enable = ct_ca9x4_clcd_enable, .setup = ct_ca9x4_clcd_setup, - .mmap = ct_ca9x4_clcd_mmap, - .remove = ct_ca9x4_clcd_remove, + .mmap = versatile_clcd_mmap_dma, + .remove = versatile_clcd_remove_dma, }; static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data); @@ -220,6 +178,11 @@ static struct platform_device pmu_device = { .resource = pmu_resources, }; +static void __init ct_ca9x4_init_early(void) +{ + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); +} + static void __init ct_ca9x4_init(void) { int i; @@ -234,22 +197,40 @@ static void __init ct_ca9x4_init(void) l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff); #endif - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++) amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource); platform_device_register(&pmu_device); } -MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4") - .boot_params = PLAT_PHYS_OFFSET + 0x00000100, +#ifdef CONFIG_SMP +static void ct_ca9x4_init_cpu_map(void) +{ + int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU)); + + for (i = 0; i < ncores; ++i) + set_cpu_possible(i, true); +} + +static void ct_ca9x4_smp_enable(unsigned int max_cpus) +{ + int i; + for (i = 0; i < max_cpus; i++) + set_cpu_present(i, true); + + scu_enable(MMIO_P2V(A9_MPCORE_SCU)); +} +#endif + +struct ct_desc ct_ca9x4_desc __initdata = { + .id = V2M_CT_ID_CA9, + .name = "CA9x4", .map_io = ct_ca9x4_map_io, + .init_early = ct_ca9x4_init_early, .init_irq = ct_ca9x4_init_irq, -#if 0 - .timer = &ct_ca9x4_timer, -#else - .timer = &v2m_timer, + .init_tile = ct_ca9x4_init, +#ifdef CONFIG_SMP + .init_cpu_map = ct_ca9x4_init_cpu_map, + .smp_enable = ct_ca9x4_smp_enable, #endif - .init_machine = ct_ca9x4_init, -MACHINE_END +}; diff --git a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h index f9e2f8d2296..a34d3d4faae 100644 --- a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h +++ b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h @@ -45,4 +45,6 @@ #define IRQ_CT_CA9X4_PMU_CPU2 94 #define IRQ_CT_CA9X4_PMU_CPU3 95 +extern struct ct_desc ct_ca9x4_desc; + #endif diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h index 98a8ded055b..0a3a3751840 100644 --- a/arch/arm/mach-vexpress/include/mach/motherboard.h +++ b/arch/arm/mach-vexpress/include/mach/motherboard.h @@ -118,4 +118,26 @@ int v2m_cfg_write(u32 devfn, u32 data); int v2m_cfg_read(u32 devfn, u32 *data); +/* + * Core tile IDs + */ +#define V2M_CT_ID_CA9 0x0c000191 +#define V2M_CT_ID_UNSUPPORTED 0xff000191 +#define V2M_CT_ID_MASK 0xff000fff + +struct ct_desc { + u32 id; + const char *name; + void (*map_io)(void); + void (*init_early)(void); + void (*init_irq)(void); + void (*init_tile)(void); +#ifdef CONFIG_SMP + void (*init_cpu_map)(void); + void (*smp_enable)(unsigned int); +#endif +}; + +extern struct ct_desc *ct_desc; + #endif diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c index 634bf1d3a31..2b5f7ac001a 100644 --- a/arch/arm/mach-vexpress/platsmp.c +++ b/arch/arm/mach-vexpress/platsmp.c @@ -10,114 +10,17 @@ */ #include <linux/init.h> #include <linux/errno.h> -#include <linux/delay.h> -#include <linux/device.h> -#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <asm/cacheflush.h> -#include <asm/smp_scu.h> #include <asm/unified.h> -#include <mach/ct-ca9x4.h> #include <mach/motherboard.h> #define V2M_PA_CS7 0x10000000 #include "core.h" -extern void vexpress_secondary_startup(void); - -/* - * control for which core is the next to come out of the secondary - * boot "holding pen" - */ -volatile int __cpuinitdata pen_release = -1; - -/* - * Write pen_release in a way that is guaranteed to be visible to all - * observers, irrespective of whether they're taking part in coherency - * or not. This is necessary for the hotplug code to work reliably. - */ -static void __cpuinit write_pen_release(int val) -{ - pen_release = val; - smp_wmb(); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); -} - -static void __iomem *scu_base_addr(void) -{ - return MMIO_P2V(A9_MPCORE_SCU); -} - -static DEFINE_SPINLOCK(boot_lock); - -void __cpuinit platform_secondary_init(unsigned int cpu) -{ - /* - * if any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - gic_secondary_init(0); - - /* - * let the primary processor know we're out of the - * pen, then head off into the C entry point - */ - write_pen_release(-1); - - /* - * Synchronise with the boot thread. - */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); -} - -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - unsigned long timeout; - - /* - * Set synchronisation state between this boot processor - * and the secondary one - */ - spin_lock(&boot_lock); - - /* - * This is really belt and braces; we hold unintended secondary - * CPUs in the holding pen until we're ready for them. However, - * since we haven't sent them a soft interrupt, they shouldn't - * be there. - */ - write_pen_release(cpu); - - /* - * Send the secondary CPU a soft interrupt, thereby causing - * the boot monitor to read the system wide flags register, - * and branch to the address found there. - */ - smp_cross_call(cpumask_of(cpu), 1); - - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) { - smp_rmb(); - if (pen_release == -1) - break; - - udelay(10); - } - - /* - * now the secondary core is starting up let it run its - * calibrations, then wait for it to finish - */ - spin_unlock(&boot_lock); - - return pen_release != -1 ? -ENOSYS : 0; -} +extern void versatile_secondary_startup(void); /* * Initialise the CPU possible map early - this describes the CPUs @@ -125,36 +28,16 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) */ void __init smp_init_cpus(void) { - void __iomem *scu_base = scu_base_addr(); - unsigned int i, ncores; - - ncores = scu_base ? scu_get_core_count(scu_base) : 1; - - /* sanity check */ - if (ncores > NR_CPUS) { - printk(KERN_WARNING - "vexpress: no. of cores (%d) greater than configured " - "maximum of %d - clipping\n", - ncores, NR_CPUS); - ncores = NR_CPUS; - } - - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); + ct_desc->init_cpu_map(); } void __init platform_smp_prepare_cpus(unsigned int max_cpus) { - int i; - /* * Initialise the present map, which describes the set of CPUs * actually populated at the present time. */ - for (i = 0; i < max_cpus; i++) - set_cpu_present(i, true); - - scu_enable(scu_base_addr()); + ct_desc->smp_enable(max_cpus); /* * Write the address of secondary startup into the @@ -163,6 +46,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) * secondary CPU branches to this address. */ writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR)); - writel(BSYM(virt_to_phys(vexpress_secondary_startup)), + writel(BSYM(virt_to_phys(versatile_secondary_startup)), MMIO_P2V(V2M_SYS_FLAGSSET)); } diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index 1edae65a0e7..ba46e8e0743 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -7,13 +7,16 @@ #include <linux/io.h> #include <linux/init.h> #include <linux/platform_device.h> +#include <linux/ata_platform.h> #include <linux/smsc911x.h> #include <linux/spinlock.h> #include <linux/sysdev.h> #include <linux/usb/isp1760.h> #include <linux/clkdev.h> +#include <asm/mach-types.h> #include <asm/sizes.h> +#include <asm/mach/arch.h> #include <asm/mach/flash.h> #include <asm/mach/map.h> #include <asm/mach/time.h> @@ -21,6 +24,7 @@ #include <asm/hardware/timer-sp.h> #include <asm/hardware/sp810.h> +#include <mach/ct-ca9x4.h> #include <mach/motherboard.h> #include <plat/sched_clock.h> @@ -42,19 +46,16 @@ static struct map_desc v2m_io_desc[] __initdata = { }, }; -void __init v2m_map_io(struct map_desc *tile, size_t num) +static void __init v2m_init_early(void) { - iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc)); - iotable_init(tile, num); + ct_desc->init_early(); + versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000); } - static void __init v2m_timer_init(void) { u32 scctrl; - versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000); - /* Select 1MHz TIMCLK as the reference clock for SP804 timers */ scctrl = readl(MMIO_P2V(V2M_SYSCTL + SCCTRL)); scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK; @@ -68,7 +69,7 @@ static void __init v2m_timer_init(void) sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0); } -struct sys_timer v2m_timer = { +static struct sys_timer v2m_timer = { .init = v2m_timer_init, }; @@ -249,6 +250,29 @@ static struct platform_device v2m_flash_device = { .dev.platform_data = &v2m_flash_data, }; +static struct pata_platform_info v2m_pata_data = { + .ioport_shift = 2, +}; + +static struct resource v2m_pata_resources[] = { + { + .start = V2M_CF, + .end = V2M_CF + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = V2M_CF + 0x100, + .end = V2M_CF + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device v2m_cf_device = { + .name = "pata_platform", + .id = -1, + .resource = v2m_pata_resources, + .num_resources = ARRAY_SIZE(v2m_pata_resources), + .dev.platform_data = &v2m_pata_data, +}; static unsigned int v2m_mmci_status(struct device *dev) { @@ -354,7 +378,44 @@ static void v2m_restart(char str, const char *cmd) printk(KERN_EMERG "Unable to reboot\n"); } -static int __init v2m_init(void) +struct ct_desc *ct_desc; + +static struct ct_desc *ct_descs[] __initdata = { +#ifdef CONFIG_ARCH_VEXPRESS_CA9X4 + &ct_ca9x4_desc, +#endif +}; + +static void __init v2m_populate_ct_desc(void) +{ + int i; + u32 current_tile_id; + + ct_desc = NULL; + current_tile_id = readl(MMIO_P2V(V2M_SYS_PROCID0)) & V2M_CT_ID_MASK; + + for (i = 0; i < ARRAY_SIZE(ct_descs) && !ct_desc; ++i) + if (ct_descs[i]->id == current_tile_id) + ct_desc = ct_descs[i]; + + if (!ct_desc) + panic("vexpress: failed to populate core tile description " + "for tile ID 0x%8x\n", current_tile_id); +} + +static void __init v2m_map_io(void) +{ + iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc)); + v2m_populate_ct_desc(); + ct_desc->map_io(); +} + +static void __init v2m_init_irq(void) +{ + ct_desc->init_irq(); +} + +static void __init v2m_init(void) { int i; @@ -363,6 +424,7 @@ static int __init v2m_init(void) platform_device_register(&v2m_pcie_i2c_device); platform_device_register(&v2m_ddc_i2c_device); platform_device_register(&v2m_flash_device); + platform_device_register(&v2m_cf_device); platform_device_register(&v2m_eth_device); platform_device_register(&v2m_usb_device); @@ -372,6 +434,14 @@ static int __init v2m_init(void) pm_power_off = v2m_power_off; arm_pm_restart = v2m_restart; - return 0; + ct_desc->init_tile(); } -arch_initcall(v2m_init); + +MACHINE_START(VEXPRESS, "ARM-Versatile Express") + .boot_params = PLAT_PHYS_OFFSET + 0x00000100, + .map_io = v2m_map_io, + .init_early = v2m_init_early, + .init_irq = v2m_init_irq, + .timer = &v2m_timer, + .init_machine = v2m_init, +MACHINE_END diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c index 5f4ddde4f02..245140c0df1 100644 --- a/arch/arm/mach-vt8500/irq.c +++ b/arch/arm/mach-vt8500/irq.c @@ -97,15 +97,15 @@ static int vt8500_irq_set_type(unsigned int irq, unsigned int flow_type) return -EINVAL; case IRQF_TRIGGER_HIGH: dctr |= VT8500_TRIGGER_HIGH; - irq_desc[orig_irq].handle_irq = handle_level_irq; + __irq_set_handler_locked(orig_irq, handle_level_irq); break; case IRQF_TRIGGER_FALLING: dctr |= VT8500_TRIGGER_FALLING; - irq_desc[orig_irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(orig_irq, handle_edge_irq); break; case IRQF_TRIGGER_RISING: dctr |= VT8500_TRIGGER_RISING; - irq_desc[orig_irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(orig_irq, handle_edge_irq); break; } writeb(dctr, base + VT8500_IC_DCTR + irq); @@ -136,8 +136,8 @@ void __init vt8500_init_irq(void) /* Disable all interrupts and route them to IRQ */ writeb(0x00, ic_regbase + VT8500_IC_DCTR + i); - set_irq_chip(i, &vt8500_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &vt8500_irq_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } } else { @@ -167,8 +167,8 @@ void __init wm8505_init_irq(void) writeb(0x00, sic_regbase + VT8500_IC_DCTR + i - 64); - set_irq_chip(i, &vt8500_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &vt8500_irq_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } } else { diff --git a/arch/arm/mach-w90x900/irq.c b/arch/arm/mach-w90x900/irq.c index 9c350103dcd..7bf143c443f 100644 --- a/arch/arm/mach-w90x900/irq.c +++ b/arch/arm/mach-w90x900/irq.c @@ -207,8 +207,8 @@ void __init nuc900_init_irq(void) __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) { - set_irq_chip(irqno, &nuc900_irq_chip); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &nuc900_irq_chip, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } } diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S index d3644db467b..f40c69656d8 100644 --- a/arch/arm/mm/cache-v4wb.S +++ b/arch/arm/mm/cache-v4wb.S @@ -32,7 +32,7 @@ /* * This is the size at which it becomes more efficient to * clean the whole cache, rather than using the individual - * cache line maintainence instructions. + * cache line maintenance instructions. * * Size Clean (ticks) Dirty (ticks) * 4096 21 20 21 53 55 54 diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S index 49c2b66cf3d..a7b276dbda1 100644 --- a/arch/arm/mm/cache-v4wt.S +++ b/arch/arm/mm/cache-v4wt.S @@ -34,7 +34,7 @@ /* * This is the size at which it becomes more efficient to * clean the whole cache, rather than using the individual - * cache line maintainence instructions. + * cache line maintenance instructions. * * *** This needs benchmarking */ diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 6136e68ce95..dc18d81ef8c 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -96,7 +96,7 @@ ENDPROC(v7_flush_dcache_all) * Flush the entire cache system. * The data cache flush is now achieved using atomic clean / invalidates * working outwards from L1 cache. This is done using Set/Way based cache - * maintainance instructions. + * maintenance instructions. * The instruction cache can still be invalidated back to the point of * unification in a single instruction. * diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 4771dba6144..82a093cee09 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -149,6 +149,7 @@ static int __init consistent_init(void) { int ret = 0; pgd_t *pgd; + pud_t *pud; pmd_t *pmd; pte_t *pte; int i = 0; @@ -156,7 +157,15 @@ static int __init consistent_init(void) do { pgd = pgd_offset(&init_mm, base); - pmd = pmd_alloc(&init_mm, pgd, base); + + pud = pud_alloc(&init_mm, pgd, base); + if (!pud) { + printk(KERN_ERR "%s: no pud tables\n", __func__); + ret = -ENOMEM; + break; + } + + pmd = pmd_alloc(&init_mm, pud, base); if (!pmd) { printk(KERN_ERR "%s: no pmd tables\n", __func__); ret = -ENOMEM; diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c index 01210dba022..7cab7917942 100644 --- a/arch/arm/mm/fault-armv.c +++ b/arch/arm/mm/fault-armv.c @@ -95,6 +95,7 @@ static int adjust_pte(struct vm_area_struct *vma, unsigned long address, { spinlock_t *ptl; pgd_t *pgd; + pud_t *pud; pmd_t *pmd; pte_t *pte; int ret; @@ -103,7 +104,11 @@ static int adjust_pte(struct vm_area_struct *vma, unsigned long address, if (pgd_none_or_clear_bad(pgd)) return 0; - pmd = pmd_offset(pgd, address); + pud = pud_offset(pgd, address); + if (pud_none_or_clear_bad(pud)) + return 0; + + pmd = pmd_offset(pud, address); if (pmd_none_or_clear_bad(pmd)) return 0; diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index f10f9bac220..bc0e1d88fd3 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -76,9 +76,11 @@ void show_pte(struct mm_struct *mm, unsigned long addr) printk(KERN_ALERT "pgd = %p\n", mm->pgd); pgd = pgd_offset(mm, addr); - printk(KERN_ALERT "[%08lx] *pgd=%08lx", addr, pgd_val(*pgd)); + printk(KERN_ALERT "[%08lx] *pgd=%08llx", + addr, (long long)pgd_val(*pgd)); do { + pud_t *pud; pmd_t *pmd; pte_t *pte; @@ -90,9 +92,21 @@ void show_pte(struct mm_struct *mm, unsigned long addr) break; } - pmd = pmd_offset(pgd, addr); + pud = pud_offset(pgd, addr); + if (PTRS_PER_PUD != 1) + printk(", *pud=%08lx", pud_val(*pud)); + + if (pud_none(*pud)) + break; + + if (pud_bad(*pud)) { + printk("(bad)"); + break; + } + + pmd = pmd_offset(pud, addr); if (PTRS_PER_PMD != 1) - printk(", *pmd=%08lx", pmd_val(*pmd)); + printk(", *pmd=%08llx", (long long)pmd_val(*pmd)); if (pmd_none(*pmd)) break; @@ -107,8 +121,9 @@ void show_pte(struct mm_struct *mm, unsigned long addr) break; pte = pte_offset_map(pmd, addr); - printk(", *pte=%08lx", pte_val(*pte)); - printk(", *ppte=%08lx", pte_val(pte[PTE_HWTABLE_PTRS])); + printk(", *pte=%08llx", (long long)pte_val(*pte)); + printk(", *ppte=%08llx", + (long long)pte_val(pte[PTE_HWTABLE_PTRS])); pte_unmap(pte); } while(0); @@ -388,6 +403,7 @@ do_translation_fault(unsigned long addr, unsigned int fsr, { unsigned int index; pgd_t *pgd, *pgd_k; + pud_t *pud, *pud_k; pmd_t *pmd, *pmd_k; if (addr < TASK_SIZE) @@ -406,12 +422,19 @@ do_translation_fault(unsigned long addr, unsigned int fsr, if (pgd_none(*pgd_k)) goto bad_area; - if (!pgd_present(*pgd)) set_pgd(pgd, *pgd_k); - pmd_k = pmd_offset(pgd_k, addr); - pmd = pmd_offset(pgd, addr); + pud = pud_offset(pgd, addr); + pud_k = pud_offset(pgd_k, addr); + + if (pud_none(*pud_k)) + goto bad_area; + if (!pud_present(*pud)) + set_pud(pud, *pud_k); + + pmd = pmd_offset(pud, addr); + pmd_k = pmd_offset(pud_k, addr); /* * On ARM one Linux PGD entry contains two hardware entries (see page diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c index 57299446f78..2be9139a4ef 100644 --- a/arch/arm/mm/idmap.c +++ b/arch/arm/mm/idmap.c @@ -4,10 +4,10 @@ #include <asm/pgalloc.h> #include <asm/pgtable.h> -static void idmap_add_pmd(pgd_t *pgd, unsigned long addr, unsigned long end, +static void idmap_add_pmd(pud_t *pud, unsigned long addr, unsigned long end, unsigned long prot) { - pmd_t *pmd = pmd_offset(pgd, addr); + pmd_t *pmd = pmd_offset(pud, addr); addr = (addr & PMD_MASK) | prot; pmd[0] = __pmd(addr); @@ -16,6 +16,18 @@ static void idmap_add_pmd(pgd_t *pgd, unsigned long addr, unsigned long end, flush_pmd_entry(pmd); } +static void idmap_add_pud(pgd_t *pgd, unsigned long addr, unsigned long end, + unsigned long prot) +{ + pud_t *pud = pud_offset(pgd, addr); + unsigned long next; + + do { + next = pud_addr_end(addr, end); + idmap_add_pmd(pud, addr, next, prot); + } while (pud++, addr = next, addr != end); +} + void identity_mapping_add(pgd_t *pgd, unsigned long addr, unsigned long end) { unsigned long prot, next; @@ -27,17 +39,28 @@ void identity_mapping_add(pgd_t *pgd, unsigned long addr, unsigned long end) pgd += pgd_index(addr); do { next = pgd_addr_end(addr, end); - idmap_add_pmd(pgd, addr, next, prot); + idmap_add_pud(pgd, addr, next, prot); } while (pgd++, addr = next, addr != end); } #ifdef CONFIG_SMP -static void idmap_del_pmd(pgd_t *pgd, unsigned long addr, unsigned long end) +static void idmap_del_pmd(pud_t *pud, unsigned long addr, unsigned long end) { - pmd_t *pmd = pmd_offset(pgd, addr); + pmd_t *pmd = pmd_offset(pud, addr); pmd_clear(pmd); } +static void idmap_del_pud(pgd_t *pgd, unsigned long addr, unsigned long end) +{ + pud_t *pud = pud_offset(pgd, addr); + unsigned long next; + + do { + next = pud_addr_end(addr, end); + idmap_del_pmd(pud, addr, next); + } while (pud++, addr = next, addr != end); +} + void identity_mapping_del(pgd_t *pgd, unsigned long addr, unsigned long end) { unsigned long next; @@ -45,7 +68,7 @@ void identity_mapping_del(pgd_t *pgd, unsigned long addr, unsigned long end) pgd += pgd_index(addr); do { next = pgd_addr_end(addr, end); - idmap_del_pmd(pgd, addr, next); + idmap_del_pud(pgd, addr, next); } while (pgd++, addr = next, addr != end); } #endif diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index cddd684364d..e591513bb53 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -78,7 +78,7 @@ __tagtable(ATAG_INITRD2, parse_tag_initrd2); */ struct meminfo meminfo; -void show_mem(void) +void show_mem(unsigned int filter) { int free = 0, total = 0, reserved = 0; int shared = 0, cached = 0, slab = 0, i; @@ -350,7 +350,7 @@ void __init bootmem_init(void) */ arm_bootmem_free(min, max_low, max_high); - high_memory = __va((max_low << PAGE_SHIFT) - 1) + 1; + high_memory = __va(((phys_addr_t)max_low << PAGE_SHIFT) - 1) + 1; /* * This doesn't seem to be used by the Linux memory manager any @@ -392,14 +392,14 @@ free_memmap(unsigned long start_pfn, unsigned long end_pfn) * Convert start_pfn/end_pfn to a struct page pointer. */ start_pg = pfn_to_page(start_pfn - 1) + 1; - end_pg = pfn_to_page(end_pfn); + end_pg = pfn_to_page(end_pfn - 1) + 1; /* * Convert to physical addresses, and * round start upwards and end downwards. */ - pg = PAGE_ALIGN(__pa(start_pg)); - pgend = __pa(end_pg) & PAGE_MASK; + pg = (unsigned long)PAGE_ALIGN(__pa(start_pg)); + pgend = (unsigned long)__pa(end_pg) & PAGE_MASK; /* * If there are free pages between these, @@ -426,6 +426,14 @@ static void __init free_unused_memmap(struct meminfo *mi) bank_start = bank_pfn_start(bank); +#ifdef CONFIG_SPARSEMEM + /* + * Take care not to free memmap entries that don't exist + * due to SPARSEMEM sections which aren't present. + */ + bank_start = min(bank_start, + ALIGN(prev_bank_end, PAGES_PER_SECTION)); +#endif /* * If we had a previous bank, and there is a space * between the current bank and the previous, free it. @@ -440,6 +448,12 @@ static void __init free_unused_memmap(struct meminfo *mi) */ prev_bank_end = ALIGN(bank_pfn_end(bank), MAX_ORDER_NR_PAGES); } + +#ifdef CONFIG_SPARSEMEM + if (!IS_ALIGNED(prev_bank_end, PAGES_PER_SECTION)) + free_memmap(prev_bank_end, + ALIGN(prev_bank_end, PAGES_PER_SECTION)); +#endif } static void __init free_highpages(void) diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h index 36960df5fb7..d2384106af9 100644 --- a/arch/arm/mm/mm.h +++ b/arch/arm/mm/mm.h @@ -7,7 +7,7 @@ extern pmd_t *top_pmd; static inline pmd_t *pmd_off(pgd_t *pgd, unsigned long virt) { - return pmd_offset(pgd, virt); + return pmd_offset(pud_offset(pgd, virt), virt); } static inline pmd_t *pmd_off_k(unsigned long virt) diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c index afe209e1e1f..74be05f3e03 100644 --- a/arch/arm/mm/mmap.c +++ b/arch/arm/mm/mmap.c @@ -7,6 +7,7 @@ #include <linux/shm.h> #include <linux/sched.h> #include <linux/io.h> +#include <linux/personality.h> #include <linux/random.h> #include <asm/cputype.h> #include <asm/system.h> @@ -82,7 +83,8 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr, mm->cached_hole_size = 0; } /* 8 bits of randomness in 20 address space bits */ - if (current->flags & PF_RANDOMIZE) + if ((current->flags & PF_RANDOMIZE) && + !(current->personality & ADDR_NO_RANDOMIZE)) addr += (get_random_int() % (1 << 8)) << PAGE_SHIFT; full_search: diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index ff7b43b5885..6cf76b3b68d 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -533,7 +533,7 @@ static void __init *early_alloc(unsigned long sz) static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot) { if (pmd_none(*pmd)) { - pte_t *pte = early_alloc(2 * PTRS_PER_PTE * sizeof(pte_t)); + pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); __pmd_populate(pmd, __pa(pte), prot); } BUG_ON(pmd_bad(*pmd)); @@ -551,11 +551,11 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, } while (pte++, addr += PAGE_SIZE, addr != end); } -static void __init alloc_init_section(pgd_t *pgd, unsigned long addr, +static void __init alloc_init_section(pud_t *pud, unsigned long addr, unsigned long end, phys_addr_t phys, const struct mem_type *type) { - pmd_t *pmd = pmd_offset(pgd, addr); + pmd_t *pmd = pmd_offset(pud, addr); /* * Try a section mapping - end, addr and phys must all be aligned @@ -584,6 +584,19 @@ static void __init alloc_init_section(pgd_t *pgd, unsigned long addr, } } +static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end, + unsigned long phys, const struct mem_type *type) +{ + pud_t *pud = pud_offset(pgd, addr); + unsigned long next; + + do { + next = pud_addr_end(addr, end); + alloc_init_section(pud, addr, next, phys, type); + phys += next - addr; + } while (pud++, addr = next, addr != end); +} + static void __init create_36bit_mapping(struct map_desc *md, const struct mem_type *type) { @@ -592,13 +605,13 @@ static void __init create_36bit_mapping(struct map_desc *md, pgd_t *pgd; addr = md->virtual; - phys = (unsigned long)__pfn_to_phys(md->pfn); + phys = __pfn_to_phys(md->pfn); length = PAGE_ALIGN(md->length); if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { printk(KERN_ERR "MM: CPU does not support supersection " "mapping for 0x%08llx at 0x%08lx\n", - __pfn_to_phys((u64)md->pfn), addr); + (long long)__pfn_to_phys((u64)md->pfn), addr); return; } @@ -611,14 +624,14 @@ static void __init create_36bit_mapping(struct map_desc *md, if (type->domain) { printk(KERN_ERR "MM: invalid domain in supersection " "mapping for 0x%08llx at 0x%08lx\n", - __pfn_to_phys((u64)md->pfn), addr); + (long long)__pfn_to_phys((u64)md->pfn), addr); return; } if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { - printk(KERN_ERR "MM: cannot create mapping for " - "0x%08llx at 0x%08lx invalid alignment\n", - __pfn_to_phys((u64)md->pfn), addr); + printk(KERN_ERR "MM: cannot create mapping for 0x%08llx" + " at 0x%08lx invalid alignment\n", + (long long)__pfn_to_phys((u64)md->pfn), addr); return; } @@ -631,7 +644,8 @@ static void __init create_36bit_mapping(struct map_desc *md, pgd = pgd_offset_k(addr); end = addr + length; do { - pmd_t *pmd = pmd_offset(pgd, addr); + pud_t *pud = pud_offset(pgd, addr); + pmd_t *pmd = pmd_offset(pud, addr); int i; for (i = 0; i < 16; i++) @@ -652,22 +666,23 @@ static void __init create_36bit_mapping(struct map_desc *md, */ static void __init create_mapping(struct map_desc *md) { - unsigned long phys, addr, length, end; + unsigned long addr, length, end; + phys_addr_t phys; const struct mem_type *type; pgd_t *pgd; if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { - printk(KERN_WARNING "BUG: not creating mapping for " - "0x%08llx at 0x%08lx in user region\n", - __pfn_to_phys((u64)md->pfn), md->virtual); + printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx" + " at 0x%08lx in user region\n", + (long long)__pfn_to_phys((u64)md->pfn), md->virtual); return; } if ((md->type == MT_DEVICE || md->type == MT_ROM) && md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) { - printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx " - "overlaps vmalloc space\n", - __pfn_to_phys((u64)md->pfn), md->virtual); + printk(KERN_WARNING "BUG: mapping for 0x%08llx" + " at 0x%08lx overlaps vmalloc space\n", + (long long)__pfn_to_phys((u64)md->pfn), md->virtual); } type = &mem_types[md->type]; @@ -681,13 +696,13 @@ static void __init create_mapping(struct map_desc *md) } addr = md->virtual & PAGE_MASK; - phys = (unsigned long)__pfn_to_phys(md->pfn); + phys = __pfn_to_phys(md->pfn); length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { - printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not " + printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not " "be mapped using pages, ignoring.\n", - __pfn_to_phys(md->pfn), addr); + (long long)__pfn_to_phys(md->pfn), addr); return; } @@ -696,7 +711,7 @@ static void __init create_mapping(struct map_desc *md) do { unsigned long next = pgd_addr_end(addr, end); - alloc_init_section(pgd, addr, next, phys, type); + alloc_init_pud(pgd, addr, next, phys, type); phys += next - addr; addr = next; @@ -794,9 +809,10 @@ static void __init sanity_check_meminfo(void) */ if (__va(bank->start) >= vmalloc_min || __va(bank->start) < (void *)PAGE_OFFSET) { - printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx " + printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx " "(vmalloc region overlap).\n", - bank->start, bank->start + bank->size - 1); + (unsigned long long)bank->start, + (unsigned long long)bank->start + bank->size - 1); continue; } @@ -807,10 +823,11 @@ static void __init sanity_check_meminfo(void) if (__va(bank->start + bank->size) > vmalloc_min || __va(bank->start + bank->size) < __va(bank->start)) { unsigned long newsize = vmalloc_min - __va(bank->start); - printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx " - "to -%.8lx (vmalloc region overlap).\n", - bank->start, bank->start + bank->size - 1, - bank->start + newsize - 1); + printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx " + "to -%.8llx (vmalloc region overlap).\n", + (unsigned long long)bank->start, + (unsigned long long)bank->start + bank->size - 1, + (unsigned long long)bank->start + newsize - 1); bank->size = newsize; } #endif diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c index 709244c66fa..b2027c154b2 100644 --- a/arch/arm/mm/pgd.c +++ b/arch/arm/mm/pgd.c @@ -23,6 +23,7 @@ pgd_t *pgd_alloc(struct mm_struct *mm) { pgd_t *new_pgd, *init_pgd; + pud_t *new_pud, *init_pud; pmd_t *new_pmd, *init_pmd; pte_t *new_pte, *init_pte; @@ -46,7 +47,11 @@ pgd_t *pgd_alloc(struct mm_struct *mm) * On ARM, first page must always be allocated since it * contains the machine vectors. */ - new_pmd = pmd_alloc(mm, new_pgd, 0); + new_pud = pud_alloc(mm, new_pgd, 0); + if (!new_pud) + goto no_pud; + + new_pmd = pmd_alloc(mm, new_pud, 0); if (!new_pmd) goto no_pmd; @@ -54,7 +59,8 @@ pgd_t *pgd_alloc(struct mm_struct *mm) if (!new_pte) goto no_pte; - init_pmd = pmd_offset(init_pgd, 0); + init_pud = pud_offset(init_pgd, 0); + init_pmd = pmd_offset(init_pud, 0); init_pte = pte_offset_map(init_pmd, 0); set_pte_ext(new_pte, *init_pte, 0); pte_unmap(init_pte); @@ -66,6 +72,8 @@ pgd_t *pgd_alloc(struct mm_struct *mm) no_pte: pmd_free(mm, new_pmd); no_pmd: + pud_free(mm, new_pud); +no_pud: free_pages((unsigned long)new_pgd, 2); no_pgd: return NULL; @@ -74,6 +82,7 @@ no_pgd: void pgd_free(struct mm_struct *mm, pgd_t *pgd_base) { pgd_t *pgd; + pud_t *pud; pmd_t *pmd; pgtable_t pte; @@ -84,7 +93,11 @@ void pgd_free(struct mm_struct *mm, pgd_t *pgd_base) if (pgd_none_or_clear_bad(pgd)) goto no_pgd; - pmd = pmd_offset(pgd, 0); + pud = pud_offset(pgd, 0); + if (pud_none_or_clear_bad(pud)) + goto no_pud; + + pmd = pmd_offset(pud, 0); if (pmd_none_or_clear_bad(pmd)) goto no_pmd; @@ -92,8 +105,11 @@ void pgd_free(struct mm_struct *mm, pgd_t *pgd_base) pmd_clear(pmd); pte_free(mm, pte); no_pmd: - pgd_clear(pgd); + pud_clear(pud); pmd_free(mm, pmd); +no_pud: + pgd_clear(pgd); + pud_free(mm, pud); no_pgd: free_pages((unsigned long) pgd_base, 2); } diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index 226e3d8351c..6c4e7fd6c8a 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S @@ -64,7 +64,7 @@ /* * This is the size at which it becomes more efficient to * clean the whole cache, rather than using the individual - * cache line maintainence instructions. + * cache line maintenance instructions. */ #define CACHE_DLIMIT 32768 diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index 86d9c2cf0bc..4ce947c1962 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S @@ -64,7 +64,7 @@ /* * This is the size at which it becomes more efficient to * clean the whole cache, rather than using the individual - * cache line maintainence instructions. + * cache line maintenance instructions. */ #define CACHE_DLIMIT 32768 diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index 83d3dd34f84..c8884c5413a 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S @@ -53,7 +53,7 @@ /* * This is the size at which it becomes more efficient to * clean the whole cache, rather than using the individual - * cache line maintainence instructions. + * cache line maintenance instructions. */ #define CACHE_DLIMIT 32768 diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index 686043ee728..413684660aa 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S @@ -53,7 +53,7 @@ /* * This is the size at which it becomes more efficient to * clean the whole cache, rather than using the individual - * cache line maintainence instructions. + * cache line maintenance instructions. */ #define CACHE_DLIMIT 32768 diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S index 665266da143..7a06e5964f5 100644 --- a/arch/arm/mm/proc-arm720.S +++ b/arch/arm/mm/proc-arm720.S @@ -63,7 +63,7 @@ ENTRY(cpu_arm720_proc_fin) /* * Function: arm720_proc_do_idle(void) * Params : r0 = unused - * Purpose : put the processer in proper idle mode + * Purpose : put the processor in proper idle mode */ ENTRY(cpu_arm720_do_idle) mov pc, lr diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 219980ec8b6..bf8a1d1cccb 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -53,7 +53,7 @@ /* * This is the size at which it becomes more efficient to * clean the whole cache, rather than using the individual - * cache line maintainence instructions. + * cache line maintenance instructions. */ #define CACHE_DLIMIT 65536 @@ -390,7 +390,7 @@ ENTRY(cpu_arm920_set_pte_ext) /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ .globl cpu_arm920_suspend_size .equ cpu_arm920_suspend_size, 4 * 3 -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP ENTRY(cpu_arm920_do_suspend) stmfd sp!, {r4 - r7, lr} mrc p15, 0, r4, c13, c0, 0 @ PID diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S index 36154b1e792..95ba1fc56e4 100644 --- a/arch/arm/mm/proc-arm922.S +++ b/arch/arm/mm/proc-arm922.S @@ -54,7 +54,7 @@ /* * This is the size at which it becomes more efficient to * clean the whole cache, rather than using the individual - * cache line maintainence instructions. (I think this should + * cache line maintenance instructions. (I think this should * be 32768). */ #define CACHE_DLIMIT 8192 diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index 89c5e0009c4..541e4774eea 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S @@ -77,7 +77,7 @@ /* * This is the size at which it becomes more efficient to * clean the whole cache, rather than using the individual - * cache line maintainence instructions. + * cache line maintenance instructions. */ #define CACHE_DLIMIT 8192 diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 6a4bdb2c94a..0ed85d930c0 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S @@ -404,7 +404,7 @@ ENTRY(cpu_arm926_set_pte_ext) /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ .globl cpu_arm926_suspend_size .equ cpu_arm926_suspend_size, 4 * 3 -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP ENTRY(cpu_arm926_do_suspend) stmfd sp!, {r4 - r7, lr} mrc p15, 0, r4, c13, c0, 0 @ PID diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index e32fa499194..34261f9486b 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -85,7 +85,7 @@ /* * Sanity check the PTE configuration for the code below - which makes - * certain assumptions about how these bits are layed out. + * certain assumptions about how these bits are laid out. */ #ifdef CONFIG_MMU #if L_PTE_SHARED != PTE_EXT_SHARED diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index 74483d1977f..184a9c997e3 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S @@ -171,7 +171,7 @@ ENTRY(cpu_sa1100_set_pte_ext) .globl cpu_sa1100_suspend_size .equ cpu_sa1100_suspend_size, 4*4 -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP ENTRY(cpu_sa1100_do_suspend) stmfd sp!, {r4 - r7, lr} mrc p15, 0, r4, c3, c0, 0 @ domain ID diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 832b6bdc192..7c99cb4c8e4 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -124,7 +124,7 @@ ENTRY(cpu_v6_set_pte_ext) /* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */ .globl cpu_v6_suspend_size .equ cpu_v6_suspend_size, 4 * 8 -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP ENTRY(cpu_v6_do_suspend) stmfd sp!, {r4 - r11, lr} mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID @@ -132,7 +132,7 @@ ENTRY(cpu_v6_do_suspend) mrc p15, 0, r6, c3, c0, 0 @ Domain ID mrc p15, 0, r7, c2, c0, 0 @ Translation table base 0 mrc p15, 0, r8, c2, c0, 1 @ Translation table base 1 - mrc p15, 0, r9, c1, c0, 1 @ auxillary control register + mrc p15, 0, r9, c1, c0, 1 @ auxiliary control register mrc p15, 0, r10, c1, c0, 2 @ co-processor access control mrc p15, 0, r11, c1, c0, 0 @ control register stmia r0, {r4 - r11} @@ -151,7 +151,7 @@ ENTRY(cpu_v6_do_resume) mcr p15, 0, r6, c3, c0, 0 @ Domain ID mcr p15, 0, r7, c2, c0, 0 @ Translation table base 0 mcr p15, 0, r8, c2, c0, 1 @ Translation table base 1 - mcr p15, 0, r9, c1, c0, 1 @ auxillary control register + mcr p15, 0, r9, c1, c0, 1 @ auxiliary control register mcr p15, 0, r10, c1, c0, 2 @ co-processor access control mcr p15, 0, ip, c2, c0, 2 @ TTB control register mcr p15, 0, ip, c7, c5, 4 @ ISB diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 262fa88a743..babfba09c89 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -211,7 +211,7 @@ cpu_v7_name: /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ .globl cpu_v7_suspend_size .equ cpu_v7_suspend_size, 4 * 8 -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP ENTRY(cpu_v7_do_suspend) stmfd sp!, {r4 - r11, lr} mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID @@ -237,7 +237,7 @@ ENTRY(cpu_v7_do_resume) mcr p15, 0, r7, c2, c0, 0 @ TTB 0 mcr p15, 0, r8, c2, c0, 1 @ TTB 1 mcr p15, 0, ip, c2, c0, 2 @ TTB control register - mcr p15, 0, r10, c1, c0, 1 @ Auxillary control register + mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control ldr r4, =PRRR @ PRRR ldr r5, =NMRR @ NMRR diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 63d8b2044e8..596213699f3 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -417,7 +417,7 @@ ENTRY(cpu_xsc3_set_pte_ext) .globl cpu_xsc3_suspend_size .equ cpu_xsc3_suspend_size, 4 * 8 -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP ENTRY(cpu_xsc3_do_suspend) stmfd sp!, {r4 - r10, lr} mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 086038cd86a..42af97664c9 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -395,7 +395,7 @@ ENTRY(xscale_dma_a0_map_area) teq r2, #DMA_TO_DEVICE beq xscale_dma_clean_range b xscale_dma_flush_range -ENDPROC(xscsale_dma_a0_map_area) +ENDPROC(xscale_dma_a0_map_area) /* * dma_unmap_area(start, size, dir) @@ -518,7 +518,7 @@ ENTRY(cpu_xscale_set_pte_ext) .globl cpu_xscale_suspend_size .equ cpu_xscale_suspend_size, 4 * 7 -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP ENTRY(cpu_xscale_do_suspend) stmfd sp!, {r4 - r10, lr} mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c index c856fa39760..f0ba0726306 100644 --- a/arch/arm/plat-mxc/3ds_debugboard.c +++ b/arch/arm/plat-mxc/3ds_debugboard.c @@ -100,14 +100,9 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) expio_irq = MXC_BOARD_IRQ_START; for (; int_valid != 0; int_valid >>= 1, expio_irq++) { - struct irq_desc *d; if ((int_valid & 1) == 0) continue; - d = irq_desc + expio_irq; - if (unlikely(!(d->handle_irq))) - pr_err("\nEXPIO irq: %d unhandled\n", expio_irq); - else - d->handle_irq(expio_irq, d); + generic_handle_irq(expio_irq); } desc->irq_data.chip->irq_ack(&desc->irq_data); @@ -186,12 +181,11 @@ int __init mxc_expio_init(u32 base, u32 p_irq) __raw_writew(0x1F, brd_io + INTR_MASK_REG); for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) { - set_irq_chip(i, &expio_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID); } - set_irq_type(p_irq, IRQF_TRIGGER_LOW); - set_irq_chained_handler(p_irq, mxc_expio_irq_handler); + irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW); + irq_set_chained_handler(p_irq, mxc_expio_irq_handler); /* Register Lan device on the debugboard */ smsc911x_resources[0].start = LAN9217_BASE_ADDR(base); diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c index deb284bc7c4..09e2bd0fcdc 100644 --- a/arch/arm/plat-mxc/avic.c +++ b/arch/arm/plat-mxc/avic.c @@ -139,8 +139,8 @@ void __init mxc_init_irq(void __iomem *irqbase) __raw_writel(0, avic_base + AVIC_INTTYPEH); __raw_writel(0, avic_base + AVIC_INTTYPEL); for (i = 0; i < MXC_INTERNAL_IRQS; i++) { - set_irq_chip(i, &mxc_avic_chip.base); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &mxc_avic_chip.base, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c index ce81481becf..4268a2bdf14 100644 --- a/arch/arm/plat-mxc/cpufreq.c +++ b/arch/arm/plat-mxc/cpufreq.c @@ -13,7 +13,7 @@ /* * A driver for the Freescale Semiconductor i.MXC CPUfreq module. - * The CPUFREQ driver is for controling CPU frequency. It allows you to change + * The CPUFREQ driver is for controlling CPU frequency. It allows you to change * the CPU clock speed on the fly. */ diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c index 6561c9df5f0..ccc789e21da 100644 --- a/arch/arm/plat-mxc/devices/platform-fec.c +++ b/arch/arm/plat-mxc/devices/platform-fec.c @@ -53,7 +53,7 @@ struct platform_device *__init imx_add_fec( struct resource res[] = { { .start = data->iobase, - .end = data->iobase + SZ_4K, + .end = data->iobase + SZ_4K - 1, .flags = IORESOURCE_MEM, }, { .start = data->irq, diff --git a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c index 10653cc8d1f..805336fdc25 100644 --- a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c +++ b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c @@ -27,7 +27,7 @@ struct platform_device *__init imx_add_imxdi_rtc( struct resource res[] = { { .start = data->iobase, - .end = data->iobase + SZ_16K, + .end = data->iobase + SZ_16K - 1, .flags = IORESOURCE_MEM, }, { .start = data->irq, diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 57d59855f9e..6cd6d7f686f 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -175,7 +175,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) { u32 irq_stat; - struct mxc_gpio_port *port = get_irq_data(irq); + struct mxc_gpio_port *port = irq_get_handler_data(irq); irq_stat = __raw_readl(port->base + GPIO_ISR) & __raw_readl(port->base + GPIO_IMR); @@ -188,7 +188,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) { int i; u32 irq_msk, irq_stat; - struct mxc_gpio_port *port = get_irq_data(irq); + struct mxc_gpio_port *port = irq_get_handler_data(irq); /* walk through all interrupt status registers */ for (i = 0; i < gpio_table_size; i++) { @@ -295,6 +295,12 @@ static int mxc_gpio_direction_output(struct gpio_chip *chip, return 0; } +/* + * This lock class tells lockdep that GPIO irqs are in a different + * category than their parents, so it won't report false recursion. + */ +static struct lock_class_key gpio_lock_class; + int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) { int i, j; @@ -311,8 +317,9 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) __raw_writel(~0, port[i].base + GPIO_ISR); for (j = port[i].virtual_irq_start; j < port[i].virtual_irq_start + 32; j++) { - set_irq_chip(j, &gpio_irq_chip); - set_irq_handler(j, handle_level_irq); + irq_set_lockdep_class(j, &gpio_lock_class); + irq_set_chip_and_handler(j, &gpio_irq_chip, + handle_level_irq); set_irq_flags(j, IRQF_VALID); } @@ -331,21 +338,23 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) { /* setup one handler for each entry */ - set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); - set_irq_data(port[i].irq, &port[i]); + irq_set_chained_handler(port[i].irq, + mx3_gpio_irq_handler); + irq_set_handler_data(port[i].irq, &port[i]); if (port[i].irq_high) { /* setup handler for GPIO 16 to 31 */ - set_irq_chained_handler(port[i].irq_high, - mx3_gpio_irq_handler); - set_irq_data(port[i].irq_high, &port[i]); + irq_set_chained_handler(port[i].irq_high, + mx3_gpio_irq_handler); + irq_set_handler_data(port[i].irq_high, + &port[i]); } } } if (cpu_is_mx2()) { /* setup one handler for all GPIO interrupts */ - set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler); - set_irq_data(port[0].irq, port); + irq_set_chained_handler(port[0].irq, mx2_gpio_irq_handler); + irq_set_handler_data(port[0].irq, port); } return 0; diff --git a/arch/arm/plat-mxc/include/mach/audmux.h b/arch/arm/plat-mxc/include/mach/audmux.h index 5cd6466964a..6fda788ed0e 100644 --- a/arch/arm/plat-mxc/include/mach/audmux.h +++ b/arch/arm/plat-mxc/include/mach/audmux.h @@ -15,6 +15,14 @@ #define MX31_AUDMUX_PORT5_SSI_PINS_5 4 #define MX31_AUDMUX_PORT6_SSI_PINS_6 5 +#define MX51_AUDMUX_PORT1_SSI0 0 +#define MX51_AUDMUX_PORT2_SSI1 1 +#define MX51_AUDMUX_PORT3 2 +#define MX51_AUDMUX_PORT4 3 +#define MX51_AUDMUX_PORT5 4 +#define MX51_AUDMUX_PORT6 5 +#define MX51_AUDMUX_PORT7 6 + /* Register definitions for the i.MX21/27 Digital Audio Multiplexer */ #define MXC_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff) #define MXC_AUDMUX_V1_PCR_INMEN (1 << 8) @@ -28,7 +36,7 @@ #define MXC_AUDMUX_V1_PCR_TCLKDIR (1 << 30) #define MXC_AUDMUX_V1_PCR_TFSDIR (1 << 31) -/* Register definitions for the i.MX25/31/35 Digital Audio Multiplexer */ +/* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */ #define MXC_AUDMUX_V2_PTCR_TFSDIR (1 << 31) #define MXC_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27) #define MXC_AUDMUX_V2_PTCR_TCLKDIR (1 << 26) diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S index bd9bb979914..2e49e71b1b9 100644 --- a/arch/arm/plat-mxc/include/mach/entry-macro.S +++ b/arch/arm/plat-mxc/include/mach/entry-macro.S @@ -33,9 +33,9 @@ .macro arch_ret_to_user, tmp1, tmp2 .endm - @ this macro checks which interrupt occured + @ this macro checks which interrupt occurred @ and returns its number in irqnr - @ and returns if an interrupt occured in irqstat + @ and returns if an interrupt occurred in irqstat .macro get_irqnr_and_base, irqnr, irqstat, base, tmp #ifndef CONFIG_MXC_TZIC @ Load offset & priority of the highest priority diff --git a/arch/arm/plat-mxc/include/mach/esdhc.h b/arch/arm/plat-mxc/include/mach/esdhc.h index a48a9aaa56b..86003f41175 100644 --- a/arch/arm/plat-mxc/include/mach/esdhc.h +++ b/arch/arm/plat-mxc/include/mach/esdhc.h @@ -10,7 +10,17 @@ #ifndef __ASM_ARCH_IMX_ESDHC_H #define __ASM_ARCH_IMX_ESDHC_H +/** + * struct esdhc_platform_data - optional platform data for esdhc on i.MX + * + * strongly recommended for i.MX25/35, not needed for other variants + * + * @wp_gpio: gpio for write_protect (-EINVAL if unused) + * @cd_gpio: gpio for card_detect interrupt (-EINVAL if unused) + */ + struct esdhc_platform_data { - unsigned int wp_gpio; /* write protect pin */ + unsigned int wp_gpio; + unsigned int cd_gpio; }; #endif /* __ASM_ARCH_IMX_ESDHC_H */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h index c4f116d214f..7a9b20abda0 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h @@ -90,12 +90,12 @@ #define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31) #define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) #define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) -#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19) -#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20) -#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21) -#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22) -#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23) -#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24) +#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19) +#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20) +#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21) +#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22) +#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 23) +#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24) #define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) #define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) #define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h index aaec2a6e7b3..5f2da75a47f 100644 --- a/arch/arm/plat-mxc/include/mach/mx50.h +++ b/arch/arm/plat-mxc/include/mach/mx50.h @@ -282,4 +282,8 @@ #define MX50_INT_APBHDMA_CHAN6 116 #define MX50_INT_APBHDMA_CHAN7 117 +#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) +extern int mx50_revision(void); +#endif + #endif /* ifndef __MACH_MX50_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 1eb339e6c85..dede19a766f 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -347,6 +347,7 @@ #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) extern int mx51_revision(void); +extern void mx51_display_revision(void); #endif /* tape-out 1 defines */ diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 7e072637eef..1aea818d9d3 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -51,6 +51,20 @@ #define IMX_CHIP_REVISION_3_3 0x33 #define IMX_CHIP_REVISION_UNKNOWN 0xff +#define IMX_CHIP_REVISION_1_0_STRING "1.0" +#define IMX_CHIP_REVISION_1_1_STRING "1.1" +#define IMX_CHIP_REVISION_1_2_STRING "1.2" +#define IMX_CHIP_REVISION_1_3_STRING "1.3" +#define IMX_CHIP_REVISION_2_0_STRING "2.0" +#define IMX_CHIP_REVISION_2_1_STRING "2.1" +#define IMX_CHIP_REVISION_2_2_STRING "2.2" +#define IMX_CHIP_REVISION_2_3_STRING "2.3" +#define IMX_CHIP_REVISION_3_0_STRING "3.0" +#define IMX_CHIP_REVISION_3_1_STRING "3.1" +#define IMX_CHIP_REVISION_3_2_STRING "3.2" +#define IMX_CHIP_REVISION_3_3_STRING "3.3" +#define IMX_CHIP_REVISION_UNKNOWN_STRING "unknown" + #ifndef __ASSEMBLY__ extern unsigned int __mxc_cpu_type; #endif @@ -181,6 +195,15 @@ struct cpu_op { u32 cpu_rate; }; +int tzic_enable_wake(int is_idle); +enum mxc_cpu_pwr_mode { + WAIT_CLOCKED, /* wfi only */ + WAIT_UNCLOCKED, /* WAIT */ + WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */ + STOP_POWER_ON, /* just STOP */ + STOP_POWER_OFF, /* STOP + SRPG */ +}; + extern struct cpu_op *(*get_cpu_op)(int *op); #endif diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h index 04c0d060d81..6bb96ef1600 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_nand.h +++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h @@ -24,7 +24,7 @@ struct mxc_nand_platform_data { unsigned int width; /* data bus width in bytes */ - unsigned int hw_ecc:1; /* 0 if supress hardware ECC */ + unsigned int hw_ecc:1; /* 0 if suppress hardware ECC */ unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */ struct mtd_partition *parts; /* partition table */ int nr_parts; /* size of parts */ diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h index 95be51bfe9a..0417da9f710 100644 --- a/arch/arm/plat-mxc/include/mach/system.h +++ b/arch/arm/plat-mxc/include/mach/system.h @@ -20,6 +20,8 @@ #include <mach/hardware.h> #include <mach/common.h> +extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode); + static inline void arch_idle(void) { #ifdef CONFIG_ARCH_MXC91231 @@ -54,7 +56,9 @@ static inline void arch_idle(void) "orr %0, %0, #0x00000004\n" "mcr p15, 0, %0, c1, c0, 0\n" : "=r" (reg)); - } else + } else if (cpu_is_mx51()) + mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); + else cpu_do_idle(); } diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c index 0c799ac2773..e1c6eff7258 100644 --- a/arch/arm/plat-mxc/irq-common.c +++ b/arch/arm/plat-mxc/irq-common.c @@ -29,7 +29,7 @@ int imx_irq_set_priority(unsigned char irq, unsigned char prio) ret = -ENOSYS; - base = get_irq_chip(irq); + base = irq_get_chip(irq); if (base) { chip = container_of(base, struct mxc_irq_chip, base); if (chip->set_priority) @@ -48,7 +48,7 @@ int mxc_set_irq_fiq(unsigned int irq, unsigned int type) ret = -ENOSYS; - base = get_irq_chip(irq); + base = irq_get_chip(irq); if (base) { chip = container_of(base, struct mxc_irq_chip, base); if (chip->set_irq_fiq) diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/plat-mxc/ssi-fiq.S index 4ddce565b35..8397a2dd19f 100644 --- a/arch/arm/plat-mxc/ssi-fiq.S +++ b/arch/arm/plat-mxc/ssi-fiq.S @@ -124,6 +124,8 @@ imx_ssi_fiq_start: 1: @ return from FIQ subs pc, lr, #4 + + .align imx_ssi_fiq_base: .word 0x0 imx_ssi_fiq_rx_buffer: diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c index 9f0c2610595..2237ff8b434 100644 --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c @@ -27,6 +27,7 @@ #include <linux/clk.h> #include <mach/hardware.h> +#include <asm/sched_clock.h> #include <asm/mach/time.h> #include <mach/common.h> @@ -105,6 +106,11 @@ static void gpt_irq_acknowledge(void) __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT); } +static cycle_t dummy_get_cycles(struct clocksource *cs) +{ + return 0; +} + static cycle_t mx1_2_get_cycles(struct clocksource *cs) { return __raw_readl(timer_base + MX1_2_TCN); @@ -118,18 +124,35 @@ static cycle_t v2_get_cycles(struct clocksource *cs) static struct clocksource clocksource_mxc = { .name = "mxc_timer1", .rating = 200, - .read = mx1_2_get_cycles, + .read = dummy_get_cycles, .mask = CLOCKSOURCE_MASK(32), .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; +static DEFINE_CLOCK_DATA(cd); +unsigned long long notrace sched_clock(void) +{ + cycle_t cyc = clocksource_mxc.read(&clocksource_mxc); + + return cyc_to_sched_clock(&cd, cyc, (u32)~0); +} + +static void notrace mxc_update_sched_clock(void) +{ + cycle_t cyc = clocksource_mxc.read(&clocksource_mxc); + update_sched_clock(&cd, cyc, (u32)~0); +} + static int __init mxc_clocksource_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); if (timer_is_v2()) clocksource_mxc.read = v2_get_cycles; + else + clocksource_mxc.read = mx1_2_get_cycles; + init_sched_clock(&cd, mxc_update_sched_clock, 32, c); clocksource_register_hz(&clocksource_mxc, c); return 0; diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index bc3a6be8a27..57f9395f87c 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c @@ -167,8 +167,8 @@ void __init tzic_init_irq(void __iomem *irqbase) /* all IRQ no FIQ Warning :: No selection */ for (i = 0; i < MXC_INTERNAL_IRQS; i++) { - set_irq_chip(i, &mxc_tzic_chip.base); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &mxc_tzic_chip.base, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c index 70620426ee5..f49748eca1a 100644 --- a/arch/arm/plat-nomadik/gpio.c +++ b/arch/arm/plat-nomadik/gpio.c @@ -54,6 +54,7 @@ struct nmk_gpio_chip { u32 rwimsc; u32 fwimsc; u32 slpm; + u32 enabled; }; static struct nmk_gpio_chip * @@ -318,7 +319,7 @@ static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) struct nmk_gpio_chip *nmk_chip; int pin = PIN_NUM(cfgs[i]); - nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); if (!nmk_chip) { ret = -EINVAL; break; @@ -397,7 +398,7 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) struct nmk_gpio_chip *nmk_chip; unsigned long flags; - nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); if (!nmk_chip) return -EINVAL; @@ -430,7 +431,7 @@ int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) struct nmk_gpio_chip *nmk_chip; unsigned long flags; - nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); if (!nmk_chip) return -EINVAL; @@ -456,7 +457,7 @@ int nmk_gpio_set_mode(int gpio, int gpio_mode) struct nmk_gpio_chip *nmk_chip; unsigned long flags; - nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); if (!nmk_chip) return -EINVAL; @@ -473,7 +474,7 @@ int nmk_gpio_get_mode(int gpio) struct nmk_gpio_chip *nmk_chip; u32 afunc, bfunc, bit; - nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); if (!nmk_chip) return -EINVAL; @@ -541,13 +542,6 @@ static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, int gpio, bool on) { -#ifdef CONFIG_ARCH_U8500 - if (cpu_is_u8500v2()) { - __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, - on ? NMK_GPIO_SLPM_WAKEUP_ENABLE - : NMK_GPIO_SLPM_WAKEUP_DISABLE); - } -#endif __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); } @@ -564,6 +558,11 @@ static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) if (!nmk_chip) return -EINVAL; + if (enable) + nmk_chip->enabled |= bitmask; + else + nmk_chip->enabled &= ~bitmask; + spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); spin_lock(&nmk_chip->lock); @@ -590,8 +589,6 @@ static void nmk_gpio_irq_unmask(struct irq_data *d) static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) { - struct irq_desc *desc = irq_to_desc(d->irq); - bool enabled = !(desc->status & IRQ_DISABLED); struct nmk_gpio_chip *nmk_chip; unsigned long flags; u32 bitmask; @@ -606,7 +603,7 @@ static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); spin_lock(&nmk_chip->lock); - if (!enabled) + if (!(nmk_chip->enabled & bitmask)) __nmk_gpio_set_wake(nmk_chip, gpio, on); if (on) @@ -622,9 +619,7 @@ static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) { - struct irq_desc *desc = irq_to_desc(d->irq); - bool enabled = !(desc->status & IRQ_DISABLED); - bool wake = desc->wake_depth; + bool enabled, wake = irqd_is_wakeup_set(d); int gpio; struct nmk_gpio_chip *nmk_chip; unsigned long flags; @@ -641,6 +636,8 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) if (type & IRQ_TYPE_LEVEL_LOW) return -EINVAL; + enabled = nmk_chip->enabled & bitmask; + spin_lock_irqsave(&nmk_chip->lock, flags); if (enabled) @@ -681,7 +678,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, u32 status) { struct nmk_gpio_chip *nmk_chip; - struct irq_chip *host_chip = get_irq_chip(irq); + struct irq_chip *host_chip = irq_get_chip(irq); unsigned int first_irq; if (host_chip->irq_mask_ack) @@ -692,7 +689,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, host_chip->irq_ack(&desc->irq_data); } - nmk_chip = get_irq_data(irq); + nmk_chip = irq_get_handler_data(irq); first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); while (status) { int bit = __ffs(status); @@ -706,7 +703,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { - struct nmk_gpio_chip *nmk_chip = get_irq_data(irq); + struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); u32 status = readl(nmk_chip->addr + NMK_GPIO_IS); __nmk_gpio_irq_handler(irq, desc, status); @@ -715,7 +712,7 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) static void nmk_gpio_secondary_irq_handler(unsigned int irq, struct irq_desc *desc) { - struct nmk_gpio_chip *nmk_chip = get_irq_data(irq); + struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); __nmk_gpio_irq_handler(irq, desc, status); @@ -728,20 +725,20 @@ static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) { - set_irq_chip(i, &nmk_gpio_irq_chip); - set_irq_handler(i, handle_edge_irq); + irq_set_chip_and_handler(i, &nmk_gpio_irq_chip, + handle_edge_irq); set_irq_flags(i, IRQF_VALID); - set_irq_chip_data(i, nmk_chip); - set_irq_type(i, IRQ_TYPE_EDGE_FALLING); + irq_set_chip_data(i, nmk_chip); + irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING); } - set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); - set_irq_data(nmk_chip->parent_irq, nmk_chip); + irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); + irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); if (nmk_chip->secondary_parent_irq >= 0) { - set_irq_chained_handler(nmk_chip->secondary_parent_irq, + irq_set_chained_handler(nmk_chip->secondary_parent_irq, nmk_gpio_secondary_irq_handler); - set_irq_data(nmk_chip->secondary_parent_irq, nmk_chip); + irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); } return 0; @@ -832,51 +829,6 @@ static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) : "? ", (mode < 0) ? "unknown" : modes[mode], pull ? "pull" : "none"); - - if (!is_out) { - int irq = gpio_to_irq(gpio); - struct irq_desc *desc = irq_to_desc(irq); - - /* This races with request_irq(), set_irq_type(), - * and set_irq_wake() ... but those are "rare". - * - * More significantly, trigger type flags aren't - * currently maintained by genirq. - */ - if (irq >= 0 && desc->action) { - char *trigger; - - switch (desc->status & IRQ_TYPE_SENSE_MASK) { - case IRQ_TYPE_NONE: - trigger = "(default)"; - break; - case IRQ_TYPE_EDGE_FALLING: - trigger = "edge-falling"; - break; - case IRQ_TYPE_EDGE_RISING: - trigger = "edge-rising"; - break; - case IRQ_TYPE_EDGE_BOTH: - trigger = "edge-both"; - break; - case IRQ_TYPE_LEVEL_HIGH: - trigger = "level-high"; - break; - case IRQ_TYPE_LEVEL_LOW: - trigger = "level-low"; - break; - default: - trigger = "?trigger?"; - break; - } - - seq_printf(s, " irq-%d %s%s", - irq, trigger, - (desc->status & IRQ_WAKEUP) - ? " wakeup" : ""); - } - } - seq_printf(s, "\n"); } } diff --git a/arch/arm/plat-nomadik/include/plat/ste_dma40.h b/arch/arm/plat-nomadik/include/plat/ste_dma40.h index 4d6dd4c39b7..c44886062f8 100644 --- a/arch/arm/plat-nomadik/include/plat/ste_dma40.h +++ b/arch/arm/plat-nomadik/include/plat/ste_dma40.h @@ -104,6 +104,8 @@ struct stedma40_half_channel_info { * * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH * @high_priority: true if high-priority + * @realtime: true if realtime mode is to be enabled. Only available on DMA40 + * version 3+, i.e DB8500v2+ * @mode: channel mode: physical, logical, or operation * @mode_opt: options for the chosen channel mode * @src_dev_type: Src device type @@ -119,6 +121,7 @@ struct stedma40_half_channel_info { struct stedma40_chan_cfg { enum stedma40_xfer_dir dir; bool high_priority; + bool realtime; enum stedma40_mode mode; enum stedma40_mode_opt mode_opt; int src_dev_type; @@ -169,25 +172,6 @@ struct stedma40_platform_data { bool stedma40_filter(struct dma_chan *chan, void *data); /** - * stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from - * scattergatter lists. - * - * @chan: dmaengine handle - * @sgl_dst: Destination scatter list - * @sgl_src: Source scatter list - * @sgl_len: The length of each scatterlist. Both lists must be of equal length - * and each element must match the corresponding element in the other scatter - * list. - * @flags: is actually enum dma_ctrl_flags. See dmaengine.h - */ - -struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan, - struct scatterlist *sgl_dst, - struct scatterlist *sgl_src, - unsigned int sgl_len, - unsigned long flags); - -/** * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave * (=device) * diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index 7d9f815cede..ea28f98d5d6 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c @@ -280,7 +280,7 @@ EXPORT_SYMBOL(omap_dsp_get_mempool_base); * Claiming GPIOs, and setting their direction and initial values, is the * responsibility of the device drivers. So is responding to probe(). * - * Board-specific knowlege like creating devices or pin setup is to be + * Board-specific knowledge like creating devices or pin setup is to be * kept out of drivers as much as possible. In particular, pin setup * may be handled by the boot loader, and drivers should expect it will * normally have been done by the time they're probed. diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 2ec3b5d9f21..c22217c2ee5 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -1019,7 +1019,7 @@ EXPORT_SYMBOL(omap_set_dma_callback); * If the channel is running the caller must disable interrupts prior calling * this function and process the returned value before re-enabling interrupt to * prevent races with the interrupt handler. Note that in continuous mode there - * is a chance for CSSA_L register overflow inbetween the two reads resulting + * is a chance for CSSA_L register overflow between the two reads resulting * in incorrect return value. */ dma_addr_t omap_get_dma_src_pos(int lch) @@ -1046,7 +1046,7 @@ EXPORT_SYMBOL(omap_get_dma_src_pos); * If the channel is running the caller must disable interrupts prior calling * this function and process the returned value before re-enabling interrupt to * prevent races with the interrupt handler. Note that in continuous mode there - * is a chance for CDSA_L register overflow inbetween the two reads resulting + * is a chance for CDSA_L register overflow between the two reads resulting * in incorrect return value. */ dma_addr_t omap_get_dma_dst_pos(int lch) diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 971d1863694..d2adcdda23c 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -755,18 +755,12 @@ static int gpio_irq_type(struct irq_data *d, unsigned type) bank = irq_data_get_irq_chip_data(d); spin_lock_irqsave(&bank->lock, flags); retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); - if (retval == 0) { - struct irq_desc *desc = irq_to_desc(d->irq); - - desc->status &= ~IRQ_TYPE_SENSE_MASK; - desc->status |= type; - } spin_unlock_irqrestore(&bank->lock, flags); if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) - __set_irq_handler_unlocked(d->irq, handle_level_irq); + __irq_set_handler_locked(d->irq, handle_level_irq); else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) - __set_irq_handler_unlocked(d->irq, handle_edge_irq); + __irq_set_handler_locked(d->irq, handle_edge_irq); return retval; } @@ -1146,7 +1140,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) desc->irq_data.chip->irq_ack(&desc->irq_data); - bank = get_irq_data(irq); + bank = irq_get_handler_data(irq); #ifdef CONFIG_ARCH_OMAP1 if (bank->method == METHOD_MPUIO) isr_reg = bank->base + @@ -1270,8 +1264,7 @@ static void gpio_unmask_irq(struct irq_data *d) unsigned int gpio = d->irq - IH_GPIO_BASE; struct gpio_bank *bank = irq_data_get_irq_chip_data(d); unsigned int irq_mask = 1 << get_gpio_index(gpio); - struct irq_desc *desc = irq_to_desc(d->irq); - u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK; + u32 trigger = irqd_get_trigger_type(d); if (trigger) _set_gpio_triggering(bank, get_gpio_index(gpio), trigger); @@ -1672,19 +1665,17 @@ static void __init omap_gpio_chip_init(struct gpio_bank *bank) for (j = bank->virtual_irq_start; j < bank->virtual_irq_start + bank_width; j++) { - struct irq_desc *d = irq_to_desc(j); - - lockdep_set_class(&d->lock, &gpio_lock_class); - set_irq_chip_data(j, bank); + irq_set_lockdep_class(j, &gpio_lock_class); + irq_set_chip_data(j, bank); if (bank_is_mpuio(bank)) - set_irq_chip(j, &mpuio_irq_chip); + irq_set_chip(j, &mpuio_irq_chip); else - set_irq_chip(j, &gpio_irq_chip); - set_irq_handler(j, handle_simple_irq); + irq_set_chip(j, &gpio_irq_chip); + irq_set_handler(j, handle_simple_irq); set_irq_flags(j, IRQF_VALID); } - set_irq_chained_handler(bank->irq, gpio_irq_handler); - set_irq_data(bank->irq, bank); + irq_set_chained_handler(bank->irq, gpio_irq_handler); + irq_set_handler_data(bank->irq, bank); } static int __devinit omap_gpio_probe(struct platform_device *pdev) diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h index 0f140ecedb0..5e04ddc18fa 100644 --- a/arch/arm/plat-omap/include/plat/display.h +++ b/arch/arm/plat-omap/include/plat/display.h @@ -58,6 +58,7 @@ enum omap_display_type { OMAP_DISPLAY_TYPE_SDI = 1 << 2, OMAP_DISPLAY_TYPE_DSI = 1 << 3, OMAP_DISPLAY_TYPE_VENC = 1 << 4, + OMAP_DISPLAY_TYPE_HDMI = 1 << 5, }; enum omap_plane { @@ -237,6 +238,13 @@ static inline int omap_display_init(struct omap_dss_board_info *board_data) } #endif +struct omap_display_platform_data { + struct omap_dss_board_info *board_data; + /* TODO: Additional members to be added when PM is considered */ + + bool (*opt_clock_available)(const char *clk_role); +}; + struct omap_video_timings { /* Unit: pixels */ u16 x_res; @@ -396,8 +404,8 @@ struct omap_dss_device { struct { u16 regn; u16 regm; - u16 regm3; - u16 regm4; + u16 regm_dispc; + u16 regm_dsi; u16 lp_clk_div; @@ -555,6 +563,9 @@ int omap_dsi_update(struct omap_dss_device *dssdev, int channel, u16 x, u16 y, u16 w, u16 h, void (*callback)(int, void *), void *data); +int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel); +int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id); +void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel); int omapdss_dsi_display_enable(struct omap_dss_device *dssdev); void omapdss_dsi_display_disable(struct omap_dss_device *dssdev); diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h index d6f9fa0f62a..cac2e8ac696 100644 --- a/arch/arm/plat-omap/include/plat/gpio.h +++ b/arch/arm/plat-omap/include/plat/gpio.h @@ -93,7 +93,7 @@ extern void omap_gpio_restore_context(void); /* Wrappers for "new style" GPIO calls, using the new infrastructure * which lets us plug in FPGA, I2C, and other implementations. * * - * The original OMAP-specfic calls should eventually be removed. + * The original OMAP-specific calls should eventually be removed. */ #include <linux/errno.h> diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index 12b31616503..1527929b445 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -90,7 +90,7 @@ enum omap_ecc { /* 1-bit ecc: stored at end of spare area */ OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */ OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */ - /* 1-bit ecc: stored at begining of spare area as romcode */ + /* 1-bit ecc: stored at beginning of spare area as romcode */ OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */ }; diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h index d7792837046..5a25098ea7e 100644 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ b/arch/arm/plat-omap/include/plat/irqs.h @@ -416,7 +416,7 @@ /* GPMC related */ #define OMAP_GPMC_IRQ_BASE (TWL_IRQ_END) -#define OMAP_GPMC_NR_IRQS 7 +#define OMAP_GPMC_NR_IRQS 8 #define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS) diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h index 98fc8b4a4cc..b9e85886b9d 100644 --- a/arch/arm/plat-omap/include/plat/omap34xx.h +++ b/arch/arm/plat-omap/include/plat/omap34xx.h @@ -56,8 +56,12 @@ #define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000) #define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200) #define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400) -#define OMAP3430_ISP_CSI2A_BASE (OMAP3430_ISP_BASE + 0x1800) -#define OMAP3430_ISP_CSI2PHY_BASE (OMAP3430_ISP_BASE + 0x1970) +#define OMAP3430_ISP_CSI2A_REGS1_BASE (OMAP3430_ISP_BASE + 0x1800) +#define OMAP3430_ISP_CSIPHY2_BASE (OMAP3430_ISP_BASE + 0x1970) +#define OMAP3630_ISP_CSI2A_REGS2_BASE (OMAP3430_ISP_BASE + 0x19C0) +#define OMAP3630_ISP_CSI2C_REGS1_BASE (OMAP3430_ISP_BASE + 0x1C00) +#define OMAP3630_ISP_CSIPHY1_BASE (OMAP3430_ISP_BASE + 0x1D70) +#define OMAP3630_ISP_CSI2C_REGS2_BASE (OMAP3430_ISP_BASE + 0x1DC0) #define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F) #define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077) @@ -69,8 +73,12 @@ #define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB) #define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB) #define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F) -#define OMAP3430_ISP_CSI2A_END (OMAP3430_ISP_CSI2A_BASE + 0x16F) -#define OMAP3430_ISP_CSI2PHY_END (OMAP3430_ISP_CSI2PHY_BASE + 0x007) +#define OMAP3430_ISP_CSI2A_REGS1_END (OMAP3430_ISP_CSI2A_REGS1_BASE + 0x16F) +#define OMAP3430_ISP_CSIPHY2_END (OMAP3430_ISP_CSIPHY2_BASE + 0x00B) +#define OMAP3630_ISP_CSI2A_REGS2_END (OMAP3630_ISP_CSI2A_REGS2_BASE + 0x3F) +#define OMAP3630_ISP_CSI2C_REGS1_END (OMAP3630_ISP_CSI2C_REGS1_BASE + 0x16F) +#define OMAP3630_ISP_CSIPHY1_END (OMAP3630_ISP_CSIPHY1_BASE + 0x00B) +#define OMAP3630_ISP_CSI2C_REGS2_END (OMAP3630_ISP_CSI2C_REGS2_BASE + 0x3F) #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) #define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000) diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h index cbe897ca7f9..2858667d2e4 100644 --- a/arch/arm/plat-omap/include/plat/onenand.h +++ b/arch/arm/plat-omap/include/plat/onenand.h @@ -32,6 +32,7 @@ struct omap_onenand_platform_data { int dma_channel; u8 flags; u8 regulator_can_sleep; + u8 skip_initial_unlocking; }; #define ONENAND_MAX_PARTITIONS 8 diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index 8a51fd58f65..34fc31ee908 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c @@ -793,6 +793,8 @@ static irqreturn_t iommu_fault_handler(int irq, void *data) clk_enable(obj->clk); errs = iommu_report_fault(obj, &da); clk_disable(obj->clk); + if (errs == 0) + return IRQ_HANDLED; /* Fault callback or TLB/PTE Dynamic loading */ if (obj->isr && !obj->isr(obj, da, errs, obj->isr_priv)) diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index d598d9fd65a..5587acf0eb2 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -1103,7 +1103,7 @@ int omap_mcbsp_pollread(unsigned int id, u16 *buf) /* resend */ return -1; } else { - /* wait for recieve confirmation */ + /* wait for receive confirmation */ int attemps = 0; while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) { if (attemps++ > 1000) { diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index 078894bc3b9..a431a138f40 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c @@ -324,9 +324,8 @@ EXPORT_SYMBOL(orion_gpio_set_blink); static void gpio_irq_ack(struct irq_data *d) { struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); - int type; + int type = irqd_get_trigger_type(d); - type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { int pin = d->irq - ochip->secondary_irq_base; @@ -337,11 +336,10 @@ static void gpio_irq_ack(struct irq_data *d) static void gpio_irq_mask(struct irq_data *d) { struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); - int type; + int type = irqd_get_trigger_type(d); void __iomem *reg; int pin; - type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) reg = GPIO_EDGE_MASK(ochip); else @@ -355,11 +353,10 @@ static void gpio_irq_mask(struct irq_data *d) static void gpio_irq_unmask(struct irq_data *d) { struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); - int type; + int type = irqd_get_trigger_type(d); void __iomem *reg; int pin; - type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) reg = GPIO_EDGE_MASK(ochip); else @@ -389,9 +386,9 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type) * Set edge/level type. */ if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { - set_irq_handler(d->irq, handle_edge_irq); + __irq_set_handler_locked(d->irq, handle_edge_irq); } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { - set_irq_handler(d->irq, handle_level_irq); + __irq_set_handler_locked(d->irq, handle_level_irq); } else { printk(KERN_ERR "failed to set irq=%d (type=%d)\n", d->irq, type); @@ -477,10 +474,10 @@ void __init orion_gpio_init(int gpio_base, int ngpio, for (i = 0; i < ngpio; i++) { unsigned int irq = secondary_irq_base + i; - set_irq_chip(irq, &orion_gpio_irq_chip); - set_irq_handler(irq, handle_level_irq); - set_irq_chip_data(irq, ochip); - irq_desc[irq].status |= IRQ_LEVEL; + irq_set_chip_and_handler(irq, &orion_gpio_irq_chip, + handle_level_irq); + irq_set_chip_data(irq, ochip); + irq_set_status_flags(irq, IRQ_LEVEL); set_irq_flags(irq, IRQF_VALID); } } @@ -488,7 +485,7 @@ void __init orion_gpio_init(int gpio_base, int ngpio, void orion_gpio_irq_handler(int pinoff) { struct orion_gpio_chip *ochip; - u32 cause; + u32 cause, type; int i; ochip = orion_gpio_chip_find(pinoff); @@ -500,15 +497,14 @@ void orion_gpio_irq_handler(int pinoff) for (i = 0; i < ochip->chip.ngpio; i++) { int irq; - struct irq_desc *desc; irq = ochip->secondary_irq_base + i; if (!(cause & (1 << i))) continue; - desc = irq_desc + irq; - if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { + type = irqd_get_trigger_type(irq_get_irq_data(irq)); + if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { /* Swap polarity (race with GPIO line) */ u32 polarity; @@ -516,7 +512,6 @@ void orion_gpio_irq_handler(int pinoff) polarity ^= 1 << i; writel(polarity, GPIO_IN_POL(ochip)); } - - desc_handle_irq(irq, desc); + generic_handle_irq(irq); } } diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c index 7d0c7eb59f0..d8d638e09f8 100644 --- a/arch/arm/plat-orion/irq.c +++ b/arch/arm/plat-orion/irq.c @@ -56,10 +56,10 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) for (i = 0; i < 32; i++) { unsigned int irq = irq_start + i; - set_irq_chip(irq, &orion_irq_chip); - set_irq_chip_data(irq, maskaddr); - set_irq_handler(irq, handle_level_irq); - irq_desc[irq].status |= IRQ_LEVEL; + irq_set_chip_and_handler(irq, &orion_irq_chip, + handle_level_irq); + irq_set_chip_data(irq, maskaddr); + irq_set_status_flags(irq, IRQ_LEVEL); set_irq_flags(irq, IRQF_VALID); } } diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c index e7de6ae2a1e..dce088f4567 100644 --- a/arch/arm/plat-pxa/gpio.c +++ b/arch/arm/plat-pxa/gpio.c @@ -284,13 +284,13 @@ void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn) } for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) { - set_irq_chip(irq, &pxa_muxed_gpio_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } /* Install handler for GPIO>=2 edge detect interrupts */ - set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler); + irq_set_chained_handler(mux_irq, pxa_gpio_demux_handler); pxa_muxed_gpio_chip.irq_set_wake = fn; } diff --git a/arch/arm/plat-pxa/include/plat/i2c.h b/arch/arm/plat-pxa/include/plat/i2c.h deleted file mode 100644 index 1a9f65e6ec0..00000000000 --- a/arch/arm/plat-pxa/include/plat/i2c.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * i2c_pxa.h - * - * Copyright (C) 2002 Intrinsyc Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#ifndef _I2C_PXA_H_ -#define _I2C_PXA_H_ - -#if 0 -#define DEF_TIMEOUT 3 -#else -/* need a longer timeout if we're dealing with the fact we may well be - * looking at a multi-master environment -*/ -#define DEF_TIMEOUT 32 -#endif - -#define BUS_ERROR (-EREMOTEIO) -#define XFER_NAKED (-ECONNREFUSED) -#define I2C_RETRY (-2000) /* an error has occurred retry transmit */ - -/* ICR initialize bit values -* -* 15. FM 0 (100 Khz operation) -* 14. UR 0 (No unit reset) -* 13. SADIE 0 (Disables the unit from interrupting on slave addresses -* matching its slave address) -* 12. ALDIE 0 (Disables the unit from interrupt when it loses arbitration -* in master mode) -* 11. SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode) -* 10. BEIE 1 (Enable interrupts from detected bus errors, no ACK sent) -* 9. IRFIE 1 (Enable interrupts from full buffer received) -* 8. ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty) -* 7. GCD 1 (Disables i2c unit response to general call messages as a slave) -* 6. IUE 0 (Disable unit until we change settings) -* 5. SCLE 1 (Enables the i2c clock output for master mode (drives SCL) -* 4. MA 0 (Only send stop with the ICR stop bit) -* 3. TB 0 (We are not transmitting a byte initially) -* 2. ACKNAK 0 (Send an ACK after the unit receives a byte) -* 1. STOP 0 (Do not send a STOP) -* 0. START 0 (Do not send a START) -* -*/ -#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) - -/* I2C status register init values - * - * 10. BED 1 (Clear bus error detected) - * 9. SAD 1 (Clear slave address detected) - * 7. IRF 1 (Clear IDBR Receive Full) - * 6. ITE 1 (Clear IDBR Transmit Empty) - * 5. ALD 1 (Clear Arbitration Loss Detected) - * 4. SSD 1 (Clear Slave Stop Detected) - */ -#define I2C_ISR_INIT 0x7FF /* status register init */ - -struct i2c_slave_client; - -struct i2c_pxa_platform_data { - unsigned int slave_addr; - struct i2c_slave_client *slave; - unsigned int class; - unsigned int use_pio :1; - unsigned int fast_mode :1; -}; - -extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info); - -#ifdef CONFIG_PXA27x -extern void pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info); -#endif - -#ifdef CONFIG_PXA3xx -extern void pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info); -#endif - -#endif diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h index 75f65647124..89e68e07b0a 100644 --- a/arch/arm/plat-pxa/include/plat/mfp.h +++ b/arch/arm/plat-pxa/include/plat/mfp.h @@ -434,7 +434,7 @@ typedef unsigned long mfp_cfg_t; * * mfp_init_addr() - accepts a table of "mfp_addr_map" structure, which * represents a range of MFP pins from "start" to "end", with the offset - * begining at "offset", to define a single pin, let "end" = -1. + * beginning at "offset", to define a single pin, let "end" = -1. * * use * diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h index 01a8448e471..442301fe48b 100644 --- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h +++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h @@ -30,6 +30,7 @@ struct pxa3xx_nand_cmdset { }; struct pxa3xx_nand_flash { + char *name; uint32_t chip_id; unsigned int page_per_block; /* Pages per block (PG_PER_BLK) */ unsigned int page_size; /* Page size in bytes (PAGE_SZ) */ @@ -37,7 +38,6 @@ struct pxa3xx_nand_flash { unsigned int dfc_width; /* Width of flash controller(DWIDTH_C) */ unsigned int num_blocks; /* Number of physical blocks in Flash */ - struct pxa3xx_nand_cmdset *cmdset; /* NAND command set */ struct pxa3xx_nand_timing *timing; /* NAND Flash timing */ }; diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index c2064c30871..0291bd6e236 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile @@ -23,7 +23,7 @@ obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o obj-$(CONFIG_CPU_FREQ_S3C24XX) += cpu-freq.o obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o -# Architecture dependant builds +# Architecture dependent builds obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o obj-$(CONFIG_PM) += pm.o diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/plat-s3c24xx/cpu-freq.c index eea75ff81d1..b3d3d027899 100644 --- a/arch/arm/plat-s3c24xx/cpu-freq.c +++ b/arch/arm/plat-s3c24xx/cpu-freq.c @@ -455,7 +455,7 @@ static int s3c_cpufreq_resume(struct cpufreq_policy *policy) /* whilst we will be called later on, we try and re-set the * cpu frequencies as soon as possible so that we do not end - * up resuming devices and then immediatley having to re-set + * up resuming devices and then immediately having to re-set * a number of settings once these devices have restarted. * * as a note, it is expected devices are not used until they diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index 6ad274e7593..27ea852e337 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c @@ -557,7 +557,7 @@ s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan) break; case S3C2410_DMALOAD_1LOADED_1RUNNING: - /* I belive in this case we do not have anything to do + /* I believe in this case we do not have anything to do * until the next buffer comes along, and we turn off the * reload */ return; diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c index 4434cb56bd9..9aee7e1668b 100644 --- a/arch/arm/plat-s3c24xx/irq.c +++ b/arch/arm/plat-s3c24xx/irq.c @@ -592,8 +592,8 @@ void __init s3c24xx_init_irq(void) case IRQ_UART1: case IRQ_UART2: case IRQ_ADCPARENT: - set_irq_chip(irqno, &s3c_irq_level_chip); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_level_chip, + handle_level_irq); break; case IRQ_RESERVED6: @@ -603,35 +603,35 @@ void __init s3c24xx_init_irq(void) default: //irqdbf("registering irq %d (s3c irq)\n", irqno); - set_irq_chip(irqno, &s3c_irq_chip); - set_irq_handler(irqno, handle_edge_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_chip, + handle_edge_irq); set_irq_flags(irqno, IRQF_VALID); } } /* setup the cascade irq handlers */ - set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7); - set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8); + irq_set_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7); + irq_set_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8); - set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0); - set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1); - set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2); - set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc); + irq_set_chained_handler(IRQ_UART0, s3c_irq_demux_uart0); + irq_set_chained_handler(IRQ_UART1, s3c_irq_demux_uart1); + irq_set_chained_handler(IRQ_UART2, s3c_irq_demux_uart2); + irq_set_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc); /* external interrupts */ for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { irqdbf("registering irq %d (ext int)\n", irqno); - set_irq_chip(irqno, &s3c_irq_eint0t4); - set_irq_handler(irqno, handle_edge_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_eint0t4, + handle_edge_irq); set_irq_flags(irqno, IRQF_VALID); } for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { irqdbf("registering irq %d (extended s3c irq)\n", irqno); - set_irq_chip(irqno, &s3c_irqext_chip); - set_irq_handler(irqno, handle_edge_irq); + irq_set_chip_and_handler(irqno, &s3c_irqext_chip, + handle_edge_irq); set_irq_flags(irqno, IRQF_VALID); } @@ -641,29 +641,28 @@ void __init s3c24xx_init_irq(void) for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); - set_irq_chip(irqno, &s3c_irq_uart0); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_uart0, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); - set_irq_chip(irqno, &s3c_irq_uart1); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_uart1, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); - set_irq_chip(irqno, &s3c_irq_uart2); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_uart2, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { irqdbf("registering irq %d (s3c adc irq)\n", irqno); - set_irq_chip(irqno, &s3c_irq_adc); - set_irq_handler(irqno, handle_edge_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_adc, handle_edge_irq); set_irq_flags(irqno, IRQF_VALID); } diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c index c3bfe9b13ac..5cf5e721e6c 100644 --- a/arch/arm/plat-s5p/cpu.c +++ b/arch/arm/plat-s5p/cpu.c @@ -39,7 +39,7 @@ static const char name_exynos4210[] = "EXYNOS4210"; static struct cpu_table cpu_ids[] __initdata = { { .idcode = 0x56440100, - .idmask = 0xffffff00, + .idmask = 0xfffff000, .map_io = s5p6440_map_io, .init_clocks = s5p6440_init_clocks, .init_uarts = s5p6440_init_uarts, @@ -47,7 +47,7 @@ static struct cpu_table cpu_ids[] __initdata = { .name = name_s5p6440, }, { .idcode = 0x36442000, - .idmask = 0xffffff00, + .idmask = 0xfffff000, .map_io = s5p6442_map_io, .init_clocks = s5p6442_init_clocks, .init_uarts = s5p6442_init_uarts, @@ -55,7 +55,7 @@ static struct cpu_table cpu_ids[] __initdata = { .name = name_s5p6442, }, { .idcode = 0x36450000, - .idmask = 0xffffff00, + .idmask = 0xfffff000, .map_io = s5p6450_map_io, .init_clocks = s5p6450_init_clocks, .init_uarts = s5p6450_init_uarts, @@ -79,7 +79,7 @@ static struct cpu_table cpu_ids[] __initdata = { .name = name_s5pv210, }, { .idcode = 0x43210000, - .idmask = 0xfffff000, + .idmask = 0xfffe0000, .map_io = exynos4_map_io, .init_clocks = exynos4_init_clocks, .init_uarts = exynos4_init_uarts, diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c index 225aa25405d..b5bb774985b 100644 --- a/arch/arm/plat-s5p/irq-eint.c +++ b/arch/arm/plat-s5p/irq-eint.c @@ -205,15 +205,14 @@ int __init s5p_init_irq_eint(void) int irq; for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++) - set_irq_chip(irq, &s5p_irq_vic_eint); + irq_set_chip(irq, &s5p_irq_vic_eint); for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) { - set_irq_chip(irq, &s5p_irq_eint); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } - set_irq_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31); + irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31); return 0; } diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c index cd87d3256e0..cd6d67c8382 100644 --- a/arch/arm/plat-s5p/irq-gpioint.c +++ b/arch/arm/plat-s5p/irq-gpioint.c @@ -43,13 +43,13 @@ LIST_HEAD(banks); static int s5p_gpioint_get_offset(struct irq_data *data) { - struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); + struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); return data->irq - chip->irq_base; } static void s5p_gpioint_ack(struct irq_data *data) { - struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); + struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); int group, offset, pend_offset; unsigned int value; @@ -64,7 +64,7 @@ static void s5p_gpioint_ack(struct irq_data *data) static void s5p_gpioint_mask(struct irq_data *data) { - struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); + struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); int group, offset, mask_offset; unsigned int value; @@ -79,7 +79,7 @@ static void s5p_gpioint_mask(struct irq_data *data) static void s5p_gpioint_unmask(struct irq_data *data) { - struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); + struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); int group, offset, mask_offset; unsigned int value; @@ -100,7 +100,7 @@ static void s5p_gpioint_mask_ack(struct irq_data *data) static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type) { - struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); + struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); int group, offset, con_offset; unsigned int value; @@ -149,7 +149,7 @@ static struct irq_chip s5p_gpioint = { static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) { - struct s5p_gpioint_bank *bank = get_irq_data(irq); + struct s5p_gpioint_bank *bank = irq_get_handler_data(irq); int group, pend_offset, mask_offset; unsigned int pend, mask; @@ -200,15 +200,15 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) if (!bank->chips) return -ENOMEM; - set_irq_chained_handler(bank->irq, s5p_gpioint_handler); - set_irq_data(bank->irq, bank); + irq_set_chained_handler(bank->irq, s5p_gpioint_handler); + irq_set_handler_data(bank->irq, bank); bank->handler = s5p_gpioint_handler; printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n", bank->irq); } /* - * chained GPIO irq has been sucessfully registered, allocate new gpio + * chained GPIO irq has been successfully registered, allocate new gpio * int group and assign irq nubmers */ @@ -219,9 +219,9 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) bank->chips[group - bank->start] = chip; for (i = 0; i < chip->chip.ngpio; i++) { irq = chip->irq_base + i; - set_irq_chip(irq, &s5p_gpioint); - set_irq_data(irq, chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip(irq, &s5p_gpioint); + irq_set_handler_data(irq, chip); + irq_set_handler(irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } return 0; diff --git a/arch/arm/plat-s5p/pm.c b/arch/arm/plat-s5p/pm.c index d592b6304b4..d15dc47b0e3 100644 --- a/arch/arm/plat-s5p/pm.c +++ b/arch/arm/plat-s5p/pm.c @@ -19,17 +19,6 @@ #define PFX "s5p pm: " -/* s3c_pm_check_resume_pin - * - * check to see if the pin is configured correctly for sleep mode, and - * make any necessary adjustments if it is not -*/ - -static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) -{ - /* nothing here yet */ -} - /* s3c_pm_configure_extint * * configure all external interrupt pins diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index 9a82b887491..983c578b827 100644 --- a/arch/arm/plat-samsung/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h @@ -21,7 +21,7 @@ struct clk; * @set_parent: set the clock's parent, see clk_set_parent(). * * Group the common clock implementations together so that we - * don't have to keep setting the same fiels again. We leave + * don't have to keep setting the same fields again. We leave * enable in struct clk. * * Adding an extra layer of indirection into the process should diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h index 5603db0b79b..3ad8386599c 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h @@ -114,7 +114,7 @@ extern unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip, * of control per GPIO, generally in the form of: * 0000 = Input * 0001 = Output - * others = Special functions (dependant on bank) + * others = Special functions (dependent on bank) * * Note, since the code to deal with the case where there are two control * registers instead of one, we do not have a separate set of functions for diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h index 5e04fa6eda7..1762dcb4cb9 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h @@ -125,7 +125,7 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr, * * These values control the state of the weak pull-{up,down} resistors * available on most pins on the S3C series. Not all chips support both - * up or down settings, and it may be dependant on the chip that is being + * up or down settings, and it may be dependent on the chip that is being * used to whether the particular mode is available. */ #define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00) @@ -138,7 +138,7 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr, * @pull: The configuration for the pull resistor. * * This function sets the state of the pull-{up,down} resistor for the - * specified pin. It will return 0 if successfull, or a negative error + * specified pin. It will return 0 if successful, or a negative error * code if the pin cannot support the requested pull setting. * * @pull is one of S3C_GPIO_PULL_NONE, S3C_GPIO_PULL_DOWN or S3C_GPIO_PULL_UP. @@ -202,7 +202,7 @@ extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin); * @drvstr: The new value of the driver strength * * This function sets the driver strength value for the specified pin. - * It will return 0 if successfull, or a negative error code if the pin + * It will return 0 if successful, or a negative error code if the pin * cannot support the requested setting. */ extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr); diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h index dac35d0a711..8cad4cf19c3 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-core.h +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h @@ -108,7 +108,7 @@ extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip); * of control per GPIO, generally in the form of: * 0000 = Input * 0001 = Output - * others = Special functions (dependant on bank) + * others = Special functions (dependent on bank) * * Note, since the code to deal with the case where there are two control * registers instead of one, we do not have a separate set of function diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index b0bdf16549d..058e09654fe 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -57,7 +57,7 @@ enum clk_types { * @cfg_gpio: Configure the GPIO for a specific card bit-width * @cfg_card: Configure the interface for a specific card and speed. This * is necessary the controllers and/or GPIO blocks require the - * changing of driver-strength and other controls dependant on + * changing of driver-strength and other controls dependent on * the card and speed of operation. * * Initialisation data specific to either the machine or the platform @@ -108,7 +108,7 @@ extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata; extern struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata; extern struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata; -/* Helper function availablity */ +/* Helper function availability */ extern void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *, int w); extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w); diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c index 6790edfaca6..79d10fca909 100644 --- a/arch/arm/plat-samsung/init.c +++ b/arch/arm/plat-samsung/init.c @@ -36,7 +36,7 @@ static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode, unsigned int count) { for (; count != 0; count--, tab++) { - if ((idcode & tab->idmask) == tab->idcode) + if ((idcode & tab->idmask) == (tab->idcode & tab->idmask)) return tab; } diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c index 4e770355ccb..4d4e571af55 100644 --- a/arch/arm/plat-samsung/irq-uart.c +++ b/arch/arm/plat-samsung/irq-uart.c @@ -107,7 +107,6 @@ static struct irq_chip s3c_irq_uart = { static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) { - struct irq_desc *desc = irq_to_desc(uirq->parent_irq); void __iomem *reg_base = uirq->regs; unsigned int irq; int offs; @@ -118,14 +117,13 @@ static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) for (offs = 0; offs < 3; offs++) { irq = uirq->base_irq + offs; - set_irq_chip(irq, &s3c_irq_uart); - set_irq_chip_data(irq, uirq); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &s3c_irq_uart, handle_level_irq); + irq_set_chip_data(irq, uirq); set_irq_flags(irq, IRQF_VALID); } - desc->irq_data.handler_data = uirq; - set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); + irq_set_handler_data(uirq->parent_irq, uirq); + irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); } /** diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c index dd8692ae5c4..d6ad66ab929 100644 --- a/arch/arm/plat-samsung/irq-vic-timer.c +++ b/arch/arm/plat-samsung/irq-vic-timer.c @@ -77,14 +77,11 @@ static struct irq_chip s3c_irq_timer = { void __init s3c_init_vic_timer_irq(unsigned int parent_irq, unsigned int timer_irq) { - struct irq_desc *desc = irq_to_desc(parent_irq); - set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer); + irq_set_chained_handler(parent_irq, s3c_irq_demux_vic_timer); + irq_set_handler_data(parent_irq, (void *)timer_irq); - set_irq_chip(timer_irq, &s3c_irq_timer); - set_irq_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0))); - set_irq_handler(timer_irq, handle_level_irq); + irq_set_chip_and_handler(timer_irq, &s3c_irq_timer, handle_level_irq); + irq_set_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0))); set_irq_flags(timer_irq, IRQF_VALID); - - desc->irq_data.handler_data = (void *)timer_irq; } diff --git a/arch/arm/plat-samsung/pm-check.c b/arch/arm/plat-samsung/pm-check.c index e4baf76f374..6b733fafe7c 100644 --- a/arch/arm/plat-samsung/pm-check.c +++ b/arch/arm/plat-samsung/pm-check.c @@ -164,7 +164,6 @@ static inline int in_region(void *ptr, int size, void *what, size_t whatsz) */ static u32 *s3c_pm_runcheck(struct resource *res, u32 *val) { - void *save_at = phys_to_virt(s3c_sleep_save_phys); unsigned long addr; unsigned long left; void *stkpage; @@ -192,11 +191,6 @@ static u32 *s3c_pm_runcheck(struct resource *res, u32 *val) goto skip_check; } - if (in_region(ptr, left, save_at, 32*4 )) { - S3C_PMDBG("skipping %08lx, has save block in\n", addr); - goto skip_check; - } - /* calculate and check the checksum */ calc = crc32_le(~0, ptr, left); diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index d5b58d31903..5c0a440d6e1 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -214,8 +214,9 @@ void s3c_pm_do_restore_core(struct sleep_save *ptr, int count) * * print any IRQs asserted at resume time (ie, we woke from) */ -static void s3c_pm_show_resume_irqs(int start, unsigned long which, - unsigned long mask) +static void __maybe_unused s3c_pm_show_resume_irqs(int start, + unsigned long which, + unsigned long mask) { int i; diff --git a/arch/arm/plat-samsung/s3c-pl330.c b/arch/arm/plat-samsung/s3c-pl330.c index b4ff8d74ac4..f85638c6f5a 100644 --- a/arch/arm/plat-samsung/s3c-pl330.c +++ b/arch/arm/plat-samsung/s3c-pl330.c @@ -68,7 +68,7 @@ struct s3c_pl330_xfer { * @req: Two requests to communicate with the PL330 engine. * @callback_fn: Callback function to the client. * @rqcfg: Channel configuration for the xfers. - * @xfer_head: Pointer to the xfer to be next excecuted. + * @xfer_head: Pointer to the xfer to be next executed. * @dmac: Pointer to the DMAC that manages this channel, NULL if the * channel is available to be acquired. * @client: Client of this channel. NULL if the diff --git a/arch/arm/plat-samsung/wakeup-mask.c b/arch/arm/plat-samsung/wakeup-mask.c index 2e09b6ad84c..dc814037297 100644 --- a/arch/arm/plat-samsung/wakeup-mask.c +++ b/arch/arm/plat-samsung/wakeup-mask.c @@ -22,7 +22,7 @@ void samsung_sync_wakemask(void __iomem *reg, struct samsung_wakeup_mask *mask, int nr_mask) { - struct irq_desc *desc; + struct irq_data *data; u32 val; val = __raw_readl(reg); @@ -33,10 +33,10 @@ void samsung_sync_wakemask(void __iomem *reg, continue; } - desc = irq_to_desc(mask->irq); + data = irq_get_irq_data(mask->irq); - /* bit of a liberty to read this directly from irq_desc. */ - if (desc->wake_depth > 0) + /* bit of a liberty to read this directly from irq_data. */ + if (irqd_is_wakeup_set(data)) val &= ~mask->bit; else val |= mask->bit; diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h index 2ae6606930a..fcc0d0ad4a1 100644 --- a/arch/arm/plat-spear/include/plat/clock.h +++ b/arch/arm/plat-spear/include/plat/clock.h @@ -89,7 +89,7 @@ struct rate_config { * @sibling: node for list of clocks having same parents * @private_data: clock specific private data * @node: list to maintain clocks linearly - * @cl: clocklook up assoicated with this clock + * @cl: clocklook up associated with this clock * @dent: object for debugfs */ struct clk { diff --git a/arch/arm/plat-spear/shirq.c b/arch/arm/plat-spear/shirq.c index 78189035e7f..961fb726124 100644 --- a/arch/arm/plat-spear/shirq.c +++ b/arch/arm/plat-spear/shirq.c @@ -68,7 +68,7 @@ static struct irq_chip shirq_chip = { static void shirq_handler(unsigned irq, struct irq_desc *desc) { u32 i, val, mask; - struct spear_shirq *shirq = get_irq_data(irq); + struct spear_shirq *shirq = irq_get_handler_data(irq); desc->irq_data.chip->irq_ack(&desc->irq_data); while ((val = readl(shirq->regs.base + shirq->regs.status_reg) & @@ -105,14 +105,14 @@ int spear_shirq_register(struct spear_shirq *shirq) if (!shirq->dev_count) return -EINVAL; - set_irq_chained_handler(shirq->irq, shirq_handler); + irq_set_chained_handler(shirq->irq, shirq_handler); for (i = 0; i < shirq->dev_count; i++) { - set_irq_chip(shirq->dev_config[i].virq, &shirq_chip); - set_irq_handler(shirq->dev_config[i].virq, handle_simple_irq); + irq_set_chip_and_handler(shirq->dev_config[i].virq, + &shirq_chip, handle_simple_irq); set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID); - set_irq_chip_data(shirq->dev_config[i].virq, shirq); + irq_set_chip_data(shirq->dev_config[i].virq, shirq); } - set_irq_data(shirq->irq, shirq); + irq_set_handler_data(shirq->irq, shirq); return 0; } diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c index aaa168683d4..6fdf9acf82e 100644 --- a/arch/arm/plat-stmp3xxx/irq.c +++ b/arch/arm/plat-stmp3xxx/irq.c @@ -35,8 +35,7 @@ void __init stmp3xxx_init_irq(struct irq_chip *chip) /* Disable all interrupts initially */ for (i = 0; i < NR_REAL_IRQS; i++) { chip->irq_mask(irq_get_irq_data(i)); - set_irq_chip(i, chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, chip, handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c index 66d5bac3ace..3def03b3217 100644 --- a/arch/arm/plat-stmp3xxx/pinmux.c +++ b/arch/arm/plat-stmp3xxx/pinmux.c @@ -489,14 +489,13 @@ static void stmp3xxx_gpio_free(struct gpio_chip *chip, unsigned offset) static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc) { - struct stmp3xxx_pinmux_bank *pm = get_irq_data(irq); + struct stmp3xxx_pinmux_bank *pm = irq_get_handler_data(irq); int gpio_irq = pm->virq; u32 stat = __raw_readl(pm->irqstat); while (stat) { if (stat & 1) - irq_desc[gpio_irq].handle_irq(gpio_irq, - &irq_desc[gpio_irq]); + generic_handle_irq(gpio_irq); gpio_irq++; stat >>= 1; } @@ -534,15 +533,15 @@ int __init stmp3xxx_pinmux_init(int virtual_irq_start) for (virq = pm->virq; virq < pm->virq; virq++) { gpio_irq_chip.irq_mask(irq_get_irq_data(virq)); - set_irq_chip(virq, &gpio_irq_chip); - set_irq_handler(virq, handle_level_irq); + irq_set_chip_and_handler(virq, &gpio_irq_chip, + handle_level_irq); set_irq_flags(virq, IRQF_VALID); } r = gpiochip_add(&pm->chip); if (r < 0) break; - set_irq_chained_handler(pm->irq, stmp3xxx_gpio_irq); - set_irq_data(pm->irq, pm); + irq_set_chained_handler(pm->irq, stmp3xxx_gpio_irq); + irq_set_handler_data(pm->irq, pm); } return r; } diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig new file mode 100644 index 00000000000..52353beb369 --- /dev/null +++ b/arch/arm/plat-versatile/Kconfig @@ -0,0 +1,17 @@ +if PLAT_VERSATILE + +config PLAT_VERSATILE_CLCD + bool + +config PLAT_VERSATILE_FPGA_IRQ + bool + +config PLAT_VERSATILE_LEDS + def_bool y if LEDS_CLASS + depends on ARCH_REALVIEW || ARCH_VERSATILE + +config PLAT_VERSATILE_SCHED_CLOCK + def_bool y if !ARCH_INTEGRATOR_AP + select HAVE_SCHED_CLOCK + +endif diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile index 16dde081993..69714db47c3 100644 --- a/arch/arm/plat-versatile/Makefile +++ b/arch/arm/plat-versatile/Makefile @@ -1,8 +1,7 @@ obj-y := clock.o -ifneq ($(CONFIG_ARCH_INTEGRATOR),y) -obj-y += sched-clock.o -endif -ifeq ($(CONFIG_LEDS_CLASS),y) -obj-$(CONFIG_ARCH_REALVIEW) += leds.o -obj-$(CONFIG_ARCH_VERSATILE) += leds.o -endif +obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o +obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o +obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o +obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o +obj-$(CONFIG_PLAT_VERSATILE_SCHED_CLOCK) += sched-clock.o +obj-$(CONFIG_SMP) += headsmp.o platsmp.o diff --git a/arch/arm/plat-versatile/clcd.c b/arch/arm/plat-versatile/clcd.c new file mode 100644 index 00000000000..6628cc27efc --- /dev/null +++ b/arch/arm/plat-versatile/clcd.c @@ -0,0 +1,182 @@ +#include <linux/device.h> +#include <linux/dma-mapping.h> +#include <linux/amba/bus.h> +#include <linux/amba/clcd.h> +#include <plat/clcd.h> + +static struct clcd_panel vga = { + .mode = { + .name = "VGA", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 39721, + .left_margin = 40, + .right_margin = 24, + .upper_margin = 32, + .lower_margin = 11, + .hsync_len = 96, + .vsync_len = 2, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + }, + .width = -1, + .height = -1, + .tim2 = TIM2_BCD | TIM2_IPC, + .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), + .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888, + .bpp = 16, +}; + +static struct clcd_panel xvga = { + .mode = { + .name = "XVGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15748, + .left_margin = 152, + .right_margin = 48, + .upper_margin = 23, + .lower_margin = 3, + .hsync_len = 104, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + }, + .width = -1, + .height = -1, + .tim2 = TIM2_BCD | TIM2_IPC, + .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), + .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888, + .bpp = 16, +}; + +/* Sanyo TM38QV67A02A - 3.8 inch QVGA (320x240) Color TFT */ +static struct clcd_panel sanyo_tm38qv67a02a = { + .mode = { + .name = "Sanyo TM38QV67A02A", + .refresh = 116, + .xres = 320, + .yres = 240, + .pixclock = 100000, + .left_margin = 6, + .right_margin = 6, + .upper_margin = 5, + .lower_margin = 5, + .hsync_len = 6, + .vsync_len = 6, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + }, + .width = -1, + .height = -1, + .tim2 = TIM2_BCD, + .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), + .caps = CLCD_CAP_5551, + .bpp = 16, +}; + +static struct clcd_panel sanyo_2_5_in = { + .mode = { + .name = "Sanyo QVGA Portrait", + .refresh = 116, + .xres = 240, + .yres = 320, + .pixclock = 100000, + .left_margin = 20, + .right_margin = 10, + .upper_margin = 2, + .lower_margin = 2, + .hsync_len = 10, + .vsync_len = 2, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + }, + .width = -1, + .height = -1, + .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC, + .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), + .caps = CLCD_CAP_5551, + .bpp = 16, +}; + +/* Epson L2F50113T00 - 2.2 inch 176x220 Color TFT */ +static struct clcd_panel epson_l2f50113t00 = { + .mode = { + .name = "Epson L2F50113T00", + .refresh = 390, + .xres = 176, + .yres = 220, + .pixclock = 62500, + .left_margin = 3, + .right_margin = 2, + .upper_margin = 1, + .lower_margin = 0, + .hsync_len = 3, + .vsync_len = 2, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + }, + .width = -1, + .height = -1, + .tim2 = TIM2_BCD | TIM2_IPC, + .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), + .caps = CLCD_CAP_5551, + .bpp = 16, +}; + +static struct clcd_panel *panels[] = { + &vga, + &xvga, + &sanyo_tm38qv67a02a, + &sanyo_2_5_in, + &epson_l2f50113t00, +}; + +struct clcd_panel *versatile_clcd_get_panel(const char *name) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(panels); i++) + if (strcmp(panels[i]->mode.name, name) == 0) + break; + + if (i < ARRAY_SIZE(panels)) + return panels[i]; + + pr_err("CLCD: couldn't get parameters for panel %s\n", name); + + return NULL; +} + +int versatile_clcd_setup_dma(struct clcd_fb *fb, unsigned long framesize) +{ + dma_addr_t dma; + + fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, + &dma, GFP_KERNEL); + if (!fb->fb.screen_base) { + pr_err("CLCD: unable to map framebuffer\n"); + return -ENOMEM; + } + + fb->fb.fix.smem_start = dma; + fb->fb.fix.smem_len = framesize; + + return 0; +} + +int versatile_clcd_mmap_dma(struct clcd_fb *fb, struct vm_area_struct *vma) +{ + return dma_mmap_writecombine(&fb->dev->dev, vma, + fb->fb.screen_base, + fb->fb.fix.smem_start, + fb->fb.fix.smem_len); +} + +void versatile_clcd_remove_dma(struct clcd_fb *fb) +{ + dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, + fb->fb.screen_base, fb->fb.fix.smem_start); +} diff --git a/arch/arm/plat-versatile/fpga-irq.c b/arch/arm/plat-versatile/fpga-irq.c new file mode 100644 index 00000000000..f0cc8e19b09 --- /dev/null +++ b/arch/arm/plat-versatile/fpga-irq.c @@ -0,0 +1,72 @@ +/* + * Support for Versatile FPGA-based IRQ controllers + */ +#include <linux/irq.h> +#include <linux/io.h> + +#include <asm/mach/irq.h> +#include <plat/fpga-irq.h> + +#define IRQ_STATUS 0x00 +#define IRQ_RAW_STATUS 0x04 +#define IRQ_ENABLE_SET 0x08 +#define IRQ_ENABLE_CLEAR 0x0c + +static void fpga_irq_mask(struct irq_data *d) +{ + struct fpga_irq_data *f = irq_data_get_irq_chip_data(d); + u32 mask = 1 << (d->irq - f->irq_start); + + writel(mask, f->base + IRQ_ENABLE_CLEAR); +} + +static void fpga_irq_unmask(struct irq_data *d) +{ + struct fpga_irq_data *f = irq_data_get_irq_chip_data(d); + u32 mask = 1 << (d->irq - f->irq_start); + + writel(mask, f->base + IRQ_ENABLE_SET); +} + +static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc) +{ + struct fpga_irq_data *f = irq_desc_get_handler_data(desc); + u32 status = readl(f->base + IRQ_STATUS); + + if (status == 0) { + do_bad_IRQ(irq, desc); + return; + } + + do { + irq = ffs(status) - 1; + status &= ~(1 << irq); + + generic_handle_irq(irq + f->irq_start); + } while (status); +} + +void __init fpga_irq_init(int parent_irq, u32 valid, struct fpga_irq_data *f) +{ + unsigned int i; + + f->chip.irq_ack = fpga_irq_mask; + f->chip.irq_mask = fpga_irq_mask; + f->chip.irq_unmask = fpga_irq_unmask; + + if (parent_irq != -1) { + irq_set_handler_data(parent_irq, f); + irq_set_chained_handler(parent_irq, fpga_irq_handle); + } + + for (i = 0; i < 32; i++) { + if (valid & (1 << i)) { + unsigned int irq = f->irq_start + i; + + irq_set_chip_data(irq, f); + irq_set_chip_and_handler(irq, &f->chip, + handle_level_irq); + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + } + } +} diff --git a/arch/arm/mach-vexpress/headsmp.S b/arch/arm/plat-versatile/headsmp.S index 7a3f0632947..d397a1fb2f5 100644 --- a/arch/arm/mach-vexpress/headsmp.S +++ b/arch/arm/plat-versatile/headsmp.S @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-vexpress/headsmp.S + * linux/arch/arm/plat-versatile/headsmp.S * * Copyright (c) 2003 ARM Limited * All Rights Reserved @@ -14,11 +14,11 @@ __INIT /* - * Versatile Express specific entry point for secondary CPUs. This - * provides a "holding pen" into which all secondary cores are held + * Realview/Versatile Express specific entry point for secondary CPUs. + * This provides a "holding pen" into which all secondary cores are held * until we're ready for them to initialise. */ -ENTRY(vexpress_secondary_startup) +ENTRY(versatile_secondary_startup) mrc p15, 0, r0, c0, c0, 5 and r0, r0, #15 adr r4, 1f diff --git a/arch/arm/plat-versatile/include/plat/clcd.h b/arch/arm/plat-versatile/include/plat/clcd.h new file mode 100644 index 00000000000..6bb6a1d2019 --- /dev/null +++ b/arch/arm/plat-versatile/include/plat/clcd.h @@ -0,0 +1,9 @@ +#ifndef PLAT_CLCD_H +#define PLAT_CLCD_H + +struct clcd_panel *versatile_clcd_get_panel(const char *); +int versatile_clcd_setup_dma(struct clcd_fb *, unsigned long); +int versatile_clcd_mmap_dma(struct clcd_fb *, struct vm_area_struct *); +void versatile_clcd_remove_dma(struct clcd_fb *); + +#endif diff --git a/arch/arm/plat-versatile/include/plat/fpga-irq.h b/arch/arm/plat-versatile/include/plat/fpga-irq.h new file mode 100644 index 00000000000..627fafd1e59 --- /dev/null +++ b/arch/arm/plat-versatile/include/plat/fpga-irq.h @@ -0,0 +1,12 @@ +#ifndef PLAT_FPGA_IRQ_H +#define PLAT_FPGA_IRQ_H + +struct fpga_irq_data { + void __iomem *base; + unsigned int irq_start; + struct irq_chip chip; +}; + +void fpga_irq_init(int, u32, struct fpga_irq_data *); + +#endif diff --git a/arch/arm/mach-vexpress/localtimer.c b/arch/arm/plat-versatile/localtimer.c index c0e3a59a0bf..0fb3961999b 100644 --- a/arch/arm/mach-vexpress/localtimer.c +++ b/arch/arm/plat-versatile/localtimer.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-vexpress/localtimer.c + * linux/arch/arm/plat-versatile/localtimer.c * * Copyright (C) 2002 ARM Ltd. * All Rights Reserved @@ -19,8 +19,9 @@ /* * Setup the local clock events for a CPU. */ -void __cpuinit local_timer_setup(struct clock_event_device *evt) +int __cpuinit local_timer_setup(struct clock_event_device *evt) { evt->irq = IRQ_LOCALTIMER; twd_timer_setup(evt); + return 0; } diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c new file mode 100644 index 00000000000..ba3d471d4bc --- /dev/null +++ b/arch/arm/plat-versatile/platsmp.c @@ -0,0 +1,104 @@ +/* + * linux/arch/arm/plat-versatile/platsmp.c + * + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/errno.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/jiffies.h> +#include <linux/smp.h> + +#include <asm/cacheflush.h> + +/* + * control for which core is the next to come out of the secondary + * boot "holding pen" + */ +volatile int __cpuinitdata pen_release = -1; + +/* + * Write pen_release in a way that is guaranteed to be visible to all + * observers, irrespective of whether they're taking part in coherency + * or not. This is necessary for the hotplug code to work reliably. + */ +static void __cpuinit write_pen_release(int val) +{ + pen_release = val; + smp_wmb(); + __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); +} + +static DEFINE_SPINLOCK(boot_lock); + +void __cpuinit platform_secondary_init(unsigned int cpu) +{ + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); + + /* + * let the primary processor know we're out of the + * pen, then head off into the C entry point + */ + write_pen_release(-1); + + /* + * Synchronise with the boot thread. + */ + spin_lock(&boot_lock); + spin_unlock(&boot_lock); +} + +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long timeout; + + /* + * Set synchronisation state between this boot processor + * and the secondary one + */ + spin_lock(&boot_lock); + + /* + * This is really belt and braces; we hold unintended secondary + * CPUs in the holding pen until we're ready for them. However, + * since we haven't sent them a soft interrupt, they shouldn't + * be there. + */ + write_pen_release(cpu); + + /* + * Send the secondary CPU a soft interrupt, thereby causing + * the boot monitor to read the system wide flags register, + * and branch to the address found there. + */ + smp_cross_call(cpumask_of(cpu), 1); + + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) { + smp_rmb(); + if (pen_release == -1) + break; + + udelay(10); + } + + /* + * now the secondary core is starting up let it run its + * calibrations, then wait for it to finish + */ + spin_unlock(&boot_lock); + + return pen_release != -1 ? -ENOSYS : 0; +} diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 9d6feaabbe7..7ca41f0a09b 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -12,2745 +12,458 @@ # # http://www.arm.linux.org.uk/developer/machines/?action=new # -# Last update: Mon Feb 7 08:59:27 2011 +# XXX: This is a cut-down version of the file; it contains only machines that +# XXX: are in mainline or have been submitted to the machine database within +# XXX: the last 12 months. If your entry is missing please email rmk at +# XXX: <linux@arm.linux.org.uk> +# +# Last update: Sun Mar 20 18:06:11 2011 # # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number # ebsa110 ARCH_EBSA110 EBSA110 0 riscpc ARCH_RPC RISCPC 1 -nexuspci ARCH_NEXUSPCI NEXUSPCI 3 ebsa285 ARCH_EBSA285 EBSA285 4 netwinder ARCH_NETWINDER NETWINDER 5 cats ARCH_CATS CATS 6 -tbox ARCH_TBOX TBOX 7 -co285 ARCH_CO285 CO285 8 -clps7110 ARCH_CLPS7110 CLPS7110 9 -archimedes ARCH_ARC ARCHIMEDES 10 -a5k ARCH_A5K A5K 11 -etoile ARCH_ETOILE ETOILE 12 -lacie_nas ARCH_LACIE_NAS LACIE_NAS 13 -clps7500 ARCH_CLPS7500 CLPS7500 14 shark ARCH_SHARK SHARK 15 brutus SA1100_BRUTUS BRUTUS 16 personal_server ARCH_PERSONAL_SERVER PERSONAL_SERVER 17 -itsy SA1100_ITSY ITSY 18 l7200 ARCH_L7200 L7200 19 pleb SA1100_PLEB PLEB 20 integrator ARCH_INTEGRATOR INTEGRATOR 21 h3600 SA1100_H3600 H3600 22 -ixp1200 ARCH_IXP1200 IXP1200 23 p720t ARCH_P720T P720T 24 assabet SA1100_ASSABET ASSABET 25 -victor SA1100_VICTOR VICTOR 26 lart SA1100_LART LART 27 -ranger SA1100_RANGER RANGER 28 graphicsclient SA1100_GRAPHICSCLIENT GRAPHICSCLIENT 29 xp860 SA1100_XP860 XP860 30 cerf SA1100_CERF CERF 31 nanoengine SA1100_NANOENGINE NANOENGINE 32 -fpic SA1100_FPIC FPIC 33 -extenex1 SA1100_EXTENEX1 EXTENEX1 34 -sherman SA1100_SHERMAN SHERMAN 35 -accelent_sa SA1100_ACCELENT ACCELENT_SA 36 -accelent_l7200 ARCH_L7200_ACCELENT ACCELENT_L7200 37 -netport SA1100_NETPORT NETPORT 38 -pangolin SA1100_PANGOLIN PANGOLIN 39 -yopy SA1100_YOPY YOPY 40 -coolidge SA1100_COOLIDGE COOLIDGE 41 -huw_webpanel SA1100_HUW_WEBPANEL HUW_WEBPANEL 42 -spotme ARCH_SPOTME SPOTME 43 -freebird ARCH_FREEBIRD FREEBIRD 44 -ti925 ARCH_TI925 TI925 45 -riscstation ARCH_RISCSTATION RISCSTATION 46 -cavy SA1100_CAVY CAVY 47 jornada720 SA1100_JORNADA720 JORNADA720 48 -omnimeter SA1100_OMNIMETER OMNIMETER 49 edb7211 ARCH_EDB7211 EDB7211 50 -citygo SA1100_CITYGO CITYGO 51 pfs168 SA1100_PFS168 PFS168 52 -spot SA1100_SPOT SPOT 53 flexanet SA1100_FLEXANET FLEXANET 54 -webpal ARCH_WEBPAL WEBPAL 55 -linpda SA1100_LINPDA LINPDA 56 -anakin ARCH_ANAKIN ANAKIN 57 -mvi SA1100_MVI MVI 58 -jupiter SA1100_JUPITER JUPITER 59 -psionw ARCH_PSIONW PSIONW 60 -aln SA1100_ALN ALN 61 -epxa ARCH_CAMELOT CAMELOT 62 -gds2200 SA1100_GDS2200 GDS2200 63 -netbook SA1100_PSION_SERIES7 PSION_SERIES7 64 -xfile SA1100_XFILE XFILE 65 -accelent_ep9312 ARCH_ACCELENT_EP9312 ACCELENT_EP9312 66 -ic200 ARCH_IC200 IC200 67 -creditlart SA1100_CREDITLART CREDITLART 68 -htm SA1100_HTM HTM 69 -iq80310 ARCH_IQ80310 IQ80310 70 -freebot SA1100_FREEBOT FREEBOT 71 -entel ARCH_ENTEL ENTEL 72 -enp3510 ARCH_ENP3510 ENP3510 73 -trizeps SA1100_TRIZEPS TRIZEPS 74 -nesa SA1100_NESA NESA 75 -venus ARCH_VENUS VENUS 76 -tardis ARCH_TARDIS TARDIS 77 -mercury ARCH_MERCURY MERCURY 78 -empeg SA1100_EMPEG EMPEG 79 -adi_evb ARCH_I80200FCC I80200FCC 80 -itt_cpb SA1100_ITT_CPB ITT_CPB 81 -svc SA1100_SVC SVC 82 -alpha2 SA1100_ALPHA2 ALPHA2 84 -alpha1 SA1100_ALPHA1 ALPHA1 85 -netarm ARCH_NETARM NETARM 86 simpad SA1100_SIMPAD SIMPAD 87 -pda1 ARCH_PDA1 PDA1 88 lubbock ARCH_LUBBOCK LUBBOCK 89 -aniko ARCH_ANIKO ANIKO 90 clep7212 ARCH_CLEP7212 CLEP7212 91 -cs89712 ARCH_CS89712 CS89712 92 -weararm SA1100_WEARARM WEARARM 93 -possio_px SA1100_POSSIO_PX POSSIO_PX 94 -sidearm SA1100_SIDEARM SIDEARM 95 -stork SA1100_STORK STORK 96 shannon SA1100_SHANNON SHANNON 97 -ace ARCH_ACE ACE 98 -ballyarm SA1100_BALLYARM BALLYARM 99 -simputer SA1100_SIMPUTER SIMPUTER 100 -nexterm SA1100_NEXTERM NEXTERM 101 -sa1100_elf SA1100_SA1100_ELF SA1100_ELF 102 -gator SA1100_GATOR GATOR 103 -granite ARCH_GRANITE GRANITE 104 consus SA1100_CONSUS CONSUS 105 aaed2000 ARCH_AAED2000 AAED2000 106 cdb89712 ARCH_CDB89712 CDB89712 107 graphicsmaster SA1100_GRAPHICSMASTER GRAPHICSMASTER 108 adsbitsy SA1100_ADSBITSY ADSBITSY 109 pxa_idp ARCH_PXA_IDP PXA_IDP 110 -plce ARCH_PLCE PLCE 111 pt_system3 SA1100_PT_SYSTEM3 PT_SYSTEM3 112 -murphy ARCH_MEDALB MEDALB 113 -eagle ARCH_EAGLE EAGLE 114 -dsc21 ARCH_DSC21 DSC21 115 -dsc24 ARCH_DSC24 DSC24 116 -ti5472 ARCH_TI5472 TI5472 117 autcpu12 ARCH_AUTCPU12 AUTCPU12 118 -uengine ARCH_UENGINE UENGINE 119 -bluestem SA1100_BLUESTEM BLUESTEM 120 -xingu8 ARCH_XINGU8 XINGU8 121 -bushstb ARCH_BUSHSTB BUSHSTB 122 -epsilon1 SA1100_EPSILON1 EPSILON1 123 -balloon SA1100_BALLOON BALLOON 124 -puppy ARCH_PUPPY PUPPY 125 -elroy SA1100_ELROY ELROY 126 -gms720 ARCH_GMS720 GMS720 127 -s24x ARCH_S24X S24X 128 -jtel_clep7312 ARCH_JTEL_CLEP7312 JTEL_CLEP7312 129 -cx821xx ARCH_CX821XX CX821XX 130 -edb7312 ARCH_EDB7312 EDB7312 131 -bsa1110 SA1100_BSA1110 BSA1110 132 -powerpin ARCH_POWERPIN POWERPIN 133 -openarm ARCH_OPENARM OPENARM 134 -whitechapel SA1100_WHITECHAPEL WHITECHAPEL 135 h3100 SA1100_H3100 H3100 136 -h3800 SA1100_H3800 H3800 137 -blue_v1 ARCH_BLUE_V1 BLUE_V1 138 -pxa_cerf ARCH_PXA_CERF PXA_CERF 139 -arm7tevb ARCH_ARM7TEVB ARM7TEVB 140 -d7400 SA1100_D7400 D7400 141 -piranha ARCH_PIRANHA PIRANHA 142 -sbcamelot SA1100_SBCAMELOT SBCAMELOT 143 -kings SA1100_KINGS KINGS 144 -smdk2400 ARCH_SMDK2400 SMDK2400 145 collie SA1100_COLLIE COLLIE 146 -idr ARCH_IDR IDR 147 badge4 SA1100_BADGE4 BADGE4 148 -webnet ARCH_WEBNET WEBNET 149 -d7300 SA1100_D7300 D7300 150 -cep SA1100_CEP CEP 151 fortunet ARCH_FORTUNET FORTUNET 152 -vc547x ARCH_VC547X VC547X 153 -filewalker SA1100_FILEWALKER FILEWALKER 154 -netgateway SA1100_NETGATEWAY NETGATEWAY 155 -symbol2800 SA1100_SYMBOL2800 SYMBOL2800 156 -suns SA1100_SUNS SUNS 157 -frodo SA1100_FRODO FRODO 158 -ms301 SA1100_MACH_TYTE_MS301 MACH_TYTE_MS301 159 mx1ads ARCH_MX1ADS MX1ADS 160 h7201 ARCH_H7201 H7201 161 h7202 ARCH_H7202 H7202 162 -amico ARCH_AMICO AMICO 163 -iam SA1100_IAM IAM 164 -tt530 SA1100_TT530 TT530 165 -sam2400 ARCH_SAM2400 SAM2400 166 -jornada56x SA1100_JORNADA56X JORNADA56X 167 -active SA1100_ACTIVE ACTIVE 168 iq80321 ARCH_IQ80321 IQ80321 169 -wid SA1100_WID WID 170 -sabinal ARCH_SABINAL SABINAL 171 -ixp425_matacumbe ARCH_IXP425_MATACUMBE IXP425_MATACUMBE 172 -miniprint SA1100_MINIPRINT MINIPRINT 173 -adm510x ARCH_ADM510X ADM510X 174 -svs200 SA1100_SVS200 SVS200 175 -atg_tcu ARCH_ATG_TCU ATG_TCU 176 -jornada820 SA1100_JORNADA820 JORNADA820 177 -s3c44b0 ARCH_S3C44B0 S3C44B0 178 -margis2 ARCH_MARGIS2 MARGIS2 179 ks8695 ARCH_KS8695 KS8695 180 -brh ARCH_BRH BRH 181 -s3c2410 ARCH_S3C2410 S3C2410 182 -possio_px30 ARCH_POSSIO_PX30 POSSIO_PX30 183 -s3c2800 ARCH_S3C2800 S3C2800 184 -fleetwood SA1100_FLEETWOOD FLEETWOOD 185 -omaha ARCH_OMAHA OMAHA 186 -ta7 ARCH_TA7 TA7 187 -nova SA1100_NOVA NOVA 188 -hmk ARCH_HMK HMK 189 -karo ARCH_KARO KARO 190 -fester SA1100_FESTER FESTER 191 -gpi ARCH_GPI GPI 192 smdk2410 ARCH_SMDK2410 SMDK2410 193 -i519 ARCH_I519 I519 194 -nexio SA1100_NEXIO NEXIO 195 -bitbox SA1100_BITBOX BITBOX 196 -g200 SA1100_G200 G200 197 -gill SA1100_GILL GILL 198 -pxa_mercury ARCH_PXA_MERCURY PXA_MERCURY 199 ceiva ARCH_CEIVA CEIVA 200 -fret SA1100_FRET FRET 201 -emailphone SA1100_EMAILPHONE EMAILPHONE 202 -h3900 ARCH_H3900 H3900 203 -pxa1 ARCH_PXA1 PXA1 204 -koan369 SA1100_KOAN369 KOAN369 205 -cogent ARCH_COGENT COGENT 206 -esl_simputer ARCH_ESL_SIMPUTER ESL_SIMPUTER 207 -esl_simputer_clr ARCH_ESL_SIMPUTER_CLR ESL_SIMPUTER_CLR 208 -esl_simputer_bw ARCH_ESL_SIMPUTER_BW ESL_SIMPUTER_BW 209 -hhp_cradle ARCH_HHP_CRADLE HHP_CRADLE 210 -he500 ARCH_HE500 HE500 211 -inhandelf2 SA1100_INHANDELF2 INHANDELF2 212 -inhandftip SA1100_INHANDFTIP INHANDFTIP 213 -dnp1110 SA1100_DNP1110 DNP1110 214 -pnp1110 SA1100_PNP1110 PNP1110 215 -csb226 ARCH_CSB226 CSB226 216 -arnold SA1100_ARNOLD ARNOLD 217 voiceblue MACH_VOICEBLUE VOICEBLUE 218 -jz8028 ARCH_JZ8028 JZ8028 219 h5400 ARCH_H5400 H5400 220 -forte SA1100_FORTE FORTE 221 -acam SA1100_ACAM ACAM 222 -abox SA1100_ABOX ABOX 223 -atmel ARCH_ATMEL ATMEL 224 -sitsang ARCH_SITSANG SITSANG 225 -cpu1110lcdnet SA1100_CPU1110LCDNET CPU1110LCDNET 226 -mpl_vcma9 ARCH_MPL_VCMA9 MPL_VCMA9 227 -opus_a1 ARCH_OPUS_A1 OPUS_A1 228 -daytona ARCH_DAYTONA DAYTONA 229 -killbear SA1100_KILLBEAR KILLBEAR 230 -yoho ARCH_YOHO YOHO 231 -jasper ARCH_JASPER JASPER 232 -dsc25 ARCH_DSC25 DSC25 233 omap_innovator MACH_OMAP_INNOVATOR OMAP_INNOVATOR 234 -mnci ARCH_RAMSES RAMSES 235 -s28x ARCH_S28X S28X 236 -mport3 ARCH_MPORT3 MPORT3 237 -pxa_eagle250 ARCH_PXA_EAGLE250 PXA_EAGLE250 238 -pdb ARCH_PDB PDB 239 -blue_2g SA1100_BLUE_2G BLUE_2G 240 -bluearch SA1100_BLUEARCH BLUEARCH 241 ixdp2400 ARCH_IXDP2400 IXDP2400 242 ixdp2800 ARCH_IXDP2800 IXDP2800 243 -explorer SA1100_EXPLORER EXPLORER 244 ixdp425 ARCH_IXDP425 IXDP425 245 -chimp ARCH_CHIMP CHIMP 246 -stork_nest ARCH_STORK_NEST STORK_NEST 247 -stork_egg ARCH_STORK_EGG STORK_EGG 248 -wismo SA1100_WISMO WISMO 249 -ezlinx ARCH_EZLINX EZLINX 250 -at91rm9200 ARCH_AT91RM9200 AT91RM9200 251 -adtech_orion ARCH_ADTECH_ORION ADTECH_ORION 252 -neptune ARCH_NEPTUNE NEPTUNE 253 hackkit SA1100_HACKKIT HACKKIT 254 -pxa_wins30 ARCH_PXA_WINS30 PXA_WINS30 255 -lavinna SA1100_LAVINNA LAVINNA 256 -pxa_uengine ARCH_PXA_UENGINE PXA_UENGINE 257 -innokom ARCH_INNOKOM INNOKOM 258 -bms ARCH_BMS BMS 259 ixcdp1100 ARCH_IXCDP1100 IXCDP1100 260 -prpmc1100 ARCH_PRPMC1100 PRPMC1100 261 at91rm9200dk ARCH_AT91RM9200DK AT91RM9200DK 262 -armstick ARCH_ARMSTICK ARMSTICK 263 -armonie ARCH_ARMONIE ARMONIE 264 -mport1 ARCH_MPORT1 MPORT1 265 -s3c5410 ARCH_S3C5410 S3C5410 266 -zcp320a ARCH_ZCP320A ZCP320A 267 -i_box ARCH_I_BOX I_BOX 268 -stlc1502 ARCH_STLC1502 STLC1502 269 -siren ARCH_SIREN SIREN 270 -greenlake ARCH_GREENLAKE GREENLAKE 271 -argus ARCH_ARGUS ARGUS 272 -combadge SA1100_COMBADGE COMBADGE 273 -rokepxa ARCH_ROKEPXA ROKEPXA 274 cintegrator ARCH_CINTEGRATOR CINTEGRATOR 275 -guidea07 ARCH_GUIDEA07 GUIDEA07 276 -tat257 ARCH_TAT257 TAT257 277 -igp2425 ARCH_IGP2425 IGP2425 278 -bluegrama ARCH_BLUEGRAMMA BLUEGRAMMA 279 -ipod ARCH_IPOD IPOD 280 -adsbitsyx ARCH_ADSBITSYX ADSBITSYX 281 -trizeps2 ARCH_TRIZEPS2 TRIZEPS2 282 viper ARCH_VIPER VIPER 283 -adsbitsyplus SA1100_ADSBITSYPLUS ADSBITSYPLUS 284 -adsagc SA1100_ADSAGC ADSAGC 285 -stp7312 ARCH_STP7312 STP7312 286 -nx_phnx MACH_NX_PHNX NX_PHNX 287 -wep_ep250 ARCH_WEP_EP250 WEP_EP250 288 -inhandelf3 ARCH_INHANDELF3 INHANDELF3 289 adi_coyote ARCH_ADI_COYOTE ADI_COYOTE 290 -iyonix ARCH_IYONIX IYONIX 291 -damicam1 ARCH_DAMICAM_SA1110 DAMICAM_SA1110 292 -meg03 ARCH_MEG03 MEG03 293 -pxa_whitechapel ARCH_PXA_WHITECHAPEL PXA_WHITECHAPEL 294 -nwsc ARCH_NWSC NWSC 295 -nwlarm ARCH_NWLARM NWLARM 296 -ixp425_mguard ARCH_IXP425_MGUARD IXP425_MGUARD 297 -pxa_netdcu4 ARCH_PXA_NETDCU4 PXA_NETDCU4 298 ixdp2401 ARCH_IXDP2401 IXDP2401 299 ixdp2801 ARCH_IXDP2801 IXDP2801 300 -zodiac ARCH_ZODIAC ZODIAC 301 -armmodul ARCH_ARMMODUL ARMMODUL 302 -ketop SA1100_KETOP KETOP 303 -av7200 ARCH_AV7200 AV7200 304 -arch_ti925 ARCH_ARCH_TI925 ARCH_TI925 305 -acq200 ARCH_ACQ200 ACQ200 306 -pt_dafit SA1100_PT_DAFIT PT_DAFIT 307 -ihba ARCH_IHBA IHBA 308 -quinque ARCH_QUINQUE QUINQUE 309 -nimbraone ARCH_NIMBRAONE NIMBRAONE 310 -nimbra29x ARCH_NIMBRA29X NIMBRA29X 311 -nimbra210 ARCH_NIMBRA210 NIMBRA210 312 -hhp_d95xx ARCH_HHP_D95XX HHP_D95XX 313 -labarm ARCH_LABARM LABARM 314 -m825xx ARCH_M825XX M825XX 315 -m7100 SA1100_M7100 M7100 316 -nipc2 ARCH_NIPC2 NIPC2 317 -fu7202 ARCH_FU7202 FU7202 318 -adsagx ARCH_ADSAGX ADSAGX 319 -pxa_pooh ARCH_PXA_POOH PXA_POOH 320 -bandon ARCH_BANDON BANDON 321 -pcm7210 ARCH_PCM7210 PCM7210 322 -nms9200 ARCH_NMS9200 NMS9200 323 -logodl ARCH_LOGODL LOGODL 324 -m7140 SA1100_M7140 M7140 325 -korebot ARCH_KOREBOT KOREBOT 326 iq31244 ARCH_IQ31244 IQ31244 327 -koan393 SA1100_KOAN393 KOAN393 328 -inhandftip3 ARCH_INHANDFTIP3 INHANDFTIP3 329 -gonzo ARCH_GONZO GONZO 330 bast ARCH_BAST BAST 331 -scanpass ARCH_SCANPASS SCANPASS 332 -ep7312_pooh ARCH_EP7312_POOH EP7312_POOH 333 -ta7s ARCH_TA7S TA7S 334 -ta7v ARCH_TA7V TA7V 335 -icarus SA1100_ICARUS ICARUS 336 -h1900 ARCH_H1900 H1900 337 -gemini SA1100_GEMINI GEMINI 338 -axim ARCH_AXIM AXIM 339 -audiotron ARCH_AUDIOTRON AUDIOTRON 340 -h2200 ARCH_H2200 H2200 341 -loox600 ARCH_LOOX600 LOOX600 342 -niop ARCH_NIOP NIOP 343 -dm310 ARCH_DM310 DM310 344 -seedpxa_c2 ARCH_SEEDPXA_C2 SEEDPXA_C2 345 -ixp4xx_mguardpci ARCH_IXP4XX_MGUARD_PCI IXP4XX_MGUARD_PCI 346 h1940 ARCH_H1940 H1940 347 -scorpio ARCH_SCORPIO SCORPIO 348 -viva ARCH_VIVA VIVA 349 -pxa_xcard ARCH_PXA_XCARD PXA_XCARD 350 -csb335 ARCH_CSB335 CSB335 351 -ixrd425 ARCH_IXRD425 IXRD425 352 -iq80315 ARCH_IQ80315 IQ80315 353 -nmp7312 ARCH_NMP7312 NMP7312 354 -cx861xx ARCH_CX861XX CX861XX 355 enp2611 ARCH_ENP2611 ENP2611 356 -xda SA1100_XDA XDA 357 -csir_ims ARCH_CSIR_IMS CSIR_IMS 358 -ixp421_dnaeeth ARCH_IXP421_DNAEETH IXP421_DNAEETH 359 -pocketserv9200 ARCH_POCKETSERV9200 POCKETSERV9200 360 -toto ARCH_TOTO TOTO 361 s3c2440 ARCH_S3C2440 S3C2440 362 -ks8695p ARCH_KS8695P KS8695P 363 -se4000 ARCH_SE4000 SE4000 364 -quadriceps ARCH_QUADRICEPS QUADRICEPS 365 -bronco ARCH_BRONCO BRONCO 366 -esl_wireless_tab ARCH_ESL_WIRELESS_TAB ESL_WIRELESS_TAB 367 -esl_sofcomp ARCH_ESL_SOFCOMP ESL_SOFCOMP 368 -s5c7375 ARCH_S5C7375 S5C7375 369 -spearhead ARCH_SPEARHEAD SPEARHEAD 370 -pantera ARCH_PANTERA PANTERA 371 -prayoglite ARCH_PRAYOGLITE PRAYOGLITE 372 gumstix ARCH_GUMSTIX GUMSTIX 373 -rcube ARCH_RCUBE RCUBE 374 -rea_olv ARCH_REA_OLV REA_OLV 375 -pxa_iphone ARCH_PXA_IPHONE PXA_IPHONE 376 -s3c3410 ARCH_S3C3410 S3C3410 377 -espd_4510b ARCH_ESPD_4510B ESPD_4510B 378 -mp1x ARCH_MP1X MP1X 379 -at91rm9200tb ARCH_AT91RM9200TB AT91RM9200TB 380 -adsvgx ARCH_ADSVGX ADSVGX 381 omap_h2 MACH_OMAP_H2 OMAP_H2 382 -pelee ARCH_PELEE PELEE 383 e740 MACH_E740 E740 384 iq80331 ARCH_IQ80331 IQ80331 385 versatile_pb ARCH_VERSATILE_PB VERSATILE_PB 387 kev7a400 MACH_KEV7A400 KEV7A400 388 lpd7a400 MACH_LPD7A400 LPD7A400 389 lpd7a404 MACH_LPD7A404 LPD7A404 390 -fujitsu_camelot ARCH_FUJITSU_CAMELOT FUJITSU_CAMELOT 391 -janus2m ARCH_JANUS2M JANUS2M 392 -embtf MACH_EMBTF EMBTF 393 -hpm MACH_HPM HPM 394 -smdk2410tk MACH_SMDK2410TK SMDK2410TK 395 -smdk2410aj MACH_SMDK2410AJ SMDK2410AJ 396 -streetracer MACH_STREETRACER STREETRACER 397 -eframe MACH_EFRAME EFRAME 398 csb337 MACH_CSB337 CSB337 399 -pxa_lark MACH_PXA_LARK PXA_LARK 400 -pxa_pnp2110 MACH_PNP2110 PNP2110 401 -tcc72x MACH_TCC72X TCC72X 402 -altair MACH_ALTAIR ALTAIR 403 -kc3 MACH_KC3 KC3 404 -sinteftd MACH_SINTEFTD SINTEFTD 405 mainstone MACH_MAINSTONE MAINSTONE 406 -aday4x MACH_ADAY4X ADAY4X 407 -lite300 MACH_LITE300 LITE300 408 -s5c7376 MACH_S5C7376 S5C7376 409 -mt02 MACH_MT02 MT02 410 -mport3s MACH_MPORT3S MPORT3S 411 -ra_alpha MACH_RA_ALPHA RA_ALPHA 412 xcep MACH_XCEP XCEP 413 arcom_vulcan MACH_ARCOM_VULCAN ARCOM_VULCAN 414 -stargate MACH_STARGATE STARGATE 415 -armadilloj MACH_ARMADILLOJ ARMADILLOJ 416 -elroy_jack MACH_ELROY_JACK ELROY_JACK 417 -backend MACH_BACKEND BACKEND 418 -s5linbox MACH_S5LINBOX S5LINBOX 419 nomadik MACH_NOMADIK NOMADIK 420 -ia_cpu_9200 MACH_IA_CPU_9200 IA_CPU_9200 421 -at91_bja1 MACH_AT91_BJA1 AT91_BJA1 422 corgi MACH_CORGI CORGI 423 poodle MACH_POODLE POODLE 424 -ten MACH_TEN TEN 425 -roverp5p MACH_ROVERP5P ROVERP5P 426 -sc2700 MACH_SC2700 SC2700 427 -ex_eagle MACH_EX_EAGLE EX_EAGLE 428 -nx_pxa12 MACH_NX_PXA12 NX_PXA12 429 -nx_pxa5 MACH_NX_PXA5 NX_PXA5 430 -blackboard2 MACH_BLACKBOARD2 BLACKBOARD2 431 -i819 MACH_I819 I819 432 -ixmb995e MACH_IXMB995E IXMB995E 433 -skyrider MACH_SKYRIDER SKYRIDER 434 -skyhawk MACH_SKYHAWK SKYHAWK 435 -enterprise MACH_ENTERPRISE ENTERPRISE 436 -dep2410 MACH_DEP2410 DEP2410 437 armcore MACH_ARMCORE ARMCORE 438 -hobbit MACH_HOBBIT HOBBIT 439 -h7210 MACH_H7210 H7210 440 -pxa_netdcu5 MACH_PXA_NETDCU5 PXA_NETDCU5 441 -acc MACH_ACC ACC 442 -esl_sarva MACH_ESL_SARVA ESL_SARVA 443 -xm250 MACH_XM250 XM250 444 -t6tc1xb MACH_T6TC1XB T6TC1XB 445 -ess710 MACH_ESS710 ESS710 446 mx31ads MACH_MX31ADS MX31ADS 447 himalaya MACH_HIMALAYA HIMALAYA 448 -bolfenk MACH_BOLFENK BOLFENK 449 -at91rm9200kr MACH_AT91RM9200KR AT91RM9200KR 450 edb9312 MACH_EDB9312 EDB9312 451 omap_generic MACH_OMAP_GENERIC OMAP_GENERIC 452 -aximx3 MACH_AXIMX3 AXIMX3 453 -eb67xdip MACH_EB67XDIP EB67XDIP 454 -webtxs MACH_WEBTXS WEBTXS 455 -hawk MACH_HAWK HAWK 456 -ccat91sbc001 MACH_CCAT91SBC001 CCAT91SBC001 457 -expresso MACH_EXPRESSO EXPRESSO 458 -h4000 MACH_H4000 H4000 459 -dino MACH_DINO DINO 460 -ml675k MACH_ML675K ML675K 461 edb9301 MACH_EDB9301 EDB9301 462 edb9315 MACH_EDB9315 EDB9315 463 -reciva_tt MACH_RECIVA_TT RECIVA_TT 464 -cstcb01 MACH_CSTCB01 CSTCB01 465 -cstcb1 MACH_CSTCB1 CSTCB1 466 -shadwell MACH_SHADWELL SHADWELL 467 -goepel263 MACH_GOEPEL263 GOEPEL263 468 -acq100 MACH_ACQ100 ACQ100 469 -mx1fs2 MACH_MX1FS2 MX1FS2 470 -hiptop_g1 MACH_HIPTOP_G1 HIPTOP_G1 471 -sparky MACH_SPARKY SPARKY 472 -ns9750 MACH_NS9750 NS9750 473 -phoenix MACH_PHOENIX PHOENIX 474 vr1000 MACH_VR1000 VR1000 475 -deisterpxa MACH_DEISTERPXA DEISTERPXA 476 -bcm1160 MACH_BCM1160 BCM1160 477 -pcm022 MACH_PCM022 PCM022 478 -adsgcx MACH_ADSGCX ADSGCX 479 -dreadnaught MACH_DREADNAUGHT DREADNAUGHT 480 -dm320 MACH_DM320 DM320 481 -markov MACH_MARKOV MARKOV 482 -cos7a400 MACH_COS7A400 COS7A400 483 -milano MACH_MILANO MILANO 484 -ue9328 MACH_UE9328 UE9328 485 -uex255 MACH_UEX255 UEX255 486 -ue2410 MACH_UE2410 UE2410 487 -a620 MACH_A620 A620 488 -ocelot MACH_OCELOT OCELOT 489 -cheetah MACH_CHEETAH CHEETAH 490 omap_perseus2 MACH_OMAP_PERSEUS2 OMAP_PERSEUS2 491 -zvue MACH_ZVUE ZVUE 492 -roverp1 MACH_ROVERP1 ROVERP1 493 -asidial2 MACH_ASIDIAL2 ASIDIAL2 494 -s3c24a0 MACH_S3C24A0 S3C24A0 495 e800 MACH_E800 E800 496 e750 MACH_E750 E750 497 -s3c5500 MACH_S3C5500 S3C5500 498 -smdk5500 MACH_SMDK5500 SMDK5500 499 -signalsync MACH_SIGNALSYNC SIGNALSYNC 500 -nbc MACH_NBC NBC 501 -kodiak MACH_KODIAK KODIAK 502 -netbookpro MACH_NETBOOKPRO NETBOOKPRO 503 -hw90200 MACH_HW90200 HW90200 504 -condor MACH_CONDOR CONDOR 505 -cup MACH_CUP CUP 506 -kite MACH_KITE KITE 507 scb9328 MACH_SCB9328 SCB9328 508 omap_h3 MACH_OMAP_H3 OMAP_H3 509 omap_h4 MACH_OMAP_H4 OMAP_H4 510 -n10 MACH_N10 N10 511 -montejade MACH_MONTAJADE MONTAJADE 512 -sg560 MACH_SG560 SG560 513 -dp1000 MACH_DP1000 DP1000 514 omap_osk MACH_OMAP_OSK OMAP_OSK 515 -rg100v3 MACH_RG100V3 RG100V3 516 -mx2ads MACH_MX2ADS MX2ADS 517 -pxa_kilo MACH_PXA_KILO PXA_KILO 518 -ixp4xx_eagle MACH_IXP4XX_EAGLE IXP4XX_EAGLE 519 tosa MACH_TOSA TOSA 520 -mb2520f MACH_MB2520F MB2520F 521 -emc1000 MACH_EMC1000 EMC1000 522 -tidsc25 MACH_TIDSC25 TIDSC25 523 -akcpmxl MACH_AKCPMXL AKCPMXL 524 -av3xx MACH_AV3XX AV3XX 525 avila MACH_AVILA AVILA 526 -pxa_mpm10 MACH_PXA_MPM10 PXA_MPM10 527 -pxa_kyanite MACH_PXA_KYANITE PXA_KYANITE 528 -sgold MACH_SGOLD SGOLD 529 -oscar MACH_OSCAR OSCAR 530 -epxa4usb2 MACH_EPXA4USB2 EPXA4USB2 531 -xsengine MACH_XSENGINE XSENGINE 532 -ip600 MACH_IP600 IP600 533 -mcan2 MACH_MCAN2 MCAN2 534 -ddi_blueridge MACH_DDI_BLUERIDGE DDI_BLUERIDGE 535 -skyminder MACH_SKYMINDER SKYMINDER 536 -lpd79520 MACH_LPD79520 LPD79520 537 edb9302 MACH_EDB9302 EDB9302 538 -hw90340 MACH_HW90340 HW90340 539 -cip_box MACH_CIP_BOX CIP_BOX 540 -ivpn MACH_IVPN IVPN 541 -rsoc2 MACH_RSOC2 RSOC2 542 husky MACH_HUSKY HUSKY 543 -boxer MACH_BOXER BOXER 544 shepherd MACH_SHEPHERD SHEPHERD 545 -aml42800aa MACH_AML42800AA AML42800AA 546 -lpc2294 MACH_LPC2294 LPC2294 548 -switchgrass MACH_SWITCHGRASS SWITCHGRASS 549 -ens_cmu MACH_ENS_CMU ENS_CMU 550 -mm6_sdb MACH_MM6_SDB MM6_SDB 551 -saturn MACH_SATURN SATURN 552 -i30030evb MACH_I30030EVB I30030EVB 553 -mxc27530evb MACH_MXC27530EVB MXC27530EVB 554 -smdk2800 MACH_SMDK2800 SMDK2800 555 -mtwilson MACH_MTWILSON MTWILSON 556 -ziti MACH_ZITI ZITI 557 -grandfather MACH_GRANDFATHER GRANDFATHER 558 -tengine MACH_TENGINE TENGINE 559 -s3c2460 MACH_S3C2460 S3C2460 560 -pdm MACH_PDM PDM 561 h4700 MACH_H4700 H4700 562 -h6300 MACH_H6300 H6300 563 -rz1700 MACH_RZ1700 RZ1700 564 -a716 MACH_A716 A716 565 -estk2440a MACH_ESTK2440A ESTK2440A 566 -atwixp425 MACH_ATWIXP425 ATWIXP425 567 -csb336 MACH_CSB336 CSB336 568 -rirm2 MACH_RIRM2 RIRM2 569 -cx23518 MACH_CX23518 CX23518 570 -cx2351x MACH_CX2351X CX2351X 571 -computime MACH_COMPUTIME COMPUTIME 572 -izarus MACH_IZARUS IZARUS 573 -pxa_rts MACH_RTS RTS 574 -se5100 MACH_SE5100 SE5100 575 -s3c2510 MACH_S3C2510 S3C2510 576 -csb437tl MACH_CSB437TL CSB437TL 577 -slauson MACH_SLAUSON SLAUSON 578 -pearlriver MACH_PEARLRIVER PEARLRIVER 579 -tdc_p210 MACH_TDC_P210 TDC_P210 580 -sg580 MACH_SG580 SG580 581 -wrsbcarm7 MACH_WRSBCARM7 WRSBCARM7 582 -ipd MACH_IPD IPD 583 -pxa_dnp2110 MACH_PXA_DNP2110 PXA_DNP2110 584 -xaeniax MACH_XAENIAX XAENIAX 585 -somn4250 MACH_SOMN4250 SOMN4250 586 -pleb2 MACH_PLEB2 PLEB2 587 -cornwallis MACH_CORNWALLIS CORNWALLIS 588 -gurney_drv MACH_GURNEY_DRV GURNEY_DRV 589 -chaffee MACH_CHAFFEE CHAFFEE 590 -rms101 MACH_RMS101 RMS101 591 rx3715 MACH_RX3715 RX3715 592 -swift MACH_SWIFT SWIFT 593 -roverp7 MACH_ROVERP7 ROVERP7 594 -pr818s MACH_PR818S PR818S 595 -trxpro MACH_TRXPRO TRXPRO 596 nslu2 MACH_NSLU2 NSLU2 597 e400 MACH_E400 E400 598 -trab MACH_TRAB TRAB 599 -cmc_pu2 MACH_CMC_PU2 CMC_PU2 600 -fulcrum MACH_FULCRUM FULCRUM 601 -netgate42x MACH_NETGATE42X NETGATE42X 602 -str710 MACH_STR710 STR710 603 ixdpg425 MACH_IXDPG425 IXDPG425 604 -tomtomgo MACH_TOMTOMGO TOMTOMGO 605 versatile_ab MACH_VERSATILE_AB VERSATILE_AB 606 edb9307 MACH_EDB9307 EDB9307 607 -sg565 MACH_SG565 SG565 608 -lpd79524 MACH_LPD79524 LPD79524 609 -lpd79525 MACH_LPD79525 LPD79525 610 -rms100 MACH_RMS100 RMS100 611 kb9200 MACH_KB9200 KB9200 612 sx1 MACH_SX1 SX1 613 -hms39c7092 MACH_HMS39C7092 HMS39C7092 614 -armadillo MACH_ARMADILLO ARMADILLO 615 -ipcu MACH_IPCU IPCU 616 -loox720 MACH_LOOX720 LOOX720 617 ixdp465 MACH_IXDP465 IXDP465 618 ixdp2351 MACH_IXDP2351 IXDP2351 619 -adsvix MACH_ADSVIX ADSVIX 620 -dm270 MACH_DM270 DM270 621 -socltplus MACH_SOCLTPLUS SOCLTPLUS 622 -ecia MACH_ECIA ECIA 623 -cm4008 MACH_CM4008 CM4008 624 -p2001 MACH_P2001 P2001 625 -twister MACH_TWISTER TWISTER 626 -mudshark MACH_MUDSHARK MUDSHARK 627 -hb2 MACH_HB2 HB2 628 iq80332 MACH_IQ80332 IQ80332 629 -sendt MACH_SENDT SENDT 630 -mx2jazz MACH_MX2JAZZ MX2JAZZ 631 -multiio MACH_MULTIIO MULTIIO 632 -hrdisplay MACH_HRDISPLAY HRDISPLAY 633 -mxc27530ads MACH_MXC27530ADS MXC27530ADS 634 -trizeps3 MACH_TRIZEPS3 TRIZEPS3 635 -zefeerdza MACH_ZEFEERDZA ZEFEERDZA 636 -zefeerdzb MACH_ZEFEERDZB ZEFEERDZB 637 -zefeerdzg MACH_ZEFEERDZG ZEFEERDZG 638 -zefeerdzn MACH_ZEFEERDZN ZEFEERDZN 639 -zefeerdzq MACH_ZEFEERDZQ ZEFEERDZQ 640 gtwx5715 MACH_GTWX5715 GTWX5715 641 -astro_jack MACH_ASTRO_JACK ASTRO_JACK 643 -tip03 MACH_TIP03 TIP03 644 -a9200ec MACH_A9200EC A9200EC 645 -pnx0105 MACH_PNX0105 PNX0105 646 -adcpoecpu MACH_ADCPOECPU ADCPOECPU 647 csb637 MACH_CSB637 CSB637 648 -mb9200 MACH_MB9200 MB9200 650 -kulun MACH_KULUN KULUN 651 -snapper MACH_SNAPPER SNAPPER 652 -optima MACH_OPTIMA OPTIMA 653 -dlhsbc MACH_DLHSBC DLHSBC 654 -x30 MACH_X30 X30 655 n30 MACH_N30 N30 656 -manga_ks8695 MACH_MANGA_KS8695 MANGA_KS8695 657 -ajax MACH_AJAX AJAX 658 nec_mp900 MACH_NEC_MP900 NEC_MP900 659 -vvtk1000 MACH_VVTK1000 VVTK1000 661 kafa MACH_KAFA KAFA 662 -vvtk3000 MACH_VVTK3000 VVTK3000 663 -pimx1 MACH_PIMX1 PIMX1 664 -ollie MACH_OLLIE OLLIE 665 -skymax MACH_SKYMAX SKYMAX 666 -jazz MACH_JAZZ JAZZ 667 -tel_t3 MACH_TEL_T3 TEL_T3 668 -aisino_fcr255 MACH_AISINO_FCR255 AISINO_FCR255 669 -btweb MACH_BTWEB BTWEB 670 -dbg_lh79520 MACH_DBG_LH79520 DBG_LH79520 671 -cm41xx MACH_CM41XX CM41XX 672 ts72xx MACH_TS72XX TS72XX 673 -nggpxa MACH_NGGPXA NGGPXA 674 -csb535 MACH_CSB535 CSB535 675 -csb536 MACH_CSB536 CSB536 676 -pxa_trakpod MACH_PXA_TRAKPOD PXA_TRAKPOD 677 -praxis MACH_PRAXIS PRAXIS 678 -lh75411 MACH_LH75411 LH75411 679 otom MACH_OTOM OTOM 680 nexcoder_2440 MACH_NEXCODER_2440 NEXCODER_2440 681 -loox410 MACH_LOOX410 LOOX410 682 -westlake MACH_WESTLAKE WESTLAKE 683 -nsb MACH_NSB NSB 684 -esl_sarva_stn MACH_ESL_SARVA_STN ESL_SARVA_STN 685 -esl_sarva_tft MACH_ESL_SARVA_TFT ESL_SARVA_TFT 686 -esl_sarva_iad MACH_ESL_SARVA_IAD ESL_SARVA_IAD 687 -esl_sarva_acc MACH_ESL_SARVA_ACC ESL_SARVA_ACC 688 -typhoon MACH_TYPHOON TYPHOON 689 -cnav MACH_CNAV CNAV 690 -a730 MACH_A730 A730 691 -netstar MACH_NETSTAR NETSTAR 692 -supercon MACH_PHASEFALE_SUPERCON PHASEFALE_SUPERCON 693 -shiva1100 MACH_SHIVA1100 SHIVA1100 694 -etexsc MACH_ETEXSC ETEXSC 695 -ixdpg465 MACH_IXDPG465 IXDPG465 696 -a9m2410 MACH_A9M2410 A9M2410 697 -a9m2440 MACH_A9M2440 A9M2440 698 -a9m9750 MACH_A9M9750 A9M9750 699 -a9m9360 MACH_A9M9360 A9M9360 700 -unc90 MACH_UNC90 UNC90 701 eco920 MACH_ECO920 ECO920 702 -satview MACH_SATVIEW SATVIEW 703 roadrunner MACH_ROADRUNNER ROADRUNNER 704 at91rm9200ek MACH_AT91RM9200EK AT91RM9200EK 705 -gp32 MACH_GP32 GP32 706 -gem MACH_GEM GEM 707 -i858 MACH_I858 I858 708 -hx2750 MACH_HX2750 HX2750 709 -mxc91131evb MACH_MXC91131EVB MXC91131EVB 710 -p700 MACH_P700 P700 711 -cpe MACH_CPE CPE 712 spitz MACH_SPITZ SPITZ 713 -nimbra340 MACH_NIMBRA340 NIMBRA340 714 -lpc22xx MACH_LPC22XX LPC22XX 715 -omap_comet3 MACH_COMET3 COMET3 716 -omap_comet4 MACH_COMET4 COMET4 717 -csb625 MACH_CSB625 CSB625 718 -fortunet2 MACH_FORTUNET2 FORTUNET2 719 -s5h2200 MACH_S5H2200 S5H2200 720 -optorm920 MACH_OPTORM920 OPTORM920 721 -adsbitsyxb MACH_ADSBITSYXB ADSBITSYXB 722 adssphere MACH_ADSSPHERE ADSSPHERE 723 -adsportal MACH_ADSPORTAL ADSPORTAL 724 -ln2410sbc MACH_LN2410SBC LN2410SBC 725 -cb3rufc MACH_CB3RUFC CB3RUFC 726 -mp2usb MACH_MP2USB MP2USB 727 -ntnp425c MACH_NTNP425C NTNP425C 728 colibri MACH_COLIBRI COLIBRI 729 -pcm7220 MACH_PCM7220 PCM7220 730 gateway7001 MACH_GATEWAY7001 GATEWAY7001 731 pcm027 MACH_PCM027 PCM027 732 -cmpxa MACH_CMPXA CMPXA 733 anubis MACH_ANUBIS ANUBIS 734 -ite8152 MACH_ITE8152 ITE8152 735 -lpc3xxx MACH_LPC3XXX LPC3XXX 736 -puppeteer MACH_PUPPETEER PUPPETEER 737 -e570 MACH_E570 E570 739 -x50 MACH_X50 X50 740 -recon MACH_RECON RECON 741 -xboardgp8 MACH_XBOARDGP8 XBOARDGP8 742 -fpic2 MACH_FPIC2 FPIC2 743 akita MACH_AKITA AKITA 744 -a81 MACH_A81 A81 745 -svm_sc25x MACH_SVM_SC25X SVM_SC25X 746 -vt020 MACH_VADATECH020 VADATECH020 747 -tli MACH_TLI TLI 748 -edb9315lc MACH_EDB9315LC EDB9315LC 749 -passec MACH_PASSEC PASSEC 750 -ds_tiger MACH_DS_TIGER DS_TIGER 751 -e310 MACH_E310 E310 752 e330 MACH_E330 E330 753 -rt3000 MACH_RT3000 RT3000 754 nokia770 MACH_NOKIA770 NOKIA770 755 -pnx0106 MACH_PNX0106 PNX0106 756 -hx21xx MACH_HX21XX HX21XX 757 -faraday MACH_FARADAY FARADAY 758 -sbc9312 MACH_SBC9312 SBC9312 759 -batman MACH_BATMAN BATMAN 760 -jpd201 MACH_JPD201 JPD201 761 -mipsa MACH_MIPSA MIPSA 762 -kacom MACH_KACOM KACOM 763 -swarcocpu MACH_SWARCOCPU SWARCOCPU 764 -swarcodsl MACH_SWARCODSL SWARCODSL 765 -blueangel MACH_BLUEANGEL BLUEANGEL 766 -hairygrama MACH_HAIRYGRAMA HAIRYGRAMA 767 -banff MACH_BANFF BANFF 768 carmeva MACH_CARMEVA CARMEVA 769 -sam255 MACH_SAM255 SAM255 770 -ppm10 MACH_PPM10 PPM10 771 edb9315a MACH_EDB9315A EDB9315A 772 -sunset MACH_SUNSET SUNSET 773 stargate2 MACH_STARGATE2 STARGATE2 774 intelmote2 MACH_INTELMOTE2 INTELMOTE2 775 trizeps4 MACH_TRIZEPS4 TRIZEPS4 776 -mainstone2 MACH_MAINSTONE2 MAINSTONE2 777 -ez_ixp42x MACH_EZ_IXP42X EZ_IXP42X 778 -tapwave_zodiac MACH_TAPWAVE_ZODIAC TAPWAVE_ZODIAC 779 -universalmeter MACH_UNIVERSALMETER UNIVERSALMETER 780 -hicoarm9 MACH_HICOARM9 HICOARM9 781 pnx4008 MACH_PNX4008 PNX4008 782 -kws6000 MACH_KWS6000 KWS6000 783 -portux920t MACH_PORTUX920T PORTUX920T 784 -ez_x5 MACH_EZ_X5 EZ_X5 785 -omap_rudolph MACH_OMAP_RUDOLPH OMAP_RUDOLPH 786 cpuat91 MACH_CPUAT91 CPUAT91 787 -rea9200 MACH_REA9200 REA9200 788 -acts_pune_sa1110 MACH_ACTS_PUNE_SA1110 ACTS_PUNE_SA1110 789 -ixp425 MACH_IXP425 IXP425 790 -i30030ads MACH_I30030ADS I30030ADS 791 -perch MACH_PERCH PERCH 792 -eis05r1 MACH_EIS05R1 EIS05R1 793 -pepperpad MACH_PEPPERPAD PEPPERPAD 794 -sb3010 MACH_SB3010 SB3010 795 -rm9200 MACH_RM9200 RM9200 796 -dma03 MACH_DMA03 DMA03 797 -road_s101 MACH_ROAD_S101 ROAD_S101 798 iq81340sc MACH_IQ81340SC IQ81340SC 799 -iq_nextgen_b MACH_IQ_NEXTGEN_B IQ_NEXTGEN_B 800 iq81340mc MACH_IQ81340MC IQ81340MC 801 -iq_nextgen_d MACH_IQ_NEXTGEN_D IQ_NEXTGEN_D 802 -iq_nextgen_e MACH_IQ_NEXTGEN_E IQ_NEXTGEN_E 803 -mallow_at91 MACH_MALLOW_AT91 MALLOW_AT91 804 -cybertracker_i MACH_CYBERTRACKER_I CYBERTRACKER_I 805 -gesbc931x MACH_GESBC931X GESBC931X 806 -centipad MACH_CENTIPAD CENTIPAD 807 -armsoc MACH_ARMSOC ARMSOC 808 -se4200 MACH_SE4200 SE4200 809 -ems197a MACH_EMS197A EMS197A 810 micro9 MACH_MICRO9 MICRO9 811 micro9l MACH_MICRO9L MICRO9L 812 -uc5471dsp MACH_UC5471DSP UC5471DSP 813 -sj5471eng MACH_SJ5471ENG SJ5471ENG 814 -none MACH_CMPXA26X CMPXA26X 815 -nc1 MACH_NC NC 816 omap_palmte MACH_OMAP_PALMTE OMAP_PALMTE 817 -ajax52x MACH_AJAX52X AJAX52X 818 -siriustar MACH_SIRIUSTAR SIRIUSTAR 819 -iodata_hdlg MACH_IODATA_HDLG IODATA_HDLG 820 -at91rm9200utl MACH_AT91RM9200UTL AT91RM9200UTL 821 -biosafe MACH_BIOSAFE BIOSAFE 822 -mp1000 MACH_MP1000 MP1000 823 -parsy MACH_PARSY PARSY 824 -ccxp270 MACH_CCXP CCXP 825 -omap_gsample MACH_OMAP_GSAMPLE OMAP_GSAMPLE 826 realview_eb MACH_REALVIEW_EB REALVIEW_EB 827 -samoa MACH_SAMOA SAMOA 828 -palmt3 MACH_PALMT3 PALMT3 829 -i878 MACH_I878 I878 830 borzoi MACH_BORZOI BORZOI 831 -gecko MACH_GECKO GECKO 832 -ds101 MACH_DS101 DS101 833 -omap_palmtt2 MACH_OMAP_PALMTT2 OMAP_PALMTT2 834 palmld MACH_PALMLD PALMLD 835 -cc9c MACH_CC9C CC9C 836 -sbc1670 MACH_SBC1670 SBC1670 837 ixdp28x5 MACH_IXDP28X5 IXDP28X5 838 omap_palmtt MACH_OMAP_PALMTT OMAP_PALMTT 839 -ml696k MACH_ML696K ML696K 840 arcom_zeus MACH_ARCOM_ZEUS ARCOM_ZEUS 841 osiris MACH_OSIRIS OSIRIS 842 -maestro MACH_MAESTRO MAESTRO 843 palmte2 MACH_PALMTE2 PALMTE2 844 -ixbbm MACH_IXBBM IXBBM 845 mx27ads MACH_MX27ADS MX27ADS 846 -ax8004 MACH_AX8004 AX8004 847 at91sam9261ek MACH_AT91SAM9261EK AT91SAM9261EK 848 loft MACH_LOFT LOFT 849 -magpie MACH_MAGPIE MAGPIE 850 mx21ads MACH_MX21ADS MX21ADS 851 -mb87m3400 MACH_MB87M3400 MB87M3400 852 -mguard_delta MACH_MGUARD_DELTA MGUARD_DELTA 853 -davinci_dvdp MACH_DAVINCI_DVDP DAVINCI_DVDP 854 -htcuniversal MACH_HTCUNIVERSAL HTCUNIVERSAL 855 -tpad MACH_TPAD TPAD 856 -roverp3 MACH_ROVERP3 ROVERP3 857 -jornada928 MACH_JORNADA928 JORNADA928 858 -mv88fxx81 MACH_MV88FXX81 MV88FXX81 859 -stmp36xx MACH_STMP36XX STMP36XX 860 -sxni79524 MACH_SXNI79524 SXNI79524 861 ams_delta MACH_AMS_DELTA AMS_DELTA 862 -uranium MACH_URANIUM URANIUM 863 -ucon MACH_UCON UCON 864 nas100d MACH_NAS100D NAS100D 865 -l083 MACH_L083_1000 L083_1000 866 -ezx MACH_EZX EZX 867 -pnx5220 MACH_PNX5220 PNX5220 868 -butte MACH_BUTTE BUTTE 869 -srm2 MACH_SRM2 SRM2 870 -dsbr MACH_DSBR DSBR 871 -crystalball MACH_CRYSTALBALL CRYSTALBALL 872 -tinypxa27x MACH_TINYPXA27X TINYPXA27X 873 -herbie MACH_HERBIE HERBIE 874 magician MACH_MAGICIAN MAGICIAN 875 -cm4002 MACH_CM4002 CM4002 876 -b4 MACH_B4 B4 877 -maui MACH_MAUI MAUI 878 -cybertracker_g MACH_CYBERTRACKER_G CYBERTRACKER_G 879 nxdkn MACH_NXDKN NXDKN 880 -mio8390 MACH_MIO8390 MIO8390 881 -omi_board MACH_OMI_BOARD OMI_BOARD 882 -mx21civ MACH_MX21CIV MX21CIV 883 -mahi_cdac MACH_MAHI_CDAC MAHI_CDAC 884 palmtx MACH_PALMTX PALMTX 885 s3c2413 MACH_S3C2413 S3C2413 887 -samsys_ep0 MACH_SAMSYS_EP0 SAMSYS_EP0 888 -wg302v1 MACH_WG302V1 WG302V1 889 wg302v2 MACH_WG302V2 WG302V2 890 -eb42x MACH_EB42X EB42X 891 -iq331es MACH_IQ331ES IQ331ES 892 -cosydsp MACH_COSYDSP COSYDSP 893 -uplat7d_proto MACH_UPLAT7D UPLAT7D 894 -ptdavinci MACH_PTDAVINCI PTDAVINCI 895 -mbus MACH_MBUS MBUS 896 -nadia2vb MACH_NADIA2VB NADIA2VB 897 -r1000 MACH_R1000 R1000 898 -hw90250 MACH_HW90250 HW90250 899 omap_2430sdp MACH_OMAP_2430SDP OMAP_2430SDP 900 davinci_evm MACH_DAVINCI_EVM DAVINCI_EVM 901 -omap_tornado MACH_OMAP_TORNADO OMAP_TORNADO 902 -olocreek MACH_OLOCREEK OLOCREEK 903 palmz72 MACH_PALMZ72 PALMZ72 904 nxdb500 MACH_NXDB500 NXDB500 905 -apf9328 MACH_APF9328 APF9328 906 -omap_wipoq MACH_OMAP_WIPOQ OMAP_WIPOQ 907 -omap_twip MACH_OMAP_TWIP OMAP_TWIP 908 -treo650 MACH_TREO650 TREO650 909 -acumen MACH_ACUMEN ACUMEN 910 -xp100 MACH_XP100 XP100 911 -fs2410 MACH_FS2410 FS2410 912 -pxa270_cerf MACH_PXA270_CERF PXA270_CERF 913 -sq2ftlpalm MACH_SQ2FTLPALM SQ2FTLPALM 914 -bsemserver MACH_BSEMSERVER BSEMSERVER 915 -netclient MACH_NETCLIENT NETCLIENT 916 palmt5 MACH_PALMT5 PALMT5 917 palmtc MACH_PALMTC PALMTC 918 omap_apollon MACH_OMAP_APOLLON OMAP_APOLLON 919 -mxc30030evb MACH_MXC30030EVB MXC30030EVB 920 -rea_cpu2 MACH_REA_2D REA_2D 921 -eti3e524 MACH_TI3E524 TI3E524 922 ateb9200 MACH_ATEB9200 ATEB9200 923 -auckland MACH_AUCKLAND AUCKLAND 924 -ak3220m MACH_AK3320M AK3320M 925 -duramax MACH_DURAMAX DURAMAX 926 n35 MACH_N35 N35 927 -pronghorn MACH_PRONGHORN PRONGHORN 928 -fundy MACH_FUNDY FUNDY 929 logicpd_pxa270 MACH_LOGICPD_PXA270 LOGICPD_PXA270 930 -cpu777 MACH_CPU777 CPU777 931 -simicon9201 MACH_SIMICON9201 SIMICON9201 932 -leap2_hpm MACH_LEAP2_HPM LEAP2_HPM 933 -cm922txa10 MACH_CM922TXA10 CM922TXA10 934 -sandgate MACH_PXA PXA 935 -sandgate2 MACH_SANDGATE2 SANDGATE2 936 -sandgate2g MACH_SANDGATE2G SANDGATE2G 937 -sandgate2p MACH_SANDGATE2P SANDGATE2P 938 -fred_jack MACH_FRED_JACK FRED_JACK 939 -ttg_color1 MACH_TTG_COLOR1 TTG_COLOR1 940 nxeb500hmi MACH_NXEB500HMI NXEB500HMI 941 -netdcu8 MACH_NETDCU8 NETDCU8 942 -ng_fvx538 MACH_NG_FVX538 NG_FVX538 944 -ng_fvs338 MACH_NG_FVS338 NG_FVS338 945 -pnx4103 MACH_PNX4103 PNX4103 946 -hesdb MACH_HESDB HESDB 947 -xsilo MACH_XSILO XSILO 948 espresso MACH_ESPRESSO ESPRESSO 949 -emlc MACH_EMLC EMLC 950 -sisteron MACH_SISTERON SISTERON 951 rx1950 MACH_RX1950 RX1950 952 -tsc_venus MACH_TSC_VENUS TSC_VENUS 953 -ds101j MACH_DS101J DS101J 954 -mxc30030ads MACH_MXC30030ADS MXC30030ADS 955 -fujitsu_wimaxsoc MACH_FUJITSU_WIMAXSOC FUJITSU_WIMAXSOC 956 -dualpcmodem MACH_DUALPCMODEM DUALPCMODEM 957 gesbc9312 MACH_GESBC9312 GESBC9312 958 -htcapache MACH_HTCAPACHE HTCAPACHE 959 -ixdp435 MACH_IXDP435 IXDP435 960 -catprovt100 MACH_CATPROVT100 CATPROVT100 961 -picotux1xx MACH_PICOTUX1XX PICOTUX1XX 962 picotux2xx MACH_PICOTUX2XX PICOTUX2XX 963 dsmg600 MACH_DSMG600 DSMG600 964 -empc2 MACH_EMPC2 EMPC2 965 -ventura MACH_VENTURA VENTURA 966 -phidget_sbc MACH_PHIDGET_SBC PHIDGET_SBC 967 -ij3k MACH_IJ3K IJ3K 968 -pisgah MACH_PISGAH PISGAH 969 omap_fsample MACH_OMAP_FSAMPLE OMAP_FSAMPLE 970 -sg720 MACH_SG720 SG720 971 -redfox MACH_REDFOX REDFOX 972 -mysh_ep9315_1 MACH_MYSH_EP9315_1 MYSH_EP9315_1 973 -tpf106 MACH_TPF106 TPF106 974 -at91rm9200kg MACH_AT91RM9200KG AT91RM9200KG 975 -rcmt2 MACH_SLEDB SLEDB 976 -ontrack MACH_ONTRACK ONTRACK 977 -pm1200 MACH_PM1200 PM1200 978 -ess24562 MACH_ESS24XXX ESS24XXX 979 -coremp7 MACH_COREMP7 COREMP7 980 -nexcoder_6446 MACH_NEXCODER_6446 NEXCODER_6446 981 -stvc8380 MACH_STVC8380 STVC8380 982 -teklynx MACH_TEKLYNX TEKLYNX 983 -carbonado MACH_CARBONADO CARBONADO 984 -sysmos_mp730 MACH_SYSMOS_MP730 SYSMOS_MP730 985 snapper_cl15 MACH_SNAPPER_CL15 SNAPPER_CL15 986 -pgigim MACH_PGIGIM PGIGIM 987 -ptx9160p2 MACH_PTX9160P2 PTX9160P2 988 -dcore1 MACH_DCORE1 DCORE1 989 -victorpxa MACH_VICTORPXA VICTORPXA 990 -mx2dtb MACH_MX2DTB MX2DTB 991 -pxa_irex_er0100 MACH_PXA_IREX_ER0100 PXA_IREX_ER0100 992 omap_palmz71 MACH_OMAP_PALMZ71 OMAP_PALMZ71 993 -bartec_deg MACH_BARTEC_DEG BARTEC_DEG 994 -hw50251 MACH_HW50251 HW50251 995 -ibox MACH_IBOX IBOX 996 -atlaslh7a404 MACH_ATLASLH7A404 ATLASLH7A404 997 -pt2026 MACH_PT2026 PT2026 998 -htcalpine MACH_HTCALPINE HTCALPINE 999 -bartec_vtu MACH_BARTEC_VTU BARTEC_VTU 1000 -vcoreii MACH_VCOREII VCOREII 1001 -pdnb3 MACH_PDNB3 PDNB3 1002 -htcbeetles MACH_HTCBEETLES HTCBEETLES 1003 -s3c6400 MACH_S3C6400 S3C6400 1004 -s3c2443 MACH_S3C2443 S3C2443 1005 -omap_ldk MACH_OMAP_LDK OMAP_LDK 1006 -smdk2460 MACH_SMDK2460 SMDK2460 1007 -smdk2440 MACH_SMDK2440 SMDK2440 1008 smdk2412 MACH_SMDK2412 SMDK2412 1009 -webbox MACH_WEBBOX WEBBOX 1010 -cwwndp MACH_CWWNDP CWWNDP 1011 -i839 MACH_DRAGON DRAGON 1012 -opendo_cpu_board MACH_OPENDO_CPU_BOARD OPENDO_CPU_BOARD 1013 -ccm2200 MACH_CCM2200 CCM2200 1014 -etwarm MACH_ETWARM ETWARM 1015 -m93030 MACH_M93030 M93030 1016 -cc7u MACH_CC7U CC7U 1017 -mtt_ranger MACH_MTT_RANGER MTT_RANGER 1018 -nexus MACH_NEXUS NEXUS 1019 -desman MACH_DESMAN DESMAN 1020 -bkde303 MACH_BKDE303 BKDE303 1021 smdk2413 MACH_SMDK2413 SMDK2413 1022 -aml_m7200 MACH_AML_M7200 AML_M7200 1023 aml_m5900 MACH_AML_M5900 AML_M5900 1024 -sg640 MACH_SG640 SG640 1025 -edg79524 MACH_EDG79524 EDG79524 1026 -ai2410 MACH_AI2410 AI2410 1027 -ixp465 MACH_IXP465 IXP465 1028 balloon3 MACH_BALLOON3 BALLOON3 1029 -heins MACH_HEINS HEINS 1030 -mpluseva MACH_MPLUSEVA MPLUSEVA 1031 -rt042 MACH_RT042 RT042 1032 -cwiem MACH_CWIEM CWIEM 1033 -cm_x270 MACH_CM_X270 CM_X270 1034 -cm_x255 MACH_CM_X255 CM_X255 1035 -esh_at91 MACH_ESH_AT91 ESH_AT91 1036 -sandgate3 MACH_SANDGATE3 SANDGATE3 1037 -primo MACH_PRIMO PRIMO 1038 -gemstone MACH_GEMSTONE GEMSTONE 1039 -pronghorn_metro MACH_PRONGHORNMETRO PRONGHORNMETRO 1040 -sidewinder MACH_SIDEWINDER SIDEWINDER 1041 -picomod1 MACH_PICOMOD1 PICOMOD1 1042 -sg590 MACH_SG590 SG590 1043 -akai9307 MACH_AKAI9307 AKAI9307 1044 -fontaine MACH_FONTAINE FONTAINE 1045 -wombat MACH_WOMBAT WOMBAT 1046 -acq300 MACH_ACQ300 ACQ300 1047 -mod272 MACH_MOD_270 MOD_270 1048 -vmc_vc0820 MACH_VC0820 VC0820 1049 -ani_aim MACH_ANI_AIM ANI_AIM 1050 -jellyfish MACH_JELLYFISH JELLYFISH 1051 -amanita MACH_AMANITA AMANITA 1052 -vlink MACH_VLINK VLINK 1053 -dexflex MACH_DEXFLEX DEXFLEX 1054 -eigen_ttq MACH_EIGEN_TTQ EIGEN_TTQ 1055 -arcom_titan MACH_ARCOM_TITAN ARCOM_TITAN 1056 -tabla MACH_TABLA TABLA 1057 -mdirac3 MACH_MDIRAC3 MDIRAC3 1058 -mrhfbp2 MACH_MRHFBP2 MRHFBP2 1059 -at91rm9200rb MACH_AT91RM9200RB AT91RM9200RB 1060 -ani_apm MACH_ANI_APM ANI_APM 1061 -ella1 MACH_ELLA1 ELLA1 1062 -inhand_pxa27x MACH_INHAND_PXA27X INHAND_PXA27X 1063 -inhand_pxa25x MACH_INHAND_PXA25X INHAND_PXA25X 1064 -empos_xm MACH_EMPOS_XM EMPOS_XM 1065 -empos MACH_EMPOS EMPOS 1066 -empos_tiny MACH_EMPOS_TINY EMPOS_TINY 1067 -empos_sm MACH_EMPOS_SM EMPOS_SM 1068 -egret MACH_EGRET EGRET 1069 -ostrich MACH_OSTRICH OSTRICH 1070 -n50 MACH_N50 N50 1071 ecbat91 MACH_ECBAT91 ECBAT91 1072 -stareast MACH_STAREAST STAREAST 1073 -dspg_dw MACH_DSPG_DW DSPG_DW 1074 onearm MACH_ONEARM ONEARM 1075 -mrg110_6 MACH_MRG110_6 MRG110_6 1076 -wrt300nv2 MACH_WRT300NV2 WRT300NV2 1077 -xm_bulverde MACH_XM_BULVERDE XM_BULVERDE 1078 -msm6100 MACH_MSM6100 MSM6100 1079 -eti_b1 MACH_ETI_B1 ETI_B1 1080 -za9l_series MACH_ZILOG_ZA9L ZILOG_ZA9L 1081 -bit2440 MACH_BIT2440 BIT2440 1082 -nbi MACH_NBI NBI 1083 smdk2443 MACH_SMDK2443 SMDK2443 1084 -vdavinci MACH_VDAVINCI VDAVINCI 1085 -atc6 MACH_ATC6 ATC6 1086 -multmdw MACH_MULTMDW MULTMDW 1087 -mba2440 MACH_MBA2440 MBA2440 1088 -ecsd MACH_ECSD ECSD 1089 -palmz31 MACH_PALMZ31 PALMZ31 1090 fsg MACH_FSG FSG 1091 -razor101 MACH_RAZOR101 RAZOR101 1092 -opera_tdm MACH_OPERA_TDM OPERA_TDM 1093 -comcerto MACH_COMCERTO COMCERTO 1094 -tb0319 MACH_TB0319 TB0319 1095 -kws8000 MACH_KWS8000 KWS8000 1096 -b2 MACH_B2 B2 1097 -lcl54 MACH_LCL54 LCL54 1098 at91sam9260ek MACH_AT91SAM9260EK AT91SAM9260EK 1099 glantank MACH_GLANTANK GLANTANK 1100 n2100 MACH_N2100 N2100 1101 -n4100 MACH_N4100 N4100 1102 -rsc4 MACH_VERTICAL_RSC4 VERTICAL_RSC4 1103 -sg8100 MACH_SG8100 SG8100 1104 -im42xx MACH_IM42XX IM42XX 1105 -ftxx MACH_FTXX FTXX 1106 -lwfusion MACH_LWFUSION LWFUSION 1107 qt2410 MACH_QT2410 QT2410 1108 kixrp435 MACH_KIXRP435 KIXRP435 1109 -ccw9c MACH_CCW9C CCW9C 1110 -dabhs MACH_DABHS DABHS 1111 -gzmx MACH_GZMX GZMX 1112 -ipnw100ap MACH_IPNW100AP IPNW100AP 1113 cc9p9360dev MACH_CC9P9360DEV CC9P9360DEV 1114 -cc9p9750dev MACH_CC9P9750DEV CC9P9750DEV 1115 -cc9p9360val MACH_CC9P9360VAL CC9P9360VAL 1116 -cc9p9750val MACH_CC9P9750VAL CC9P9750VAL 1117 -nx70v MACH_NX70V NX70V 1118 -at91rm9200df MACH_AT91RM9200DF AT91RM9200DF 1119 -se_pilot2 MACH_SE_PILOT2 SE_PILOT2 1120 -mtcn_t800 MACH_MTCN_T800 MTCN_T800 1121 -vcmx212 MACH_VCMX212 VCMX212 1122 -lynx MACH_LYNX LYNX 1123 -at91sam9260id MACH_AT91SAM9260ID AT91SAM9260ID 1124 -hw86052 MACH_HW86052 HW86052 1125 -pilz_pmi3 MACH_PILZ_PMI3 PILZ_PMI3 1126 edb9302a MACH_EDB9302A EDB9302A 1127 edb9307a MACH_EDB9307A EDB9307A 1128 -ct_dfs MACH_CT_DFS CT_DFS 1129 -pilz_pmi4 MACH_PILZ_PMI4 PILZ_PMI4 1130 -xceednp_ixp MACH_XCEEDNP_IXP XCEEDNP_IXP 1131 -smdk2442b MACH_SMDK2442B SMDK2442B 1132 -xnode MACH_XNODE XNODE 1133 -aidx270 MACH_AIDX270 AIDX270 1134 -rema MACH_REMA REMA 1135 -bps1000 MACH_BPS1000 BPS1000 1136 -hw90350 MACH_HW90350 HW90350 1137 omap_3430sdp MACH_OMAP_3430SDP OMAP_3430SDP 1138 -bluetouch MACH_BLUETOUCH BLUETOUCH 1139 vstms MACH_VSTMS VSTMS 1140 -xsbase270 MACH_XSBASE270 XSBASE270 1141 -at91sam9260ek_cn MACH_AT91SAM9260EK_CN AT91SAM9260EK_CN 1142 -adsturboxb MACH_ADSTURBOXB ADSTURBOXB 1143 -oti4110 MACH_OTI4110 OTI4110 1144 -hme_pxa MACH_HME_PXA HME_PXA 1145 -deisterdca MACH_DEISTERDCA DEISTERDCA 1146 -ces_ssem2 MACH_CES_SSEM2 CES_SSEM2 1147 -ces_mtr MACH_CES_MTR CES_MTR 1148 -tds_avng_sbc MACH_TDS_AVNG_SBC TDS_AVNG_SBC 1149 -everest MACH_EVEREST EVEREST 1150 -pnx4010 MACH_PNX4010 PNX4010 1151 -oxnas MACH_OXNAS OXNAS 1152 -fiori MACH_FIORI FIORI 1153 -ml1200 MACH_ML1200 ML1200 1154 -pecos MACH_PECOS PECOS 1155 -nb2xxx MACH_NB2XXX NB2XXX 1156 -hw6900 MACH_HW6900 HW6900 1157 -cdcs_quoll MACH_CDCS_QUOLL CDCS_QUOLL 1158 -quicksilver MACH_QUICKSILVER QUICKSILVER 1159 -uplat926 MACH_UPLAT926 UPLAT926 1160 -dep2410_dep2410 MACH_DEP2410_THOMAS DEP2410_THOMAS 1161 -dtk2410 MACH_DTK2410 DTK2410 1162 -chili MACH_CHILI CHILI 1163 -demeter MACH_DEMETER DEMETER 1164 -dionysus MACH_DIONYSUS DIONYSUS 1165 -as352x MACH_AS352X AS352X 1166 -service MACH_SERVICE SERVICE 1167 -cs_e9301 MACH_CS_E9301 CS_E9301 1168 micro9m MACH_MICRO9M MICRO9M 1169 -ia_mospck MACH_IA_MOSPCK IA_MOSPCK 1170 -ql201b MACH_QL201B QL201B 1171 -bbm MACH_BBM BBM 1174 -exxx MACH_EXXX EXXX 1175 -wma11b MACH_WMA11B WMA11B 1176 -pelco_atlas MACH_PELCO_ATLAS PELCO_ATLAS 1177 -g500 MACH_G500 G500 1178 bug MACH_BUG BUG 1179 -mx33ads MACH_MX33ADS MX33ADS 1180 -chub MACH_CHUB CHUB 1181 -neo1973_gta01 MACH_NEO1973_GTA01 NEO1973_GTA01 1182 -w90n740 MACH_W90N740 W90N740 1183 -medallion_sa2410 MACH_MEDALLION_SA2410 MEDALLION_SA2410 1184 -ia_cpu_9200_2 MACH_IA_CPU_9200_2 IA_CPU_9200_2 1185 -dimmrm9200 MACH_DIMMRM9200 DIMMRM9200 1186 -pm9261 MACH_PM9261 PM9261 1187 -ml7304 MACH_ML7304 ML7304 1189 -ucp250 MACH_UCP250 UCP250 1190 -intboard MACH_INTBOARD INTBOARD 1191 -gulfstream MACH_GULFSTREAM GULFSTREAM 1192 -labquest MACH_LABQUEST LABQUEST 1193 -vcmx313 MACH_VCMX313 VCMX313 1194 -urg200 MACH_URG200 URG200 1195 -cpux255lcdnet MACH_CPUX255LCDNET CPUX255LCDNET 1196 -netdcu9 MACH_NETDCU9 NETDCU9 1197 -netdcu10 MACH_NETDCU10 NETDCU10 1198 -dspg_dga MACH_DSPG_DGA DSPG_DGA 1199 -dspg_dvw MACH_DSPG_DVW DSPG_DVW 1200 -solos MACH_SOLOS SOLOS 1201 at91sam9263ek MACH_AT91SAM9263EK AT91SAM9263EK 1202 -osstbox MACH_OSSTBOX OSSTBOX 1203 -kbat9261 MACH_KBAT9261 KBAT9261 1204 -ct1100 MACH_CT1100 CT1100 1205 -akcppxa MACH_AKCPPXA AKCPPXA 1206 -ochaya1020 MACH_OCHAYA1020 OCHAYA1020 1207 -hitrack MACH_HITRACK HITRACK 1208 -syme1 MACH_SYME1 SYME1 1209 -syhl1 MACH_SYHL1 SYHL1 1210 -empca400 MACH_EMPCA400 EMPCA400 1211 em7210 MACH_EM7210 EM7210 1212 -htchermes MACH_HTCHERMES HTCHERMES 1213 -eti_c1 MACH_ETI_C1 ETI_C1 1214 -ac100 MACH_AC100 AC100 1216 -sneetch MACH_SNEETCH SNEETCH 1217 -studentmate MACH_STUDENTMATE STUDENTMATE 1218 -zir2410 MACH_ZIR2410 ZIR2410 1219 -zir2413 MACH_ZIR2413 ZIR2413 1220 -dlonip3 MACH_DLONIP3 DLONIP3 1221 -instream MACH_INSTREAM INSTREAM 1222 -ambarella MACH_AMBARELLA AMBARELLA 1223 -nevis MACH_NEVIS NEVIS 1224 -htc_trinity MACH_HTC_TRINITY HTC_TRINITY 1225 -ql202b MACH_QL202B QL202B 1226 vpac270 MACH_VPAC270 VPAC270 1227 -rd129 MACH_RD129 RD129 1228 -htcwizard MACH_HTCWIZARD HTCWIZARD 1229 treo680 MACH_TREO680 TREO680 1230 -tecon_tmezon MACH_TECON_TMEZON TECON_TMEZON 1231 zylonite MACH_ZYLONITE ZYLONITE 1233 -gene1270 MACH_GENE1270 GENE1270 1234 -zir2412 MACH_ZIR2412 ZIR2412 1235 mx31lite MACH_MX31LITE MX31LITE 1236 -t700wx MACH_T700WX T700WX 1237 -vf100 MACH_VF100 VF100 1238 -nsb2 MACH_NSB2 NSB2 1239 -nxhmi_bb MACH_NXHMI_BB NXHMI_BB 1240 -nxhmi_re MACH_NXHMI_RE NXHMI_RE 1241 -n4100pro MACH_N4100PRO N4100PRO 1242 -sam9260 MACH_SAM9260 SAM9260 1243 -omap_treo600 MACH_OMAP_TREO600 OMAP_TREO600 1244 -indy2410 MACH_INDY2410 INDY2410 1245 -nelt_a MACH_NELT_A NELT_A 1246 -n311 MACH_N311 N311 1248 -at91sam9260vgk MACH_AT91SAM9260VGK AT91SAM9260VGK 1249 -at91leppe MACH_AT91LEPPE AT91LEPPE 1250 -at91lepccn MACH_AT91LEPCCN AT91LEPCCN 1251 -apc7100 MACH_APC7100 APC7100 1252 -stargazer MACH_STARGAZER STARGAZER 1253 -sonata MACH_SONATA SONATA 1254 -schmoogie MACH_SCHMOOGIE SCHMOOGIE 1255 -aztool MACH_AZTOOL AZTOOL 1256 mioa701 MACH_MIOA701 MIOA701 1257 -sxni9260 MACH_SXNI9260 SXNI9260 1258 -mxc27520evb MACH_MXC27520EVB MXC27520EVB 1259 armadillo5x0 MACH_ARMADILLO5X0 ARMADILLO5X0 1260 -mb9260 MACH_MB9260 MB9260 1261 -mb9263 MACH_MB9263 MB9263 1262 -ipac9302 MACH_IPAC9302 IPAC9302 1263 cc9p9360js MACH_CC9P9360JS CC9P9360JS 1264 -gallium MACH_GALLIUM GALLIUM 1265 -msc2410 MACH_MSC2410 MSC2410 1266 -ghi270 MACH_GHI270 GHI270 1267 -davinci_leonardo MACH_DAVINCI_LEONARDO DAVINCI_LEONARDO 1268 -oiab MACH_OIAB OIAB 1269 smdk6400 MACH_SMDK6400 SMDK6400 1270 nokia_n800 MACH_NOKIA_N800 NOKIA_N800 1271 -greenphone MACH_GREENPHONE GREENPHONE 1272 -compex42x MACH_COMPEXWP18 COMPEXWP18 1273 -xmate MACH_XMATE XMATE 1274 -energizer MACH_ENERGIZER ENERGIZER 1275 -ime1 MACH_IME1 IME1 1276 -sweda_tms MACH_SWEDATMS SWEDATMS 1277 -ntnp435c MACH_NTNP435C NTNP435C 1278 -spectro2 MACH_SPECTRO2 SPECTRO2 1279 -h6039 MACH_H6039 H6039 1280 ep80219 MACH_EP80219 EP80219 1281 -samoa_ii MACH_SAMOA_II SAMOA_II 1282 -cwmxl MACH_CWMXL CWMXL 1283 -as9200 MACH_AS9200 AS9200 1284 -sfx1149 MACH_SFX1149 SFX1149 1285 -navi010 MACH_NAVI010 NAVI010 1286 -multmdp MACH_MULTMDP MULTMDP 1287 -scb9520 MACH_SCB9520 SCB9520 1288 -htcathena MACH_HTCATHENA HTCATHENA 1289 -xp179 MACH_XP179 XP179 1290 -h4300 MACH_H4300 H4300 1291 goramo_mlr MACH_GORAMO_MLR GORAMO_MLR 1292 -mxc30020evb MACH_MXC30020EVB MXC30020EVB 1293 -adsbitsyg5 MACH_ADSBITSYG5 ADSBITSYG5 1294 -adsportalplus MACH_ADSPORTALPLUS ADSPORTALPLUS 1295 -mmsp2plus MACH_MMSP2PLUS MMSP2PLUS 1296 em_x270 MACH_EM_X270 EM_X270 1297 -tpp302 MACH_TPP302 TPP302 1298 -tpp104 MACH_TPM104 TPM104 1299 -tpm102 MACH_TPM102 TPM102 1300 -tpm109 MACH_TPM109 TPM109 1301 -fbxo1 MACH_FBXO1 FBXO1 1302 -hxd8 MACH_HXD8 HXD8 1303 neo1973_gta02 MACH_NEO1973_GTA02 NEO1973_GTA02 1304 -emtest MACH_EMTEST EMTEST 1305 -ad6900 MACH_AD6900 AD6900 1306 -europa MACH_EUROPA EUROPA 1307 -metroconnect MACH_METROCONNECT METROCONNECT 1308 -ez_s2410 MACH_EZ_S2410 EZ_S2410 1309 -ez_s2440 MACH_EZ_S2440 EZ_S2440 1310 -ez_ep9312 MACH_EZ_EP9312 EZ_EP9312 1311 -ez_ep9315 MACH_EZ_EP9315 EZ_EP9315 1312 -ez_x7 MACH_EZ_X7 EZ_X7 1313 -godotdb MACH_GODOTDB GODOTDB 1314 -mistral MACH_MISTRAL MISTRAL 1315 -msm MACH_MSM MSM 1316 -ct5910 MACH_CT5910 CT5910 1317 -ct5912 MACH_CT5912 CT5912 1318 -hynet_ine MACH_HYNET_INE HYNET_INE 1319 -hynet_app MACH_HYNET_APP HYNET_APP 1320 -msm7200 MACH_MSM7200 MSM7200 1321 -msm7600 MACH_MSM7600 MSM7600 1322 -ceb255 MACH_CEB255 CEB255 1323 -ciel MACH_CIEL CIEL 1324 -slm5650 MACH_SLM5650 SLM5650 1325 at91sam9rlek MACH_AT91SAM9RLEK AT91SAM9RLEK 1326 -comtech_router MACH_COMTECH_ROUTER COMTECH_ROUTER 1327 -sbc2410x MACH_SBC2410X SBC2410X 1328 -at4x0bd MACH_AT4X0BD AT4X0BD 1329 -cbifr MACH_CBIFR CBIFR 1330 -arcom_quantum MACH_ARCOM_QUANTUM ARCOM_QUANTUM 1331 -matrix520 MACH_MATRIX520 MATRIX520 1332 -matrix510 MACH_MATRIX510 MATRIX510 1333 -matrix500 MACH_MATRIX500 MATRIX500 1334 -m501 MACH_M501 M501 1335 -aaeon1270 MACH_AAEON1270 AAEON1270 1336 -matrix500ev MACH_MATRIX500EV MATRIX500EV 1337 -pac500 MACH_PAC500 PAC500 1338 -pnx8181 MACH_PNX8181 PNX8181 1339 colibri320 MACH_COLIBRI320 COLIBRI320 1340 -aztoolbb MACH_AZTOOLBB AZTOOLBB 1341 -aztoolg2 MACH_AZTOOLG2 AZTOOLG2 1342 -dvlhost MACH_DVLHOST DVLHOST 1343 -zir9200 MACH_ZIR9200 ZIR9200 1344 -zir9260 MACH_ZIR9260 ZIR9260 1345 -cocopah MACH_COCOPAH COCOPAH 1346 -nds MACH_NDS NDS 1347 -rosencrantz MACH_ROSENCRANTZ ROSENCRANTZ 1348 -fttx_odsc MACH_FTTX_ODSC FTTX_ODSC 1349 -classe_r6904 MACH_CLASSE_R6904 CLASSE_R6904 1350 cam60 MACH_CAM60 CAM60 1351 -mxc30031ads MACH_MXC30031ADS MXC30031ADS 1352 -datacall MACH_DATACALL DATACALL 1353 at91eb01 MACH_AT91EB01 AT91EB01 1354 -rty MACH_RTY RTY 1355 -dwl2100 MACH_DWL2100 DWL2100 1356 -vinsi MACH_VINSI VINSI 1357 db88f5281 MACH_DB88F5281 DB88F5281 1358 csb726 MACH_CSB726 CSB726 1359 -tik27 MACH_TIK27 TIK27 1360 -mx_uc7420 MACH_MX_UC7420 MX_UC7420 1361 -rirm3 MACH_RIRM3 RIRM3 1362 -pelco_odyssey MACH_PELCO_ODYSSEY PELCO_ODYSSEY 1363 -adx_abox MACH_ADX_ABOX ADX_ABOX 1365 -adx_tpid MACH_ADX_TPID ADX_TPID 1366 -minicheck MACH_MINICHECK MINICHECK 1367 -idam MACH_IDAM IDAM 1368 -mario_mx MACH_MARIO_MX MARIO_MX 1369 -vi1888 MACH_VI1888 VI1888 1370 -zr4230 MACH_ZR4230 ZR4230 1371 -t1_ix_blue MACH_T1_IX_BLUE T1_IX_BLUE 1372 -syhq2 MACH_SYHQ2 SYHQ2 1373 -computime_r3 MACH_COMPUTIME_R3 COMPUTIME_R3 1374 -oratis MACH_ORATIS ORATIS 1375 -mikko MACH_MIKKO MIKKO 1376 -holon MACH_HOLON HOLON 1377 -olip8 MACH_OLIP8 OLIP8 1378 -ghi270hg MACH_GHI270HG GHI270HG 1379 davinci_dm6467_evm MACH_DAVINCI_DM6467_EVM DAVINCI_DM6467_EVM 1380 davinci_dm355_evm MACH_DAVINCI_DM355_EVM DAVINCI_DM355_EVM 1381 -blackriver MACH_BLACKRIVER BLACKRIVER 1383 -sandgate_wp MACH_SANDGATEWP SANDGATEWP 1384 -cdotbwsg MACH_CDOTBWSG CDOTBWSG 1385 -quark963 MACH_QUARK963 QUARK963 1386 -csb735 MACH_CSB735 CSB735 1387 littleton MACH_LITTLETON LITTLETON 1388 -mio_p550 MACH_MIO_P550 MIO_P550 1389 -motion2440 MACH_MOTION2440 MOTION2440 1390 -imm500 MACH_IMM500 IMM500 1391 -homematic MACH_HOMEMATIC HOMEMATIC 1392 -ermine MACH_ERMINE ERMINE 1393 -kb9202b MACH_KB9202B KB9202B 1394 -hs1xx MACH_HS1XX HS1XX 1395 -studentmate2440 MACH_STUDENTMATE2440 STUDENTMATE2440 1396 -arvoo_l1_z1 MACH_ARVOO_L1_Z1 ARVOO_L1_Z1 1397 -dep2410k MACH_DEP2410K DEP2410K 1398 -xxsvideo MACH_XXSVIDEO XXSVIDEO 1399 -im4004 MACH_IM4004 IM4004 1400 -ochaya1050 MACH_OCHAYA1050 OCHAYA1050 1401 -lep9261 MACH_LEP9261 LEP9261 1402 -svenmeb MACH_SVENMEB SVENMEB 1403 -fortunet2ne MACH_FORTUNET2NE FORTUNET2NE 1404 -nxhx MACH_NXHX NXHX 1406 realview_pb11mp MACH_REALVIEW_PB11MP REALVIEW_PB11MP 1407 -ids500 MACH_IDS500 IDS500 1408 -ors_n725 MACH_ORS_N725 ORS_N725 1409 -hsdarm MACH_HSDARM HSDARM 1410 -sha_pon003 MACH_SHA_PON003 SHA_PON003 1411 -sha_pon004 MACH_SHA_PON004 SHA_PON004 1412 -sha_pon007 MACH_SHA_PON007 SHA_PON007 1413 -sha_pon011 MACH_SHA_PON011 SHA_PON011 1414 -h6042 MACH_H6042 H6042 1415 -h6043 MACH_H6043 H6043 1416 -looxc550 MACH_LOOXC550 LOOXC550 1417 -cnty_titan MACH_CNTY_TITAN CNTY_TITAN 1418 -app3xx MACH_APP3XX APP3XX 1419 -sideoatsgrama MACH_SIDEOATSGRAMA SIDEOATSGRAMA 1420 -treo700p MACH_TREO700P TREO700P 1421 -treo700w MACH_TREO700W TREO700W 1422 -treo750 MACH_TREO750 TREO750 1423 -treo755p MACH_TREO755P TREO755P 1424 -ezreganut9200 MACH_EZREGANUT9200 EZREGANUT9200 1425 -sarge MACH_SARGE SARGE 1426 -a696 MACH_A696 A696 1427 -turtle1916 MACH_TURTLE TURTLE 1428 mx27_3ds MACH_MX27_3DS MX27_3DS 1430 -bishop MACH_BISHOP BISHOP 1431 -pxx MACH_PXX PXX 1432 -redwood MACH_REDWOOD REDWOOD 1433 -omap_2430dlp MACH_OMAP_2430DLP OMAP_2430DLP 1436 -omap_2430osk MACH_OMAP_2430OSK OMAP_2430OSK 1437 -sardine MACH_SARDINE SARDINE 1438 halibut MACH_HALIBUT HALIBUT 1439 trout MACH_TROUT TROUT 1440 -goldfish MACH_GOLDFISH GOLDFISH 1441 -gesbc2440 MACH_GESBC2440 GESBC2440 1442 -nomad MACH_NOMAD NOMAD 1443 -rosalind MACH_ROSALIND ROSALIND 1444 -cc9p9215 MACH_CC9P9215 CC9P9215 1445 -cc9p9210 MACH_CC9P9210 CC9P9210 1446 -cc9p9215js MACH_CC9P9215JS CC9P9215JS 1447 -cc9p9210js MACH_CC9P9210JS CC9P9210JS 1448 -nasffe MACH_NASFFE NASFFE 1449 -tn2x0bd MACH_TN2X0BD TN2X0BD 1450 -gwmpxa MACH_GWMPXA GWMPXA 1451 -exyplus MACH_EXYPLUS EXYPLUS 1452 -jadoo21 MACH_JADOO21 JADOO21 1453 -looxn560 MACH_LOOXN560 LOOXN560 1454 -bonsai MACH_BONSAI BONSAI 1455 -adsmilgato MACH_ADSMILGATO ADSMILGATO 1456 -gba MACH_GBA GBA 1457 -h6044 MACH_H6044 H6044 1458 -app MACH_APP APP 1459 tct_hammer MACH_TCT_HAMMER TCT_HAMMER 1460 herald MACH_HERALD HERALD 1461 -artemis MACH_ARTEMIS ARTEMIS 1462 -htctitan MACH_HTCTITAN HTCTITAN 1463 -qranium MACH_QRANIUM QRANIUM 1464 -adx_wsc2 MACH_ADX_WSC2 ADX_WSC2 1465 -adx_medcom MACH_ADX_MEDCOM ADX_MEDCOM 1466 -bboard MACH_BBOARD BBOARD 1467 -cambria MACH_CAMBRIA CAMBRIA 1468 -mt7xxx MACH_MT7XXX MT7XXX 1469 -matrix512 MACH_MATRIX512 MATRIX512 1470 -matrix522 MACH_MATRIX522 MATRIX522 1471 -ipac5010 MACH_IPAC5010 IPAC5010 1472 -sakura MACH_SAKURA SAKURA 1473 -grocx MACH_GROCX GROCX 1474 -pm9263 MACH_PM9263 PM9263 1475 sim_one MACH_SIM_ONE SIM_ONE 1476 -acq132 MACH_ACQ132 ACQ132 1477 -datr MACH_DATR DATR 1478 -actux1 MACH_ACTUX1 ACTUX1 1479 -actux2 MACH_ACTUX2 ACTUX2 1480 -actux3 MACH_ACTUX3 ACTUX3 1481 -flexit MACH_FLEXIT FLEXIT 1482 -bh2x0bd MACH_BH2X0BD BH2X0BD 1483 -atb2002 MACH_ATB2002 ATB2002 1484 -xenon MACH_XENON XENON 1485 -fm607 MACH_FM607 FM607 1486 -matrix514 MACH_MATRIX514 MATRIX514 1487 -matrix524 MACH_MATRIX524 MATRIX524 1488 -inpod MACH_INPOD INPOD 1489 jive MACH_JIVE JIVE 1490 -tll_mx21 MACH_TLL_MX21 TLL_MX21 1491 -sbc2800 MACH_SBC2800 SBC2800 1492 -cc7ucamry MACH_CC7UCAMRY CC7UCAMRY 1493 -ubisys_p9_sc15 MACH_UBISYS_P9_SC15 UBISYS_P9_SC15 1494 -ubisys_p9_ssc2d10 MACH_UBISYS_P9_SSC2D10 UBISYS_P9_SSC2D10 1495 -ubisys_p9_rcu3 MACH_UBISYS_P9_RCU3 UBISYS_P9_RCU3 1496 -aml_m8000 MACH_AML_M8000 AML_M8000 1497 -snapper_270 MACH_SNAPPER_270 SNAPPER_270 1498 -omap_bbx MACH_OMAP_BBX OMAP_BBX 1499 -ucn2410 MACH_UCN2410 UCN2410 1500 sam9_l9260 MACH_SAM9_L9260 SAM9_L9260 1501 -eti_c2 MACH_ETI_C2 ETI_C2 1502 -avalanche MACH_AVALANCHE AVALANCHE 1503 realview_pb1176 MACH_REALVIEW_PB1176 REALVIEW_PB1176 1504 -dp1500 MACH_DP1500 DP1500 1505 -apple_iphone MACH_APPLE_IPHONE APPLE_IPHONE 1506 yl9200 MACH_YL9200 YL9200 1507 rd88f5182 MACH_RD88F5182 RD88F5182 1508 kurobox_pro MACH_KUROBOX_PRO KUROBOX_PRO 1509 -se_poet MACH_SE_POET SE_POET 1510 mx31_3ds MACH_MX31_3DS MX31_3DS 1511 -r270 MACH_R270 R270 1512 -armour21 MACH_ARMOUR21 ARMOUR21 1513 -dt2 MACH_DT2 DT2 1514 -vt4 MACH_VT4 VT4 1515 -tyco320 MACH_TYCO320 TYCO320 1516 -adma MACH_ADMA ADMA 1517 -wp188 MACH_WP188 WP188 1518 -corsica MACH_CORSICA CORSICA 1519 -bigeye MACH_BIGEYE BIGEYE 1520 -tll5000 MACH_TLL5000 TLL5000 1522 -bebot MACH_BEBOT BEBOT 1523 qong MACH_QONG QONG 1524 -tcompact MACH_TCOMPACT TCOMPACT 1525 -puma5 MACH_PUMA5 PUMA5 1526 -elara MACH_ELARA ELARA 1527 -ellington MACH_ELLINGTON ELLINGTON 1528 -xda_atom MACH_XDA_ATOM XDA_ATOM 1529 -energizer2 MACH_ENERGIZER2 ENERGIZER2 1530 -odin MACH_ODIN ODIN 1531 -actux4 MACH_ACTUX4 ACTUX4 1532 -esl_omap MACH_ESL_OMAP ESL_OMAP 1533 omap2evm MACH_OMAP2EVM OMAP2EVM 1534 omap3evm MACH_OMAP3EVM OMAP3EVM 1535 -adx_pcu57 MACH_ADX_PCU57 ADX_PCU57 1536 -monaco MACH_MONACO MONACO 1537 -levante MACH_LEVANTE LEVANTE 1538 -tmxipx425 MACH_TMXIPX425 TMXIPX425 1539 -leep MACH_LEEP LEEP 1540 -raad MACH_RAAD RAAD 1541 dns323 MACH_DNS323 DNS323 1542 -ap1000 MACH_AP1000 AP1000 1543 -a9sam6432 MACH_A9SAM6432 A9SAM6432 1544 -shiny MACH_SHINY SHINY 1545 omap3_beagle MACH_OMAP3_BEAGLE OMAP3_BEAGLE 1546 -csr_bdb2 MACH_CSR_BDB2 CSR_BDB2 1547 nokia_n810 MACH_NOKIA_N810 NOKIA_N810 1548 -c270 MACH_C270 C270 1549 -sentry MACH_SENTRY SENTRY 1550 pcm038 MACH_PCM038 PCM038 1551 -anc300 MACH_ANC300 ANC300 1552 -htckaiser MACH_HTCKAISER HTCKAISER 1553 -sbat100 MACH_SBAT100 SBAT100 1554 -modunorm MACH_MODUNORM MODUNORM 1555 -pelos_twarm MACH_PELOS_TWARM PELOS_TWARM 1556 -flank MACH_FLANK FLANK 1557 -sirloin MACH_SIRLOIN SIRLOIN 1558 -brisket MACH_BRISKET BRISKET 1559 -chuck MACH_CHUCK CHUCK 1560 -otter MACH_OTTER OTTER 1561 -davinci_ldk MACH_DAVINCI_LDK DAVINCI_LDK 1562 -phreedom MACH_PHREEDOM PHREEDOM 1563 -sg310 MACH_SG310 SG310 1564 ts_x09 MACH_TS209 TS209 1565 at91cap9adk MACH_AT91CAP9ADK AT91CAP9ADK 1566 -tion9315 MACH_TION9315 TION9315 1567 -mast MACH_MAST MAST 1568 -pfw MACH_PFW PFW 1569 -yl_p2440 MACH_YL_P2440 YL_P2440 1570 -zsbc32 MACH_ZSBC32 ZSBC32 1571 -omap_pace2 MACH_OMAP_PACE2 OMAP_PACE2 1572 -imx_pace2 MACH_IMX_PACE2 IMX_PACE2 1573 mx31moboard MACH_MX31MOBOARD MX31MOBOARD 1574 -mx37_3ds MACH_MX37_3DS MX37_3DS 1575 -rcc MACH_RCC RCC 1576 -dmp MACH_ARM9 ARM9 1577 -vision_ep9307 MACH_VISION_EP9307 VISION_EP9307 1578 -scly1000 MACH_SCLY1000 SCLY1000 1579 -fontel_ep MACH_FONTEL_EP FONTEL_EP 1580 -voiceblue3g MACH_VOICEBLUE3G VOICEBLUE3G 1581 -tt9200 MACH_TT9200 TT9200 1582 -digi2410 MACH_DIGI2410 DIGI2410 1583 terastation_pro2 MACH_TERASTATION_PRO2 TERASTATION_PRO2 1584 linkstation_pro MACH_LINKSTATION_PRO LINKSTATION_PRO 1585 -motorola_a780 MACH_MOTOROLA_A780 MOTOROLA_A780 1587 -motorola_e6 MACH_MOTOROLA_E6 MOTOROLA_E6 1588 -motorola_e2 MACH_MOTOROLA_E2 MOTOROLA_E2 1589 -motorola_e680 MACH_MOTOROLA_E680 MOTOROLA_E680 1590 -ur2410 MACH_UR2410 UR2410 1591 -tas9261 MACH_TAS9261 TAS9261 1592 -davinci_hermes_hd MACH_HERMES_HD HERMES_HD 1593 -davinci_perseo_hd MACH_PERSEO_HD PERSEO_HD 1594 -stargazer2 MACH_STARGAZER2 STARGAZER2 1595 e350 MACH_E350 E350 1596 -wpcm450 MACH_WPCM450 WPCM450 1597 -cartesio MACH_CARTESIO CARTESIO 1598 -toybox MACH_TOYBOX TOYBOX 1599 -tx27 MACH_TX27 TX27 1600 ts409 MACH_TS409 TS409 1601 -p300 MACH_P300 P300 1602 -xdacomet MACH_XDACOMET XDACOMET 1603 -dexflex2 MACH_DEXFLEX2 DEXFLEX2 1604 -ow MACH_OW OW 1605 -armebs3 MACH_ARMEBS3 ARMEBS3 1606 -u3 MACH_U3 U3 1607 -smdk2450 MACH_SMDK2450 SMDK2450 1608 -rsi_ews MACH_RSI_EWS RSI_EWS 1609 -tnb MACH_TNB TNB 1610 -toepath MACH_TOEPATH TOEPATH 1611 -kb9263 MACH_KB9263 KB9263 1612 -mt7108 MACH_MT7108 MT7108 1613 -smtr2440 MACH_SMTR2440 SMTR2440 1614 -manao MACH_MANAO MANAO 1615 cm_x300 MACH_CM_X300 CM_X300 1616 -gulfstream_kp MACH_GULFSTREAM_KP GULFSTREAM_KP 1617 -lanreadyfn522 MACH_LANREADYFN522 LANREADYFN522 1618 -arma37 MACH_ARMA37 ARMA37 1619 -mendel MACH_MENDEL MENDEL 1620 -pelco_iliad MACH_PELCO_ILIAD PELCO_ILIAD 1621 -unit2p MACH_UNIT2P UNIT2P 1622 -inc20otter MACH_INC20OTTER INC20OTTER 1623 at91sam9g20ek MACH_AT91SAM9G20EK AT91SAM9G20EK 1624 -sc_ge2 MACH_STORCENTER STORCENTER 1625 smdk6410 MACH_SMDK6410 SMDK6410 1626 u300 MACH_U300 U300 1627 -u500 MACH_U500 U500 1628 -ds9260 MACH_DS9260 DS9260 1629 -riverrock MACH_RIVERROCK RIVERROCK 1630 -scibath MACH_SCIBATH SCIBATH 1631 -at91sam7se MACH_AT91SAM7SE512EK AT91SAM7SE512EK 1632 wrt350n_v2 MACH_WRT350N_V2 WRT350N_V2 1633 -multimedia MACH_MULTIMEDIA MULTIMEDIA 1634 -marvin MACH_MARVIN MARVIN 1635 -x500 MACH_X500 X500 1636 -awlug4lcu MACH_AWLUG4LCU AWLUG4LCU 1637 -palermoc MACH_PALERMOC PALERMOC 1638 omap_ldp MACH_OMAP_LDP OMAP_LDP 1639 -ip500 MACH_IP500 IP500 1640 -ase2 MACH_ASE2 ASE2 1642 -mx35evb MACH_MX35EVB MX35EVB 1643 -aml_m8050 MACH_AML_M8050 AML_M8050 1644 mx35_3ds MACH_MX35_3DS MX35_3DS 1645 -mars MACH_MARS MARS 1646 neuros_osd2 MACH_NEUROS_OSD2 NEUROS_OSD2 1647 -badger MACH_BADGER BADGER 1648 trizeps4wl MACH_TRIZEPS4WL TRIZEPS4WL 1649 -trizeps5 MACH_TRIZEPS5 TRIZEPS5 1650 -marlin MACH_MARLIN MARLIN 1651 ts78xx MACH_TS78XX TS78XX 1652 -hpipaq214 MACH_HPIPAQ214 HPIPAQ214 1653 -at572d940dcm MACH_AT572D940DCM AT572D940DCM 1654 -ne1board MACH_NE1BOARD NE1BOARD 1655 -zante MACH_ZANTE ZANTE 1656 sffsdr MACH_SFFSDR SFFSDR 1657 -tw2662 MACH_TW2662 TW2662 1658 -vf10xx MACH_VF10XX VF10XX 1659 -zoran43xx MACH_ZORAN43XX ZORAN43XX 1660 -sonix926 MACH_SONIX926 SONIX926 1661 -celestialsemi MACH_CELESTIALSEMI CELESTIALSEMI 1662 -cc9m2443js MACH_CC9M2443JS CC9M2443JS 1663 -tw5334 MACH_TW5334 TW5334 1664 -omap_htcartemis MACH_HTCARTEMIS HTCARTEMIS 1665 -nal_hlite MACH_NAL_HLITE NAL_HLITE 1666 -htcvogue MACH_HTCVOGUE HTCVOGUE 1667 -smartweb MACH_SMARTWEB SMARTWEB 1668 -mv86xx MACH_MV86XX MV86XX 1669 -mv87xx MACH_MV87XX MV87XX 1670 -songyoungho MACH_SONGYOUNGHO SONGYOUNGHO 1671 -younghotema MACH_YOUNGHOTEMA YOUNGHOTEMA 1672 pcm037 MACH_PCM037 PCM037 1673 -mmvp MACH_MMVP MMVP 1674 -mmap MACH_MMAP MMAP 1675 -ptid2410 MACH_PTID2410 PTID2410 1676 -james_926 MACH_JAMES_926 JAMES_926 1677 -fm6000 MACH_FM6000 FM6000 1678 db88f6281_bp MACH_DB88F6281_BP DB88F6281_BP 1680 rd88f6192_nas MACH_RD88F6192_NAS RD88F6192_NAS 1681 rd88f6281 MACH_RD88F6281 RD88F6281 1682 db78x00_bp MACH_DB78X00_BP DB78X00_BP 1683 smdk2416 MACH_SMDK2416 SMDK2416 1685 -oce_spider_si MACH_OCE_SPIDER_SI OCE_SPIDER_SI 1686 -oce_spider_sk MACH_OCE_SPIDER_SK OCE_SPIDER_SK 1687 -rovern6 MACH_ROVERN6 ROVERN6 1688 -pelco_evolution MACH_PELCO_EVOLUTION PELCO_EVOLUTION 1689 wbd111 MACH_WBD111 WBD111 1690 -elaracpe MACH_ELARACPE ELARACPE 1691 -mabv3 MACH_MABV3 MABV3 1692 mv2120 MACH_MV2120 MV2120 1693 -csb737 MACH_CSB737 CSB737 1695 mx51_3ds MACH_MX51_3DS MX51_3DS 1696 -g900 MACH_G900 G900 1697 -apf27 MACH_APF27 APF27 1698 -ggus2000 MACH_GGUS2000 GGUS2000 1699 -omap_2430_mimic MACH_OMAP_2430_MIMIC OMAP_2430_MIMIC 1700 imx27lite MACH_IMX27LITE IMX27LITE 1701 -almex MACH_ALMEX ALMEX 1702 -control MACH_CONTROL CONTROL 1703 -mba2410 MACH_MBA2410 MBA2410 1704 -volcano MACH_VOLCANO VOLCANO 1705 -zenith MACH_ZENITH ZENITH 1706 -muchip MACH_MUCHIP MUCHIP 1707 -magellan MACH_MAGELLAN MAGELLAN 1708 usb_a9260 MACH_USB_A9260 USB_A9260 1709 usb_a9263 MACH_USB_A9263 USB_A9263 1710 qil_a9260 MACH_QIL_A9260 QIL_A9260 1711 -cme9210 MACH_CME9210 CME9210 1712 -hczh4 MACH_HCZH4 HCZH4 1713 -spearbasic MACH_SPEARBASIC SPEARBASIC 1714 -dep2440 MACH_DEP2440 DEP2440 1715 -hdl_gxr MACH_HDL_GXR HDL_GXR 1716 -hdl_gt MACH_HDL_GT HDL_GT 1717 -hdl_4g MACH_HDL_4G HDL_4G 1718 -s3c6000 MACH_S3C6000 S3C6000 1719 -mmsp2_mdk MACH_MMSP2_MDK MMSP2_MDK 1720 -mpx220 MACH_MPX220 MPX220 1721 kzm_arm11_01 MACH_KZM_ARM11_01 KZM_ARM11_01 1722 -htc_polaris MACH_HTC_POLARIS HTC_POLARIS 1723 -htc_kaiser MACH_HTC_KAISER HTC_KAISER 1724 -lg_ks20 MACH_LG_KS20 LG_KS20 1725 -hhgps MACH_HHGPS HHGPS 1726 nokia_n810_wimax MACH_NOKIA_N810_WIMAX NOKIA_N810_WIMAX 1727 -insight MACH_INSIGHT INSIGHT 1728 sapphire MACH_SAPPHIRE SAPPHIRE 1729 -csb637xo MACH_CSB637XO CSB637XO 1730 -evisiong MACH_EVISIONG EVISIONG 1731 stmp37xx MACH_STMP37XX STMP37XX 1732 stmp378x MACH_STMP378X STMP378X 1733 -tnt MACH_TNT TNT 1734 -tbxt MACH_TBXT TBXT 1735 -playmate MACH_PLAYMATE PLAYMATE 1736 -pns10 MACH_PNS10 PNS10 1737 -eznavi MACH_EZNAVI EZNAVI 1738 -ps4000 MACH_PS4000 PS4000 1739 ezx_a780 MACH_EZX_A780 EZX_A780 1740 ezx_e680 MACH_EZX_E680 EZX_E680 1741 ezx_a1200 MACH_EZX_A1200 EZX_A1200 1742 ezx_e6 MACH_EZX_E6 EZX_E6 1743 ezx_e2 MACH_EZX_E2 EZX_E2 1744 ezx_a910 MACH_EZX_A910 EZX_A910 1745 -cwmx31 MACH_CWMX31 CWMX31 1746 -sl2312 MACH_SL2312 SL2312 1747 -blenny MACH_BLENNY BLENNY 1748 -ds107 MACH_DS107 DS107 1749 -dsx07 MACH_DSX07 DSX07 1750 -picocom1 MACH_PICOCOM1 PICOCOM1 1751 -lynx_wolverine MACH_LYNX_WOLVERINE LYNX_WOLVERINE 1752 -ubisys_p9_sc19 MACH_UBISYS_P9_SC19 UBISYS_P9_SC19 1753 -kratos_low MACH_KRATOS_LOW KRATOS_LOW 1754 -m700 MACH_M700 M700 1755 edmini_v2 MACH_EDMINI_V2 EDMINI_V2 1756 zipit2 MACH_ZIPIT2 ZIPIT2 1757 -hslfemtocell MACH_HSLFEMTOCELL HSLFEMTOCELL 1758 -daintree_at91 MACH_DAINTREE_AT91 DAINTREE_AT91 1759 -sg560usb MACH_SG560USB SG560USB 1760 omap3_pandora MACH_OMAP3_PANDORA OMAP3_PANDORA 1761 -usr8200 MACH_USR8200 USR8200 1762 -s1s65k MACH_S1S65K S1S65K 1763 -s2s65a MACH_S2S65A S2S65A 1764 -icore MACH_ICORE ICORE 1765 mss2 MACH_MSS2 MSS2 1766 -belmont MACH_BELMONT BELMONT 1767 -asusp525 MACH_ASUSP525 ASUSP525 1768 lb88rc8480 MACH_LB88RC8480 LB88RC8480 1769 -hipxa MACH_HIPXA HIPXA 1770 mx25_3ds MACH_MX25_3DS MX25_3DS 1771 -m800 MACH_M800 M800 1772 omap3530_lv_som MACH_OMAP3530_LV_SOM OMAP3530_LV_SOM 1773 -prima_evb MACH_PRIMA_EVB PRIMA_EVB 1774 -mx31bt1 MACH_MX31BT1 MX31BT1 1775 -atlas4_evb MACH_ATLAS4_EVB ATLAS4_EVB 1776 -mx31cicada MACH_MX31CICADA MX31CICADA 1777 -mi424wr MACH_MI424WR MI424WR 1778 -axs_ultrax MACH_AXS_ULTRAX AXS_ULTRAX 1779 -at572d940deb MACH_AT572D940DEB AT572D940DEB 1780 davinci_da830_evm MACH_DAVINCI_DA830_EVM DAVINCI_DA830_EVM 1781 -ep9302 MACH_EP9302 EP9302 1782 at572d940hfek MACH_AT572D940HFEB AT572D940HFEB 1783 -cybook3 MACH_CYBOOK3 CYBOOK3 1784 -wdg002 MACH_WDG002 WDG002 1785 -sg560adsl MACH_SG560ADSL SG560ADSL 1786 -nextio_n2800_ica MACH_NEXTIO_N2800_ICA NEXTIO_N2800_ICA 1787 dove_db MACH_DOVE_DB DOVE_DB 1788 -marvell_newdb MACH_MARVELL_NEWDB MARVELL_NEWDB 1789 -vandihud MACH_VANDIHUD VANDIHUD 1790 -magx_e8 MACH_MAGX_E8 MAGX_E8 1791 -magx_z6 MACH_MAGX_Z6 MAGX_Z6 1792 -magx_v8 MACH_MAGX_V8 MAGX_V8 1793 -magx_u9 MACH_MAGX_U9 MAGX_U9 1794 -toughcf08 MACH_TOUGHCF08 TOUGHCF08 1795 -zw4400 MACH_ZW4400 ZW4400 1796 -marat91 MACH_MARAT91 MARAT91 1797 overo MACH_OVERO OVERO 1798 at2440evb MACH_AT2440EVB AT2440EVB 1799 neocore926 MACH_NEOCORE926 NEOCORE926 1800 wnr854t MACH_WNR854T WNR854T 1801 -imx27 MACH_IMX27 IMX27 1802 -moose_db MACH_MOOSE_DB MOOSE_DB 1803 -fab4 MACH_FAB4 FAB4 1804 -htcdiamond MACH_HTCDIAMOND HTCDIAMOND 1805 -fiona MACH_FIONA FIONA 1806 -mxc30030_x MACH_MXC30030_X MXC30030_X 1807 -bmp1000 MACH_BMP1000 BMP1000 1808 -logi9200 MACH_LOGI9200 LOGI9200 1809 -tqma31 MACH_TQMA31 TQMA31 1810 -ccw9p9215js MACH_CCW9P9215JS CCW9P9215JS 1811 rd88f5181l_ge MACH_RD88F5181L_GE RD88F5181L_GE 1812 -sifmain MACH_SIFMAIN SIFMAIN 1813 -sam9_l9261 MACH_SAM9_L9261 SAM9_L9261 1814 -cc9m2443 MACH_CC9M2443 CC9M2443 1815 -xaria300 MACH_XARIA300 XARIA300 1816 -it9200 MACH_IT9200 IT9200 1817 rd88f5181l_fxo MACH_RD88F5181L_FXO RD88F5181L_FXO 1818 -kriss_sensor MACH_KRISS_SENSOR KRISS_SENSOR 1819 -pilz_pmi5 MACH_PILZ_PMI5 PILZ_PMI5 1820 -jade MACH_JADE JADE 1821 -ks8695_softplc MACH_KS8695_SOFTPLC KS8695_SOFTPLC 1822 -gprisc3 MACH_GPRISC3 GPRISC3 1823 stamp9g20 MACH_STAMP9G20 STAMP9G20 1824 -smdk6430 MACH_SMDK6430 SMDK6430 1825 smdkc100 MACH_SMDKC100 SMDKC100 1826 tavorevb MACH_TAVOREVB TAVOREVB 1827 saar MACH_SAAR SAAR 1828 -deister_eyecam MACH_DEISTER_EYECAM DEISTER_EYECAM 1829 at91sam9m10g45ek MACH_AT91SAM9M10G45EK AT91SAM9M10G45EK 1830 -linkstation_produo MACH_LINKSTATION_PRODUO LINKSTATION_PRODUO 1831 -hit_b0 MACH_HIT_B0 HIT_B0 1832 -adx_rmu MACH_ADX_RMU ADX_RMU 1833 -xg_cpe_main MACH_XG_CPE_MAIN XG_CPE_MAIN 1834 -edb9407a MACH_EDB9407A EDB9407A 1835 -dtb9608 MACH_DTB9608 DTB9608 1836 -em104v1 MACH_EM104V1 EM104V1 1837 -demo MACH_DEMO DEMO 1838 -logi9260 MACH_LOGI9260 LOGI9260 1839 -mx31_exm32 MACH_MX31_EXM32 MX31_EXM32 1840 -usb_a9g20 MACH_USB_A9G20 USB_A9G20 1841 -picproje2008 MACH_PICPROJE2008 PICPROJE2008 1842 -cs_e9315 MACH_CS_E9315 CS_E9315 1843 -qil_a9g20 MACH_QIL_A9G20 QIL_A9G20 1844 -sha_pon020 MACH_SHA_PON020 SHA_PON020 1845 -nad MACH_NAD NAD 1846 -sbc35_a9260 MACH_SBC35_A9260 SBC35_A9260 1847 -sbc35_a9g20 MACH_SBC35_A9G20 SBC35_A9G20 1848 -davinci_beginning MACH_DAVINCI_BEGINNING DAVINCI_BEGINNING 1849 -uwc MACH_UWC UWC 1850 mxlads MACH_MXLADS MXLADS 1851 -htcnike MACH_HTCNIKE HTCNIKE 1852 -deister_pxa270 MACH_DEISTER_PXA270 DEISTER_PXA270 1853 -cme9210js MACH_CME9210JS CME9210JS 1854 -cc9p9360 MACH_CC9P9360 CC9P9360 1855 -mocha MACH_MOCHA MOCHA 1856 -wapd170ag MACH_WAPD170AG WAPD170AG 1857 linkstation_mini MACH_LINKSTATION_MINI LINKSTATION_MINI 1858 afeb9260 MACH_AFEB9260 AFEB9260 1859 -w90x900 MACH_W90X900 W90X900 1860 -w90x700 MACH_W90X700 W90X700 1861 -kt300ip MACH_KT300IP KT300IP 1862 -kt300ip_g20 MACH_KT300IP_G20 KT300IP_G20 1863 -srcm MACH_SRCM SRCM 1864 -wlnx_9260 MACH_WLNX_9260 WLNX_9260 1865 -openmoko_gta03 MACH_OPENMOKO_GTA03 OPENMOKO_GTA03 1866 -osprey2 MACH_OSPREY2 OSPREY2 1867 -kbio9260 MACH_KBIO9260 KBIO9260 1868 -ginza MACH_GINZA GINZA 1869 -a636n MACH_A636N A636N 1870 imx27ipcam MACH_IMX27IPCAM IMX27IPCAM 1871 -nemoc MACH_NEMOC NEMOC 1872 -geneva MACH_GENEVA GENEVA 1873 -htcpharos MACH_HTCPHAROS HTCPHAROS 1874 -neonc MACH_NEONC NEONC 1875 -nas7100 MACH_NAS7100 NAS7100 1876 -teuphone MACH_TEUPHONE TEUPHONE 1877 -annax_eth2 MACH_ANNAX_ETH2 ANNAX_ETH2 1878 -csb733 MACH_CSB733 CSB733 1879 -bk3 MACH_BK3 BK3 1880 -omap_em32 MACH_OMAP_EM32 OMAP_EM32 1881 -et9261cp MACH_ET9261CP ET9261CP 1882 -jasperc MACH_JASPERC JASPERC 1883 -issi_arm9 MACH_ISSI_ARM9 ISSI_ARM9 1884 -ued MACH_UED UED 1885 -esiblade MACH_ESIBLADE ESIBLADE 1886 -eye02 MACH_EYE02 EYE02 1887 -imx27kbd MACH_IMX27KBD IMX27KBD 1888 -sst61vc010_fpga MACH_SST61VC010_FPGA SST61VC010_FPGA 1889 -kixvp435 MACH_KIXVP435 KIXVP435 1890 -kixnp435 MACH_KIXNP435 KIXNP435 1891 -africa MACH_AFRICA AFRICA 1892 -nh233 MACH_NH233 NH233 1893 rd88f6183ap_ge MACH_RD88F6183AP_GE RD88F6183AP_GE 1894 -bcm4760 MACH_BCM4760 BCM4760 1895 -eddy_v2 MACH_EDDY_V2 EDDY_V2 1896 realview_pba8 MACH_REALVIEW_PBA8 REALVIEW_PBA8 1897 -hid_a7 MACH_HID_A7 HID_A7 1898 -hero MACH_HERO HERO 1899 -omap_poseidon MACH_OMAP_POSEIDON OMAP_POSEIDON 1900 realview_pbx MACH_REALVIEW_PBX REALVIEW_PBX 1901 micro9s MACH_MICRO9S MICRO9S 1902 -mako MACH_MAKO MAKO 1903 -xdaflame MACH_XDAFLAME XDAFLAME 1904 -phidget_sbc2 MACH_PHIDGET_SBC2 PHIDGET_SBC2 1905 -limestone MACH_LIMESTONE LIMESTONE 1906 -iprobe_c32 MACH_IPROBE_C32 IPROBE_C32 1907 rut100 MACH_RUT100 RUT100 1908 -asusp535 MACH_ASUSP535 ASUSP535 1909 -htcraphael MACH_HTCRAPHAEL HTCRAPHAEL 1910 -sygdg1 MACH_SYGDG1 SYGDG1 1911 -sygdg2 MACH_SYGDG2 SYGDG2 1912 -seoul MACH_SEOUL SEOUL 1913 -salerno MACH_SALERNO SALERNO 1914 -ucn_s3c64xx MACH_UCN_S3C64XX UCN_S3C64XX 1915 -msm7201a MACH_MSM7201A MSM7201A 1916 -lpr1 MACH_LPR1 LPR1 1917 -armadillo500fx MACH_ARMADILLO500FX ARMADILLO500FX 1918 g3evm MACH_G3EVM G3EVM 1919 -z3_dm355 MACH_Z3_DM355 Z3_DM355 1920 w90p910evb MACH_W90P910EVB W90P910EVB 1921 -w90p920evb MACH_W90P920EVB W90P920EVB 1922 w90p950evb MACH_W90P950EVB W90P950EVB 1923 w90n960evb MACH_W90N960EVB W90N960EVB 1924 -camhd MACH_CAMHD CAMHD 1925 -mvc100 MACH_MVC100 MVC100 1926 -electrum_200 MACH_ELECTRUM_200 ELECTRUM_200 1927 -htcjade MACH_HTCJADE HTCJADE 1928 -memphis MACH_MEMPHIS MEMPHIS 1929 -imx27sbc MACH_IMX27SBC IMX27SBC 1930 -lextar MACH_LEXTAR LEXTAR 1931 mv88f6281gtw_ge MACH_MV88F6281GTW_GE MV88F6281GTW_GE 1932 ncp MACH_NCP NCP 1933 -z32an_series MACH_Z32AN Z32AN 1934 -tmq_capd MACH_TMQ_CAPD TMQ_CAPD 1935 -omap3_wl MACH_OMAP3_WL OMAP3_WL 1936 -chumby MACH_CHUMBY CHUMBY 1937 -atsarm9 MACH_ATSARM9 ATSARM9 1938 davinci_dm365_evm MACH_DAVINCI_DM365_EVM DAVINCI_DM365_EVM 1939 -bahamas MACH_BAHAMAS BAHAMAS 1940 -das MACH_DAS DAS 1941 -minidas MACH_MINIDAS MINIDAS 1942 -vk1000 MACH_VK1000 VK1000 1943 centro MACH_CENTRO CENTRO 1944 -ctera_2bay MACH_CTERA_2BAY CTERA_2BAY 1945 -edgeconnect MACH_EDGECONNECT EDGECONNECT 1946 -nd27000 MACH_ND27000 ND27000 1947 -cobra MACH_GEMALTO_COBRA GEMALTO_COBRA 1948 -ingelabs_comet MACH_INGELABS_COMET INGELABS_COMET 1949 -pollux_wiz MACH_POLLUX_WIZ POLLUX_WIZ 1950 -blackstone MACH_BLACKSTONE BLACKSTONE 1951 -topaz MACH_TOPAZ TOPAZ 1952 -aixle MACH_AIXLE AIXLE 1953 -mw998 MACH_MW998 MW998 1954 nokia_rx51 MACH_NOKIA_RX51 NOKIA_RX51 1955 -vsc5605ev MACH_VSC5605EV VSC5605EV 1956 -nt98700dk MACH_NT98700DK NT98700DK 1957 -icontact MACH_ICONTACT ICONTACT 1958 -swarco_frcpu MACH_SWARCO_FRCPU SWARCO_FRCPU 1959 -swarco_scpu MACH_SWARCO_SCPU SWARCO_SCPU 1960 -bbox_p16 MACH_BBOX_P16 BBOX_P16 1961 -bstd MACH_BSTD BSTD 1962 -sbc2440ii MACH_SBC2440II SBC2440II 1963 -pcm034 MACH_PCM034 PCM034 1964 -neso MACH_NESO NESO 1965 -wlnx_9g20 MACH_WLNX_9G20 WLNX_9G20 1966 omap_zoom2 MACH_OMAP_ZOOM2 OMAP_ZOOM2 1967 -totemnova MACH_TOTEMNOVA TOTEMNOVA 1968 -c5000 MACH_C5000 C5000 1969 -unipo_at91sam9263 MACH_UNIPO_AT91SAM9263 UNIPO_AT91SAM9263 1970 -ethernut5 MACH_ETHERNUT5 ETHERNUT5 1971 -arm11 MACH_ARM11 ARM11 1972 cpuat9260 MACH_CPUAT9260 CPUAT9260 1973 -cpupxa255 MACH_CPUPXA255 CPUPXA255 1974 eukrea_cpuimx27 MACH_CPUIMX27 CPUIMX27 1975 -cheflux MACH_CHEFLUX CHEFLUX 1976 -eb_cpux9k2 MACH_EB_CPUX9K2 EB_CPUX9K2 1977 -opcotec MACH_OPCOTEC OPCOTEC 1978 -yt MACH_YT YT 1979 -motoq MACH_MOTOQ MOTOQ 1980 -bsb1 MACH_BSB1 BSB1 1981 acs5k MACH_ACS5K ACS5K 1982 -milan MACH_MILAN MILAN 1983 -quartzv2 MACH_QUARTZV2 QUARTZV2 1984 -rsvp MACH_RSVP RSVP 1985 -rmp200 MACH_RMP200 RMP200 1986 snapper_9260 MACH_SNAPPER_9260 SNAPPER_9260 1987 dsm320 MACH_DSM320 DSM320 1988 -adsgcm MACH_ADSGCM ADSGCM 1989 -ase2_400 MACH_ASE2_400 ASE2_400 1990 -pizza MACH_PIZZA PIZZA 1991 -spot_ngpl MACH_SPOT_NGPL SPOT_NGPL 1992 -armata MACH_ARMATA ARMATA 1993 exeda MACH_EXEDA EXEDA 1994 -mx31sf005 MACH_MX31SF005 MX31SF005 1995 -f5d8231_4_v2 MACH_F5D8231_4_V2 F5D8231_4_V2 1996 -q2440 MACH_Q2440 Q2440 1997 -qq2440 MACH_QQ2440 QQ2440 1998 mini2440 MACH_MINI2440 MINI2440 1999 colibri300 MACH_COLIBRI300 COLIBRI300 2000 -jades MACH_JADES JADES 2001 -spark MACH_SPARK SPARK 2002 -benzina MACH_BENZINA BENZINA 2003 -blaze MACH_BLAZE BLAZE 2004 linkstation_ls_hgl MACH_LINKSTATION_LS_HGL LINKSTATION_LS_HGL 2005 -htckovsky MACH_HTCKOVSKY HTCKOVSKY 2006 -sony_prs505 MACH_SONY_PRS505 SONY_PRS505 2007 -hanlin_v3 MACH_HANLIN_V3 HANLIN_V3 2008 -sapphira MACH_SAPPHIRA SAPPHIRA 2009 -dack_sda_01 MACH_DACK_SDA_01 DACK_SDA_01 2010 -armbox MACH_ARMBOX ARMBOX 2011 -harris_rvp MACH_HARRIS_RVP HARRIS_RVP 2012 -ribaldo MACH_RIBALDO RIBALDO 2013 -agora MACH_AGORA AGORA 2014 -omap3_mini MACH_OMAP3_MINI OMAP3_MINI 2015 -a9sam6432_b MACH_A9SAM6432_B A9SAM6432_B 2016 -usg2410 MACH_USG2410 USG2410 2017 -pc72052_i10_revb MACH_PC72052_I10_REVB PC72052_I10_REVB 2018 -mx35_exm32 MACH_MX35_EXM32 MX35_EXM32 2019 -topas910 MACH_TOPAS910 TOPAS910 2020 -hyena MACH_HYENA HYENA 2021 -pospax MACH_POSPAX POSPAX 2022 -hdl_gx MACH_HDL_GX HDL_GX 2023 -ctera_4bay MACH_CTERA_4BAY CTERA_4BAY 2024 -ctera_plug_c MACH_CTERA_PLUG_C CTERA_PLUG_C 2025 -crwea_plug_i MACH_CRWEA_PLUG_I CRWEA_PLUG_I 2026 -egauge2 MACH_EGAUGE2 EGAUGE2 2027 -didj MACH_DIDJ DIDJ 2028 -m_s3c2443 MACH_MEISTER MEISTER 2029 -htcblackstone MACH_HTCBLACKSTONE HTCBLACKSTONE 2030 cpuat9g20 MACH_CPUAT9G20 CPUAT9G20 2031 smdk6440 MACH_SMDK6440 SMDK6440 2032 -omap_35xx_mvp MACH_OMAP_35XX_MVP OMAP_35XX_MVP 2033 -ctera_plug_i MACH_CTERA_PLUG_I CTERA_PLUG_I 2034 -pvg610_100 MACH_PVG610 PVG610 2035 -hprw6815 MACH_HPRW6815 HPRW6815 2036 -omap3_oswald MACH_OMAP3_OSWALD OMAP3_OSWALD 2037 nas4220b MACH_NAS4220B NAS4220B 2038 -htcraphael_cdma MACH_HTCRAPHAEL_CDMA HTCRAPHAEL_CDMA 2039 -htcdiamond_cdma MACH_HTCDIAMOND_CDMA HTCDIAMOND_CDMA 2040 -scaler MACH_SCALER SCALER 2041 zylonite2 MACH_ZYLONITE2 ZYLONITE2 2042 aspenite MACH_ASPENITE ASPENITE 2043 -teton MACH_TETON TETON 2044 ttc_dkb MACH_TTC_DKB TTC_DKB 2045 -bishop2 MACH_BISHOP2 BISHOP2 2046 -ippv5 MACH_IPPV5 IPPV5 2047 -farm926 MACH_FARM926 FARM926 2048 -mmccpu MACH_MMCCPU MMCCPU 2049 -sgmsfl MACH_SGMSFL SGMSFL 2050 -tt8000 MACH_TT8000 TT8000 2051 -zrn4300lp MACH_ZRN4300LP ZRN4300LP 2052 -mptc MACH_MPTC MPTC 2053 -h6051 MACH_H6051 H6051 2054 -pvg610_101 MACH_PVG610_101 PVG610_101 2055 -stamp9261_pc_evb MACH_STAMP9261_PC_EVB STAMP9261_PC_EVB 2056 -pelco_odysseus MACH_PELCO_ODYSSEUS PELCO_ODYSSEUS 2057 -tny_a9260 MACH_TNY_A9260 TNY_A9260 2058 -tny_a9g20 MACH_TNY_A9G20 TNY_A9G20 2059 -aesop_mp2530f MACH_AESOP_MP2530F AESOP_MP2530F 2060 -dx900 MACH_DX900 DX900 2061 -cpodc2 MACH_CPODC2 CPODC2 2062 -tilt_8925 MACH_TILT_8925 TILT_8925 2063 -davinci_dm357_evm MACH_DAVINCI_DM357_EVM DAVINCI_DM357_EVM 2064 -swordfish MACH_SWORDFISH SWORDFISH 2065 -corvus MACH_CORVUS CORVUS 2066 -taurus MACH_TAURUS TAURUS 2067 -axm MACH_AXM AXM 2068 -axc MACH_AXC AXC 2069 -baby MACH_BABY BABY 2070 -mp200 MACH_MP200 MP200 2071 pcm043 MACH_PCM043 PCM043 2072 -hanlin_v3c MACH_HANLIN_V3C HANLIN_V3C 2073 -kbk9g20 MACH_KBK9G20 KBK9G20 2074 -adsturbog5 MACH_ADSTURBOG5 ADSTURBOG5 2075 -avenger_lite1 MACH_AVENGER_LITE1 AVENGER_LITE1 2076 -suc82x MACH_SUC SUC 2077 -at91sam7s256 MACH_AT91SAM7S256 AT91SAM7S256 2078 -mendoza MACH_MENDOZA MENDOZA 2079 -kira MACH_KIRA KIRA 2080 -mx1hbm MACH_MX1HBM MX1HBM 2081 -quatro43xx MACH_QUATRO43XX QUATRO43XX 2082 -quatro4230 MACH_QUATRO4230 QUATRO4230 2083 -nsb400 MACH_NSB400 NSB400 2084 -drp255 MACH_DRP255 DRP255 2085 -thoth MACH_THOTH THOTH 2086 -firestone MACH_FIRESTONE FIRESTONE 2087 -asusp750 MACH_ASUSP750 ASUSP750 2088 -ctera_dl MACH_CTERA_DL CTERA_DL 2089 -socr MACH_SOCR SOCR 2090 -htcoxygen MACH_HTCOXYGEN HTCOXYGEN 2091 -heroc MACH_HEROC HEROC 2092 -zeno6800 MACH_ZENO6800 ZENO6800 2093 -sc2mcs MACH_SC2MCS SC2MCS 2094 -gene100 MACH_GENE100 GENE100 2095 -as353x MACH_AS353X AS353X 2096 sheevaplug MACH_SHEEVAPLUG SHEEVAPLUG 2097 -at91sam9g20 MACH_AT91SAM9G20 AT91SAM9G20 2098 -mv88f6192gtw_fe MACH_MV88F6192GTW_FE MV88F6192GTW_FE 2099 -cc9200 MACH_CC9200 CC9200 2100 -sm9200 MACH_SM9200 SM9200 2101 -tp9200 MACH_TP9200 TP9200 2102 -snapperdv MACH_SNAPPERDV SNAPPERDV 2103 avengers_lite MACH_AVENGERS_LITE AVENGERS_LITE 2104 -avengers_lite1 MACH_AVENGERS_LITE1 AVENGERS_LITE1 2105 -omap3axon MACH_OMAP3AXON OMAP3AXON 2106 -ma8xx MACH_MA8XX MA8XX 2107 -mp201ek MACH_MP201EK MP201EK 2108 -davinci_tux MACH_DAVINCI_TUX DAVINCI_TUX 2109 -mpa1600 MACH_MPA1600 MPA1600 2110 -pelco_troy MACH_PELCO_TROY PELCO_TROY 2111 -nsb667 MACH_NSB667 NSB667 2112 -rovers5_4mpix MACH_ROVERS5_4MPIX ROVERS5_4MPIX 2113 -twocom MACH_TWOCOM TWOCOM 2114 -ubisys_p9_rcu3r2 MACH_UBISYS_P9_RCU3R2 UBISYS_P9_RCU3R2 2115 -hero_espresso MACH_HERO_ESPRESSO HERO_ESPRESSO 2116 -afeusb MACH_AFEUSB AFEUSB 2117 -t830 MACH_T830 T830 2118 -spd8020_cc MACH_SPD8020_CC SPD8020_CC 2119 -om_3d7k MACH_OM_3D7K OM_3D7K 2120 -picocom2 MACH_PICOCOM2 PICOCOM2 2121 -uwg4mx27 MACH_UWG4MX27 UWG4MX27 2122 -uwg4mx31 MACH_UWG4MX31 UWG4MX31 2123 -cherry MACH_CHERRY CHERRY 2124 mx51_babbage MACH_MX51_BABBAGE MX51_BABBAGE 2125 -s3c2440turkiye MACH_S3C2440TURKIYE S3C2440TURKIYE 2126 -tx37 MACH_TX37 TX37 2127 -sbc2800_9g20 MACH_SBC2800_9G20 SBC2800_9G20 2128 -benzglb MACH_BENZGLB BENZGLB 2129 -benztd MACH_BENZTD BENZTD 2130 -cartesio_plus MACH_CARTESIO_PLUS CARTESIO_PLUS 2131 -solrad_g20 MACH_SOLRAD_G20 SOLRAD_G20 2132 -mx27wallace MACH_MX27WALLACE MX27WALLACE 2133 -fmzwebmodul MACH_FMZWEBMODUL FMZWEBMODUL 2134 rd78x00_masa MACH_RD78X00_MASA RD78X00_MASA 2135 -smallogger MACH_SMALLOGGER SMALLOGGER 2136 -ccw9p9215 MACH_CCW9P9215 CCW9P9215 2137 dm355_leopard MACH_DM355_LEOPARD DM355_LEOPARD 2138 ts219 MACH_TS219 TS219 2139 -tny_a9263 MACH_TNY_A9263 TNY_A9263 2140 -apollo MACH_APOLLO APOLLO 2141 -at91cap9stk MACH_AT91CAP9STK AT91CAP9STK 2142 -spc300 MACH_SPC300 SPC300 2143 -eko MACH_EKO EKO 2144 -ccw9m2443 MACH_CCW9M2443 CCW9M2443 2145 -ccw9m2443js MACH_CCW9M2443JS CCW9M2443JS 2146 -m2m_router_device MACH_M2M_ROUTER_DEVICE M2M_ROUTER_DEVICE 2147 -str9104nas MACH_STAR9104NAS STAR9104NAS 2148 pca100 MACH_PCA100 PCA100 2149 -z3_dm365_mod_01 MACH_Z3_DM365_MOD_01 Z3_DM365_MOD_01 2150 -hipox MACH_HIPOX HIPOX 2151 -omap3_piteds MACH_OMAP3_PITEDS OMAP3_PITEDS 2152 -bm150r MACH_BM150R BM150R 2153 -tbone MACH_TBONE TBONE 2154 -merlin MACH_MERLIN MERLIN 2155 -falcon MACH_FALCON FALCON 2156 davinci_da850_evm MACH_DAVINCI_DA850_EVM DAVINCI_DA850_EVM 2157 -s5p6440 MACH_S5P6440 S5P6440 2158 at91sam9g10ek MACH_AT91SAM9G10EK AT91SAM9G10EK 2159 omap_4430sdp MACH_OMAP_4430SDP OMAP_4430SDP 2160 -lpc313x MACH_LPC313X LPC313X 2161 magx_zn5 MACH_MAGX_ZN5 MAGX_ZN5 2162 -magx_em30 MACH_MAGX_EM30 MAGX_EM30 2163 -magx_ve66 MACH_MAGX_VE66 MAGX_VE66 2164 -meesc MACH_MEESC MEESC 2165 -otc570 MACH_OTC570 OTC570 2166 -bcu2412 MACH_BCU2412 BCU2412 2167 -beacon MACH_BEACON BEACON 2168 -actia_tgw MACH_ACTIA_TGW ACTIA_TGW 2169 -e4430 MACH_E4430 E4430 2170 -ql300 MACH_QL300 QL300 2171 -btmavb101 MACH_BTMAVB101 BTMAVB101 2172 -btmawb101 MACH_BTMAWB101 BTMAWB101 2173 -sq201 MACH_SQ201 SQ201 2174 -quatro45xx MACH_QUATRO45XX QUATRO45XX 2175 -openpad MACH_OPENPAD OPENPAD 2176 -tx25 MACH_TX25 TX25 2177 omap3_torpedo MACH_OMAP3_TORPEDO OMAP3_TORPEDO 2178 -htcraphael_k MACH_HTCRAPHAEL_K HTCRAPHAEL_K 2179 -lal43 MACH_LAL43 LAL43 2181 -htcraphael_cdma500 MACH_HTCRAPHAEL_CDMA500 HTCRAPHAEL_CDMA500 2182 anw6410 MACH_ANW6410 ANW6410 2183 -htcprophet MACH_HTCPROPHET HTCPROPHET 2185 -cfa_10022 MACH_CFA_10022 CFA_10022 2186 imx27_visstrim_m10 MACH_IMX27_VISSTRIM_M10 IMX27_VISSTRIM_M10 2187 -px2imx27 MACH_PX2IMX27 PX2IMX27 2188 -stm3210e_eval MACH_STM3210E_EVAL STM3210E_EVAL 2189 -dvs10 MACH_DVS10 DVS10 2190 portuxg20 MACH_PORTUXG20 PORTUXG20 2191 -arm_spv MACH_ARM_SPV ARM_SPV 2192 smdkc110 MACH_SMDKC110 SMDKC110 2193 -cabespresso MACH_CABESPRESSO CABESPRESSO 2194 -hmc800 MACH_HMC800 HMC800 2195 -sholes MACH_SHOLES SHOLES 2196 -btmxc31 MACH_BTMXC31 BTMXC31 2197 -dt501 MACH_DT501 DT501 2198 -ktx MACH_KTX KTX 2199 omap3517evm MACH_OMAP3517EVM OMAP3517EVM 2200 netspace_v2 MACH_NETSPACE_V2 NETSPACE_V2 2201 netspace_max_v2 MACH_NETSPACE_MAX_V2 NETSPACE_MAX_V2 2202 d2net_v2 MACH_D2NET_V2 D2NET_V2 2203 net2big_v2 MACH_NET2BIG_V2 NET2BIG_V2 2204 -net4big_v2 MACH_NET4BIG_V2 NET4BIG_V2 2205 net5big_v2 MACH_NET5BIG_V2 NET5BIG_V2 2206 -endb2443 MACH_ENDB2443 ENDB2443 2207 inetspace_v2 MACH_INETSPACE_V2 INETSPACE_V2 2208 -tros MACH_TROS TROS 2209 -pelco_homer MACH_PELCO_HOMER PELCO_HOMER 2210 -ofsp8 MACH_OFSP8 OFSP8 2211 at91sam9g45ekes MACH_AT91SAM9G45EKES AT91SAM9G45EKES 2212 -guf_cupid MACH_GUF_CUPID GUF_CUPID 2213 -eab1r MACH_EAB1R EAB1R 2214 -desirec MACH_DESIREC DESIREC 2215 -cordoba MACH_CORDOBA CORDOBA 2216 -irvine MACH_IRVINE IRVINE 2217 -sff772 MACH_SFF772 SFF772 2218 -pelco_milano MACH_PELCO_MILANO PELCO_MILANO 2219 pc7302 MACH_PC7302 PC7302 2220 -bip6000 MACH_BIP6000 BIP6000 2221 -silvermoon MACH_SILVERMOON SILVERMOON 2222 -vc0830 MACH_VC0830 VC0830 2223 -dt430 MACH_DT430 DT430 2224 -ji42pf MACH_JI42PF JI42PF 2225 -gnet_ksm MACH_GNET_KSM GNET_KSM 2226 -gnet_sgm MACH_GNET_SGM GNET_SGM 2227 -gnet_sgr MACH_GNET_SGR GNET_SGR 2228 -omap3_icetekevm MACH_OMAP3_ICETEKEVM OMAP3_ICETEKEVM 2229 -pnp MACH_PNP PNP 2230 -ctera_2bay_k MACH_CTERA_2BAY_K CTERA_2BAY_K 2231 -ctera_2bay_u MACH_CTERA_2BAY_U CTERA_2BAY_U 2232 -sas_c MACH_SAS_C SAS_C 2233 -vma2315 MACH_VMA2315 VMA2315 2234 -vcs MACH_VCS VCS 2235 spear600 MACH_SPEAR600 SPEAR600 2236 spear300 MACH_SPEAR300 SPEAR300 2237 -spear1300 MACH_SPEAR1300 SPEAR1300 2238 lilly1131 MACH_LILLY1131 LILLY1131 2239 -arvoo_ax301 MACH_ARVOO_AX301 ARVOO_AX301 2240 -mapphone MACH_MAPPHONE MAPPHONE 2241 -legend MACH_LEGEND LEGEND 2242 -salsa MACH_SALSA SALSA 2243 -lounge MACH_LOUNGE LOUNGE 2244 -vision MACH_VISION VISION 2245 -vmb20 MACH_VMB20 VMB20 2246 -hy2410 MACH_HY2410 HY2410 2247 -hy9315 MACH_HY9315 HY9315 2248 -bullwinkle MACH_BULLWINKLE BULLWINKLE 2249 -arm_ultimator2 MACH_ARM_ULTIMATOR2 ARM_ULTIMATOR2 2250 -vs_v210 MACH_VS_V210 VS_V210 2252 -vs_v212 MACH_VS_V212 VS_V212 2253 hmt MACH_HMT HMT 2254 -km_kirkwood MACH_KM_KIRKWOOD KM_KIRKWOOD 2255 -vesper MACH_VESPER VESPER 2256 -str9 MACH_STR9 STR9 2257 -omap3_wl_ff MACH_OMAP3_WL_FF OMAP3_WL_FF 2258 -simcom MACH_SIMCOM SIMCOM 2259 -mcwebio MACH_MCWEBIO MCWEBIO 2260 -omap3_phrazer MACH_OMAP3_PHRAZER OMAP3_PHRAZER 2261 -darwin MACH_DARWIN DARWIN 2262 -oratiscomu MACH_ORATISCOMU ORATISCOMU 2263 -rtsbc20 MACH_RTSBC20 RTSBC20 2264 -sgh_i780 MACH_I780 I780 2265 -gemini324 MACH_GEMINI324 GEMINI324 2266 -oratislan MACH_ORATISLAN ORATISLAN 2267 -oratisalog MACH_ORATISALOG ORATISALOG 2268 -oratismadi MACH_ORATISMADI ORATISMADI 2269 -oratisot16 MACH_ORATISOT16 ORATISOT16 2270 -oratisdesk MACH_ORATISDESK ORATISDESK 2271 vexpress MACH_VEXPRESS VEXPRESS 2272 -sintexo MACH_SINTEXO SINTEXO 2273 -cm3389 MACH_CM3389 CM3389 2274 -omap3_cio MACH_OMAP3_CIO OMAP3_CIO 2275 -sgh_i900 MACH_SGH_I900 SGH_I900 2276 -bst100 MACH_BST100 BST100 2277 -passion MACH_PASSION PASSION 2278 -indesign_at91sam MACH_INDESIGN_AT91SAM INDESIGN_AT91SAM 2279 -c4_badger MACH_C4_BADGER C4_BADGER 2280 -c4_viper MACH_C4_VIPER C4_VIPER 2281 d2net MACH_D2NET D2NET 2282 bigdisk MACH_BIGDISK BIGDISK 2283 -notalvision MACH_NOTALVISION NOTALVISION 2284 -omap3_kboc MACH_OMAP3_KBOC OMAP3_KBOC 2285 -cyclone MACH_CYCLONE CYCLONE 2286 -ninja MACH_NINJA NINJA 2287 at91sam9g20ek_2mmc MACH_AT91SAM9G20EK_2MMC AT91SAM9G20EK_2MMC 2288 bcmring MACH_BCMRING BCMRING 2289 -resol_dl2 MACH_RESOL_DL2 RESOL_DL2 2290 -ifosw MACH_IFOSW IFOSW 2291 -htcrhodium MACH_HTCRHODIUM HTCRHODIUM 2292 -htctopaz MACH_HTCTOPAZ HTCTOPAZ 2293 -matrix504 MACH_MATRIX504 MATRIX504 2294 -mrfsa MACH_MRFSA MRFSA 2295 -sc_p270 MACH_SC_P270 SC_P270 2296 -atlas5_evb MACH_ATLAS5_EVB ATLAS5_EVB 2297 -pelco_lobox MACH_PELCO_LOBOX PELCO_LOBOX 2298 -dilax_pcu200 MACH_DILAX_PCU200 DILAX_PCU200 2299 -leonardo MACH_LEONARDO LEONARDO 2300 -zoran_approach7 MACH_ZORAN_APPROACH7 ZORAN_APPROACH7 2301 -dp6xx MACH_DP6XX DP6XX 2302 -bcm2153_vesper MACH_BCM2153_VESPER BCM2153_VESPER 2303 mahimahi MACH_MAHIMAHI MAHIMAHI 2304 -clickc MACH_CLICKC CLICKC 2305 -zb_gateway MACH_ZB_GATEWAY ZB_GATEWAY 2306 -tazcard MACH_TAZCARD TAZCARD 2307 -tazdev MACH_TAZDEV TAZDEV 2308 -annax_cb_arm MACH_ANNAX_CB_ARM ANNAX_CB_ARM 2309 -annax_dm3 MACH_ANNAX_DM3 ANNAX_DM3 2310 -cerebric MACH_CEREBRIC CEREBRIC 2311 -orca MACH_ORCA ORCA 2312 -pc9260 MACH_PC9260 PC9260 2313 -ems285a MACH_EMS285A EMS285A 2314 -gec2410 MACH_GEC2410 GEC2410 2315 -gec2440 MACH_GEC2440 GEC2440 2316 -mw903 MACH_ARCH_MW903 ARCH_MW903 2317 -mw2440 MACH_MW2440 MW2440 2318 -ecac2378 MACH_ECAC2378 ECAC2378 2319 -tazkiosk MACH_TAZKIOSK TAZKIOSK 2320 -whiterabbit_mch MACH_WHITERABBIT_MCH WHITERABBIT_MCH 2321 -sbox9263 MACH_SBOX9263 SBOX9263 2322 -oreo MACH_OREO OREO 2323 smdk6442 MACH_SMDK6442 SMDK6442 2324 openrd_base MACH_OPENRD_BASE OPENRD_BASE 2325 -incredible MACH_INCREDIBLE INCREDIBLE 2326 -incrediblec MACH_INCREDIBLEC INCREDIBLEC 2327 -heroct MACH_HEROCT HEROCT 2328 -mmnet1000 MACH_MMNET1000 MMNET1000 2329 devkit8000 MACH_DEVKIT8000 DEVKIT8000 2330 -devkit9000 MACH_DEVKIT9000 DEVKIT9000 2331 -mx31txtr MACH_MX31TXTR MX31TXTR 2332 -u380 MACH_U380 U380 2333 -oamp3_hualu MACH_HUALU_BOARD HUALU_BOARD 2334 -npcmx50 MACH_NPCMX50 NPCMX50 2335 mx51_efikamx MACH_MX51_EFIKAMX MX51_EFIKAMX 2336 -mx51_lange52 MACH_MX51_LANGE52 MX51_LANGE52 2337 -riom MACH_RIOM RIOM 2338 -comcas MACH_COMCAS COMCAS 2339 -wsi_mx27 MACH_WSI_MX27 WSI_MX27 2340 cm_t35 MACH_CM_T35 CM_T35 2341 net2big MACH_NET2BIG NET2BIG 2342 -motorola_a1600 MACH_MOTOROLA_A1600 MOTOROLA_A1600 2343 igep0020 MACH_IGEP0020 IGEP0020 2344 -igep0010 MACH_IGEP0010 IGEP0010 2345 -mv6281gtwge2 MACH_MV6281GTWGE2 MV6281GTWGE2 2346 -scat100 MACH_SCAT100 SCAT100 2347 -sanmina MACH_SANMINA SANMINA 2348 -momento MACH_MOMENTO MOMENTO 2349 -nuc9xx MACH_NUC9XX NUC9XX 2350 -nuc910evb MACH_NUC910EVB NUC910EVB 2351 -nuc920evb MACH_NUC920EVB NUC920EVB 2352 -nuc950evb MACH_NUC950EVB NUC950EVB 2353 -nuc945evb MACH_NUC945EVB NUC945EVB 2354 -nuc960evb MACH_NUC960EVB NUC960EVB 2355 nuc932evb MACH_NUC932EVB NUC932EVB 2356 -nuc900 MACH_NUC900 NUC900 2357 -sd1soc MACH_SD1SOC SD1SOC 2358 -ln2440bc MACH_LN2440BC LN2440BC 2359 -rsbc MACH_RSBC RSBC 2360 openrd_client MACH_OPENRD_CLIENT OPENRD_CLIENT 2361 -hpipaq11x MACH_HPIPAQ11X HPIPAQ11X 2362 -wayland MACH_WAYLAND WAYLAND 2363 -acnbsx102 MACH_ACNBSX102 ACNBSX102 2364 -hwat91 MACH_HWAT91 HWAT91 2365 -at91sam9263cs MACH_AT91SAM9263CS AT91SAM9263CS 2366 -csb732 MACH_CSB732 CSB732 2367 u8500 MACH_U8500 U8500 2368 -huqiu MACH_HUQIU HUQIU 2369 mx51_efikasb MACH_MX51_EFIKASB MX51_EFIKASB 2370 -pmt1g MACH_PMT1G PMT1G 2371 -htcelf MACH_HTCELF HTCELF 2372 -armadillo420 MACH_ARMADILLO420 ARMADILLO420 2373 -armadillo440 MACH_ARMADILLO440 ARMADILLO440 2374 -u_chip_dual_arm MACH_U_CHIP_DUAL_ARM U_CHIP_DUAL_ARM 2375 -csr_bdb3 MACH_CSR_BDB3 CSR_BDB3 2376 -dolby_cat1018 MACH_DOLBY_CAT1018 DOLBY_CAT1018 2377 -hy9307 MACH_HY9307 HY9307 2378 -aspire_easystore MACH_A_ES A_ES 2379 -davinci_irif MACH_DAVINCI_IRIF DAVINCI_IRIF 2380 -agama9263 MACH_AGAMA9263 AGAMA9263 2381 marvell_jasper MACH_MARVELL_JASPER MARVELL_JASPER 2382 flint MACH_FLINT FLINT 2383 tavorevb3 MACH_TAVOREVB3 TAVOREVB3 2384 -sch_m490 MACH_SCH_M490 SCH_M490 2386 -rbl01 MACH_RBL01 RBL01 2387 -omnifi MACH_OMNIFI OMNIFI 2388 -otavalo MACH_OTAVALO OTAVALO 2389 -sienna MACH_SIENNA SIENNA 2390 -htc_excalibur_s620 MACH_HTC_EXCALIBUR_S620 HTC_EXCALIBUR_S620 2391 -htc_opal MACH_HTC_OPAL HTC_OPAL 2392 touchbook MACH_TOUCHBOOK TOUCHBOOK 2393 -latte MACH_LATTE LATTE 2394 -xa200 MACH_XA200 XA200 2395 -nimrod MACH_NIMROD NIMROD 2396 -cc9p9215_3g MACH_CC9P9215_3G CC9P9215_3G 2397 -cc9p9215_3gjs MACH_CC9P9215_3GJS CC9P9215_3GJS 2398 -tk71 MACH_TK71 TK71 2399 -comham3525 MACH_COMHAM3525 COMHAM3525 2400 -mx31erebus MACH_MX31EREBUS MX31EREBUS 2401 -mcardmx27 MACH_MCARDMX27 MCARDMX27 2402 -paradise MACH_PARADISE PARADISE 2403 -tide MACH_TIDE TIDE 2404 -wzl2440 MACH_WZL2440 WZL2440 2405 -sdrdemo MACH_SDRDEMO SDRDEMO 2406 -ethercan2 MACH_ETHERCAN2 ETHERCAN2 2407 -ecmimg20 MACH_ECMIMG20 ECMIMG20 2408 -omap_dragon MACH_OMAP_DRAGON OMAP_DRAGON 2409 -halo MACH_HALO HALO 2410 -huangshan MACH_HUANGSHAN HUANGSHAN 2411 -vl_ma2sc MACH_VL_MA2SC VL_MA2SC 2412 raumfeld_rc MACH_RAUMFELD_RC RAUMFELD_RC 2413 raumfeld_connector MACH_RAUMFELD_CONNECTOR RAUMFELD_CONNECTOR 2414 raumfeld_speaker MACH_RAUMFELD_SPEAKER RAUMFELD_SPEAKER 2415 -multibus_master MACH_MULTIBUS_MASTER MULTIBUS_MASTER 2416 -multibus_pbk MACH_MULTIBUS_PBK MULTIBUS_PBK 2417 tnetv107x MACH_TNETV107X TNETV107X 2418 -snake MACH_SNAKE SNAKE 2419 -cwmx27 MACH_CWMX27 CWMX27 2420 -sch_m480 MACH_SCH_M480 SCH_M480 2421 -platypus MACH_PLATYPUS PLATYPUS 2422 -pss2 MACH_PSS2 PSS2 2423 -davinci_apm150 MACH_DAVINCI_APM150 DAVINCI_APM150 2424 -str9100 MACH_STR9100 STR9100 2425 -net5big MACH_NET5BIG NET5BIG 2426 -seabed9263 MACH_SEABED9263 SEABED9263 2427 -mx51_m2id MACH_MX51_M2ID MX51_M2ID 2428 -octvocplus_eb MACH_OCTVOCPLUS_EB OCTVOCPLUS_EB 2429 -klk_firefox MACH_KLK_FIREFOX KLK_FIREFOX 2430 -klk_wirma_module MACH_KLK_WIRMA_MODULE KLK_WIRMA_MODULE 2431 -klk_wirma_mmi MACH_KLK_WIRMA_MMI KLK_WIRMA_MMI 2432 -supersonic MACH_SUPERSONIC SUPERSONIC 2433 -liberty MACH_LIBERTY LIBERTY 2434 -mh355 MACH_MH355 MH355 2435 -pc7802 MACH_PC7802 PC7802 2436 -gnet_sgc MACH_GNET_SGC GNET_SGC 2437 -einstein15 MACH_EINSTEIN15 EINSTEIN15 2438 -cmpd MACH_CMPD CMPD 2439 -davinci_hase1 MACH_DAVINCI_HASE1 DAVINCI_HASE1 2440 -lgeincitephone MACH_LGEINCITEPHONE LGEINCITEPHONE 2441 -ea313x MACH_EA313X EA313X 2442 -fwbd_39064 MACH_FWBD_39064 FWBD_39064 2443 -fwbd_390128 MACH_FWBD_390128 FWBD_390128 2444 -pelco_moe MACH_PELCO_MOE PELCO_MOE 2445 -minimix27 MACH_MINIMIX27 MINIMIX27 2446 -omap3_thunder MACH_OMAP3_THUNDER OMAP3_THUNDER 2447 -passionc MACH_PASSIONC PASSIONC 2448 -mx27amata MACH_MX27AMATA MX27AMATA 2449 -bgat1 MACH_BGAT1 BGAT1 2450 -buzz MACH_BUZZ BUZZ 2451 -mb9g20 MACH_MB9G20 MB9G20 2452 -yushan MACH_YUSHAN YUSHAN 2453 -lizard MACH_LIZARD LIZARD 2454 -omap3polycom MACH_OMAP3POLYCOM OMAP3POLYCOM 2455 smdkv210 MACH_SMDKV210 SMDKV210 2456 -bravo MACH_BRAVO BRAVO 2457 -siogentoo1 MACH_SIOGENTOO1 SIOGENTOO1 2458 -siogentoo2 MACH_SIOGENTOO2 SIOGENTOO2 2459 -sm3k MACH_SM3K SM3K 2460 -acer_tempo_f900 MACH_ACER_TEMPO_F900 ACER_TEMPO_F900 2461 -sst61vc010_dev MACH_SST61VC010_DEV SST61VC010_DEV 2462 -glittertind MACH_GLITTERTIND GLITTERTIND 2463 omap_zoom3 MACH_OMAP_ZOOM3 OMAP_ZOOM3 2464 omap_3630sdp MACH_OMAP_3630SDP OMAP_3630SDP 2465 -cybook2440 MACH_CYBOOK2440 CYBOOK2440 2466 -torino_s MACH_TORINO_S TORINO_S 2467 -havana MACH_HAVANA HAVANA 2468 -beaumont_11 MACH_BEAUMONT_11 BEAUMONT_11 2469 -vanguard MACH_VANGUARD VANGUARD 2470 -s5pc110_draco MACH_S5PC110_DRACO S5PC110_DRACO 2471 -cartesio_two MACH_CARTESIO_TWO CARTESIO_TWO 2472 -aster MACH_ASTER ASTER 2473 -voguesv210 MACH_VOGUESV210 VOGUESV210 2474 -acm500x MACH_ACM500X ACM500X 2475 -km9260 MACH_KM9260 KM9260 2476 -nideflexg1 MACH_NIDEFLEXG1 NIDEFLEXG1 2477 -ctera_plug_io MACH_CTERA_PLUG_IO CTERA_PLUG_IO 2478 smartq7 MACH_SMARTQ7 SMARTQ7 2479 -at91sam9g10ek2 MACH_AT91SAM9G10EK2 AT91SAM9G10EK2 2480 -asusp527 MACH_ASUSP527 ASUSP527 2481 -at91sam9g20mpm2 MACH_AT91SAM9G20MPM2 AT91SAM9G20MPM2 2482 -topasa900 MACH_TOPASA900 TOPASA900 2483 -electrum_100 MACH_ELECTRUM_100 ELECTRUM_100 2484 -mx51grb MACH_MX51GRB MX51GRB 2485 -xea300 MACH_XEA300 XEA300 2486 -htcstartrek MACH_HTCSTARTREK HTCSTARTREK 2487 -lima MACH_LIMA LIMA 2488 -csb740 MACH_CSB740 CSB740 2489 -usb_s8815 MACH_USB_S8815 USB_S8815 2490 -watson_efm_plugin MACH_WATSON_EFM_PLUGIN WATSON_EFM_PLUGIN 2491 -milkyway MACH_MILKYWAY MILKYWAY 2492 g4evm MACH_G4EVM G4EVM 2493 -picomod6 MACH_PICOMOD6 PICOMOD6 2494 omapl138_hawkboard MACH_OMAPL138_HAWKBOARD OMAPL138_HAWKBOARD 2495 -ip6000 MACH_IP6000 IP6000 2496 -ip6010 MACH_IP6010 IP6010 2497 -utm400 MACH_UTM400 UTM400 2498 -omap3_zybex MACH_OMAP3_ZYBEX OMAP3_ZYBEX 2499 -wireless_space MACH_WIRELESS_SPACE WIRELESS_SPACE 2500 -sx560 MACH_SX560 SX560 2501 ts41x MACH_TS41X TS41X 2502 -elphel10373 MACH_ELPHEL10373 ELPHEL10373 2503 -rhobot MACH_RHOBOT RHOBOT 2504 -mx51_refresh MACH_MX51_REFRESH MX51_REFRESH 2505 -ls9260 MACH_LS9260 LS9260 2506 -shank MACH_SHANK SHANK 2507 -qsd8x50_st1 MACH_QSD8X50_ST1 QSD8X50_ST1 2508 -at91sam9m10ekes MACH_AT91SAM9M10EKES AT91SAM9M10EKES 2509 -hiram MACH_HIRAM HIRAM 2510 phy3250 MACH_PHY3250 PHY3250 2511 -ea3250 MACH_EA3250 EA3250 2512 -fdi3250 MACH_FDI3250 FDI3250 2513 -whitestone MACH_WHITESTONE WHITESTONE 2514 -at91sam9263nit MACH_AT91SAM9263NIT AT91SAM9263NIT 2515 -ccmx51 MACH_CCMX51 CCMX51 2516 -ccmx51js MACH_CCMX51JS CCMX51JS 2517 -ccwmx51 MACH_CCWMX51 CCWMX51 2518 -ccwmx51js MACH_CCWMX51JS CCWMX51JS 2519 mini6410 MACH_MINI6410 MINI6410 2520 -tiny6410 MACH_TINY6410 TINY6410 2521 -nano6410 MACH_NANO6410 NANO6410 2522 -at572d940hfnldb MACH_AT572D940HFNLDB AT572D940HFNLDB 2523 -htcleo MACH_HTCLEO HTCLEO 2524 -avp13 MACH_AVP13 AVP13 2525 -xxsvideod MACH_XXSVIDEOD XXSVIDEOD 2526 -vpnext MACH_VPNEXT VPNEXT 2527 -swarco_itc3 MACH_SWARCO_ITC3 SWARCO_ITC3 2528 -tx51 MACH_TX51 TX51 2529 -dolby_cat1021 MACH_DOLBY_CAT1021 DOLBY_CAT1021 2530 mx28evk MACH_MX28EVK MX28EVK 2531 -phoenix260 MACH_PHOENIX260 PHOENIX260 2532 -uvaca_stork MACH_UVACA_STORK UVACA_STORK 2533 smartq5 MACH_SMARTQ5 SMARTQ5 2534 -all3078 MACH_ALL3078 ALL3078 2535 -ctera_2bay_ds MACH_CTERA_2BAY_DS CTERA_2BAY_DS 2536 -siogentoo3 MACH_SIOGENTOO3 SIOGENTOO3 2537 -epb5000 MACH_EPB5000 EPB5000 2538 -hy9263 MACH_HY9263 HY9263 2539 -acer_tempo_m900 MACH_ACER_TEMPO_M900 ACER_TEMPO_M900 2540 -acer_tempo_dx650 MACH_ACER_TEMPO_DX900 ACER_TEMPO_DX900 2541 -acer_tempo_x960 MACH_ACER_TEMPO_X960 ACER_TEMPO_X960 2542 -acer_eten_v900 MACH_ACER_ETEN_V900 ACER_ETEN_V900 2543 -acer_eten_x900 MACH_ACER_ETEN_X900 ACER_ETEN_X900 2544 -bonnell MACH_BONNELL BONNELL 2545 -oht_mx27 MACH_OHT_MX27 OHT_MX27 2546 -htcquartz MACH_HTCQUARTZ HTCQUARTZ 2547 davinci_dm6467tevm MACH_DAVINCI_DM6467TEVM DAVINCI_DM6467TEVM 2548 -c3ax03 MACH_C3AX03 C3AX03 2549 mxt_td60 MACH_MXT_TD60 MXT_TD60 2550 -esyx MACH_ESYX ESYX 2551 -dove_db2 MACH_DOVE_DB2 DOVE_DB2 2552 -bulldog MACH_BULLDOG BULLDOG 2553 -derell_me2000 MACH_DERELL_ME2000 DERELL_ME2000 2554 -bcmring_base MACH_BCMRING_BASE BCMRING_BASE 2555 -bcmring_evm MACH_BCMRING_EVM BCMRING_EVM 2556 -bcmring_evm_jazz MACH_BCMRING_EVM_JAZZ BCMRING_EVM_JAZZ 2557 -bcmring_sp MACH_BCMRING_SP BCMRING_SP 2558 -bcmring_sv MACH_BCMRING_SV BCMRING_SV 2559 -bcmring_sv_jazz MACH_BCMRING_SV_JAZZ BCMRING_SV_JAZZ 2560 -bcmring_tablet MACH_BCMRING_TABLET BCMRING_TABLET 2561 -bcmring_vp MACH_BCMRING_VP BCMRING_VP 2562 -bcmring_evm_seikor MACH_BCMRING_EVM_SEIKOR BCMRING_EVM_SEIKOR 2563 -bcmring_sp_wqvga MACH_BCMRING_SP_WQVGA BCMRING_SP_WQVGA 2564 -bcmring_custom MACH_BCMRING_CUSTOM BCMRING_CUSTOM 2565 -acer_s200 MACH_ACER_S200 ACER_S200 2566 -bt270 MACH_BT270 BT270 2567 -iseo MACH_ISEO ISEO 2568 -cezanne MACH_CEZANNE CEZANNE 2569 -lucca MACH_LUCCA LUCCA 2570 -supersmart MACH_SUPERSMART SUPERSMART 2571 -arm11_board MACH_CS_MISANO CS_MISANO 2572 -magnolia2 MACH_MAGNOLIA2 MAGNOLIA2 2573 -emxx MACH_EMXX EMXX 2574 -outlaw MACH_OUTLAW OUTLAW 2575 -riot_bei2 MACH_RIOT_BEI2 RIOT_BEI2 2576 -riot_vox MACH_RIOT_VOX RIOT_VOX 2577 -riot_x37 MACH_RIOT_X37 RIOT_X37 2578 -mega25mx MACH_MEGA25MX MEGA25MX 2579 -benzina2 MACH_BENZINA2 BENZINA2 2580 -ignite MACH_IGNITE IGNITE 2581 -foggia MACH_FOGGIA FOGGIA 2582 -arezzo MACH_AREZZO AREZZO 2583 -leica_skywalker MACH_LEICA_SKYWALKER LEICA_SKYWALKER 2584 -jacinto2_jamr MACH_JACINTO2_JAMR JACINTO2_JAMR 2585 -gts_nova MACH_GTS_NOVA GTS_NOVA 2586 -p3600 MACH_P3600 P3600 2587 -dlt2 MACH_DLT2 DLT2 2588 -df3120 MACH_DF3120 DF3120 2589 -ecucore_9g20 MACH_ECUCORE_9G20 ECUCORE_9G20 2590 -nautel_lpc3240 MACH_NAUTEL_LPC3240 NAUTEL_LPC3240 2591 -glacier MACH_GLACIER GLACIER 2592 -phrazer_bulldog MACH_PHRAZER_BULLDOG PHRAZER_BULLDOG 2593 -omap3_bulldog MACH_OMAP3_BULLDOG OMAP3_BULLDOG 2594 -pca101 MACH_PCA101 PCA101 2595 -buzzc MACH_BUZZC BUZZC 2596 -sasie2 MACH_SASIE2 SASIE2 2597 -davinci_cio MACH_DAVINCI_CIO DAVINCI_CIO 2598 -smartmeter_dl MACH_SMARTMETER_DL SMARTMETER_DL 2599 -wzl6410 MACH_WZL6410 WZL6410 2600 -wzl6410m MACH_WZL6410M WZL6410M 2601 -wzl6410f MACH_WZL6410F WZL6410F 2602 -wzl6410i MACH_WZL6410I WZL6410I 2603 -spacecom1 MACH_SPACECOM1 SPACECOM1 2604 -pingu920 MACH_PINGU920 PINGU920 2605 -bravoc MACH_BRAVOC BRAVOC 2606 -cybo2440 MACH_CYBO2440 CYBO2440 2607 -vdssw MACH_VDSSW VDSSW 2608 -romulus MACH_ROMULUS ROMULUS 2609 -omap_magic MACH_OMAP_MAGIC OMAP_MAGIC 2610 -eltd100 MACH_ELTD100 ELTD100 2611 capc7117 MACH_CAPC7117 CAPC7117 2612 -swan MACH_SWAN SWAN 2613 -veu MACH_VEU VEU 2614 -rm2 MACH_RM2 RM2 2615 -tt2100 MACH_TT2100 TT2100 2616 -venice MACH_VENICE VENICE 2617 -pc7323 MACH_PC7323 PC7323 2618 -masp MACH_MASP MASP 2619 -fujitsu_tvstbsoc0 MACH_FUJITSU_TVSTBSOC FUJITSU_TVSTBSOC 2620 -fujitsu_tvstbsoc1 MACH_FUJITSU_TVSTBSOC1 FUJITSU_TVSTBSOC1 2621 -lexikon MACH_LEXIKON LEXIKON 2622 -mini2440v2 MACH_MINI2440V2 MINI2440V2 2623 icontrol MACH_ICONTROL ICONTROL 2624 -gplugd MACH_SHEEVAD SHEEVAD 2625 -qsd8x50a_st1_1 MACH_QSD8X50A_ST1_1 QSD8X50A_ST1_1 2626 qsd8x50a_st1_5 MACH_QSD8X50A_ST1_5 QSD8X50A_ST1_5 2627 -bee MACH_BEE BEE 2628 mx23evk MACH_MX23EVK MX23EVK 2629 ap4evb MACH_AP4EVB AP4EVB 2630 -stockholm MACH_STOCKHOLM STOCKHOLM 2631 -lpc_h3131 MACH_LPC_H3131 LPC_H3131 2632 -stingray MACH_STINGRAY STINGRAY 2633 -kraken MACH_KRAKEN KRAKEN 2634 -gw2388 MACH_GW2388 GW2388 2635 -jadecpu MACH_JADECPU JADECPU 2636 -carlisle MACH_CARLISLE CARLISLE 2637 -lux_sf9 MACH_LUX_SF9 LUX_SF9 2638 -nemid_tb MACH_NEMID_TB NEMID_TB 2639 -terrier MACH_TERRIER TERRIER 2640 -turbot MACH_TURBOT TURBOT 2641 -sanddab MACH_SANDDAB SANDDAB 2642 -mx35_cicada MACH_MX35_CICADA MX35_CICADA 2643 -ghi2703d MACH_GHI2703D GHI2703D 2644 -lux_sfx9 MACH_LUX_SFX9 LUX_SFX9 2645 -lux_sf9g MACH_LUX_SF9G LUX_SF9G 2646 -lux_edk9 MACH_LUX_EDK9 LUX_EDK9 2647 -hw90240 MACH_HW90240 HW90240 2648 -dm365_leopard MACH_DM365_LEOPARD DM365_LEOPARD 2649 mityomapl138 MACH_MITYOMAPL138 MITYOMAPL138 2650 -scat110 MACH_SCAT110 SCAT110 2651 -acer_a1 MACH_ACER_A1 ACER_A1 2652 -cmcontrol MACH_CMCONTROL CMCONTROL 2653 -pelco_lamar MACH_PELCO_LAMAR PELCO_LAMAR 2654 -rfp43 MACH_RFP43 RFP43 2655 -sk86r0301 MACH_SK86R0301 SK86R0301 2656 -ctpxa MACH_CTPXA CTPXA 2657 -epb_arm9_a MACH_EPB_ARM9_A EPB_ARM9_A 2658 guruplug MACH_GURUPLUG GURUPLUG 2659 spear310 MACH_SPEAR310 SPEAR310 2660 spear320 MACH_SPEAR320 SPEAR320 2661 -robotx MACH_ROBOTX ROBOTX 2662 -lsxhl MACH_LSXHL LSXHL 2663 -smartlite MACH_SMARTLITE SMARTLITE 2664 -cws2 MACH_CWS2 CWS2 2665 -m619 MACH_M619 M619 2666 -smartview MACH_SMARTVIEW SMARTVIEW 2667 -lsa_salsa MACH_LSA_SALSA LSA_SALSA 2668 -kizbox MACH_KIZBOX KIZBOX 2669 -htccharmer MACH_HTCCHARMER HTCCHARMER 2670 -guf_neso_lt MACH_GUF_NESO_LT GUF_NESO_LT 2671 -pm9g45 MACH_PM9G45 PM9G45 2672 -htcpanther MACH_HTCPANTHER HTCPANTHER 2673 -htcpanther_cdma MACH_HTCPANTHER_CDMA HTCPANTHER_CDMA 2674 -reb01 MACH_REB01 REB01 2675 aquila MACH_AQUILA AQUILA 2676 -spark_sls_hw2 MACH_SPARK_SLS_HW2 SPARK_SLS_HW2 2677 sheeva_esata MACH_ESATA_SHEEVAPLUG ESATA_SHEEVAPLUG 2678 msm7x30_surf MACH_MSM7X30_SURF MSM7X30_SURF 2679 -micro2440 MACH_MICRO2440 MICRO2440 2680 -am2440 MACH_AM2440 AM2440 2681 -tq2440 MACH_TQ2440 TQ2440 2682 -lpc2478oem MACH_LPC2478OEM LPC2478OEM 2683 -ak880x MACH_AK880X AK880X 2684 -cobra3530 MACH_COBRA3530 COBRA3530 2685 -pmppb MACH_PMPPB PMPPB 2686 -u6715 MACH_U6715 U6715 2687 -axar1500_sender MACH_AXAR1500_SENDER AXAR1500_SENDER 2688 -g30_dvb MACH_G30_DVB G30_DVB 2689 -vc088x MACH_VC088X VC088X 2690 -mioa702 MACH_MIOA702 MIOA702 2691 -hpmin MACH_HPMIN HPMIN 2692 -ak880xak MACH_AK880XAK AK880XAK 2693 -arm926tomap850 MACH_ARM926TOMAP850 ARM926TOMAP850 2694 -lkevm MACH_LKEVM LKEVM 2695 -mw6410 MACH_MW6410 MW6410 2696 terastation_wxl MACH_TERASTATION_WXL TERASTATION_WXL 2697 -cpu8000e MACH_CPU8000E CPU8000E 2698 -catania MACH_CATANIA CATANIA 2699 -tokyo MACH_TOKYO TOKYO 2700 -msm7201a_surf MACH_MSM7201A_SURF MSM7201A_SURF 2701 -msm7201a_ffa MACH_MSM7201A_FFA MSM7201A_FFA 2702 msm7x25_surf MACH_MSM7X25_SURF MSM7X25_SURF 2703 msm7x25_ffa MACH_MSM7X25_FFA MSM7X25_FFA 2704 msm7x27_surf MACH_MSM7X27_SURF MSM7X27_SURF 2705 msm7x27_ffa MACH_MSM7X27_FFA MSM7X27_FFA 2706 msm7x30_ffa MACH_MSM7X30_FFA MSM7X30_FFA 2707 qsd8x50_surf MACH_QSD8X50_SURF QSD8X50_SURF 2708 -qsd8x50_comet MACH_QSD8X50_COMET QSD8X50_COMET 2709 -qsd8x50_ffa MACH_QSD8X50_FFA QSD8X50_FFA 2710 -qsd8x50a_surf MACH_QSD8X50A_SURF QSD8X50A_SURF 2711 -qsd8x50a_ffa MACH_QSD8X50A_FFA QSD8X50A_FFA 2712 -adx_xgcp10 MACH_ADX_XGCP10 ADX_XGCP10 2713 -mcgwumts2a MACH_MCGWUMTS2A MCGWUMTS2A 2714 -mobikt MACH_MOBIKT MOBIKT 2715 mx53_evk MACH_MX53_EVK MX53_EVK 2716 igep0030 MACH_IGEP0030 IGEP0030 2717 -axell_h40_h50_ctrl MACH_AXELL_H40_H50_CTRL AXELL_H40_H50_CTRL 2718 -dtcommod MACH_DTCOMMOD DTCOMMOD 2719 -gould MACH_GOULD GOULD 2720 -siberia MACH_SIBERIA SIBERIA 2721 sbc3530 MACH_SBC3530 SBC3530 2722 -qarm MACH_QARM QARM 2723 -mips MACH_MIPS MIPS 2724 -mx27grb MACH_MX27GRB MX27GRB 2725 -sbc8100 MACH_SBC8100 SBC8100 2726 saarb MACH_SAARB SAARB 2727 -omap3mini MACH_OMAP3MINI OMAP3MINI 2728 -cnmbook7se MACH_CNMBOOK7SE CNMBOOK7SE 2729 -catan MACH_CATAN CATAN 2730 harmony MACH_HARMONY HARMONY 2731 -tonga MACH_TONGA TONGA 2732 -cybook_orizon MACH_CYBOOK_ORIZON CYBOOK_ORIZON 2733 -htcrhodiumcdma MACH_HTCRHODIUMCDMA HTCRHODIUMCDMA 2734 -epc_g45 MACH_EPC_G45 EPC_G45 2735 -epc_lpc3250 MACH_EPC_LPC3250 EPC_LPC3250 2736 -mxc91341evb MACH_MXC91341EVB MXC91341EVB 2737 -rtw1000 MACH_RTW1000 RTW1000 2738 -bobcat MACH_BOBCAT BOBCAT 2739 -trizeps6 MACH_TRIZEPS6 TRIZEPS6 2740 msm7x30_fluid MACH_MSM7X30_FLUID MSM7X30_FLUID 2741 -nedap9263 MACH_NEDAP9263 NEDAP9263 2742 -netgear_ms2110 MACH_NETGEAR_MS2110 NETGEAR_MS2110 2743 -bmx MACH_BMX BMX 2744 -netstream MACH_NETSTREAM NETSTREAM 2745 -vpnext_rcu MACH_VPNEXT_RCU VPNEXT_RCU 2746 -vpnext_mpu MACH_VPNEXT_MPU VPNEXT_MPU 2747 -bcmring_tablet_v1 MACH_BCMRING_TABLET_V1 BCMRING_TABLET_V1 2748 -sgarm10 MACH_SGARM10 SGARM10 2749 cm_t3517 MACH_CM_T3517 CM_T3517 2750 -omap3_cps MACH_OMAP3_CPS OMAP3_CPS 2751 -axar1500_receiver MACH_AXAR1500_RECEIVER AXAR1500_RECEIVER 2752 wbd222 MACH_WBD222 WBD222 2753 -mt65xx MACH_MT65XX MT65XX 2754 msm8x60_surf MACH_MSM8X60_SURF MSM8X60_SURF 2755 msm8x60_sim MACH_MSM8X60_SIM MSM8X60_SIM 2756 -vmc300 MACH_VMC300 VMC300 2757 tcc8000_sdk MACH_TCC8000_SDK TCC8000_SDK 2758 -nanos MACH_NANOS NANOS 2759 -stamp9g10 MACH_STAMP9G10 STAMP9G10 2760 -stamp9g45 MACH_STAMP9G45 STAMP9G45 2761 -h6053 MACH_H6053 H6053 2762 -smint01 MACH_SMINT01 SMINT01 2763 -prtlvt2 MACH_PRTLVT2 PRTLVT2 2764 ap420 MACH_AP420 AP420 2765 -htcshift MACH_HTCSHIFT HTCSHIFT 2766 davinci_dm365_fc MACH_DAVINCI_DM365_FC DAVINCI_DM365_FC 2767 msm8x55_surf MACH_MSM8X55_SURF MSM8X55_SURF 2768 msm8x55_ffa MACH_MSM8X55_FFA MSM8X55_FFA 2769 @@ -2761,7 +474,6 @@ oreo_controller MACH_OREO_CONTROLLER OREO_CONTROLLER 2773 kopin_models MACH_KOPIN_MODELS KOPIN_MODELS 2774 ttc_vision2 MACH_TTC_VISION2 TTC_VISION2 2775 cns3420vb MACH_CNS3420VB CNS3420VB 2776 -lpc2 MACH_LPC2 LPC2 2777 olympus MACH_OLYMPUS OLYMPUS 2778 vortex MACH_VORTEX VORTEX 2779 s5pc200 MACH_S5PC200 S5PC200 2780 @@ -2788,7 +500,6 @@ ti8168evm MACH_TI8168EVM TI8168EVM 2800 neocoreomap MACH_NEOCOREOMAP NEOCOREOMAP 2801 withings_wbp MACH_WITHINGS_WBP WITHINGS_WBP 2802 dbps MACH_DBPS DBPS 2803 -sbc9261 MACH_SBC9261 SBC9261 2804 pcbfp0001 MACH_PCBFP0001 PCBFP0001 2805 speedy MACH_SPEEDY SPEEDY 2806 chrysaor MACH_CHRYSAOR CHRYSAOR 2807 @@ -2812,7 +523,6 @@ p565 MACH_P565 P565 2824 acer_a4 MACH_ACER_A4 ACER_A4 2825 davinci_dm368_bip MACH_DAVINCI_DM368_BIP DAVINCI_DM368_BIP 2826 eshare MACH_ESHARE ESHARE 2827 -hw_omapl138_europa MACH_HW_OMAPL138_EUROPA HW_OMAPL138_EUROPA 2828 wlbargn MACH_WLBARGN WLBARGN 2829 bm170 MACH_BM170 BM170 2830 netspace_mini_v2 MACH_NETSPACE_MINI_V2 NETSPACE_MINI_V2 2831 @@ -2879,7 +589,6 @@ davinci_picto MACH_DAVINCI_PICTO DAVINCI_PICTO 2891 mecha MACH_MECHA MECHA 2892 bubba3 MACH_BUBBA3 BUBBA3 2893 pupitre MACH_PUPITRE PUPITRE 2894 -tegra_harmony MACH_TEGRA_HARMONY TEGRA_HARMONY 2895 tegra_vogue MACH_TEGRA_VOGUE TEGRA_VOGUE 2896 tegra_e1165 MACH_TEGRA_E1165 TEGRA_E1165 2897 simplenet MACH_SIMPLENET SIMPLENET 2898 @@ -2969,7 +678,6 @@ netspace_lite_v2 MACH_NETSPACE_LITE_V2 NETSPACE_LITE_V2 2983 ssc MACH_SSC SSC 2984 premierwave_en MACH_PREMIERWAVE_EN PREMIERWAVE_EN 2985 wasabi MACH_WASABI WASABI 2986 -vivow MACH_VIVOW VIVOW 2987 mx50_rdp MACH_MX50_RDP MX50_RDP 2988 universal_c210 MACH_UNIVERSAL_C210 UNIVERSAL_C210 2989 real6410 MACH_REAL6410 REAL6410 2990 @@ -3017,12 +725,10 @@ remus MACH_REMUS REMUS 3031 at91cap7xdk MACH_AT91CAP7XDK AT91CAP7XDK 3032 at91cap7stk MACH_AT91CAP7STK AT91CAP7STK 3033 kt_sbc_sam9_1 MACH_KT_SBC_SAM9_1 KT_SBC_SAM9_1 3034 -oratisrouter MACH_ORATISROUTER ORATISROUTER 3035 armada_xp_db MACH_ARMADA_XP_DB ARMADA_XP_DB 3036 spdm MACH_SPDM SPDM 3037 gtib MACH_GTIB GTIB 3038 dgm3240 MACH_DGM3240 DGM3240 3039 -atlas_i_lpe MACH_ATLAS_I_LPE ATLAS_I_LPE 3040 htcmega MACH_HTCMEGA HTCMEGA 3041 tricorder MACH_TRICORDER TRICORDER 3042 tx28 MACH_TX28 TX28 3043 @@ -3062,7 +768,6 @@ clod MACH_CLOD CLOD 3077 rump MACH_RUMP RUMP 3078 tenderloin MACH_TENDERLOIN TENDERLOIN 3079 shortloin MACH_SHORTLOIN SHORTLOIN 3080 -crespo MACH_CRESPO CRESPO 3081 antares MACH_ANTARES ANTARES 3082 wb40n MACH_WB40N WB40N 3083 herring MACH_HERRING HERRING 3084 @@ -3111,7 +816,6 @@ smartqv3 MACH_SMARTQV3 SMARTQV3 3126 smartqv7 MACH_SMARTQV7 SMARTQV7 3127 paz00 MACH_PAZ00 PAZ00 3128 acmenetusfoxg20 MACH_ACMENETUSFOXG20 ACMENETUSFOXG20 3129 -htcwillow MACH_HTCWILLOW HTCWILLOW 3130 fwbd_0404 MACH_FWBD_0404 FWBD_0404 3131 hdgu MACH_HDGU HDGU 3132 pyramid MACH_PYRAMID PYRAMID 3133 @@ -3162,7 +866,6 @@ b5500 MACH_B5500 B5500 3177 s5500 MACH_S5500 S5500 3178 icon MACH_ICON ICON 3179 elephant MACH_ELEPHANT ELEPHANT 3180 -msm8x60_fusion MACH_MSM8X60_FUSION MSM8X60_FUSION 3181 shooter MACH_SHOOTER SHOOTER 3182 spade_lte MACH_SPADE_LTE SPADE_LTE 3183 philhwani MACH_PHILHWANI PHILHWANI 3184 @@ -3174,13 +877,11 @@ ag5evm MACH_AG5EVM AG5EVM 3189 sc575plc MACH_SC575PLC SC575PLC 3190 sc575hmi MACH_SC575IPC SC575IPC 3191 omap3_tdm3730 MACH_OMAP3_TDM3730 OMAP3_TDM3730 3192 -g7 MACH_G7 G7 3193 top9000_eval MACH_TOP9000_EVAL TOP9000_EVAL 3194 top9000_su MACH_TOP9000_SU TOP9000_SU 3195 utm300 MACH_UTM300 UTM300 3196 tsunagi MACH_TSUNAGI TSUNAGI 3197 ts75xx MACH_TS75XX TS75XX 3198 -msm8x60_fusn_ffa MACH_MSM8X60_FUSN_FFA MSM8X60_FUSN_FFA 3199 ts47xx MACH_TS47XX TS47XX 3200 da850_k5 MACH_DA850_K5 DA850_K5 3201 ax502 MACH_AX502 AX502 3202 @@ -3285,7 +986,6 @@ rfl109145_ssrv MACH_RFL109145_SSRV RFL109145_SSRV 3304 nmh MACH_NMH NMH 3305 wn802t MACH_WN802T WN802T 3306 dragonet MACH_DRAGONET DRAGONET 3307 -geneva_b MACH_GENEVA_B GENEVA_B 3308 at91sam9263desk16l MACH_AT91SAM9263DESK16L AT91SAM9263DESK16L 3309 bcmhana_sv MACH_BCMHANA_SV BCMHANA_SV 3310 bcmhana_tablet MACH_BCMHANA_TABLET BCMHANA_TABLET 3311 @@ -3316,3 +1016,86 @@ rover_g8 MACH_ROVER_G8 ROVER_G8 3335 t5388p MACH_T5388P T5388P 3336 dingo MACH_DINGO DINGO 3337 goflexhome MACH_GOFLEXHOME GOFLEXHOME 3338 +lanreadyfn511 MACH_LANREADYFN511 LANREADYFN511 3340 +omap3_baia MACH_OMAP3_BAIA OMAP3_BAIA 3341 +omap3smartdisplay MACH_OMAP3SMARTDISPLAY OMAP3SMARTDISPLAY 3342 +xilinx MACH_XILINX XILINX 3343 +a2f MACH_A2F A2F 3344 +sky25 MACH_SKY25 SKY25 3345 +ccmx53 MACH_CCMX53 CCMX53 3346 +ccmx53js MACH_CCMX53JS CCMX53JS 3347 +ccwmx53 MACH_CCWMX53 CCWMX53 3348 +ccwmx53js MACH_CCWMX53JS CCWMX53JS 3349 +frisms MACH_FRISMS FRISMS 3350 +msm7x27a_ffa MACH_MSM7X27A_FFA MSM7X27A_FFA 3351 +msm7x27a_surf MACH_MSM7X27A_SURF MSM7X27A_SURF 3352 +msm7x27a_rumi3 MACH_MSM7X27A_RUMI3 MSM7X27A_RUMI3 3353 +dimmsam9g20 MACH_DIMMSAM9G20 DIMMSAM9G20 3354 +dimm_imx28 MACH_DIMM_IMX28 DIMM_IMX28 3355 +amk_a4 MACH_AMK_A4 AMK_A4 3356 +gnet_sgme MACH_GNET_SGME GNET_SGME 3357 +shooter_u MACH_SHOOTER_U SHOOTER_U 3358 +vmx53 MACH_VMX53 VMX53 3359 +rhino MACH_RHINO RHINO 3360 +armlex4210 MACH_ARMLEX4210 ARMLEX4210 3361 +swarcoextmodem MACH_SWARCOEXTMODEM SWARCOEXTMODEM 3362 +snowball MACH_SNOWBALL SNOWBALL 3363 +pcm049 MACH_PCM049 PCM049 3364 +vigor MACH_VIGOR VIGOR 3365 +oslo_amundsen MACH_OSLO_AMUNDSEN OSLO_AMUNDSEN 3366 +gsl_diamond MACH_GSL_DIAMOND GSL_DIAMOND 3367 +cv2201 MACH_CV2201 CV2201 3368 +cv2202 MACH_CV2202 CV2202 3369 +cv2203 MACH_CV2203 CV2203 3370 +vit_ibox MACH_VIT_IBOX VIT_IBOX 3371 +dm6441_esp MACH_DM6441_ESP DM6441_ESP 3372 +at91sam9x5ek MACH_AT91SAM9X5EK AT91SAM9X5EK 3373 +libra MACH_LIBRA LIBRA 3374 +easycrrh MACH_EASYCRRH EASYCRRH 3375 +tripel MACH_TRIPEL TRIPEL 3376 +endian_mini MACH_ENDIAN_MINI ENDIAN_MINI 3377 +xilinx_ep107 MACH_XILINX_EP107 XILINX_EP107 3378 +nuri MACH_NURI NURI 3379 +janus MACH_JANUS JANUS 3380 +ddnas MACH_DDNAS DDNAS 3381 +tag MACH_TAG TAG 3382 +tagw MACH_TAGW TAGW 3383 +nitrogen_vm_imx51 MACH_NITROGEN_VM_IMX51 NITROGEN_VM_IMX51 3384 +viprinet MACH_VIPRINET VIPRINET 3385 +bockw MACH_BOCKW BOCKW 3386 +eva2000 MACH_EVA2000 EVA2000 3387 +steelyard MACH_STEELYARD STEELYARD 3388 +sdh001 MACH_MACH_SDH001 MACH_SDH001 3390 +nsslsboard MACH_NSSLSBOARD NSSLSBOARD 3392 +geneva_b5 MACH_GENEVA_B5 GENEVA_B5 3393 +spear1340 MACH_SPEAR1340 SPEAR1340 3394 +rexmas MACH_REXMAS REXMAS 3395 +msm8960_cdp MACH_MSM8960_CDP MSM8960_CDP 3396 +msm8960_mdp MACH_MSM8960_MDP MSM8960_MDP 3397 +msm8960_fluid MACH_MSM8960_FLUID MSM8960_FLUID 3398 +msm8960_apq MACH_MSM8960_APQ MSM8960_APQ 3399 +helios_v2 MACH_HELIOS_V2 HELIOS_V2 3400 +mif10p MACH_MIF10P MIF10P 3401 +iam28 MACH_IAM28 IAM28 3402 +picasso MACH_PICASSO PICASSO 3403 +mr301a MACH_MR301A MR301A 3404 +notle MACH_NOTLE NOTLE 3405 +eelx2 MACH_EELX2 EELX2 3406 +moon MACH_MOON MOON 3407 +ruby MACH_RUBY RUBY 3408 +goldengate MACH_GOLDENGATE GOLDENGATE 3409 +ctbu_gen2 MACH_CTBU_GEN2 CTBU_GEN2 3410 +kmp_am17_01 MACH_KMP_AM17_01 KMP_AM17_01 3411 +wtplug MACH_WTPLUG WTPLUG 3412 +mx27su2 MACH_MX27SU2 MX27SU2 3413 +nb31 MACH_NB31 NB31 3414 +hjsdu MACH_HJSDU HJSDU 3415 +td3_rev1 MACH_TD3_REV1 TD3_REV1 3416 +eag_ci4000 MACH_EAG_CI4000 EAG_CI4000 3417 +net5big_nand_v2 MACH_NET5BIG_NAND_V2 NET5BIG_NAND_V2 3418 +cpx2 MACH_CPX2 CPX2 3419 +net2big_nand_v2 MACH_NET2BIG_NAND_V2 NET2BIG_NAND_V2 3420 +ecuv5 MACH_ECUV5 ECUV5 3421 +hsgx6d MACH_HSGX6D HSGX6D 3422 +dawad7 MACH_DAWAD7 DAWAD7 3423 +sam9repeater MACH_SAM9REPEATER SAM9REPEATER 3424 diff --git a/arch/arm/vfp/Makefile b/arch/arm/vfp/Makefile index 39f6d8e1af7..6de73aab019 100644 --- a/arch/arm/vfp/Makefile +++ b/arch/arm/vfp/Makefile @@ -4,8 +4,8 @@ # Copyright (C) 2001 ARM Limited # -# EXTRA_CFLAGS := -DDEBUG -# EXTRA_AFLAGS := -DDEBUG +# ccflags-y := -DDEBUG +# asflags-y := -DDEBUG KBUILD_AFLAGS :=$(KBUILD_AFLAGS:-msoft-float=-Wa,-mfpu=softvfp+vfp) LDFLAGS +=--no-warn-mismatch diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index bbf3da012af..f74695075e6 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -78,6 +78,14 @@ static void vfp_thread_exit(struct thread_info *thread) put_cpu(); } +static void vfp_thread_copy(struct thread_info *thread) +{ + struct thread_info *parent = current_thread_info(); + + vfp_sync_hwstate(parent); + thread->vfpstate = parent->vfpstate; +} + /* * When this function is called with the following 'cmd's, the following * is true while this function is being run: @@ -104,12 +112,17 @@ static void vfp_thread_exit(struct thread_info *thread) static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v) { struct thread_info *thread = v; + u32 fpexc; +#ifdef CONFIG_SMP + unsigned int cpu; +#endif - if (likely(cmd == THREAD_NOTIFY_SWITCH)) { - u32 fpexc = fmrx(FPEXC); + switch (cmd) { + case THREAD_NOTIFY_SWITCH: + fpexc = fmrx(FPEXC); #ifdef CONFIG_SMP - unsigned int cpu = thread->cpu; + cpu = thread->cpu; /* * On SMP, if VFP is enabled, save the old state in @@ -134,13 +147,20 @@ static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v) * old state. */ fmxr(FPEXC, fpexc & ~FPEXC_EN); - return NOTIFY_DONE; - } + break; - if (cmd == THREAD_NOTIFY_FLUSH) + case THREAD_NOTIFY_FLUSH: vfp_thread_flush(thread); - else + break; + + case THREAD_NOTIFY_EXIT: vfp_thread_exit(thread); + break; + + case THREAD_NOTIFY_COPY: + vfp_thread_copy(thread); + break; + } return NOTIFY_DONE; } diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig index cd2062fe0f6..e9d689b7c83 100644 --- a/arch/avr32/Kconfig +++ b/arch/avr32/Kconfig @@ -6,6 +6,10 @@ config AVR32 select HAVE_CLK select HAVE_OPROFILE select HAVE_KPROBES + select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_PROBE + select HARDIRQS_SW_RESEND + select GENERIC_IRQ_SHOW help AVR32 is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular @@ -17,9 +21,6 @@ config AVR32 config GENERIC_GPIO def_bool y -config GENERIC_HARDIRQS - def_bool y - config STACKTRACE_SUPPORT def_bool y @@ -29,12 +30,6 @@ config LOCKDEP_SUPPORT config TRACE_IRQFLAGS_SUPPORT def_bool y -config HARDIRQS_SW_RESEND - def_bool y - -config GENERIC_IRQ_PROBE - def_bool y - config RWSEM_GENERIC_SPINLOCK def_bool y diff --git a/arch/avr32/boards/atngw100/mrmt.c b/arch/avr32/boards/atngw100/mrmt.c index 7919be311f4..f9143196345 100644 --- a/arch/avr32/boards/atngw100/mrmt.c +++ b/arch/avr32/boards/atngw100/mrmt.c @@ -301,7 +301,7 @@ static int __init mrmt1_init(void) /* Select the Touchscreen interrupt pin mode */ at32_select_periph( GPIO_PIOB_BASE, 1 << (PB_EXTINT_BASE+TS_IRQ), GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH); - set_irq_type( AT32_EXTINT(TS_IRQ), IRQ_TYPE_EDGE_FALLING ); + irq_set_irq_type(AT32_EXTINT(TS_IRQ), IRQ_TYPE_EDGE_FALLING); at32_spi_setup_slaves(0,spi01_board_info,ARRAY_SIZE(spi01_board_info)); spi_register_board_info(spi01_board_info,ARRAY_SIZE(spi01_board_info)); #endif diff --git a/arch/avr32/boards/atngw100/setup.c b/arch/avr32/boards/atngw100/setup.c index 659d119ce71..fafed4c38fd 100644 --- a/arch/avr32/boards/atngw100/setup.c +++ b/arch/avr32/boards/atngw100/setup.c @@ -322,6 +322,6 @@ static int __init atngw100_arch_init(void) /* set_irq_type() after the arch_initcall for EIC has run, and * before the I2C subsystem could try using this IRQ. */ - return set_irq_type(AT32_EXTINT(3), IRQ_TYPE_EDGE_FALLING); + return irq_set_irq_type(AT32_EXTINT(3), IRQ_TYPE_EDGE_FALLING); } arch_initcall(atngw100_arch_init); diff --git a/arch/avr32/include/asm/bitops.h b/arch/avr32/include/asm/bitops.h index f7dd5f71edf..72444d97f80 100644 --- a/arch/avr32/include/asm/bitops.h +++ b/arch/avr32/include/asm/bitops.h @@ -299,8 +299,7 @@ static inline int ffs(unsigned long word) #include <asm-generic/bitops/hweight.h> #include <asm-generic/bitops/lock.h> -#include <asm-generic/bitops/ext2-non-atomic.h> +#include <asm-generic/bitops/le.h> #include <asm-generic/bitops/ext2-atomic.h> -#include <asm-generic/bitops/minix-le.h> #endif /* __ASM_AVR32_BITOPS_H */ diff --git a/arch/avr32/include/asm/setup.h b/arch/avr32/include/asm/setup.h index ff5b7cf6be4..160543dbec7 100644 --- a/arch/avr32/include/asm/setup.h +++ b/arch/avr32/include/asm/setup.h @@ -94,6 +94,13 @@ struct tag_ethernet { #define ETH_INVALID_PHY 0xff +/* board information */ +#define ATAG_BOARDINFO 0x54410008 + +struct tag_boardinfo { + u32 board_number; +}; + struct tag { struct tag_header hdr; union { @@ -102,6 +109,7 @@ struct tag { struct tag_cmdline cmdline; struct tag_clock clock; struct tag_ethernet ethernet; + struct tag_boardinfo boardinfo; } u; }; @@ -128,6 +136,7 @@ extern struct tag *bootloader_tags; extern resource_size_t fbmem_start; extern resource_size_t fbmem_size; +extern u32 board_number; void setup_processor(void); diff --git a/arch/avr32/include/asm/types.h b/arch/avr32/include/asm/types.h index 9cefda6f534..72667a3b1af 100644 --- a/arch/avr32/include/asm/types.h +++ b/arch/avr32/include/asm/types.h @@ -23,14 +23,6 @@ typedef unsigned short umode_t; #define BITS_PER_LONG 32 -#ifndef __ASSEMBLY__ - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -#endif /* __ASSEMBLY__ */ - #endif /* __KERNEL__ */ diff --git a/arch/avr32/kernel/avr32_ksyms.c b/arch/avr32/kernel/avr32_ksyms.c index 11e310c567a..d93ead02dae 100644 --- a/arch/avr32/kernel/avr32_ksyms.c +++ b/arch/avr32/kernel/avr32_ksyms.c @@ -58,8 +58,8 @@ EXPORT_SYMBOL(find_first_zero_bit); EXPORT_SYMBOL(find_next_zero_bit); EXPORT_SYMBOL(find_first_bit); EXPORT_SYMBOL(find_next_bit); -EXPORT_SYMBOL(generic_find_next_le_bit); -EXPORT_SYMBOL(generic_find_next_zero_le_bit); +EXPORT_SYMBOL(find_next_bit_le); +EXPORT_SYMBOL(find_next_zero_bit_le); /* I/O primitives (lib/io-*.S) */ EXPORT_SYMBOL(__raw_readsb); diff --git a/arch/avr32/kernel/irq.c b/arch/avr32/kernel/irq.c index 9604f7758f9..bc3aa18293d 100644 --- a/arch/avr32/kernel/irq.c +++ b/arch/avr32/kernel/irq.c @@ -26,40 +26,3 @@ void __weak nmi_disable(void) { } - -#ifdef CONFIG_PROC_FS -int show_interrupts(struct seq_file *p, void *v) -{ - int i = *(loff_t *)v, cpu; - struct irqaction *action; - unsigned long flags; - - if (i == 0) { - seq_puts(p, " "); - for_each_online_cpu(cpu) - seq_printf(p, "CPU%d ", cpu); - seq_putc(p, '\n'); - } - - if (i < NR_IRQS) { - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); - action = irq_desc[i].action; - if (!action) - goto unlock; - - seq_printf(p, "%3d: ", i); - for_each_online_cpu(cpu) - seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); - seq_printf(p, " %8s", irq_desc[i].chip->name ? : "-"); - seq_printf(p, " %s", action->name); - for (action = action->next; action; action = action->next) - seq_printf(p, ", %s", action->name); - - seq_putc(p, '\n'); - unlock: - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); - } - - return 0; -} -#endif diff --git a/arch/avr32/kernel/setup.c b/arch/avr32/kernel/setup.c index 5c7083916c3..bb0974cce4a 100644 --- a/arch/avr32/kernel/setup.c +++ b/arch/avr32/kernel/setup.c @@ -391,6 +391,21 @@ static int __init parse_tag_clock(struct tag *tag) __tagtable(ATAG_CLOCK, parse_tag_clock); /* + * The board_number correspond to the bd->bi_board_number in U-Boot. This + * parameter is only available during initialisation and can be used in some + * kind of board identification. + */ +u32 __initdata board_number; + +static int __init parse_tag_boardinfo(struct tag *tag) +{ + board_number = tag->u.boardinfo.board_number; + + return 0; +} +__tagtable(ATAG_BOARDINFO, parse_tag_boardinfo); + +/* * Scan the tag table for this tag, and call its parse function. The * tag table is built by the linker from all the __tagtable * declarations. diff --git a/arch/avr32/kernel/traps.c b/arch/avr32/kernel/traps.c index b91b2044af9..7aa25756412 100644 --- a/arch/avr32/kernel/traps.c +++ b/arch/avr32/kernel/traps.c @@ -95,28 +95,6 @@ void _exception(long signr, struct pt_regs *regs, int code, info.si_code = code; info.si_addr = (void __user *)addr; force_sig_info(signr, &info, current); - - /* - * Init gets no signals that it doesn't have a handler for. - * That's all very well, but if it has caused a synchronous - * exception and we ignore the resulting signal, it will just - * generate the same exception over and over again and we get - * nowhere. Better to kill it and let the kernel panic. - */ - if (is_global_init(current)) { - __sighandler_t handler; - - spin_lock_irq(¤t->sighand->siglock); - handler = current->sighand->action[signr-1].sa.sa_handler; - spin_unlock_irq(¤t->sighand->siglock); - if (handler == SIG_DFL) { - /* init has generated a synchronous exception - and it doesn't have a handler for the signal */ - printk(KERN_CRIT "init has generated signal %ld " - "but has no handler for it\n", signr); - do_exit(signr); - } - } } asmlinkage void do_nmi(unsigned long ecr, struct pt_regs *regs) diff --git a/arch/avr32/lib/findbit.S b/arch/avr32/lib/findbit.S index 997b33b2288..b93586460be 100644 --- a/arch/avr32/lib/findbit.S +++ b/arch/avr32/lib/findbit.S @@ -123,7 +123,7 @@ ENTRY(find_next_bit) brgt 1b retal r11 -ENTRY(generic_find_next_le_bit) +ENTRY(find_next_bit_le) lsr r8, r10, 5 sub r9, r11, r10 retle r11 @@ -153,7 +153,7 @@ ENTRY(generic_find_next_le_bit) brgt 1b retal r11 -ENTRY(generic_find_next_zero_le_bit) +ENTRY(find_next_zero_bit_le) lsr r8, r10, 5 sub r9, r11, r10 retle r11 diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c index e67c9994542..bfc9d071db9 100644 --- a/arch/avr32/mach-at32ap/at32ap700x.c +++ b/arch/avr32/mach-at32ap/at32ap700x.c @@ -2048,6 +2048,11 @@ at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data, rx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT; rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3); rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); + rx_dws->src_master = 0; + rx_dws->dst_master = 1; + rx_dws->src_msize = DW_DMA_MSIZE_1; + rx_dws->dst_msize = DW_DMA_MSIZE_1; + rx_dws->fc = DW_DMA_FC_D_P2M; } /* Check if DMA slave interface for playback should be configured. */ @@ -2056,6 +2061,11 @@ at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data, tx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT; tx_dws->cfg_hi = DWC_CFGH_DST_PER(4); tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); + tx_dws->src_master = 0; + tx_dws->dst_master = 1; + tx_dws->src_msize = DW_DMA_MSIZE_1; + tx_dws->dst_msize = DW_DMA_MSIZE_1; + tx_dws->fc = DW_DMA_FC_D_M2P; } if (platform_device_add_data(pdev, data, @@ -2128,6 +2138,11 @@ at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data) dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT; dws->cfg_hi = DWC_CFGH_DST_PER(2); dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); + dws->src_master = 0; + dws->dst_master = 1; + dws->src_msize = DW_DMA_MSIZE_1; + dws->dst_msize = DW_DMA_MSIZE_1; + dws->fc = DW_DMA_FC_D_M2P; if (platform_device_add_data(pdev, data, sizeof(struct atmel_abdac_pdata))) diff --git a/arch/avr32/mach-at32ap/clock.c b/arch/avr32/mach-at32ap/clock.c index 442f08c5e64..86925fd6ea5 100644 --- a/arch/avr32/mach-at32ap/clock.c +++ b/arch/avr32/mach-at32ap/clock.c @@ -35,22 +35,30 @@ void at32_clk_register(struct clk *clk) spin_unlock(&clk_list_lock); } -struct clk *clk_get(struct device *dev, const char *id) +static struct clk *__clk_get(struct device *dev, const char *id) { struct clk *clk; - spin_lock(&clk_list_lock); - list_for_each_entry(clk, &at32_clock_list, list) { if (clk->dev == dev && strcmp(id, clk->name) == 0) { - spin_unlock(&clk_list_lock); return clk; } } - spin_unlock(&clk_list_lock); return ERR_PTR(-ENOENT); } + +struct clk *clk_get(struct device *dev, const char *id) +{ + struct clk *clk; + + spin_lock(&clk_list_lock); + clk = __clk_get(dev, id); + spin_unlock(&clk_list_lock); + + return clk; +} + EXPORT_SYMBOL(clk_get); void clk_put(struct clk *clk) @@ -257,15 +265,15 @@ static int clk_show(struct seq_file *s, void *unused) spin_lock(&clk_list_lock); /* show clock tree as derived from the three oscillators */ - clk = clk_get(NULL, "osc32k"); + clk = __clk_get(NULL, "osc32k"); dump_clock(clk, &r); clk_put(clk); - clk = clk_get(NULL, "osc0"); + clk = __clk_get(NULL, "osc0"); dump_clock(clk, &r); clk_put(clk); - clk = clk_get(NULL, "osc1"); + clk = __clk_get(NULL, "osc1"); dump_clock(clk, &r); clk_put(clk); diff --git a/arch/avr32/mach-at32ap/extint.c b/arch/avr32/mach-at32ap/extint.c index e9d12058ffd..fbc2aeaebdd 100644 --- a/arch/avr32/mach-at32ap/extint.c +++ b/arch/avr32/mach-at32ap/extint.c @@ -61,45 +61,42 @@ struct eic { static struct eic *nmi_eic; static bool nmi_enabled; -static void eic_ack_irq(unsigned int irq) +static void eic_ack_irq(struct irq_data *d) { - struct eic *eic = get_irq_chip_data(irq); - eic_writel(eic, ICR, 1 << (irq - eic->first_irq)); + struct eic *eic = irq_data_get_irq_chip_data(d); + eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq)); } -static void eic_mask_irq(unsigned int irq) +static void eic_mask_irq(struct irq_data *d) { - struct eic *eic = get_irq_chip_data(irq); - eic_writel(eic, IDR, 1 << (irq - eic->first_irq)); + struct eic *eic = irq_data_get_irq_chip_data(d); + eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq)); } -static void eic_mask_ack_irq(unsigned int irq) +static void eic_mask_ack_irq(struct irq_data *d) { - struct eic *eic = get_irq_chip_data(irq); - eic_writel(eic, ICR, 1 << (irq - eic->first_irq)); - eic_writel(eic, IDR, 1 << (irq - eic->first_irq)); + struct eic *eic = irq_data_get_irq_chip_data(d); + eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq)); + eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq)); } -static void eic_unmask_irq(unsigned int irq) +static void eic_unmask_irq(struct irq_data *d) { - struct eic *eic = get_irq_chip_data(irq); - eic_writel(eic, IER, 1 << (irq - eic->first_irq)); + struct eic *eic = irq_data_get_irq_chip_data(d); + eic_writel(eic, IER, 1 << (d->irq - eic->first_irq)); } -static int eic_set_irq_type(unsigned int irq, unsigned int flow_type) +static int eic_set_irq_type(struct irq_data *d, unsigned int flow_type) { - struct eic *eic = get_irq_chip_data(irq); - struct irq_desc *desc; + struct eic *eic = irq_data_get_irq_chip_data(d); + unsigned int irq = d->irq; unsigned int i = irq - eic->first_irq; u32 mode, edge, level; - int ret = 0; flow_type &= IRQ_TYPE_SENSE_MASK; if (flow_type == IRQ_TYPE_NONE) flow_type = IRQ_TYPE_LEVEL_LOW; - desc = &irq_desc[irq]; - mode = eic_readl(eic, MODE); edge = eic_readl(eic, EDGE); level = eic_readl(eic, LEVEL); @@ -122,39 +119,34 @@ static int eic_set_irq_type(unsigned int irq, unsigned int flow_type) edge &= ~(1 << i); break; default: - ret = -EINVAL; - break; + return -EINVAL; } - if (ret == 0) { - eic_writel(eic, MODE, mode); - eic_writel(eic, EDGE, edge); - eic_writel(eic, LEVEL, level); - - if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) { - flow_type |= IRQ_LEVEL; - __set_irq_handler_unlocked(irq, handle_level_irq); - } else - __set_irq_handler_unlocked(irq, handle_edge_irq); - desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); - desc->status |= flow_type; - } + eic_writel(eic, MODE, mode); + eic_writel(eic, EDGE, edge); + eic_writel(eic, LEVEL, level); - return ret; + irqd_set_trigger_type(d, flow_type); + if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + __irq_set_handler_locked(irq, handle_level_irq); + else + __irq_set_handler_locked(irq, handle_edge_irq); + + return IRQ_SET_MASK_OK_NOCOPY; } static struct irq_chip eic_chip = { .name = "eic", - .ack = eic_ack_irq, - .mask = eic_mask_irq, - .mask_ack = eic_mask_ack_irq, - .unmask = eic_unmask_irq, - .set_type = eic_set_irq_type, + .irq_ack = eic_ack_irq, + .irq_mask = eic_mask_irq, + .irq_mask_ack = eic_mask_ack_irq, + .irq_unmask = eic_unmask_irq, + .irq_set_type = eic_set_irq_type, }; static void demux_eic_irq(unsigned int irq, struct irq_desc *desc) { - struct eic *eic = desc->handler_data; + struct eic *eic = irq_desc_get_handler_data(desc); unsigned long status, pending; unsigned int i; @@ -199,7 +191,7 @@ static int __init eic_probe(struct platform_device *pdev) regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); int_irq = platform_get_irq(pdev, 0); - if (!regs || !int_irq) { + if (!regs || (int)int_irq <= 0) { dev_dbg(&pdev->dev, "missing regs and/or irq resource\n"); return -ENXIO; } @@ -234,13 +226,13 @@ static int __init eic_probe(struct platform_device *pdev) eic->chip = &eic_chip; for (i = 0; i < nr_of_irqs; i++) { - set_irq_chip_and_handler(eic->first_irq + i, &eic_chip, + irq_set_chip_and_handler(eic->first_irq + i, &eic_chip, handle_level_irq); - set_irq_chip_data(eic->first_irq + i, eic); + irq_set_chip_data(eic->first_irq + i, eic); } - set_irq_chained_handler(int_irq, demux_eic_irq); - set_irq_data(int_irq, eic); + irq_set_chained_handler(int_irq, demux_eic_irq); + irq_set_handler_data(int_irq, eic); if (pdev->id == 0) { nmi_eic = eic; diff --git a/arch/avr32/mach-at32ap/intc.c b/arch/avr32/mach-at32ap/intc.c index 994c4545e2b..21ce35f33aa 100644 --- a/arch/avr32/mach-at32ap/intc.c +++ b/arch/avr32/mach-at32ap/intc.c @@ -34,12 +34,12 @@ extern struct platform_device at32_intc0_device; * TODO: We may be able to implement mask/unmask by setting IxM flags * in the status register. */ -static void intc_mask_irq(unsigned int irq) +static void intc_mask_irq(struct irq_data *d) { } -static void intc_unmask_irq(unsigned int irq) +static void intc_unmask_irq(struct irq_data *d) { } @@ -47,8 +47,8 @@ static void intc_unmask_irq(unsigned int irq) static struct intc intc0 = { .chip = { .name = "intc", - .mask = intc_mask_irq, - .unmask = intc_unmask_irq, + .irq_mask = intc_mask_irq, + .irq_unmask = intc_unmask_irq, }, }; @@ -57,7 +57,6 @@ static struct intc intc0 = { */ asmlinkage void do_IRQ(int level, struct pt_regs *regs) { - struct irq_desc *desc; struct pt_regs *old_regs; unsigned int irq; unsigned long status_reg; @@ -69,8 +68,7 @@ asmlinkage void do_IRQ(int level, struct pt_regs *regs) irq_enter(); irq = intc_readl(&intc0, INTCAUSE0 - 4 * level); - desc = irq_desc + irq; - desc->handle_irq(irq, desc); + generic_handle_irq(irq); /* * Clear all interrupt level masks so that we may handle @@ -128,7 +126,7 @@ void __init init_IRQ(void) intc_writel(&intc0, INTPR0 + 4 * i, offset); readback = intc_readl(&intc0, INTPR0 + 4 * i); if (readback == offset) - set_irq_chip_and_handler(i, &intc0.chip, + irq_set_chip_and_handler(i, &intc0.chip, handle_simple_irq); } diff --git a/arch/avr32/mach-at32ap/pio.c b/arch/avr32/mach-at32ap/pio.c index 09a274c9d0b..2e0aa853a4b 100644 --- a/arch/avr32/mach-at32ap/pio.c +++ b/arch/avr32/mach-at32ap/pio.c @@ -249,23 +249,23 @@ static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) /* GPIO IRQ support */ -static void gpio_irq_mask(unsigned irq) +static void gpio_irq_mask(struct irq_data *d) { - unsigned gpio = irq_to_gpio(irq); + unsigned gpio = irq_to_gpio(d->irq); struct pio_device *pio = &pio_dev[gpio >> 5]; pio_writel(pio, IDR, 1 << (gpio & 0x1f)); } -static void gpio_irq_unmask(unsigned irq) +static void gpio_irq_unmask(struct irq_data *d) { - unsigned gpio = irq_to_gpio(irq); + unsigned gpio = irq_to_gpio(d->irq); struct pio_device *pio = &pio_dev[gpio >> 5]; pio_writel(pio, IER, 1 << (gpio & 0x1f)); } -static int gpio_irq_type(unsigned irq, unsigned type) +static int gpio_irq_type(struct irq_data *d, unsigned type) { if (type != IRQ_TYPE_EDGE_BOTH && type != IRQ_TYPE_NONE) return -EINVAL; @@ -275,20 +275,19 @@ static int gpio_irq_type(unsigned irq, unsigned type) static struct irq_chip gpio_irqchip = { .name = "gpio", - .mask = gpio_irq_mask, - .unmask = gpio_irq_unmask, - .set_type = gpio_irq_type, + .irq_mask = gpio_irq_mask, + .irq_unmask = gpio_irq_unmask, + .irq_set_type = gpio_irq_type, }; static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) { - struct pio_device *pio = get_irq_chip_data(irq); + struct pio_device *pio = irq_desc_get_chip_data(desc); unsigned gpio_irq; - gpio_irq = (unsigned) get_irq_data(irq); + gpio_irq = (unsigned) irq_get_handler_data(irq); for (;;) { u32 isr; - struct irq_desc *d; /* ack pending GPIO interrupts */ isr = pio_readl(pio, ISR) & pio_readl(pio, IMR); @@ -301,9 +300,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) isr &= ~(1 << i); i += gpio_irq; - d = &irq_desc[i]; - - d->handle_irq(i, d); + generic_handle_irq(i); } while (isr); } } @@ -313,16 +310,16 @@ gpio_irq_setup(struct pio_device *pio, int irq, int gpio_irq) { unsigned i; - set_irq_chip_data(irq, pio); - set_irq_data(irq, (void *) gpio_irq); + irq_set_chip_data(irq, pio); + irq_set_handler_data(irq, (void *)gpio_irq); for (i = 0; i < 32; i++, gpio_irq++) { - set_irq_chip_data(gpio_irq, pio); - set_irq_chip_and_handler(gpio_irq, &gpio_irqchip, - handle_simple_irq); + irq_set_chip_data(gpio_irq, pio); + irq_set_chip_and_handler(gpio_irq, &gpio_irqchip, + handle_simple_irq); } - set_irq_chained_handler(irq, gpio_irq_handler); + irq_set_chained_handler(irq, gpio_irq_handler); } /*--------------------------------------------------------------------------*/ diff --git a/arch/avr32/mach-at32ap/pm-at32ap700x.S b/arch/avr32/mach-at32ap/pm-at32ap700x.S index 17503b0ed6c..f868f4ce761 100644 --- a/arch/avr32/mach-at32ap/pm-at32ap700x.S +++ b/arch/avr32/mach-at32ap/pm-at32ap700x.S @@ -53,7 +53,7 @@ cpu_enter_idle: st.w r8[TI_flags], r9 unmask_interrupts sleep CPU_SLEEP_IDLE - .size cpu_idle_sleep, . - cpu_idle_sleep + .size cpu_enter_idle, . - cpu_enter_idle /* * Common return path for PM functions that don't run from diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index c09577ddc3c..8addb1220b4 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -31,6 +31,7 @@ config BLACKFIN select HAVE_OPROFILE select ARCH_WANT_OPTIONAL_GPIOLIB select HAVE_GENERIC_HARDIRQS + select GENERIC_ATOMIC64 select GENERIC_IRQ_PROBE select IRQ_PER_CPU if SMP @@ -690,13 +691,13 @@ endmenu menu "Blackfin Kernel Optimizations" - depends on !SMP comment "Memory Optimizations" config I_ENTRY_L1 bool "Locate interrupt entry code in L1 Memory" default y + depends on !SMP help If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. (less latency) @@ -704,6 +705,7 @@ config I_ENTRY_L1 config EXCPT_IRQ_SYSC_L1 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" default y + depends on !SMP help If enabled, the entire ASM lowlevel exception and interrupt entry code (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. @@ -712,6 +714,7 @@ config EXCPT_IRQ_SYSC_L1 config DO_IRQ_L1 bool "Locate frequently called do_irq dispatcher function in L1 Memory" default y + depends on !SMP help If enabled, the frequently called do_irq dispatcher function is linked into L1 instruction memory. (less latency) @@ -719,6 +722,7 @@ config DO_IRQ_L1 config CORE_TIMER_IRQ_L1 bool "Locate frequently called timer_interrupt() function in L1 Memory" default y + depends on !SMP help If enabled, the frequently called timer_interrupt() function is linked into L1 instruction memory. (less latency) @@ -726,6 +730,7 @@ config CORE_TIMER_IRQ_L1 config IDLE_L1 bool "Locate frequently idle function in L1 Memory" default y + depends on !SMP help If enabled, the frequently called idle function is linked into L1 instruction memory. (less latency) @@ -733,6 +738,7 @@ config IDLE_L1 config SCHEDULE_L1 bool "Locate kernel schedule function in L1 Memory" default y + depends on !SMP help If enabled, the frequently called kernel schedule is linked into L1 instruction memory. (less latency) @@ -740,6 +746,7 @@ config SCHEDULE_L1 config ARITHMETIC_OPS_L1 bool "Locate kernel owned arithmetic functions in L1 Memory" default y + depends on !SMP help If enabled, arithmetic functions are linked into L1 instruction memory. (less latency) @@ -747,6 +754,7 @@ config ARITHMETIC_OPS_L1 config ACCESS_OK_L1 bool "Locate access_ok function in L1 Memory" default y + depends on !SMP help If enabled, the access_ok function is linked into L1 instruction memory. (less latency) @@ -754,6 +762,7 @@ config ACCESS_OK_L1 config MEMSET_L1 bool "Locate memset function in L1 Memory" default y + depends on !SMP help If enabled, the memset function is linked into L1 instruction memory. (less latency) @@ -761,6 +770,7 @@ config MEMSET_L1 config MEMCPY_L1 bool "Locate memcpy function in L1 Memory" default y + depends on !SMP help If enabled, the memcpy function is linked into L1 instruction memory. (less latency) @@ -768,6 +778,7 @@ config MEMCPY_L1 config STRCMP_L1 bool "locate strcmp function in L1 Memory" default y + depends on !SMP help If enabled, the strcmp function is linked into L1 instruction memory (less latency). @@ -775,6 +786,7 @@ config STRCMP_L1 config STRNCMP_L1 bool "locate strncmp function in L1 Memory" default y + depends on !SMP help If enabled, the strncmp function is linked into L1 instruction memory (less latency). @@ -782,6 +794,7 @@ config STRNCMP_L1 config STRCPY_L1 bool "locate strcpy function in L1 Memory" default y + depends on !SMP help If enabled, the strcpy function is linked into L1 instruction memory (less latency). @@ -789,6 +802,7 @@ config STRCPY_L1 config STRNCPY_L1 bool "locate strncpy function in L1 Memory" default y + depends on !SMP help If enabled, the strncpy function is linked into L1 instruction memory (less latency). @@ -796,6 +810,7 @@ config STRNCPY_L1 config SYS_BFIN_SPINLOCK_L1 bool "Locate sys_bfin_spinlock function in L1 Memory" default y + depends on !SMP help If enabled, sys_bfin_spinlock function is linked into L1 instruction memory. (less latency) @@ -803,6 +818,7 @@ config SYS_BFIN_SPINLOCK_L1 config IP_CHECKSUM_L1 bool "Locate IP Checksum function in L1 Memory" default n + depends on !SMP help If enabled, the IP Checksum function is linked into L1 instruction memory. (less latency) @@ -811,7 +827,7 @@ config CACHELINE_ALIGNED_L1 bool "Locate cacheline_aligned data to L1 Data Memory" default y if !BF54x default n if BF54x - depends on !BF531 + depends on !SMP && !BF531 help If enabled, cacheline_aligned data is linked into L1 data memory. (less latency) @@ -819,7 +835,7 @@ config CACHELINE_ALIGNED_L1 config SYSCALL_TAB_L1 bool "Locate Syscall Table L1 Data Memory" default n - depends on !BF531 + depends on !SMP && !BF531 help If enabled, the Syscall LUT is linked into L1 data memory. (less latency) @@ -827,16 +843,16 @@ config SYSCALL_TAB_L1 config CPLB_SWITCH_TAB_L1 bool "Locate CPLB Switch Tables L1 Data Memory" default n - depends on !BF531 + depends on !SMP && !BF531 help If enabled, the CPLB Switch Tables are linked into L1 data memory. (less latency) -config CACHE_FLUSH_L1 - bool "Locate cache flush funcs in L1 Inst Memory" +config ICACHE_FLUSH_L1 + bool "Locate icache flush funcs in L1 Inst Memory" default y help - If enabled, the Blackfin cache flushing functions are linked + If enabled, the Blackfin icache flushing functions are linked into L1 instruction memory. Note that this might be required to address anomalies, but @@ -844,9 +860,18 @@ config CACHE_FLUSH_L1 If you are using a processor affected by an anomaly, the build system will double check for you and prevent it. +config DCACHE_FLUSH_L1 + bool "Locate dcache flush funcs in L1 Inst Memory" + default y + depends on !SMP + help + If enabled, the Blackfin dcache flushing functions are linked + into L1 instruction memory. + config APP_STACK_L1 bool "Support locating application stack in L1 Scratch Memory" default y + depends on !SMP help If enabled the application stack can be located in L1 scratch memory (less latency). @@ -856,7 +881,7 @@ config APP_STACK_L1 config EXCEPTION_L1_SCRATCH bool "Locate exception stack in L1 Scratch Memory" default n - depends on !APP_STACK_L1 + depends on !SMP && !APP_STACK_L1 help Whenever an exception occurs, use the L1 Scratch memory for stack storage. You cannot place the stacks of FLAT binaries @@ -868,6 +893,7 @@ comment "Speed Optimizations" config BFIN_INS_LOWOVERHEAD bool "ins[bwl] low overhead, higher interrupt latency" default y + depends on !SMP help Reads on the Blackfin are speculative. In Blackfin terms, this means they can be interrupted at any time (even after they have been issued diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug index acb83799a21..2641731f24c 100644 --- a/arch/blackfin/Kconfig.debug +++ b/arch/blackfin/Kconfig.debug @@ -59,7 +59,7 @@ config EXACT_HWERR be reported multiple cycles after the error happens. This delay can cause the wrong application, or even the kernel to receive a signal to be killed. If you are getting HW errors in your system, - try turning this on to ensure they are at least comming from the + try turning this on to ensure they are at least coming from the proper thread. On production systems, it is safe (and a small optimization) to say N. diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig index db8d38a12a9..5edcb58d6f7 100644 --- a/arch/blackfin/configs/BF518F-EZBRD_defconfig +++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig @@ -115,6 +115,7 @@ CONFIG_DEBUG_DOUBLEFAULT=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y CONFIG_EARLY_PRINTK=y CONFIG_CPLB_INFO=y +CONFIG_BFIN_PSEUDODBG_INSNS=y CONFIG_CRYPTO=y # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRC_CCITT=m diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig index 3e50d7857c2..2e549572d4f 100644 --- a/arch/blackfin/configs/BF526-EZBRD_defconfig +++ b/arch/blackfin/configs/BF526-EZBRD_defconfig @@ -153,6 +153,7 @@ CONFIG_DEBUG_DOUBLEFAULT=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y CONFIG_EARLY_PRINTK=y CONFIG_CPLB_INFO=y +CONFIG_BFIN_PSEUDODBG_INSNS=y CONFIG_CRYPTO=y # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRC_CCITT=m diff --git a/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig b/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig index 362f59dd522..ad0881ba30a 100644 --- a/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig +++ b/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig @@ -46,7 +46,6 @@ CONFIG_UNIX=y # CONFIG_WIRELESS is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y -# CONFIG_MISC_DEVICES is not set # CONFIG_INPUT_MOUSEDEV is not set CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_KEYBOARD is not set diff --git a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig index 023ff0df269..95cf2ba9de1 100644 --- a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig +++ b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig @@ -183,5 +183,6 @@ CONFIG_DEBUG_DOUBLEFAULT=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y CONFIG_EARLY_PRINTK=y CONFIG_CPLB_INFO=y +CONFIG_BFIN_PSEUDODBG_INSNS=y CONFIG_CRYPTO=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig index 4e5a121b3c5..8be8e33fac5 100644 --- a/arch/blackfin/configs/BF527-EZKIT_defconfig +++ b/arch/blackfin/configs/BF527-EZKIT_defconfig @@ -175,5 +175,6 @@ CONFIG_DEBUG_DOUBLEFAULT=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y CONFIG_EARLY_PRINTK=y CONFIG_CPLB_INFO=y +CONFIG_BFIN_PSEUDODBG_INSNS=y CONFIG_CRYPTO=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig index 9f8fc84e4ac..a7eb54bf308 100644 --- a/arch/blackfin/configs/BF533-EZKIT_defconfig +++ b/arch/blackfin/configs/BF533-EZKIT_defconfig @@ -108,5 +108,6 @@ CONFIG_DEBUG_DOUBLEFAULT=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y CONFIG_EARLY_PRINTK=y CONFIG_CPLB_INFO=y +CONFIG_BFIN_PSEUDODBG_INSNS=y CONFIG_CRYPTO=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig index ccc432b722a..0aafde6c8c2 100644 --- a/arch/blackfin/configs/BF533-STAMP_defconfig +++ b/arch/blackfin/configs/BF533-STAMP_defconfig @@ -122,5 +122,6 @@ CONFIG_DEBUG_DOUBLEFAULT=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y CONFIG_EARLY_PRINTK=y CONFIG_CPLB_INFO=y +CONFIG_BFIN_PSEUDODBG_INSNS=y CONFIG_CRYPTO=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig index 566695472a8..c9077fb5813 100644 --- a/arch/blackfin/configs/BF537-STAMP_defconfig +++ b/arch/blackfin/configs/BF537-STAMP_defconfig @@ -133,5 +133,6 @@ CONFIG_DEBUG_DOUBLEFAULT=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y CONFIG_EARLY_PRINTK=y CONFIG_CPLB_INFO=y +CONFIG_BFIN_PSEUDODBG_INSNS=y CONFIG_CRYPTO=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig index ac22124ccb6..580bf4296a1 100644 --- a/arch/blackfin/configs/BF538-EZKIT_defconfig +++ b/arch/blackfin/configs/BF538-EZKIT_defconfig @@ -70,7 +70,6 @@ CONFIG_MTD_ROM=m CONFIG_MTD_PHYSMAP=m CONFIG_MTD_NAND=m CONFIG_BLK_DEV_RAM=y -# CONFIG_MISC_DEVICES is not set CONFIG_NETDEVICES=y CONFIG_PHYLIB=y CONFIG_SMSC_PHY=y @@ -131,5 +130,6 @@ CONFIG_DEBUG_DOUBLEFAULT=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y CONFIG_EARLY_PRINTK=y CONFIG_CPLB_INFO=y +CONFIG_BFIN_PSEUDODBG_INSNS=y CONFIG_CRYPTO=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig index 944404b6ff0..56151b5dbc4 100644 --- a/arch/blackfin/configs/BF548-EZKIT_defconfig +++ b/arch/blackfin/configs/BF548-EZKIT_defconfig @@ -205,5 +205,6 @@ CONFIG_DEBUG_DOUBLEFAULT=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y CONFIG_EARLY_PRINTK=y CONFIG_CPLB_INFO=y +CONFIG_BFIN_PSEUDODBG_INSNS=y CONFIG_CRYPTO=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/BF561-ACVILON_defconfig b/arch/blackfin/configs/BF561-ACVILON_defconfig index b7c8451f26a..77a27e31d6d 100644 --- a/arch/blackfin/configs/BF561-ACVILON_defconfig +++ b/arch/blackfin/configs/BF561-ACVILON_defconfig @@ -63,7 +63,6 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=2 CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_MISC_DEVICES is not set CONFIG_SCSI=y # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y diff --git a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig index 7e67ba31e99..f5ed34e12e0 100644 --- a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig +++ b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig @@ -109,5 +109,6 @@ CONFIG_DEBUG_DOUBLEFAULT=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y CONFIG_EARLY_PRINTK=y CONFIG_CPLB_INFO=y +CONFIG_BFIN_PSEUDODBG_INSNS=y CONFIG_CRYPTO=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig index 141e5933e1a..1c0a82a1059 100644 --- a/arch/blackfin/configs/BF561-EZKIT_defconfig +++ b/arch/blackfin/configs/BF561-EZKIT_defconfig @@ -111,5 +111,6 @@ CONFIG_DEBUG_DOUBLEFAULT=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y CONFIG_EARLY_PRINTK=y CONFIG_CPLB_INFO=y +CONFIG_BFIN_PSEUDODBG_INSNS=y CONFIG_CRYPTO=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig index 97ebe09a737..85014319672 100644 --- a/arch/blackfin/configs/BlackStamp_defconfig +++ b/arch/blackfin/configs/BlackStamp_defconfig @@ -58,6 +58,7 @@ CONFIG_MTD_M25P80=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=y CONFIG_BLK_DEV_RAM=y +CONFIG_MISC_DEVICES=y CONFIG_EEPROM_AT25=y CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig index c2457543e58..dbf750cd2db 100644 --- a/arch/blackfin/configs/CM-BF527_defconfig +++ b/arch/blackfin/configs/CM-BF527_defconfig @@ -64,7 +64,6 @@ CONFIG_MTD_ROM=m CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_GPIO_ADDR=y CONFIG_BLK_DEV_RAM=y -# CONFIG_MISC_DEVICES is not set CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y # CONFIG_SCSI_LOWLEVEL is not set diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig index baf1c1573e5..07ffbdae34e 100644 --- a/arch/blackfin/configs/CM-BF533_defconfig +++ b/arch/blackfin/configs/CM-BF533_defconfig @@ -44,7 +44,6 @@ CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_RAM=y CONFIG_MTD_PHYSMAP=y -# CONFIG_MISC_DEVICES is not set CONFIG_NETDEVICES=y # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig index df267588efe..31d954216c0 100644 --- a/arch/blackfin/configs/CM-BF548_defconfig +++ b/arch/blackfin/configs/CM-BF548_defconfig @@ -63,7 +63,6 @@ CONFIG_MTD_RAM=y CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_PHYSMAP=y CONFIG_BLK_DEV_RAM=y -# CONFIG_MISC_DEVICES is not set CONFIG_SCSI=m CONFIG_BLK_DEV_SD=m # CONFIG_SCSI_LOWLEVEL is not set diff --git a/arch/blackfin/configs/DNP5370_defconfig b/arch/blackfin/configs/DNP5370_defconfig index f50313657f3..b192acfae38 100644 --- a/arch/blackfin/configs/DNP5370_defconfig +++ b/arch/blackfin/configs/DNP5370_defconfig @@ -55,7 +55,6 @@ CONFIG_MTD_NAND=y CONFIG_MTD_NAND_PLATFORM=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y -# CONFIG_MISC_DEVICES is not set CONFIG_NETDEVICES=y CONFIG_DAVICOM_PHY=y CONFIG_NET_ETHERNET=y diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig index 7450127b645..06e9f497fae 100644 --- a/arch/blackfin/configs/H8606_defconfig +++ b/arch/blackfin/configs/H8606_defconfig @@ -45,6 +45,7 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_M25P80=y # CONFIG_M25PXX_USE_FAST_READ is not set CONFIG_BLK_DEV_RAM=y +CONFIG_MISC_DEVICES=y CONFIG_EEPROM_AT25=y CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig index 853809510ee..12e66cd7cda 100644 --- a/arch/blackfin/configs/SRV1_defconfig +++ b/arch/blackfin/configs/SRV1_defconfig @@ -48,6 +48,7 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_UCLINUX=y CONFIG_MTD_NAND=m CONFIG_BLK_DEV_RAM=y +CONFIG_MISC_DEVICES=y CONFIG_EEPROM_AT25=m CONFIG_NETDEVICES=y # CONFIG_NETDEV_1000 is not set diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h index d27c6274247..e4850895716 100644 --- a/arch/blackfin/include/asm/atomic.h +++ b/arch/blackfin/include/asm/atomic.h @@ -121,4 +121,6 @@ static inline int atomic_test_mask(int mask, atomic_t *v) #endif +#include <asm-generic/atomic64.h> + #endif diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h index 29f4fd88617..8a0fed16058 100644 --- a/arch/blackfin/include/asm/bitops.h +++ b/arch/blackfin/include/asm/bitops.h @@ -25,9 +25,7 @@ #include <asm-generic/bitops/const_hweight.h> #include <asm-generic/bitops/lock.h> -#include <asm-generic/bitops/ext2-non-atomic.h> #include <asm-generic/bitops/ext2-atomic.h> -#include <asm-generic/bitops/minix.h> #ifndef CONFIG_SMP #include <linux/irqflags.h> @@ -114,6 +112,9 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr) #endif /* CONFIG_SMP */ +/* Needs to be after test_bit and friends */ +#include <asm-generic/bitops/le.h> + /* * hweightN: returns the hamming weight (i.e. the number * of bits set) of a N-bit word diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h index e3f0f4c4981..7600fe0696a 100644 --- a/arch/blackfin/include/asm/def_LPBlackfin.h +++ b/arch/blackfin/include/asm/def_LPBlackfin.h @@ -58,14 +58,26 @@ ({ BUG(); 0; }); \ }) #define bfin_write(addr, val) \ -({ \ +do { \ switch (sizeof(*(addr))) { \ case 1: bfin_write8(addr, val); break; \ case 2: bfin_write16(addr, val); break; \ case 4: bfin_write32(addr, val); break; \ default: BUG(); \ } \ -}) +} while (0) + +#define bfin_write_or(addr, bits) \ +do { \ + void *__addr = (void *)(addr); \ + bfin_write(__addr, bfin_read(__addr) | (bits)); \ +} while (0) + +#define bfin_write_and(addr, bits) \ +do { \ + void *__addr = (void *)(addr); \ + bfin_write(__addr, bfin_read(__addr) & (bits)); \ +} while (0) #endif /* __ASSEMBLY__ */ diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h index 3047120cfcf..edf2a2ad518 100644 --- a/arch/blackfin/include/asm/dpmc.h +++ b/arch/blackfin/include/asm/dpmc.h @@ -125,6 +125,9 @@ void unset_dram_srfs(void); #define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16)) +#ifdef CONFIG_CPU_FREQ +#define CPUFREQ_CPU 0 +#endif struct bfin_dpmc_platform_data { const unsigned int *tuple_tab; unsigned short tabsize; diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h index 40f94a704c0..9e0cc0e2534 100644 --- a/arch/blackfin/include/asm/ipipe.h +++ b/arch/blackfin/include/asm/ipipe.h @@ -34,11 +34,12 @@ #include <asm/bitops.h> #include <asm/atomic.h> #include <asm/traps.h> +#include <asm/bitsperlong.h> -#define IPIPE_ARCH_STRING "1.12-00" +#define IPIPE_ARCH_STRING "1.16-01" #define IPIPE_MAJOR_NUMBER 1 -#define IPIPE_MINOR_NUMBER 12 -#define IPIPE_PATCH_NUMBER 0 +#define IPIPE_MINOR_NUMBER 16 +#define IPIPE_PATCH_NUMBER 1 #ifdef CONFIG_SMP #error "I-pipe/blackfin: SMP not implemented" @@ -55,25 +56,19 @@ do { \ #define task_hijacked(p) \ ({ \ int __x__ = __ipipe_root_domain_p; \ - __clear_bit(IPIPE_SYNC_FLAG, &ipipe_root_cpudom_var(status)); \ if (__x__) \ - hard_local_irq_enable(); \ + hard_local_irq_enable(); \ !__x__; \ }) struct ipipe_domain; struct ipipe_sysinfo { - - int ncpus; /* Number of CPUs on board */ - u64 cpufreq; /* CPU frequency (in Hz) */ - - /* Arch-dependent block */ - - struct { - unsigned tmirq; /* Timer tick IRQ */ - u64 tmfreq; /* Timer frequency */ - } archdep; + int sys_nr_cpus; /* Number of CPUs on board */ + int sys_hrtimer_irq; /* hrtimer device IRQ */ + u64 sys_hrtimer_freq; /* hrtimer device frequency */ + u64 sys_hrclock_freq; /* hrclock device frequency */ + u64 sys_cpu_freq; /* CPU frequency (Hz) */ }; #define ipipe_read_tsc(t) \ @@ -115,9 +110,19 @@ void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq); -#define __ipipe_enable_irq(irq) (irq_desc[irq].chip->unmask(irq)) +#define __ipipe_enable_irq(irq) \ + do { \ + struct irq_desc *desc = irq_to_desc(irq); \ + struct irq_chip *chip = get_irq_desc_chip(desc); \ + chip->irq_unmask(&desc->irq_data); \ + } while (0) -#define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq)) +#define __ipipe_disable_irq(irq) \ + do { \ + struct irq_desc *desc = irq_to_desc(irq); \ + struct irq_chip *chip = get_irq_desc_chip(desc); \ + chip->irq_mask(&desc->irq_data); \ + } while (0) static inline int __ipipe_check_tickdev(const char *devname) { @@ -128,12 +133,11 @@ void __ipipe_enable_pipeline(void); #define __ipipe_hook_critical_ipi(ipd) do { } while (0) -#define __ipipe_sync_pipeline ___ipipe_sync_pipeline -void ___ipipe_sync_pipeline(unsigned long syncmask); +void ___ipipe_sync_pipeline(void); void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs); -int __ipipe_get_irq_priority(unsigned irq); +int __ipipe_get_irq_priority(unsigned int irq); void __ipipe_serial_debug(const char *fmt, ...); @@ -152,7 +156,10 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul) return ffs(ul) - 1; } -#define __ipipe_run_irqtail() /* Must be a macro */ \ +#define __ipipe_do_root_xirq(ipd, irq) \ + ((ipd)->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs))) + +#define __ipipe_run_irqtail(irq) /* Must be a macro */ \ do { \ unsigned long __pending; \ CSYNC(); \ @@ -164,42 +171,8 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul) } \ } while (0) -#define __ipipe_run_isr(ipd, irq) \ - do { \ - if (!__ipipe_pipeline_head_p(ipd)) \ - hard_local_irq_enable(); \ - if (ipd == ipipe_root_domain) { \ - if (unlikely(ipipe_virtual_irq_p(irq))) { \ - irq_enter(); \ - ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \ - irq_exit(); \ - } else \ - ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \ - } else { \ - __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ - ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \ - /* Attempt to exit the outer interrupt level before \ - * starting the deferred IRQ processing. */ \ - __ipipe_run_irqtail(); \ - __set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ - } \ - hard_local_irq_disable(); \ - } while (0) - #define __ipipe_syscall_watched_p(p, sc) \ - (((p)->flags & PF_EVNOTIFY) || (unsigned long)sc >= NR_syscalls) - -void ipipe_init_irq_threads(void); - -int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); - -#ifdef CONFIG_TICKSOURCE_CORETMR -#define IRQ_SYSTMR IRQ_CORETMR -#define IRQ_PRIOTMR IRQ_CORETMR -#else -#define IRQ_SYSTMR IRQ_TIMER0 -#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 -#endif + (ipipe_notifier_enabled_p(p) || (unsigned long)sc >= NR_syscalls) #ifdef CONFIG_BF561 #define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val) @@ -219,11 +192,11 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); #define task_hijacked(p) 0 #define ipipe_trap_notify(t, r) 0 +#define __ipipe_root_tick_p(regs) 1 -#define ipipe_init_irq_threads() do { } while (0) -#define ipipe_start_irq_thread(irq, desc) 0 +#endif /* !CONFIG_IPIPE */ -#ifndef CONFIG_TICKSOURCE_GPTMR0 +#ifdef CONFIG_TICKSOURCE_CORETMR #define IRQ_SYSTMR IRQ_CORETMR #define IRQ_PRIOTMR IRQ_CORETMR #else @@ -231,10 +204,6 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); #define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 #endif -#define __ipipe_root_tick_p(regs) 1 - -#endif /* !CONFIG_IPIPE */ - #define ipipe_update_tick_evtdev(evtdev) do { } while (0) #endif /* !__ASM_BLACKFIN_IPIPE_H */ diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h index 00409201d9e..84a4ffd3674 100644 --- a/arch/blackfin/include/asm/ipipe_base.h +++ b/arch/blackfin/include/asm/ipipe_base.h @@ -24,8 +24,10 @@ #ifdef CONFIG_IPIPE +#include <asm/bitsperlong.h> +#include <mach/irq.h> + #define IPIPE_NR_XIRQS NR_IRQS -#define IPIPE_IRQ_ISHIFT 5 /* 2^5 for 32bits arch. */ /* Blackfin-specific, per-cpu pipeline status */ #define IPIPE_SYNCDEFER_FLAG 15 @@ -42,11 +44,14 @@ #define IPIPE_EVENT_INIT (IPIPE_FIRST_EVENT + 4) #define IPIPE_EVENT_EXIT (IPIPE_FIRST_EVENT + 5) #define IPIPE_EVENT_CLEANUP (IPIPE_FIRST_EVENT + 6) -#define IPIPE_LAST_EVENT IPIPE_EVENT_CLEANUP +#define IPIPE_EVENT_RETURN (IPIPE_FIRST_EVENT + 7) +#define IPIPE_LAST_EVENT IPIPE_EVENT_RETURN #define IPIPE_NR_EVENTS (IPIPE_LAST_EVENT + 1) #define IPIPE_TIMER_IRQ IRQ_CORETMR +#define __IPIPE_FEATURE_SYSINFO_V2 1 + #ifndef __ASSEMBLY__ extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ @@ -63,6 +68,8 @@ void __ipipe_unlock_root(void); #endif /* !__ASSEMBLY__ */ +#define __IPIPE_FEATURE_SYSINFO_V2 1 + #endif /* CONFIG_IPIPE */ #endif /* !__ASM_BLACKFIN_IPIPE_BASE_H */ diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h index 3365cb97f53..b4bbb75a9e1 100644 --- a/arch/blackfin/include/asm/irqflags.h +++ b/arch/blackfin/include/asm/irqflags.h @@ -89,15 +89,33 @@ static inline void __hard_local_irq_restore(unsigned long flags) #ifdef CONFIG_IPIPE #include <linux/compiler.h> -#include <linux/ipipe_base.h> #include <linux/ipipe_trace.h> +/* + * Way too many inter-deps between low-level headers in this port, so + * we redeclare the required bits we cannot pick from + * <asm/ipipe_base.h> to prevent circular dependencies. + */ +void __ipipe_stall_root(void); +void __ipipe_unstall_root(void); +unsigned long __ipipe_test_root(void); +unsigned long __ipipe_test_and_stall_root(void); +void __ipipe_restore_root(unsigned long flags); + +#ifdef CONFIG_IPIPE_DEBUG_CONTEXT +struct ipipe_domain; +extern struct ipipe_domain ipipe_root; +void ipipe_check_context(struct ipipe_domain *ipd); +#define __check_irqop_context(ipd) ipipe_check_context(&ipipe_root) +#else /* !CONFIG_IPIPE_DEBUG_CONTEXT */ +#define __check_irqop_context(ipd) do { } while (0) +#endif /* !CONFIG_IPIPE_DEBUG_CONTEXT */ /* * Interrupt pipe interface to linux/irqflags.h. */ static inline void arch_local_irq_disable(void) { - ipipe_check_context(ipipe_root_domain); + __check_irqop_context(); __ipipe_stall_root(); barrier(); } @@ -105,7 +123,7 @@ static inline void arch_local_irq_disable(void) static inline void arch_local_irq_enable(void) { barrier(); - ipipe_check_context(ipipe_root_domain); + __check_irqop_context(); __ipipe_unstall_root(); } @@ -119,16 +137,21 @@ static inline int arch_irqs_disabled_flags(unsigned long flags) return flags == bfin_no_irqs; } -static inline void arch_local_irq_save_ptr(unsigned long *_flags) +static inline unsigned long arch_local_irq_save(void) { - x = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags; + unsigned long flags; + + __check_irqop_context(); + flags = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags; barrier(); + + return flags; } -static inline unsigned long arch_local_irq_save(void) +static inline void arch_local_irq_restore(unsigned long flags) { - ipipe_check_context(ipipe_root_domain); - return __hard_local_irq_save(); + __check_irqop_context(); + __ipipe_restore_root(flags == bfin_no_irqs); } static inline unsigned long arch_mangle_irq_bits(int virt, unsigned long real) @@ -192,7 +215,10 @@ static inline void hard_local_irq_restore(unsigned long flags) # define hard_local_irq_restore(flags) __hard_local_irq_restore(flags) #endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */ -#else /* CONFIG_IPIPE */ +#define hard_local_irq_save_cond() hard_local_irq_save() +#define hard_local_irq_restore_cond(flags) hard_local_irq_restore(flags) + +#else /* !CONFIG_IPIPE */ /* * Direct interface to linux/irqflags.h. @@ -212,7 +238,48 @@ static inline void hard_local_irq_restore(unsigned long flags) #define hard_local_irq_restore(flags) __hard_local_irq_restore(flags) #define hard_local_irq_enable() __hard_local_irq_enable() #define hard_local_irq_disable() __hard_local_irq_disable() - +#define hard_local_irq_save_cond() hard_local_save_flags() +#define hard_local_irq_restore_cond(flags) do { (void)(flags); } while (0) #endif /* !CONFIG_IPIPE */ + +#ifdef CONFIG_SMP +#define hard_local_irq_save_smp() hard_local_irq_save() +#define hard_local_irq_restore_smp(flags) hard_local_irq_restore(flags) +#else +#define hard_local_irq_save_smp() hard_local_save_flags() +#define hard_local_irq_restore_smp(flags) do { (void)(flags); } while (0) +#endif + +/* + * Remap the arch-neutral IRQ state manipulation macros to the + * blackfin-specific hard_local_irq_* API. + */ +#define local_irq_save_hw(flags) \ + do { \ + (flags) = hard_local_irq_save(); \ + } while (0) +#define local_irq_restore_hw(flags) \ + do { \ + hard_local_irq_restore(flags); \ + } while (0) +#define local_irq_disable_hw() \ + do { \ + hard_local_irq_disable(); \ + } while (0) +#define local_irq_enable_hw() \ + do { \ + hard_local_irq_enable(); \ + } while (0) +#define local_irq_save_hw_notrace(flags) \ + do { \ + (flags) = __hard_local_irq_save(); \ + } while (0) +#define local_irq_restore_hw_notrace(flags) \ + do { \ + __hard_local_irq_restore(flags); \ + } while (0) + +#define irqs_disabled_hw() hard_irqs_disabled() + #endif diff --git a/arch/blackfin/include/asm/smp.h b/arch/blackfin/include/asm/smp.h index f5b53796711..af6c0aa79ba 100644 --- a/arch/blackfin/include/asm/smp.h +++ b/arch/blackfin/include/asm/smp.h @@ -17,7 +17,12 @@ #define raw_smp_processor_id() blackfin_core_id() -extern char coreb_trampoline_start, coreb_trampoline_end; +extern void bfin_relocate_coreb_l1_mem(void); + +#if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1) +asmlinkage void blackfin_icache_flush_range_l1(unsigned long *ptr); +extern unsigned long blackfin_iflush_l1_entry[NR_CPUS]; +#endif struct corelock_slot { int lock; @@ -34,7 +39,7 @@ extern unsigned long dcache_invld_count[NR_CPUS]; void smp_icache_flush_range_others(unsigned long start, unsigned long end); #ifdef CONFIG_HOTPLUG_CPU -void coreb_sleep(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); +void coreb_die(void); void cpu_die(void); void platform_cpu_die(void); int __cpu_disable(void); diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h index 19e2c7c3e63..44bd0cced72 100644 --- a/arch/blackfin/include/asm/system.h +++ b/arch/blackfin/include/asm/system.h @@ -19,11 +19,11 @@ * Force strict CPU ordering. */ #define nop() __asm__ __volatile__ ("nop;\n\t" : : ) -#define mb() __asm__ __volatile__ ("" : : : "memory") -#define rmb() __asm__ __volatile__ ("" : : : "memory") -#define wmb() __asm__ __volatile__ ("" : : : "memory") -#define set_mb(var, value) do { (void) xchg(&var, value); } while (0) -#define read_barrier_depends() do { } while(0) +#define smp_mb() mb() +#define smp_rmb() rmb() +#define smp_wmb() wmb() +#define set_mb(var, value) do { var = value; mb(); } while (0) +#define smp_read_barrier_depends() read_barrier_depends() #ifdef CONFIG_SMP asmlinkage unsigned long __raw_xchg_1_asm(volatile void *ptr, unsigned long value); @@ -37,16 +37,16 @@ asmlinkage unsigned long __raw_cmpxchg_4_asm(volatile void *ptr, unsigned long new, unsigned long old); #ifdef __ARCH_SYNC_CORE_DCACHE -# define smp_mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0) -# define smp_rmb() do { barrier(); smp_check_barrier(); } while (0) -# define smp_wmb() do { barrier(); smp_mark_barrier(); } while (0) -#define smp_read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0) - +/* Force Core data cache coherence */ +# define mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0) +# define rmb() do { barrier(); smp_check_barrier(); } while (0) +# define wmb() do { barrier(); smp_mark_barrier(); } while (0) +# define read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0) #else -# define smp_mb() barrier() -# define smp_rmb() barrier() -# define smp_wmb() barrier() -#define smp_read_barrier_depends() barrier() +# define mb() barrier() +# define rmb() barrier() +# define wmb() barrier() +# define read_barrier_depends() do { } while (0) #endif static inline unsigned long __xchg(unsigned long x, volatile void *ptr, @@ -99,10 +99,10 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, #else /* !CONFIG_SMP */ -#define smp_mb() barrier() -#define smp_rmb() barrier() -#define smp_wmb() barrier() -#define smp_read_barrier_depends() do { } while(0) +#define mb() barrier() +#define rmb() barrier() +#define wmb() barrier() +#define read_barrier_depends() do { } while (0) struct __xchg_dummy { unsigned long a[100]; diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h index 9fe0da612c0..70c4e511cae 100644 --- a/arch/blackfin/include/asm/traps.h +++ b/arch/blackfin/include/asm/traps.h @@ -57,7 +57,7 @@ #define HWC_x3(level) \ "External Memory Addressing Error\n" #define EXC_0x04(level) \ - "Unimplmented exception occured\n" \ + "Unimplmented exception occurred\n" \ level " - Maybe you forgot to install a custom exception handler?\n" #define HWC_x12(level) \ "Performance Monitor Overflow\n" diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h index 928ae975b87..ff9a9f35d50 100644 --- a/arch/blackfin/include/asm/unistd.h +++ b/arch/blackfin/include/asm/unistd.h @@ -393,8 +393,12 @@ #define __NR_fanotify_mark 372 #define __NR_prlimit64 373 #define __NR_cacheflush 374 +#define __NR_name_to_handle_at 375 +#define __NR_open_by_handle_at 376 +#define __NR_clock_adjtime 377 +#define __NR_syncfs 378 -#define __NR_syscall 375 +#define __NR_syscall 379 #define NR_syscalls __NR_syscall /* Old optional stuff no one actually uses */ diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c index 1e485dfdc9f..6ce8dce753c 100644 --- a/arch/blackfin/kernel/bfin_dma_5xx.c +++ b/arch/blackfin/kernel/bfin_dma_5xx.c @@ -84,6 +84,24 @@ static int __init proc_dma_init(void) late_initcall(proc_dma_init); #endif +static void set_dma_peripheral_map(unsigned int channel, const char *device_id) +{ +#ifdef CONFIG_BF54x + unsigned int per_map; + + switch (channel) { + case CH_UART2_RX: per_map = 0xC << 12; break; + case CH_UART2_TX: per_map = 0xD << 12; break; + case CH_UART3_RX: per_map = 0xE << 12; break; + case CH_UART3_TX: per_map = 0xF << 12; break; + default: return; + } + + if (strncmp(device_id, "BFIN_UART", 9) == 0) + dma_ch[channel].regs->peripheral_map = per_map; +#endif +} + /** * request_dma - request a DMA channel * @@ -111,19 +129,7 @@ int request_dma(unsigned int channel, const char *device_id) return -EBUSY; } -#ifdef CONFIG_BF54x - if (channel >= CH_UART2_RX && channel <= CH_UART3_TX) { - unsigned int per_map; - per_map = dma_ch[channel].regs->peripheral_map & 0xFFF; - if (strncmp(device_id, "BFIN_UART", 9) == 0) - dma_ch[channel].regs->peripheral_map = per_map | - ((channel - CH_UART2_RX + 0xC)<<12); - else - dma_ch[channel].regs->peripheral_map = per_map | - ((channel - CH_UART2_RX + 0x6)<<12); - } -#endif - + set_dma_peripheral_map(channel, device_id); dma_ch[channel].device_id = device_id; dma_ch[channel].irq = 0; diff --git a/arch/blackfin/kernel/gptimers.c b/arch/blackfin/kernel/gptimers.c index cdbe075de1d..8b81dc04488 100644 --- a/arch/blackfin/kernel/gptimers.c +++ b/arch/blackfin/kernel/gptimers.c @@ -268,7 +268,7 @@ void disable_gptimers(uint16_t mask) _disable_gptimers(mask); for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i) if (mask & (1 << i)) - group_regs[BFIN_TIMER_OCTET(i)]->status |= trun_mask[i]; + group_regs[BFIN_TIMER_OCTET(i)]->status = trun_mask[i]; SSYNC(); } EXPORT_SYMBOL(disable_gptimers); diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c index 3b1da4aff2a..f37019c847c 100644 --- a/arch/blackfin/kernel/ipipe.c +++ b/arch/blackfin/kernel/ipipe.c @@ -154,7 +154,7 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) * pending for it. */ if (test_bit(IPIPE_AHEAD_FLAG, &this_domain->flags) && - ipipe_head_cpudom_var(irqpend_himask) == 0) + !__ipipe_ipending_p(ipipe_head_cpudom_ptr())) goto out; __ipipe_walk_pipeline(head); @@ -185,25 +185,21 @@ void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq) } EXPORT_SYMBOL(__ipipe_disable_irqdesc); -int __ipipe_syscall_root(struct pt_regs *regs) +asmlinkage int __ipipe_syscall_root(struct pt_regs *regs) { struct ipipe_percpu_domain_data *p; - unsigned long flags; + void (*hook)(void); int ret; + WARN_ON_ONCE(irqs_disabled_hw()); + /* - * We need to run the IRQ tail hook whenever we don't - * propagate a syscall to higher domains, because we know that - * important operations might be pending there (e.g. Xenomai - * deferred rescheduling). + * We need to run the IRQ tail hook each time we intercept a + * syscall, because we know that important operations might be + * pending there (e.g. Xenomai deferred rescheduling). */ - - if (regs->orig_p0 < NR_syscalls) { - void (*hook)(void) = (void (*)(void))__ipipe_irq_tail_hook; - hook(); - if ((current->flags & PF_EVNOTIFY) == 0) - return 0; - } + hook = (__typeof__(hook))__ipipe_irq_tail_hook; + hook(); /* * This routine either returns: @@ -214,51 +210,47 @@ int __ipipe_syscall_root(struct pt_regs *regs) * tail work has to be performed (for handling signals etc). */ - if (!__ipipe_event_monitored_p(IPIPE_EVENT_SYSCALL)) + if (!__ipipe_syscall_watched_p(current, regs->orig_p0) || + !__ipipe_event_monitored_p(IPIPE_EVENT_SYSCALL)) return 0; ret = __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL, regs); - flags = hard_local_irq_save(); + hard_local_irq_disable(); - if (!__ipipe_root_domain_p) { - hard_local_irq_restore(flags); - return 1; + /* + * This is the end of the syscall path, so we may + * safely assume a valid Linux task stack here. + */ + if (current->ipipe_flags & PF_EVTRET) { + current->ipipe_flags &= ~PF_EVTRET; + __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs); } - p = ipipe_root_cpudom_ptr(); - if ((p->irqpend_himask & IPIPE_IRQMASK_VIRT) != 0) - __ipipe_sync_pipeline(IPIPE_IRQMASK_VIRT); + if (!__ipipe_root_domain_p) + ret = -1; + else { + p = ipipe_root_cpudom_ptr(); + if (__ipipe_ipending_p(p)) + __ipipe_sync_pipeline(); + } - hard_local_irq_restore(flags); + hard_local_irq_enable(); return -ret; } -unsigned long ipipe_critical_enter(void (*syncfn) (void)) -{ - unsigned long flags; - - flags = hard_local_irq_save(); - - return flags; -} - -void ipipe_critical_exit(unsigned long flags) -{ - hard_local_irq_restore(flags); -} - static void __ipipe_no_irqtail(void) { } int ipipe_get_sysinfo(struct ipipe_sysinfo *info) { - info->ncpus = num_online_cpus(); - info->cpufreq = ipipe_cpu_freq(); - info->archdep.tmirq = IPIPE_TIMER_IRQ; - info->archdep.tmfreq = info->cpufreq; + info->sys_nr_cpus = num_online_cpus(); + info->sys_cpu_freq = ipipe_cpu_freq(); + info->sys_hrtimer_irq = IPIPE_TIMER_IRQ; + info->sys_hrtimer_freq = __ipipe_core_clock; + info->sys_hrclock_freq = __ipipe_core_clock; return 0; } @@ -289,6 +281,7 @@ int ipipe_trigger_irq(unsigned irq) asmlinkage void __ipipe_sync_root(void) { void (*irq_tail_hook)(void) = (void (*)(void))__ipipe_irq_tail_hook; + struct ipipe_percpu_domain_data *p; unsigned long flags; BUG_ON(irqs_disabled()); @@ -300,19 +293,20 @@ asmlinkage void __ipipe_sync_root(void) clear_thread_flag(TIF_IRQ_SYNC); - if (ipipe_root_cpudom_var(irqpend_himask) != 0) - __ipipe_sync_pipeline(IPIPE_IRQMASK_ANY); + p = ipipe_root_cpudom_ptr(); + if (__ipipe_ipending_p(p)) + __ipipe_sync_pipeline(); hard_local_irq_restore(flags); } -void ___ipipe_sync_pipeline(unsigned long syncmask) +void ___ipipe_sync_pipeline(void) { if (__ipipe_root_domain_p && test_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status))) return; - __ipipe_sync_stage(syncmask); + __ipipe_sync_stage(); } void __ipipe_disable_root_irqs_hw(void) diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c index 64cff54a8a5..1696d34f51c 100644 --- a/arch/blackfin/kernel/irqchip.c +++ b/arch/blackfin/kernel/irqchip.c @@ -39,21 +39,23 @@ int show_interrupts(struct seq_file *p, void *v) unsigned long flags; if (i < NR_IRQS) { - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); - action = irq_desc[i].action; + struct irq_desc *desc = irq_to_desc(i); + + raw_spin_lock_irqsave(&desc->lock, flags); + action = desc->action; if (!action) goto skip; seq_printf(p, "%3d: ", i); for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); - seq_printf(p, " %8s", irq_desc[i].chip->name); + seq_printf(p, " %8s", irq_desc_get_chip(desc)->name); seq_printf(p, " %s", action->name); for (action = action->next; action; action = action->next) seq_printf(p, " %s", action->name); seq_putc(p, '\n'); skip: - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); + raw_spin_unlock_irqrestore(&desc->lock, flags); } else if (i == NR_IRQS) { seq_printf(p, "NMI: "); for_each_online_cpu(j) diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c index eb92592fd80..9b80b152435 100644 --- a/arch/blackfin/kernel/kgdb.c +++ b/arch/blackfin/kernel/kgdb.c @@ -181,7 +181,7 @@ static int bfin_set_hw_break(unsigned long addr, int len, enum kgdb_bptype type) return -ENOSPC; } - /* Becasue hardware data watchpoint impelemented in current + /* Because hardware data watchpoint impelemented in current * Blackfin can not trigger an exception event as the hardware * instrction watchpoint does, we ignaore all data watch point here. * They can be turned on easily after future blackfin design @@ -422,11 +422,7 @@ int kgdb_arch_handle_exception(int vector, int signo, struct kgdb_arch arch_kgdb_ops = { .gdb_bpt_instr = {0xa1}, -#ifdef CONFIG_SMP - .flags = KGDB_HW_BREAKPOINT|KGDB_THR_PROC_SWAP, -#else .flags = KGDB_HW_BREAKPOINT, -#endif .set_hw_breakpoint = bfin_set_hw_break, .remove_hw_breakpoint = bfin_remove_hw_break, .disable_hw_break = bfin_disable_hw_debug, diff --git a/arch/blackfin/kernel/module.c b/arch/blackfin/kernel/module.c index a6dfa6b71e6..35e350cad9d 100644 --- a/arch/blackfin/kernel/module.c +++ b/arch/blackfin/kernel/module.c @@ -4,7 +4,7 @@ * Licensed under the GPL-2 or later */ -#define pr_fmt(fmt) "module %s: " fmt +#define pr_fmt(fmt) "module %s: " fmt, mod->name #include <linux/moduleloader.h> #include <linux/elf.h> @@ -57,8 +57,7 @@ module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, dest = l1_inst_sram_alloc(s->sh_size); mod->arch.text_l1 = dest; if (dest == NULL) { - pr_err("L1 inst memory allocation failed\n", - mod->name); + pr_err("L1 inst memory allocation failed\n"); return -1; } dma_memcpy(dest, (void *)s->sh_addr, s->sh_size); @@ -70,8 +69,7 @@ module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, dest = l1_data_sram_alloc(s->sh_size); mod->arch.data_a_l1 = dest; if (dest == NULL) { - pr_err("L1 data memory allocation failed\n", - mod->name); + pr_err("L1 data memory allocation failed\n"); return -1; } memcpy(dest, (void *)s->sh_addr, s->sh_size); @@ -83,8 +81,7 @@ module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, dest = l1_data_sram_zalloc(s->sh_size); mod->arch.bss_a_l1 = dest; if (dest == NULL) { - pr_err("L1 data memory allocation failed\n", - mod->name); + pr_err("L1 data memory allocation failed\n"); return -1; } @@ -93,8 +90,7 @@ module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, dest = l1_data_B_sram_alloc(s->sh_size); mod->arch.data_b_l1 = dest; if (dest == NULL) { - pr_err("L1 data memory allocation failed\n", - mod->name); + pr_err("L1 data memory allocation failed\n"); return -1; } memcpy(dest, (void *)s->sh_addr, s->sh_size); @@ -104,8 +100,7 @@ module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, dest = l1_data_B_sram_alloc(s->sh_size); mod->arch.bss_b_l1 = dest; if (dest == NULL) { - pr_err("L1 data memory allocation failed\n", - mod->name); + pr_err("L1 data memory allocation failed\n"); return -1; } memset(dest, 0, s->sh_size); @@ -117,8 +112,7 @@ module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, dest = l2_sram_alloc(s->sh_size); mod->arch.text_l2 = dest; if (dest == NULL) { - pr_err("L2 SRAM allocation failed\n", - mod->name); + pr_err("L2 SRAM allocation failed\n"); return -1; } memcpy(dest, (void *)s->sh_addr, s->sh_size); @@ -130,8 +124,7 @@ module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, dest = l2_sram_alloc(s->sh_size); mod->arch.data_l2 = dest; if (dest == NULL) { - pr_err("L2 SRAM allocation failed\n", - mod->name); + pr_err("L2 SRAM allocation failed\n"); return -1; } memcpy(dest, (void *)s->sh_addr, s->sh_size); @@ -143,8 +136,7 @@ module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, dest = l2_sram_zalloc(s->sh_size); mod->arch.bss_l2 = dest; if (dest == NULL) { - pr_err("L2 SRAM allocation failed\n", - mod->name); + pr_err("L2 SRAM allocation failed\n"); return -1; } @@ -160,9 +152,9 @@ module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, int apply_relocate(Elf_Shdr * sechdrs, const char *strtab, - unsigned int symindex, unsigned int relsec, struct module *me) + unsigned int symindex, unsigned int relsec, struct module *mod) { - pr_err(".rel unsupported\n", me->name); + pr_err(".rel unsupported\n"); return -ENOEXEC; } @@ -186,7 +178,7 @@ apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, Elf32_Sym *sym; unsigned long location, value, size; - pr_debug("applying relocate section %u to %u\n", mod->name, + pr_debug("applying relocate section %u to %u\n", relsec, sechdrs[relsec].sh_info); for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { @@ -203,14 +195,14 @@ apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, #ifdef CONFIG_SMP if (location >= COREB_L1_DATA_A_START) { - pr_err("cannot relocate in L1: %u (SMP kernel)", - mod->name, ELF32_R_TYPE(rel[i].r_info)); + pr_err("cannot relocate in L1: %u (SMP kernel)\n", + ELF32_R_TYPE(rel[i].r_info)); return -ENOEXEC; } #endif pr_debug("location is %lx, value is %lx type is %d\n", - mod->name, location, value, ELF32_R_TYPE(rel[i].r_info)); + location, value, ELF32_R_TYPE(rel[i].r_info)); switch (ELF32_R_TYPE(rel[i].r_info)) { @@ -230,11 +222,11 @@ apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, case R_BFIN_PCREL12_JUMP_S: case R_BFIN_PCREL10: pr_err("unsupported relocation: %u (no -mlong-calls?)\n", - mod->name, ELF32_R_TYPE(rel[i].r_info)); + ELF32_R_TYPE(rel[i].r_info)); return -ENOEXEC; default: - pr_err("unknown relocation: %u\n", mod->name, + pr_err("unknown relocation: %u\n", ELF32_R_TYPE(rel[i].r_info)); return -ENOEXEC; } @@ -251,8 +243,7 @@ apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, isram_memcpy((void *)location, &value, size); break; default: - pr_err("invalid relocation for %#lx\n", - mod->name, location); + pr_err("invalid relocation for %#lx\n", location); return -ENOEXEC; } } diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index ac71dc15cbd..805c6132c77 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -215,11 +215,48 @@ void __init bfin_relocate_l1_mem(void) early_dma_memcpy_done(); +#if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1) + blackfin_iflush_l1_entry[0] = (unsigned long)blackfin_icache_flush_range_l1; +#endif + /* if necessary, copy L2 text/data to L2 SRAM */ if (L2_LENGTH && l2_len) memcpy(_stext_l2, _l2_lma, l2_len); } +#ifdef CONFIG_SMP +void __init bfin_relocate_coreb_l1_mem(void) +{ + unsigned long text_l1_len = (unsigned long)_text_l1_len; + unsigned long data_l1_len = (unsigned long)_data_l1_len; + unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len; + + blackfin_dma_early_init(); + + /* if necessary, copy L1 text to L1 instruction SRAM */ + if (L1_CODE_LENGTH && text_l1_len) + early_dma_memcpy((void *)COREB_L1_CODE_START, _text_l1_lma, + text_l1_len); + + /* if necessary, copy L1 data to L1 data bank A SRAM */ + if (L1_DATA_A_LENGTH && data_l1_len) + early_dma_memcpy((void *)COREB_L1_DATA_A_START, _data_l1_lma, + data_l1_len); + + /* if necessary, copy L1 data B to L1 data bank B SRAM */ + if (L1_DATA_B_LENGTH && data_b_l1_len) + early_dma_memcpy((void *)COREB_L1_DATA_B_START, _data_b_l1_lma, + data_b_l1_len); + + early_dma_memcpy_done(); + +#ifdef CONFIG_ICACHE_FLUSH_L1 + blackfin_iflush_l1_entry[1] = (unsigned long)blackfin_icache_flush_range_l1 - + (unsigned long)_stext_l1 + COREB_L1_CODE_START; +#endif +} +#endif + #ifdef CONFIG_ROMKERNEL void __init bfin_relocate_xip_data(void) { diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c index 8c9a43daf80..cdb4beb6bc8 100644 --- a/arch/blackfin/kernel/time-ts.c +++ b/arch/blackfin/kernel/time-ts.c @@ -206,8 +206,14 @@ irqreturn_t bfin_gptmr0_interrupt(int irq, void *dev_id) { struct clock_event_device *evt = dev_id; smp_mb(); - evt->event_handler(evt); + /* + * We want to ACK before we handle so that we can handle smaller timer + * intervals. This way if the timer expires again while we're handling + * things, we're more likely to see that 2nd int rather than swallowing + * it by ACKing the int at the end of this handler. + */ bfin_gptmr0_ack(); + evt->event_handler(evt); return IRQ_HANDLED; } diff --git a/arch/blackfin/kernel/trace.c b/arch/blackfin/kernel/trace.c index 05b550891ce..050db44fe91 100644 --- a/arch/blackfin/kernel/trace.c +++ b/arch/blackfin/kernel/trace.c @@ -912,10 +912,11 @@ void show_regs(struct pt_regs *fp) /* if no interrupts are going off, don't print this out */ if (fp->ipend & ~0x3F) { for (i = 0; i < (NR_IRQS - 1); i++) { + struct irq_desc *desc = irq_to_desc(i); if (!in_atomic) - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); + raw_spin_lock_irqsave(&desc->lock, flags); - action = irq_desc[i].action; + action = desc->action; if (!action) goto unlock; @@ -928,7 +929,7 @@ void show_regs(struct pt_regs *fp) pr_cont("\n"); unlock: if (!in_atomic) - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); + raw_spin_unlock_irqrestore(&desc->lock, flags); } } diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index 59c1df75e4d..655f25d139a 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -98,7 +98,7 @@ asmlinkage notrace void trap_c(struct pt_regs *fp) /* send the appropriate signal to the user program */ switch (trapnr) { - /* This table works in conjuction with the one in ./mach-common/entry.S + /* This table works in conjunction with the one in ./mach-common/entry.S * Some exceptions are handled there (in assembly, in exception space) * Some are handled here, (in C, in interrupt space) * Some, like CPLB, are handled in both, where the normal path is diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S index c40d07f708e..854fa49f1c3 100644 --- a/arch/blackfin/kernel/vmlinux.lds.S +++ b/arch/blackfin/kernel/vmlinux.lds.S @@ -136,7 +136,7 @@ SECTIONS . = ALIGN(16); INIT_DATA_SECTION(16) - PERCPU(32, 4) + PERCPU(32, PAGE_SIZE) .exit.data : { @@ -176,6 +176,7 @@ SECTIONS { . = ALIGN(4); __stext_l1 = .; + *(.l1.text.head) *(.l1.text) #ifdef CONFIG_SCHEDULE_L1 SCHED_TEXT diff --git a/arch/blackfin/lib/ins.S b/arch/blackfin/lib/ins.S index 3edbd8db659..79caccea85c 100644 --- a/arch/blackfin/lib/ins.S +++ b/arch/blackfin/lib/ins.S @@ -67,7 +67,7 @@ * - DMA version, which do not suffer from this issue. DMA versions have * different name (prefixed by dma_ ), and are located in * ../kernel/bfin_dma_5xx.c - * Using the dma related functions are recommended for transfering large + * Using the dma related functions are recommended for transferring large * buffers in/out of FIFOs. */ diff --git a/arch/blackfin/lib/memmove.S b/arch/blackfin/lib/memmove.S index 80c240acac6..4eca566237a 100644 --- a/arch/blackfin/lib/memmove.S +++ b/arch/blackfin/lib/memmove.S @@ -60,7 +60,7 @@ ENTRY(_memmove) [P0++] = R1; CC = P2 == 0; /* any remaining bytes? */ - P3 = I0; /* Ammend P3 to updated ptr. */ + P3 = I0; /* Amend P3 to updated ptr. */ IF !CC JUMP .Lbytes; P3 = I1; RTS; diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h index 27285823fb2..cb1172f5075 100644 --- a/arch/blackfin/mach-bf518/include/mach/defBF512.h +++ b/arch/blackfin/mach-bf518/include/mach/defBF512.h @@ -1201,25 +1201,6 @@ #define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ #define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ - -/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/ -/* HDMAx_CTL Masks */ -#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */ -#define REP 0x0002 /* HDMA Request Polarity */ -#define UTE 0x0004 /* Urgency Threshold Enable */ -#define OIE 0x0010 /* Overflow Interrupt Enable */ -#define BDIE 0x0020 /* Block Done Interrupt Enable */ -#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */ -#define DRQ 0x0300 /* HDMA Request Type */ -#define DRQ_NONE 0x0000 /* No Request */ -#define DRQ_SINGLE 0x0100 /* Channels Request Single */ -#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */ -#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */ -#define RBC 0x1000 /* Reload BCNT With IBCNT */ -#define PS 0x2000 /* HDMA Pin Status */ -#define OI 0x4000 /* Overflow Interrupt Generated */ -#define BDI 0x8000 /* Block Done Interrupt Generated */ - /* entry addresses of the user-callable Boot ROM functions */ #define _BOOTROM_RESET 0xEF000000 diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h index 89f5420ee6c..84ef11e5264 100644 --- a/arch/blackfin/mach-bf527/include/mach/defBF522.h +++ b/arch/blackfin/mach-bf527/include/mach/defBF522.h @@ -1204,25 +1204,6 @@ #define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ #define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ - -/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/ -/* HDMAx_CTL Masks */ -#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */ -#define REP 0x0002 /* HDMA Request Polarity */ -#define UTE 0x0004 /* Urgency Threshold Enable */ -#define OIE 0x0010 /* Overflow Interrupt Enable */ -#define BDIE 0x0020 /* Block Done Interrupt Enable */ -#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */ -#define DRQ 0x0300 /* HDMA Request Type */ -#define DRQ_NONE 0x0000 /* No Request */ -#define DRQ_SINGLE 0x0100 /* Channels Request Single */ -#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */ -#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */ -#define RBC 0x1000 /* Reload BCNT With IBCNT */ -#define PS 0x2000 /* HDMA Pin Status */ -#define OI 0x4000 /* Overflow Interrupt Generated */ -#define BDI 0x8000 /* Block Done Interrupt Generated */ - /* entry addresses of the user-callable Boot ROM functions */ #define _BOOTROM_RESET 0xEF000000 diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c index f869a371148..a377d8afea0 100644 --- a/arch/blackfin/mach-bf533/boards/ip0x.c +++ b/arch/blackfin/mach-bf533/boards/ip0x.c @@ -289,8 +289,6 @@ static struct platform_device *ip0x_devices[] __initdata = { static int __init ip0x_init(void) { - int i; - printk(KERN_INFO "%s(): registering device resources\n", __func__); platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices)); diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c index 2c776e188a9..d582b810e7a 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c @@ -775,7 +775,7 @@ static int __init cm_bf537e_init(void) #endif #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) - irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; + irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN); #endif return 0; } diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c index 085661175ec..cbb8098604c 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c @@ -740,7 +740,7 @@ static int __init cm_bf537u_init(void) #endif #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) - irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; + irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN); #endif return 0; } diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c index e1e9ea02ad8..6b4ff4605bf 100644 --- a/arch/blackfin/mach-bf537/boards/dnp5370.c +++ b/arch/blackfin/mach-bf537/boards/dnp5370.c @@ -128,30 +128,11 @@ static struct platform_device asmb_flash_device = { #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) -#define MMC_SPI_CARD_DETECT_INT IRQ_PF5 - -static int bfin_mmc_spi_init(struct device *dev, - irqreturn_t (*detect_int)(int, void *), void *data) -{ - return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int, - IRQF_TRIGGER_FALLING, "mmc-spi-detect", data); -} - -static void bfin_mmc_spi_exit(struct device *dev, void *data) -{ - free_irq(MMC_SPI_CARD_DETECT_INT, data); -} - static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, /* use no dma transfer with this chip*/ .bits_per_word = 8, }; -static struct mmc_spi_platform_data bfin_mmc_spi_pdata = { - .init = bfin_mmc_spi_init, - .exit = bfin_mmc_spi_exit, - .detect_delay = 100, /* msecs */ -}; #endif #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE) @@ -192,7 +173,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 20000000, .bus_num = 0, .chip_select = 1, - .platform_data = &bfin_mmc_spi_pdata, .controller_data = &mmc_spi_chip_info, .mode = SPI_MODE_3, }, diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index 2c69785a7bb..3fa335405b3 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -2530,7 +2530,7 @@ static struct resource bfin_pata_resources[] = { static struct pata_platform_info bfin_pata_platform_data = { .ioport_shift = 0, }; -/* CompactFlash Storage Card Memory Mapped Adressing +/* CompactFlash Storage Card Memory Mapped Addressing * /REG = A11 = 1 */ static struct resource bfin_pata_resources[] = { diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c index 0761b201abc..164a7e02c02 100644 --- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c @@ -742,7 +742,7 @@ static int __init tcm_bf537_init(void) #endif #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) - irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; + irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN); #endif return 0; } diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h index 725bb35f3aa..4a031dde173 100644 --- a/arch/blackfin/mach-bf537/include/mach/defBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h @@ -1520,24 +1520,6 @@ #define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ #define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ -/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/ -/* HDMAx_CTL Masks */ -#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */ -#define REP 0x0002 /* HDMA Request Polarity */ -#define UTE 0x0004 /* Urgency Threshold Enable */ -#define OIE 0x0010 /* Overflow Interrupt Enable */ -#define BDIE 0x0020 /* Block Done Interrupt Enable */ -#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */ -#define DRQ 0x0300 /* HDMA Request Type */ -#define DRQ_NONE 0x0000 /* No Request */ -#define DRQ_SINGLE 0x0100 /* Channels Request Single */ -#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */ -#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */ -#define RBC 0x1000 /* Reload BCNT With IBCNT */ -#define PS 0x2000 /* HDMA Pin Status */ -#define OI 0x4000 /* Overflow Interrupt Generated */ -#define BDI 0x8000 /* Block Done Interrupt Generated */ - /* entry addresses of the user-callable Boot ROM functions */ #define _BOOTROM_RESET 0xEF000000 diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig index 70189a0d1a1..94acb586832 100644 --- a/arch/blackfin/mach-bf548/Kconfig +++ b/arch/blackfin/mach-bf548/Kconfig @@ -42,6 +42,65 @@ config BF548_ATAPI_ALTERNATIVE_PORT async address or GPIO port F and G. Select y to route it to GPIO. +choice + prompt "UART2 DMA channel selection" + depends on SERIAL_BFIN_UART2 + default UART2_DMA_RX_ON_DMA18 + help + UART2 DMA channel selection + RX -> DMA18 + TX -> DMA19 + or + RX -> DMA13 + TX -> DMA14 + +config UART2_DMA_RX_ON_DMA18 + bool "UART2 DMA RX -> DMA18 TX -> DMA19" + help + UART2 DMA channel assignment + RX -> DMA18 + TX -> DMA19 + use SPORT2 default DMA channel + +config UART2_DMA_RX_ON_DMA13 + bool "UART2 DMA RX -> DMA13 TX -> DMA14" + help + UART2 DMA channel assignment + RX -> DMA13 + TX -> DMA14 + use EPPI1 EPPI2 default DMA channel +endchoice + +choice + prompt "UART3 DMA channel selection" + depends on SERIAL_BFIN_UART3 + default UART3_DMA_RX_ON_DMA20 + help + UART3 DMA channel selection + RX -> DMA20 + TX -> DMA21 + or + RX -> DMA15 + TX -> DMA16 + +config UART3_DMA_RX_ON_DMA20 + bool "UART3 DMA RX -> DMA20 TX -> DMA21" + help + UART3 DMA channel assignment + RX -> DMA20 + TX -> DMA21 + use SPORT3 default DMA channel + +config UART3_DMA_RX_ON_DMA15 + bool "UART3 DMA RX -> DMA15 TX -> DMA16" + help + UART3 DMA channel assignment + RX -> DMA15 + TX -> DMA16 + use PIXC default DMA channel + +endchoice + comment "Interrupt Priority Assignment" menu "Priority" diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index ce5a2bb147d..93e19a54a88 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -778,11 +778,12 @@ static struct platform_device bfin_sport3_uart_device = { #endif #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) -static unsigned short bfin_can_peripherals[] = { + +static unsigned short bfin_can0_peripherals[] = { P_CAN0_RX, P_CAN0_TX, 0 }; -static struct resource bfin_can_resources[] = { +static struct resource bfin_can0_resources[] = { { .start = 0xFFC02A00, .end = 0xFFC02FFF, @@ -805,14 +806,53 @@ static struct resource bfin_can_resources[] = { }, }; -static struct platform_device bfin_can_device = { +static struct platform_device bfin_can0_device = { .name = "bfin_can", - .num_resources = ARRAY_SIZE(bfin_can_resources), - .resource = bfin_can_resources, + .id = 0, + .num_resources = ARRAY_SIZE(bfin_can0_resources), + .resource = bfin_can0_resources, .dev = { - .platform_data = &bfin_can_peripherals, /* Passed to driver */ + .platform_data = &bfin_can0_peripherals, /* Passed to driver */ }, }; + +static unsigned short bfin_can1_peripherals[] = { + P_CAN1_RX, P_CAN1_TX, 0 +}; + +static struct resource bfin_can1_resources[] = { + { + .start = 0xFFC03200, + .end = 0xFFC037FF, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_CAN1_RX, + .end = IRQ_CAN1_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_CAN1_TX, + .end = IRQ_CAN1_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_CAN1_ERROR, + .end = IRQ_CAN1_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bfin_can1_device = { + .name = "bfin_can", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_can1_resources), + .resource = bfin_can1_resources, + .dev = { + .platform_data = &bfin_can1_peripherals, /* Passed to driver */ + }, +}; + #endif #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) @@ -1366,7 +1406,8 @@ static struct platform_device *ezkit_devices[] __initdata = { #endif #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) - &bfin_can_device, + &bfin_can0_device, + &bfin_can1_device, #endif #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h index 4070079e2c0..ffd0537295a 100644 --- a/arch/blackfin/mach-bf548/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h @@ -81,7 +81,11 @@ /* PLL Status Register Is Inaccurate */ #define ANOMALY_05000351 (__SILICON_REVISION__ < 1) /* bfrom_SysControl() Firmware Function Performs Improper System Reset */ -#define ANOMALY_05000353 (__SILICON_REVISION__ < 2) +/* + * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing + * shows that the fix itself does not cover all cases. + */ +#define ANOMALY_05000353 (1) /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ #define ANOMALY_05000355 (__SILICON_REVISION__ < 1) /* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */ diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h index 642468c1bcb..bcccab36629 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF544.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h @@ -657,22 +657,4 @@ /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ -/* Bit masks for HMDMAx_CONTROL */ - -#define HMDMAEN 0x1 /* Handshake MDMA Enable */ -#define REP 0x2 /* Handshake MDMA Request Polarity */ -#define UTE 0x8 /* Urgency Threshold Enable */ -#define OIE 0x10 /* Overflow Interrupt Enable */ -#define BDIE 0x20 /* Block Done Interrupt Enable */ -#define MBDI 0x40 /* Mask Block Done Interrupt */ -#define DRQ 0x300 /* Handshake MDMA Request Type */ -#define RBC 0x1000 /* Force Reload of BCOUNT */ -#define PS 0x2000 /* Pin Status */ -#define OI 0x4000 /* Overflow Interrupt Generated */ -#define BDI 0x8000 /* Block Done Interrupt Generated */ - -/* ******************************************* */ -/* MULTI BIT MACRO ENUMERATIONS */ -/* ******************************************* */ - #endif /* _DEF_BF544_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h index 2f3337cd311..1cbba115f96 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF547.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h @@ -1063,23 +1063,4 @@ #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ -/* Bit masks for HMDMAx_CONTROL */ - -#define HMDMAEN 0x1 /* Handshake MDMA Enable */ -#define REP 0x2 /* Handshake MDMA Request Polarity */ -#define UTE 0x8 /* Urgency Threshold Enable */ -#define OIE 0x10 /* Overflow Interrupt Enable */ -#define BDIE 0x20 /* Block Done Interrupt Enable */ -#define MBDI 0x40 /* Mask Block Done Interrupt */ -#define DRQ 0x300 /* Handshake MDMA Request Type */ -#define RBC 0x1000 /* Force Reload of BCOUNT */ -#define PS 0x2000 /* Pin Status */ -#define OI 0x4000 /* Overflow Interrupt Generated */ -#define BDI 0x8000 /* Block Done Interrupt Generated */ - -/* ******************************************* */ -/* MULTI BIT MACRO ENUMERATIONS */ -/* ******************************************* */ - - #endif /* _DEF_BF547_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/dma.h b/arch/blackfin/mach-bf548/include/mach/dma.h index a30d242c739..1a1091b071f 100644 --- a/arch/blackfin/mach-bf548/include/mach/dma.h +++ b/arch/blackfin/mach-bf548/include/mach/dma.h @@ -27,17 +27,37 @@ #define CH_PIXC_OVERLAY 16 #define CH_PIXC_OUTPUT 17 #define CH_SPORT2_RX 18 -#define CH_UART2_RX 18 #define CH_SPORT2_TX 19 -#define CH_UART2_TX 19 #define CH_SPORT3_RX 20 -#define CH_UART3_RX 20 #define CH_SPORT3_TX 21 -#define CH_UART3_TX 21 #define CH_SDH 22 #define CH_NFC 22 #define CH_SPI2 23 +#if defined(CONFIG_UART2_DMA_RX_ON_DMA13) +#define CH_UART2_RX 13 +#define IRQ_UART2_RX BFIN_IRQ(37) /* UART2 RX USE EPP1 (DMA13) Interrupt */ +#define CH_UART2_TX 14 +#define IRQ_UART2_TX BFIN_IRQ(38) /* UART2 RX USE EPP1 (DMA14) Interrupt */ +#else /* Default USE SPORT2's DMA Channel */ +#define CH_UART2_RX 18 +#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */ +#define CH_UART2_TX 19 +#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */ +#endif + +#if defined(CONFIG_UART3_DMA_RX_ON_DMA15) +#define CH_UART3_RX 15 +#define IRQ_UART3_RX BFIN_IRQ(64) /* UART3 RX USE PIXC IN0 (DMA15) Interrupt */ +#define CH_UART3_TX 16 +#define IRQ_UART3_TX BFIN_IRQ(65) /* UART3 TX USE PIXC IN1 (DMA16) Interrupt */ +#else /* Default USE SPORT3's DMA Channel */ +#define CH_UART3_RX 20 +#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */ +#define CH_UART3_TX 21 +#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */ +#endif + #define CH_MEM_STREAM0_DEST 24 #define CH_MEM_STREAM0_SRC 25 #define CH_MEM_STREAM1_DEST 26 diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h index 99fd1b2c53d..7f87787e773 100644 --- a/arch/blackfin/mach-bf548/include/mach/irq.h +++ b/arch/blackfin/mach-bf548/include/mach/irq.h @@ -74,13 +74,9 @@ Events (highest priority) EMU 0 #define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ #define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ #define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ -#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */ #define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ -#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */ #define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ -#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */ #define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ -#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */ #define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ #define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ #define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c index 3b67929d4c0..87595cd38af 100644 --- a/arch/blackfin/mach-bf561/boards/cm_bf561.c +++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c @@ -541,7 +541,7 @@ static int __init cm_bf561_init(void) #endif #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) - irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; + irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN); #endif return 0; } diff --git a/arch/blackfin/mach-bf561/hotplug.c b/arch/blackfin/mach-bf561/hotplug.c index 4cd3b28cd04..0123117b8ff 100644 --- a/arch/blackfin/mach-bf561/hotplug.c +++ b/arch/blackfin/mach-bf561/hotplug.c @@ -5,30 +5,36 @@ * Licensed under the GPL-2 or later. */ +#include <linux/smp.h> #include <asm/blackfin.h> -#include <asm/irq.h> -#include <asm/smp.h> - -#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) +#include <asm/cacheflush.h> +#include <mach/pll.h> int hotplug_coreb; void platform_cpu_die(void) { - unsigned long iwr[2] = {0, 0}; - unsigned long bank = SIC_SYSIRQ(IRQ_SUPPLE_0) / 32; - unsigned long bit = 1 << (SIC_SYSIRQ(IRQ_SUPPLE_0) % 32); + unsigned long iwr; hotplug_coreb = 1; - iwr[bank] = bit; + /* + * When CoreB wakes up, the code in _coreb_trampoline_start cannot + * turn off the data cache. This causes the CoreB failed to boot. + * As a workaround, we invalidate all the data cache before sleep. + */ + blackfin_invalidate_entire_dcache(); /* disable core timer */ bfin_write_TCNTL(0); - /* clear ipi interrupt IRQ_SUPPLE_0 */ + /* clear ipi interrupt IRQ_SUPPLE_0 of CoreB */ bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + 1))); SSYNC(); - coreb_sleep(iwr[0], iwr[1], 0); + /* set CoreB wakeup by ipi0, iwr will be discarded */ + bfin_iwr_set_sup0(&iwr, &iwr, &iwr); + SSYNC(); + + coreb_die(); } diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S index 4624eebbf9c..4c462838f4e 100644 --- a/arch/blackfin/mach-bf561/secondary.S +++ b/arch/blackfin/mach-bf561/secondary.S @@ -13,7 +13,11 @@ #include <asm/asm-offsets.h> #include <asm/trace.h> -__INIT +/* + * This code must come first as CoreB is hardcoded (in hardware) + * to start at the beginning of its L1 instruction memory. + */ +.section .l1.text.head /* Lay the initial stack into the L1 scratch area of Core B */ #define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12) @@ -160,43 +164,34 @@ ENTRY(_coreb_trampoline_start) .LWAIT_HERE: jump .LWAIT_HERE; ENDPROC(_coreb_trampoline_start) -ENTRY(_coreb_trampoline_end) +#ifdef CONFIG_HOTPLUG_CPU .section ".text" -ENTRY(_set_sicb_iwr) - P0.H = hi(SICB_IWR0); - P0.L = lo(SICB_IWR0); - P1.H = hi(SICB_IWR1); - P1.L = lo(SICB_IWR1); - [P0] = R0; - [P1] = R1; - SSYNC; - RTS; -ENDPROC(_set_sicb_iwr) - -ENTRY(_coreb_sleep) +ENTRY(_coreb_die) sp.l = lo(INITIAL_STACK); sp.h = hi(INITIAL_STACK); fp = sp; usp = sp; - call _set_sicb_iwr; - CLI R2; SSYNC; IDLE; STI R2; R0 = IWR_DISABLE_ALL; - R1 = IWR_DISABLE_ALL; - call _set_sicb_iwr; + P0.H = hi(SYSMMR_BASE); + P0.L = lo(SYSMMR_BASE); + [P0 + (SICB_IWR0 - SYSMMR_BASE)] = R0; + [P0 + (SICB_IWR1 - SYSMMR_BASE)] = R0; + SSYNC; p0.h = hi(COREB_L1_CODE_START); p0.l = lo(COREB_L1_CODE_START); jump (p0); -ENDPROC(_coreb_sleep) +ENDPROC(_coreb_die) +#endif -__CPUINIT +__INIT ENTRY(_coreb_start) [--sp] = reti; diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c index 1074a7ef81c..7b07740cf68 100644 --- a/arch/blackfin/mach-bf561/smp.c +++ b/arch/blackfin/mach-bf561/smp.c @@ -30,18 +30,11 @@ void __init platform_init_cpus(void) void __init platform_prepare_cpus(unsigned int max_cpus) { - int len; - - len = &coreb_trampoline_end - &coreb_trampoline_start + 1; - BUG_ON(len > L1_CODE_LENGTH); - - dma_memcpy((void *)COREB_L1_CODE_START, &coreb_trampoline_start, len); + bfin_relocate_coreb_l1_mem(); /* Both cores ought to be present on a bf561! */ cpu_set(0, cpu_present_map); /* CoreA */ cpu_set(1, cpu_present_map); /* CoreB */ - - printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_L1_CODE_START); } int __init setup_profiling_timer(unsigned int multiplier) /* not supported */ @@ -161,9 +154,13 @@ void platform_clear_ipi(unsigned int cpu, int irq) void __cpuinit bfin_local_timer_setup(void) { #if defined(CONFIG_TICKSOURCE_CORETMR) + struct irq_data *data = irq_get_irq_data(IRQ_CORETMR); + struct irq_chip *chip = irq_data_get_irq_chip(data); + bfin_coretmr_init(); bfin_coretmr_clockevent_init(); - get_irq_chip(IRQ_CORETMR)->unmask(IRQ_CORETMR); + + chip->irq_unmask(data); #else /* Power down the core timer, just to play safe. */ bfin_write_TCNTL(0); diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c index bceb98126c2..d8643fdd0fc 100644 --- a/arch/blackfin/mach-common/arch_checks.c +++ b/arch/blackfin/mach-common/arch_checks.c @@ -61,6 +61,6 @@ # error "Anomaly 05000220 does not allow you to use Write Back cache with L2 or External Memory" #endif -#if ANOMALY_05000491 && !defined(CONFIG_CACHE_FLUSH_L1) +#if ANOMALY_05000491 && !defined(CONFIG_ICACHE_FLUSH_L1) # error You need IFLUSH in L1 inst while Anomaly 05000491 applies #endif diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S index ab4a925a443..9f4dd35bfd7 100644 --- a/arch/blackfin/mach-common/cache.S +++ b/arch/blackfin/mach-common/cache.S @@ -11,12 +11,6 @@ #include <asm/cache.h> #include <asm/page.h> -#ifdef CONFIG_CACHE_FLUSH_L1 -.section .l1.text -#else -.text -#endif - /* 05000443 - IFLUSH cannot be last instruction in hardware loop */ #if ANOMALY_05000443 # define BROK_FLUSH_INST "IFLUSH" @@ -68,11 +62,43 @@ RTS; .endm +#ifdef CONFIG_ICACHE_FLUSH_L1 +.section .l1.text +#else +.text +#endif + /* Invalidate all instruction cache lines assocoiated with this memory area */ +#ifdef CONFIG_SMP +# define _blackfin_icache_flush_range _blackfin_icache_flush_range_l1 +#endif ENTRY(_blackfin_icache_flush_range) do_flush IFLUSH ENDPROC(_blackfin_icache_flush_range) +#ifdef CONFIG_SMP +.text +# undef _blackfin_icache_flush_range +ENTRY(_blackfin_icache_flush_range) + p0.L = LO(DSPID); + p0.H = HI(DSPID); + r3 = [p0]; + r3 = r3.b (z); + p2 = r3; + p0.L = _blackfin_iflush_l1_entry; + p0.H = _blackfin_iflush_l1_entry; + p0 = p0 + (p2 << 2); + p1 = [p0]; + jump (p1); +ENDPROC(_blackfin_icache_flush_range) +#endif + +#ifdef CONFIG_DCACHE_FLUSH_L1 +.section .l1.text +#else +.text +#endif + /* Throw away all D-cached data in specified region without any obligation to * write them back. Since the Blackfin ISA does not have an "invalidate" * instruction, we use flush/invalidate. Perhaps as a speed optimization we diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c index f4cf11d362e..85dc6d69f9c 100644 --- a/arch/blackfin/mach-common/cpufreq.c +++ b/arch/blackfin/mach-common/cpufreq.c @@ -1,7 +1,7 @@ /* * Blackfin core clock scaling * - * Copyright 2008-2009 Analog Devices Inc. + * Copyright 2008-2011 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -16,10 +16,8 @@ #include <asm/time.h> #include <asm/dpmc.h> -#define CPUFREQ_CPU 0 - /* this is the table of CCLK frequencies, in Hz */ -/* .index is the entry in the auxillary dpm_state_table[] */ +/* .index is the entry in the auxiliary dpm_state_table[] */ static struct cpufreq_frequency_table bfin_freq_table[] = { { .frequency = CPUFREQ_TABLE_END, @@ -46,7 +44,7 @@ static struct bfin_dpm_state { #if defined(CONFIG_CYCLES_CLOCKSOURCE) /* - * normalized to maximum frequncy offset for CYCLES, + * normalized to maximum frequency offset for CYCLES, * used in time-ts cycles clock source, but could be used * somewhere also. */ diff --git a/arch/blackfin/mach-common/dpmc.c b/arch/blackfin/mach-common/dpmc.c index 02c7efd1bcf..382099fd556 100644 --- a/arch/blackfin/mach-common/dpmc.c +++ b/arch/blackfin/mach-common/dpmc.c @@ -61,17 +61,63 @@ err_out: } #ifdef CONFIG_CPU_FREQ +# ifdef CONFIG_SMP +static void bfin_idle_this_cpu(void *info) +{ + unsigned long flags = 0; + unsigned long iwr0, iwr1, iwr2; + unsigned int cpu = smp_processor_id(); + + local_irq_save_hw(flags); + bfin_iwr_set_sup0(&iwr0, &iwr1, &iwr2); + + platform_clear_ipi(cpu, IRQ_SUPPLE_0); + SSYNC(); + asm("IDLE;"); + bfin_iwr_restore(iwr0, iwr1, iwr2); + + local_irq_restore_hw(flags); +} + +static void bfin_idle_cpu(void) +{ + smp_call_function(bfin_idle_this_cpu, NULL, 0); +} + +static void bfin_wakeup_cpu(void) +{ + unsigned int cpu; + unsigned int this_cpu = smp_processor_id(); + cpumask_t mask = cpu_online_map; + + cpu_clear(this_cpu, mask); + for_each_cpu_mask(cpu, mask) + platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); +} + +# else +static void bfin_idle_cpu(void) {} +static void bfin_wakeup_cpu(void) {} +# endif + static int vreg_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data) { struct cpufreq_freqs *freq = data; + if (freq->cpu != CPUFREQ_CPU) + return 0; + if (val == CPUFREQ_PRECHANGE && freq->old < freq->new) { + bfin_idle_cpu(); bfin_set_vlev(bfin_get_vlev(freq->new)); udelay(pdata->vr_settling_time); /* Wait until Volatge settled */ - - } else if (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) + bfin_wakeup_cpu(); + } else if (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) { + bfin_idle_cpu(); bfin_set_vlev(bfin_get_vlev(freq->new)); + bfin_wakeup_cpu(); + } return 0; } diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index bc08c98d008..f96933f48a7 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -268,7 +268,7 @@ ENTRY(_handle_bad_cplb) /* To get here, we just tried and failed to change a CPLB * so, handle things in trap_c (C code), by lowering to * IRQ5, just like we normally do. Since this is not a - * "normal" return path, we have a do alot of stuff to + * "normal" return path, we have a do a lot of stuff to * the stack to get ready so, we can fall through - we * need to make a CPLB exception look like a normal exception */ @@ -817,7 +817,7 @@ _new_old_task: rets = [sp++]; /* - * When we come out of resume, r0 carries "old" task, becuase we are + * When we come out of resume, r0 carries "old" task, because we are * in "new" task. */ rts; @@ -952,8 +952,17 @@ ENDPROC(_evt_up_evt14) #ifdef CONFIG_IPIPE _resume_kernel_from_int: + r1 = LO(~0x8000) (Z); + r1 = r0 & r1; + r0 = 1; + r0 = r1 - r0; + r2 = r1 & r0; + cc = r2 == 0; + /* Sync the root stage only from the outer interrupt level. */ + if !cc jump .Lnosync; r0.l = ___ipipe_sync_root; r0.h = ___ipipe_sync_root; + [--sp] = reti; [--sp] = rets; [--sp] = ( r7:4, p5:3 ); SP += -12; @@ -961,6 +970,8 @@ _resume_kernel_from_int: SP += 12; ( r7:4, p5:3 ) = [sp++]; rets = [sp++]; + reti = [sp++]; +.Lnosync: rts #elif defined(CONFIG_PREEMPT) @@ -1738,6 +1749,10 @@ ENTRY(_sys_call_table) .long _sys_fanotify_mark .long _sys_prlimit64 .long _sys_cacheflush + .long _sys_name_to_handle_at /* 375 */ + .long _sys_open_by_handle_at + .long _sys_clock_adjtime + .long _sys_syncfs .rept NR_syscalls-(.-_sys_call_table)/4 .long _sys_ni_syscall diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S index 4391621d904..76de5724c1e 100644 --- a/arch/blackfin/mach-common/head.S +++ b/arch/blackfin/mach-common/head.S @@ -31,6 +31,7 @@ ENDPROC(__init_clear_bss) ENTRY(__start) /* R0: argument of command line string, passed from uboot, save it */ R7 = R0; + /* Enable Cycle Counter and Nesting Of Interrupts */ #ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES R0 = SYSCFG_SNEN; @@ -38,76 +39,49 @@ ENTRY(__start) R0 = SYSCFG_SNEN | SYSCFG_CCEN; #endif SYSCFG = R0; - R0 = 0; - - /* Clear Out All the data and pointer Registers */ - R1 = R0; - R2 = R0; - R3 = R0; - R4 = R0; - R5 = R0; - R6 = R0; - - P0 = R0; - P1 = R0; - P2 = R0; - P3 = R0; - P4 = R0; - P5 = R0; - - LC0 = r0; - LC1 = r0; - L0 = r0; - L1 = r0; - L2 = r0; - L3 = r0; - - /* Clear Out All the DAG Registers */ - B0 = r0; - B1 = r0; - B2 = r0; - B3 = r0; - - I0 = r0; - I1 = r0; - I2 = r0; - I3 = r0; - - M0 = r0; - M1 = r0; - M2 = r0; - M3 = r0; + + /* Optimization register tricks: keep a base value in the + * reserved P registers so we use the load/store with an + * offset syntax. R0 = [P5 + <constant>]; + * P5 - core MMR base + * R6 - 0 + */ + r6 = 0; + p5.l = 0; + p5.h = hi(COREMMR_BASE); + + /* Zero out registers required by Blackfin ABI */ + + /* Disable circular buffers */ + L0 = r6; + L1 = r6; + L2 = r6; + L3 = r6; + + /* Disable hardware loops in case we were started by 'go' */ + LC0 = r6; + LC1 = r6; /* * Clear ITEST_COMMAND and DTEST_COMMAND registers, * Leaving these as non-zero can confuse the emulator */ - p0.L = LO(DTEST_COMMAND); - p0.H = HI(DTEST_COMMAND); - [p0] = R0; - [p0 + (ITEST_COMMAND - DTEST_COMMAND)] = R0; + [p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6; + [p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6; CSYNC; trace_buffer_init(p0,r0); - P0 = R1; - R0 = R1; /* Turn off the icache */ - p0.l = LO(IMEM_CONTROL); - p0.h = HI(IMEM_CONTROL); - R1 = [p0]; - R0 = ~ENICPLB; - R0 = R0 & R1; - [p0] = R0; + r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)]; + BITCLR (r1, ENICPLB_P); + [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1; SSYNC; /* Turn off the dcache */ - p0.l = LO(DMEM_CONTROL); - p0.h = HI(DMEM_CONTROL); - R1 = [p0]; - R0 = ~ENDCPLB; - R0 = R0 & R1; - [p0] = R0; + r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)]; + BITCLR (r1, ENDCPLB_P); + [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1; SSYNC; /* in case of double faults, save a few things */ @@ -122,25 +96,25 @@ ENTRY(__start) * below */ GET_PDA(p0, r0); - r6 = [p0 + PDA_DF_RETX]; + r5 = [p0 + PDA_DF_RETX]; p1.l = _init_saved_retx; p1.h = _init_saved_retx; - [p1] = r6; + [p1] = r5; - r6 = [p0 + PDA_DF_DCPLB]; + r5 = [p0 + PDA_DF_DCPLB]; p1.l = _init_saved_dcplb_fault_addr; p1.h = _init_saved_dcplb_fault_addr; - [p1] = r6; + [p1] = r5; - r6 = [p0 + PDA_DF_ICPLB]; + r5 = [p0 + PDA_DF_ICPLB]; p1.l = _init_saved_icplb_fault_addr; p1.h = _init_saved_icplb_fault_addr; - [p1] = r6; + [p1] = r5; - r6 = [p0 + PDA_DF_SEQSTAT]; + r5 = [p0 + PDA_DF_SEQSTAT]; p1.l = _init_saved_seqstat; p1.h = _init_saved_seqstat; - [p1] = r6; + [p1] = r5; #endif /* Initialize stack pointer */ @@ -155,7 +129,7 @@ ENTRY(__start) sti r0; #endif - r0 = 0 (x); + r0 = r6; /* Zero out all of the fun bss regions */ #if L1_DATA_A_LENGTH > 0 r1.l = __sbss_l1; @@ -200,7 +174,7 @@ ENTRY(__start) sp.l = lo(KERNEL_CLOCK_STACK); sp.h = hi(KERNEL_CLOCK_STACK); call _init_clocks; - sp = usp; /* usp hasnt been touched, so restore from there */ + sp = usp; /* usp hasn't been touched, so restore from there */ #endif /* This section keeps the processor in supervisor mode @@ -210,11 +184,9 @@ ENTRY(__start) /* EVT15 = _real_start */ - p0.l = lo(EVT15); - p0.h = hi(EVT15); p1.l = _real_start; p1.h = _real_start; - [p0] = p1; + [p5 + (EVT15 - COREMMR_BASE)] = p1; csync; #ifdef CONFIG_EARLY_PRINTK diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S index 2df37db3b49..469ce7282dc 100644 --- a/arch/blackfin/mach-common/interrupt.S +++ b/arch/blackfin/mach-common/interrupt.S @@ -274,16 +274,16 @@ ENDPROC(_evt_system_call) * level to EVT14 to prepare the caller for a normal interrupt * return through RTI. * - * We currently use this facility in two occasions: + * We currently use this feature in two occasions: * - * - to branch to __ipipe_irq_tail_hook as requested by a high + * - before branching to __ipipe_irq_tail_hook as requested by a high * priority domain after the pipeline delivered an interrupt, * e.g. such as Xenomai, in order to start its rescheduling * procedure, since we may not switch tasks when IRQ levels are * nested on the Blackfin, so we have to fake an interrupt return * so that we may reschedule immediately. * - * - to branch to sync_root_irqs, in order to play any interrupt + * - before branching to __ipipe_sync_root(), in order to play any interrupt * pending for the root domain (i.e. the Linux kernel). This lowers * the core priority level enough so that Linux IRQ handlers may * never delay interrupts handled by high priority domains; we defer diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index a604f19d8dc..43d9fb195c1 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c @@ -15,6 +15,7 @@ #include <linux/kernel_stat.h> #include <linux/seq_file.h> #include <linux/irq.h> +#include <linux/sched.h> #ifdef CONFIG_IPIPE #include <linux/ipipe.h> #endif @@ -124,21 +125,21 @@ static void __init search_IAR(void) * This is for core internal IRQs */ -static void bfin_ack_noop(unsigned int irq) +static void bfin_ack_noop(struct irq_data *d) { /* Dummy function. */ } -static void bfin_core_mask_irq(unsigned int irq) +static void bfin_core_mask_irq(struct irq_data *d) { - bfin_irq_flags &= ~(1 << irq); + bfin_irq_flags &= ~(1 << d->irq); if (!hard_irqs_disabled()) hard_local_irq_enable(); } -static void bfin_core_unmask_irq(unsigned int irq) +static void bfin_core_unmask_irq(struct irq_data *d) { - bfin_irq_flags |= 1 << irq; + bfin_irq_flags |= 1 << d->irq; /* * If interrupts are enabled, IMASK must contain the same value * as bfin_irq_flags. Make sure that invariant holds. If interrupts @@ -176,6 +177,11 @@ static void bfin_internal_mask_irq(unsigned int irq) hard_local_irq_restore(flags); } +static void bfin_internal_mask_irq_chip(struct irq_data *d) +{ + bfin_internal_mask_irq(d->irq); +} + #ifdef CONFIG_SMP static void bfin_internal_unmask_irq_affinity(unsigned int irq, const struct cpumask *affinity) @@ -211,19 +217,24 @@ static void bfin_internal_unmask_irq(unsigned int irq) } #ifdef CONFIG_SMP -static void bfin_internal_unmask_irq(unsigned int irq) +static void bfin_internal_unmask_irq_chip(struct irq_data *d) { - struct irq_desc *desc = irq_to_desc(irq); - bfin_internal_unmask_irq_affinity(irq, desc->affinity); + bfin_internal_unmask_irq_affinity(d->irq, d->affinity); } -static int bfin_internal_set_affinity(unsigned int irq, const struct cpumask *mask) +static int bfin_internal_set_affinity(struct irq_data *d, + const struct cpumask *mask, bool force) { - bfin_internal_mask_irq(irq); - bfin_internal_unmask_irq_affinity(irq, mask); + bfin_internal_mask_irq(d->irq); + bfin_internal_unmask_irq_affinity(d->irq, mask); return 0; } +#else +static void bfin_internal_unmask_irq_chip(struct irq_data *d) +{ + bfin_internal_unmask_irq(d->irq); +} #endif #ifdef CONFIG_PM @@ -279,28 +290,33 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state) return 0; } + +static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state) +{ + return bfin_internal_set_wake(d->irq, state); +} #endif static struct irq_chip bfin_core_irqchip = { .name = "CORE", - .ack = bfin_ack_noop, - .mask = bfin_core_mask_irq, - .unmask = bfin_core_unmask_irq, + .irq_ack = bfin_ack_noop, + .irq_mask = bfin_core_mask_irq, + .irq_unmask = bfin_core_unmask_irq, }; static struct irq_chip bfin_internal_irqchip = { .name = "INTN", - .ack = bfin_ack_noop, - .mask = bfin_internal_mask_irq, - .unmask = bfin_internal_unmask_irq, - .mask_ack = bfin_internal_mask_irq, - .disable = bfin_internal_mask_irq, - .enable = bfin_internal_unmask_irq, + .irq_ack = bfin_ack_noop, + .irq_mask = bfin_internal_mask_irq_chip, + .irq_unmask = bfin_internal_unmask_irq_chip, + .irq_mask_ack = bfin_internal_mask_irq_chip, + .irq_disable = bfin_internal_mask_irq_chip, + .irq_enable = bfin_internal_unmask_irq_chip, #ifdef CONFIG_SMP - .set_affinity = bfin_internal_set_affinity, + .irq_set_affinity = bfin_internal_set_affinity, #endif #ifdef CONFIG_PM - .set_wake = bfin_internal_set_wake, + .irq_set_wake = bfin_internal_set_wake_chip, #endif }; @@ -312,33 +328,32 @@ static void bfin_handle_irq(unsigned irq) __ipipe_handle_irq(irq, ®s); ipipe_trace_irq_exit(irq); #else /* !CONFIG_IPIPE */ - struct irq_desc *desc = irq_desc + irq; - desc->handle_irq(irq, desc); + generic_handle_irq(irq); #endif /* !CONFIG_IPIPE */ } #ifdef BF537_GENERIC_ERROR_INT_DEMUX static int error_int_mask; -static void bfin_generic_error_mask_irq(unsigned int irq) +static void bfin_generic_error_mask_irq(struct irq_data *d) { - error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR)); + error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR)); if (!error_int_mask) bfin_internal_mask_irq(IRQ_GENERIC_ERROR); } -static void bfin_generic_error_unmask_irq(unsigned int irq) +static void bfin_generic_error_unmask_irq(struct irq_data *d) { bfin_internal_unmask_irq(IRQ_GENERIC_ERROR); - error_int_mask |= 1L << (irq - IRQ_PPI_ERROR); + error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR); } static struct irq_chip bfin_generic_error_irqchip = { .name = "ERROR", - .ack = bfin_ack_noop, - .mask_ack = bfin_generic_error_mask_irq, - .mask = bfin_generic_error_mask_irq, - .unmask = bfin_generic_error_unmask_irq, + .irq_ack = bfin_ack_noop, + .irq_mask_ack = bfin_generic_error_mask_irq, + .irq_mask = bfin_generic_error_mask_irq, + .irq_unmask = bfin_generic_error_unmask_irq, }; static void bfin_demux_error_irq(unsigned int int_err_irq, @@ -448,8 +463,10 @@ static void bfin_mac_status_ack_irq(unsigned int irq) } } -static void bfin_mac_status_mask_irq(unsigned int irq) +static void bfin_mac_status_mask_irq(struct irq_data *d) { + unsigned int irq = d->irq; + mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT)); #ifdef BF537_GENERIC_ERROR_INT_DEMUX switch (irq) { @@ -466,8 +483,10 @@ static void bfin_mac_status_mask_irq(unsigned int irq) bfin_mac_status_ack_irq(irq); } -static void bfin_mac_status_unmask_irq(unsigned int irq) +static void bfin_mac_status_unmask_irq(struct irq_data *d) { + unsigned int irq = d->irq; + #ifdef BF537_GENERIC_ERROR_INT_DEMUX switch (irq) { case IRQ_MAC_PHYINT: @@ -484,7 +503,7 @@ static void bfin_mac_status_unmask_irq(unsigned int irq) } #ifdef CONFIG_PM -int bfin_mac_status_set_wake(unsigned int irq, unsigned int state) +int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state) { #ifdef BF537_GENERIC_ERROR_INT_DEMUX return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state); @@ -496,12 +515,12 @@ int bfin_mac_status_set_wake(unsigned int irq, unsigned int state) static struct irq_chip bfin_mac_status_irqchip = { .name = "MACST", - .ack = bfin_ack_noop, - .mask_ack = bfin_mac_status_mask_irq, - .mask = bfin_mac_status_mask_irq, - .unmask = bfin_mac_status_unmask_irq, + .irq_ack = bfin_ack_noop, + .irq_mask_ack = bfin_mac_status_mask_irq, + .irq_mask = bfin_mac_status_mask_irq, + .irq_unmask = bfin_mac_status_unmask_irq, #ifdef CONFIG_PM - .set_wake = bfin_mac_status_set_wake, + .irq_set_wake = bfin_mac_status_set_wake, #endif }; @@ -538,13 +557,9 @@ static void bfin_demux_mac_status_irq(unsigned int int_err_irq, static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) { #ifdef CONFIG_IPIPE - _set_irq_handler(irq, handle_level_irq); -#else - struct irq_desc *desc = irq_desc + irq; - /* May not call generic set_irq_handler() due to spinlock - recursion. */ - desc->handle_irq = handle; + handle = handle_level_irq; #endif + __irq_set_handler_locked(irq, handle); } static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); @@ -552,58 +567,59 @@ extern void bfin_gpio_irq_prepare(unsigned gpio); #if !defined(CONFIG_BF54x) -static void bfin_gpio_ack_irq(unsigned int irq) +static void bfin_gpio_ack_irq(struct irq_data *d) { /* AFAIK ack_irq in case mask_ack is provided * get's only called for edge sense irqs */ - set_gpio_data(irq_to_gpio(irq), 0); + set_gpio_data(irq_to_gpio(d->irq), 0); } -static void bfin_gpio_mask_ack_irq(unsigned int irq) +static void bfin_gpio_mask_ack_irq(struct irq_data *d) { - struct irq_desc *desc = irq_desc + irq; + unsigned int irq = d->irq; u32 gpionr = irq_to_gpio(irq); - if (desc->handle_irq == handle_edge_irq) + if (!irqd_is_level_type(d)) set_gpio_data(gpionr, 0); set_gpio_maska(gpionr, 0); } -static void bfin_gpio_mask_irq(unsigned int irq) +static void bfin_gpio_mask_irq(struct irq_data *d) { - set_gpio_maska(irq_to_gpio(irq), 0); + set_gpio_maska(irq_to_gpio(d->irq), 0); } -static void bfin_gpio_unmask_irq(unsigned int irq) +static void bfin_gpio_unmask_irq(struct irq_data *d) { - set_gpio_maska(irq_to_gpio(irq), 1); + set_gpio_maska(irq_to_gpio(d->irq), 1); } -static unsigned int bfin_gpio_irq_startup(unsigned int irq) +static unsigned int bfin_gpio_irq_startup(struct irq_data *d) { - u32 gpionr = irq_to_gpio(irq); + u32 gpionr = irq_to_gpio(d->irq); if (__test_and_set_bit(gpionr, gpio_enabled)) bfin_gpio_irq_prepare(gpionr); - bfin_gpio_unmask_irq(irq); + bfin_gpio_unmask_irq(d); return 0; } -static void bfin_gpio_irq_shutdown(unsigned int irq) +static void bfin_gpio_irq_shutdown(struct irq_data *d) { - u32 gpionr = irq_to_gpio(irq); + u32 gpionr = irq_to_gpio(d->irq); - bfin_gpio_mask_irq(irq); + bfin_gpio_mask_irq(d); __clear_bit(gpionr, gpio_enabled); bfin_gpio_irq_free(gpionr); } -static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) +static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type) { + unsigned int irq = d->irq; int ret; char buf[16]; u32 gpionr = irq_to_gpio(irq); @@ -664,9 +680,9 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) } #ifdef CONFIG_PM -int bfin_gpio_set_wake(unsigned int irq, unsigned int state) +int bfin_gpio_set_wake(struct irq_data *d, unsigned int state) { - return gpio_pm_wakeup_ctrl(irq_to_gpio(irq), state); + return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state); } #endif @@ -818,14 +834,13 @@ void init_pint_lut(void) } } -static void bfin_gpio_ack_irq(unsigned int irq) +static void bfin_gpio_ack_irq(struct irq_data *d) { - struct irq_desc *desc = irq_desc + irq; - u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; + u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; u32 pintbit = PINT_BIT(pint_val); u32 bank = PINT_2_BANK(pint_val); - if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { + if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { if (pint[bank]->invert_set & pintbit) pint[bank]->invert_clear = pintbit; else @@ -835,14 +850,13 @@ static void bfin_gpio_ack_irq(unsigned int irq) } -static void bfin_gpio_mask_ack_irq(unsigned int irq) +static void bfin_gpio_mask_ack_irq(struct irq_data *d) { - struct irq_desc *desc = irq_desc + irq; - u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; + u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; u32 pintbit = PINT_BIT(pint_val); u32 bank = PINT_2_BANK(pint_val); - if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { + if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { if (pint[bank]->invert_set & pintbit) pint[bank]->invert_clear = pintbit; else @@ -853,24 +867,25 @@ static void bfin_gpio_mask_ack_irq(unsigned int irq) pint[bank]->mask_clear = pintbit; } -static void bfin_gpio_mask_irq(unsigned int irq) +static void bfin_gpio_mask_irq(struct irq_data *d) { - u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; + u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val); } -static void bfin_gpio_unmask_irq(unsigned int irq) +static void bfin_gpio_unmask_irq(struct irq_data *d) { - u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; + u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; u32 pintbit = PINT_BIT(pint_val); u32 bank = PINT_2_BANK(pint_val); pint[bank]->mask_set = pintbit; } -static unsigned int bfin_gpio_irq_startup(unsigned int irq) +static unsigned int bfin_gpio_irq_startup(struct irq_data *d) { + unsigned int irq = d->irq; u32 gpionr = irq_to_gpio(irq); u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; @@ -884,22 +899,23 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq) if (__test_and_set_bit(gpionr, gpio_enabled)) bfin_gpio_irq_prepare(gpionr); - bfin_gpio_unmask_irq(irq); + bfin_gpio_unmask_irq(d); return 0; } -static void bfin_gpio_irq_shutdown(unsigned int irq) +static void bfin_gpio_irq_shutdown(struct irq_data *d) { - u32 gpionr = irq_to_gpio(irq); + u32 gpionr = irq_to_gpio(d->irq); - bfin_gpio_mask_irq(irq); + bfin_gpio_mask_irq(d); __clear_bit(gpionr, gpio_enabled); bfin_gpio_irq_free(gpionr); } -static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) +static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type) { + unsigned int irq = d->irq; int ret; char buf[16]; u32 gpionr = irq_to_gpio(irq); @@ -961,10 +977,10 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) u32 pint_saved_masks[NR_PINT_SYS_IRQS]; u32 pint_wakeup_masks[NR_PINT_SYS_IRQS]; -int bfin_gpio_set_wake(unsigned int irq, unsigned int state) +int bfin_gpio_set_wake(struct irq_data *d, unsigned int state) { u32 pint_irq; - u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; + u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; u32 bank = PINT_2_BANK(pint_val); u32 pintbit = PINT_BIT(pint_val); @@ -1066,17 +1082,17 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq, static struct irq_chip bfin_gpio_irqchip = { .name = "GPIO", - .ack = bfin_gpio_ack_irq, - .mask = bfin_gpio_mask_irq, - .mask_ack = bfin_gpio_mask_ack_irq, - .unmask = bfin_gpio_unmask_irq, - .disable = bfin_gpio_mask_irq, - .enable = bfin_gpio_unmask_irq, - .set_type = bfin_gpio_irq_type, - .startup = bfin_gpio_irq_startup, - .shutdown = bfin_gpio_irq_shutdown, + .irq_ack = bfin_gpio_ack_irq, + .irq_mask = bfin_gpio_mask_irq, + .irq_mask_ack = bfin_gpio_mask_ack_irq, + .irq_unmask = bfin_gpio_unmask_irq, + .irq_disable = bfin_gpio_mask_irq, + .irq_enable = bfin_gpio_unmask_irq, + .irq_set_type = bfin_gpio_irq_type, + .irq_startup = bfin_gpio_irq_startup, + .irq_shutdown = bfin_gpio_irq_shutdown, #ifdef CONFIG_PM - .set_wake = bfin_gpio_set_wake, + .irq_set_wake = bfin_gpio_set_wake, #endif }; @@ -1147,9 +1163,9 @@ int __init init_arch_irq(void) for (irq = 0; irq <= SYS_IRQS; irq++) { if (irq <= IRQ_CORETMR) - set_irq_chip(irq, &bfin_core_irqchip); + irq_set_chip(irq, &bfin_core_irqchip); else - set_irq_chip(irq, &bfin_internal_irqchip); + irq_set_chip(irq, &bfin_internal_irqchip); switch (irq) { #if defined(CONFIG_BF53x) @@ -1173,50 +1189,50 @@ int __init init_arch_irq(void) #elif defined(CONFIG_BF538) || defined(CONFIG_BF539) case IRQ_PORTF_INTA: #endif - set_irq_chained_handler(irq, - bfin_demux_gpio_irq); + irq_set_chained_handler(irq, bfin_demux_gpio_irq); break; #ifdef BF537_GENERIC_ERROR_INT_DEMUX case IRQ_GENERIC_ERROR: - set_irq_chained_handler(irq, bfin_demux_error_irq); + irq_set_chained_handler(irq, bfin_demux_error_irq); break; #endif #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) case IRQ_MAC_ERROR: - set_irq_chained_handler(irq, bfin_demux_mac_status_irq); + irq_set_chained_handler(irq, + bfin_demux_mac_status_irq); break; #endif #ifdef CONFIG_SMP case IRQ_SUPPLE_0: case IRQ_SUPPLE_1: - set_irq_handler(irq, handle_percpu_irq); + irq_set_handler(irq, handle_percpu_irq); break; #endif #ifdef CONFIG_TICKSOURCE_CORETMR case IRQ_CORETMR: # ifdef CONFIG_SMP - set_irq_handler(irq, handle_percpu_irq); + irq_set_handler(irq, handle_percpu_irq); break; # else - set_irq_handler(irq, handle_simple_irq); + irq_set_handler(irq, handle_simple_irq); break; # endif #endif #ifdef CONFIG_TICKSOURCE_GPTMR0 case IRQ_TIMER0: - set_irq_handler(irq, handle_simple_irq); + irq_set_handler(irq, handle_simple_irq); break; #endif #ifdef CONFIG_IPIPE default: - set_irq_handler(irq, handle_level_irq); + irq_set_handler(irq, handle_level_irq); break; #else /* !CONFIG_IPIPE */ default: - set_irq_handler(irq, handle_simple_irq); + irq_set_handler(irq, handle_simple_irq); break; #endif /* !CONFIG_IPIPE */ } @@ -1224,22 +1240,22 @@ int __init init_arch_irq(void) #ifdef BF537_GENERIC_ERROR_INT_DEMUX for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) - set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip, + irq_set_chip_and_handler(irq, &bfin_generic_error_irqchip, handle_level_irq); #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) - set_irq_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq); + irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq); #endif #endif #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++) - set_irq_chip_and_handler(irq, &bfin_mac_status_irqchip, + irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip, handle_level_irq); #endif /* if configured as edge, then will be changed to do_edge_IRQ */ for (irq = GPIO_IRQ_BASE; irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) - set_irq_chip_and_handler(irq, &bfin_gpio_irqchip, + irq_set_chip_and_handler(irq, &bfin_gpio_irqchip, handle_level_irq); bfin_write_IMASK(0); @@ -1373,7 +1389,7 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) struct ipipe_domain *this_domain = __ipipe_current_domain; struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; - int irq, s; + int irq, s = 0; if (likely(vec == EVT_IVTMR_P)) irq = IRQ_CORETMR; @@ -1423,6 +1439,21 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10; } + /* + * We don't want Linux interrupt handlers to run at the + * current core priority level (i.e. < EVT15), since this + * might delay other interrupts handled by a high priority + * domain. Here is what we do instead: + * + * - we raise the SYNCDEFER bit to prevent + * __ipipe_handle_irq() to sync the pipeline for the root + * stage for the incoming interrupt. Upon return, that IRQ is + * pending in the interrupt log. + * + * - we raise the TIF_IRQ_SYNC bit for the current thread, so + * that _schedule_and_signal_from_int will eventually sync the + * pipeline from EVT15. + */ if (this_domain == ipipe_root_domain) { s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status); barrier(); @@ -1432,6 +1463,24 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) __ipipe_handle_irq(irq, regs); ipipe_trace_irq_exit(irq); + if (user_mode(regs) && + !ipipe_test_foreign_stack() && + (current->ipipe_flags & PF_EVTRET) != 0) { + /* + * Testing for user_regs() does NOT fully eliminate + * foreign stack contexts, because of the forged + * interrupt returns we do through + * __ipipe_call_irqtail. In that case, we might have + * preempted a foreign stack context in a high + * priority domain, with a single interrupt level now + * pending after the irqtail unwinding is done. In + * which case user_mode() is now true, and the event + * gets dispatched spuriously. + */ + current->ipipe_flags &= ~PF_EVTRET; + __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs); + } + if (this_domain == ipipe_root_domain) { set_thread_flag(TIF_IRQ_SYNC); if (!s) { diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c index 9f251406a76..8bce5ed031e 100644 --- a/arch/blackfin/mach-common/smp.c +++ b/arch/blackfin/mach-common/smp.c @@ -40,6 +40,10 @@ */ struct corelock_slot corelock __attribute__ ((__section__(".l2.bss"))); +#ifdef CONFIG_ICACHE_FLUSH_L1 +unsigned long blackfin_iflush_l1_entry[NR_CPUS]; +#endif + void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb, *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb, *init_saved_dcplb_fault_addr_coreb; @@ -108,6 +112,19 @@ static void ipi_flush_icache(void *info) blackfin_dcache_invalidate_range((unsigned long)fdata, (unsigned long)fdata + sizeof(*fdata)); + /* Make sure all write buffers in the data side of the core + * are flushed before trying to invalidate the icache. This + * needs to be after the data flush and before the icache + * flush so that the SSYNC does the right thing in preventing + * the instruction prefetcher from hitting things in cached + * memory at the wrong time -- it runs much further ahead than + * the pipeline. + */ + SSYNC(); + + /* ipi_flaush_icache is invoked by generic flush_icache_range, + * so call blackfin arch icache flush directly here. + */ blackfin_icache_flush_range(fdata->start, fdata->end); } @@ -244,12 +261,13 @@ int smp_call_function(void (*func)(void *info), void *info, int wait) { cpumask_t callmap; + preempt_disable(); callmap = cpu_online_map; cpu_clear(smp_processor_id(), callmap); - if (cpus_empty(callmap)) - return 0; + if (!cpus_empty(callmap)) + smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait); - smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait); + preempt_enable(); return 0; } @@ -286,12 +304,13 @@ void smp_send_stop(void) { cpumask_t callmap; + preempt_disable(); callmap = cpu_online_map; cpu_clear(smp_processor_id(), callmap); - if (cpus_empty(callmap)) - return; + if (!cpus_empty(callmap)) + smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0); - smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0); + preempt_enable(); return; } @@ -361,8 +380,6 @@ void __cpuinit secondary_start_kernel(void) */ init_exception_vectors(); - bfin_setup_caches(cpu); - local_irq_disable(); /* Attach the new idle task to the global mm. */ @@ -381,6 +398,8 @@ void __cpuinit secondary_start_kernel(void) local_irq_enable(); + bfin_setup_caches(cpu); + /* * Calibrate loops per jiffy value. * IRQs need to be enabled here - D-cache can be invalidated diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig index 4db5b46e1ef..a6d03069d0f 100644 --- a/arch/cris/Kconfig +++ b/arch/cris/Kconfig @@ -55,7 +55,6 @@ config CRIS default y select HAVE_IDE select HAVE_GENERIC_HARDIRQS - select GENERIC_HARDIRQS_NO_DEPRECATED select GENERIC_IRQ_SHOW config HZ @@ -276,7 +275,6 @@ config ETRAX_AXISFLASHMAP select MTD_CHAR select MTD_BLOCK select MTD_PARTITIONS - select MTD_CONCAT select MTD_COMPLEX_MAPPINGS help This option enables MTD mapping of flash devices. Needed to use @@ -297,8 +295,7 @@ config ETRAX_RTC choice prompt "RTC chip" depends on ETRAX_RTC - default ETRAX_PCF8563 if ETRAX_ARCH_V32 - default ETRAX_DS1302 if ETRAX_ARCH_V10 + default ETRAX_DS1302 config ETRAX_DS1302 depends on ETRAX_ARCH_V10 diff --git a/arch/cris/arch-v10/README.mm b/arch/cris/arch-v10/README.mm index 517d1f027fe..67731d75cb5 100644 --- a/arch/cris/arch-v10/README.mm +++ b/arch/cris/arch-v10/README.mm @@ -38,7 +38,7 @@ space. We also use it to keep the user-mode virtual mapping in the same map during kernel-mode, so that the kernel easily can access the corresponding user-mode process' data. -As a comparision, the Linux/i386 2.0 puts the kernel and physical RAM at +As a comparison, the Linux/i386 2.0 puts the kernel and physical RAM at address 0, overlapping with the user-mode virtual space, so that descriptor registers are needed for each memory access to specify which MMU space to map through. That changed in 2.2, putting the kernel/physical RAM at diff --git a/arch/cris/arch-v10/drivers/axisflashmap.c b/arch/cris/arch-v10/drivers/axisflashmap.c index b2079703af7..ed708e19d09 100644 --- a/arch/cris/arch-v10/drivers/axisflashmap.c +++ b/arch/cris/arch-v10/drivers/axisflashmap.c @@ -234,7 +234,6 @@ static struct mtd_info *flash_probe(void) } if (mtd_cse0 && mtd_cse1) { -#ifdef CONFIG_MTD_CONCAT struct mtd_info *mtds[] = { mtd_cse0, mtd_cse1 }; /* Since the concatenation layer adds a small overhead we @@ -246,11 +245,6 @@ static struct mtd_info *flash_probe(void) */ mtd_cse = mtd_concat_create(mtds, ARRAY_SIZE(mtds), "cse0+cse1"); -#else - printk(KERN_ERR "%s and %s: Cannot concatenate due to kernel " - "(mis)configuration!\n", map_cse0.name, map_cse1.name); - mtd_cse = NULL; -#endif if (!mtd_cse) { printk(KERN_ERR "%s and %s: Concatenation failed!\n", map_cse0.name, map_cse1.name); diff --git a/arch/cris/arch-v10/drivers/pcf8563.c b/arch/cris/arch-v10/drivers/pcf8563.c index ea69faba9b6..1391b731ad1 100644 --- a/arch/cris/arch-v10/drivers/pcf8563.c +++ b/arch/cris/arch-v10/drivers/pcf8563.c @@ -345,7 +345,7 @@ static long pcf8563_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned int ret; mutex_lock(&pcf8563_mutex); - return pcf8563_ioctl(filp, cmd, arg); + ret = pcf8563_ioctl(filp, cmd, arg); mutex_unlock(&pcf8563_mutex); return ret; diff --git a/arch/cris/arch-v10/drivers/sync_serial.c b/arch/cris/arch-v10/drivers/sync_serial.c index 399dc1ec8e6..85026537361 100644 --- a/arch/cris/arch-v10/drivers/sync_serial.c +++ b/arch/cris/arch-v10/drivers/sync_serial.c @@ -31,7 +31,7 @@ #include <asm/sync_serial.h> #include <arch/io_interface_mux.h> -/* The receiver is a bit tricky beacuse of the continuous stream of data.*/ +/* The receiver is a bit tricky because of the continuous stream of data.*/ /* */ /* Three DMA descriptors are linked together. Each DMA descriptor is */ /* responsible for port->bufchunk of a common buffer. */ diff --git a/arch/cris/arch-v10/kernel/signal.c b/arch/cris/arch-v10/kernel/signal.c index b6be705c2a3..e78fe49a984 100644 --- a/arch/cris/arch-v10/kernel/signal.c +++ b/arch/cris/arch-v10/kernel/signal.c @@ -537,7 +537,7 @@ void do_signal(int canrestart, struct pt_regs *regs) RESTART_CRIS_SYS(regs); } if (regs->r10 == -ERESTART_RESTARTBLOCK) { - regs->r10 = __NR_restart_syscall; + regs->r9 = __NR_restart_syscall; regs->irp -= 2; } } diff --git a/arch/cris/arch-v32/drivers/Kconfig b/arch/cris/arch-v32/drivers/Kconfig index a2dd740c590..1633b120aa8 100644 --- a/arch/cris/arch-v32/drivers/Kconfig +++ b/arch/cris/arch-v32/drivers/Kconfig @@ -406,7 +406,6 @@ config ETRAX_AXISFLASHMAP select MTD_CHAR select MTD_BLOCK select MTD_PARTITIONS - select MTD_CONCAT select MTD_COMPLEX_MAPPINGS help This option enables MTD mapping of flash devices. Needed to use diff --git a/arch/cris/arch-v32/drivers/Makefile b/arch/cris/arch-v32/drivers/Makefile index e8c02437eda..39aa3c117a8 100644 --- a/arch/cris/arch-v32/drivers/Makefile +++ b/arch/cris/arch-v32/drivers/Makefile @@ -7,7 +7,6 @@ obj-$(CONFIG_ETRAX_AXISFLASHMAP) += axisflashmap.o obj-$(CONFIG_ETRAXFS) += mach-fs/ obj-$(CONFIG_CRIS_MACH_ARTPEC3) += mach-a3/ obj-$(CONFIG_ETRAX_IOP_FW_LOAD) += iop_fw_load.o -obj-$(CONFIG_ETRAX_PCF8563) += pcf8563.o obj-$(CONFIG_ETRAX_I2C) += i2c.o obj-$(CONFIG_ETRAX_SYNCHRONOUS_SERIAL) += sync_serial.o obj-$(CONFIG_PCI) += pci/ diff --git a/arch/cris/arch-v32/drivers/axisflashmap.c b/arch/cris/arch-v32/drivers/axisflashmap.c index 51e1e85df96..7b155f8203b 100644 --- a/arch/cris/arch-v32/drivers/axisflashmap.c +++ b/arch/cris/arch-v32/drivers/axisflashmap.c @@ -215,7 +215,7 @@ static struct mtd_partition main_partition = { }; #endif -/* Auxilliary partition if we find another flash */ +/* Auxiliary partition if we find another flash */ static struct mtd_partition aux_partition = { .name = "aux", .size = 0, @@ -275,7 +275,6 @@ static struct mtd_info *flash_probe(void) } if (count > 1) { -#ifdef CONFIG_MTD_CONCAT /* Since the concatenation layer adds a small overhead we * could try to figure out if the chips in cse0 and cse1 are * identical and reprobe the whole cse0+cse1 window. But since @@ -284,11 +283,6 @@ static struct mtd_info *flash_probe(void) * complicating the probing procedure. */ mtd_total = mtd_concat_create(mtds, count, "cse0+cse1"); -#else - printk(KERN_ERR "%s and %s: Cannot concatenate due to kernel " - "(mis)configuration!\n", map_cse0.name, map_cse1.name); - mtd_toal = NULL; -#endif if (!mtd_total) { printk(KERN_ERR "%s and %s: Concatenation failed!\n", map_cse0.name, map_cse1.name); diff --git a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c index 25d6f2b3a72..f58f2c1c529 100644 --- a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c +++ b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c @@ -165,7 +165,7 @@ struct mtd_info *__init crisv32_nand_flash_probe(void) /* Enable the following for a flash based bad block table */ /* this->options = NAND_USE_FLASH_BBT; */ - /* Scan to find existance of the device */ + /* Scan to find existence of the device */ if (nand_scan(crisv32_mtd, 1)) { err = -ENXIO; goto out_mtd; diff --git a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c index c5a0f54763c..d5b0cc9f976 100644 --- a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c +++ b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c @@ -156,7 +156,7 @@ struct mtd_info *__init crisv32_nand_flash_probe(void) /* Enable the following for a flash based bad block table */ /* this->options = NAND_USE_FLASH_BBT; */ - /* Scan to find existance of the device */ + /* Scan to find existence of the device */ if (nand_scan(crisv32_mtd, 1)) { err = -ENXIO; goto out_ior; diff --git a/arch/cris/arch-v32/drivers/pcf8563.c b/arch/cris/arch-v32/drivers/pcf8563.c deleted file mode 100644 index b6e4fc0aad4..00000000000 --- a/arch/cris/arch-v32/drivers/pcf8563.c +++ /dev/null @@ -1,377 +0,0 @@ -/* - * PCF8563 RTC - * - * From Phillips' datasheet: - * - * The PCF8563 is a CMOS real-time clock/calendar optimized for low power - * consumption. A programmable clock output, interrupt output and voltage - * low detector are also provided. All address and data are transferred - * serially via two-line bidirectional I2C-bus. Maximum bus speed is - * 400 kbits/s. The built-in word address register is incremented - * automatically after each written or read byte. - * - * Copyright (c) 2002-2007, Axis Communications AB - * All rights reserved. - * - * Author: Tobias Anderberg <tobiasa@axis.com>. - * - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/sched.h> -#include <linux/init.h> -#include <linux/fs.h> -#include <linux/ioctl.h> -#include <linux/delay.h> -#include <linux/bcd.h> -#include <linux/mutex.h> - -#include <asm/uaccess.h> -#include <asm/system.h> -#include <asm/io.h> -#include <asm/rtc.h> - -#include "i2c.h" - -#define PCF8563_MAJOR 121 /* Local major number. */ -#define DEVICE_NAME "rtc" /* Name which is registered in /proc/devices. */ -#define PCF8563_NAME "PCF8563" -#define DRIVER_VERSION "$Revision: 1.17 $" - -/* Two simple wrapper macros, saves a few keystrokes. */ -#define rtc_read(x) i2c_readreg(RTC_I2C_READ, x) -#define rtc_write(x,y) i2c_writereg(RTC_I2C_WRITE, x, y) - -static DEFINE_MUTEX(pcf8563_mutex); -static DEFINE_MUTEX(rtc_lock); /* Protect state etc */ - -static const unsigned char days_in_month[] = - { 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; - -static long pcf8563_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); - -/* Cache VL bit value read at driver init since writing the RTC_SECOND - * register clears the VL status. - */ -static int voltage_low; - -static const struct file_operations pcf8563_fops = { - .owner = THIS_MODULE, - .unlocked_ioctl = pcf8563_unlocked_ioctl, - .llseek = noop_llseek, -}; - -unsigned char -pcf8563_readreg(int reg) -{ - unsigned char res = rtc_read(reg); - - /* The PCF8563 does not return 0 for unimplemented bits. */ - switch (reg) { - case RTC_SECONDS: - case RTC_MINUTES: - res &= 0x7F; - break; - case RTC_HOURS: - case RTC_DAY_OF_MONTH: - res &= 0x3F; - break; - case RTC_WEEKDAY: - res &= 0x07; - break; - case RTC_MONTH: - res &= 0x1F; - break; - case RTC_CONTROL1: - res &= 0xA8; - break; - case RTC_CONTROL2: - res &= 0x1F; - break; - case RTC_CLOCKOUT_FREQ: - case RTC_TIMER_CONTROL: - res &= 0x83; - break; - } - return res; -} - -void -pcf8563_writereg(int reg, unsigned char val) -{ - rtc_write(reg, val); -} - -void -get_rtc_time(struct rtc_time *tm) -{ - tm->tm_sec = rtc_read(RTC_SECONDS); - tm->tm_min = rtc_read(RTC_MINUTES); - tm->tm_hour = rtc_read(RTC_HOURS); - tm->tm_mday = rtc_read(RTC_DAY_OF_MONTH); - tm->tm_wday = rtc_read(RTC_WEEKDAY); - tm->tm_mon = rtc_read(RTC_MONTH); - tm->tm_year = rtc_read(RTC_YEAR); - - if (tm->tm_sec & 0x80) { - printk(KERN_ERR "%s: RTC Voltage Low - reliable date/time " - "information is no longer guaranteed!\n", PCF8563_NAME); - } - - tm->tm_year = bcd2bin(tm->tm_year) + - ((tm->tm_mon & 0x80) ? 100 : 0); - tm->tm_sec &= 0x7F; - tm->tm_min &= 0x7F; - tm->tm_hour &= 0x3F; - tm->tm_mday &= 0x3F; - tm->tm_wday &= 0x07; /* Not coded in BCD. */ - tm->tm_mon &= 0x1F; - - tm->tm_sec = bcd2bin(tm->tm_sec); - tm->tm_min = bcd2bin(tm->tm_min); - tm->tm_hour = bcd2bin(tm->tm_hour); - tm->tm_mday = bcd2bin(tm->tm_mday); - tm->tm_mon = bcd2bin(tm->tm_mon); - tm->tm_mon--; /* Month is 1..12 in RTC but 0..11 in linux */ -} - -int __init -pcf8563_init(void) -{ - static int res; - static int first = 1; - - if (!first) - return res; - first = 0; - - /* Initiate the i2c protocol. */ - res = i2c_init(); - if (res < 0) { - printk(KERN_CRIT "pcf8563_init: Failed to init i2c.\n"); - return res; - } - - /* - * First of all we need to reset the chip. This is done by - * clearing control1, control2 and clk freq and resetting - * all alarms. - */ - if (rtc_write(RTC_CONTROL1, 0x00) < 0) - goto err; - - if (rtc_write(RTC_CONTROL2, 0x00) < 0) - goto err; - - if (rtc_write(RTC_CLOCKOUT_FREQ, 0x00) < 0) - goto err; - - if (rtc_write(RTC_TIMER_CONTROL, 0x03) < 0) - goto err; - - /* Reset the alarms. */ - if (rtc_write(RTC_MINUTE_ALARM, 0x80) < 0) - goto err; - - if (rtc_write(RTC_HOUR_ALARM, 0x80) < 0) - goto err; - - if (rtc_write(RTC_DAY_ALARM, 0x80) < 0) - goto err; - - if (rtc_write(RTC_WEEKDAY_ALARM, 0x80) < 0) - goto err; - - /* Check for low voltage, and warn about it. */ - if (rtc_read(RTC_SECONDS) & 0x80) { - voltage_low = 1; - printk(KERN_WARNING "%s: RTC Voltage Low - reliable " - "date/time information is no longer guaranteed!\n", - PCF8563_NAME); - } - - return res; - -err: - printk(KERN_INFO "%s: Error initializing chip.\n", PCF8563_NAME); - res = -1; - return res; -} - -void __exit -pcf8563_exit(void) -{ - unregister_chrdev(PCF8563_MAJOR, DEVICE_NAME); -} - -/* - * ioctl calls for this driver. Why return -ENOTTY upon error? Because - * POSIX says so! - */ -static int pcf8563_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) -{ - /* Some sanity checks. */ - if (_IOC_TYPE(cmd) != RTC_MAGIC) - return -ENOTTY; - - if (_IOC_NR(cmd) > RTC_MAX_IOCTL) - return -ENOTTY; - - switch (cmd) { - case RTC_RD_TIME: - { - struct rtc_time tm; - - mutex_lock(&rtc_lock); - memset(&tm, 0, sizeof tm); - get_rtc_time(&tm); - - if (copy_to_user((struct rtc_time *) arg, &tm, - sizeof tm)) { - mutex_unlock(&rtc_lock); - return -EFAULT; - } - - mutex_unlock(&rtc_lock); - - return 0; - } - case RTC_SET_TIME: - { - int leap; - int year; - int century; - struct rtc_time tm; - - memset(&tm, 0, sizeof tm); - if (!capable(CAP_SYS_TIME)) - return -EPERM; - - if (copy_from_user(&tm, (struct rtc_time *) arg, - sizeof tm)) - return -EFAULT; - - /* Convert from struct tm to struct rtc_time. */ - tm.tm_year += 1900; - tm.tm_mon += 1; - - /* - * Check if tm.tm_year is a leap year. A year is a leap - * year if it is divisible by 4 but not 100, except - * that years divisible by 400 _are_ leap years. - */ - year = tm.tm_year; - leap = (tm.tm_mon == 2) && - ((year % 4 == 0 && year % 100 != 0) || year % 400 == 0); - - /* Perform some sanity checks. */ - if ((tm.tm_year < 1970) || - (tm.tm_mon > 12) || - (tm.tm_mday == 0) || - (tm.tm_mday > days_in_month[tm.tm_mon] + leap) || - (tm.tm_wday >= 7) || - (tm.tm_hour >= 24) || - (tm.tm_min >= 60) || - (tm.tm_sec >= 60)) - return -EINVAL; - - century = (tm.tm_year >= 2000) ? 0x80 : 0; - tm.tm_year = tm.tm_year % 100; - - tm.tm_year = bin2bcd(tm.tm_year); - tm.tm_mon = bin2bcd(tm.tm_mon); - tm.tm_mday = bin2bcd(tm.tm_mday); - tm.tm_hour = bin2bcd(tm.tm_hour); - tm.tm_min = bin2bcd(tm.tm_min); - tm.tm_sec = bin2bcd(tm.tm_sec); - tm.tm_mon |= century; - - mutex_lock(&rtc_lock); - - rtc_write(RTC_YEAR, tm.tm_year); - rtc_write(RTC_MONTH, tm.tm_mon); - rtc_write(RTC_WEEKDAY, tm.tm_wday); /* Not coded in BCD. */ - rtc_write(RTC_DAY_OF_MONTH, tm.tm_mday); - rtc_write(RTC_HOURS, tm.tm_hour); - rtc_write(RTC_MINUTES, tm.tm_min); - rtc_write(RTC_SECONDS, tm.tm_sec); - - mutex_unlock(&rtc_lock); - - return 0; - } - case RTC_VL_READ: - if (voltage_low) - printk(KERN_ERR "%s: RTC Voltage Low - " - "reliable date/time information is no " - "longer guaranteed!\n", PCF8563_NAME); - - if (copy_to_user((int *) arg, &voltage_low, sizeof(int))) - return -EFAULT; - return 0; - - case RTC_VL_CLR: - { - /* Clear the VL bit in the seconds register in case - * the time has not been set already (which would - * have cleared it). This does not really matter - * because of the cached voltage_low value but do it - * anyway for consistency. */ - - int ret = rtc_read(RTC_SECONDS); - - rtc_write(RTC_SECONDS, (ret & 0x7F)); - - /* Clear the cached value. */ - voltage_low = 0; - - return 0; - } - default: - return -ENOTTY; - } - - return 0; -} - -static long pcf8563_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) -{ - int ret; - - mutex_lock(&pcf8563_mutex); - return pcf8563_ioctl(filp, cmd, arg); - mutex_unlock(&pcf8563_mutex); - - return ret; -} - -static int __init pcf8563_register(void) -{ - if (pcf8563_init() < 0) { - printk(KERN_INFO "%s: Unable to initialize Real-Time Clock " - "Driver, %s\n", PCF8563_NAME, DRIVER_VERSION); - return -1; - } - - if (register_chrdev(PCF8563_MAJOR, DEVICE_NAME, &pcf8563_fops) < 0) { - printk(KERN_INFO "%s: Unable to get major numer %d for RTC " - "device.\n", PCF8563_NAME, PCF8563_MAJOR); - return -1; - } - - printk(KERN_INFO "%s Real-Time Clock Driver, %s\n", PCF8563_NAME, - DRIVER_VERSION); - - /* Check for low voltage, and warn about it. */ - if (voltage_low) { - printk(KERN_WARNING "%s: RTC Voltage Low - reliable date/time " - "information is no longer guaranteed!\n", PCF8563_NAME); - } - - return 0; -} - -module_init(pcf8563_register); -module_exit(pcf8563_exit); diff --git a/arch/cris/arch-v32/drivers/sync_serial.c b/arch/cris/arch-v32/drivers/sync_serial.c index c8637a9195e..a6a180bc566 100644 --- a/arch/cris/arch-v32/drivers/sync_serial.c +++ b/arch/cris/arch-v32/drivers/sync_serial.c @@ -33,7 +33,7 @@ #include <asm/sync_serial.h> -/* The receiver is a bit tricky beacuse of the continuous stream of data.*/ +/* The receiver is a bit tricky because of the continuous stream of data.*/ /* */ /* Three DMA descriptors are linked together. Each DMA descriptor is */ /* responsible for port->bufchunk of a common buffer. */ diff --git a/arch/cris/arch-v32/kernel/entry.S b/arch/cris/arch-v32/kernel/entry.S index 0ecb50b8f0d..3abf12c23e5 100644 --- a/arch/cris/arch-v32/kernel/entry.S +++ b/arch/cris/arch-v32/kernel/entry.S @@ -182,7 +182,7 @@ _syscall_traced: move.d $r0, [$sp] ;; The registers carrying parameters (R10-R13) are intact. The optional - ;; fifth and sixth parameters is in MOF and SRP respectivly. Put them + ;; fifth and sixth parameters is in MOF and SRP respectively. Put them ;; back on the stack. subq 4, $sp move $srp, [$sp] diff --git a/arch/cris/arch-v32/kernel/irq.c b/arch/cris/arch-v32/kernel/irq.c index 8023176e19b..68a1a5901ca 100644 --- a/arch/cris/arch-v32/kernel/irq.c +++ b/arch/cris/arch-v32/kernel/irq.c @@ -374,7 +374,7 @@ crisv32_do_multiple(struct pt_regs* regs) irq_enter(); for (i = 0; i < NBR_REGS; i++) { - /* Get which IRQs that happend. */ + /* Get which IRQs that happened. */ masked[i] = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], r_masked_vect, i); diff --git a/arch/cris/arch-v32/kernel/kgdb.c b/arch/cris/arch-v32/kernel/kgdb.c index 6b653323d79..c0343c3ea7f 100644 --- a/arch/cris/arch-v32/kernel/kgdb.c +++ b/arch/cris/arch-v32/kernel/kgdb.c @@ -925,7 +925,7 @@ stub_is_stopped(int sigval) if (reg.eda >= bp_d_regs[bp * 2] && reg.eda <= bp_d_regs[bp * 2 + 1]) { - /* EDA withing range for this BP; it must be the one + /* EDA within range for this BP; it must be the one we're looking for. */ stopped_data_address = reg.eda; break; diff --git a/arch/cris/arch-v32/kernel/process.c b/arch/cris/arch-v32/kernel/process.c index 562f8471890..0570e8ce603 100644 --- a/arch/cris/arch-v32/kernel/process.c +++ b/arch/cris/arch-v32/kernel/process.c @@ -149,7 +149,7 @@ copy_thread(unsigned long clone_flags, unsigned long usp, childregs->r10 = 0; /* Child returns 0 after a fork/clone. */ /* Set a new TLS ? - * The TLS is in $mof beacuse it is the 5th argument to sys_clone. + * The TLS is in $mof because it is the 5th argument to sys_clone. */ if (p->mm && (clone_flags & CLONE_SETTLS)) { task_thread_info(p)->tls = regs->mof; diff --git a/arch/cris/arch-v32/kernel/signal.c b/arch/cris/arch-v32/kernel/signal.c index b3a05ae5621..ce4ab1a5552 100644 --- a/arch/cris/arch-v32/kernel/signal.c +++ b/arch/cris/arch-v32/kernel/signal.c @@ -610,7 +610,7 @@ ugdb_trap_user(struct thread_info *ti, int sig) user_regs(ti)->spc = 0; } /* FIXME: Filter out false h/w breakpoint hits (i.e. EDA - not withing any configured h/w breakpoint range). Synchronize with + not within any configured h/w breakpoint range). Synchronize with what already exists for kernel debugging. */ if (((user_regs(ti)->exs & 0xff00) >> 8) == BREAK_8_INTR_VECT) { /* Break 8: subtract 2 from ERP unless in a delay slot. */ diff --git a/arch/cris/arch-v32/mach-a3/arbiter.c b/arch/cris/arch-v32/mach-a3/arbiter.c index 8b924db71c9..15f5c9de263 100644 --- a/arch/cris/arch-v32/mach-a3/arbiter.c +++ b/arch/cris/arch-v32/mach-a3/arbiter.c @@ -568,7 +568,7 @@ crisv32_foo_arbiter_irq(int irq, void *dev_id) REG_WR(marb_foo_bp, watch->instance, rw_ack, ack); REG_WR(marb_foo, regi_marb_foo, rw_ack_intr, ack_intr); - printk(KERN_DEBUG "IRQ occured at %X\n", (unsigned)get_irq_regs()); + printk(KERN_DEBUG "IRQ occurred at %X\n", (unsigned)get_irq_regs()); if (watch->cb) watch->cb(); @@ -624,7 +624,7 @@ crisv32_bar_arbiter_irq(int irq, void *dev_id) REG_WR(marb_bar_bp, watch->instance, rw_ack, ack); REG_WR(marb_bar, regi_marb_bar, rw_ack_intr, ack_intr); - printk(KERN_DEBUG "IRQ occured at %X\n", (unsigned)get_irq_regs()->erp); + printk(KERN_DEBUG "IRQ occurred at %X\n", (unsigned)get_irq_regs()->erp); if (watch->cb) watch->cb(); diff --git a/arch/cris/arch-v32/mach-fs/arbiter.c b/arch/cris/arch-v32/mach-fs/arbiter.c index 82ef293c4c8..3f8ebb5c147 100644 --- a/arch/cris/arch-v32/mach-fs/arbiter.c +++ b/arch/cris/arch-v32/mach-fs/arbiter.c @@ -395,7 +395,7 @@ static irqreturn_t crisv32_arbiter_irq(int irq, void *dev_id) REG_WR(marb_bp, watch->instance, rw_ack, ack); REG_WR(marb, regi_marb, rw_ack_intr, ack_intr); - printk(KERN_INFO "IRQ occured at %lX\n", get_irq_regs()->erp); + printk(KERN_INFO "IRQ occurred at %lX\n", get_irq_regs()->erp); if (watch->cb) watch->cb(); diff --git a/arch/cris/boot/rescue/head_v10.S b/arch/cris/boot/rescue/head_v10.S index 2fafe247a25..af55df0994b 100644 --- a/arch/cris/boot/rescue/head_v10.S +++ b/arch/cris/boot/rescue/head_v10.S @@ -7,7 +7,7 @@ * for each partition that this code should check. * * If any of the checksums fail, we assume the flash is so - * corrupt that we cant use it to boot into the ftp flash + * corrupt that we can't use it to boot into the ftp flash * loader, and instead we initialize the serial port to * receive a flash-loader and new flash image. we dont include * any flash code here, but just accept a certain amount of diff --git a/arch/cris/include/arch-v32/arch/hwregs/Makefile b/arch/cris/include/arch-v32/arch/hwregs/Makefile index f9a05d2aa06..b8b3f8d666e 100644 --- a/arch/cris/include/arch-v32/arch/hwregs/Makefile +++ b/arch/cris/include/arch-v32/arch/hwregs/Makefile @@ -1,6 +1,6 @@ # Makefile to generate or copy the latest register definitions # and related datastructures and helpermacros. -# The offical place for these files is at: +# The official place for these files is at: RELEASE ?= r1_alfa5 OFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/Makefile b/arch/cris/include/arch-v32/arch/hwregs/iop/Makefile index a90056a095e..0747a22e3c0 100644 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/Makefile +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/Makefile @@ -1,7 +1,7 @@ # $Id: Makefile,v 1.3 2004/01/07 20:34:55 johana Exp $ # Makefile to generate or copy the latest register definitions # and related datastructures and helpermacros. -# The offical place for these files is probably at: +# The official place for these files is probably at: RELEASE ?= r1_alfa5 IOPOFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/ diff --git a/arch/cris/include/asm/bitops.h b/arch/cris/include/asm/bitops.h index 9e69cfb7f13..310e0de67aa 100644 --- a/arch/cris/include/asm/bitops.h +++ b/arch/cris/include/asm/bitops.h @@ -154,12 +154,11 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr) #include <asm-generic/bitops/find.h> #include <asm-generic/bitops/lock.h> -#include <asm-generic/bitops/ext2-non-atomic.h> +#include <asm-generic/bitops/le.h> #define ext2_set_bit_atomic(l,n,a) test_and_set_bit(n,a) #define ext2_clear_bit_atomic(l,n,a) test_and_clear_bit(n,a) -#include <asm-generic/bitops/minix.h> #include <asm-generic/bitops/sched.h> #endif /* __KERNEL__ */ diff --git a/arch/cris/include/asm/pgtable.h b/arch/cris/include/asm/pgtable.h index 9eaae217b21..7df43013835 100644 --- a/arch/cris/include/asm/pgtable.h +++ b/arch/cris/include/asm/pgtable.h @@ -97,7 +97,7 @@ extern unsigned long empty_zero_page; #define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0) #define pmd_none(x) (!pmd_val(x)) -/* by removing the _PAGE_KERNEL bit from the comparision, the same pmd_bad +/* by removing the _PAGE_KERNEL bit from the comparison, the same pmd_bad * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries. */ #define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_KERNEL)) != _PAGE_TABLE) diff --git a/arch/cris/include/asm/thread_info.h b/arch/cris/include/asm/thread_info.h index 91776069ca8..29b74a10583 100644 --- a/arch/cris/include/asm/thread_info.h +++ b/arch/cris/include/asm/thread_info.h @@ -68,7 +68,7 @@ struct thread_info { #define init_thread_info (init_thread_union.thread_info) /* thread information allocation */ -#define alloc_thread_info(tsk) ((struct thread_info *) __get_free_pages(GFP_KERNEL,1)) +#define alloc_thread_info(tsk, node) ((struct thread_info *) __get_free_pages(GFP_KERNEL,1)) #define free_thread_info(ti) free_pages((unsigned long) (ti), 1) #endif /* !__ASSEMBLY__ */ diff --git a/arch/cris/include/asm/types.h b/arch/cris/include/asm/types.h index 5790262cbe8..551a12c0aa0 100644 --- a/arch/cris/include/asm/types.h +++ b/arch/cris/include/asm/types.h @@ -16,15 +16,6 @@ typedef unsigned short umode_t; #define BITS_PER_LONG 32 -#ifndef __ASSEMBLY__ - -/* Dma addresses are 32-bits wide, just like our other addresses. */ - -typedef u32 dma_addr_t; -typedef u32 dma64_addr_t; - -#endif /* __ASSEMBLY__ */ - #endif /* __KERNEL__ */ #endif diff --git a/arch/cris/kernel/traps.c b/arch/cris/kernel/traps.c index 541efbf0937..8da53f34c7a 100644 --- a/arch/cris/kernel/traps.c +++ b/arch/cris/kernel/traps.c @@ -183,7 +183,7 @@ __initcall(oops_nmi_register); /* * This gets called from entry.S when the watchdog has bitten. Show something - * similiar to an Oops dump, and if the kernel is configured to be a nice + * similar to an Oops dump, and if the kernel is configured to be a nice * doggy, then halt instead of reboot. */ void diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig index 747499a1b31..064f6219674 100644 --- a/arch/frv/Kconfig +++ b/arch/frv/Kconfig @@ -6,6 +6,7 @@ config FRV select HAVE_IRQ_WORK select HAVE_PERF_EVENTS select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_SHOW config ZONE_DMA bool @@ -22,6 +23,10 @@ config GENERIC_FIND_NEXT_BIT bool default y +config GENERIC_FIND_BIT_LE + bool + default y + config GENERIC_HWEIGHT bool default y @@ -357,7 +362,6 @@ menu "Power management options" config ARCH_SUSPEND_POSSIBLE def_bool y - depends on !SMP source kernel/power/Kconfig endmenu diff --git a/arch/frv/include/asm/bitops.h b/arch/frv/include/asm/bitops.h index 50ae91b2967..a1d00b0c6ed 100644 --- a/arch/frv/include/asm/bitops.h +++ b/arch/frv/include/asm/bitops.h @@ -401,13 +401,11 @@ int __ilog2_u64(u64 n) #include <asm-generic/bitops/hweight.h> #include <asm-generic/bitops/lock.h> -#include <asm-generic/bitops/ext2-non-atomic.h> +#include <asm-generic/bitops/le.h> #define ext2_set_bit_atomic(lock,nr,addr) test_and_set_bit ((nr) ^ 0x18, (addr)) #define ext2_clear_bit_atomic(lock,nr,addr) test_and_clear_bit((nr) ^ 0x18, (addr)) -#include <asm-generic/bitops/minix-le.h> - #endif /* __KERNEL__ */ #endif /* _ASM_BITOPS_H */ diff --git a/arch/frv/include/asm/pci.h b/arch/frv/include/asm/pci.h index 0d599790985..ef03baf5d89 100644 --- a/arch/frv/include/asm/pci.h +++ b/arch/frv/include/asm/pci.h @@ -54,7 +54,7 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, #endif /* - * These are pretty much arbitary with the CoMEM implementation. + * These are pretty much arbitrary with the CoMEM implementation. * We have the whole address space to ourselves. */ #define PCIBIOS_MIN_IO 0x100 diff --git a/arch/frv/include/asm/processor.h b/arch/frv/include/asm/processor.h index 3744f2e47f4..4b789ab182b 100644 --- a/arch/frv/include/asm/processor.h +++ b/arch/frv/include/asm/processor.h @@ -137,7 +137,7 @@ unsigned long get_wchan(struct task_struct *p); #define KSTK_ESP(tsk) ((tsk)->thread.frame0->sp) /* Allocation and freeing of basic task resources. */ -extern struct task_struct *alloc_task_struct(void); +extern struct task_struct *alloc_task_struct_node(int node); extern void free_task_struct(struct task_struct *p); #define cpu_relax() barrier() diff --git a/arch/frv/include/asm/spr-regs.h b/arch/frv/include/asm/spr-regs.h index 01e6af5e99b..d3883021f23 100644 --- a/arch/frv/include/asm/spr-regs.h +++ b/arch/frv/include/asm/spr-regs.h @@ -274,7 +274,7 @@ #define MSR0_RD 0xc0000000 /* rounding mode */ #define MSR0_RD_NEAREST 0x00000000 /* - nearest */ #define MSR0_RD_ZERO 0x40000000 /* - zero */ -#define MSR0_RD_POS_INF 0x80000000 /* - postive infinity */ +#define MSR0_RD_POS_INF 0x80000000 /* - positive infinity */ #define MSR0_RD_NEG_INF 0xc0000000 /* - negative infinity */ /* diff --git a/arch/frv/include/asm/system.h b/arch/frv/include/asm/system.h index 0a6d8d9ca45..6c10fd2c626 100644 --- a/arch/frv/include/asm/system.h +++ b/arch/frv/include/asm/system.h @@ -45,21 +45,12 @@ do { \ #define wmb() asm volatile ("membar" : : :"memory") #define read_barrier_depends() do { } while (0) -#ifdef CONFIG_SMP -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() -#define smp_read_barrier_depends() read_barrier_depends() -#define set_mb(var, value) \ - do { xchg(&var, (value)); } while (0) -#else #define smp_mb() barrier() #define smp_rmb() barrier() #define smp_wmb() barrier() #define smp_read_barrier_depends() do {} while(0) #define set_mb(var, value) \ do { var = (value); barrier(); } while (0) -#endif extern void die_if_kernel(const char *, ...) __attribute__((format(printf, 1, 2))); extern void free_initmem(void); diff --git a/arch/frv/include/asm/thread_info.h b/arch/frv/include/asm/thread_info.h index 11f33ead29b..cefbe73dc11 100644 --- a/arch/frv/include/asm/thread_info.h +++ b/arch/frv/include/asm/thread_info.h @@ -21,6 +21,8 @@ #define THREAD_SIZE 8192 +#define __HAVE_ARCH_TASK_STRUCT_ALLOCATOR + /* * low level task data that entry.S needs immediate access to * - this struct should fit entirely inside of one cache line @@ -84,16 +86,11 @@ register struct thread_info *__current_thread_info asm("gr15"); /* thread information allocation */ #ifdef CONFIG_DEBUG_STACK_USAGE -#define alloc_thread_info(tsk) \ - ({ \ - struct thread_info *ret; \ - \ - ret = kzalloc(THREAD_SIZE, GFP_KERNEL); \ - \ - ret; \ - }) +#define alloc_thread_info_node(tsk, node) \ + kzalloc_node(THREAD_SIZE, GFP_KERNEL, node) #else -#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL) +#define alloc_thread_info_node(tsk, node) \ + kmalloc_node(THREAD_SIZE, GFP_KERNEL, node) #endif #define free_thread_info(info) kfree(info) diff --git a/arch/frv/include/asm/types.h b/arch/frv/include/asm/types.h index 613bf1e962f..aa3e7fdc7f2 100644 --- a/arch/frv/include/asm/types.h +++ b/arch/frv/include/asm/types.h @@ -27,14 +27,6 @@ typedef unsigned short umode_t; #define BITS_PER_LONG 32 -#ifndef __ASSEMBLY__ - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -#endif /* __ASSEMBLY__ */ - #endif /* __KERNEL__ */ #endif /* _ASM_TYPES_H */ diff --git a/arch/frv/include/asm/virtconvert.h b/arch/frv/include/asm/virtconvert.h index 59788fa2a81..b26d70ab911 100644 --- a/arch/frv/include/asm/virtconvert.h +++ b/arch/frv/include/asm/virtconvert.h @@ -1,4 +1,4 @@ -/* virtconvert.h: virtual/physical/page address convertion +/* virtconvert.h: virtual/physical/page address conversion * * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. * Written by David Howells (dhowells@redhat.com) diff --git a/arch/frv/kernel/entry-table.S b/arch/frv/kernel/entry-table.S index bf35f33e48c..06c5ae191e5 100644 --- a/arch/frv/kernel/entry-table.S +++ b/arch/frv/kernel/entry-table.S @@ -86,7 +86,7 @@ __break_usertrap_fixup_table: .globl __break_kerneltrap_fixup_table __break_kerneltrap_fixup_table: - # handler declaration for a sofware or program interrupt + # handler declaration for a software or program interrupt .macro VECTOR_SOFTPROG tbr_tt, vec .section .trap.user .org \tbr_tt @@ -145,7 +145,7 @@ __break_kerneltrap_fixup_table: .long \vec .endm - # handler declaration for an MMU only sofware or program interrupt + # handler declaration for an MMU only software or program interrupt .macro VECTOR_SP_MMU tbr_tt, vec #ifdef CONFIG_MMU VECTOR_SOFTPROG \tbr_tt, \vec diff --git a/arch/frv/kernel/irq-mb93091.c b/arch/frv/kernel/irq-mb93091.c index 4dd9adaf115..9afc2ea400d 100644 --- a/arch/frv/kernel/irq-mb93091.c +++ b/arch/frv/kernel/irq-mb93091.c @@ -36,45 +36,45 @@ /* * on-motherboard FPGA PIC operations */ -static void frv_fpga_mask(unsigned int irq) +static void frv_fpga_mask(struct irq_data *d) { uint16_t imr = __get_IMR(); - imr |= 1 << (irq - IRQ_BASE_FPGA); + imr |= 1 << (d->irq - IRQ_BASE_FPGA); __set_IMR(imr); } -static void frv_fpga_ack(unsigned int irq) +static void frv_fpga_ack(struct irq_data *d) { - __clr_IFR(1 << (irq - IRQ_BASE_FPGA)); + __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA)); } -static void frv_fpga_mask_ack(unsigned int irq) +static void frv_fpga_mask_ack(struct irq_data *d) { uint16_t imr = __get_IMR(); - imr |= 1 << (irq - IRQ_BASE_FPGA); + imr |= 1 << (d->irq - IRQ_BASE_FPGA); __set_IMR(imr); - __clr_IFR(1 << (irq - IRQ_BASE_FPGA)); + __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA)); } -static void frv_fpga_unmask(unsigned int irq) +static void frv_fpga_unmask(struct irq_data *d) { uint16_t imr = __get_IMR(); - imr &= ~(1 << (irq - IRQ_BASE_FPGA)); + imr &= ~(1 << (d->irq - IRQ_BASE_FPGA)); __set_IMR(imr); } static struct irq_chip frv_fpga_pic = { .name = "mb93091", - .ack = frv_fpga_ack, - .mask = frv_fpga_mask, - .mask_ack = frv_fpga_mask_ack, - .unmask = frv_fpga_unmask, + .irq_ack = frv_fpga_ack, + .irq_mask = frv_fpga_mask, + .irq_mask_ack = frv_fpga_mask_ack, + .irq_unmask = frv_fpga_unmask, }; /* @@ -146,9 +146,9 @@ void __init fpga_init(void) __clr_IFR(0x0000); for (irq = IRQ_BASE_FPGA + 1; irq <= IRQ_BASE_FPGA + 14; irq++) - set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_level_irq); + irq_set_chip_and_handler(irq, &frv_fpga_pic, handle_level_irq); - set_irq_chip_and_handler(IRQ_FPGA_NMI, &frv_fpga_pic, handle_edge_irq); + irq_set_chip_and_handler(IRQ_FPGA_NMI, &frv_fpga_pic, handle_edge_irq); /* the FPGA drives the first four external IRQ inputs on the CPU PIC */ setup_irq(IRQ_CPU_EXTERNAL0, &fpga_irq[0]); diff --git a/arch/frv/kernel/irq-mb93093.c b/arch/frv/kernel/irq-mb93093.c index e4520903187..4d4ad09d3c9 100644 --- a/arch/frv/kernel/irq-mb93093.c +++ b/arch/frv/kernel/irq-mb93093.c @@ -35,45 +35,44 @@ /* * off-CPU FPGA PIC operations */ -static void frv_fpga_mask(unsigned int irq) +static void frv_fpga_mask(struct irq_data *d) { uint16_t imr = __get_IMR(); - imr |= 1 << (irq - IRQ_BASE_FPGA); + imr |= 1 << (d->irq - IRQ_BASE_FPGA); __set_IMR(imr); } -static void frv_fpga_ack(unsigned int irq) +static void frv_fpga_ack(struct irq_data *d) { - __clr_IFR(1 << (irq - IRQ_BASE_FPGA)); + __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA)); } -static void frv_fpga_mask_ack(unsigned int irq) +static void frv_fpga_mask_ack(struct irq_data *d) { uint16_t imr = __get_IMR(); - imr |= 1 << (irq - IRQ_BASE_FPGA); + imr |= 1 << (d->irq - IRQ_BASE_FPGA); __set_IMR(imr); - __clr_IFR(1 << (irq - IRQ_BASE_FPGA)); + __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA)); } -static void frv_fpga_unmask(unsigned int irq) +static void frv_fpga_unmask(struct irq_data *d) { uint16_t imr = __get_IMR(); - imr &= ~(1 << (irq - IRQ_BASE_FPGA)); + imr &= ~(1 << (d->irq - IRQ_BASE_FPGA)); __set_IMR(imr); } static struct irq_chip frv_fpga_pic = { .name = "mb93093", - .ack = frv_fpga_ack, - .mask = frv_fpga_mask, - .mask_ack = frv_fpga_mask_ack, - .unmask = frv_fpga_unmask, - .end = frv_fpga_end, + .irq_ack = frv_fpga_ack, + .irq_mask = frv_fpga_mask, + .irq_mask_ack = frv_fpga_mask_ack, + .irq_unmask = frv_fpga_unmask, }; /* @@ -94,7 +93,7 @@ static irqreturn_t fpga_interrupt(int irq, void *_mask) irq = 31 - irq; mask &= ~(1 << irq); - generic_irq_handle(IRQ_BASE_FPGA + irq); + generic_handle_irq(IRQ_BASE_FPGA + irq); } return IRQ_HANDLED; @@ -125,7 +124,7 @@ void __init fpga_init(void) __clr_IFR(0x0000); for (irq = IRQ_BASE_FPGA + 8; irq <= IRQ_BASE_FPGA + 10; irq++) - set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_edge_irq); + irq_set_chip_and_handler(irq, &frv_fpga_pic, handle_edge_irq); /* the FPGA drives external IRQ input #2 on the CPU PIC */ setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[0]); diff --git a/arch/frv/kernel/irq-mb93493.c b/arch/frv/kernel/irq-mb93493.c index ba55ecdfb24..4d034c7840c 100644 --- a/arch/frv/kernel/irq-mb93493.c +++ b/arch/frv/kernel/irq-mb93493.c @@ -45,46 +45,46 @@ * daughter board PIC operations * - there is no way to ACK interrupts in the MB93493 chip */ -static void frv_mb93493_mask(unsigned int irq) +static void frv_mb93493_mask(struct irq_data *d) { uint32_t iqsr; volatile void *piqsr; - if (IRQ_ROUTING & (1 << (irq - IRQ_BASE_MB93493))) + if (IRQ_ROUTING & (1 << (d->irq - IRQ_BASE_MB93493))) piqsr = __addr_MB93493_IQSR(1); else piqsr = __addr_MB93493_IQSR(0); iqsr = readl(piqsr); - iqsr &= ~(1 << (irq - IRQ_BASE_MB93493 + 16)); + iqsr &= ~(1 << (d->irq - IRQ_BASE_MB93493 + 16)); writel(iqsr, piqsr); } -static void frv_mb93493_ack(unsigned int irq) +static void frv_mb93493_ack(struct irq_data *d) { } -static void frv_mb93493_unmask(unsigned int irq) +static void frv_mb93493_unmask(struct irq_data *d) { uint32_t iqsr; volatile void *piqsr; - if (IRQ_ROUTING & (1 << (irq - IRQ_BASE_MB93493))) + if (IRQ_ROUTING & (1 << (d->irq - IRQ_BASE_MB93493))) piqsr = __addr_MB93493_IQSR(1); else piqsr = __addr_MB93493_IQSR(0); iqsr = readl(piqsr); - iqsr |= 1 << (irq - IRQ_BASE_MB93493 + 16); + iqsr |= 1 << (d->irq - IRQ_BASE_MB93493 + 16); writel(iqsr, piqsr); } static struct irq_chip frv_mb93493_pic = { .name = "mb93093", - .ack = frv_mb93493_ack, - .mask = frv_mb93493_mask, - .mask_ack = frv_mb93493_mask, - .unmask = frv_mb93493_unmask, + .irq_ack = frv_mb93493_ack, + .irq_mask = frv_mb93493_mask, + .irq_mask_ack = frv_mb93493_mask, + .irq_unmask = frv_mb93493_unmask, }; /* @@ -139,7 +139,8 @@ void __init mb93493_init(void) int irq; for (irq = IRQ_BASE_MB93493 + 0; irq <= IRQ_BASE_MB93493 + 10; irq++) - set_irq_chip_and_handler(irq, &frv_mb93493_pic, handle_edge_irq); + irq_set_chip_and_handler(irq, &frv_mb93493_pic, + handle_edge_irq); /* the MB93493 drives external IRQ inputs on the CPU PIC */ setup_irq(IRQ_CPU_MB93493_0, &mb93493_irq[0]); diff --git a/arch/frv/kernel/irq.c b/arch/frv/kernel/irq.c index 625136625a7..a5f624a9f55 100644 --- a/arch/frv/kernel/irq.c +++ b/arch/frv/kernel/irq.c @@ -47,89 +47,45 @@ extern void __init mb93493_init(void); atomic_t irq_err_count; -/* - * Generic, controller-independent functions: - */ -int show_interrupts(struct seq_file *p, void *v) +int arch_show_interrupts(struct seq_file *p, int prec) { - int i = *(loff_t *) v, cpu; - struct irqaction * action; - unsigned long flags; - - if (i == 0) { - char cpuname[12]; - - seq_printf(p, " "); - for_each_present_cpu(cpu) { - sprintf(cpuname, "CPU%d", cpu); - seq_printf(p, " %10s", cpuname); - } - seq_putc(p, '\n'); - } - - if (i < NR_IRQS) { - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); - action = irq_desc[i].action; - if (action) { - seq_printf(p, "%3d: ", i); - for_each_present_cpu(cpu) - seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); - seq_printf(p, " %10s", irq_desc[i].chip->name ? : "-"); - seq_printf(p, " %s", action->name); - for (action = action->next; - action; - action = action->next) - seq_printf(p, ", %s", action->name); - - seq_putc(p, '\n'); - } - - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); - } else if (i == NR_IRQS) { - seq_printf(p, "Err: %10u\n", atomic_read(&irq_err_count)); - } - + seq_printf(p, "%*s: ", prec, "ERR"); + seq_printf(p, "%10u\n", atomic_read(&irq_err_count)); return 0; } /* * on-CPU PIC operations */ -static void frv_cpupic_ack(unsigned int irqlevel) +static void frv_cpupic_ack(struct irq_data *d) { - __clr_RC(irqlevel); + __clr_RC(d->irq); __clr_IRL(); } -static void frv_cpupic_mask(unsigned int irqlevel) +static void frv_cpupic_mask(struct irq_data *d) { - __set_MASK(irqlevel); + __set_MASK(d->irq); } -static void frv_cpupic_mask_ack(unsigned int irqlevel) +static void frv_cpupic_mask_ack(struct irq_data *d) { - __set_MASK(irqlevel); - __clr_RC(irqlevel); + __set_MASK(d->irq); + __clr_RC(d->irq); __clr_IRL(); } -static void frv_cpupic_unmask(unsigned int irqlevel) -{ - __clr_MASK(irqlevel); -} - -static void frv_cpupic_end(unsigned int irqlevel) +static void frv_cpupic_unmask(struct irq_data *d) { - __clr_MASK(irqlevel); + __clr_MASK(d->irq); } static struct irq_chip frv_cpu_pic = { .name = "cpu", - .ack = frv_cpupic_ack, - .mask = frv_cpupic_mask, - .mask_ack = frv_cpupic_mask_ack, - .unmask = frv_cpupic_unmask, - .end = frv_cpupic_end, + .irq_ack = frv_cpupic_ack, + .irq_mask = frv_cpupic_mask, + .irq_mask_ack = frv_cpupic_mask_ack, + .irq_unmask = frv_cpupic_unmask, }; /* @@ -161,10 +117,10 @@ void __init init_IRQ(void) int level; for (level = 1; level <= 14; level++) - set_irq_chip_and_handler(level, &frv_cpu_pic, + irq_set_chip_and_handler(level, &frv_cpu_pic, handle_level_irq); - set_irq_handler(IRQ_CPU_TIMER0, handle_edge_irq); + irq_set_handler(IRQ_CPU_TIMER0, handle_edge_irq); /* set the trigger levels for internal interrupt sources * - timers all falling-edge diff --git a/arch/frv/kernel/process.c b/arch/frv/kernel/process.c index efad12071c2..9d359752646 100644 --- a/arch/frv/kernel/process.c +++ b/arch/frv/kernel/process.c @@ -44,9 +44,10 @@ asmlinkage void ret_from_fork(void); void (*pm_power_off)(void); EXPORT_SYMBOL(pm_power_off); -struct task_struct *alloc_task_struct(void) +struct task_struct *alloc_task_struct_node(int node) { - struct task_struct *p = kmalloc(THREAD_SIZE, GFP_KERNEL); + struct task_struct *p = kmalloc_node(THREAD_SIZE, GFP_KERNEL, node); + if (p) atomic_set((atomic_t *)(p+1), 1); return p; diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig index 6df692d1475..e20322ffcaf 100644 --- a/arch/h8300/Kconfig +++ b/arch/h8300/Kconfig @@ -3,7 +3,7 @@ config H8300 default y select HAVE_IDE select HAVE_GENERIC_HARDIRQS - select GENERIC_HARDIRQS_NO_DEPRECATED + select GENERIC_IRQ_SHOW config SYMBOL_PREFIX string @@ -45,6 +45,10 @@ config GENERIC_FIND_NEXT_BIT bool default y +config GENERIC_FIND_BIT_LE + bool + default y + config GENERIC_HWEIGHT bool default y diff --git a/arch/h8300/boot/compressed/Makefile b/arch/h8300/boot/compressed/Makefile index d6189e057ed..6745cb1ffb4 100644 --- a/arch/h8300/boot/compressed/Makefile +++ b/arch/h8300/boot/compressed/Makefile @@ -5,7 +5,7 @@ # targets := vmlinux vmlinux.bin vmlinux.bin.gz head.o misc.o piggy.o -EXTRA_AFLAGS := -traditional +asflags-y := -traditional OBJECTS = $(obj)/head.o $(obj)/misc.o diff --git a/arch/h8300/include/asm/bitops.h b/arch/h8300/include/asm/bitops.h index cb9ddf5fc54..e856c1bb341 100644 --- a/arch/h8300/include/asm/bitops.h +++ b/arch/h8300/include/asm/bitops.h @@ -200,9 +200,8 @@ static __inline__ unsigned long __ffs(unsigned long word) #include <asm-generic/bitops/sched.h> #include <asm-generic/bitops/hweight.h> #include <asm-generic/bitops/lock.h> -#include <asm-generic/bitops/ext2-non-atomic.h> +#include <asm-generic/bitops/le.h> #include <asm-generic/bitops/ext2-atomic.h> -#include <asm-generic/bitops/minix.h> #endif /* __KERNEL__ */ diff --git a/arch/h8300/include/asm/types.h b/arch/h8300/include/asm/types.h index 12875190b15..bb2c91a3522 100644 --- a/arch/h8300/include/asm/types.h +++ b/arch/h8300/include/asm/types.h @@ -22,10 +22,6 @@ typedef unsigned short umode_t; #define BITS_PER_LONG 32 -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ diff --git a/arch/h8300/kernel/irq.c b/arch/h8300/kernel/irq.c index 7643d39925d..1f67fed476a 100644 --- a/arch/h8300/kernel/irq.c +++ b/arch/h8300/kernel/irq.c @@ -155,7 +155,7 @@ void __init init_IRQ(void) setup_vector(); for (c = 0; c < NR_IRQS; c++) - set_irq_chip_and_handler(c, &h8300irq_chip, handle_simple_irq); + irq_set_chip_and_handler(c, &h8300irq_chip, handle_simple_irq); } asmlinkage void do_IRQ(int irq) @@ -164,34 +164,3 @@ asmlinkage void do_IRQ(int irq) generic_handle_irq(irq); irq_exit(); } - -#if defined(CONFIG_PROC_FS) -int show_interrupts(struct seq_file *p, void *v) -{ - int i = *(loff_t *) v; - struct irqaction * action; - unsigned long flags; - - if (i == 0) - seq_puts(p, " CPU0"); - - if (i < NR_IRQS) { - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); - action = irq_desc[i].action; - if (!action) - goto unlock; - seq_printf(p, "%3d: ",i); - seq_printf(p, "%10u ", kstat_irqs(i)); - seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name); - seq_printf(p, "-%-8s", irq_desc[i].name); - seq_printf(p, " %s", action->name); - - for (action=action->next; action; action = action->next) - seq_printf(p, ", %s", action->name); - seq_putc(p, '\n'); -unlock: - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); - } - return 0; -} -#endif diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index fcf3b437a2d..e5cc56ae6ce 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -26,6 +26,7 @@ config IA64 select GENERIC_IRQ_PROBE select GENERIC_PENDING_IRQ if SMP select IRQ_PER_CPU + select GENERIC_IRQ_SHOW default y help The Itanium Processor Family is Intel's 64-bit successor to @@ -413,11 +414,11 @@ config PERMIT_BSP_REMOVE support. config FORCE_CPEI_RETARGET - bool "Force assumption that CPEI can be re-targetted" + bool "Force assumption that CPEI can be re-targeted" depends on PERMIT_BSP_REMOVE default n ---help--- - Say Y if you need to force the assumption that CPEI can be re-targetted to + Say Y if you need to force the assumption that CPEI can be re-targeted to any cpu in the system. This hint is available via ACPI 3.0 specifications. Tiger4 systems are capable of re-directing CPEI to any CPU other than BSP. This option it useful to enable this feature on older BIOS's as well. diff --git a/arch/ia64/hp/sim/hpsim_irq.c b/arch/ia64/hp/sim/hpsim_irq.c index b272261d77c..4bd9a63260e 100644 --- a/arch/ia64/hp/sim/hpsim_irq.c +++ b/arch/ia64/hp/sim/hpsim_irq.c @@ -11,42 +11,41 @@ #include <linux/irq.h> static unsigned int -hpsim_irq_startup (unsigned int irq) +hpsim_irq_startup(struct irq_data *data) { return 0; } static void -hpsim_irq_noop (unsigned int irq) +hpsim_irq_noop(struct irq_data *data) { } static int -hpsim_set_affinity_noop(unsigned int a, const struct cpumask *b) +hpsim_set_affinity_noop(struct irq_data *d, const struct cpumask *b, bool f) { return 0; } static struct irq_chip irq_type_hp_sim = { - .name = "hpsim", - .startup = hpsim_irq_startup, - .shutdown = hpsim_irq_noop, - .enable = hpsim_irq_noop, - .disable = hpsim_irq_noop, - .ack = hpsim_irq_noop, - .end = hpsim_irq_noop, - .set_affinity = hpsim_set_affinity_noop, + .name = "hpsim", + .irq_startup = hpsim_irq_startup, + .irq_shutdown = hpsim_irq_noop, + .irq_enable = hpsim_irq_noop, + .irq_disable = hpsim_irq_noop, + .irq_ack = hpsim_irq_noop, + .irq_set_affinity = hpsim_set_affinity_noop, }; void __init hpsim_irq_init (void) { - struct irq_desc *idesc; int i; - for (i = 0; i < NR_IRQS; ++i) { - idesc = irq_desc + i; - if (idesc->chip == &no_irq_chip) - idesc->chip = &irq_type_hp_sim; + for_each_active_irq(i) { + struct irq_chip *chip = irq_get_chip(i); + + if (chip == &no_irq_chip) + irq_set_chip(i, &irq_type_hp_sim); } } diff --git a/arch/ia64/include/asm/acpi.h b/arch/ia64/include/asm/acpi.h index 837dc82a013..a06dfb13d51 100644 --- a/arch/ia64/include/asm/acpi.h +++ b/arch/ia64/include/asm/acpi.h @@ -128,9 +128,9 @@ static inline const char *acpi_get_sysname (void) int acpi_request_vector (u32 int_type); int acpi_gsi_to_irq (u32 gsi, unsigned int *irq); -/* routines for saving/restoring kernel state */ -extern int acpi_save_state_mem(void); -extern void acpi_restore_state_mem(void); +/* Low-level suspend routine. */ +extern int acpi_suspend_lowlevel(void); + extern unsigned long acpi_wakeup_address; /* diff --git a/arch/ia64/include/asm/bitops.h b/arch/ia64/include/asm/bitops.h index 9da3df6f1a5..b76f7e00921 100644 --- a/arch/ia64/include/asm/bitops.h +++ b/arch/ia64/include/asm/bitops.h @@ -456,12 +456,11 @@ static __inline__ unsigned long __arch_hweight64(unsigned long x) #ifdef __KERNEL__ -#include <asm-generic/bitops/ext2-non-atomic.h> +#include <asm-generic/bitops/le.h> #define ext2_set_bit_atomic(l,n,a) test_and_set_bit(n,a) #define ext2_clear_bit_atomic(l,n,a) test_and_clear_bit(n,a) -#include <asm-generic/bitops/minix.h> #include <asm-generic/bitops/sched.h> #endif /* __KERNEL__ */ diff --git a/arch/ia64/include/asm/hw_irq.h b/arch/ia64/include/asm/hw_irq.h index bf2e37493e0..a681d02cb32 100644 --- a/arch/ia64/include/asm/hw_irq.h +++ b/arch/ia64/include/asm/hw_irq.h @@ -151,9 +151,6 @@ static inline void ia64_native_resend_irq(unsigned int vector) /* * Default implementations for the irq-descriptor API: */ - -extern struct irq_desc irq_desc[NR_IRQS]; - #ifndef CONFIG_IA64_GENERIC static inline ia64_vector __ia64_irq_to_vector(int irq) { diff --git a/arch/ia64/include/asm/pal.h b/arch/ia64/include/asm/pal.h index 6a292505b39..2e69284df8e 100644 --- a/arch/ia64/include/asm/pal.h +++ b/arch/ia64/include/asm/pal.h @@ -1669,7 +1669,7 @@ typedef union pal_vp_info_u { } pal_vp_info_u_t; /* - * Returns infomation about virtual processor features + * Returns information about virtual processor features */ static inline s64 ia64_pal_vp_info (u64 feature_set, u64 vp_buffer, u64 *vp_info, u64 *vmm_id) diff --git a/arch/ia64/include/asm/perfmon_default_smpl.h b/arch/ia64/include/asm/perfmon_default_smpl.h index 74724b24c2b..a2d560c6723 100644 --- a/arch/ia64/include/asm/perfmon_default_smpl.h +++ b/arch/ia64/include/asm/perfmon_default_smpl.h @@ -67,8 +67,8 @@ typedef struct { unsigned long ip; /* where did the overflow interrupt happened */ unsigned long tstamp; /* ar.itc when entering perfmon intr. handler */ - unsigned short cpu; /* cpu on which the overflow occured */ - unsigned short set; /* event set active when overflow ocurred */ + unsigned short cpu; /* cpu on which the overflow occurred */ + unsigned short set; /* event set active when overflow occurred */ int tgid; /* thread group id (for NPTL, this is getpid()) */ } pfm_default_smpl_entry_t; diff --git a/arch/ia64/include/asm/sn/bte.h b/arch/ia64/include/asm/sn/bte.h index 96798d2da7c..cc6c4dbf53a 100644 --- a/arch/ia64/include/asm/sn/bte.h +++ b/arch/ia64/include/asm/sn/bte.h @@ -216,7 +216,7 @@ extern void bte_error_handler(unsigned long); bte_copy(0, dest, len, ((mode) | BTE_ZERO_FILL), notification) /* - * The following is the prefered way of calling bte_unaligned_copy + * The following is the preferred way of calling bte_unaligned_copy * If the copy is fully cache line aligned, then bte_copy is * used instead. Since bte_copy is inlined, this saves a call * stack. NOTE: bte_copy is called synchronously and does block diff --git a/arch/ia64/include/asm/sn/shub_mmr.h b/arch/ia64/include/asm/sn/shub_mmr.h index 7de1d1d4b71..a84d870f429 100644 --- a/arch/ia64/include/asm/sn/shub_mmr.h +++ b/arch/ia64/include/asm/sn/shub_mmr.h @@ -459,7 +459,7 @@ /* ==================================================================== */ /* Some MMRs are functionally identical (or close enough) on both SHUB1 */ /* and SHUB2 that it makes sense to define a geberic name for the MMR. */ -/* It is acceptible to use (for example) SH_IPI_INT to reference the */ +/* It is acceptable to use (for example) SH_IPI_INT to reference the */ /* the IPI MMR. The value of SH_IPI_INT is determined at runtime based */ /* on the type of the SHUB. Do not use these #defines in performance */ /* critical code or loops - there is a small performance penalty. */ diff --git a/arch/ia64/include/asm/sn/shubio.h b/arch/ia64/include/asm/sn/shubio.h index 6052422a22b..ecb8a49476b 100644 --- a/arch/ia64/include/asm/sn/shubio.h +++ b/arch/ia64/include/asm/sn/shubio.h @@ -1383,7 +1383,7 @@ typedef union ii_ibcr_u { * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The * * errant header is thereby captured, and no further spurious read * * respones are captured until IXSS[VALID] is cleared by setting the * - * appropriate bit in IECLR.Everytime a spurious read response is * + * appropriate bit in IECLR. Every time a spurious read response is * * detected, the SPUR_RD bit of the PRB corresponding to the incoming * * message's SIDN field is set. This always happens, regarless of * * whether a header is captured. The programmer should check * @@ -2738,7 +2738,7 @@ typedef union ii_ippr_u { /************************************************************************ * * * The following defines which were not formed into structures are * - * probably indentical to another register, and the name of the * + * probably identical to another register, and the name of the * * register is provided against each of these registers. This * * information needs to be checked carefully * * * diff --git a/arch/ia64/include/asm/thread_info.h b/arch/ia64/include/asm/thread_info.h index b6a5ba2aca3..ff0cc84e7bc 100644 --- a/arch/ia64/include/asm/thread_info.h +++ b/arch/ia64/include/asm/thread_info.h @@ -59,11 +59,12 @@ struct thread_info { #ifndef ASM_OFFSETS_C /* how to get the thread information struct from C */ #define current_thread_info() ((struct thread_info *) ((char *) current + IA64_TASK_SIZE)) -#define alloc_thread_info(tsk) ((struct thread_info *) ((char *) (tsk) + IA64_TASK_SIZE)) +#define alloc_thread_info_node(tsk, node) \ + ((struct thread_info *) ((char *) (tsk) + IA64_TASK_SIZE)) #define task_thread_info(tsk) ((struct thread_info *) ((char *) (tsk) + IA64_TASK_SIZE)) #else #define current_thread_info() ((struct thread_info *) 0) -#define alloc_thread_info(tsk) ((struct thread_info *) 0) +#define alloc_thread_info_node(tsk, node) ((struct thread_info *) 0) #define task_thread_info(tsk) ((struct thread_info *) 0) #endif #define free_thread_info(ti) /* nothing */ @@ -84,7 +85,14 @@ struct thread_info { #define end_of_stack(p) (unsigned long *)((void *)(p) + IA64_RBS_OFFSET) #define __HAVE_ARCH_TASK_STRUCT_ALLOCATOR -#define alloc_task_struct() ((struct task_struct *)__get_free_pages(GFP_KERNEL | __GFP_COMP, KERNEL_STACK_SIZE_ORDER)) +#define alloc_task_struct_node(node) \ +({ \ + struct page *page = alloc_pages_node(node, GFP_KERNEL | __GFP_COMP, \ + KERNEL_STACK_SIZE_ORDER); \ + struct task_struct *ret = page ? page_address(page) : NULL; \ + \ + ret; \ +}) #define free_task_struct(tsk) free_pages((unsigned long) (tsk), KERNEL_STACK_SIZE_ORDER) #endif /* !__ASSEMBLY */ diff --git a/arch/ia64/include/asm/types.h b/arch/ia64/include/asm/types.h index 93773fd37be..82b3939d271 100644 --- a/arch/ia64/include/asm/types.h +++ b/arch/ia64/include/asm/types.h @@ -40,9 +40,6 @@ struct fnptr { unsigned long gp; }; -/* DMA addresses are 64-bits wide, in general. */ -typedef u64 dma_addr_t; - # endif /* __KERNEL__ */ #endif /* !__ASSEMBLY__ */ diff --git a/arch/ia64/include/asm/unistd.h b/arch/ia64/include/asm/unistd.h index 954d398a54b..404d037c5e1 100644 --- a/arch/ia64/include/asm/unistd.h +++ b/arch/ia64/include/asm/unistd.h @@ -315,11 +315,15 @@ #define __NR_fanotify_init 1323 #define __NR_fanotify_mark 1324 #define __NR_prlimit64 1325 +#define __NR_name_to_handle_at 1326 +#define __NR_open_by_handle_at 1327 +#define __NR_clock_adjtime 1328 +#define __NR_syncfs 1329 #ifdef __KERNEL__ -#define NR_syscalls 302 /* length of syscall table */ +#define NR_syscalls 306 /* length of syscall table */ /* * The following defines stop scripts/checksyscalls.sh from complaining about diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c index 90ebceb899a..3be485a300b 100644 --- a/arch/ia64/kernel/acpi.c +++ b/arch/ia64/kernel/acpi.c @@ -803,7 +803,7 @@ int acpi_isa_irq_to_gsi(unsigned isa_irq, u32 *gsi) * ACPI based hotplug CPU support */ #ifdef CONFIG_ACPI_HOTPLUG_CPU -static +static __cpuinit int acpi_map_cpu2node(acpi_handle handle, int cpu, int physid) { #ifdef CONFIG_ACPI_NUMA @@ -878,7 +878,7 @@ __init void prefill_possible_map(void) set_cpu_possible(i, true); } -int acpi_map_lsapic(acpi_handle handle, int *pcpu) +static int __cpuinit _acpi_map_lsapic(acpi_handle handle, int *pcpu) { struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; union acpi_object *obj; @@ -929,6 +929,11 @@ int acpi_map_lsapic(acpi_handle handle, int *pcpu) return (0); } +/* wrapper to silence section mismatch warning */ +int __ref acpi_map_lsapic(acpi_handle handle, int *pcpu) +{ + return _acpi_map_lsapic(handle, pcpu); +} EXPORT_SYMBOL(acpi_map_lsapic); int acpi_unmap_lsapic(int cpu) @@ -1034,18 +1039,8 @@ int acpi_unregister_ioapic(acpi_handle handle, u32 gsi_base) EXPORT_SYMBOL(acpi_unregister_ioapic); /* - * acpi_save_state_mem() - save kernel state + * acpi_suspend_lowlevel() - save kernel state and suspend. * * TBD when when IA64 starts to support suspend... */ -int acpi_save_state_mem(void) { return 0; } - -/* - * acpi_restore_state() - */ -void acpi_restore_state_mem(void) {} - -/* - * do_suspend_lowlevel() - */ -void do_suspend_lowlevel(void) {} +int acpi_suspend_lowlevel(void) { return 0; } diff --git a/arch/ia64/kernel/crash_dump.c b/arch/ia64/kernel/crash_dump.c index 23e91290e41..c8c9298666f 100644 --- a/arch/ia64/kernel/crash_dump.c +++ b/arch/ia64/kernel/crash_dump.c @@ -13,9 +13,6 @@ #include <asm/page.h> #include <asm/uaccess.h> -/* Stores the physical address of elf header of crash image. */ -unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX; - /** * copy_oldmem_page - copy one page from "oldmem" * @pfn: page frame number to be copied diff --git a/arch/ia64/kernel/cyclone.c b/arch/ia64/kernel/cyclone.c index d52f1f78eff..1b811c61bdc 100644 --- a/arch/ia64/kernel/cyclone.c +++ b/arch/ia64/kernel/cyclone.c @@ -31,7 +31,7 @@ static struct clocksource clocksource_cyclone = { .rating = 300, .read = read_cyclone, .mask = (1LL << 40) - 1, - .mult = 0, /*to be caluclated*/ + .mult = 0, /*to be calculated*/ .shift = 16, .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; diff --git a/arch/ia64/kernel/efi.c b/arch/ia64/kernel/efi.c index a0f00192850..6fc03aff046 100644 --- a/arch/ia64/kernel/efi.c +++ b/arch/ia64/kernel/efi.c @@ -23,6 +23,7 @@ */ #include <linux/module.h> #include <linux/bootmem.h> +#include <linux/crash_dump.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/types.h> diff --git a/arch/ia64/kernel/entry.S b/arch/ia64/kernel/entry.S index 244704a174d..6de2e23b363 100644 --- a/arch/ia64/kernel/entry.S +++ b/arch/ia64/kernel/entry.S @@ -1771,6 +1771,10 @@ sys_call_table: data8 sys_fanotify_init data8 sys_fanotify_mark data8 sys_prlimit64 // 1325 + data8 sys_name_to_handle_at + data8 sys_open_by_handle_at + data8 sys_clock_adjtime + data8 sys_syncfs .org sys_call_table + 8*NR_syscalls // guard against failures to increase NR_syscalls #endif /* __IA64_ASM_PARAVIRTUALIZED_NATIVE */ diff --git a/arch/ia64/kernel/iosapic.c b/arch/ia64/kernel/iosapic.c index 22c38404f53..b0f9afebb14 100644 --- a/arch/ia64/kernel/iosapic.c +++ b/arch/ia64/kernel/iosapic.c @@ -257,7 +257,7 @@ set_rte (unsigned int gsi, unsigned int irq, unsigned int dest, int mask) } static void -nop (unsigned int irq) +nop (struct irq_data *data) { /* do nothing... */ } @@ -287,8 +287,9 @@ kexec_disable_iosapic(void) #endif static void -mask_irq (unsigned int irq) +mask_irq (struct irq_data *data) { + unsigned int irq = data->irq; u32 low32; int rte_index; struct iosapic_rte_info *rte; @@ -305,8 +306,9 @@ mask_irq (unsigned int irq) } static void -unmask_irq (unsigned int irq) +unmask_irq (struct irq_data *data) { + unsigned int irq = data->irq; u32 low32; int rte_index; struct iosapic_rte_info *rte; @@ -323,9 +325,11 @@ unmask_irq (unsigned int irq) static int -iosapic_set_affinity(unsigned int irq, const struct cpumask *mask) +iosapic_set_affinity(struct irq_data *data, const struct cpumask *mask, + bool force) { #ifdef CONFIG_SMP + unsigned int irq = data->irq; u32 high32, low32; int cpu, dest, rte_index; int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0; @@ -379,32 +383,33 @@ iosapic_set_affinity(unsigned int irq, const struct cpumask *mask) */ static unsigned int -iosapic_startup_level_irq (unsigned int irq) +iosapic_startup_level_irq (struct irq_data *data) { - unmask_irq(irq); + unmask_irq(data); return 0; } static void -iosapic_unmask_level_irq (unsigned int irq) +iosapic_unmask_level_irq (struct irq_data *data) { + unsigned int irq = data->irq; ia64_vector vec = irq_to_vector(irq); struct iosapic_rte_info *rte; int do_unmask_irq = 0; irq_complete_move(irq); - if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) { + if (unlikely(irqd_is_setaffinity_pending(data))) { do_unmask_irq = 1; - mask_irq(irq); + mask_irq(data); } else - unmask_irq(irq); + unmask_irq(data); list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) iosapic_eoi(rte->iosapic->addr, vec); if (unlikely(do_unmask_irq)) { - move_masked_irq(irq); - unmask_irq(irq); + irq_move_masked_irq(data); + unmask_irq(data); } } @@ -414,15 +419,15 @@ iosapic_unmask_level_irq (unsigned int irq) #define iosapic_ack_level_irq nop static struct irq_chip irq_type_iosapic_level = { - .name = "IO-SAPIC-level", - .startup = iosapic_startup_level_irq, - .shutdown = iosapic_shutdown_level_irq, - .enable = iosapic_enable_level_irq, - .disable = iosapic_disable_level_irq, - .ack = iosapic_ack_level_irq, - .mask = mask_irq, - .unmask = iosapic_unmask_level_irq, - .set_affinity = iosapic_set_affinity + .name = "IO-SAPIC-level", + .irq_startup = iosapic_startup_level_irq, + .irq_shutdown = iosapic_shutdown_level_irq, + .irq_enable = iosapic_enable_level_irq, + .irq_disable = iosapic_disable_level_irq, + .irq_ack = iosapic_ack_level_irq, + .irq_mask = mask_irq, + .irq_unmask = iosapic_unmask_level_irq, + .irq_set_affinity = iosapic_set_affinity }; /* @@ -430,9 +435,9 @@ static struct irq_chip irq_type_iosapic_level = { */ static unsigned int -iosapic_startup_edge_irq (unsigned int irq) +iosapic_startup_edge_irq (struct irq_data *data) { - unmask_irq(irq); + unmask_irq(data); /* * IOSAPIC simply drops interrupts pended while the * corresponding pin was masked, so we can't know if an @@ -442,37 +447,25 @@ iosapic_startup_edge_irq (unsigned int irq) } static void -iosapic_ack_edge_irq (unsigned int irq) +iosapic_ack_edge_irq (struct irq_data *data) { - struct irq_desc *idesc = irq_desc + irq; - - irq_complete_move(irq); - move_native_irq(irq); - /* - * Once we have recorded IRQ_PENDING already, we can mask the - * interrupt for real. This prevents IRQ storms from unhandled - * devices. - */ - if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) == - (IRQ_PENDING|IRQ_DISABLED)) - mask_irq(irq); + irq_complete_move(data->irq); + irq_move_irq(data); } #define iosapic_enable_edge_irq unmask_irq #define iosapic_disable_edge_irq nop -#define iosapic_end_edge_irq nop static struct irq_chip irq_type_iosapic_edge = { - .name = "IO-SAPIC-edge", - .startup = iosapic_startup_edge_irq, - .shutdown = iosapic_disable_edge_irq, - .enable = iosapic_enable_edge_irq, - .disable = iosapic_disable_edge_irq, - .ack = iosapic_ack_edge_irq, - .end = iosapic_end_edge_irq, - .mask = mask_irq, - .unmask = unmask_irq, - .set_affinity = iosapic_set_affinity + .name = "IO-SAPIC-edge", + .irq_startup = iosapic_startup_edge_irq, + .irq_shutdown = iosapic_disable_edge_irq, + .irq_enable = iosapic_enable_edge_irq, + .irq_disable = iosapic_disable_edge_irq, + .irq_ack = iosapic_ack_edge_irq, + .irq_mask = mask_irq, + .irq_unmask = unmask_irq, + .irq_set_affinity = iosapic_set_affinity }; static unsigned int @@ -562,8 +555,7 @@ static int register_intr (unsigned int gsi, int irq, unsigned char delivery, unsigned long polarity, unsigned long trigger) { - struct irq_desc *idesc; - struct irq_chip *irq_type; + struct irq_chip *chip, *irq_type; int index; struct iosapic_rte_info *rte; @@ -610,19 +602,18 @@ register_intr (unsigned int gsi, int irq, unsigned char delivery, irq_type = iosapic_get_irq_chip(trigger); - idesc = irq_desc + irq; - if (irq_type != NULL && idesc->chip != irq_type) { - if (idesc->chip != &no_irq_chip) + chip = irq_get_chip(irq); + if (irq_type != NULL && chip != irq_type) { + if (chip != &no_irq_chip) printk(KERN_WARNING "%s: changing vector %d from %s to %s\n", __func__, irq_to_vector(irq), - idesc->chip->name, irq_type->name); - idesc->chip = irq_type; + chip->name, irq_type->name); + chip = irq_type; } - if (trigger == IOSAPIC_EDGE) - __set_irq_handler_unlocked(irq, handle_edge_irq); - else - __set_irq_handler_unlocked(irq, handle_level_irq); + __irq_set_chip_handler_name_locked(irq, chip, trigger == IOSAPIC_EDGE ? + handle_edge_irq : handle_level_irq, + NULL); return 0; } @@ -732,6 +723,7 @@ iosapic_register_intr (unsigned int gsi, struct iosapic_rte_info *rte; u32 low32; unsigned char dmode; + struct irq_desc *desc; /* * If this GSI has already been registered (i.e., it's a @@ -759,12 +751,13 @@ iosapic_register_intr (unsigned int gsi, goto unlock_iosapic_lock; } - raw_spin_lock(&irq_desc[irq].lock); + desc = irq_to_desc(irq); + raw_spin_lock(&desc->lock); dest = get_target_cpu(gsi, irq); dmode = choose_dmode(); err = register_intr(gsi, irq, dmode, polarity, trigger); if (err < 0) { - raw_spin_unlock(&irq_desc[irq].lock); + raw_spin_unlock(&desc->lock); irq = err; goto unlock_iosapic_lock; } @@ -783,7 +776,7 @@ iosapic_register_intr (unsigned int gsi, (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), cpu_logical_id(dest), dest, irq_to_vector(irq)); - raw_spin_unlock(&irq_desc[irq].lock); + raw_spin_unlock(&desc->lock); unlock_iosapic_lock: spin_unlock_irqrestore(&iosapic_lock, flags); return irq; @@ -794,7 +787,6 @@ iosapic_unregister_intr (unsigned int gsi) { unsigned long flags; int irq, index; - struct irq_desc *idesc; u32 low32; unsigned long trigger, polarity; unsigned int dest; @@ -824,7 +816,6 @@ iosapic_unregister_intr (unsigned int gsi) if (--rte->refcnt > 0) goto out; - idesc = irq_desc + irq; rte->refcnt = NO_REF_RTE; /* Mask the interrupt */ @@ -848,7 +839,7 @@ iosapic_unregister_intr (unsigned int gsi) if (iosapic_intr_info[irq].count == 0) { #ifdef CONFIG_SMP /* Clear affinity */ - cpumask_setall(idesc->affinity); + cpumask_setall(irq_get_irq_data(irq)->affinity); #endif /* Clear the interrupt information */ iosapic_intr_info[irq].dest = 0; diff --git a/arch/ia64/kernel/irq.c b/arch/ia64/kernel/irq.c index 94ee9d067cb..ad69606613e 100644 --- a/arch/ia64/kernel/irq.c +++ b/arch/ia64/kernel/irq.c @@ -53,47 +53,9 @@ atomic_t irq_err_count; /* * /proc/interrupts printing: */ - -int show_interrupts(struct seq_file *p, void *v) +int arch_show_interrupts(struct seq_file *p, int prec) { - int i = *(loff_t *) v, j; - struct irqaction * action; - unsigned long flags; - - if (i == 0) { - char cpuname[16]; - seq_printf(p, " "); - for_each_online_cpu(j) { - snprintf(cpuname, 10, "CPU%d", j); - seq_printf(p, "%10s ", cpuname); - } - seq_putc(p, '\n'); - } - - if (i < NR_IRQS) { - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); - action = irq_desc[i].action; - if (!action) - goto skip; - seq_printf(p, "%3d: ",i); -#ifndef CONFIG_SMP - seq_printf(p, "%10u ", kstat_irqs(i)); -#else - for_each_online_cpu(j) { - seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); - } -#endif - seq_printf(p, " %14s", irq_desc[i].chip->name); - seq_printf(p, " %s", action->name); - - for (action=action->next; action; action = action->next) - seq_printf(p, ", %s", action->name); - - seq_putc(p, '\n'); -skip: - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); - } else if (i == NR_IRQS) - seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count)); + seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count)); return 0; } @@ -103,7 +65,7 @@ static char irq_redir [NR_IRQS]; // = { [0 ... NR_IRQS-1] = 1 }; void set_irq_affinity_info (unsigned int irq, int hwid, int redir) { if (irq < NR_IRQS) { - cpumask_copy(irq_desc[irq].affinity, + cpumask_copy(irq_get_irq_data(irq)->affinity, cpumask_of(cpu_logical_id(hwid))); irq_redir[irq] = (char) (redir & 0xff); } @@ -130,13 +92,14 @@ unsigned int vectors_in_migration[NR_IRQS]; */ static void migrate_irqs(void) { - struct irq_desc *desc; int irq, new_cpu; for (irq=0; irq < NR_IRQS; irq++) { - desc = irq_desc + irq; + struct irq_desc *desc = irq_to_desc(irq); + struct irq_data *data = irq_desc_get_irq_data(desc); + struct irq_chip *chip = irq_data_get_irq_chip(data); - if (desc->status == IRQ_DISABLED) + if (irqd_irq_disabled(data)) continue; /* @@ -145,10 +108,10 @@ static void migrate_irqs(void) * tell CPU not to respond to these local intr sources. * such as ITV,CPEI,MCA etc. */ - if (desc->status == IRQ_PER_CPU) + if (irqd_is_per_cpu(data)) continue; - if (cpumask_any_and(irq_desc[irq].affinity, cpu_online_mask) + if (cpumask_any_and(data->affinity, cpu_online_mask) >= nr_cpu_ids) { /* * Save it for phase 2 processing @@ -160,16 +123,16 @@ static void migrate_irqs(void) /* * Al three are essential, currently WARN_ON.. maybe panic? */ - if (desc->chip && desc->chip->disable && - desc->chip->enable && desc->chip->set_affinity) { - desc->chip->disable(irq); - desc->chip->set_affinity(irq, - cpumask_of(new_cpu)); - desc->chip->enable(irq); + if (chip && chip->irq_disable && + chip->irq_enable && chip->irq_set_affinity) { + chip->irq_disable(data); + chip->irq_set_affinity(data, + cpumask_of(new_cpu), false); + chip->irq_enable(data); } else { - WARN_ON((!(desc->chip) || !(desc->chip->disable) || - !(desc->chip->enable) || - !(desc->chip->set_affinity))); + WARN_ON((!chip || !chip->irq_disable || + !chip->irq_enable || + !chip->irq_set_affinity)); } } } diff --git a/arch/ia64/kernel/irq_ia64.c b/arch/ia64/kernel/irq_ia64.c index 38c07b86690..5b704740f16 100644 --- a/arch/ia64/kernel/irq_ia64.c +++ b/arch/ia64/kernel/irq_ia64.c @@ -343,7 +343,7 @@ static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id) if (irq < 0) continue; - desc = irq_desc + irq; + desc = irq_to_desc(irq); cfg = irq_cfg + irq; raw_spin_lock(&desc->lock); if (!cfg->move_cleanup_count) @@ -626,17 +626,15 @@ static struct irqaction tlb_irqaction = { void ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action) { - struct irq_desc *desc; unsigned int irq; irq = vec; BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL)); - desc = irq_desc + irq; - desc->status |= IRQ_PER_CPU; - set_irq_chip(irq, &irq_type_ia64_lsapic); + irq_set_status_flags(irq, IRQ_PER_CPU); + irq_set_chip(irq, &irq_type_ia64_lsapic); if (action) setup_irq(irq, action); - set_irq_handler(irq, handle_percpu_irq); + irq_set_handler(irq, handle_percpu_irq); } void __init diff --git a/arch/ia64/kernel/irq_lsapic.c b/arch/ia64/kernel/irq_lsapic.c index fc1549d4564..1b3a776e516 100644 --- a/arch/ia64/kernel/irq_lsapic.c +++ b/arch/ia64/kernel/irq_lsapic.c @@ -15,31 +15,30 @@ #include <linux/irq.h> static unsigned int -lsapic_noop_startup (unsigned int irq) +lsapic_noop_startup (struct irq_data *data) { return 0; } static void -lsapic_noop (unsigned int irq) +lsapic_noop (struct irq_data *data) { /* nothing to do... */ } -static int lsapic_retrigger(unsigned int irq) +static int lsapic_retrigger(struct irq_data *data) { - ia64_resend_irq(irq); + ia64_resend_irq(data->irq); return 1; } struct irq_chip irq_type_ia64_lsapic = { - .name = "LSAPIC", - .startup = lsapic_noop_startup, - .shutdown = lsapic_noop, - .enable = lsapic_noop, - .disable = lsapic_noop, - .ack = lsapic_noop, - .end = lsapic_noop, - .retrigger = lsapic_retrigger, + .name = "LSAPIC", + .irq_startup = lsapic_noop_startup, + .irq_shutdown = lsapic_noop, + .irq_enable = lsapic_noop, + .irq_disable = lsapic_noop, + .irq_ack = lsapic_noop, + .irq_retrigger = lsapic_retrigger, }; diff --git a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c index 80d50b83d41..84fb405eee8 100644 --- a/arch/ia64/kernel/mca.c +++ b/arch/ia64/kernel/mca.c @@ -2125,7 +2125,6 @@ ia64_mca_late_init(void) cpe_poll_timer.function = ia64_mca_cpe_poll; { - struct irq_desc *desc; unsigned int irq; if (cpe_vector >= 0) { @@ -2133,8 +2132,7 @@ ia64_mca_late_init(void) irq = local_vector_to_irq(cpe_vector); if (irq > 0) { cpe_poll_enabled = 0; - desc = irq_desc + irq; - desc->status |= IRQ_PER_CPU; + irq_set_status_flags(irq, IRQ_PER_CPU); setup_irq(irq, &mca_cpe_irqaction); ia64_cpe_irq = irq; ia64_mca_register_cpev(cpe_vector); diff --git a/arch/ia64/kernel/msi_ia64.c b/arch/ia64/kernel/msi_ia64.c index 00b19a416ea..009df5434a7 100644 --- a/arch/ia64/kernel/msi_ia64.c +++ b/arch/ia64/kernel/msi_ia64.c @@ -12,12 +12,13 @@ static struct irq_chip ia64_msi_chip; #ifdef CONFIG_SMP -static int ia64_set_msi_irq_affinity(unsigned int irq, - const cpumask_t *cpu_mask) +static int ia64_set_msi_irq_affinity(struct irq_data *idata, + const cpumask_t *cpu_mask, bool force) { struct msi_msg msg; u32 addr, data; int cpu = first_cpu(*cpu_mask); + unsigned int irq = idata->irq; if (!cpu_online(cpu)) return -1; @@ -38,7 +39,7 @@ static int ia64_set_msi_irq_affinity(unsigned int irq, msg.data = data; write_msi_msg(irq, &msg); - cpumask_copy(irq_desc[irq].affinity, cpumask_of(cpu)); + cpumask_copy(idata->affinity, cpumask_of(cpu)); return 0; } @@ -55,7 +56,7 @@ int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) if (irq < 0) return irq; - set_irq_msi(irq, desc); + irq_set_msi_desc(irq, desc); cpus_and(mask, irq_to_domain(irq), cpu_online_map); dest_phys_id = cpu_physical_id(first_cpu(mask)); vector = irq_to_vector(irq); @@ -74,7 +75,7 @@ int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) MSI_DATA_VECTOR(vector); write_msi_msg(irq, &msg); - set_irq_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq); + irq_set_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq); return 0; } @@ -84,16 +85,16 @@ void ia64_teardown_msi_irq(unsigned int irq) destroy_irq(irq); } -static void ia64_ack_msi_irq(unsigned int irq) +static void ia64_ack_msi_irq(struct irq_data *data) { - irq_complete_move(irq); - move_native_irq(irq); + irq_complete_move(data->irq); + irq_move_irq(data); ia64_eoi(); } -static int ia64_msi_retrigger_irq(unsigned int irq) +static int ia64_msi_retrigger_irq(struct irq_data *data) { - unsigned int vector = irq_to_vector(irq); + unsigned int vector = irq_to_vector(data->irq); ia64_resend_irq(vector); return 1; @@ -103,14 +104,14 @@ static int ia64_msi_retrigger_irq(unsigned int irq) * Generic ops used on most IA64 platforms. */ static struct irq_chip ia64_msi_chip = { - .name = "PCI-MSI", - .irq_mask = mask_msi_irq, - .irq_unmask = unmask_msi_irq, - .ack = ia64_ack_msi_irq, + .name = "PCI-MSI", + .irq_mask = mask_msi_irq, + .irq_unmask = unmask_msi_irq, + .irq_ack = ia64_ack_msi_irq, #ifdef CONFIG_SMP - .set_affinity = ia64_set_msi_irq_affinity, + .irq_set_affinity = ia64_set_msi_irq_affinity, #endif - .retrigger = ia64_msi_retrigger_irq, + .irq_retrigger = ia64_msi_retrigger_irq, }; @@ -132,8 +133,10 @@ void arch_teardown_msi_irq(unsigned int irq) #ifdef CONFIG_DMAR #ifdef CONFIG_SMP -static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) +static int dmar_msi_set_affinity(struct irq_data *data, + const struct cpumask *mask, bool force) { + unsigned int irq = data->irq; struct irq_cfg *cfg = irq_cfg + irq; struct msi_msg msg; int cpu = cpumask_first(mask); @@ -152,7 +155,7 @@ static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) msg.address_lo |= MSI_ADDR_DEST_ID_CPU(cpu_physical_id(cpu)); dmar_msi_write(irq, &msg); - cpumask_copy(irq_desc[irq].affinity, mask); + cpumask_copy(data->affinity, mask); return 0; } @@ -162,11 +165,11 @@ static struct irq_chip dmar_msi_type = { .name = "DMAR_MSI", .irq_unmask = dmar_msi_unmask, .irq_mask = dmar_msi_mask, - .ack = ia64_ack_msi_irq, + .irq_ack = ia64_ack_msi_irq, #ifdef CONFIG_SMP - .set_affinity = dmar_msi_set_affinity, + .irq_set_affinity = dmar_msi_set_affinity, #endif - .retrigger = ia64_msi_retrigger_irq, + .irq_retrigger = ia64_msi_retrigger_irq, }; static int @@ -203,8 +206,8 @@ int arch_setup_dmar_msi(unsigned int irq) if (ret < 0) return ret; dmar_msi_write(irq, &msg); - set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, - "edge"); + irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, + "edge"); return 0; } #endif /* CONFIG_DMAR */ diff --git a/arch/ia64/kernel/perfmon_default_smpl.c b/arch/ia64/kernel/perfmon_default_smpl.c index 5f637bbfccc..30c644ea44c 100644 --- a/arch/ia64/kernel/perfmon_default_smpl.c +++ b/arch/ia64/kernel/perfmon_default_smpl.c @@ -150,7 +150,7 @@ default_handler(struct task_struct *task, void *buf, pfm_ovfl_arg_t *arg, struct * current = task running at the time of the overflow. * * per-task mode: - * - this is ususally the task being monitored. + * - this is usually the task being monitored. * Under certain conditions, it might be a different task * * system-wide: diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c index 911cf974970..5e2c72498c5 100644 --- a/arch/ia64/kernel/setup.c +++ b/arch/ia64/kernel/setup.c @@ -479,25 +479,7 @@ static __init int setup_nomca(char *s) } early_param("nomca", setup_nomca); -/* - * Note: elfcorehdr_addr is not just limited to vmcore. It is also used by - * is_kdump_kernel() to determine if we are booting after a panic. Hence - * ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE. - */ #ifdef CONFIG_CRASH_DUMP -/* elfcorehdr= specifies the location of elf core header - * stored by the crashed kernel. - */ -static int __init parse_elfcorehdr(char *arg) -{ - if (!arg) - return -EINVAL; - - elfcorehdr_addr = memparse(arg, &arg); - return 0; -} -early_param("elfcorehdr", parse_elfcorehdr); - int __init reserve_elfcorehdr(u64 *start, u64 *end) { u64 length; diff --git a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c index d003b502a43..14ec641003d 100644 --- a/arch/ia64/kernel/smpboot.c +++ b/arch/ia64/kernel/smpboot.c @@ -677,7 +677,7 @@ extern void fixup_irqs(void); int migrate_platform_irqs(unsigned int cpu) { int new_cpei_cpu; - struct irq_desc *desc = NULL; + struct irq_data *data = NULL; const struct cpumask *mask; int retval = 0; @@ -693,20 +693,20 @@ int migrate_platform_irqs(unsigned int cpu) new_cpei_cpu = any_online_cpu(cpu_online_map); mask = cpumask_of(new_cpei_cpu); set_cpei_target_cpu(new_cpei_cpu); - desc = irq_desc + ia64_cpe_irq; + data = irq_get_irq_data(ia64_cpe_irq); /* * Switch for now, immediately, we need to do fake intr * as other interrupts, but need to study CPEI behaviour with * polling before making changes. */ - if (desc) { - desc->chip->disable(ia64_cpe_irq); - desc->chip->set_affinity(ia64_cpe_irq, mask); - desc->chip->enable(ia64_cpe_irq); - printk ("Re-targetting CPEI to cpu %d\n", new_cpei_cpu); + if (data && data->chip) { + data->chip->irq_disable(data); + data->chip->irq_set_affinity(data, mask, false); + data->chip->irq_enable(data); + printk ("Re-targeting CPEI to cpu %d\n", new_cpei_cpu); } } - if (!desc) { + if (!data) { printk ("Unable to retarget CPEI, offline cpu [%d] failed\n", cpu); retval = -EBUSY; } diff --git a/arch/ia64/kernel/topology.c b/arch/ia64/kernel/topology.c index 0baa1bbb65f..0e0e0cc9e39 100644 --- a/arch/ia64/kernel/topology.c +++ b/arch/ia64/kernel/topology.c @@ -43,7 +43,7 @@ int __ref arch_register_cpu(int num) { #ifdef CONFIG_ACPI /* - * If CPEI can be re-targetted or if this is not + * If CPEI can be re-targeted or if this is not * CPEI target, then it is hotpluggable */ if (can_cpei_retarget() || !is_cpu_cpei_target(num)) diff --git a/arch/ia64/kvm/Makefile b/arch/ia64/kvm/Makefile index 1089b3e918a..db3d7c5d107 100644 --- a/arch/ia64/kvm/Makefile +++ b/arch/ia64/kvm/Makefile @@ -45,8 +45,8 @@ FORCE : $(obj)/$(offsets-file) # Makefile for Kernel-based Virtual Machine module # -EXTRA_CFLAGS += -Ivirt/kvm -Iarch/ia64/kvm/ -EXTRA_AFLAGS += -Ivirt/kvm -Iarch/ia64/kvm/ +ccflags-y := -Ivirt/kvm -Iarch/ia64/kvm/ +asflags-y := -Ivirt/kvm -Iarch/ia64/kvm/ common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o ioapic.o \ coalesced_mmio.o irq_comm.o assigned-dev.o) diff --git a/arch/ia64/kvm/process.c b/arch/ia64/kvm/process.c index bb862fb224f..b0398740b48 100644 --- a/arch/ia64/kvm/process.c +++ b/arch/ia64/kvm/process.c @@ -987,7 +987,7 @@ static void vmm_sanity_check(struct kvm_vcpu *vcpu) static void kvm_do_resume_op(struct kvm_vcpu *vcpu) { - vmm_sanity_check(vcpu); /*Guarantee vcpu runing on healthy vmm!*/ + vmm_sanity_check(vcpu); /*Guarantee vcpu running on healthy vmm!*/ if (test_and_clear_bit(KVM_REQ_RESUME, &vcpu->requests)) { vcpu_do_resume(vcpu); diff --git a/arch/ia64/lib/do_csum.S b/arch/ia64/lib/do_csum.S index 6bec2fc9f5b..1a431a5cf86 100644 --- a/arch/ia64/lib/do_csum.S +++ b/arch/ia64/lib/do_csum.S @@ -201,7 +201,7 @@ GLOBAL_ENTRY(do_csum) ;; (p6) adds result1[0]=1,result1[0] (p9) br.cond.sptk .do_csum_exit // if (count == 1) exit - // Fall through to caluculate the checksum, feeding result1[0] as + // Fall through to calculate the checksum, feeding result1[0] as // the initial value in result1[0]. // // Calculate the checksum loading two 8-byte words per loop. diff --git a/arch/ia64/mm/contig.c b/arch/ia64/mm/contig.c index 54bf5405981..9a018cde5d8 100644 --- a/arch/ia64/mm/contig.c +++ b/arch/ia64/mm/contig.c @@ -36,7 +36,7 @@ static unsigned long max_gap; * Shows a simple page count of reserved and used pages in the system. * For discontig machines, it does this on a per-pgdat basis. */ -void show_mem(void) +void show_mem(unsigned int filter) { int i, total_reserved = 0; int total_shared = 0, total_cached = 0; diff --git a/arch/ia64/mm/discontig.c b/arch/ia64/mm/discontig.c index 61620323bb6..82ab1bc6afb 100644 --- a/arch/ia64/mm/discontig.c +++ b/arch/ia64/mm/discontig.c @@ -614,7 +614,7 @@ void __cpuinit *per_cpu_init(void) * Shows a simple page count of reserved and used pages in the system. * For discontig machines, it does this on a per-pgdat basis. */ -void show_mem(void) +void show_mem(unsigned int filter) { int i, total_reserved = 0; int total_shared = 0, total_cached = 0; diff --git a/arch/ia64/sn/kernel/Makefile b/arch/ia64/sn/kernel/Makefile index 0591038735a..d27df1d45da 100644 --- a/arch/ia64/sn/kernel/Makefile +++ b/arch/ia64/sn/kernel/Makefile @@ -7,7 +7,7 @@ # Copyright (C) 1999,2001-2006,2008 Silicon Graphics, Inc. All Rights Reserved. # -EXTRA_CFLAGS += -Iarch/ia64/sn/include +ccflags-y := -Iarch/ia64/sn/include obj-y += setup.o bte.o bte_error.o irq.o mca.o idle.o \ huberror.o io_acpi_init.o io_common.o \ diff --git a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c index 13c15d96809..81a1f4e6bcd 100644 --- a/arch/ia64/sn/kernel/irq.c +++ b/arch/ia64/sn/kernel/irq.c @@ -23,11 +23,9 @@ #include <asm/sn/sn_sal.h> #include <asm/sn/sn_feature_sets.h> -static void force_interrupt(int irq); static void register_intr_pda(struct sn_irq_info *sn_irq_info); static void unregister_intr_pda(struct sn_irq_info *sn_irq_info); -int sn_force_interrupt_flag = 1; extern int sn_ioif_inited; struct list_head **sn_irq_lh; static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */ @@ -78,62 +76,40 @@ u64 sn_intr_redirect(nasid_t local_nasid, int local_widget, return ret_stuff.status; } -static unsigned int sn_startup_irq(unsigned int irq) +static unsigned int sn_startup_irq(struct irq_data *data) { return 0; } -static void sn_shutdown_irq(unsigned int irq) +static void sn_shutdown_irq(struct irq_data *data) { } extern void ia64_mca_register_cpev(int); -static void sn_disable_irq(unsigned int irq) +static void sn_disable_irq(struct irq_data *data) { - if (irq == local_vector_to_irq(IA64_CPE_VECTOR)) + if (data->irq == local_vector_to_irq(IA64_CPE_VECTOR)) ia64_mca_register_cpev(0); } -static void sn_enable_irq(unsigned int irq) +static void sn_enable_irq(struct irq_data *data) { - if (irq == local_vector_to_irq(IA64_CPE_VECTOR)) - ia64_mca_register_cpev(irq); + if (data->irq == local_vector_to_irq(IA64_CPE_VECTOR)) + ia64_mca_register_cpev(data->irq); } -static void sn_ack_irq(unsigned int irq) +static void sn_ack_irq(struct irq_data *data) { u64 event_occurred, mask; + unsigned int irq = data->irq & 0xff; - irq = irq & 0xff; event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED)); mask = event_occurred & SH_ALL_INT_MASK; HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask); __set_bit(irq, (volatile void *)pda->sn_in_service_ivecs); - move_native_irq(irq); -} - -static void sn_end_irq(unsigned int irq) -{ - int ivec; - u64 event_occurred; - - ivec = irq & 0xff; - if (ivec == SGI_UART_VECTOR) { - event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR (SH_EVENT_OCCURRED)); - /* If the UART bit is set here, we may have received an - * interrupt from the UART that the driver missed. To - * make sure, we IPI ourselves to force us to look again. - */ - if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) { - platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR, - IA64_IPI_DM_INT, 0); - } - } - __clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs); - if (sn_force_interrupt_flag) - force_interrupt(irq); + irq_move_irq(data); } static void sn_irq_info_free(struct rcu_head *head); @@ -228,9 +204,11 @@ finish_up: return new_irq_info; } -static int sn_set_affinity_irq(unsigned int irq, const struct cpumask *mask) +static int sn_set_affinity_irq(struct irq_data *data, + const struct cpumask *mask, bool force) { struct sn_irq_info *sn_irq_info, *sn_irq_info_safe; + unsigned int irq = data->irq; nasid_t nasid; int slice; @@ -249,7 +227,7 @@ void sn_set_err_irq_affinity(unsigned int irq) { /* * On systems which support CPU disabling (SHub2), all error interrupts - * are targetted at the boot CPU. + * are targeted at the boot CPU. */ if (is_shub2() && sn_prom_feature_available(PRF_CPU_DISABLE_SUPPORT)) set_irq_affinity_info(irq, cpu_physical_id(0), 0); @@ -259,26 +237,25 @@ void sn_set_err_irq_affinity(unsigned int irq) { } #endif static void -sn_mask_irq(unsigned int irq) +sn_mask_irq(struct irq_data *data) { } static void -sn_unmask_irq(unsigned int irq) +sn_unmask_irq(struct irq_data *data) { } struct irq_chip irq_type_sn = { - .name = "SN hub", - .startup = sn_startup_irq, - .shutdown = sn_shutdown_irq, - .enable = sn_enable_irq, - .disable = sn_disable_irq, - .ack = sn_ack_irq, - .end = sn_end_irq, - .mask = sn_mask_irq, - .unmask = sn_unmask_irq, - .set_affinity = sn_set_affinity_irq + .name = "SN hub", + .irq_startup = sn_startup_irq, + .irq_shutdown = sn_shutdown_irq, + .irq_enable = sn_enable_irq, + .irq_disable = sn_disable_irq, + .irq_ack = sn_ack_irq, + .irq_mask = sn_mask_irq, + .irq_unmask = sn_unmask_irq, + .irq_set_affinity = sn_set_affinity_irq }; ia64_vector sn_irq_to_vector(int irq) @@ -296,15 +273,13 @@ unsigned int sn_local_vector_to_irq(u8 vector) void sn_irq_init(void) { int i; - struct irq_desc *base_desc = irq_desc; ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR; ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR; for (i = 0; i < NR_IRQS; i++) { - if (base_desc[i].chip == &no_irq_chip) { - base_desc[i].chip = &irq_type_sn; - } + if (irq_get_chip(i) == &no_irq_chip) + irq_set_chip(i, &irq_type_sn); } } @@ -378,7 +353,6 @@ void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info) int cpu = nasid_slice_to_cpuid(nasid, slice); #ifdef CONFIG_SMP int cpuphys; - struct irq_desc *desc; #endif pci_dev_get(pci_dev); @@ -395,12 +369,11 @@ void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info) #ifdef CONFIG_SMP cpuphys = cpu_physical_id(cpu); set_irq_affinity_info(sn_irq_info->irq_irq, cpuphys, 0); - desc = irq_to_desc(sn_irq_info->irq_irq); /* * Affinity was set by the PROM, prevent it from * being reset by the request_irq() path. */ - desc->status |= IRQ_AFFINITY_SET; + irqd_mark_affinity_was_set(irq_get_irq_data(sn_irq_info->irq_irq)); #endif } @@ -439,25 +412,11 @@ sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info) pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type]; /* Don't force an interrupt if the irq has been disabled */ - if (!(irq_desc[sn_irq_info->irq_irq].status & IRQ_DISABLED) && + if (!irqd_irq_disabled(irq_get_irq_data(sn_irq_info->irq_irq)) && pci_provider && pci_provider->force_interrupt) (*pci_provider->force_interrupt)(sn_irq_info); } -static void force_interrupt(int irq) -{ - struct sn_irq_info *sn_irq_info; - - if (!sn_ioif_inited) - return; - - rcu_read_lock(); - list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list) - sn_call_force_intr_provider(sn_irq_info); - - rcu_read_unlock(); -} - /* * Check for lost interrupts. If the PIC int_status reg. says that * an interrupt has been sent, but not handled, and the interrupt @@ -476,7 +435,7 @@ static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info) /* * Bridge types attached to TIO (anything but PIC) do not need this WAR * since they do not target Shub II interrupt registers. If that - * ever changes, this check needs to accomodate. + * ever changes, this check needs to accommodate. */ if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC) return; diff --git a/arch/ia64/sn/kernel/msi_sn.c b/arch/ia64/sn/kernel/msi_sn.c index a5e500f0285..2b98b9e088d 100644 --- a/arch/ia64/sn/kernel/msi_sn.c +++ b/arch/ia64/sn/kernel/msi_sn.c @@ -144,16 +144,16 @@ int sn_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *entry) */ msg.data = 0x100 + irq; - set_irq_msi(irq, entry); + irq_set_msi_desc(irq, entry); write_msi_msg(irq, &msg); - set_irq_chip_and_handler(irq, &sn_msi_chip, handle_edge_irq); + irq_set_chip_and_handler(irq, &sn_msi_chip, handle_edge_irq); return 0; } #ifdef CONFIG_SMP -static int sn_set_msi_irq_affinity(unsigned int irq, - const struct cpumask *cpu_mask) +static int sn_set_msi_irq_affinity(struct irq_data *data, + const struct cpumask *cpu_mask, bool force) { struct msi_msg msg; int slice; @@ -164,7 +164,7 @@ static int sn_set_msi_irq_affinity(unsigned int irq, struct sn_irq_info *sn_irq_info; struct sn_irq_info *new_irq_info; struct sn_pcibus_provider *provider; - unsigned int cpu; + unsigned int cpu, irq = data->irq; cpu = cpumask_first(cpu_mask); sn_irq_info = sn_msi_info[irq].sn_irq_info; @@ -206,33 +206,33 @@ static int sn_set_msi_irq_affinity(unsigned int irq, msg.address_lo = (u32)(bus_addr & 0x00000000ffffffff); write_msi_msg(irq, &msg); - cpumask_copy(irq_desc[irq].affinity, cpu_mask); + cpumask_copy(data->affinity, cpu_mask); return 0; } #endif /* CONFIG_SMP */ -static void sn_ack_msi_irq(unsigned int irq) +static void sn_ack_msi_irq(struct irq_data *data) { - move_native_irq(irq); + irq_move_irq(data); ia64_eoi(); } -static int sn_msi_retrigger_irq(unsigned int irq) +static int sn_msi_retrigger_irq(struct irq_data *data) { - unsigned int vector = irq; + unsigned int vector = data->irq; ia64_resend_irq(vector); return 1; } static struct irq_chip sn_msi_chip = { - .name = "PCI-MSI", - .irq_mask = mask_msi_irq, - .irq_unmask = unmask_msi_irq, - .ack = sn_ack_msi_irq, + .name = "PCI-MSI", + .irq_mask = mask_msi_irq, + .irq_unmask = unmask_msi_irq, + .irq_ack = sn_ack_msi_irq, #ifdef CONFIG_SMP - .set_affinity = sn_set_msi_irq_affinity, + .irq_set_affinity = sn_set_msi_irq_affinity, #endif - .retrigger = sn_msi_retrigger_irq, + .irq_retrigger = sn_msi_retrigger_irq, }; diff --git a/arch/ia64/sn/kernel/sn2/Makefile b/arch/ia64/sn/kernel/sn2/Makefile index 08e6565dc90..3d09108d427 100644 --- a/arch/ia64/sn/kernel/sn2/Makefile +++ b/arch/ia64/sn/kernel/sn2/Makefile @@ -9,7 +9,7 @@ # sn2 specific kernel files # -EXTRA_CFLAGS += -Iarch/ia64/sn/include +ccflags-y := -Iarch/ia64/sn/include obj-y += cache.o io.o ptc_deadlock.o sn2_smp.o sn_proc_fs.o \ prominfo_proc.o timer.o timer_interrupt.o sn_hwperf.o diff --git a/arch/ia64/sn/kernel/sn2/sn_proc_fs.c b/arch/ia64/sn/kernel/sn2/sn_proc_fs.c index c76d8dc3aea..7aab87f4806 100644 --- a/arch/ia64/sn/kernel/sn2/sn_proc_fs.c +++ b/arch/ia64/sn/kernel/sn2/sn_proc_fs.c @@ -45,38 +45,6 @@ static int licenseID_open(struct inode *inode, struct file *file) return single_open(file, licenseID_show, NULL); } -/* - * Enable forced interrupt by default. - * When set, the sn interrupt handler writes the force interrupt register on - * the bridge chip. The hardware will then send an interrupt message if the - * interrupt line is active. This mimics a level sensitive interrupt. - */ -extern int sn_force_interrupt_flag; - -static int sn_force_interrupt_show(struct seq_file *s, void *p) -{ - seq_printf(s, "Force interrupt is %s\n", - sn_force_interrupt_flag ? "enabled" : "disabled"); - return 0; -} - -static ssize_t sn_force_interrupt_write_proc(struct file *file, - const char __user *buffer, size_t count, loff_t *data) -{ - char val; - - if (copy_from_user(&val, buffer, 1)) - return -EFAULT; - - sn_force_interrupt_flag = (val == '0') ? 0 : 1; - return count; -} - -static int sn_force_interrupt_open(struct inode *inode, struct file *file) -{ - return single_open(file, sn_force_interrupt_show, NULL); -} - static int coherence_id_show(struct seq_file *s, void *p) { seq_printf(s, "%d\n", partition_coherence_id()); @@ -114,14 +82,6 @@ static const struct file_operations proc_license_id_fops = { .release = single_release, }; -static const struct file_operations proc_sn_force_intr_fops = { - .open = sn_force_interrupt_open, - .read = seq_read, - .write = sn_force_interrupt_write_proc, - .llseek = seq_lseek, - .release = single_release, -}; - static const struct file_operations proc_coherence_id_fops = { .open = coherence_id_open, .read = seq_read, @@ -149,8 +109,6 @@ void register_sn_procfs(void) proc_create("system_serial_number", 0444, sgi_proc_dir, &proc_system_sn_fops); proc_create("licenseID", 0444, sgi_proc_dir, &proc_license_id_fops); - proc_create("sn_force_interrupt", 0644, sgi_proc_dir, - &proc_sn_force_intr_fops); proc_create("coherence_id", 0444, sgi_proc_dir, &proc_coherence_id_fops); proc_create("sn_topology", 0444, sgi_proc_dir, &proc_sn_topo_fops); diff --git a/arch/ia64/sn/pci/Makefile b/arch/ia64/sn/pci/Makefile index ad4ef34dfe2..df2a9014542 100644 --- a/arch/ia64/sn/pci/Makefile +++ b/arch/ia64/sn/pci/Makefile @@ -7,6 +7,6 @@ # # Makefile for the sn pci general routines. -EXTRA_CFLAGS += -Iarch/ia64/sn/include +ccflags-y := -Iarch/ia64/sn/include obj-y := pci_dma.o tioca_provider.o tioce_provider.o pcibr/ diff --git a/arch/ia64/sn/pci/pcibr/Makefile b/arch/ia64/sn/pci/pcibr/Makefile index 01192d3247d..396bcae3630 100644 --- a/arch/ia64/sn/pci/pcibr/Makefile +++ b/arch/ia64/sn/pci/pcibr/Makefile @@ -7,7 +7,7 @@ # # Makefile for the sn2 io routines. -EXTRA_CFLAGS += -Iarch/ia64/sn/include +ccflags-y := -Iarch/ia64/sn/include obj-y += pcibr_dma.o pcibr_reg.o \ pcibr_ate.o pcibr_provider.o diff --git a/arch/ia64/sn/pci/pcibr/pcibr_dma.c b/arch/ia64/sn/pci/pcibr/pcibr_dma.c index c659ad5613a..33def666a66 100644 --- a/arch/ia64/sn/pci/pcibr/pcibr_dma.c +++ b/arch/ia64/sn/pci/pcibr/pcibr_dma.c @@ -227,7 +227,7 @@ pcibr_dma_unmap(struct pci_dev *hwdev, dma_addr_t dma_handle, int direction) * after doing the read. For PIC this routine then forces a fake interrupt * on another line, which is logically associated with the slot that the PIO * is addressed to. It then spins while watching the memory location that - * the interrupt is targetted to. When the interrupt response arrives, we + * the interrupt is targeted to. When the interrupt response arrives, we * are sure that the DMA has landed in memory and it is safe for the driver * to proceed. For TIOCP use the Device(x) Write Request Buffer Flush * Bridge register since it ensures the data has entered the coherence domain, diff --git a/arch/ia64/uv/kernel/Makefile b/arch/ia64/uv/kernel/Makefile index 8d92b4684d8..124e441d383 100644 --- a/arch/ia64/uv/kernel/Makefile +++ b/arch/ia64/uv/kernel/Makefile @@ -7,7 +7,7 @@ # Copyright (C) 2008 Silicon Graphics, Inc. All Rights Reserved. # -EXTRA_CFLAGS += -Iarch/ia64/sn/include +ccflags-y := -Iarch/ia64/sn/include obj-y += setup.o obj-$(CONFIG_IA64_GENERIC) += machvec.o diff --git a/arch/ia64/xen/irq_xen.c b/arch/ia64/xen/irq_xen.c index a3fb7cf9ae1..108bb858acf 100644 --- a/arch/ia64/xen/irq_xen.c +++ b/arch/ia64/xen/irq_xen.c @@ -138,7 +138,6 @@ static void __xen_register_percpu_irq(unsigned int cpu, unsigned int vec, struct irqaction *action, int save) { - struct irq_desc *desc; int irq = 0; if (xen_slab_ready) { @@ -223,8 +222,7 @@ __xen_register_percpu_irq(unsigned int cpu, unsigned int vec, * mark the interrupt for migrations and trigger it * on cpu hotplug. */ - desc = irq_desc + irq; - desc->status |= IRQ_PER_CPU; + irq_set_status_flags(irq, IRQ_PER_CPU); } } diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig index ef4c1e442be..736b808d229 100644 --- a/arch/m32r/Kconfig +++ b/arch/m32r/Kconfig @@ -8,8 +8,8 @@ config M32R select HAVE_KERNEL_BZIP2 select HAVE_KERNEL_LZMA select HAVE_GENERIC_HARDIRQS - select GENERIC_HARDIRQS_NO_DEPRECATED select GENERIC_IRQ_PROBE + select GENERIC_IRQ_SHOW config SBUS bool @@ -260,6 +260,10 @@ config GENERIC_FIND_NEXT_BIT bool default y +config GENERIC_FIND_BIT_LE + bool + default y + config GENERIC_HWEIGHT bool default y diff --git a/arch/m32r/include/asm/bitops.h b/arch/m32r/include/asm/bitops.h index aaddf0d5760..6300f22cdbd 100644 --- a/arch/m32r/include/asm/bitops.h +++ b/arch/m32r/include/asm/bitops.h @@ -266,9 +266,8 @@ static __inline__ int test_and_change_bit(int nr, volatile void * addr) #ifdef __KERNEL__ -#include <asm-generic/bitops/ext2-non-atomic.h> +#include <asm-generic/bitops/le.h> #include <asm-generic/bitops/ext2-atomic.h> -#include <asm-generic/bitops/minix.h> #endif /* __KERNEL__ */ diff --git a/arch/m32r/include/asm/m32104ut/m32104ut_pld.h b/arch/m32r/include/asm/m32104ut/m32104ut_pld.h index 2dc89d68b6d..1feae9709f2 100644 --- a/arch/m32r/include/asm/m32104ut/m32104ut_pld.h +++ b/arch/m32r/include/asm/m32104ut/m32104ut_pld.h @@ -4,7 +4,7 @@ /* * include/asm-m32r/m32104ut/m32104ut_pld.h * - * Definitions for Programable Logic Device(PLD) on M32104UT board. + * Definitions for Programmable Logic Device(PLD) on M32104UT board. * Based on m32700ut_pld.h * * Copyright (c) 2002 Takeo Takahashi diff --git a/arch/m32r/include/asm/m32700ut/m32700ut_pld.h b/arch/m32r/include/asm/m32700ut/m32700ut_pld.h index 57623beb44c..35294670b18 100644 --- a/arch/m32r/include/asm/m32700ut/m32700ut_pld.h +++ b/arch/m32r/include/asm/m32700ut/m32700ut_pld.h @@ -4,7 +4,7 @@ /* * include/asm-m32r/m32700ut/m32700ut_pld.h * - * Definitions for Programable Logic Device(PLD) on M32700UT board. + * Definitions for Programmable Logic Device(PLD) on M32700UT board. * * Copyright (c) 2002 Takeo Takahashi * diff --git a/arch/m32r/include/asm/opsput/opsput_pld.h b/arch/m32r/include/asm/opsput/opsput_pld.h index 3f11ea1aac2..6901401fe9e 100644 --- a/arch/m32r/include/asm/opsput/opsput_pld.h +++ b/arch/m32r/include/asm/opsput/opsput_pld.h @@ -4,7 +4,7 @@ /* * include/asm-m32r/opsput/opsput_pld.h * - * Definitions for Programable Logic Device(PLD) on OPSPUT board. + * Definitions for Programmable Logic Device(PLD) on OPSPUT board. * * Copyright (c) 2002 Takeo Takahashi * diff --git a/arch/m32r/include/asm/pgtable-2level.h b/arch/m32r/include/asm/pgtable-2level.h index bca3475f959..9cdaf7350ef 100644 --- a/arch/m32r/include/asm/pgtable-2level.h +++ b/arch/m32r/include/asm/pgtable-2level.h @@ -44,7 +44,7 @@ static inline int pgd_present(pgd_t pgd) { return 1; } #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) /* - * (pmds are folded into pgds so this doesnt get actually called, + * (pmds are folded into pgds so this doesn't get actually called, * but the define is needed for a generic inline function.) */ #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) diff --git a/arch/m32r/include/asm/thread_info.h b/arch/m32r/include/asm/thread_info.h index 71faff5bcc2..0227dba4406 100644 --- a/arch/m32r/include/asm/thread_info.h +++ b/arch/m32r/include/asm/thread_info.h @@ -96,16 +96,11 @@ static inline struct thread_info *current_thread_info(void) /* thread information allocation */ #ifdef CONFIG_DEBUG_STACK_USAGE -#define alloc_thread_info(tsk) \ - ({ \ - struct thread_info *ret; \ - \ - ret = kzalloc(THREAD_SIZE, GFP_KERNEL); \ - \ - ret; \ - }) +#define alloc_thread_info_node(tsk, node) \ + kzalloc_node(THREAD_SIZE, GFP_KERNEL, node) #else -#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL) +#define alloc_thread_info_node(tsk, node) \ + kmalloc_node(THREAD_SIZE, GFP_KERNEL, node) #endif #define free_thread_info(info) kfree(info) diff --git a/arch/m32r/include/asm/types.h b/arch/m32r/include/asm/types.h index bc9f7fff0ac..bd0035597b3 100644 --- a/arch/m32r/include/asm/types.h +++ b/arch/m32r/include/asm/types.h @@ -16,15 +16,6 @@ typedef unsigned short umode_t; #define BITS_PER_LONG 32 -#ifndef __ASSEMBLY__ - -/* DMA addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; -typedef u64 dma64_addr_t; - -#endif /* __ASSEMBLY__ */ - #endif /* __KERNEL__ */ #endif /* _ASM_M32R_TYPES_H */ diff --git a/arch/m32r/kernel/irq.c b/arch/m32r/kernel/irq.c index 76eaf3883fb..c7272b89428 100644 --- a/arch/m32r/kernel/irq.c +++ b/arch/m32r/kernel/irq.c @@ -18,55 +18,10 @@ #include <linux/kernel_stat.h> #include <linux/interrupt.h> -#include <linux/seq_file.h> #include <linux/module.h> #include <asm/uaccess.h> /* - * Generic, controller-independent functions: - */ - -int show_interrupts(struct seq_file *p, void *v) -{ - int i = *(loff_t *) v, j; - struct irqaction * action; - unsigned long flags; - - if (i == 0) { - seq_printf(p, " "); - for_each_online_cpu(j) - seq_printf(p, "CPU%d ",j); - seq_putc(p, '\n'); - } - - if (i < NR_IRQS) { - struct irq_desc *desc = irq_to_desc(i); - - raw_spin_lock_irqsave(&desc->lock, flags); - action = desc->action; - if (!action) - goto skip; - seq_printf(p, "%3d: ",i); -#ifndef CONFIG_SMP - seq_printf(p, "%10u ", kstat_irqs(i)); -#else - for_each_online_cpu(j) - seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); -#endif - seq_printf(p, " %14s", desc->irq_data.chip->name); - seq_printf(p, " %s", action->name); - - for (action=action->next; action; action = action->next) - seq_printf(p, ", %s", action->name); - - seq_putc(p, '\n'); -skip: - raw_spin_unlock_irqrestore(&desc->lock, flags); - } - return 0; -} - -/* * do_IRQ handles all normal device IRQs (the special * SMP cross-CPU interrupts have their own specific * handlers). diff --git a/arch/m32r/mm/fault.c b/arch/m32r/mm/fault.c index b8ec002aef8..2c9aeb45384 100644 --- a/arch/m32r/mm/fault.c +++ b/arch/m32r/mm/fault.c @@ -120,7 +120,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long error_code, /* When running in the kernel we expect faults to occur only to * addresses in user space. All other faults represent errors in the - * kernel and should generate an OOPS. Unfortunatly, in the case of an + * kernel and should generate an OOPS. Unfortunately, in the case of an * erroneous fault occurring in a code path which already holds mmap_sem * we will deadlock attempting to validate the fault against the * address space. Luckily the kernel only validly references user @@ -128,7 +128,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long error_code, * exceptions table. * * As the vast majority of faults will be valid we will only perform - * the source reference check when there is a possibilty of a deadlock. + * the source reference check when there is a possibility of a deadlock. * Attempt to lock the address space, if we cannot we then validate the * source. If this is invalid we can skip the address space check, * thus avoiding the deadlock. diff --git a/arch/m32r/platforms/m32104ut/setup.c b/arch/m32r/platforms/m32104ut/setup.c index 4a693d02c1e..34671d32cef 100644 --- a/arch/m32r/platforms/m32104ut/setup.c +++ b/arch/m32r/platforms/m32104ut/setup.c @@ -76,7 +76,7 @@ void __init init_IRQ(void) #if defined(CONFIG_SMC91X) /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ - set_irq_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type, handle_level_irq); /* "H" level sense */ cu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; @@ -84,20 +84,20 @@ void __init init_IRQ(void) #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_m32104ut_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; disable_m32104ut_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; disable_m32104ut_irq(M32R_IRQ_SIO0_S); diff --git a/arch/m32r/platforms/m32700ut/setup.c b/arch/m32r/platforms/m32700ut/setup.c index 2074bcc841e..1053e1cb740 100644 --- a/arch/m32r/platforms/m32700ut/setup.c +++ b/arch/m32r/platforms/m32700ut/setup.c @@ -259,76 +259,76 @@ void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/ - set_irq_chip_and_handler(M32700UT_LAN_IRQ_LAN, + irq_set_chip_and_handler(M32700UT_LAN_IRQ_LAN, &m32700ut_lanpld_irq_type, handle_level_irq); lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_m32700ut_irq(M32R_IRQ_MFT2); /* SIO0 : receive */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO0_R); /* SIO0 : send */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO0_S); /* SIO1 : receive */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO1_R); /* SIO1 : send */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO1_S); /* DMA1 : */ - set_irq_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_DMA1].icucr = 0; disable_m32700ut_irq(M32R_IRQ_DMA1); #ifdef CONFIG_SERIAL_M32R_PLDSIO /* INT#1: SIO0 Receive on PLD */ - set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV); /* INT#1: SIO0 Send on PLD */ - set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND); #endif /* CONFIG_SERIAL_M32R_PLDSIO */ /* INT#1: CFC IREQ on PLD */ - set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ); /* INT#1: CFC Insert on PLD */ - set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT); /* INT#1: CFC Eject on PLD */ - set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT); @@ -349,7 +349,7 @@ void __init init_IRQ(void) #if defined(CONFIG_USB) outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ - set_irq_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1, + irq_set_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1, &m32700ut_lcdpld_irq_type, handle_level_irq); lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ @@ -366,7 +366,7 @@ void __init init_IRQ(void) /* * INT3# is used for AR */ - set_irq_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_m32700ut_irq(M32R_IRQ_INT3); diff --git a/arch/m32r/platforms/mappi/setup.c b/arch/m32r/platforms/mappi/setup.c index cdd8c457402..35130ac3f8d 100644 --- a/arch/m32r/platforms/mappi/setup.c +++ b/arch/m32r/platforms/mappi/setup.c @@ -75,39 +75,39 @@ void __init init_IRQ(void) #ifdef CONFIG_NE2000 /* INT0 : LAN controller (RTL8019AS) */ - set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; disable_mappi_irq(M32R_IRQ_INT0); #endif /* CONFIG_M32R_NE2000 */ /* MFT2 : system timer */ - set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_S); @@ -115,13 +115,13 @@ void __init init_IRQ(void) #if defined(CONFIG_M32R_PCC) /* INT1 : pccard0 interrupt */ - set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; disable_mappi_irq(M32R_IRQ_INT1); /* INT2 : pccard1 interrupt */ - set_irq_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; disable_mappi_irq(M32R_IRQ_INT2); diff --git a/arch/m32r/platforms/mappi2/setup.c b/arch/m32r/platforms/mappi2/setup.c index 9117c30ea36..f3ed6b60a5f 100644 --- a/arch/m32r/platforms/mappi2/setup.c +++ b/arch/m32r/platforms/mappi2/setup.c @@ -76,38 +76,38 @@ void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT0 : LAN controller (SMC91111) */ - set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi2_irq(M32R_IRQ_INT0); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type, + irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type, handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi2_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO1_S); @@ -115,27 +115,27 @@ void __init init_IRQ(void) #if defined(CONFIG_USB) /* INT1 : USB Host controller interrupt */ - set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; disable_mappi2_irq(M32R_IRQ_INT1); #endif /* CONFIG_USB */ /* ICUCR40: CFC IREQ */ - set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type, handle_level_irq); icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; disable_mappi2_irq(PLD_IRQ_CFIREQ); #if defined(CONFIG_M32R_CFC) /* ICUCR41: CFC Insert */ - set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type, handle_level_irq); icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; disable_mappi2_irq(PLD_IRQ_CFC_INSERT); /* ICUCR42: CFC Eject */ - set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type, handle_level_irq); icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi2_irq(PLD_IRQ_CFC_EJECT); diff --git a/arch/m32r/platforms/mappi3/setup.c b/arch/m32r/platforms/mappi3/setup.c index b44f5ded2bb..2408e356ad1 100644 --- a/arch/m32r/platforms/mappi3/setup.c +++ b/arch/m32r/platforms/mappi3/setup.c @@ -75,38 +75,38 @@ void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT0 : LAN controller (SMC91111) */ - set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi3_irq(M32R_IRQ_INT0); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type, + irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type, handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi3_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO1_S); @@ -114,21 +114,21 @@ void __init init_IRQ(void) #if defined(CONFIG_USB) /* INT1 : USB Host controller interrupt */ - set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; disable_mappi3_irq(M32R_IRQ_INT1); #endif /* CONFIG_USB */ /* CFC IREQ */ - set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type, handle_level_irq); icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; disable_mappi3_irq(PLD_IRQ_CFIREQ); #if defined(CONFIG_M32R_CFC) /* ICUCR41: CFC Insert & eject */ - set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type, handle_level_irq); icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; disable_mappi3_irq(PLD_IRQ_CFC_INSERT); @@ -136,7 +136,7 @@ void __init init_IRQ(void) #endif /* CONFIG_M32R_CFC */ /* IDE IREQ */ - set_irq_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type, + irq_set_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type, handle_level_irq); icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi3_irq(PLD_IRQ_IDEIREQ); diff --git a/arch/m32r/platforms/oaks32r/setup.c b/arch/m32r/platforms/oaks32r/setup.c index 19a02db7b81..83b46b067a1 100644 --- a/arch/m32r/platforms/oaks32r/setup.c +++ b/arch/m32r/platforms/oaks32r/setup.c @@ -74,39 +74,39 @@ void __init init_IRQ(void) #ifdef CONFIG_NE2000 /* INT3 : LAN controller (RTL8019AS) */ - set_irq_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_oaks32r_irq(M32R_IRQ_INT3); #endif /* CONFIG_M32R_NE2000 */ /* MFT2 : system timer */ - set_irq_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type, + irq_set_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type, handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_oaks32r_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO1_S); diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c index 12731547e8b..32660705f5f 100644 --- a/arch/m32r/platforms/opsput/setup.c +++ b/arch/m32r/platforms/opsput/setup.c @@ -259,76 +259,76 @@ void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ - set_irq_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type, + irq_set_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type, handle_level_irq); lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - set_irq_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type, + irq_set_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type, handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_opsput_irq(M32R_IRQ_MFT2); /* SIO0 : receive */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO0_R); /* SIO0 : send */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO0_S); /* SIO1 : receive */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO1_R); /* SIO1 : send */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO1_S); /* DMA1 : */ - set_irq_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type, + irq_set_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type, handle_level_irq); icu_data[M32R_IRQ_DMA1].icucr = 0; disable_opsput_irq(M32R_IRQ_DMA1); #ifdef CONFIG_SERIAL_M32R_PLDSIO /* INT#1: SIO0 Receive on PLD */ - set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV); /* INT#1: SIO0 Send on PLD */ - set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_opsput_pld_irq(PLD_IRQ_SIO0_SND); #endif /* CONFIG_SERIAL_M32R_PLDSIO */ /* INT#1: CFC IREQ on PLD */ - set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ disable_opsput_pld_irq(PLD_IRQ_CFIREQ); /* INT#1: CFC Insert on PLD */ - set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT); /* INT#1: CFC Eject on PLD */ - set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT); @@ -349,7 +349,7 @@ void __init init_IRQ(void) #if defined(CONFIG_USB) outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ - set_irq_chip_and_handler(OPSPUT_LCD_IRQ_USB_INT1, + irq_set_chip_and_handler(OPSPUT_LCD_IRQ_USB_INT1, &opsput_lcdpld_irq_type, handle_level_irq); lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1); @@ -365,7 +365,7 @@ void __init init_IRQ(void) /* * INT3# is used for AR */ - set_irq_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_opsput_irq(M32R_IRQ_INT3); diff --git a/arch/m32r/platforms/usrv/setup.c b/arch/m32r/platforms/usrv/setup.c index f3cff26d6e7..0c7a1e8c77b 100644 --- a/arch/m32r/platforms/usrv/setup.c +++ b/arch/m32r/platforms/usrv/setup.c @@ -138,32 +138,32 @@ void __init init_IRQ(void) once++; /* MFT2 : system timer */ - set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi_irq(M32R_IRQ_MFT2); #if defined(CONFIG_SERIAL_M32R_SIO) /* SIO0_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_S); @@ -171,7 +171,7 @@ void __init init_IRQ(void) /* INT#67-#71: CFC#0 IREQ on PLD */ for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) { - set_irq_chip_and_handler(PLD_IRQ_CF0 + i, + irq_set_chip_and_handler(PLD_IRQ_CF0 + i, &m32700ut_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr @@ -181,14 +181,14 @@ void __init init_IRQ(void) #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) /* INT#76: 16552D#0 IREQ on PLD */ - set_irq_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr = PLD_ICUCR_ISMOD03; /* 'H' level sense */ disable_m32700ut_pld_irq(PLD_IRQ_UART0); /* INT#77: 16552D#1 IREQ on PLD */ - set_irq_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr = PLD_ICUCR_ISMOD03; /* 'H' level sense */ @@ -197,7 +197,7 @@ void __init init_IRQ(void) #if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) /* INT#80: AK4524 IREQ on PLD */ - set_irq_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr = PLD_ICUCR_ISMOD01; /* 'L' level sense */ diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 525174d4167..75531da02a4 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -1,13 +1,10 @@ config M68K bool default y - select HAVE_AOUT select HAVE_IDE - select GENERIC_ATOMIC64 - -config MMU - bool - default y + select HAVE_AOUT if MMU + select GENERIC_ATOMIC64 if MMU + select HAVE_GENERIC_HARDIRQS if !MMU config RWSEM_GENERIC_SPINLOCK bool @@ -34,457 +31,67 @@ config TIME_LOW_RES bool default y -config GENERIC_IOMAP - bool - default y - -config ARCH_MAY_HAVE_PC_FDC - bool - depends on BROKEN && (Q40 || SUN3X) - default y - config NO_IOPORT def_bool y config NO_DMA - def_bool SUN3 + def_bool (MMU && SUN3) || (!MMU && !COLDFIRE) +config ZONE_DMA + bool + default y config HZ int + default 1000 if CLEOPATRA default 100 -config ARCH_USES_GETTIMEOFFSET - def_bool y - source "init/Kconfig" source "kernel/Kconfig.freezer" -menu "Platform dependent setup" - -config EISA - bool - ---help--- - The Extended Industry Standard Architecture (EISA) bus was - developed as an open alternative to the IBM MicroChannel bus. - - The EISA bus provided some of the features of the IBM MicroChannel - bus while maintaining backward compatibility with cards made for - the older ISA bus. The EISA bus saw limited use between 1988 and - 1995 when it was made obsolete by the PCI bus. - - Say Y here if you are building a kernel for an EISA-based machine. - - Otherwise, say N. - -config MCA - bool - help - MicroChannel Architecture is found in some IBM PS/2 machines and - laptops. It is a bus system similar to PCI or ISA. See - <file:Documentation/mca.txt> (and especially the web page given - there) before attempting to build an MCA bus kernel. - -config PCMCIA - tristate - ---help--- - Say Y here if you want to attach PCMCIA- or PC-cards to your Linux - computer. These are credit-card size devices such as network cards, - modems or hard drives often used with laptops computers. There are - actually two varieties of these cards: the older 16 bit PCMCIA cards - and the newer 32 bit CardBus cards. If you want to use CardBus - cards, you need to say Y here and also to "CardBus support" below. - - To use your PC-cards, you will need supporting software from David - Hinds' pcmcia-cs package (see the file <file:Documentation/Changes> - for location). Please also read the PCMCIA-HOWTO, available from - <http://www.tldp.org/docs.html#howto>. - - To compile this driver as modules, choose M here: the - modules will be called pcmcia_core and ds. - -config AMIGA - bool "Amiga support" - select MMU_MOTOROLA if MMU - help - This option enables support for the Amiga series of computers. If - you plan to use this kernel on an Amiga, say Y here and browse the - material available in <file:Documentation/m68k>; otherwise say N. - -config ATARI - bool "Atari support" - select MMU_MOTOROLA if MMU - help - This option enables support for the 68000-based Atari series of - computers (including the TT, Falcon and Medusa). If you plan to use - this kernel on an Atari, say Y here and browse the material - available in <file:Documentation/m68k>; otherwise say N. - -config MAC - bool "Macintosh support" - select MMU_MOTOROLA if MMU - help - This option enables support for the Apple Macintosh series of - computers (yes, there is experimental support now, at least for part - of the series). - - Say N unless you're willing to code the remaining necessary support. - ;) - -config NUBUS - bool - depends on MAC - default y - -config M68K_L2_CACHE - bool - depends on MAC - default y - -config APOLLO - bool "Apollo support" - select MMU_MOTOROLA if MMU - help - Say Y here if you want to run Linux on an MC680x0-based Apollo - Domain workstation such as the DN3500. - -config VME - bool "VME (Motorola and BVM) support" - select MMU_MOTOROLA if MMU - help - Say Y here if you want to build a kernel for a 680x0 based VME - board. Boards currently supported include Motorola boards MVME147, - MVME162, MVME166, MVME167, MVME172, and MVME177. BVME4000 and - BVME6000 boards from BVM Ltd are also supported. - -config MVME147 - bool "MVME147 support" - depends on VME - help - Say Y to include support for early Motorola VME boards. This will - build a kernel which can run on MVME147 single-board computers. If - you select this option you will have to select the appropriate - drivers for SCSI, Ethernet and serial ports later on. - -config MVME16x - bool "MVME162, 166 and 167 support" - depends on VME - help - Say Y to include support for Motorola VME boards. This will build a - kernel which can run on MVME162, MVME166, MVME167, MVME172, and - MVME177 boards. If you select this option you will have to select - the appropriate drivers for SCSI, Ethernet and serial ports later - on. - -config BVME6000 - bool "BVME4000 and BVME6000 support" - depends on VME - help - Say Y to include support for VME boards from BVM Ltd. This will - build a kernel which can run on BVME4000 and BVME6000 boards. If - you select this option you will have to select the appropriate - drivers for SCSI, Ethernet and serial ports later on. - -config HP300 - bool "HP9000/300 and HP9000/400 support" - select MMU_MOTOROLA if MMU - help - This option enables support for the HP9000/300 and HP9000/400 series - of workstations. Support for these machines is still somewhat - experimental. If you plan to try to use the kernel on such a machine - say Y here. - Everybody else says N. - -config DIO - bool "DIO bus support" - depends on HP300 +config MMU + bool "MMU-based Paged Memory Management Support" default y help - Say Y here to enable support for the "DIO" expansion bus used in - HP300 machines. If you are using such a system you almost certainly - want this. - -config SUN3X - bool "Sun3x support" - select MMU_MOTOROLA if MMU - select M68030 - help - This option enables support for the Sun 3x series of workstations. - Be warned that this support is very experimental. - Note that Sun 3x kernels are not compatible with Sun 3 hardware. - General Linux information on the Sun 3x series (now discontinued) - is at <http://www.angelfire.com/ca2/tech68k/sun3.html>. - - If you don't want to compile a kernel for a Sun 3x, say N. - -config Q40 - bool "Q40/Q60 support" - select MMU_MOTOROLA if MMU - help - The Q40 is a Motorola 68040-based successor to the Sinclair QL - manufactured in Germany. There is an official Q40 home page at - <http://www.q40.de/>. This option enables support for the Q40 and - Q60. Select your CPU below. For 68LC060 don't forget to enable FPU - emulation. - -config SUN3 - bool "Sun3 support" - depends on !MMU_MOTOROLA - select MMU_SUN3 if MMU - select M68020 - help - This option enables support for the Sun 3 series of workstations - (3/50, 3/60, 3/1xx, 3/2xx systems). Enabling this option requires - that all other hardware types must be disabled, as Sun 3 kernels - are incompatible with all other m68k targets (including Sun 3x!). - - If you don't want to compile a kernel exclusively for a Sun 3, say N. - -config NATFEAT - bool "ARAnyM emulator support" - depends on ATARI - help - This option enables support for ARAnyM native features, such as - access to a disk image as /dev/hda. - -config NFBLOCK - tristate "NatFeat block device support" - depends on BLOCK && NATFEAT - help - Say Y to include support for the ARAnyM NatFeat block device - which allows direct access to the hard drives without using - the hardware emulation. - -config NFCON - tristate "NatFeat console driver" - depends on NATFEAT - help - Say Y to include support for the ARAnyM NatFeat console driver - which allows the console output to be redirected to the stderr - output of ARAnyM. - -config NFETH - tristate "NatFeat Ethernet support" - depends on NET_ETHERNET && NATFEAT - help - Say Y to include support for the ARAnyM NatFeat network device - which will emulate a regular ethernet device while presenting an - ethertap device to the host system. - -comment "Processor type" - -config M68020 - bool "68020 support" - help - If you anticipate running this kernel on a computer with a MC68020 - processor, say Y. Otherwise, say N. Note that the 68020 requires a - 68851 MMU (Memory Management Unit) to run Linux/m68k, except on the - Sun 3, which provides its own version. - -config M68030 - bool "68030 support" - depends on !MMU_SUN3 - help - If you anticipate running this kernel on a computer with a MC68030 - processor, say Y. Otherwise, say N. Note that a MC68EC030 will not - work, as it does not include an MMU (Memory Management Unit). - -config M68040 - bool "68040 support" - depends on !MMU_SUN3 - help - If you anticipate running this kernel on a computer with a MC68LC040 - or MC68040 processor, say Y. Otherwise, say N. Note that an - MC68EC040 will not work, as it does not include an MMU (Memory - Management Unit). - -config M68060 - bool "68060 support" - depends on !MMU_SUN3 - help - If you anticipate running this kernel on a computer with a MC68060 - processor, say Y. Otherwise, say N. - -config MMU_MOTOROLA - bool - -config MMU_SUN3 - bool - depends on MMU && !MMU_MOTOROLA - -config M68KFPU_EMU - bool "Math emulation support (EXPERIMENTAL)" - depends on EXPERIMENTAL - help - At some point in the future, this will cause floating-point math - instructions to be emulated by the kernel on machines that lack a - floating-point math coprocessor. Thrill-seekers and chronically - sleep-deprived psychotic hacker types can say Y now, everyone else - should probably wait a while. - -config M68KFPU_EMU_EXTRAPREC - bool "Math emulation extra precision" - depends on M68KFPU_EMU - help - The fpu uses normally a few bit more during calculations for - correct rounding, the emulator can (often) do the same but this - extra calculation can cost quite some time, so you can disable - it here. The emulator will then "only" calculate with a 64 bit - mantissa and round slightly incorrect, what is more than enough - for normal usage. - -config M68KFPU_EMU_ONLY - bool "Math emulation only kernel" - depends on M68KFPU_EMU - help - This option prevents any floating-point instructions from being - compiled into the kernel, thereby the kernel doesn't save any - floating point context anymore during task switches, so this - kernel will only be usable on machines without a floating-point - math coprocessor. This makes the kernel a bit faster as no tests - needs to be executed whether a floating-point instruction in the - kernel should be executed or not. - -config ADVANCED - bool "Advanced configuration options" - ---help--- - This gives you access to some advanced options for the CPU. The - defaults should be fine for most users, but these options may make - it possible for you to improve performance somewhat if you know what - you are doing. - - Note that the answer to this question won't directly affect the - kernel: saying N will just cause the configurator to skip all - the questions about these options. + Select if you want MMU-based virtualised addressing space + support by paged memory management. If unsure, say 'Y'. - Most users should say N to this question. - -config RMW_INSNS - bool "Use read-modify-write instructions" - depends on ADVANCED - ---help--- - This allows to use certain instructions that work with indivisible - read-modify-write bus cycles. While this is faster than the - workaround of disabling interrupts, it can conflict with DMA - ( = direct memory access) on many Amiga systems, and it is also said - to destabilize other machines. It is very likely that this will - cause serious problems on any Amiga or Atari Medusa if set. The only - configuration where it should work are 68030-based Ataris, where it - apparently improves performance. But you've been warned! Unless you - really know what you are doing, say N. Try Y only if you're quite - adventurous. - -config SINGLE_MEMORY_CHUNK - bool "Use one physical chunk of memory only" if ADVANCED && !SUN3 - default y if SUN3 - select NEED_MULTIPLE_NODES - help - Ignore all but the first contiguous chunk of physical memory for VM - purposes. This will save a few bytes kernel size and may speed up - some operations. Say N if not sure. +menu "Platform dependent setup" -config 060_WRITETHROUGH - bool "Use write-through caching for 68060 supervisor accesses" - depends on ADVANCED && M68060 - ---help--- - The 68060 generally uses copyback caching of recently accessed data. - Copyback caching means that memory writes will be held in an on-chip - cache and only written back to memory some time later. Saying Y - here will force supervisor (kernel) accesses to use writethrough - caching. Writethrough caching means that data is written to memory - straight away, so that cache and memory data always agree. - Writethrough caching is less efficient, but is needed for some - drivers on 68060 based systems where the 68060 bus snooping signal - is hardwired on. The 53c710 SCSI driver is known to suffer from - this problem. - -config ARCH_DISCONTIGMEM_ENABLE - def_bool !SINGLE_MEMORY_CHUNK - -config NODES_SHIFT - int - default "3" - depends on !SINGLE_MEMORY_CHUNK +if MMU +source arch/m68k/Kconfig.mmu +endif +if !MMU +source arch/m68k/Kconfig.nommu +endif source "mm/Kconfig" endmenu -menu "General setup" +menu "Executable file formats" source "fs/Kconfig.binfmt" -config ZORRO - bool "Amiga Zorro (AutoConfig) bus support" - depends on AMIGA - help - This enables support for the Zorro bus in the Amiga. If you have - expansion cards in your Amiga that conform to the Amiga - AutoConfig(tm) specification, say Y, otherwise N. Note that even - expansion cards that do not fit in the Zorro slots but fit in e.g. - the CPU slot may fall in this category, so you have to say Y to let - Linux use these. - -config AMIGA_PCMCIA - bool "Amiga 1200/600 PCMCIA support (EXPERIMENTAL)" - depends on AMIGA && EXPERIMENTAL - help - Include support in the kernel for pcmcia on Amiga 1200 and Amiga - 600. If you intend to use pcmcia cards say Y; otherwise say N. - -config STRAM_PROC - bool "ST-RAM statistics in /proc" - depends on ATARI - help - Say Y here to report ST-RAM usage statistics in /proc/stram. - -config HEARTBEAT - bool "Use power LED as a heartbeat" if AMIGA || APOLLO || ATARI || MAC ||Q40 - default y if !AMIGA && !APOLLO && !ATARI && !MAC && !Q40 && HP300 - help - Use the power-on LED on your machine as a load meter. The exact - behavior is platform-dependent, but normally the flash frequency is - a hyperbolic function of the 5-minute load average. - -# We have a dedicated heartbeat LED. :-) -config PROC_HARDWARE - bool "/proc/hardware support" - help - Say Y here to support the /proc/hardware file, which gives you - access to information about the machine you're running on, - including the model, CPU, MMU, clock speed, BogoMIPS rating, - and memory size. - -config ISA - bool - depends on Q40 || AMIGA_PCMCIA - default y - help - Find out whether you have ISA slots on your motherboard. ISA is the - name of a bus system, i.e. the way the CPU talks to the other stuff - inside your box. Other bus systems are PCI, EISA, MicroChannel - (MCA) or VESA. ISA is an older system, now being displaced by PCI; - newer boards don't support it. If you have ISA, say Y, otherwise N. - -config GENERIC_ISA_DMA - bool - depends on Q40 || AMIGA_PCMCIA - default y - -config ZONE_DMA - bool - default y +endmenu -source "drivers/pci/Kconfig" +if !MMU +menu "Power management options" -source "drivers/zorro/Kconfig" +config PM + bool "Power Management support" + help + Support processor power management modes endmenu +endif source "net/Kconfig" source "drivers/Kconfig" +if MMU + menu "Character devices" config ATARI_MFPSER @@ -627,6 +234,8 @@ config SERIAL_CONSOLE endmenu +endif + source "fs/Kconfig" source "arch/m68k/Kconfig.debug" diff --git a/arch/m68k/Kconfig.debug b/arch/m68k/Kconfig.debug index f53b6d5300e..2bdb1b01115 100644 --- a/arch/m68k/Kconfig.debug +++ b/arch/m68k/Kconfig.debug @@ -2,4 +2,38 @@ menu "Kernel hacking" source "lib/Kconfig.debug" +if !MMU + +config FULLDEBUG + bool "Full Symbolic/Source Debugging support" + help + Enable debugging symbols on kernel build. + +config HIGHPROFILE + bool "Use fast second timer for profiling" + depends on COLDFIRE + help + Use a fast secondary clock to produce profiling information. + +config BOOTPARAM + bool 'Compiled-in Kernel Boot Parameter' + +config BOOTPARAM_STRING + string 'Kernel Boot Parameter' + default 'console=ttyS0,19200' + depends on BOOTPARAM + +config NO_KERNEL_MSG + bool "Suppress Kernel BUG Messages" + help + Do not output any debug BUG messages within the kernel. + +config BDM_DISABLE + bool "Disable BDM signals" + depends on (EXPERIMENTAL && COLDFIRE) + help + Disable the ColdFire CPU's BDM signals. + +endif + endmenu diff --git a/arch/m68k/Kconfig.mmu b/arch/m68k/Kconfig.mmu new file mode 100644 index 00000000000..16539b1d5d3 --- /dev/null +++ b/arch/m68k/Kconfig.mmu @@ -0,0 +1,417 @@ +config GENERIC_IOMAP + bool + default y + +config ARCH_MAY_HAVE_PC_FDC + bool + depends on BROKEN && (Q40 || SUN3X) + default y + +config ARCH_USES_GETTIMEOFFSET + def_bool y + +config EISA + bool + ---help--- + The Extended Industry Standard Architecture (EISA) bus was + developed as an open alternative to the IBM MicroChannel bus. + + The EISA bus provided some of the features of the IBM MicroChannel + bus while maintaining backward compatibility with cards made for + the older ISA bus. The EISA bus saw limited use between 1988 and + 1995 when it was made obsolete by the PCI bus. + + Say Y here if you are building a kernel for an EISA-based machine. + + Otherwise, say N. + +config MCA + bool + help + MicroChannel Architecture is found in some IBM PS/2 machines and + laptops. It is a bus system similar to PCI or ISA. See + <file:Documentation/mca.txt> (and especially the web page given + there) before attempting to build an MCA bus kernel. + +config PCMCIA + tristate + ---help--- + Say Y here if you want to attach PCMCIA- or PC-cards to your Linux + computer. These are credit-card size devices such as network cards, + modems or hard drives often used with laptops computers. There are + actually two varieties of these cards: the older 16 bit PCMCIA cards + and the newer 32 bit CardBus cards. If you want to use CardBus + cards, you need to say Y here and also to "CardBus support" below. + + To use your PC-cards, you will need supporting software from David + Hinds' pcmcia-cs package (see the file <file:Documentation/Changes> + for location). Please also read the PCMCIA-HOWTO, available from + <http://www.tldp.org/docs.html#howto>. + + To compile this driver as modules, choose M here: the + modules will be called pcmcia_core and ds. + +config AMIGA + bool "Amiga support" + select MMU_MOTOROLA if MMU + help + This option enables support for the Amiga series of computers. If + you plan to use this kernel on an Amiga, say Y here and browse the + material available in <file:Documentation/m68k>; otherwise say N. + +config ATARI + bool "Atari support" + select MMU_MOTOROLA if MMU + help + This option enables support for the 68000-based Atari series of + computers (including the TT, Falcon and Medusa). If you plan to use + this kernel on an Atari, say Y here and browse the material + available in <file:Documentation/m68k>; otherwise say N. + +config MAC + bool "Macintosh support" + select MMU_MOTOROLA if MMU + help + This option enables support for the Apple Macintosh series of + computers (yes, there is experimental support now, at least for part + of the series). + + Say N unless you're willing to code the remaining necessary support. + ;) + +config NUBUS + bool + depends on MAC + default y + +config M68K_L2_CACHE + bool + depends on MAC + default y + +config APOLLO + bool "Apollo support" + select MMU_MOTOROLA if MMU + help + Say Y here if you want to run Linux on an MC680x0-based Apollo + Domain workstation such as the DN3500. + +config VME + bool "VME (Motorola and BVM) support" + select MMU_MOTOROLA if MMU + help + Say Y here if you want to build a kernel for a 680x0 based VME + board. Boards currently supported include Motorola boards MVME147, + MVME162, MVME166, MVME167, MVME172, and MVME177. BVME4000 and + BVME6000 boards from BVM Ltd are also supported. + +config MVME147 + bool "MVME147 support" + depends on VME + help + Say Y to include support for early Motorola VME boards. This will + build a kernel which can run on MVME147 single-board computers. If + you select this option you will have to select the appropriate + drivers for SCSI, Ethernet and serial ports later on. + +config MVME16x + bool "MVME162, 166 and 167 support" + depends on VME + help + Say Y to include support for Motorola VME boards. This will build a + kernel which can run on MVME162, MVME166, MVME167, MVME172, and + MVME177 boards. If you select this option you will have to select + the appropriate drivers for SCSI, Ethernet and serial ports later + on. + +config BVME6000 + bool "BVME4000 and BVME6000 support" + depends on VME + help + Say Y to include support for VME boards from BVM Ltd. This will + build a kernel which can run on BVME4000 and BVME6000 boards. If + you select this option you will have to select the appropriate + drivers for SCSI, Ethernet and serial ports later on. + +config HP300 + bool "HP9000/300 and HP9000/400 support" + select MMU_MOTOROLA if MMU + help + This option enables support for the HP9000/300 and HP9000/400 series + of workstations. Support for these machines is still somewhat + experimental. If you plan to try to use the kernel on such a machine + say Y here. + Everybody else says N. + +config DIO + bool "DIO bus support" + depends on HP300 + default y + help + Say Y here to enable support for the "DIO" expansion bus used in + HP300 machines. If you are using such a system you almost certainly + want this. + +config SUN3X + bool "Sun3x support" + select MMU_MOTOROLA if MMU + select M68030 + help + This option enables support for the Sun 3x series of workstations. + Be warned that this support is very experimental. + Note that Sun 3x kernels are not compatible with Sun 3 hardware. + General Linux information on the Sun 3x series (now discontinued) + is at <http://www.angelfire.com/ca2/tech68k/sun3.html>. + + If you don't want to compile a kernel for a Sun 3x, say N. + +config Q40 + bool "Q40/Q60 support" + select MMU_MOTOROLA if MMU + help + The Q40 is a Motorola 68040-based successor to the Sinclair QL + manufactured in Germany. There is an official Q40 home page at + <http://www.q40.de/>. This option enables support for the Q40 and + Q60. Select your CPU below. For 68LC060 don't forget to enable FPU + emulation. + +config SUN3 + bool "Sun3 support" + depends on !MMU_MOTOROLA + select MMU_SUN3 if MMU + select M68020 + help + This option enables support for the Sun 3 series of workstations + (3/50, 3/60, 3/1xx, 3/2xx systems). Enabling this option requires + that all other hardware types must be disabled, as Sun 3 kernels + are incompatible with all other m68k targets (including Sun 3x!). + + If you don't want to compile a kernel exclusively for a Sun 3, say N. + +config NATFEAT + bool "ARAnyM emulator support" + depends on ATARI + help + This option enables support for ARAnyM native features, such as + access to a disk image as /dev/hda. + +config NFBLOCK + tristate "NatFeat block device support" + depends on BLOCK && NATFEAT + help + Say Y to include support for the ARAnyM NatFeat block device + which allows direct access to the hard drives without using + the hardware emulation. + +config NFCON + tristate "NatFeat console driver" + depends on NATFEAT + help + Say Y to include support for the ARAnyM NatFeat console driver + which allows the console output to be redirected to the stderr + output of ARAnyM. + +config NFETH + tristate "NatFeat Ethernet support" + depends on NET_ETHERNET && NATFEAT + help + Say Y to include support for the ARAnyM NatFeat network device + which will emulate a regular ethernet device while presenting an + ethertap device to the host system. + +comment "Processor type" + +config M68020 + bool "68020 support" + help + If you anticipate running this kernel on a computer with a MC68020 + processor, say Y. Otherwise, say N. Note that the 68020 requires a + 68851 MMU (Memory Management Unit) to run Linux/m68k, except on the + Sun 3, which provides its own version. + +config M68030 + bool "68030 support" + depends on !MMU_SUN3 + help + If you anticipate running this kernel on a computer with a MC68030 + processor, say Y. Otherwise, say N. Note that a MC68EC030 will not + work, as it does not include an MMU (Memory Management Unit). + +config M68040 + bool "68040 support" + depends on !MMU_SUN3 + help + If you anticipate running this kernel on a computer with a MC68LC040 + or MC68040 processor, say Y. Otherwise, say N. Note that an + MC68EC040 will not work, as it does not include an MMU (Memory + Management Unit). + +config M68060 + bool "68060 support" + depends on !MMU_SUN3 + help + If you anticipate running this kernel on a computer with a MC68060 + processor, say Y. Otherwise, say N. + +config MMU_MOTOROLA + bool + +config MMU_SUN3 + bool + depends on MMU && !MMU_MOTOROLA + +config M68KFPU_EMU + bool "Math emulation support (EXPERIMENTAL)" + depends on EXPERIMENTAL + help + At some point in the future, this will cause floating-point math + instructions to be emulated by the kernel on machines that lack a + floating-point math coprocessor. Thrill-seekers and chronically + sleep-deprived psychotic hacker types can say Y now, everyone else + should probably wait a while. + +config M68KFPU_EMU_EXTRAPREC + bool "Math emulation extra precision" + depends on M68KFPU_EMU + help + The fpu uses normally a few bit more during calculations for + correct rounding, the emulator can (often) do the same but this + extra calculation can cost quite some time, so you can disable + it here. The emulator will then "only" calculate with a 64 bit + mantissa and round slightly incorrect, what is more than enough + for normal usage. + +config M68KFPU_EMU_ONLY + bool "Math emulation only kernel" + depends on M68KFPU_EMU + help + This option prevents any floating-point instructions from being + compiled into the kernel, thereby the kernel doesn't save any + floating point context anymore during task switches, so this + kernel will only be usable on machines without a floating-point + math coprocessor. This makes the kernel a bit faster as no tests + needs to be executed whether a floating-point instruction in the + kernel should be executed or not. + +config ADVANCED + bool "Advanced configuration options" + ---help--- + This gives you access to some advanced options for the CPU. The + defaults should be fine for most users, but these options may make + it possible for you to improve performance somewhat if you know what + you are doing. + + Note that the answer to this question won't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about these options. + + Most users should say N to this question. + +config RMW_INSNS + bool "Use read-modify-write instructions" + depends on ADVANCED + ---help--- + This allows to use certain instructions that work with indivisible + read-modify-write bus cycles. While this is faster than the + workaround of disabling interrupts, it can conflict with DMA + ( = direct memory access) on many Amiga systems, and it is also said + to destabilize other machines. It is very likely that this will + cause serious problems on any Amiga or Atari Medusa if set. The only + configuration where it should work are 68030-based Ataris, where it + apparently improves performance. But you've been warned! Unless you + really know what you are doing, say N. Try Y only if you're quite + adventurous. + +config SINGLE_MEMORY_CHUNK + bool "Use one physical chunk of memory only" if ADVANCED && !SUN3 + default y if SUN3 + select NEED_MULTIPLE_NODES + help + Ignore all but the first contiguous chunk of physical memory for VM + purposes. This will save a few bytes kernel size and may speed up + some operations. Say N if not sure. + +config 060_WRITETHROUGH + bool "Use write-through caching for 68060 supervisor accesses" + depends on ADVANCED && M68060 + ---help--- + The 68060 generally uses copyback caching of recently accessed data. + Copyback caching means that memory writes will be held in an on-chip + cache and only written back to memory some time later. Saying Y + here will force supervisor (kernel) accesses to use writethrough + caching. Writethrough caching means that data is written to memory + straight away, so that cache and memory data always agree. + Writethrough caching is less efficient, but is needed for some + drivers on 68060 based systems where the 68060 bus snooping signal + is hardwired on. The 53c710 SCSI driver is known to suffer from + this problem. + +config ARCH_DISCONTIGMEM_ENABLE + def_bool !SINGLE_MEMORY_CHUNK + +config NODES_SHIFT + int + default "3" + depends on !SINGLE_MEMORY_CHUNK + +config ZORRO + bool "Amiga Zorro (AutoConfig) bus support" + depends on AMIGA + help + This enables support for the Zorro bus in the Amiga. If you have + expansion cards in your Amiga that conform to the Amiga + AutoConfig(tm) specification, say Y, otherwise N. Note that even + expansion cards that do not fit in the Zorro slots but fit in e.g. + the CPU slot may fall in this category, so you have to say Y to let + Linux use these. + +config AMIGA_PCMCIA + bool "Amiga 1200/600 PCMCIA support (EXPERIMENTAL)" + depends on AMIGA && EXPERIMENTAL + help + Include support in the kernel for pcmcia on Amiga 1200 and Amiga + 600. If you intend to use pcmcia cards say Y; otherwise say N. + +config STRAM_PROC + bool "ST-RAM statistics in /proc" + depends on ATARI + help + Say Y here to report ST-RAM usage statistics in /proc/stram. + +config HEARTBEAT + bool "Use power LED as a heartbeat" if AMIGA || APOLLO || ATARI || MAC ||Q40 + default y if !AMIGA && !APOLLO && !ATARI && !MAC && !Q40 && HP300 + help + Use the power-on LED on your machine as a load meter. The exact + behavior is platform-dependent, but normally the flash frequency is + a hyperbolic function of the 5-minute load average. + +# We have a dedicated heartbeat LED. :-) +config PROC_HARDWARE + bool "/proc/hardware support" + help + Say Y here to support the /proc/hardware file, which gives you + access to information about the machine you're running on, + including the model, CPU, MMU, clock speed, BogoMIPS rating, + and memory size. + +config ISA + bool + depends on Q40 || AMIGA_PCMCIA + default y + help + Find out whether you have ISA slots on your motherboard. ISA is the + name of a bus system, i.e. the way the CPU talks to the other stuff + inside your box. Other bus systems are PCI, EISA, MicroChannel + (MCA) or VESA. ISA is an older system, now being displaced by PCI; + newer boards don't support it. If you have ISA, say Y, otherwise N. + +config GENERIC_ISA_DMA + bool + depends on Q40 || AMIGA_PCMCIA + default y + +source "drivers/pci/Kconfig" + +source "drivers/zorro/Kconfig" + diff --git a/arch/m68knommu/Kconfig b/arch/m68k/Kconfig.nommu index b5424cf948e..273bccab951 100644 --- a/arch/m68knommu/Kconfig +++ b/arch/m68k/Kconfig.nommu @@ -1,43 +1,7 @@ -config M68K - bool - default y - select HAVE_IDE - select HAVE_GENERIC_HARDIRQS - select GENERIC_HARDIRQS_NO_DEPRECATED - -config MMU - bool - default n - -config NO_DMA - bool - depends on !COLDFIRE - default y - config FPU bool default n -config ZONE_DMA - bool - default y - -config RWSEM_GENERIC_SPINLOCK - bool - default y - -config RWSEM_XCHGADD_ALGORITHM - bool - default n - -config ARCH_HAS_ILOG2_U32 - bool - default n - -config ARCH_HAS_ILOG2_U64 - bool - default n - config GENERIC_FIND_NEXT_BIT bool default y @@ -46,29 +10,14 @@ config GENERIC_GPIO bool default n -config GENERIC_HWEIGHT - bool - default y - -config GENERIC_CALIBRATE_DELAY - bool - default y - config GENERIC_CMOS_UPDATE bool default y -config TIME_LOW_RES - bool - default y - config GENERIC_CLOCKEVENTS bool default n -config NO_IOPORT - def_bool y - config COLDFIRE_SW_A7 bool default n @@ -85,12 +34,6 @@ config HAVE_MBAR config HAVE_IPSBAR bool -source "init/Kconfig" - -source "kernel/Kconfig.freezer" - -menu "Processor type and features" - choice prompt "CPU" default M68EZ328 @@ -630,11 +573,6 @@ config 4KSTACKS running more threads on a system and also reduces the pressure on the VM subsystem for higher order allocations. -config HZ - int - default 1000 if CLEOPATRA - default 100 - comment "RAM configuration" config RAMBASE @@ -803,10 +741,6 @@ endif source "kernel/time/Kconfig" -source "mm/Kconfig" - -endmenu - config ISA_DMA_API bool depends on !M5272 @@ -814,31 +748,3 @@ config ISA_DMA_API source "drivers/pcmcia/Kconfig" -menu "Executable file formats" - -source "fs/Kconfig.binfmt" - -endmenu - -menu "Power management options" - -config PM - bool "Power Management support" - help - Support processor power management modes - -endmenu - -source "net/Kconfig" - -source "drivers/Kconfig" - -source "fs/Kconfig" - -source "arch/m68knommu/Kconfig.debug" - -source "security/Kconfig" - -source "crypto/Kconfig" - -source "lib/Kconfig" diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile index b793163abc6..be46cadd401 100644 --- a/arch/m68k/Makefile +++ b/arch/m68k/Makefile @@ -1,123 +1,7 @@ -# -# m68k/Makefile -# -# This file is included by the global makefile so that you can add your own -# architecture-specific flags and dependencies. Remember to do have actions -# for "archclean" and "archdep" for cleaning up and making dependencies for -# this architecture -# -# This file is subject to the terms and conditions of the GNU General Public -# License. See the file "COPYING" in the main directory of this archive -# for more details. -# -# Copyright (C) 1994 by Hamish Macdonald -# - KBUILD_DEFCONFIG := multi_defconfig -# override top level makefile -AS += -m68020 -LDFLAGS := -m m68kelf -KBUILD_LDFLAGS_MODULE += -T $(srctree)/arch/m68k/kernel/module.lds -ifneq ($(SUBARCH),$(ARCH)) - ifeq ($(CROSS_COMPILE),) - CROSS_COMPILE := $(call cc-cross-prefix, \ - m68k-linux-gnu- m68k-linux- m68k-unknown-linux-gnu-) - endif -endif - -ifdef CONFIG_SUN3 -LDFLAGS_vmlinux = -N -endif - -CHECKFLAGS += -D__mc68000__ - -# without -fno-strength-reduce the 53c7xx.c driver fails ;-( -KBUILD_CFLAGS += -pipe -fno-strength-reduce -ffixed-a2 - -# enable processor switch if compiled only for a single cpu -ifndef CONFIG_M68020 -ifndef CONFIG_M68030 - -ifndef CONFIG_M68060 -KBUILD_CFLAGS += -m68040 -endif - -ifndef CONFIG_M68040 -KBUILD_CFLAGS += -m68060 -endif - -endif -endif - -ifdef CONFIG_KGDB -# If configured for kgdb support, include debugging infos and keep the -# frame pointer -KBUILD_CFLAGS := $(subst -fomit-frame-pointer,,$(KBUILD_CFLAGS)) -g -endif - -ifndef CONFIG_SUN3 -head-y := arch/m68k/kernel/head.o +ifdef CONFIG_MMU +include $(srctree)/arch/m68k/Makefile_mm else -head-y := arch/m68k/kernel/sun3-head.o +include $(srctree)/arch/m68k/Makefile_no endif - -core-y += arch/m68k/kernel/ arch/m68k/mm/ -libs-y += arch/m68k/lib/ - -core-$(CONFIG_Q40) += arch/m68k/q40/ -core-$(CONFIG_AMIGA) += arch/m68k/amiga/ -core-$(CONFIG_ATARI) += arch/m68k/atari/ -core-$(CONFIG_MAC) += arch/m68k/mac/ -core-$(CONFIG_HP300) += arch/m68k/hp300/ -core-$(CONFIG_APOLLO) += arch/m68k/apollo/ -core-$(CONFIG_MVME147) += arch/m68k/mvme147/ -core-$(CONFIG_MVME16x) += arch/m68k/mvme16x/ -core-$(CONFIG_BVME6000) += arch/m68k/bvme6000/ -core-$(CONFIG_SUN3X) += arch/m68k/sun3x/ arch/m68k/sun3/ -core-$(CONFIG_SUN3) += arch/m68k/sun3/ arch/m68k/sun3/prom/ -core-$(CONFIG_NATFEAT) += arch/m68k/emu/ -core-$(CONFIG_M68040) += arch/m68k/fpsp040/ -core-$(CONFIG_M68060) += arch/m68k/ifpsp060/ -core-$(CONFIG_M68KFPU_EMU) += arch/m68k/math-emu/ - -all: zImage - -lilo: vmlinux - if [ -f $(INSTALL_PATH)/vmlinux ]; then mv -f $(INSTALL_PATH)/vmlinux $(INSTALL_PATH)/vmlinux.old; fi - if [ -f $(INSTALL_PATH)/System.map ]; then mv -f $(INSTALL_PATH)/System.map $(INSTALL_PATH)/System.old; fi - cat vmlinux > $(INSTALL_PATH)/vmlinux - cp System.map $(INSTALL_PATH)/System.map - if [ -x /sbin/lilo ]; then /sbin/lilo; else /etc/lilo/install; fi - -zImage compressed: vmlinux.gz - -vmlinux.gz: vmlinux - -ifndef CONFIG_KGDB - cp vmlinux vmlinux.tmp - $(STRIP) vmlinux.tmp - gzip -9c vmlinux.tmp >vmlinux.gz - rm vmlinux.tmp -else - gzip -9c vmlinux >vmlinux.gz -endif - -bzImage: vmlinux.bz2 - -vmlinux.bz2: vmlinux - -ifndef CONFIG_KGDB - cp vmlinux vmlinux.tmp - $(STRIP) vmlinux.tmp - bzip2 -1c vmlinux.tmp >vmlinux.bz2 - rm vmlinux.tmp -else - bzip2 -1c vmlinux >vmlinux.bz2 -endif - -archclean: - rm -f vmlinux.gz vmlinux.bz2 - -install: - sh $(srctree)/arch/m68k/install.sh $(KERNELRELEASE) vmlinux.gz System.map "$(INSTALL_PATH)" diff --git a/arch/m68k/Makefile_mm b/arch/m68k/Makefile_mm new file mode 100644 index 00000000000..d449b6d5aec --- /dev/null +++ b/arch/m68k/Makefile_mm @@ -0,0 +1,121 @@ +# +# m68k/Makefile +# +# This file is included by the global makefile so that you can add your own +# architecture-specific flags and dependencies. Remember to do have actions +# for "archclean" and "archdep" for cleaning up and making dependencies for +# this architecture +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +# Copyright (C) 1994 by Hamish Macdonald +# + +# override top level makefile +AS += -m68020 +LDFLAGS := -m m68kelf +KBUILD_LDFLAGS_MODULE += -T $(srctree)/arch/m68k/kernel/module.lds +ifneq ($(SUBARCH),$(ARCH)) + ifeq ($(CROSS_COMPILE),) + CROSS_COMPILE := $(call cc-cross-prefix, \ + m68k-linux-gnu- m68k-linux- m68k-unknown-linux-gnu-) + endif +endif + +ifdef CONFIG_SUN3 +LDFLAGS_vmlinux = -N +endif + +CHECKFLAGS += -D__mc68000__ + +# without -fno-strength-reduce the 53c7xx.c driver fails ;-( +KBUILD_CFLAGS += -pipe -fno-strength-reduce -ffixed-a2 + +# enable processor switch if compiled only for a single cpu +ifndef CONFIG_M68020 +ifndef CONFIG_M68030 + +ifndef CONFIG_M68060 +KBUILD_CFLAGS += -m68040 +endif + +ifndef CONFIG_M68040 +KBUILD_CFLAGS += -m68060 +endif + +endif +endif + +ifdef CONFIG_KGDB +# If configured for kgdb support, include debugging infos and keep the +# frame pointer +KBUILD_CFLAGS := $(subst -fomit-frame-pointer,,$(KBUILD_CFLAGS)) -g +endif + +ifndef CONFIG_SUN3 +head-y := arch/m68k/kernel/head.o +else +head-y := arch/m68k/kernel/sun3-head.o +endif + +core-y += arch/m68k/kernel/ arch/m68k/mm/ +libs-y += arch/m68k/lib/ + +core-$(CONFIG_Q40) += arch/m68k/q40/ +core-$(CONFIG_AMIGA) += arch/m68k/amiga/ +core-$(CONFIG_ATARI) += arch/m68k/atari/ +core-$(CONFIG_MAC) += arch/m68k/mac/ +core-$(CONFIG_HP300) += arch/m68k/hp300/ +core-$(CONFIG_APOLLO) += arch/m68k/apollo/ +core-$(CONFIG_MVME147) += arch/m68k/mvme147/ +core-$(CONFIG_MVME16x) += arch/m68k/mvme16x/ +core-$(CONFIG_BVME6000) += arch/m68k/bvme6000/ +core-$(CONFIG_SUN3X) += arch/m68k/sun3x/ arch/m68k/sun3/ +core-$(CONFIG_SUN3) += arch/m68k/sun3/ arch/m68k/sun3/prom/ +core-$(CONFIG_NATFEAT) += arch/m68k/emu/ +core-$(CONFIG_M68040) += arch/m68k/fpsp040/ +core-$(CONFIG_M68060) += arch/m68k/ifpsp060/ +core-$(CONFIG_M68KFPU_EMU) += arch/m68k/math-emu/ + +all: zImage + +lilo: vmlinux + if [ -f $(INSTALL_PATH)/vmlinux ]; then mv -f $(INSTALL_PATH)/vmlinux $(INSTALL_PATH)/vmlinux.old; fi + if [ -f $(INSTALL_PATH)/System.map ]; then mv -f $(INSTALL_PATH)/System.map $(INSTALL_PATH)/System.old; fi + cat vmlinux > $(INSTALL_PATH)/vmlinux + cp System.map $(INSTALL_PATH)/System.map + if [ -x /sbin/lilo ]; then /sbin/lilo; else /etc/lilo/install; fi + +zImage compressed: vmlinux.gz + +vmlinux.gz: vmlinux + +ifndef CONFIG_KGDB + cp vmlinux vmlinux.tmp + $(STRIP) vmlinux.tmp + gzip -9c vmlinux.tmp >vmlinux.gz + rm vmlinux.tmp +else + gzip -9c vmlinux >vmlinux.gz +endif + +bzImage: vmlinux.bz2 + +vmlinux.bz2: vmlinux + +ifndef CONFIG_KGDB + cp vmlinux vmlinux.tmp + $(STRIP) vmlinux.tmp + bzip2 -1c vmlinux.tmp >vmlinux.bz2 + rm vmlinux.tmp +else + bzip2 -1c vmlinux >vmlinux.bz2 +endif + +archclean: + rm -f vmlinux.gz vmlinux.bz2 + +install: + sh $(srctree)/arch/m68k/install.sh $(KERNELRELEASE) vmlinux.gz System.map "$(INSTALL_PATH)" diff --git a/arch/m68knommu/Makefile b/arch/m68k/Makefile_no index 589613fed31..81652ab893e 100644 --- a/arch/m68knommu/Makefile +++ b/arch/m68k/Makefile_no @@ -1,5 +1,5 @@ # -# arch/m68knommu/Makefile +# arch/m68k/Makefile # # This file is subject to the terms and conditions of the GNU General Public # License. See the file "COPYING" in the main directory of this archive @@ -8,8 +8,6 @@ # (C) Copyright 2002, Greg Ungerer <gerg@snapgear.com> # -KBUILD_DEFCONFIG := m5208evb_defconfig - platform-$(CONFIG_M68328) := 68328 platform-$(CONFIG_M68EZ328) := 68EZ328 platform-$(CONFIG_M68VZ328) := 68VZ328 @@ -82,7 +80,7 @@ cpuclass-$(CONFIG_M68360) := 68360 CPUCLASS := $(cpuclass-y) ifneq ($(CPUCLASS),$(PLATFORM)) -CLASSDIR := arch/m68knommu/platform/$(cpuclass-y)/ +CLASSDIR := arch/m68k/platform/$(cpuclass-y)/ endif export PLATFORM BOARD MODEL CPUCLASS @@ -114,13 +112,13 @@ KBUILD_CFLAGS += $(cflags-y) KBUILD_CFLAGS += -D__linux__ KBUILD_CFLAGS += -DUTS_SYSNAME=\"uClinux\" -head-y := arch/m68knommu/platform/$(cpuclass-y)/head.o +head-y := arch/m68k/platform/$(cpuclass-y)/head.o -core-y += arch/m68knommu/kernel/ \ - arch/m68knommu/mm/ \ +core-y += arch/m68k/kernel/ \ + arch/m68k/mm/ \ $(CLASSDIR) \ - arch/m68knommu/platform/$(PLATFORM)/ -libs-y += arch/m68knommu/lib/ + arch/m68k/platform/$(PLATFORM)/ +libs-y += arch/m68k/lib/ archclean: diff --git a/arch/m68k/atari/atakeyb.c b/arch/m68k/atari/atakeyb.c index 5890897d28b..b995513d527 100644 --- a/arch/m68k/atari/atakeyb.c +++ b/arch/m68k/atari/atakeyb.c @@ -130,7 +130,7 @@ KEYBOARD_STATE kb_state; * it's really hard to decide whether they're mouse or keyboard bytes. Since * overruns usually occur when moving the Atari mouse rapidly, they're seen as * mouse bytes here. If this is wrong, only a make code of the keyboard gets - * lost, which isn't too bad. Loosing a break code would be disastrous, + * lost, which isn't too bad. Losing a break code would be disastrous, * because then the keyboard repeat strikes... */ diff --git a/arch/m68knommu/configs/m5208evb_defconfig b/arch/m68k/configs/m5208evb_defconfig index 2f5655c577a..c1616824e20 100644 --- a/arch/m68knommu/configs/m5208evb_defconfig +++ b/arch/m68k/configs/m5208evb_defconfig @@ -1,3 +1,4 @@ +# CONFIG_MMU is not set CONFIG_EXPERIMENTAL=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -37,6 +38,7 @@ CONFIG_INET=y # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set +# CONFIG_FW_LOADER is not set CONFIG_MTD=y CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CHAR=y diff --git a/arch/m68knommu/configs/m5249evb_defconfig b/arch/m68k/configs/m5249evb_defconfig index 16df72bfbd4..a6599e42fac 100644 --- a/arch/m68knommu/configs/m5249evb_defconfig +++ b/arch/m68k/configs/m5249evb_defconfig @@ -1,3 +1,4 @@ +# CONFIG_MMU is not set CONFIG_EXPERIMENTAL=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -35,6 +36,7 @@ CONFIG_INET=y # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set +# CONFIG_FW_LOADER is not set CONFIG_MTD=y CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CHAR=y diff --git a/arch/m68knommu/configs/m5272c3_defconfig b/arch/m68k/configs/m5272c3_defconfig index 4e6ea50c7f3..3fa60a57a0f 100644 --- a/arch/m68knommu/configs/m5272c3_defconfig +++ b/arch/m68k/configs/m5272c3_defconfig @@ -1,3 +1,4 @@ +# CONFIG_MMU is not set CONFIG_EXPERIMENTAL=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -33,6 +34,7 @@ CONFIG_INET=y # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set +# CONFIG_FW_LOADER is not set CONFIG_MTD=y CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CHAR=y diff --git a/arch/m68knommu/configs/m5275evb_defconfig b/arch/m68k/configs/m5275evb_defconfig index f3dd74115a3..33c32aeca12 100644 --- a/arch/m68knommu/configs/m5275evb_defconfig +++ b/arch/m68k/configs/m5275evb_defconfig @@ -1,3 +1,4 @@ +# CONFIG_MMU is not set CONFIG_EXPERIMENTAL=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -36,6 +37,7 @@ CONFIG_INET=y # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set +# CONFIG_FW_LOADER is not set CONFIG_MTD=y CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CHAR=y diff --git a/arch/m68knommu/configs/m5307c3_defconfig b/arch/m68k/configs/m5307c3_defconfig index bce0a20c373..43795f41f7c 100644 --- a/arch/m68knommu/configs/m5307c3_defconfig +++ b/arch/m68k/configs/m5307c3_defconfig @@ -1,3 +1,4 @@ +# CONFIG_MMU is not set CONFIG_EXPERIMENTAL=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -35,6 +36,7 @@ CONFIG_INET=y # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set +# CONFIG_FW_LOADER is not set CONFIG_MTD=y CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CHAR=y diff --git a/arch/m68knommu/configs/m5407c3_defconfig b/arch/m68k/configs/m5407c3_defconfig index 618cc32691f..72746c57a57 100644 --- a/arch/m68knommu/configs/m5407c3_defconfig +++ b/arch/m68k/configs/m5407c3_defconfig @@ -1,3 +1,4 @@ +# CONFIG_MMU is not set CONFIG_EXPERIMENTAL=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -35,6 +36,7 @@ CONFIG_INET=y # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set +# CONFIG_FW_LOADER is not set CONFIG_MTD=y CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CHAR=y diff --git a/arch/m68k/fpsp040/bindec.S b/arch/m68k/fpsp040/bindec.S index 72f1159cb80..f2e79523104 100644 --- a/arch/m68k/fpsp040/bindec.S +++ b/arch/m68k/fpsp040/bindec.S @@ -609,7 +609,7 @@ do_fint: | A6. This test occurs only on the first pass. If the | result is exactly 10^LEN, decrement ILOG and divide | the mantissa by 10. The calculation of 10^LEN cannot -| be inexact, since all powers of ten upto 10^27 are exact +| be inexact, since all powers of ten up to 10^27 are exact | in extended precision, so the use of a previous power-of-ten | table will introduce no error. | diff --git a/arch/m68k/ifpsp060/src/fpsp.S b/arch/m68k/ifpsp060/src/fpsp.S index 26e85e2b7a5..78cb60f5bb4 100644 --- a/arch/m68k/ifpsp060/src/fpsp.S +++ b/arch/m68k/ifpsp060/src/fpsp.S @@ -11813,7 +11813,7 @@ fmul_unfl_ena: bne.b fmul_unfl_ena_sd # no, sgl or dbl # if the rnd mode is anything but RZ, then we have to re-do the above -# multiplication becuase we used RZ for all. +# multiplication because we used RZ for all. fmov.l L_SCR3(%a6),%fpcr # set FPCR fmul_unfl_ena_cont: @@ -18095,7 +18095,7 @@ fscc_mem_op: rts -# addresing mode is post-increment. write the result byte. if the write +# addressing mode is post-increment. write the result byte. if the write # fails then don't update the address register. if write passes then # call inc_areg() to update the address register. fscc_mem_inc: @@ -20876,7 +20876,7 @@ dst_get_dupper: swap %d0 # d0 now in upper word lsl.l &0x4,%d0 # d0 in proper place for dbl prec exp tst.b FTEMP_EX(%a0) # test sign - bpl.b dst_get_dman # if postive, go process mantissa + bpl.b dst_get_dman # if positive, go process mantissa bset &0x1f,%d0 # if negative, set sign dst_get_dman: mov.l FTEMP_HI(%a0),%d1 # get ms mantissa @@ -22943,7 +22943,7 @@ tbl_ovfl_result: # FP_SRC(a6) = packed operand now as a binary FP number # # # # ALGORITHM *********************************************************** # -# Get the correct <ea> whihc is the value on the exception stack # +# Get the correct <ea> which is the value on the exception stack # # frame w/ maybe a correction factor if the <ea> is -(an) or (an)+. # # Then, fetch the operand from memory. If the fetch fails, exit # # through facc_in_x(). # @@ -24096,7 +24096,7 @@ do_fint12: # A6. This test occurs only on the first pass. If the # result is exactly 10^LEN, decrement ILOG and divide # the mantissa by 10. The calculation of 10^LEN cannot -# be inexact, since all powers of ten upto 10^27 are exact +# be inexact, since all powers of ten up to 10^27 are exact # in extended precision, so the use of a previous power-of-ten # table will introduce no error. # diff --git a/arch/m68k/ifpsp060/src/pfpsp.S b/arch/m68k/ifpsp060/src/pfpsp.S index e71ba0ab013..4aedef973cf 100644 --- a/arch/m68k/ifpsp060/src/pfpsp.S +++ b/arch/m68k/ifpsp060/src/pfpsp.S @@ -7777,7 +7777,7 @@ dst_get_dupper: swap %d0 # d0 now in upper word lsl.l &0x4,%d0 # d0 in proper place for dbl prec exp tst.b FTEMP_EX(%a0) # test sign - bpl.b dst_get_dman # if postive, go process mantissa + bpl.b dst_get_dman # if positive, go process mantissa bset &0x1f,%d0 # if negative, set sign dst_get_dman: mov.l FTEMP_HI(%a0),%d1 # get ms mantissa @@ -8244,7 +8244,7 @@ fmul_unfl_ena: bne.b fmul_unfl_ena_sd # no, sgl or dbl # if the rnd mode is anything but RZ, then we have to re-do the above -# multiplication becuase we used RZ for all. +# multiplication because we used RZ for all. fmov.l L_SCR3(%a6),%fpcr # set FPCR fmul_unfl_ena_cont: @@ -12903,7 +12903,7 @@ store_fpreg_7: # FP_SRC(a6) = packed operand now as a binary FP number # # # # ALGORITHM *********************************************************** # -# Get the correct <ea> whihc is the value on the exception stack # +# Get the correct <ea> which is the value on the exception stack # # frame w/ maybe a correction factor if the <ea> is -(an) or (an)+. # # Then, fetch the operand from memory. If the fetch fails, exit # # through facc_in_x(). # @@ -14056,7 +14056,7 @@ do_fint12: # A6. This test occurs only on the first pass. If the # result is exactly 10^LEN, decrement ILOG and divide # the mantissa by 10. The calculation of 10^LEN cannot -# be inexact, since all powers of ten upto 10^27 are exact +# be inexact, since all powers of ten up to 10^27 are exact # in extended precision, so the use of a previous power-of-ten # table will introduce no error. # diff --git a/arch/m68k/include/asm/atariints.h b/arch/m68k/include/asm/atariints.h index f597892e43a..656bbbf5a6f 100644 --- a/arch/m68k/include/asm/atariints.h +++ b/arch/m68k/include/asm/atariints.h @@ -146,7 +146,7 @@ static inline void clear_mfp_bit( unsigned irq, int type ) /* * {en,dis}able_irq have the usual semantics of temporary blocking the - * interrupt, but not loosing requests that happen between disabling and + * interrupt, but not losing requests that happen between disabling and * enabling. This is done with the MFP mask registers. */ diff --git a/arch/m68k/include/asm/bitops_mm.h b/arch/m68k/include/asm/bitops_mm.h index b4ecdaada52..9d69f6e6236 100644 --- a/arch/m68k/include/asm/bitops_mm.h +++ b/arch/m68k/include/asm/bitops_mm.h @@ -325,58 +325,45 @@ static inline int __fls(int x) #include <asm-generic/bitops/hweight.h> #include <asm-generic/bitops/lock.h> -/* Bitmap functions for the minix filesystem */ +/* Bitmap functions for the little endian bitmap. */ -static inline int minix_find_first_zero_bit(const void *vaddr, unsigned size) +static inline void __set_bit_le(int nr, void *addr) { - const unsigned short *p = vaddr, *addr = vaddr; - int res; - unsigned short num; - - if (!size) - return 0; - - size = (size >> 4) + ((size & 15) > 0); - while (*p++ == 0xffff) - { - if (--size == 0) - return (p - addr) << 4; - } + __set_bit(nr ^ 24, addr); +} - num = ~*--p; - __asm__ __volatile__ ("bfffo %1{#16,#16},%0" - : "=d" (res) : "d" (num & -num)); - return ((p - addr) << 4) + (res ^ 31); +static inline void __clear_bit_le(int nr, void *addr) +{ + __clear_bit(nr ^ 24, addr); } -#define minix_test_and_set_bit(nr, addr) __test_and_set_bit((nr) ^ 16, (unsigned long *)(addr)) -#define minix_set_bit(nr,addr) __set_bit((nr) ^ 16, (unsigned long *)(addr)) -#define minix_test_and_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 16, (unsigned long *)(addr)) +static inline int __test_and_set_bit_le(int nr, void *addr) +{ + return __test_and_set_bit(nr ^ 24, addr); +} -static inline int minix_test_bit(int nr, const void *vaddr) +static inline int test_and_set_bit_le(int nr, void *addr) { - const unsigned short *p = vaddr; - return (p[nr >> 4] & (1U << (nr & 15))) != 0; + return test_and_set_bit(nr ^ 24, addr); } -/* Bitmap functions for the ext2 filesystem. */ +static inline int __test_and_clear_bit_le(int nr, void *addr) +{ + return __test_and_clear_bit(nr ^ 24, addr); +} -#define ext2_set_bit(nr, addr) __test_and_set_bit((nr) ^ 24, (unsigned long *)(addr)) -#define ext2_set_bit_atomic(lock, nr, addr) test_and_set_bit((nr) ^ 24, (unsigned long *)(addr)) -#define ext2_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 24, (unsigned long *)(addr)) -#define ext2_clear_bit_atomic(lock, nr, addr) test_and_clear_bit((nr) ^ 24, (unsigned long *)(addr)) -#define ext2_find_next_zero_bit(addr, size, offset) \ - generic_find_next_zero_le_bit((unsigned long *)addr, size, offset) -#define ext2_find_next_bit(addr, size, offset) \ - generic_find_next_le_bit((unsigned long *)addr, size, offset) +static inline int test_and_clear_bit_le(int nr, void *addr) +{ + return test_and_clear_bit(nr ^ 24, addr); +} -static inline int ext2_test_bit(int nr, const void *vaddr) +static inline int test_bit_le(int nr, const void *vaddr) { const unsigned char *p = vaddr; return (p[nr >> 3] & (1U << (nr & 7))) != 0; } -static inline int ext2_find_first_zero_bit(const void *vaddr, unsigned size) +static inline int find_first_zero_bit_le(const void *vaddr, unsigned size) { const unsigned long *p = vaddr, *addr = vaddr; int res; @@ -393,33 +380,36 @@ static inline int ext2_find_first_zero_bit(const void *vaddr, unsigned size) --p; for (res = 0; res < 32; res++) - if (!ext2_test_bit (res, p)) + if (!test_bit_le(res, p)) break; return (p - addr) * 32 + res; } -static inline unsigned long generic_find_next_zero_le_bit(const unsigned long *addr, +static inline unsigned long find_next_zero_bit_le(const void *addr, unsigned long size, unsigned long offset) { - const unsigned long *p = addr + (offset >> 5); + const unsigned long *p = addr; int bit = offset & 31UL, res; if (offset >= size) return size; + p += offset >> 5; + if (bit) { + offset -= bit; /* Look for zero in first longword */ for (res = bit; res < 32; res++) - if (!ext2_test_bit (res, p)) - return (p - addr) * 32 + res; + if (!test_bit_le(res, p)) + return offset + res; p++; + offset += 32; } /* No zero yet, search remaining full bytes for a zero */ - res = ext2_find_first_zero_bit (p, size - 32 * (p - addr)); - return (p - addr) * 32 + res; + return offset + find_first_zero_bit_le(p, size - offset); } -static inline int ext2_find_first_bit(const void *vaddr, unsigned size) +static inline int find_first_bit_le(const void *vaddr, unsigned size) { const unsigned long *p = vaddr, *addr = vaddr; int res; @@ -435,32 +425,42 @@ static inline int ext2_find_first_bit(const void *vaddr, unsigned size) --p; for (res = 0; res < 32; res++) - if (ext2_test_bit(res, p)) + if (test_bit_le(res, p)) break; return (p - addr) * 32 + res; } -static inline unsigned long generic_find_next_le_bit(const unsigned long *addr, +static inline unsigned long find_next_bit_le(const void *addr, unsigned long size, unsigned long offset) { - const unsigned long *p = addr + (offset >> 5); + const unsigned long *p = addr; int bit = offset & 31UL, res; if (offset >= size) return size; + p += offset >> 5; + if (bit) { + offset -= bit; /* Look for one in first longword */ for (res = bit; res < 32; res++) - if (ext2_test_bit(res, p)) - return (p - addr) * 32 + res; + if (test_bit_le(res, p)) + return offset + res; p++; + offset += 32; } /* No set bit yet, search remaining full bytes for a set bit */ - res = ext2_find_first_bit(p, size - 32 * (p - addr)); - return (p - addr) * 32 + res; + return offset + find_first_bit_le(p, size - offset); } +/* Bitmap functions for the ext2 filesystem. */ + +#define ext2_set_bit_atomic(lock, nr, addr) \ + test_and_set_bit_le(nr, addr) +#define ext2_clear_bit_atomic(lock, nr, addr) \ + test_and_clear_bit_le(nr, addr) + #endif /* __KERNEL__ */ #endif /* _M68K_BITOPS_H */ diff --git a/arch/m68k/include/asm/bitops_no.h b/arch/m68k/include/asm/bitops_no.h index 9d3cbe5fad1..7d3779fdc5b 100644 --- a/arch/m68k/include/asm/bitops_no.h +++ b/arch/m68k/include/asm/bitops_no.h @@ -196,7 +196,19 @@ static __inline__ int __test_bit(int nr, const volatile unsigned long * addr) #include <asm-generic/bitops/hweight.h> #include <asm-generic/bitops/lock.h> -static __inline__ int ext2_set_bit(int nr, volatile void * addr) +#define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7) + +static inline void __set_bit_le(int nr, void *addr) +{ + __set_bit(nr ^ BITOP_LE_SWIZZLE, addr); +} + +static inline void __clear_bit_le(int nr, void *addr) +{ + __clear_bit(nr ^ BITOP_LE_SWIZZLE, addr); +} + +static inline int __test_and_set_bit_le(int nr, volatile void *addr) { char retval; @@ -215,7 +227,7 @@ static __inline__ int ext2_set_bit(int nr, volatile void * addr) return retval; } -static __inline__ int ext2_clear_bit(int nr, volatile void * addr) +static inline int __test_and_clear_bit_le(int nr, volatile void *addr) { char retval; @@ -238,7 +250,7 @@ static __inline__ int ext2_clear_bit(int nr, volatile void * addr) ({ \ int ret; \ spin_lock(lock); \ - ret = ext2_set_bit((nr), (addr)); \ + ret = __test_and_set_bit_le((nr), (addr)); \ spin_unlock(lock); \ ret; \ }) @@ -247,12 +259,12 @@ static __inline__ int ext2_clear_bit(int nr, volatile void * addr) ({ \ int ret; \ spin_lock(lock); \ - ret = ext2_clear_bit((nr), (addr)); \ + ret = __test_and_clear_bit_le((nr), (addr)); \ spin_unlock(lock); \ ret; \ }) -static __inline__ int ext2_test_bit(int nr, const volatile void * addr) +static inline int test_bit_le(int nr, const volatile void *addr) { char retval; @@ -271,10 +283,10 @@ static __inline__ int ext2_test_bit(int nr, const volatile void * addr) return retval; } -#define ext2_find_first_zero_bit(addr, size) \ - ext2_find_next_zero_bit((addr), (size), 0) +#define find_first_zero_bit_le(addr, size) \ + find_next_zero_bit_le((addr), (size), 0) -static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) +static inline unsigned long find_next_zero_bit_le(void *addr, unsigned long size, unsigned long offset) { unsigned long *p = ((unsigned long *) addr) + (offset >> 5); unsigned long result = offset & ~31UL; @@ -324,10 +336,6 @@ found_middle: return result + ffz(__swab32(tmp)); } -#define ext2_find_next_bit(addr, size, off) \ - generic_find_next_le_bit((unsigned long *)(addr), (size), (off)) -#include <asm-generic/bitops/minix.h> - #endif /* __KERNEL__ */ #include <asm-generic/bitops/fls.h> diff --git a/arch/m68k/include/asm/bootstd.h b/arch/m68k/include/asm/bootstd.h index bdc1a4ac4fe..e518f5a575b 100644 --- a/arch/m68k/include/asm/bootstd.h +++ b/arch/m68k/include/asm/bootstd.h @@ -31,7 +31,7 @@ #define __BN_flash_write_range 20 /* Calling conventions compatible to (uC)linux/68k - * We use simmilar macros to call into the bootloader as for uClinux + * We use similar macros to call into the bootloader as for uClinux */ #define __bsc_return(type, res) \ diff --git a/arch/m68k/include/asm/commproc.h b/arch/m68k/include/asm/commproc.h index edf5eb6c08d..a73998528d2 100644 --- a/arch/m68k/include/asm/commproc.h +++ b/arch/m68k/include/asm/commproc.h @@ -88,7 +88,7 @@ typedef struct cpm_buf_desc { /* rx bd status/control bits */ -#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ +#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */ #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */ @@ -96,7 +96,7 @@ typedef struct cpm_buf_desc { #define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */ #define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ +#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */ #define BD_SC_ID ((ushort)0x0100) /* Received too many idles */ #define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */ diff --git a/arch/m68k/include/asm/delay_no.h b/arch/m68k/include/asm/delay_no.h index 55cbd6294ab..c3a0edc90f2 100644 --- a/arch/m68k/include/asm/delay_no.h +++ b/arch/m68k/include/asm/delay_no.h @@ -16,7 +16,7 @@ static inline void __delay(unsigned long loops) * long word alignment which is the faster version. * The 0x4a8e is of course a 'tstl %fp' instruction. This is better * than using a NOP (0x4e71) instruction because it executes in one - * cycle not three and doesn't allow for an arbitary delay waiting + * cycle not three and doesn't allow for an arbitrary delay waiting * for bus cycles to finish. Also fp/a6 isn't likely to cause a * stall waiting for the register to become valid if such is added * to the coldfire at some stage. diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h index c64c7b74cf8..b2046839f4b 100644 --- a/arch/m68k/include/asm/gpio.h +++ b/arch/m68k/include/asm/gpio.h @@ -31,7 +31,7 @@ * GPIOs in a single control area, others have some GPIOs implemented in * different modules. * - * This implementation attempts accomodate the differences while presenting + * This implementation attempts accommodate the differences while presenting * a generic interface that will optimize to as few instructions as possible. */ #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index 55d5a4c5fe0..b6bf2c518ba 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -157,7 +157,7 @@ #define MCFFEC_SIZE 0x800 /* Register set size */ /* - * Reset Controll Unit. + * Reset Control Unit. */ #define MCF_RCR 0xFC0A0000 #define MCF_RSR 0xFC0A0001 diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h index 8996df62ede..6235921eca4 100644 --- a/arch/m68k/include/asm/m523xsim.h +++ b/arch/m68k/include/asm/m523xsim.h @@ -48,7 +48,7 @@ #define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ /* - * Reset Controll Unit (relative to IPSBAR). + * Reset Control Unit (relative to IPSBAR). */ #define MCF_RCR 0x110000 #define MCF_RSR 0x110001 diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index 74855a66c05..758810ef91e 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h @@ -283,7 +283,7 @@ #endif /* - * Reset Controll Unit (relative to IPSBAR). + * Reset Control Unit (relative to IPSBAR). */ #define MCF_RCR 0x110000 #define MCF_RSR 0x110001 diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index 4c94c01f36c..8f8609fcc9b 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h @@ -29,7 +29,7 @@ #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ #define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ #define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ -#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/ +#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/ #define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ #define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ #define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h index 762c58c8905..51e00b00b8a 100644 --- a/arch/m68k/include/asm/m5407sim.h +++ b/arch/m68k/include/asm/m5407sim.h @@ -29,7 +29,7 @@ #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ #define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ #define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ -#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/ +#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/ #define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ #define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ #define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ diff --git a/arch/m68k/include/asm/m68360_quicc.h b/arch/m68k/include/asm/m68360_quicc.h index 6d40f4d18e1..59414cc108d 100644 --- a/arch/m68k/include/asm/m68360_quicc.h +++ b/arch/m68k/include/asm/m68360_quicc.h @@ -32,7 +32,7 @@ struct user_data { /* BASE + 0x000: user data memory */ volatile unsigned char udata_bd_ucode[0x400]; /*user data bd's Ucode*/ volatile unsigned char udata_bd[0x200]; /*user data Ucode */ - volatile unsigned char ucode_ext[0x100]; /*Ucode Extention ram */ + volatile unsigned char ucode_ext[0x100]; /*Ucode Extension ram */ volatile unsigned char RESERVED1[0x500]; /* Reserved area */ }; #else diff --git a/arch/m68k/include/asm/mac_oss.h b/arch/m68k/include/asm/mac_oss.h index 7221f725193..3cf2b6ed685 100644 --- a/arch/m68k/include/asm/mac_oss.h +++ b/arch/m68k/include/asm/mac_oss.h @@ -61,7 +61,7 @@ /* * OSS Interrupt levels for various sub-systems * - * This mapping is layed out with two things in mind: first, we try to keep + * This mapping is laid out with two things in mind: first, we try to keep * things on their own levels to avoid having to do double-dispatches. Second, * the levels match as closely as possible the alternate IRQ mapping mode (aka * "A/UX mode") available on some VIA machines. diff --git a/arch/m68k/include/asm/mac_via.h b/arch/m68k/include/asm/mac_via.h index 39afb438b65..a59665e1d41 100644 --- a/arch/m68k/include/asm/mac_via.h +++ b/arch/m68k/include/asm/mac_via.h @@ -204,7 +204,7 @@ #define vT2CL 0x1000 /* [VIA only] Timer two counter low. */ #define vT2CH 0x1200 /* [VIA only] Timer two counter high. */ #define vSR 0x1400 /* [VIA only] Shift register. */ -#define vACR 0x1600 /* [VIA only] Auxilary control register. */ +#define vACR 0x1600 /* [VIA only] Auxiliary control register. */ #define vPCR 0x1800 /* [VIA only] Peripheral control register. */ /* CHRP sez never ever to *write* this. * Mac family says never to *change* this. diff --git a/arch/m68k/include/asm/macintosh.h b/arch/m68k/include/asm/macintosh.h index 50db3591ca1..c2a1c5eac1a 100644 --- a/arch/m68k/include/asm/macintosh.h +++ b/arch/m68k/include/asm/macintosh.h @@ -14,7 +14,7 @@ extern void mac_init_IRQ(void); extern int mac_irq_pending(unsigned int); /* - * Floppy driver magic hook - probably shouldnt be here + * Floppy driver magic hook - probably shouldn't be here */ extern void via1_set_head(int); diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h index 92b276fe824..351c2723787 100644 --- a/arch/m68k/include/asm/mcftimer.h +++ b/arch/m68k/include/asm/mcftimer.h @@ -27,7 +27,7 @@ /* * Bit definitions for the Timer Mode Register (TMR). - * Register bit flags are common accross ColdFires. + * Register bit flags are common across ColdFires. */ #define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ #define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ diff --git a/arch/m68k/include/asm/types.h b/arch/m68k/include/asm/types.h index 6441cb5f8e7..b17fd115a4e 100644 --- a/arch/m68k/include/asm/types.h +++ b/arch/m68k/include/asm/types.h @@ -23,15 +23,6 @@ typedef unsigned short umode_t; #define BITS_PER_LONG 32 -#ifndef __ASSEMBLY__ - -/* DMA addresses are always 32-bits wide */ - -typedef u32 dma_addr_t; -typedef u32 dma64_addr_t; - -#endif /* __ASSEMBLY__ */ - #endif /* __KERNEL__ */ #endif /* _M68K_TYPES_H */ diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h index 26d851d385b..29e17907d9f 100644 --- a/arch/m68k/include/asm/unistd.h +++ b/arch/m68k/include/asm/unistd.h @@ -343,10 +343,14 @@ #define __NR_fanotify_init 337 #define __NR_fanotify_mark 338 #define __NR_prlimit64 339 +#define __NR_name_to_handle_at 340 +#define __NR_open_by_handle_at 341 +#define __NR_clock_adjtime 342 +#define __NR_syncfs 343 #ifdef __KERNEL__ -#define NR_syscalls 340 +#define NR_syscalls 344 #define __ARCH_WANT_IPC_PARSE_VERSION #define __ARCH_WANT_OLD_READDIR diff --git a/arch/m68k/kernel/Makefile b/arch/m68k/kernel/Makefile index 55d5d6b680a..c482ebc9dd5 100644 --- a/arch/m68k/kernel/Makefile +++ b/arch/m68k/kernel/Makefile @@ -1,17 +1,5 @@ -# -# Makefile for the linux kernel. -# - -ifndef CONFIG_SUN3 - extra-y := head.o +ifdef CONFIG_MMU +include arch/m68k/kernel/Makefile_mm else - extra-y := sun3-head.o +include arch/m68k/kernel/Makefile_no endif -extra-y += vmlinux.lds - -obj-y := entry.o process.o traps.o ints.o signal.o ptrace.o module.o \ - sys_m68k.o time.o setup.o m68k_ksyms.o devres.o - -devres-y = ../../../kernel/irq/devres.o - -obj-y$(CONFIG_MMU_SUN3) += dma.o # no, it's not a typo diff --git a/arch/m68k/kernel/Makefile_mm b/arch/m68k/kernel/Makefile_mm new file mode 100644 index 00000000000..55d5d6b680a --- /dev/null +++ b/arch/m68k/kernel/Makefile_mm @@ -0,0 +1,17 @@ +# +# Makefile for the linux kernel. +# + +ifndef CONFIG_SUN3 + extra-y := head.o +else + extra-y := sun3-head.o +endif +extra-y += vmlinux.lds + +obj-y := entry.o process.o traps.o ints.o signal.o ptrace.o module.o \ + sys_m68k.o time.o setup.o m68k_ksyms.o devres.o + +devres-y = ../../../kernel/irq/devres.o + +obj-y$(CONFIG_MMU_SUN3) += dma.o # no, it's not a typo diff --git a/arch/m68knommu/kernel/Makefile b/arch/m68k/kernel/Makefile_no index 37c3fc074c0..37c3fc074c0 100644 --- a/arch/m68knommu/kernel/Makefile +++ b/arch/m68k/kernel/Makefile_no diff --git a/arch/m68k/kernel/asm-offsets.c b/arch/m68k/kernel/asm-offsets.c index 78e59b82ebc..59a69a5c62f 100644 --- a/arch/m68k/kernel/asm-offsets.c +++ b/arch/m68k/kernel/asm-offsets.c @@ -1,100 +1,5 @@ -/* - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - */ - -#define ASM_OFFSETS_C - -#include <linux/stddef.h> -#include <linux/sched.h> -#include <linux/kernel_stat.h> -#include <linux/kbuild.h> -#include <asm/bootinfo.h> -#include <asm/irq.h> -#include <asm/amigahw.h> -#include <linux/font.h> - -int main(void) -{ - /* offsets into the task struct */ - DEFINE(TASK_THREAD, offsetof(struct task_struct, thread)); - DEFINE(TASK_INFO, offsetof(struct task_struct, thread.info)); - DEFINE(TASK_MM, offsetof(struct task_struct, mm)); #ifdef CONFIG_MMU - DEFINE(TASK_TINFO, offsetof(struct task_struct, thread.info)); +#include "asm-offsets_mm.c" +#else +#include "asm-offsets_no.c" #endif - - /* offsets into the thread struct */ - DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp)); - DEFINE(THREAD_USP, offsetof(struct thread_struct, usp)); - DEFINE(THREAD_SR, offsetof(struct thread_struct, sr)); - DEFINE(THREAD_FS, offsetof(struct thread_struct, fs)); - DEFINE(THREAD_CRP, offsetof(struct thread_struct, crp)); - DEFINE(THREAD_ESP0, offsetof(struct thread_struct, esp0)); - DEFINE(THREAD_FPREG, offsetof(struct thread_struct, fp)); - DEFINE(THREAD_FPCNTL, offsetof(struct thread_struct, fpcntl)); - DEFINE(THREAD_FPSTATE, offsetof(struct thread_struct, fpstate)); - - /* offsets into the thread_info struct */ - DEFINE(TINFO_PREEMPT, offsetof(struct thread_info, preempt_count)); - DEFINE(TINFO_FLAGS, offsetof(struct thread_info, flags)); - - /* offsets into the pt_regs */ - DEFINE(PT_OFF_D0, offsetof(struct pt_regs, d0)); - DEFINE(PT_OFF_ORIG_D0, offsetof(struct pt_regs, orig_d0)); - DEFINE(PT_OFF_D1, offsetof(struct pt_regs, d1)); - DEFINE(PT_OFF_D2, offsetof(struct pt_regs, d2)); - DEFINE(PT_OFF_D3, offsetof(struct pt_regs, d3)); - DEFINE(PT_OFF_D4, offsetof(struct pt_regs, d4)); - DEFINE(PT_OFF_D5, offsetof(struct pt_regs, d5)); - DEFINE(PT_OFF_A0, offsetof(struct pt_regs, a0)); - DEFINE(PT_OFF_A1, offsetof(struct pt_regs, a1)); - DEFINE(PT_OFF_A2, offsetof(struct pt_regs, a2)); - DEFINE(PT_OFF_PC, offsetof(struct pt_regs, pc)); - DEFINE(PT_OFF_SR, offsetof(struct pt_regs, sr)); - /* bitfields are a bit difficult */ - DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4); - - /* offsets into the irq_cpustat_t struct */ - DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending)); - - /* offsets into the bi_record struct */ - DEFINE(BIR_TAG, offsetof(struct bi_record, tag)); - DEFINE(BIR_SIZE, offsetof(struct bi_record, size)); - DEFINE(BIR_DATA, offsetof(struct bi_record, data)); - - /* offsets into font_desc (drivers/video/console/font.h) */ - DEFINE(FONT_DESC_IDX, offsetof(struct font_desc, idx)); - DEFINE(FONT_DESC_NAME, offsetof(struct font_desc, name)); - DEFINE(FONT_DESC_WIDTH, offsetof(struct font_desc, width)); - DEFINE(FONT_DESC_HEIGHT, offsetof(struct font_desc, height)); - DEFINE(FONT_DESC_DATA, offsetof(struct font_desc, data)); - DEFINE(FONT_DESC_PREF, offsetof(struct font_desc, pref)); - - /* signal defines */ - DEFINE(LSIGSEGV, SIGSEGV); - DEFINE(LSEGV_MAPERR, SEGV_MAPERR); - DEFINE(LSIGTRAP, SIGTRAP); - DEFINE(LTRAP_TRACE, TRAP_TRACE); - - /* offsets into the custom struct */ - DEFINE(CUSTOMBASE, &amiga_custom); - DEFINE(C_INTENAR, offsetof(struct CUSTOM, intenar)); - DEFINE(C_INTREQR, offsetof(struct CUSTOM, intreqr)); - DEFINE(C_INTENA, offsetof(struct CUSTOM, intena)); - DEFINE(C_INTREQ, offsetof(struct CUSTOM, intreq)); - DEFINE(C_SERDATR, offsetof(struct CUSTOM, serdatr)); - DEFINE(C_SERDAT, offsetof(struct CUSTOM, serdat)); - DEFINE(C_SERPER, offsetof(struct CUSTOM, serper)); - DEFINE(CIAABASE, &ciaa); - DEFINE(CIABBASE, &ciab); - DEFINE(C_PRA, offsetof(struct CIA, pra)); - DEFINE(ZTWOBASE, zTwoBase); - - return 0; -} diff --git a/arch/m68k/kernel/asm-offsets_mm.c b/arch/m68k/kernel/asm-offsets_mm.c new file mode 100644 index 00000000000..78e59b82ebc --- /dev/null +++ b/arch/m68k/kernel/asm-offsets_mm.c @@ -0,0 +1,100 @@ +/* + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + */ + +#define ASM_OFFSETS_C + +#include <linux/stddef.h> +#include <linux/sched.h> +#include <linux/kernel_stat.h> +#include <linux/kbuild.h> +#include <asm/bootinfo.h> +#include <asm/irq.h> +#include <asm/amigahw.h> +#include <linux/font.h> + +int main(void) +{ + /* offsets into the task struct */ + DEFINE(TASK_THREAD, offsetof(struct task_struct, thread)); + DEFINE(TASK_INFO, offsetof(struct task_struct, thread.info)); + DEFINE(TASK_MM, offsetof(struct task_struct, mm)); +#ifdef CONFIG_MMU + DEFINE(TASK_TINFO, offsetof(struct task_struct, thread.info)); +#endif + + /* offsets into the thread struct */ + DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp)); + DEFINE(THREAD_USP, offsetof(struct thread_struct, usp)); + DEFINE(THREAD_SR, offsetof(struct thread_struct, sr)); + DEFINE(THREAD_FS, offsetof(struct thread_struct, fs)); + DEFINE(THREAD_CRP, offsetof(struct thread_struct, crp)); + DEFINE(THREAD_ESP0, offsetof(struct thread_struct, esp0)); + DEFINE(THREAD_FPREG, offsetof(struct thread_struct, fp)); + DEFINE(THREAD_FPCNTL, offsetof(struct thread_struct, fpcntl)); + DEFINE(THREAD_FPSTATE, offsetof(struct thread_struct, fpstate)); + + /* offsets into the thread_info struct */ + DEFINE(TINFO_PREEMPT, offsetof(struct thread_info, preempt_count)); + DEFINE(TINFO_FLAGS, offsetof(struct thread_info, flags)); + + /* offsets into the pt_regs */ + DEFINE(PT_OFF_D0, offsetof(struct pt_regs, d0)); + DEFINE(PT_OFF_ORIG_D0, offsetof(struct pt_regs, orig_d0)); + DEFINE(PT_OFF_D1, offsetof(struct pt_regs, d1)); + DEFINE(PT_OFF_D2, offsetof(struct pt_regs, d2)); + DEFINE(PT_OFF_D3, offsetof(struct pt_regs, d3)); + DEFINE(PT_OFF_D4, offsetof(struct pt_regs, d4)); + DEFINE(PT_OFF_D5, offsetof(struct pt_regs, d5)); + DEFINE(PT_OFF_A0, offsetof(struct pt_regs, a0)); + DEFINE(PT_OFF_A1, offsetof(struct pt_regs, a1)); + DEFINE(PT_OFF_A2, offsetof(struct pt_regs, a2)); + DEFINE(PT_OFF_PC, offsetof(struct pt_regs, pc)); + DEFINE(PT_OFF_SR, offsetof(struct pt_regs, sr)); + /* bitfields are a bit difficult */ + DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4); + + /* offsets into the irq_cpustat_t struct */ + DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending)); + + /* offsets into the bi_record struct */ + DEFINE(BIR_TAG, offsetof(struct bi_record, tag)); + DEFINE(BIR_SIZE, offsetof(struct bi_record, size)); + DEFINE(BIR_DATA, offsetof(struct bi_record, data)); + + /* offsets into font_desc (drivers/video/console/font.h) */ + DEFINE(FONT_DESC_IDX, offsetof(struct font_desc, idx)); + DEFINE(FONT_DESC_NAME, offsetof(struct font_desc, name)); + DEFINE(FONT_DESC_WIDTH, offsetof(struct font_desc, width)); + DEFINE(FONT_DESC_HEIGHT, offsetof(struct font_desc, height)); + DEFINE(FONT_DESC_DATA, offsetof(struct font_desc, data)); + DEFINE(FONT_DESC_PREF, offsetof(struct font_desc, pref)); + + /* signal defines */ + DEFINE(LSIGSEGV, SIGSEGV); + DEFINE(LSEGV_MAPERR, SEGV_MAPERR); + DEFINE(LSIGTRAP, SIGTRAP); + DEFINE(LTRAP_TRACE, TRAP_TRACE); + + /* offsets into the custom struct */ + DEFINE(CUSTOMBASE, &amiga_custom); + DEFINE(C_INTENAR, offsetof(struct CUSTOM, intenar)); + DEFINE(C_INTREQR, offsetof(struct CUSTOM, intreqr)); + DEFINE(C_INTENA, offsetof(struct CUSTOM, intena)); + DEFINE(C_INTREQ, offsetof(struct CUSTOM, intreq)); + DEFINE(C_SERDATR, offsetof(struct CUSTOM, serdatr)); + DEFINE(C_SERDAT, offsetof(struct CUSTOM, serdat)); + DEFINE(C_SERPER, offsetof(struct CUSTOM, serper)); + DEFINE(CIAABASE, &ciaa); + DEFINE(CIABBASE, &ciab); + DEFINE(C_PRA, offsetof(struct CIA, pra)); + DEFINE(ZTWOBASE, zTwoBase); + + return 0; +} diff --git a/arch/m68knommu/kernel/asm-offsets.c b/arch/m68k/kernel/asm-offsets_no.c index ffe02f41ad4..ffe02f41ad4 100644 --- a/arch/m68knommu/kernel/asm-offsets.c +++ b/arch/m68k/kernel/asm-offsets_no.c diff --git a/arch/m68k/kernel/dma.c b/arch/m68k/kernel/dma.c index 4bbb3c2a888..90e8cb726c8 100644 --- a/arch/m68k/kernel/dma.c +++ b/arch/m68k/kernel/dma.c @@ -1,130 +1,5 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#undef DEBUG - -#include <linux/dma-mapping.h> -#include <linux/device.h> -#include <linux/kernel.h> -#include <linux/scatterlist.h> -#include <linux/slab.h> -#include <linux/vmalloc.h> - -#include <asm/pgalloc.h> - -void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *handle, gfp_t flag) -{ - struct page *page, **map; - pgprot_t pgprot; - void *addr; - int i, order; - - pr_debug("dma_alloc_coherent: %d,%x\n", size, flag); - - size = PAGE_ALIGN(size); - order = get_order(size); - - page = alloc_pages(flag, order); - if (!page) - return NULL; - - *handle = page_to_phys(page); - map = kmalloc(sizeof(struct page *) << order, flag & ~__GFP_DMA); - if (!map) { - __free_pages(page, order); - return NULL; - } - split_page(page, order); - - order = 1 << order; - size >>= PAGE_SHIFT; - map[0] = page; - for (i = 1; i < size; i++) - map[i] = page + i; - for (; i < order; i++) - __free_page(page + i); - pgprot = __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY); - if (CPU_IS_040_OR_060) - pgprot_val(pgprot) |= _PAGE_GLOBAL040 | _PAGE_NOCACHE_S; - else - pgprot_val(pgprot) |= _PAGE_NOCACHE030; - addr = vmap(map, size, VM_MAP, pgprot); - kfree(map); - - return addr; -} -EXPORT_SYMBOL(dma_alloc_coherent); - -void dma_free_coherent(struct device *dev, size_t size, - void *addr, dma_addr_t handle) -{ - pr_debug("dma_free_coherent: %p, %x\n", addr, handle); - vfree(addr); -} -EXPORT_SYMBOL(dma_free_coherent); - -void dma_sync_single_for_device(struct device *dev, dma_addr_t handle, - size_t size, enum dma_data_direction dir) -{ - switch (dir) { - case DMA_TO_DEVICE: - cache_push(handle, size); - break; - case DMA_FROM_DEVICE: - cache_clear(handle, size); - break; - default: - if (printk_ratelimit()) - printk("dma_sync_single_for_device: unsupported dir %u\n", dir); - break; - } -} -EXPORT_SYMBOL(dma_sync_single_for_device); - -void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction dir) -{ - int i; - - for (i = 0; i < nents; sg++, i++) - dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir); -} -EXPORT_SYMBOL(dma_sync_sg_for_device); - -dma_addr_t dma_map_single(struct device *dev, void *addr, size_t size, - enum dma_data_direction dir) -{ - dma_addr_t handle = virt_to_bus(addr); - - dma_sync_single_for_device(dev, handle, size, dir); - return handle; -} -EXPORT_SYMBOL(dma_map_single); - -dma_addr_t dma_map_page(struct device *dev, struct page *page, - unsigned long offset, size_t size, - enum dma_data_direction dir) -{ - dma_addr_t handle = page_to_phys(page) + offset; - - dma_sync_single_for_device(dev, handle, size, dir); - return handle; -} -EXPORT_SYMBOL(dma_map_page); - -int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction dir) -{ - int i; - - for (i = 0; i < nents; sg++, i++) { - sg->dma_address = sg_phys(sg); - dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir); - } - return nents; -} -EXPORT_SYMBOL(dma_map_sg); +#ifdef CONFIG_MMU +#include "dma_mm.c" +#else +#include "dma_no.c" +#endif diff --git a/arch/m68k/kernel/dma_mm.c b/arch/m68k/kernel/dma_mm.c new file mode 100644 index 00000000000..4bbb3c2a888 --- /dev/null +++ b/arch/m68k/kernel/dma_mm.c @@ -0,0 +1,130 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#undef DEBUG + +#include <linux/dma-mapping.h> +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/scatterlist.h> +#include <linux/slab.h> +#include <linux/vmalloc.h> + +#include <asm/pgalloc.h> + +void *dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *handle, gfp_t flag) +{ + struct page *page, **map; + pgprot_t pgprot; + void *addr; + int i, order; + + pr_debug("dma_alloc_coherent: %d,%x\n", size, flag); + + size = PAGE_ALIGN(size); + order = get_order(size); + + page = alloc_pages(flag, order); + if (!page) + return NULL; + + *handle = page_to_phys(page); + map = kmalloc(sizeof(struct page *) << order, flag & ~__GFP_DMA); + if (!map) { + __free_pages(page, order); + return NULL; + } + split_page(page, order); + + order = 1 << order; + size >>= PAGE_SHIFT; + map[0] = page; + for (i = 1; i < size; i++) + map[i] = page + i; + for (; i < order; i++) + __free_page(page + i); + pgprot = __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY); + if (CPU_IS_040_OR_060) + pgprot_val(pgprot) |= _PAGE_GLOBAL040 | _PAGE_NOCACHE_S; + else + pgprot_val(pgprot) |= _PAGE_NOCACHE030; + addr = vmap(map, size, VM_MAP, pgprot); + kfree(map); + + return addr; +} +EXPORT_SYMBOL(dma_alloc_coherent); + +void dma_free_coherent(struct device *dev, size_t size, + void *addr, dma_addr_t handle) +{ + pr_debug("dma_free_coherent: %p, %x\n", addr, handle); + vfree(addr); +} +EXPORT_SYMBOL(dma_free_coherent); + +void dma_sync_single_for_device(struct device *dev, dma_addr_t handle, + size_t size, enum dma_data_direction dir) +{ + switch (dir) { + case DMA_TO_DEVICE: + cache_push(handle, size); + break; + case DMA_FROM_DEVICE: + cache_clear(handle, size); + break; + default: + if (printk_ratelimit()) + printk("dma_sync_single_for_device: unsupported dir %u\n", dir); + break; + } +} +EXPORT_SYMBOL(dma_sync_single_for_device); + +void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction dir) +{ + int i; + + for (i = 0; i < nents; sg++, i++) + dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir); +} +EXPORT_SYMBOL(dma_sync_sg_for_device); + +dma_addr_t dma_map_single(struct device *dev, void *addr, size_t size, + enum dma_data_direction dir) +{ + dma_addr_t handle = virt_to_bus(addr); + + dma_sync_single_for_device(dev, handle, size, dir); + return handle; +} +EXPORT_SYMBOL(dma_map_single); + +dma_addr_t dma_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction dir) +{ + dma_addr_t handle = page_to_phys(page) + offset; + + dma_sync_single_for_device(dev, handle, size, dir); + return handle; +} +EXPORT_SYMBOL(dma_map_page); + +int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction dir) +{ + int i; + + for (i = 0; i < nents; sg++, i++) { + sg->dma_address = sg_phys(sg); + dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir); + } + return nents; +} +EXPORT_SYMBOL(dma_map_sg); diff --git a/arch/m68knommu/kernel/dma.c b/arch/m68k/kernel/dma_no.c index fc61541aeb7..fc61541aeb7 100644 --- a/arch/m68knommu/kernel/dma.c +++ b/arch/m68k/kernel/dma_no.c diff --git a/arch/m68k/kernel/entry.S b/arch/m68k/kernel/entry.S index 1559dea36e5..081cf96f243 100644 --- a/arch/m68k/kernel/entry.S +++ b/arch/m68k/kernel/entry.S @@ -1,753 +1,5 @@ -/* -*- mode: asm -*- - * - * linux/arch/m68k/kernel/entry.S - * - * Copyright (C) 1991, 1992 Linus Torvalds - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file README.legal in the main directory of this archive - * for more details. - * - * Linux/m68k support by Hamish Macdonald - * - * 68060 fixes by Jesper Skov - * - */ - -/* - * entry.S contains the system-call and fault low-level handling routines. - * This also contains the timer-interrupt handler, as well as all interrupts - * and faults that can result in a task-switch. - * - * NOTE: This code handles signal-recognition, which happens every time - * after a timer-interrupt and after each system call. - * - */ - -/* - * 12/03/96 Jes: Currently we only support m68k single-cpu systems, so - * all pointers that used to be 'current' are now entry - * number 0 in the 'current_set' list. - * - * 6/05/00 RZ: addedd writeback completion after return from sighandler - * for 68040 - */ - -#include <linux/linkage.h> -#include <asm/entry.h> -#include <asm/errno.h> -#include <asm/setup.h> -#include <asm/segment.h> -#include <asm/traps.h> -#include <asm/unistd.h> - -#include <asm/asm-offsets.h> - -.globl system_call, buserr, trap, resume -.globl sys_call_table -.globl sys_fork, sys_clone, sys_vfork -.globl ret_from_interrupt, bad_interrupt -.globl auto_irqhandler_fixup -.globl user_irqvec_fixup, user_irqhandler_fixup - -.text -ENTRY(buserr) - SAVE_ALL_INT - GET_CURRENT(%d0) - movel %sp,%sp@- | stack frame pointer argument - bsrl buserr_c - addql #4,%sp - jra .Lret_from_exception - -ENTRY(trap) - SAVE_ALL_INT - GET_CURRENT(%d0) - movel %sp,%sp@- | stack frame pointer argument - bsrl trap_c - addql #4,%sp - jra .Lret_from_exception - - | After a fork we jump here directly from resume, - | so that %d1 contains the previous task - | schedule_tail now used regardless of CONFIG_SMP -ENTRY(ret_from_fork) - movel %d1,%sp@- - jsr schedule_tail - addql #4,%sp - jra .Lret_from_exception - -do_trace_entry: - movel #-ENOSYS,%sp@(PT_OFF_D0)| needed for strace - subql #4,%sp - SAVE_SWITCH_STACK - jbsr syscall_trace - RESTORE_SWITCH_STACK - addql #4,%sp - movel %sp@(PT_OFF_ORIG_D0),%d0 - cmpl #NR_syscalls,%d0 - jcs syscall -badsys: - movel #-ENOSYS,%sp@(PT_OFF_D0) - jra ret_from_syscall - -do_trace_exit: - subql #4,%sp - SAVE_SWITCH_STACK - jbsr syscall_trace - RESTORE_SWITCH_STACK - addql #4,%sp - jra .Lret_from_exception - -ENTRY(ret_from_signal) - tstb %curptr@(TASK_INFO+TINFO_FLAGS+2) - jge 1f - jbsr syscall_trace -1: RESTORE_SWITCH_STACK - addql #4,%sp -/* on 68040 complete pending writebacks if any */ -#ifdef CONFIG_M68040 - bfextu %sp@(PT_OFF_FORMATVEC){#0,#4},%d0 - subql #7,%d0 | bus error frame ? - jbne 1f - movel %sp,%sp@- - jbsr berr_040cleanup - addql #4,%sp -1: +#ifdef CONFIG_MMU +#include "entry_mm.S" +#else +#include "entry_no.S" #endif - jra .Lret_from_exception - -ENTRY(system_call) - SAVE_ALL_SYS - - GET_CURRENT(%d1) - | save top of frame - movel %sp,%curptr@(TASK_THREAD+THREAD_ESP0) - - | syscall trace? - tstb %curptr@(TASK_INFO+TINFO_FLAGS+2) - jmi do_trace_entry - cmpl #NR_syscalls,%d0 - jcc badsys -syscall: - jbsr @(sys_call_table,%d0:l:4)@(0) - movel %d0,%sp@(PT_OFF_D0) | save the return value -ret_from_syscall: - |oriw #0x0700,%sr - movew %curptr@(TASK_INFO+TINFO_FLAGS+2),%d0 - jne syscall_exit_work -1: RESTORE_ALL - -syscall_exit_work: - btst #5,%sp@(PT_OFF_SR) | check if returning to kernel - bnes 1b | if so, skip resched, signals - lslw #1,%d0 - jcs do_trace_exit - jmi do_delayed_trace - lslw #8,%d0 - jmi do_signal_return - pea resume_userspace - jra schedule - - -ENTRY(ret_from_exception) -.Lret_from_exception: - btst #5,%sp@(PT_OFF_SR) | check if returning to kernel - bnes 1f | if so, skip resched, signals - | only allow interrupts when we are really the last one on the - | kernel stack, otherwise stack overflow can occur during - | heavy interrupt load - andw #ALLOWINT,%sr - -resume_userspace: - moveb %curptr@(TASK_INFO+TINFO_FLAGS+3),%d0 - jne exit_work -1: RESTORE_ALL - -exit_work: - | save top of frame - movel %sp,%curptr@(TASK_THREAD+THREAD_ESP0) - lslb #1,%d0 - jmi do_signal_return - pea resume_userspace - jra schedule - - -do_signal_return: - |andw #ALLOWINT,%sr - subql #4,%sp | dummy return address - SAVE_SWITCH_STACK - pea %sp@(SWITCH_STACK_SIZE) - bsrl do_signal - addql #4,%sp - RESTORE_SWITCH_STACK - addql #4,%sp - jbra resume_userspace - -do_delayed_trace: - bclr #7,%sp@(PT_OFF_SR) | clear trace bit in SR - pea 1 | send SIGTRAP - movel %curptr,%sp@- - pea LSIGTRAP - jbsr send_sig - addql #8,%sp - addql #4,%sp - jbra resume_userspace - - -/* This is the main interrupt handler for autovector interrupts */ - -ENTRY(auto_inthandler) - SAVE_ALL_INT - GET_CURRENT(%d0) - addqb #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1) - | put exception # in d0 - bfextu %sp@(PT_OFF_FORMATVEC){#4,#10},%d0 - subw #VEC_SPUR,%d0 - - movel %sp,%sp@- - movel %d0,%sp@- | put vector # on stack -auto_irqhandler_fixup = . + 2 - jsr __m68k_handle_int | process the IRQ - addql #8,%sp | pop parameters off stack - -ret_from_interrupt: - subqb #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1) - jeq ret_from_last_interrupt -2: RESTORE_ALL - - ALIGN -ret_from_last_interrupt: - moveq #(~ALLOWINT>>8)&0xff,%d0 - andb %sp@(PT_OFF_SR),%d0 - jne 2b - - /* check if we need to do software interrupts */ - tstl irq_stat+CPUSTAT_SOFTIRQ_PENDING - jeq .Lret_from_exception - pea ret_from_exception - jra do_softirq - -/* Handler for user defined interrupt vectors */ - -ENTRY(user_inthandler) - SAVE_ALL_INT - GET_CURRENT(%d0) - addqb #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1) - | put exception # in d0 - bfextu %sp@(PT_OFF_FORMATVEC){#4,#10},%d0 -user_irqvec_fixup = . + 2 - subw #VEC_USER,%d0 - - movel %sp,%sp@- - movel %d0,%sp@- | put vector # on stack -user_irqhandler_fixup = . + 2 - jsr __m68k_handle_int | process the IRQ - addql #8,%sp | pop parameters off stack - - subqb #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1) - jeq ret_from_last_interrupt - RESTORE_ALL - -/* Handler for uninitialized and spurious interrupts */ - -ENTRY(bad_inthandler) - SAVE_ALL_INT - GET_CURRENT(%d0) - addqb #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1) - - movel %sp,%sp@- - jsr handle_badint - addql #4,%sp - - subqb #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1) - jeq ret_from_last_interrupt - RESTORE_ALL - - -ENTRY(sys_fork) - SAVE_SWITCH_STACK - pea %sp@(SWITCH_STACK_SIZE) - jbsr m68k_fork - addql #4,%sp - RESTORE_SWITCH_STACK - rts - -ENTRY(sys_clone) - SAVE_SWITCH_STACK - pea %sp@(SWITCH_STACK_SIZE) - jbsr m68k_clone - addql #4,%sp - RESTORE_SWITCH_STACK - rts - -ENTRY(sys_vfork) - SAVE_SWITCH_STACK - pea %sp@(SWITCH_STACK_SIZE) - jbsr m68k_vfork - addql #4,%sp - RESTORE_SWITCH_STACK - rts - -ENTRY(sys_sigreturn) - SAVE_SWITCH_STACK - jbsr do_sigreturn - RESTORE_SWITCH_STACK - rts - -ENTRY(sys_rt_sigreturn) - SAVE_SWITCH_STACK - jbsr do_rt_sigreturn - RESTORE_SWITCH_STACK - rts - -resume: - /* - * Beware - when entering resume, prev (the current task) is - * in a0, next (the new task) is in a1,so don't change these - * registers until their contents are no longer needed. - */ - - /* save sr */ - movew %sr,%a0@(TASK_THREAD+THREAD_SR) - - /* save fs (sfc,%dfc) (may be pointing to kernel memory) */ - movec %sfc,%d0 - movew %d0,%a0@(TASK_THREAD+THREAD_FS) - - /* save usp */ - /* it is better to use a movel here instead of a movew 8*) */ - movec %usp,%d0 - movel %d0,%a0@(TASK_THREAD+THREAD_USP) - - /* save non-scratch registers on stack */ - SAVE_SWITCH_STACK - - /* save current kernel stack pointer */ - movel %sp,%a0@(TASK_THREAD+THREAD_KSP) - - /* save floating point context */ -#ifndef CONFIG_M68KFPU_EMU_ONLY -#ifdef CONFIG_M68KFPU_EMU - tstl m68k_fputype - jeq 3f -#endif - fsave %a0@(TASK_THREAD+THREAD_FPSTATE) - -#if defined(CONFIG_M68060) -#if !defined(CPU_M68060_ONLY) - btst #3,m68k_cputype+3 - beqs 1f -#endif - /* The 060 FPU keeps status in bits 15-8 of the first longword */ - tstb %a0@(TASK_THREAD+THREAD_FPSTATE+2) - jeq 3f -#if !defined(CPU_M68060_ONLY) - jra 2f -#endif -#endif /* CONFIG_M68060 */ -#if !defined(CPU_M68060_ONLY) -1: tstb %a0@(TASK_THREAD+THREAD_FPSTATE) - jeq 3f -#endif -2: fmovemx %fp0-%fp7,%a0@(TASK_THREAD+THREAD_FPREG) - fmoveml %fpcr/%fpsr/%fpiar,%a0@(TASK_THREAD+THREAD_FPCNTL) -3: -#endif /* CONFIG_M68KFPU_EMU_ONLY */ - /* Return previous task in %d1 */ - movel %curptr,%d1 - - /* switch to new task (a1 contains new task) */ - movel %a1,%curptr - - /* restore floating point context */ -#ifndef CONFIG_M68KFPU_EMU_ONLY -#ifdef CONFIG_M68KFPU_EMU - tstl m68k_fputype - jeq 4f -#endif -#if defined(CONFIG_M68060) -#if !defined(CPU_M68060_ONLY) - btst #3,m68k_cputype+3 - beqs 1f -#endif - /* The 060 FPU keeps status in bits 15-8 of the first longword */ - tstb %a1@(TASK_THREAD+THREAD_FPSTATE+2) - jeq 3f -#if !defined(CPU_M68060_ONLY) - jra 2f -#endif -#endif /* CONFIG_M68060 */ -#if !defined(CPU_M68060_ONLY) -1: tstb %a1@(TASK_THREAD+THREAD_FPSTATE) - jeq 3f -#endif -2: fmovemx %a1@(TASK_THREAD+THREAD_FPREG),%fp0-%fp7 - fmoveml %a1@(TASK_THREAD+THREAD_FPCNTL),%fpcr/%fpsr/%fpiar -3: frestore %a1@(TASK_THREAD+THREAD_FPSTATE) -4: -#endif /* CONFIG_M68KFPU_EMU_ONLY */ - - /* restore the kernel stack pointer */ - movel %a1@(TASK_THREAD+THREAD_KSP),%sp - - /* restore non-scratch registers */ - RESTORE_SWITCH_STACK - - /* restore user stack pointer */ - movel %a1@(TASK_THREAD+THREAD_USP),%a0 - movel %a0,%usp - - /* restore fs (sfc,%dfc) */ - movew %a1@(TASK_THREAD+THREAD_FS),%a0 - movec %a0,%sfc - movec %a0,%dfc - - /* restore status register */ - movew %a1@(TASK_THREAD+THREAD_SR),%sr - - rts - -.data -ALIGN -sys_call_table: - .long sys_restart_syscall /* 0 - old "setup()" system call, used for restarting */ - .long sys_exit - .long sys_fork - .long sys_read - .long sys_write - .long sys_open /* 5 */ - .long sys_close - .long sys_waitpid - .long sys_creat - .long sys_link - .long sys_unlink /* 10 */ - .long sys_execve - .long sys_chdir - .long sys_time - .long sys_mknod - .long sys_chmod /* 15 */ - .long sys_chown16 - .long sys_ni_syscall /* old break syscall holder */ - .long sys_stat - .long sys_lseek - .long sys_getpid /* 20 */ - .long sys_mount - .long sys_oldumount - .long sys_setuid16 - .long sys_getuid16 - .long sys_stime /* 25 */ - .long sys_ptrace - .long sys_alarm - .long sys_fstat - .long sys_pause - .long sys_utime /* 30 */ - .long sys_ni_syscall /* old stty syscall holder */ - .long sys_ni_syscall /* old gtty syscall holder */ - .long sys_access - .long sys_nice - .long sys_ni_syscall /* 35 */ /* old ftime syscall holder */ - .long sys_sync - .long sys_kill - .long sys_rename - .long sys_mkdir - .long sys_rmdir /* 40 */ - .long sys_dup - .long sys_pipe - .long sys_times - .long sys_ni_syscall /* old prof syscall holder */ - .long sys_brk /* 45 */ - .long sys_setgid16 - .long sys_getgid16 - .long sys_signal - .long sys_geteuid16 - .long sys_getegid16 /* 50 */ - .long sys_acct - .long sys_umount /* recycled never used phys() */ - .long sys_ni_syscall /* old lock syscall holder */ - .long sys_ioctl - .long sys_fcntl /* 55 */ - .long sys_ni_syscall /* old mpx syscall holder */ - .long sys_setpgid - .long sys_ni_syscall /* old ulimit syscall holder */ - .long sys_ni_syscall - .long sys_umask /* 60 */ - .long sys_chroot - .long sys_ustat - .long sys_dup2 - .long sys_getppid - .long sys_getpgrp /* 65 */ - .long sys_setsid - .long sys_sigaction - .long sys_sgetmask - .long sys_ssetmask - .long sys_setreuid16 /* 70 */ - .long sys_setregid16 - .long sys_sigsuspend - .long sys_sigpending - .long sys_sethostname - .long sys_setrlimit /* 75 */ - .long sys_old_getrlimit - .long sys_getrusage - .long sys_gettimeofday - .long sys_settimeofday - .long sys_getgroups16 /* 80 */ - .long sys_setgroups16 - .long sys_old_select - .long sys_symlink - .long sys_lstat - .long sys_readlink /* 85 */ - .long sys_uselib - .long sys_swapon - .long sys_reboot - .long sys_old_readdir - .long sys_old_mmap /* 90 */ - .long sys_munmap - .long sys_truncate - .long sys_ftruncate - .long sys_fchmod - .long sys_fchown16 /* 95 */ - .long sys_getpriority - .long sys_setpriority - .long sys_ni_syscall /* old profil syscall holder */ - .long sys_statfs - .long sys_fstatfs /* 100 */ - .long sys_ni_syscall /* ioperm for i386 */ - .long sys_socketcall - .long sys_syslog - .long sys_setitimer - .long sys_getitimer /* 105 */ - .long sys_newstat - .long sys_newlstat - .long sys_newfstat - .long sys_ni_syscall - .long sys_ni_syscall /* 110 */ /* iopl for i386 */ - .long sys_vhangup - .long sys_ni_syscall /* obsolete idle() syscall */ - .long sys_ni_syscall /* vm86old for i386 */ - .long sys_wait4 - .long sys_swapoff /* 115 */ - .long sys_sysinfo - .long sys_ipc - .long sys_fsync - .long sys_sigreturn - .long sys_clone /* 120 */ - .long sys_setdomainname - .long sys_newuname - .long sys_cacheflush /* modify_ldt for i386 */ - .long sys_adjtimex - .long sys_mprotect /* 125 */ - .long sys_sigprocmask - .long sys_ni_syscall /* old "create_module" */ - .long sys_init_module - .long sys_delete_module - .long sys_ni_syscall /* 130 - old "get_kernel_syms" */ - .long sys_quotactl - .long sys_getpgid - .long sys_fchdir - .long sys_bdflush - .long sys_sysfs /* 135 */ - .long sys_personality - .long sys_ni_syscall /* for afs_syscall */ - .long sys_setfsuid16 - .long sys_setfsgid16 - .long sys_llseek /* 140 */ - .long sys_getdents - .long sys_select - .long sys_flock - .long sys_msync - .long sys_readv /* 145 */ - .long sys_writev - .long sys_getsid - .long sys_fdatasync - .long sys_sysctl - .long sys_mlock /* 150 */ - .long sys_munlock - .long sys_mlockall - .long sys_munlockall - .long sys_sched_setparam - .long sys_sched_getparam /* 155 */ - .long sys_sched_setscheduler - .long sys_sched_getscheduler - .long sys_sched_yield - .long sys_sched_get_priority_max - .long sys_sched_get_priority_min /* 160 */ - .long sys_sched_rr_get_interval - .long sys_nanosleep - .long sys_mremap - .long sys_setresuid16 - .long sys_getresuid16 /* 165 */ - .long sys_getpagesize - .long sys_ni_syscall /* old sys_query_module */ - .long sys_poll - .long sys_nfsservctl - .long sys_setresgid16 /* 170 */ - .long sys_getresgid16 - .long sys_prctl - .long sys_rt_sigreturn - .long sys_rt_sigaction - .long sys_rt_sigprocmask /* 175 */ - .long sys_rt_sigpending - .long sys_rt_sigtimedwait - .long sys_rt_sigqueueinfo - .long sys_rt_sigsuspend - .long sys_pread64 /* 180 */ - .long sys_pwrite64 - .long sys_lchown16; - .long sys_getcwd - .long sys_capget - .long sys_capset /* 185 */ - .long sys_sigaltstack - .long sys_sendfile - .long sys_ni_syscall /* streams1 */ - .long sys_ni_syscall /* streams2 */ - .long sys_vfork /* 190 */ - .long sys_getrlimit - .long sys_mmap2 - .long sys_truncate64 - .long sys_ftruncate64 - .long sys_stat64 /* 195 */ - .long sys_lstat64 - .long sys_fstat64 - .long sys_chown - .long sys_getuid - .long sys_getgid /* 200 */ - .long sys_geteuid - .long sys_getegid - .long sys_setreuid - .long sys_setregid - .long sys_getgroups /* 205 */ - .long sys_setgroups - .long sys_fchown - .long sys_setresuid - .long sys_getresuid - .long sys_setresgid /* 210 */ - .long sys_getresgid - .long sys_lchown - .long sys_setuid - .long sys_setgid - .long sys_setfsuid /* 215 */ - .long sys_setfsgid - .long sys_pivot_root - .long sys_ni_syscall - .long sys_ni_syscall - .long sys_getdents64 /* 220 */ - .long sys_gettid - .long sys_tkill - .long sys_setxattr - .long sys_lsetxattr - .long sys_fsetxattr /* 225 */ - .long sys_getxattr - .long sys_lgetxattr - .long sys_fgetxattr - .long sys_listxattr - .long sys_llistxattr /* 230 */ - .long sys_flistxattr - .long sys_removexattr - .long sys_lremovexattr - .long sys_fremovexattr - .long sys_futex /* 235 */ - .long sys_sendfile64 - .long sys_mincore - .long sys_madvise - .long sys_fcntl64 - .long sys_readahead /* 240 */ - .long sys_io_setup - .long sys_io_destroy - .long sys_io_getevents - .long sys_io_submit - .long sys_io_cancel /* 245 */ - .long sys_fadvise64 - .long sys_exit_group - .long sys_lookup_dcookie - .long sys_epoll_create - .long sys_epoll_ctl /* 250 */ - .long sys_epoll_wait - .long sys_remap_file_pages - .long sys_set_tid_address - .long sys_timer_create - .long sys_timer_settime /* 255 */ - .long sys_timer_gettime - .long sys_timer_getoverrun - .long sys_timer_delete - .long sys_clock_settime - .long sys_clock_gettime /* 260 */ - .long sys_clock_getres - .long sys_clock_nanosleep - .long sys_statfs64 - .long sys_fstatfs64 - .long sys_tgkill /* 265 */ - .long sys_utimes - .long sys_fadvise64_64 - .long sys_mbind - .long sys_get_mempolicy - .long sys_set_mempolicy /* 270 */ - .long sys_mq_open - .long sys_mq_unlink - .long sys_mq_timedsend - .long sys_mq_timedreceive - .long sys_mq_notify /* 275 */ - .long sys_mq_getsetattr - .long sys_waitid - .long sys_ni_syscall /* for sys_vserver */ - .long sys_add_key - .long sys_request_key /* 280 */ - .long sys_keyctl - .long sys_ioprio_set - .long sys_ioprio_get - .long sys_inotify_init - .long sys_inotify_add_watch /* 285 */ - .long sys_inotify_rm_watch - .long sys_migrate_pages - .long sys_openat - .long sys_mkdirat - .long sys_mknodat /* 290 */ - .long sys_fchownat - .long sys_futimesat - .long sys_fstatat64 - .long sys_unlinkat - .long sys_renameat /* 295 */ - .long sys_linkat - .long sys_symlinkat - .long sys_readlinkat - .long sys_fchmodat - .long sys_faccessat /* 300 */ - .long sys_ni_syscall /* Reserved for pselect6 */ - .long sys_ni_syscall /* Reserved for ppoll */ - .long sys_unshare - .long sys_set_robust_list - .long sys_get_robust_list /* 305 */ - .long sys_splice - .long sys_sync_file_range - .long sys_tee - .long sys_vmsplice - .long sys_move_pages /* 310 */ - .long sys_sched_setaffinity - .long sys_sched_getaffinity - .long sys_kexec_load - .long sys_getcpu - .long sys_epoll_pwait /* 315 */ - .long sys_utimensat - .long sys_signalfd - .long sys_timerfd_create - .long sys_eventfd - .long sys_fallocate /* 320 */ - .long sys_timerfd_settime - .long sys_timerfd_gettime - .long sys_signalfd4 - .long sys_eventfd2 - .long sys_epoll_create1 /* 325 */ - .long sys_dup3 - .long sys_pipe2 - .long sys_inotify_init1 - .long sys_preadv - .long sys_pwritev /* 330 */ - .long sys_rt_tgsigqueueinfo - .long sys_perf_event_open - .long sys_get_thread_area - .long sys_set_thread_area - .long sys_atomic_cmpxchg_32 /* 335 */ - .long sys_atomic_barrier - .long sys_fanotify_init - .long sys_fanotify_mark - .long sys_prlimit64 - diff --git a/arch/m68k/kernel/entry_mm.S b/arch/m68k/kernel/entry_mm.S new file mode 100644 index 00000000000..1359ee65957 --- /dev/null +++ b/arch/m68k/kernel/entry_mm.S @@ -0,0 +1,757 @@ +/* -*- mode: asm -*- + * + * linux/arch/m68k/kernel/entry.S + * + * Copyright (C) 1991, 1992 Linus Torvalds + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file README.legal in the main directory of this archive + * for more details. + * + * Linux/m68k support by Hamish Macdonald + * + * 68060 fixes by Jesper Skov + * + */ + +/* + * entry.S contains the system-call and fault low-level handling routines. + * This also contains the timer-interrupt handler, as well as all interrupts + * and faults that can result in a task-switch. + * + * NOTE: This code handles signal-recognition, which happens every time + * after a timer-interrupt and after each system call. + * + */ + +/* + * 12/03/96 Jes: Currently we only support m68k single-cpu systems, so + * all pointers that used to be 'current' are now entry + * number 0 in the 'current_set' list. + * + * 6/05/00 RZ: addedd writeback completion after return from sighandler + * for 68040 + */ + +#include <linux/linkage.h> +#include <asm/entry.h> +#include <asm/errno.h> +#include <asm/setup.h> +#include <asm/segment.h> +#include <asm/traps.h> +#include <asm/unistd.h> + +#include <asm/asm-offsets.h> + +.globl system_call, buserr, trap, resume +.globl sys_call_table +.globl sys_fork, sys_clone, sys_vfork +.globl ret_from_interrupt, bad_interrupt +.globl auto_irqhandler_fixup +.globl user_irqvec_fixup, user_irqhandler_fixup + +.text +ENTRY(buserr) + SAVE_ALL_INT + GET_CURRENT(%d0) + movel %sp,%sp@- | stack frame pointer argument + bsrl buserr_c + addql #4,%sp + jra .Lret_from_exception + +ENTRY(trap) + SAVE_ALL_INT + GET_CURRENT(%d0) + movel %sp,%sp@- | stack frame pointer argument + bsrl trap_c + addql #4,%sp + jra .Lret_from_exception + + | After a fork we jump here directly from resume, + | so that %d1 contains the previous task + | schedule_tail now used regardless of CONFIG_SMP +ENTRY(ret_from_fork) + movel %d1,%sp@- + jsr schedule_tail + addql #4,%sp + jra .Lret_from_exception + +do_trace_entry: + movel #-ENOSYS,%sp@(PT_OFF_D0)| needed for strace + subql #4,%sp + SAVE_SWITCH_STACK + jbsr syscall_trace + RESTORE_SWITCH_STACK + addql #4,%sp + movel %sp@(PT_OFF_ORIG_D0),%d0 + cmpl #NR_syscalls,%d0 + jcs syscall +badsys: + movel #-ENOSYS,%sp@(PT_OFF_D0) + jra ret_from_syscall + +do_trace_exit: + subql #4,%sp + SAVE_SWITCH_STACK + jbsr syscall_trace + RESTORE_SWITCH_STACK + addql #4,%sp + jra .Lret_from_exception + +ENTRY(ret_from_signal) + tstb %curptr@(TASK_INFO+TINFO_FLAGS+2) + jge 1f + jbsr syscall_trace +1: RESTORE_SWITCH_STACK + addql #4,%sp +/* on 68040 complete pending writebacks if any */ +#ifdef CONFIG_M68040 + bfextu %sp@(PT_OFF_FORMATVEC){#0,#4},%d0 + subql #7,%d0 | bus error frame ? + jbne 1f + movel %sp,%sp@- + jbsr berr_040cleanup + addql #4,%sp +1: +#endif + jra .Lret_from_exception + +ENTRY(system_call) + SAVE_ALL_SYS + + GET_CURRENT(%d1) + | save top of frame + movel %sp,%curptr@(TASK_THREAD+THREAD_ESP0) + + | syscall trace? + tstb %curptr@(TASK_INFO+TINFO_FLAGS+2) + jmi do_trace_entry + cmpl #NR_syscalls,%d0 + jcc badsys +syscall: + jbsr @(sys_call_table,%d0:l:4)@(0) + movel %d0,%sp@(PT_OFF_D0) | save the return value +ret_from_syscall: + |oriw #0x0700,%sr + movew %curptr@(TASK_INFO+TINFO_FLAGS+2),%d0 + jne syscall_exit_work +1: RESTORE_ALL + +syscall_exit_work: + btst #5,%sp@(PT_OFF_SR) | check if returning to kernel + bnes 1b | if so, skip resched, signals + lslw #1,%d0 + jcs do_trace_exit + jmi do_delayed_trace + lslw #8,%d0 + jmi do_signal_return + pea resume_userspace + jra schedule + + +ENTRY(ret_from_exception) +.Lret_from_exception: + btst #5,%sp@(PT_OFF_SR) | check if returning to kernel + bnes 1f | if so, skip resched, signals + | only allow interrupts when we are really the last one on the + | kernel stack, otherwise stack overflow can occur during + | heavy interrupt load + andw #ALLOWINT,%sr + +resume_userspace: + moveb %curptr@(TASK_INFO+TINFO_FLAGS+3),%d0 + jne exit_work +1: RESTORE_ALL + +exit_work: + | save top of frame + movel %sp,%curptr@(TASK_THREAD+THREAD_ESP0) + lslb #1,%d0 + jmi do_signal_return + pea resume_userspace + jra schedule + + +do_signal_return: + |andw #ALLOWINT,%sr + subql #4,%sp | dummy return address + SAVE_SWITCH_STACK + pea %sp@(SWITCH_STACK_SIZE) + bsrl do_signal + addql #4,%sp + RESTORE_SWITCH_STACK + addql #4,%sp + jbra resume_userspace + +do_delayed_trace: + bclr #7,%sp@(PT_OFF_SR) | clear trace bit in SR + pea 1 | send SIGTRAP + movel %curptr,%sp@- + pea LSIGTRAP + jbsr send_sig + addql #8,%sp + addql #4,%sp + jbra resume_userspace + + +/* This is the main interrupt handler for autovector interrupts */ + +ENTRY(auto_inthandler) + SAVE_ALL_INT + GET_CURRENT(%d0) + addqb #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1) + | put exception # in d0 + bfextu %sp@(PT_OFF_FORMATVEC){#4,#10},%d0 + subw #VEC_SPUR,%d0 + + movel %sp,%sp@- + movel %d0,%sp@- | put vector # on stack +auto_irqhandler_fixup = . + 2 + jsr __m68k_handle_int | process the IRQ + addql #8,%sp | pop parameters off stack + +ret_from_interrupt: + subqb #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1) + jeq ret_from_last_interrupt +2: RESTORE_ALL + + ALIGN +ret_from_last_interrupt: + moveq #(~ALLOWINT>>8)&0xff,%d0 + andb %sp@(PT_OFF_SR),%d0 + jne 2b + + /* check if we need to do software interrupts */ + tstl irq_stat+CPUSTAT_SOFTIRQ_PENDING + jeq .Lret_from_exception + pea ret_from_exception + jra do_softirq + +/* Handler for user defined interrupt vectors */ + +ENTRY(user_inthandler) + SAVE_ALL_INT + GET_CURRENT(%d0) + addqb #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1) + | put exception # in d0 + bfextu %sp@(PT_OFF_FORMATVEC){#4,#10},%d0 +user_irqvec_fixup = . + 2 + subw #VEC_USER,%d0 + + movel %sp,%sp@- + movel %d0,%sp@- | put vector # on stack +user_irqhandler_fixup = . + 2 + jsr __m68k_handle_int | process the IRQ + addql #8,%sp | pop parameters off stack + + subqb #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1) + jeq ret_from_last_interrupt + RESTORE_ALL + +/* Handler for uninitialized and spurious interrupts */ + +ENTRY(bad_inthandler) + SAVE_ALL_INT + GET_CURRENT(%d0) + addqb #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1) + + movel %sp,%sp@- + jsr handle_badint + addql #4,%sp + + subqb #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1) + jeq ret_from_last_interrupt + RESTORE_ALL + + +ENTRY(sys_fork) + SAVE_SWITCH_STACK + pea %sp@(SWITCH_STACK_SIZE) + jbsr m68k_fork + addql #4,%sp + RESTORE_SWITCH_STACK + rts + +ENTRY(sys_clone) + SAVE_SWITCH_STACK + pea %sp@(SWITCH_STACK_SIZE) + jbsr m68k_clone + addql #4,%sp + RESTORE_SWITCH_STACK + rts + +ENTRY(sys_vfork) + SAVE_SWITCH_STACK + pea %sp@(SWITCH_STACK_SIZE) + jbsr m68k_vfork + addql #4,%sp + RESTORE_SWITCH_STACK + rts + +ENTRY(sys_sigreturn) + SAVE_SWITCH_STACK + jbsr do_sigreturn + RESTORE_SWITCH_STACK + rts + +ENTRY(sys_rt_sigreturn) + SAVE_SWITCH_STACK + jbsr do_rt_sigreturn + RESTORE_SWITCH_STACK + rts + +resume: + /* + * Beware - when entering resume, prev (the current task) is + * in a0, next (the new task) is in a1,so don't change these + * registers until their contents are no longer needed. + */ + + /* save sr */ + movew %sr,%a0@(TASK_THREAD+THREAD_SR) + + /* save fs (sfc,%dfc) (may be pointing to kernel memory) */ + movec %sfc,%d0 + movew %d0,%a0@(TASK_THREAD+THREAD_FS) + + /* save usp */ + /* it is better to use a movel here instead of a movew 8*) */ + movec %usp,%d0 + movel %d0,%a0@(TASK_THREAD+THREAD_USP) + + /* save non-scratch registers on stack */ + SAVE_SWITCH_STACK + + /* save current kernel stack pointer */ + movel %sp,%a0@(TASK_THREAD+THREAD_KSP) + + /* save floating point context */ +#ifndef CONFIG_M68KFPU_EMU_ONLY +#ifdef CONFIG_M68KFPU_EMU + tstl m68k_fputype + jeq 3f +#endif + fsave %a0@(TASK_THREAD+THREAD_FPSTATE) + +#if defined(CONFIG_M68060) +#if !defined(CPU_M68060_ONLY) + btst #3,m68k_cputype+3 + beqs 1f +#endif + /* The 060 FPU keeps status in bits 15-8 of the first longword */ + tstb %a0@(TASK_THREAD+THREAD_FPSTATE+2) + jeq 3f +#if !defined(CPU_M68060_ONLY) + jra 2f +#endif +#endif /* CONFIG_M68060 */ +#if !defined(CPU_M68060_ONLY) +1: tstb %a0@(TASK_THREAD+THREAD_FPSTATE) + jeq 3f +#endif +2: fmovemx %fp0-%fp7,%a0@(TASK_THREAD+THREAD_FPREG) + fmoveml %fpcr/%fpsr/%fpiar,%a0@(TASK_THREAD+THREAD_FPCNTL) +3: +#endif /* CONFIG_M68KFPU_EMU_ONLY */ + /* Return previous task in %d1 */ + movel %curptr,%d1 + + /* switch to new task (a1 contains new task) */ + movel %a1,%curptr + + /* restore floating point context */ +#ifndef CONFIG_M68KFPU_EMU_ONLY +#ifdef CONFIG_M68KFPU_EMU + tstl m68k_fputype + jeq 4f +#endif +#if defined(CONFIG_M68060) +#if !defined(CPU_M68060_ONLY) + btst #3,m68k_cputype+3 + beqs 1f +#endif + /* The 060 FPU keeps status in bits 15-8 of the first longword */ + tstb %a1@(TASK_THREAD+THREAD_FPSTATE+2) + jeq 3f +#if !defined(CPU_M68060_ONLY) + jra 2f +#endif +#endif /* CONFIG_M68060 */ +#if !defined(CPU_M68060_ONLY) +1: tstb %a1@(TASK_THREAD+THREAD_FPSTATE) + jeq 3f +#endif +2: fmovemx %a1@(TASK_THREAD+THREAD_FPREG),%fp0-%fp7 + fmoveml %a1@(TASK_THREAD+THREAD_FPCNTL),%fpcr/%fpsr/%fpiar +3: frestore %a1@(TASK_THREAD+THREAD_FPSTATE) +4: +#endif /* CONFIG_M68KFPU_EMU_ONLY */ + + /* restore the kernel stack pointer */ + movel %a1@(TASK_THREAD+THREAD_KSP),%sp + + /* restore non-scratch registers */ + RESTORE_SWITCH_STACK + + /* restore user stack pointer */ + movel %a1@(TASK_THREAD+THREAD_USP),%a0 + movel %a0,%usp + + /* restore fs (sfc,%dfc) */ + movew %a1@(TASK_THREAD+THREAD_FS),%a0 + movec %a0,%sfc + movec %a0,%dfc + + /* restore status register */ + movew %a1@(TASK_THREAD+THREAD_SR),%sr + + rts + +.data +ALIGN +sys_call_table: + .long sys_restart_syscall /* 0 - old "setup()" system call, used for restarting */ + .long sys_exit + .long sys_fork + .long sys_read + .long sys_write + .long sys_open /* 5 */ + .long sys_close + .long sys_waitpid + .long sys_creat + .long sys_link + .long sys_unlink /* 10 */ + .long sys_execve + .long sys_chdir + .long sys_time + .long sys_mknod + .long sys_chmod /* 15 */ + .long sys_chown16 + .long sys_ni_syscall /* old break syscall holder */ + .long sys_stat + .long sys_lseek + .long sys_getpid /* 20 */ + .long sys_mount + .long sys_oldumount + .long sys_setuid16 + .long sys_getuid16 + .long sys_stime /* 25 */ + .long sys_ptrace + .long sys_alarm + .long sys_fstat + .long sys_pause + .long sys_utime /* 30 */ + .long sys_ni_syscall /* old stty syscall holder */ + .long sys_ni_syscall /* old gtty syscall holder */ + .long sys_access + .long sys_nice + .long sys_ni_syscall /* 35 */ /* old ftime syscall holder */ + .long sys_sync + .long sys_kill + .long sys_rename + .long sys_mkdir + .long sys_rmdir /* 40 */ + .long sys_dup + .long sys_pipe + .long sys_times + .long sys_ni_syscall /* old prof syscall holder */ + .long sys_brk /* 45 */ + .long sys_setgid16 + .long sys_getgid16 + .long sys_signal + .long sys_geteuid16 + .long sys_getegid16 /* 50 */ + .long sys_acct + .long sys_umount /* recycled never used phys() */ + .long sys_ni_syscall /* old lock syscall holder */ + .long sys_ioctl + .long sys_fcntl /* 55 */ + .long sys_ni_syscall /* old mpx syscall holder */ + .long sys_setpgid + .long sys_ni_syscall /* old ulimit syscall holder */ + .long sys_ni_syscall + .long sys_umask /* 60 */ + .long sys_chroot + .long sys_ustat + .long sys_dup2 + .long sys_getppid + .long sys_getpgrp /* 65 */ + .long sys_setsid + .long sys_sigaction + .long sys_sgetmask + .long sys_ssetmask + .long sys_setreuid16 /* 70 */ + .long sys_setregid16 + .long sys_sigsuspend + .long sys_sigpending + .long sys_sethostname + .long sys_setrlimit /* 75 */ + .long sys_old_getrlimit + .long sys_getrusage + .long sys_gettimeofday + .long sys_settimeofday + .long sys_getgroups16 /* 80 */ + .long sys_setgroups16 + .long sys_old_select + .long sys_symlink + .long sys_lstat + .long sys_readlink /* 85 */ + .long sys_uselib + .long sys_swapon + .long sys_reboot + .long sys_old_readdir + .long sys_old_mmap /* 90 */ + .long sys_munmap + .long sys_truncate + .long sys_ftruncate + .long sys_fchmod + .long sys_fchown16 /* 95 */ + .long sys_getpriority + .long sys_setpriority + .long sys_ni_syscall /* old profil syscall holder */ + .long sys_statfs + .long sys_fstatfs /* 100 */ + .long sys_ni_syscall /* ioperm for i386 */ + .long sys_socketcall + .long sys_syslog + .long sys_setitimer + .long sys_getitimer /* 105 */ + .long sys_newstat + .long sys_newlstat + .long sys_newfstat + .long sys_ni_syscall + .long sys_ni_syscall /* 110 */ /* iopl for i386 */ + .long sys_vhangup + .long sys_ni_syscall /* obsolete idle() syscall */ + .long sys_ni_syscall /* vm86old for i386 */ + .long sys_wait4 + .long sys_swapoff /* 115 */ + .long sys_sysinfo + .long sys_ipc + .long sys_fsync + .long sys_sigreturn + .long sys_clone /* 120 */ + .long sys_setdomainname + .long sys_newuname + .long sys_cacheflush /* modify_ldt for i386 */ + .long sys_adjtimex + .long sys_mprotect /* 125 */ + .long sys_sigprocmask + .long sys_ni_syscall /* old "create_module" */ + .long sys_init_module + .long sys_delete_module + .long sys_ni_syscall /* 130 - old "get_kernel_syms" */ + .long sys_quotactl + .long sys_getpgid + .long sys_fchdir + .long sys_bdflush + .long sys_sysfs /* 135 */ + .long sys_personality + .long sys_ni_syscall /* for afs_syscall */ + .long sys_setfsuid16 + .long sys_setfsgid16 + .long sys_llseek /* 140 */ + .long sys_getdents + .long sys_select + .long sys_flock + .long sys_msync + .long sys_readv /* 145 */ + .long sys_writev + .long sys_getsid + .long sys_fdatasync + .long sys_sysctl + .long sys_mlock /* 150 */ + .long sys_munlock + .long sys_mlockall + .long sys_munlockall + .long sys_sched_setparam + .long sys_sched_getparam /* 155 */ + .long sys_sched_setscheduler + .long sys_sched_getscheduler + .long sys_sched_yield + .long sys_sched_get_priority_max + .long sys_sched_get_priority_min /* 160 */ + .long sys_sched_rr_get_interval + .long sys_nanosleep + .long sys_mremap + .long sys_setresuid16 + .long sys_getresuid16 /* 165 */ + .long sys_getpagesize + .long sys_ni_syscall /* old sys_query_module */ + .long sys_poll + .long sys_nfsservctl + .long sys_setresgid16 /* 170 */ + .long sys_getresgid16 + .long sys_prctl + .long sys_rt_sigreturn + .long sys_rt_sigaction + .long sys_rt_sigprocmask /* 175 */ + .long sys_rt_sigpending + .long sys_rt_sigtimedwait + .long sys_rt_sigqueueinfo + .long sys_rt_sigsuspend + .long sys_pread64 /* 180 */ + .long sys_pwrite64 + .long sys_lchown16; + .long sys_getcwd + .long sys_capget + .long sys_capset /* 185 */ + .long sys_sigaltstack + .long sys_sendfile + .long sys_ni_syscall /* streams1 */ + .long sys_ni_syscall /* streams2 */ + .long sys_vfork /* 190 */ + .long sys_getrlimit + .long sys_mmap2 + .long sys_truncate64 + .long sys_ftruncate64 + .long sys_stat64 /* 195 */ + .long sys_lstat64 + .long sys_fstat64 + .long sys_chown + .long sys_getuid + .long sys_getgid /* 200 */ + .long sys_geteuid + .long sys_getegid + .long sys_setreuid + .long sys_setregid + .long sys_getgroups /* 205 */ + .long sys_setgroups + .long sys_fchown + .long sys_setresuid + .long sys_getresuid + .long sys_setresgid /* 210 */ + .long sys_getresgid + .long sys_lchown + .long sys_setuid + .long sys_setgid + .long sys_setfsuid /* 215 */ + .long sys_setfsgid + .long sys_pivot_root + .long sys_ni_syscall + .long sys_ni_syscall + .long sys_getdents64 /* 220 */ + .long sys_gettid + .long sys_tkill + .long sys_setxattr + .long sys_lsetxattr + .long sys_fsetxattr /* 225 */ + .long sys_getxattr + .long sys_lgetxattr + .long sys_fgetxattr + .long sys_listxattr + .long sys_llistxattr /* 230 */ + .long sys_flistxattr + .long sys_removexattr + .long sys_lremovexattr + .long sys_fremovexattr + .long sys_futex /* 235 */ + .long sys_sendfile64 + .long sys_mincore + .long sys_madvise + .long sys_fcntl64 + .long sys_readahead /* 240 */ + .long sys_io_setup + .long sys_io_destroy + .long sys_io_getevents + .long sys_io_submit + .long sys_io_cancel /* 245 */ + .long sys_fadvise64 + .long sys_exit_group + .long sys_lookup_dcookie + .long sys_epoll_create + .long sys_epoll_ctl /* 250 */ + .long sys_epoll_wait + .long sys_remap_file_pages + .long sys_set_tid_address + .long sys_timer_create + .long sys_timer_settime /* 255 */ + .long sys_timer_gettime + .long sys_timer_getoverrun + .long sys_timer_delete + .long sys_clock_settime + .long sys_clock_gettime /* 260 */ + .long sys_clock_getres + .long sys_clock_nanosleep + .long sys_statfs64 + .long sys_fstatfs64 + .long sys_tgkill /* 265 */ + .long sys_utimes + .long sys_fadvise64_64 + .long sys_mbind + .long sys_get_mempolicy + .long sys_set_mempolicy /* 270 */ + .long sys_mq_open + .long sys_mq_unlink + .long sys_mq_timedsend + .long sys_mq_timedreceive + .long sys_mq_notify /* 275 */ + .long sys_mq_getsetattr + .long sys_waitid + .long sys_ni_syscall /* for sys_vserver */ + .long sys_add_key + .long sys_request_key /* 280 */ + .long sys_keyctl + .long sys_ioprio_set + .long sys_ioprio_get + .long sys_inotify_init + .long sys_inotify_add_watch /* 285 */ + .long sys_inotify_rm_watch + .long sys_migrate_pages + .long sys_openat + .long sys_mkdirat + .long sys_mknodat /* 290 */ + .long sys_fchownat + .long sys_futimesat + .long sys_fstatat64 + .long sys_unlinkat + .long sys_renameat /* 295 */ + .long sys_linkat + .long sys_symlinkat + .long sys_readlinkat + .long sys_fchmodat + .long sys_faccessat /* 300 */ + .long sys_ni_syscall /* Reserved for pselect6 */ + .long sys_ni_syscall /* Reserved for ppoll */ + .long sys_unshare + .long sys_set_robust_list + .long sys_get_robust_list /* 305 */ + .long sys_splice + .long sys_sync_file_range + .long sys_tee + .long sys_vmsplice + .long sys_move_pages /* 310 */ + .long sys_sched_setaffinity + .long sys_sched_getaffinity + .long sys_kexec_load + .long sys_getcpu + .long sys_epoll_pwait /* 315 */ + .long sys_utimensat + .long sys_signalfd + .long sys_timerfd_create + .long sys_eventfd + .long sys_fallocate /* 320 */ + .long sys_timerfd_settime + .long sys_timerfd_gettime + .long sys_signalfd4 + .long sys_eventfd2 + .long sys_epoll_create1 /* 325 */ + .long sys_dup3 + .long sys_pipe2 + .long sys_inotify_init1 + .long sys_preadv + .long sys_pwritev /* 330 */ + .long sys_rt_tgsigqueueinfo + .long sys_perf_event_open + .long sys_get_thread_area + .long sys_set_thread_area + .long sys_atomic_cmpxchg_32 /* 335 */ + .long sys_atomic_barrier + .long sys_fanotify_init + .long sys_fanotify_mark + .long sys_prlimit64 + .long sys_name_to_handle_at /* 340 */ + .long sys_open_by_handle_at + .long sys_clock_adjtime + .long sys_syncfs + diff --git a/arch/m68knommu/kernel/entry.S b/arch/m68k/kernel/entry_no.S index 2783f25e38b..2783f25e38b 100644 --- a/arch/m68knommu/kernel/entry.S +++ b/arch/m68k/kernel/entry_no.S diff --git a/arch/m68k/kernel/head.S b/arch/m68k/kernel/head.S index ef54128baa0..27622b3273c 100644 --- a/arch/m68k/kernel/head.S +++ b/arch/m68k/kernel/head.S @@ -134,7 +134,7 @@ * Thanks to a small helping routine enabling the mmu got quite simple * and there is only one way left. mmu_engage makes a complete a new mapping * that only includes the absolute necessary to be able to jump to the final - * postion and to restore the original mapping. + * position and to restore the original mapping. * As this code doesn't need a transparent translation register anymore this * means all registers are free to be used by machines that needs them for * other purposes. @@ -969,7 +969,7 @@ L(mmu_init_amiga): is_not_040_or_060(1f) /* - * 040: Map the 16Meg range physical 0x0 upto logical 0x8000.0000 + * 040: Map the 16Meg range physical 0x0 up to logical 0x8000.0000 */ mmu_map #0x80000000,#0,#0x01000000,#_PAGE_NOCACHE_S /* @@ -982,7 +982,7 @@ L(mmu_init_amiga): 1: /* - * 030: Map the 32Meg range physical 0x0 upto logical 0x8000.0000 + * 030: Map the 32Meg range physical 0x0 up to logical 0x8000.0000 */ mmu_map #0x80000000,#0,#0x02000000,#_PAGE_NOCACHE030 mmu_map_tt #1,#0x40000000,#0x20000000,#_PAGE_NOCACHE030 @@ -1074,7 +1074,7 @@ L(notq40): is_040(1f) /* - * 030: Map the 32Meg range physical 0x0 upto logical 0xf000.0000 + * 030: Map the 32Meg range physical 0x0 up to logical 0xf000.0000 */ mmu_map #0xf0000000,#0,#0x02000000,#_PAGE_NOCACHE030 @@ -1082,7 +1082,7 @@ L(notq40): 1: /* - * 040: Map the 16Meg range physical 0x0 upto logical 0xf000.0000 + * 040: Map the 16Meg range physical 0x0 up to logical 0xf000.0000 */ mmu_map #0xf0000000,#0,#0x01000000,#_PAGE_NOCACHE_S @@ -3078,7 +3078,7 @@ func_start serial_putc,%d0/%d1/%a0/%a1 /* * If the loader gave us a board type then we can use that to * select an appropriate output routine; otherwise we just use - * the Bug code. If we haev to use the Bug that means the Bug + * the Bug code. If we have to use the Bug that means the Bug * workspace has to be valid, which means the Bug has to use * the SRAM, which is non-standard. */ diff --git a/arch/m68knommu/kernel/init_task.c b/arch/m68k/kernel/init_task.c index cbf9dc3cc51..cbf9dc3cc51 100644 --- a/arch/m68knommu/kernel/init_task.c +++ b/arch/m68k/kernel/init_task.c diff --git a/arch/m68knommu/kernel/irq.c b/arch/m68k/kernel/irq.c index c7dd48f37be..15dbc3e9d20 100644 --- a/arch/m68knommu/kernel/irq.c +++ b/arch/m68k/kernel/irq.c @@ -44,7 +44,7 @@ int show_interrupts(struct seq_file *p, void *v) if (ap) { seq_printf(p, "%3d: ", irq); seq_printf(p, "%10u ", kstat_irqs(irq)); - seq_printf(p, "%14s ", get_irq_desc_chip(desc)->name); + seq_printf(p, "%14s ", irq_desc_get_chip(desc)->name); seq_printf(p, "%s", ap->name); for (ap = ap->next; ap; ap = ap->next) diff --git a/arch/m68k/kernel/m68k_ksyms.c b/arch/m68k/kernel/m68k_ksyms.c index d900e77e536..4752c28ce0a 100644 --- a/arch/m68k/kernel/m68k_ksyms.c +++ b/arch/m68k/kernel/m68k_ksyms.c @@ -1,16 +1,5 @@ -#include <linux/module.h> - -asmlinkage long long __ashldi3 (long long, int); -asmlinkage long long __ashrdi3 (long long, int); -asmlinkage long long __lshrdi3 (long long, int); -asmlinkage long long __muldi3 (long long, long long); - -/* The following are special because they're not called - explicitly (the C compiler generates them). Fortunately, - their interface isn't gonna change any time soon now, so - it's OK to leave it out of version control. */ -EXPORT_SYMBOL(__ashldi3); -EXPORT_SYMBOL(__ashrdi3); -EXPORT_SYMBOL(__lshrdi3); -EXPORT_SYMBOL(__muldi3); - +#ifdef CONFIG_MMU +#include "m68k_ksyms_mm.c" +#else +#include "m68k_ksyms_no.c" +#endif diff --git a/arch/m68k/kernel/m68k_ksyms_mm.c b/arch/m68k/kernel/m68k_ksyms_mm.c new file mode 100644 index 00000000000..d900e77e536 --- /dev/null +++ b/arch/m68k/kernel/m68k_ksyms_mm.c @@ -0,0 +1,16 @@ +#include <linux/module.h> + +asmlinkage long long __ashldi3 (long long, int); +asmlinkage long long __ashrdi3 (long long, int); +asmlinkage long long __lshrdi3 (long long, int); +asmlinkage long long __muldi3 (long long, long long); + +/* The following are special because they're not called + explicitly (the C compiler generates them). Fortunately, + their interface isn't gonna change any time soon now, so + it's OK to leave it out of version control. */ +EXPORT_SYMBOL(__ashldi3); +EXPORT_SYMBOL(__ashrdi3); +EXPORT_SYMBOL(__lshrdi3); +EXPORT_SYMBOL(__muldi3); + diff --git a/arch/m68knommu/kernel/m68k_ksyms.c b/arch/m68k/kernel/m68k_ksyms_no.c index 39fe0a7aec3..39fe0a7aec3 100644 --- a/arch/m68knommu/kernel/m68k_ksyms.c +++ b/arch/m68k/kernel/m68k_ksyms_no.c diff --git a/arch/m68k/kernel/module.c b/arch/m68k/kernel/module.c index cd6bcb1c957..7ea203ce6b1 100644 --- a/arch/m68k/kernel/module.c +++ b/arch/m68k/kernel/module.c @@ -1,155 +1,5 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include <linux/moduleloader.h> -#include <linux/elf.h> -#include <linux/vmalloc.h> -#include <linux/fs.h> -#include <linux/string.h> -#include <linux/kernel.h> - -#if 0 -#define DEBUGP printk +#ifdef CONFIG_MMU +#include "module_mm.c" #else -#define DEBUGP(fmt...) +#include "module_no.c" #endif - -#ifdef CONFIG_MODULES - -void *module_alloc(unsigned long size) -{ - if (size == 0) - return NULL; - return vmalloc(size); -} - - -/* Free memory returned from module_alloc */ -void module_free(struct module *mod, void *module_region) -{ - vfree(module_region); -} - -/* We don't need anything special. */ -int module_frob_arch_sections(Elf_Ehdr *hdr, - Elf_Shdr *sechdrs, - char *secstrings, - struct module *mod) -{ - return 0; -} - -int apply_relocate(Elf32_Shdr *sechdrs, - const char *strtab, - unsigned int symindex, - unsigned int relsec, - struct module *me) -{ - unsigned int i; - Elf32_Rel *rel = (void *)sechdrs[relsec].sh_addr; - Elf32_Sym *sym; - uint32_t *location; - - DEBUGP("Applying relocate section %u to %u\n", relsec, - sechdrs[relsec].sh_info); - for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { - /* This is where to make the change */ - location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr - + rel[i].r_offset; - /* This is the symbol it is referring to. Note that all - undefined symbols have been resolved. */ - sym = (Elf32_Sym *)sechdrs[symindex].sh_addr - + ELF32_R_SYM(rel[i].r_info); - - switch (ELF32_R_TYPE(rel[i].r_info)) { - case R_68K_32: - /* We add the value into the location given */ - *location += sym->st_value; - break; - case R_68K_PC32: - /* Add the value, subtract its postition */ - *location += sym->st_value - (uint32_t)location; - break; - default: - printk(KERN_ERR "module %s: Unknown relocation: %u\n", - me->name, ELF32_R_TYPE(rel[i].r_info)); - return -ENOEXEC; - } - } - return 0; -} - -int apply_relocate_add(Elf32_Shdr *sechdrs, - const char *strtab, - unsigned int symindex, - unsigned int relsec, - struct module *me) -{ - unsigned int i; - Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr; - Elf32_Sym *sym; - uint32_t *location; - - DEBUGP("Applying relocate_add section %u to %u\n", relsec, - sechdrs[relsec].sh_info); - for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { - /* This is where to make the change */ - location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr - + rel[i].r_offset; - /* This is the symbol it is referring to. Note that all - undefined symbols have been resolved. */ - sym = (Elf32_Sym *)sechdrs[symindex].sh_addr - + ELF32_R_SYM(rel[i].r_info); - - switch (ELF32_R_TYPE(rel[i].r_info)) { - case R_68K_32: - /* We add the value into the location given */ - *location = rel[i].r_addend + sym->st_value; - break; - case R_68K_PC32: - /* Add the value, subtract its postition */ - *location = rel[i].r_addend + sym->st_value - (uint32_t)location; - break; - default: - printk(KERN_ERR "module %s: Unknown relocation: %u\n", - me->name, ELF32_R_TYPE(rel[i].r_info)); - return -ENOEXEC; - } - } - return 0; -} - -int module_finalize(const Elf_Ehdr *hdr, - const Elf_Shdr *sechdrs, - struct module *mod) -{ - module_fixup(mod, mod->arch.fixup_start, mod->arch.fixup_end); - - return 0; -} - -void module_arch_cleanup(struct module *mod) -{ -} - -#endif /* CONFIG_MODULES */ - -void module_fixup(struct module *mod, struct m68k_fixup_info *start, - struct m68k_fixup_info *end) -{ - struct m68k_fixup_info *fixup; - - for (fixup = start; fixup < end; fixup++) { - switch (fixup->type) { - case m68k_fixup_memoffset: - *(u32 *)fixup->addr = m68k_memoffset; - break; - case m68k_fixup_vnode_shift: - *(u16 *)fixup->addr += m68k_virt_to_node_shift; - break; - } - } -} diff --git a/arch/m68k/kernel/module_mm.c b/arch/m68k/kernel/module_mm.c new file mode 100644 index 00000000000..cd6bcb1c957 --- /dev/null +++ b/arch/m68k/kernel/module_mm.c @@ -0,0 +1,155 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include <linux/moduleloader.h> +#include <linux/elf.h> +#include <linux/vmalloc.h> +#include <linux/fs.h> +#include <linux/string.h> +#include <linux/kernel.h> + +#if 0 +#define DEBUGP printk +#else +#define DEBUGP(fmt...) +#endif + +#ifdef CONFIG_MODULES + +void *module_alloc(unsigned long size) +{ + if (size == 0) + return NULL; + return vmalloc(size); +} + + +/* Free memory returned from module_alloc */ +void module_free(struct module *mod, void *module_region) +{ + vfree(module_region); +} + +/* We don't need anything special. */ +int module_frob_arch_sections(Elf_Ehdr *hdr, + Elf_Shdr *sechdrs, + char *secstrings, + struct module *mod) +{ + return 0; +} + +int apply_relocate(Elf32_Shdr *sechdrs, + const char *strtab, + unsigned int symindex, + unsigned int relsec, + struct module *me) +{ + unsigned int i; + Elf32_Rel *rel = (void *)sechdrs[relsec].sh_addr; + Elf32_Sym *sym; + uint32_t *location; + + DEBUGP("Applying relocate section %u to %u\n", relsec, + sechdrs[relsec].sh_info); + for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { + /* This is where to make the change */ + location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr + + rel[i].r_offset; + /* This is the symbol it is referring to. Note that all + undefined symbols have been resolved. */ + sym = (Elf32_Sym *)sechdrs[symindex].sh_addr + + ELF32_R_SYM(rel[i].r_info); + + switch (ELF32_R_TYPE(rel[i].r_info)) { + case R_68K_32: + /* We add the value into the location given */ + *location += sym->st_value; + break; + case R_68K_PC32: + /* Add the value, subtract its postition */ + *location += sym->st_value - (uint32_t)location; + break; + default: + printk(KERN_ERR "module %s: Unknown relocation: %u\n", + me->name, ELF32_R_TYPE(rel[i].r_info)); + return -ENOEXEC; + } + } + return 0; +} + +int apply_relocate_add(Elf32_Shdr *sechdrs, + const char *strtab, + unsigned int symindex, + unsigned int relsec, + struct module *me) +{ + unsigned int i; + Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr; + Elf32_Sym *sym; + uint32_t *location; + + DEBUGP("Applying relocate_add section %u to %u\n", relsec, + sechdrs[relsec].sh_info); + for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { + /* This is where to make the change */ + location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr + + rel[i].r_offset; + /* This is the symbol it is referring to. Note that all + undefined symbols have been resolved. */ + sym = (Elf32_Sym *)sechdrs[symindex].sh_addr + + ELF32_R_SYM(rel[i].r_info); + + switch (ELF32_R_TYPE(rel[i].r_info)) { + case R_68K_32: + /* We add the value into the location given */ + *location = rel[i].r_addend + sym->st_value; + break; + case R_68K_PC32: + /* Add the value, subtract its postition */ + *location = rel[i].r_addend + sym->st_value - (uint32_t)location; + break; + default: + printk(KERN_ERR "module %s: Unknown relocation: %u\n", + me->name, ELF32_R_TYPE(rel[i].r_info)); + return -ENOEXEC; + } + } + return 0; +} + +int module_finalize(const Elf_Ehdr *hdr, + const Elf_Shdr *sechdrs, + struct module *mod) +{ + module_fixup(mod, mod->arch.fixup_start, mod->arch.fixup_end); + + return 0; +} + +void module_arch_cleanup(struct module *mod) +{ +} + +#endif /* CONFIG_MODULES */ + +void module_fixup(struct module *mod, struct m68k_fixup_info *start, + struct m68k_fixup_info *end) +{ + struct m68k_fixup_info *fixup; + + for (fixup = start; fixup < end; fixup++) { + switch (fixup->type) { + case m68k_fixup_memoffset: + *(u32 *)fixup->addr = m68k_memoffset; + break; + case m68k_fixup_vnode_shift: + *(u16 *)fixup->addr += m68k_virt_to_node_shift; + break; + } + } +} diff --git a/arch/m68knommu/kernel/module.c b/arch/m68k/kernel/module_no.c index d11ffae7956..d11ffae7956 100644 --- a/arch/m68knommu/kernel/module.c +++ b/arch/m68k/kernel/module_no.c diff --git a/arch/m68k/kernel/process.c b/arch/m68k/kernel/process.c index c2a1fc23dd7..6cf4bd6e34f 100644 --- a/arch/m68k/kernel/process.c +++ b/arch/m68k/kernel/process.c @@ -1,354 +1,5 @@ -/* - * linux/arch/m68k/kernel/process.c - * - * Copyright (C) 1995 Hamish Macdonald - * - * 68060 fixes by Jesper Skov - */ - -/* - * This file handles the architecture-dependent parts of process handling.. - */ - -#include <linux/errno.h> -#include <linux/module.h> -#include <linux/sched.h> -#include <linux/kernel.h> -#include <linux/mm.h> -#include <linux/slab.h> -#include <linux/fs.h> -#include <linux/smp.h> -#include <linux/stddef.h> -#include <linux/unistd.h> -#include <linux/ptrace.h> -#include <linux/user.h> -#include <linux/reboot.h> -#include <linux/init_task.h> -#include <linux/mqueue.h> - -#include <asm/uaccess.h> -#include <asm/system.h> -#include <asm/traps.h> -#include <asm/machdep.h> -#include <asm/setup.h> -#include <asm/pgtable.h> - -/* - * Initial task/thread structure. Make this a per-architecture thing, - * because different architectures tend to have different - * alignment requirements and potentially different initial - * setup. - */ -static struct signal_struct init_signals = INIT_SIGNALS(init_signals); -static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); -union thread_union init_thread_union __init_task_data - __attribute__((aligned(THREAD_SIZE))) = - { INIT_THREAD_INFO(init_task) }; - -/* initial task structure */ -struct task_struct init_task = INIT_TASK(init_task); - -EXPORT_SYMBOL(init_task); - -asmlinkage void ret_from_fork(void); - - -/* - * Return saved PC from a blocked thread - */ -unsigned long thread_saved_pc(struct task_struct *tsk) -{ - struct switch_stack *sw = (struct switch_stack *)tsk->thread.ksp; - /* Check whether the thread is blocked in resume() */ - if (in_sched_functions(sw->retpc)) - return ((unsigned long *)sw->a6)[1]; - else - return sw->retpc; -} - -/* - * The idle loop on an m68k.. - */ -static void default_idle(void) -{ - if (!need_resched()) -#if defined(MACH_ATARI_ONLY) - /* block out HSYNC on the atari (falcon) */ - __asm__("stop #0x2200" : : : "cc"); +#ifdef CONFIG_MMU +#include "process_mm.c" #else - __asm__("stop #0x2000" : : : "cc"); +#include "process_no.c" #endif -} - -void (*idle)(void) = default_idle; - -/* - * The idle thread. There's no useful work to be - * done, so just try to conserve power and have a - * low exit latency (ie sit in a loop waiting for - * somebody to say that they'd like to reschedule) - */ -void cpu_idle(void) -{ - /* endless idle loop with no priority at all */ - while (1) { - while (!need_resched()) - idle(); - preempt_enable_no_resched(); - schedule(); - preempt_disable(); - } -} - -void machine_restart(char * __unused) -{ - if (mach_reset) - mach_reset(); - for (;;); -} - -void machine_halt(void) -{ - if (mach_halt) - mach_halt(); - for (;;); -} - -void machine_power_off(void) -{ - if (mach_power_off) - mach_power_off(); - for (;;); -} - -void (*pm_power_off)(void) = machine_power_off; -EXPORT_SYMBOL(pm_power_off); - -void show_regs(struct pt_regs * regs) -{ - printk("\n"); - printk("Format %02x Vector: %04x PC: %08lx Status: %04x %s\n", - regs->format, regs->vector, regs->pc, regs->sr, print_tainted()); - printk("ORIG_D0: %08lx D0: %08lx A2: %08lx A1: %08lx\n", - regs->orig_d0, regs->d0, regs->a2, regs->a1); - printk("A0: %08lx D5: %08lx D4: %08lx\n", - regs->a0, regs->d5, regs->d4); - printk("D3: %08lx D2: %08lx D1: %08lx\n", - regs->d3, regs->d2, regs->d1); - if (!(regs->sr & PS_S)) - printk("USP: %08lx\n", rdusp()); -} - -/* - * Create a kernel thread - */ -int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags) -{ - int pid; - mm_segment_t fs; - - fs = get_fs(); - set_fs (KERNEL_DS); - - { - register long retval __asm__ ("d0"); - register long clone_arg __asm__ ("d1") = flags | CLONE_VM | CLONE_UNTRACED; - - retval = __NR_clone; - __asm__ __volatile__ - ("clrl %%d2\n\t" - "trap #0\n\t" /* Linux/m68k system call */ - "tstl %0\n\t" /* child or parent */ - "jne 1f\n\t" /* parent - jump */ - "lea %%sp@(%c7),%6\n\t" /* reload current */ - "movel %6@,%6\n\t" - "movel %3,%%sp@-\n\t" /* push argument */ - "jsr %4@\n\t" /* call fn */ - "movel %0,%%d1\n\t" /* pass exit value */ - "movel %2,%%d0\n\t" /* exit */ - "trap #0\n" - "1:" - : "+d" (retval) - : "i" (__NR_clone), "i" (__NR_exit), - "r" (arg), "a" (fn), "d" (clone_arg), "r" (current), - "i" (-THREAD_SIZE) - : "d2"); - - pid = retval; - } - - set_fs (fs); - return pid; -} -EXPORT_SYMBOL(kernel_thread); - -void flush_thread(void) -{ - unsigned long zero = 0; - set_fs(USER_DS); - current->thread.fs = __USER_DS; - if (!FPU_IS_EMU) - asm volatile (".chip 68k/68881\n\t" - "frestore %0@\n\t" - ".chip 68k" : : "a" (&zero)); -} - -/* - * "m68k_fork()".. By the time we get here, the - * non-volatile registers have also been saved on the - * stack. We do some ugly pointer stuff here.. (see - * also copy_thread) - */ - -asmlinkage int m68k_fork(struct pt_regs *regs) -{ - return do_fork(SIGCHLD, rdusp(), regs, 0, NULL, NULL); -} - -asmlinkage int m68k_vfork(struct pt_regs *regs) -{ - return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, rdusp(), regs, 0, - NULL, NULL); -} - -asmlinkage int m68k_clone(struct pt_regs *regs) -{ - unsigned long clone_flags; - unsigned long newsp; - int __user *parent_tidptr, *child_tidptr; - - /* syscall2 puts clone_flags in d1 and usp in d2 */ - clone_flags = regs->d1; - newsp = regs->d2; - parent_tidptr = (int __user *)regs->d3; - child_tidptr = (int __user *)regs->d4; - if (!newsp) - newsp = rdusp(); - return do_fork(clone_flags, newsp, regs, 0, - parent_tidptr, child_tidptr); -} - -int copy_thread(unsigned long clone_flags, unsigned long usp, - unsigned long unused, - struct task_struct * p, struct pt_regs * regs) -{ - struct pt_regs * childregs; - struct switch_stack * childstack, *stack; - unsigned long *retp; - - childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1; - - *childregs = *regs; - childregs->d0 = 0; - - retp = ((unsigned long *) regs); - stack = ((struct switch_stack *) retp) - 1; - - childstack = ((struct switch_stack *) childregs) - 1; - *childstack = *stack; - childstack->retpc = (unsigned long)ret_from_fork; - - p->thread.usp = usp; - p->thread.ksp = (unsigned long)childstack; - - if (clone_flags & CLONE_SETTLS) - task_thread_info(p)->tp_value = regs->d5; - - /* - * Must save the current SFC/DFC value, NOT the value when - * the parent was last descheduled - RGH 10-08-96 - */ - p->thread.fs = get_fs().seg; - - if (!FPU_IS_EMU) { - /* Copy the current fpu state */ - asm volatile ("fsave %0" : : "m" (p->thread.fpstate[0]) : "memory"); - - if (!CPU_IS_060 ? p->thread.fpstate[0] : p->thread.fpstate[2]) - asm volatile ("fmovemx %/fp0-%/fp7,%0\n\t" - "fmoveml %/fpiar/%/fpcr/%/fpsr,%1" - : : "m" (p->thread.fp[0]), "m" (p->thread.fpcntl[0]) - : "memory"); - /* Restore the state in case the fpu was busy */ - asm volatile ("frestore %0" : : "m" (p->thread.fpstate[0])); - } - - return 0; -} - -/* Fill in the fpu structure for a core dump. */ - -int dump_fpu (struct pt_regs *regs, struct user_m68kfp_struct *fpu) -{ - char fpustate[216]; - - if (FPU_IS_EMU) { - int i; - - memcpy(fpu->fpcntl, current->thread.fpcntl, 12); - memcpy(fpu->fpregs, current->thread.fp, 96); - /* Convert internal fpu reg representation - * into long double format - */ - for (i = 0; i < 24; i += 3) - fpu->fpregs[i] = ((fpu->fpregs[i] & 0xffff0000) << 15) | - ((fpu->fpregs[i] & 0x0000ffff) << 16); - return 1; - } - - /* First dump the fpu context to avoid protocol violation. */ - asm volatile ("fsave %0" :: "m" (fpustate[0]) : "memory"); - if (!CPU_IS_060 ? !fpustate[0] : !fpustate[2]) - return 0; - - asm volatile ("fmovem %/fpiar/%/fpcr/%/fpsr,%0" - :: "m" (fpu->fpcntl[0]) - : "memory"); - asm volatile ("fmovemx %/fp0-%/fp7,%0" - :: "m" (fpu->fpregs[0]) - : "memory"); - return 1; -} -EXPORT_SYMBOL(dump_fpu); - -/* - * sys_execve() executes a new program. - */ -asmlinkage int sys_execve(const char __user *name, - const char __user *const __user *argv, - const char __user *const __user *envp) -{ - int error; - char * filename; - struct pt_regs *regs = (struct pt_regs *) &name; - - filename = getname(name); - error = PTR_ERR(filename); - if (IS_ERR(filename)) - return error; - error = do_execve(filename, argv, envp, regs); - putname(filename); - return error; -} - -unsigned long get_wchan(struct task_struct *p) -{ - unsigned long fp, pc; - unsigned long stack_page; - int count = 0; - if (!p || p == current || p->state == TASK_RUNNING) - return 0; - - stack_page = (unsigned long)task_stack_page(p); - fp = ((struct switch_stack *)p->thread.ksp)->a6; - do { - if (fp < stack_page+sizeof(struct thread_info) || - fp >= 8184+stack_page) - return 0; - pc = ((unsigned long *)fp)[1]; - if (!in_sched_functions(pc)) - return pc; - fp = *(unsigned long *) fp; - } while (count++ < 16); - return 0; -} diff --git a/arch/m68k/kernel/process_mm.c b/arch/m68k/kernel/process_mm.c new file mode 100644 index 00000000000..c2a1fc23dd7 --- /dev/null +++ b/arch/m68k/kernel/process_mm.c @@ -0,0 +1,354 @@ +/* + * linux/arch/m68k/kernel/process.c + * + * Copyright (C) 1995 Hamish Macdonald + * + * 68060 fixes by Jesper Skov + */ + +/* + * This file handles the architecture-dependent parts of process handling.. + */ + +#include <linux/errno.h> +#include <linux/module.h> +#include <linux/sched.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/slab.h> +#include <linux/fs.h> +#include <linux/smp.h> +#include <linux/stddef.h> +#include <linux/unistd.h> +#include <linux/ptrace.h> +#include <linux/user.h> +#include <linux/reboot.h> +#include <linux/init_task.h> +#include <linux/mqueue.h> + +#include <asm/uaccess.h> +#include <asm/system.h> +#include <asm/traps.h> +#include <asm/machdep.h> +#include <asm/setup.h> +#include <asm/pgtable.h> + +/* + * Initial task/thread structure. Make this a per-architecture thing, + * because different architectures tend to have different + * alignment requirements and potentially different initial + * setup. + */ +static struct signal_struct init_signals = INIT_SIGNALS(init_signals); +static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); +union thread_union init_thread_union __init_task_data + __attribute__((aligned(THREAD_SIZE))) = + { INIT_THREAD_INFO(init_task) }; + +/* initial task structure */ +struct task_struct init_task = INIT_TASK(init_task); + +EXPORT_SYMBOL(init_task); + +asmlinkage void ret_from_fork(void); + + +/* + * Return saved PC from a blocked thread + */ +unsigned long thread_saved_pc(struct task_struct *tsk) +{ + struct switch_stack *sw = (struct switch_stack *)tsk->thread.ksp; + /* Check whether the thread is blocked in resume() */ + if (in_sched_functions(sw->retpc)) + return ((unsigned long *)sw->a6)[1]; + else + return sw->retpc; +} + +/* + * The idle loop on an m68k.. + */ +static void default_idle(void) +{ + if (!need_resched()) +#if defined(MACH_ATARI_ONLY) + /* block out HSYNC on the atari (falcon) */ + __asm__("stop #0x2200" : : : "cc"); +#else + __asm__("stop #0x2000" : : : "cc"); +#endif +} + +void (*idle)(void) = default_idle; + +/* + * The idle thread. There's no useful work to be + * done, so just try to conserve power and have a + * low exit latency (ie sit in a loop waiting for + * somebody to say that they'd like to reschedule) + */ +void cpu_idle(void) +{ + /* endless idle loop with no priority at all */ + while (1) { + while (!need_resched()) + idle(); + preempt_enable_no_resched(); + schedule(); + preempt_disable(); + } +} + +void machine_restart(char * __unused) +{ + if (mach_reset) + mach_reset(); + for (;;); +} + +void machine_halt(void) +{ + if (mach_halt) + mach_halt(); + for (;;); +} + +void machine_power_off(void) +{ + if (mach_power_off) + mach_power_off(); + for (;;); +} + +void (*pm_power_off)(void) = machine_power_off; +EXPORT_SYMBOL(pm_power_off); + +void show_regs(struct pt_regs * regs) +{ + printk("\n"); + printk("Format %02x Vector: %04x PC: %08lx Status: %04x %s\n", + regs->format, regs->vector, regs->pc, regs->sr, print_tainted()); + printk("ORIG_D0: %08lx D0: %08lx A2: %08lx A1: %08lx\n", + regs->orig_d0, regs->d0, regs->a2, regs->a1); + printk("A0: %08lx D5: %08lx D4: %08lx\n", + regs->a0, regs->d5, regs->d4); + printk("D3: %08lx D2: %08lx D1: %08lx\n", + regs->d3, regs->d2, regs->d1); + if (!(regs->sr & PS_S)) + printk("USP: %08lx\n", rdusp()); +} + +/* + * Create a kernel thread + */ +int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags) +{ + int pid; + mm_segment_t fs; + + fs = get_fs(); + set_fs (KERNEL_DS); + + { + register long retval __asm__ ("d0"); + register long clone_arg __asm__ ("d1") = flags | CLONE_VM | CLONE_UNTRACED; + + retval = __NR_clone; + __asm__ __volatile__ + ("clrl %%d2\n\t" + "trap #0\n\t" /* Linux/m68k system call */ + "tstl %0\n\t" /* child or parent */ + "jne 1f\n\t" /* parent - jump */ + "lea %%sp@(%c7),%6\n\t" /* reload current */ + "movel %6@,%6\n\t" + "movel %3,%%sp@-\n\t" /* push argument */ + "jsr %4@\n\t" /* call fn */ + "movel %0,%%d1\n\t" /* pass exit value */ + "movel %2,%%d0\n\t" /* exit */ + "trap #0\n" + "1:" + : "+d" (retval) + : "i" (__NR_clone), "i" (__NR_exit), + "r" (arg), "a" (fn), "d" (clone_arg), "r" (current), + "i" (-THREAD_SIZE) + : "d2"); + + pid = retval; + } + + set_fs (fs); + return pid; +} +EXPORT_SYMBOL(kernel_thread); + +void flush_thread(void) +{ + unsigned long zero = 0; + set_fs(USER_DS); + current->thread.fs = __USER_DS; + if (!FPU_IS_EMU) + asm volatile (".chip 68k/68881\n\t" + "frestore %0@\n\t" + ".chip 68k" : : "a" (&zero)); +} + +/* + * "m68k_fork()".. By the time we get here, the + * non-volatile registers have also been saved on the + * stack. We do some ugly pointer stuff here.. (see + * also copy_thread) + */ + +asmlinkage int m68k_fork(struct pt_regs *regs) +{ + return do_fork(SIGCHLD, rdusp(), regs, 0, NULL, NULL); +} + +asmlinkage int m68k_vfork(struct pt_regs *regs) +{ + return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, rdusp(), regs, 0, + NULL, NULL); +} + +asmlinkage int m68k_clone(struct pt_regs *regs) +{ + unsigned long clone_flags; + unsigned long newsp; + int __user *parent_tidptr, *child_tidptr; + + /* syscall2 puts clone_flags in d1 and usp in d2 */ + clone_flags = regs->d1; + newsp = regs->d2; + parent_tidptr = (int __user *)regs->d3; + child_tidptr = (int __user *)regs->d4; + if (!newsp) + newsp = rdusp(); + return do_fork(clone_flags, newsp, regs, 0, + parent_tidptr, child_tidptr); +} + +int copy_thread(unsigned long clone_flags, unsigned long usp, + unsigned long unused, + struct task_struct * p, struct pt_regs * regs) +{ + struct pt_regs * childregs; + struct switch_stack * childstack, *stack; + unsigned long *retp; + + childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1; + + *childregs = *regs; + childregs->d0 = 0; + + retp = ((unsigned long *) regs); + stack = ((struct switch_stack *) retp) - 1; + + childstack = ((struct switch_stack *) childregs) - 1; + *childstack = *stack; + childstack->retpc = (unsigned long)ret_from_fork; + + p->thread.usp = usp; + p->thread.ksp = (unsigned long)childstack; + + if (clone_flags & CLONE_SETTLS) + task_thread_info(p)->tp_value = regs->d5; + + /* + * Must save the current SFC/DFC value, NOT the value when + * the parent was last descheduled - RGH 10-08-96 + */ + p->thread.fs = get_fs().seg; + + if (!FPU_IS_EMU) { + /* Copy the current fpu state */ + asm volatile ("fsave %0" : : "m" (p->thread.fpstate[0]) : "memory"); + + if (!CPU_IS_060 ? p->thread.fpstate[0] : p->thread.fpstate[2]) + asm volatile ("fmovemx %/fp0-%/fp7,%0\n\t" + "fmoveml %/fpiar/%/fpcr/%/fpsr,%1" + : : "m" (p->thread.fp[0]), "m" (p->thread.fpcntl[0]) + : "memory"); + /* Restore the state in case the fpu was busy */ + asm volatile ("frestore %0" : : "m" (p->thread.fpstate[0])); + } + + return 0; +} + +/* Fill in the fpu structure for a core dump. */ + +int dump_fpu (struct pt_regs *regs, struct user_m68kfp_struct *fpu) +{ + char fpustate[216]; + + if (FPU_IS_EMU) { + int i; + + memcpy(fpu->fpcntl, current->thread.fpcntl, 12); + memcpy(fpu->fpregs, current->thread.fp, 96); + /* Convert internal fpu reg representation + * into long double format + */ + for (i = 0; i < 24; i += 3) + fpu->fpregs[i] = ((fpu->fpregs[i] & 0xffff0000) << 15) | + ((fpu->fpregs[i] & 0x0000ffff) << 16); + return 1; + } + + /* First dump the fpu context to avoid protocol violation. */ + asm volatile ("fsave %0" :: "m" (fpustate[0]) : "memory"); + if (!CPU_IS_060 ? !fpustate[0] : !fpustate[2]) + return 0; + + asm volatile ("fmovem %/fpiar/%/fpcr/%/fpsr,%0" + :: "m" (fpu->fpcntl[0]) + : "memory"); + asm volatile ("fmovemx %/fp0-%/fp7,%0" + :: "m" (fpu->fpregs[0]) + : "memory"); + return 1; +} +EXPORT_SYMBOL(dump_fpu); + +/* + * sys_execve() executes a new program. + */ +asmlinkage int sys_execve(const char __user *name, + const char __user *const __user *argv, + const char __user *const __user *envp) +{ + int error; + char * filename; + struct pt_regs *regs = (struct pt_regs *) &name; + + filename = getname(name); + error = PTR_ERR(filename); + if (IS_ERR(filename)) + return error; + error = do_execve(filename, argv, envp, regs); + putname(filename); + return error; +} + +unsigned long get_wchan(struct task_struct *p) +{ + unsigned long fp, pc; + unsigned long stack_page; + int count = 0; + if (!p || p == current || p->state == TASK_RUNNING) + return 0; + + stack_page = (unsigned long)task_stack_page(p); + fp = ((struct switch_stack *)p->thread.ksp)->a6; + do { + if (fp < stack_page+sizeof(struct thread_info) || + fp >= 8184+stack_page) + return 0; + pc = ((unsigned long *)fp)[1]; + if (!in_sched_functions(pc)) + return pc; + fp = *(unsigned long *) fp; + } while (count++ < 16); + return 0; +} diff --git a/arch/m68knommu/kernel/process.c b/arch/m68k/kernel/process_no.c index e2a63af5d51..e2a63af5d51 100644 --- a/arch/m68knommu/kernel/process.c +++ b/arch/m68k/kernel/process_no.c diff --git a/arch/m68k/kernel/ptrace.c b/arch/m68k/kernel/ptrace.c index 0b252683cef..07a417550e9 100644 --- a/arch/m68k/kernel/ptrace.c +++ b/arch/m68k/kernel/ptrace.c @@ -1,277 +1,5 @@ -/* - * linux/arch/m68k/kernel/ptrace.c - * - * Copyright (C) 1994 by Hamish Macdonald - * Taken from linux/kernel/ptrace.c and modified for M680x0. - * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds - * - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file COPYING in the main directory of - * this archive for more details. - */ - -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/mm.h> -#include <linux/smp.h> -#include <linux/errno.h> -#include <linux/ptrace.h> -#include <linux/user.h> -#include <linux/signal.h> - -#include <asm/uaccess.h> -#include <asm/page.h> -#include <asm/pgtable.h> -#include <asm/system.h> -#include <asm/processor.h> - -/* - * does not yet catch signals sent when the child dies. - * in exit.c or in signal.c. - */ - -/* determines which bits in the SR the user has access to. */ -/* 1 = access 0 = no access */ -#define SR_MASK 0x001f - -/* sets the trace bits. */ -#define TRACE_BITS 0xC000 -#define T1_BIT 0x8000 -#define T0_BIT 0x4000 - -/* Find the stack offset for a register, relative to thread.esp0. */ -#define PT_REG(reg) ((long)&((struct pt_regs *)0)->reg) -#define SW_REG(reg) ((long)&((struct switch_stack *)0)->reg \ - - sizeof(struct switch_stack)) -/* Mapping from PT_xxx to the stack offset at which the register is - saved. Notice that usp has no stack-slot and needs to be treated - specially (see get_reg/put_reg below). */ -static const int regoff[] = { - [0] = PT_REG(d1), - [1] = PT_REG(d2), - [2] = PT_REG(d3), - [3] = PT_REG(d4), - [4] = PT_REG(d5), - [5] = SW_REG(d6), - [6] = SW_REG(d7), - [7] = PT_REG(a0), - [8] = PT_REG(a1), - [9] = PT_REG(a2), - [10] = SW_REG(a3), - [11] = SW_REG(a4), - [12] = SW_REG(a5), - [13] = SW_REG(a6), - [14] = PT_REG(d0), - [15] = -1, - [16] = PT_REG(orig_d0), - [17] = PT_REG(sr), - [18] = PT_REG(pc), -}; - -/* - * Get contents of register REGNO in task TASK. - */ -static inline long get_reg(struct task_struct *task, int regno) -{ - unsigned long *addr; - - if (regno == PT_USP) - addr = &task->thread.usp; - else if (regno < ARRAY_SIZE(regoff)) - addr = (unsigned long *)(task->thread.esp0 + regoff[regno]); - else - return 0; - /* Need to take stkadj into account. */ - if (regno == PT_SR || regno == PT_PC) { - long stkadj = *(long *)(task->thread.esp0 + PT_REG(stkadj)); - addr = (unsigned long *) ((unsigned long)addr + stkadj); - /* The sr is actually a 16 bit register. */ - if (regno == PT_SR) - return *(unsigned short *)addr; - } - return *addr; -} - -/* - * Write contents of register REGNO in task TASK. - */ -static inline int put_reg(struct task_struct *task, int regno, - unsigned long data) -{ - unsigned long *addr; - - if (regno == PT_USP) - addr = &task->thread.usp; - else if (regno < ARRAY_SIZE(regoff)) - addr = (unsigned long *)(task->thread.esp0 + regoff[regno]); - else - return -1; - /* Need to take stkadj into account. */ - if (regno == PT_SR || regno == PT_PC) { - long stkadj = *(long *)(task->thread.esp0 + PT_REG(stkadj)); - addr = (unsigned long *) ((unsigned long)addr + stkadj); - /* The sr is actually a 16 bit register. */ - if (regno == PT_SR) { - *(unsigned short *)addr = data; - return 0; - } - } - *addr = data; - return 0; -} - -/* - * Make sure the single step bit is not set. - */ -static inline void singlestep_disable(struct task_struct *child) -{ - unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS; - put_reg(child, PT_SR, tmp); - clear_tsk_thread_flag(child, TIF_DELAYED_TRACE); -} - -/* - * Called by kernel/ptrace.c when detaching.. - */ -void ptrace_disable(struct task_struct *child) -{ - singlestep_disable(child); -} - -void user_enable_single_step(struct task_struct *child) -{ - unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS; - put_reg(child, PT_SR, tmp | T1_BIT); - set_tsk_thread_flag(child, TIF_DELAYED_TRACE); -} - -void user_enable_block_step(struct task_struct *child) -{ - unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS; - put_reg(child, PT_SR, tmp | T0_BIT); -} - -void user_disable_single_step(struct task_struct *child) -{ - singlestep_disable(child); -} - -long arch_ptrace(struct task_struct *child, long request, - unsigned long addr, unsigned long data) -{ - unsigned long tmp; - int i, ret = 0; - int regno = addr >> 2; /* temporary hack. */ - unsigned long __user *datap = (unsigned long __user *) data; - - switch (request) { - /* read the word at location addr in the USER area. */ - case PTRACE_PEEKUSR: - if (addr & 3) - goto out_eio; - - if (regno >= 0 && regno < 19) { - tmp = get_reg(child, regno); - } else if (regno >= 21 && regno < 49) { - tmp = child->thread.fp[regno - 21]; - /* Convert internal fpu reg representation - * into long double format - */ - if (FPU_IS_EMU && (regno < 45) && !(regno % 3)) - tmp = ((tmp & 0xffff0000) << 15) | - ((tmp & 0x0000ffff) << 16); - } else - goto out_eio; - ret = put_user(tmp, datap); - break; - - case PTRACE_POKEUSR: - /* write the word at location addr in the USER area */ - if (addr & 3) - goto out_eio; - - if (regno == PT_SR) { - data &= SR_MASK; - data |= get_reg(child, PT_SR) & ~SR_MASK; - } - if (regno >= 0 && regno < 19) { - if (put_reg(child, regno, data)) - goto out_eio; - } else if (regno >= 21 && regno < 48) { - /* Convert long double format - * into internal fpu reg representation - */ - if (FPU_IS_EMU && (regno < 45) && !(regno % 3)) { - data <<= 15; - data = (data & 0xffff0000) | - ((data & 0x0000ffff) >> 1); - } - child->thread.fp[regno - 21] = data; - } else - goto out_eio; - break; - - case PTRACE_GETREGS: /* Get all gp regs from the child. */ - for (i = 0; i < 19; i++) { - tmp = get_reg(child, i); - ret = put_user(tmp, datap); - if (ret) - break; - datap++; - } - break; - - case PTRACE_SETREGS: /* Set all gp regs in the child. */ - for (i = 0; i < 19; i++) { - ret = get_user(tmp, datap); - if (ret) - break; - if (i == PT_SR) { - tmp &= SR_MASK; - tmp |= get_reg(child, PT_SR) & ~SR_MASK; - } - put_reg(child, i, tmp); - datap++; - } - break; - - case PTRACE_GETFPREGS: /* Get the child FPU state. */ - if (copy_to_user(datap, &child->thread.fp, - sizeof(struct user_m68kfp_struct))) - ret = -EFAULT; - break; - - case PTRACE_SETFPREGS: /* Set the child FPU state. */ - if (copy_from_user(&child->thread.fp, datap, - sizeof(struct user_m68kfp_struct))) - ret = -EFAULT; - break; - - case PTRACE_GET_THREAD_AREA: - ret = put_user(task_thread_info(child)->tp_value, datap); - break; - - default: - ret = ptrace_request(child, request, addr, data); - break; - } - - return ret; -out_eio: - return -EIO; -} - -asmlinkage void syscall_trace(void) -{ - ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) - ? 0x80 : 0)); - /* - * this isn't the same as continuing with a signal, but it will do - * for normal use. strace only continues with a signal if the - * stopping signal is not SIGTRAP. -brl - */ - if (current->exit_code) { - send_sig(current->exit_code, current, 1); - current->exit_code = 0; - } -} +#ifdef CONFIG_MMU +#include "ptrace_mm.c" +#else +#include "ptrace_no.c" +#endif diff --git a/arch/m68k/kernel/ptrace_mm.c b/arch/m68k/kernel/ptrace_mm.c new file mode 100644 index 00000000000..0b252683cef --- /dev/null +++ b/arch/m68k/kernel/ptrace_mm.c @@ -0,0 +1,277 @@ +/* + * linux/arch/m68k/kernel/ptrace.c + * + * Copyright (C) 1994 by Hamish Macdonald + * Taken from linux/kernel/ptrace.c and modified for M680x0. + * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of + * this archive for more details. + */ + +#include <linux/kernel.h> +#include <linux/sched.h> +#include <linux/mm.h> +#include <linux/smp.h> +#include <linux/errno.h> +#include <linux/ptrace.h> +#include <linux/user.h> +#include <linux/signal.h> + +#include <asm/uaccess.h> +#include <asm/page.h> +#include <asm/pgtable.h> +#include <asm/system.h> +#include <asm/processor.h> + +/* + * does not yet catch signals sent when the child dies. + * in exit.c or in signal.c. + */ + +/* determines which bits in the SR the user has access to. */ +/* 1 = access 0 = no access */ +#define SR_MASK 0x001f + +/* sets the trace bits. */ +#define TRACE_BITS 0xC000 +#define T1_BIT 0x8000 +#define T0_BIT 0x4000 + +/* Find the stack offset for a register, relative to thread.esp0. */ +#define PT_REG(reg) ((long)&((struct pt_regs *)0)->reg) +#define SW_REG(reg) ((long)&((struct switch_stack *)0)->reg \ + - sizeof(struct switch_stack)) +/* Mapping from PT_xxx to the stack offset at which the register is + saved. Notice that usp has no stack-slot and needs to be treated + specially (see get_reg/put_reg below). */ +static const int regoff[] = { + [0] = PT_REG(d1), + [1] = PT_REG(d2), + [2] = PT_REG(d3), + [3] = PT_REG(d4), + [4] = PT_REG(d5), + [5] = SW_REG(d6), + [6] = SW_REG(d7), + [7] = PT_REG(a0), + [8] = PT_REG(a1), + [9] = PT_REG(a2), + [10] = SW_REG(a3), + [11] = SW_REG(a4), + [12] = SW_REG(a5), + [13] = SW_REG(a6), + [14] = PT_REG(d0), + [15] = -1, + [16] = PT_REG(orig_d0), + [17] = PT_REG(sr), + [18] = PT_REG(pc), +}; + +/* + * Get contents of register REGNO in task TASK. + */ +static inline long get_reg(struct task_struct *task, int regno) +{ + unsigned long *addr; + + if (regno == PT_USP) + addr = &task->thread.usp; + else if (regno < ARRAY_SIZE(regoff)) + addr = (unsigned long *)(task->thread.esp0 + regoff[regno]); + else + return 0; + /* Need to take stkadj into account. */ + if (regno == PT_SR || regno == PT_PC) { + long stkadj = *(long *)(task->thread.esp0 + PT_REG(stkadj)); + addr = (unsigned long *) ((unsigned long)addr + stkadj); + /* The sr is actually a 16 bit register. */ + if (regno == PT_SR) + return *(unsigned short *)addr; + } + return *addr; +} + +/* + * Write contents of register REGNO in task TASK. + */ +static inline int put_reg(struct task_struct *task, int regno, + unsigned long data) +{ + unsigned long *addr; + + if (regno == PT_USP) + addr = &task->thread.usp; + else if (regno < ARRAY_SIZE(regoff)) + addr = (unsigned long *)(task->thread.esp0 + regoff[regno]); + else + return -1; + /* Need to take stkadj into account. */ + if (regno == PT_SR || regno == PT_PC) { + long stkadj = *(long *)(task->thread.esp0 + PT_REG(stkadj)); + addr = (unsigned long *) ((unsigned long)addr + stkadj); + /* The sr is actually a 16 bit register. */ + if (regno == PT_SR) { + *(unsigned short *)addr = data; + return 0; + } + } + *addr = data; + return 0; +} + +/* + * Make sure the single step bit is not set. + */ +static inline void singlestep_disable(struct task_struct *child) +{ + unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS; + put_reg(child, PT_SR, tmp); + clear_tsk_thread_flag(child, TIF_DELAYED_TRACE); +} + +/* + * Called by kernel/ptrace.c when detaching.. + */ +void ptrace_disable(struct task_struct *child) +{ + singlestep_disable(child); +} + +void user_enable_single_step(struct task_struct *child) +{ + unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS; + put_reg(child, PT_SR, tmp | T1_BIT); + set_tsk_thread_flag(child, TIF_DELAYED_TRACE); +} + +void user_enable_block_step(struct task_struct *child) +{ + unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS; + put_reg(child, PT_SR, tmp | T0_BIT); +} + +void user_disable_single_step(struct task_struct *child) +{ + singlestep_disable(child); +} + +long arch_ptrace(struct task_struct *child, long request, + unsigned long addr, unsigned long data) +{ + unsigned long tmp; + int i, ret = 0; + int regno = addr >> 2; /* temporary hack. */ + unsigned long __user *datap = (unsigned long __user *) data; + + switch (request) { + /* read the word at location addr in the USER area. */ + case PTRACE_PEEKUSR: + if (addr & 3) + goto out_eio; + + if (regno >= 0 && regno < 19) { + tmp = get_reg(child, regno); + } else if (regno >= 21 && regno < 49) { + tmp = child->thread.fp[regno - 21]; + /* Convert internal fpu reg representation + * into long double format + */ + if (FPU_IS_EMU && (regno < 45) && !(regno % 3)) + tmp = ((tmp & 0xffff0000) << 15) | + ((tmp & 0x0000ffff) << 16); + } else + goto out_eio; + ret = put_user(tmp, datap); + break; + + case PTRACE_POKEUSR: + /* write the word at location addr in the USER area */ + if (addr & 3) + goto out_eio; + + if (regno == PT_SR) { + data &= SR_MASK; + data |= get_reg(child, PT_SR) & ~SR_MASK; + } + if (regno >= 0 && regno < 19) { + if (put_reg(child, regno, data)) + goto out_eio; + } else if (regno >= 21 && regno < 48) { + /* Convert long double format + * into internal fpu reg representation + */ + if (FPU_IS_EMU && (regno < 45) && !(regno % 3)) { + data <<= 15; + data = (data & 0xffff0000) | + ((data & 0x0000ffff) >> 1); + } + child->thread.fp[regno - 21] = data; + } else + goto out_eio; + break; + + case PTRACE_GETREGS: /* Get all gp regs from the child. */ + for (i = 0; i < 19; i++) { + tmp = get_reg(child, i); + ret = put_user(tmp, datap); + if (ret) + break; + datap++; + } + break; + + case PTRACE_SETREGS: /* Set all gp regs in the child. */ + for (i = 0; i < 19; i++) { + ret = get_user(tmp, datap); + if (ret) + break; + if (i == PT_SR) { + tmp &= SR_MASK; + tmp |= get_reg(child, PT_SR) & ~SR_MASK; + } + put_reg(child, i, tmp); + datap++; + } + break; + + case PTRACE_GETFPREGS: /* Get the child FPU state. */ + if (copy_to_user(datap, &child->thread.fp, + sizeof(struct user_m68kfp_struct))) + ret = -EFAULT; + break; + + case PTRACE_SETFPREGS: /* Set the child FPU state. */ + if (copy_from_user(&child->thread.fp, datap, + sizeof(struct user_m68kfp_struct))) + ret = -EFAULT; + break; + + case PTRACE_GET_THREAD_AREA: + ret = put_user(task_thread_info(child)->tp_value, datap); + break; + + default: + ret = ptrace_request(child, request, addr, data); + break; + } + + return ret; +out_eio: + return -EIO; +} + +asmlinkage void syscall_trace(void) +{ + ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) + ? 0x80 : 0)); + /* + * this isn't the same as continuing with a signal, but it will do + * for normal use. strace only continues with a signal if the + * stopping signal is not SIGTRAP. -brl + */ + if (current->exit_code) { + send_sig(current->exit_code, current, 1); + current->exit_code = 0; + } +} diff --git a/arch/m68knommu/kernel/ptrace.c b/arch/m68k/kernel/ptrace_no.c index 6709fb70733..6709fb70733 100644 --- a/arch/m68knommu/kernel/ptrace.c +++ b/arch/m68k/kernel/ptrace_no.c diff --git a/arch/m68k/kernel/setup.c b/arch/m68k/kernel/setup.c index 334d8364037..4bf129f1d2e 100644 --- a/arch/m68k/kernel/setup.c +++ b/arch/m68k/kernel/setup.c @@ -1,533 +1,5 @@ -/* - * linux/arch/m68k/kernel/setup.c - * - * Copyright (C) 1995 Hamish Macdonald - */ - -/* - * This file handles the architecture-dependent parts of system setup - */ - -#include <linux/kernel.h> -#include <linux/mm.h> -#include <linux/sched.h> -#include <linux/delay.h> -#include <linux/interrupt.h> -#include <linux/fs.h> -#include <linux/console.h> -#include <linux/genhd.h> -#include <linux/errno.h> -#include <linux/string.h> -#include <linux/init.h> -#include <linux/bootmem.h> -#include <linux/proc_fs.h> -#include <linux/seq_file.h> -#include <linux/module.h> -#include <linux/initrd.h> - -#include <asm/bootinfo.h> -#include <asm/sections.h> -#include <asm/setup.h> -#include <asm/fpu.h> -#include <asm/irq.h> -#include <asm/io.h> -#include <asm/machdep.h> -#ifdef CONFIG_AMIGA -#include <asm/amigahw.h> -#endif -#ifdef CONFIG_ATARI -#include <asm/atarihw.h> -#include <asm/atari_stram.h> -#endif -#ifdef CONFIG_SUN3X -#include <asm/dvma.h> -#endif -#include <asm/natfeat.h> - -#if !FPSTATESIZE || !NR_IRQS -#warning No CPU/platform type selected, your kernel will not work! -#warning Are you building an allnoconfig kernel? -#endif - -unsigned long m68k_machtype; -EXPORT_SYMBOL(m68k_machtype); -unsigned long m68k_cputype; -EXPORT_SYMBOL(m68k_cputype); -unsigned long m68k_fputype; -unsigned long m68k_mmutype; -EXPORT_SYMBOL(m68k_mmutype); -#ifdef CONFIG_VME -unsigned long vme_brdtype; -EXPORT_SYMBOL(vme_brdtype); -#endif - -int m68k_is040or060; -EXPORT_SYMBOL(m68k_is040or060); - -extern unsigned long availmem; - -int m68k_num_memory; -EXPORT_SYMBOL(m68k_num_memory); -int m68k_realnum_memory; -EXPORT_SYMBOL(m68k_realnum_memory); -unsigned long m68k_memoffset; -struct mem_info m68k_memory[NUM_MEMINFO]; -EXPORT_SYMBOL(m68k_memory); - -struct mem_info m68k_ramdisk; - -static char m68k_command_line[CL_SIZE]; - -void (*mach_sched_init) (irq_handler_t handler) __initdata = NULL; -/* machine dependent irq functions */ -void (*mach_init_IRQ) (void) __initdata = NULL; -void (*mach_get_model) (char *model); -void (*mach_get_hardware_list) (struct seq_file *m); -/* machine dependent timer functions */ -unsigned long (*mach_gettimeoffset) (void); -int (*mach_hwclk) (int, struct rtc_time*); -EXPORT_SYMBOL(mach_hwclk); -int (*mach_set_clock_mmss) (unsigned long); -unsigned int (*mach_get_ss)(void); -int (*mach_get_rtc_pll)(struct rtc_pll_info *); -int (*mach_set_rtc_pll)(struct rtc_pll_info *); -EXPORT_SYMBOL(mach_get_ss); -EXPORT_SYMBOL(mach_get_rtc_pll); -EXPORT_SYMBOL(mach_set_rtc_pll); -void (*mach_reset)( void ); -void (*mach_halt)( void ); -void (*mach_power_off)( void ); -long mach_max_dma_address = 0x00ffffff; /* default set to the lower 16MB */ -#ifdef CONFIG_HEARTBEAT -void (*mach_heartbeat) (int); -EXPORT_SYMBOL(mach_heartbeat); -#endif -#ifdef CONFIG_M68K_L2_CACHE -void (*mach_l2_flush) (int); -#endif -#if defined(CONFIG_INPUT_M68K_BEEP) || defined(CONFIG_INPUT_M68K_BEEP_MODULE) -void (*mach_beep)(unsigned int, unsigned int); -EXPORT_SYMBOL(mach_beep); -#endif -#if defined(CONFIG_ISA) && defined(MULTI_ISA) -int isa_type; -int isa_sex; -EXPORT_SYMBOL(isa_type); -EXPORT_SYMBOL(isa_sex); -#endif - -extern int amiga_parse_bootinfo(const struct bi_record *); -extern int atari_parse_bootinfo(const struct bi_record *); -extern int mac_parse_bootinfo(const struct bi_record *); -extern int q40_parse_bootinfo(const struct bi_record *); -extern int bvme6000_parse_bootinfo(const struct bi_record *); -extern int mvme16x_parse_bootinfo(const struct bi_record *); -extern int mvme147_parse_bootinfo(const struct bi_record *); -extern int hp300_parse_bootinfo(const struct bi_record *); -extern int apollo_parse_bootinfo(const struct bi_record *); - -extern void config_amiga(void); -extern void config_atari(void); -extern void config_mac(void); -extern void config_sun3(void); -extern void config_apollo(void); -extern void config_mvme147(void); -extern void config_mvme16x(void); -extern void config_bvme6000(void); -extern void config_hp300(void); -extern void config_q40(void); -extern void config_sun3x(void); - -#define MASK_256K 0xfffc0000 - -extern void paging_init(void); - -static void __init m68k_parse_bootinfo(const struct bi_record *record) -{ - while (record->tag != BI_LAST) { - int unknown = 0; - const unsigned long *data = record->data; - - switch (record->tag) { - case BI_MACHTYPE: - case BI_CPUTYPE: - case BI_FPUTYPE: - case BI_MMUTYPE: - /* Already set up by head.S */ - break; - - case BI_MEMCHUNK: - if (m68k_num_memory < NUM_MEMINFO) { - m68k_memory[m68k_num_memory].addr = data[0]; - m68k_memory[m68k_num_memory].size = data[1]; - m68k_num_memory++; - } else - printk("m68k_parse_bootinfo: too many memory chunks\n"); - break; - - case BI_RAMDISK: - m68k_ramdisk.addr = data[0]; - m68k_ramdisk.size = data[1]; - break; - - case BI_COMMAND_LINE: - strlcpy(m68k_command_line, (const char *)data, - sizeof(m68k_command_line)); - break; - - default: - if (MACH_IS_AMIGA) - unknown = amiga_parse_bootinfo(record); - else if (MACH_IS_ATARI) - unknown = atari_parse_bootinfo(record); - else if (MACH_IS_MAC) - unknown = mac_parse_bootinfo(record); - else if (MACH_IS_Q40) - unknown = q40_parse_bootinfo(record); - else if (MACH_IS_BVME6000) - unknown = bvme6000_parse_bootinfo(record); - else if (MACH_IS_MVME16x) - unknown = mvme16x_parse_bootinfo(record); - else if (MACH_IS_MVME147) - unknown = mvme147_parse_bootinfo(record); - else if (MACH_IS_HP300) - unknown = hp300_parse_bootinfo(record); - else if (MACH_IS_APOLLO) - unknown = apollo_parse_bootinfo(record); - else - unknown = 1; - } - if (unknown) - printk("m68k_parse_bootinfo: unknown tag 0x%04x ignored\n", - record->tag); - record = (struct bi_record *)((unsigned long)record + - record->size); - } - - m68k_realnum_memory = m68k_num_memory; -#ifdef CONFIG_SINGLE_MEMORY_CHUNK - if (m68k_num_memory > 1) { - printk("Ignoring last %i chunks of physical memory\n", - (m68k_num_memory - 1)); - m68k_num_memory = 1; - } -#endif -} - -void __init setup_arch(char **cmdline_p) -{ - int i; - - /* The bootinfo is located right after the kernel bss */ - m68k_parse_bootinfo((const struct bi_record *)_end); - - if (CPU_IS_040) - m68k_is040or060 = 4; - else if (CPU_IS_060) - m68k_is040or060 = 6; - - /* FIXME: m68k_fputype is passed in by Penguin booter, which can - * be confused by software FPU emulation. BEWARE. - * We should really do our own FPU check at startup. - * [what do we do with buggy 68LC040s? if we have problems - * with them, we should add a test to check_bugs() below] */ -#ifndef CONFIG_M68KFPU_EMU_ONLY - /* clear the fpu if we have one */ - if (m68k_fputype & (FPU_68881|FPU_68882|FPU_68040|FPU_68060)) { - volatile int zero = 0; - asm volatile ("frestore %0" : : "m" (zero)); - } -#endif - - if (CPU_IS_060) { - u32 pcr; - - asm (".chip 68060; movec %%pcr,%0; .chip 68k" - : "=d" (pcr)); - if (((pcr >> 8) & 0xff) <= 5) { - printk("Enabling workaround for errata I14\n"); - asm (".chip 68060; movec %0,%%pcr; .chip 68k" - : : "d" (pcr | 0x20)); - } - } - - init_mm.start_code = PAGE_OFFSET; - init_mm.end_code = (unsigned long)_etext; - init_mm.end_data = (unsigned long)_edata; - init_mm.brk = (unsigned long)_end; - - *cmdline_p = m68k_command_line; - memcpy(boot_command_line, *cmdline_p, CL_SIZE); - - parse_early_param(); - -#ifdef CONFIG_DUMMY_CONSOLE - conswitchp = &dummy_con; -#endif - - switch (m68k_machtype) { -#ifdef CONFIG_AMIGA - case MACH_AMIGA: - config_amiga(); - break; -#endif -#ifdef CONFIG_ATARI - case MACH_ATARI: - config_atari(); - break; -#endif -#ifdef CONFIG_MAC - case MACH_MAC: - config_mac(); - break; -#endif -#ifdef CONFIG_SUN3 - case MACH_SUN3: - config_sun3(); - break; -#endif -#ifdef CONFIG_APOLLO - case MACH_APOLLO: - config_apollo(); - break; -#endif -#ifdef CONFIG_MVME147 - case MACH_MVME147: - config_mvme147(); - break; -#endif -#ifdef CONFIG_MVME16x - case MACH_MVME16x: - config_mvme16x(); - break; -#endif -#ifdef CONFIG_BVME6000 - case MACH_BVME6000: - config_bvme6000(); - break; -#endif -#ifdef CONFIG_HP300 - case MACH_HP300: - config_hp300(); - break; -#endif -#ifdef CONFIG_Q40 - case MACH_Q40: - config_q40(); - break; -#endif -#ifdef CONFIG_SUN3X - case MACH_SUN3X: - config_sun3x(); - break; -#endif - default: - panic("No configuration setup"); - } - -#ifdef CONFIG_NATFEAT - nf_init(); -#endif - - paging_init(); - -#ifndef CONFIG_SUN3 - for (i = 1; i < m68k_num_memory; i++) - free_bootmem_node(NODE_DATA(i), m68k_memory[i].addr, - m68k_memory[i].size); -#ifdef CONFIG_BLK_DEV_INITRD - if (m68k_ramdisk.size) { - reserve_bootmem_node(__virt_to_node(phys_to_virt(m68k_ramdisk.addr)), - m68k_ramdisk.addr, m68k_ramdisk.size, - BOOTMEM_DEFAULT); - initrd_start = (unsigned long)phys_to_virt(m68k_ramdisk.addr); - initrd_end = initrd_start + m68k_ramdisk.size; - printk("initrd: %08lx - %08lx\n", initrd_start, initrd_end); - } -#endif - -#ifdef CONFIG_ATARI - if (MACH_IS_ATARI) - atari_stram_reserve_pages((void *)availmem); -#endif -#ifdef CONFIG_SUN3X - if (MACH_IS_SUN3X) { - dvma_init(); - } -#endif - -#endif /* !CONFIG_SUN3 */ - -/* set ISA defs early as possible */ -#if defined(CONFIG_ISA) && defined(MULTI_ISA) - if (MACH_IS_Q40) { - isa_type = ISA_TYPE_Q40; - isa_sex = 0; - } -#ifdef CONFIG_AMIGA_PCMCIA - if (MACH_IS_AMIGA && AMIGAHW_PRESENT(PCMCIA)) { - isa_type = ISA_TYPE_AG; - isa_sex = 1; - } -#endif -#endif -} - -static int show_cpuinfo(struct seq_file *m, void *v) -{ - const char *cpu, *mmu, *fpu; - unsigned long clockfreq, clockfactor; - -#define LOOP_CYCLES_68020 (8) -#define LOOP_CYCLES_68030 (8) -#define LOOP_CYCLES_68040 (3) -#define LOOP_CYCLES_68060 (1) - - if (CPU_IS_020) { - cpu = "68020"; - clockfactor = LOOP_CYCLES_68020; - } else if (CPU_IS_030) { - cpu = "68030"; - clockfactor = LOOP_CYCLES_68030; - } else if (CPU_IS_040) { - cpu = "68040"; - clockfactor = LOOP_CYCLES_68040; - } else if (CPU_IS_060) { - cpu = "68060"; - clockfactor = LOOP_CYCLES_68060; - } else { - cpu = "680x0"; - clockfactor = 0; - } - -#ifdef CONFIG_M68KFPU_EMU_ONLY - fpu = "none(soft float)"; +#ifdef CONFIG_MMU +#include "setup_mm.c" #else - if (m68k_fputype & FPU_68881) - fpu = "68881"; - else if (m68k_fputype & FPU_68882) - fpu = "68882"; - else if (m68k_fputype & FPU_68040) - fpu = "68040"; - else if (m68k_fputype & FPU_68060) - fpu = "68060"; - else if (m68k_fputype & FPU_SUNFPA) - fpu = "Sun FPA"; - else - fpu = "none"; -#endif - - if (m68k_mmutype & MMU_68851) - mmu = "68851"; - else if (m68k_mmutype & MMU_68030) - mmu = "68030"; - else if (m68k_mmutype & MMU_68040) - mmu = "68040"; - else if (m68k_mmutype & MMU_68060) - mmu = "68060"; - else if (m68k_mmutype & MMU_SUN3) - mmu = "Sun-3"; - else if (m68k_mmutype & MMU_APOLLO) - mmu = "Apollo"; - else - mmu = "unknown"; - - clockfreq = loops_per_jiffy * HZ * clockfactor; - - seq_printf(m, "CPU:\t\t%s\n" - "MMU:\t\t%s\n" - "FPU:\t\t%s\n" - "Clocking:\t%lu.%1luMHz\n" - "BogoMips:\t%lu.%02lu\n" - "Calibration:\t%lu loops\n", - cpu, mmu, fpu, - clockfreq/1000000,(clockfreq/100000)%10, - loops_per_jiffy/(500000/HZ),(loops_per_jiffy/(5000/HZ))%100, - loops_per_jiffy); - return 0; -} - -static void *c_start(struct seq_file *m, loff_t *pos) -{ - return *pos < 1 ? (void *)1 : NULL; -} -static void *c_next(struct seq_file *m, void *v, loff_t *pos) -{ - ++*pos; - return NULL; -} -static void c_stop(struct seq_file *m, void *v) -{ -} -const struct seq_operations cpuinfo_op = { - .start = c_start, - .next = c_next, - .stop = c_stop, - .show = show_cpuinfo, -}; - -#ifdef CONFIG_PROC_HARDWARE -static int hardware_proc_show(struct seq_file *m, void *v) -{ - char model[80]; - unsigned long mem; - int i; - - if (mach_get_model) - mach_get_model(model); - else - strcpy(model, "Unknown m68k"); - - seq_printf(m, "Model:\t\t%s\n", model); - for (mem = 0, i = 0; i < m68k_num_memory; i++) - mem += m68k_memory[i].size; - seq_printf(m, "System Memory:\t%ldK\n", mem >> 10); - - if (mach_get_hardware_list) - mach_get_hardware_list(m); - - return 0; -} - -static int hardware_proc_open(struct inode *inode, struct file *file) -{ - return single_open(file, hardware_proc_show, NULL); -} - -static const struct file_operations hardware_proc_fops = { - .open = hardware_proc_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int __init proc_hardware_init(void) -{ - proc_create("hardware", 0, NULL, &hardware_proc_fops); - return 0; -} -module_init(proc_hardware_init); +#include "setup_no.c" #endif - -void check_bugs(void) -{ -#ifndef CONFIG_M68KFPU_EMU - if (m68k_fputype == 0) { - printk(KERN_EMERG "*** YOU DO NOT HAVE A FLOATING POINT UNIT, " - "WHICH IS REQUIRED BY LINUX/M68K ***\n"); - printk(KERN_EMERG "Upgrade your hardware or join the FPU " - "emulation project\n"); - panic("no FPU"); - } -#endif /* !CONFIG_M68KFPU_EMU */ -} - -#ifdef CONFIG_ADB -static int __init adb_probe_sync_enable (char *str) { - extern int __adb_probe_sync; - __adb_probe_sync = 1; - return 1; -} - -__setup("adb_sync", adb_probe_sync_enable); -#endif /* CONFIG_ADB */ diff --git a/arch/m68k/kernel/setup_mm.c b/arch/m68k/kernel/setup_mm.c new file mode 100644 index 00000000000..334d8364037 --- /dev/null +++ b/arch/m68k/kernel/setup_mm.c @@ -0,0 +1,533 @@ +/* + * linux/arch/m68k/kernel/setup.c + * + * Copyright (C) 1995 Hamish Macdonald + */ + +/* + * This file handles the architecture-dependent parts of system setup + */ + +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/sched.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/fs.h> +#include <linux/console.h> +#include <linux/genhd.h> +#include <linux/errno.h> +#include <linux/string.h> +#include <linux/init.h> +#include <linux/bootmem.h> +#include <linux/proc_fs.h> +#include <linux/seq_file.h> +#include <linux/module.h> +#include <linux/initrd.h> + +#include <asm/bootinfo.h> +#include <asm/sections.h> +#include <asm/setup.h> +#include <asm/fpu.h> +#include <asm/irq.h> +#include <asm/io.h> +#include <asm/machdep.h> +#ifdef CONFIG_AMIGA +#include <asm/amigahw.h> +#endif +#ifdef CONFIG_ATARI +#include <asm/atarihw.h> +#include <asm/atari_stram.h> +#endif +#ifdef CONFIG_SUN3X +#include <asm/dvma.h> +#endif +#include <asm/natfeat.h> + +#if !FPSTATESIZE || !NR_IRQS +#warning No CPU/platform type selected, your kernel will not work! +#warning Are you building an allnoconfig kernel? +#endif + +unsigned long m68k_machtype; +EXPORT_SYMBOL(m68k_machtype); +unsigned long m68k_cputype; +EXPORT_SYMBOL(m68k_cputype); +unsigned long m68k_fputype; +unsigned long m68k_mmutype; +EXPORT_SYMBOL(m68k_mmutype); +#ifdef CONFIG_VME +unsigned long vme_brdtype; +EXPORT_SYMBOL(vme_brdtype); +#endif + +int m68k_is040or060; +EXPORT_SYMBOL(m68k_is040or060); + +extern unsigned long availmem; + +int m68k_num_memory; +EXPORT_SYMBOL(m68k_num_memory); +int m68k_realnum_memory; +EXPORT_SYMBOL(m68k_realnum_memory); +unsigned long m68k_memoffset; +struct mem_info m68k_memory[NUM_MEMINFO]; +EXPORT_SYMBOL(m68k_memory); + +struct mem_info m68k_ramdisk; + +static char m68k_command_line[CL_SIZE]; + +void (*mach_sched_init) (irq_handler_t handler) __initdata = NULL; +/* machine dependent irq functions */ +void (*mach_init_IRQ) (void) __initdata = NULL; +void (*mach_get_model) (char *model); +void (*mach_get_hardware_list) (struct seq_file *m); +/* machine dependent timer functions */ +unsigned long (*mach_gettimeoffset) (void); +int (*mach_hwclk) (int, struct rtc_time*); +EXPORT_SYMBOL(mach_hwclk); +int (*mach_set_clock_mmss) (unsigned long); +unsigned int (*mach_get_ss)(void); +int (*mach_get_rtc_pll)(struct rtc_pll_info *); +int (*mach_set_rtc_pll)(struct rtc_pll_info *); +EXPORT_SYMBOL(mach_get_ss); +EXPORT_SYMBOL(mach_get_rtc_pll); +EXPORT_SYMBOL(mach_set_rtc_pll); +void (*mach_reset)( void ); +void (*mach_halt)( void ); +void (*mach_power_off)( void ); +long mach_max_dma_address = 0x00ffffff; /* default set to the lower 16MB */ +#ifdef CONFIG_HEARTBEAT +void (*mach_heartbeat) (int); +EXPORT_SYMBOL(mach_heartbeat); +#endif +#ifdef CONFIG_M68K_L2_CACHE +void (*mach_l2_flush) (int); +#endif +#if defined(CONFIG_INPUT_M68K_BEEP) || defined(CONFIG_INPUT_M68K_BEEP_MODULE) +void (*mach_beep)(unsigned int, unsigned int); +EXPORT_SYMBOL(mach_beep); +#endif +#if defined(CONFIG_ISA) && defined(MULTI_ISA) +int isa_type; +int isa_sex; +EXPORT_SYMBOL(isa_type); +EXPORT_SYMBOL(isa_sex); +#endif + +extern int amiga_parse_bootinfo(const struct bi_record *); +extern int atari_parse_bootinfo(const struct bi_record *); +extern int mac_parse_bootinfo(const struct bi_record *); +extern int q40_parse_bootinfo(const struct bi_record *); +extern int bvme6000_parse_bootinfo(const struct bi_record *); +extern int mvme16x_parse_bootinfo(const struct bi_record *); +extern int mvme147_parse_bootinfo(const struct bi_record *); +extern int hp300_parse_bootinfo(const struct bi_record *); +extern int apollo_parse_bootinfo(const struct bi_record *); + +extern void config_amiga(void); +extern void config_atari(void); +extern void config_mac(void); +extern void config_sun3(void); +extern void config_apollo(void); +extern void config_mvme147(void); +extern void config_mvme16x(void); +extern void config_bvme6000(void); +extern void config_hp300(void); +extern void config_q40(void); +extern void config_sun3x(void); + +#define MASK_256K 0xfffc0000 + +extern void paging_init(void); + +static void __init m68k_parse_bootinfo(const struct bi_record *record) +{ + while (record->tag != BI_LAST) { + int unknown = 0; + const unsigned long *data = record->data; + + switch (record->tag) { + case BI_MACHTYPE: + case BI_CPUTYPE: + case BI_FPUTYPE: + case BI_MMUTYPE: + /* Already set up by head.S */ + break; + + case BI_MEMCHUNK: + if (m68k_num_memory < NUM_MEMINFO) { + m68k_memory[m68k_num_memory].addr = data[0]; + m68k_memory[m68k_num_memory].size = data[1]; + m68k_num_memory++; + } else + printk("m68k_parse_bootinfo: too many memory chunks\n"); + break; + + case BI_RAMDISK: + m68k_ramdisk.addr = data[0]; + m68k_ramdisk.size = data[1]; + break; + + case BI_COMMAND_LINE: + strlcpy(m68k_command_line, (const char *)data, + sizeof(m68k_command_line)); + break; + + default: + if (MACH_IS_AMIGA) + unknown = amiga_parse_bootinfo(record); + else if (MACH_IS_ATARI) + unknown = atari_parse_bootinfo(record); + else if (MACH_IS_MAC) + unknown = mac_parse_bootinfo(record); + else if (MACH_IS_Q40) + unknown = q40_parse_bootinfo(record); + else if (MACH_IS_BVME6000) + unknown = bvme6000_parse_bootinfo(record); + else if (MACH_IS_MVME16x) + unknown = mvme16x_parse_bootinfo(record); + else if (MACH_IS_MVME147) + unknown = mvme147_parse_bootinfo(record); + else if (MACH_IS_HP300) + unknown = hp300_parse_bootinfo(record); + else if (MACH_IS_APOLLO) + unknown = apollo_parse_bootinfo(record); + else + unknown = 1; + } + if (unknown) + printk("m68k_parse_bootinfo: unknown tag 0x%04x ignored\n", + record->tag); + record = (struct bi_record *)((unsigned long)record + + record->size); + } + + m68k_realnum_memory = m68k_num_memory; +#ifdef CONFIG_SINGLE_MEMORY_CHUNK + if (m68k_num_memory > 1) { + printk("Ignoring last %i chunks of physical memory\n", + (m68k_num_memory - 1)); + m68k_num_memory = 1; + } +#endif +} + +void __init setup_arch(char **cmdline_p) +{ + int i; + + /* The bootinfo is located right after the kernel bss */ + m68k_parse_bootinfo((const struct bi_record *)_end); + + if (CPU_IS_040) + m68k_is040or060 = 4; + else if (CPU_IS_060) + m68k_is040or060 = 6; + + /* FIXME: m68k_fputype is passed in by Penguin booter, which can + * be confused by software FPU emulation. BEWARE. + * We should really do our own FPU check at startup. + * [what do we do with buggy 68LC040s? if we have problems + * with them, we should add a test to check_bugs() below] */ +#ifndef CONFIG_M68KFPU_EMU_ONLY + /* clear the fpu if we have one */ + if (m68k_fputype & (FPU_68881|FPU_68882|FPU_68040|FPU_68060)) { + volatile int zero = 0; + asm volatile ("frestore %0" : : "m" (zero)); + } +#endif + + if (CPU_IS_060) { + u32 pcr; + + asm (".chip 68060; movec %%pcr,%0; .chip 68k" + : "=d" (pcr)); + if (((pcr >> 8) & 0xff) <= 5) { + printk("Enabling workaround for errata I14\n"); + asm (".chip 68060; movec %0,%%pcr; .chip 68k" + : : "d" (pcr | 0x20)); + } + } + + init_mm.start_code = PAGE_OFFSET; + init_mm.end_code = (unsigned long)_etext; + init_mm.end_data = (unsigned long)_edata; + init_mm.brk = (unsigned long)_end; + + *cmdline_p = m68k_command_line; + memcpy(boot_command_line, *cmdline_p, CL_SIZE); + + parse_early_param(); + +#ifdef CONFIG_DUMMY_CONSOLE + conswitchp = &dummy_con; +#endif + + switch (m68k_machtype) { +#ifdef CONFIG_AMIGA + case MACH_AMIGA: + config_amiga(); + break; +#endif +#ifdef CONFIG_ATARI + case MACH_ATARI: + config_atari(); + break; +#endif +#ifdef CONFIG_MAC + case MACH_MAC: + config_mac(); + break; +#endif +#ifdef CONFIG_SUN3 + case MACH_SUN3: + config_sun3(); + break; +#endif +#ifdef CONFIG_APOLLO + case MACH_APOLLO: + config_apollo(); + break; +#endif +#ifdef CONFIG_MVME147 + case MACH_MVME147: + config_mvme147(); + break; +#endif +#ifdef CONFIG_MVME16x + case MACH_MVME16x: + config_mvme16x(); + break; +#endif +#ifdef CONFIG_BVME6000 + case MACH_BVME6000: + config_bvme6000(); + break; +#endif +#ifdef CONFIG_HP300 + case MACH_HP300: + config_hp300(); + break; +#endif +#ifdef CONFIG_Q40 + case MACH_Q40: + config_q40(); + break; +#endif +#ifdef CONFIG_SUN3X + case MACH_SUN3X: + config_sun3x(); + break; +#endif + default: + panic("No configuration setup"); + } + +#ifdef CONFIG_NATFEAT + nf_init(); +#endif + + paging_init(); + +#ifndef CONFIG_SUN3 + for (i = 1; i < m68k_num_memory; i++) + free_bootmem_node(NODE_DATA(i), m68k_memory[i].addr, + m68k_memory[i].size); +#ifdef CONFIG_BLK_DEV_INITRD + if (m68k_ramdisk.size) { + reserve_bootmem_node(__virt_to_node(phys_to_virt(m68k_ramdisk.addr)), + m68k_ramdisk.addr, m68k_ramdisk.size, + BOOTMEM_DEFAULT); + initrd_start = (unsigned long)phys_to_virt(m68k_ramdisk.addr); + initrd_end = initrd_start + m68k_ramdisk.size; + printk("initrd: %08lx - %08lx\n", initrd_start, initrd_end); + } +#endif + +#ifdef CONFIG_ATARI + if (MACH_IS_ATARI) + atari_stram_reserve_pages((void *)availmem); +#endif +#ifdef CONFIG_SUN3X + if (MACH_IS_SUN3X) { + dvma_init(); + } +#endif + +#endif /* !CONFIG_SUN3 */ + +/* set ISA defs early as possible */ +#if defined(CONFIG_ISA) && defined(MULTI_ISA) + if (MACH_IS_Q40) { + isa_type = ISA_TYPE_Q40; + isa_sex = 0; + } +#ifdef CONFIG_AMIGA_PCMCIA + if (MACH_IS_AMIGA && AMIGAHW_PRESENT(PCMCIA)) { + isa_type = ISA_TYPE_AG; + isa_sex = 1; + } +#endif +#endif +} + +static int show_cpuinfo(struct seq_file *m, void *v) +{ + const char *cpu, *mmu, *fpu; + unsigned long clockfreq, clockfactor; + +#define LOOP_CYCLES_68020 (8) +#define LOOP_CYCLES_68030 (8) +#define LOOP_CYCLES_68040 (3) +#define LOOP_CYCLES_68060 (1) + + if (CPU_IS_020) { + cpu = "68020"; + clockfactor = LOOP_CYCLES_68020; + } else if (CPU_IS_030) { + cpu = "68030"; + clockfactor = LOOP_CYCLES_68030; + } else if (CPU_IS_040) { + cpu = "68040"; + clockfactor = LOOP_CYCLES_68040; + } else if (CPU_IS_060) { + cpu = "68060"; + clockfactor = LOOP_CYCLES_68060; + } else { + cpu = "680x0"; + clockfactor = 0; + } + +#ifdef CONFIG_M68KFPU_EMU_ONLY + fpu = "none(soft float)"; +#else + if (m68k_fputype & FPU_68881) + fpu = "68881"; + else if (m68k_fputype & FPU_68882) + fpu = "68882"; + else if (m68k_fputype & FPU_68040) + fpu = "68040"; + else if (m68k_fputype & FPU_68060) + fpu = "68060"; + else if (m68k_fputype & FPU_SUNFPA) + fpu = "Sun FPA"; + else + fpu = "none"; +#endif + + if (m68k_mmutype & MMU_68851) + mmu = "68851"; + else if (m68k_mmutype & MMU_68030) + mmu = "68030"; + else if (m68k_mmutype & MMU_68040) + mmu = "68040"; + else if (m68k_mmutype & MMU_68060) + mmu = "68060"; + else if (m68k_mmutype & MMU_SUN3) + mmu = "Sun-3"; + else if (m68k_mmutype & MMU_APOLLO) + mmu = "Apollo"; + else + mmu = "unknown"; + + clockfreq = loops_per_jiffy * HZ * clockfactor; + + seq_printf(m, "CPU:\t\t%s\n" + "MMU:\t\t%s\n" + "FPU:\t\t%s\n" + "Clocking:\t%lu.%1luMHz\n" + "BogoMips:\t%lu.%02lu\n" + "Calibration:\t%lu loops\n", + cpu, mmu, fpu, + clockfreq/1000000,(clockfreq/100000)%10, + loops_per_jiffy/(500000/HZ),(loops_per_jiffy/(5000/HZ))%100, + loops_per_jiffy); + return 0; +} + +static void *c_start(struct seq_file *m, loff_t *pos) +{ + return *pos < 1 ? (void *)1 : NULL; +} +static void *c_next(struct seq_file *m, void *v, loff_t *pos) +{ + ++*pos; + return NULL; +} +static void c_stop(struct seq_file *m, void *v) +{ +} +const struct seq_operations cpuinfo_op = { + .start = c_start, + .next = c_next, + .stop = c_stop, + .show = show_cpuinfo, +}; + +#ifdef CONFIG_PROC_HARDWARE +static int hardware_proc_show(struct seq_file *m, void *v) +{ + char model[80]; + unsigned long mem; + int i; + + if (mach_get_model) + mach_get_model(model); + else + strcpy(model, "Unknown m68k"); + + seq_printf(m, "Model:\t\t%s\n", model); + for (mem = 0, i = 0; i < m68k_num_memory; i++) + mem += m68k_memory[i].size; + seq_printf(m, "System Memory:\t%ldK\n", mem >> 10); + + if (mach_get_hardware_list) + mach_get_hardware_list(m); + + return 0; +} + +static int hardware_proc_open(struct inode *inode, struct file *file) +{ + return single_open(file, hardware_proc_show, NULL); +} + +static const struct file_operations hardware_proc_fops = { + .open = hardware_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init proc_hardware_init(void) +{ + proc_create("hardware", 0, NULL, &hardware_proc_fops); + return 0; +} +module_init(proc_hardware_init); +#endif + +void check_bugs(void) +{ +#ifndef CONFIG_M68KFPU_EMU + if (m68k_fputype == 0) { + printk(KERN_EMERG "*** YOU DO NOT HAVE A FLOATING POINT UNIT, " + "WHICH IS REQUIRED BY LINUX/M68K ***\n"); + printk(KERN_EMERG "Upgrade your hardware or join the FPU " + "emulation project\n"); + panic("no FPU"); + } +#endif /* !CONFIG_M68KFPU_EMU */ +} + +#ifdef CONFIG_ADB +static int __init adb_probe_sync_enable (char *str) { + extern int __adb_probe_sync; + __adb_probe_sync = 1; + return 1; +} + +__setup("adb_sync", adb_probe_sync_enable); +#endif /* CONFIG_ADB */ diff --git a/arch/m68knommu/kernel/setup.c b/arch/m68k/kernel/setup_no.c index 16b2de7f510..16b2de7f510 100644 --- a/arch/m68knommu/kernel/setup.c +++ b/arch/m68k/kernel/setup_no.c diff --git a/arch/m68k/kernel/signal.c b/arch/m68k/kernel/signal.c index a0afc239304..2e25713e2ea 100644 --- a/arch/m68k/kernel/signal.c +++ b/arch/m68k/kernel/signal.c @@ -1,1017 +1,5 @@ -/* - * linux/arch/m68k/kernel/signal.c - * - * Copyright (C) 1991, 1992 Linus Torvalds - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -/* - * Linux/m68k support by Hamish Macdonald - * - * 68060 fixes by Jesper Skov - * - * 1997-12-01 Modified for POSIX.1b signals by Andreas Schwab - * - * mathemu support by Roman Zippel - * (Note: fpstate in the signal context is completely ignored for the emulator - * and the internal floating point format is put on stack) - */ - -/* - * ++roman (07/09/96): implemented signal stacks (specially for tosemu on - * Atari :-) Current limitation: Only one sigstack can be active at one time. - * If a second signal with SA_ONSTACK set arrives while working on a sigstack, - * SA_ONSTACK is ignored. This behaviour avoids lots of trouble with nested - * signal handlers! - */ - -#include <linux/sched.h> -#include <linux/mm.h> -#include <linux/kernel.h> -#include <linux/signal.h> -#include <linux/syscalls.h> -#include <linux/errno.h> -#include <linux/wait.h> -#include <linux/ptrace.h> -#include <linux/unistd.h> -#include <linux/stddef.h> -#include <linux/highuid.h> -#include <linux/personality.h> -#include <linux/tty.h> -#include <linux/binfmts.h> -#include <linux/module.h> - -#include <asm/setup.h> -#include <asm/uaccess.h> -#include <asm/pgtable.h> -#include <asm/traps.h> -#include <asm/ucontext.h> - -#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) - -static const int frame_extra_sizes[16] = { - [1] = -1, /* sizeof(((struct frame *)0)->un.fmt1), */ - [2] = sizeof(((struct frame *)0)->un.fmt2), - [3] = sizeof(((struct frame *)0)->un.fmt3), - [4] = sizeof(((struct frame *)0)->un.fmt4), - [5] = -1, /* sizeof(((struct frame *)0)->un.fmt5), */ - [6] = -1, /* sizeof(((struct frame *)0)->un.fmt6), */ - [7] = sizeof(((struct frame *)0)->un.fmt7), - [8] = -1, /* sizeof(((struct frame *)0)->un.fmt8), */ - [9] = sizeof(((struct frame *)0)->un.fmt9), - [10] = sizeof(((struct frame *)0)->un.fmta), - [11] = sizeof(((struct frame *)0)->un.fmtb), - [12] = -1, /* sizeof(((struct frame *)0)->un.fmtc), */ - [13] = -1, /* sizeof(((struct frame *)0)->un.fmtd), */ - [14] = -1, /* sizeof(((struct frame *)0)->un.fmte), */ - [15] = -1, /* sizeof(((struct frame *)0)->un.fmtf), */ -}; - -int handle_kernel_fault(struct pt_regs *regs) -{ - const struct exception_table_entry *fixup; - struct pt_regs *tregs; - - /* Are we prepared to handle this kernel fault? */ - fixup = search_exception_tables(regs->pc); - if (!fixup) - return 0; - - /* Create a new four word stack frame, discarding the old one. */ - regs->stkadj = frame_extra_sizes[regs->format]; - tregs = (struct pt_regs *)((long)regs + regs->stkadj); - tregs->vector = regs->vector; - tregs->format = 0; - tregs->pc = fixup->fixup; - tregs->sr = regs->sr; - - return 1; -} - -/* - * Atomically swap in the new signal mask, and wait for a signal. - */ -asmlinkage int -sys_sigsuspend(int unused0, int unused1, old_sigset_t mask) -{ - mask &= _BLOCKABLE; - spin_lock_irq(¤t->sighand->siglock); - current->saved_sigmask = current->blocked; - siginitset(¤t->blocked, mask); - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - current->state = TASK_INTERRUPTIBLE; - schedule(); - set_restore_sigmask(); - - return -ERESTARTNOHAND; -} - -asmlinkage int -sys_sigaction(int sig, const struct old_sigaction __user *act, - struct old_sigaction __user *oact) -{ - struct k_sigaction new_ka, old_ka; - int ret; - - if (act) { - old_sigset_t mask; - if (!access_ok(VERIFY_READ, act, sizeof(*act)) || - __get_user(new_ka.sa.sa_handler, &act->sa_handler) || - __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) || - __get_user(new_ka.sa.sa_flags, &act->sa_flags) || - __get_user(mask, &act->sa_mask)) - return -EFAULT; - siginitset(&new_ka.sa.sa_mask, mask); - } - - ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL); - - if (!ret && oact) { - if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) || - __put_user(old_ka.sa.sa_handler, &oact->sa_handler) || - __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) || - __put_user(old_ka.sa.sa_flags, &oact->sa_flags) || - __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask)) - return -EFAULT; - } - - return ret; -} - -asmlinkage int -sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss) -{ - return do_sigaltstack(uss, uoss, rdusp()); -} - - -/* - * Do a signal return; undo the signal stack. - * - * Keep the return code on the stack quadword aligned! - * That makes the cache flush below easier. - */ - -struct sigframe -{ - char __user *pretcode; - int sig; - int code; - struct sigcontext __user *psc; - char retcode[8]; - unsigned long extramask[_NSIG_WORDS-1]; - struct sigcontext sc; -}; - -struct rt_sigframe -{ - char __user *pretcode; - int sig; - struct siginfo __user *pinfo; - void __user *puc; - char retcode[8]; - struct siginfo info; - struct ucontext uc; -}; - - -static unsigned char fpu_version; /* version number of fpu, set by setup_frame */ - -static inline int restore_fpu_state(struct sigcontext *sc) -{ - int err = 1; - - if (FPU_IS_EMU) { - /* restore registers */ - memcpy(current->thread.fpcntl, sc->sc_fpcntl, 12); - memcpy(current->thread.fp, sc->sc_fpregs, 24); - return 0; - } - - if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) { - /* Verify the frame format. */ - if (!CPU_IS_060 && (sc->sc_fpstate[0] != fpu_version)) - goto out; - if (CPU_IS_020_OR_030) { - if (m68k_fputype & FPU_68881 && - !(sc->sc_fpstate[1] == 0x18 || sc->sc_fpstate[1] == 0xb4)) - goto out; - if (m68k_fputype & FPU_68882 && - !(sc->sc_fpstate[1] == 0x38 || sc->sc_fpstate[1] == 0xd4)) - goto out; - } else if (CPU_IS_040) { - if (!(sc->sc_fpstate[1] == 0x00 || - sc->sc_fpstate[1] == 0x28 || - sc->sc_fpstate[1] == 0x60)) - goto out; - } else if (CPU_IS_060) { - if (!(sc->sc_fpstate[3] == 0x00 || - sc->sc_fpstate[3] == 0x60 || - sc->sc_fpstate[3] == 0xe0)) - goto out; - } else - goto out; - - __asm__ volatile (".chip 68k/68881\n\t" - "fmovemx %0,%%fp0-%%fp1\n\t" - "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t" - ".chip 68k" - : /* no outputs */ - : "m" (*sc->sc_fpregs), "m" (*sc->sc_fpcntl)); - } - __asm__ volatile (".chip 68k/68881\n\t" - "frestore %0\n\t" - ".chip 68k" : : "m" (*sc->sc_fpstate)); - err = 0; - -out: - return err; -} - -#define FPCONTEXT_SIZE 216 -#define uc_fpstate uc_filler[0] -#define uc_formatvec uc_filler[FPCONTEXT_SIZE/4] -#define uc_extra uc_filler[FPCONTEXT_SIZE/4+1] - -static inline int rt_restore_fpu_state(struct ucontext __user *uc) -{ - unsigned char fpstate[FPCONTEXT_SIZE]; - int context_size = CPU_IS_060 ? 8 : 0; - fpregset_t fpregs; - int err = 1; - - if (FPU_IS_EMU) { - /* restore fpu control register */ - if (__copy_from_user(current->thread.fpcntl, - uc->uc_mcontext.fpregs.f_fpcntl, 12)) - goto out; - /* restore all other fpu register */ - if (__copy_from_user(current->thread.fp, - uc->uc_mcontext.fpregs.f_fpregs, 96)) - goto out; - return 0; - } - - if (__get_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate)) - goto out; - if (CPU_IS_060 ? fpstate[2] : fpstate[0]) { - if (!CPU_IS_060) - context_size = fpstate[1]; - /* Verify the frame format. */ - if (!CPU_IS_060 && (fpstate[0] != fpu_version)) - goto out; - if (CPU_IS_020_OR_030) { - if (m68k_fputype & FPU_68881 && - !(context_size == 0x18 || context_size == 0xb4)) - goto out; - if (m68k_fputype & FPU_68882 && - !(context_size == 0x38 || context_size == 0xd4)) - goto out; - } else if (CPU_IS_040) { - if (!(context_size == 0x00 || - context_size == 0x28 || - context_size == 0x60)) - goto out; - } else if (CPU_IS_060) { - if (!(fpstate[3] == 0x00 || - fpstate[3] == 0x60 || - fpstate[3] == 0xe0)) - goto out; - } else - goto out; - if (__copy_from_user(&fpregs, &uc->uc_mcontext.fpregs, - sizeof(fpregs))) - goto out; - __asm__ volatile (".chip 68k/68881\n\t" - "fmovemx %0,%%fp0-%%fp7\n\t" - "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t" - ".chip 68k" - : /* no outputs */ - : "m" (*fpregs.f_fpregs), - "m" (*fpregs.f_fpcntl)); - } - if (context_size && - __copy_from_user(fpstate + 4, (long __user *)&uc->uc_fpstate + 1, - context_size)) - goto out; - __asm__ volatile (".chip 68k/68881\n\t" - "frestore %0\n\t" - ".chip 68k" : : "m" (*fpstate)); - err = 0; - -out: - return err; -} - -static int mangle_kernel_stack(struct pt_regs *regs, int formatvec, - void __user *fp) -{ - int fsize = frame_extra_sizes[formatvec >> 12]; - if (fsize < 0) { - /* - * user process trying to return with weird frame format - */ -#ifdef DEBUG - printk("user process returning with weird frame format\n"); -#endif - return 1; - } - if (!fsize) { - regs->format = formatvec >> 12; - regs->vector = formatvec & 0xfff; - } else { - struct switch_stack *sw = (struct switch_stack *)regs - 1; - unsigned long buf[fsize / 2]; /* yes, twice as much */ - - /* that'll make sure that expansion won't crap over data */ - if (copy_from_user(buf + fsize / 4, fp, fsize)) - return 1; - - /* point of no return */ - regs->format = formatvec >> 12; - regs->vector = formatvec & 0xfff; -#define frame_offset (sizeof(struct pt_regs)+sizeof(struct switch_stack)) - __asm__ __volatile__ - (" movel %0,%/a0\n\t" - " subl %1,%/a0\n\t" /* make room on stack */ - " movel %/a0,%/sp\n\t" /* set stack pointer */ - /* move switch_stack and pt_regs */ - "1: movel %0@+,%/a0@+\n\t" - " dbra %2,1b\n\t" - " lea %/sp@(%c3),%/a0\n\t" /* add offset of fmt */ - " lsrl #2,%1\n\t" - " subql #1,%1\n\t" - /* copy to the gap we'd made */ - "2: movel %4@+,%/a0@+\n\t" - " dbra %1,2b\n\t" - " bral ret_from_signal\n" - : /* no outputs, it doesn't ever return */ - : "a" (sw), "d" (fsize), "d" (frame_offset/4-1), - "n" (frame_offset), "a" (buf + fsize/4) - : "a0"); -#undef frame_offset - } - return 0; -} - -static inline int -restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __user *fp) -{ - int formatvec; - struct sigcontext context; - int err; - - /* Always make any pending restarted system calls return -EINTR */ - current_thread_info()->restart_block.fn = do_no_restart_syscall; - - /* get previous context */ - if (copy_from_user(&context, usc, sizeof(context))) - goto badframe; - - /* restore passed registers */ - regs->d0 = context.sc_d0; - regs->d1 = context.sc_d1; - regs->a0 = context.sc_a0; - regs->a1 = context.sc_a1; - regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff); - regs->pc = context.sc_pc; - regs->orig_d0 = -1; /* disable syscall checks */ - wrusp(context.sc_usp); - formatvec = context.sc_formatvec; - - err = restore_fpu_state(&context); - - if (err || mangle_kernel_stack(regs, formatvec, fp)) - goto badframe; - - return 0; - -badframe: - return 1; -} - -static inline int -rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw, - struct ucontext __user *uc) -{ - int temp; - greg_t __user *gregs = uc->uc_mcontext.gregs; - unsigned long usp; - int err; - - /* Always make any pending restarted system calls return -EINTR */ - current_thread_info()->restart_block.fn = do_no_restart_syscall; - - err = __get_user(temp, &uc->uc_mcontext.version); - if (temp != MCONTEXT_VERSION) - goto badframe; - /* restore passed registers */ - err |= __get_user(regs->d0, &gregs[0]); - err |= __get_user(regs->d1, &gregs[1]); - err |= __get_user(regs->d2, &gregs[2]); - err |= __get_user(regs->d3, &gregs[3]); - err |= __get_user(regs->d4, &gregs[4]); - err |= __get_user(regs->d5, &gregs[5]); - err |= __get_user(sw->d6, &gregs[6]); - err |= __get_user(sw->d7, &gregs[7]); - err |= __get_user(regs->a0, &gregs[8]); - err |= __get_user(regs->a1, &gregs[9]); - err |= __get_user(regs->a2, &gregs[10]); - err |= __get_user(sw->a3, &gregs[11]); - err |= __get_user(sw->a4, &gregs[12]); - err |= __get_user(sw->a5, &gregs[13]); - err |= __get_user(sw->a6, &gregs[14]); - err |= __get_user(usp, &gregs[15]); - wrusp(usp); - err |= __get_user(regs->pc, &gregs[16]); - err |= __get_user(temp, &gregs[17]); - regs->sr = (regs->sr & 0xff00) | (temp & 0xff); - regs->orig_d0 = -1; /* disable syscall checks */ - err |= __get_user(temp, &uc->uc_formatvec); - - err |= rt_restore_fpu_state(uc); - - if (err || do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT) - goto badframe; - - if (mangle_kernel_stack(regs, temp, &uc->uc_extra)) - goto badframe; - - return 0; - -badframe: - return 1; -} - -asmlinkage int do_sigreturn(unsigned long __unused) -{ - struct switch_stack *sw = (struct switch_stack *) &__unused; - struct pt_regs *regs = (struct pt_regs *) (sw + 1); - unsigned long usp = rdusp(); - struct sigframe __user *frame = (struct sigframe __user *)(usp - 4); - sigset_t set; - - if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - if (__get_user(set.sig[0], &frame->sc.sc_mask) || - (_NSIG_WORDS > 1 && - __copy_from_user(&set.sig[1], &frame->extramask, - sizeof(frame->extramask)))) - goto badframe; - - sigdelsetmask(&set, ~_BLOCKABLE); - current->blocked = set; - recalc_sigpending(); - - if (restore_sigcontext(regs, &frame->sc, frame + 1)) - goto badframe; - return regs->d0; - -badframe: - force_sig(SIGSEGV, current); - return 0; -} - -asmlinkage int do_rt_sigreturn(unsigned long __unused) -{ - struct switch_stack *sw = (struct switch_stack *) &__unused; - struct pt_regs *regs = (struct pt_regs *) (sw + 1); - unsigned long usp = rdusp(); - struct rt_sigframe __user *frame = (struct rt_sigframe __user *)(usp - 4); - sigset_t set; - - if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) - goto badframe; - - sigdelsetmask(&set, ~_BLOCKABLE); - current->blocked = set; - recalc_sigpending(); - - if (rt_restore_ucontext(regs, sw, &frame->uc)) - goto badframe; - return regs->d0; - -badframe: - force_sig(SIGSEGV, current); - return 0; -} - -/* - * Set up a signal frame. - */ - -static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs) -{ - if (FPU_IS_EMU) { - /* save registers */ - memcpy(sc->sc_fpcntl, current->thread.fpcntl, 12); - memcpy(sc->sc_fpregs, current->thread.fp, 24); - return; - } - - __asm__ volatile (".chip 68k/68881\n\t" - "fsave %0\n\t" - ".chip 68k" - : : "m" (*sc->sc_fpstate) : "memory"); - - if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) { - fpu_version = sc->sc_fpstate[0]; - if (CPU_IS_020_OR_030 && - regs->vector >= (VEC_FPBRUC * 4) && - regs->vector <= (VEC_FPNAN * 4)) { - /* Clear pending exception in 68882 idle frame */ - if (*(unsigned short *) sc->sc_fpstate == 0x1f38) - sc->sc_fpstate[0x38] |= 1 << 3; - } - __asm__ volatile (".chip 68k/68881\n\t" - "fmovemx %%fp0-%%fp1,%0\n\t" - "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t" - ".chip 68k" - : "=m" (*sc->sc_fpregs), - "=m" (*sc->sc_fpcntl) - : /* no inputs */ - : "memory"); - } -} - -static inline int rt_save_fpu_state(struct ucontext __user *uc, struct pt_regs *regs) -{ - unsigned char fpstate[FPCONTEXT_SIZE]; - int context_size = CPU_IS_060 ? 8 : 0; - int err = 0; - - if (FPU_IS_EMU) { - /* save fpu control register */ - err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpcntl, - current->thread.fpcntl, 12); - /* save all other fpu register */ - err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpregs, - current->thread.fp, 96); - return err; - } - - __asm__ volatile (".chip 68k/68881\n\t" - "fsave %0\n\t" - ".chip 68k" - : : "m" (*fpstate) : "memory"); - - err |= __put_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate); - if (CPU_IS_060 ? fpstate[2] : fpstate[0]) { - fpregset_t fpregs; - if (!CPU_IS_060) - context_size = fpstate[1]; - fpu_version = fpstate[0]; - if (CPU_IS_020_OR_030 && - regs->vector >= (VEC_FPBRUC * 4) && - regs->vector <= (VEC_FPNAN * 4)) { - /* Clear pending exception in 68882 idle frame */ - if (*(unsigned short *) fpstate == 0x1f38) - fpstate[0x38] |= 1 << 3; - } - __asm__ volatile (".chip 68k/68881\n\t" - "fmovemx %%fp0-%%fp7,%0\n\t" - "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t" - ".chip 68k" - : "=m" (*fpregs.f_fpregs), - "=m" (*fpregs.f_fpcntl) - : /* no inputs */ - : "memory"); - err |= copy_to_user(&uc->uc_mcontext.fpregs, &fpregs, - sizeof(fpregs)); - } - if (context_size) - err |= copy_to_user((long __user *)&uc->uc_fpstate + 1, fpstate + 4, - context_size); - return err; -} - -static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs, - unsigned long mask) -{ - sc->sc_mask = mask; - sc->sc_usp = rdusp(); - sc->sc_d0 = regs->d0; - sc->sc_d1 = regs->d1; - sc->sc_a0 = regs->a0; - sc->sc_a1 = regs->a1; - sc->sc_sr = regs->sr; - sc->sc_pc = regs->pc; - sc->sc_formatvec = regs->format << 12 | regs->vector; - save_fpu_state(sc, regs); -} - -static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs *regs) -{ - struct switch_stack *sw = (struct switch_stack *)regs - 1; - greg_t __user *gregs = uc->uc_mcontext.gregs; - int err = 0; - - err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version); - err |= __put_user(regs->d0, &gregs[0]); - err |= __put_user(regs->d1, &gregs[1]); - err |= __put_user(regs->d2, &gregs[2]); - err |= __put_user(regs->d3, &gregs[3]); - err |= __put_user(regs->d4, &gregs[4]); - err |= __put_user(regs->d5, &gregs[5]); - err |= __put_user(sw->d6, &gregs[6]); - err |= __put_user(sw->d7, &gregs[7]); - err |= __put_user(regs->a0, &gregs[8]); - err |= __put_user(regs->a1, &gregs[9]); - err |= __put_user(regs->a2, &gregs[10]); - err |= __put_user(sw->a3, &gregs[11]); - err |= __put_user(sw->a4, &gregs[12]); - err |= __put_user(sw->a5, &gregs[13]); - err |= __put_user(sw->a6, &gregs[14]); - err |= __put_user(rdusp(), &gregs[15]); - err |= __put_user(regs->pc, &gregs[16]); - err |= __put_user(regs->sr, &gregs[17]); - err |= __put_user((regs->format << 12) | regs->vector, &uc->uc_formatvec); - err |= rt_save_fpu_state(uc, regs); - return err; -} - -static inline void push_cache (unsigned long vaddr) -{ - /* - * Using the old cache_push_v() was really a big waste. - * - * What we are trying to do is to flush 8 bytes to ram. - * Flushing 2 cache lines of 16 bytes is much cheaper than - * flushing 1 or 2 pages, as previously done in - * cache_push_v(). - * Jes - */ - if (CPU_IS_040) { - unsigned long temp; - - __asm__ __volatile__ (".chip 68040\n\t" - "nop\n\t" - "ptestr (%1)\n\t" - "movec %%mmusr,%0\n\t" - ".chip 68k" - : "=r" (temp) - : "a" (vaddr)); - - temp &= PAGE_MASK; - temp |= vaddr & ~PAGE_MASK; - - __asm__ __volatile__ (".chip 68040\n\t" - "nop\n\t" - "cpushl %%bc,(%0)\n\t" - ".chip 68k" - : : "a" (temp)); - } - else if (CPU_IS_060) { - unsigned long temp; - __asm__ __volatile__ (".chip 68060\n\t" - "plpar (%0)\n\t" - ".chip 68k" - : "=a" (temp) - : "0" (vaddr)); - __asm__ __volatile__ (".chip 68060\n\t" - "cpushl %%bc,(%0)\n\t" - ".chip 68k" - : : "a" (temp)); - } - else { - /* - * 68030/68020 have no writeback cache; - * still need to clear icache. - * Note that vaddr is guaranteed to be long word aligned. - */ - unsigned long temp; - asm volatile ("movec %%cacr,%0" : "=r" (temp)); - temp += 4; - asm volatile ("movec %0,%%caar\n\t" - "movec %1,%%cacr" - : : "r" (vaddr), "r" (temp)); - asm volatile ("movec %0,%%caar\n\t" - "movec %1,%%cacr" - : : "r" (vaddr + 4), "r" (temp)); - } -} - -static inline void __user * -get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) -{ - unsigned long usp; - - /* Default to using normal stack. */ - usp = rdusp(); - - /* This is the X/Open sanctioned signal stack switching. */ - if (ka->sa.sa_flags & SA_ONSTACK) { - if (!sas_ss_flags(usp)) - usp = current->sas_ss_sp + current->sas_ss_size; - } - return (void __user *)((usp - frame_size) & -8UL); -} - -static int setup_frame (int sig, struct k_sigaction *ka, - sigset_t *set, struct pt_regs *regs) -{ - struct sigframe __user *frame; - int fsize = frame_extra_sizes[regs->format]; - struct sigcontext context; - int err = 0; - - if (fsize < 0) { -#ifdef DEBUG - printk ("setup_frame: Unknown frame format %#x\n", - regs->format); -#endif - goto give_sigsegv; - } - - frame = get_sigframe(ka, regs, sizeof(*frame) + fsize); - - if (fsize) - err |= copy_to_user (frame + 1, regs + 1, fsize); - - err |= __put_user((current_thread_info()->exec_domain - && current_thread_info()->exec_domain->signal_invmap - && sig < 32 - ? current_thread_info()->exec_domain->signal_invmap[sig] - : sig), - &frame->sig); - - err |= __put_user(regs->vector, &frame->code); - err |= __put_user(&frame->sc, &frame->psc); - - if (_NSIG_WORDS > 1) - err |= copy_to_user(frame->extramask, &set->sig[1], - sizeof(frame->extramask)); - - setup_sigcontext(&context, regs, set->sig[0]); - err |= copy_to_user (&frame->sc, &context, sizeof(context)); - - /* Set up to return from userspace. */ - err |= __put_user(frame->retcode, &frame->pretcode); - /* moveq #,d0; trap #0 */ - err |= __put_user(0x70004e40 + (__NR_sigreturn << 16), - (long __user *)(frame->retcode)); - - if (err) - goto give_sigsegv; - - push_cache ((unsigned long) &frame->retcode); - - /* - * Set up registers for signal handler. All the state we are about - * to destroy is successfully copied to sigframe. - */ - wrusp ((unsigned long) frame); - regs->pc = (unsigned long) ka->sa.sa_handler; - - /* - * This is subtle; if we build more than one sigframe, all but the - * first one will see frame format 0 and have fsize == 0, so we won't - * screw stkadj. - */ - if (fsize) - regs->stkadj = fsize; - - /* Prepare to skip over the extra stuff in the exception frame. */ - if (regs->stkadj) { - struct pt_regs *tregs = - (struct pt_regs *)((ulong)regs + regs->stkadj); -#ifdef DEBUG - printk("Performing stackadjust=%04x\n", regs->stkadj); -#endif - /* This must be copied with decreasing addresses to - handle overlaps. */ - tregs->vector = 0; - tregs->format = 0; - tregs->pc = regs->pc; - tregs->sr = regs->sr; - } - return 0; - -give_sigsegv: - force_sigsegv(sig, current); - return err; -} - -static int setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info, - sigset_t *set, struct pt_regs *regs) -{ - struct rt_sigframe __user *frame; - int fsize = frame_extra_sizes[regs->format]; - int err = 0; - - if (fsize < 0) { -#ifdef DEBUG - printk ("setup_frame: Unknown frame format %#x\n", - regs->format); -#endif - goto give_sigsegv; - } - - frame = get_sigframe(ka, regs, sizeof(*frame)); - - if (fsize) - err |= copy_to_user (&frame->uc.uc_extra, regs + 1, fsize); - - err |= __put_user((current_thread_info()->exec_domain - && current_thread_info()->exec_domain->signal_invmap - && sig < 32 - ? current_thread_info()->exec_domain->signal_invmap[sig] - : sig), - &frame->sig); - err |= __put_user(&frame->info, &frame->pinfo); - err |= __put_user(&frame->uc, &frame->puc); - err |= copy_siginfo_to_user(&frame->info, info); - - /* Create the ucontext. */ - err |= __put_user(0, &frame->uc.uc_flags); - err |= __put_user(NULL, &frame->uc.uc_link); - err |= __put_user((void __user *)current->sas_ss_sp, - &frame->uc.uc_stack.ss_sp); - err |= __put_user(sas_ss_flags(rdusp()), - &frame->uc.uc_stack.ss_flags); - err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size); - err |= rt_setup_ucontext(&frame->uc, regs); - err |= copy_to_user (&frame->uc.uc_sigmask, set, sizeof(*set)); - - /* Set up to return from userspace. */ - err |= __put_user(frame->retcode, &frame->pretcode); -#ifdef __mcoldfire__ - /* movel #__NR_rt_sigreturn,d0; trap #0 */ - err |= __put_user(0x203c0000, (long __user *)(frame->retcode + 0)); - err |= __put_user(0x00004e40 + (__NR_rt_sigreturn << 16), - (long __user *)(frame->retcode + 4)); +#ifdef CONFIG_MMU +#include "signal_mm.c" #else - /* moveq #,d0; notb d0; trap #0 */ - err |= __put_user(0x70004600 + ((__NR_rt_sigreturn ^ 0xff) << 16), - (long __user *)(frame->retcode + 0)); - err |= __put_user(0x4e40, (short __user *)(frame->retcode + 4)); -#endif - - if (err) - goto give_sigsegv; - - push_cache ((unsigned long) &frame->retcode); - - /* - * Set up registers for signal handler. All the state we are about - * to destroy is successfully copied to sigframe. - */ - wrusp ((unsigned long) frame); - regs->pc = (unsigned long) ka->sa.sa_handler; - - /* - * This is subtle; if we build more than one sigframe, all but the - * first one will see frame format 0 and have fsize == 0, so we won't - * screw stkadj. - */ - if (fsize) - regs->stkadj = fsize; - - /* Prepare to skip over the extra stuff in the exception frame. */ - if (regs->stkadj) { - struct pt_regs *tregs = - (struct pt_regs *)((ulong)regs + regs->stkadj); -#ifdef DEBUG - printk("Performing stackadjust=%04x\n", regs->stkadj); +#include "signal_no.c" #endif - /* This must be copied with decreasing addresses to - handle overlaps. */ - tregs->vector = 0; - tregs->format = 0; - tregs->pc = regs->pc; - tregs->sr = regs->sr; - } - return 0; - -give_sigsegv: - force_sigsegv(sig, current); - return err; -} - -static inline void -handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler) -{ - switch (regs->d0) { - case -ERESTARTNOHAND: - if (!has_handler) - goto do_restart; - regs->d0 = -EINTR; - break; - - case -ERESTART_RESTARTBLOCK: - if (!has_handler) { - regs->d0 = __NR_restart_syscall; - regs->pc -= 2; - break; - } - regs->d0 = -EINTR; - break; - - case -ERESTARTSYS: - if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) { - regs->d0 = -EINTR; - break; - } - /* fallthrough */ - case -ERESTARTNOINTR: - do_restart: - regs->d0 = regs->orig_d0; - regs->pc -= 2; - break; - } -} - -void ptrace_signal_deliver(struct pt_regs *regs, void *cookie) -{ - if (regs->orig_d0 < 0) - return; - switch (regs->d0) { - case -ERESTARTNOHAND: - case -ERESTARTSYS: - case -ERESTARTNOINTR: - regs->d0 = regs->orig_d0; - regs->orig_d0 = -1; - regs->pc -= 2; - break; - } -} - -/* - * OK, we're invoking a handler - */ -static void -handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info, - sigset_t *oldset, struct pt_regs *regs) -{ - int err; - /* are we from a system call? */ - if (regs->orig_d0 >= 0) - /* If so, check system call restarting.. */ - handle_restart(regs, ka, 1); - - /* set up the stack frame */ - if (ka->sa.sa_flags & SA_SIGINFO) - err = setup_rt_frame(sig, ka, info, oldset, regs); - else - err = setup_frame(sig, ka, oldset, regs); - - if (err) - return; - - sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); - if (!(ka->sa.sa_flags & SA_NODEFER)) - sigaddset(¤t->blocked,sig); - recalc_sigpending(); - - if (test_thread_flag(TIF_DELAYED_TRACE)) { - regs->sr &= ~0x8000; - send_sig(SIGTRAP, current, 1); - } - - clear_thread_flag(TIF_RESTORE_SIGMASK); -} - -/* - * Note that 'init' is a special process: it doesn't get signals it doesn't - * want to handle. Thus you cannot kill init even with a SIGKILL even by - * mistake. - */ -asmlinkage void do_signal(struct pt_regs *regs) -{ - siginfo_t info; - struct k_sigaction ka; - int signr; - sigset_t *oldset; - - current->thread.esp0 = (unsigned long) regs; - - if (test_thread_flag(TIF_RESTORE_SIGMASK)) - oldset = ¤t->saved_sigmask; - else - oldset = ¤t->blocked; - - signr = get_signal_to_deliver(&info, &ka, regs, NULL); - if (signr > 0) { - /* Whee! Actually deliver the signal. */ - handle_signal(signr, &ka, &info, oldset, regs); - return; - } - - /* Did we come from a system call? */ - if (regs->orig_d0 >= 0) - /* Restart the system call - no handlers present */ - handle_restart(regs, NULL, 0); - - /* If there's no signal to deliver, we just restore the saved mask. */ - if (test_thread_flag(TIF_RESTORE_SIGMASK)) { - clear_thread_flag(TIF_RESTORE_SIGMASK); - sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL); - } -} diff --git a/arch/m68k/kernel/signal_mm.c b/arch/m68k/kernel/signal_mm.c new file mode 100644 index 00000000000..a0afc239304 --- /dev/null +++ b/arch/m68k/kernel/signal_mm.c @@ -0,0 +1,1017 @@ +/* + * linux/arch/m68k/kernel/signal.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +/* + * Linux/m68k support by Hamish Macdonald + * + * 68060 fixes by Jesper Skov + * + * 1997-12-01 Modified for POSIX.1b signals by Andreas Schwab + * + * mathemu support by Roman Zippel + * (Note: fpstate in the signal context is completely ignored for the emulator + * and the internal floating point format is put on stack) + */ + +/* + * ++roman (07/09/96): implemented signal stacks (specially for tosemu on + * Atari :-) Current limitation: Only one sigstack can be active at one time. + * If a second signal with SA_ONSTACK set arrives while working on a sigstack, + * SA_ONSTACK is ignored. This behaviour avoids lots of trouble with nested + * signal handlers! + */ + +#include <linux/sched.h> +#include <linux/mm.h> +#include <linux/kernel.h> +#include <linux/signal.h> +#include <linux/syscalls.h> +#include <linux/errno.h> +#include <linux/wait.h> +#include <linux/ptrace.h> +#include <linux/unistd.h> +#include <linux/stddef.h> +#include <linux/highuid.h> +#include <linux/personality.h> +#include <linux/tty.h> +#include <linux/binfmts.h> +#include <linux/module.h> + +#include <asm/setup.h> +#include <asm/uaccess.h> +#include <asm/pgtable.h> +#include <asm/traps.h> +#include <asm/ucontext.h> + +#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) + +static const int frame_extra_sizes[16] = { + [1] = -1, /* sizeof(((struct frame *)0)->un.fmt1), */ + [2] = sizeof(((struct frame *)0)->un.fmt2), + [3] = sizeof(((struct frame *)0)->un.fmt3), + [4] = sizeof(((struct frame *)0)->un.fmt4), + [5] = -1, /* sizeof(((struct frame *)0)->un.fmt5), */ + [6] = -1, /* sizeof(((struct frame *)0)->un.fmt6), */ + [7] = sizeof(((struct frame *)0)->un.fmt7), + [8] = -1, /* sizeof(((struct frame *)0)->un.fmt8), */ + [9] = sizeof(((struct frame *)0)->un.fmt9), + [10] = sizeof(((struct frame *)0)->un.fmta), + [11] = sizeof(((struct frame *)0)->un.fmtb), + [12] = -1, /* sizeof(((struct frame *)0)->un.fmtc), */ + [13] = -1, /* sizeof(((struct frame *)0)->un.fmtd), */ + [14] = -1, /* sizeof(((struct frame *)0)->un.fmte), */ + [15] = -1, /* sizeof(((struct frame *)0)->un.fmtf), */ +}; + +int handle_kernel_fault(struct pt_regs *regs) +{ + const struct exception_table_entry *fixup; + struct pt_regs *tregs; + + /* Are we prepared to handle this kernel fault? */ + fixup = search_exception_tables(regs->pc); + if (!fixup) + return 0; + + /* Create a new four word stack frame, discarding the old one. */ + regs->stkadj = frame_extra_sizes[regs->format]; + tregs = (struct pt_regs *)((long)regs + regs->stkadj); + tregs->vector = regs->vector; + tregs->format = 0; + tregs->pc = fixup->fixup; + tregs->sr = regs->sr; + + return 1; +} + +/* + * Atomically swap in the new signal mask, and wait for a signal. + */ +asmlinkage int +sys_sigsuspend(int unused0, int unused1, old_sigset_t mask) +{ + mask &= _BLOCKABLE; + spin_lock_irq(¤t->sighand->siglock); + current->saved_sigmask = current->blocked; + siginitset(¤t->blocked, mask); + recalc_sigpending(); + spin_unlock_irq(¤t->sighand->siglock); + + current->state = TASK_INTERRUPTIBLE; + schedule(); + set_restore_sigmask(); + + return -ERESTARTNOHAND; +} + +asmlinkage int +sys_sigaction(int sig, const struct old_sigaction __user *act, + struct old_sigaction __user *oact) +{ + struct k_sigaction new_ka, old_ka; + int ret; + + if (act) { + old_sigset_t mask; + if (!access_ok(VERIFY_READ, act, sizeof(*act)) || + __get_user(new_ka.sa.sa_handler, &act->sa_handler) || + __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) || + __get_user(new_ka.sa.sa_flags, &act->sa_flags) || + __get_user(mask, &act->sa_mask)) + return -EFAULT; + siginitset(&new_ka.sa.sa_mask, mask); + } + + ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL); + + if (!ret && oact) { + if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) || + __put_user(old_ka.sa.sa_handler, &oact->sa_handler) || + __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) || + __put_user(old_ka.sa.sa_flags, &oact->sa_flags) || + __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask)) + return -EFAULT; + } + + return ret; +} + +asmlinkage int +sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss) +{ + return do_sigaltstack(uss, uoss, rdusp()); +} + + +/* + * Do a signal return; undo the signal stack. + * + * Keep the return code on the stack quadword aligned! + * That makes the cache flush below easier. + */ + +struct sigframe +{ + char __user *pretcode; + int sig; + int code; + struct sigcontext __user *psc; + char retcode[8]; + unsigned long extramask[_NSIG_WORDS-1]; + struct sigcontext sc; +}; + +struct rt_sigframe +{ + char __user *pretcode; + int sig; + struct siginfo __user *pinfo; + void __user *puc; + char retcode[8]; + struct siginfo info; + struct ucontext uc; +}; + + +static unsigned char fpu_version; /* version number of fpu, set by setup_frame */ + +static inline int restore_fpu_state(struct sigcontext *sc) +{ + int err = 1; + + if (FPU_IS_EMU) { + /* restore registers */ + memcpy(current->thread.fpcntl, sc->sc_fpcntl, 12); + memcpy(current->thread.fp, sc->sc_fpregs, 24); + return 0; + } + + if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) { + /* Verify the frame format. */ + if (!CPU_IS_060 && (sc->sc_fpstate[0] != fpu_version)) + goto out; + if (CPU_IS_020_OR_030) { + if (m68k_fputype & FPU_68881 && + !(sc->sc_fpstate[1] == 0x18 || sc->sc_fpstate[1] == 0xb4)) + goto out; + if (m68k_fputype & FPU_68882 && + !(sc->sc_fpstate[1] == 0x38 || sc->sc_fpstate[1] == 0xd4)) + goto out; + } else if (CPU_IS_040) { + if (!(sc->sc_fpstate[1] == 0x00 || + sc->sc_fpstate[1] == 0x28 || + sc->sc_fpstate[1] == 0x60)) + goto out; + } else if (CPU_IS_060) { + if (!(sc->sc_fpstate[3] == 0x00 || + sc->sc_fpstate[3] == 0x60 || + sc->sc_fpstate[3] == 0xe0)) + goto out; + } else + goto out; + + __asm__ volatile (".chip 68k/68881\n\t" + "fmovemx %0,%%fp0-%%fp1\n\t" + "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t" + ".chip 68k" + : /* no outputs */ + : "m" (*sc->sc_fpregs), "m" (*sc->sc_fpcntl)); + } + __asm__ volatile (".chip 68k/68881\n\t" + "frestore %0\n\t" + ".chip 68k" : : "m" (*sc->sc_fpstate)); + err = 0; + +out: + return err; +} + +#define FPCONTEXT_SIZE 216 +#define uc_fpstate uc_filler[0] +#define uc_formatvec uc_filler[FPCONTEXT_SIZE/4] +#define uc_extra uc_filler[FPCONTEXT_SIZE/4+1] + +static inline int rt_restore_fpu_state(struct ucontext __user *uc) +{ + unsigned char fpstate[FPCONTEXT_SIZE]; + int context_size = CPU_IS_060 ? 8 : 0; + fpregset_t fpregs; + int err = 1; + + if (FPU_IS_EMU) { + /* restore fpu control register */ + if (__copy_from_user(current->thread.fpcntl, + uc->uc_mcontext.fpregs.f_fpcntl, 12)) + goto out; + /* restore all other fpu register */ + if (__copy_from_user(current->thread.fp, + uc->uc_mcontext.fpregs.f_fpregs, 96)) + goto out; + return 0; + } + + if (__get_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate)) + goto out; + if (CPU_IS_060 ? fpstate[2] : fpstate[0]) { + if (!CPU_IS_060) + context_size = fpstate[1]; + /* Verify the frame format. */ + if (!CPU_IS_060 && (fpstate[0] != fpu_version)) + goto out; + if (CPU_IS_020_OR_030) { + if (m68k_fputype & FPU_68881 && + !(context_size == 0x18 || context_size == 0xb4)) + goto out; + if (m68k_fputype & FPU_68882 && + !(context_size == 0x38 || context_size == 0xd4)) + goto out; + } else if (CPU_IS_040) { + if (!(context_size == 0x00 || + context_size == 0x28 || + context_size == 0x60)) + goto out; + } else if (CPU_IS_060) { + if (!(fpstate[3] == 0x00 || + fpstate[3] == 0x60 || + fpstate[3] == 0xe0)) + goto out; + } else + goto out; + if (__copy_from_user(&fpregs, &uc->uc_mcontext.fpregs, + sizeof(fpregs))) + goto out; + __asm__ volatile (".chip 68k/68881\n\t" + "fmovemx %0,%%fp0-%%fp7\n\t" + "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t" + ".chip 68k" + : /* no outputs */ + : "m" (*fpregs.f_fpregs), + "m" (*fpregs.f_fpcntl)); + } + if (context_size && + __copy_from_user(fpstate + 4, (long __user *)&uc->uc_fpstate + 1, + context_size)) + goto out; + __asm__ volatile (".chip 68k/68881\n\t" + "frestore %0\n\t" + ".chip 68k" : : "m" (*fpstate)); + err = 0; + +out: + return err; +} + +static int mangle_kernel_stack(struct pt_regs *regs, int formatvec, + void __user *fp) +{ + int fsize = frame_extra_sizes[formatvec >> 12]; + if (fsize < 0) { + /* + * user process trying to return with weird frame format + */ +#ifdef DEBUG + printk("user process returning with weird frame format\n"); +#endif + return 1; + } + if (!fsize) { + regs->format = formatvec >> 12; + regs->vector = formatvec & 0xfff; + } else { + struct switch_stack *sw = (struct switch_stack *)regs - 1; + unsigned long buf[fsize / 2]; /* yes, twice as much */ + + /* that'll make sure that expansion won't crap over data */ + if (copy_from_user(buf + fsize / 4, fp, fsize)) + return 1; + + /* point of no return */ + regs->format = formatvec >> 12; + regs->vector = formatvec & 0xfff; +#define frame_offset (sizeof(struct pt_regs)+sizeof(struct switch_stack)) + __asm__ __volatile__ + (" movel %0,%/a0\n\t" + " subl %1,%/a0\n\t" /* make room on stack */ + " movel %/a0,%/sp\n\t" /* set stack pointer */ + /* move switch_stack and pt_regs */ + "1: movel %0@+,%/a0@+\n\t" + " dbra %2,1b\n\t" + " lea %/sp@(%c3),%/a0\n\t" /* add offset of fmt */ + " lsrl #2,%1\n\t" + " subql #1,%1\n\t" + /* copy to the gap we'd made */ + "2: movel %4@+,%/a0@+\n\t" + " dbra %1,2b\n\t" + " bral ret_from_signal\n" + : /* no outputs, it doesn't ever return */ + : "a" (sw), "d" (fsize), "d" (frame_offset/4-1), + "n" (frame_offset), "a" (buf + fsize/4) + : "a0"); +#undef frame_offset + } + return 0; +} + +static inline int +restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __user *fp) +{ + int formatvec; + struct sigcontext context; + int err; + + /* Always make any pending restarted system calls return -EINTR */ + current_thread_info()->restart_block.fn = do_no_restart_syscall; + + /* get previous context */ + if (copy_from_user(&context, usc, sizeof(context))) + goto badframe; + + /* restore passed registers */ + regs->d0 = context.sc_d0; + regs->d1 = context.sc_d1; + regs->a0 = context.sc_a0; + regs->a1 = context.sc_a1; + regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff); + regs->pc = context.sc_pc; + regs->orig_d0 = -1; /* disable syscall checks */ + wrusp(context.sc_usp); + formatvec = context.sc_formatvec; + + err = restore_fpu_state(&context); + + if (err || mangle_kernel_stack(regs, formatvec, fp)) + goto badframe; + + return 0; + +badframe: + return 1; +} + +static inline int +rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw, + struct ucontext __user *uc) +{ + int temp; + greg_t __user *gregs = uc->uc_mcontext.gregs; + unsigned long usp; + int err; + + /* Always make any pending restarted system calls return -EINTR */ + current_thread_info()->restart_block.fn = do_no_restart_syscall; + + err = __get_user(temp, &uc->uc_mcontext.version); + if (temp != MCONTEXT_VERSION) + goto badframe; + /* restore passed registers */ + err |= __get_user(regs->d0, &gregs[0]); + err |= __get_user(regs->d1, &gregs[1]); + err |= __get_user(regs->d2, &gregs[2]); + err |= __get_user(regs->d3, &gregs[3]); + err |= __get_user(regs->d4, &gregs[4]); + err |= __get_user(regs->d5, &gregs[5]); + err |= __get_user(sw->d6, &gregs[6]); + err |= __get_user(sw->d7, &gregs[7]); + err |= __get_user(regs->a0, &gregs[8]); + err |= __get_user(regs->a1, &gregs[9]); + err |= __get_user(regs->a2, &gregs[10]); + err |= __get_user(sw->a3, &gregs[11]); + err |= __get_user(sw->a4, &gregs[12]); + err |= __get_user(sw->a5, &gregs[13]); + err |= __get_user(sw->a6, &gregs[14]); + err |= __get_user(usp, &gregs[15]); + wrusp(usp); + err |= __get_user(regs->pc, &gregs[16]); + err |= __get_user(temp, &gregs[17]); + regs->sr = (regs->sr & 0xff00) | (temp & 0xff); + regs->orig_d0 = -1; /* disable syscall checks */ + err |= __get_user(temp, &uc->uc_formatvec); + + err |= rt_restore_fpu_state(uc); + + if (err || do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT) + goto badframe; + + if (mangle_kernel_stack(regs, temp, &uc->uc_extra)) + goto badframe; + + return 0; + +badframe: + return 1; +} + +asmlinkage int do_sigreturn(unsigned long __unused) +{ + struct switch_stack *sw = (struct switch_stack *) &__unused; + struct pt_regs *regs = (struct pt_regs *) (sw + 1); + unsigned long usp = rdusp(); + struct sigframe __user *frame = (struct sigframe __user *)(usp - 4); + sigset_t set; + + if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) + goto badframe; + if (__get_user(set.sig[0], &frame->sc.sc_mask) || + (_NSIG_WORDS > 1 && + __copy_from_user(&set.sig[1], &frame->extramask, + sizeof(frame->extramask)))) + goto badframe; + + sigdelsetmask(&set, ~_BLOCKABLE); + current->blocked = set; + recalc_sigpending(); + + if (restore_sigcontext(regs, &frame->sc, frame + 1)) + goto badframe; + return regs->d0; + +badframe: + force_sig(SIGSEGV, current); + return 0; +} + +asmlinkage int do_rt_sigreturn(unsigned long __unused) +{ + struct switch_stack *sw = (struct switch_stack *) &__unused; + struct pt_regs *regs = (struct pt_regs *) (sw + 1); + unsigned long usp = rdusp(); + struct rt_sigframe __user *frame = (struct rt_sigframe __user *)(usp - 4); + sigset_t set; + + if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) + goto badframe; + if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) + goto badframe; + + sigdelsetmask(&set, ~_BLOCKABLE); + current->blocked = set; + recalc_sigpending(); + + if (rt_restore_ucontext(regs, sw, &frame->uc)) + goto badframe; + return regs->d0; + +badframe: + force_sig(SIGSEGV, current); + return 0; +} + +/* + * Set up a signal frame. + */ + +static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs) +{ + if (FPU_IS_EMU) { + /* save registers */ + memcpy(sc->sc_fpcntl, current->thread.fpcntl, 12); + memcpy(sc->sc_fpregs, current->thread.fp, 24); + return; + } + + __asm__ volatile (".chip 68k/68881\n\t" + "fsave %0\n\t" + ".chip 68k" + : : "m" (*sc->sc_fpstate) : "memory"); + + if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) { + fpu_version = sc->sc_fpstate[0]; + if (CPU_IS_020_OR_030 && + regs->vector >= (VEC_FPBRUC * 4) && + regs->vector <= (VEC_FPNAN * 4)) { + /* Clear pending exception in 68882 idle frame */ + if (*(unsigned short *) sc->sc_fpstate == 0x1f38) + sc->sc_fpstate[0x38] |= 1 << 3; + } + __asm__ volatile (".chip 68k/68881\n\t" + "fmovemx %%fp0-%%fp1,%0\n\t" + "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t" + ".chip 68k" + : "=m" (*sc->sc_fpregs), + "=m" (*sc->sc_fpcntl) + : /* no inputs */ + : "memory"); + } +} + +static inline int rt_save_fpu_state(struct ucontext __user *uc, struct pt_regs *regs) +{ + unsigned char fpstate[FPCONTEXT_SIZE]; + int context_size = CPU_IS_060 ? 8 : 0; + int err = 0; + + if (FPU_IS_EMU) { + /* save fpu control register */ + err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpcntl, + current->thread.fpcntl, 12); + /* save all other fpu register */ + err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpregs, + current->thread.fp, 96); + return err; + } + + __asm__ volatile (".chip 68k/68881\n\t" + "fsave %0\n\t" + ".chip 68k" + : : "m" (*fpstate) : "memory"); + + err |= __put_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate); + if (CPU_IS_060 ? fpstate[2] : fpstate[0]) { + fpregset_t fpregs; + if (!CPU_IS_060) + context_size = fpstate[1]; + fpu_version = fpstate[0]; + if (CPU_IS_020_OR_030 && + regs->vector >= (VEC_FPBRUC * 4) && + regs->vector <= (VEC_FPNAN * 4)) { + /* Clear pending exception in 68882 idle frame */ + if (*(unsigned short *) fpstate == 0x1f38) + fpstate[0x38] |= 1 << 3; + } + __asm__ volatile (".chip 68k/68881\n\t" + "fmovemx %%fp0-%%fp7,%0\n\t" + "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t" + ".chip 68k" + : "=m" (*fpregs.f_fpregs), + "=m" (*fpregs.f_fpcntl) + : /* no inputs */ + : "memory"); + err |= copy_to_user(&uc->uc_mcontext.fpregs, &fpregs, + sizeof(fpregs)); + } + if (context_size) + err |= copy_to_user((long __user *)&uc->uc_fpstate + 1, fpstate + 4, + context_size); + return err; +} + +static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs, + unsigned long mask) +{ + sc->sc_mask = mask; + sc->sc_usp = rdusp(); + sc->sc_d0 = regs->d0; + sc->sc_d1 = regs->d1; + sc->sc_a0 = regs->a0; + sc->sc_a1 = regs->a1; + sc->sc_sr = regs->sr; + sc->sc_pc = regs->pc; + sc->sc_formatvec = regs->format << 12 | regs->vector; + save_fpu_state(sc, regs); +} + +static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs *regs) +{ + struct switch_stack *sw = (struct switch_stack *)regs - 1; + greg_t __user *gregs = uc->uc_mcontext.gregs; + int err = 0; + + err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version); + err |= __put_user(regs->d0, &gregs[0]); + err |= __put_user(regs->d1, &gregs[1]); + err |= __put_user(regs->d2, &gregs[2]); + err |= __put_user(regs->d3, &gregs[3]); + err |= __put_user(regs->d4, &gregs[4]); + err |= __put_user(regs->d5, &gregs[5]); + err |= __put_user(sw->d6, &gregs[6]); + err |= __put_user(sw->d7, &gregs[7]); + err |= __put_user(regs->a0, &gregs[8]); + err |= __put_user(regs->a1, &gregs[9]); + err |= __put_user(regs->a2, &gregs[10]); + err |= __put_user(sw->a3, &gregs[11]); + err |= __put_user(sw->a4, &gregs[12]); + err |= __put_user(sw->a5, &gregs[13]); + err |= __put_user(sw->a6, &gregs[14]); + err |= __put_user(rdusp(), &gregs[15]); + err |= __put_user(regs->pc, &gregs[16]); + err |= __put_user(regs->sr, &gregs[17]); + err |= __put_user((regs->format << 12) | regs->vector, &uc->uc_formatvec); + err |= rt_save_fpu_state(uc, regs); + return err; +} + +static inline void push_cache (unsigned long vaddr) +{ + /* + * Using the old cache_push_v() was really a big waste. + * + * What we are trying to do is to flush 8 bytes to ram. + * Flushing 2 cache lines of 16 bytes is much cheaper than + * flushing 1 or 2 pages, as previously done in + * cache_push_v(). + * Jes + */ + if (CPU_IS_040) { + unsigned long temp; + + __asm__ __volatile__ (".chip 68040\n\t" + "nop\n\t" + "ptestr (%1)\n\t" + "movec %%mmusr,%0\n\t" + ".chip 68k" + : "=r" (temp) + : "a" (vaddr)); + + temp &= PAGE_MASK; + temp |= vaddr & ~PAGE_MASK; + + __asm__ __volatile__ (".chip 68040\n\t" + "nop\n\t" + "cpushl %%bc,(%0)\n\t" + ".chip 68k" + : : "a" (temp)); + } + else if (CPU_IS_060) { + unsigned long temp; + __asm__ __volatile__ (".chip 68060\n\t" + "plpar (%0)\n\t" + ".chip 68k" + : "=a" (temp) + : "0" (vaddr)); + __asm__ __volatile__ (".chip 68060\n\t" + "cpushl %%bc,(%0)\n\t" + ".chip 68k" + : : "a" (temp)); + } + else { + /* + * 68030/68020 have no writeback cache; + * still need to clear icache. + * Note that vaddr is guaranteed to be long word aligned. + */ + unsigned long temp; + asm volatile ("movec %%cacr,%0" : "=r" (temp)); + temp += 4; + asm volatile ("movec %0,%%caar\n\t" + "movec %1,%%cacr" + : : "r" (vaddr), "r" (temp)); + asm volatile ("movec %0,%%caar\n\t" + "movec %1,%%cacr" + : : "r" (vaddr + 4), "r" (temp)); + } +} + +static inline void __user * +get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) +{ + unsigned long usp; + + /* Default to using normal stack. */ + usp = rdusp(); + + /* This is the X/Open sanctioned signal stack switching. */ + if (ka->sa.sa_flags & SA_ONSTACK) { + if (!sas_ss_flags(usp)) + usp = current->sas_ss_sp + current->sas_ss_size; + } + return (void __user *)((usp - frame_size) & -8UL); +} + +static int setup_frame (int sig, struct k_sigaction *ka, + sigset_t *set, struct pt_regs *regs) +{ + struct sigframe __user *frame; + int fsize = frame_extra_sizes[regs->format]; + struct sigcontext context; + int err = 0; + + if (fsize < 0) { +#ifdef DEBUG + printk ("setup_frame: Unknown frame format %#x\n", + regs->format); +#endif + goto give_sigsegv; + } + + frame = get_sigframe(ka, regs, sizeof(*frame) + fsize); + + if (fsize) + err |= copy_to_user (frame + 1, regs + 1, fsize); + + err |= __put_user((current_thread_info()->exec_domain + && current_thread_info()->exec_domain->signal_invmap + && sig < 32 + ? current_thread_info()->exec_domain->signal_invmap[sig] + : sig), + &frame->sig); + + err |= __put_user(regs->vector, &frame->code); + err |= __put_user(&frame->sc, &frame->psc); + + if (_NSIG_WORDS > 1) + err |= copy_to_user(frame->extramask, &set->sig[1], + sizeof(frame->extramask)); + + setup_sigcontext(&context, regs, set->sig[0]); + err |= copy_to_user (&frame->sc, &context, sizeof(context)); + + /* Set up to return from userspace. */ + err |= __put_user(frame->retcode, &frame->pretcode); + /* moveq #,d0; trap #0 */ + err |= __put_user(0x70004e40 + (__NR_sigreturn << 16), + (long __user *)(frame->retcode)); + + if (err) + goto give_sigsegv; + + push_cache ((unsigned long) &frame->retcode); + + /* + * Set up registers for signal handler. All the state we are about + * to destroy is successfully copied to sigframe. + */ + wrusp ((unsigned long) frame); + regs->pc = (unsigned long) ka->sa.sa_handler; + + /* + * This is subtle; if we build more than one sigframe, all but the + * first one will see frame format 0 and have fsize == 0, so we won't + * screw stkadj. + */ + if (fsize) + regs->stkadj = fsize; + + /* Prepare to skip over the extra stuff in the exception frame. */ + if (regs->stkadj) { + struct pt_regs *tregs = + (struct pt_regs *)((ulong)regs + regs->stkadj); +#ifdef DEBUG + printk("Performing stackadjust=%04x\n", regs->stkadj); +#endif + /* This must be copied with decreasing addresses to + handle overlaps. */ + tregs->vector = 0; + tregs->format = 0; + tregs->pc = regs->pc; + tregs->sr = regs->sr; + } + return 0; + +give_sigsegv: + force_sigsegv(sig, current); + return err; +} + +static int setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info, + sigset_t *set, struct pt_regs *regs) +{ + struct rt_sigframe __user *frame; + int fsize = frame_extra_sizes[regs->format]; + int err = 0; + + if (fsize < 0) { +#ifdef DEBUG + printk ("setup_frame: Unknown frame format %#x\n", + regs->format); +#endif + goto give_sigsegv; + } + + frame = get_sigframe(ka, regs, sizeof(*frame)); + + if (fsize) + err |= copy_to_user (&frame->uc.uc_extra, regs + 1, fsize); + + err |= __put_user((current_thread_info()->exec_domain + && current_thread_info()->exec_domain->signal_invmap + && sig < 32 + ? current_thread_info()->exec_domain->signal_invmap[sig] + : sig), + &frame->sig); + err |= __put_user(&frame->info, &frame->pinfo); + err |= __put_user(&frame->uc, &frame->puc); + err |= copy_siginfo_to_user(&frame->info, info); + + /* Create the ucontext. */ + err |= __put_user(0, &frame->uc.uc_flags); + err |= __put_user(NULL, &frame->uc.uc_link); + err |= __put_user((void __user *)current->sas_ss_sp, + &frame->uc.uc_stack.ss_sp); + err |= __put_user(sas_ss_flags(rdusp()), + &frame->uc.uc_stack.ss_flags); + err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size); + err |= rt_setup_ucontext(&frame->uc, regs); + err |= copy_to_user (&frame->uc.uc_sigmask, set, sizeof(*set)); + + /* Set up to return from userspace. */ + err |= __put_user(frame->retcode, &frame->pretcode); +#ifdef __mcoldfire__ + /* movel #__NR_rt_sigreturn,d0; trap #0 */ + err |= __put_user(0x203c0000, (long __user *)(frame->retcode + 0)); + err |= __put_user(0x00004e40 + (__NR_rt_sigreturn << 16), + (long __user *)(frame->retcode + 4)); +#else + /* moveq #,d0; notb d0; trap #0 */ + err |= __put_user(0x70004600 + ((__NR_rt_sigreturn ^ 0xff) << 16), + (long __user *)(frame->retcode + 0)); + err |= __put_user(0x4e40, (short __user *)(frame->retcode + 4)); +#endif + + if (err) + goto give_sigsegv; + + push_cache ((unsigned long) &frame->retcode); + + /* + * Set up registers for signal handler. All the state we are about + * to destroy is successfully copied to sigframe. + */ + wrusp ((unsigned long) frame); + regs->pc = (unsigned long) ka->sa.sa_handler; + + /* + * This is subtle; if we build more than one sigframe, all but the + * first one will see frame format 0 and have fsize == 0, so we won't + * screw stkadj. + */ + if (fsize) + regs->stkadj = fsize; + + /* Prepare to skip over the extra stuff in the exception frame. */ + if (regs->stkadj) { + struct pt_regs *tregs = + (struct pt_regs *)((ulong)regs + regs->stkadj); +#ifdef DEBUG + printk("Performing stackadjust=%04x\n", regs->stkadj); +#endif + /* This must be copied with decreasing addresses to + handle overlaps. */ + tregs->vector = 0; + tregs->format = 0; + tregs->pc = regs->pc; + tregs->sr = regs->sr; + } + return 0; + +give_sigsegv: + force_sigsegv(sig, current); + return err; +} + +static inline void +handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler) +{ + switch (regs->d0) { + case -ERESTARTNOHAND: + if (!has_handler) + goto do_restart; + regs->d0 = -EINTR; + break; + + case -ERESTART_RESTARTBLOCK: + if (!has_handler) { + regs->d0 = __NR_restart_syscall; + regs->pc -= 2; + break; + } + regs->d0 = -EINTR; + break; + + case -ERESTARTSYS: + if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) { + regs->d0 = -EINTR; + break; + } + /* fallthrough */ + case -ERESTARTNOINTR: + do_restart: + regs->d0 = regs->orig_d0; + regs->pc -= 2; + break; + } +} + +void ptrace_signal_deliver(struct pt_regs *regs, void *cookie) +{ + if (regs->orig_d0 < 0) + return; + switch (regs->d0) { + case -ERESTARTNOHAND: + case -ERESTARTSYS: + case -ERESTARTNOINTR: + regs->d0 = regs->orig_d0; + regs->orig_d0 = -1; + regs->pc -= 2; + break; + } +} + +/* + * OK, we're invoking a handler + */ +static void +handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info, + sigset_t *oldset, struct pt_regs *regs) +{ + int err; + /* are we from a system call? */ + if (regs->orig_d0 >= 0) + /* If so, check system call restarting.. */ + handle_restart(regs, ka, 1); + + /* set up the stack frame */ + if (ka->sa.sa_flags & SA_SIGINFO) + err = setup_rt_frame(sig, ka, info, oldset, regs); + else + err = setup_frame(sig, ka, oldset, regs); + + if (err) + return; + + sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); + if (!(ka->sa.sa_flags & SA_NODEFER)) + sigaddset(¤t->blocked,sig); + recalc_sigpending(); + + if (test_thread_flag(TIF_DELAYED_TRACE)) { + regs->sr &= ~0x8000; + send_sig(SIGTRAP, current, 1); + } + + clear_thread_flag(TIF_RESTORE_SIGMASK); +} + +/* + * Note that 'init' is a special process: it doesn't get signals it doesn't + * want to handle. Thus you cannot kill init even with a SIGKILL even by + * mistake. + */ +asmlinkage void do_signal(struct pt_regs *regs) +{ + siginfo_t info; + struct k_sigaction ka; + int signr; + sigset_t *oldset; + + current->thread.esp0 = (unsigned long) regs; + + if (test_thread_flag(TIF_RESTORE_SIGMASK)) + oldset = ¤t->saved_sigmask; + else + oldset = ¤t->blocked; + + signr = get_signal_to_deliver(&info, &ka, regs, NULL); + if (signr > 0) { + /* Whee! Actually deliver the signal. */ + handle_signal(signr, &ka, &info, oldset, regs); + return; + } + + /* Did we come from a system call? */ + if (regs->orig_d0 >= 0) + /* Restart the system call - no handlers present */ + handle_restart(regs, NULL, 0); + + /* If there's no signal to deliver, we just restore the saved mask. */ + if (test_thread_flag(TIF_RESTORE_SIGMASK)) { + clear_thread_flag(TIF_RESTORE_SIGMASK); + sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL); + } +} diff --git a/arch/m68knommu/kernel/signal.c b/arch/m68k/kernel/signal_no.c index 36a81bb6835..36a81bb6835 100644 --- a/arch/m68knommu/kernel/signal.c +++ b/arch/m68k/kernel/signal_no.c diff --git a/arch/m68k/kernel/sys_m68k.c b/arch/m68k/kernel/sys_m68k.c index 3db2e7f902a..63013df3358 100644 --- a/arch/m68k/kernel/sys_m68k.c +++ b/arch/m68k/kernel/sys_m68k.c @@ -1,546 +1,5 @@ -/* - * linux/arch/m68k/kernel/sys_m68k.c - * - * This file contains various random system calls that - * have a non-standard calling sequence on the Linux/m68k - * platform. - */ - -#include <linux/capability.h> -#include <linux/errno.h> -#include <linux/sched.h> -#include <linux/mm.h> -#include <linux/fs.h> -#include <linux/smp.h> -#include <linux/sem.h> -#include <linux/msg.h> -#include <linux/shm.h> -#include <linux/stat.h> -#include <linux/syscalls.h> -#include <linux/mman.h> -#include <linux/file.h> -#include <linux/ipc.h> - -#include <asm/setup.h> -#include <asm/uaccess.h> -#include <asm/cachectl.h> -#include <asm/traps.h> -#include <asm/page.h> -#include <asm/unistd.h> -#include <linux/elf.h> -#include <asm/tlb.h> - -asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address, - unsigned long error_code); - -asmlinkage long sys_mmap2(unsigned long addr, unsigned long len, - unsigned long prot, unsigned long flags, - unsigned long fd, unsigned long pgoff) -{ - /* - * This is wrong for sun3 - there PAGE_SIZE is 8Kb, - * so we need to shift the argument down by 1; m68k mmap64(3) - * (in libc) expects the last argument of mmap2 in 4Kb units. - */ - return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff); -} - -/* Convert virtual (user) address VADDR to physical address PADDR */ -#define virt_to_phys_040(vaddr) \ -({ \ - unsigned long _mmusr, _paddr; \ - \ - __asm__ __volatile__ (".chip 68040\n\t" \ - "ptestr (%1)\n\t" \ - "movec %%mmusr,%0\n\t" \ - ".chip 68k" \ - : "=r" (_mmusr) \ - : "a" (vaddr)); \ - _paddr = (_mmusr & MMU_R_040) ? (_mmusr & PAGE_MASK) : 0; \ - _paddr; \ -}) - -static inline int -cache_flush_040 (unsigned long addr, int scope, int cache, unsigned long len) -{ - unsigned long paddr, i; - - switch (scope) - { - case FLUSH_SCOPE_ALL: - switch (cache) - { - case FLUSH_CACHE_DATA: - /* This nop is needed for some broken versions of the 68040. */ - __asm__ __volatile__ ("nop\n\t" - ".chip 68040\n\t" - "cpusha %dc\n\t" - ".chip 68k"); - break; - case FLUSH_CACHE_INSN: - __asm__ __volatile__ ("nop\n\t" - ".chip 68040\n\t" - "cpusha %ic\n\t" - ".chip 68k"); - break; - default: - case FLUSH_CACHE_BOTH: - __asm__ __volatile__ ("nop\n\t" - ".chip 68040\n\t" - "cpusha %bc\n\t" - ".chip 68k"); - break; - } - break; - - case FLUSH_SCOPE_LINE: - /* Find the physical address of the first mapped page in the - address range. */ - if ((paddr = virt_to_phys_040(addr))) { - paddr += addr & ~(PAGE_MASK | 15); - len = (len + (addr & 15) + 15) >> 4; - } else { - unsigned long tmp = PAGE_SIZE - (addr & ~PAGE_MASK); - - if (len <= tmp) - return 0; - addr += tmp; - len -= tmp; - tmp = PAGE_SIZE; - for (;;) - { - if ((paddr = virt_to_phys_040(addr))) - break; - if (len <= tmp) - return 0; - addr += tmp; - len -= tmp; - } - len = (len + 15) >> 4; - } - i = (PAGE_SIZE - (paddr & ~PAGE_MASK)) >> 4; - while (len--) - { - switch (cache) - { - case FLUSH_CACHE_DATA: - __asm__ __volatile__ ("nop\n\t" - ".chip 68040\n\t" - "cpushl %%dc,(%0)\n\t" - ".chip 68k" - : : "a" (paddr)); - break; - case FLUSH_CACHE_INSN: - __asm__ __volatile__ ("nop\n\t" - ".chip 68040\n\t" - "cpushl %%ic,(%0)\n\t" - ".chip 68k" - : : "a" (paddr)); - break; - default: - case FLUSH_CACHE_BOTH: - __asm__ __volatile__ ("nop\n\t" - ".chip 68040\n\t" - "cpushl %%bc,(%0)\n\t" - ".chip 68k" - : : "a" (paddr)); - break; - } - if (!--i && len) - { - /* - * No need to page align here since it is done by - * virt_to_phys_040(). - */ - addr += PAGE_SIZE; - i = PAGE_SIZE / 16; - /* Recompute physical address when crossing a page - boundary. */ - for (;;) - { - if ((paddr = virt_to_phys_040(addr))) - break; - if (len <= i) - return 0; - len -= i; - addr += PAGE_SIZE; - } - } - else - paddr += 16; - } - break; - - default: - case FLUSH_SCOPE_PAGE: - len += (addr & ~PAGE_MASK) + (PAGE_SIZE - 1); - for (len >>= PAGE_SHIFT; len--; addr += PAGE_SIZE) - { - if (!(paddr = virt_to_phys_040(addr))) - continue; - switch (cache) - { - case FLUSH_CACHE_DATA: - __asm__ __volatile__ ("nop\n\t" - ".chip 68040\n\t" - "cpushp %%dc,(%0)\n\t" - ".chip 68k" - : : "a" (paddr)); - break; - case FLUSH_CACHE_INSN: - __asm__ __volatile__ ("nop\n\t" - ".chip 68040\n\t" - "cpushp %%ic,(%0)\n\t" - ".chip 68k" - : : "a" (paddr)); - break; - default: - case FLUSH_CACHE_BOTH: - __asm__ __volatile__ ("nop\n\t" - ".chip 68040\n\t" - "cpushp %%bc,(%0)\n\t" - ".chip 68k" - : : "a" (paddr)); - break; - } - } - break; - } - return 0; -} - -#define virt_to_phys_060(vaddr) \ -({ \ - unsigned long paddr; \ - __asm__ __volatile__ (".chip 68060\n\t" \ - "plpar (%0)\n\t" \ - ".chip 68k" \ - : "=a" (paddr) \ - : "0" (vaddr)); \ - (paddr); /* XXX */ \ -}) - -static inline int -cache_flush_060 (unsigned long addr, int scope, int cache, unsigned long len) -{ - unsigned long paddr, i; - - /* - * 68060 manual says: - * cpush %dc : flush DC, remains valid (with our %cacr setup) - * cpush %ic : invalidate IC - * cpush %bc : flush DC + invalidate IC - */ - switch (scope) - { - case FLUSH_SCOPE_ALL: - switch (cache) - { - case FLUSH_CACHE_DATA: - __asm__ __volatile__ (".chip 68060\n\t" - "cpusha %dc\n\t" - ".chip 68k"); - break; - case FLUSH_CACHE_INSN: - __asm__ __volatile__ (".chip 68060\n\t" - "cpusha %ic\n\t" - ".chip 68k"); - break; - default: - case FLUSH_CACHE_BOTH: - __asm__ __volatile__ (".chip 68060\n\t" - "cpusha %bc\n\t" - ".chip 68k"); - break; - } - break; - - case FLUSH_SCOPE_LINE: - /* Find the physical address of the first mapped page in the - address range. */ - len += addr & 15; - addr &= -16; - if (!(paddr = virt_to_phys_060(addr))) { - unsigned long tmp = PAGE_SIZE - (addr & ~PAGE_MASK); - - if (len <= tmp) - return 0; - addr += tmp; - len -= tmp; - tmp = PAGE_SIZE; - for (;;) - { - if ((paddr = virt_to_phys_060(addr))) - break; - if (len <= tmp) - return 0; - addr += tmp; - len -= tmp; - } - } - len = (len + 15) >> 4; - i = (PAGE_SIZE - (paddr & ~PAGE_MASK)) >> 4; - while (len--) - { - switch (cache) - { - case FLUSH_CACHE_DATA: - __asm__ __volatile__ (".chip 68060\n\t" - "cpushl %%dc,(%0)\n\t" - ".chip 68k" - : : "a" (paddr)); - break; - case FLUSH_CACHE_INSN: - __asm__ __volatile__ (".chip 68060\n\t" - "cpushl %%ic,(%0)\n\t" - ".chip 68k" - : : "a" (paddr)); - break; - default: - case FLUSH_CACHE_BOTH: - __asm__ __volatile__ (".chip 68060\n\t" - "cpushl %%bc,(%0)\n\t" - ".chip 68k" - : : "a" (paddr)); - break; - } - if (!--i && len) - { - - /* - * We just want to jump to the first cache line - * in the next page. - */ - addr += PAGE_SIZE; - addr &= PAGE_MASK; - - i = PAGE_SIZE / 16; - /* Recompute physical address when crossing a page - boundary. */ - for (;;) - { - if ((paddr = virt_to_phys_060(addr))) - break; - if (len <= i) - return 0; - len -= i; - addr += PAGE_SIZE; - } - } - else - paddr += 16; - } - break; - - default: - case FLUSH_SCOPE_PAGE: - len += (addr & ~PAGE_MASK) + (PAGE_SIZE - 1); - addr &= PAGE_MASK; /* Workaround for bug in some - revisions of the 68060 */ - for (len >>= PAGE_SHIFT; len--; addr += PAGE_SIZE) - { - if (!(paddr = virt_to_phys_060(addr))) - continue; - switch (cache) - { - case FLUSH_CACHE_DATA: - __asm__ __volatile__ (".chip 68060\n\t" - "cpushp %%dc,(%0)\n\t" - ".chip 68k" - : : "a" (paddr)); - break; - case FLUSH_CACHE_INSN: - __asm__ __volatile__ (".chip 68060\n\t" - "cpushp %%ic,(%0)\n\t" - ".chip 68k" - : : "a" (paddr)); - break; - default: - case FLUSH_CACHE_BOTH: - __asm__ __volatile__ (".chip 68060\n\t" - "cpushp %%bc,(%0)\n\t" - ".chip 68k" - : : "a" (paddr)); - break; - } - } - break; - } - return 0; -} - -/* sys_cacheflush -- flush (part of) the processor cache. */ -asmlinkage int -sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len) -{ - struct vm_area_struct *vma; - int ret = -EINVAL; - - if (scope < FLUSH_SCOPE_LINE || scope > FLUSH_SCOPE_ALL || - cache & ~FLUSH_CACHE_BOTH) - goto out; - - if (scope == FLUSH_SCOPE_ALL) { - /* Only the superuser may explicitly flush the whole cache. */ - ret = -EPERM; - if (!capable(CAP_SYS_ADMIN)) - goto out; - } else { - /* - * Verify that the specified address region actually belongs - * to this process. - */ - vma = find_vma (current->mm, addr); - ret = -EINVAL; - /* Check for overflow. */ - if (addr + len < addr) - goto out; - if (vma == NULL || addr < vma->vm_start || addr + len > vma->vm_end) - goto out; - } - - if (CPU_IS_020_OR_030) { - if (scope == FLUSH_SCOPE_LINE && len < 256) { - unsigned long cacr; - __asm__ ("movec %%cacr, %0" : "=r" (cacr)); - if (cache & FLUSH_CACHE_INSN) - cacr |= 4; - if (cache & FLUSH_CACHE_DATA) - cacr |= 0x400; - len >>= 2; - while (len--) { - __asm__ __volatile__ ("movec %1, %%caar\n\t" - "movec %0, %%cacr" - : /* no outputs */ - : "r" (cacr), "r" (addr)); - addr += 4; - } - } else { - /* Flush the whole cache, even if page granularity requested. */ - unsigned long cacr; - __asm__ ("movec %%cacr, %0" : "=r" (cacr)); - if (cache & FLUSH_CACHE_INSN) - cacr |= 8; - if (cache & FLUSH_CACHE_DATA) - cacr |= 0x800; - __asm__ __volatile__ ("movec %0, %%cacr" : : "r" (cacr)); - } - ret = 0; - goto out; - } else { - /* - * 040 or 060: don't blindly trust 'scope', someone could - * try to flush a few megs of memory. - */ - - if (len>=3*PAGE_SIZE && scope<FLUSH_SCOPE_PAGE) - scope=FLUSH_SCOPE_PAGE; - if (len>=10*PAGE_SIZE && scope<FLUSH_SCOPE_ALL) - scope=FLUSH_SCOPE_ALL; - if (CPU_IS_040) { - ret = cache_flush_040 (addr, scope, cache, len); - } else if (CPU_IS_060) { - ret = cache_flush_060 (addr, scope, cache, len); - } - } -out: - return ret; -} - -asmlinkage int sys_getpagesize(void) -{ - return PAGE_SIZE; -} - -/* - * Do a system call from kernel instead of calling sys_execve so we - * end up with proper pt_regs. - */ -int kernel_execve(const char *filename, - const char *const argv[], - const char *const envp[]) -{ - register long __res asm ("%d0") = __NR_execve; - register long __a asm ("%d1") = (long)(filename); - register long __b asm ("%d2") = (long)(argv); - register long __c asm ("%d3") = (long)(envp); - asm volatile ("trap #0" : "+d" (__res) - : "d" (__a), "d" (__b), "d" (__c)); - return __res; -} - -asmlinkage unsigned long sys_get_thread_area(void) -{ - return current_thread_info()->tp_value; -} - -asmlinkage int sys_set_thread_area(unsigned long tp) -{ - current_thread_info()->tp_value = tp; - return 0; -} - -/* This syscall gets its arguments in A0 (mem), D2 (oldval) and - D1 (newval). */ -asmlinkage int -sys_atomic_cmpxchg_32(unsigned long newval, int oldval, int d3, int d4, int d5, - unsigned long __user * mem) -{ - /* This was borrowed from ARM's implementation. */ - for (;;) { - struct mm_struct *mm = current->mm; - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - spinlock_t *ptl; - unsigned long mem_value; - - down_read(&mm->mmap_sem); - pgd = pgd_offset(mm, (unsigned long)mem); - if (!pgd_present(*pgd)) - goto bad_access; - pmd = pmd_offset(pgd, (unsigned long)mem); - if (!pmd_present(*pmd)) - goto bad_access; - pte = pte_offset_map_lock(mm, pmd, (unsigned long)mem, &ptl); - if (!pte_present(*pte) || !pte_dirty(*pte) - || !pte_write(*pte)) { - pte_unmap_unlock(pte, ptl); - goto bad_access; - } - - mem_value = *mem; - if (mem_value == oldval) - *mem = newval; - - pte_unmap_unlock(pte, ptl); - up_read(&mm->mmap_sem); - return mem_value; - - bad_access: - up_read(&mm->mmap_sem); - /* This is not necessarily a bad access, we can get here if - a memory we're trying to write to should be copied-on-write. - Make the kernel do the necessary page stuff, then re-iterate. - Simulate a write access fault to do that. */ - { - /* The first argument of the function corresponds to - D1, which is the first field of struct pt_regs. */ - struct pt_regs *fp = (struct pt_regs *)&newval; - - /* '3' is an RMW flag. */ - if (do_page_fault(fp, (unsigned long)mem, 3)) - /* If the do_page_fault() failed, we don't - have anything meaningful to return. - There should be a SIGSEGV pending for - the process. */ - return 0xdeadbeef; - } - } -} - -asmlinkage int sys_atomic_barrier(void) -{ - /* no code needed for uniprocs */ - return 0; -} +#ifdef CONFIG_MMU +#include "sys_m68k_mm.c" +#else +#include "sys_m68k_no.c" +#endif diff --git a/arch/m68k/kernel/sys_m68k_mm.c b/arch/m68k/kernel/sys_m68k_mm.c new file mode 100644 index 00000000000..3db2e7f902a --- /dev/null +++ b/arch/m68k/kernel/sys_m68k_mm.c @@ -0,0 +1,546 @@ +/* + * linux/arch/m68k/kernel/sys_m68k.c + * + * This file contains various random system calls that + * have a non-standard calling sequence on the Linux/m68k + * platform. + */ + +#include <linux/capability.h> +#include <linux/errno.h> +#include <linux/sched.h> +#include <linux/mm.h> +#include <linux/fs.h> +#include <linux/smp.h> +#include <linux/sem.h> +#include <linux/msg.h> +#include <linux/shm.h> +#include <linux/stat.h> +#include <linux/syscalls.h> +#include <linux/mman.h> +#include <linux/file.h> +#include <linux/ipc.h> + +#include <asm/setup.h> +#include <asm/uaccess.h> +#include <asm/cachectl.h> +#include <asm/traps.h> +#include <asm/page.h> +#include <asm/unistd.h> +#include <linux/elf.h> +#include <asm/tlb.h> + +asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address, + unsigned long error_code); + +asmlinkage long sys_mmap2(unsigned long addr, unsigned long len, + unsigned long prot, unsigned long flags, + unsigned long fd, unsigned long pgoff) +{ + /* + * This is wrong for sun3 - there PAGE_SIZE is 8Kb, + * so we need to shift the argument down by 1; m68k mmap64(3) + * (in libc) expects the last argument of mmap2 in 4Kb units. + */ + return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff); +} + +/* Convert virtual (user) address VADDR to physical address PADDR */ +#define virt_to_phys_040(vaddr) \ +({ \ + unsigned long _mmusr, _paddr; \ + \ + __asm__ __volatile__ (".chip 68040\n\t" \ + "ptestr (%1)\n\t" \ + "movec %%mmusr,%0\n\t" \ + ".chip 68k" \ + : "=r" (_mmusr) \ + : "a" (vaddr)); \ + _paddr = (_mmusr & MMU_R_040) ? (_mmusr & PAGE_MASK) : 0; \ + _paddr; \ +}) + +static inline int +cache_flush_040 (unsigned long addr, int scope, int cache, unsigned long len) +{ + unsigned long paddr, i; + + switch (scope) + { + case FLUSH_SCOPE_ALL: + switch (cache) + { + case FLUSH_CACHE_DATA: + /* This nop is needed for some broken versions of the 68040. */ + __asm__ __volatile__ ("nop\n\t" + ".chip 68040\n\t" + "cpusha %dc\n\t" + ".chip 68k"); + break; + case FLUSH_CACHE_INSN: + __asm__ __volatile__ ("nop\n\t" + ".chip 68040\n\t" + "cpusha %ic\n\t" + ".chip 68k"); + break; + default: + case FLUSH_CACHE_BOTH: + __asm__ __volatile__ ("nop\n\t" + ".chip 68040\n\t" + "cpusha %bc\n\t" + ".chip 68k"); + break; + } + break; + + case FLUSH_SCOPE_LINE: + /* Find the physical address of the first mapped page in the + address range. */ + if ((paddr = virt_to_phys_040(addr))) { + paddr += addr & ~(PAGE_MASK | 15); + len = (len + (addr & 15) + 15) >> 4; + } else { + unsigned long tmp = PAGE_SIZE - (addr & ~PAGE_MASK); + + if (len <= tmp) + return 0; + addr += tmp; + len -= tmp; + tmp = PAGE_SIZE; + for (;;) + { + if ((paddr = virt_to_phys_040(addr))) + break; + if (len <= tmp) + return 0; + addr += tmp; + len -= tmp; + } + len = (len + 15) >> 4; + } + i = (PAGE_SIZE - (paddr & ~PAGE_MASK)) >> 4; + while (len--) + { + switch (cache) + { + case FLUSH_CACHE_DATA: + __asm__ __volatile__ ("nop\n\t" + ".chip 68040\n\t" + "cpushl %%dc,(%0)\n\t" + ".chip 68k" + : : "a" (paddr)); + break; + case FLUSH_CACHE_INSN: + __asm__ __volatile__ ("nop\n\t" + ".chip 68040\n\t" + "cpushl %%ic,(%0)\n\t" + ".chip 68k" + : : "a" (paddr)); + break; + default: + case FLUSH_CACHE_BOTH: + __asm__ __volatile__ ("nop\n\t" + ".chip 68040\n\t" + "cpushl %%bc,(%0)\n\t" + ".chip 68k" + : : "a" (paddr)); + break; + } + if (!--i && len) + { + /* + * No need to page align here since it is done by + * virt_to_phys_040(). + */ + addr += PAGE_SIZE; + i = PAGE_SIZE / 16; + /* Recompute physical address when crossing a page + boundary. */ + for (;;) + { + if ((paddr = virt_to_phys_040(addr))) + break; + if (len <= i) + return 0; + len -= i; + addr += PAGE_SIZE; + } + } + else + paddr += 16; + } + break; + + default: + case FLUSH_SCOPE_PAGE: + len += (addr & ~PAGE_MASK) + (PAGE_SIZE - 1); + for (len >>= PAGE_SHIFT; len--; addr += PAGE_SIZE) + { + if (!(paddr = virt_to_phys_040(addr))) + continue; + switch (cache) + { + case FLUSH_CACHE_DATA: + __asm__ __volatile__ ("nop\n\t" + ".chip 68040\n\t" + "cpushp %%dc,(%0)\n\t" + ".chip 68k" + : : "a" (paddr)); + break; + case FLUSH_CACHE_INSN: + __asm__ __volatile__ ("nop\n\t" + ".chip 68040\n\t" + "cpushp %%ic,(%0)\n\t" + ".chip 68k" + : : "a" (paddr)); + break; + default: + case FLUSH_CACHE_BOTH: + __asm__ __volatile__ ("nop\n\t" + ".chip 68040\n\t" + "cpushp %%bc,(%0)\n\t" + ".chip 68k" + : : "a" (paddr)); + break; + } + } + break; + } + return 0; +} + +#define virt_to_phys_060(vaddr) \ +({ \ + unsigned long paddr; \ + __asm__ __volatile__ (".chip 68060\n\t" \ + "plpar (%0)\n\t" \ + ".chip 68k" \ + : "=a" (paddr) \ + : "0" (vaddr)); \ + (paddr); /* XXX */ \ +}) + +static inline int +cache_flush_060 (unsigned long addr, int scope, int cache, unsigned long len) +{ + unsigned long paddr, i; + + /* + * 68060 manual says: + * cpush %dc : flush DC, remains valid (with our %cacr setup) + * cpush %ic : invalidate IC + * cpush %bc : flush DC + invalidate IC + */ + switch (scope) + { + case FLUSH_SCOPE_ALL: + switch (cache) + { + case FLUSH_CACHE_DATA: + __asm__ __volatile__ (".chip 68060\n\t" + "cpusha %dc\n\t" + ".chip 68k"); + break; + case FLUSH_CACHE_INSN: + __asm__ __volatile__ (".chip 68060\n\t" + "cpusha %ic\n\t" + ".chip 68k"); + break; + default: + case FLUSH_CACHE_BOTH: + __asm__ __volatile__ (".chip 68060\n\t" + "cpusha %bc\n\t" + ".chip 68k"); + break; + } + break; + + case FLUSH_SCOPE_LINE: + /* Find the physical address of the first mapped page in the + address range. */ + len += addr & 15; + addr &= -16; + if (!(paddr = virt_to_phys_060(addr))) { + unsigned long tmp = PAGE_SIZE - (addr & ~PAGE_MASK); + + if (len <= tmp) + return 0; + addr += tmp; + len -= tmp; + tmp = PAGE_SIZE; + for (;;) + { + if ((paddr = virt_to_phys_060(addr))) + break; + if (len <= tmp) + return 0; + addr += tmp; + len -= tmp; + } + } + len = (len + 15) >> 4; + i = (PAGE_SIZE - (paddr & ~PAGE_MASK)) >> 4; + while (len--) + { + switch (cache) + { + case FLUSH_CACHE_DATA: + __asm__ __volatile__ (".chip 68060\n\t" + "cpushl %%dc,(%0)\n\t" + ".chip 68k" + : : "a" (paddr)); + break; + case FLUSH_CACHE_INSN: + __asm__ __volatile__ (".chip 68060\n\t" + "cpushl %%ic,(%0)\n\t" + ".chip 68k" + : : "a" (paddr)); + break; + default: + case FLUSH_CACHE_BOTH: + __asm__ __volatile__ (".chip 68060\n\t" + "cpushl %%bc,(%0)\n\t" + ".chip 68k" + : : "a" (paddr)); + break; + } + if (!--i && len) + { + + /* + * We just want to jump to the first cache line + * in the next page. + */ + addr += PAGE_SIZE; + addr &= PAGE_MASK; + + i = PAGE_SIZE / 16; + /* Recompute physical address when crossing a page + boundary. */ + for (;;) + { + if ((paddr = virt_to_phys_060(addr))) + break; + if (len <= i) + return 0; + len -= i; + addr += PAGE_SIZE; + } + } + else + paddr += 16; + } + break; + + default: + case FLUSH_SCOPE_PAGE: + len += (addr & ~PAGE_MASK) + (PAGE_SIZE - 1); + addr &= PAGE_MASK; /* Workaround for bug in some + revisions of the 68060 */ + for (len >>= PAGE_SHIFT; len--; addr += PAGE_SIZE) + { + if (!(paddr = virt_to_phys_060(addr))) + continue; + switch (cache) + { + case FLUSH_CACHE_DATA: + __asm__ __volatile__ (".chip 68060\n\t" + "cpushp %%dc,(%0)\n\t" + ".chip 68k" + : : "a" (paddr)); + break; + case FLUSH_CACHE_INSN: + __asm__ __volatile__ (".chip 68060\n\t" + "cpushp %%ic,(%0)\n\t" + ".chip 68k" + : : "a" (paddr)); + break; + default: + case FLUSH_CACHE_BOTH: + __asm__ __volatile__ (".chip 68060\n\t" + "cpushp %%bc,(%0)\n\t" + ".chip 68k" + : : "a" (paddr)); + break; + } + } + break; + } + return 0; +} + +/* sys_cacheflush -- flush (part of) the processor cache. */ +asmlinkage int +sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len) +{ + struct vm_area_struct *vma; + int ret = -EINVAL; + + if (scope < FLUSH_SCOPE_LINE || scope > FLUSH_SCOPE_ALL || + cache & ~FLUSH_CACHE_BOTH) + goto out; + + if (scope == FLUSH_SCOPE_ALL) { + /* Only the superuser may explicitly flush the whole cache. */ + ret = -EPERM; + if (!capable(CAP_SYS_ADMIN)) + goto out; + } else { + /* + * Verify that the specified address region actually belongs + * to this process. + */ + vma = find_vma (current->mm, addr); + ret = -EINVAL; + /* Check for overflow. */ + if (addr + len < addr) + goto out; + if (vma == NULL || addr < vma->vm_start || addr + len > vma->vm_end) + goto out; + } + + if (CPU_IS_020_OR_030) { + if (scope == FLUSH_SCOPE_LINE && len < 256) { + unsigned long cacr; + __asm__ ("movec %%cacr, %0" : "=r" (cacr)); + if (cache & FLUSH_CACHE_INSN) + cacr |= 4; + if (cache & FLUSH_CACHE_DATA) + cacr |= 0x400; + len >>= 2; + while (len--) { + __asm__ __volatile__ ("movec %1, %%caar\n\t" + "movec %0, %%cacr" + : /* no outputs */ + : "r" (cacr), "r" (addr)); + addr += 4; + } + } else { + /* Flush the whole cache, even if page granularity requested. */ + unsigned long cacr; + __asm__ ("movec %%cacr, %0" : "=r" (cacr)); + if (cache & FLUSH_CACHE_INSN) + cacr |= 8; + if (cache & FLUSH_CACHE_DATA) + cacr |= 0x800; + __asm__ __volatile__ ("movec %0, %%cacr" : : "r" (cacr)); + } + ret = 0; + goto out; + } else { + /* + * 040 or 060: don't blindly trust 'scope', someone could + * try to flush a few megs of memory. + */ + + if (len>=3*PAGE_SIZE && scope<FLUSH_SCOPE_PAGE) + scope=FLUSH_SCOPE_PAGE; + if (len>=10*PAGE_SIZE && scope<FLUSH_SCOPE_ALL) + scope=FLUSH_SCOPE_ALL; + if (CPU_IS_040) { + ret = cache_flush_040 (addr, scope, cache, len); + } else if (CPU_IS_060) { + ret = cache_flush_060 (addr, scope, cache, len); + } + } +out: + return ret; +} + +asmlinkage int sys_getpagesize(void) +{ + return PAGE_SIZE; +} + +/* + * Do a system call from kernel instead of calling sys_execve so we + * end up with proper pt_regs. + */ +int kernel_execve(const char *filename, + const char *const argv[], + const char *const envp[]) +{ + register long __res asm ("%d0") = __NR_execve; + register long __a asm ("%d1") = (long)(filename); + register long __b asm ("%d2") = (long)(argv); + register long __c asm ("%d3") = (long)(envp); + asm volatile ("trap #0" : "+d" (__res) + : "d" (__a), "d" (__b), "d" (__c)); + return __res; +} + +asmlinkage unsigned long sys_get_thread_area(void) +{ + return current_thread_info()->tp_value; +} + +asmlinkage int sys_set_thread_area(unsigned long tp) +{ + current_thread_info()->tp_value = tp; + return 0; +} + +/* This syscall gets its arguments in A0 (mem), D2 (oldval) and + D1 (newval). */ +asmlinkage int +sys_atomic_cmpxchg_32(unsigned long newval, int oldval, int d3, int d4, int d5, + unsigned long __user * mem) +{ + /* This was borrowed from ARM's implementation. */ + for (;;) { + struct mm_struct *mm = current->mm; + pgd_t *pgd; + pmd_t *pmd; + pte_t *pte; + spinlock_t *ptl; + unsigned long mem_value; + + down_read(&mm->mmap_sem); + pgd = pgd_offset(mm, (unsigned long)mem); + if (!pgd_present(*pgd)) + goto bad_access; + pmd = pmd_offset(pgd, (unsigned long)mem); + if (!pmd_present(*pmd)) + goto bad_access; + pte = pte_offset_map_lock(mm, pmd, (unsigned long)mem, &ptl); + if (!pte_present(*pte) || !pte_dirty(*pte) + || !pte_write(*pte)) { + pte_unmap_unlock(pte, ptl); + goto bad_access; + } + + mem_value = *mem; + if (mem_value == oldval) + *mem = newval; + + pte_unmap_unlock(pte, ptl); + up_read(&mm->mmap_sem); + return mem_value; + + bad_access: + up_read(&mm->mmap_sem); + /* This is not necessarily a bad access, we can get here if + a memory we're trying to write to should be copied-on-write. + Make the kernel do the necessary page stuff, then re-iterate. + Simulate a write access fault to do that. */ + { + /* The first argument of the function corresponds to + D1, which is the first field of struct pt_regs. */ + struct pt_regs *fp = (struct pt_regs *)&newval; + + /* '3' is an RMW flag. */ + if (do_page_fault(fp, (unsigned long)mem, 3)) + /* If the do_page_fault() failed, we don't + have anything meaningful to return. + There should be a SIGSEGV pending for + the process. */ + return 0xdeadbeef; + } + } +} + +asmlinkage int sys_atomic_barrier(void) +{ + /* no code needed for uniprocs */ + return 0; +} diff --git a/arch/m68knommu/kernel/sys_m68k.c b/arch/m68k/kernel/sys_m68k_no.c index 68488ae47f0..68488ae47f0 100644 --- a/arch/m68knommu/kernel/sys_m68k.c +++ b/arch/m68k/kernel/sys_m68k_no.c diff --git a/arch/m68knommu/kernel/syscalltable.S b/arch/m68k/kernel/syscalltable.S index 79b1ed198c0..9b8393d8adb 100644 --- a/arch/m68knommu/kernel/syscalltable.S +++ b/arch/m68k/kernel/syscalltable.S @@ -358,6 +358,10 @@ ENTRY(sys_call_table) .long sys_fanotify_init .long sys_fanotify_mark .long sys_prlimit64 + .long sys_name_to_handle_at /* 340 */ + .long sys_open_by_handle_at + .long sys_clock_adjtime + .long sys_syncfs .rept NR_syscalls-(.-sys_call_table)/4 .long sys_ni_syscall diff --git a/arch/m68k/kernel/time.c b/arch/m68k/kernel/time.c index 18b34ee5db3..a5cf40c26de 100644 --- a/arch/m68k/kernel/time.c +++ b/arch/m68k/kernel/time.c @@ -1,114 +1,5 @@ -/* - * linux/arch/m68k/kernel/time.c - * - * Copyright (C) 1991, 1992, 1995 Linus Torvalds - * - * This file contains the m68k-specific time handling details. - * Most of the stuff is located in the machine specific files. - * - * 1997-09-10 Updated NTP code according to technical memorandum Jan '96 - * "A Kernel Model for Precision Timekeeping" by Dave Mills - */ - -#include <linux/errno.h> -#include <linux/module.h> -#include <linux/sched.h> -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/string.h> -#include <linux/mm.h> -#include <linux/rtc.h> -#include <linux/platform_device.h> - -#include <asm/machdep.h> -#include <asm/io.h> -#include <asm/irq_regs.h> - -#include <linux/time.h> -#include <linux/timex.h> -#include <linux/profile.h> - -static inline int set_rtc_mmss(unsigned long nowtime) -{ - if (mach_set_clock_mmss) - return mach_set_clock_mmss (nowtime); - return -1; -} - -/* - * timer_interrupt() needs to keep up the real-time clock, - * as well as call the "xtime_update()" routine every clocktick - */ -static irqreturn_t timer_interrupt(int irq, void *dummy) -{ - xtime_update(1); - update_process_times(user_mode(get_irq_regs())); - profile_tick(CPU_PROFILING); - -#ifdef CONFIG_HEARTBEAT - /* use power LED as a heartbeat instead -- much more useful - for debugging -- based on the version for PReP by Cort */ - /* acts like an actual heart beat -- ie thump-thump-pause... */ - if (mach_heartbeat) { - static unsigned cnt = 0, period = 0, dist = 0; - - if (cnt == 0 || cnt == dist) - mach_heartbeat( 1 ); - else if (cnt == 7 || cnt == dist+7) - mach_heartbeat( 0 ); - - if (++cnt > period) { - cnt = 0; - /* The hyperbolic function below modifies the heartbeat period - * length in dependency of the current (5min) load. It goes - * through the points f(0)=126, f(1)=86, f(5)=51, - * f(inf)->30. */ - period = ((672<<FSHIFT)/(5*avenrun[0]+(7<<FSHIFT))) + 30; - dist = period / 4; - } - } -#endif /* CONFIG_HEARTBEAT */ - return IRQ_HANDLED; -} - -void read_persistent_clock(struct timespec *ts) -{ - struct rtc_time time; - ts->tv_sec = 0; - ts->tv_nsec = 0; - - if (mach_hwclk) { - mach_hwclk(0, &time); - - if ((time.tm_year += 1900) < 1970) - time.tm_year += 100; - ts->tv_sec = mktime(time.tm_year, time.tm_mon, time.tm_mday, - time.tm_hour, time.tm_min, time.tm_sec); - } -} - -void __init time_init(void) -{ - mach_sched_init(timer_interrupt); -} - -u32 arch_gettimeoffset(void) -{ - return mach_gettimeoffset() * 1000; -} - -static int __init rtc_init(void) -{ - struct platform_device *pdev; - - if (!mach_hwclk) - return -ENODEV; - - pdev = platform_device_register_simple("rtc-generic", -1, NULL, 0); - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - return 0; -} - -module_init(rtc_init); +#ifdef CONFIG_MMU +#include "time_mm.c" +#else +#include "time_no.c" +#endif diff --git a/arch/m68k/kernel/time_mm.c b/arch/m68k/kernel/time_mm.c new file mode 100644 index 00000000000..18b34ee5db3 --- /dev/null +++ b/arch/m68k/kernel/time_mm.c @@ -0,0 +1,114 @@ +/* + * linux/arch/m68k/kernel/time.c + * + * Copyright (C) 1991, 1992, 1995 Linus Torvalds + * + * This file contains the m68k-specific time handling details. + * Most of the stuff is located in the machine specific files. + * + * 1997-09-10 Updated NTP code according to technical memorandum Jan '96 + * "A Kernel Model for Precision Timekeeping" by Dave Mills + */ + +#include <linux/errno.h> +#include <linux/module.h> +#include <linux/sched.h> +#include <linux/kernel.h> +#include <linux/param.h> +#include <linux/string.h> +#include <linux/mm.h> +#include <linux/rtc.h> +#include <linux/platform_device.h> + +#include <asm/machdep.h> +#include <asm/io.h> +#include <asm/irq_regs.h> + +#include <linux/time.h> +#include <linux/timex.h> +#include <linux/profile.h> + +static inline int set_rtc_mmss(unsigned long nowtime) +{ + if (mach_set_clock_mmss) + return mach_set_clock_mmss (nowtime); + return -1; +} + +/* + * timer_interrupt() needs to keep up the real-time clock, + * as well as call the "xtime_update()" routine every clocktick + */ +static irqreturn_t timer_interrupt(int irq, void *dummy) +{ + xtime_update(1); + update_process_times(user_mode(get_irq_regs())); + profile_tick(CPU_PROFILING); + +#ifdef CONFIG_HEARTBEAT + /* use power LED as a heartbeat instead -- much more useful + for debugging -- based on the version for PReP by Cort */ + /* acts like an actual heart beat -- ie thump-thump-pause... */ + if (mach_heartbeat) { + static unsigned cnt = 0, period = 0, dist = 0; + + if (cnt == 0 || cnt == dist) + mach_heartbeat( 1 ); + else if (cnt == 7 || cnt == dist+7) + mach_heartbeat( 0 ); + + if (++cnt > period) { + cnt = 0; + /* The hyperbolic function below modifies the heartbeat period + * length in dependency of the current (5min) load. It goes + * through the points f(0)=126, f(1)=86, f(5)=51, + * f(inf)->30. */ + period = ((672<<FSHIFT)/(5*avenrun[0]+(7<<FSHIFT))) + 30; + dist = period / 4; + } + } +#endif /* CONFIG_HEARTBEAT */ + return IRQ_HANDLED; +} + +void read_persistent_clock(struct timespec *ts) +{ + struct rtc_time time; + ts->tv_sec = 0; + ts->tv_nsec = 0; + + if (mach_hwclk) { + mach_hwclk(0, &time); + + if ((time.tm_year += 1900) < 1970) + time.tm_year += 100; + ts->tv_sec = mktime(time.tm_year, time.tm_mon, time.tm_mday, + time.tm_hour, time.tm_min, time.tm_sec); + } +} + +void __init time_init(void) +{ + mach_sched_init(timer_interrupt); +} + +u32 arch_gettimeoffset(void) +{ + return mach_gettimeoffset() * 1000; +} + +static int __init rtc_init(void) +{ + struct platform_device *pdev; + + if (!mach_hwclk) + return -ENODEV; + + pdev = platform_device_register_simple("rtc-generic", -1, NULL, 0); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + return 0; +} + +module_init(rtc_init); diff --git a/arch/m68knommu/kernel/time.c b/arch/m68k/kernel/time_no.c index 6623909f70e..6623909f70e 100644 --- a/arch/m68knommu/kernel/time.c +++ b/arch/m68k/kernel/time_no.c diff --git a/arch/m68k/kernel/traps.c b/arch/m68k/kernel/traps.c index 4022bbc2887..c98add3f5f0 100644 --- a/arch/m68k/kernel/traps.c +++ b/arch/m68k/kernel/traps.c @@ -1,1207 +1,5 @@ -/* - * linux/arch/m68k/kernel/traps.c - * - * Copyright (C) 1993, 1994 by Hamish Macdonald - * - * 68040 fixes by Michael Rausch - * 68040 fixes by Martin Apel - * 68040 fixes and writeback by Richard Zidlicky - * 68060 fixes by Roman Hodek - * 68060 fixes by Jesper Skov - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -/* - * Sets up all exception vectors - */ - -#include <linux/sched.h> -#include <linux/signal.h> -#include <linux/kernel.h> -#include <linux/mm.h> -#include <linux/module.h> -#include <linux/user.h> -#include <linux/string.h> -#include <linux/linkage.h> -#include <linux/init.h> -#include <linux/ptrace.h> -#include <linux/kallsyms.h> - -#include <asm/setup.h> -#include <asm/fpu.h> -#include <asm/system.h> -#include <asm/uaccess.h> -#include <asm/traps.h> -#include <asm/pgalloc.h> -#include <asm/machdep.h> -#include <asm/siginfo.h> - -/* assembler routines */ -asmlinkage void system_call(void); -asmlinkage void buserr(void); -asmlinkage void trap(void); -asmlinkage void nmihandler(void); -#ifdef CONFIG_M68KFPU_EMU -asmlinkage void fpu_emu(void); -#endif - -e_vector vectors[256]; - -/* nmi handler for the Amiga */ -asm(".text\n" - __ALIGN_STR "\n" - "nmihandler: rte"); - -/* - * this must be called very early as the kernel might - * use some instruction that are emulated on the 060 - * and so we're prepared for early probe attempts (e.g. nf_init). - */ -void __init base_trap_init(void) -{ - if (MACH_IS_SUN3X) { - extern e_vector *sun3x_prom_vbr; - - __asm__ volatile ("movec %%vbr, %0" : "=r" (sun3x_prom_vbr)); - } - - /* setup the exception vector table */ - __asm__ volatile ("movec %0,%%vbr" : : "r" ((void*)vectors)); - - if (CPU_IS_060) { - /* set up ISP entry points */ - asmlinkage void unimp_vec(void) asm ("_060_isp_unimp"); - - vectors[VEC_UNIMPII] = unimp_vec; - } - - vectors[VEC_BUSERR] = buserr; - vectors[VEC_ILLEGAL] = trap; - vectors[VEC_SYS] = system_call; -} - -void __init trap_init (void) -{ - int i; - - for (i = VEC_SPUR; i <= VEC_INT7; i++) - vectors[i] = bad_inthandler; - - for (i = 0; i < VEC_USER; i++) - if (!vectors[i]) - vectors[i] = trap; - - for (i = VEC_USER; i < 256; i++) - vectors[i] = bad_inthandler; - -#ifdef CONFIG_M68KFPU_EMU - if (FPU_IS_EMU) - vectors[VEC_LINE11] = fpu_emu; -#endif - - if (CPU_IS_040 && !FPU_IS_EMU) { - /* set up FPSP entry points */ - asmlinkage void dz_vec(void) asm ("dz"); - asmlinkage void inex_vec(void) asm ("inex"); - asmlinkage void ovfl_vec(void) asm ("ovfl"); - asmlinkage void unfl_vec(void) asm ("unfl"); - asmlinkage void snan_vec(void) asm ("snan"); - asmlinkage void operr_vec(void) asm ("operr"); - asmlinkage void bsun_vec(void) asm ("bsun"); - asmlinkage void fline_vec(void) asm ("fline"); - asmlinkage void unsupp_vec(void) asm ("unsupp"); - - vectors[VEC_FPDIVZ] = dz_vec; - vectors[VEC_FPIR] = inex_vec; - vectors[VEC_FPOVER] = ovfl_vec; - vectors[VEC_FPUNDER] = unfl_vec; - vectors[VEC_FPNAN] = snan_vec; - vectors[VEC_FPOE] = operr_vec; - vectors[VEC_FPBRUC] = bsun_vec; - vectors[VEC_LINE11] = fline_vec; - vectors[VEC_FPUNSUP] = unsupp_vec; - } - - if (CPU_IS_060 && !FPU_IS_EMU) { - /* set up IFPSP entry points */ - asmlinkage void snan_vec6(void) asm ("_060_fpsp_snan"); - asmlinkage void operr_vec6(void) asm ("_060_fpsp_operr"); - asmlinkage void ovfl_vec6(void) asm ("_060_fpsp_ovfl"); - asmlinkage void unfl_vec6(void) asm ("_060_fpsp_unfl"); - asmlinkage void dz_vec6(void) asm ("_060_fpsp_dz"); - asmlinkage void inex_vec6(void) asm ("_060_fpsp_inex"); - asmlinkage void fline_vec6(void) asm ("_060_fpsp_fline"); - asmlinkage void unsupp_vec6(void) asm ("_060_fpsp_unsupp"); - asmlinkage void effadd_vec6(void) asm ("_060_fpsp_effadd"); - - vectors[VEC_FPNAN] = snan_vec6; - vectors[VEC_FPOE] = operr_vec6; - vectors[VEC_FPOVER] = ovfl_vec6; - vectors[VEC_FPUNDER] = unfl_vec6; - vectors[VEC_FPDIVZ] = dz_vec6; - vectors[VEC_FPIR] = inex_vec6; - vectors[VEC_LINE11] = fline_vec6; - vectors[VEC_FPUNSUP] = unsupp_vec6; - vectors[VEC_UNIMPEA] = effadd_vec6; - } - - /* if running on an amiga, make the NMI interrupt do nothing */ - if (MACH_IS_AMIGA) { - vectors[VEC_INT7] = nmihandler; - } -} - - -static const char *vec_names[] = { - [VEC_RESETSP] = "RESET SP", - [VEC_RESETPC] = "RESET PC", - [VEC_BUSERR] = "BUS ERROR", - [VEC_ADDRERR] = "ADDRESS ERROR", - [VEC_ILLEGAL] = "ILLEGAL INSTRUCTION", - [VEC_ZERODIV] = "ZERO DIVIDE", - [VEC_CHK] = "CHK", - [VEC_TRAP] = "TRAPcc", - [VEC_PRIV] = "PRIVILEGE VIOLATION", - [VEC_TRACE] = "TRACE", - [VEC_LINE10] = "LINE 1010", - [VEC_LINE11] = "LINE 1111", - [VEC_RESV12] = "UNASSIGNED RESERVED 12", - [VEC_COPROC] = "COPROCESSOR PROTOCOL VIOLATION", - [VEC_FORMAT] = "FORMAT ERROR", - [VEC_UNINT] = "UNINITIALIZED INTERRUPT", - [VEC_RESV16] = "UNASSIGNED RESERVED 16", - [VEC_RESV17] = "UNASSIGNED RESERVED 17", - [VEC_RESV18] = "UNASSIGNED RESERVED 18", - [VEC_RESV19] = "UNASSIGNED RESERVED 19", - [VEC_RESV20] = "UNASSIGNED RESERVED 20", - [VEC_RESV21] = "UNASSIGNED RESERVED 21", - [VEC_RESV22] = "UNASSIGNED RESERVED 22", - [VEC_RESV23] = "UNASSIGNED RESERVED 23", - [VEC_SPUR] = "SPURIOUS INTERRUPT", - [VEC_INT1] = "LEVEL 1 INT", - [VEC_INT2] = "LEVEL 2 INT", - [VEC_INT3] = "LEVEL 3 INT", - [VEC_INT4] = "LEVEL 4 INT", - [VEC_INT5] = "LEVEL 5 INT", - [VEC_INT6] = "LEVEL 6 INT", - [VEC_INT7] = "LEVEL 7 INT", - [VEC_SYS] = "SYSCALL", - [VEC_TRAP1] = "TRAP #1", - [VEC_TRAP2] = "TRAP #2", - [VEC_TRAP3] = "TRAP #3", - [VEC_TRAP4] = "TRAP #4", - [VEC_TRAP5] = "TRAP #5", - [VEC_TRAP6] = "TRAP #6", - [VEC_TRAP7] = "TRAP #7", - [VEC_TRAP8] = "TRAP #8", - [VEC_TRAP9] = "TRAP #9", - [VEC_TRAP10] = "TRAP #10", - [VEC_TRAP11] = "TRAP #11", - [VEC_TRAP12] = "TRAP #12", - [VEC_TRAP13] = "TRAP #13", - [VEC_TRAP14] = "TRAP #14", - [VEC_TRAP15] = "TRAP #15", - [VEC_FPBRUC] = "FPCP BSUN", - [VEC_FPIR] = "FPCP INEXACT", - [VEC_FPDIVZ] = "FPCP DIV BY 0", - [VEC_FPUNDER] = "FPCP UNDERFLOW", - [VEC_FPOE] = "FPCP OPERAND ERROR", - [VEC_FPOVER] = "FPCP OVERFLOW", - [VEC_FPNAN] = "FPCP SNAN", - [VEC_FPUNSUP] = "FPCP UNSUPPORTED OPERATION", - [VEC_MMUCFG] = "MMU CONFIGURATION ERROR", - [VEC_MMUILL] = "MMU ILLEGAL OPERATION ERROR", - [VEC_MMUACC] = "MMU ACCESS LEVEL VIOLATION ERROR", - [VEC_RESV59] = "UNASSIGNED RESERVED 59", - [VEC_UNIMPEA] = "UNASSIGNED RESERVED 60", - [VEC_UNIMPII] = "UNASSIGNED RESERVED 61", - [VEC_RESV62] = "UNASSIGNED RESERVED 62", - [VEC_RESV63] = "UNASSIGNED RESERVED 63", -}; - -static const char *space_names[] = { - [0] = "Space 0", - [USER_DATA] = "User Data", - [USER_PROGRAM] = "User Program", -#ifndef CONFIG_SUN3 - [3] = "Space 3", +#ifdef CONFIG_MMU +#include "traps_mm.c" #else - [FC_CONTROL] = "Control", -#endif - [4] = "Space 4", - [SUPER_DATA] = "Super Data", - [SUPER_PROGRAM] = "Super Program", - [CPU_SPACE] = "CPU" -}; - -void die_if_kernel(char *,struct pt_regs *,int); -asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address, - unsigned long error_code); -int send_fault_sig(struct pt_regs *regs); - -asmlinkage void trap_c(struct frame *fp); - -#if defined (CONFIG_M68060) -static inline void access_error060 (struct frame *fp) -{ - unsigned long fslw = fp->un.fmt4.pc; /* is really FSLW for access error */ - -#ifdef DEBUG - printk("fslw=%#lx, fa=%#lx\n", fslw, fp->un.fmt4.effaddr); -#endif - - if (fslw & MMU060_BPE) { - /* branch prediction error -> clear branch cache */ - __asm__ __volatile__ ("movec %/cacr,%/d0\n\t" - "orl #0x00400000,%/d0\n\t" - "movec %/d0,%/cacr" - : : : "d0" ); - /* return if there's no other error */ - if (!(fslw & MMU060_ERR_BITS) && !(fslw & MMU060_SEE)) - return; - } - - if (fslw & (MMU060_DESC_ERR | MMU060_WP | MMU060_SP)) { - unsigned long errorcode; - unsigned long addr = fp->un.fmt4.effaddr; - - if (fslw & MMU060_MA) - addr = (addr + PAGE_SIZE - 1) & PAGE_MASK; - - errorcode = 1; - if (fslw & MMU060_DESC_ERR) { - __flush_tlb040_one(addr); - errorcode = 0; - } - if (fslw & MMU060_W) - errorcode |= 2; -#ifdef DEBUG - printk("errorcode = %d\n", errorcode ); -#endif - do_page_fault(&fp->ptregs, addr, errorcode); - } else if (fslw & (MMU060_SEE)){ - /* Software Emulation Error. - * fault during mem_read/mem_write in ifpsp060/os.S - */ - send_fault_sig(&fp->ptregs); - } else if (!(fslw & (MMU060_RE|MMU060_WE)) || - send_fault_sig(&fp->ptregs) > 0) { - printk("pc=%#lx, fa=%#lx\n", fp->ptregs.pc, fp->un.fmt4.effaddr); - printk( "68060 access error, fslw=%lx\n", fslw ); - trap_c( fp ); - } -} -#endif /* CONFIG_M68060 */ - -#if defined (CONFIG_M68040) -static inline unsigned long probe040(int iswrite, unsigned long addr, int wbs) -{ - unsigned long mmusr; - mm_segment_t old_fs = get_fs(); - - set_fs(MAKE_MM_SEG(wbs)); - - if (iswrite) - asm volatile (".chip 68040; ptestw (%0); .chip 68k" : : "a" (addr)); - else - asm volatile (".chip 68040; ptestr (%0); .chip 68k" : : "a" (addr)); - - asm volatile (".chip 68040; movec %%mmusr,%0; .chip 68k" : "=r" (mmusr)); - - set_fs(old_fs); - - return mmusr; -} - -static inline int do_040writeback1(unsigned short wbs, unsigned long wba, - unsigned long wbd) -{ - int res = 0; - mm_segment_t old_fs = get_fs(); - - /* set_fs can not be moved, otherwise put_user() may oops */ - set_fs(MAKE_MM_SEG(wbs)); - - switch (wbs & WBSIZ_040) { - case BA_SIZE_BYTE: - res = put_user(wbd & 0xff, (char __user *)wba); - break; - case BA_SIZE_WORD: - res = put_user(wbd & 0xffff, (short __user *)wba); - break; - case BA_SIZE_LONG: - res = put_user(wbd, (int __user *)wba); - break; - } - - /* set_fs can not be moved, otherwise put_user() may oops */ - set_fs(old_fs); - - -#ifdef DEBUG - printk("do_040writeback1, res=%d\n",res); -#endif - - return res; -} - -/* after an exception in a writeback the stack frame corresponding - * to that exception is discarded, set a few bits in the old frame - * to simulate what it should look like - */ -static inline void fix_xframe040(struct frame *fp, unsigned long wba, unsigned short wbs) -{ - fp->un.fmt7.faddr = wba; - fp->un.fmt7.ssw = wbs & 0xff; - if (wba != current->thread.faddr) - fp->un.fmt7.ssw |= MA_040; -} - -static inline void do_040writebacks(struct frame *fp) -{ - int res = 0; -#if 0 - if (fp->un.fmt7.wb1s & WBV_040) - printk("access_error040: cannot handle 1st writeback. oops.\n"); -#endif - - if ((fp->un.fmt7.wb2s & WBV_040) && - !(fp->un.fmt7.wb2s & WBTT_040)) { - res = do_040writeback1(fp->un.fmt7.wb2s, fp->un.fmt7.wb2a, - fp->un.fmt7.wb2d); - if (res) - fix_xframe040(fp, fp->un.fmt7.wb2a, fp->un.fmt7.wb2s); - else - fp->un.fmt7.wb2s = 0; - } - - /* do the 2nd wb only if the first one was successful (except for a kernel wb) */ - if (fp->un.fmt7.wb3s & WBV_040 && (!res || fp->un.fmt7.wb3s & 4)) { - res = do_040writeback1(fp->un.fmt7.wb3s, fp->un.fmt7.wb3a, - fp->un.fmt7.wb3d); - if (res) - { - fix_xframe040(fp, fp->un.fmt7.wb3a, fp->un.fmt7.wb3s); - - fp->un.fmt7.wb2s = fp->un.fmt7.wb3s; - fp->un.fmt7.wb3s &= (~WBV_040); - fp->un.fmt7.wb2a = fp->un.fmt7.wb3a; - fp->un.fmt7.wb2d = fp->un.fmt7.wb3d; - } - else - fp->un.fmt7.wb3s = 0; - } - - if (res) - send_fault_sig(&fp->ptregs); -} - -/* - * called from sigreturn(), must ensure userspace code didn't - * manipulate exception frame to circumvent protection, then complete - * pending writebacks - * we just clear TM2 to turn it into a userspace access - */ -asmlinkage void berr_040cleanup(struct frame *fp) -{ - fp->un.fmt7.wb2s &= ~4; - fp->un.fmt7.wb3s &= ~4; - - do_040writebacks(fp); -} - -static inline void access_error040(struct frame *fp) -{ - unsigned short ssw = fp->un.fmt7.ssw; - unsigned long mmusr; - -#ifdef DEBUG - printk("ssw=%#x, fa=%#lx\n", ssw, fp->un.fmt7.faddr); - printk("wb1s=%#x, wb2s=%#x, wb3s=%#x\n", fp->un.fmt7.wb1s, - fp->un.fmt7.wb2s, fp->un.fmt7.wb3s); - printk ("wb2a=%lx, wb3a=%lx, wb2d=%lx, wb3d=%lx\n", - fp->un.fmt7.wb2a, fp->un.fmt7.wb3a, - fp->un.fmt7.wb2d, fp->un.fmt7.wb3d); -#endif - - if (ssw & ATC_040) { - unsigned long addr = fp->un.fmt7.faddr; - unsigned long errorcode; - - /* - * The MMU status has to be determined AFTER the address - * has been corrected if there was a misaligned access (MA). - */ - if (ssw & MA_040) - addr = (addr + 7) & -8; - - /* MMU error, get the MMUSR info for this access */ - mmusr = probe040(!(ssw & RW_040), addr, ssw); -#ifdef DEBUG - printk("mmusr = %lx\n", mmusr); -#endif - errorcode = 1; - if (!(mmusr & MMU_R_040)) { - /* clear the invalid atc entry */ - __flush_tlb040_one(addr); - errorcode = 0; - } - - /* despite what documentation seems to say, RMW - * accesses have always both the LK and RW bits set */ - if (!(ssw & RW_040) || (ssw & LK_040)) - errorcode |= 2; - - if (do_page_fault(&fp->ptregs, addr, errorcode)) { -#ifdef DEBUG - printk("do_page_fault() !=0\n"); -#endif - if (user_mode(&fp->ptregs)){ - /* delay writebacks after signal delivery */ -#ifdef DEBUG - printk(".. was usermode - return\n"); -#endif - return; - } - /* disable writeback into user space from kernel - * (if do_page_fault didn't fix the mapping, - * the writeback won't do good) - */ -disable_wb: -#ifdef DEBUG - printk(".. disabling wb2\n"); -#endif - if (fp->un.fmt7.wb2a == fp->un.fmt7.faddr) - fp->un.fmt7.wb2s &= ~WBV_040; - if (fp->un.fmt7.wb3a == fp->un.fmt7.faddr) - fp->un.fmt7.wb3s &= ~WBV_040; - } - } else { - /* In case of a bus error we either kill the process or expect - * the kernel to catch the fault, which then is also responsible - * for cleaning up the mess. - */ - current->thread.signo = SIGBUS; - current->thread.faddr = fp->un.fmt7.faddr; - if (send_fault_sig(&fp->ptregs) >= 0) - printk("68040 bus error (ssw=%x, faddr=%lx)\n", ssw, - fp->un.fmt7.faddr); - goto disable_wb; - } - - do_040writebacks(fp); -} -#endif /* CONFIG_M68040 */ - -#if defined(CONFIG_SUN3) -#include <asm/sun3mmu.h> - -extern int mmu_emu_handle_fault (unsigned long, int, int); - -/* sun3 version of bus_error030 */ - -static inline void bus_error030 (struct frame *fp) -{ - unsigned char buserr_type = sun3_get_buserr (); - unsigned long addr, errorcode; - unsigned short ssw = fp->un.fmtb.ssw; - extern unsigned long _sun3_map_test_start, _sun3_map_test_end; - -#ifdef DEBUG - if (ssw & (FC | FB)) - printk ("Instruction fault at %#010lx\n", - ssw & FC ? - fp->ptregs.format == 0xa ? fp->ptregs.pc + 2 : fp->un.fmtb.baddr - 2 - : - fp->ptregs.format == 0xa ? fp->ptregs.pc + 4 : fp->un.fmtb.baddr); - if (ssw & DF) - printk ("Data %s fault at %#010lx in %s (pc=%#lx)\n", - ssw & RW ? "read" : "write", - fp->un.fmtb.daddr, - space_names[ssw & DFC], fp->ptregs.pc); -#endif - - /* - * Check if this page should be demand-mapped. This needs to go before - * the testing for a bad kernel-space access (demand-mapping applies - * to kernel accesses too). - */ - - if ((ssw & DF) - && (buserr_type & (SUN3_BUSERR_PROTERR | SUN3_BUSERR_INVALID))) { - if (mmu_emu_handle_fault (fp->un.fmtb.daddr, ssw & RW, 0)) - return; - } - - /* Check for kernel-space pagefault (BAD). */ - if (fp->ptregs.sr & PS_S) { - /* kernel fault must be a data fault to user space */ - if (! ((ssw & DF) && ((ssw & DFC) == USER_DATA))) { - // try checking the kernel mappings before surrender - if (mmu_emu_handle_fault (fp->un.fmtb.daddr, ssw & RW, 1)) - return; - /* instruction fault or kernel data fault! */ - if (ssw & (FC | FB)) - printk ("Instruction fault at %#010lx\n", - fp->ptregs.pc); - if (ssw & DF) { - /* was this fault incurred testing bus mappings? */ - if((fp->ptregs.pc >= (unsigned long)&_sun3_map_test_start) && - (fp->ptregs.pc <= (unsigned long)&_sun3_map_test_end)) { - send_fault_sig(&fp->ptregs); - return; - } - - printk ("Data %s fault at %#010lx in %s (pc=%#lx)\n", - ssw & RW ? "read" : "write", - fp->un.fmtb.daddr, - space_names[ssw & DFC], fp->ptregs.pc); - } - printk ("BAD KERNEL BUSERR\n"); - - die_if_kernel("Oops", &fp->ptregs,0); - force_sig(SIGKILL, current); - return; - } - } else { - /* user fault */ - if (!(ssw & (FC | FB)) && !(ssw & DF)) - /* not an instruction fault or data fault! BAD */ - panic ("USER BUSERR w/o instruction or data fault"); - } - - - /* First handle the data fault, if any. */ - if (ssw & DF) { - addr = fp->un.fmtb.daddr; - -// errorcode bit 0: 0 -> no page 1 -> protection fault -// errorcode bit 1: 0 -> read fault 1 -> write fault - -// (buserr_type & SUN3_BUSERR_PROTERR) -> protection fault -// (buserr_type & SUN3_BUSERR_INVALID) -> invalid page fault - - if (buserr_type & SUN3_BUSERR_PROTERR) - errorcode = 0x01; - else if (buserr_type & SUN3_BUSERR_INVALID) - errorcode = 0x00; - else { -#ifdef DEBUG - printk ("*** unexpected busfault type=%#04x\n", buserr_type); - printk ("invalid %s access at %#lx from pc %#lx\n", - !(ssw & RW) ? "write" : "read", addr, - fp->ptregs.pc); -#endif - die_if_kernel ("Oops", &fp->ptregs, buserr_type); - force_sig (SIGBUS, current); - return; - } - -//todo: wtf is RM bit? --m - if (!(ssw & RW) || ssw & RM) - errorcode |= 0x02; - - /* Handle page fault. */ - do_page_fault (&fp->ptregs, addr, errorcode); - - /* Retry the data fault now. */ - return; - } - - /* Now handle the instruction fault. */ - - /* Get the fault address. */ - if (fp->ptregs.format == 0xA) - addr = fp->ptregs.pc + 4; - else - addr = fp->un.fmtb.baddr; - if (ssw & FC) - addr -= 2; - - if (buserr_type & SUN3_BUSERR_INVALID) { - if (!mmu_emu_handle_fault (fp->un.fmtb.daddr, 1, 0)) - do_page_fault (&fp->ptregs, addr, 0); - } else { -#ifdef DEBUG - printk ("protection fault on insn access (segv).\n"); -#endif - force_sig (SIGSEGV, current); - } -} -#else -#if defined(CPU_M68020_OR_M68030) -static inline void bus_error030 (struct frame *fp) -{ - volatile unsigned short temp; - unsigned short mmusr; - unsigned long addr, errorcode; - unsigned short ssw = fp->un.fmtb.ssw; -#ifdef DEBUG - unsigned long desc; - - printk ("pid = %x ", current->pid); - printk ("SSW=%#06x ", ssw); - - if (ssw & (FC | FB)) - printk ("Instruction fault at %#010lx\n", - ssw & FC ? - fp->ptregs.format == 0xa ? fp->ptregs.pc + 2 : fp->un.fmtb.baddr - 2 - : - fp->ptregs.format == 0xa ? fp->ptregs.pc + 4 : fp->un.fmtb.baddr); - if (ssw & DF) - printk ("Data %s fault at %#010lx in %s (pc=%#lx)\n", - ssw & RW ? "read" : "write", - fp->un.fmtb.daddr, - space_names[ssw & DFC], fp->ptregs.pc); -#endif - - /* ++andreas: If a data fault and an instruction fault happen - at the same time map in both pages. */ - - /* First handle the data fault, if any. */ - if (ssw & DF) { - addr = fp->un.fmtb.daddr; - -#ifdef DEBUG - asm volatile ("ptestr %3,%2@,#7,%0\n\t" - "pmove %%psr,%1@" - : "=a&" (desc) - : "a" (&temp), "a" (addr), "d" (ssw)); -#else - asm volatile ("ptestr %2,%1@,#7\n\t" - "pmove %%psr,%0@" - : : "a" (&temp), "a" (addr), "d" (ssw)); -#endif - mmusr = temp; - -#ifdef DEBUG - printk("mmusr is %#x for addr %#lx in task %p\n", - mmusr, addr, current); - printk("descriptor address is %#lx, contents %#lx\n", - __va(desc), *(unsigned long *)__va(desc)); -#endif - - errorcode = (mmusr & MMU_I) ? 0 : 1; - if (!(ssw & RW) || (ssw & RM)) - errorcode |= 2; - - if (mmusr & (MMU_I | MMU_WP)) { - if (ssw & 4) { - printk("Data %s fault at %#010lx in %s (pc=%#lx)\n", - ssw & RW ? "read" : "write", - fp->un.fmtb.daddr, - space_names[ssw & DFC], fp->ptregs.pc); - goto buserr; - } - /* Don't try to do anything further if an exception was - handled. */ - if (do_page_fault (&fp->ptregs, addr, errorcode) < 0) - return; - } else if (!(mmusr & MMU_I)) { - /* probably a 020 cas fault */ - if (!(ssw & RM) && send_fault_sig(&fp->ptregs) > 0) - printk("unexpected bus error (%#x,%#x)\n", ssw, mmusr); - } else if (mmusr & (MMU_B|MMU_L|MMU_S)) { - printk("invalid %s access at %#lx from pc %#lx\n", - !(ssw & RW) ? "write" : "read", addr, - fp->ptregs.pc); - die_if_kernel("Oops",&fp->ptregs,mmusr); - force_sig(SIGSEGV, current); - return; - } else { -#if 0 - static volatile long tlong; -#endif - - printk("weird %s access at %#lx from pc %#lx (ssw is %#x)\n", - !(ssw & RW) ? "write" : "read", addr, - fp->ptregs.pc, ssw); - asm volatile ("ptestr #1,%1@,#0\n\t" - "pmove %%psr,%0@" - : /* no outputs */ - : "a" (&temp), "a" (addr)); - mmusr = temp; - - printk ("level 0 mmusr is %#x\n", mmusr); -#if 0 - asm volatile ("pmove %%tt0,%0@" - : /* no outputs */ - : "a" (&tlong)); - printk("tt0 is %#lx, ", tlong); - asm volatile ("pmove %%tt1,%0@" - : /* no outputs */ - : "a" (&tlong)); - printk("tt1 is %#lx\n", tlong); -#endif -#ifdef DEBUG - printk("Unknown SIGSEGV - 1\n"); -#endif - die_if_kernel("Oops",&fp->ptregs,mmusr); - force_sig(SIGSEGV, current); - return; - } - - /* setup an ATC entry for the access about to be retried */ - if (!(ssw & RW) || (ssw & RM)) - asm volatile ("ploadw %1,%0@" : /* no outputs */ - : "a" (addr), "d" (ssw)); - else - asm volatile ("ploadr %1,%0@" : /* no outputs */ - : "a" (addr), "d" (ssw)); - } - - /* Now handle the instruction fault. */ - - if (!(ssw & (FC|FB))) - return; - - if (fp->ptregs.sr & PS_S) { - printk("Instruction fault at %#010lx\n", - fp->ptregs.pc); - buserr: - printk ("BAD KERNEL BUSERR\n"); - die_if_kernel("Oops",&fp->ptregs,0); - force_sig(SIGKILL, current); - return; - } - - /* get the fault address */ - if (fp->ptregs.format == 10) - addr = fp->ptregs.pc + 4; - else - addr = fp->un.fmtb.baddr; - if (ssw & FC) - addr -= 2; - - if ((ssw & DF) && ((addr ^ fp->un.fmtb.daddr) & PAGE_MASK) == 0) - /* Insn fault on same page as data fault. But we - should still create the ATC entry. */ - goto create_atc_entry; - -#ifdef DEBUG - asm volatile ("ptestr #1,%2@,#7,%0\n\t" - "pmove %%psr,%1@" - : "=a&" (desc) - : "a" (&temp), "a" (addr)); -#else - asm volatile ("ptestr #1,%1@,#7\n\t" - "pmove %%psr,%0@" - : : "a" (&temp), "a" (addr)); -#endif - mmusr = temp; - -#ifdef DEBUG - printk ("mmusr is %#x for addr %#lx in task %p\n", - mmusr, addr, current); - printk ("descriptor address is %#lx, contents %#lx\n", - __va(desc), *(unsigned long *)__va(desc)); -#endif - - if (mmusr & MMU_I) - do_page_fault (&fp->ptregs, addr, 0); - else if (mmusr & (MMU_B|MMU_L|MMU_S)) { - printk ("invalid insn access at %#lx from pc %#lx\n", - addr, fp->ptregs.pc); -#ifdef DEBUG - printk("Unknown SIGSEGV - 2\n"); -#endif - die_if_kernel("Oops",&fp->ptregs,mmusr); - force_sig(SIGSEGV, current); - return; - } - -create_atc_entry: - /* setup an ATC entry for the access about to be retried */ - asm volatile ("ploadr #2,%0@" : /* no outputs */ - : "a" (addr)); -} -#endif /* CPU_M68020_OR_M68030 */ -#endif /* !CONFIG_SUN3 */ - -asmlinkage void buserr_c(struct frame *fp) -{ - /* Only set esp0 if coming from user mode */ - if (user_mode(&fp->ptregs)) - current->thread.esp0 = (unsigned long) fp; - -#ifdef DEBUG - printk ("*** Bus Error *** Format is %x\n", fp->ptregs.format); -#endif - - switch (fp->ptregs.format) { -#if defined (CONFIG_M68060) - case 4: /* 68060 access error */ - access_error060 (fp); - break; -#endif -#if defined (CONFIG_M68040) - case 0x7: /* 68040 access error */ - access_error040 (fp); - break; -#endif -#if defined (CPU_M68020_OR_M68030) - case 0xa: - case 0xb: - bus_error030 (fp); - break; -#endif - default: - die_if_kernel("bad frame format",&fp->ptregs,0); -#ifdef DEBUG - printk("Unknown SIGSEGV - 4\n"); -#endif - force_sig(SIGSEGV, current); - } -} - - -static int kstack_depth_to_print = 48; - -void show_trace(unsigned long *stack) -{ - unsigned long *endstack; - unsigned long addr; - int i; - - printk("Call Trace:"); - addr = (unsigned long)stack + THREAD_SIZE - 1; - endstack = (unsigned long *)(addr & -THREAD_SIZE); - i = 0; - while (stack + 1 <= endstack) { - addr = *stack++; - /* - * If the address is either in the text segment of the - * kernel, or in the region which contains vmalloc'ed - * memory, it *may* be the address of a calling - * routine; if so, print it so that someone tracing - * down the cause of the crash will be able to figure - * out the call path that was taken. - */ - if (__kernel_text_address(addr)) { -#ifndef CONFIG_KALLSYMS - if (i % 5 == 0) - printk("\n "); -#endif - printk(" [<%08lx>] %pS\n", addr, (void *)addr); - i++; - } - } - printk("\n"); -} - -void show_registers(struct pt_regs *regs) -{ - struct frame *fp = (struct frame *)regs; - mm_segment_t old_fs = get_fs(); - u16 c, *cp; - unsigned long addr; - int i; - - print_modules(); - printk("PC: [<%08lx>] %pS\n", regs->pc, (void *)regs->pc); - printk("SR: %04x SP: %p a2: %08lx\n", regs->sr, regs, regs->a2); - printk("d0: %08lx d1: %08lx d2: %08lx d3: %08lx\n", - regs->d0, regs->d1, regs->d2, regs->d3); - printk("d4: %08lx d5: %08lx a0: %08lx a1: %08lx\n", - regs->d4, regs->d5, regs->a0, regs->a1); - - printk("Process %s (pid: %d, task=%p)\n", - current->comm, task_pid_nr(current), current); - addr = (unsigned long)&fp->un; - printk("Frame format=%X ", regs->format); - switch (regs->format) { - case 0x2: - printk("instr addr=%08lx\n", fp->un.fmt2.iaddr); - addr += sizeof(fp->un.fmt2); - break; - case 0x3: - printk("eff addr=%08lx\n", fp->un.fmt3.effaddr); - addr += sizeof(fp->un.fmt3); - break; - case 0x4: - printk((CPU_IS_060 ? "fault addr=%08lx fslw=%08lx\n" - : "eff addr=%08lx pc=%08lx\n"), - fp->un.fmt4.effaddr, fp->un.fmt4.pc); - addr += sizeof(fp->un.fmt4); - break; - case 0x7: - printk("eff addr=%08lx ssw=%04x faddr=%08lx\n", - fp->un.fmt7.effaddr, fp->un.fmt7.ssw, fp->un.fmt7.faddr); - printk("wb 1 stat/addr/data: %04x %08lx %08lx\n", - fp->un.fmt7.wb1s, fp->un.fmt7.wb1a, fp->un.fmt7.wb1dpd0); - printk("wb 2 stat/addr/data: %04x %08lx %08lx\n", - fp->un.fmt7.wb2s, fp->un.fmt7.wb2a, fp->un.fmt7.wb2d); - printk("wb 3 stat/addr/data: %04x %08lx %08lx\n", - fp->un.fmt7.wb3s, fp->un.fmt7.wb3a, fp->un.fmt7.wb3d); - printk("push data: %08lx %08lx %08lx %08lx\n", - fp->un.fmt7.wb1dpd0, fp->un.fmt7.pd1, fp->un.fmt7.pd2, - fp->un.fmt7.pd3); - addr += sizeof(fp->un.fmt7); - break; - case 0x9: - printk("instr addr=%08lx\n", fp->un.fmt9.iaddr); - addr += sizeof(fp->un.fmt9); - break; - case 0xa: - printk("ssw=%04x isc=%04x isb=%04x daddr=%08lx dobuf=%08lx\n", - fp->un.fmta.ssw, fp->un.fmta.isc, fp->un.fmta.isb, - fp->un.fmta.daddr, fp->un.fmta.dobuf); - addr += sizeof(fp->un.fmta); - break; - case 0xb: - printk("ssw=%04x isc=%04x isb=%04x daddr=%08lx dobuf=%08lx\n", - fp->un.fmtb.ssw, fp->un.fmtb.isc, fp->un.fmtb.isb, - fp->un.fmtb.daddr, fp->un.fmtb.dobuf); - printk("baddr=%08lx dibuf=%08lx ver=%x\n", - fp->un.fmtb.baddr, fp->un.fmtb.dibuf, fp->un.fmtb.ver); - addr += sizeof(fp->un.fmtb); - break; - default: - printk("\n"); - } - show_stack(NULL, (unsigned long *)addr); - - printk("Code:"); - set_fs(KERNEL_DS); - cp = (u16 *)regs->pc; - for (i = -8; i < 16; i++) { - if (get_user(c, cp + i) && i >= 0) { - printk(" Bad PC value."); - break; - } - printk(i ? " %04x" : " <%04x>", c); - } - set_fs(old_fs); - printk ("\n"); -} - -void show_stack(struct task_struct *task, unsigned long *stack) -{ - unsigned long *p; - unsigned long *endstack; - int i; - - if (!stack) { - if (task) - stack = (unsigned long *)task->thread.esp0; - else - stack = (unsigned long *)&stack; - } - endstack = (unsigned long *)(((unsigned long)stack + THREAD_SIZE - 1) & -THREAD_SIZE); - - printk("Stack from %08lx:", (unsigned long)stack); - p = stack; - for (i = 0; i < kstack_depth_to_print; i++) { - if (p + 1 > endstack) - break; - if (i % 8 == 0) - printk("\n "); - printk(" %08lx", *p++); - } - printk("\n"); - show_trace(stack); -} - -/* - * The architecture-independent backtrace generator - */ -void dump_stack(void) -{ - unsigned long stack; - - show_trace(&stack); -} - -EXPORT_SYMBOL(dump_stack); - -void bad_super_trap (struct frame *fp) -{ - console_verbose(); - if (fp->ptregs.vector < 4 * ARRAY_SIZE(vec_names)) - printk ("*** %s *** FORMAT=%X\n", - vec_names[(fp->ptregs.vector) >> 2], - fp->ptregs.format); - else - printk ("*** Exception %d *** FORMAT=%X\n", - (fp->ptregs.vector) >> 2, - fp->ptregs.format); - if (fp->ptregs.vector >> 2 == VEC_ADDRERR && CPU_IS_020_OR_030) { - unsigned short ssw = fp->un.fmtb.ssw; - - printk ("SSW=%#06x ", ssw); - - if (ssw & RC) - printk ("Pipe stage C instruction fault at %#010lx\n", - (fp->ptregs.format) == 0xA ? - fp->ptregs.pc + 2 : fp->un.fmtb.baddr - 2); - if (ssw & RB) - printk ("Pipe stage B instruction fault at %#010lx\n", - (fp->ptregs.format) == 0xA ? - fp->ptregs.pc + 4 : fp->un.fmtb.baddr); - if (ssw & DF) - printk ("Data %s fault at %#010lx in %s (pc=%#lx)\n", - ssw & RW ? "read" : "write", - fp->un.fmtb.daddr, space_names[ssw & DFC], - fp->ptregs.pc); - } - printk ("Current process id is %d\n", task_pid_nr(current)); - die_if_kernel("BAD KERNEL TRAP", &fp->ptregs, 0); -} - -asmlinkage void trap_c(struct frame *fp) -{ - int sig; - siginfo_t info; - - if (fp->ptregs.sr & PS_S) { - if (fp->ptregs.vector == VEC_TRACE << 2) { - /* traced a trapping instruction on a 68020/30, - * real exception will be executed afterwards. - */ - } else if (!handle_kernel_fault(&fp->ptregs)) - bad_super_trap(fp); - return; - } - - /* send the appropriate signal to the user program */ - switch ((fp->ptregs.vector) >> 2) { - case VEC_ADDRERR: - info.si_code = BUS_ADRALN; - sig = SIGBUS; - break; - case VEC_ILLEGAL: - case VEC_LINE10: - case VEC_LINE11: - info.si_code = ILL_ILLOPC; - sig = SIGILL; - break; - case VEC_PRIV: - info.si_code = ILL_PRVOPC; - sig = SIGILL; - break; - case VEC_COPROC: - info.si_code = ILL_COPROC; - sig = SIGILL; - break; - case VEC_TRAP1: - case VEC_TRAP2: - case VEC_TRAP3: - case VEC_TRAP4: - case VEC_TRAP5: - case VEC_TRAP6: - case VEC_TRAP7: - case VEC_TRAP8: - case VEC_TRAP9: - case VEC_TRAP10: - case VEC_TRAP11: - case VEC_TRAP12: - case VEC_TRAP13: - case VEC_TRAP14: - info.si_code = ILL_ILLTRP; - sig = SIGILL; - break; - case VEC_FPBRUC: - case VEC_FPOE: - case VEC_FPNAN: - info.si_code = FPE_FLTINV; - sig = SIGFPE; - break; - case VEC_FPIR: - info.si_code = FPE_FLTRES; - sig = SIGFPE; - break; - case VEC_FPDIVZ: - info.si_code = FPE_FLTDIV; - sig = SIGFPE; - break; - case VEC_FPUNDER: - info.si_code = FPE_FLTUND; - sig = SIGFPE; - break; - case VEC_FPOVER: - info.si_code = FPE_FLTOVF; - sig = SIGFPE; - break; - case VEC_ZERODIV: - info.si_code = FPE_INTDIV; - sig = SIGFPE; - break; - case VEC_CHK: - case VEC_TRAP: - info.si_code = FPE_INTOVF; - sig = SIGFPE; - break; - case VEC_TRACE: /* ptrace single step */ - info.si_code = TRAP_TRACE; - sig = SIGTRAP; - break; - case VEC_TRAP15: /* breakpoint */ - info.si_code = TRAP_BRKPT; - sig = SIGTRAP; - break; - default: - info.si_code = ILL_ILLOPC; - sig = SIGILL; - break; - } - info.si_signo = sig; - info.si_errno = 0; - switch (fp->ptregs.format) { - default: - info.si_addr = (void *) fp->ptregs.pc; - break; - case 2: - info.si_addr = (void *) fp->un.fmt2.iaddr; - break; - case 7: - info.si_addr = (void *) fp->un.fmt7.effaddr; - break; - case 9: - info.si_addr = (void *) fp->un.fmt9.iaddr; - break; - case 10: - info.si_addr = (void *) fp->un.fmta.daddr; - break; - case 11: - info.si_addr = (void *) fp->un.fmtb.daddr; - break; - } - force_sig_info (sig, &info, current); -} - -void die_if_kernel (char *str, struct pt_regs *fp, int nr) -{ - if (!(fp->sr & PS_S)) - return; - - console_verbose(); - printk("%s: %08x\n",str,nr); - show_registers(fp); - add_taint(TAINT_DIE); - do_exit(SIGSEGV); -} - -/* - * This function is called if an error occur while accessing - * user-space from the fpsp040 code. - */ -asmlinkage void fpsp040_die(void) -{ - do_exit(SIGSEGV); -} - -#ifdef CONFIG_M68KFPU_EMU -asmlinkage void fpemu_signal(int signal, int code, void *addr) -{ - siginfo_t info; - - info.si_signo = signal; - info.si_errno = 0; - info.si_code = code; - info.si_addr = addr; - force_sig_info(signal, &info, current); -} +#include "traps_no.c" #endif diff --git a/arch/m68k/kernel/traps_mm.c b/arch/m68k/kernel/traps_mm.c new file mode 100644 index 00000000000..4022bbc2887 --- /dev/null +++ b/arch/m68k/kernel/traps_mm.c @@ -0,0 +1,1207 @@ +/* + * linux/arch/m68k/kernel/traps.c + * + * Copyright (C) 1993, 1994 by Hamish Macdonald + * + * 68040 fixes by Michael Rausch + * 68040 fixes by Martin Apel + * 68040 fixes and writeback by Richard Zidlicky + * 68060 fixes by Roman Hodek + * 68060 fixes by Jesper Skov + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +/* + * Sets up all exception vectors + */ + +#include <linux/sched.h> +#include <linux/signal.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/module.h> +#include <linux/user.h> +#include <linux/string.h> +#include <linux/linkage.h> +#include <linux/init.h> +#include <linux/ptrace.h> +#include <linux/kallsyms.h> + +#include <asm/setup.h> +#include <asm/fpu.h> +#include <asm/system.h> +#include <asm/uaccess.h> +#include <asm/traps.h> +#include <asm/pgalloc.h> +#include <asm/machdep.h> +#include <asm/siginfo.h> + +/* assembler routines */ +asmlinkage void system_call(void); +asmlinkage void buserr(void); +asmlinkage void trap(void); +asmlinkage void nmihandler(void); +#ifdef CONFIG_M68KFPU_EMU +asmlinkage void fpu_emu(void); +#endif + +e_vector vectors[256]; + +/* nmi handler for the Amiga */ +asm(".text\n" + __ALIGN_STR "\n" + "nmihandler: rte"); + +/* + * this must be called very early as the kernel might + * use some instruction that are emulated on the 060 + * and so we're prepared for early probe attempts (e.g. nf_init). + */ +void __init base_trap_init(void) +{ + if (MACH_IS_SUN3X) { + extern e_vector *sun3x_prom_vbr; + + __asm__ volatile ("movec %%vbr, %0" : "=r" (sun3x_prom_vbr)); + } + + /* setup the exception vector table */ + __asm__ volatile ("movec %0,%%vbr" : : "r" ((void*)vectors)); + + if (CPU_IS_060) { + /* set up ISP entry points */ + asmlinkage void unimp_vec(void) asm ("_060_isp_unimp"); + + vectors[VEC_UNIMPII] = unimp_vec; + } + + vectors[VEC_BUSERR] = buserr; + vectors[VEC_ILLEGAL] = trap; + vectors[VEC_SYS] = system_call; +} + +void __init trap_init (void) +{ + int i; + + for (i = VEC_SPUR; i <= VEC_INT7; i++) + vectors[i] = bad_inthandler; + + for (i = 0; i < VEC_USER; i++) + if (!vectors[i]) + vectors[i] = trap; + + for (i = VEC_USER; i < 256; i++) + vectors[i] = bad_inthandler; + +#ifdef CONFIG_M68KFPU_EMU + if (FPU_IS_EMU) + vectors[VEC_LINE11] = fpu_emu; +#endif + + if (CPU_IS_040 && !FPU_IS_EMU) { + /* set up FPSP entry points */ + asmlinkage void dz_vec(void) asm ("dz"); + asmlinkage void inex_vec(void) asm ("inex"); + asmlinkage void ovfl_vec(void) asm ("ovfl"); + asmlinkage void unfl_vec(void) asm ("unfl"); + asmlinkage void snan_vec(void) asm ("snan"); + asmlinkage void operr_vec(void) asm ("operr"); + asmlinkage void bsun_vec(void) asm ("bsun"); + asmlinkage void fline_vec(void) asm ("fline"); + asmlinkage void unsupp_vec(void) asm ("unsupp"); + + vectors[VEC_FPDIVZ] = dz_vec; + vectors[VEC_FPIR] = inex_vec; + vectors[VEC_FPOVER] = ovfl_vec; + vectors[VEC_FPUNDER] = unfl_vec; + vectors[VEC_FPNAN] = snan_vec; + vectors[VEC_FPOE] = operr_vec; + vectors[VEC_FPBRUC] = bsun_vec; + vectors[VEC_LINE11] = fline_vec; + vectors[VEC_FPUNSUP] = unsupp_vec; + } + + if (CPU_IS_060 && !FPU_IS_EMU) { + /* set up IFPSP entry points */ + asmlinkage void snan_vec6(void) asm ("_060_fpsp_snan"); + asmlinkage void operr_vec6(void) asm ("_060_fpsp_operr"); + asmlinkage void ovfl_vec6(void) asm ("_060_fpsp_ovfl"); + asmlinkage void unfl_vec6(void) asm ("_060_fpsp_unfl"); + asmlinkage void dz_vec6(void) asm ("_060_fpsp_dz"); + asmlinkage void inex_vec6(void) asm ("_060_fpsp_inex"); + asmlinkage void fline_vec6(void) asm ("_060_fpsp_fline"); + asmlinkage void unsupp_vec6(void) asm ("_060_fpsp_unsupp"); + asmlinkage void effadd_vec6(void) asm ("_060_fpsp_effadd"); + + vectors[VEC_FPNAN] = snan_vec6; + vectors[VEC_FPOE] = operr_vec6; + vectors[VEC_FPOVER] = ovfl_vec6; + vectors[VEC_FPUNDER] = unfl_vec6; + vectors[VEC_FPDIVZ] = dz_vec6; + vectors[VEC_FPIR] = inex_vec6; + vectors[VEC_LINE11] = fline_vec6; + vectors[VEC_FPUNSUP] = unsupp_vec6; + vectors[VEC_UNIMPEA] = effadd_vec6; + } + + /* if running on an amiga, make the NMI interrupt do nothing */ + if (MACH_IS_AMIGA) { + vectors[VEC_INT7] = nmihandler; + } +} + + +static const char *vec_names[] = { + [VEC_RESETSP] = "RESET SP", + [VEC_RESETPC] = "RESET PC", + [VEC_BUSERR] = "BUS ERROR", + [VEC_ADDRERR] = "ADDRESS ERROR", + [VEC_ILLEGAL] = "ILLEGAL INSTRUCTION", + [VEC_ZERODIV] = "ZERO DIVIDE", + [VEC_CHK] = "CHK", + [VEC_TRAP] = "TRAPcc", + [VEC_PRIV] = "PRIVILEGE VIOLATION", + [VEC_TRACE] = "TRACE", + [VEC_LINE10] = "LINE 1010", + [VEC_LINE11] = "LINE 1111", + [VEC_RESV12] = "UNASSIGNED RESERVED 12", + [VEC_COPROC] = "COPROCESSOR PROTOCOL VIOLATION", + [VEC_FORMAT] = "FORMAT ERROR", + [VEC_UNINT] = "UNINITIALIZED INTERRUPT", + [VEC_RESV16] = "UNASSIGNED RESERVED 16", + [VEC_RESV17] = "UNASSIGNED RESERVED 17", + [VEC_RESV18] = "UNASSIGNED RESERVED 18", + [VEC_RESV19] = "UNASSIGNED RESERVED 19", + [VEC_RESV20] = "UNASSIGNED RESERVED 20", + [VEC_RESV21] = "UNASSIGNED RESERVED 21", + [VEC_RESV22] = "UNASSIGNED RESERVED 22", + [VEC_RESV23] = "UNASSIGNED RESERVED 23", + [VEC_SPUR] = "SPURIOUS INTERRUPT", + [VEC_INT1] = "LEVEL 1 INT", + [VEC_INT2] = "LEVEL 2 INT", + [VEC_INT3] = "LEVEL 3 INT", + [VEC_INT4] = "LEVEL 4 INT", + [VEC_INT5] = "LEVEL 5 INT", + [VEC_INT6] = "LEVEL 6 INT", + [VEC_INT7] = "LEVEL 7 INT", + [VEC_SYS] = "SYSCALL", + [VEC_TRAP1] = "TRAP #1", + [VEC_TRAP2] = "TRAP #2", + [VEC_TRAP3] = "TRAP #3", + [VEC_TRAP4] = "TRAP #4", + [VEC_TRAP5] = "TRAP #5", + [VEC_TRAP6] = "TRAP #6", + [VEC_TRAP7] = "TRAP #7", + [VEC_TRAP8] = "TRAP #8", + [VEC_TRAP9] = "TRAP #9", + [VEC_TRAP10] = "TRAP #10", + [VEC_TRAP11] = "TRAP #11", + [VEC_TRAP12] = "TRAP #12", + [VEC_TRAP13] = "TRAP #13", + [VEC_TRAP14] = "TRAP #14", + [VEC_TRAP15] = "TRAP #15", + [VEC_FPBRUC] = "FPCP BSUN", + [VEC_FPIR] = "FPCP INEXACT", + [VEC_FPDIVZ] = "FPCP DIV BY 0", + [VEC_FPUNDER] = "FPCP UNDERFLOW", + [VEC_FPOE] = "FPCP OPERAND ERROR", + [VEC_FPOVER] = "FPCP OVERFLOW", + [VEC_FPNAN] = "FPCP SNAN", + [VEC_FPUNSUP] = "FPCP UNSUPPORTED OPERATION", + [VEC_MMUCFG] = "MMU CONFIGURATION ERROR", + [VEC_MMUILL] = "MMU ILLEGAL OPERATION ERROR", + [VEC_MMUACC] = "MMU ACCESS LEVEL VIOLATION ERROR", + [VEC_RESV59] = "UNASSIGNED RESERVED 59", + [VEC_UNIMPEA] = "UNASSIGNED RESERVED 60", + [VEC_UNIMPII] = "UNASSIGNED RESERVED 61", + [VEC_RESV62] = "UNASSIGNED RESERVED 62", + [VEC_RESV63] = "UNASSIGNED RESERVED 63", +}; + +static const char *space_names[] = { + [0] = "Space 0", + [USER_DATA] = "User Data", + [USER_PROGRAM] = "User Program", +#ifndef CONFIG_SUN3 + [3] = "Space 3", +#else + [FC_CONTROL] = "Control", +#endif + [4] = "Space 4", + [SUPER_DATA] = "Super Data", + [SUPER_PROGRAM] = "Super Program", + [CPU_SPACE] = "CPU" +}; + +void die_if_kernel(char *,struct pt_regs *,int); +asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address, + unsigned long error_code); +int send_fault_sig(struct pt_regs *regs); + +asmlinkage void trap_c(struct frame *fp); + +#if defined (CONFIG_M68060) +static inline void access_error060 (struct frame *fp) +{ + unsigned long fslw = fp->un.fmt4.pc; /* is really FSLW for access error */ + +#ifdef DEBUG + printk("fslw=%#lx, fa=%#lx\n", fslw, fp->un.fmt4.effaddr); +#endif + + if (fslw & MMU060_BPE) { + /* branch prediction error -> clear branch cache */ + __asm__ __volatile__ ("movec %/cacr,%/d0\n\t" + "orl #0x00400000,%/d0\n\t" + "movec %/d0,%/cacr" + : : : "d0" ); + /* return if there's no other error */ + if (!(fslw & MMU060_ERR_BITS) && !(fslw & MMU060_SEE)) + return; + } + + if (fslw & (MMU060_DESC_ERR | MMU060_WP | MMU060_SP)) { + unsigned long errorcode; + unsigned long addr = fp->un.fmt4.effaddr; + + if (fslw & MMU060_MA) + addr = (addr + PAGE_SIZE - 1) & PAGE_MASK; + + errorcode = 1; + if (fslw & MMU060_DESC_ERR) { + __flush_tlb040_one(addr); + errorcode = 0; + } + if (fslw & MMU060_W) + errorcode |= 2; +#ifdef DEBUG + printk("errorcode = %d\n", errorcode ); +#endif + do_page_fault(&fp->ptregs, addr, errorcode); + } else if (fslw & (MMU060_SEE)){ + /* Software Emulation Error. + * fault during mem_read/mem_write in ifpsp060/os.S + */ + send_fault_sig(&fp->ptregs); + } else if (!(fslw & (MMU060_RE|MMU060_WE)) || + send_fault_sig(&fp->ptregs) > 0) { + printk("pc=%#lx, fa=%#lx\n", fp->ptregs.pc, fp->un.fmt4.effaddr); + printk( "68060 access error, fslw=%lx\n", fslw ); + trap_c( fp ); + } +} +#endif /* CONFIG_M68060 */ + +#if defined (CONFIG_M68040) +static inline unsigned long probe040(int iswrite, unsigned long addr, int wbs) +{ + unsigned long mmusr; + mm_segment_t old_fs = get_fs(); + + set_fs(MAKE_MM_SEG(wbs)); + + if (iswrite) + asm volatile (".chip 68040; ptestw (%0); .chip 68k" : : "a" (addr)); + else + asm volatile (".chip 68040; ptestr (%0); .chip 68k" : : "a" (addr)); + + asm volatile (".chip 68040; movec %%mmusr,%0; .chip 68k" : "=r" (mmusr)); + + set_fs(old_fs); + + return mmusr; +} + +static inline int do_040writeback1(unsigned short wbs, unsigned long wba, + unsigned long wbd) +{ + int res = 0; + mm_segment_t old_fs = get_fs(); + + /* set_fs can not be moved, otherwise put_user() may oops */ + set_fs(MAKE_MM_SEG(wbs)); + + switch (wbs & WBSIZ_040) { + case BA_SIZE_BYTE: + res = put_user(wbd & 0xff, (char __user *)wba); + break; + case BA_SIZE_WORD: + res = put_user(wbd & 0xffff, (short __user *)wba); + break; + case BA_SIZE_LONG: + res = put_user(wbd, (int __user *)wba); + break; + } + + /* set_fs can not be moved, otherwise put_user() may oops */ + set_fs(old_fs); + + +#ifdef DEBUG + printk("do_040writeback1, res=%d\n",res); +#endif + + return res; +} + +/* after an exception in a writeback the stack frame corresponding + * to that exception is discarded, set a few bits in the old frame + * to simulate what it should look like + */ +static inline void fix_xframe040(struct frame *fp, unsigned long wba, unsigned short wbs) +{ + fp->un.fmt7.faddr = wba; + fp->un.fmt7.ssw = wbs & 0xff; + if (wba != current->thread.faddr) + fp->un.fmt7.ssw |= MA_040; +} + +static inline void do_040writebacks(struct frame *fp) +{ + int res = 0; +#if 0 + if (fp->un.fmt7.wb1s & WBV_040) + printk("access_error040: cannot handle 1st writeback. oops.\n"); +#endif + + if ((fp->un.fmt7.wb2s & WBV_040) && + !(fp->un.fmt7.wb2s & WBTT_040)) { + res = do_040writeback1(fp->un.fmt7.wb2s, fp->un.fmt7.wb2a, + fp->un.fmt7.wb2d); + if (res) + fix_xframe040(fp, fp->un.fmt7.wb2a, fp->un.fmt7.wb2s); + else + fp->un.fmt7.wb2s = 0; + } + + /* do the 2nd wb only if the first one was successful (except for a kernel wb) */ + if (fp->un.fmt7.wb3s & WBV_040 && (!res || fp->un.fmt7.wb3s & 4)) { + res = do_040writeback1(fp->un.fmt7.wb3s, fp->un.fmt7.wb3a, + fp->un.fmt7.wb3d); + if (res) + { + fix_xframe040(fp, fp->un.fmt7.wb3a, fp->un.fmt7.wb3s); + + fp->un.fmt7.wb2s = fp->un.fmt7.wb3s; + fp->un.fmt7.wb3s &= (~WBV_040); + fp->un.fmt7.wb2a = fp->un.fmt7.wb3a; + fp->un.fmt7.wb2d = fp->un.fmt7.wb3d; + } + else + fp->un.fmt7.wb3s = 0; + } + + if (res) + send_fault_sig(&fp->ptregs); +} + +/* + * called from sigreturn(), must ensure userspace code didn't + * manipulate exception frame to circumvent protection, then complete + * pending writebacks + * we just clear TM2 to turn it into a userspace access + */ +asmlinkage void berr_040cleanup(struct frame *fp) +{ + fp->un.fmt7.wb2s &= ~4; + fp->un.fmt7.wb3s &= ~4; + + do_040writebacks(fp); +} + +static inline void access_error040(struct frame *fp) +{ + unsigned short ssw = fp->un.fmt7.ssw; + unsigned long mmusr; + +#ifdef DEBUG + printk("ssw=%#x, fa=%#lx\n", ssw, fp->un.fmt7.faddr); + printk("wb1s=%#x, wb2s=%#x, wb3s=%#x\n", fp->un.fmt7.wb1s, + fp->un.fmt7.wb2s, fp->un.fmt7.wb3s); + printk ("wb2a=%lx, wb3a=%lx, wb2d=%lx, wb3d=%lx\n", + fp->un.fmt7.wb2a, fp->un.fmt7.wb3a, + fp->un.fmt7.wb2d, fp->un.fmt7.wb3d); +#endif + + if (ssw & ATC_040) { + unsigned long addr = fp->un.fmt7.faddr; + unsigned long errorcode; + + /* + * The MMU status has to be determined AFTER the address + * has been corrected if there was a misaligned access (MA). + */ + if (ssw & MA_040) + addr = (addr + 7) & -8; + + /* MMU error, get the MMUSR info for this access */ + mmusr = probe040(!(ssw & RW_040), addr, ssw); +#ifdef DEBUG + printk("mmusr = %lx\n", mmusr); +#endif + errorcode = 1; + if (!(mmusr & MMU_R_040)) { + /* clear the invalid atc entry */ + __flush_tlb040_one(addr); + errorcode = 0; + } + + /* despite what documentation seems to say, RMW + * accesses have always both the LK and RW bits set */ + if (!(ssw & RW_040) || (ssw & LK_040)) + errorcode |= 2; + + if (do_page_fault(&fp->ptregs, addr, errorcode)) { +#ifdef DEBUG + printk("do_page_fault() !=0\n"); +#endif + if (user_mode(&fp->ptregs)){ + /* delay writebacks after signal delivery */ +#ifdef DEBUG + printk(".. was usermode - return\n"); +#endif + return; + } + /* disable writeback into user space from kernel + * (if do_page_fault didn't fix the mapping, + * the writeback won't do good) + */ +disable_wb: +#ifdef DEBUG + printk(".. disabling wb2\n"); +#endif + if (fp->un.fmt7.wb2a == fp->un.fmt7.faddr) + fp->un.fmt7.wb2s &= ~WBV_040; + if (fp->un.fmt7.wb3a == fp->un.fmt7.faddr) + fp->un.fmt7.wb3s &= ~WBV_040; + } + } else { + /* In case of a bus error we either kill the process or expect + * the kernel to catch the fault, which then is also responsible + * for cleaning up the mess. + */ + current->thread.signo = SIGBUS; + current->thread.faddr = fp->un.fmt7.faddr; + if (send_fault_sig(&fp->ptregs) >= 0) + printk("68040 bus error (ssw=%x, faddr=%lx)\n", ssw, + fp->un.fmt7.faddr); + goto disable_wb; + } + + do_040writebacks(fp); +} +#endif /* CONFIG_M68040 */ + +#if defined(CONFIG_SUN3) +#include <asm/sun3mmu.h> + +extern int mmu_emu_handle_fault (unsigned long, int, int); + +/* sun3 version of bus_error030 */ + +static inline void bus_error030 (struct frame *fp) +{ + unsigned char buserr_type = sun3_get_buserr (); + unsigned long addr, errorcode; + unsigned short ssw = fp->un.fmtb.ssw; + extern unsigned long _sun3_map_test_start, _sun3_map_test_end; + +#ifdef DEBUG + if (ssw & (FC | FB)) + printk ("Instruction fault at %#010lx\n", + ssw & FC ? + fp->ptregs.format == 0xa ? fp->ptregs.pc + 2 : fp->un.fmtb.baddr - 2 + : + fp->ptregs.format == 0xa ? fp->ptregs.pc + 4 : fp->un.fmtb.baddr); + if (ssw & DF) + printk ("Data %s fault at %#010lx in %s (pc=%#lx)\n", + ssw & RW ? "read" : "write", + fp->un.fmtb.daddr, + space_names[ssw & DFC], fp->ptregs.pc); +#endif + + /* + * Check if this page should be demand-mapped. This needs to go before + * the testing for a bad kernel-space access (demand-mapping applies + * to kernel accesses too). + */ + + if ((ssw & DF) + && (buserr_type & (SUN3_BUSERR_PROTERR | SUN3_BUSERR_INVALID))) { + if (mmu_emu_handle_fault (fp->un.fmtb.daddr, ssw & RW, 0)) + return; + } + + /* Check for kernel-space pagefault (BAD). */ + if (fp->ptregs.sr & PS_S) { + /* kernel fault must be a data fault to user space */ + if (! ((ssw & DF) && ((ssw & DFC) == USER_DATA))) { + // try checking the kernel mappings before surrender + if (mmu_emu_handle_fault (fp->un.fmtb.daddr, ssw & RW, 1)) + return; + /* instruction fault or kernel data fault! */ + if (ssw & (FC | FB)) + printk ("Instruction fault at %#010lx\n", + fp->ptregs.pc); + if (ssw & DF) { + /* was this fault incurred testing bus mappings? */ + if((fp->ptregs.pc >= (unsigned long)&_sun3_map_test_start) && + (fp->ptregs.pc <= (unsigned long)&_sun3_map_test_end)) { + send_fault_sig(&fp->ptregs); + return; + } + + printk ("Data %s fault at %#010lx in %s (pc=%#lx)\n", + ssw & RW ? "read" : "write", + fp->un.fmtb.daddr, + space_names[ssw & DFC], fp->ptregs.pc); + } + printk ("BAD KERNEL BUSERR\n"); + + die_if_kernel("Oops", &fp->ptregs,0); + force_sig(SIGKILL, current); + return; + } + } else { + /* user fault */ + if (!(ssw & (FC | FB)) && !(ssw & DF)) + /* not an instruction fault or data fault! BAD */ + panic ("USER BUSERR w/o instruction or data fault"); + } + + + /* First handle the data fault, if any. */ + if (ssw & DF) { + addr = fp->un.fmtb.daddr; + +// errorcode bit 0: 0 -> no page 1 -> protection fault +// errorcode bit 1: 0 -> read fault 1 -> write fault + +// (buserr_type & SUN3_BUSERR_PROTERR) -> protection fault +// (buserr_type & SUN3_BUSERR_INVALID) -> invalid page fault + + if (buserr_type & SUN3_BUSERR_PROTERR) + errorcode = 0x01; + else if (buserr_type & SUN3_BUSERR_INVALID) + errorcode = 0x00; + else { +#ifdef DEBUG + printk ("*** unexpected busfault type=%#04x\n", buserr_type); + printk ("invalid %s access at %#lx from pc %#lx\n", + !(ssw & RW) ? "write" : "read", addr, + fp->ptregs.pc); +#endif + die_if_kernel ("Oops", &fp->ptregs, buserr_type); + force_sig (SIGBUS, current); + return; + } + +//todo: wtf is RM bit? --m + if (!(ssw & RW) || ssw & RM) + errorcode |= 0x02; + + /* Handle page fault. */ + do_page_fault (&fp->ptregs, addr, errorcode); + + /* Retry the data fault now. */ + return; + } + + /* Now handle the instruction fault. */ + + /* Get the fault address. */ + if (fp->ptregs.format == 0xA) + addr = fp->ptregs.pc + 4; + else + addr = fp->un.fmtb.baddr; + if (ssw & FC) + addr -= 2; + + if (buserr_type & SUN3_BUSERR_INVALID) { + if (!mmu_emu_handle_fault (fp->un.fmtb.daddr, 1, 0)) + do_page_fault (&fp->ptregs, addr, 0); + } else { +#ifdef DEBUG + printk ("protection fault on insn access (segv).\n"); +#endif + force_sig (SIGSEGV, current); + } +} +#else +#if defined(CPU_M68020_OR_M68030) +static inline void bus_error030 (struct frame *fp) +{ + volatile unsigned short temp; + unsigned short mmusr; + unsigned long addr, errorcode; + unsigned short ssw = fp->un.fmtb.ssw; +#ifdef DEBUG + unsigned long desc; + + printk ("pid = %x ", current->pid); + printk ("SSW=%#06x ", ssw); + + if (ssw & (FC | FB)) + printk ("Instruction fault at %#010lx\n", + ssw & FC ? + fp->ptregs.format == 0xa ? fp->ptregs.pc + 2 : fp->un.fmtb.baddr - 2 + : + fp->ptregs.format == 0xa ? fp->ptregs.pc + 4 : fp->un.fmtb.baddr); + if (ssw & DF) + printk ("Data %s fault at %#010lx in %s (pc=%#lx)\n", + ssw & RW ? "read" : "write", + fp->un.fmtb.daddr, + space_names[ssw & DFC], fp->ptregs.pc); +#endif + + /* ++andreas: If a data fault and an instruction fault happen + at the same time map in both pages. */ + + /* First handle the data fault, if any. */ + if (ssw & DF) { + addr = fp->un.fmtb.daddr; + +#ifdef DEBUG + asm volatile ("ptestr %3,%2@,#7,%0\n\t" + "pmove %%psr,%1@" + : "=a&" (desc) + : "a" (&temp), "a" (addr), "d" (ssw)); +#else + asm volatile ("ptestr %2,%1@,#7\n\t" + "pmove %%psr,%0@" + : : "a" (&temp), "a" (addr), "d" (ssw)); +#endif + mmusr = temp; + +#ifdef DEBUG + printk("mmusr is %#x for addr %#lx in task %p\n", + mmusr, addr, current); + printk("descriptor address is %#lx, contents %#lx\n", + __va(desc), *(unsigned long *)__va(desc)); +#endif + + errorcode = (mmusr & MMU_I) ? 0 : 1; + if (!(ssw & RW) || (ssw & RM)) + errorcode |= 2; + + if (mmusr & (MMU_I | MMU_WP)) { + if (ssw & 4) { + printk("Data %s fault at %#010lx in %s (pc=%#lx)\n", + ssw & RW ? "read" : "write", + fp->un.fmtb.daddr, + space_names[ssw & DFC], fp->ptregs.pc); + goto buserr; + } + /* Don't try to do anything further if an exception was + handled. */ + if (do_page_fault (&fp->ptregs, addr, errorcode) < 0) + return; + } else if (!(mmusr & MMU_I)) { + /* probably a 020 cas fault */ + if (!(ssw & RM) && send_fault_sig(&fp->ptregs) > 0) + printk("unexpected bus error (%#x,%#x)\n", ssw, mmusr); + } else if (mmusr & (MMU_B|MMU_L|MMU_S)) { + printk("invalid %s access at %#lx from pc %#lx\n", + !(ssw & RW) ? "write" : "read", addr, + fp->ptregs.pc); + die_if_kernel("Oops",&fp->ptregs,mmusr); + force_sig(SIGSEGV, current); + return; + } else { +#if 0 + static volatile long tlong; +#endif + + printk("weird %s access at %#lx from pc %#lx (ssw is %#x)\n", + !(ssw & RW) ? "write" : "read", addr, + fp->ptregs.pc, ssw); + asm volatile ("ptestr #1,%1@,#0\n\t" + "pmove %%psr,%0@" + : /* no outputs */ + : "a" (&temp), "a" (addr)); + mmusr = temp; + + printk ("level 0 mmusr is %#x\n", mmusr); +#if 0 + asm volatile ("pmove %%tt0,%0@" + : /* no outputs */ + : "a" (&tlong)); + printk("tt0 is %#lx, ", tlong); + asm volatile ("pmove %%tt1,%0@" + : /* no outputs */ + : "a" (&tlong)); + printk("tt1 is %#lx\n", tlong); +#endif +#ifdef DEBUG + printk("Unknown SIGSEGV - 1\n"); +#endif + die_if_kernel("Oops",&fp->ptregs,mmusr); + force_sig(SIGSEGV, current); + return; + } + + /* setup an ATC entry for the access about to be retried */ + if (!(ssw & RW) || (ssw & RM)) + asm volatile ("ploadw %1,%0@" : /* no outputs */ + : "a" (addr), "d" (ssw)); + else + asm volatile ("ploadr %1,%0@" : /* no outputs */ + : "a" (addr), "d" (ssw)); + } + + /* Now handle the instruction fault. */ + + if (!(ssw & (FC|FB))) + return; + + if (fp->ptregs.sr & PS_S) { + printk("Instruction fault at %#010lx\n", + fp->ptregs.pc); + buserr: + printk ("BAD KERNEL BUSERR\n"); + die_if_kernel("Oops",&fp->ptregs,0); + force_sig(SIGKILL, current); + return; + } + + /* get the fault address */ + if (fp->ptregs.format == 10) + addr = fp->ptregs.pc + 4; + else + addr = fp->un.fmtb.baddr; + if (ssw & FC) + addr -= 2; + + if ((ssw & DF) && ((addr ^ fp->un.fmtb.daddr) & PAGE_MASK) == 0) + /* Insn fault on same page as data fault. But we + should still create the ATC entry. */ + goto create_atc_entry; + +#ifdef DEBUG + asm volatile ("ptestr #1,%2@,#7,%0\n\t" + "pmove %%psr,%1@" + : "=a&" (desc) + : "a" (&temp), "a" (addr)); +#else + asm volatile ("ptestr #1,%1@,#7\n\t" + "pmove %%psr,%0@" + : : "a" (&temp), "a" (addr)); +#endif + mmusr = temp; + +#ifdef DEBUG + printk ("mmusr is %#x for addr %#lx in task %p\n", + mmusr, addr, current); + printk ("descriptor address is %#lx, contents %#lx\n", + __va(desc), *(unsigned long *)__va(desc)); +#endif + + if (mmusr & MMU_I) + do_page_fault (&fp->ptregs, addr, 0); + else if (mmusr & (MMU_B|MMU_L|MMU_S)) { + printk ("invalid insn access at %#lx from pc %#lx\n", + addr, fp->ptregs.pc); +#ifdef DEBUG + printk("Unknown SIGSEGV - 2\n"); +#endif + die_if_kernel("Oops",&fp->ptregs,mmusr); + force_sig(SIGSEGV, current); + return; + } + +create_atc_entry: + /* setup an ATC entry for the access about to be retried */ + asm volatile ("ploadr #2,%0@" : /* no outputs */ + : "a" (addr)); +} +#endif /* CPU_M68020_OR_M68030 */ +#endif /* !CONFIG_SUN3 */ + +asmlinkage void buserr_c(struct frame *fp) +{ + /* Only set esp0 if coming from user mode */ + if (user_mode(&fp->ptregs)) + current->thread.esp0 = (unsigned long) fp; + +#ifdef DEBUG + printk ("*** Bus Error *** Format is %x\n", fp->ptregs.format); +#endif + + switch (fp->ptregs.format) { +#if defined (CONFIG_M68060) + case 4: /* 68060 access error */ + access_error060 (fp); + break; +#endif +#if defined (CONFIG_M68040) + case 0x7: /* 68040 access error */ + access_error040 (fp); + break; +#endif +#if defined (CPU_M68020_OR_M68030) + case 0xa: + case 0xb: + bus_error030 (fp); + break; +#endif + default: + die_if_kernel("bad frame format",&fp->ptregs,0); +#ifdef DEBUG + printk("Unknown SIGSEGV - 4\n"); +#endif + force_sig(SIGSEGV, current); + } +} + + +static int kstack_depth_to_print = 48; + +void show_trace(unsigned long *stack) +{ + unsigned long *endstack; + unsigned long addr; + int i; + + printk("Call Trace:"); + addr = (unsigned long)stack + THREAD_SIZE - 1; + endstack = (unsigned long *)(addr & -THREAD_SIZE); + i = 0; + while (stack + 1 <= endstack) { + addr = *stack++; + /* + * If the address is either in the text segment of the + * kernel, or in the region which contains vmalloc'ed + * memory, it *may* be the address of a calling + * routine; if so, print it so that someone tracing + * down the cause of the crash will be able to figure + * out the call path that was taken. + */ + if (__kernel_text_address(addr)) { +#ifndef CONFIG_KALLSYMS + if (i % 5 == 0) + printk("\n "); +#endif + printk(" [<%08lx>] %pS\n", addr, (void *)addr); + i++; + } + } + printk("\n"); +} + +void show_registers(struct pt_regs *regs) +{ + struct frame *fp = (struct frame *)regs; + mm_segment_t old_fs = get_fs(); + u16 c, *cp; + unsigned long addr; + int i; + + print_modules(); + printk("PC: [<%08lx>] %pS\n", regs->pc, (void *)regs->pc); + printk("SR: %04x SP: %p a2: %08lx\n", regs->sr, regs, regs->a2); + printk("d0: %08lx d1: %08lx d2: %08lx d3: %08lx\n", + regs->d0, regs->d1, regs->d2, regs->d3); + printk("d4: %08lx d5: %08lx a0: %08lx a1: %08lx\n", + regs->d4, regs->d5, regs->a0, regs->a1); + + printk("Process %s (pid: %d, task=%p)\n", + current->comm, task_pid_nr(current), current); + addr = (unsigned long)&fp->un; + printk("Frame format=%X ", regs->format); + switch (regs->format) { + case 0x2: + printk("instr addr=%08lx\n", fp->un.fmt2.iaddr); + addr += sizeof(fp->un.fmt2); + break; + case 0x3: + printk("eff addr=%08lx\n", fp->un.fmt3.effaddr); + addr += sizeof(fp->un.fmt3); + break; + case 0x4: + printk((CPU_IS_060 ? "fault addr=%08lx fslw=%08lx\n" + : "eff addr=%08lx pc=%08lx\n"), + fp->un.fmt4.effaddr, fp->un.fmt4.pc); + addr += sizeof(fp->un.fmt4); + break; + case 0x7: + printk("eff addr=%08lx ssw=%04x faddr=%08lx\n", + fp->un.fmt7.effaddr, fp->un.fmt7.ssw, fp->un.fmt7.faddr); + printk("wb 1 stat/addr/data: %04x %08lx %08lx\n", + fp->un.fmt7.wb1s, fp->un.fmt7.wb1a, fp->un.fmt7.wb1dpd0); + printk("wb 2 stat/addr/data: %04x %08lx %08lx\n", + fp->un.fmt7.wb2s, fp->un.fmt7.wb2a, fp->un.fmt7.wb2d); + printk("wb 3 stat/addr/data: %04x %08lx %08lx\n", + fp->un.fmt7.wb3s, fp->un.fmt7.wb3a, fp->un.fmt7.wb3d); + printk("push data: %08lx %08lx %08lx %08lx\n", + fp->un.fmt7.wb1dpd0, fp->un.fmt7.pd1, fp->un.fmt7.pd2, + fp->un.fmt7.pd3); + addr += sizeof(fp->un.fmt7); + break; + case 0x9: + printk("instr addr=%08lx\n", fp->un.fmt9.iaddr); + addr += sizeof(fp->un.fmt9); + break; + case 0xa: + printk("ssw=%04x isc=%04x isb=%04x daddr=%08lx dobuf=%08lx\n", + fp->un.fmta.ssw, fp->un.fmta.isc, fp->un.fmta.isb, + fp->un.fmta.daddr, fp->un.fmta.dobuf); + addr += sizeof(fp->un.fmta); + break; + case 0xb: + printk("ssw=%04x isc=%04x isb=%04x daddr=%08lx dobuf=%08lx\n", + fp->un.fmtb.ssw, fp->un.fmtb.isc, fp->un.fmtb.isb, + fp->un.fmtb.daddr, fp->un.fmtb.dobuf); + printk("baddr=%08lx dibuf=%08lx ver=%x\n", + fp->un.fmtb.baddr, fp->un.fmtb.dibuf, fp->un.fmtb.ver); + addr += sizeof(fp->un.fmtb); + break; + default: + printk("\n"); + } + show_stack(NULL, (unsigned long *)addr); + + printk("Code:"); + set_fs(KERNEL_DS); + cp = (u16 *)regs->pc; + for (i = -8; i < 16; i++) { + if (get_user(c, cp + i) && i >= 0) { + printk(" Bad PC value."); + break; + } + printk(i ? " %04x" : " <%04x>", c); + } + set_fs(old_fs); + printk ("\n"); +} + +void show_stack(struct task_struct *task, unsigned long *stack) +{ + unsigned long *p; + unsigned long *endstack; + int i; + + if (!stack) { + if (task) + stack = (unsigned long *)task->thread.esp0; + else + stack = (unsigned long *)&stack; + } + endstack = (unsigned long *)(((unsigned long)stack + THREAD_SIZE - 1) & -THREAD_SIZE); + + printk("Stack from %08lx:", (unsigned long)stack); + p = stack; + for (i = 0; i < kstack_depth_to_print; i++) { + if (p + 1 > endstack) + break; + if (i % 8 == 0) + printk("\n "); + printk(" %08lx", *p++); + } + printk("\n"); + show_trace(stack); +} + +/* + * The architecture-independent backtrace generator + */ +void dump_stack(void) +{ + unsigned long stack; + + show_trace(&stack); +} + +EXPORT_SYMBOL(dump_stack); + +void bad_super_trap (struct frame *fp) +{ + console_verbose(); + if (fp->ptregs.vector < 4 * ARRAY_SIZE(vec_names)) + printk ("*** %s *** FORMAT=%X\n", + vec_names[(fp->ptregs.vector) >> 2], + fp->ptregs.format); + else + printk ("*** Exception %d *** FORMAT=%X\n", + (fp->ptregs.vector) >> 2, + fp->ptregs.format); + if (fp->ptregs.vector >> 2 == VEC_ADDRERR && CPU_IS_020_OR_030) { + unsigned short ssw = fp->un.fmtb.ssw; + + printk ("SSW=%#06x ", ssw); + + if (ssw & RC) + printk ("Pipe stage C instruction fault at %#010lx\n", + (fp->ptregs.format) == 0xA ? + fp->ptregs.pc + 2 : fp->un.fmtb.baddr - 2); + if (ssw & RB) + printk ("Pipe stage B instruction fault at %#010lx\n", + (fp->ptregs.format) == 0xA ? + fp->ptregs.pc + 4 : fp->un.fmtb.baddr); + if (ssw & DF) + printk ("Data %s fault at %#010lx in %s (pc=%#lx)\n", + ssw & RW ? "read" : "write", + fp->un.fmtb.daddr, space_names[ssw & DFC], + fp->ptregs.pc); + } + printk ("Current process id is %d\n", task_pid_nr(current)); + die_if_kernel("BAD KERNEL TRAP", &fp->ptregs, 0); +} + +asmlinkage void trap_c(struct frame *fp) +{ + int sig; + siginfo_t info; + + if (fp->ptregs.sr & PS_S) { + if (fp->ptregs.vector == VEC_TRACE << 2) { + /* traced a trapping instruction on a 68020/30, + * real exception will be executed afterwards. + */ + } else if (!handle_kernel_fault(&fp->ptregs)) + bad_super_trap(fp); + return; + } + + /* send the appropriate signal to the user program */ + switch ((fp->ptregs.vector) >> 2) { + case VEC_ADDRERR: + info.si_code = BUS_ADRALN; + sig = SIGBUS; + break; + case VEC_ILLEGAL: + case VEC_LINE10: + case VEC_LINE11: + info.si_code = ILL_ILLOPC; + sig = SIGILL; + break; + case VEC_PRIV: + info.si_code = ILL_PRVOPC; + sig = SIGILL; + break; + case VEC_COPROC: + info.si_code = ILL_COPROC; + sig = SIGILL; + break; + case VEC_TRAP1: + case VEC_TRAP2: + case VEC_TRAP3: + case VEC_TRAP4: + case VEC_TRAP5: + case VEC_TRAP6: + case VEC_TRAP7: + case VEC_TRAP8: + case VEC_TRAP9: + case VEC_TRAP10: + case VEC_TRAP11: + case VEC_TRAP12: + case VEC_TRAP13: + case VEC_TRAP14: + info.si_code = ILL_ILLTRP; + sig = SIGILL; + break; + case VEC_FPBRUC: + case VEC_FPOE: + case VEC_FPNAN: + info.si_code = FPE_FLTINV; + sig = SIGFPE; + break; + case VEC_FPIR: + info.si_code = FPE_FLTRES; + sig = SIGFPE; + break; + case VEC_FPDIVZ: + info.si_code = FPE_FLTDIV; + sig = SIGFPE; + break; + case VEC_FPUNDER: + info.si_code = FPE_FLTUND; + sig = SIGFPE; + break; + case VEC_FPOVER: + info.si_code = FPE_FLTOVF; + sig = SIGFPE; + break; + case VEC_ZERODIV: + info.si_code = FPE_INTDIV; + sig = SIGFPE; + break; + case VEC_CHK: + case VEC_TRAP: + info.si_code = FPE_INTOVF; + sig = SIGFPE; + break; + case VEC_TRACE: /* ptrace single step */ + info.si_code = TRAP_TRACE; + sig = SIGTRAP; + break; + case VEC_TRAP15: /* breakpoint */ + info.si_code = TRAP_BRKPT; + sig = SIGTRAP; + break; + default: + info.si_code = ILL_ILLOPC; + sig = SIGILL; + break; + } + info.si_signo = sig; + info.si_errno = 0; + switch (fp->ptregs.format) { + default: + info.si_addr = (void *) fp->ptregs.pc; + break; + case 2: + info.si_addr = (void *) fp->un.fmt2.iaddr; + break; + case 7: + info.si_addr = (void *) fp->un.fmt7.effaddr; + break; + case 9: + info.si_addr = (void *) fp->un.fmt9.iaddr; + break; + case 10: + info.si_addr = (void *) fp->un.fmta.daddr; + break; + case 11: + info.si_addr = (void *) fp->un.fmtb.daddr; + break; + } + force_sig_info (sig, &info, current); +} + +void die_if_kernel (char *str, struct pt_regs *fp, int nr) +{ + if (!(fp->sr & PS_S)) + return; + + console_verbose(); + printk("%s: %08x\n",str,nr); + show_registers(fp); + add_taint(TAINT_DIE); + do_exit(SIGSEGV); +} + +/* + * This function is called if an error occur while accessing + * user-space from the fpsp040 code. + */ +asmlinkage void fpsp040_die(void) +{ + do_exit(SIGSEGV); +} + +#ifdef CONFIG_M68KFPU_EMU +asmlinkage void fpemu_signal(int signal, int code, void *addr) +{ + siginfo_t info; + + info.si_signo = signal; + info.si_errno = 0; + info.si_code = code; + info.si_addr = addr; + force_sig_info(signal, &info, current); +} +#endif diff --git a/arch/m68knommu/kernel/traps.c b/arch/m68k/kernel/traps_no.c index a768008dfd0..a768008dfd0 100644 --- a/arch/m68knommu/kernel/traps.c +++ b/arch/m68k/kernel/traps_no.c diff --git a/arch/m68k/kernel/vmlinux.lds.S b/arch/m68k/kernel/vmlinux.lds.S index 99ba315bd0a..030dabf0bc5 100644 --- a/arch/m68k/kernel/vmlinux.lds.S +++ b/arch/m68k/kernel/vmlinux.lds.S @@ -1,10 +1,5 @@ -PHDRS -{ - text PT_LOAD FILEHDR PHDRS FLAGS (7); - data PT_LOAD FLAGS (7); -} -#ifdef CONFIG_SUN3 -#include "vmlinux-sun3.lds" +#ifdef CONFIG_MMU +#include "vmlinux.lds_mm.S" #else -#include "vmlinux-std.lds" +#include "vmlinux.lds_no.S" #endif diff --git a/arch/m68k/kernel/vmlinux.lds_mm.S b/arch/m68k/kernel/vmlinux.lds_mm.S new file mode 100644 index 00000000000..99ba315bd0a --- /dev/null +++ b/arch/m68k/kernel/vmlinux.lds_mm.S @@ -0,0 +1,10 @@ +PHDRS +{ + text PT_LOAD FILEHDR PHDRS FLAGS (7); + data PT_LOAD FLAGS (7); +} +#ifdef CONFIG_SUN3 +#include "vmlinux-sun3.lds" +#else +#include "vmlinux-std.lds" +#endif diff --git a/arch/m68knommu/kernel/vmlinux.lds.S b/arch/m68k/kernel/vmlinux.lds_no.S index 47e15ebfd89..f4d715cdca0 100644 --- a/arch/m68knommu/kernel/vmlinux.lds.S +++ b/arch/m68k/kernel/vmlinux.lds_no.S @@ -3,7 +3,7 @@ * * (C) Copyright 2002-2006, Greg Ungerer <gerg@snapgear.com> * - * This linker script is equiped to build either ROM loaded or RAM + * This linker script is equipped to build either ROM loaded or RAM * run kernels. */ diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile index af9abf8d9d9..1f95881d843 100644 --- a/arch/m68k/lib/Makefile +++ b/arch/m68k/lib/Makefile @@ -1,6 +1,5 @@ -# -# Makefile for m68k-specific library files.. -# - -lib-y := ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \ - checksum.o string.o uaccess.o +ifdef CONFIG_MMU +include arch/m68k/lib/Makefile_mm +else +include arch/m68k/lib/Makefile_no +endif diff --git a/arch/m68k/lib/Makefile_mm b/arch/m68k/lib/Makefile_mm new file mode 100644 index 00000000000..af9abf8d9d9 --- /dev/null +++ b/arch/m68k/lib/Makefile_mm @@ -0,0 +1,6 @@ +# +# Makefile for m68k-specific library files.. +# + +lib-y := ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \ + checksum.o string.o uaccess.o diff --git a/arch/m68knommu/lib/Makefile b/arch/m68k/lib/Makefile_no index 32d852e586d..32d852e586d 100644 --- a/arch/m68knommu/lib/Makefile +++ b/arch/m68k/lib/Makefile_no diff --git a/arch/m68k/lib/checksum.c b/arch/m68k/lib/checksum.c index 6216f12a756..1297536060d 100644 --- a/arch/m68k/lib/checksum.c +++ b/arch/m68k/lib/checksum.c @@ -1,425 +1,5 @@ -/* - * INET An implementation of the TCP/IP protocol suite for the LINUX - * operating system. INET is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * IP/TCP/UDP checksumming routines - * - * Authors: Jorge Cwik, <jorge@laser.satlink.net> - * Arnt Gulbrandsen, <agulbra@nvg.unit.no> - * Tom May, <ftom@netcom.com> - * Andreas Schwab, <schwab@issan.informatik.uni-dortmund.de> - * Lots of code moved from tcp.c and ip.c; see those files - * for more names. - * - * 03/02/96 Jes Sorensen, Andreas Schwab, Roman Hodek: - * Fixed some nasty bugs, causing some horrible crashes. - * A: At some points, the sum (%0) was used as - * length-counter instead of the length counter - * (%1). Thanks to Roman Hodek for pointing this out. - * B: GCC seems to mess up if one uses too many - * data-registers to hold input values and one tries to - * specify d0 and d1 as scratch registers. Letting gcc - * choose these registers itself solves the problem. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * 1998/8/31 Andreas Schwab: - * Zero out rest of buffer on exception in - * csum_partial_copy_from_user. - */ - -#include <linux/module.h> -#include <net/checksum.h> - -/* - * computes a partial checksum, e.g. for TCP/UDP fragments - */ - -__wsum csum_partial(const void *buff, int len, __wsum sum) -{ - unsigned long tmp1, tmp2; - /* - * Experiments with ethernet and slip connections show that buff - * is aligned on either a 2-byte or 4-byte boundary. - */ - __asm__("movel %2,%3\n\t" - "btst #1,%3\n\t" /* Check alignment */ - "jeq 2f\n\t" - "subql #2,%1\n\t" /* buff%4==2: treat first word */ - "jgt 1f\n\t" - "addql #2,%1\n\t" /* len was == 2, treat only rest */ - "jra 4f\n" - "1:\t" - "addw %2@+,%0\n\t" /* add first word to sum */ - "clrl %3\n\t" - "addxl %3,%0\n" /* add X bit */ - "2:\t" - /* unrolled loop for the main part: do 8 longs at once */ - "movel %1,%3\n\t" /* save len in tmp1 */ - "lsrl #5,%1\n\t" /* len/32 */ - "jeq 2f\n\t" /* not enough... */ - "subql #1,%1\n" - "1:\t" - "movel %2@+,%4\n\t" - "addxl %4,%0\n\t" - "movel %2@+,%4\n\t" - "addxl %4,%0\n\t" - "movel %2@+,%4\n\t" - "addxl %4,%0\n\t" - "movel %2@+,%4\n\t" - "addxl %4,%0\n\t" - "movel %2@+,%4\n\t" - "addxl %4,%0\n\t" - "movel %2@+,%4\n\t" - "addxl %4,%0\n\t" - "movel %2@+,%4\n\t" - "addxl %4,%0\n\t" - "movel %2@+,%4\n\t" - "addxl %4,%0\n\t" - "dbra %1,1b\n\t" - "clrl %4\n\t" - "addxl %4,%0\n\t" /* add X bit */ - "clrw %1\n\t" - "subql #1,%1\n\t" - "jcc 1b\n" - "2:\t" - "movel %3,%1\n\t" /* restore len from tmp1 */ - "andw #0x1c,%3\n\t" /* number of rest longs */ - "jeq 4f\n\t" - "lsrw #2,%3\n\t" - "subqw #1,%3\n" - "3:\t" - /* loop for rest longs */ - "movel %2@+,%4\n\t" - "addxl %4,%0\n\t" - "dbra %3,3b\n\t" - "clrl %4\n\t" - "addxl %4,%0\n" /* add X bit */ - "4:\t" - /* now check for rest bytes that do not fit into longs */ - "andw #3,%1\n\t" - "jeq 7f\n\t" - "clrl %4\n\t" /* clear tmp2 for rest bytes */ - "subqw #2,%1\n\t" - "jlt 5f\n\t" - "movew %2@+,%4\n\t" /* have rest >= 2: get word */ - "swap %4\n\t" /* into bits 16..31 */ - "tstw %1\n\t" /* another byte? */ - "jeq 6f\n" - "5:\t" - "moveb %2@,%4\n\t" /* have odd rest: get byte */ - "lslw #8,%4\n\t" /* into bits 8..15; 16..31 untouched */ - "6:\t" - "addl %4,%0\n\t" /* now add rest long to sum */ - "clrl %4\n\t" - "addxl %4,%0\n" /* add X bit */ - "7:\t" - : "=d" (sum), "=d" (len), "=a" (buff), - "=&d" (tmp1), "=&d" (tmp2) - : "0" (sum), "1" (len), "2" (buff) - ); - return(sum); -} - -EXPORT_SYMBOL(csum_partial); - - -/* - * copy from user space while checksumming, with exception handling. - */ - -__wsum -csum_partial_copy_from_user(const void __user *src, void *dst, - int len, __wsum sum, int *csum_err) -{ - /* - * GCC doesn't like more than 10 operands for the asm - * statements so we have to use tmp2 for the error - * code. - */ - unsigned long tmp1, tmp2; - - __asm__("movel %2,%4\n\t" - "btst #1,%4\n\t" /* Check alignment */ - "jeq 2f\n\t" - "subql #2,%1\n\t" /* buff%4==2: treat first word */ - "jgt 1f\n\t" - "addql #2,%1\n\t" /* len was == 2, treat only rest */ - "jra 4f\n" - "1:\n" - "10:\t" - "movesw %2@+,%4\n\t" /* add first word to sum */ - "addw %4,%0\n\t" - "movew %4,%3@+\n\t" - "clrl %4\n\t" - "addxl %4,%0\n" /* add X bit */ - "2:\t" - /* unrolled loop for the main part: do 8 longs at once */ - "movel %1,%4\n\t" /* save len in tmp1 */ - "lsrl #5,%1\n\t" /* len/32 */ - "jeq 2f\n\t" /* not enough... */ - "subql #1,%1\n" - "1:\n" - "11:\t" - "movesl %2@+,%5\n\t" - "addxl %5,%0\n\t" - "movel %5,%3@+\n\t" - "12:\t" - "movesl %2@+,%5\n\t" - "addxl %5,%0\n\t" - "movel %5,%3@+\n\t" - "13:\t" - "movesl %2@+,%5\n\t" - "addxl %5,%0\n\t" - "movel %5,%3@+\n\t" - "14:\t" - "movesl %2@+,%5\n\t" - "addxl %5,%0\n\t" - "movel %5,%3@+\n\t" - "15:\t" - "movesl %2@+,%5\n\t" - "addxl %5,%0\n\t" - "movel %5,%3@+\n\t" - "16:\t" - "movesl %2@+,%5\n\t" - "addxl %5,%0\n\t" - "movel %5,%3@+\n\t" - "17:\t" - "movesl %2@+,%5\n\t" - "addxl %5,%0\n\t" - "movel %5,%3@+\n\t" - "18:\t" - "movesl %2@+,%5\n\t" - "addxl %5,%0\n\t" - "movel %5,%3@+\n\t" - "dbra %1,1b\n\t" - "clrl %5\n\t" - "addxl %5,%0\n\t" /* add X bit */ - "clrw %1\n\t" - "subql #1,%1\n\t" - "jcc 1b\n" - "2:\t" - "movel %4,%1\n\t" /* restore len from tmp1 */ - "andw #0x1c,%4\n\t" /* number of rest longs */ - "jeq 4f\n\t" - "lsrw #2,%4\n\t" - "subqw #1,%4\n" - "3:\n" - /* loop for rest longs */ - "19:\t" - "movesl %2@+,%5\n\t" - "addxl %5,%0\n\t" - "movel %5,%3@+\n\t" - "dbra %4,3b\n\t" - "clrl %5\n\t" - "addxl %5,%0\n" /* add X bit */ - "4:\t" - /* now check for rest bytes that do not fit into longs */ - "andw #3,%1\n\t" - "jeq 7f\n\t" - "clrl %5\n\t" /* clear tmp2 for rest bytes */ - "subqw #2,%1\n\t" - "jlt 5f\n\t" - "20:\t" - "movesw %2@+,%5\n\t" /* have rest >= 2: get word */ - "movew %5,%3@+\n\t" - "swap %5\n\t" /* into bits 16..31 */ - "tstw %1\n\t" /* another byte? */ - "jeq 6f\n" - "5:\n" - "21:\t" - "movesb %2@,%5\n\t" /* have odd rest: get byte */ - "moveb %5,%3@+\n\t" - "lslw #8,%5\n\t" /* into bits 8..15; 16..31 untouched */ - "6:\t" - "addl %5,%0\n\t" /* now add rest long to sum */ - "clrl %5\n\t" - "addxl %5,%0\n\t" /* add X bit */ - "7:\t" - "clrl %5\n" /* no error - clear return value */ - "8:\n" - ".section .fixup,\"ax\"\n" - ".even\n" - /* If any exception occurs zero out the rest. - Similarities with the code above are intentional :-) */ - "90:\t" - "clrw %3@+\n\t" - "movel %1,%4\n\t" - "lsrl #5,%1\n\t" - "jeq 1f\n\t" - "subql #1,%1\n" - "91:\t" - "clrl %3@+\n" - "92:\t" - "clrl %3@+\n" - "93:\t" - "clrl %3@+\n" - "94:\t" - "clrl %3@+\n" - "95:\t" - "clrl %3@+\n" - "96:\t" - "clrl %3@+\n" - "97:\t" - "clrl %3@+\n" - "98:\t" - "clrl %3@+\n\t" - "dbra %1,91b\n\t" - "clrw %1\n\t" - "subql #1,%1\n\t" - "jcc 91b\n" - "1:\t" - "movel %4,%1\n\t" - "andw #0x1c,%4\n\t" - "jeq 1f\n\t" - "lsrw #2,%4\n\t" - "subqw #1,%4\n" - "99:\t" - "clrl %3@+\n\t" - "dbra %4,99b\n\t" - "1:\t" - "andw #3,%1\n\t" - "jeq 9f\n" - "100:\t" - "clrw %3@+\n\t" - "tstw %1\n\t" - "jeq 9f\n" - "101:\t" - "clrb %3@+\n" - "9:\t" -#define STR(X) STR1(X) -#define STR1(X) #X - "moveq #-" STR(EFAULT) ",%5\n\t" - "jra 8b\n" - ".previous\n" - ".section __ex_table,\"a\"\n" - ".long 10b,90b\n" - ".long 11b,91b\n" - ".long 12b,92b\n" - ".long 13b,93b\n" - ".long 14b,94b\n" - ".long 15b,95b\n" - ".long 16b,96b\n" - ".long 17b,97b\n" - ".long 18b,98b\n" - ".long 19b,99b\n" - ".long 20b,100b\n" - ".long 21b,101b\n" - ".previous" - : "=d" (sum), "=d" (len), "=a" (src), "=a" (dst), - "=&d" (tmp1), "=d" (tmp2) - : "0" (sum), "1" (len), "2" (src), "3" (dst) - ); - - *csum_err = tmp2; - - return(sum); -} - -EXPORT_SYMBOL(csum_partial_copy_from_user); - - -/* - * copy from kernel space while checksumming, otherwise like csum_partial - */ - -__wsum -csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum) -{ - unsigned long tmp1, tmp2; - __asm__("movel %2,%4\n\t" - "btst #1,%4\n\t" /* Check alignment */ - "jeq 2f\n\t" - "subql #2,%1\n\t" /* buff%4==2: treat first word */ - "jgt 1f\n\t" - "addql #2,%1\n\t" /* len was == 2, treat only rest */ - "jra 4f\n" - "1:\t" - "movew %2@+,%4\n\t" /* add first word to sum */ - "addw %4,%0\n\t" - "movew %4,%3@+\n\t" - "clrl %4\n\t" - "addxl %4,%0\n" /* add X bit */ - "2:\t" - /* unrolled loop for the main part: do 8 longs at once */ - "movel %1,%4\n\t" /* save len in tmp1 */ - "lsrl #5,%1\n\t" /* len/32 */ - "jeq 2f\n\t" /* not enough... */ - "subql #1,%1\n" - "1:\t" - "movel %2@+,%5\n\t" - "addxl %5,%0\n\t" - "movel %5,%3@+\n\t" - "movel %2@+,%5\n\t" - "addxl %5,%0\n\t" - "movel %5,%3@+\n\t" - "movel %2@+,%5\n\t" - "addxl %5,%0\n\t" - "movel %5,%3@+\n\t" - "movel %2@+,%5\n\t" - "addxl %5,%0\n\t" - "movel %5,%3@+\n\t" - "movel %2@+,%5\n\t" - "addxl %5,%0\n\t" - "movel %5,%3@+\n\t" - "movel %2@+,%5\n\t" - "addxl %5,%0\n\t" - "movel %5,%3@+\n\t" - "movel %2@+,%5\n\t" - "addxl %5,%0\n\t" - "movel %5,%3@+\n\t" - "movel %2@+,%5\n\t" - "addxl %5,%0\n\t" - "movel %5,%3@+\n\t" - "dbra %1,1b\n\t" - "clrl %5\n\t" - "addxl %5,%0\n\t" /* add X bit */ - "clrw %1\n\t" - "subql #1,%1\n\t" - "jcc 1b\n" - "2:\t" - "movel %4,%1\n\t" /* restore len from tmp1 */ - "andw #0x1c,%4\n\t" /* number of rest longs */ - "jeq 4f\n\t" - "lsrw #2,%4\n\t" - "subqw #1,%4\n" - "3:\t" - /* loop for rest longs */ - "movel %2@+,%5\n\t" - "addxl %5,%0\n\t" - "movel %5,%3@+\n\t" - "dbra %4,3b\n\t" - "clrl %5\n\t" - "addxl %5,%0\n" /* add X bit */ - "4:\t" - /* now check for rest bytes that do not fit into longs */ - "andw #3,%1\n\t" - "jeq 7f\n\t" - "clrl %5\n\t" /* clear tmp2 for rest bytes */ - "subqw #2,%1\n\t" - "jlt 5f\n\t" - "movew %2@+,%5\n\t" /* have rest >= 2: get word */ - "movew %5,%3@+\n\t" - "swap %5\n\t" /* into bits 16..31 */ - "tstw %1\n\t" /* another byte? */ - "jeq 6f\n" - "5:\t" - "moveb %2@,%5\n\t" /* have odd rest: get byte */ - "moveb %5,%3@+\n\t" - "lslw #8,%5\n" /* into bits 8..15; 16..31 untouched */ - "6:\t" - "addl %5,%0\n\t" /* now add rest long to sum */ - "clrl %5\n\t" - "addxl %5,%0\n" /* add X bit */ - "7:\t" - : "=d" (sum), "=d" (len), "=a" (src), "=a" (dst), - "=&d" (tmp1), "=&d" (tmp2) - : "0" (sum), "1" (len), "2" (src), "3" (dst) - ); - return(sum); -} -EXPORT_SYMBOL(csum_partial_copy_nocheck); +#ifdef CONFIG_MMU +#include "checksum_mm.c" +#else +#include "checksum_no.c" +#endif diff --git a/arch/m68k/lib/checksum_mm.c b/arch/m68k/lib/checksum_mm.c new file mode 100644 index 00000000000..6216f12a756 --- /dev/null +++ b/arch/m68k/lib/checksum_mm.c @@ -0,0 +1,425 @@ +/* + * INET An implementation of the TCP/IP protocol suite for the LINUX + * operating system. INET is implemented using the BSD Socket + * interface as the means of communication with the user level. + * + * IP/TCP/UDP checksumming routines + * + * Authors: Jorge Cwik, <jorge@laser.satlink.net> + * Arnt Gulbrandsen, <agulbra@nvg.unit.no> + * Tom May, <ftom@netcom.com> + * Andreas Schwab, <schwab@issan.informatik.uni-dortmund.de> + * Lots of code moved from tcp.c and ip.c; see those files + * for more names. + * + * 03/02/96 Jes Sorensen, Andreas Schwab, Roman Hodek: + * Fixed some nasty bugs, causing some horrible crashes. + * A: At some points, the sum (%0) was used as + * length-counter instead of the length counter + * (%1). Thanks to Roman Hodek for pointing this out. + * B: GCC seems to mess up if one uses too many + * data-registers to hold input values and one tries to + * specify d0 and d1 as scratch registers. Letting gcc + * choose these registers itself solves the problem. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * 1998/8/31 Andreas Schwab: + * Zero out rest of buffer on exception in + * csum_partial_copy_from_user. + */ + +#include <linux/module.h> +#include <net/checksum.h> + +/* + * computes a partial checksum, e.g. for TCP/UDP fragments + */ + +__wsum csum_partial(const void *buff, int len, __wsum sum) +{ + unsigned long tmp1, tmp2; + /* + * Experiments with ethernet and slip connections show that buff + * is aligned on either a 2-byte or 4-byte boundary. + */ + __asm__("movel %2,%3\n\t" + "btst #1,%3\n\t" /* Check alignment */ + "jeq 2f\n\t" + "subql #2,%1\n\t" /* buff%4==2: treat first word */ + "jgt 1f\n\t" + "addql #2,%1\n\t" /* len was == 2, treat only rest */ + "jra 4f\n" + "1:\t" + "addw %2@+,%0\n\t" /* add first word to sum */ + "clrl %3\n\t" + "addxl %3,%0\n" /* add X bit */ + "2:\t" + /* unrolled loop for the main part: do 8 longs at once */ + "movel %1,%3\n\t" /* save len in tmp1 */ + "lsrl #5,%1\n\t" /* len/32 */ + "jeq 2f\n\t" /* not enough... */ + "subql #1,%1\n" + "1:\t" + "movel %2@+,%4\n\t" + "addxl %4,%0\n\t" + "movel %2@+,%4\n\t" + "addxl %4,%0\n\t" + "movel %2@+,%4\n\t" + "addxl %4,%0\n\t" + "movel %2@+,%4\n\t" + "addxl %4,%0\n\t" + "movel %2@+,%4\n\t" + "addxl %4,%0\n\t" + "movel %2@+,%4\n\t" + "addxl %4,%0\n\t" + "movel %2@+,%4\n\t" + "addxl %4,%0\n\t" + "movel %2@+,%4\n\t" + "addxl %4,%0\n\t" + "dbra %1,1b\n\t" + "clrl %4\n\t" + "addxl %4,%0\n\t" /* add X bit */ + "clrw %1\n\t" + "subql #1,%1\n\t" + "jcc 1b\n" + "2:\t" + "movel %3,%1\n\t" /* restore len from tmp1 */ + "andw #0x1c,%3\n\t" /* number of rest longs */ + "jeq 4f\n\t" + "lsrw #2,%3\n\t" + "subqw #1,%3\n" + "3:\t" + /* loop for rest longs */ + "movel %2@+,%4\n\t" + "addxl %4,%0\n\t" + "dbra %3,3b\n\t" + "clrl %4\n\t" + "addxl %4,%0\n" /* add X bit */ + "4:\t" + /* now check for rest bytes that do not fit into longs */ + "andw #3,%1\n\t" + "jeq 7f\n\t" + "clrl %4\n\t" /* clear tmp2 for rest bytes */ + "subqw #2,%1\n\t" + "jlt 5f\n\t" + "movew %2@+,%4\n\t" /* have rest >= 2: get word */ + "swap %4\n\t" /* into bits 16..31 */ + "tstw %1\n\t" /* another byte? */ + "jeq 6f\n" + "5:\t" + "moveb %2@,%4\n\t" /* have odd rest: get byte */ + "lslw #8,%4\n\t" /* into bits 8..15; 16..31 untouched */ + "6:\t" + "addl %4,%0\n\t" /* now add rest long to sum */ + "clrl %4\n\t" + "addxl %4,%0\n" /* add X bit */ + "7:\t" + : "=d" (sum), "=d" (len), "=a" (buff), + "=&d" (tmp1), "=&d" (tmp2) + : "0" (sum), "1" (len), "2" (buff) + ); + return(sum); +} + +EXPORT_SYMBOL(csum_partial); + + +/* + * copy from user space while checksumming, with exception handling. + */ + +__wsum +csum_partial_copy_from_user(const void __user *src, void *dst, + int len, __wsum sum, int *csum_err) +{ + /* + * GCC doesn't like more than 10 operands for the asm + * statements so we have to use tmp2 for the error + * code. + */ + unsigned long tmp1, tmp2; + + __asm__("movel %2,%4\n\t" + "btst #1,%4\n\t" /* Check alignment */ + "jeq 2f\n\t" + "subql #2,%1\n\t" /* buff%4==2: treat first word */ + "jgt 1f\n\t" + "addql #2,%1\n\t" /* len was == 2, treat only rest */ + "jra 4f\n" + "1:\n" + "10:\t" + "movesw %2@+,%4\n\t" /* add first word to sum */ + "addw %4,%0\n\t" + "movew %4,%3@+\n\t" + "clrl %4\n\t" + "addxl %4,%0\n" /* add X bit */ + "2:\t" + /* unrolled loop for the main part: do 8 longs at once */ + "movel %1,%4\n\t" /* save len in tmp1 */ + "lsrl #5,%1\n\t" /* len/32 */ + "jeq 2f\n\t" /* not enough... */ + "subql #1,%1\n" + "1:\n" + "11:\t" + "movesl %2@+,%5\n\t" + "addxl %5,%0\n\t" + "movel %5,%3@+\n\t" + "12:\t" + "movesl %2@+,%5\n\t" + "addxl %5,%0\n\t" + "movel %5,%3@+\n\t" + "13:\t" + "movesl %2@+,%5\n\t" + "addxl %5,%0\n\t" + "movel %5,%3@+\n\t" + "14:\t" + "movesl %2@+,%5\n\t" + "addxl %5,%0\n\t" + "movel %5,%3@+\n\t" + "15:\t" + "movesl %2@+,%5\n\t" + "addxl %5,%0\n\t" + "movel %5,%3@+\n\t" + "16:\t" + "movesl %2@+,%5\n\t" + "addxl %5,%0\n\t" + "movel %5,%3@+\n\t" + "17:\t" + "movesl %2@+,%5\n\t" + "addxl %5,%0\n\t" + "movel %5,%3@+\n\t" + "18:\t" + "movesl %2@+,%5\n\t" + "addxl %5,%0\n\t" + "movel %5,%3@+\n\t" + "dbra %1,1b\n\t" + "clrl %5\n\t" + "addxl %5,%0\n\t" /* add X bit */ + "clrw %1\n\t" + "subql #1,%1\n\t" + "jcc 1b\n" + "2:\t" + "movel %4,%1\n\t" /* restore len from tmp1 */ + "andw #0x1c,%4\n\t" /* number of rest longs */ + "jeq 4f\n\t" + "lsrw #2,%4\n\t" + "subqw #1,%4\n" + "3:\n" + /* loop for rest longs */ + "19:\t" + "movesl %2@+,%5\n\t" + "addxl %5,%0\n\t" + "movel %5,%3@+\n\t" + "dbra %4,3b\n\t" + "clrl %5\n\t" + "addxl %5,%0\n" /* add X bit */ + "4:\t" + /* now check for rest bytes that do not fit into longs */ + "andw #3,%1\n\t" + "jeq 7f\n\t" + "clrl %5\n\t" /* clear tmp2 for rest bytes */ + "subqw #2,%1\n\t" + "jlt 5f\n\t" + "20:\t" + "movesw %2@+,%5\n\t" /* have rest >= 2: get word */ + "movew %5,%3@+\n\t" + "swap %5\n\t" /* into bits 16..31 */ + "tstw %1\n\t" /* another byte? */ + "jeq 6f\n" + "5:\n" + "21:\t" + "movesb %2@,%5\n\t" /* have odd rest: get byte */ + "moveb %5,%3@+\n\t" + "lslw #8,%5\n\t" /* into bits 8..15; 16..31 untouched */ + "6:\t" + "addl %5,%0\n\t" /* now add rest long to sum */ + "clrl %5\n\t" + "addxl %5,%0\n\t" /* add X bit */ + "7:\t" + "clrl %5\n" /* no error - clear return value */ + "8:\n" + ".section .fixup,\"ax\"\n" + ".even\n" + /* If any exception occurs zero out the rest. + Similarities with the code above are intentional :-) */ + "90:\t" + "clrw %3@+\n\t" + "movel %1,%4\n\t" + "lsrl #5,%1\n\t" + "jeq 1f\n\t" + "subql #1,%1\n" + "91:\t" + "clrl %3@+\n" + "92:\t" + "clrl %3@+\n" + "93:\t" + "clrl %3@+\n" + "94:\t" + "clrl %3@+\n" + "95:\t" + "clrl %3@+\n" + "96:\t" + "clrl %3@+\n" + "97:\t" + "clrl %3@+\n" + "98:\t" + "clrl %3@+\n\t" + "dbra %1,91b\n\t" + "clrw %1\n\t" + "subql #1,%1\n\t" + "jcc 91b\n" + "1:\t" + "movel %4,%1\n\t" + "andw #0x1c,%4\n\t" + "jeq 1f\n\t" + "lsrw #2,%4\n\t" + "subqw #1,%4\n" + "99:\t" + "clrl %3@+\n\t" + "dbra %4,99b\n\t" + "1:\t" + "andw #3,%1\n\t" + "jeq 9f\n" + "100:\t" + "clrw %3@+\n\t" + "tstw %1\n\t" + "jeq 9f\n" + "101:\t" + "clrb %3@+\n" + "9:\t" +#define STR(X) STR1(X) +#define STR1(X) #X + "moveq #-" STR(EFAULT) ",%5\n\t" + "jra 8b\n" + ".previous\n" + ".section __ex_table,\"a\"\n" + ".long 10b,90b\n" + ".long 11b,91b\n" + ".long 12b,92b\n" + ".long 13b,93b\n" + ".long 14b,94b\n" + ".long 15b,95b\n" + ".long 16b,96b\n" + ".long 17b,97b\n" + ".long 18b,98b\n" + ".long 19b,99b\n" + ".long 20b,100b\n" + ".long 21b,101b\n" + ".previous" + : "=d" (sum), "=d" (len), "=a" (src), "=a" (dst), + "=&d" (tmp1), "=d" (tmp2) + : "0" (sum), "1" (len), "2" (src), "3" (dst) + ); + + *csum_err = tmp2; + + return(sum); +} + +EXPORT_SYMBOL(csum_partial_copy_from_user); + + +/* + * copy from kernel space while checksumming, otherwise like csum_partial + */ + +__wsum +csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum) +{ + unsigned long tmp1, tmp2; + __asm__("movel %2,%4\n\t" + "btst #1,%4\n\t" /* Check alignment */ + "jeq 2f\n\t" + "subql #2,%1\n\t" /* buff%4==2: treat first word */ + "jgt 1f\n\t" + "addql #2,%1\n\t" /* len was == 2, treat only rest */ + "jra 4f\n" + "1:\t" + "movew %2@+,%4\n\t" /* add first word to sum */ + "addw %4,%0\n\t" + "movew %4,%3@+\n\t" + "clrl %4\n\t" + "addxl %4,%0\n" /* add X bit */ + "2:\t" + /* unrolled loop for the main part: do 8 longs at once */ + "movel %1,%4\n\t" /* save len in tmp1 */ + "lsrl #5,%1\n\t" /* len/32 */ + "jeq 2f\n\t" /* not enough... */ + "subql #1,%1\n" + "1:\t" + "movel %2@+,%5\n\t" + "addxl %5,%0\n\t" + "movel %5,%3@+\n\t" + "movel %2@+,%5\n\t" + "addxl %5,%0\n\t" + "movel %5,%3@+\n\t" + "movel %2@+,%5\n\t" + "addxl %5,%0\n\t" + "movel %5,%3@+\n\t" + "movel %2@+,%5\n\t" + "addxl %5,%0\n\t" + "movel %5,%3@+\n\t" + "movel %2@+,%5\n\t" + "addxl %5,%0\n\t" + "movel %5,%3@+\n\t" + "movel %2@+,%5\n\t" + "addxl %5,%0\n\t" + "movel %5,%3@+\n\t" + "movel %2@+,%5\n\t" + "addxl %5,%0\n\t" + "movel %5,%3@+\n\t" + "movel %2@+,%5\n\t" + "addxl %5,%0\n\t" + "movel %5,%3@+\n\t" + "dbra %1,1b\n\t" + "clrl %5\n\t" + "addxl %5,%0\n\t" /* add X bit */ + "clrw %1\n\t" + "subql #1,%1\n\t" + "jcc 1b\n" + "2:\t" + "movel %4,%1\n\t" /* restore len from tmp1 */ + "andw #0x1c,%4\n\t" /* number of rest longs */ + "jeq 4f\n\t" + "lsrw #2,%4\n\t" + "subqw #1,%4\n" + "3:\t" + /* loop for rest longs */ + "movel %2@+,%5\n\t" + "addxl %5,%0\n\t" + "movel %5,%3@+\n\t" + "dbra %4,3b\n\t" + "clrl %5\n\t" + "addxl %5,%0\n" /* add X bit */ + "4:\t" + /* now check for rest bytes that do not fit into longs */ + "andw #3,%1\n\t" + "jeq 7f\n\t" + "clrl %5\n\t" /* clear tmp2 for rest bytes */ + "subqw #2,%1\n\t" + "jlt 5f\n\t" + "movew %2@+,%5\n\t" /* have rest >= 2: get word */ + "movew %5,%3@+\n\t" + "swap %5\n\t" /* into bits 16..31 */ + "tstw %1\n\t" /* another byte? */ + "jeq 6f\n" + "5:\t" + "moveb %2@,%5\n\t" /* have odd rest: get byte */ + "moveb %5,%3@+\n\t" + "lslw #8,%5\n" /* into bits 8..15; 16..31 untouched */ + "6:\t" + "addl %5,%0\n\t" /* now add rest long to sum */ + "clrl %5\n\t" + "addxl %5,%0\n" /* add X bit */ + "7:\t" + : "=d" (sum), "=d" (len), "=a" (src), "=a" (dst), + "=&d" (tmp1), "=&d" (tmp2) + : "0" (sum), "1" (len), "2" (src), "3" (dst) + ); + return(sum); +} +EXPORT_SYMBOL(csum_partial_copy_nocheck); diff --git a/arch/m68knommu/lib/checksum.c b/arch/m68k/lib/checksum_no.c index eccf25d3d73..eccf25d3d73 100644 --- a/arch/m68knommu/lib/checksum.c +++ b/arch/m68k/lib/checksum_no.c diff --git a/arch/m68knommu/lib/delay.c b/arch/m68k/lib/delay.c index 5bd5472d38a..5bd5472d38a 100644 --- a/arch/m68knommu/lib/delay.c +++ b/arch/m68k/lib/delay.c diff --git a/arch/m68knommu/lib/divsi3.S b/arch/m68k/lib/divsi3.S index ec307b61991..ec307b61991 100644 --- a/arch/m68knommu/lib/divsi3.S +++ b/arch/m68k/lib/divsi3.S diff --git a/arch/m68knommu/lib/memcpy.c b/arch/m68k/lib/memcpy.c index b50dbcad474..b50dbcad474 100644 --- a/arch/m68knommu/lib/memcpy.c +++ b/arch/m68k/lib/memcpy.c diff --git a/arch/m68knommu/lib/memmove.c b/arch/m68k/lib/memmove.c index b3dcfe9dab7..b3dcfe9dab7 100644 --- a/arch/m68knommu/lib/memmove.c +++ b/arch/m68k/lib/memmove.c diff --git a/arch/m68knommu/lib/memset.c b/arch/m68k/lib/memset.c index 1389bf45563..1389bf45563 100644 --- a/arch/m68knommu/lib/memset.c +++ b/arch/m68k/lib/memset.c diff --git a/arch/m68knommu/lib/modsi3.S b/arch/m68k/lib/modsi3.S index ef384943576..ef384943576 100644 --- a/arch/m68knommu/lib/modsi3.S +++ b/arch/m68k/lib/modsi3.S diff --git a/arch/m68k/lib/muldi3.c b/arch/m68k/lib/muldi3.c index be4f275649e..16e0eb338ee 100644 --- a/arch/m68k/lib/muldi3.c +++ b/arch/m68k/lib/muldi3.c @@ -1,63 +1,5 @@ -/* muldi3.c extracted from gcc-2.7.2.3/libgcc2.c and - gcc-2.7.2.3/longlong.h which is: */ -/* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#define BITS_PER_UNIT 8 - -#define umul_ppmm(w1, w0, u, v) \ - __asm__ ("mulu%.l %3,%1:%0" \ - : "=d" ((USItype)(w0)), \ - "=d" ((USItype)(w1)) \ - : "%0" ((USItype)(u)), \ - "dmi" ((USItype)(v))) - -#define __umulsidi3(u, v) \ - ({DIunion __w; \ - umul_ppmm (__w.s.high, __w.s.low, u, v); \ - __w.ll; }) - -typedef int SItype __attribute__ ((mode (SI))); -typedef unsigned int USItype __attribute__ ((mode (SI))); -typedef int DItype __attribute__ ((mode (DI))); -typedef int word_type __attribute__ ((mode (__word__))); - -struct DIstruct {SItype high, low;}; - -typedef union -{ - struct DIstruct s; - DItype ll; -} DIunion; - -DItype -__muldi3 (DItype u, DItype v) -{ - DIunion w; - DIunion uu, vv; - - uu.ll = u, - vv.ll = v; - - w.ll = __umulsidi3 (uu.s.low, vv.s.low); - w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high - + (USItype) uu.s.high * (USItype) vv.s.low); - - return w.ll; -} +#ifdef CONFIG_MMU +#include "muldi3_mm.c" +#else +#include "muldi3_no.c" +#endif diff --git a/arch/m68knommu/lib/ashrdi3.c b/arch/m68k/lib/muldi3_mm.c index 78efb65e315..be4f275649e 100644 --- a/arch/m68knommu/lib/ashrdi3.c +++ b/arch/m68k/lib/muldi3_mm.c @@ -1,4 +1,5 @@ -/* ashrdi3.c extracted from gcc-2.7.2/libgcc2.c which is: */ +/* muldi3.c extracted from gcc-2.7.2.3/libgcc2.c and + gcc-2.7.2.3/longlong.h which is: */ /* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc. This file is part of GNU CC. @@ -20,7 +21,19 @@ Boston, MA 02111-1307, USA. */ #define BITS_PER_UNIT 8 -typedef int SItype __attribute__ ((mode (SI))); +#define umul_ppmm(w1, w0, u, v) \ + __asm__ ("mulu%.l %3,%1:%0" \ + : "=d" ((USItype)(w0)), \ + "=d" ((USItype)(w1)) \ + : "%0" ((USItype)(u)), \ + "dmi" ((USItype)(v))) + +#define __umulsidi3(u, v) \ + ({DIunion __w; \ + umul_ppmm (__w.s.high, __w.s.low, u, v); \ + __w.ll; }) + +typedef int SItype __attribute__ ((mode (SI))); typedef unsigned int USItype __attribute__ ((mode (SI))); typedef int DItype __attribute__ ((mode (DI))); typedef int word_type __attribute__ ((mode (__word__))); @@ -34,30 +47,17 @@ typedef union } DIunion; DItype -__ashrdi3 (DItype u, word_type b) +__muldi3 (DItype u, DItype v) { DIunion w; - word_type bm; - DIunion uu; - - if (b == 0) - return u; - - uu.ll = u; - - bm = (sizeof (SItype) * BITS_PER_UNIT) - b; - if (bm <= 0) - { - /* w.s.high = 1..1 or 0..0 */ - w.s.high = uu.s.high >> (sizeof (SItype) * BITS_PER_UNIT - 1); - w.s.low = uu.s.high >> -bm; - } - else - { - USItype carries = (USItype)uu.s.high << bm; - w.s.high = uu.s.high >> b; - w.s.low = ((USItype)uu.s.low >> b) | carries; - } + DIunion uu, vv; + + uu.ll = u, + vv.ll = v; + + w.ll = __umulsidi3 (uu.s.low, vv.s.low); + w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high + + (USItype) uu.s.high * (USItype) vv.s.low); return w.ll; } diff --git a/arch/m68knommu/lib/muldi3.c b/arch/m68k/lib/muldi3_no.c index 34af72c3030..34af72c3030 100644 --- a/arch/m68knommu/lib/muldi3.c +++ b/arch/m68k/lib/muldi3_no.c diff --git a/arch/m68knommu/lib/mulsi3.S b/arch/m68k/lib/mulsi3.S index ce29ea37b45..ce29ea37b45 100644 --- a/arch/m68knommu/lib/mulsi3.S +++ b/arch/m68k/lib/mulsi3.S diff --git a/arch/m68knommu/lib/udivsi3.S b/arch/m68k/lib/udivsi3.S index c424c4a1f0a..c424c4a1f0a 100644 --- a/arch/m68knommu/lib/udivsi3.S +++ b/arch/m68k/lib/udivsi3.S diff --git a/arch/m68knommu/lib/umodsi3.S b/arch/m68k/lib/umodsi3.S index 5def5f62647..5def5f62647 100644 --- a/arch/m68knommu/lib/umodsi3.S +++ b/arch/m68k/lib/umodsi3.S diff --git a/arch/m68k/mm/Makefile b/arch/m68k/mm/Makefile index 5eaa43c4cb3..b60270e4954 100644 --- a/arch/m68k/mm/Makefile +++ b/arch/m68k/mm/Makefile @@ -1,8 +1,5 @@ -# -# Makefile for the linux m68k-specific parts of the memory manager. -# - -obj-y := cache.o init.o fault.o hwtest.o - -obj-$(CONFIG_MMU_MOTOROLA) += kmap.o memory.o motorola.o -obj-$(CONFIG_MMU_SUN3) += sun3kmap.o sun3mmu.o +ifdef CONFIG_MMU +include arch/m68k/mm/Makefile_mm +else +include arch/m68k/mm/Makefile_no +endif diff --git a/arch/m68k/mm/Makefile_mm b/arch/m68k/mm/Makefile_mm new file mode 100644 index 00000000000..5eaa43c4cb3 --- /dev/null +++ b/arch/m68k/mm/Makefile_mm @@ -0,0 +1,8 @@ +# +# Makefile for the linux m68k-specific parts of the memory manager. +# + +obj-y := cache.o init.o fault.o hwtest.o + +obj-$(CONFIG_MMU_MOTOROLA) += kmap.o memory.o motorola.o +obj-$(CONFIG_MMU_SUN3) += sun3kmap.o sun3mmu.o diff --git a/arch/m68knommu/mm/Makefile b/arch/m68k/mm/Makefile_no index b54ab6b4b52..b54ab6b4b52 100644 --- a/arch/m68knommu/mm/Makefile +++ b/arch/m68k/mm/Makefile_no diff --git a/arch/m68k/mm/init.c b/arch/m68k/mm/init.c index 8bc842554e5..27b5ce089a3 100644 --- a/arch/m68k/mm/init.c +++ b/arch/m68k/mm/init.c @@ -1,150 +1,5 @@ -/* - * linux/arch/m68k/mm/init.c - * - * Copyright (C) 1995 Hamish Macdonald - * - * Contains common initialization routines, specific init code moved - * to motorola.c and sun3mmu.c - */ - -#include <linux/module.h> -#include <linux/signal.h> -#include <linux/sched.h> -#include <linux/mm.h> -#include <linux/swap.h> -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/bootmem.h> -#include <linux/gfp.h> - -#include <asm/setup.h> -#include <asm/uaccess.h> -#include <asm/page.h> -#include <asm/pgalloc.h> -#include <asm/system.h> -#include <asm/machdep.h> -#include <asm/io.h> -#ifdef CONFIG_ATARI -#include <asm/atari_stram.h> -#endif -#include <asm/sections.h> -#include <asm/tlb.h> - -DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); - -pg_data_t pg_data_map[MAX_NUMNODES]; -EXPORT_SYMBOL(pg_data_map); - -int m68k_virt_to_node_shift; - -#ifndef CONFIG_SINGLE_MEMORY_CHUNK -pg_data_t *pg_data_table[65]; -EXPORT_SYMBOL(pg_data_table); -#endif - -void __init m68k_setup_node(int node) -{ -#ifndef CONFIG_SINGLE_MEMORY_CHUNK - struct mem_info *info = m68k_memory + node; - int i, end; - - i = (unsigned long)phys_to_virt(info->addr) >> __virt_to_node_shift(); - end = (unsigned long)phys_to_virt(info->addr + info->size - 1) >> __virt_to_node_shift(); - for (; i <= end; i++) { - if (pg_data_table[i]) - printk("overlap at %u for chunk %u\n", i, node); - pg_data_table[i] = pg_data_map + node; - } -#endif - pg_data_map[node].bdata = bootmem_node_data + node; - node_set_online(node); -} - - -/* - * ZERO_PAGE is a special page that is used for zero-initialized - * data and COW. - */ - -void *empty_zero_page; -EXPORT_SYMBOL(empty_zero_page); - -extern void init_pointer_table(unsigned long ptable); - -/* References to section boundaries */ - -extern pmd_t *zero_pgtable; - -void __init mem_init(void) -{ - pg_data_t *pgdat; - int codepages = 0; - int datapages = 0; - int initpages = 0; - int i; - -#ifdef CONFIG_ATARI - if (MACH_IS_ATARI) - atari_stram_mem_init_hook(); -#endif - - /* this will put all memory onto the freelists */ - totalram_pages = num_physpages = 0; - for_each_online_pgdat(pgdat) { - num_physpages += pgdat->node_present_pages; - - totalram_pages += free_all_bootmem_node(pgdat); - for (i = 0; i < pgdat->node_spanned_pages; i++) { - struct page *page = pgdat->node_mem_map + i; - char *addr = page_to_virt(page); - - if (!PageReserved(page)) - continue; - if (addr >= _text && - addr < _etext) - codepages++; - else if (addr >= __init_begin && - addr < __init_end) - initpages++; - else - datapages++; - } - } - -#ifndef CONFIG_SUN3 - /* insert pointer tables allocated so far into the tablelist */ - init_pointer_table((unsigned long)kernel_pg_dir); - for (i = 0; i < PTRS_PER_PGD; i++) { - if (pgd_present(kernel_pg_dir[i])) - init_pointer_table(__pgd_page(kernel_pg_dir[i])); - } - - /* insert also pointer table that we used to unmap the zero page */ - if (zero_pgtable) - init_pointer_table((unsigned long)zero_pgtable); -#endif - - printk("Memory: %luk/%luk available (%dk kernel code, %dk data, %dk init)\n", - nr_free_pages() << (PAGE_SHIFT-10), - totalram_pages << (PAGE_SHIFT-10), - codepages << (PAGE_SHIFT-10), - datapages << (PAGE_SHIFT-10), - initpages << (PAGE_SHIFT-10)); -} - -#ifdef CONFIG_BLK_DEV_INITRD -void free_initrd_mem(unsigned long start, unsigned long end) -{ - int pages = 0; - for (; start < end; start += PAGE_SIZE) { - ClearPageReserved(virt_to_page(start)); - init_page_count(virt_to_page(start)); - free_page(start); - totalram_pages++; - pages++; - } - printk ("Freeing initrd memory: %dk freed\n", pages); -} +#ifdef CONFIG_MMU +#include "init_mm.c" +#else +#include "init_no.c" #endif diff --git a/arch/m68k/mm/init_mm.c b/arch/m68k/mm/init_mm.c new file mode 100644 index 00000000000..8bc842554e5 --- /dev/null +++ b/arch/m68k/mm/init_mm.c @@ -0,0 +1,150 @@ +/* + * linux/arch/m68k/mm/init.c + * + * Copyright (C) 1995 Hamish Macdonald + * + * Contains common initialization routines, specific init code moved + * to motorola.c and sun3mmu.c + */ + +#include <linux/module.h> +#include <linux/signal.h> +#include <linux/sched.h> +#include <linux/mm.h> +#include <linux/swap.h> +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/bootmem.h> +#include <linux/gfp.h> + +#include <asm/setup.h> +#include <asm/uaccess.h> +#include <asm/page.h> +#include <asm/pgalloc.h> +#include <asm/system.h> +#include <asm/machdep.h> +#include <asm/io.h> +#ifdef CONFIG_ATARI +#include <asm/atari_stram.h> +#endif +#include <asm/sections.h> +#include <asm/tlb.h> + +DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); + +pg_data_t pg_data_map[MAX_NUMNODES]; +EXPORT_SYMBOL(pg_data_map); + +int m68k_virt_to_node_shift; + +#ifndef CONFIG_SINGLE_MEMORY_CHUNK +pg_data_t *pg_data_table[65]; +EXPORT_SYMBOL(pg_data_table); +#endif + +void __init m68k_setup_node(int node) +{ +#ifndef CONFIG_SINGLE_MEMORY_CHUNK + struct mem_info *info = m68k_memory + node; + int i, end; + + i = (unsigned long)phys_to_virt(info->addr) >> __virt_to_node_shift(); + end = (unsigned long)phys_to_virt(info->addr + info->size - 1) >> __virt_to_node_shift(); + for (; i <= end; i++) { + if (pg_data_table[i]) + printk("overlap at %u for chunk %u\n", i, node); + pg_data_table[i] = pg_data_map + node; + } +#endif + pg_data_map[node].bdata = bootmem_node_data + node; + node_set_online(node); +} + + +/* + * ZERO_PAGE is a special page that is used for zero-initialized + * data and COW. + */ + +void *empty_zero_page; +EXPORT_SYMBOL(empty_zero_page); + +extern void init_pointer_table(unsigned long ptable); + +/* References to section boundaries */ + +extern pmd_t *zero_pgtable; + +void __init mem_init(void) +{ + pg_data_t *pgdat; + int codepages = 0; + int datapages = 0; + int initpages = 0; + int i; + +#ifdef CONFIG_ATARI + if (MACH_IS_ATARI) + atari_stram_mem_init_hook(); +#endif + + /* this will put all memory onto the freelists */ + totalram_pages = num_physpages = 0; + for_each_online_pgdat(pgdat) { + num_physpages += pgdat->node_present_pages; + + totalram_pages += free_all_bootmem_node(pgdat); + for (i = 0; i < pgdat->node_spanned_pages; i++) { + struct page *page = pgdat->node_mem_map + i; + char *addr = page_to_virt(page); + + if (!PageReserved(page)) + continue; + if (addr >= _text && + addr < _etext) + codepages++; + else if (addr >= __init_begin && + addr < __init_end) + initpages++; + else + datapages++; + } + } + +#ifndef CONFIG_SUN3 + /* insert pointer tables allocated so far into the tablelist */ + init_pointer_table((unsigned long)kernel_pg_dir); + for (i = 0; i < PTRS_PER_PGD; i++) { + if (pgd_present(kernel_pg_dir[i])) + init_pointer_table(__pgd_page(kernel_pg_dir[i])); + } + + /* insert also pointer table that we used to unmap the zero page */ + if (zero_pgtable) + init_pointer_table((unsigned long)zero_pgtable); +#endif + + printk("Memory: %luk/%luk available (%dk kernel code, %dk data, %dk init)\n", + nr_free_pages() << (PAGE_SHIFT-10), + totalram_pages << (PAGE_SHIFT-10), + codepages << (PAGE_SHIFT-10), + datapages << (PAGE_SHIFT-10), + initpages << (PAGE_SHIFT-10)); +} + +#ifdef CONFIG_BLK_DEV_INITRD +void free_initrd_mem(unsigned long start, unsigned long end) +{ + int pages = 0; + for (; start < end; start += PAGE_SIZE) { + ClearPageReserved(virt_to_page(start)); + init_page_count(virt_to_page(start)); + free_page(start); + totalram_pages++; + pages++; + } + printk ("Freeing initrd memory: %dk freed\n", pages); +} +#endif diff --git a/arch/m68knommu/mm/init.c b/arch/m68k/mm/init_no.c index 8a6653f56bd..8a6653f56bd 100644 --- a/arch/m68knommu/mm/init.c +++ b/arch/m68k/mm/init_no.c diff --git a/arch/m68k/mm/kmap.c b/arch/m68k/mm/kmap.c index 69345849454..a373d136b2b 100644 --- a/arch/m68k/mm/kmap.c +++ b/arch/m68k/mm/kmap.c @@ -1,367 +1,5 @@ -/* - * linux/arch/m68k/mm/kmap.c - * - * Copyright (C) 1997 Roman Hodek - * - * 10/01/99 cleaned up the code and changing to the same interface - * used by other architectures /Roman Zippel - */ - -#include <linux/module.h> -#include <linux/mm.h> -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/types.h> -#include <linux/slab.h> -#include <linux/vmalloc.h> - -#include <asm/setup.h> -#include <asm/segment.h> -#include <asm/page.h> -#include <asm/pgalloc.h> -#include <asm/io.h> -#include <asm/system.h> - -#undef DEBUG - -#define PTRTREESIZE (256*1024) - -/* - * For 040/060 we can use the virtual memory area like other architectures, - * but for 020/030 we want to use early termination page descriptor and we - * can't mix this with normal page descriptors, so we have to copy that code - * (mm/vmalloc.c) and return appriorate aligned addresses. - */ - -#ifdef CPU_M68040_OR_M68060_ONLY - -#define IO_SIZE PAGE_SIZE - -static inline struct vm_struct *get_io_area(unsigned long size) -{ - return get_vm_area(size, VM_IOREMAP); -} - - -static inline void free_io_area(void *addr) -{ - vfree((void *)(PAGE_MASK & (unsigned long)addr)); -} - +#ifdef CONFIG_MMU +#include "kmap_mm.c" #else - -#define IO_SIZE (256*1024) - -static struct vm_struct *iolist; - -static struct vm_struct *get_io_area(unsigned long size) -{ - unsigned long addr; - struct vm_struct **p, *tmp, *area; - - area = kmalloc(sizeof(*area), GFP_KERNEL); - if (!area) - return NULL; - addr = KMAP_START; - for (p = &iolist; (tmp = *p) ; p = &tmp->next) { - if (size + addr < (unsigned long)tmp->addr) - break; - if (addr > KMAP_END-size) { - kfree(area); - return NULL; - } - addr = tmp->size + (unsigned long)tmp->addr; - } - area->addr = (void *)addr; - area->size = size + IO_SIZE; - area->next = *p; - *p = area; - return area; -} - -static inline void free_io_area(void *addr) -{ - struct vm_struct **p, *tmp; - - if (!addr) - return; - addr = (void *)((unsigned long)addr & -IO_SIZE); - for (p = &iolist ; (tmp = *p) ; p = &tmp->next) { - if (tmp->addr == addr) { - *p = tmp->next; - __iounmap(tmp->addr, tmp->size); - kfree(tmp); - return; - } - } -} - +#include "kmap_no.c" #endif - -/* - * Map some physical address range into the kernel address space. - */ -/* Rewritten by Andreas Schwab to remove all races. */ - -void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag) -{ - struct vm_struct *area; - unsigned long virtaddr, retaddr; - long offset; - pgd_t *pgd_dir; - pmd_t *pmd_dir; - pte_t *pte_dir; - - /* - * Don't allow mappings that wrap.. - */ - if (!size || physaddr > (unsigned long)(-size)) - return NULL; - -#ifdef CONFIG_AMIGA - if (MACH_IS_AMIGA) { - if ((physaddr >= 0x40000000) && (physaddr + size < 0x60000000) - && (cacheflag == IOMAP_NOCACHE_SER)) - return (void __iomem *)physaddr; - } -#endif - -#ifdef DEBUG - printk("ioremap: 0x%lx,0x%lx(%d) - ", physaddr, size, cacheflag); -#endif - /* - * Mappings have to be aligned - */ - offset = physaddr & (IO_SIZE - 1); - physaddr &= -IO_SIZE; - size = (size + offset + IO_SIZE - 1) & -IO_SIZE; - - /* - * Ok, go for it.. - */ - area = get_io_area(size); - if (!area) - return NULL; - - virtaddr = (unsigned long)area->addr; - retaddr = virtaddr + offset; -#ifdef DEBUG - printk("0x%lx,0x%lx,0x%lx", physaddr, virtaddr, retaddr); -#endif - - /* - * add cache and table flags to physical address - */ - if (CPU_IS_040_OR_060) { - physaddr |= (_PAGE_PRESENT | _PAGE_GLOBAL040 | - _PAGE_ACCESSED | _PAGE_DIRTY); - switch (cacheflag) { - case IOMAP_FULL_CACHING: - physaddr |= _PAGE_CACHE040; - break; - case IOMAP_NOCACHE_SER: - default: - physaddr |= _PAGE_NOCACHE_S; - break; - case IOMAP_NOCACHE_NONSER: - physaddr |= _PAGE_NOCACHE; - break; - case IOMAP_WRITETHROUGH: - physaddr |= _PAGE_CACHE040W; - break; - } - } else { - physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY); - switch (cacheflag) { - case IOMAP_NOCACHE_SER: - case IOMAP_NOCACHE_NONSER: - default: - physaddr |= _PAGE_NOCACHE030; - break; - case IOMAP_FULL_CACHING: - case IOMAP_WRITETHROUGH: - break; - } - } - - while ((long)size > 0) { -#ifdef DEBUG - if (!(virtaddr & (PTRTREESIZE-1))) - printk ("\npa=%#lx va=%#lx ", physaddr, virtaddr); -#endif - pgd_dir = pgd_offset_k(virtaddr); - pmd_dir = pmd_alloc(&init_mm, pgd_dir, virtaddr); - if (!pmd_dir) { - printk("ioremap: no mem for pmd_dir\n"); - return NULL; - } - - if (CPU_IS_020_OR_030) { - pmd_dir->pmd[(virtaddr/PTRTREESIZE) & 15] = physaddr; - physaddr += PTRTREESIZE; - virtaddr += PTRTREESIZE; - size -= PTRTREESIZE; - } else { - pte_dir = pte_alloc_kernel(pmd_dir, virtaddr); - if (!pte_dir) { - printk("ioremap: no mem for pte_dir\n"); - return NULL; - } - - pte_val(*pte_dir) = physaddr; - virtaddr += PAGE_SIZE; - physaddr += PAGE_SIZE; - size -= PAGE_SIZE; - } - } -#ifdef DEBUG - printk("\n"); -#endif - flush_tlb_all(); - - return (void __iomem *)retaddr; -} -EXPORT_SYMBOL(__ioremap); - -/* - * Unmap a ioremap()ed region again - */ -void iounmap(void __iomem *addr) -{ -#ifdef CONFIG_AMIGA - if ((!MACH_IS_AMIGA) || - (((unsigned long)addr < 0x40000000) || - ((unsigned long)addr > 0x60000000))) - free_io_area((__force void *)addr); -#else - free_io_area((__force void *)addr); -#endif -} -EXPORT_SYMBOL(iounmap); - -/* - * __iounmap unmaps nearly everything, so be careful - * it doesn't free currently pointer/page tables anymore but it - * wans't used anyway and might be added later. - */ -void __iounmap(void *addr, unsigned long size) -{ - unsigned long virtaddr = (unsigned long)addr; - pgd_t *pgd_dir; - pmd_t *pmd_dir; - pte_t *pte_dir; - - while ((long)size > 0) { - pgd_dir = pgd_offset_k(virtaddr); - if (pgd_bad(*pgd_dir)) { - printk("iounmap: bad pgd(%08lx)\n", pgd_val(*pgd_dir)); - pgd_clear(pgd_dir); - return; - } - pmd_dir = pmd_offset(pgd_dir, virtaddr); - - if (CPU_IS_020_OR_030) { - int pmd_off = (virtaddr/PTRTREESIZE) & 15; - int pmd_type = pmd_dir->pmd[pmd_off] & _DESCTYPE_MASK; - - if (pmd_type == _PAGE_PRESENT) { - pmd_dir->pmd[pmd_off] = 0; - virtaddr += PTRTREESIZE; - size -= PTRTREESIZE; - continue; - } else if (pmd_type == 0) - continue; - } - - if (pmd_bad(*pmd_dir)) { - printk("iounmap: bad pmd (%08lx)\n", pmd_val(*pmd_dir)); - pmd_clear(pmd_dir); - return; - } - pte_dir = pte_offset_kernel(pmd_dir, virtaddr); - - pte_val(*pte_dir) = 0; - virtaddr += PAGE_SIZE; - size -= PAGE_SIZE; - } - - flush_tlb_all(); -} - -/* - * Set new cache mode for some kernel address space. - * The caller must push data for that range itself, if such data may already - * be in the cache. - */ -void kernel_set_cachemode(void *addr, unsigned long size, int cmode) -{ - unsigned long virtaddr = (unsigned long)addr; - pgd_t *pgd_dir; - pmd_t *pmd_dir; - pte_t *pte_dir; - - if (CPU_IS_040_OR_060) { - switch (cmode) { - case IOMAP_FULL_CACHING: - cmode = _PAGE_CACHE040; - break; - case IOMAP_NOCACHE_SER: - default: - cmode = _PAGE_NOCACHE_S; - break; - case IOMAP_NOCACHE_NONSER: - cmode = _PAGE_NOCACHE; - break; - case IOMAP_WRITETHROUGH: - cmode = _PAGE_CACHE040W; - break; - } - } else { - switch (cmode) { - case IOMAP_NOCACHE_SER: - case IOMAP_NOCACHE_NONSER: - default: - cmode = _PAGE_NOCACHE030; - break; - case IOMAP_FULL_CACHING: - case IOMAP_WRITETHROUGH: - cmode = 0; - } - } - - while ((long)size > 0) { - pgd_dir = pgd_offset_k(virtaddr); - if (pgd_bad(*pgd_dir)) { - printk("iocachemode: bad pgd(%08lx)\n", pgd_val(*pgd_dir)); - pgd_clear(pgd_dir); - return; - } - pmd_dir = pmd_offset(pgd_dir, virtaddr); - - if (CPU_IS_020_OR_030) { - int pmd_off = (virtaddr/PTRTREESIZE) & 15; - - if ((pmd_dir->pmd[pmd_off] & _DESCTYPE_MASK) == _PAGE_PRESENT) { - pmd_dir->pmd[pmd_off] = (pmd_dir->pmd[pmd_off] & - _CACHEMASK040) | cmode; - virtaddr += PTRTREESIZE; - size -= PTRTREESIZE; - continue; - } - } - - if (pmd_bad(*pmd_dir)) { - printk("iocachemode: bad pmd (%08lx)\n", pmd_val(*pmd_dir)); - pmd_clear(pmd_dir); - return; - } - pte_dir = pte_offset_kernel(pmd_dir, virtaddr); - - pte_val(*pte_dir) = (pte_val(*pte_dir) & _CACHEMASK040) | cmode; - virtaddr += PAGE_SIZE; - size -= PAGE_SIZE; - } - - flush_tlb_all(); -} -EXPORT_SYMBOL(kernel_set_cachemode); diff --git a/arch/m68k/mm/kmap_mm.c b/arch/m68k/mm/kmap_mm.c new file mode 100644 index 00000000000..69345849454 --- /dev/null +++ b/arch/m68k/mm/kmap_mm.c @@ -0,0 +1,367 @@ +/* + * linux/arch/m68k/mm/kmap.c + * + * Copyright (C) 1997 Roman Hodek + * + * 10/01/99 cleaned up the code and changing to the same interface + * used by other architectures /Roman Zippel + */ + +#include <linux/module.h> +#include <linux/mm.h> +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/types.h> +#include <linux/slab.h> +#include <linux/vmalloc.h> + +#include <asm/setup.h> +#include <asm/segment.h> +#include <asm/page.h> +#include <asm/pgalloc.h> +#include <asm/io.h> +#include <asm/system.h> + +#undef DEBUG + +#define PTRTREESIZE (256*1024) + +/* + * For 040/060 we can use the virtual memory area like other architectures, + * but for 020/030 we want to use early termination page descriptor and we + * can't mix this with normal page descriptors, so we have to copy that code + * (mm/vmalloc.c) and return appriorate aligned addresses. + */ + +#ifdef CPU_M68040_OR_M68060_ONLY + +#define IO_SIZE PAGE_SIZE + +static inline struct vm_struct *get_io_area(unsigned long size) +{ + return get_vm_area(size, VM_IOREMAP); +} + + +static inline void free_io_area(void *addr) +{ + vfree((void *)(PAGE_MASK & (unsigned long)addr)); +} + +#else + +#define IO_SIZE (256*1024) + +static struct vm_struct *iolist; + +static struct vm_struct *get_io_area(unsigned long size) +{ + unsigned long addr; + struct vm_struct **p, *tmp, *area; + + area = kmalloc(sizeof(*area), GFP_KERNEL); + if (!area) + return NULL; + addr = KMAP_START; + for (p = &iolist; (tmp = *p) ; p = &tmp->next) { + if (size + addr < (unsigned long)tmp->addr) + break; + if (addr > KMAP_END-size) { + kfree(area); + return NULL; + } + addr = tmp->size + (unsigned long)tmp->addr; + } + area->addr = (void *)addr; + area->size = size + IO_SIZE; + area->next = *p; + *p = area; + return area; +} + +static inline void free_io_area(void *addr) +{ + struct vm_struct **p, *tmp; + + if (!addr) + return; + addr = (void *)((unsigned long)addr & -IO_SIZE); + for (p = &iolist ; (tmp = *p) ; p = &tmp->next) { + if (tmp->addr == addr) { + *p = tmp->next; + __iounmap(tmp->addr, tmp->size); + kfree(tmp); + return; + } + } +} + +#endif + +/* + * Map some physical address range into the kernel address space. + */ +/* Rewritten by Andreas Schwab to remove all races. */ + +void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag) +{ + struct vm_struct *area; + unsigned long virtaddr, retaddr; + long offset; + pgd_t *pgd_dir; + pmd_t *pmd_dir; + pte_t *pte_dir; + + /* + * Don't allow mappings that wrap.. + */ + if (!size || physaddr > (unsigned long)(-size)) + return NULL; + +#ifdef CONFIG_AMIGA + if (MACH_IS_AMIGA) { + if ((physaddr >= 0x40000000) && (physaddr + size < 0x60000000) + && (cacheflag == IOMAP_NOCACHE_SER)) + return (void __iomem *)physaddr; + } +#endif + +#ifdef DEBUG + printk("ioremap: 0x%lx,0x%lx(%d) - ", physaddr, size, cacheflag); +#endif + /* + * Mappings have to be aligned + */ + offset = physaddr & (IO_SIZE - 1); + physaddr &= -IO_SIZE; + size = (size + offset + IO_SIZE - 1) & -IO_SIZE; + + /* + * Ok, go for it.. + */ + area = get_io_area(size); + if (!area) + return NULL; + + virtaddr = (unsigned long)area->addr; + retaddr = virtaddr + offset; +#ifdef DEBUG + printk("0x%lx,0x%lx,0x%lx", physaddr, virtaddr, retaddr); +#endif + + /* + * add cache and table flags to physical address + */ + if (CPU_IS_040_OR_060) { + physaddr |= (_PAGE_PRESENT | _PAGE_GLOBAL040 | + _PAGE_ACCESSED | _PAGE_DIRTY); + switch (cacheflag) { + case IOMAP_FULL_CACHING: + physaddr |= _PAGE_CACHE040; + break; + case IOMAP_NOCACHE_SER: + default: + physaddr |= _PAGE_NOCACHE_S; + break; + case IOMAP_NOCACHE_NONSER: + physaddr |= _PAGE_NOCACHE; + break; + case IOMAP_WRITETHROUGH: + physaddr |= _PAGE_CACHE040W; + break; + } + } else { + physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY); + switch (cacheflag) { + case IOMAP_NOCACHE_SER: + case IOMAP_NOCACHE_NONSER: + default: + physaddr |= _PAGE_NOCACHE030; + break; + case IOMAP_FULL_CACHING: + case IOMAP_WRITETHROUGH: + break; + } + } + + while ((long)size > 0) { +#ifdef DEBUG + if (!(virtaddr & (PTRTREESIZE-1))) + printk ("\npa=%#lx va=%#lx ", physaddr, virtaddr); +#endif + pgd_dir = pgd_offset_k(virtaddr); + pmd_dir = pmd_alloc(&init_mm, pgd_dir, virtaddr); + if (!pmd_dir) { + printk("ioremap: no mem for pmd_dir\n"); + return NULL; + } + + if (CPU_IS_020_OR_030) { + pmd_dir->pmd[(virtaddr/PTRTREESIZE) & 15] = physaddr; + physaddr += PTRTREESIZE; + virtaddr += PTRTREESIZE; + size -= PTRTREESIZE; + } else { + pte_dir = pte_alloc_kernel(pmd_dir, virtaddr); + if (!pte_dir) { + printk("ioremap: no mem for pte_dir\n"); + return NULL; + } + + pte_val(*pte_dir) = physaddr; + virtaddr += PAGE_SIZE; + physaddr += PAGE_SIZE; + size -= PAGE_SIZE; + } + } +#ifdef DEBUG + printk("\n"); +#endif + flush_tlb_all(); + + return (void __iomem *)retaddr; +} +EXPORT_SYMBOL(__ioremap); + +/* + * Unmap a ioremap()ed region again + */ +void iounmap(void __iomem *addr) +{ +#ifdef CONFIG_AMIGA + if ((!MACH_IS_AMIGA) || + (((unsigned long)addr < 0x40000000) || + ((unsigned long)addr > 0x60000000))) + free_io_area((__force void *)addr); +#else + free_io_area((__force void *)addr); +#endif +} +EXPORT_SYMBOL(iounmap); + +/* + * __iounmap unmaps nearly everything, so be careful + * it doesn't free currently pointer/page tables anymore but it + * wans't used anyway and might be added later. + */ +void __iounmap(void *addr, unsigned long size) +{ + unsigned long virtaddr = (unsigned long)addr; + pgd_t *pgd_dir; + pmd_t *pmd_dir; + pte_t *pte_dir; + + while ((long)size > 0) { + pgd_dir = pgd_offset_k(virtaddr); + if (pgd_bad(*pgd_dir)) { + printk("iounmap: bad pgd(%08lx)\n", pgd_val(*pgd_dir)); + pgd_clear(pgd_dir); + return; + } + pmd_dir = pmd_offset(pgd_dir, virtaddr); + + if (CPU_IS_020_OR_030) { + int pmd_off = (virtaddr/PTRTREESIZE) & 15; + int pmd_type = pmd_dir->pmd[pmd_off] & _DESCTYPE_MASK; + + if (pmd_type == _PAGE_PRESENT) { + pmd_dir->pmd[pmd_off] = 0; + virtaddr += PTRTREESIZE; + size -= PTRTREESIZE; + continue; + } else if (pmd_type == 0) + continue; + } + + if (pmd_bad(*pmd_dir)) { + printk("iounmap: bad pmd (%08lx)\n", pmd_val(*pmd_dir)); + pmd_clear(pmd_dir); + return; + } + pte_dir = pte_offset_kernel(pmd_dir, virtaddr); + + pte_val(*pte_dir) = 0; + virtaddr += PAGE_SIZE; + size -= PAGE_SIZE; + } + + flush_tlb_all(); +} + +/* + * Set new cache mode for some kernel address space. + * The caller must push data for that range itself, if such data may already + * be in the cache. + */ +void kernel_set_cachemode(void *addr, unsigned long size, int cmode) +{ + unsigned long virtaddr = (unsigned long)addr; + pgd_t *pgd_dir; + pmd_t *pmd_dir; + pte_t *pte_dir; + + if (CPU_IS_040_OR_060) { + switch (cmode) { + case IOMAP_FULL_CACHING: + cmode = _PAGE_CACHE040; + break; + case IOMAP_NOCACHE_SER: + default: + cmode = _PAGE_NOCACHE_S; + break; + case IOMAP_NOCACHE_NONSER: + cmode = _PAGE_NOCACHE; + break; + case IOMAP_WRITETHROUGH: + cmode = _PAGE_CACHE040W; + break; + } + } else { + switch (cmode) { + case IOMAP_NOCACHE_SER: + case IOMAP_NOCACHE_NONSER: + default: + cmode = _PAGE_NOCACHE030; + break; + case IOMAP_FULL_CACHING: + case IOMAP_WRITETHROUGH: + cmode = 0; + } + } + + while ((long)size > 0) { + pgd_dir = pgd_offset_k(virtaddr); + if (pgd_bad(*pgd_dir)) { + printk("iocachemode: bad pgd(%08lx)\n", pgd_val(*pgd_dir)); + pgd_clear(pgd_dir); + return; + } + pmd_dir = pmd_offset(pgd_dir, virtaddr); + + if (CPU_IS_020_OR_030) { + int pmd_off = (virtaddr/PTRTREESIZE) & 15; + + if ((pmd_dir->pmd[pmd_off] & _DESCTYPE_MASK) == _PAGE_PRESENT) { + pmd_dir->pmd[pmd_off] = (pmd_dir->pmd[pmd_off] & + _CACHEMASK040) | cmode; + virtaddr += PTRTREESIZE; + size -= PTRTREESIZE; + continue; + } + } + + if (pmd_bad(*pmd_dir)) { + printk("iocachemode: bad pmd (%08lx)\n", pmd_val(*pmd_dir)); + pmd_clear(pmd_dir); + return; + } + pte_dir = pte_offset_kernel(pmd_dir, virtaddr); + + pte_val(*pte_dir) = (pte_val(*pte_dir) & _CACHEMASK040) | cmode; + virtaddr += PAGE_SIZE; + size -= PAGE_SIZE; + } + + flush_tlb_all(); +} +EXPORT_SYMBOL(kernel_set_cachemode); diff --git a/arch/m68knommu/mm/kmap.c b/arch/m68k/mm/kmap_no.c index ece8d5ad4e6..ece8d5ad4e6 100644 --- a/arch/m68knommu/mm/kmap.c +++ b/arch/m68k/mm/kmap_no.c diff --git a/arch/m68k/mm/motorola.c b/arch/m68k/mm/motorola.c index 02b7a03e422..8b3db1c587f 100644 --- a/arch/m68k/mm/motorola.c +++ b/arch/m68k/mm/motorola.c @@ -300,6 +300,8 @@ void __init paging_init(void) zones_size[ZONE_DMA] = m68k_memory[i].size >> PAGE_SHIFT; free_area_init_node(i, zones_size, m68k_memory[i].addr >> PAGE_SHIFT, NULL); + if (node_present_pages(i)) + node_set_state(i, N_NORMAL_MEMORY); } } diff --git a/arch/m68knommu/platform/5206/Makefile b/arch/m68k/platform/5206/Makefile index b5db05625cf..b5db05625cf 100644 --- a/arch/m68knommu/platform/5206/Makefile +++ b/arch/m68k/platform/5206/Makefile diff --git a/arch/m68knommu/platform/5206/config.c b/arch/m68k/platform/5206/config.c index 9c335465e66..9c335465e66 100644 --- a/arch/m68knommu/platform/5206/config.c +++ b/arch/m68k/platform/5206/config.c diff --git a/arch/m68knommu/platform/5206/gpio.c b/arch/m68k/platform/5206/gpio.c index b9ab4a120f2..b9ab4a120f2 100644 --- a/arch/m68knommu/platform/5206/gpio.c +++ b/arch/m68k/platform/5206/gpio.c diff --git a/arch/m68knommu/platform/5206e/Makefile b/arch/m68k/platform/5206e/Makefile index b5db05625cf..b5db05625cf 100644 --- a/arch/m68knommu/platform/5206e/Makefile +++ b/arch/m68k/platform/5206e/Makefile diff --git a/arch/m68knommu/platform/5206e/config.c b/arch/m68k/platform/5206e/config.c index 942397984c6..942397984c6 100644 --- a/arch/m68knommu/platform/5206e/config.c +++ b/arch/m68k/platform/5206e/config.c diff --git a/arch/m68knommu/platform/5206e/gpio.c b/arch/m68k/platform/5206e/gpio.c index b9ab4a120f2..b9ab4a120f2 100644 --- a/arch/m68knommu/platform/5206e/gpio.c +++ b/arch/m68k/platform/5206e/gpio.c diff --git a/arch/m68knommu/platform/520x/Makefile b/arch/m68k/platform/520x/Makefile index ad3f4e5a57c..ad3f4e5a57c 100644 --- a/arch/m68knommu/platform/520x/Makefile +++ b/arch/m68k/platform/520x/Makefile diff --git a/arch/m68knommu/platform/520x/config.c b/arch/m68k/platform/520x/config.c index 621238f1a21..621238f1a21 100644 --- a/arch/m68knommu/platform/520x/config.c +++ b/arch/m68k/platform/520x/config.c diff --git a/arch/m68knommu/platform/520x/gpio.c b/arch/m68k/platform/520x/gpio.c index d757328563d..d757328563d 100644 --- a/arch/m68knommu/platform/520x/gpio.c +++ b/arch/m68k/platform/520x/gpio.c diff --git a/arch/m68knommu/platform/523x/Makefile b/arch/m68k/platform/523x/Makefile index c04b8f71c88..c04b8f71c88 100644 --- a/arch/m68knommu/platform/523x/Makefile +++ b/arch/m68k/platform/523x/Makefile diff --git a/arch/m68knommu/platform/523x/config.c b/arch/m68k/platform/523x/config.c index 418a76feb1e..71f4436ec80 100644 --- a/arch/m68knommu/platform/523x/config.c +++ b/arch/m68k/platform/523x/config.c @@ -3,7 +3,7 @@ /* * linux/arch/m68knommu/platform/523x/config.c * - * Sub-architcture dependant initialization code for the Freescale + * Sub-architcture dependent initialization code for the Freescale * 523x CPUs. * * Copyright (C) 1999-2005, Greg Ungerer (gerg@snapgear.com) diff --git a/arch/m68knommu/platform/523x/gpio.c b/arch/m68k/platform/523x/gpio.c index 327ebf142c8..327ebf142c8 100644 --- a/arch/m68knommu/platform/523x/gpio.c +++ b/arch/m68k/platform/523x/gpio.c diff --git a/arch/m68knommu/platform/5249/Makefile b/arch/m68k/platform/5249/Makefile index 4bed30fd007..4bed30fd007 100644 --- a/arch/m68knommu/platform/5249/Makefile +++ b/arch/m68k/platform/5249/Makefile diff --git a/arch/m68knommu/platform/5249/config.c b/arch/m68k/platform/5249/config.c index ceb31e5744a..ceb31e5744a 100644 --- a/arch/m68knommu/platform/5249/config.c +++ b/arch/m68k/platform/5249/config.c diff --git a/arch/m68knommu/platform/5249/gpio.c b/arch/m68k/platform/5249/gpio.c index 2b56c6ef65b..2b56c6ef65b 100644 --- a/arch/m68knommu/platform/5249/gpio.c +++ b/arch/m68k/platform/5249/gpio.c diff --git a/arch/m68knommu/platform/5249/intc2.c b/arch/m68k/platform/5249/intc2.c index 8f4b63e1736..f343bf7bf5b 100644 --- a/arch/m68knommu/platform/5249/intc2.c +++ b/arch/m68k/platform/5249/intc2.c @@ -51,8 +51,8 @@ static int __init mcf_intc2_init(void) /* GPIO interrupt sources */ for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) { - set_irq_chip(irq, &intc2_irq_gpio_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip(irq, &intc2_irq_gpio_chip); + irq_set_handler(irq, handle_edge_irq); } return 0; diff --git a/arch/m68knommu/platform/5272/Makefile b/arch/m68k/platform/5272/Makefile index 34110fc1430..34110fc1430 100644 --- a/arch/m68knommu/platform/5272/Makefile +++ b/arch/m68k/platform/5272/Makefile diff --git a/arch/m68knommu/platform/5272/config.c b/arch/m68k/platform/5272/config.c index 65bb582734e..65bb582734e 100644 --- a/arch/m68knommu/platform/5272/config.c +++ b/arch/m68k/platform/5272/config.c diff --git a/arch/m68knommu/platform/5272/gpio.c b/arch/m68k/platform/5272/gpio.c index 57ac10a5d7f..57ac10a5d7f 100644 --- a/arch/m68knommu/platform/5272/gpio.c +++ b/arch/m68k/platform/5272/gpio.c diff --git a/arch/m68knommu/platform/5272/intc.c b/arch/m68k/platform/5272/intc.c index 969ff0a467c..7e715dfe281 100644 --- a/arch/m68knommu/platform/5272/intc.c +++ b/arch/m68k/platform/5272/intc.c @@ -33,7 +33,7 @@ * * Note that the external interrupts are edge triggered (unlike the * internal interrupt sources which are level triggered). Which means - * they also need acknowledgeing via acknowledge bits. + * they also need acknowledging via acknowledge bits. */ struct irqmap { unsigned char icr; @@ -145,7 +145,7 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type) */ static void intc_external_irq(unsigned int irq, struct irq_desc *desc) { - get_irq_desc_chip(desc)->irq_ack(&desc->irq_data); + irq_desc_get_chip(desc)->irq_ack(&desc->irq_data); handle_simple_irq(irq, desc); } @@ -171,16 +171,16 @@ void __init init_IRQ(void) writel(0x88888888, MCF_MBAR + MCFSIM_ICR4); for (irq = 0; (irq < NR_IRQS); irq++) { - set_irq_chip(irq, &intc_irq_chip); + irq_set_chip(irq, &intc_irq_chip); edge = 0; if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) edge = intc_irqmap[irq - MCFINT_VECBASE].ack; if (edge) { - set_irq_type(irq, IRQ_TYPE_EDGE_RISING); - set_irq_handler(irq, intc_external_irq); + irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); + irq_set_handler(irq, intc_external_irq); } else { - set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); - set_irq_handler(irq, handle_level_irq); + irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); + irq_set_handler(irq, handle_level_irq); } } } diff --git a/arch/m68knommu/platform/527x/Makefile b/arch/m68k/platform/527x/Makefile index 6ac4b57370e..6ac4b57370e 100644 --- a/arch/m68knommu/platform/527x/Makefile +++ b/arch/m68k/platform/527x/Makefile diff --git a/arch/m68knommu/platform/527x/config.c b/arch/m68k/platform/527x/config.c index fa359593b61..3ebc769cefd 100644 --- a/arch/m68knommu/platform/527x/config.c +++ b/arch/m68k/platform/527x/config.c @@ -3,7 +3,7 @@ /* * linux/arch/m68knommu/platform/527x/config.c * - * Sub-architcture dependant initialization code for the Freescale + * Sub-architcture dependent initialization code for the Freescale * 5270/5271 CPUs. * * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com) diff --git a/arch/m68knommu/platform/527x/gpio.c b/arch/m68k/platform/527x/gpio.c index 205da0aa0f2..205da0aa0f2 100644 --- a/arch/m68knommu/platform/527x/gpio.c +++ b/arch/m68k/platform/527x/gpio.c diff --git a/arch/m68knommu/platform/528x/Makefile b/arch/m68k/platform/528x/Makefile index 6ac4b57370e..6ac4b57370e 100644 --- a/arch/m68knommu/platform/528x/Makefile +++ b/arch/m68k/platform/528x/Makefile diff --git a/arch/m68knommu/platform/528x/config.c b/arch/m68k/platform/528x/config.c index ac39fc66121..7abe77a2f3e 100644 --- a/arch/m68knommu/platform/528x/config.c +++ b/arch/m68k/platform/528x/config.c @@ -3,7 +3,7 @@ /* * linux/arch/m68knommu/platform/528x/config.c * - * Sub-architcture dependant initialization code for the Freescale + * Sub-architcture dependent initialization code for the Freescale * 5280, 5281 and 5282 CPUs. * * Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com) diff --git a/arch/m68knommu/platform/528x/gpio.c b/arch/m68k/platform/528x/gpio.c index 526db665d87..526db665d87 100644 --- a/arch/m68knommu/platform/528x/gpio.c +++ b/arch/m68k/platform/528x/gpio.c diff --git a/arch/m68knommu/platform/5307/Makefile b/arch/m68k/platform/5307/Makefile index d4293b791f2..d4293b791f2 100644 --- a/arch/m68knommu/platform/5307/Makefile +++ b/arch/m68k/platform/5307/Makefile diff --git a/arch/m68knommu/platform/5307/config.c b/arch/m68k/platform/5307/config.c index 00900ac06a9..00900ac06a9 100644 --- a/arch/m68knommu/platform/5307/config.c +++ b/arch/m68k/platform/5307/config.c diff --git a/arch/m68knommu/platform/5307/gpio.c b/arch/m68k/platform/5307/gpio.c index 5850612b4a3..5850612b4a3 100644 --- a/arch/m68knommu/platform/5307/gpio.c +++ b/arch/m68k/platform/5307/gpio.c diff --git a/arch/m68knommu/platform/5307/nettel.c b/arch/m68k/platform/5307/nettel.c index e925ea4602f..e925ea4602f 100644 --- a/arch/m68knommu/platform/5307/nettel.c +++ b/arch/m68k/platform/5307/nettel.c diff --git a/arch/m68knommu/platform/532x/Makefile b/arch/m68k/platform/532x/Makefile index ce01669399c..ce01669399c 100644 --- a/arch/m68knommu/platform/532x/Makefile +++ b/arch/m68k/platform/532x/Makefile diff --git a/arch/m68knommu/platform/532x/config.c b/arch/m68k/platform/532x/config.c index ca51323f957..ca51323f957 100644 --- a/arch/m68knommu/platform/532x/config.c +++ b/arch/m68k/platform/532x/config.c diff --git a/arch/m68knommu/platform/532x/gpio.c b/arch/m68k/platform/532x/gpio.c index 212a85deac9..212a85deac9 100644 --- a/arch/m68knommu/platform/532x/gpio.c +++ b/arch/m68k/platform/532x/gpio.c diff --git a/arch/m68knommu/platform/5407/Makefile b/arch/m68k/platform/5407/Makefile index e83fe148edd..e83fe148edd 100644 --- a/arch/m68knommu/platform/5407/Makefile +++ b/arch/m68k/platform/5407/Makefile diff --git a/arch/m68knommu/platform/5407/config.c b/arch/m68k/platform/5407/config.c index 70ea789a400..70ea789a400 100644 --- a/arch/m68knommu/platform/5407/config.c +++ b/arch/m68k/platform/5407/config.c diff --git a/arch/m68knommu/platform/5407/gpio.c b/arch/m68k/platform/5407/gpio.c index 5850612b4a3..5850612b4a3 100644 --- a/arch/m68knommu/platform/5407/gpio.c +++ b/arch/m68k/platform/5407/gpio.c diff --git a/arch/m68knommu/platform/54xx/Makefile b/arch/m68k/platform/54xx/Makefile index 6cfd090ec3c..6cfd090ec3c 100644 --- a/arch/m68knommu/platform/54xx/Makefile +++ b/arch/m68k/platform/54xx/Makefile diff --git a/arch/m68knommu/platform/54xx/config.c b/arch/m68k/platform/54xx/config.c index 78130984db9..78130984db9 100644 --- a/arch/m68knommu/platform/54xx/config.c +++ b/arch/m68k/platform/54xx/config.c diff --git a/arch/m68knommu/platform/54xx/firebee.c b/arch/m68k/platform/54xx/firebee.c index 46d50534f98..46d50534f98 100644 --- a/arch/m68knommu/platform/54xx/firebee.c +++ b/arch/m68k/platform/54xx/firebee.c diff --git a/arch/m68knommu/platform/68328/Makefile b/arch/m68k/platform/68328/Makefile index 5e5435552d5..5e5435552d5 100644 --- a/arch/m68knommu/platform/68328/Makefile +++ b/arch/m68k/platform/68328/Makefile diff --git a/arch/m68knommu/platform/68328/bootlogo.h b/arch/m68k/platform/68328/bootlogo.h index 67bc2c17386..67bc2c17386 100644 --- a/arch/m68knommu/platform/68328/bootlogo.h +++ b/arch/m68k/platform/68328/bootlogo.h diff --git a/arch/m68knommu/platform/68328/bootlogo.pl b/arch/m68k/platform/68328/bootlogo.pl index b04ae3f50da..b04ae3f50da 100644 --- a/arch/m68knommu/platform/68328/bootlogo.pl +++ b/arch/m68k/platform/68328/bootlogo.pl diff --git a/arch/m68knommu/platform/68328/config.c b/arch/m68k/platform/68328/config.c index a7bd21deb00..a7bd21deb00 100644 --- a/arch/m68knommu/platform/68328/config.c +++ b/arch/m68k/platform/68328/config.c diff --git a/arch/m68knommu/platform/68328/entry.S b/arch/m68k/platform/68328/entry.S index 676960cf022..676960cf022 100644 --- a/arch/m68knommu/platform/68328/entry.S +++ b/arch/m68k/platform/68328/entry.S diff --git a/arch/m68knommu/platform/68328/head-de2.S b/arch/m68k/platform/68328/head-de2.S index f632fdcb93e..f632fdcb93e 100644 --- a/arch/m68knommu/platform/68328/head-de2.S +++ b/arch/m68k/platform/68328/head-de2.S diff --git a/arch/m68knommu/platform/68328/head-pilot.S b/arch/m68k/platform/68328/head-pilot.S index aecff532b34..aecff532b34 100644 --- a/arch/m68knommu/platform/68328/head-pilot.S +++ b/arch/m68k/platform/68328/head-pilot.S diff --git a/arch/m68knommu/platform/68328/head-ram.S b/arch/m68k/platform/68328/head-ram.S index 7f1aeeacb21..7f1aeeacb21 100644 --- a/arch/m68knommu/platform/68328/head-ram.S +++ b/arch/m68k/platform/68328/head-ram.S diff --git a/arch/m68knommu/platform/68328/head-rom.S b/arch/m68k/platform/68328/head-rom.S index 6ec77d3ea0b..6ec77d3ea0b 100644 --- a/arch/m68knommu/platform/68328/head-rom.S +++ b/arch/m68k/platform/68328/head-rom.S diff --git a/arch/m68knommu/platform/68328/ints.c b/arch/m68k/platform/68328/ints.c index e5631831a20..a90288cf744 100644 --- a/arch/m68knommu/platform/68328/ints.c +++ b/arch/m68k/platform/68328/ints.c @@ -179,8 +179,8 @@ void __init init_IRQ(void) IMR = ~0; for (i = 0; (i < NR_IRQS); i++) { - set_irq_chip(i, &intc_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip(i, &intc_irq_chip); + irq_set_handler(i, handle_level_irq); } } diff --git a/arch/m68knommu/platform/68328/romvec.S b/arch/m68k/platform/68328/romvec.S index 31084466eae..31084466eae 100644 --- a/arch/m68knommu/platform/68328/romvec.S +++ b/arch/m68k/platform/68328/romvec.S diff --git a/arch/m68knommu/platform/68328/timers.c b/arch/m68k/platform/68328/timers.c index 309f725995b..309f725995b 100644 --- a/arch/m68knommu/platform/68328/timers.c +++ b/arch/m68k/platform/68328/timers.c diff --git a/arch/m68knommu/platform/68360/Makefile b/arch/m68k/platform/68360/Makefile index cf5af73a578..cf5af73a578 100644 --- a/arch/m68knommu/platform/68360/Makefile +++ b/arch/m68k/platform/68360/Makefile diff --git a/arch/m68knommu/platform/68360/commproc.c b/arch/m68k/platform/68360/commproc.c index 8e4e10cc008..8e4e10cc008 100644 --- a/arch/m68knommu/platform/68360/commproc.c +++ b/arch/m68k/platform/68360/commproc.c diff --git a/arch/m68knommu/platform/68360/config.c b/arch/m68k/platform/68360/config.c index 9dd5bca3874..9dd5bca3874 100644 --- a/arch/m68knommu/platform/68360/config.c +++ b/arch/m68k/platform/68360/config.c diff --git a/arch/m68knommu/platform/68360/entry.S b/arch/m68k/platform/68360/entry.S index 46c1b18c9dc..46c1b18c9dc 100644 --- a/arch/m68knommu/platform/68360/entry.S +++ b/arch/m68k/platform/68360/entry.S diff --git a/arch/m68knommu/platform/68360/head-ram.S b/arch/m68k/platform/68360/head-ram.S index 8eb94fb6b97..8eb94fb6b97 100644 --- a/arch/m68knommu/platform/68360/head-ram.S +++ b/arch/m68k/platform/68360/head-ram.S diff --git a/arch/m68knommu/platform/68360/head-rom.S b/arch/m68k/platform/68360/head-rom.S index 97510e55b80..97510e55b80 100644 --- a/arch/m68knommu/platform/68360/head-rom.S +++ b/arch/m68k/platform/68360/head-rom.S diff --git a/arch/m68knommu/platform/68360/ints.c b/arch/m68k/platform/68360/ints.c index 8de3feb568c..4af0f4e30f7 100644 --- a/arch/m68knommu/platform/68360/ints.c +++ b/arch/m68k/platform/68360/ints.c @@ -132,8 +132,8 @@ void init_IRQ(void) pquicc->intr_cimr = 0x00000000; for (i = 0; (i < NR_IRQS); i++) { - set_irq_chip(i, &intc_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip(i, &intc_irq_chip); + irq_set_handler(i, handle_level_irq); } } diff --git a/arch/m68knommu/platform/68EZ328/Makefile b/arch/m68k/platform/68EZ328/Makefile index ee97735a242..ee97735a242 100644 --- a/arch/m68knommu/platform/68EZ328/Makefile +++ b/arch/m68k/platform/68EZ328/Makefile diff --git a/arch/m68knommu/platform/68EZ328/bootlogo.h b/arch/m68k/platform/68EZ328/bootlogo.h index e842bdae583..e842bdae583 100644 --- a/arch/m68knommu/platform/68EZ328/bootlogo.h +++ b/arch/m68k/platform/68EZ328/bootlogo.h diff --git a/arch/m68knommu/platform/68EZ328/config.c b/arch/m68k/platform/68EZ328/config.c index 1be1a16f689..1be1a16f689 100644 --- a/arch/m68knommu/platform/68EZ328/config.c +++ b/arch/m68k/platform/68EZ328/config.c diff --git a/arch/m68knommu/platform/68VZ328/Makefile b/arch/m68k/platform/68VZ328/Makefile index 447ffa0fd7c..447ffa0fd7c 100644 --- a/arch/m68knommu/platform/68VZ328/Makefile +++ b/arch/m68k/platform/68VZ328/Makefile diff --git a/arch/m68knommu/platform/68VZ328/config.c b/arch/m68k/platform/68VZ328/config.c index eabaabe8af3..eabaabe8af3 100644 --- a/arch/m68knommu/platform/68VZ328/config.c +++ b/arch/m68k/platform/68VZ328/config.c diff --git a/arch/m68knommu/platform/Makefile b/arch/m68k/platform/Makefile index fc932bf65d3..fc932bf65d3 100644 --- a/arch/m68knommu/platform/Makefile +++ b/arch/m68k/platform/Makefile diff --git a/arch/m68knommu/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile index a8967baabd7..a8967baabd7 100644 --- a/arch/m68knommu/platform/coldfire/Makefile +++ b/arch/m68k/platform/coldfire/Makefile diff --git a/arch/m68knommu/platform/coldfire/cache.c b/arch/m68k/platform/coldfire/cache.c index 235d3c4f4f0..71beeaf0c5c 100644 --- a/arch/m68knommu/platform/coldfire/cache.c +++ b/arch/m68k/platform/coldfire/cache.c @@ -1,7 +1,7 @@ /***************************************************************************/ /* - * cache.c -- general ColdFire Cache maintainence code + * cache.c -- general ColdFire Cache maintenance code * * Copyright (C) 2010, Greg Ungerer (gerg@snapgear.com) */ diff --git a/arch/m68knommu/platform/coldfire/clk.c b/arch/m68k/platform/coldfire/clk.c index 9f1260c5e2a..9f1260c5e2a 100644 --- a/arch/m68knommu/platform/coldfire/clk.c +++ b/arch/m68k/platform/coldfire/clk.c diff --git a/arch/m68knommu/platform/coldfire/dma.c b/arch/m68k/platform/coldfire/dma.c index e88b95e2cc6..e88b95e2cc6 100644 --- a/arch/m68knommu/platform/coldfire/dma.c +++ b/arch/m68k/platform/coldfire/dma.c diff --git a/arch/m68knommu/platform/coldfire/dma_timer.c b/arch/m68k/platform/coldfire/dma_timer.c index a5f562823d7..a5f562823d7 100644 --- a/arch/m68knommu/platform/coldfire/dma_timer.c +++ b/arch/m68k/platform/coldfire/dma_timer.c diff --git a/arch/m68knommu/platform/coldfire/entry.S b/arch/m68k/platform/coldfire/entry.S index 5837cf080b6..eab63f09965 100644 --- a/arch/m68knommu/platform/coldfire/entry.S +++ b/arch/m68k/platform/coldfire/entry.S @@ -163,7 +163,7 @@ Lsignal_return: /* * This is the generic interrupt handler (for all hardware interrupt - * sources). Calls upto high level code to do all the work. + * sources). Calls up to high level code to do all the work. */ ENTRY(inthandler) SAVE_ALL diff --git a/arch/m68knommu/platform/coldfire/gpio.c b/arch/m68k/platform/coldfire/gpio.c index ff004579345..ff004579345 100644 --- a/arch/m68knommu/platform/coldfire/gpio.c +++ b/arch/m68k/platform/coldfire/gpio.c diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68k/platform/coldfire/head.S index 129bff4956b..6ae91a49918 100644 --- a/arch/m68knommu/platform/coldfire/head.S +++ b/arch/m68k/platform/coldfire/head.S @@ -20,7 +20,7 @@ /* * If we don't have a fixed memory size, then lets build in code - * to auto detect the DRAM size. Obviously this is the prefered + * to auto detect the DRAM size. Obviously this is the preferred * method, and should work for most boards. It won't work for those * that do not have their RAM starting at address 0, and it only * works on SDRAM (not boards fitted with SRAM). diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68k/platform/coldfire/intc-2.c index 2cbfbf035db..74b55cfbc3c 100644 --- a/arch/m68knommu/platform/coldfire/intc-2.c +++ b/arch/m68k/platform/coldfire/intc-2.c @@ -164,7 +164,7 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type) } if (tb) - set_irq_handler(irq, handle_edge_irq); + irq_set_handler(irq, handle_edge_irq); irq -= EINT0; pa = __raw_readw(MCFEPORT_EPPAR); @@ -204,11 +204,11 @@ void __init init_IRQ(void) for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) { if ((irq >= EINT1) && (irq <=EINT7)) - set_irq_chip(irq, &intc_irq_chip_edge_port); + irq_set_chip(irq, &intc_irq_chip_edge_port); else - set_irq_chip(irq, &intc_irq_chip); - set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); - set_irq_handler(irq, handle_level_irq); + irq_set_chip(irq, &intc_irq_chip); + irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); + irq_set_handler(irq, handle_level_irq); } } diff --git a/arch/m68knommu/platform/coldfire/intc-simr.c b/arch/m68k/platform/coldfire/intc-simr.c index e642b24ab72..d6a4d9d53e4 100644 --- a/arch/m68knommu/platform/coldfire/intc-simr.c +++ b/arch/m68k/platform/coldfire/intc-simr.c @@ -141,7 +141,7 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type) } if (tb) - set_irq_handler(irq, handle_edge_irq); + irq_set_handler(irq, handle_edge_irq); ebit = irq2ebit(irq) * 2; pa = __raw_readw(MCFEPORT_EPPAR); @@ -181,11 +181,11 @@ void __init init_IRQ(void) eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0); for (irq = MCFINT_VECBASE; (irq < eirq); irq++) { if ((irq >= EINT1) && (irq <= EINT7)) - set_irq_chip(irq, &intc_irq_chip_edge_port); + irq_set_chip(irq, &intc_irq_chip_edge_port); else - set_irq_chip(irq, &intc_irq_chip); - set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); - set_irq_handler(irq, handle_level_irq); + irq_set_chip(irq, &intc_irq_chip); + irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); + irq_set_handler(irq, handle_level_irq); } } diff --git a/arch/m68knommu/platform/coldfire/intc.c b/arch/m68k/platform/coldfire/intc.c index d648081a63f..0bbb414856e 100644 --- a/arch/m68knommu/platform/coldfire/intc.c +++ b/arch/m68k/platform/coldfire/intc.c @@ -37,7 +37,7 @@ unsigned char mcf_irq2imr[NR_IRQS]; /* * In the early version 2 core ColdFire parts the IMR register was 16 bits * in size. Version 3 (and later version 2) core parts have a 32 bit - * sized IMR register. Provide some size independant methods to access the + * sized IMR register. Provide some size independent methods to access the * IMR register. */ #ifdef MCFSIM_IMR_IS_16BITS @@ -143,9 +143,9 @@ void __init init_IRQ(void) mcf_maskimr(0xffffffff); for (irq = 0; (irq < NR_IRQS); irq++) { - set_irq_chip(irq, &intc_irq_chip); - set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); - set_irq_handler(irq, handle_level_irq); + irq_set_chip(irq, &intc_irq_chip); + irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); + irq_set_handler(irq, handle_level_irq); } } diff --git a/arch/m68knommu/platform/coldfire/pinmux.c b/arch/m68k/platform/coldfire/pinmux.c index 8c62b825939..8c62b825939 100644 --- a/arch/m68knommu/platform/coldfire/pinmux.c +++ b/arch/m68k/platform/coldfire/pinmux.c diff --git a/arch/m68knommu/platform/coldfire/pit.c b/arch/m68k/platform/coldfire/pit.c index c2b980926be..c2b980926be 100644 --- a/arch/m68knommu/platform/coldfire/pit.c +++ b/arch/m68k/platform/coldfire/pit.c diff --git a/arch/m68knommu/platform/coldfire/sltimers.c b/arch/m68k/platform/coldfire/sltimers.c index 0a1b937c3e1..6a85daf9a7f 100644 --- a/arch/m68knommu/platform/coldfire/sltimers.c +++ b/arch/m68k/platform/coldfire/sltimers.c @@ -106,7 +106,7 @@ static cycle_t mcfslt_read_clk(struct clocksource *cs) cycles = mcfslt_cnt; local_irq_restore(flags); - /* substract because slice timers count down */ + /* subtract because slice timers count down */ return cycles - scnt; } diff --git a/arch/m68knommu/platform/coldfire/timers.c b/arch/m68k/platform/coldfire/timers.c index 60242f65fea..60242f65fea 100644 --- a/arch/m68knommu/platform/coldfire/timers.c +++ b/arch/m68k/platform/coldfire/timers.c diff --git a/arch/m68knommu/platform/coldfire/vectors.c b/arch/m68k/platform/coldfire/vectors.c index a21d3f870b7..a21d3f870b7 100644 --- a/arch/m68knommu/platform/coldfire/vectors.c +++ b/arch/m68k/platform/coldfire/vectors.c diff --git a/arch/m68k/q40/README b/arch/m68k/q40/README index f877b724979..b26d5f55e91 100644 --- a/arch/m68k/q40/README +++ b/arch/m68k/q40/README @@ -89,7 +89,7 @@ The main interrupt register IIRQ_REG will indicate whether an IRQ was internal or from some ISA devices, EIRQ_REG can distinguish up to 8 ISA IRQs. The Q40 custom chip is programmable to provide 2 periodic timers: - - 50 or 200 Hz - level 2, !!THIS CANT BE DISABLED!! + - 50 or 200 Hz - level 2, !!THIS CAN'T BE DISABLED!! - 10 or 20 KHz - level 4, used for dma-sound Linux uses the 200 Hz interrupt for timer and beep by default. diff --git a/arch/m68knommu/Kconfig.debug b/arch/m68knommu/Kconfig.debug deleted file mode 100644 index ed6d9a83bfd..00000000000 --- a/arch/m68knommu/Kconfig.debug +++ /dev/null @@ -1,35 +0,0 @@ -menu "Kernel hacking" - -source "lib/Kconfig.debug" - -config FULLDEBUG - bool "Full Symbolic/Source Debugging support" - help - Enable debugging symbols on kernel build. - -config HIGHPROFILE - bool "Use fast second timer for profiling" - depends on COLDFIRE - help - Use a fast secondary clock to produce profiling information. - -config BOOTPARAM - bool 'Compiled-in Kernel Boot Parameter' - -config BOOTPARAM_STRING - string 'Kernel Boot Parameter' - default 'console=ttyS0,19200' - depends on BOOTPARAM - -config NO_KERNEL_MSG - bool "Suppress Kernel BUG Messages" - help - Do not output any debug BUG messages within the kernel. - -config BDM_DISABLE - bool "Disable BDM signals" - depends on (EXPERIMENTAL && COLDFIRE) - help - Disable the ColdFire CPU's BDM signals. - -endmenu diff --git a/arch/m68knommu/defconfig b/arch/m68knommu/defconfig deleted file mode 100644 index 2f5655c577a..00000000000 --- a/arch/m68knommu/defconfig +++ /dev/null @@ -1,74 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_KALLSYMS is not set -# CONFIG_HOTPLUG is not set -# CONFIG_FUTEX is not set -# CONFIG_EPOLL is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_M520x=y -CONFIG_CLOCK_SET=y -CONFIG_CLOCK_FREQ=166666666 -CONFIG_CLOCK_DIV=2 -CONFIG_M5208EVB=y -# CONFIG_4KSTACKS is not set -CONFIG_RAMBASE=0x40000000 -CONFIG_RAMSIZE=0x2000000 -CONFIG_VECTORBASE=0x40000000 -CONFIG_KERNELBASE=0x40020000 -CONFIG_RAM16BIT=y -CONFIG_BINFMT_FLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_RAM=y -CONFIG_MTD_UCLINUX=y -CONFIG_BLK_DEV_RAM=y -# CONFIG_MISC_DEVICES is not set -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_FEC=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_SERIAL_MCF=y -CONFIG_SERIAL_MCF_BAUDRATE=115200 -CONFIG_SERIAL_MCF_CONSOLE=y -# CONFIG_UNIX98_PTYS is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_EXT2_FS=y -# CONFIG_FILE_LOCKING is not set -# CONFIG_DNOTIFY is not set -# CONFIG_SYSFS is not set -CONFIG_ROMFS_FS=y -CONFIG_ROMFS_BACKED_BY_MTD=y -# CONFIG_NETWORK_FILESYSTEMS is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_FULLDEBUG=y -CONFIG_BOOTPARAM=y -CONFIG_BOOTPARAM_STRING="root=/dev/mtdblock0" diff --git a/arch/m68knommu/kernel/.gitignore b/arch/m68knommu/kernel/.gitignore deleted file mode 100644 index c5f676c3c22..00000000000 --- a/arch/m68knommu/kernel/.gitignore +++ /dev/null @@ -1 +0,0 @@ -vmlinux.lds diff --git a/arch/m68knommu/lib/ashldi3.c b/arch/m68knommu/lib/ashldi3.c deleted file mode 100644 index 008403eb8ce..00000000000 --- a/arch/m68knommu/lib/ashldi3.c +++ /dev/null @@ -1,62 +0,0 @@ -/* ashrdi3.c extracted from gcc-2.95.2/libgcc2.c which is: */ -/* Copyright (C) 1989, 92-98, 1999 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#define BITS_PER_UNIT 8 - -typedef int SItype __attribute__ ((mode (SI))); -typedef unsigned int USItype __attribute__ ((mode (SI))); -typedef int DItype __attribute__ ((mode (DI))); -typedef int word_type __attribute__ ((mode (__word__))); - -struct DIstruct {SItype high, low;}; - -typedef union -{ - struct DIstruct s; - DItype ll; -} DIunion; - -DItype -__ashldi3 (DItype u, word_type b) -{ - DIunion w; - word_type bm; - DIunion uu; - - if (b == 0) - return u; - - uu.ll = u; - - bm = (sizeof (SItype) * BITS_PER_UNIT) - b; - if (bm <= 0) - { - w.s.low = 0; - w.s.high = (USItype)uu.s.low << -bm; - } - else - { - USItype carries = (USItype)uu.s.low >> bm; - w.s.low = (USItype)uu.s.low << b; - w.s.high = ((USItype)uu.s.high << b) | carries; - } - - return w.ll; -} diff --git a/arch/m68knommu/lib/lshrdi3.c b/arch/m68knommu/lib/lshrdi3.c deleted file mode 100644 index 93b1cb6fdee..00000000000 --- a/arch/m68knommu/lib/lshrdi3.c +++ /dev/null @@ -1,62 +0,0 @@ -/* lshrdi3.c extracted from gcc-2.7.2/libgcc2.c which is: */ -/* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#define BITS_PER_UNIT 8 - -typedef int SItype __attribute__ ((mode (SI))); -typedef unsigned int USItype __attribute__ ((mode (SI))); -typedef int DItype __attribute__ ((mode (DI))); -typedef int word_type __attribute__ ((mode (__word__))); - -struct DIstruct {SItype high, low;}; - -typedef union -{ - struct DIstruct s; - DItype ll; -} DIunion; - -DItype -__lshrdi3 (DItype u, word_type b) -{ - DIunion w; - word_type bm; - DIunion uu; - - if (b == 0) - return u; - - uu.ll = u; - - bm = (sizeof (SItype) * BITS_PER_UNIT) - b; - if (bm <= 0) - { - w.s.high = 0; - w.s.low = (USItype)uu.s.high >> -bm; - } - else - { - USItype carries = (USItype)uu.s.high << bm; - w.s.high = (USItype)uu.s.high >> b; - w.s.low = ((USItype)uu.s.low >> b) | carries; - } - - return w.ll; -} diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 922c4194c7b..eccdefe70d4 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -6,7 +6,6 @@ config MICROBLAZE select HAVE_FUNCTION_GRAPH_TRACER select HAVE_DYNAMIC_FTRACE select HAVE_FTRACE_MCOUNT_RECORD - select USB_ARCH_HAS_EHCI select ARCH_WANT_OPTIONAL_GPIOLIB select HAVE_OPROFILE select HAVE_ARCH_KGDB @@ -17,7 +16,7 @@ config MICROBLAZE select OF_EARLY_FLATTREE select HAVE_GENERIC_HARDIRQS select GENERIC_IRQ_PROBE - select GENERIC_HARDIRQS_NO_DEPRECATED + select GENERIC_IRQ_SHOW config SWAP def_bool n @@ -37,6 +36,9 @@ config ARCH_HAS_ILOG2_U64 config GENERIC_FIND_NEXT_BIT def_bool y +config GENERIC_FIND_BIT_LE + def_bool y + config GENERIC_HWEIGHT def_bool y diff --git a/arch/microblaze/Makefile b/arch/microblaze/Makefile index 6f432e6df9a..b23c40eb7a5 100644 --- a/arch/microblaze/Makefile +++ b/arch/microblaze/Makefile @@ -18,7 +18,7 @@ export CPU_VER CPU_MAJOR CPU_MINOR CPU_REV # rather than bools y/n # Work out HW multipler support. This is tricky. -# 1. Spartan2 has no HW multiplers. +# 1. Spartan2 has no HW multipliers. # 2. MicroBlaze v3.x always uses them, except in Spartan 2 # 3. All other FPGa/CPU ver combos, we can trust the CONFIG_ settings ifeq (,$(findstring spartan2,$(CONFIG_XILINX_MICROBLAZE0_FAMILY))) diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h index eae32220f44..8cdac14b55b 100644 --- a/arch/microblaze/include/asm/io.h +++ b/arch/microblaze/include/asm/io.h @@ -70,7 +70,7 @@ static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr) /* * read (readb, readw, readl, readq) and write (writeb, writew, - * writel, writeq) accessors are for PCI and thus littel endian. + * writel, writeq) accessors are for PCI and thus little endian. * Linux 2.4 for Microblaze had this wrong. */ static inline unsigned char readb(const volatile void __iomem *addr) diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h index 10717669e0c..746df91e579 100644 --- a/arch/microblaze/include/asm/pci-bridge.h +++ b/arch/microblaze/include/asm/pci-bridge.h @@ -76,7 +76,7 @@ struct pci_controller { * Used for variants of PCI indirect handling and possible quirks: * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 * EXT_REG - provides access to PCI-e extended registers - * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS + * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS * to determine which bus number to match on when generating type0 * config cycles diff --git a/arch/microblaze/include/asm/pci.h b/arch/microblaze/include/asm/pci.h index 2232ff942ba..ba65cf47254 100644 --- a/arch/microblaze/include/asm/pci.h +++ b/arch/microblaze/include/asm/pci.h @@ -158,7 +158,7 @@ extern void pci_resource_to_user(const struct pci_dev *dev, int bar, extern void pcibios_setup_bus_devices(struct pci_bus *bus); extern void pcibios_setup_bus_self(struct pci_bus *bus); -/* This part of code was originaly in xilinx-pci.h */ +/* This part of code was originally in xilinx-pci.h */ #ifdef CONFIG_PCI_XILINX extern void __init xilinx_pci_init(void); #else diff --git a/arch/microblaze/include/asm/unistd.h b/arch/microblaze/include/asm/unistd.h index d770b00ec6b..30edd61a6b8 100644 --- a/arch/microblaze/include/asm/unistd.h +++ b/arch/microblaze/include/asm/unistd.h @@ -386,8 +386,12 @@ #define __NR_fanotify_init 368 #define __NR_fanotify_mark 369 #define __NR_prlimit64 370 +#define __NR_name_to_handle_at 371 +#define __NR_open_by_handle_at 372 +#define __NR_clock_adjtime 373 +#define __NR_syncfs 374 -#define __NR_syscalls 371 +#define __NR_syscalls 375 #ifdef __KERNEL__ #ifndef __ASSEMBLY__ diff --git a/arch/microblaze/kernel/Makefile b/arch/microblaze/kernel/Makefile index f0cb5c26c81..494b63b72dd 100644 --- a/arch/microblaze/kernel/Makefile +++ b/arch/microblaze/kernel/Makefile @@ -10,6 +10,7 @@ CFLAGS_REMOVE_early_printk.o = -pg CFLAGS_REMOVE_selfmod.o = -pg CFLAGS_REMOVE_heartbeat.o = -pg CFLAGS_REMOVE_ftrace.o = -pg +CFLAGS_REMOVE_process.o = -pg endif extra-y := head.o vmlinux.lds diff --git a/arch/microblaze/kernel/cpu/Makefile b/arch/microblaze/kernel/cpu/Makefile index 59cc7bceaf8..fceed4edea4 100644 --- a/arch/microblaze/kernel/cpu/Makefile +++ b/arch/microblaze/kernel/cpu/Makefile @@ -6,7 +6,7 @@ ifdef CONFIG_FUNCTION_TRACER CFLAGS_REMOVE_cache.o = -pg endif -EXTRA_CFLAGS += -DCPU_MAJOR=$(CPU_MAJOR) -DCPU_MINOR=$(CPU_MINOR) \ +ccflags-y := -DCPU_MAJOR=$(CPU_MAJOR) -DCPU_MINOR=$(CPU_MINOR) \ -DCPU_REV=$(CPU_REV) obj-y += cache.o cpuinfo.o cpuinfo-pvr-full.o cpuinfo-static.o mb.o pvr.o diff --git a/arch/microblaze/kernel/cpu/cache.c b/arch/microblaze/kernel/cpu/cache.c index cf0afd90a2c..4b7d8a3f4ae 100644 --- a/arch/microblaze/kernel/cpu/cache.c +++ b/arch/microblaze/kernel/cpu/cache.c @@ -129,7 +129,7 @@ do { \ * to use for simple wdc or wic. * * start address is cache aligned - * end address is not aligned, if end is aligned then I have to substract + * end address is not aligned, if end is aligned then I have to subtract * cacheline length because I can't flush/invalidate the next cacheline. * If is not, I align it because I will flush/invalidate whole line. */ diff --git a/arch/microblaze/kernel/ftrace.c b/arch/microblaze/kernel/ftrace.c index 515feb40455..357d56abe24 100644 --- a/arch/microblaze/kernel/ftrace.c +++ b/arch/microblaze/kernel/ftrace.c @@ -51,6 +51,9 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr) : "r" (parent), "r" (return_hooker) ); + flush_dcache_range((u32)parent, (u32)parent + 4); + flush_icache_range((u32)parent, (u32)parent + 4); + if (unlikely(faulted)) { ftrace_graph_stop(); WARN_ON(1); @@ -95,6 +98,9 @@ static int ftrace_modify_code(unsigned long addr, unsigned int value) if (unlikely(faulted)) return -EFAULT; + flush_dcache_range(addr, addr + 4); + flush_icache_range(addr, addr + 4); + return 0; } @@ -195,8 +201,6 @@ int ftrace_update_ftrace_func(ftrace_func_t func) ret += ftrace_modify_code((unsigned long)&ftrace_caller, MICROBLAZE_NOP); - /* All changes are done - lets do caches consistent */ - flush_icache(); return ret; } @@ -210,7 +214,6 @@ int ftrace_enable_ftrace_graph_caller(void) old_jump = *(unsigned int *)ip; /* save jump over instruction */ ret = ftrace_modify_code(ip, MICROBLAZE_NOP); - flush_icache(); pr_debug("%s: Replace instruction: 0x%x\n", __func__, old_jump); return ret; @@ -222,7 +225,6 @@ int ftrace_disable_ftrace_graph_caller(void) unsigned long ip = (unsigned long)(&ftrace_call_graph); ret = ftrace_modify_code(ip, old_jump); - flush_icache(); pr_debug("%s\n", __func__); return ret; diff --git a/arch/microblaze/kernel/intc.c b/arch/microblaze/kernel/intc.c index e4661285118..c88f066f41b 100644 --- a/arch/microblaze/kernel/intc.c +++ b/arch/microblaze/kernel/intc.c @@ -50,7 +50,7 @@ static void intc_enable_or_unmask(struct irq_data *d) * ack function since the handle_level_irq function * acks the irq before calling the interrupt handler */ - if (irq_to_desc(d->irq)->status & IRQ_LEVEL) + if (irqd_is_level_type(d)) out_be32(INTC_BASE + IAR, mask); } @@ -157,12 +157,12 @@ void __init init_IRQ(void) for (i = 0; i < nr_irq; ++i) { if (intr_type & (0x00000001 << i)) { - set_irq_chip_and_handler_name(i, &intc_dev, - handle_edge_irq, intc_dev.name); + irq_set_chip_and_handler_name(i, &intc_dev, + handle_edge_irq, "edge"); irq_clear_status_flags(i, IRQ_LEVEL); } else { - set_irq_chip_and_handler_name(i, &intc_dev, - handle_level_irq, intc_dev.name); + irq_set_chip_and_handler_name(i, &intc_dev, + handle_level_irq, "level"); irq_set_status_flags(i, IRQ_LEVEL); } } diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c index 09882241372..ce7ac8435d5 100644 --- a/arch/microblaze/kernel/irq.c +++ b/arch/microblaze/kernel/irq.c @@ -47,48 +47,6 @@ next_irq: trace_hardirqs_on(); } -int show_interrupts(struct seq_file *p, void *v) -{ - int i = *(loff_t *) v, j; - struct irq_desc *desc; - struct irqaction *action; - unsigned long flags; - - if (i == 0) { - seq_printf(p, " "); - for_each_online_cpu(j) - seq_printf(p, "CPU%-8d", j); - seq_putc(p, '\n'); - } - - if (i < nr_irq) { - desc = irq_to_desc(i); - raw_spin_lock_irqsave(&desc->lock, flags); - action = desc->action; - if (!action) - goto skip; - seq_printf(p, "%3d: ", i); -#ifndef CONFIG_SMP - seq_printf(p, "%10u ", kstat_irqs(i)); -#else - for_each_online_cpu(j) - seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); -#endif - seq_printf(p, " %8s", desc->status & - IRQ_LEVEL ? "level" : "edge"); - seq_printf(p, " %8s", desc->irq_data.chip->name); - seq_printf(p, " %s", action->name); - - for (action = action->next; action; action = action->next) - seq_printf(p, ", %s", action->name); - - seq_putc(p, '\n'); -skip: - raw_spin_unlock_irqrestore(&desc->lock, flags); - } - return 0; -} - /* MS: There is no any advance mapping mechanism. We are using simple 32bit intc without any cascades or any connection that's why mapping is 1:1 */ unsigned int irq_create_mapping(struct irq_host *host, irq_hw_number_t hwirq) diff --git a/arch/microblaze/kernel/syscall_table.S b/arch/microblaze/kernel/syscall_table.S index e88a930fd1e..85cea81d1ca 100644 --- a/arch/microblaze/kernel/syscall_table.S +++ b/arch/microblaze/kernel/syscall_table.S @@ -375,3 +375,7 @@ ENTRY(sys_call_table) .long sys_fanotify_init .long sys_fanotify_mark .long sys_prlimit64 /* 370 */ + .long sys_name_to_handle_at + .long sys_open_by_handle_at + .long sys_clock_adjtime + .long sys_syncfs diff --git a/arch/microblaze/lib/Makefile b/arch/microblaze/lib/Makefile index f1fcbff3da2..10c320aa908 100644 --- a/arch/microblaze/lib/Makefile +++ b/arch/microblaze/lib/Makefile @@ -2,6 +2,12 @@ # Makefile # +ifdef CONFIG_FUNCTION_TRACER +CFLAGS_REMOVE_ashldi3.o = -pg +CFLAGS_REMOVE_ashrdi3.o = -pg +CFLAGS_REMOVE_lshrdi3.o = -pg +endif + lib-y := memset.o ifeq ($(CONFIG_OPT_LIB_ASM),y) diff --git a/arch/microblaze/lib/memcpy.c b/arch/microblaze/lib/memcpy.c index cc495d7d99c..52746e718df 100644 --- a/arch/microblaze/lib/memcpy.c +++ b/arch/microblaze/lib/memcpy.c @@ -63,8 +63,8 @@ void *memcpy(void *v_dst, const void *v_src, __kernel_size_t c) if (likely(c >= 4)) { unsigned value, buf_hold; - /* Align the dstination to a word boundry. */ - /* This is done in an endian independant manner. */ + /* Align the destination to a word boundary. */ + /* This is done in an endian independent manner. */ switch ((unsigned long)dst & 3) { case 1: *dst++ = *src++; @@ -80,7 +80,7 @@ void *memcpy(void *v_dst, const void *v_src, __kernel_size_t c) i_dst = (void *)dst; /* Choose a copy scheme based on the source */ - /* alignment relative to dstination. */ + /* alignment relative to destination. */ switch ((unsigned long)src & 3) { case 0x0: /* Both byte offsets are aligned */ i_src = (const void *)src; @@ -173,7 +173,7 @@ void *memcpy(void *v_dst, const void *v_src, __kernel_size_t c) } /* Finish off any remaining bytes */ - /* simple fast copy, ... unless a cache boundry is crossed */ + /* simple fast copy, ... unless a cache boundary is crossed */ switch (c) { case 3: *dst++ = *src++; diff --git a/arch/microblaze/lib/memmove.c b/arch/microblaze/lib/memmove.c index 810fd68775e..2146c3752a8 100644 --- a/arch/microblaze/lib/memmove.c +++ b/arch/microblaze/lib/memmove.c @@ -83,8 +83,8 @@ void *memmove(void *v_dst, const void *v_src, __kernel_size_t c) if (c >= 4) { unsigned value, buf_hold; - /* Align the destination to a word boundry. */ - /* This is done in an endian independant manner. */ + /* Align the destination to a word boundary. */ + /* This is done in an endian independent manner. */ switch ((unsigned long)dst & 3) { case 3: @@ -193,7 +193,7 @@ void *memmove(void *v_dst, const void *v_src, __kernel_size_t c) dst = (void *)i_dst; } - /* simple fast copy, ... unless a cache boundry is crossed */ + /* simple fast copy, ... unless a cache boundary is crossed */ /* Finish off any remaining bytes */ switch (c) { case 4: diff --git a/arch/microblaze/lib/memset.c b/arch/microblaze/lib/memset.c index 834565d1607..ddf67939576 100644 --- a/arch/microblaze/lib/memset.c +++ b/arch/microblaze/lib/memset.c @@ -64,7 +64,7 @@ void *memset(void *v_src, int c, __kernel_size_t n) if (likely(n >= 4)) { /* Align the destination to a word boundary */ - /* This is done in an endian independant manner */ + /* This is done in an endian independent manner */ switch ((unsigned) src & 3) { case 1: *src++ = c; diff --git a/arch/microblaze/pci/indirect_pci.c b/arch/microblaze/pci/indirect_pci.c index 25f18f017f2..4196eb6bd76 100644 --- a/arch/microblaze/pci/indirect_pci.c +++ b/arch/microblaze/pci/indirect_pci.c @@ -108,7 +108,7 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | (devfn << 8) | reg | cfg_type)); - /* surpress setting of PCI_PRIMARY_BUS */ + /* suppress setting of PCI_PRIMARY_BUS */ if (hose->indirect_type & INDIRECT_TYPE_SURPRESS_PRIMARY_BUS) if ((offset == PCI_PRIMARY_BUS) && (bus->number == hose->first_busno)) diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c index 1e01a125363..53599067d2f 100644 --- a/arch/microblaze/pci/pci-common.c +++ b/arch/microblaze/pci/pci-common.c @@ -237,7 +237,7 @@ int pci_read_irq_line(struct pci_dev *pci_dev) virq = irq_create_mapping(NULL, line); if (virq != NO_IRQ) - set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); } else { pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", oirq.size, oirq.specifier[0], oirq.specifier[1], diff --git a/arch/microblaze/platform/generic/Kconfig.auto b/arch/microblaze/platform/generic/Kconfig.auto index 5d86fc19029..25a6f019e94 100644 --- a/arch/microblaze/platform/generic/Kconfig.auto +++ b/arch/microblaze/platform/generic/Kconfig.auto @@ -29,7 +29,7 @@ config KERNEL_BASE_ADDR BASE Address for kernel config XILINX_MICROBLAZE0_FAMILY - string "Targetted FPGA family" + string "Targeted FPGA family" default "virtex5" config XILINX_MICROBLAZE0_USE_MSR_INSTR diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d88983516e2..351c80fbba7 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -22,6 +22,7 @@ config MIPS select HAVE_DMA_API_DEBUG select HAVE_GENERIC_HARDIRQS select GENERIC_IRQ_PROBE + select GENERIC_IRQ_SHOW select HAVE_ARCH_JUMP_LABEL menu "Machine selection" @@ -777,6 +778,10 @@ config GENERIC_FIND_NEXT_BIT bool default y +config GENERIC_FIND_BIT_LE + bool + default y + config GENERIC_HWEIGHT bool default y @@ -858,6 +863,9 @@ config GPIO_TXX9 config CFE bool +config ARCH_DMA_ADDR_T_64BIT + def_bool (HIGHMEM && 64BIT_PHYS_ADDR) || 64BIT + config DMA_COHERENT bool @@ -989,9 +997,6 @@ config IRQ_GT641XX config IRQ_GIC bool -config IRQ_CPU_OCTEON - bool - config MIPS_BOARDS_GEN bool @@ -1127,7 +1132,7 @@ config CPU_LOONGSON2E The Loongson 2E processor implements the MIPS III instruction set with many extensions. - It has an internal FPGA northbridge, which is compatiable to + It has an internal FPGA northbridge, which is compatible to bonito64. config CPU_LOONGSON2F @@ -1351,8 +1356,6 @@ config CPU_SB1 config CPU_CAVIUM_OCTEON bool "Cavium Octeon processor" depends on SYS_HAS_CPU_CAVIUM_OCTEON - select IRQ_CPU - select IRQ_CPU_OCTEON select CPU_HAS_PREFETCH select CPU_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_SMP @@ -2340,6 +2343,16 @@ source "drivers/pcmcia/Kconfig" source "drivers/pci/hotplug/Kconfig" +config RAPIDIO + bool "RapidIO support" + depends on PCI + default n + help + If you say Y here, the kernel will include drivers and + infrastructure code to support RapidIO interconnect devices. + +source "drivers/rapidio/Kconfig" + endmenu menu "Executable file formats" diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 7c1102e41fe..53e3514ba10 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -101,7 +101,7 @@ cflags-y += -ffreestanding # carefully avoid to add it redundantly because gcc 3.3/3.4 complains # when fed the toolchain default! # -# Certain gcc versions upto gcc 4.1.1 (probably 4.2-subversion as of +# Certain gcc versions up to gcc 4.1.1 (probably 4.2-subversion as of # 2006-10-10 don't properly change the predefined symbols if -EB / -EL # are used, so we kludge that here. A bug has been filed at # http://gcc.gnu.org/bugzilla/show_bug.cgi?id=29413. @@ -286,11 +286,11 @@ CLEAN_FILES += vmlinux.32 vmlinux.64 archprepare: ifdef CONFIG_MIPS32_N32 @echo ' Checking missing-syscalls for N32' - $(Q)$(MAKE) $(build)=. missing-syscalls EXTRA_CFLAGS="-mabi=n32" + $(Q)$(MAKE) $(build)=. missing-syscalls ccflags-y="-mabi=n32" endif ifdef CONFIG_MIPS32_O32 @echo ' Checking missing-syscalls for O32' - $(Q)$(MAKE) $(build)=. missing-syscalls EXTRA_CFLAGS="-mabi=32" + $(Q)$(MAKE) $(build)=. missing-syscalls ccflags-y="-mabi=32" endif install: @@ -314,5 +314,5 @@ define archhelp echo ' vmlinuz.bin - Raw binary zboot image' echo ' vmlinuz.srec - SREC zboot image' echo - echo ' These will be default as apropriate for a configured platform.' + echo ' These will be default as appropriate for a configured platform.' endef diff --git a/arch/mips/alchemy/common/clocks.c b/arch/mips/alchemy/common/clocks.c index af0fe41055a..f38298a8b98 100644 --- a/arch/mips/alchemy/common/clocks.c +++ b/arch/mips/alchemy/common/clocks.c @@ -75,7 +75,7 @@ void set_au1x00_uart_baud_base(unsigned long new_baud_base) * counter, if it exists. If we don't have an accurate processor * speed, all of the peripherals that derive their clocks based on * this advertised speed will introduce error and sometimes not work - * properly. This function is futher convoluted to still allow configurations + * properly. This function is further convoluted to still allow configurations * to do that in case they have really, really old silicon with a * write-only PLL register. -- Dan */ diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index 9f78ada83b3..55dd7c88851 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c @@ -39,7 +39,7 @@ #include <asm/mach-pb1x00/pb1000.h> #endif -static int au1x_ic_settype(unsigned int irq, unsigned int flow_type); +static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type); /* NOTE on interrupt priorities: The original writers of this code said: * @@ -218,17 +218,17 @@ struct au1xxx_irqmap au1200_irqmap[] __initdata = { }; -static void au1x_ic0_unmask(unsigned int irq_nr) +static void au1x_ic0_unmask(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; au_writel(1 << bit, IC0_MASKSET); au_writel(1 << bit, IC0_WAKESET); au_sync(); } -static void au1x_ic1_unmask(unsigned int irq_nr) +static void au1x_ic1_unmask(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; au_writel(1 << bit, IC1_MASKSET); au_writel(1 << bit, IC1_WAKESET); @@ -236,31 +236,31 @@ static void au1x_ic1_unmask(unsigned int irq_nr) * nowhere in the current kernel sources is it disabled. --mlau */ #if defined(CONFIG_MIPS_PB1000) - if (irq_nr == AU1000_GPIO15_INT) + if (d->irq == AU1000_GPIO15_INT) au_writel(0x4000, PB1000_MDR); /* enable int */ #endif au_sync(); } -static void au1x_ic0_mask(unsigned int irq_nr) +static void au1x_ic0_mask(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; au_writel(1 << bit, IC0_MASKCLR); au_writel(1 << bit, IC0_WAKECLR); au_sync(); } -static void au1x_ic1_mask(unsigned int irq_nr) +static void au1x_ic1_mask(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; au_writel(1 << bit, IC1_MASKCLR); au_writel(1 << bit, IC1_WAKECLR); au_sync(); } -static void au1x_ic0_ack(unsigned int irq_nr) +static void au1x_ic0_ack(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; /* * This may assume that we don't get interrupts from @@ -271,9 +271,9 @@ static void au1x_ic0_ack(unsigned int irq_nr) au_sync(); } -static void au1x_ic1_ack(unsigned int irq_nr) +static void au1x_ic1_ack(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; /* * This may assume that we don't get interrupts from @@ -284,9 +284,9 @@ static void au1x_ic1_ack(unsigned int irq_nr) au_sync(); } -static void au1x_ic0_maskack(unsigned int irq_nr) +static void au1x_ic0_maskack(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; au_writel(1 << bit, IC0_WAKECLR); au_writel(1 << bit, IC0_MASKCLR); @@ -295,9 +295,9 @@ static void au1x_ic0_maskack(unsigned int irq_nr) au_sync(); } -static void au1x_ic1_maskack(unsigned int irq_nr) +static void au1x_ic1_maskack(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; au_writel(1 << bit, IC1_WAKECLR); au_writel(1 << bit, IC1_MASKCLR); @@ -306,9 +306,9 @@ static void au1x_ic1_maskack(unsigned int irq_nr) au_sync(); } -static int au1x_ic1_setwake(unsigned int irq, unsigned int on) +static int au1x_ic1_setwake(struct irq_data *d, unsigned int on) { - int bit = irq - AU1000_INTC1_INT_BASE; + int bit = d->irq - AU1000_INTC1_INT_BASE; unsigned long wakemsk, flags; /* only GPIO 0-7 can act as wakeup source. Fortunately these @@ -336,28 +336,30 @@ static int au1x_ic1_setwake(unsigned int irq, unsigned int on) */ static struct irq_chip au1x_ic0_chip = { .name = "Alchemy-IC0", - .ack = au1x_ic0_ack, - .mask = au1x_ic0_mask, - .mask_ack = au1x_ic0_maskack, - .unmask = au1x_ic0_unmask, - .set_type = au1x_ic_settype, + .irq_ack = au1x_ic0_ack, + .irq_mask = au1x_ic0_mask, + .irq_mask_ack = au1x_ic0_maskack, + .irq_unmask = au1x_ic0_unmask, + .irq_set_type = au1x_ic_settype, }; static struct irq_chip au1x_ic1_chip = { .name = "Alchemy-IC1", - .ack = au1x_ic1_ack, - .mask = au1x_ic1_mask, - .mask_ack = au1x_ic1_maskack, - .unmask = au1x_ic1_unmask, - .set_type = au1x_ic_settype, - .set_wake = au1x_ic1_setwake, + .irq_ack = au1x_ic1_ack, + .irq_mask = au1x_ic1_mask, + .irq_mask_ack = au1x_ic1_maskack, + .irq_unmask = au1x_ic1_unmask, + .irq_set_type = au1x_ic_settype, + .irq_set_wake = au1x_ic1_setwake, }; -static int au1x_ic_settype(unsigned int irq, unsigned int flow_type) +static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type) { struct irq_chip *chip; unsigned long icr[6]; - unsigned int bit, ic; + unsigned int bit, ic, irq = d->irq; + irq_flow_handler_t handler = NULL; + unsigned char *name = NULL; int ret; if (irq >= AU1000_INTC1_INT_BASE) { @@ -387,47 +389,47 @@ static int au1x_ic_settype(unsigned int irq, unsigned int flow_type) au_writel(1 << bit, icr[5]); au_writel(1 << bit, icr[4]); au_writel(1 << bit, icr[0]); - set_irq_chip_and_handler_name(irq, chip, - handle_edge_irq, "riseedge"); + handler = handle_edge_irq; + name = "riseedge"; break; case IRQ_TYPE_EDGE_FALLING: /* 0:1:0 */ au_writel(1 << bit, icr[5]); au_writel(1 << bit, icr[1]); au_writel(1 << bit, icr[3]); - set_irq_chip_and_handler_name(irq, chip, - handle_edge_irq, "falledge"); + handler = handle_edge_irq; + name = "falledge"; break; case IRQ_TYPE_EDGE_BOTH: /* 0:1:1 */ au_writel(1 << bit, icr[5]); au_writel(1 << bit, icr[1]); au_writel(1 << bit, icr[0]); - set_irq_chip_and_handler_name(irq, chip, - handle_edge_irq, "bothedge"); + handler = handle_edge_irq; + name = "bothedge"; break; case IRQ_TYPE_LEVEL_HIGH: /* 1:0:1 */ au_writel(1 << bit, icr[2]); au_writel(1 << bit, icr[4]); au_writel(1 << bit, icr[0]); - set_irq_chip_and_handler_name(irq, chip, - handle_level_irq, "hilevel"); + handler = handle_level_irq; + name = "hilevel"; break; case IRQ_TYPE_LEVEL_LOW: /* 1:1:0 */ au_writel(1 << bit, icr[2]); au_writel(1 << bit, icr[1]); au_writel(1 << bit, icr[3]); - set_irq_chip_and_handler_name(irq, chip, - handle_level_irq, "lowlevel"); + handler = handle_level_irq; + name = "lowlevel"; break; case IRQ_TYPE_NONE: /* 0:0:0 */ au_writel(1 << bit, icr[5]); au_writel(1 << bit, icr[4]); au_writel(1 << bit, icr[3]); - /* set at least chip so we can call set_irq_type() on it */ - set_irq_chip(irq, chip); break; default: ret = -EINVAL; } + __irq_set_chip_handler_name_locked(d->irq, chip, handler, name); + au_sync(); return ret; @@ -504,11 +506,11 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map) */ for (i = AU1000_INTC0_INT_BASE; (i < AU1000_INTC0_INT_BASE + 32); i++) - au1x_ic_settype(i, IRQ_TYPE_NONE); + au1x_ic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE); for (i = AU1000_INTC1_INT_BASE; (i < AU1000_INTC1_INT_BASE + 32); i++) - au1x_ic_settype(i, IRQ_TYPE_NONE); + au1x_ic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE); /* * Initialize IC0, which is fixed per processor. @@ -526,7 +528,7 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map) au_writel(1 << bit, IC0_ASSIGNSET); } - au1x_ic_settype(irq_nr, map->im_type); + au1x_ic_settype(irq_get_irq_data(irq_nr), map->im_type); ++map; } diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c index c52af8821da..596ad00e7f0 100644 --- a/arch/mips/alchemy/devboards/bcsr.c +++ b/arch/mips/alchemy/devboards/bcsr.c @@ -97,26 +97,26 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d) * CPLD generates tons of spurious interrupts (at least on my DB1200). * -- mlau */ -static void bcsr_irq_mask(unsigned int irq_nr) +static void bcsr_irq_mask(struct irq_data *d) { - unsigned short v = 1 << (irq_nr - bcsr_csc_base); + unsigned short v = 1 << (d->irq - bcsr_csc_base); __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR); __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); wmb(); } -static void bcsr_irq_maskack(unsigned int irq_nr) +static void bcsr_irq_maskack(struct irq_data *d) { - unsigned short v = 1 << (irq_nr - bcsr_csc_base); + unsigned short v = 1 << (d->irq - bcsr_csc_base); __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR); __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */ wmb(); } -static void bcsr_irq_unmask(unsigned int irq_nr) +static void bcsr_irq_unmask(struct irq_data *d) { - unsigned short v = 1 << (irq_nr - bcsr_csc_base); + unsigned short v = 1 << (d->irq - bcsr_csc_base); __raw_writew(v, bcsr_virt + BCSR_REG_INTSET); __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET); wmb(); @@ -124,9 +124,9 @@ static void bcsr_irq_unmask(unsigned int irq_nr) static struct irq_chip bcsr_irq_type = { .name = "CPLD", - .mask = bcsr_irq_mask, - .mask_ack = bcsr_irq_maskack, - .unmask = bcsr_irq_unmask, + .irq_mask = bcsr_irq_mask, + .irq_mask_ack = bcsr_irq_maskack, + .irq_unmask = bcsr_irq_unmask, }; void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq) @@ -142,8 +142,8 @@ void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq) bcsr_csc_base = csc_start; for (irq = csc_start; irq <= csc_end; irq++) - set_irq_chip_and_handler_name(irq, &bcsr_irq_type, - handle_level_irq, "level"); + irq_set_chip_and_handler_name(irq, &bcsr_irq_type, + handle_level_irq, "level"); - set_irq_chained_handler(hook_irq, bcsr_csc_handler); + irq_set_chained_handler(hook_irq, bcsr_csc_handler); } diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c index 88761954755..4a8980027ec 100644 --- a/arch/mips/alchemy/devboards/db1200/setup.c +++ b/arch/mips/alchemy/devboards/db1200/setup.c @@ -63,20 +63,19 @@ void __init board_setup(void) static int __init db1200_arch_init(void) { /* GPIO7 is low-level triggered CPLD cascade */ - set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); /* insert/eject pairs: one of both is always screaming. To avoid * issues they must not be automatically enabled when initially * requested. */ - irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN; - irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN; - irq_to_desc(DB1200_PC0_INSERT_INT)->status |= IRQ_NOAUTOEN; - irq_to_desc(DB1200_PC0_EJECT_INT)->status |= IRQ_NOAUTOEN; - irq_to_desc(DB1200_PC1_INSERT_INT)->status |= IRQ_NOAUTOEN; - irq_to_desc(DB1200_PC1_EJECT_INT)->status |= IRQ_NOAUTOEN; - + irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN); return 0; } arch_initcall(db1200_arch_init); diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c index 9e45971343e..5c956fe8760 100644 --- a/arch/mips/alchemy/devboards/db1x00/board_setup.c +++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c @@ -127,13 +127,10 @@ const char *get_system_type(void) void __init board_setup(void) { unsigned long bcsr1, bcsr2; - u32 pin_func; bcsr1 = DB1000_BCSR_PHYS_ADDR; bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS; - pin_func = 0; - #ifdef CONFIG_MIPS_DB1000 printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n"); #endif @@ -164,12 +161,16 @@ void __init board_setup(void) /* Not valid for Au1550 */ #if defined(CONFIG_IRDA) && \ (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100)) - /* Set IRFIRSEL instead of GPIO15 */ - pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF; - au_writel(pin_func, SYS_PINFUNC); - /* Power off until the driver is in use */ - bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK, - BCSR_RESETS_IRDA_MODE_OFF); + { + u32 pin_func; + + /* Set IRFIRSEL instead of GPIO15 */ + pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF; + au_writel(pin_func, SYS_PINFUNC); + /* Power off until the driver is in use */ + bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK, + BCSR_RESETS_IRDA_MODE_OFF); + } #endif bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */ @@ -177,31 +178,35 @@ void __init board_setup(void) alchemy_gpio1_input_enable(); #ifdef CONFIG_MIPS_MIRAGE - /* GPIO[20] is output */ - alchemy_gpio_direction_output(20, 0); + { + u32 pin_func; - /* Set GPIO[210:208] instead of SSI_0 */ - pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0; + /* GPIO[20] is output */ + alchemy_gpio_direction_output(20, 0); - /* Set GPIO[215:211] for LEDs */ - pin_func |= 5 << 2; + /* Set GPIO[210:208] instead of SSI_0 */ + pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0; - /* Set GPIO[214:213] for more LEDs */ - pin_func |= 5 << 12; + /* Set GPIO[215:211] for LEDs */ + pin_func |= 5 << 2; - /* Set GPIO[207:200] instead of PCMCIA/LCD */ - pin_func |= SYS_PF_LCD | SYS_PF_PC; - au_writel(pin_func, SYS_PINFUNC); + /* Set GPIO[214:213] for more LEDs */ + pin_func |= 5 << 12; - /* - * Enable speaker amplifier. This should - * be part of the audio driver. - */ - alchemy_gpio_direction_output(209, 1); + /* Set GPIO[207:200] instead of PCMCIA/LCD */ + pin_func |= SYS_PF_LCD | SYS_PF_PC; + au_writel(pin_func, SYS_PINFUNC); - pm_power_off = mirage_power_off; - _machine_halt = mirage_power_off; - _machine_restart = (void(*)(char *))mips_softreset; + /* + * Enable speaker amplifier. This should + * be part of the audio driver. + */ + alchemy_gpio_direction_output(209, 1); + + pm_power_off = mirage_power_off; + _machine_halt = mirage_power_off; + _machine_restart = (void(*)(char *))mips_softreset; + } #endif #ifdef CONFIG_MIPS_BOSPORUS @@ -215,35 +220,35 @@ void __init board_setup(void) static int __init db1x00_init_irq(void) { #if defined(CONFIG_MIPS_MIRAGE) - set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */ + irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */ #elif defined(CONFIG_MIPS_DB1550) - set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ - set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */ - set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */ - set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ - set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ - set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ + irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ + irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */ + irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */ + irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ + irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ + irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ #elif defined(CONFIG_MIPS_DB1500) - set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ - set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ - set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ - set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ - set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ - set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ + irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ + irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ + irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ + irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ + irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ + irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ #elif defined(CONFIG_MIPS_DB1100) - set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ - set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ - set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ - set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ - set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ - set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ + irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ + irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ + irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ + irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ + irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ + irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ #elif defined(CONFIG_MIPS_DB1000) - set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ - set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ - set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ - set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ - set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ - set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ + irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ + irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ + irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ + irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ + irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ + irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ #endif return 0; } diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c index f6540ec47a6..2d85c4b5be0 100644 --- a/arch/mips/alchemy/devboards/pb1000/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c @@ -197,7 +197,7 @@ void __init board_setup(void) static int __init pb1000_init_irq(void) { - set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW); return 0; } arch_initcall(pb1000_init_irq); diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100/board_setup.c index 90dda5f3ecc..d108fd573aa 100644 --- a/arch/mips/alchemy/devboards/pb1100/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1100/board_setup.c @@ -117,10 +117,10 @@ void __init board_setup(void) static int __init pb1100_init_irq(void) { - set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */ - set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */ - set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */ - set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */ + irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */ + irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */ + irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */ + irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */ return 0; } diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c index 8b4466f2d44..6d06b07c238 100644 --- a/arch/mips/alchemy/devboards/pb1200/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1200/board_setup.c @@ -142,7 +142,7 @@ static int __init pb1200_init_irq(void) panic("Game over. Your score is 0."); } - set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT); return 0; diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c index 9cd9dfa698e..83f46215eb0 100644 --- a/arch/mips/alchemy/devboards/pb1500/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c @@ -134,14 +134,14 @@ void __init board_setup(void) static int __init pb1500_init_irq(void) { - set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */ - set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */ - set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ - set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); - set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); - set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); - set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); - set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */ + irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */ + irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ + irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); + irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); return 0; } diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c index 9d7d6edafa8..b790213848b 100644 --- a/arch/mips/alchemy/devboards/pb1550/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c @@ -73,9 +73,9 @@ void __init board_setup(void) static int __init pb1550_init_irq(void) { - set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); - set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); - set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH); + irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH); /* enable both PCMCIA card irqs in the shared line */ alchemy_gpio2_enable_int(201); diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c index 40b84b99119..cf436ab679a 100644 --- a/arch/mips/alchemy/mtx-1/board_setup.c +++ b/arch/mips/alchemy/mtx-1/board_setup.c @@ -123,11 +123,11 @@ mtx1_pci_idsel(unsigned int devsel, int assert) static int __init mtx1_init_irq(void) { - set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); - set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); - set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); - set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); - set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); + irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); return 0; } diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c index 80c521e5290..febfb0fb089 100644 --- a/arch/mips/alchemy/xxs1500/board_setup.c +++ b/arch/mips/alchemy/xxs1500/board_setup.c @@ -85,19 +85,19 @@ void __init board_setup(void) static int __init xxs1500_init_irq(void) { - set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); - set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); - set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); - set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); - set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); - set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); + irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW); - set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); - set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); - set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); - set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); - set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */ - set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */ + irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); return 0; } diff --git a/arch/mips/alchemy/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c index 15125c2fda7..34a90a4bb6f 100644 --- a/arch/mips/alchemy/xxs1500/init.c +++ b/arch/mips/alchemy/xxs1500/init.c @@ -51,10 +51,9 @@ void __init prom_init(void) prom_init_cmdline(); memsize_str = prom_getenv("memsize"); - if (!memsize_str) + if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize)) memsize = 0x04000000; - else - strict_strtoul(memsize_str, 0, &memsize); + add_memory_region(0, memsize, BOOT_MEM_RAM); } diff --git a/arch/mips/ar7/irq.c b/arch/mips/ar7/irq.c index 4ec2642c568..03db3daadbd 100644 --- a/arch/mips/ar7/irq.c +++ b/arch/mips/ar7/irq.c @@ -49,51 +49,51 @@ static int ar7_irq_base; -static void ar7_unmask_irq(unsigned int irq) +static void ar7_unmask_irq(struct irq_data *d) { - writel(1 << ((irq - ar7_irq_base) % 32), - REG(ESR_OFFSET(irq - ar7_irq_base))); + writel(1 << ((d->irq - ar7_irq_base) % 32), + REG(ESR_OFFSET(d->irq - ar7_irq_base))); } -static void ar7_mask_irq(unsigned int irq) +static void ar7_mask_irq(struct irq_data *d) { - writel(1 << ((irq - ar7_irq_base) % 32), - REG(ECR_OFFSET(irq - ar7_irq_base))); + writel(1 << ((d->irq - ar7_irq_base) % 32), + REG(ECR_OFFSET(d->irq - ar7_irq_base))); } -static void ar7_ack_irq(unsigned int irq) +static void ar7_ack_irq(struct irq_data *d) { - writel(1 << ((irq - ar7_irq_base) % 32), - REG(CR_OFFSET(irq - ar7_irq_base))); + writel(1 << ((d->irq - ar7_irq_base) % 32), + REG(CR_OFFSET(d->irq - ar7_irq_base))); } -static void ar7_unmask_sec_irq(unsigned int irq) +static void ar7_unmask_sec_irq(struct irq_data *d) { - writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); + writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); } -static void ar7_mask_sec_irq(unsigned int irq) +static void ar7_mask_sec_irq(struct irq_data *d) { - writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); + writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); } -static void ar7_ack_sec_irq(unsigned int irq) +static void ar7_ack_sec_irq(struct irq_data *d) { - writel(1 << (irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); + writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); } static struct irq_chip ar7_irq_type = { .name = "AR7", - .unmask = ar7_unmask_irq, - .mask = ar7_mask_irq, - .ack = ar7_ack_irq + .irq_unmask = ar7_unmask_irq, + .irq_mask = ar7_mask_irq, + .irq_ack = ar7_ack_irq }; static struct irq_chip ar7_sec_irq_type = { .name = "AR7", - .unmask = ar7_unmask_sec_irq, - .mask = ar7_mask_sec_irq, - .ack = ar7_ack_sec_irq, + .irq_unmask = ar7_unmask_sec_irq, + .irq_mask = ar7_mask_sec_irq, + .irq_ack = ar7_ack_sec_irq, }; static struct irqaction ar7_cascade_action = { @@ -119,11 +119,11 @@ static void __init ar7_irq_init(int base) for (i = 0; i < 40; i++) { writel(i, REG(CHNL_OFFSET(i))); /* Primary IRQ's */ - set_irq_chip_and_handler(base + i, &ar7_irq_type, + irq_set_chip_and_handler(base + i, &ar7_irq_type, handle_level_irq); /* Secondary IRQ's */ if (i < 32) - set_irq_chip_and_handler(base + i + 40, + irq_set_chip_and_handler(base + i + 40, &ar7_sec_irq_type, handle_level_irq); } diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c index 1bf7f719ba5..ac610d5fe3b 100644 --- a/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c @@ -62,13 +62,12 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc) spurious_interrupt(); } -static void ar71xx_misc_irq_unmask(unsigned int irq) +static void ar71xx_misc_irq_unmask(struct irq_data *d) { + unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE; void __iomem *base = ath79_reset_base; u32 t; - irq -= ATH79_MISC_IRQ_BASE; - t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); @@ -76,13 +75,12 @@ static void ar71xx_misc_irq_unmask(unsigned int irq) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); } -static void ar71xx_misc_irq_mask(unsigned int irq) +static void ar71xx_misc_irq_mask(struct irq_data *d) { + unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE; void __iomem *base = ath79_reset_base; u32 t; - irq -= ATH79_MISC_IRQ_BASE; - t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); @@ -90,13 +88,12 @@ static void ar71xx_misc_irq_mask(unsigned int irq) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); } -static void ar724x_misc_irq_ack(unsigned int irq) +static void ar724x_misc_irq_ack(struct irq_data *d) { + unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE; void __iomem *base = ath79_reset_base; u32 t; - irq -= ATH79_MISC_IRQ_BASE; - t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS); @@ -106,8 +103,8 @@ static void ar724x_misc_irq_ack(unsigned int irq) static struct irq_chip ath79_misc_irq_chip = { .name = "MISC", - .unmask = ar71xx_misc_irq_unmask, - .mask = ar71xx_misc_irq_mask, + .irq_unmask = ar71xx_misc_irq_unmask, + .irq_mask = ar71xx_misc_irq_mask, }; static void __init ath79_misc_irq_init(void) @@ -119,20 +116,19 @@ static void __init ath79_misc_irq_init(void) __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); if (soc_is_ar71xx() || soc_is_ar913x()) - ath79_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask; + ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; else if (soc_is_ar724x()) - ath79_misc_irq_chip.ack = ar724x_misc_irq_ack; + ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; else BUG(); for (i = ATH79_MISC_IRQ_BASE; i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) { - irq_desc[i].status = IRQ_DISABLED; - set_irq_chip_and_handler(i, &ath79_misc_irq_chip, + irq_set_chip_and_handler(i, &ath79_misc_irq_chip, handle_level_irq); } - set_irq_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler); + irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler); } asmlinkage void plat_irq_dispatch(void) diff --git a/arch/mips/bcm63xx/boards/Makefile b/arch/mips/bcm63xx/boards/Makefile index e5cc86dc1da..9f64fb41407 100644 --- a/arch/mips/bcm63xx/boards/Makefile +++ b/arch/mips/bcm63xx/boards/Makefile @@ -1,3 +1,3 @@ obj-$(CONFIG_BOARD_BCM963XX) += board_bcm963xx.o -EXTRA_CFLAGS += -Werror +ccflags-y := -Werror diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index 3be87f2422f..cea6021cb8d 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -76,88 +76,80 @@ asmlinkage void plat_irq_dispatch(void) * internal IRQs operations: only mask/unmask on PERF irq mask * register. */ -static inline void bcm63xx_internal_irq_mask(unsigned int irq) +static inline void bcm63xx_internal_irq_mask(struct irq_data *d) { + unsigned int irq = d->irq - IRQ_INTERNAL_BASE; u32 mask; - irq -= IRQ_INTERNAL_BASE; mask = bcm_perf_readl(PERF_IRQMASK_REG); mask &= ~(1 << irq); bcm_perf_writel(mask, PERF_IRQMASK_REG); } -static void bcm63xx_internal_irq_unmask(unsigned int irq) +static void bcm63xx_internal_irq_unmask(struct irq_data *d) { + unsigned int irq = d->irq - IRQ_INTERNAL_BASE; u32 mask; - irq -= IRQ_INTERNAL_BASE; mask = bcm_perf_readl(PERF_IRQMASK_REG); mask |= (1 << irq); bcm_perf_writel(mask, PERF_IRQMASK_REG); } -static unsigned int bcm63xx_internal_irq_startup(unsigned int irq) -{ - bcm63xx_internal_irq_unmask(irq); - return 0; -} - /* * external IRQs operations: mask/unmask and clear on PERF external * irq control register. */ -static void bcm63xx_external_irq_mask(unsigned int irq) +static void bcm63xx_external_irq_mask(struct irq_data *d) { + unsigned int irq = d->irq - IRQ_EXT_BASE; u32 reg; - irq -= IRQ_EXT_BASE; reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); reg &= ~EXTIRQ_CFG_MASK(irq); bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); } -static void bcm63xx_external_irq_unmask(unsigned int irq) +static void bcm63xx_external_irq_unmask(struct irq_data *d) { + unsigned int irq = d->irq - IRQ_EXT_BASE; u32 reg; - irq -= IRQ_EXT_BASE; reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); reg |= EXTIRQ_CFG_MASK(irq); bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); } -static void bcm63xx_external_irq_clear(unsigned int irq) +static void bcm63xx_external_irq_clear(struct irq_data *d) { + unsigned int irq = d->irq - IRQ_EXT_BASE; u32 reg; - irq -= IRQ_EXT_BASE; reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); reg |= EXTIRQ_CFG_CLEAR(irq); bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); } -static unsigned int bcm63xx_external_irq_startup(unsigned int irq) +static unsigned int bcm63xx_external_irq_startup(struct irq_data *d) { - set_c0_status(0x100 << (irq - IRQ_MIPS_BASE)); + set_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE)); irq_enable_hazard(); - bcm63xx_external_irq_unmask(irq); + bcm63xx_external_irq_unmask(d); return 0; } -static void bcm63xx_external_irq_shutdown(unsigned int irq) +static void bcm63xx_external_irq_shutdown(struct irq_data *d) { - bcm63xx_external_irq_mask(irq); - clear_c0_status(0x100 << (irq - IRQ_MIPS_BASE)); + bcm63xx_external_irq_mask(d); + clear_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE)); irq_disable_hazard(); } -static int bcm63xx_external_irq_set_type(unsigned int irq, +static int bcm63xx_external_irq_set_type(struct irq_data *d, unsigned int flow_type) { + unsigned int irq = d->irq - IRQ_EXT_BASE; u32 reg; - struct irq_desc *desc = irq_desc + irq; - - irq -= IRQ_EXT_BASE; flow_type &= IRQ_TYPE_SENSE_MASK; @@ -199,37 +191,32 @@ static int bcm63xx_external_irq_set_type(unsigned int irq, } bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); - if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) { - desc->status |= IRQ_LEVEL; - desc->handle_irq = handle_level_irq; - } else { - desc->handle_irq = handle_edge_irq; - } + irqd_set_trigger_type(d, flow_type); + if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + __irq_set_handler_locked(d->irq, handle_level_irq); + else + __irq_set_handler_locked(d->irq, handle_edge_irq); - return 0; + return IRQ_SET_MASK_OK_NOCOPY; } static struct irq_chip bcm63xx_internal_irq_chip = { .name = "bcm63xx_ipic", - .startup = bcm63xx_internal_irq_startup, - .shutdown = bcm63xx_internal_irq_mask, - - .mask = bcm63xx_internal_irq_mask, - .mask_ack = bcm63xx_internal_irq_mask, - .unmask = bcm63xx_internal_irq_unmask, + .irq_mask = bcm63xx_internal_irq_mask, + .irq_unmask = bcm63xx_internal_irq_unmask, }; static struct irq_chip bcm63xx_external_irq_chip = { .name = "bcm63xx_epic", - .startup = bcm63xx_external_irq_startup, - .shutdown = bcm63xx_external_irq_shutdown, + .irq_startup = bcm63xx_external_irq_startup, + .irq_shutdown = bcm63xx_external_irq_shutdown, - .ack = bcm63xx_external_irq_clear, + .irq_ack = bcm63xx_external_irq_clear, - .mask = bcm63xx_external_irq_mask, - .unmask = bcm63xx_external_irq_unmask, + .irq_mask = bcm63xx_external_irq_mask, + .irq_unmask = bcm63xx_external_irq_unmask, - .set_type = bcm63xx_external_irq_set_type, + .irq_set_type = bcm63xx_external_irq_set_type, }; static struct irqaction cpu_ip2_cascade_action = { @@ -243,11 +230,11 @@ void __init arch_init_irq(void) mips_cpu_irq_init(); for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i) - set_irq_chip_and_handler(i, &bcm63xx_internal_irq_chip, + irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip, handle_level_irq); for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i) - set_irq_chip_and_handler(i, &bcm63xx_external_irq_chip, + irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip, handle_edge_irq); setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action); diff --git a/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c b/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c index 88c9d963be8..9a6243676e2 100644 --- a/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c +++ b/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c @@ -16,8 +16,8 @@ int main(int argc, char *argv[]) { + unsigned long long vmlinux_size, vmlinux_load_addr, vmlinuz_load_addr; struct stat sb; - uint64_t vmlinux_size, vmlinux_load_addr, vmlinuz_load_addr; if (argc != 3) { fprintf(stderr, "Usage: %s <pathname> <vmlinux_load_addr>\n", diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index caae2285816..cad555ebeca 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -1,11 +1,7 @@ -config CAVIUM_OCTEON_SPECIFIC_OPTIONS - bool "Enable Octeon specific options" - depends on CPU_CAVIUM_OCTEON - default "y" +if CPU_CAVIUM_OCTEON config CAVIUM_CN63XXP1 bool "Enable CN63XXP1 errata worarounds" - depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS default "n" help The CN63XXP1 chip requires build time workarounds to @@ -16,7 +12,6 @@ config CAVIUM_CN63XXP1 config CAVIUM_OCTEON_2ND_KERNEL bool "Build the kernel to be used as a 2nd kernel on the same chip" - depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS default "n" help This option configures this kernel to be linked at a different @@ -26,7 +21,6 @@ config CAVIUM_OCTEON_2ND_KERNEL config CAVIUM_OCTEON_HW_FIX_UNALIGNED bool "Enable hardware fixups of unaligned loads and stores" - depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS default "y" help Configure the Octeon hardware to automatically fix unaligned loads @@ -38,7 +32,6 @@ config CAVIUM_OCTEON_HW_FIX_UNALIGNED config CAVIUM_OCTEON_CVMSEG_SIZE int "Number of L1 cache lines reserved for CVMSEG memory" - depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS range 0 54 default 1 help @@ -50,7 +43,6 @@ config CAVIUM_OCTEON_CVMSEG_SIZE config CAVIUM_OCTEON_LOCK_L2 bool "Lock often used kernel code in the L2" - depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS default "y" help Enable locking parts of the kernel into the L2 cache. @@ -93,7 +85,6 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY config ARCH_SPARSEMEM_ENABLE def_bool y select SPARSEMEM_STATIC - depends on CPU_CAVIUM_OCTEON config CAVIUM_OCTEON_HELPER def_bool y @@ -107,6 +98,8 @@ config NEED_SG_DMA_LENGTH config SWIOTLB def_bool y - depends on CPU_CAVIUM_OCTEON select IOMMU_HELPER select NEED_SG_DMA_LENGTH + + +endif # CPU_CAVIUM_OCTEON diff --git a/arch/mips/cavium-octeon/executive/octeon-model.c b/arch/mips/cavium-octeon/executive/octeon-model.c index 9afc3794ed1..c8d35684504 100644 --- a/arch/mips/cavium-octeon/executive/octeon-model.c +++ b/arch/mips/cavium-octeon/executive/octeon-model.c @@ -75,7 +75,7 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer) num_cores = cvmx_octeon_num_cores(); - /* Make sure the non existant devices look disabled */ + /* Make sure the non existent devices look disabled */ switch ((chip_id >> 8) & 0xff) { case 6: /* CN50XX */ case 2: /* CN30XX */ diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index ce7500cdf5b..ffd4ae660f7 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -3,10 +3,13 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks + * Copyright (C) 2004-2008, 2009, 2010, 2011 Cavium Networks */ -#include <linux/irq.h> + #include <linux/interrupt.h> +#include <linux/bitops.h> +#include <linux/percpu.h> +#include <linux/irq.h> #include <linux/smp.h> #include <asm/octeon/octeon.h> @@ -14,6 +17,47 @@ static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock); static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock); +static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu0_en_mirror); +static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu1_en_mirror); + +static __read_mostly u8 octeon_irq_ciu_to_irq[8][64]; + +union octeon_ciu_chip_data { + void *p; + unsigned long l; + struct { + unsigned int line:6; + unsigned int bit:6; + } s; +}; + +struct octeon_core_chip_data { + struct mutex core_irq_mutex; + bool current_en; + bool desired_en; + u8 bit; +}; + +#define MIPS_CORE_IRQ_LINES 8 + +static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES]; + +static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit, + struct irq_chip *chip, + irq_flow_handler_t handler) +{ + union octeon_ciu_chip_data cd; + + irq_set_chip_and_handler(irq, chip, handler); + + cd.l = 0; + cd.s.line = line; + cd.s.bit = bit; + + irq_set_chip_data(irq, cd.p); + octeon_irq_ciu_to_irq[line][bit] = irq; +} + static int octeon_coreid_for_cpu(int cpu) { #ifdef CONFIG_SMP @@ -23,9 +67,20 @@ static int octeon_coreid_for_cpu(int cpu) #endif } -static void octeon_irq_core_ack(unsigned int irq) +static int octeon_cpu_for_coreid(int coreid) +{ +#ifdef CONFIG_SMP + return cpu_number_map(coreid); +#else + return smp_processor_id(); +#endif +} + +static void octeon_irq_core_ack(struct irq_data *data) { - unsigned int bit = irq - OCTEON_IRQ_SW0; + struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); + unsigned int bit = cd->bit; + /* * We don't need to disable IRQs to make these atomic since * they are already disabled earlier in the low level @@ -37,131 +92,121 @@ static void octeon_irq_core_ack(unsigned int irq) clear_c0_cause(0x100 << bit); } -static void octeon_irq_core_eoi(unsigned int irq) +static void octeon_irq_core_eoi(struct irq_data *data) { - struct irq_desc *desc = irq_to_desc(irq); - unsigned int bit = irq - OCTEON_IRQ_SW0; - /* - * If an IRQ is being processed while we are disabling it the - * handler will attempt to unmask the interrupt after it has - * been disabled. - */ - if ((unlikely(desc->status & IRQ_DISABLED))) - return; + struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); + /* * We don't need to disable IRQs to make these atomic since * they are already disabled earlier in the low level * interrupt code. */ - set_c0_status(0x100 << bit); + set_c0_status(0x100 << cd->bit); } -static void octeon_irq_core_enable(unsigned int irq) +static void octeon_irq_core_set_enable_local(void *arg) { - unsigned long flags; - unsigned int bit = irq - OCTEON_IRQ_SW0; + struct irq_data *data = arg; + struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); + unsigned int mask = 0x100 << cd->bit; /* - * We need to disable interrupts to make sure our updates are - * atomic. + * Interrupts are already disabled, so these are atomic. */ - local_irq_save(flags); - set_c0_status(0x100 << bit); - local_irq_restore(flags); + if (cd->desired_en) + set_c0_status(mask); + else + clear_c0_status(mask); + } -static void octeon_irq_core_disable_local(unsigned int irq) +static void octeon_irq_core_disable(struct irq_data *data) { - unsigned long flags; - unsigned int bit = irq - OCTEON_IRQ_SW0; - /* - * We need to disable interrupts to make sure our updates are - * atomic. - */ - local_irq_save(flags); - clear_c0_status(0x100 << bit); - local_irq_restore(flags); + struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); + cd->desired_en = false; } -static void octeon_irq_core_disable(unsigned int irq) +static void octeon_irq_core_enable(struct irq_data *data) { -#ifdef CONFIG_SMP - on_each_cpu((void (*)(void *)) octeon_irq_core_disable_local, - (void *) (long) irq, 1); -#else - octeon_irq_core_disable_local(irq); -#endif + struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); + cd->desired_en = true; } -static struct irq_chip octeon_irq_chip_core = { - .name = "Core", - .enable = octeon_irq_core_enable, - .disable = octeon_irq_core_disable, - .ack = octeon_irq_core_ack, - .eoi = octeon_irq_core_eoi, -}; +static void octeon_irq_core_bus_lock(struct irq_data *data) +{ + struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); + mutex_lock(&cd->core_irq_mutex); +} -static void octeon_irq_ciu0_ack(unsigned int irq) +static void octeon_irq_core_bus_sync_unlock(struct irq_data *data) { - switch (irq) { - case OCTEON_IRQ_GMX_DRP0: - case OCTEON_IRQ_GMX_DRP1: - case OCTEON_IRQ_IPD_DRP: - case OCTEON_IRQ_KEY_ZERO: - case OCTEON_IRQ_TIMER0: - case OCTEON_IRQ_TIMER1: - case OCTEON_IRQ_TIMER2: - case OCTEON_IRQ_TIMER3: - { - int index = cvmx_get_core_num() * 2; - u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); - /* - * CIU timer type interrupts must be acknoleged by - * writing a '1' bit to their sum0 bit. - */ - cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask); - break; - } - default: - break; + struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); + + if (cd->desired_en != cd->current_en) { + on_each_cpu(octeon_irq_core_set_enable_local, data, 1); + + cd->current_en = cd->desired_en; } - /* - * In order to avoid any locking accessing the CIU, we - * acknowledge CIU interrupts by disabling all of them. This - * way we can use a per core register and avoid any out of - * core locking requirements. This has the side affect that - * CIU interrupts can't be processed recursively. - * - * We don't need to disable IRQs to make these atomic since - * they are already disabled earlier in the low level - * interrupt code. - */ - clear_c0_status(0x100 << 2); + mutex_unlock(&cd->core_irq_mutex); } -static void octeon_irq_ciu0_eoi(unsigned int irq) +static struct irq_chip octeon_irq_chip_core = { + .name = "Core", + .irq_enable = octeon_irq_core_enable, + .irq_disable = octeon_irq_core_disable, + .irq_ack = octeon_irq_core_ack, + .irq_eoi = octeon_irq_core_eoi, + .irq_bus_lock = octeon_irq_core_bus_lock, + .irq_bus_sync_unlock = octeon_irq_core_bus_sync_unlock, + + .irq_cpu_online = octeon_irq_core_eoi, + .irq_cpu_offline = octeon_irq_core_ack, + .flags = IRQCHIP_ONOFFLINE_ENABLED, +}; + +static void __init octeon_irq_init_core(void) { - /* - * Enable all CIU interrupts again. We don't need to disable - * IRQs to make these atomic since they are already disabled - * earlier in the low level interrupt code. - */ - set_c0_status(0x100 << 2); + int i; + int irq; + struct octeon_core_chip_data *cd; + + for (i = 0; i < MIPS_CORE_IRQ_LINES; i++) { + cd = &octeon_irq_core_chip_data[i]; + cd->current_en = false; + cd->desired_en = false; + cd->bit = i; + mutex_init(&cd->core_irq_mutex); + + irq = OCTEON_IRQ_SW0 + i; + switch (irq) { + case OCTEON_IRQ_TIMER: + case OCTEON_IRQ_SW0: + case OCTEON_IRQ_SW1: + case OCTEON_IRQ_5: + case OCTEON_IRQ_PERF: + irq_set_chip_data(irq, cd); + irq_set_chip_and_handler(irq, &octeon_irq_chip_core, + handle_percpu_irq); + break; + default: + break; + } + } } -static int next_coreid_for_irq(struct irq_desc *desc) +static int next_cpu_for_irq(struct irq_data *data) { #ifdef CONFIG_SMP - int coreid; - int weight = cpumask_weight(desc->affinity); + int cpu; + int weight = cpumask_weight(data->affinity); if (weight > 1) { - int cpu = smp_processor_id(); + cpu = smp_processor_id(); for (;;) { - cpu = cpumask_next(cpu, desc->affinity); + cpu = cpumask_next(cpu, data->affinity); if (cpu >= nr_cpu_ids) { cpu = -1; continue; @@ -169,83 +214,175 @@ static int next_coreid_for_irq(struct irq_desc *desc) break; } } - coreid = octeon_coreid_for_cpu(cpu); } else if (weight == 1) { - coreid = octeon_coreid_for_cpu(cpumask_first(desc->affinity)); + cpu = cpumask_first(data->affinity); } else { - coreid = cvmx_get_core_num(); + cpu = smp_processor_id(); } - return coreid; + return cpu; #else - return cvmx_get_core_num(); + return smp_processor_id(); #endif } -static void octeon_irq_ciu0_enable(unsigned int irq) +static void octeon_irq_ciu_enable(struct irq_data *data) { - struct irq_desc *desc = irq_to_desc(irq); - int coreid = next_coreid_for_irq(desc); + int cpu = next_cpu_for_irq(data); + int coreid = octeon_coreid_for_cpu(cpu); + unsigned long *pen; unsigned long flags; - uint64_t en0; - int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ + union octeon_ciu_chip_data cd; + + cd.p = irq_data_get_irq_chip_data(data); - raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); - en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - en0 |= 1ull << bit; - cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); - cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); + if (cd.s.line == 0) { + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); + pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); + set_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); + } else { + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); + pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); + set_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); + } } -static void octeon_irq_ciu0_enable_mbox(unsigned int irq) +static void octeon_irq_ciu_enable_local(struct irq_data *data) { - int coreid = cvmx_get_core_num(); + unsigned long *pen; + unsigned long flags; + union octeon_ciu_chip_data cd; + + cd.p = irq_data_get_irq_chip_data(data); + + if (cd.s.line == 0) { + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); + pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror); + set_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); + } else { + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); + pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror); + set_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); + } +} + +static void octeon_irq_ciu_disable_local(struct irq_data *data) +{ + unsigned long *pen; unsigned long flags; - uint64_t en0; - int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ + union octeon_ciu_chip_data cd; + + cd.p = irq_data_get_irq_chip_data(data); - raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); - en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - en0 |= 1ull << bit; - cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); - cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); + if (cd.s.line == 0) { + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); + pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror); + clear_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); + } else { + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); + pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror); + clear_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); + } } -static void octeon_irq_ciu0_disable(unsigned int irq) +static void octeon_irq_ciu_disable_all(struct irq_data *data) { - int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ unsigned long flags; - uint64_t en0; + unsigned long *pen; int cpu; - raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); - for_each_online_cpu(cpu) { - int coreid = octeon_coreid_for_cpu(cpu); - en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - en0 &= ~(1ull << bit); - cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); + union octeon_ciu_chip_data cd; + + wmb(); /* Make sure flag changes arrive before register updates. */ + + cd.p = irq_data_get_irq_chip_data(data); + + if (cd.s.line == 0) { + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); + pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); + clear_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); + } + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); + } else { + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); + pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); + clear_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); + } + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); + } +} + +static void octeon_irq_ciu_enable_all(struct irq_data *data) +{ + unsigned long flags; + unsigned long *pen; + int cpu; + union octeon_ciu_chip_data cd; + + cd.p = irq_data_get_irq_chip_data(data); + + if (cd.s.line == 0) { + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); + pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); + set_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); + } + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); + } else { + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); + pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); + set_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); + } + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); } - /* - * We need to do a read after the last update to make sure all - * of them are done. - */ - cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); - raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); } /* * Enable the irq on the next core in the affinity set for chips that * have the EN*_W1{S,C} registers. */ -static void octeon_irq_ciu0_enable_v2(unsigned int irq) +static void octeon_irq_ciu_enable_v2(struct irq_data *data) { - int index; - u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); - struct irq_desc *desc = irq_to_desc(irq); + u64 mask; + int cpu = next_cpu_for_irq(data); + union octeon_ciu_chip_data cd; + + cd.p = irq_data_get_irq_chip_data(data); + mask = 1ull << (cd.s.bit); - if ((desc->status & IRQ_DISABLED) == 0) { - index = next_coreid_for_irq(desc) * 2; + /* + * Called under the desc lock, so these should never get out + * of sync. + */ + if (cd.s.line == 0) { + int index = octeon_coreid_for_cpu(cpu) * 2; + set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu)); cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); + } else { + int index = octeon_coreid_for_cpu(cpu) * 2 + 1; + set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); } } @@ -253,83 +390,155 @@ static void octeon_irq_ciu0_enable_v2(unsigned int irq) * Enable the irq on the current CPU for chips that * have the EN*_W1{S,C} registers. */ -static void octeon_irq_ciu0_enable_mbox_v2(unsigned int irq) +static void octeon_irq_ciu_enable_local_v2(struct irq_data *data) +{ + u64 mask; + union octeon_ciu_chip_data cd; + + cd.p = irq_data_get_irq_chip_data(data); + mask = 1ull << (cd.s.bit); + + if (cd.s.line == 0) { + int index = cvmx_get_core_num() * 2; + set_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu0_en_mirror)); + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); + } else { + int index = cvmx_get_core_num() * 2 + 1; + set_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu1_en_mirror)); + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); + } +} + +static void octeon_irq_ciu_disable_local_v2(struct irq_data *data) { - int index; - u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); + u64 mask; + union octeon_ciu_chip_data cd; - index = cvmx_get_core_num() * 2; - cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); + cd.p = irq_data_get_irq_chip_data(data); + mask = 1ull << (cd.s.bit); + + if (cd.s.line == 0) { + int index = cvmx_get_core_num() * 2; + clear_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu0_en_mirror)); + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); + } else { + int index = cvmx_get_core_num() * 2 + 1; + clear_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu1_en_mirror)); + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); + } } /* - * Disable the irq on the current core for chips that have the EN*_W1{S,C} - * registers. + * Write to the W1C bit in CVMX_CIU_INTX_SUM0 to clear the irq. */ -static void octeon_irq_ciu0_ack_v2(unsigned int irq) -{ - int index = cvmx_get_core_num() * 2; - u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); - - switch (irq) { - case OCTEON_IRQ_GMX_DRP0: - case OCTEON_IRQ_GMX_DRP1: - case OCTEON_IRQ_IPD_DRP: - case OCTEON_IRQ_KEY_ZERO: - case OCTEON_IRQ_TIMER0: - case OCTEON_IRQ_TIMER1: - case OCTEON_IRQ_TIMER2: - case OCTEON_IRQ_TIMER3: - /* - * CIU timer type interrupts must be acknoleged by - * writing a '1' bit to their sum0 bit. - */ +static void octeon_irq_ciu_ack(struct irq_data *data) +{ + u64 mask; + union octeon_ciu_chip_data cd; + + cd.p = data->chip_data; + mask = 1ull << (cd.s.bit); + + if (cd.s.line == 0) { + int index = cvmx_get_core_num() * 2; cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask); - break; - default: - break; + } else { + cvmx_write_csr(CVMX_CIU_INT_SUM1, mask); } - - cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); } /* - * Enable the irq on the current core for chips that have the EN*_W1{S,C} + * Disable the irq on the all cores for chips that have the EN*_W1{S,C} * registers. */ -static void octeon_irq_ciu0_eoi_mbox_v2(unsigned int irq) +static void octeon_irq_ciu_disable_all_v2(struct irq_data *data) { - struct irq_desc *desc = irq_to_desc(irq); - int index = cvmx_get_core_num() * 2; - u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); + int cpu; + u64 mask; + union octeon_ciu_chip_data cd; - if (likely((desc->status & IRQ_DISABLED) == 0)) - cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); + wmb(); /* Make sure flag changes arrive before register updates. */ + + cd.p = data->chip_data; + mask = 1ull << (cd.s.bit); + + if (cd.s.line == 0) { + for_each_online_cpu(cpu) { + int index = octeon_coreid_for_cpu(cpu) * 2; + clear_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu)); + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); + } + } else { + for_each_online_cpu(cpu) { + int index = octeon_coreid_for_cpu(cpu) * 2 + 1; + clear_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); + } + } } /* - * Disable the irq on the all cores for chips that have the EN*_W1{S,C} + * Enable the irq on the all cores for chips that have the EN*_W1{S,C} * registers. */ -static void octeon_irq_ciu0_disable_all_v2(unsigned int irq) +static void octeon_irq_ciu_enable_all_v2(struct irq_data *data) { - u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); - int index; int cpu; - for_each_online_cpu(cpu) { - index = octeon_coreid_for_cpu(cpu) * 2; - cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); + u64 mask; + union octeon_ciu_chip_data cd; + + cd.p = data->chip_data; + mask = 1ull << (cd.s.bit); + + if (cd.s.line == 0) { + for_each_online_cpu(cpu) { + int index = octeon_coreid_for_cpu(cpu) * 2; + set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu)); + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); + } + } else { + for_each_online_cpu(cpu) { + int index = octeon_coreid_for_cpu(cpu) * 2 + 1; + set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); + } } } #ifdef CONFIG_SMP -static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest) + +static void octeon_irq_cpu_offline_ciu(struct irq_data *data) +{ + int cpu = smp_processor_id(); + cpumask_t new_affinity; + + if (!cpumask_test_cpu(cpu, data->affinity)) + return; + + if (cpumask_weight(data->affinity) > 1) { + /* + * It has multi CPU affinity, just remove this CPU + * from the affinity set. + */ + cpumask_copy(&new_affinity, data->affinity); + cpumask_clear_cpu(cpu, &new_affinity); + } else { + /* Otherwise, put it on lowest numbered online CPU. */ + cpumask_clear(&new_affinity); + cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity); + } + __irq_set_affinity_locked(data, &new_affinity); +} + +static int octeon_irq_ciu_set_affinity(struct irq_data *data, + const struct cpumask *dest, bool force) { int cpu; - struct irq_desc *desc = irq_to_desc(irq); - int enable_one = (desc->status & IRQ_DISABLED) == 0; + bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data); unsigned long flags; - int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ + union octeon_ciu_chip_data cd; + + cd.p = data->chip_data; /* * For non-v2 CIU, we will allow only single CPU affinity. @@ -339,26 +548,40 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask * if (cpumask_weight(dest) != 1) return -EINVAL; - raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); - for_each_online_cpu(cpu) { - int coreid = octeon_coreid_for_cpu(cpu); - uint64_t en0 = - cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - if (cpumask_test_cpu(cpu, dest) && enable_one) { - enable_one = 0; - en0 |= 1ull << bit; - } else { - en0 &= ~(1ull << bit); + if (!enable_one) + return 0; + + if (cd.s.line == 0) { + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); + unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); + + if (cpumask_test_cpu(cpu, dest) && enable_one) { + enable_one = false; + set_bit(cd.s.bit, pen); + } else { + clear_bit(cd.s.bit, pen); + } + cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); } - cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); + } else { + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); + unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); + + if (cpumask_test_cpu(cpu, dest) && enable_one) { + enable_one = false; + set_bit(cd.s.bit, pen); + } else { + clear_bit(cd.s.bit, pen); + } + cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); + } + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); } - /* - * We need to do a read after the last update to make sure all - * of them are done. - */ - cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); - raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); - return 0; } @@ -366,22 +589,46 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask * * Set affinity for the irq for chips that have the EN*_W1{S,C} * registers. */ -static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq, - const struct cpumask *dest) +static int octeon_irq_ciu_set_affinity_v2(struct irq_data *data, + const struct cpumask *dest, + bool force) { int cpu; - int index; - struct irq_desc *desc = irq_to_desc(irq); - int enable_one = (desc->status & IRQ_DISABLED) == 0; - u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); - - for_each_online_cpu(cpu) { - index = octeon_coreid_for_cpu(cpu) * 2; - if (cpumask_test_cpu(cpu, dest) && enable_one) { - enable_one = 0; - cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); - } else { - cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); + bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data); + u64 mask; + union octeon_ciu_chip_data cd; + + if (!enable_one) + return 0; + + cd.p = data->chip_data; + mask = 1ull << cd.s.bit; + + if (cd.s.line == 0) { + for_each_online_cpu(cpu) { + unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); + int index = octeon_coreid_for_cpu(cpu) * 2; + if (cpumask_test_cpu(cpu, dest) && enable_one) { + enable_one = false; + set_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); + } else { + clear_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); + } + } + } else { + for_each_online_cpu(cpu) { + unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); + int index = octeon_coreid_for_cpu(cpu) * 2 + 1; + if (cpumask_test_cpu(cpu, dest) && enable_one) { + enable_one = false; + set_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); + } else { + clear_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); + } } } return 0; @@ -389,80 +636,102 @@ static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq, #endif /* + * The v1 CIU code already masks things, so supply a dummy version to + * the core chip code. + */ +static void octeon_irq_dummy_mask(struct irq_data *data) +{ +} + +/* * Newer octeon chips have support for lockless CIU operation. */ -static struct irq_chip octeon_irq_chip_ciu0_v2 = { - .name = "CIU0", - .enable = octeon_irq_ciu0_enable_v2, - .disable = octeon_irq_ciu0_disable_all_v2, - .eoi = octeon_irq_ciu0_enable_v2, +static struct irq_chip octeon_irq_chip_ciu_v2 = { + .name = "CIU", + .irq_enable = octeon_irq_ciu_enable_v2, + .irq_disable = octeon_irq_ciu_disable_all_v2, + .irq_mask = octeon_irq_ciu_disable_local_v2, + .irq_unmask = octeon_irq_ciu_enable_v2, #ifdef CONFIG_SMP - .set_affinity = octeon_irq_ciu0_set_affinity_v2, + .irq_set_affinity = octeon_irq_ciu_set_affinity_v2, + .irq_cpu_offline = octeon_irq_cpu_offline_ciu, #endif }; -static struct irq_chip octeon_irq_chip_ciu0 = { - .name = "CIU0", - .enable = octeon_irq_ciu0_enable, - .disable = octeon_irq_ciu0_disable, - .eoi = octeon_irq_ciu0_eoi, +static struct irq_chip octeon_irq_chip_ciu_edge_v2 = { + .name = "CIU-E", + .irq_enable = octeon_irq_ciu_enable_v2, + .irq_disable = octeon_irq_ciu_disable_all_v2, + .irq_ack = octeon_irq_ciu_ack, + .irq_mask = octeon_irq_ciu_disable_local_v2, + .irq_unmask = octeon_irq_ciu_enable_v2, #ifdef CONFIG_SMP - .set_affinity = octeon_irq_ciu0_set_affinity, + .irq_set_affinity = octeon_irq_ciu_set_affinity_v2, + .irq_cpu_offline = octeon_irq_cpu_offline_ciu, #endif }; -/* The mbox versions don't do any affinity or round-robin. */ -static struct irq_chip octeon_irq_chip_ciu0_mbox_v2 = { - .name = "CIU0-M", - .enable = octeon_irq_ciu0_enable_mbox_v2, - .disable = octeon_irq_ciu0_disable, - .eoi = octeon_irq_ciu0_eoi_mbox_v2, +static struct irq_chip octeon_irq_chip_ciu = { + .name = "CIU", + .irq_enable = octeon_irq_ciu_enable, + .irq_disable = octeon_irq_ciu_disable_all, + .irq_mask = octeon_irq_dummy_mask, +#ifdef CONFIG_SMP + .irq_set_affinity = octeon_irq_ciu_set_affinity, + .irq_cpu_offline = octeon_irq_cpu_offline_ciu, +#endif }; -static struct irq_chip octeon_irq_chip_ciu0_mbox = { - .name = "CIU0-M", - .enable = octeon_irq_ciu0_enable_mbox, - .disable = octeon_irq_ciu0_disable, - .eoi = octeon_irq_ciu0_eoi, +static struct irq_chip octeon_irq_chip_ciu_edge = { + .name = "CIU-E", + .irq_enable = octeon_irq_ciu_enable, + .irq_disable = octeon_irq_ciu_disable_all, + .irq_mask = octeon_irq_dummy_mask, + .irq_ack = octeon_irq_ciu_ack, +#ifdef CONFIG_SMP + .irq_set_affinity = octeon_irq_ciu_set_affinity, + .irq_cpu_offline = octeon_irq_cpu_offline_ciu, +#endif }; -static void octeon_irq_ciu1_ack(unsigned int irq) -{ - /* - * In order to avoid any locking accessing the CIU, we - * acknowledge CIU interrupts by disabling all of them. This - * way we can use a per core register and avoid any out of - * core locking requirements. This has the side affect that - * CIU interrupts can't be processed recursively. We don't - * need to disable IRQs to make these atomic since they are - * already disabled earlier in the low level interrupt code. - */ - clear_c0_status(0x100 << 3); -} +/* The mbox versions don't do any affinity or round-robin. */ +static struct irq_chip octeon_irq_chip_ciu_mbox_v2 = { + .name = "CIU-M", + .irq_enable = octeon_irq_ciu_enable_all_v2, + .irq_disable = octeon_irq_ciu_disable_all_v2, + .irq_ack = octeon_irq_ciu_disable_local_v2, + .irq_eoi = octeon_irq_ciu_enable_local_v2, + + .irq_cpu_online = octeon_irq_ciu_enable_local_v2, + .irq_cpu_offline = octeon_irq_ciu_disable_local_v2, + .flags = IRQCHIP_ONOFFLINE_ENABLED, +}; -static void octeon_irq_ciu1_eoi(unsigned int irq) -{ - /* - * Enable all CIU interrupts again. We don't need to disable - * IRQs to make these atomic since they are already disabled - * earlier in the low level interrupt code. - */ - set_c0_status(0x100 << 3); -} +static struct irq_chip octeon_irq_chip_ciu_mbox = { + .name = "CIU-M", + .irq_enable = octeon_irq_ciu_enable_all, + .irq_disable = octeon_irq_ciu_disable_all, + + .irq_cpu_online = octeon_irq_ciu_enable_local, + .irq_cpu_offline = octeon_irq_ciu_disable_local, + .flags = IRQCHIP_ONOFFLINE_ENABLED, +}; -static void octeon_irq_ciu1_enable(unsigned int irq) +/* + * Watchdog interrupts are special. They are associated with a single + * core, so we hardwire the affinity to that core. + */ +static void octeon_irq_ciu_wd_enable(struct irq_data *data) { - struct irq_desc *desc = irq_to_desc(irq); - int coreid = next_coreid_for_irq(desc); unsigned long flags; - uint64_t en1; - int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ + unsigned long *pen; + int coreid = data->irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ + int cpu = octeon_cpu_for_coreid(coreid); raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); - en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); - en1 |= 1ull << bit; - cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); - cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); + pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); + set_bit(coreid, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); } @@ -470,286 +739,281 @@ static void octeon_irq_ciu1_enable(unsigned int irq) * Watchdog interrupts are special. They are associated with a single * core, so we hardwire the affinity to that core. */ -static void octeon_irq_ciu1_wd_enable(unsigned int irq) +static void octeon_irq_ciu1_wd_enable_v2(struct irq_data *data) { - unsigned long flags; - uint64_t en1; - int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ - int coreid = bit; + int coreid = data->irq - OCTEON_IRQ_WDOG0; + int cpu = octeon_cpu_for_coreid(coreid); - raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); - en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); - en1 |= 1ull << bit; - cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); - cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); - raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); + set_bit(coreid, &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(coreid * 2 + 1), 1ull << coreid); } -static void octeon_irq_ciu1_disable(unsigned int irq) + +static struct irq_chip octeon_irq_chip_ciu_wd_v2 = { + .name = "CIU-W", + .irq_enable = octeon_irq_ciu1_wd_enable_v2, + .irq_disable = octeon_irq_ciu_disable_all_v2, + .irq_mask = octeon_irq_ciu_disable_local_v2, + .irq_unmask = octeon_irq_ciu_enable_local_v2, +}; + +static struct irq_chip octeon_irq_chip_ciu_wd = { + .name = "CIU-W", + .irq_enable = octeon_irq_ciu_wd_enable, + .irq_disable = octeon_irq_ciu_disable_all, + .irq_mask = octeon_irq_dummy_mask, +}; + +static void octeon_irq_ip2_v1(void) { - int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ - unsigned long flags; - uint64_t en1; - int cpu; - raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); - for_each_online_cpu(cpu) { - int coreid = octeon_coreid_for_cpu(cpu); - en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); - en1 &= ~(1ull << bit); - cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); + const unsigned long core_id = cvmx_get_core_num(); + u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2)); + + ciu_sum &= __get_cpu_var(octeon_irq_ciu0_en_mirror); + clear_c0_status(STATUSF_IP2); + if (likely(ciu_sum)) { + int bit = fls64(ciu_sum) - 1; + int irq = octeon_irq_ciu_to_irq[0][bit]; + if (likely(irq)) + do_IRQ(irq); + else + spurious_interrupt(); + } else { + spurious_interrupt(); } - /* - * We need to do a read after the last update to make sure all - * of them are done. - */ - cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); - raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); + set_c0_status(STATUSF_IP2); } -/* - * Enable the irq on the current core for chips that have the EN*_W1{S,C} - * registers. - */ -static void octeon_irq_ciu1_enable_v2(unsigned int irq) +static void octeon_irq_ip2_v2(void) { - int index; - u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); - struct irq_desc *desc = irq_to_desc(irq); - - if ((desc->status & IRQ_DISABLED) == 0) { - index = next_coreid_for_irq(desc) * 2 + 1; - cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); + const unsigned long core_id = cvmx_get_core_num(); + u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2)); + + ciu_sum &= __get_cpu_var(octeon_irq_ciu0_en_mirror); + if (likely(ciu_sum)) { + int bit = fls64(ciu_sum) - 1; + int irq = octeon_irq_ciu_to_irq[0][bit]; + if (likely(irq)) + do_IRQ(irq); + else + spurious_interrupt(); + } else { + spurious_interrupt(); } } - -/* - * Watchdog interrupts are special. They are associated with a single - * core, so we hardwire the affinity to that core. - */ -static void octeon_irq_ciu1_wd_enable_v2(unsigned int irq) +static void octeon_irq_ip3_v1(void) { - int index; - int coreid = irq - OCTEON_IRQ_WDOG0; - u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); - struct irq_desc *desc = irq_to_desc(irq); - - if ((desc->status & IRQ_DISABLED) == 0) { - index = coreid * 2 + 1; - cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); + u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1); + + ciu_sum &= __get_cpu_var(octeon_irq_ciu1_en_mirror); + clear_c0_status(STATUSF_IP3); + if (likely(ciu_sum)) { + int bit = fls64(ciu_sum) - 1; + int irq = octeon_irq_ciu_to_irq[1][bit]; + if (likely(irq)) + do_IRQ(irq); + else + spurious_interrupt(); + } else { + spurious_interrupt(); } + set_c0_status(STATUSF_IP3); } -/* - * Disable the irq on the current core for chips that have the EN*_W1{S,C} - * registers. - */ -static void octeon_irq_ciu1_ack_v2(unsigned int irq) +static void octeon_irq_ip3_v2(void) { - int index = cvmx_get_core_num() * 2 + 1; - u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); - - cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); + u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1); + + ciu_sum &= __get_cpu_var(octeon_irq_ciu1_en_mirror); + if (likely(ciu_sum)) { + int bit = fls64(ciu_sum) - 1; + int irq = octeon_irq_ciu_to_irq[1][bit]; + if (likely(irq)) + do_IRQ(irq); + else + spurious_interrupt(); + } else { + spurious_interrupt(); + } } -/* - * Disable the irq on the all cores for chips that have the EN*_W1{S,C} - * registers. - */ -static void octeon_irq_ciu1_disable_all_v2(unsigned int irq) +static void octeon_irq_ip4_mask(void) { - u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); - int index; - int cpu; - for_each_online_cpu(cpu) { - index = octeon_coreid_for_cpu(cpu) * 2 + 1; - cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); - } + clear_c0_status(STATUSF_IP4); + spurious_interrupt(); } -#ifdef CONFIG_SMP -static int octeon_irq_ciu1_set_affinity(unsigned int irq, - const struct cpumask *dest) -{ - int cpu; - struct irq_desc *desc = irq_to_desc(irq); - int enable_one = (desc->status & IRQ_DISABLED) == 0; - unsigned long flags; - int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ +static void (*octeon_irq_ip2)(void); +static void (*octeon_irq_ip3)(void); +static void (*octeon_irq_ip4)(void); - /* - * For non-v2 CIU, we will allow only single CPU affinity. - * This removes the need to do locking in the .ack/.eoi - * functions. - */ - if (cpumask_weight(dest) != 1) - return -EINVAL; +void __cpuinitdata (*octeon_irq_setup_secondary)(void); - raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); - for_each_online_cpu(cpu) { - int coreid = octeon_coreid_for_cpu(cpu); - uint64_t en1 = - cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); - if (cpumask_test_cpu(cpu, dest) && enable_one) { - enable_one = 0; - en1 |= 1ull << bit; - } else { - en1 &= ~(1ull << bit); - } - cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); - } +static void __cpuinit octeon_irq_percpu_enable(void) +{ + irq_cpu_online(); +} + +static void __cpuinit octeon_irq_init_ciu_percpu(void) +{ + int coreid = cvmx_get_core_num(); /* - * We need to do a read after the last update to make sure all - * of them are done. + * Disable All CIU Interrupts. The ones we need will be + * enabled later. Read the SUM register so we know the write + * completed. */ - cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); - raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); - - return 0; + cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0); + cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); + cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); + cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); + cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2))); } -/* - * Set affinity for the irq for chips that have the EN*_W1{S,C} - * registers. - */ -static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq, - const struct cpumask *dest) +static void __cpuinit octeon_irq_setup_secondary_ciu(void) { - int cpu; - int index; - struct irq_desc *desc = irq_to_desc(irq); - int enable_one = (desc->status & IRQ_DISABLED) == 0; - u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); - for_each_online_cpu(cpu) { - index = octeon_coreid_for_cpu(cpu) * 2 + 1; - if (cpumask_test_cpu(cpu, dest) && enable_one) { - enable_one = 0; - cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); - } else { - cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); - } - } - return 0; -} -#endif -/* - * Newer octeon chips have support for lockless CIU operation. - */ -static struct irq_chip octeon_irq_chip_ciu1_v2 = { - .name = "CIU1", - .enable = octeon_irq_ciu1_enable_v2, - .disable = octeon_irq_ciu1_disable_all_v2, - .eoi = octeon_irq_ciu1_enable_v2, -#ifdef CONFIG_SMP - .set_affinity = octeon_irq_ciu1_set_affinity_v2, -#endif -}; + __get_cpu_var(octeon_irq_ciu0_en_mirror) = 0; + __get_cpu_var(octeon_irq_ciu1_en_mirror) = 0; -static struct irq_chip octeon_irq_chip_ciu1 = { - .name = "CIU1", - .enable = octeon_irq_ciu1_enable, - .disable = octeon_irq_ciu1_disable, - .eoi = octeon_irq_ciu1_eoi, -#ifdef CONFIG_SMP - .set_affinity = octeon_irq_ciu1_set_affinity, -#endif -}; + octeon_irq_init_ciu_percpu(); + octeon_irq_percpu_enable(); -static struct irq_chip octeon_irq_chip_ciu1_wd_v2 = { - .name = "CIU1-W", - .enable = octeon_irq_ciu1_wd_enable_v2, - .disable = octeon_irq_ciu1_disable_all_v2, - .eoi = octeon_irq_ciu1_wd_enable_v2, -}; + /* Enable the CIU lines */ + set_c0_status(STATUSF_IP3 | STATUSF_IP2); + clear_c0_status(STATUSF_IP4); +} -static struct irq_chip octeon_irq_chip_ciu1_wd = { - .name = "CIU1-W", - .enable = octeon_irq_ciu1_wd_enable, - .disable = octeon_irq_ciu1_disable, - .eoi = octeon_irq_ciu1_eoi, -}; +static void __init octeon_irq_init_ciu(void) +{ + unsigned int i; + struct irq_chip *chip; + struct irq_chip *chip_edge; + struct irq_chip *chip_mbox; + struct irq_chip *chip_wd; + + octeon_irq_init_ciu_percpu(); + octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; -static void (*octeon_ciu0_ack)(unsigned int); -static void (*octeon_ciu1_ack)(unsigned int); + if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) || + OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) || + OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) || + OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + octeon_irq_ip2 = octeon_irq_ip2_v2; + octeon_irq_ip3 = octeon_irq_ip3_v2; + chip = &octeon_irq_chip_ciu_v2; + chip_edge = &octeon_irq_chip_ciu_edge_v2; + chip_mbox = &octeon_irq_chip_ciu_mbox_v2; + chip_wd = &octeon_irq_chip_ciu_wd_v2; + } else { + octeon_irq_ip2 = octeon_irq_ip2_v1; + octeon_irq_ip3 = octeon_irq_ip3_v1; + chip = &octeon_irq_chip_ciu; + chip_edge = &octeon_irq_chip_ciu_edge; + chip_mbox = &octeon_irq_chip_ciu_mbox; + chip_wd = &octeon_irq_chip_ciu_wd; + } + octeon_irq_ip4 = octeon_irq_ip4_mask; + + /* Mips internal */ + octeon_irq_init_core(); + + /* CIU_0 */ + for (i = 0; i < 16; i++) + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq); + for (i = 0; i < 16; i++) + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip, handle_level_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART0, 0, 34, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART1, 0, 35, chip, handle_level_irq); + + for (i = 0; i < 4; i++) + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, chip, handle_level_irq); + for (i = 0; i < 4; i++) + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, chip, handle_level_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI, 0, 45, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TRACE0, 0, 47, chip, handle_level_irq); + + for (i = 0; i < 2; i++) + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GMX_DRP0, 0, i + 48, chip_edge, handle_edge_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD_DRP, 0, 50, chip_edge, handle_edge_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY_ZERO, 0, 51, chip_edge, handle_edge_irq); + + for (i = 0; i < 4; i++) + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip_edge, handle_edge_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PCM, 0, 57, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MPI, 0, 58, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI2, 0, 59, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_POWIQ, 0, 60, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPDPPTHR, 0, 61, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII0, 0, 62, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq); + + /* CIU_1 */ + for (i = 0; i < 16; i++) + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART2, 1, 16, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII1, 1, 18, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_NAND, 1, 19, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MIO, 1, 20, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IOB, 1, 21, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_FPA, 1, 22, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_POW, 1, 23, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_L2C, 1, 24, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD, 1, 25, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PIP, 1, 26, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PKO, 1, 27, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_ZIP, 1, 28, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TIM, 1, 29, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RAD, 1, 30, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY, 1, 31, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFA, 1, 32, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_USBCTL, 1, 33, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SLI, 1, 34, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DPI, 1, 35, chip, handle_level_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGX0, 1, 36, chip, handle_level_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGL, 1, 46, chip, handle_level_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PTP, 1, 47, chip_edge, handle_edge_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM0, 1, 48, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM1, 1, 49, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO0, 1, 50, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO1, 1, 51, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_LMC0, 1, 52, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFM, 1, 56, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RST, 1, 63, chip, handle_level_irq); + + /* Enable the CIU lines */ + set_c0_status(STATUSF_IP3 | STATUSF_IP2); + clear_c0_status(STATUSF_IP4); +} void __init arch_init_irq(void) { - unsigned int irq; - struct irq_chip *chip0; - struct irq_chip *chip0_mbox; - struct irq_chip *chip1; - struct irq_chip *chip1_wd; - #ifdef CONFIG_SMP /* Set the default affinity to the boot cpu. */ cpumask_clear(irq_default_affinity); cpumask_set_cpu(smp_processor_id(), irq_default_affinity); #endif - - if (NR_IRQS < OCTEON_IRQ_LAST) - pr_err("octeon_irq_init: NR_IRQS is set too low\n"); - - if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) || - OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) || - OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) { - octeon_ciu0_ack = octeon_irq_ciu0_ack_v2; - octeon_ciu1_ack = octeon_irq_ciu1_ack_v2; - chip0 = &octeon_irq_chip_ciu0_v2; - chip0_mbox = &octeon_irq_chip_ciu0_mbox_v2; - chip1 = &octeon_irq_chip_ciu1_v2; - chip1_wd = &octeon_irq_chip_ciu1_wd_v2; - } else { - octeon_ciu0_ack = octeon_irq_ciu0_ack; - octeon_ciu1_ack = octeon_irq_ciu1_ack; - chip0 = &octeon_irq_chip_ciu0; - chip0_mbox = &octeon_irq_chip_ciu0_mbox; - chip1 = &octeon_irq_chip_ciu1; - chip1_wd = &octeon_irq_chip_ciu1_wd; - } - - /* 0 - 15 reserved for i8259 master and slave controller. */ - - /* 17 - 23 Mips internal */ - for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) { - set_irq_chip_and_handler(irq, &octeon_irq_chip_core, - handle_percpu_irq); - } - - /* 24 - 87 CIU_INT_SUM0 */ - for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) { - switch (irq) { - case OCTEON_IRQ_MBOX0: - case OCTEON_IRQ_MBOX1: - set_irq_chip_and_handler(irq, chip0_mbox, handle_percpu_irq); - break; - default: - set_irq_chip_and_handler(irq, chip0, handle_fasteoi_irq); - break; - } - } - - /* 88 - 151 CIU_INT_SUM1 */ - for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_WDOG15; irq++) - set_irq_chip_and_handler(irq, chip1_wd, handle_fasteoi_irq); - - for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED151; irq++) - set_irq_chip_and_handler(irq, chip1, handle_fasteoi_irq); - - set_c0_status(0x300 << 2); + octeon_irq_init_ciu(); } asmlinkage void plat_irq_dispatch(void) { - const unsigned long core_id = cvmx_get_core_num(); - const uint64_t ciu_sum0_address = CVMX_CIU_INTX_SUM0(core_id * 2); - const uint64_t ciu_en0_address = CVMX_CIU_INTX_EN0(core_id * 2); - const uint64_t ciu_sum1_address = CVMX_CIU_INT_SUM1; - const uint64_t ciu_en1_address = CVMX_CIU_INTX_EN1(core_id * 2 + 1); unsigned long cop0_cause; unsigned long cop0_status; - uint64_t ciu_en; - uint64_t ciu_sum; - unsigned int irq; while (1) { cop0_cause = read_c0_cause(); @@ -757,33 +1021,16 @@ asmlinkage void plat_irq_dispatch(void) cop0_cause &= cop0_status; cop0_cause &= ST0_IM; - if (unlikely(cop0_cause & STATUSF_IP2)) { - ciu_sum = cvmx_read_csr(ciu_sum0_address); - ciu_en = cvmx_read_csr(ciu_en0_address); - ciu_sum &= ciu_en; - if (likely(ciu_sum)) { - irq = fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1; - octeon_ciu0_ack(irq); - do_IRQ(irq); - } else { - spurious_interrupt(); - } - } else if (unlikely(cop0_cause & STATUSF_IP3)) { - ciu_sum = cvmx_read_csr(ciu_sum1_address); - ciu_en = cvmx_read_csr(ciu_en1_address); - ciu_sum &= ciu_en; - if (likely(ciu_sum)) { - irq = fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1; - octeon_ciu1_ack(irq); - do_IRQ(irq); - } else { - spurious_interrupt(); - } - } else if (likely(cop0_cause)) { + if (unlikely(cop0_cause & STATUSF_IP2)) + octeon_irq_ip2(); + else if (unlikely(cop0_cause & STATUSF_IP3)) + octeon_irq_ip3(); + else if (unlikely(cop0_cause & STATUSF_IP4)) + octeon_irq_ip4(); + else if (likely(cop0_cause)) do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE); - } else { + else break; - } } } @@ -791,83 +1038,7 @@ asmlinkage void plat_irq_dispatch(void) void fixup_irqs(void) { - int irq; - struct irq_desc *desc; - cpumask_t new_affinity; - unsigned long flags; - int do_set_affinity; - int cpu; - - cpu = smp_processor_id(); - - for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) - octeon_irq_core_disable_local(irq); - - for (irq = OCTEON_IRQ_WORKQ0; irq < OCTEON_IRQ_LAST; irq++) { - desc = irq_to_desc(irq); - switch (irq) { - case OCTEON_IRQ_MBOX0: - case OCTEON_IRQ_MBOX1: - /* The eoi function will disable them on this CPU. */ - desc->chip->eoi(irq); - break; - case OCTEON_IRQ_WDOG0: - case OCTEON_IRQ_WDOG1: - case OCTEON_IRQ_WDOG2: - case OCTEON_IRQ_WDOG3: - case OCTEON_IRQ_WDOG4: - case OCTEON_IRQ_WDOG5: - case OCTEON_IRQ_WDOG6: - case OCTEON_IRQ_WDOG7: - case OCTEON_IRQ_WDOG8: - case OCTEON_IRQ_WDOG9: - case OCTEON_IRQ_WDOG10: - case OCTEON_IRQ_WDOG11: - case OCTEON_IRQ_WDOG12: - case OCTEON_IRQ_WDOG13: - case OCTEON_IRQ_WDOG14: - case OCTEON_IRQ_WDOG15: - /* - * These have special per CPU semantics and - * are handled in the watchdog driver. - */ - break; - default: - raw_spin_lock_irqsave(&desc->lock, flags); - /* - * If this irq has an action, it is in use and - * must be migrated if it has affinity to this - * cpu. - */ - if (desc->action && cpumask_test_cpu(cpu, desc->affinity)) { - if (cpumask_weight(desc->affinity) > 1) { - /* - * It has multi CPU affinity, - * just remove this CPU from - * the affinity set. - */ - cpumask_copy(&new_affinity, desc->affinity); - cpumask_clear_cpu(cpu, &new_affinity); - } else { - /* - * Otherwise, put it on lowest - * numbered online CPU. - */ - cpumask_clear(&new_affinity); - cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity); - } - do_set_affinity = 1; - } else { - do_set_affinity = 0; - } - raw_spin_unlock_irqrestore(&desc->lock, flags); - - if (do_set_affinity) - irq_set_affinity(irq, &new_affinity); - - break; - } - } + irq_cpu_offline(); } #endif /* CONFIG_HOTPLUG_CPU */ diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index cecaf62aef3..cd61d7281d9 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -75,7 +75,7 @@ static int __init octeon_cf_device_init(void) * zero. */ - /* Asume that CS1 immediately follows. */ + /* Assume that CS1 immediately follows. */ mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1)); region_base = mio_boot_reg_cfg.s.base << 16; diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index b0c3686c96d..0707fae3f0e 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -420,7 +420,6 @@ void octeon_user_io_init(void) void __init prom_init(void) { struct cvmx_sysinfo *sysinfo; - const int coreid = cvmx_get_core_num(); int i; int argc; #ifdef CONFIG_CAVIUM_RESERVE32 @@ -537,17 +536,6 @@ void __init prom_init(void) octeon_uart = octeon_get_boot_uart(); - /* - * Disable All CIU Interrupts. The ones we need will be - * enabled later. Read the SUM register so we know the write - * completed. - */ - cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0); - cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); - cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); - cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); - cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2))); - #ifdef CONFIG_SMP octeon_write_lcd("LinuxSMP"); #else @@ -674,7 +662,7 @@ void __init plat_mem_setup(void) * some memory vectors. When SPARSEMEM is in use, it doesn't * verify that the size is big enough for the final * vectors. Making the smallest chuck 4MB seems to be enough - * to consistantly work. + * to consistently work. */ mem_alloc_size = 4 << 20; if (mem_alloc_size > MAX_MEMORY) diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index 391cefe556b..ba78b21cc8d 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -171,41 +171,19 @@ static void octeon_boot_secondary(int cpu, struct task_struct *idle) * After we've done initial boot, this function is called to allow the * board code to clean up state, if needed */ -static void octeon_init_secondary(void) +static void __cpuinit octeon_init_secondary(void) { - const int coreid = cvmx_get_core_num(); - union cvmx_ciu_intx_sum0 interrupt_enable; unsigned int sr; -#ifdef CONFIG_HOTPLUG_CPU - struct linux_app_boot_info *labi; - - labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); - - if (labi->labi_signature != LABI_SIGNATURE) - panic("The bootloader version on this board is incorrect."); -#endif - sr = set_c0_status(ST0_BEV); write_c0_ebase((u32)ebase); write_c0_status(sr); octeon_check_cpu_bist(); octeon_init_cvmcount(); - /* - pr_info("SMP: CPU%d (CoreId %lu) started\n", cpu, coreid); - */ - /* Enable Mailbox interrupts to this core. These are the only - interrupts allowed on line 3 */ - cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), 0xffffffff); - interrupt_enable.u64 = 0; - interrupt_enable.s.mbox = 0x3; - cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), interrupt_enable.u64); - cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); - cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); - cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); - /* Enable core interrupt processing for 2,3 and 7 */ - set_c0_status(0x8c01); + + octeon_irq_setup_secondary(); + raw_local_irq_enable(); } /** @@ -214,6 +192,15 @@ static void octeon_init_secondary(void) */ void octeon_prepare_cpus(unsigned int max_cpus) { +#ifdef CONFIG_HOTPLUG_CPU + struct linux_app_boot_info *labi; + + labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); + + if (labi->labi_signature != LABI_SIGNATURE) + panic("The bootloader version on this board is incorrect."); +#endif + cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff); if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED, "mailbox0", mailbox_interrupt)) { diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c index cb41954fc32..824e08c7379 100644 --- a/arch/mips/dec/ioasic-irq.c +++ b/arch/mips/dec/ioasic-irq.c @@ -17,80 +17,48 @@ #include <asm/dec/ioasic_addrs.h> #include <asm/dec/ioasic_ints.h> - static int ioasic_irq_base; - -static inline void unmask_ioasic_irq(unsigned int irq) +static void unmask_ioasic_irq(struct irq_data *d) { u32 simr; simr = ioasic_read(IO_REG_SIMR); - simr |= (1 << (irq - ioasic_irq_base)); + simr |= (1 << (d->irq - ioasic_irq_base)); ioasic_write(IO_REG_SIMR, simr); } -static inline void mask_ioasic_irq(unsigned int irq) +static void mask_ioasic_irq(struct irq_data *d) { u32 simr; simr = ioasic_read(IO_REG_SIMR); - simr &= ~(1 << (irq - ioasic_irq_base)); + simr &= ~(1 << (d->irq - ioasic_irq_base)); ioasic_write(IO_REG_SIMR, simr); } -static inline void clear_ioasic_irq(unsigned int irq) +static void ack_ioasic_irq(struct irq_data *d) { - u32 sir; - - sir = ~(1 << (irq - ioasic_irq_base)); - ioasic_write(IO_REG_SIR, sir); -} - -static inline void ack_ioasic_irq(unsigned int irq) -{ - mask_ioasic_irq(irq); + mask_ioasic_irq(d); fast_iob(); } -static inline void end_ioasic_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - unmask_ioasic_irq(irq); -} - static struct irq_chip ioasic_irq_type = { .name = "IO-ASIC", - .ack = ack_ioasic_irq, - .mask = mask_ioasic_irq, - .mask_ack = ack_ioasic_irq, - .unmask = unmask_ioasic_irq, + .irq_ack = ack_ioasic_irq, + .irq_mask = mask_ioasic_irq, + .irq_mask_ack = ack_ioasic_irq, + .irq_unmask = unmask_ioasic_irq, }; - -#define unmask_ioasic_dma_irq unmask_ioasic_irq - -#define mask_ioasic_dma_irq mask_ioasic_irq - -#define ack_ioasic_dma_irq ack_ioasic_irq - -static inline void end_ioasic_dma_irq(unsigned int irq) -{ - clear_ioasic_irq(irq); - fast_iob(); - end_ioasic_irq(irq); -} - static struct irq_chip ioasic_dma_irq_type = { .name = "IO-ASIC-DMA", - .ack = ack_ioasic_dma_irq, - .mask = mask_ioasic_dma_irq, - .mask_ack = ack_ioasic_dma_irq, - .unmask = unmask_ioasic_dma_irq, - .end = end_ioasic_dma_irq, + .irq_ack = ack_ioasic_irq, + .irq_mask = mask_ioasic_irq, + .irq_mask_ack = ack_ioasic_irq, + .irq_unmask = unmask_ioasic_irq, }; - void __init init_ioasic_irqs(int base) { int i; @@ -100,10 +68,10 @@ void __init init_ioasic_irqs(int base) fast_iob(); for (i = base; i < base + IO_INR_DMA; i++) - set_irq_chip_and_handler(i, &ioasic_irq_type, + irq_set_chip_and_handler(i, &ioasic_irq_type, handle_level_irq); for (; i < base + IO_IRQ_LINES; i++) - set_irq_chip(i, &ioasic_dma_irq_type); + irq_set_chip(i, &ioasic_dma_irq_type); ioasic_irq_base = base; } diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c index ed90a8deabc..37199f742c4 100644 --- a/arch/mips/dec/kn02-irq.c +++ b/arch/mips/dec/kn02-irq.c @@ -27,43 +27,40 @@ */ u32 cached_kn02_csr; - static int kn02_irq_base; - -static inline void unmask_kn02_irq(unsigned int irq) +static void unmask_kn02_irq(struct irq_data *d) { volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); - cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16)); + cached_kn02_csr |= (1 << (d->irq - kn02_irq_base + 16)); *csr = cached_kn02_csr; } -static inline void mask_kn02_irq(unsigned int irq) +static void mask_kn02_irq(struct irq_data *d) { volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); - cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16)); + cached_kn02_csr &= ~(1 << (d->irq - kn02_irq_base + 16)); *csr = cached_kn02_csr; } -static void ack_kn02_irq(unsigned int irq) +static void ack_kn02_irq(struct irq_data *d) { - mask_kn02_irq(irq); + mask_kn02_irq(d); iob(); } static struct irq_chip kn02_irq_type = { .name = "KN02-CSR", - .ack = ack_kn02_irq, - .mask = mask_kn02_irq, - .mask_ack = ack_kn02_irq, - .unmask = unmask_kn02_irq, + .irq_ack = ack_kn02_irq, + .irq_mask = mask_kn02_irq, + .irq_mask_ack = ack_kn02_irq, + .irq_unmask = unmask_kn02_irq, }; - void __init init_kn02_irqs(int base) { volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + @@ -76,7 +73,7 @@ void __init init_kn02_irqs(int base) iob(); for (i = base; i < base + KN02_IRQ_LINES; i++) - set_irq_chip_and_handler(i, &kn02_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &kn02_irq_type, handle_level_irq); kn02_irq_base = base; } diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c index 3a96799eb65..3dbd7a5a6ad 100644 --- a/arch/mips/emma/markeins/irq.c +++ b/arch/mips/emma/markeins/irq.c @@ -34,13 +34,10 @@ #include <asm/emma/emma2rh.h> -static void emma2rh_irq_enable(unsigned int irq) +static void emma2rh_irq_enable(struct irq_data *d) { - u32 reg_value; - u32 reg_bitmask; - u32 reg_index; - - irq -= EMMA2RH_IRQ_BASE; + unsigned int irq = d->irq - EMMA2RH_IRQ_BASE; + u32 reg_value, reg_bitmask, reg_index; reg_index = EMMA2RH_BHIF_INT_EN_0 + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32); @@ -49,13 +46,10 @@ static void emma2rh_irq_enable(unsigned int irq) emma2rh_out32(reg_index, reg_value | reg_bitmask); } -static void emma2rh_irq_disable(unsigned int irq) +static void emma2rh_irq_disable(struct irq_data *d) { - u32 reg_value; - u32 reg_bitmask; - u32 reg_index; - - irq -= EMMA2RH_IRQ_BASE; + unsigned int irq = d->irq - EMMA2RH_IRQ_BASE; + u32 reg_value, reg_bitmask, reg_index; reg_index = EMMA2RH_BHIF_INT_EN_0 + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32); @@ -66,10 +60,8 @@ static void emma2rh_irq_disable(unsigned int irq) struct irq_chip emma2rh_irq_controller = { .name = "emma2rh_irq", - .ack = emma2rh_irq_disable, - .mask = emma2rh_irq_disable, - .mask_ack = emma2rh_irq_disable, - .unmask = emma2rh_irq_enable, + .irq_mask = emma2rh_irq_disable, + .irq_unmask = emma2rh_irq_enable, }; void emma2rh_irq_init(void) @@ -77,28 +69,26 @@ void emma2rh_irq_init(void) u32 i; for (i = 0; i < NUM_EMMA2RH_IRQ; i++) - set_irq_chip_and_handler_name(EMMA2RH_IRQ_BASE + i, + irq_set_chip_and_handler_name(EMMA2RH_IRQ_BASE + i, &emma2rh_irq_controller, handle_level_irq, "level"); } -static void emma2rh_sw_irq_enable(unsigned int irq) +static void emma2rh_sw_irq_enable(struct irq_data *d) { + unsigned int irq = d->irq - EMMA2RH_SW_IRQ_BASE; u32 reg; - irq -= EMMA2RH_SW_IRQ_BASE; - reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); reg |= 1 << irq; emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); } -static void emma2rh_sw_irq_disable(unsigned int irq) +static void emma2rh_sw_irq_disable(struct irq_data *d) { + unsigned int irq = d->irq - EMMA2RH_SW_IRQ_BASE; u32 reg; - irq -= EMMA2RH_SW_IRQ_BASE; - reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); reg &= ~(1 << irq); emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); @@ -106,10 +96,8 @@ static void emma2rh_sw_irq_disable(unsigned int irq) struct irq_chip emma2rh_sw_irq_controller = { .name = "emma2rh_sw_irq", - .ack = emma2rh_sw_irq_disable, - .mask = emma2rh_sw_irq_disable, - .mask_ack = emma2rh_sw_irq_disable, - .unmask = emma2rh_sw_irq_enable, + .irq_mask = emma2rh_sw_irq_disable, + .irq_unmask = emma2rh_sw_irq_enable, }; void emma2rh_sw_irq_init(void) @@ -117,44 +105,43 @@ void emma2rh_sw_irq_init(void) u32 i; for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++) - set_irq_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i, + irq_set_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i, &emma2rh_sw_irq_controller, handle_level_irq, "level"); } -static void emma2rh_gpio_irq_enable(unsigned int irq) +static void emma2rh_gpio_irq_enable(struct irq_data *d) { + unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE; u32 reg; - irq -= EMMA2RH_GPIO_IRQ_BASE; - reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); reg |= 1 << irq; emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); } -static void emma2rh_gpio_irq_disable(unsigned int irq) +static void emma2rh_gpio_irq_disable(struct irq_data *d) { + unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE; u32 reg; - irq -= EMMA2RH_GPIO_IRQ_BASE; - reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); reg &= ~(1 << irq); emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); } -static void emma2rh_gpio_irq_ack(unsigned int irq) +static void emma2rh_gpio_irq_ack(struct irq_data *d) { - irq -= EMMA2RH_GPIO_IRQ_BASE; + unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE; + emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); } -static void emma2rh_gpio_irq_mask_ack(unsigned int irq) +static void emma2rh_gpio_irq_mask_ack(struct irq_data *d) { + unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE; u32 reg; - irq -= EMMA2RH_GPIO_IRQ_BASE; emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); @@ -164,10 +151,10 @@ static void emma2rh_gpio_irq_mask_ack(unsigned int irq) struct irq_chip emma2rh_gpio_irq_controller = { .name = "emma2rh_gpio_irq", - .ack = emma2rh_gpio_irq_ack, - .mask = emma2rh_gpio_irq_disable, - .mask_ack = emma2rh_gpio_irq_mask_ack, - .unmask = emma2rh_gpio_irq_enable, + .irq_ack = emma2rh_gpio_irq_ack, + .irq_mask = emma2rh_gpio_irq_disable, + .irq_mask_ack = emma2rh_gpio_irq_mask_ack, + .irq_unmask = emma2rh_gpio_irq_enable, }; void emma2rh_gpio_irq_init(void) @@ -175,7 +162,7 @@ void emma2rh_gpio_irq_init(void) u32 i; for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++) - set_irq_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i, + irq_set_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i, &emma2rh_gpio_irq_controller, handle_edge_irq, "edge"); } diff --git a/arch/mips/fw/arc/Makefile b/arch/mips/fw/arc/Makefile index e0aaad482b0..5314b37aff2 100644 --- a/arch/mips/fw/arc/Makefile +++ b/arch/mips/fw/arc/Makefile @@ -9,4 +9,4 @@ lib-$(CONFIG_ARC_MEMORY) += memory.o lib-$(CONFIG_ARC_CONSOLE) += arc_con.o lib-$(CONFIG_ARC_PROMLIB) += promlib.o -EXTRA_CFLAGS += -Werror +ccflags-y := -Werror diff --git a/arch/mips/fw/arc/promlib.c b/arch/mips/fw/arc/promlib.c index c508c00dbb6..b7f9dd3c93c 100644 --- a/arch/mips/fw/arc/promlib.c +++ b/arch/mips/fw/arc/promlib.c @@ -4,7 +4,7 @@ * for more details. * * Copyright (C) 1996 David S. Miller (dm@sgi.com) - * Compability with board caches, Ulf Carlsson + * Compatibility with board caches, Ulf Carlsson */ #include <linux/kernel.h> #include <asm/sgialib.h> diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 50b4ef288c5..2e1ad4c652b 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -676,9 +676,8 @@ static inline int ffs(int word) #include <asm/arch_hweight.h> #include <asm-generic/bitops/const_hweight.h> -#include <asm-generic/bitops/ext2-non-atomic.h> +#include <asm-generic/bitops/le.h> #include <asm-generic/bitops/ext2-atomic.h> -#include <asm-generic/bitops/minix.h> #endif /* __KERNEL__ */ diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h index 650ac9ba734..b4db69fbc40 100644 --- a/arch/mips/include/asm/cache.h +++ b/arch/mips/include/asm/cache.h @@ -17,6 +17,6 @@ #define SMP_CACHE_SHIFT L1_CACHE_SHIFT #define SMP_CACHE_BYTES L1_CACHE_BYTES -#define __read_mostly __attribute__((__section__(".data.read_mostly"))) +#define __read_mostly __attribute__((__section__(".data..read_mostly"))) #endif /* _ASM_CACHE_H */ diff --git a/arch/mips/include/asm/cevt-r4k.h b/arch/mips/include/asm/cevt-r4k.h index fa4328f9124..65f9bdd02f1 100644 --- a/arch/mips/include/asm/cevt-r4k.h +++ b/arch/mips/include/asm/cevt-r4k.h @@ -14,6 +14,9 @@ #ifndef __ASM_CEVT_R4K_H #define __ASM_CEVT_R4K_H +#include <linux/clockchips.h> +#include <asm/time.h> + DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device); void mips_event_handler(struct clock_event_device *dev); diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h index b9c8203688d..c0ead631384 100644 --- a/arch/mips/include/asm/dec/prom.h +++ b/arch/mips/include/asm/dec/prom.h @@ -108,7 +108,7 @@ extern int (*__pmax_close)(int); /* * On MIPS64 we have to call PROM functions via a helper - * dispatcher to accomodate ABI incompatibilities. + * dispatcher to accommodate ABI incompatibilities. */ #define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \ __asm__(#fun " = call_o32") diff --git a/arch/mips/include/asm/floppy.h b/arch/mips/include/asm/floppy.h index 992d232adc8..c5c7c0e6064 100644 --- a/arch/mips/include/asm/floppy.h +++ b/arch/mips/include/asm/floppy.h @@ -24,7 +24,7 @@ static inline void fd_cacheflush(char * addr, long size) * And on Mips's the CMOS info fails also ... * * FIXME: This information should come from the ARC configuration tree - * or whereever a particular machine has stored this ... + * or wherever a particular machine has stored this ... */ #define FLOPPY0_TYPE fd_drive_type(0) #define FLOPPY1_TYPE fd_drive_type(1) diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h index f5e85601532..c565b7c3f0b 100644 --- a/arch/mips/include/asm/hugetlb.h +++ b/arch/mips/include/asm/hugetlb.h @@ -70,6 +70,7 @@ static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm, static inline void huge_ptep_clear_flush(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) { + flush_tlb_mm(vma->vm_mm); } static inline int huge_pte_none(pte_t pte) diff --git a/arch/mips/include/asm/hw_irq.h b/arch/mips/include/asm/hw_irq.h index aca05a43a97..77adda297ad 100644 --- a/arch/mips/include/asm/hw_irq.h +++ b/arch/mips/include/asm/hw_irq.h @@ -13,7 +13,7 @@ extern atomic_t irq_err_count; /* - * interrupt-retrigger: NOP for now. This may not be apropriate for all + * interrupt-retrigger: NOP for now. This may not be appropriate for all * machines, we'll see ... */ diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 5b017f23e24..b04e4de5dd2 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -242,7 +242,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, * This version of ioremap ensures that the memory is marked uncachable * on the CPU as well as honouring existing caching rules from things like * the PCI bus. Note that there are other caches and buffers on many - * busses. In paticular driver authors should read up on PCI writes + * busses. In particular driver authors should read up on PCI writes * * It's useful if some control registers are in such an area and * write combining or read caching is not desirable: diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h index b003ed52ed1..0ec01294b06 100644 --- a/arch/mips/include/asm/irq.h +++ b/arch/mips/include/asm/irq.h @@ -55,9 +55,9 @@ static inline void smtc_im_ack_irq(unsigned int irq) #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF #include <linux/cpumask.h> -extern int plat_set_irq_affinity(unsigned int irq, - const struct cpumask *affinity); -extern void smtc_forward_irq(unsigned int irq); +extern int plat_set_irq_affinity(struct irq_data *d, + const struct cpumask *affinity, bool force); +extern void smtc_forward_irq(struct irq_data *d); /* * IRQ affinity hook invoked at the beginning of interrupt dispatch @@ -70,51 +70,53 @@ extern void smtc_forward_irq(unsigned int irq); * cpumask implementations, this version is optimistically assuming * that cpumask.h macro overhead is reasonable during interrupt dispatch. */ -#define IRQ_AFFINITY_HOOK(irq) \ -do { \ - if (!cpumask_test_cpu(smp_processor_id(), irq_desc[irq].affinity)) {\ - smtc_forward_irq(irq); \ - irq_exit(); \ - return; \ - } \ -} while (0) +static inline int handle_on_other_cpu(unsigned int irq) +{ + struct irq_data *d = irq_get_irq_data(irq); + + if (cpumask_test_cpu(smp_processor_id(), d->affinity)) + return 0; + smtc_forward_irq(d); + return 1; +} #else /* Not doing SMTC affinity */ -#define IRQ_AFFINITY_HOOK(irq) do { } while (0) +static inline int handle_on_other_cpu(unsigned int irq) { return 0; } #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP +static inline void smtc_im_backstop(unsigned int irq) +{ + if (irq_hwmask[irq] & 0x0000ff00) + write_c0_tccontext(read_c0_tccontext() & + ~(irq_hwmask[irq] & 0x0000ff00)); +} + /* * Clear interrupt mask handling "backstop" if irq_hwmask * entry so indicates. This implies that the ack() or end() * functions will take over re-enabling the low-level mask. * Otherwise it will be done on return from exception. */ -#define __DO_IRQ_SMTC_HOOK(irq) \ -do { \ - IRQ_AFFINITY_HOOK(irq); \ - if (irq_hwmask[irq] & 0x0000ff00) \ - write_c0_tccontext(read_c0_tccontext() & \ - ~(irq_hwmask[irq] & 0x0000ff00)); \ -} while (0) - -#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) \ -do { \ - if (irq_hwmask[irq] & 0x0000ff00) \ - write_c0_tccontext(read_c0_tccontext() & \ - ~(irq_hwmask[irq] & 0x0000ff00)); \ -} while (0) +static inline int smtc_handle_on_other_cpu(unsigned int irq) +{ + int ret = handle_on_other_cpu(irq); + + if (!ret) + smtc_im_backstop(irq); + return ret; +} #else -#define __DO_IRQ_SMTC_HOOK(irq) \ -do { \ - IRQ_AFFINITY_HOOK(irq); \ -} while (0) -#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { } while (0) +static inline void smtc_im_backstop(unsigned int irq) { } +static inline int smtc_handle_on_other_cpu(unsigned int irq) +{ + return handle_on_other_cpu(irq); +} #endif diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h index 9ef3b0d1789..309cbcd6909 100644 --- a/arch/mips/include/asm/irqflags.h +++ b/arch/mips/include/asm/irqflags.h @@ -174,7 +174,7 @@ __asm__( "mtc0 \\flags, $2, 1 \n" #elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) /* - * Slow, but doesn't suffer from a relativly unlikely race + * Slow, but doesn't suffer from a relatively unlikely race * condition we're having since days 1. */ " beqz \\flags, 1f \n" diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h index 5325084d5c4..ed72e6a26b7 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h @@ -4,7 +4,7 @@ #define TAGVER_LEN 4 /* Length of Tag Version */ #define TAGLAYOUT_LEN 4 /* Length of FlashLayoutVer */ #define SIG1_LEN 20 /* Company Signature 1 Length */ -#define SIG2_LEN 14 /* Company Signature 2 Lenght */ +#define SIG2_LEN 14 /* Company Signature 2 Length */ #define BOARDID_LEN 16 /* Length of BoardId */ #define ENDIANFLAG_LEN 2 /* Endian Flag Length */ #define CHIPID_LEN 6 /* Chip Id Length */ @@ -88,7 +88,7 @@ struct bcm_tag { char kernel_crc[CRC_LEN]; /* 228-235: Unused at present */ char reserved1[8]; - /* 236-239: CRC32 of header excluding tagVersion */ + /* 236-239: CRC32 of header excluding last 20 bytes */ char header_crc[CRC_LEN]; /* 240-255: Unused at present */ char reserved2[16]; diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h index 6ddab8aef64..5b05f186e39 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/irq.h +++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h @@ -11,172 +11,91 @@ #define NR_IRQS OCTEON_IRQ_LAST #define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0 -/* 0 - 7 represent the i8259 master */ -#define OCTEON_IRQ_I8259M0 0 -#define OCTEON_IRQ_I8259M1 1 -#define OCTEON_IRQ_I8259M2 2 -#define OCTEON_IRQ_I8259M3 3 -#define OCTEON_IRQ_I8259M4 4 -#define OCTEON_IRQ_I8259M5 5 -#define OCTEON_IRQ_I8259M6 6 -#define OCTEON_IRQ_I8259M7 7 -/* 8 - 15 represent the i8259 slave */ -#define OCTEON_IRQ_I8259S0 8 -#define OCTEON_IRQ_I8259S1 9 -#define OCTEON_IRQ_I8259S2 10 -#define OCTEON_IRQ_I8259S3 11 -#define OCTEON_IRQ_I8259S4 12 -#define OCTEON_IRQ_I8259S5 13 -#define OCTEON_IRQ_I8259S6 14 -#define OCTEON_IRQ_I8259S7 15 -/* 16 - 23 represent the 8 MIPS standard interrupt sources */ -#define OCTEON_IRQ_SW0 16 -#define OCTEON_IRQ_SW1 17 -#define OCTEON_IRQ_CIU0 18 -#define OCTEON_IRQ_CIU1 19 -#define OCTEON_IRQ_CIU4 20 -#define OCTEON_IRQ_5 21 -#define OCTEON_IRQ_PERF 22 -#define OCTEON_IRQ_TIMER 23 -/* 24 - 87 represent the sources in CIU_INTX_EN0 */ -#define OCTEON_IRQ_WORKQ0 24 -#define OCTEON_IRQ_WORKQ1 25 -#define OCTEON_IRQ_WORKQ2 26 -#define OCTEON_IRQ_WORKQ3 27 -#define OCTEON_IRQ_WORKQ4 28 -#define OCTEON_IRQ_WORKQ5 29 -#define OCTEON_IRQ_WORKQ6 30 -#define OCTEON_IRQ_WORKQ7 31 -#define OCTEON_IRQ_WORKQ8 32 -#define OCTEON_IRQ_WORKQ9 33 -#define OCTEON_IRQ_WORKQ10 34 -#define OCTEON_IRQ_WORKQ11 35 -#define OCTEON_IRQ_WORKQ12 36 -#define OCTEON_IRQ_WORKQ13 37 -#define OCTEON_IRQ_WORKQ14 38 -#define OCTEON_IRQ_WORKQ15 39 -#define OCTEON_IRQ_GPIO0 40 -#define OCTEON_IRQ_GPIO1 41 -#define OCTEON_IRQ_GPIO2 42 -#define OCTEON_IRQ_GPIO3 43 -#define OCTEON_IRQ_GPIO4 44 -#define OCTEON_IRQ_GPIO5 45 -#define OCTEON_IRQ_GPIO6 46 -#define OCTEON_IRQ_GPIO7 47 -#define OCTEON_IRQ_GPIO8 48 -#define OCTEON_IRQ_GPIO9 49 -#define OCTEON_IRQ_GPIO10 50 -#define OCTEON_IRQ_GPIO11 51 -#define OCTEON_IRQ_GPIO12 52 -#define OCTEON_IRQ_GPIO13 53 -#define OCTEON_IRQ_GPIO14 54 -#define OCTEON_IRQ_GPIO15 55 -#define OCTEON_IRQ_MBOX0 56 -#define OCTEON_IRQ_MBOX1 57 -#define OCTEON_IRQ_UART0 58 -#define OCTEON_IRQ_UART1 59 -#define OCTEON_IRQ_PCI_INT0 60 -#define OCTEON_IRQ_PCI_INT1 61 -#define OCTEON_IRQ_PCI_INT2 62 -#define OCTEON_IRQ_PCI_INT3 63 -#define OCTEON_IRQ_PCI_MSI0 64 -#define OCTEON_IRQ_PCI_MSI1 65 -#define OCTEON_IRQ_PCI_MSI2 66 -#define OCTEON_IRQ_PCI_MSI3 67 -#define OCTEON_IRQ_RESERVED68 68 /* Summary of CIU_INT_SUM1 */ -#define OCTEON_IRQ_TWSI 69 -#define OCTEON_IRQ_RML 70 -#define OCTEON_IRQ_TRACE 71 -#define OCTEON_IRQ_GMX_DRP0 72 -#define OCTEON_IRQ_GMX_DRP1 73 -#define OCTEON_IRQ_IPD_DRP 74 -#define OCTEON_IRQ_KEY_ZERO 75 -#define OCTEON_IRQ_TIMER0 76 -#define OCTEON_IRQ_TIMER1 77 -#define OCTEON_IRQ_TIMER2 78 -#define OCTEON_IRQ_TIMER3 79 -#define OCTEON_IRQ_USB0 80 -#define OCTEON_IRQ_PCM 81 -#define OCTEON_IRQ_MPI 82 -#define OCTEON_IRQ_TWSI2 83 -#define OCTEON_IRQ_POWIQ 84 -#define OCTEON_IRQ_IPDPPTHR 85 -#define OCTEON_IRQ_MII0 86 -#define OCTEON_IRQ_BOOTDMA 87 -/* 88 - 151 represent the sources in CIU_INTX_EN1 */ -#define OCTEON_IRQ_WDOG0 88 -#define OCTEON_IRQ_WDOG1 89 -#define OCTEON_IRQ_WDOG2 90 -#define OCTEON_IRQ_WDOG3 91 -#define OCTEON_IRQ_WDOG4 92 -#define OCTEON_IRQ_WDOG5 93 -#define OCTEON_IRQ_WDOG6 94 -#define OCTEON_IRQ_WDOG7 95 -#define OCTEON_IRQ_WDOG8 96 -#define OCTEON_IRQ_WDOG9 97 -#define OCTEON_IRQ_WDOG10 98 -#define OCTEON_IRQ_WDOG11 99 -#define OCTEON_IRQ_WDOG12 100 -#define OCTEON_IRQ_WDOG13 101 -#define OCTEON_IRQ_WDOG14 102 -#define OCTEON_IRQ_WDOG15 103 -#define OCTEON_IRQ_UART2 104 -#define OCTEON_IRQ_USB1 105 -#define OCTEON_IRQ_MII1 106 -#define OCTEON_IRQ_RESERVED107 107 -#define OCTEON_IRQ_RESERVED108 108 -#define OCTEON_IRQ_RESERVED109 109 -#define OCTEON_IRQ_RESERVED110 110 -#define OCTEON_IRQ_RESERVED111 111 -#define OCTEON_IRQ_RESERVED112 112 -#define OCTEON_IRQ_RESERVED113 113 -#define OCTEON_IRQ_RESERVED114 114 -#define OCTEON_IRQ_RESERVED115 115 -#define OCTEON_IRQ_RESERVED116 116 -#define OCTEON_IRQ_RESERVED117 117 -#define OCTEON_IRQ_RESERVED118 118 -#define OCTEON_IRQ_RESERVED119 119 -#define OCTEON_IRQ_RESERVED120 120 -#define OCTEON_IRQ_RESERVED121 121 -#define OCTEON_IRQ_RESERVED122 122 -#define OCTEON_IRQ_RESERVED123 123 -#define OCTEON_IRQ_RESERVED124 124 -#define OCTEON_IRQ_RESERVED125 125 -#define OCTEON_IRQ_RESERVED126 126 -#define OCTEON_IRQ_RESERVED127 127 -#define OCTEON_IRQ_RESERVED128 128 -#define OCTEON_IRQ_RESERVED129 129 -#define OCTEON_IRQ_RESERVED130 130 -#define OCTEON_IRQ_RESERVED131 131 -#define OCTEON_IRQ_RESERVED132 132 -#define OCTEON_IRQ_RESERVED133 133 -#define OCTEON_IRQ_RESERVED134 134 -#define OCTEON_IRQ_RESERVED135 135 -#define OCTEON_IRQ_RESERVED136 136 -#define OCTEON_IRQ_RESERVED137 137 -#define OCTEON_IRQ_RESERVED138 138 -#define OCTEON_IRQ_RESERVED139 139 -#define OCTEON_IRQ_RESERVED140 140 -#define OCTEON_IRQ_RESERVED141 141 -#define OCTEON_IRQ_RESERVED142 142 -#define OCTEON_IRQ_RESERVED143 143 -#define OCTEON_IRQ_RESERVED144 144 -#define OCTEON_IRQ_RESERVED145 145 -#define OCTEON_IRQ_RESERVED146 146 -#define OCTEON_IRQ_RESERVED147 147 -#define OCTEON_IRQ_RESERVED148 148 -#define OCTEON_IRQ_RESERVED149 149 -#define OCTEON_IRQ_RESERVED150 150 -#define OCTEON_IRQ_RESERVED151 151 +enum octeon_irq { +/* 1 - 8 represent the 8 MIPS standard interrupt sources */ + OCTEON_IRQ_SW0 = 1, + OCTEON_IRQ_SW1, +/* CIU0, CUI2, CIU4 are 3, 4, 5 */ + OCTEON_IRQ_5 = 6, + OCTEON_IRQ_PERF, + OCTEON_IRQ_TIMER, +/* sources in CIU_INTX_EN0 */ + OCTEON_IRQ_WORKQ0, + OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16, + OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16, + OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15, + OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16, + OCTEON_IRQ_MBOX1, + OCTEON_IRQ_UART0, + OCTEON_IRQ_UART1, + OCTEON_IRQ_UART2, + OCTEON_IRQ_PCI_INT0, + OCTEON_IRQ_PCI_INT1, + OCTEON_IRQ_PCI_INT2, + OCTEON_IRQ_PCI_INT3, + OCTEON_IRQ_PCI_MSI0, + OCTEON_IRQ_PCI_MSI1, + OCTEON_IRQ_PCI_MSI2, + OCTEON_IRQ_PCI_MSI3, + + OCTEON_IRQ_TWSI, + OCTEON_IRQ_TWSI2, + OCTEON_IRQ_RML, + OCTEON_IRQ_TRACE0, + OCTEON_IRQ_GMX_DRP0 = OCTEON_IRQ_TRACE0 + 4, + OCTEON_IRQ_IPD_DRP = OCTEON_IRQ_GMX_DRP0 + 5, + OCTEON_IRQ_KEY_ZERO, + OCTEON_IRQ_TIMER0, + OCTEON_IRQ_TIMER1, + OCTEON_IRQ_TIMER2, + OCTEON_IRQ_TIMER3, + OCTEON_IRQ_USB0, + OCTEON_IRQ_USB1, + OCTEON_IRQ_PCM, + OCTEON_IRQ_MPI, + OCTEON_IRQ_POWIQ, + OCTEON_IRQ_IPDPPTHR, + OCTEON_IRQ_MII0, + OCTEON_IRQ_MII1, + OCTEON_IRQ_BOOTDMA, + + OCTEON_IRQ_NAND, + OCTEON_IRQ_MIO, /* Summary of MIO_BOOT_ERR */ + OCTEON_IRQ_IOB, /* Summary of IOB_INT_SUM */ + OCTEON_IRQ_FPA, /* Summary of FPA_INT_SUM */ + OCTEON_IRQ_POW, /* Summary of POW_ECC_ERR */ + OCTEON_IRQ_L2C, /* Summary of L2C_INT_STAT */ + OCTEON_IRQ_IPD, /* Summary of IPD_INT_SUM */ + OCTEON_IRQ_PIP, /* Summary of PIP_INT_REG */ + OCTEON_IRQ_PKO, /* Summary of PKO_REG_ERROR */ + OCTEON_IRQ_ZIP, /* Summary of ZIP_ERROR */ + OCTEON_IRQ_TIM, /* Summary of TIM_REG_ERROR */ + OCTEON_IRQ_RAD, /* Summary of RAD_REG_ERROR */ + OCTEON_IRQ_KEY, /* Summary of KEY_INT_SUM */ + OCTEON_IRQ_DFA, /* Summary of DFA */ + OCTEON_IRQ_USBCTL, /* Summary of USBN0_INT_SUM */ + OCTEON_IRQ_SLI, /* Summary of SLI_INT_SUM */ + OCTEON_IRQ_DPI, /* Summary of DPI_INT_SUM */ + OCTEON_IRQ_AGX0, /* Summary of GMX0*+PCS0_INT*_REG */ + OCTEON_IRQ_AGL = OCTEON_IRQ_AGX0 + 5, + OCTEON_IRQ_PTP, + OCTEON_IRQ_PEM0, + OCTEON_IRQ_PEM1, + OCTEON_IRQ_SRIO0, + OCTEON_IRQ_SRIO1, + OCTEON_IRQ_LMC0, + OCTEON_IRQ_DFM = OCTEON_IRQ_LMC0 + 4, /* Summary of DFM */ + OCTEON_IRQ_RST, +}; #ifdef CONFIG_PCI_MSI -/* 152 - 215 represent the MSI interrupts 0-63 */ -#define OCTEON_IRQ_MSI_BIT0 152 -#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255) +/* 152 - 407 represent the MSI interrupts 0-255 */ +#define OCTEON_IRQ_MSI_BIT0 (OCTEON_IRQ_RST + 1) -#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1) +#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255) +#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1) #else -#define OCTEON_IRQ_LAST 152 +#define OCTEON_IRQ_LAST (OCTEON_IRQ_RST + 1) #endif #endif diff --git a/arch/mips/include/asm/mach-ip32/mc146818rtc.h b/arch/mips/include/asm/mach-ip32/mc146818rtc.h index c28ba8d8407..6b6bab43d5c 100644 --- a/arch/mips/include/asm/mach-ip32/mc146818rtc.h +++ b/arch/mips/include/asm/mach-ip32/mc146818rtc.h @@ -26,7 +26,7 @@ static inline void CMOS_WRITE(unsigned char data, unsigned long addr) } /* - * FIXME: Do it right. For now just assume that noone lives in 20th century + * FIXME: Do it right. For now just assume that no one lives in 20th century * and no O2 user in 22th century ;-) */ #define mc146818_decode_year(year) ((year) + 2000) diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h index 021f77ca59e..2a8e2bb5d53 100644 --- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h @@ -1,5 +1,5 @@ /* - * The header file of cs5536 sourth bridge. + * The header file of cs5536 south bridge. * * Copyright (C) 2007 Lemote, Inc. * Author : jlliu <liujl@lemote.com> diff --git a/arch/mips/include/asm/mach-pb1x00/pb1000.h b/arch/mips/include/asm/mach-pb1x00/pb1000.h index 6d1ff9060e4..65059255dc1 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1000.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1000.h @@ -1,5 +1,5 @@ /* - * Alchemy Semi Pb1000 Referrence Board + * Alchemy Semi Pb1000 Reference Board * * Copyright 2001, 2008 MontaVista Software Inc. * Author: MontaVista Software, Inc. <source@mvista.com> diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h index 962eb55dc88..fce4332ebb7 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1200.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h @@ -1,5 +1,5 @@ /* - * AMD Alchemy Pb1200 Referrence Board + * AMD Alchemy Pb1200 Reference Board * Board Registers defines. * * ######################################################################## diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h index fc4d766641c..f835c88e959 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1550.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h @@ -1,5 +1,5 @@ /* - * AMD Alchemy Semi PB1550 Referrence Board + * AMD Alchemy Semi PB1550 Reference Board * Board Registers defines. * * Copyright 2004 Embedded Edge LLC. diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h index f76029c2406..a8e72cf1214 100644 --- a/arch/mips/include/asm/mach-powertv/dma-coherence.h +++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h @@ -48,7 +48,7 @@ static inline unsigned long virt_to_phys_from_pte(void *addr) /* check for a valid page */ if (pte_present(pte)) { /* get the physical address the page is - * refering to */ + * referring to */ phys_addr = (unsigned long) page_to_phys(pte_page(pte)); /* add the offset within the page */ diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 4d987097538..6a6f8a8f542 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -922,7 +922,7 @@ do { \ #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) /* - * The WatchLo register. There may be upto 8 of them. + * The WatchLo register. There may be up to 8 of them. */ #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) @@ -942,7 +942,7 @@ do { \ #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) /* - * The WatchHi register. There may be upto 8 of them. + * The WatchHi register. There may be up to 8 of them. */ #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h index f3c23a43f84..4e4c3a8282d 100644 --- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h +++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h @@ -200,7 +200,7 @@ enum cvmx_chip_types_enum { CVMX_CHIP_TYPE_MAX, }; -/* Compatability alias for NAC38 name change, planned to be removed +/* Compatibility alias for NAC38 name change, planned to be removed * from SDK 1.7 */ #define CVMX_BOARD_TYPE_NAO38 CVMX_BOARD_TYPE_NAC38 diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h index 8e708bdb43f..877845b84b1 100644 --- a/arch/mips/include/asm/octeon/cvmx-bootmem.h +++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h @@ -67,7 +67,7 @@ struct cvmx_bootmem_block_header { /* * Structure for named memory blocks. Number of descriptors available - * can be changed without affecting compatiblity, but name length + * can be changed without affecting compatibility, but name length * changes require a bump in the bootmem descriptor version Note: This * structure must be naturally 64 bit aligned, as a single memory * image will be used by both 32 and 64 bit programs. diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h index 0b32c5b118e..2c8ff9e33ec 100644 --- a/arch/mips/include/asm/octeon/cvmx-l2c.h +++ b/arch/mips/include/asm/octeon/cvmx-l2c.h @@ -157,7 +157,7 @@ enum cvmx_l2c_tad_event { /** * Configure one of the four L2 Cache performance counters to capture event - * occurences. + * occurrences. * * @counter: The counter to configure. Range 0..3. * @event: The type of L2 Cache event occurrence to count. diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h index 9d9381e2e3d..7e1286706d4 100644 --- a/arch/mips/include/asm/octeon/cvmx.h +++ b/arch/mips/include/asm/octeon/cvmx.h @@ -151,7 +151,7 @@ enum cvmx_mips_space { #endif /** - * Convert a memory pointer (void*) into a hardware compatable + * Convert a memory pointer (void*) into a hardware compatible * memory address (uint64_t). Octeon hardware widgets don't * understand logical addresses. * diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index 6b34afd0d4e..f72f768cd3a 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h @@ -257,4 +257,6 @@ extern struct cvmx_bootinfo *octeon_bootinfo; extern uint64_t octeon_bootloader_entry_addr; +extern void (*octeon_irq_setup_secondary)(void); + #endif /* __ASM_OCTEON_OCTEON_H */ diff --git a/arch/mips/include/asm/paccess.h b/arch/mips/include/asm/paccess.h index c2394f8b0fe..9ce5a1e7e14 100644 --- a/arch/mips/include/asm/paccess.h +++ b/arch/mips/include/asm/paccess.h @@ -7,7 +7,7 @@ * Copyright (C) 1999, 2000 Silicon Graphics, Inc. * * Protected memory access. Used for everything that might take revenge - * by sending a DBE error like accessing possibly non-existant memory or + * by sending a DBE error like accessing possibly non-existent memory or * devices. */ #ifndef _ASM_PACCESS_H diff --git a/arch/mips/include/asm/pci/bridge.h b/arch/mips/include/asm/pci/bridge.h index f1f508e4f97..be44fb0266d 100644 --- a/arch/mips/include/asm/pci/bridge.h +++ b/arch/mips/include/asm/pci/bridge.h @@ -262,7 +262,7 @@ typedef volatile struct bridge_s { } bridge_t; /* - * Field formats for Error Command Word and Auxillary Error Command Word + * Field formats for Error Command Word and Auxiliary Error Command Word * of bridge. */ typedef struct bridge_err_cmdword_s { diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/cpu-feature-overrides.h b/arch/mips/include/asm/pmc-sierra/msp71xx/cpu-feature-overrides.h new file mode 100644 index 00000000000..a80801b094b --- /dev/null +++ b/arch/mips/include/asm/pmc-sierra/msp71xx/cpu-feature-overrides.h @@ -0,0 +1,21 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org) + */ +#ifndef __ASM_MACH_MSP71XX_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_MSP71XX_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_mips16 1 +#define cpu_has_dsp 1 +#define cpu_has_mipsmt 1 +#define cpu_has_fpu 0 + +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#endif /* __ASM_MACH_MSP71XX_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_gpio_macros.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_gpio_macros.h new file mode 100644 index 00000000000..156f320c69e --- /dev/null +++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_gpio_macros.h @@ -0,0 +1,343 @@ +/* + * + * Macros for external SMP-safe access to the PMC MSP71xx reference + * board GPIO pins + * + * Copyright 2010 PMC-Sierra, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __MSP_GPIO_MACROS_H__ +#define __MSP_GPIO_MACROS_H__ + +#include <msp_regops.h> +#include <msp_regs.h> + +#ifdef CONFIG_PMC_MSP7120_GW +#define MSP_NUM_GPIOS 20 +#else +#define MSP_NUM_GPIOS 28 +#endif + +/* -- GPIO Enumerations -- */ +enum msp_gpio_data { + MSP_GPIO_LO = 0, + MSP_GPIO_HI = 1, + MSP_GPIO_NONE, /* Special - Means pin is out of range */ + MSP_GPIO_TOGGLE, /* Special - Sets pin to opposite */ +}; + +enum msp_gpio_mode { + MSP_GPIO_INPUT = 0x0, + /* MSP_GPIO_ INTERRUPT = 0x1, Not supported yet */ + MSP_GPIO_UART_INPUT = 0x2, /* Only GPIO 4 or 5 */ + MSP_GPIO_OUTPUT = 0x8, + MSP_GPIO_UART_OUTPUT = 0x9, /* Only GPIO 2 or 3 */ + MSP_GPIO_PERIF_TIMERA = 0x9, /* Only GPIO 0 or 1 */ + MSP_GPIO_PERIF_TIMERB = 0xa, /* Only GPIO 0 or 1 */ + MSP_GPIO_UNKNOWN = 0xb, /* No such GPIO or mode */ +}; + +/* -- Static Tables -- */ + +/* Maps pins to data register */ +static volatile u32 * const MSP_GPIO_DATA_REGISTER[] = { + /* GPIO 0 and 1 on the first register */ + GPIO_DATA1_REG, GPIO_DATA1_REG, + /* GPIO 2, 3, 4, and 5 on the second register */ + GPIO_DATA2_REG, GPIO_DATA2_REG, GPIO_DATA2_REG, GPIO_DATA2_REG, + /* GPIO 6, 7, 8, and 9 on the third register */ + GPIO_DATA3_REG, GPIO_DATA3_REG, GPIO_DATA3_REG, GPIO_DATA3_REG, + /* GPIO 10, 11, 12, 13, 14, and 15 on the fourth register */ + GPIO_DATA4_REG, GPIO_DATA4_REG, GPIO_DATA4_REG, GPIO_DATA4_REG, + GPIO_DATA4_REG, GPIO_DATA4_REG, + /* GPIO 16 - 23 on the first strange EXTENDED register */ + EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, + EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, + EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, + /* GPIO 24 - 27 on the second strange EXTENDED register */ + EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG, + EXTENDED_GPIO2_REG, +}; + +/* Maps pins to mode register */ +static volatile u32 * const MSP_GPIO_MODE_REGISTER[] = { + /* GPIO 0 and 1 on the first register */ + GPIO_CFG1_REG, GPIO_CFG1_REG, + /* GPIO 2, 3, 4, and 5 on the second register */ + GPIO_CFG2_REG, GPIO_CFG2_REG, GPIO_CFG2_REG, GPIO_CFG2_REG, + /* GPIO 6, 7, 8, and 9 on the third register */ + GPIO_CFG3_REG, GPIO_CFG3_REG, GPIO_CFG3_REG, GPIO_CFG3_REG, + /* GPIO 10, 11, 12, 13, 14, and 15 on the fourth register */ + GPIO_CFG4_REG, GPIO_CFG4_REG, GPIO_CFG4_REG, GPIO_CFG4_REG, + GPIO_CFG4_REG, GPIO_CFG4_REG, + /* GPIO 16 - 23 on the first strange EXTENDED register */ + EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, + EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, + EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, + /* GPIO 24 - 27 on the second strange EXTENDED register */ + EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG, + EXTENDED_GPIO2_REG, +}; + +/* Maps 'basic' pins to relative offset from 0 per register */ +static int MSP_GPIO_OFFSET[] = { + /* GPIO 0 and 1 on the first register */ + 0, 0, + /* GPIO 2, 3, 4, and 5 on the second register */ + 2, 2, 2, 2, + /* GPIO 6, 7, 8, and 9 on the third register */ + 6, 6, 6, 6, + /* GPIO 10, 11, 12, 13, 14, and 15 on the fourth register */ + 10, 10, 10, 10, 10, 10, +}; + +/* Maps MODE to allowed pin mask */ +static unsigned int MSP_GPIO_MODE_ALLOWED[] = { + 0xffffffff, /* Mode 0 - INPUT */ + 0x00000, /* Mode 1 - INTERRUPT */ + 0x00030, /* Mode 2 - UART_INPUT (GPIO 4, 5)*/ + 0, 0, 0, 0, 0, /* Modes 3, 4, 5, 6, and 7 are reserved */ + 0xffffffff, /* Mode 8 - OUTPUT */ + 0x0000f, /* Mode 9 - UART_OUTPUT/ + PERF_TIMERA (GPIO 0, 1, 2, 3) */ + 0x00003, /* Mode a - PERF_TIMERB (GPIO 0, 1) */ + 0x00000, /* Mode b - Not really a mode! */ +}; + +/* -- Bit masks -- */ + +/* This gives you the 'register relative offset gpio' number */ +#define OFFSET_GPIO_NUMBER(gpio) (gpio - MSP_GPIO_OFFSET[gpio]) + +/* These take the 'register relative offset gpio' number */ +#define BASIC_DATA_REG_MASK(ogpio) (1 << ogpio) +#define BASIC_MODE_REG_VALUE(mode, ogpio) \ + (mode << BASIC_MODE_REG_SHIFT(ogpio)) +#define BASIC_MODE_REG_MASK(ogpio) \ + BASIC_MODE_REG_VALUE(0xf, ogpio) +#define BASIC_MODE_REG_SHIFT(ogpio) (ogpio * 4) +#define BASIC_MODE_REG_FROM_REG(data, ogpio) \ + ((data & BASIC_MODE_REG_MASK(ogpio)) >> BASIC_MODE_REG_SHIFT(ogpio)) + +/* These take the actual GPIO number (0 through 15) */ +#define BASIC_DATA_MASK(gpio) \ + BASIC_DATA_REG_MASK(OFFSET_GPIO_NUMBER(gpio)) +#define BASIC_MODE_MASK(gpio) \ + BASIC_MODE_REG_MASK(OFFSET_GPIO_NUMBER(gpio)) +#define BASIC_MODE(mode, gpio) \ + BASIC_MODE_REG_VALUE(mode, OFFSET_GPIO_NUMBER(gpio)) +#define BASIC_MODE_SHIFT(gpio) \ + BASIC_MODE_REG_SHIFT(OFFSET_GPIO_NUMBER(gpio)) +#define BASIC_MODE_FROM_REG(data, gpio) \ + BASIC_MODE_REG_FROM_REG(data, OFFSET_GPIO_NUMBER(gpio)) + +/* + * Each extended GPIO register is 32 bits long and is responsible for up to + * eight GPIOs. The least significant 16 bits contain the set and clear bit + * pair for each of the GPIOs. The most significant 16 bits contain the + * disable and enable bit pair for each of the GPIOs. For example, the + * extended GPIO reg for GPIOs 16-23 is as follows: + * + * 31: GPIO23_DISABLE + * ... + * 19: GPIO17_DISABLE + * 18: GPIO17_ENABLE + * 17: GPIO16_DISABLE + * 16: GPIO16_ENABLE + * ... + * 3: GPIO17_SET + * 2: GPIO17_CLEAR + * 1: GPIO16_SET + * 0: GPIO16_CLEAR + */ + +/* This gives the 'register relative offset gpio' number */ +#define EXTENDED_OFFSET_GPIO(gpio) (gpio < 24 ? gpio - 16 : gpio - 24) + +/* These take the 'register relative offset gpio' number */ +#define EXTENDED_REG_DISABLE(ogpio) (0x2 << ((ogpio * 2) + 16)) +#define EXTENDED_REG_ENABLE(ogpio) (0x1 << ((ogpio * 2) + 16)) +#define EXTENDED_REG_SET(ogpio) (0x2 << (ogpio * 2)) +#define EXTENDED_REG_CLR(ogpio) (0x1 << (ogpio * 2)) + +/* These take the actual GPIO number (16 through 27) */ +#define EXTENDED_DISABLE(gpio) \ + EXTENDED_REG_DISABLE(EXTENDED_OFFSET_GPIO(gpio)) +#define EXTENDED_ENABLE(gpio) \ + EXTENDED_REG_ENABLE(EXTENDED_OFFSET_GPIO(gpio)) +#define EXTENDED_SET(gpio) \ + EXTENDED_REG_SET(EXTENDED_OFFSET_GPIO(gpio)) +#define EXTENDED_CLR(gpio) \ + EXTENDED_REG_CLR(EXTENDED_OFFSET_GPIO(gpio)) + +#define EXTENDED_FULL_MASK (0xffffffff) + +/* -- API inline-functions -- */ + +/* + * Gets the current value of the specified pin + */ +static inline enum msp_gpio_data msp_gpio_pin_get(unsigned int gpio) +{ + u32 pinhi_mask = 0, pinhi_mask2 = 0; + + if (gpio >= MSP_NUM_GPIOS) + return MSP_GPIO_NONE; + + if (gpio < 16) { + pinhi_mask = BASIC_DATA_MASK(gpio); + } else { + /* + * Two cases are possible with the EXTENDED register: + * - In output mode (ENABLED flag set), check the CLR bit + * - In input mode (ENABLED flag not set), check the SET bit + */ + pinhi_mask = EXTENDED_ENABLE(gpio) | EXTENDED_CLR(gpio); + pinhi_mask2 = EXTENDED_SET(gpio); + } + if (((*MSP_GPIO_DATA_REGISTER[gpio] & pinhi_mask) == pinhi_mask) || + (*MSP_GPIO_DATA_REGISTER[gpio] & pinhi_mask2)) + return MSP_GPIO_HI; + else + return MSP_GPIO_LO; +} + +/* Sets the specified pin to the specified value */ +static inline void msp_gpio_pin_set(enum msp_gpio_data data, unsigned int gpio) +{ + if (gpio >= MSP_NUM_GPIOS) + return; + + if (gpio < 16) { + if (data == MSP_GPIO_TOGGLE) + toggle_reg32(MSP_GPIO_DATA_REGISTER[gpio], + BASIC_DATA_MASK(gpio)); + else if (data == MSP_GPIO_HI) + set_reg32(MSP_GPIO_DATA_REGISTER[gpio], + BASIC_DATA_MASK(gpio)); + else + clear_reg32(MSP_GPIO_DATA_REGISTER[gpio], + BASIC_DATA_MASK(gpio)); + } else { + if (data == MSP_GPIO_TOGGLE) { + /* Special ugly case: + * We have to read the CLR bit. + * If set, we write the CLR bit. + * If not, we write the SET bit. + */ + u32 tmpdata; + + custom_read_reg32(MSP_GPIO_DATA_REGISTER[gpio], + tmpdata); + if (tmpdata & EXTENDED_CLR(gpio)) + tmpdata = EXTENDED_CLR(gpio); + else + tmpdata = EXTENDED_SET(gpio); + custom_write_reg32(MSP_GPIO_DATA_REGISTER[gpio], + tmpdata); + } else { + u32 newdata; + + if (data == MSP_GPIO_HI) + newdata = EXTENDED_SET(gpio); + else + newdata = EXTENDED_CLR(gpio); + set_value_reg32(MSP_GPIO_DATA_REGISTER[gpio], + EXTENDED_FULL_MASK, newdata); + } + } +} + +/* Sets the specified pin to the specified value */ +static inline void msp_gpio_pin_hi(unsigned int gpio) +{ + msp_gpio_pin_set(MSP_GPIO_HI, gpio); +} + +/* Sets the specified pin to the specified value */ +static inline void msp_gpio_pin_lo(unsigned int gpio) +{ + msp_gpio_pin_set(MSP_GPIO_LO, gpio); +} + +/* Sets the specified pin to the opposite value */ +static inline void msp_gpio_pin_toggle(unsigned int gpio) +{ + msp_gpio_pin_set(MSP_GPIO_TOGGLE, gpio); +} + +/* Gets the mode of the specified pin */ +static inline enum msp_gpio_mode msp_gpio_pin_get_mode(unsigned int gpio) +{ + enum msp_gpio_mode retval = MSP_GPIO_UNKNOWN; + uint32_t data; + + if (gpio >= MSP_NUM_GPIOS) + return retval; + + data = *MSP_GPIO_MODE_REGISTER[gpio]; + + if (gpio < 16) { + retval = BASIC_MODE_FROM_REG(data, gpio); + } else { + /* Extended pins can only be either INPUT or OUTPUT */ + if (data & EXTENDED_ENABLE(gpio)) + retval = MSP_GPIO_OUTPUT; + else + retval = MSP_GPIO_INPUT; + } + + return retval; +} + +/* + * Sets the specified mode on the requested pin + * Returns 0 on success, or -1 if that mode is not allowed on this pin + */ +static inline int msp_gpio_pin_mode(enum msp_gpio_mode mode, unsigned int gpio) +{ + u32 modemask, newmode; + + if ((1 << gpio) & ~MSP_GPIO_MODE_ALLOWED[mode]) + return -1; + + if (gpio >= MSP_NUM_GPIOS) + return -1; + + if (gpio < 16) { + modemask = BASIC_MODE_MASK(gpio); + newmode = BASIC_MODE(mode, gpio); + } else { + modemask = EXTENDED_FULL_MASK; + if (mode == MSP_GPIO_INPUT) + newmode = EXTENDED_DISABLE(gpio); + else + newmode = EXTENDED_ENABLE(gpio); + } + /* Do the set atomically */ + set_value_reg32(MSP_GPIO_MODE_REGISTER[gpio], modemask, newmode); + + return 0; +} + +#endif /* __MSP_GPIO_MACROS_H__ */ diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h index 60a5a38dd5b..7d41474e548 100644 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h +++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h @@ -205,7 +205,7 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr) * custom_read_reg32(address, tmp); <-- Reads the address and put the value * in the 'tmp' variable given * - * From here on out, you are (basicly) atomic, so don't do anything too + * From here on out, you are (basically) atomic, so don't do anything too * fancy! * Also, this code may loop if the end of this block fails to write * everything back safely due do the other CPU, so do NOT do anything diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h index 603eb737b4a..692c1b658b9 100644 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h +++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h @@ -91,12 +91,10 @@ /* MAC C device registers */ #define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000) /* ADSL2 device registers */ -#define MSP_USB_BASE (MSP_MSB_BASE + 0xB40000) - /* USB device registers */ -#define MSP_USB_BASE_START (MSP_MSB_BASE + 0xB40100) - /* USB device registers */ -#define MSP_USB_BASE_END (MSP_MSB_BASE + 0xB401FF) - /* USB device registers */ +#define MSP_USB0_BASE (MSP_MSB_BASE + 0xB00000) + /* USB0 device registers */ +#define MSP_USB1_BASE (MSP_MSB_BASE + 0x300000) + /* USB1 device registers */ #define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000) /* CPU interface registers */ @@ -319,8 +317,11 @@ #define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184) /* CPU/SLP Error status 1 */ -#define EXTENDED_GPIO_REG regptr(MSP_SLP_BASE + 0x188) - /* Extended GPIO register */ +/* Extended GPIO registers */ +#define EXTENDED_GPIO1_REG regptr(MSP_SLP_BASE + 0x188) +#define EXTENDED_GPIO2_REG regptr(MSP_SLP_BASE + 0x18c) +#define EXTENDED_GPIO_REG EXTENDED_GPIO1_REG + /* Backward-compatibility */ /* System Error registers */ #define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190) diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h new file mode 100644 index 00000000000..4c9348df9df --- /dev/null +++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h @@ -0,0 +1,144 @@ +/****************************************************************** + * Copyright (c) 2000-2007 PMC-Sierra INC. + * + * This program is free software; you can redistribute it + * and/or modify it under the terms of the GNU General + * Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + * PURPOSE. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA + * 02139, USA. + * + * PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS + * SOFTWARE. + */ +#ifndef MSP_USB_H_ +#define MSP_USB_H_ + +#ifdef CONFIG_MSP_HAS_DUAL_USB +#define NUM_USB_DEVS 2 +#else +#define NUM_USB_DEVS 1 +#endif + +/* Register spaces for USB host 0 */ +#define MSP_USB0_MAB_START (MSP_USB0_BASE + 0x0) +#define MSP_USB0_MAB_END (MSP_USB0_BASE + 0x17) +#define MSP_USB0_ID_START (MSP_USB0_BASE + 0x40000) +#define MSP_USB0_ID_END (MSP_USB0_BASE + 0x4008f) +#define MSP_USB0_HS_START (MSP_USB0_BASE + 0x40100) +#define MSP_USB0_HS_END (MSP_USB0_BASE + 0x401FF) + +/* Register spaces for USB host 1 */ +#define MSP_USB1_MAB_START (MSP_USB1_BASE + 0x0) +#define MSP_USB1_MAB_END (MSP_USB1_BASE + 0x17) +#define MSP_USB1_ID_START (MSP_USB1_BASE + 0x40000) +#define MSP_USB1_ID_END (MSP_USB1_BASE + 0x4008f) +#define MSP_USB1_HS_START (MSP_USB1_BASE + 0x40100) +#define MSP_USB1_HS_END (MSP_USB1_BASE + 0x401ff) + +/* USB Identification registers */ +struct msp_usbid_regs { + u32 id; /* 0x0: Identification register */ + u32 hwgen; /* 0x4: General HW params */ + u32 hwhost; /* 0x8: Host HW params */ + u32 hwdev; /* 0xc: Device HW params */ + u32 hwtxbuf; /* 0x10: Tx buffer HW params */ + u32 hwrxbuf; /* 0x14: Rx buffer HW params */ + u32 reserved[26]; + u32 timer0_load; /* 0x80: General-purpose timer 0 load*/ + u32 timer0_ctrl; /* 0x84: General-purpose timer 0 control */ + u32 timer1_load; /* 0x88: General-purpose timer 1 load*/ + u32 timer1_ctrl; /* 0x8c: General-purpose timer 1 control */ +}; + +/* MSBus to AMBA registers */ +struct msp_mab_regs { + u32 isr; /* 0x0: Interrupt status */ + u32 imr; /* 0x4: Interrupt mask */ + u32 thcr0; /* 0x8: Transaction header capture 0 */ + u32 thcr1; /* 0xc: Transaction header capture 1 */ + u32 int_stat; /* 0x10: Interrupt status summary */ + u32 phy_cfg; /* 0x14: USB phy config */ +}; + +/* EHCI registers */ +struct msp_usbhs_regs { + u32 hciver; /* 0x0: Version and offset to operational regs */ + u32 hcsparams; /* 0x4: Host control structural parameters */ + u32 hccparams; /* 0x8: Host control capability parameters */ + u32 reserved0[5]; + u32 dciver; /* 0x20: Device interface version */ + u32 dccparams; /* 0x24: Device control capability parameters */ + u32 reserved1[6]; + u32 cmd; /* 0x40: USB command */ + u32 sts; /* 0x44: USB status */ + u32 int_ena; /* 0x48: USB interrupt enable */ + u32 frindex; /* 0x4c: Frame index */ + u32 reserved3; + union { + struct { + u32 flb_addr; /* 0x54: Frame list base address */ + u32 next_async_addr; /* 0x58: next asynchronous addr */ + u32 ttctrl; /* 0x5c: embedded transaction translator + async buffer status */ + u32 burst_size; /* 0x60: Controller burst size */ + u32 tx_fifo_ctrl; /* 0x64: Tx latency FIFO tuning */ + u32 reserved0[4]; + u32 endpt_nak; /* 0x78: Endpoint NAK */ + u32 endpt_nak_ena; /* 0x7c: Endpoint NAK enable */ + u32 cfg_flag; /* 0x80: Config flag */ + u32 port_sc1; /* 0x84: Port status & control 1 */ + u32 reserved1[7]; + u32 otgsc; /* 0xa4: OTG status & control */ + u32 mode; /* 0xa8: USB controller mode */ + } host; + + struct { + u32 dev_addr; /* 0x54: Device address */ + u32 endpt_list_addr; /* 0x58: Endpoint list address */ + u32 reserved0[7]; + u32 endpt_nak; /* 0x74 */ + u32 endpt_nak_ctrl; /* 0x78 */ + u32 cfg_flag; /* 0x80 */ + u32 port_sc1; /* 0x84: Port status & control 1 */ + u32 reserved[7]; + u32 otgsc; /* 0xa4: OTG status & control */ + u32 mode; /* 0xa8: USB controller mode */ + u32 endpt_setup_stat; /* 0xac */ + u32 endpt_prime; /* 0xb0 */ + u32 endpt_flush; /* 0xb4 */ + u32 endpt_stat; /* 0xb8 */ + u32 endpt_complete; /* 0xbc */ + u32 endpt_ctrl0; /* 0xc0 */ + u32 endpt_ctrl1; /* 0xc4 */ + u32 endpt_ctrl2; /* 0xc8 */ + u32 endpt_ctrl3; /* 0xcc */ + } device; + } u; +}; +/* + * Container for the more-generic platform_device. + * This exists mainly as a way to map the non-standard register + * spaces and make them accessible to the USB ISR. + */ +struct mspusb_device { + struct msp_mab_regs __iomem *mab_regs; + struct msp_usbid_regs __iomem *usbid_regs; + struct msp_usbhs_regs __iomem *usbhs_regs; + struct platform_device dev; +}; + +#define to_mspusb_device(x) container_of((x), struct mspusb_device, dev) +#define TO_HOST_ID(x) ((x) & 0x3) +#endif /*MSP_USB_H_*/ diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index ead6928fa6b..c104f1039a6 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -337,7 +337,7 @@ unsigned long get_wchan(struct task_struct *p); /* * Return_address is a replacement for __builtin_return_address(count) * which on certain architectures cannot reasonably be implemented in GCC - * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386). + * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386). * Note that __builtin_return_address(x>=1) is forbidden because GCC * aborts compilation on some CPUs. It's simply not possible to unwind * some CPU's stackframes. diff --git a/arch/mips/include/asm/sgi/ioc.h b/arch/mips/include/asm/sgi/ioc.h index 57a971904cf..380347b648e 100644 --- a/arch/mips/include/asm/sgi/ioc.h +++ b/arch/mips/include/asm/sgi/ioc.h @@ -17,7 +17,7 @@ #include <asm/sgi/pi1.h> /* - * All registers are 8-bit wide alligned on 32-bit boundary. Bad things + * All registers are 8-bit wide aligned on 32-bit boundary. Bad things * happen if you try word access them. You have been warned. */ diff --git a/arch/mips/include/asm/sibyte/sb1250_mac.h b/arch/mips/include/asm/sibyte/sb1250_mac.h index 591b9061fd8..77f78728423 100644 --- a/arch/mips/include/asm/sibyte/sb1250_mac.h +++ b/arch/mips/include/asm/sibyte/sb1250_mac.h @@ -520,7 +520,7 @@ #define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER) /* - * MAC Recieve Address Filter Exact Match Registers (Table 9-21) + * MAC Receive Address Filter Exact Match Registers (Table 9-21) * Registers: MAC_ADDR0_0 through MAC_ADDR7_0 * Registers: MAC_ADDR0_1 through MAC_ADDR7_1 * Registers: MAC_ADDR0_2 through MAC_ADDR7_2 @@ -538,7 +538,7 @@ /* No bitfields */ /* - * MAC Recieve Address Filter Hash Match Registers (Table 9-22) + * MAC Receive Address Filter Hash Match Registers (Table 9-22) * Registers: MAC_HASH0_0 through MAC_HASH7_0 * Registers: MAC_HASH0_1 through MAC_HASH7_1 * Registers: MAC_HASH0_2 through MAC_HASH7_2 diff --git a/arch/mips/include/asm/siginfo.h b/arch/mips/include/asm/siginfo.h index 1ca64b4d33d..20ebeb875ee 100644 --- a/arch/mips/include/asm/siginfo.h +++ b/arch/mips/include/asm/siginfo.h @@ -101,7 +101,7 @@ typedef struct siginfo { /* * si_code values - * Again these have been choosen to be IRIX compatible. + * Again these have been chosen to be IRIX compatible. */ #undef SI_ASYNCIO #undef SI_TIMER diff --git a/arch/mips/include/asm/sn/klconfig.h b/arch/mips/include/asm/sn/klconfig.h index 09e590daca1..fe02900b930 100644 --- a/arch/mips/include/asm/sn/klconfig.h +++ b/arch/mips/include/asm/sn/klconfig.h @@ -78,7 +78,7 @@ typedef s32 klconf_off_t; */ #define MAX_SLOTS_PER_NODE (1 + 2 + 6 + 2) -/* XXX if each node is guranteed to have some memory */ +/* XXX if each node is guaranteed to have some memory */ #define MAX_PCI_DEVS 8 @@ -539,7 +539,7 @@ typedef struct klinfo_s { /* Generic info */ #define KLSTRUCT_IOC3_TTY 24 /* Early Access IO proms are compatible - only with KLSTRUCT values upto 24. */ + only with KLSTRUCT values up to 24. */ #define KLSTRUCT_FIBERCHANNEL 25 #define KLSTRUCT_MOD_SERIAL_NUM 26 diff --git a/arch/mips/include/asm/sn/sn0/hubio.h b/arch/mips/include/asm/sn/sn0/hubio.h index 31c76c021bb..46286d8302a 100644 --- a/arch/mips/include/asm/sn/sn0/hubio.h +++ b/arch/mips/include/asm/sn/sn0/hubio.h @@ -622,7 +622,7 @@ typedef union h1_icrbb_u { */ #define IIO_ICRB_PROC0 0 /* Source of request is Proc 0 */ #define IIO_ICRB_PROC1 1 /* Source of request is Proc 1 */ -#define IIO_ICRB_GB_REQ 2 /* Source is Guranteed BW request */ +#define IIO_ICRB_GB_REQ 2 /* Source is Guaranteed BW request */ #define IIO_ICRB_IO_REQ 3 /* Source is Normal IO request */ /* diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h index 396e402fbe2..ca61e846ab0 100644 --- a/arch/mips/include/asm/spinlock.h +++ b/arch/mips/include/asm/spinlock.h @@ -245,16 +245,16 @@ static inline void arch_read_lock(arch_rwlock_t *rw) __asm__ __volatile__( " .set noreorder # arch_read_lock \n" "1: ll %1, %2 \n" - " bltz %1, 2f \n" + " bltz %1, 3f \n" " addu %1, 1 \n" - " sc %1, %0 \n" + "2: sc %1, %0 \n" " beqz %1, 1b \n" " nop \n" " .subsection 2 \n" - "2: ll %1, %2 \n" - " bltz %1, 2b \n" + "3: ll %1, %2 \n" + " bltz %1, 3b \n" " addu %1, 1 \n" - " b 1b \n" + " b 2b \n" " nop \n" " .previous \n" " .set reorder \n" @@ -324,16 +324,16 @@ static inline void arch_write_lock(arch_rwlock_t *rw) __asm__ __volatile__( " .set noreorder # arch_write_lock \n" "1: ll %1, %2 \n" - " bnez %1, 2f \n" + " bnez %1, 3f \n" " lui %1, 0x8000 \n" - " sc %1, %0 \n" - " beqz %1, 2f \n" + "2: sc %1, %0 \n" + " beqz %1, 3f \n" " nop \n" " .subsection 2 \n" - "2: ll %1, %2 \n" - " bnez %1, 2b \n" + "3: ll %1, %2 \n" + " bnez %1, 3b \n" " lui %1, 0x8000 \n" - " b 1b \n" + " b 2b \n" " nop \n" " .previous \n" " .set reorder \n" diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index 58730c5ce4b..b4ba2449444 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -346,7 +346,7 @@ * we can't dispatch it directly without trashing * some registers, so we'll try to detect this unlikely * case and program a software interrupt in the VPE, - * as would be done for a cross-VPE IPI. To accomodate + * as would be done for a cross-VPE IPI. To accommodate * the handling of that case, we're doing a DVPE instead * of just a DMT here to protect against other threads. * This is a lot of cruft to cover a tiny window. diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index d309556cacf..d71160de4d1 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -88,9 +88,11 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR #ifdef CONFIG_DEBUG_STACK_USAGE -#define alloc_thread_info(tsk) kzalloc(THREAD_SIZE, GFP_KERNEL) +#define alloc_thread_info_node(tsk, node) \ + kzalloc_node(THREAD_SIZE, GFP_KERNEL, node) #else -#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL) +#define alloc_thread_info_node(tsk, node) \ + kmalloc_node(THREAD_SIZE, GFP_KERNEL, node) #endif #define free_thread_info(info) kfree(info) diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h index 544a2854598..533812b6188 100644 --- a/arch/mips/include/asm/types.h +++ b/arch/mips/include/asm/types.h @@ -33,14 +33,6 @@ typedef unsigned short umode_t; #ifdef __KERNEL__ #ifndef __ASSEMBLY__ -#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \ - || defined(CONFIG_64BIT) -typedef u64 dma_addr_t; -#else -typedef u32 dma_addr_t; -#endif -typedef u64 dma64_addr_t; - /* * Don't use phys_t. You've been warned. */ diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h index 550725b881d..fa2e37ea2be 100644 --- a/arch/mips/include/asm/unistd.h +++ b/arch/mips/include/asm/unistd.h @@ -359,16 +359,20 @@ #define __NR_fanotify_init (__NR_Linux + 336) #define __NR_fanotify_mark (__NR_Linux + 337) #define __NR_prlimit64 (__NR_Linux + 338) +#define __NR_name_to_handle_at (__NR_Linux + 339) +#define __NR_open_by_handle_at (__NR_Linux + 340) +#define __NR_clock_adjtime (__NR_Linux + 341) +#define __NR_syncfs (__NR_Linux + 342) /* * Offset of the last Linux o32 flavoured syscall */ -#define __NR_Linux_syscalls 338 +#define __NR_Linux_syscalls 342 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ #define __NR_O32_Linux 4000 -#define __NR_O32_Linux_syscalls 338 +#define __NR_O32_Linux_syscalls 342 #if _MIPS_SIM == _MIPS_SIM_ABI64 @@ -674,16 +678,20 @@ #define __NR_fanotify_init (__NR_Linux + 295) #define __NR_fanotify_mark (__NR_Linux + 296) #define __NR_prlimit64 (__NR_Linux + 297) +#define __NR_name_to_handle_at (__NR_Linux + 298) +#define __NR_open_by_handle_at (__NR_Linux + 299) +#define __NR_clock_adjtime (__NR_Linux + 300) +#define __NR_syncfs (__NR_Linux + 301) /* * Offset of the last Linux 64-bit flavoured syscall */ -#define __NR_Linux_syscalls 297 +#define __NR_Linux_syscalls 301 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ #define __NR_64_Linux 5000 -#define __NR_64_Linux_syscalls 297 +#define __NR_64_Linux_syscalls 301 #if _MIPS_SIM == _MIPS_SIM_NABI32 @@ -994,16 +1002,20 @@ #define __NR_fanotify_init (__NR_Linux + 300) #define __NR_fanotify_mark (__NR_Linux + 301) #define __NR_prlimit64 (__NR_Linux + 302) +#define __NR_name_to_handle_at (__NR_Linux + 303) +#define __NR_open_by_handle_at (__NR_Linux + 304) +#define __NR_clock_adjtime (__NR_Linux + 305) +#define __NR_syncfs (__NR_Linux + 306) /* * Offset of the last N32 flavoured syscall */ -#define __NR_Linux_syscalls 302 +#define __NR_Linux_syscalls 306 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ #define __NR_N32_Linux 6000 -#define __NR_N32_Linux_syscalls 302 +#define __NR_N32_Linux_syscalls 306 #ifdef __KERNEL__ diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h index 22361d5e3bf..fa133c1bc1f 100644 --- a/arch/mips/include/asm/war.h +++ b/arch/mips/include/asm/war.h @@ -227,7 +227,7 @@ #endif /* - * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that + * On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that * may cause ll / sc and lld / scd sequences to execute non-atomically. */ #ifndef R10000_LLSC_WAR diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c index 35b3e2f0af0..260df475094 100644 --- a/arch/mips/jazz/irq.c +++ b/arch/mips/jazz/irq.c @@ -23,9 +23,9 @@ static DEFINE_RAW_SPINLOCK(r4030_lock); -static void enable_r4030_irq(unsigned int irq) +static void enable_r4030_irq(struct irq_data *d) { - unsigned int mask = 1 << (irq - JAZZ_IRQ_START); + unsigned int mask = 1 << (d->irq - JAZZ_IRQ_START); unsigned long flags; raw_spin_lock_irqsave(&r4030_lock, flags); @@ -34,9 +34,9 @@ static void enable_r4030_irq(unsigned int irq) raw_spin_unlock_irqrestore(&r4030_lock, flags); } -void disable_r4030_irq(unsigned int irq) +void disable_r4030_irq(struct irq_data *d) { - unsigned int mask = ~(1 << (irq - JAZZ_IRQ_START)); + unsigned int mask = ~(1 << (d->irq - JAZZ_IRQ_START)); unsigned long flags; raw_spin_lock_irqsave(&r4030_lock, flags); @@ -47,10 +47,8 @@ void disable_r4030_irq(unsigned int irq) static struct irq_chip r4030_irq_type = { .name = "R4030", - .ack = disable_r4030_irq, - .mask = disable_r4030_irq, - .mask_ack = disable_r4030_irq, - .unmask = enable_r4030_irq, + .irq_mask = disable_r4030_irq, + .irq_unmask = enable_r4030_irq, }; void __init init_r4030_ints(void) @@ -58,7 +56,7 @@ void __init init_r4030_ints(void) int i; for (i = JAZZ_IRQ_START; i <= JAZZ_IRQ_END; i++) - set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &r4030_irq_type, handle_level_irq); r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */ diff --git a/arch/mips/jazz/jazzdma.c b/arch/mips/jazz/jazzdma.c index 9ce9f64cb76..2d8e447cb82 100644 --- a/arch/mips/jazz/jazzdma.c +++ b/arch/mips/jazz/jazzdma.c @@ -211,7 +211,7 @@ EXPORT_SYMBOL(vdma_free); */ int vdma_remap(unsigned long laddr, unsigned long paddr, unsigned long size) { - int first, pages, npages; + int first, pages; if (laddr > 0xffffff) { if (vdma_debug) @@ -228,8 +228,7 @@ int vdma_remap(unsigned long laddr, unsigned long paddr, unsigned long size) return -EINVAL; /* invalid physical address */ } - npages = pages = - (((paddr & (VDMA_PAGESIZE - 1)) + size) >> 12) + 1; + pages = (((paddr & (VDMA_PAGESIZE - 1)) + size) >> 12) + 1; first = laddr >> 12; if (vdma_debug) printk("vdma_remap: first=%x, pages=%x\n", first, pages); diff --git a/arch/mips/jz4740/Makefile b/arch/mips/jz4740/Makefile index a604eaeb6c0..a9dff332125 100644 --- a/arch/mips/jz4740/Makefile +++ b/arch/mips/jz4740/Makefile @@ -17,4 +17,4 @@ obj-$(CONFIG_JZ4740_QI_LB60) += board-qi_lb60.o obj-$(CONFIG_PM) += pm.o -EXTRA_CFLAGS += -Werror -Wall +ccflags-y := -Werror -Wall diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c index 2c0e107966a..c3b04be3fb2 100644 --- a/arch/mips/jz4740/board-qi_lb60.c +++ b/arch/mips/jz4740/board-qi_lb60.c @@ -23,6 +23,7 @@ #include <linux/spi/spi_gpio.h> #include <linux/power_supply.h> #include <linux/power/jz4740-battery.h> +#include <linux/power/gpio-charger.h> #include <asm/mach-jz4740/jz4740_fb.h> #include <asm/mach-jz4740/jz4740_mmc.h> @@ -49,14 +50,14 @@ static bool is_avt2; /* NAND */ static struct nand_ecclayout qi_lb60_ecclayout_1gb = { -/* .eccbytes = 36, + .eccbytes = 36, .eccpos = { 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41 - },*/ + }, .oobfree = { { .offset = 2, .length = 4 }, { .offset = 42, .length = 22 } @@ -64,7 +65,7 @@ static struct nand_ecclayout qi_lb60_ecclayout_1gb = { }; /* Early prototypes of the QI LB60 had only 1GB of NAND. - * In order to support these devices aswell the partition and ecc layout is + * In order to support these devices as well the partition and ecc layout is * initialized depending on the NAND size */ static struct mtd_partition qi_lb60_partitions_1gb[] = { { @@ -85,7 +86,7 @@ static struct mtd_partition qi_lb60_partitions_1gb[] = { }; static struct nand_ecclayout qi_lb60_ecclayout_2gb = { -/* .eccbytes = 72, + .eccbytes = 72, .eccpos = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, @@ -96,7 +97,7 @@ static struct nand_ecclayout qi_lb60_ecclayout_2gb = { 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83 - },*/ + }, .oobfree = { { .offset = 2, .length = 10 }, { .offset = 84, .length = 44 }, @@ -396,6 +397,28 @@ static struct platform_device qi_lb60_pwm_beeper = { }, }; +/* charger */ +static char *qi_lb60_batteries[] = { + "battery", +}; + +static struct gpio_charger_platform_data qi_lb60_charger_pdata = { + .name = "usb", + .type = POWER_SUPPLY_TYPE_USB, + .gpio = JZ_GPIO_PORTD(28), + .gpio_active_low = 1, + .supplied_to = qi_lb60_batteries, + .num_supplicants = ARRAY_SIZE(qi_lb60_batteries), +}; + +static struct platform_device qi_lb60_charger_device = { + .name = "gpio-charger", + .dev = { + .platform_data = &qi_lb60_charger_pdata, + }, +}; + + static struct platform_device *jz_platform_devices[] __initdata = { &jz4740_udc_device, &jz4740_mmc_device, @@ -410,12 +433,13 @@ static struct platform_device *jz_platform_devices[] __initdata = { &jz4740_adc_device, &qi_lb60_gpio_keys, &qi_lb60_pwm_beeper, + &qi_lb60_charger_device, }; static void __init board_gpio_setup(void) { /* We only need to enable/disable pullup here for pins used in generic - * drivers. Everything else is done by the drivers themselfs. */ + * drivers. Everything else is done by the drivers themselves. */ jz_gpio_disable_pullup(QI_LB60_GPIO_SD_VCC_EN_N); jz_gpio_disable_pullup(QI_LB60_GPIO_SD_CD); } diff --git a/arch/mips/jz4740/dma.c b/arch/mips/jz4740/dma.c index 5ebe75a6835..d7feb898692 100644 --- a/arch/mips/jz4740/dma.c +++ b/arch/mips/jz4740/dma.c @@ -242,9 +242,7 @@ EXPORT_SYMBOL_GPL(jz4740_dma_get_residue); static void jz4740_dma_chan_irq(struct jz4740_dma_chan *dma) { - uint32_t status; - - status = jz4740_dma_read(JZ_REG_DMA_STATUS_CTRL(dma->id)); + (void) jz4740_dma_read(JZ_REG_DMA_STATUS_CTRL(dma->id)); jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0, JZ_DMA_STATUS_CTRL_ENABLE | JZ_DMA_STATUS_CTRL_TRANSFER_DONE); diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c index 88e6aeda5bf..73031f7fc82 100644 --- a/arch/mips/jz4740/gpio.c +++ b/arch/mips/jz4740/gpio.c @@ -86,7 +86,6 @@ struct jz_gpio_chip { spinlock_t lock; struct gpio_chip gpio_chip; - struct irq_chip irq_chip; struct sys_device sysdev; }; @@ -102,9 +101,9 @@ static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *g return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip); } -static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(unsigned int irq) +static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(struct irq_data *data) { - return get_irq_chip_data(irq); + return irq_data_get_irq_chip_data(data); } static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg) @@ -307,7 +306,7 @@ static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc) uint32_t flag; unsigned int gpio_irq; unsigned int gpio_bank; - struct jz_gpio_chip *chip = get_irq_desc_data(desc); + struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc); gpio_bank = JZ4740_IRQ_GPIO0 - irq; @@ -325,62 +324,52 @@ static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc) generic_handle_irq(gpio_irq); }; -static inline void jz_gpio_set_irq_bit(unsigned int irq, unsigned int reg) +static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg) { - struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); - writel(IRQ_TO_BIT(irq), chip->base + reg); + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); + writel(IRQ_TO_BIT(data->irq), chip->base + reg); } -static void jz_gpio_irq_mask(unsigned int irq) +static void jz_gpio_irq_mask(struct irq_data *data) { - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_SET); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_MASK_SET); }; -static void jz_gpio_irq_unmask(unsigned int irq) +static void jz_gpio_irq_unmask(struct irq_data *data) { - struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); - jz_gpio_check_trigger_both(chip, irq); + jz_gpio_check_trigger_both(chip, data->irq); - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_MASK_CLEAR); }; /* TODO: Check if function is gpio */ -static unsigned int jz_gpio_irq_startup(unsigned int irq) +static unsigned int jz_gpio_irq_startup(struct irq_data *data) { - struct irq_desc *desc = irq_to_desc(irq); - - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_SET); - - desc->status &= ~IRQ_MASKED; - jz_gpio_irq_unmask(irq); - + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET); + jz_gpio_irq_unmask(data); return 0; } -static void jz_gpio_irq_shutdown(unsigned int irq) +static void jz_gpio_irq_shutdown(struct irq_data *data) { - struct irq_desc *desc = irq_to_desc(irq); - - jz_gpio_irq_mask(irq); - desc->status |= IRQ_MASKED; + jz_gpio_irq_mask(data); /* Set direction to input */ - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR); - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR); } -static void jz_gpio_irq_ack(unsigned int irq) +static void jz_gpio_irq_ack(struct irq_data *data) { - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_FLAG_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_FLAG_CLEAR); }; -static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) +static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type) { - struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); - struct irq_desc *desc = irq_to_desc(irq); - - jz_gpio_irq_mask(irq); + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); + unsigned int irq = data->irq; if (flow_type == IRQ_TYPE_EDGE_BOTH) { uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN); @@ -395,45 +384,54 @@ static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) switch (flow_type) { case IRQ_TYPE_EDGE_RISING: - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET); - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET); break; case IRQ_TYPE_EDGE_FALLING: - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR); - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET); break; case IRQ_TYPE_LEVEL_HIGH: - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET); - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR); break; case IRQ_TYPE_LEVEL_LOW: - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR); - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR); break; default: return -EINVAL; } - if (!(desc->status & IRQ_MASKED)) - jz_gpio_irq_unmask(irq); - return 0; } -static int jz_gpio_irq_set_wake(unsigned int irq, unsigned int on) +static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on) { - struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); spin_lock(&chip->lock); if (on) - chip->wakeup |= IRQ_TO_BIT(irq); + chip->wakeup |= IRQ_TO_BIT(data->irq); else - chip->wakeup &= ~IRQ_TO_BIT(irq); + chip->wakeup &= ~IRQ_TO_BIT(data->irq); spin_unlock(&chip->lock); - set_irq_wake(chip->irq, on); + irq_set_irq_wake(chip->irq, on); return 0; } +static struct irq_chip jz_gpio_irq_chip = { + .name = "GPIO", + .irq_mask = jz_gpio_irq_mask, + .irq_unmask = jz_gpio_irq_unmask, + .irq_ack = jz_gpio_irq_ack, + .irq_startup = jz_gpio_irq_startup, + .irq_shutdown = jz_gpio_irq_shutdown, + .irq_set_type = jz_gpio_irq_set_type, + .irq_set_wake = jz_gpio_irq_set_wake, + .flags = IRQCHIP_SET_TYPE_MASKED, +}; + /* * This lock class tells lockdep that GPIO irqs are in a different * category than their parents, so it won't report false recursion. @@ -452,16 +450,6 @@ static struct lock_class_key gpio_lock_class; .base = JZ4740_GPIO_BASE_ ## _bank, \ .ngpio = JZ4740_GPIO_NUM_ ## _bank, \ }, \ - .irq_chip = { \ - .name = "GPIO Bank " # _bank, \ - .mask = jz_gpio_irq_mask, \ - .unmask = jz_gpio_irq_unmask, \ - .ack = jz_gpio_irq_ack, \ - .startup = jz_gpio_irq_startup, \ - .shutdown = jz_gpio_irq_shutdown, \ - .set_type = jz_gpio_irq_set_type, \ - .set_wake = jz_gpio_irq_set_wake, \ - }, \ } static struct jz_gpio_chip jz4740_gpio_chips[] = { @@ -522,13 +510,14 @@ static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id) gpiochip_add(&chip->gpio_chip); chip->irq = JZ4740_IRQ_INTC_GPIO(id); - set_irq_data(chip->irq, chip); - set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler); + irq_set_handler_data(chip->irq, chip); + irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler); for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) { - lockdep_set_class(&irq_desc[irq].lock, &gpio_lock_class); - set_irq_chip_data(irq, chip); - set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq); + irq_set_lockdep_class(irq, &gpio_lock_class); + irq_set_chip_data(irq, chip); + irq_set_chip_and_handler(irq, &jz_gpio_irq_chip, + handle_level_irq); } return 0; diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c index 7d33ff83580..d82c0c430e0 100644 --- a/arch/mips/jz4740/irq.c +++ b/arch/mips/jz4740/irq.c @@ -43,32 +43,37 @@ static uint32_t jz_intc_saved; #define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE) -static void intc_irq_unmask(unsigned int irq) +static inline unsigned long intc_irq_bit(struct irq_data *data) { - writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK); + return (unsigned long)irq_data_get_irq_chip_data(data); } -static void intc_irq_mask(unsigned int irq) +static void intc_irq_unmask(struct irq_data *data) { - writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK); + writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_CLEAR_MASK); } -static int intc_irq_set_wake(unsigned int irq, unsigned int on) +static void intc_irq_mask(struct irq_data *data) +{ + writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_SET_MASK); +} + +static int intc_irq_set_wake(struct irq_data *data, unsigned int on) { if (on) - jz_intc_wakeup |= IRQ_BIT(irq); + jz_intc_wakeup |= intc_irq_bit(data); else - jz_intc_wakeup &= ~IRQ_BIT(irq); + jz_intc_wakeup &= ~intc_irq_bit(data); return 0; } static struct irq_chip intc_irq_type = { .name = "INTC", - .mask = intc_irq_mask, - .mask_ack = intc_irq_mask, - .unmask = intc_irq_unmask, - .set_wake = intc_irq_set_wake, + .irq_mask = intc_irq_mask, + .irq_mask_ack = intc_irq_mask, + .irq_unmask = intc_irq_unmask, + .irq_set_wake = intc_irq_set_wake, }; static irqreturn_t jz4740_cascade(int irq, void *data) @@ -95,9 +100,12 @@ void __init arch_init_irq(void) jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14); + /* Mask all irqs */ + writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK); + for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) { - intc_irq_mask(i); - set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq); + irq_set_chip_data(i, (void *)IRQ_BIT(i)); + irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq); } setup_irq(2, &jz4740_cascade_action); diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c index fe01678d94f..eaa853a54af 100644 --- a/arch/mips/jz4740/time.c +++ b/arch/mips/jz4740/time.c @@ -89,7 +89,7 @@ static int jz4740_clockevent_set_next(unsigned long evt, static struct clock_event_device jz4740_clockevent = { .name = "jz4740-timer", - .features = CLOCK_EVT_FEAT_PERIODIC, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .set_next_event = jz4740_clockevent_set_next, .set_mode = jz4740_clockevent_set_mode, .rating = 200, diff --git a/arch/mips/jz4740/timer.c b/arch/mips/jz4740/timer.c index b2c01512905..654d5c3900b 100644 --- a/arch/mips/jz4740/timer.c +++ b/arch/mips/jz4740/timer.c @@ -27,11 +27,13 @@ void jz4740_timer_enable_watchdog(void) { writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); } +EXPORT_SYMBOL_GPL(jz4740_timer_enable_watchdog); void jz4740_timer_disable_watchdog(void) { writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); } +EXPORT_SYMBOL_GPL(jz4740_timer_disable_watchdog); void __init jz4740_timer_init(void) { diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c index b8bb8ba6086..f305ca14351 100644 --- a/arch/mips/kernel/cpu-bugs64.c +++ b/arch/mips/kernel/cpu-bugs64.c @@ -73,7 +73,7 @@ static inline void mult_sh_align_mod(long *v1, long *v2, long *w, : "0" (5), "1" (8), "2" (5)); align_mod(align, mod); /* - * The trailing nop is needed to fullfill the two-instruction + * The trailing nop is needed to fulfill the two-instruction * requirement between reading hi/lo and staring a mult/div. * Leaving it out may cause gas insert a nop itself breaking * the desired alignment of the next chunk. diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c index 94ca2b018af..feb8021a305 100644 --- a/arch/mips/kernel/ftrace.c +++ b/arch/mips/kernel/ftrace.c @@ -23,6 +23,7 @@ #define JAL 0x0c000000 /* jump & link: ip --> ra, jump to target */ #define ADDR_MASK 0x03ffffff /* op_code|addr : 31...26|25 ....0 */ +#define JUMP_RANGE_MASK ((1UL << 28) - 1) #define INSN_NOP 0x00000000 /* nop */ #define INSN_JAL(addr) \ @@ -44,12 +45,12 @@ static inline void ftrace_dyn_arch_init_insns(void) /* jal (ftrace_caller + 8), jump over the first two instruction */ buf = (u32 *)&insn_jal_ftrace_caller; - uasm_i_jal(&buf, (FTRACE_ADDR + 8)); + uasm_i_jal(&buf, (FTRACE_ADDR + 8) & JUMP_RANGE_MASK); #ifdef CONFIG_FUNCTION_GRAPH_TRACER /* j ftrace_graph_caller */ buf = (u32 *)&insn_j_ftrace_graph_caller; - uasm_i_j(&buf, (unsigned long)ftrace_graph_caller); + uasm_i_j(&buf, (unsigned long)ftrace_graph_caller & JUMP_RANGE_MASK); #endif } diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index c58176cc796..c018696765d 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c @@ -31,19 +31,19 @@ static int i8259A_auto_eoi = -1; DEFINE_RAW_SPINLOCK(i8259A_lock); -static void disable_8259A_irq(unsigned int irq); -static void enable_8259A_irq(unsigned int irq); -static void mask_and_ack_8259A(unsigned int irq); +static void disable_8259A_irq(struct irq_data *d); +static void enable_8259A_irq(struct irq_data *d); +static void mask_and_ack_8259A(struct irq_data *d); static void init_8259A(int auto_eoi); static struct irq_chip i8259A_chip = { - .name = "XT-PIC", - .mask = disable_8259A_irq, - .disable = disable_8259A_irq, - .unmask = enable_8259A_irq, - .mask_ack = mask_and_ack_8259A, + .name = "XT-PIC", + .irq_mask = disable_8259A_irq, + .irq_disable = disable_8259A_irq, + .irq_unmask = enable_8259A_irq, + .irq_mask_ack = mask_and_ack_8259A, #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF - .set_affinity = plat_set_irq_affinity, + .irq_set_affinity = plat_set_irq_affinity, #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ }; @@ -59,12 +59,11 @@ static unsigned int cached_irq_mask = 0xffff; #define cached_master_mask (cached_irq_mask) #define cached_slave_mask (cached_irq_mask >> 8) -static void disable_8259A_irq(unsigned int irq) +static void disable_8259A_irq(struct irq_data *d) { - unsigned int mask; + unsigned int mask, irq = d->irq - I8259A_IRQ_BASE; unsigned long flags; - irq -= I8259A_IRQ_BASE; mask = 1 << irq; raw_spin_lock_irqsave(&i8259A_lock, flags); cached_irq_mask |= mask; @@ -75,12 +74,11 @@ static void disable_8259A_irq(unsigned int irq) raw_spin_unlock_irqrestore(&i8259A_lock, flags); } -static void enable_8259A_irq(unsigned int irq) +static void enable_8259A_irq(struct irq_data *d) { - unsigned int mask; + unsigned int mask, irq = d->irq - I8259A_IRQ_BASE; unsigned long flags; - irq -= I8259A_IRQ_BASE; mask = ~(1 << irq); raw_spin_lock_irqsave(&i8259A_lock, flags); cached_irq_mask &= mask; @@ -112,7 +110,7 @@ int i8259A_irq_pending(unsigned int irq) void make_8259A_irq(unsigned int irq) { disable_irq_nosync(irq); - set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq); + irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq); enable_irq(irq); } @@ -145,12 +143,11 @@ static inline int i8259A_irq_real(unsigned int irq) * first, _then_ send the EOI, and the order of EOI * to the two 8259s is important! */ -static void mask_and_ack_8259A(unsigned int irq) +static void mask_and_ack_8259A(struct irq_data *d) { - unsigned int irqmask; + unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE; unsigned long flags; - irq -= I8259A_IRQ_BASE; irqmask = 1 << irq; raw_spin_lock_irqsave(&i8259A_lock, flags); /* @@ -290,9 +287,9 @@ static void init_8259A(int auto_eoi) * In AEOI mode we just have to mask the interrupt * when acking. */ - i8259A_chip.mask_ack = disable_8259A_irq; + i8259A_chip.irq_mask_ack = disable_8259A_irq; else - i8259A_chip.mask_ack = mask_and_ack_8259A; + i8259A_chip.irq_mask_ack = mask_and_ack_8259A; udelay(100); /* wait for 8259A to initialize */ @@ -339,8 +336,8 @@ void __init init_i8259_irqs(void) init_8259A(0); for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) { - set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq); - set_irq_probe(i); + irq_set_chip_and_handler(i, &i8259A_chip, handle_level_irq); + irq_set_probe(i); } setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2); diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c index 1774271af84..0c527f65219 100644 --- a/arch/mips/kernel/irq-gic.c +++ b/arch/mips/kernel/irq-gic.c @@ -87,17 +87,10 @@ unsigned int gic_get_int(void) return i; } -static unsigned int gic_irq_startup(unsigned int irq) +static void gic_irq_ack(struct irq_data *d) { - irq -= _irqbase; - pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); - GIC_SET_INTR_MASK(irq); - return 0; -} + unsigned int irq = d->irq - _irqbase; -static void gic_irq_ack(unsigned int irq) -{ - irq -= _irqbase; pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); GIC_CLR_INTR_MASK(irq); @@ -105,16 +98,16 @@ static void gic_irq_ack(unsigned int irq) GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq); } -static void gic_mask_irq(unsigned int irq) +static void gic_mask_irq(struct irq_data *d) { - irq -= _irqbase; + unsigned int irq = d->irq - _irqbase; pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); GIC_CLR_INTR_MASK(irq); } -static void gic_unmask_irq(unsigned int irq) +static void gic_unmask_irq(struct irq_data *d) { - irq -= _irqbase; + unsigned int irq = d->irq - _irqbase; pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); GIC_SET_INTR_MASK(irq); } @@ -123,13 +116,14 @@ static void gic_unmask_irq(unsigned int irq) static DEFINE_SPINLOCK(gic_lock); -static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask) +static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, + bool force) { + unsigned int irq = d->irq - _irqbase; cpumask_t tmp = CPU_MASK_NONE; unsigned long flags; int i; - irq -= _irqbase; pr_debug("%s(%d) called\n", __func__, irq); cpumask_and(&tmp, cpumask, cpu_online_mask); if (cpus_empty(tmp)) @@ -147,23 +141,22 @@ static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask) set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask); } - cpumask_copy(irq_desc[irq].affinity, cpumask); + cpumask_copy(d->affinity, cpumask); spin_unlock_irqrestore(&gic_lock, flags); - return 0; + return IRQ_SET_MASK_OK_NOCOPY; } #endif static struct irq_chip gic_irq_controller = { - .name = "MIPS GIC", - .startup = gic_irq_startup, - .ack = gic_irq_ack, - .mask = gic_mask_irq, - .mask_ack = gic_mask_irq, - .unmask = gic_unmask_irq, - .eoi = gic_unmask_irq, + .name = "MIPS GIC", + .irq_ack = gic_irq_ack, + .irq_mask = gic_mask_irq, + .irq_mask_ack = gic_mask_irq, + .irq_unmask = gic_unmask_irq, + .irq_eoi = gic_unmask_irq, #ifdef CONFIG_SMP - .set_affinity = gic_set_affinity, + .irq_set_affinity = gic_set_affinity, #endif }; @@ -236,7 +229,7 @@ static void __init gic_basic_init(int numintrs, int numvpes, vpe_local_setup(numvpes); for (i = _irqbase; i < (_irqbase + numintrs); i++) - set_irq_chip(i, &gic_irq_controller); + irq_set_chip(i, &gic_irq_controller); } void __init gic_init(unsigned long gic_base_addr, diff --git a/arch/mips/kernel/irq-gt641xx.c b/arch/mips/kernel/irq-gt641xx.c index 42ef81461bf..883fc6cead3 100644 --- a/arch/mips/kernel/irq-gt641xx.c +++ b/arch/mips/kernel/irq-gt641xx.c @@ -29,64 +29,64 @@ static DEFINE_RAW_SPINLOCK(gt641xx_irq_lock); -static void ack_gt641xx_irq(unsigned int irq) +static void ack_gt641xx_irq(struct irq_data *d) { unsigned long flags; u32 cause; raw_spin_lock_irqsave(>641xx_irq_lock, flags); cause = GT_READ(GT_INTRCAUSE_OFS); - cause &= ~GT641XX_IRQ_TO_BIT(irq); + cause &= ~GT641XX_IRQ_TO_BIT(d->irq); GT_WRITE(GT_INTRCAUSE_OFS, cause); raw_spin_unlock_irqrestore(>641xx_irq_lock, flags); } -static void mask_gt641xx_irq(unsigned int irq) +static void mask_gt641xx_irq(struct irq_data *d) { unsigned long flags; u32 mask; raw_spin_lock_irqsave(>641xx_irq_lock, flags); mask = GT_READ(GT_INTRMASK_OFS); - mask &= ~GT641XX_IRQ_TO_BIT(irq); + mask &= ~GT641XX_IRQ_TO_BIT(d->irq); GT_WRITE(GT_INTRMASK_OFS, mask); raw_spin_unlock_irqrestore(>641xx_irq_lock, flags); } -static void mask_ack_gt641xx_irq(unsigned int irq) +static void mask_ack_gt641xx_irq(struct irq_data *d) { unsigned long flags; u32 cause, mask; raw_spin_lock_irqsave(>641xx_irq_lock, flags); mask = GT_READ(GT_INTRMASK_OFS); - mask &= ~GT641XX_IRQ_TO_BIT(irq); + mask &= ~GT641XX_IRQ_TO_BIT(d->irq); GT_WRITE(GT_INTRMASK_OFS, mask); cause = GT_READ(GT_INTRCAUSE_OFS); - cause &= ~GT641XX_IRQ_TO_BIT(irq); + cause &= ~GT641XX_IRQ_TO_BIT(d->irq); GT_WRITE(GT_INTRCAUSE_OFS, cause); raw_spin_unlock_irqrestore(>641xx_irq_lock, flags); } -static void unmask_gt641xx_irq(unsigned int irq) +static void unmask_gt641xx_irq(struct irq_data *d) { unsigned long flags; u32 mask; raw_spin_lock_irqsave(>641xx_irq_lock, flags); mask = GT_READ(GT_INTRMASK_OFS); - mask |= GT641XX_IRQ_TO_BIT(irq); + mask |= GT641XX_IRQ_TO_BIT(d->irq); GT_WRITE(GT_INTRMASK_OFS, mask); raw_spin_unlock_irqrestore(>641xx_irq_lock, flags); } static struct irq_chip gt641xx_irq_chip = { .name = "GT641xx", - .ack = ack_gt641xx_irq, - .mask = mask_gt641xx_irq, - .mask_ack = mask_ack_gt641xx_irq, - .unmask = unmask_gt641xx_irq, + .irq_ack = ack_gt641xx_irq, + .irq_mask = mask_gt641xx_irq, + .irq_mask_ack = mask_ack_gt641xx_irq, + .irq_unmask = unmask_gt641xx_irq, }; void gt641xx_irq_dispatch(void) @@ -126,6 +126,6 @@ void __init gt641xx_irq_init(void) * bit31: logical or of bits[25:1]. */ for (i = 1; i < 30; i++) - set_irq_chip_and_handler(GT641XX_IRQ_BASE + i, - >641xx_irq_chip, handle_level_irq); + irq_set_chip_and_handler(GT641XX_IRQ_BASE + i, + >641xx_irq_chip, handle_level_irq); } diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index 6a8cd28133d..0c6afeed89d 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c @@ -28,8 +28,10 @@ static unsigned long _icctrl_msc; static unsigned int irq_base; /* mask off an interrupt */ -static inline void mask_msc_irq(unsigned int irq) +static inline void mask_msc_irq(struct irq_data *d) { + unsigned int irq = d->irq; + if (irq < (irq_base + 32)) MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base)); else @@ -37,8 +39,10 @@ static inline void mask_msc_irq(unsigned int irq) } /* unmask an interrupt */ -static inline void unmask_msc_irq(unsigned int irq) +static inline void unmask_msc_irq(struct irq_data *d) { + unsigned int irq = d->irq; + if (irq < (irq_base + 32)) MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base)); else @@ -48,9 +52,11 @@ static inline void unmask_msc_irq(unsigned int irq) /* * Masks and ACKs an IRQ */ -static void level_mask_and_ack_msc_irq(unsigned int irq) +static void level_mask_and_ack_msc_irq(struct irq_data *d) { - mask_msc_irq(irq); + unsigned int irq = d->irq; + + mask_msc_irq(d); if (!cpu_has_veic) MSCIC_WRITE(MSC01_IC_EOI, 0); /* This actually needs to be a call into platform code */ @@ -60,9 +66,11 @@ static void level_mask_and_ack_msc_irq(unsigned int irq) /* * Masks and ACKs an IRQ */ -static void edge_mask_and_ack_msc_irq(unsigned int irq) +static void edge_mask_and_ack_msc_irq(struct irq_data *d) { - mask_msc_irq(irq); + unsigned int irq = d->irq; + + mask_msc_irq(d); if (!cpu_has_veic) MSCIC_WRITE(MSC01_IC_EOI, 0); else { @@ -75,15 +83,6 @@ static void edge_mask_and_ack_msc_irq(unsigned int irq) } /* - * End IRQ processing - */ -static void end_msc_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - unmask_msc_irq(irq); -} - -/* * Interrupt handler for interrupts coming from SOC-it. */ void ll_msc_irq(void) @@ -107,22 +106,20 @@ static void msc_bind_eic_interrupt(int irq, int set) static struct irq_chip msc_levelirq_type = { .name = "SOC-it-Level", - .ack = level_mask_and_ack_msc_irq, - .mask = mask_msc_irq, - .mask_ack = level_mask_and_ack_msc_irq, - .unmask = unmask_msc_irq, - .eoi = unmask_msc_irq, - .end = end_msc_irq, + .irq_ack = level_mask_and_ack_msc_irq, + .irq_mask = mask_msc_irq, + .irq_mask_ack = level_mask_and_ack_msc_irq, + .irq_unmask = unmask_msc_irq, + .irq_eoi = unmask_msc_irq, }; static struct irq_chip msc_edgeirq_type = { .name = "SOC-it-Edge", - .ack = edge_mask_and_ack_msc_irq, - .mask = mask_msc_irq, - .mask_ack = edge_mask_and_ack_msc_irq, - .unmask = unmask_msc_irq, - .eoi = unmask_msc_irq, - .end = end_msc_irq, + .irq_ack = edge_mask_and_ack_msc_irq, + .irq_mask = mask_msc_irq, + .irq_mask_ack = edge_mask_and_ack_msc_irq, + .irq_unmask = unmask_msc_irq, + .irq_eoi = unmask_msc_irq, }; @@ -140,16 +137,20 @@ void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqma switch (imp->im_type) { case MSC01_IRQ_EDGE: - set_irq_chip_and_handler_name(irqbase + n, - &msc_edgeirq_type, handle_edge_irq, "edge"); + irq_set_chip_and_handler_name(irqbase + n, + &msc_edgeirq_type, + handle_edge_irq, + "edge"); if (cpu_has_veic) MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); else MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); break; case MSC01_IRQ_LEVEL: - set_irq_chip_and_handler_name(irqbase+n, - &msc_levelirq_type, handle_level_irq, "level"); + irq_set_chip_and_handler_name(irqbase + n, + &msc_levelirq_type, + handle_level_irq, + "level"); if (cpu_has_veic) MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); else diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c index 9731e8b4786..a8a8977d588 100644 --- a/arch/mips/kernel/irq-rm7000.c +++ b/arch/mips/kernel/irq-rm7000.c @@ -18,23 +18,23 @@ #include <asm/mipsregs.h> #include <asm/system.h> -static inline void unmask_rm7k_irq(unsigned int irq) +static inline void unmask_rm7k_irq(struct irq_data *d) { - set_c0_intcontrol(0x100 << (irq - RM7K_CPU_IRQ_BASE)); + set_c0_intcontrol(0x100 << (d->irq - RM7K_CPU_IRQ_BASE)); } -static inline void mask_rm7k_irq(unsigned int irq) +static inline void mask_rm7k_irq(struct irq_data *d) { - clear_c0_intcontrol(0x100 << (irq - RM7K_CPU_IRQ_BASE)); + clear_c0_intcontrol(0x100 << (d->irq - RM7K_CPU_IRQ_BASE)); } static struct irq_chip rm7k_irq_controller = { .name = "RM7000", - .ack = mask_rm7k_irq, - .mask = mask_rm7k_irq, - .mask_ack = mask_rm7k_irq, - .unmask = unmask_rm7k_irq, - .eoi = unmask_rm7k_irq + .irq_ack = mask_rm7k_irq, + .irq_mask = mask_rm7k_irq, + .irq_mask_ack = mask_rm7k_irq, + .irq_unmask = unmask_rm7k_irq, + .irq_eoi = unmask_rm7k_irq }; void __init rm7k_cpu_irq_init(void) @@ -45,6 +45,6 @@ void __init rm7k_cpu_irq_init(void) clear_c0_intcontrol(0x00000f00); /* Mask all */ for (i = base; i < base + 4; i++) - set_irq_chip_and_handler(i, &rm7k_irq_controller, + irq_set_chip_and_handler(i, &rm7k_irq_controller, handle_percpu_irq); } diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c index b7e4025b58a..38874a4b925 100644 --- a/arch/mips/kernel/irq-rm9000.c +++ b/arch/mips/kernel/irq-rm9000.c @@ -19,22 +19,22 @@ #include <asm/mipsregs.h> #include <asm/system.h> -static inline void unmask_rm9k_irq(unsigned int irq) +static inline void unmask_rm9k_irq(struct irq_data *d) { - set_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE)); + set_c0_intcontrol(0x1000 << (d->irq - RM9K_CPU_IRQ_BASE)); } -static inline void mask_rm9k_irq(unsigned int irq) +static inline void mask_rm9k_irq(struct irq_data *d) { - clear_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE)); + clear_c0_intcontrol(0x1000 << (d->irq - RM9K_CPU_IRQ_BASE)); } -static inline void rm9k_cpu_irq_enable(unsigned int irq) +static inline void rm9k_cpu_irq_enable(struct irq_data *d) { unsigned long flags; local_irq_save(flags); - unmask_rm9k_irq(irq); + unmask_rm9k_irq(d); local_irq_restore(flags); } @@ -43,50 +43,47 @@ static inline void rm9k_cpu_irq_enable(unsigned int irq) */ static void local_rm9k_perfcounter_irq_startup(void *args) { - unsigned int irq = (unsigned int) args; - - rm9k_cpu_irq_enable(irq); + rm9k_cpu_irq_enable(args); } -static unsigned int rm9k_perfcounter_irq_startup(unsigned int irq) +static unsigned int rm9k_perfcounter_irq_startup(struct irq_data *d) { - on_each_cpu(local_rm9k_perfcounter_irq_startup, (void *) irq, 1); + on_each_cpu(local_rm9k_perfcounter_irq_startup, d, 1); return 0; } static void local_rm9k_perfcounter_irq_shutdown(void *args) { - unsigned int irq = (unsigned int) args; unsigned long flags; local_irq_save(flags); - mask_rm9k_irq(irq); + mask_rm9k_irq(args); local_irq_restore(flags); } -static void rm9k_perfcounter_irq_shutdown(unsigned int irq) +static void rm9k_perfcounter_irq_shutdown(struct irq_data *d) { - on_each_cpu(local_rm9k_perfcounter_irq_shutdown, (void *) irq, 1); + on_each_cpu(local_rm9k_perfcounter_irq_shutdown, d, 1); } static struct irq_chip rm9k_irq_controller = { .name = "RM9000", - .ack = mask_rm9k_irq, - .mask = mask_rm9k_irq, - .mask_ack = mask_rm9k_irq, - .unmask = unmask_rm9k_irq, - .eoi = unmask_rm9k_irq + .irq_ack = mask_rm9k_irq, + .irq_mask = mask_rm9k_irq, + .irq_mask_ack = mask_rm9k_irq, + .irq_unmask = unmask_rm9k_irq, + .irq_eoi = unmask_rm9k_irq }; static struct irq_chip rm9k_perfcounter_irq = { .name = "RM9000", - .startup = rm9k_perfcounter_irq_startup, - .shutdown = rm9k_perfcounter_irq_shutdown, - .ack = mask_rm9k_irq, - .mask = mask_rm9k_irq, - .mask_ack = mask_rm9k_irq, - .unmask = unmask_rm9k_irq, + .irq_startup = rm9k_perfcounter_irq_startup, + .irq_shutdown = rm9k_perfcounter_irq_shutdown, + .irq_ack = mask_rm9k_irq, + .irq_mask = mask_rm9k_irq, + .irq_mask_ack = mask_rm9k_irq, + .irq_unmask = unmask_rm9k_irq, }; unsigned int rm9000_perfcount_irq; @@ -101,10 +98,10 @@ void __init rm9k_cpu_irq_init(void) clear_c0_intcontrol(0x0000f000); /* Mask all */ for (i = base; i < base + 4; i++) - set_irq_chip_and_handler(i, &rm9k_irq_controller, + irq_set_chip_and_handler(i, &rm9k_irq_controller, handle_level_irq); rm9000_perfcount_irq = base + 1; - set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq, + irq_set_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq, handle_percpu_irq); } diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 4f93db58a79..9b734d74ae8 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -81,48 +81,9 @@ void ack_bad_irq(unsigned int irq) atomic_t irq_err_count; -/* - * Generic, controller-independent functions: - */ - -int show_interrupts(struct seq_file *p, void *v) +int arch_show_interrupts(struct seq_file *p, int prec) { - int i = *(loff_t *) v, j; - struct irqaction * action; - unsigned long flags; - - if (i == 0) { - seq_printf(p, " "); - for_each_online_cpu(j) - seq_printf(p, "CPU%d ", j); - seq_putc(p, '\n'); - } - - if (i < NR_IRQS) { - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); - action = irq_desc[i].action; - if (!action) - goto skip; - seq_printf(p, "%3d: ", i); -#ifndef CONFIG_SMP - seq_printf(p, "%10u ", kstat_irqs(i)); -#else - for_each_online_cpu(j) - seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); -#endif - seq_printf(p, " %14s", irq_desc[i].chip->name); - seq_printf(p, " %s", action->name); - - for (action=action->next; action; action = action->next) - seq_printf(p, ", %s", action->name); - - seq_putc(p, '\n'); -skip: - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); - } else if (i == NR_IRQS) { - seq_putc(p, '\n'); - seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count)); - } + seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count)); return 0; } @@ -141,7 +102,7 @@ void __init init_IRQ(void) #endif for (i = 0; i < NR_IRQS; i++) - set_irq_noprobe(i); + irq_set_noprobe(i); arch_init_irq(); @@ -183,8 +144,8 @@ void __irq_entry do_IRQ(unsigned int irq) { irq_enter(); check_stack_overflow(); - __DO_IRQ_SMTC_HOOK(irq); - generic_handle_irq(irq); + if (!smtc_handle_on_other_cpu(irq)) + generic_handle_irq(irq); irq_exit(); } @@ -197,7 +158,7 @@ void __irq_entry do_IRQ(unsigned int irq) void __irq_entry do_IRQ_no_affinity(unsigned int irq) { irq_enter(); - __NO_AFFINITY_IRQ_SMTC_HOOK(irq); + smtc_im_backstop(irq); generic_handle_irq(irq); irq_exit(); } diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 0262abe0912..6e71b284f6c 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c @@ -37,42 +37,38 @@ #include <asm/mipsmtregs.h> #include <asm/system.h> -static inline void unmask_mips_irq(unsigned int irq) +static inline void unmask_mips_irq(struct irq_data *d) { - set_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE)); + set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); irq_enable_hazard(); } -static inline void mask_mips_irq(unsigned int irq) +static inline void mask_mips_irq(struct irq_data *d) { - clear_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE)); + clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); irq_disable_hazard(); } static struct irq_chip mips_cpu_irq_controller = { .name = "MIPS", - .ack = mask_mips_irq, - .mask = mask_mips_irq, - .mask_ack = mask_mips_irq, - .unmask = unmask_mips_irq, - .eoi = unmask_mips_irq, + .irq_ack = mask_mips_irq, + .irq_mask = mask_mips_irq, + .irq_mask_ack = mask_mips_irq, + .irq_unmask = unmask_mips_irq, + .irq_eoi = unmask_mips_irq, }; /* * Basically the same as above but taking care of all the MT stuff */ -#define unmask_mips_mt_irq unmask_mips_irq -#define mask_mips_mt_irq mask_mips_irq - -static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) +static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d) { unsigned int vpflags = dvpe(); - clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE)); + clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); evpe(vpflags); - unmask_mips_mt_irq(irq); - + unmask_mips_irq(d); return 0; } @@ -80,22 +76,22 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) * While we ack the interrupt interrupts are disabled and thus we don't need * to deal with concurrency issues. Same for mips_cpu_irq_end. */ -static void mips_mt_cpu_irq_ack(unsigned int irq) +static void mips_mt_cpu_irq_ack(struct irq_data *d) { unsigned int vpflags = dvpe(); - clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE)); + clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); evpe(vpflags); - mask_mips_mt_irq(irq); + mask_mips_irq(d); } static struct irq_chip mips_mt_cpu_irq_controller = { .name = "MIPS", - .startup = mips_mt_cpu_irq_startup, - .ack = mips_mt_cpu_irq_ack, - .mask = mask_mips_mt_irq, - .mask_ack = mips_mt_cpu_irq_ack, - .unmask = unmask_mips_mt_irq, - .eoi = unmask_mips_mt_irq, + .irq_startup = mips_mt_cpu_irq_startup, + .irq_ack = mips_mt_cpu_irq_ack, + .irq_mask = mask_mips_irq, + .irq_mask_ack = mips_mt_cpu_irq_ack, + .irq_unmask = unmask_mips_irq, + .irq_eoi = unmask_mips_irq, }; void __init mips_cpu_irq_init(void) @@ -113,10 +109,10 @@ void __init mips_cpu_irq_init(void) */ if (cpu_has_mipsmt) for (i = irq_base; i < irq_base + 2; i++) - set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller, + irq_set_chip_and_handler(i, &mips_mt_cpu_irq_controller, handle_percpu_irq); for (i = irq_base + 2; i < irq_base + 8; i++) - set_irq_chip_and_handler(i, &mips_cpu_irq_controller, + irq_set_chip_and_handler(i, &mips_cpu_irq_controller, handle_percpu_irq); } diff --git a/arch/mips/kernel/irq_txx9.c b/arch/mips/kernel/irq_txx9.c index 95a96f69172..b0c55b50218 100644 --- a/arch/mips/kernel/irq_txx9.c +++ b/arch/mips/kernel/irq_txx9.c @@ -63,9 +63,9 @@ static struct { unsigned char mode; } txx9irq[TXx9_MAX_IR] __read_mostly; -static void txx9_irq_unmask(unsigned int irq) +static void txx9_irq_unmask(struct irq_data *d) { - unsigned int irq_nr = irq - TXX9_IRQ_BASE; + unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16 ) / 2]; int ofs = irq_nr / 16 * 16 + (irq_nr & 1) * 8; @@ -79,9 +79,9 @@ static void txx9_irq_unmask(unsigned int irq) #endif } -static inline void txx9_irq_mask(unsigned int irq) +static inline void txx9_irq_mask(struct irq_data *d) { - unsigned int irq_nr = irq - TXX9_IRQ_BASE; + unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16) / 2]; int ofs = irq_nr / 16 * 16 + (irq_nr & 1) * 8; @@ -99,19 +99,19 @@ static inline void txx9_irq_mask(unsigned int irq) #endif } -static void txx9_irq_mask_ack(unsigned int irq) +static void txx9_irq_mask_ack(struct irq_data *d) { - unsigned int irq_nr = irq - TXX9_IRQ_BASE; + unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; - txx9_irq_mask(irq); + txx9_irq_mask(d); /* clear edge detection */ if (unlikely(TXx9_IRCR_EDGE(txx9irq[irq_nr].mode))) __raw_writel(TXx9_IRSCR_EIClrE | irq_nr, &txx9_ircptr->scr); } -static int txx9_irq_set_type(unsigned int irq, unsigned int flow_type) +static int txx9_irq_set_type(struct irq_data *d, unsigned int flow_type) { - unsigned int irq_nr = irq - TXX9_IRQ_BASE; + unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; u32 cr; u32 __iomem *crp; int ofs; @@ -139,11 +139,11 @@ static int txx9_irq_set_type(unsigned int irq, unsigned int flow_type) static struct irq_chip txx9_irq_chip = { .name = "TXX9", - .ack = txx9_irq_mask_ack, - .mask = txx9_irq_mask, - .mask_ack = txx9_irq_mask_ack, - .unmask = txx9_irq_unmask, - .set_type = txx9_irq_set_type, + .irq_ack = txx9_irq_mask_ack, + .irq_mask = txx9_irq_mask, + .irq_mask_ack = txx9_irq_mask_ack, + .irq_unmask = txx9_irq_unmask, + .irq_set_type = txx9_irq_set_type, }; void __init txx9_irq_init(unsigned long baseaddr) @@ -154,8 +154,8 @@ void __init txx9_irq_init(unsigned long baseaddr) for (i = 0; i < TXx9_MAX_IR; i++) { txx9irq[i].level = 4; /* middle level */ txx9irq[i].mode = TXx9_IRCR_LOW; - set_irq_chip_and_handler(TXX9_IRQ_BASE + i, - &txx9_irq_chip, handle_level_irq); + irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &txx9_irq_chip, + handle_level_irq); } /* mask all IRC interrupts */ diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index d9a7db78ed6..75266ff4cc3 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -721,7 +721,7 @@ static void mipsxx_pmu_start(void) /* * MIPS performance counters can be per-TC. The control registers can - * not be directly accessed accross CPUs. Hence if we want to do global + * not be directly accessed across CPUs. Hence if we want to do global * control, we need cross CPU calls. on_each_cpu() can help us, but we * can not make sure this function is called with interrupts enabled. So * here we pause local counters and then grab a rwlock and leave the diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index ae167df73dd..d2112d3cf11 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -410,7 +410,7 @@ unsigned long unwind_stack(struct task_struct *task, unsigned long *sp, if (!kallsyms_lookup_size_offset(pc, &size, &ofs)) return 0; /* - * Return ra if an exception occured at the first instruction + * Return ra if an exception occurred at the first instruction */ if (unlikely(ofs == 0)) { pc = *ra; diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index d21c388c011..584e6b55c86 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -540,8 +540,8 @@ asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit) secure_computing(regs->regs[2]); if (unlikely(current->audit_context) && entryexit) - audit_syscall_exit(AUDITSC_RESULT(regs->regs[2]), - regs->regs[2]); + audit_syscall_exit(AUDITSC_RESULT(regs->regs[7]), + -regs->regs[2]); if (!(current->ptrace & PT_PTRACED)) goto out; diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index fbaabad0e6e..7f1377eb22d 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -565,7 +565,7 @@ einval: li v0, -ENOSYS sys sys_ioprio_get 2 /* 4315 */ sys sys_utimensat 4 sys sys_signalfd 3 - sys sys_ni_syscall 0 + sys sys_ni_syscall 0 /* was timerfd */ sys sys_eventfd 1 sys sys_fallocate 6 /* 4320 */ sys sys_timerfd_create 2 @@ -586,6 +586,10 @@ einval: li v0, -ENOSYS sys sys_fanotify_init 2 sys sys_fanotify_mark 6 sys sys_prlimit64 4 + sys sys_name_to_handle_at 5 + sys sys_open_by_handle_at 3 /* 4340 */ + sys sys_clock_adjtime 2 + sys sys_syncfs 1 .endm /* We pre-compute the number of _instruction_ bytes needed to diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index 3f417928320..7c0ef7f128b 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -404,7 +404,7 @@ sys_call_table: PTR sys_ioprio_get PTR sys_utimensat /* 5275 */ PTR sys_signalfd - PTR sys_ni_syscall + PTR sys_ni_syscall /* was timerfd */ PTR sys_eventfd PTR sys_fallocate PTR sys_timerfd_create /* 5280 */ @@ -425,4 +425,8 @@ sys_call_table: PTR sys_fanotify_init /* 5295 */ PTR sys_fanotify_mark PTR sys_prlimit64 + PTR sys_name_to_handle_at + PTR sys_open_by_handle_at + PTR sys_clock_adjtime /* 5300 */ + PTR sys_syncfs .size sys_call_table,.-sys_call_table diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index f08ece6d8ac..de6c5563bea 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -403,7 +403,7 @@ EXPORT(sysn32_call_table) PTR sys_ioprio_get PTR compat_sys_utimensat PTR compat_sys_signalfd /* 6280 */ - PTR sys_ni_syscall + PTR sys_ni_syscall /* was timerfd */ PTR sys_eventfd PTR sys_fallocate PTR sys_timerfd_create @@ -425,4 +425,8 @@ EXPORT(sysn32_call_table) PTR sys_fanotify_init /* 6300 */ PTR sys_fanotify_mark PTR sys_prlimit64 + PTR sys_name_to_handle_at + PTR sys_open_by_handle_at + PTR compat_sys_clock_adjtime /* 6305 */ + PTR sys_syncfs .size sysn32_call_table,.-sysn32_call_table diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 78d768a3e19..b0541dda883 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -522,7 +522,7 @@ sys_call_table: PTR sys_ioprio_get /* 4315 */ PTR compat_sys_utimensat PTR compat_sys_signalfd - PTR sys_ni_syscall + PTR sys_ni_syscall /* was timerfd */ PTR sys_eventfd PTR sys32_fallocate /* 4320 */ PTR sys_timerfd_create @@ -543,4 +543,8 @@ sys_call_table: PTR sys_fanotify_init PTR sys_32_fanotify_mark PTR sys_prlimit64 + PTR sys_name_to_handle_at + PTR compat_sys_open_by_handle_at /* 4340 */ + PTR compat_sys_clock_adjtime + PTR sys_syncfs .size sys_call_table,.-sys_call_table diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index c0e81418ba2..1ec56e635d0 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -120,7 +120,7 @@ static void vsmp_send_ipi_single(int cpu, unsigned int action) local_irq_save(flags); - vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */ + vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */ switch (action) { case SMP_CALL_FUNCTION: diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 39c08254b0f..5a88cc4ccd5 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -677,8 +677,9 @@ void smtc_set_irq_affinity(unsigned int irq, cpumask_t affinity) */ } -void smtc_forward_irq(unsigned int irq) +void smtc_forward_irq(struct irq_data *d) { + unsigned int irq = d->irq; int target; /* @@ -692,7 +693,7 @@ void smtc_forward_irq(unsigned int irq) * and efficiency, we just pick the easiest one to find. */ - target = cpumask_first(irq_desc[irq].affinity); + target = cpumask_first(d->affinity); /* * We depend on the platform code to have correctly processed @@ -707,12 +708,10 @@ void smtc_forward_irq(unsigned int irq) */ /* If no one is eligible, service locally */ - if (target >= NR_CPUS) { + if (target >= NR_CPUS) do_IRQ_no_affinity(irq); - return; - } - - smtc_send_ipi(target, IRQ_AFFINITY_IPI, irq); + else + smtc_send_ipi(target, IRQ_AFFINITY_IPI, irq); } #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ @@ -1147,7 +1146,7 @@ static void setup_cross_vpe_interrupts(unsigned int nvpe) setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); - set_irq_handler(cpu_ipi_irq, handle_percpu_irq); + irq_set_handler(cpu_ipi_irq, handle_percpu_irq); } /* diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index fb749740551..1083ad4e101 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -102,7 +102,7 @@ static __init int cpu_has_mfc0_count_bug(void) case CPU_R4400SC: case CPU_R4400MC: /* - * The published errata for the R4400 upto 3.0 say the CPU + * The published errata for the R4400 up to 3.0 say the CPU * has the mfc0 from count bug. */ if ((current_cpu_data.processor_id & 0xff) <= 0x30) diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 832afbb8758..e4b0b0bec03 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -74,6 +74,7 @@ SECTIONS INIT_TASK_DATA(PAGE_SIZE) NOSAVE_DATA CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) + READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) DATA_DATA CONSTRUCTORS } diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index ab52b7cf3b6..dbb6b408f00 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -19,7 +19,7 @@ * VPE support module * * Provides support for loading a MIPS SP program on VPE1. - * The SP enviroment is rather simple, no tlb's. It needs to be relocatable + * The SP environment is rather simple, no tlb's. It needs to be relocatable * (or partially linked). You should initialise your stack in the startup * code. This loader looks for the symbol __start and sets up * execution to resume from there. The MIPS SDE kit contains suitable examples. diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c index 1353fb135ed..de4c165515d 100644 --- a/arch/mips/lasat/interrupt.c +++ b/arch/mips/lasat/interrupt.c @@ -32,24 +32,24 @@ static volatile int *lasat_int_status; static volatile int *lasat_int_mask; static volatile int lasat_int_mask_shift; -void disable_lasat_irq(unsigned int irq_nr) +void disable_lasat_irq(struct irq_data *d) { - irq_nr -= LASAT_IRQ_BASE; + unsigned int irq_nr = d->irq - LASAT_IRQ_BASE; + *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift; } -void enable_lasat_irq(unsigned int irq_nr) +void enable_lasat_irq(struct irq_data *d) { - irq_nr -= LASAT_IRQ_BASE; + unsigned int irq_nr = d->irq - LASAT_IRQ_BASE; + *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift; } static struct irq_chip lasat_irq_type = { .name = "Lasat", - .ack = disable_lasat_irq, - .mask = disable_lasat_irq, - .mask_ack = disable_lasat_irq, - .unmask = enable_lasat_irq, + .irq_mask = disable_lasat_irq, + .irq_unmask = enable_lasat_irq, }; static inline int ls1bit32(unsigned int x) @@ -128,7 +128,7 @@ void __init arch_init_irq(void) mips_cpu_irq_init(); for (i = LASAT_IRQ_BASE; i <= LASAT_IRQ_END; i++) - set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &lasat_irq_type, handle_level_irq); setup_irq(LASAT_CASCADE_IRQ, &cascade); } diff --git a/arch/mips/lib/strnlen_user.S b/arch/mips/lib/strnlen_user.S index c768e300061..64457162f7e 100644 --- a/arch/mips/lib/strnlen_user.S +++ b/arch/mips/lib/strnlen_user.S @@ -17,7 +17,7 @@ .previous /* - * Return the size of a string including the ending NUL character upto a + * Return the size of a string including the ending NUL character up to a * maximum of a1 or 0 in case of error. * * Note: for performance reasons we deliberately accept that a user may diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c index 2dc2a4cc632..f27d7ccca92 100644 --- a/arch/mips/loongson/common/bonito-irq.c +++ b/arch/mips/loongson/common/bonito-irq.c @@ -16,24 +16,22 @@ #include <loongson.h> -static inline void bonito_irq_enable(unsigned int irq) +static inline void bonito_irq_enable(struct irq_data *d) { - LOONGSON_INTENSET = (1 << (irq - LOONGSON_IRQ_BASE)); + LOONGSON_INTENSET = (1 << (d->irq - LOONGSON_IRQ_BASE)); mmiowb(); } -static inline void bonito_irq_disable(unsigned int irq) +static inline void bonito_irq_disable(struct irq_data *d) { - LOONGSON_INTENCLR = (1 << (irq - LOONGSON_IRQ_BASE)); + LOONGSON_INTENCLR = (1 << (d->irq - LOONGSON_IRQ_BASE)); mmiowb(); } static struct irq_chip bonito_irq_type = { - .name = "bonito_irq", - .ack = bonito_irq_disable, - .mask = bonito_irq_disable, - .mask_ack = bonito_irq_disable, - .unmask = bonito_irq_enable, + .name = "bonito_irq", + .irq_mask = bonito_irq_disable, + .irq_unmask = bonito_irq_enable, }; static struct irqaction __maybe_unused dma_timeout_irqaction = { @@ -46,7 +44,8 @@ void bonito_irq_init(void) u32 i; for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++) - set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &bonito_irq_type, + handle_level_irq); #ifdef CONFIG_CPU_LOONGSON2E setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction); diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c index 11b193f848f..d93830ad611 100644 --- a/arch/mips/loongson/common/env.c +++ b/arch/mips/loongson/common/env.c @@ -29,9 +29,10 @@ unsigned long memsize, highmemsize; #define parse_even_earlier(res, option, p) \ do { \ - int ret; \ + unsigned int tmp __maybe_unused; \ + \ if (strncmp(option, (char *)p, strlen(option)) == 0) \ - ret = strict_strtol((char *)p + strlen(option"="), 10, &res); \ + tmp = strict_strtol((char *)p + strlen(option"="), 10, &res); \ } while (0) void __init prom_init_env(void) diff --git a/arch/mips/math-emu/dp_fsp.c b/arch/mips/math-emu/dp_fsp.c index 1dfbd92ba9d..daed6834dc1 100644 --- a/arch/mips/math-emu/dp_fsp.c +++ b/arch/mips/math-emu/dp_fsp.c @@ -62,7 +62,7 @@ ieee754dp ieee754dp_fsp(ieee754sp x) break; } - /* CANT possibly overflow,underflow, or need rounding + /* CAN'T possibly overflow,underflow, or need rounding */ /* drop the hidden bit */ diff --git a/arch/mips/math-emu/dp_mul.c b/arch/mips/math-emu/dp_mul.c index aa566e785f5..09175f46192 100644 --- a/arch/mips/math-emu/dp_mul.c +++ b/arch/mips/math-emu/dp_mul.c @@ -104,7 +104,7 @@ ieee754dp ieee754dp_mul(ieee754dp x, ieee754dp y) case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM): break; } - /* rm = xm * ym, re = xe+ye basicly */ + /* rm = xm * ym, re = xe+ye basically */ assert(xm & DP_HIDDEN_BIT); assert(ym & DP_HIDDEN_BIT); { diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c index 36d975ae08f..3c4a8c5ba7f 100644 --- a/arch/mips/math-emu/dsemul.c +++ b/arch/mips/math-emu/dsemul.c @@ -32,7 +32,7 @@ * not change cp0_epc due to the instruction * * According to the spec: - * 1) it shouldnt be a branch :-) + * 1) it shouldn't be a branch :-) * 2) it can be a COP instruction :-( * 3) if we are tring to run a protected memory space we must take * special care on memory access instructions :-( diff --git a/arch/mips/math-emu/sp_mul.c b/arch/mips/math-emu/sp_mul.c index c06bb4022be..2722a2570ea 100644 --- a/arch/mips/math-emu/sp_mul.c +++ b/arch/mips/math-emu/sp_mul.c @@ -104,7 +104,7 @@ ieee754sp ieee754sp_mul(ieee754sp x, ieee754sp y) case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM): break; } - /* rm = xm * ym, re = xe+ye basicly */ + /* rm = xm * ym, re = xe+ye basically */ assert(xm & SP_HIDDEN_BIT); assert(ym & SP_HIDDEN_BIT); diff --git a/arch/mips/mipssim/sim_smtc.c b/arch/mips/mipssim/sim_smtc.c index 5da30b6a65b..30df47258c2 100644 --- a/arch/mips/mipssim/sim_smtc.c +++ b/arch/mips/mipssim/sim_smtc.c @@ -27,6 +27,7 @@ #include <asm/atomic.h> #include <asm/cpu.h> #include <asm/processor.h> +#include <asm/smtc.h> #include <asm/system.h> #include <asm/mmu_context.h> #include <asm/smtc_ipi.h> @@ -57,8 +58,6 @@ static inline void ssmtc_send_ipi_mask(const struct cpumask *mask, */ static void __cpuinit ssmtc_init_secondary(void) { - void smtc_init_secondary(void); - smtc_init_secondary(); } diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index b4923a75cb4..71bddf8f7d2 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1075,7 +1075,6 @@ static int __cpuinit probe_scache(void) unsigned long flags, addr, begin, end, pow2; unsigned int config = read_c0_config(); struct cpuinfo_mips *c = ¤t_cpu_data; - int tmp; if (config & CONF_SC) return 0; @@ -1108,7 +1107,6 @@ static int __cpuinit probe_scache(void) /* Now search for the wrap around point. */ pow2 = (128 * 1024); - tmp = 0; for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { cache_op(Index_Load_Tag_SD, addr); __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ diff --git a/arch/mips/mm/cex-sb1.S b/arch/mips/mm/cex-sb1.S index 2d08268bb70..89c412bc4b6 100644 --- a/arch/mips/mm/cex-sb1.S +++ b/arch/mips/mm/cex-sb1.S @@ -79,7 +79,7 @@ LEAF(except_vec2_sb1) recovered_dcache: /* * Unlock CacheErr-D (which in turn unlocks CacheErr-DPA). - * Ought to log the occurence of this recovered dcache error. + * Ought to log the occurrence of this recovered dcache error. */ b recovered mtc0 $0,C0_CERR_D diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 04f9e17db9d..f5734c2c809 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -352,7 +352,7 @@ static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p) /* * Write random or indexed TLB entry, and care about the hazards from - * the preceeding mtc0 and for the following eret. + * the preceding mtc0 and for the following eret. */ enum tlb_write_entry { tlb_random, tlb_indexed }; @@ -1151,8 +1151,8 @@ static void __cpuinit build_r4000_tlb_refill_handler(void) struct uasm_reloc *r = relocs; u32 *f; unsigned int final_len; - struct mips_huge_tlb_info htlb_info; - enum vmalloc64_mode vmalloc_mode; + struct mips_huge_tlb_info htlb_info __maybe_unused; + enum vmalloc64_mode vmalloc_mode __maybe_unused; memset(tlb_handler, 0, sizeof(tlb_handler)); memset(labels, 0, sizeof(labels)); diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c index 414f0c99b19..31180c321a1 100644 --- a/arch/mips/mti-malta/malta-init.c +++ b/arch/mips/mti-malta/malta-init.c @@ -193,8 +193,6 @@ extern struct plat_smp_ops msmtc_smp_ops; void __init prom_init(void) { - int result; - prom_argc = fw_arg0; _prom_argv = (int *) fw_arg1; _prom_envp = (int *) fw_arg2; @@ -360,20 +358,14 @@ void __init prom_init(void) #ifdef CONFIG_SERIAL_8250_CONSOLE console_config(); #endif - /* Early detection of CMP support */ - result = gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ); - #ifdef CONFIG_MIPS_CMP - if (result) + /* Early detection of CMP support */ + if (gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ)) register_smp_ops(&cmp_smp_ops); + else #endif #ifdef CONFIG_MIPS_MT_SMP -#ifdef CONFIG_MIPS_CMP - if (!result) register_smp_ops(&vsmp_smp_ops); -#else - register_smp_ops(&vsmp_smp_ops); -#endif #endif #ifdef CONFIG_MIPS_MT_SMTC register_smp_ops(&msmtc_smp_ops); diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index b79b24afe3a..e85c977328d 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -56,7 +56,6 @@ static DEFINE_RAW_SPINLOCK(mips_irq_lock); static inline int mips_pcibios_iack(void) { int irq; - u32 dummy; /* * Determine highest priority pending interrupt by performing @@ -83,7 +82,7 @@ static inline int mips_pcibios_iack(void) BONITO_PCIMAP_CFG = 0x20000; /* Flush Bonito register block */ - dummy = BONITO_PCIMAP_CFG; + (void) BONITO_PCIMAP_CFG; iob(); /* sync */ irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg); @@ -472,7 +471,7 @@ static void __init fill_ipi_map(void) void __init arch_init_ipiirq(int irq, struct irqaction *action) { setup_irq(irq, action); - set_irq_handler(irq, handle_percpu_irq); + irq_set_handler(irq, handle_percpu_irq); } void __init arch_init_irq(void) diff --git a/arch/mips/mti-malta/malta-smtc.c b/arch/mips/mti-malta/malta-smtc.c index 192cfd2a539..49a38b09a48 100644 --- a/arch/mips/mti-malta/malta-smtc.c +++ b/arch/mips/mti-malta/malta-smtc.c @@ -34,7 +34,6 @@ static void msmtc_send_ipi_mask(const struct cpumask *mask, unsigned int action) */ static void __cpuinit msmtc_init_secondary(void) { - void smtc_init_secondary(void); int myvpe; /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */ @@ -114,7 +113,8 @@ struct plat_smp_ops msmtc_smp_ops = { */ -int plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity) +int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, + bool force) { cpumask_t tmask; int cpu = 0; @@ -130,7 +130,7 @@ int plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity) * cleared in the affinity mask, there will never be any * interrupt forwarding. But as soon as a program or operator * sets affinity for one of the related IRQs, we need to make - * sure that we don't ever try to forward across the VPE boundry, + * sure that we don't ever try to forward across the VPE boundary, * at least not until we engineer a system where the interrupt * _ack() or _end() function can somehow know that it corresponds * to an interrupt taken on another VPE, and perform the appropriate @@ -144,7 +144,7 @@ int plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity) if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu)) cpu_clear(cpu, tmask); } - cpumask_copy(irq_desc[irq].affinity, &tmask); + cpumask_copy(d->affinity, &tmask); if (cpus_empty(tmask)) /* @@ -155,8 +155,8 @@ int plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity) "IRQ affinity leaves no legal CPU for IRQ %d\n", irq); /* Do any generic SMTC IRQ affinity setup */ - smtc_set_irq_affinity(irq, tmask); + smtc_set_irq_affinity(d->irq, tmask); - return 0; + return IRQ_SET_MASK_OK_NOCOPY; } #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c index 3c6f190aa61..1620b83cd13 100644 --- a/arch/mips/mti-malta/malta-time.c +++ b/arch/mips/mti-malta/malta-time.c @@ -119,7 +119,7 @@ static void __init plat_perf_setup(void) set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; #ifdef CONFIG_SMP - set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq); + irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq); #endif } } diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile index 02cc65e52d1..4b9d7044e26 100644 --- a/arch/mips/oprofile/Makefile +++ b/arch/mips/oprofile/Makefile @@ -1,4 +1,4 @@ -EXTRA_CFLAGS := -Werror +ccflags-y := -Werror obj-$(CONFIG_OPROFILE) += oprofile.o diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c index d8080499872..5d530f89d87 100644 --- a/arch/mips/pci/msi-octeon.c +++ b/arch/mips/pci/msi-octeon.c @@ -172,7 +172,7 @@ msi_irq_allocated: pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control); - set_irq_msi(irq, desc); + irq_set_msi_desc(irq, desc); write_msi_msg(irq, &msg); return 0; } @@ -259,11 +259,11 @@ static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock); static u64 msi_rcv_reg[4]; static u64 mis_ena_reg[4]; -static void octeon_irq_msi_enable_pcie(unsigned int irq) +static void octeon_irq_msi_enable_pcie(struct irq_data *data) { u64 en; unsigned long flags; - int msi_number = irq - OCTEON_IRQ_MSI_BIT0; + int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0; int irq_index = msi_number >> 6; int irq_bit = msi_number & 0x3f; @@ -275,11 +275,11 @@ static void octeon_irq_msi_enable_pcie(unsigned int irq) raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); } -static void octeon_irq_msi_disable_pcie(unsigned int irq) +static void octeon_irq_msi_disable_pcie(struct irq_data *data) { u64 en; unsigned long flags; - int msi_number = irq - OCTEON_IRQ_MSI_BIT0; + int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0; int irq_index = msi_number >> 6; int irq_bit = msi_number & 0x3f; @@ -293,11 +293,11 @@ static void octeon_irq_msi_disable_pcie(unsigned int irq) static struct irq_chip octeon_irq_chip_msi_pcie = { .name = "MSI", - .enable = octeon_irq_msi_enable_pcie, - .disable = octeon_irq_msi_disable_pcie, + .irq_enable = octeon_irq_msi_enable_pcie, + .irq_disable = octeon_irq_msi_disable_pcie, }; -static void octeon_irq_msi_enable_pci(unsigned int irq) +static void octeon_irq_msi_enable_pci(struct irq_data *data) { /* * Octeon PCI doesn't have the ability to mask/unmask MSI @@ -308,15 +308,15 @@ static void octeon_irq_msi_enable_pci(unsigned int irq) */ } -static void octeon_irq_msi_disable_pci(unsigned int irq) +static void octeon_irq_msi_disable_pci(struct irq_data *data) { /* See comment in enable */ } static struct irq_chip octeon_irq_chip_msi_pci = { .name = "MSI", - .enable = octeon_irq_msi_enable_pci, - .disable = octeon_irq_msi_disable_pci, + .irq_enable = octeon_irq_msi_enable_pci, + .irq_disable = octeon_irq_msi_disable_pci, }; /* @@ -388,7 +388,7 @@ int __init octeon_msi_initialize(void) } for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++) - set_irq_chip_and_handler(irq, msi, handle_simple_irq); + irq_set_chip_and_handler(irq, msi, handle_simple_irq); if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0, diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c index 68798f869c0..8fbfbf2b931 100644 --- a/arch/mips/pci/ops-pmcmsp.c +++ b/arch/mips/pci/ops-pmcmsp.c @@ -344,7 +344,7 @@ static irqreturn_t bpci_interrupt(int irq, void *dev_id) * PCI_ACCESS_WRITE and PCI_ACCESS_READ. * * bus - pointer to the bus number of the device to - * be targetted for the configuration cycle. + * be targeted for the configuration cycle. * The only element of the pci_bus structure * used is bus->number. This argument determines * if the configuration access will be Type 0 or @@ -354,7 +354,7 @@ static irqreturn_t bpci_interrupt(int irq, void *dev_id) * * devfn - this is an 8-bit field. The lower three bits * specify the function number of the device to - * be targetted for the configuration cycle, with + * be targeted for the configuration cycle, with * all three-bit combinations being legal. The * upper five bits specify the device number, * with legal values being 10 to 31. diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c index 6f5e24c6ae6..af8c3199696 100644 --- a/arch/mips/pci/pci-bcm1480.c +++ b/arch/mips/pci/pci-bcm1480.c @@ -210,7 +210,7 @@ static int __init bcm1480_pcibios_init(void) PCIBIOS_MIN_IO = 0x00008000UL; PCIBIOS_MIN_MEM = 0x01000000UL; - /* Set I/O resource limits. - unlimited for now to accomodate HT */ + /* Set I/O resource limits. - unlimited for now to accommodate HT */ ioport_resource.end = 0xffffffffUL; iomem_resource.end = 0xffffffffUL; diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index 2d74fc9ae3b..ed1c54284b8 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -441,7 +441,7 @@ static void octeon_pci_initialize(void) /* * TDOMC must be set to one in PCI mode. TDOMC should be set to 4 - * in PCI-X mode to allow four oustanding splits. Otherwise, + * in PCI-X mode to allow four outstanding splits. Otherwise, * should not change from its reset value. Don't write PCI_CFG19 * in PCI mode (0x82000001 reset value), write it to 0x82000004 * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero. @@ -515,7 +515,7 @@ static void octeon_pci_initialize(void) #endif /* USE_OCTEON_INTERNAL_ARBITER */ /* - * Preferrably written to 1 to set MLTD. [RDSATI,TRTAE, + * Preferably written to 1 to set MLTD. [RDSATI,TRTAE, * TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to * 1..7. */ diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 38bc28005b4..33bba7bff25 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -125,7 +125,7 @@ void __devinit register_pci_controller(struct pci_controller *hose) hose_tail = &hose->next; /* - * Do not panic here but later - this might hapen before console init. + * Do not panic here but later - this might happen before console init. */ if (!hose->io_map_base) { printk(KERN_WARNING diff --git a/arch/mips/pmc-sierra/Kconfig b/arch/mips/pmc-sierra/Kconfig index 8d798497c61..bbd76082fa8 100644 --- a/arch/mips/pmc-sierra/Kconfig +++ b/arch/mips/pmc-sierra/Kconfig @@ -23,6 +23,8 @@ config PMC_MSP7120_GW select SYS_SUPPORTS_MULTITHREADING select IRQ_MSP_CIC select HW_HAS_PCI + select MSP_HAS_USB + select MSP_ETH config PMC_MSP7120_FPGA bool "PMC-Sierra MSP7120 FPGA" @@ -35,3 +37,16 @@ endchoice config HYPERTRANSPORT bool "Hypertransport Support for PMC-Sierra Yosemite" depends on PMC_YOSEMITE + +config MSP_HAS_USB + boolean + depends on PMC_MSP + +config MSP_ETH + boolean + select MSP_HAS_MAC + depends on PMC_MSP + +config MSP_HAS_MAC + boolean + depends on PMC_MSP diff --git a/arch/mips/pmc-sierra/msp71xx/Makefile b/arch/mips/pmc-sierra/msp71xx/Makefile index e107f79b149..cefba7733b7 100644 --- a/arch/mips/pmc-sierra/msp71xx/Makefile +++ b/arch/mips/pmc-sierra/msp71xx/Makefile @@ -6,7 +6,9 @@ obj-y += msp_prom.o msp_setup.o msp_irq.o \ obj-$(CONFIG_HAVE_GPIO_LIB) += gpio.o gpio_extended.o obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o -obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o +obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o msp_irq_per.o obj-$(CONFIG_PCI) += msp_pci.o -obj-$(CONFIG_MSPETH) += msp_eth.o -obj-$(CONFIG_USB_MSP71XX) += msp_usb.o +obj-$(CONFIG_MSP_HAS_MAC) += msp_eth.o +obj-$(CONFIG_MSP_HAS_USB) += msp_usb.o +obj-$(CONFIG_MIPS_MT_SMP) += msp_smp.o +obj-$(CONFIG_MIPS_MT_SMTC) += msp_smtc.o diff --git a/arch/mips/pmc-sierra/msp71xx/msp_eth.c b/arch/mips/pmc-sierra/msp71xx/msp_eth.c new file mode 100644 index 00000000000..c584df393de --- /dev/null +++ b/arch/mips/pmc-sierra/msp71xx/msp_eth.c @@ -0,0 +1,187 @@ +/* + * The setup file for ethernet related hardware on PMC-Sierra MSP processors. + * + * Copyright 2010 PMC-Sierra, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/ioport.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <msp_regs.h> +#include <msp_int.h> +#include <msp_gpio_macros.h> + + +#define MSP_ETHERNET_GPIO0 14 +#define MSP_ETHERNET_GPIO1 15 +#define MSP_ETHERNET_GPIO2 16 + +#ifdef CONFIG_MSP_HAS_TSMAC +#define MSP_TSMAC_SIZE 0x10020 +#define MSP_TSMAC_ID "pmc_tsmac" + +static struct resource msp_tsmac0_resources[] = { + [0] = { + .start = MSP_MAC0_BASE, + .end = MSP_MAC0_BASE + MSP_TSMAC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MSP_INT_MAC0, + .end = MSP_INT_MAC0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource msp_tsmac1_resources[] = { + [0] = { + .start = MSP_MAC1_BASE, + .end = MSP_MAC1_BASE + MSP_TSMAC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MSP_INT_MAC1, + .end = MSP_INT_MAC1, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource msp_tsmac2_resources[] = { + [0] = { + .start = MSP_MAC2_BASE, + .end = MSP_MAC2_BASE + MSP_TSMAC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MSP_INT_SAR, + .end = MSP_INT_SAR, + .flags = IORESOURCE_IRQ, + }, +}; + + +static struct platform_device tsmac_device[] = { + [0] = { + .name = MSP_TSMAC_ID, + .id = 0, + .num_resources = ARRAY_SIZE(msp_tsmac0_resources), + .resource = msp_tsmac0_resources, + }, + [1] = { + .name = MSP_TSMAC_ID, + .id = 1, + .num_resources = ARRAY_SIZE(msp_tsmac1_resources), + .resource = msp_tsmac1_resources, + }, + [2] = { + .name = MSP_TSMAC_ID, + .id = 2, + .num_resources = ARRAY_SIZE(msp_tsmac2_resources), + .resource = msp_tsmac2_resources, + }, +}; +#define msp_eth_devs tsmac_device + +#else +/* If it is not TSMAC assume MSP_ETH (100Mbps) */ +#define MSP_ETH_ID "pmc_mspeth" +#define MSP_ETH_SIZE 0xE0 +static struct resource msp_eth0_resources[] = { + [0] = { + .start = MSP_MAC0_BASE, + .end = MSP_MAC0_BASE + MSP_ETH_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MSP_INT_MAC0, + .end = MSP_INT_MAC0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource msp_eth1_resources[] = { + [0] = { + .start = MSP_MAC1_BASE, + .end = MSP_MAC1_BASE + MSP_ETH_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MSP_INT_MAC1, + .end = MSP_INT_MAC1, + .flags = IORESOURCE_IRQ, + }, +}; + + + +static struct platform_device mspeth_device[] = { + [0] = { + .name = MSP_ETH_ID, + .id = 0, + .num_resources = ARRAY_SIZE(msp_eth0_resources), + .resource = msp_eth0_resources, + }, + [1] = { + .name = MSP_ETH_ID, + .id = 1, + .num_resources = ARRAY_SIZE(msp_eth1_resources), + .resource = msp_eth1_resources, + }, + +}; +#define msp_eth_devs mspeth_device + +#endif +int __init msp_eth_setup(void) +{ + int i, ret = 0; + + /* Configure the GPIO and take the ethernet PHY out of reset */ + msp_gpio_pin_mode(MSP_GPIO_OUTPUT, MSP_ETHERNET_GPIO0); + msp_gpio_pin_hi(MSP_ETHERNET_GPIO0); + +#ifdef CONFIG_MSP_HAS_TSMAC + /* 3 phys on boards with TSMAC */ + msp_gpio_pin_mode(MSP_GPIO_OUTPUT, MSP_ETHERNET_GPIO1); + msp_gpio_pin_hi(MSP_ETHERNET_GPIO1); + + msp_gpio_pin_mode(MSP_GPIO_OUTPUT, MSP_ETHERNET_GPIO2); + msp_gpio_pin_hi(MSP_ETHERNET_GPIO2); +#endif + for (i = 0; i < ARRAY_SIZE(msp_eth_devs); i++) { + ret = platform_device_register(&msp_eth_devs[i]); + printk(KERN_INFO "device: %d, return value = %d\n", i, ret); + if (ret) { + platform_device_unregister(&msp_eth_devs[i]); + break; + } + } + + if (ret) + printk(KERN_WARNING "Could not initialize " + "MSPETH device structures.\n"); + + return ret; +} +subsys_initcall(msp_eth_setup); diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq.c b/arch/mips/pmc-sierra/msp71xx/msp_irq.c index 734d598a2e3..4531c4a514b 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_irq.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq.c @@ -19,8 +19,6 @@ #include <msp_int.h> -extern void msp_int_handle(void); - /* SLP bases systems */ extern void msp_slp_irq_init(void); extern void msp_slp_irq_dispatch(void); @@ -29,6 +27,18 @@ extern void msp_slp_irq_dispatch(void); extern void msp_cic_irq_init(void); extern void msp_cic_irq_dispatch(void); +/* VSMP support init */ +extern void msp_vsmp_int_init(void); + +/* vectored interrupt implementation */ + +/* SW0/1 interrupts are used for SMP/SMTC */ +static inline void mac0_int_dispatch(void) { do_IRQ(MSP_INT_MAC0); } +static inline void mac1_int_dispatch(void) { do_IRQ(MSP_INT_MAC1); } +static inline void mac2_int_dispatch(void) { do_IRQ(MSP_INT_SAR); } +static inline void usb_int_dispatch(void) { do_IRQ(MSP_INT_USB); } +static inline void sec_int_dispatch(void) { do_IRQ(MSP_INT_SEC); } + /* * The PMC-Sierra MSP interrupts are arranged in a 3 level cascaded * hierarchical system. The first level are the direct MIPS interrupts @@ -96,29 +106,57 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs) do_IRQ(MSP_INT_SW1); } -static struct irqaction cascade_msp = { +static struct irqaction cic_cascade_msp = { .handler = no_action, - .name = "MSP cascade" + .name = "MSP CIC cascade" }; +static struct irqaction per_cascade_msp = { + .handler = no_action, + .name = "MSP PER cascade" +}; void __init arch_init_irq(void) { + /* assume we'll be using vectored interrupt mode except in UP mode*/ +#ifdef CONFIG_MIPS_MT + BUG_ON(!cpu_has_vint); +#endif /* initialize the 1st-level CPU based interrupt controller */ mips_cpu_irq_init(); #ifdef CONFIG_IRQ_MSP_CIC msp_cic_irq_init(); - +#ifdef CONFIG_MIPS_MT + set_vi_handler(MSP_INT_CIC, msp_cic_irq_dispatch); + set_vi_handler(MSP_INT_MAC0, mac0_int_dispatch); + set_vi_handler(MSP_INT_MAC1, mac1_int_dispatch); + set_vi_handler(MSP_INT_SAR, mac2_int_dispatch); + set_vi_handler(MSP_INT_USB, usb_int_dispatch); + set_vi_handler(MSP_INT_SEC, sec_int_dispatch); +#ifdef CONFIG_MIPS_MT_SMP + msp_vsmp_int_init(); +#elif defined CONFIG_MIPS_MT_SMTC + /*Set hwmask for all platform devices */ + irq_hwmask[MSP_INT_MAC0] = C_IRQ0; + irq_hwmask[MSP_INT_MAC1] = C_IRQ1; + irq_hwmask[MSP_INT_USB] = C_IRQ2; + irq_hwmask[MSP_INT_SAR] = C_IRQ3; + irq_hwmask[MSP_INT_SEC] = C_IRQ5; + +#endif /* CONFIG_MIPS_MT_SMP */ +#endif /* CONFIG_MIPS_MT */ /* setup the cascaded interrupts */ - setup_irq(MSP_INT_CIC, &cascade_msp); - setup_irq(MSP_INT_PER, &cascade_msp); + setup_irq(MSP_INT_CIC, &cic_cascade_msp); + setup_irq(MSP_INT_PER, &per_cascade_msp); + #else /* setup the 2nd-level SLP register based interrupt controller */ + /* VSMP /SMTC support support is not enabled for SLP */ msp_slp_irq_init(); /* setup the cascaded SLP/PER interrupts */ - setup_irq(MSP_INT_SLP, &cascade_msp); - setup_irq(MSP_INT_PER, &cascade_msp); + setup_irq(MSP_INT_SLP, &cic_cascade_msp); + setup_irq(MSP_INT_PER, &per_cascade_msp); #endif } diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c index 07e71ff2433..c4fa2d775d8 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c @@ -1,8 +1,7 @@ /* - * This file define the irq handler for MSP SLM subsystem interrupts. + * Copyright 2010 PMC-Sierra, Inc, derived from irq_cpu.c * - * Copyright 2005-2007 PMC-Sierra, Inc, derived from irq_cpu.c - * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com + * This file define the irq handler for MSP CIC subsystem interrupts. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -16,119 +15,203 @@ #include <linux/bitops.h> #include <linux/irq.h> +#include <asm/mipsregs.h> #include <asm/system.h> #include <msp_cic_int.h> #include <msp_regs.h> /* - * NOTE: We are only enabling support for VPE0 right now. + * External API */ +extern void msp_per_irq_init(void); +extern void msp_per_irq_dispatch(void); -static inline void unmask_msp_cic_irq(unsigned int irq) + +/* + * Convenience Macro. Should be somewhere generic. + */ +#define get_current_vpe() \ + ((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE) + +#ifdef CONFIG_SMP + +#define LOCK_VPE(flags, mtflags) \ +do { \ + local_irq_save(flags); \ + mtflags = dmt(); \ +} while (0) + +#define UNLOCK_VPE(flags, mtflags) \ +do { \ + emt(mtflags); \ + local_irq_restore(flags);\ +} while (0) + +#define LOCK_CORE(flags, mtflags) \ +do { \ + local_irq_save(flags); \ + mtflags = dvpe(); \ +} while (0) + +#define UNLOCK_CORE(flags, mtflags) \ +do { \ + evpe(mtflags); \ + local_irq_restore(flags);\ +} while (0) + +#else + +#define LOCK_VPE(flags, mtflags) +#define UNLOCK_VPE(flags, mtflags) +#endif + +/* ensure writes to cic are completed */ +static inline void cic_wmb(void) { + const volatile void __iomem *cic_mem = CIC_VPE0_MSK_REG; + volatile u32 dummy_read; - /* check for PER interrupt range */ - if (irq < MSP_PER_INTBASE) - *CIC_VPE0_MSK_REG |= (1 << (irq - MSP_CIC_INTBASE)); - else - *PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE)); + wmb(); + dummy_read = __raw_readl(cic_mem); + dummy_read++; } -static inline void mask_msp_cic_irq(unsigned int irq) +static void unmask_cic_irq(struct irq_data *d) { - /* check for PER interrupt range */ - if (irq < MSP_PER_INTBASE) - *CIC_VPE0_MSK_REG &= ~(1 << (irq - MSP_CIC_INTBASE)); - else - *PER_INT_MSK_REG &= ~(1 << (irq - MSP_PER_INTBASE)); + volatile u32 *cic_msk_reg = CIC_VPE0_MSK_REG; + int vpe; +#ifdef CONFIG_SMP + unsigned int mtflags; + unsigned long flags; + + /* + * Make sure we have IRQ affinity. It may have changed while + * we were processing the IRQ. + */ + if (!cpumask_test_cpu(smp_processor_id(), d->affinity)) + return; +#endif + + vpe = get_current_vpe(); + LOCK_VPE(flags, mtflags); + cic_msk_reg[vpe] |= (1 << (d->irq - MSP_CIC_INTBASE)); + UNLOCK_VPE(flags, mtflags); + cic_wmb(); } -/* - * While we ack the interrupt interrupts are disabled and thus we don't need - * to deal with concurrency issues. Same for msp_cic_irq_end. - */ -static inline void ack_msp_cic_irq(unsigned int irq) +static void mask_cic_irq(struct irq_data *d) { - mask_msp_cic_irq(irq); - + volatile u32 *cic_msk_reg = CIC_VPE0_MSK_REG; + int vpe = get_current_vpe(); +#ifdef CONFIG_SMP + unsigned long flags, mtflags; +#endif + LOCK_VPE(flags, mtflags); + cic_msk_reg[vpe] &= ~(1 << (d->irq - MSP_CIC_INTBASE)); + UNLOCK_VPE(flags, mtflags); + cic_wmb(); +} +static void msp_cic_irq_ack(struct irq_data *d) +{ + mask_cic_irq(d); /* - * only really necessary for 18, 16-14 and sometimes 3:0 (since - * these can be edge sensitive) but it doesn't hurt for the others. - */ - - /* check for PER interrupt range */ - if (irq < MSP_PER_INTBASE) - *CIC_STS_REG = (1 << (irq - MSP_CIC_INTBASE)); - else - *PER_INT_STS_REG = (1 << (irq - MSP_PER_INTBASE)); + * Only really necessary for 18, 16-14 and sometimes 3:0 + * (since these can be edge sensitive) but it doesn't + * hurt for the others + */ + *CIC_STS_REG = (1 << (d->irq - MSP_CIC_INTBASE)); + smtc_im_ack_irq(d->irq); } +/*Note: Limiting to VSMP . Not tested in SMTC */ + +#ifdef CONFIG_MIPS_MT_SMP +static int msp_cic_irq_set_affinity(struct irq_data *d, + const struct cpumask *cpumask, bool force) +{ + int cpu; + unsigned long flags; + unsigned int mtflags; + unsigned long imask = (1 << (irq - MSP_CIC_INTBASE)); + volatile u32 *cic_mask = (volatile u32 *)CIC_VPE0_MSK_REG; + + /* timer balancing should be disabled in kernel code */ + BUG_ON(irq == MSP_INT_VPE0_TIMER || irq == MSP_INT_VPE1_TIMER); + + LOCK_CORE(flags, mtflags); + /* enable if any of each VPE's TCs require this IRQ */ + for_each_online_cpu(cpu) { + if (cpumask_test_cpu(cpu, cpumask)) + cic_mask[cpu] |= imask; + else + cic_mask[cpu] &= ~imask; + + } + + UNLOCK_CORE(flags, mtflags); + return 0; + +} +#endif + static struct irq_chip msp_cic_irq_controller = { .name = "MSP_CIC", - .ack = ack_msp_cic_irq, - .mask = ack_msp_cic_irq, - .mask_ack = ack_msp_cic_irq, - .unmask = unmask_msp_cic_irq, + .irq_mask = mask_cic_irq, + .irq_mask_ack = msp_cic_irq_ack, + .irq_unmask = unmask_cic_irq, + .irq_ack = msp_cic_irq_ack, +#ifdef CONFIG_MIPS_MT_SMP + .irq_set_affinity = msp_cic_irq_set_affinity, +#endif }; - void __init msp_cic_irq_init(void) { int i; - /* Mask/clear interrupts. */ *CIC_VPE0_MSK_REG = 0x00000000; - *PER_INT_MSK_REG = 0x00000000; + *CIC_VPE1_MSK_REG = 0x00000000; *CIC_STS_REG = 0xFFFFFFFF; - *PER_INT_STS_REG = 0xFFFFFFFF; - -#if defined(CONFIG_PMC_MSP7120_GW) || \ - defined(CONFIG_PMC_MSP7120_EVAL) /* - * The MSP7120 RG and EVBD boards use IRQ[6:4] for PCI. - * These inputs map to EXT_INT_POL[6:4] inside the CIC. - * They are to be active low, level sensitive. - */ + * The MSP7120 RG and EVBD boards use IRQ[6:4] for PCI. + * These inputs map to EXT_INT_POL[6:4] inside the CIC. + * They are to be active low, level sensitive. + */ *CIC_EXT_CFG_REG &= 0xFFFF8F8F; -#endif /* initialize all the IRQ descriptors */ - for (i = MSP_CIC_INTBASE; i < MSP_PER_INTBASE + 32; i++) - set_irq_chip_and_handler(i, &msp_cic_irq_controller, + for (i = MSP_CIC_INTBASE ; i < MSP_CIC_INTBASE + 32 ; i++) { + irq_set_chip_and_handler(i, &msp_cic_irq_controller, handle_level_irq); +#ifdef CONFIG_MIPS_MT_SMTC + /* Mask of CIC interrupt */ + irq_hwmask[i] = C_IRQ4; +#endif + } + + /* Initialize the PER interrupt sub-system */ + msp_per_irq_init(); } +/* CIC masked by CIC vector processing before dispatch called */ void msp_cic_irq_dispatch(void) { - u32 pending; - int intbase; - - intbase = MSP_CIC_INTBASE; - pending = *CIC_STS_REG & *CIC_VPE0_MSK_REG; - - /* check for PER interrupt */ - if (pending == (1 << (MSP_INT_PER - MSP_CIC_INTBASE))) { - intbase = MSP_PER_INTBASE; - pending = *PER_INT_STS_REG & *PER_INT_MSK_REG; - } - - /* check for spurious interrupt */ - if (pending == 0x00000000) { - printk(KERN_ERR - "Spurious %s interrupt? status %08x, mask %08x\n", - (intbase == MSP_CIC_INTBASE) ? "CIC" : "PER", - (intbase == MSP_CIC_INTBASE) ? - *CIC_STS_REG : *PER_INT_STS_REG, - (intbase == MSP_CIC_INTBASE) ? - *CIC_VPE0_MSK_REG : *PER_INT_MSK_REG); - return; - } - - /* check for the timer and dispatch it first */ - if ((intbase == MSP_CIC_INTBASE) && - (pending & (1 << (MSP_INT_VPE0_TIMER - MSP_CIC_INTBASE)))) + volatile u32 *cic_msk_reg = (volatile u32 *)CIC_VPE0_MSK_REG; + u32 cic_mask; + u32 pending; + int cic_status = *CIC_STS_REG; + cic_mask = cic_msk_reg[get_current_vpe()]; + pending = cic_status & cic_mask; + if (pending & (1 << (MSP_INT_VPE0_TIMER - MSP_CIC_INTBASE))) { do_IRQ(MSP_INT_VPE0_TIMER); - else - do_IRQ(ffs(pending) + intbase - 1); + } else if (pending & (1 << (MSP_INT_VPE1_TIMER - MSP_CIC_INTBASE))) { + do_IRQ(MSP_INT_VPE1_TIMER); + } else if (pending & (1 << (MSP_INT_PER - MSP_CIC_INTBASE))) { + msp_per_irq_dispatch(); + } else if (pending) { + do_IRQ(ffs(pending) + MSP_CIC_INTBASE - 1); + } else{ + spurious_interrupt(); + } } diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c new file mode 100644 index 00000000000..98fd0099d96 --- /dev/null +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c @@ -0,0 +1,135 @@ +/* + * Copyright 2010 PMC-Sierra, Inc, derived from irq_cpu.c + * + * This file define the irq handler for MSP PER subsystem interrupts. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/spinlock.h> +#include <linux/bitops.h> + +#include <asm/mipsregs.h> +#include <asm/system.h> + +#include <msp_cic_int.h> +#include <msp_regs.h> + + +/* + * Convenience Macro. Should be somewhere generic. + */ +#define get_current_vpe() \ + ((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE) + +#ifdef CONFIG_SMP +/* + * The PER registers must be protected from concurrent access. + */ + +static DEFINE_SPINLOCK(per_lock); +#endif + +/* ensure writes to per are completed */ + +static inline void per_wmb(void) +{ + const volatile void __iomem *per_mem = PER_INT_MSK_REG; + volatile u32 dummy_read; + + wmb(); + dummy_read = __raw_readl(per_mem); + dummy_read++; +} + +static inline void unmask_per_irq(struct irq_data *d) +{ +#ifdef CONFIG_SMP + unsigned long flags; + spin_lock_irqsave(&per_lock, flags); + *PER_INT_MSK_REG |= (1 << (d->irq - MSP_PER_INTBASE)); + spin_unlock_irqrestore(&per_lock, flags); +#else + *PER_INT_MSK_REG |= (1 << (d->irq - MSP_PER_INTBASE)); +#endif + per_wmb(); +} + +static inline void mask_per_irq(struct irq_data *d) +{ +#ifdef CONFIG_SMP + unsigned long flags; + spin_lock_irqsave(&per_lock, flags); + *PER_INT_MSK_REG &= ~(1 << (d->irq - MSP_PER_INTBASE)); + spin_unlock_irqrestore(&per_lock, flags); +#else + *PER_INT_MSK_REG &= ~(1 << (d->irq - MSP_PER_INTBASE)); +#endif + per_wmb(); +} + +static inline void msp_per_irq_ack(struct irq_data *d) +{ + mask_per_irq(d); + /* + * In the PER interrupt controller, only bits 11 and 10 + * are write-to-clear, (SPI TX complete, SPI RX complete). + * It does nothing for any others. + */ + *PER_INT_STS_REG = (1 << (d->irq - MSP_PER_INTBASE)); +} + +#ifdef CONFIG_SMP +static int msp_per_irq_set_affinity(struct irq_data *d, + const struct cpumask *affinity, bool force) +{ + /* WTF is this doing ????? */ + unmask_per_irq(d); + return 0; +} +#endif + +static struct irq_chip msp_per_irq_controller = { + .name = "MSP_PER", + .irq_enable = unmask_per_irq, + .irq_disable = mask_per_irq, + .irq_ack = msp_per_irq_ack, +#ifdef CONFIG_SMP + .irq_set_affinity = msp_per_irq_set_affinity, +#endif +}; + +void __init msp_per_irq_init(void) +{ + int i; + /* Mask/clear interrupts. */ + *PER_INT_MSK_REG = 0x00000000; + *PER_INT_STS_REG = 0xFFFFFFFF; + /* initialize all the IRQ descriptors */ + for (i = MSP_PER_INTBASE; i < MSP_PER_INTBASE + 32; i++) { + irq_set_chip(i, &msp_per_irq_controller); +#ifdef CONFIG_MIPS_MT_SMTC + irq_hwmask[i] = C_IRQ4; +#endif + } +} + +void msp_per_irq_dispatch(void) +{ + u32 per_mask = *PER_INT_MSK_REG; + u32 per_status = *PER_INT_STS_REG; + u32 pending; + + pending = per_status & per_mask; + if (pending) { + do_IRQ(ffs(pending) + MSP_PER_INTBASE - 1); + } else { + spurious_interrupt(); + } +} diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c index 61f39023234..5bbcc47da6b 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c @@ -21,8 +21,10 @@ #include <msp_slp_int.h> #include <msp_regs.h> -static inline void unmask_msp_slp_irq(unsigned int irq) +static inline void unmask_msp_slp_irq(struct irq_data *d) { + unsigned int irq = d->irq; + /* check for PER interrupt range */ if (irq < MSP_PER_INTBASE) *SLP_INT_MSK_REG |= (1 << (irq - MSP_SLP_INTBASE)); @@ -30,8 +32,10 @@ static inline void unmask_msp_slp_irq(unsigned int irq) *PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE)); } -static inline void mask_msp_slp_irq(unsigned int irq) +static inline void mask_msp_slp_irq(struct irq_data *d) { + unsigned int irq = d->irq; + /* check for PER interrupt range */ if (irq < MSP_PER_INTBASE) *SLP_INT_MSK_REG &= ~(1 << (irq - MSP_SLP_INTBASE)); @@ -43,8 +47,10 @@ static inline void mask_msp_slp_irq(unsigned int irq) * While we ack the interrupt interrupts are disabled and thus we don't need * to deal with concurrency issues. Same for msp_slp_irq_end. */ -static inline void ack_msp_slp_irq(unsigned int irq) +static inline void ack_msp_slp_irq(struct irq_data *d) { + unsigned int irq = d->irq; + /* check for PER interrupt range */ if (irq < MSP_PER_INTBASE) *SLP_INT_STS_REG = (1 << (irq - MSP_SLP_INTBASE)); @@ -54,9 +60,9 @@ static inline void ack_msp_slp_irq(unsigned int irq) static struct irq_chip msp_slp_irq_controller = { .name = "MSP_SLP", - .ack = ack_msp_slp_irq, - .mask = mask_msp_slp_irq, - .unmask = unmask_msp_slp_irq, + .irq_ack = ack_msp_slp_irq, + .irq_mask = mask_msp_slp_irq, + .irq_unmask = unmask_msp_slp_irq, }; void __init msp_slp_irq_init(void) @@ -71,7 +77,7 @@ void __init msp_slp_irq_init(void) /* initialize all the IRQ descriptors */ for (i = MSP_SLP_INTBASE; i < MSP_PER_INTBASE + 32; i++) - set_irq_chip_and_handler(i, &msp_slp_irq_controller, + irq_set_chip_and_handler(i, &msp_slp_irq_controller, handle_level_irq); } diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c index a54e85b3cf2..2413ea67877 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c @@ -146,6 +146,8 @@ void __init plat_mem_setup(void) pm_power_off = msp_power_off; } +extern struct plat_smp_ops msp_smtc_smp_ops; + void __init prom_init(void) { unsigned long family; @@ -226,10 +228,18 @@ void __init prom_init(void) */ msp_serial_setup(); +#ifdef CONFIG_MIPS_MT_SMP + register_smp_ops(&vsmp_smp_ops); +#endif + +#ifdef CONFIG_MIPS_MT_SMTC + register_smp_ops(&msp_smtc_smp_ops); +#endif + #ifdef CONFIG_PMCTWILED /* * Setup LED states before the subsys_initcall loads other - * dependant drivers/modules. + * dependent drivers/modules. */ pmctwiled_setup(); #endif diff --git a/arch/mips/pmc-sierra/msp71xx/msp_smp.c b/arch/mips/pmc-sierra/msp71xx/msp_smp.c new file mode 100644 index 00000000000..bec17901ff0 --- /dev/null +++ b/arch/mips/pmc-sierra/msp71xx/msp_smp.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. + * Copyright (C) 2001 Ralf Baechle + * Copyright (C) 2010 PMC-Sierra, Inc. + * + * VSMP support for MSP platforms . Derived from malta vsmp support. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +#include <linux/smp.h> +#include <linux/interrupt.h> + +#ifdef CONFIG_MIPS_MT_SMP +#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */ +#define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for call */ + + +static void ipi_resched_dispatch(void) +{ + do_IRQ(MIPS_CPU_IPI_RESCHED_IRQ); +} + +static void ipi_call_dispatch(void) +{ + do_IRQ(MIPS_CPU_IPI_CALL_IRQ); +} + +static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) +{ + return IRQ_HANDLED; +} + +static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) +{ + smp_call_function_interrupt(); + + return IRQ_HANDLED; +} + +static struct irqaction irq_resched = { + .handler = ipi_resched_interrupt, + .flags = IRQF_DISABLED | IRQF_PERCPU, + .name = "IPI_resched" +}; + +static struct irqaction irq_call = { + .handler = ipi_call_interrupt, + .flags = IRQF_DISABLED | IRQF_PERCPU, + .name = "IPI_call" +}; + +void __init arch_init_ipiirq(int irq, struct irqaction *action) +{ + setup_irq(irq, action); + irq_set_handler(irq, handle_percpu_irq); +} + +void __init msp_vsmp_int_init(void) +{ + set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); + set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); + arch_init_ipiirq(MIPS_CPU_IPI_RESCHED_IRQ, &irq_resched); + arch_init_ipiirq(MIPS_CPU_IPI_CALL_IRQ, &irq_call); +} +#endif /* CONFIG_MIPS_MT_SMP */ diff --git a/arch/mips/pmc-sierra/msp71xx/msp_smtc.c b/arch/mips/pmc-sierra/msp71xx/msp_smtc.c new file mode 100644 index 00000000000..c8dcc1c01e1 --- /dev/null +++ b/arch/mips/pmc-sierra/msp71xx/msp_smtc.c @@ -0,0 +1,105 @@ +/* + * MSP71xx Platform-specific hooks for SMP operation + */ +#include <linux/irq.h> +#include <linux/init.h> + +#include <asm/mipsmtregs.h> +#include <asm/mipsregs.h> +#include <asm/smtc.h> +#include <asm/smtc_ipi.h> + +/* VPE/SMP Prototype implements platform interfaces directly */ + +/* + * Cause the specified action to be performed on a targeted "CPU" + */ + +static void msp_smtc_send_ipi_single(int cpu, unsigned int action) +{ + /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ + smtc_send_ipi(cpu, LINUX_SMP_IPI, action); +} + +static void msp_smtc_send_ipi_mask(const struct cpumask *mask, + unsigned int action) +{ + unsigned int i; + + for_each_cpu(i, mask) + msp_smtc_send_ipi_single(i, action); +} + +/* + * Post-config but pre-boot cleanup entry point + */ +static void __cpuinit msp_smtc_init_secondary(void) +{ + int myvpe; + + /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */ + myvpe = read_c0_tcbind() & TCBIND_CURVPE; + if (myvpe > 0) + change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 | + STATUSF_IP6 | STATUSF_IP7); + smtc_init_secondary(); +} + +/* + * Platform "CPU" startup hook + */ +static void __cpuinit msp_smtc_boot_secondary(int cpu, + struct task_struct *idle) +{ + smtc_boot_secondary(cpu, idle); +} + +/* + * SMP initialization finalization entry point + */ +static void __cpuinit msp_smtc_smp_finish(void) +{ + smtc_smp_finish(); +} + +/* + * Hook for after all CPUs are online + */ + +static void msp_smtc_cpus_done(void) +{ +} + +/* + * Platform SMP pre-initialization + * + * As noted above, we can assume a single CPU for now + * but it may be multithreaded. + */ + +static void __init msp_smtc_smp_setup(void) +{ + /* + * we won't get the definitive value until + * we've run smtc_prepare_cpus later, but + */ + + if (read_c0_config3() & (1 << 2)) + smp_num_siblings = smtc_build_cpu_map(0); +} + +static void __init msp_smtc_prepare_cpus(unsigned int max_cpus) +{ + smtc_prepare_cpus(max_cpus); +} + +struct plat_smp_ops msp_smtc_smp_ops = { + .send_ipi_single = msp_smtc_send_ipi_single, + .send_ipi_mask = msp_smtc_send_ipi_mask, + .init_secondary = msp_smtc_init_secondary, + .smp_finish = msp_smtc_smp_finish, + .cpus_done = msp_smtc_cpus_done, + .boot_secondary = msp_smtc_boot_secondary, + .smp_setup = msp_smtc_smp_setup, + .prepare_cpus = msp_smtc_prepare_cpus, +}; diff --git a/arch/mips/pmc-sierra/msp71xx/msp_time.c b/arch/mips/pmc-sierra/msp71xx/msp_time.c index 01df84ce31e..8b42f307a7a 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_time.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_time.c @@ -29,6 +29,7 @@ #include <linux/module.h> #include <linux/ptrace.h> +#include <asm/cevt-r4k.h> #include <asm/mipsregs.h> #include <asm/time.h> @@ -36,6 +37,12 @@ #include <msp_int.h> #include <msp_regs.h> +#define get_current_vpe() \ + ((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE) + +static struct irqaction timer_vpe1; +static int tim_installed; + void __init plat_time_init(void) { char *endp, *s; @@ -83,5 +90,12 @@ void __init plat_time_init(void) unsigned int __cpuinit get_c0_compare_int(void) { - return MSP_INT_VPE0_TIMER; + /* MIPS_MT modes may want timer for second VPE */ + if ((get_current_vpe()) && !tim_installed) { + memcpy(&timer_vpe1, &c0_compare_irqaction, sizeof(timer_vpe1)); + setup_irq(MSP_INT_VPE1_TIMER, &timer_vpe1); + tim_installed++; + } + + return get_current_vpe() ? MSP_INT_VPE1_TIMER : MSP_INT_VPE0_TIMER; } diff --git a/arch/mips/pmc-sierra/msp71xx/msp_usb.c b/arch/mips/pmc-sierra/msp71xx/msp_usb.c index 0ee01e359dd..9a1aef89bd4 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_usb.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_usb.c @@ -1,7 +1,7 @@ /* * The setup file for USB related hardware on PMC-Sierra MSP processors. * - * Copyright 2006-2007 PMC-Sierra, Inc. + * Copyright 2006 PMC-Sierra, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -23,8 +23,8 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ +#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_GADGET) -#include <linux/dma-mapping.h> #include <linux/init.h> #include <linux/ioport.h> #include <linux/platform_device.h> @@ -34,40 +34,56 @@ #include <msp_regs.h> #include <msp_int.h> #include <msp_prom.h> +#include <msp_usb.h> + #if defined(CONFIG_USB_EHCI_HCD) -static struct resource msp_usbhost_resources [] = { - [0] = { - .start = MSP_USB_BASE_START, - .end = MSP_USB_BASE_END, - .flags = IORESOURCE_MEM, +static struct resource msp_usbhost0_resources[] = { + [0] = { /* EHCI-HS operational and capabilities registers */ + .start = MSP_USB0_HS_START, + .end = MSP_USB0_HS_END, + .flags = IORESOURCE_MEM, }, [1] = { - .start = MSP_INT_USB, - .end = MSP_INT_USB, - .flags = IORESOURCE_IRQ, + .start = MSP_INT_USB, + .end = MSP_INT_USB, + .flags = IORESOURCE_IRQ, + }, + [2] = { /* MSBus-to-AMBA bridge register space */ + .start = MSP_USB0_MAB_START, + .end = MSP_USB0_MAB_END, + .flags = IORESOURCE_MEM, + }, + [3] = { /* Identification and general hardware parameters */ + .start = MSP_USB0_ID_START, + .end = MSP_USB0_ID_END, + .flags = IORESOURCE_MEM, }, }; -static u64 msp_usbhost_dma_mask = DMA_BIT_MASK(32); +static u64 msp_usbhost0_dma_mask = 0xffffffffUL; -static struct platform_device msp_usbhost_device = { - .name = "pmcmsp-ehci", - .id = 0, +static struct mspusb_device msp_usbhost0_device = { .dev = { - .dma_mask = &msp_usbhost_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), + .name = "pmcmsp-ehci", + .id = 0, + .dev = { + .dma_mask = &msp_usbhost0_dma_mask, + .coherent_dma_mask = 0xffffffffUL, + }, + .num_resources = ARRAY_SIZE(msp_usbhost0_resources), + .resource = msp_usbhost0_resources, }, - .num_resources = ARRAY_SIZE(msp_usbhost_resources), - .resource = msp_usbhost_resources, }; -#endif /* CONFIG_USB_EHCI_HCD */ -#if defined(CONFIG_USB_GADGET) -static struct resource msp_usbdev_resources [] = { - [0] = { - .start = MSP_USB_BASE, - .end = MSP_USB_BASE_END, +/* MSP7140/MSP82XX has two USB2 hosts. */ +#ifdef CONFIG_MSP_HAS_DUAL_USB +static u64 msp_usbhost1_dma_mask = 0xffffffffUL; + +static struct resource msp_usbhost1_resources[] = { + [0] = { /* EHCI-HS operational and capabilities registers */ + .start = MSP_USB1_HS_START, + .end = MSP_USB1_HS_END, .flags = IORESOURCE_MEM, }, [1] = { @@ -75,76 +91,173 @@ static struct resource msp_usbdev_resources [] = { .end = MSP_INT_USB, .flags = IORESOURCE_IRQ, }, + [2] = { /* MSBus-to-AMBA bridge register space */ + .start = MSP_USB1_MAB_START, + .end = MSP_USB1_MAB_END, + .flags = IORESOURCE_MEM, + }, + [3] = { /* Identification and general hardware parameters */ + .start = MSP_USB1_ID_START, + .end = MSP_USB1_ID_END, + .flags = IORESOURCE_MEM, + }, +}; + +static struct mspusb_device msp_usbhost1_device = { + .dev = { + .name = "pmcmsp-ehci", + .id = 1, + .dev = { + .dma_mask = &msp_usbhost1_dma_mask, + .coherent_dma_mask = 0xffffffffUL, + }, + .num_resources = ARRAY_SIZE(msp_usbhost1_resources), + .resource = msp_usbhost1_resources, + }, }; +#endif /* CONFIG_MSP_HAS_DUAL_USB */ +#endif /* CONFIG_USB_EHCI_HCD */ -static u64 msp_usbdev_dma_mask = DMA_BIT_MASK(32); +#if defined(CONFIG_USB_GADGET) +static struct resource msp_usbdev0_resources[] = { + [0] = { /* EHCI-HS operational and capabilities registers */ + .start = MSP_USB0_HS_START, + .end = MSP_USB0_HS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MSP_INT_USB, + .end = MSP_INT_USB, + .flags = IORESOURCE_IRQ, + }, + [2] = { /* MSBus-to-AMBA bridge register space */ + .start = MSP_USB0_MAB_START, + .end = MSP_USB0_MAB_END, + .flags = IORESOURCE_MEM, + }, + [3] = { /* Identification and general hardware parameters */ + .start = MSP_USB0_ID_START, + .end = MSP_USB0_ID_END, + .flags = IORESOURCE_MEM, + }, +}; -static struct platform_device msp_usbdev_device = { - .name = "msp71xx_udc", - .id = 0, +static u64 msp_usbdev_dma_mask = 0xffffffffUL; + +/* This may need to be converted to a mspusb_device, too. */ +static struct mspusb_device msp_usbdev0_device = { .dev = { - .dma_mask = &msp_usbdev_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), + .name = "msp71xx_udc", + .id = 0, + .dev = { + .dma_mask = &msp_usbdev_dma_mask, + .coherent_dma_mask = 0xffffffffUL, + }, + .num_resources = ARRAY_SIZE(msp_usbdev0_resources), + .resource = msp_usbdev0_resources, }, - .num_resources = ARRAY_SIZE(msp_usbdev_resources), - .resource = msp_usbdev_resources, }; -#endif /* CONFIG_USB_GADGET */ -#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_GADGET) -static struct platform_device *msp_devs[1]; -#endif +#ifdef CONFIG_MSP_HAS_DUAL_USB +static struct resource msp_usbdev1_resources[] = { + [0] = { /* EHCI-HS operational and capabilities registers */ + .start = MSP_USB1_HS_START, + .end = MSP_USB1_HS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MSP_INT_USB, + .end = MSP_INT_USB, + .flags = IORESOURCE_IRQ, + }, + [2] = { /* MSBus-to-AMBA bridge register space */ + .start = MSP_USB1_MAB_START, + .end = MSP_USB1_MAB_END, + .flags = IORESOURCE_MEM, + }, + [3] = { /* Identification and general hardware parameters */ + .start = MSP_USB1_ID_START, + .end = MSP_USB1_ID_END, + .flags = IORESOURCE_MEM, + }, +}; +/* This may need to be converted to a mspusb_device, too. */ +static struct mspusb_device msp_usbdev1_device = { + .dev = { + .name = "msp71xx_udc", + .id = 0, + .dev = { + .dma_mask = &msp_usbdev_dma_mask, + .coherent_dma_mask = 0xffffffffUL, + }, + .num_resources = ARRAY_SIZE(msp_usbdev1_resources), + .resource = msp_usbdev1_resources, + }, +}; + +#endif /* CONFIG_MSP_HAS_DUAL_USB */ +#endif /* CONFIG_USB_GADGET */ static int __init msp_usb_setup(void) { -#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_GADGET) - char *strp; - char envstr[32]; - unsigned int val = 0; - int result = 0; + char *strp; + char envstr[32]; + struct platform_device *msp_devs[NUM_USB_DEVS]; + unsigned int val; + /* construct environment name usbmode */ + /* set usbmode <host/device> as pmon environment var */ /* - * construct environment name usbmode - * set usbmode <host/device> as pmon environment var + * Could this perhaps be integrated into the "features" env var? + * Use the features key "U", and follow with "H" for host-mode, + * "D" for device-mode. If it works for Ethernet, why not USB... + * -- hammtrev, 2007/03/22 */ snprintf((char *)&envstr[0], sizeof(envstr), "usbmode"); -#if defined(CONFIG_USB_EHCI_HCD) - /* default to host mode */ + /* set default host mode */ val = 1; -#endif /* get environment string */ strp = prom_getenv((char *)&envstr[0]); if (strp) { + /* compare string */ if (!strcmp(strp, "device")) val = 0; } if (val) { #if defined(CONFIG_USB_EHCI_HCD) - /* get host mode device */ - msp_devs[0] = &msp_usbhost_device; - ppfinit("platform add USB HOST done %s.\n", - msp_devs[0]->name); - - result = platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs)); -#endif /* CONFIG_USB_EHCI_HCD */ - } + msp_devs[0] = &msp_usbhost0_device.dev; + ppfinit("platform add USB HOST done %s.\n", msp_devs[0]->name); +#ifdef CONFIG_MSP_HAS_DUAL_USB + msp_devs[1] = &msp_usbhost1_device.dev; + ppfinit("platform add USB HOST done %s.\n", msp_devs[1]->name); +#endif +#else + ppfinit("%s: echi_hcd not supported\n", __FILE__); +#endif /* CONFIG_USB_EHCI_HCD */ + } else { #if defined(CONFIG_USB_GADGET) - else { /* get device mode structure */ - msp_devs[0] = &msp_usbdev_device; - ppfinit("platform add USB DEVICE done %s.\n", - msp_devs[0]->name); - - result = platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs)); + msp_devs[0] = &msp_usbdev0_device.dev; + ppfinit("platform add USB DEVICE done %s.\n" + , msp_devs[0]->name); +#ifdef CONFIG_MSP_HAS_DUAL_USB + msp_devs[1] = &msp_usbdev1_device.dev; + ppfinit("platform add USB DEVICE done %s.\n" + , msp_devs[1]->name); +#endif +#else + ppfinit("%s: usb_gadget not supported\n", __FILE__); +#endif /* CONFIG_USB_GADGET */ } -#endif /* CONFIG_USB_GADGET */ -#endif /* CONFIG_USB_EHCI_HCD || CONFIG_USB_GADGET */ + /* add device */ + platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs)); - return result; + return 0; } subsys_initcall(msp_usb_setup); +#endif /* CONFIG_USB_EHCI_HCD || CONFIG_USB_GADGET */ diff --git a/arch/mips/pmc-sierra/yosemite/Makefile b/arch/mips/pmc-sierra/yosemite/Makefile index b16f95c3df6..02f5fb94ea2 100644 --- a/arch/mips/pmc-sierra/yosemite/Makefile +++ b/arch/mips/pmc-sierra/yosemite/Makefile @@ -6,4 +6,4 @@ obj-y += irq.o prom.o py-console.o setup.o obj-$(CONFIG_SMP) += smp.o -EXTRA_CFLAGS += -Werror +ccflags-y := -Werror diff --git a/arch/mips/pnx833x/common/interrupts.c b/arch/mips/pnx833x/common/interrupts.c index 941916f8aaf..adc171c8846 100644 --- a/arch/mips/pnx833x/common/interrupts.c +++ b/arch/mips/pnx833x/common/interrupts.c @@ -152,10 +152,6 @@ static inline void pnx833x_hard_disable_pic_irq(unsigned int irq) PNX833X_PIC_INT_REG(irq) = 0; } -static int irqflags[PNX833X_PIC_NUM_IRQ]; /* initialized by zeroes */ -#define IRQFLAG_STARTED 1 -#define IRQFLAG_DISABLED 2 - static DEFINE_RAW_SPINLOCK(pnx833x_irq_lock); static unsigned int pnx833x_startup_pic_irq(unsigned int irq) @@ -164,108 +160,54 @@ static unsigned int pnx833x_startup_pic_irq(unsigned int irq) unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; raw_spin_lock_irqsave(&pnx833x_irq_lock, flags); - - irqflags[pic_irq] = IRQFLAG_STARTED; /* started, not disabled */ pnx833x_hard_enable_pic_irq(pic_irq); - raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags); return 0; } -static void pnx833x_shutdown_pic_irq(unsigned int irq) -{ - unsigned long flags; - unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; - - raw_spin_lock_irqsave(&pnx833x_irq_lock, flags); - - irqflags[pic_irq] = 0; /* not started */ - pnx833x_hard_disable_pic_irq(pic_irq); - - raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags); -} - -static void pnx833x_enable_pic_irq(unsigned int irq) +static void pnx833x_enable_pic_irq(struct irq_data *d) { unsigned long flags; - unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; + unsigned int pic_irq = d->irq - PNX833X_PIC_IRQ_BASE; raw_spin_lock_irqsave(&pnx833x_irq_lock, flags); - - irqflags[pic_irq] &= ~IRQFLAG_DISABLED; - if (irqflags[pic_irq] == IRQFLAG_STARTED) - pnx833x_hard_enable_pic_irq(pic_irq); - + pnx833x_hard_enable_pic_irq(pic_irq); raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags); } -static void pnx833x_disable_pic_irq(unsigned int irq) +static void pnx833x_disable_pic_irq(struct irq_data *d) { unsigned long flags; - unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; + unsigned int pic_irq = d->irq - PNX833X_PIC_IRQ_BASE; raw_spin_lock_irqsave(&pnx833x_irq_lock, flags); - - irqflags[pic_irq] |= IRQFLAG_DISABLED; pnx833x_hard_disable_pic_irq(pic_irq); - raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags); } -static void pnx833x_ack_pic_irq(unsigned int irq) -{ -} - -static void pnx833x_end_pic_irq(unsigned int irq) -{ -} - static DEFINE_RAW_SPINLOCK(pnx833x_gpio_pnx833x_irq_lock); -static unsigned int pnx833x_startup_gpio_irq(unsigned int irq) -{ - int pin = irq - PNX833X_GPIO_IRQ_BASE; - unsigned long flags; - raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); - pnx833x_gpio_enable_irq(pin); - raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags); - return 0; -} - -static void pnx833x_enable_gpio_irq(unsigned int irq) +static void pnx833x_enable_gpio_irq(struct irq_data *d) { - int pin = irq - PNX833X_GPIO_IRQ_BASE; + int pin = d->irq - PNX833X_GPIO_IRQ_BASE; unsigned long flags; raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); pnx833x_gpio_enable_irq(pin); raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags); } -static void pnx833x_disable_gpio_irq(unsigned int irq) +static void pnx833x_disable_gpio_irq(struct irq_data *d) { - int pin = irq - PNX833X_GPIO_IRQ_BASE; + int pin = d->irq - PNX833X_GPIO_IRQ_BASE; unsigned long flags; raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); pnx833x_gpio_disable_irq(pin); raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags); } -static void pnx833x_ack_gpio_irq(unsigned int irq) -{ -} - -static void pnx833x_end_gpio_irq(unsigned int irq) -{ - int pin = irq - PNX833X_GPIO_IRQ_BASE; - unsigned long flags; - raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); - pnx833x_gpio_clear_irq(pin); - raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags); -} - -static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type) +static int pnx833x_set_type_gpio_irq(struct irq_data *d, unsigned int flow_type) { - int pin = irq - PNX833X_GPIO_IRQ_BASE; + int pin = d->irq - PNX833X_GPIO_IRQ_BASE; int gpio_mode; switch (flow_type) { @@ -296,23 +238,15 @@ static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type) static struct irq_chip pnx833x_pic_irq_type = { .name = "PNX-PIC", - .startup = pnx833x_startup_pic_irq, - .shutdown = pnx833x_shutdown_pic_irq, - .enable = pnx833x_enable_pic_irq, - .disable = pnx833x_disable_pic_irq, - .ack = pnx833x_ack_pic_irq, - .end = pnx833x_end_pic_irq + .irq_enable = pnx833x_enable_pic_irq, + .irq_disable = pnx833x_disable_pic_irq, }; static struct irq_chip pnx833x_gpio_irq_type = { .name = "PNX-GPIO", - .startup = pnx833x_startup_gpio_irq, - .shutdown = pnx833x_disable_gpio_irq, - .enable = pnx833x_enable_gpio_irq, - .disable = pnx833x_disable_gpio_irq, - .ack = pnx833x_ack_gpio_irq, - .end = pnx833x_end_gpio_irq, - .set_type = pnx833x_set_type_gpio_irq + .irq_enable = pnx833x_enable_gpio_irq, + .irq_disable = pnx833x_disable_gpio_irq, + .irq_set_type = pnx833x_set_type_gpio_irq, }; void __init arch_init_irq(void) @@ -325,11 +259,13 @@ void __init arch_init_irq(void) /* Set IRQ information in irq_desc */ for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) { pnx833x_hard_disable_pic_irq(irq); - set_irq_chip_and_handler(irq, &pnx833x_pic_irq_type, handle_simple_irq); + irq_set_chip_and_handler(irq, &pnx833x_pic_irq_type, + handle_simple_irq); } for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++) - set_irq_chip_and_handler(irq, &pnx833x_gpio_irq_type, handle_simple_irq); + irq_set_chip_and_handler(irq, &pnx833x_gpio_irq_type, + handle_simple_irq); /* Set PIC priority limiter register to 0 */ PNX833X_PIC_INT_PRIORITY = 0; diff --git a/arch/mips/pnx833x/common/platform.c b/arch/mips/pnx833x/common/platform.c index ce45df17fd0..87167dcc79f 100644 --- a/arch/mips/pnx833x/common/platform.c +++ b/arch/mips/pnx833x/common/platform.c @@ -165,7 +165,7 @@ static struct i2c_pnx0105_dev pnx833x_i2c_dev[] = { { .base = PNX833X_I2C0_PORTS_START, .irq = -1, /* should be PNX833X_PIC_I2C0_INT but polling is faster */ - .clock = 6, /* 0 == 400 kHz, 4 == 100 kHz(Maximum HDMI), 6 = 50kHz(Prefered HDCP) */ + .clock = 6, /* 0 == 400 kHz, 4 == 100 kHz(Maximum HDMI), 6 = 50kHz(Preferred HDCP) */ .bus_addr = 0, /* no slave support */ }, { diff --git a/arch/mips/pnx8550/common/int.c b/arch/mips/pnx8550/common/int.c index cfed5051dc6..6b93c81779c 100644 --- a/arch/mips/pnx8550/common/int.c +++ b/arch/mips/pnx8550/common/int.c @@ -114,8 +114,10 @@ static inline void unmask_gic_int(unsigned int irq_nr) PNX8550_GIC_REQ(irq_nr) = (1<<26 | 1<<16) | (1<<28) | gic_prio[irq_nr]; } -static inline void mask_irq(unsigned int irq_nr) +static inline void mask_irq(struct irq_data *d) { + unsigned int irq_nr = d->irq; + if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) { modify_cp0_intmask(1 << irq_nr, 0); } else if ((PNX8550_INT_GIC_MIN <= irq_nr) && @@ -129,8 +131,10 @@ static inline void mask_irq(unsigned int irq_nr) } } -static inline void unmask_irq(unsigned int irq_nr) +static inline void unmask_irq(struct irq_data *d) { + unsigned int irq_nr = d->irq; + if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) { modify_cp0_intmask(0, 1 << irq_nr); } else if ((PNX8550_INT_GIC_MIN <= irq_nr) && @@ -157,10 +161,8 @@ int pnx8550_set_gic_priority(int irq, int priority) static struct irq_chip level_irq_type = { .name = "PNX Level IRQ", - .ack = mask_irq, - .mask = mask_irq, - .mask_ack = mask_irq, - .unmask = unmask_irq, + .irq_mask = mask_irq, + .irq_unmask = unmask_irq, }; static struct irqaction gic_action = { @@ -180,10 +182,8 @@ void __init arch_init_irq(void) int i; int configPR; - for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { - set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); - mask_irq(i); /* mask the irq just in case */ - } + for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) + irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq); /* init of GIC/IPC interrupts */ /* should be done before cp0 since cp0 init enables the GIC int */ @@ -206,7 +206,7 @@ void __init arch_init_irq(void) /* mask/priority is still 0 so we will not get any * interrupts until it is unmasked */ - set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq); } /* Priority level 0 */ @@ -215,20 +215,20 @@ void __init arch_init_irq(void) /* Set int vector table address */ PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; - set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type, + irq_set_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type, handle_level_irq); setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); /* init of Timer interrupts */ for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) - set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq); /* Stop Timer 1-3 */ configPR = read_c0_config7(); configPR |= 0x00000038; write_c0_config7(configPR); - set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type, + irq_set_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type, handle_level_irq); setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); } diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S index dbb5c7b4b70..f8a751c0328 100644 --- a/arch/mips/power/hibernate.S +++ b/arch/mips/power/hibernate.S @@ -35,7 +35,7 @@ LEAF(swsusp_arch_resume) 0: PTR_L t1, PBE_ADDRESS(t0) /* source */ PTR_L t2, PBE_ORIG_ADDRESS(t0) /* destination */ - PTR_ADDIU t3, t1, PAGE_SIZE + PTR_ADDU t3, t1, PAGE_SIZE 1: REG_L t8, (t1) REG_S t8, (t2) diff --git a/arch/mips/powertv/Makefile b/arch/mips/powertv/Makefile index baf6e9092a9..348d2e850ef 100644 --- a/arch/mips/powertv/Makefile +++ b/arch/mips/powertv/Makefile @@ -28,4 +28,4 @@ obj-y += init.o ioremap.o memory.o powertv_setup.o reset.o time.o \ obj-$(CONFIG_USB) += powertv-usb.o -EXTRA_CFLAGS += -Wall +ccflags-y := -Wall diff --git a/arch/mips/powertv/asic/Makefile b/arch/mips/powertv/asic/Makefile index f0e95dc0ac9..d810a33182a 100644 --- a/arch/mips/powertv/asic/Makefile +++ b/arch/mips/powertv/asic/Makefile @@ -20,4 +20,4 @@ obj-y += asic-calliope.o asic-cronus.o asic-gaia.o asic-zeus.o \ asic_devices.o asic_int.o irq_asic.o prealloc-calliope.o \ prealloc-cronus.o prealloc-cronuslite.o prealloc-gaia.o prealloc-zeus.o -EXTRA_CFLAGS += -Wall -Werror +ccflags-y := -Wall -Werror diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c index e5538243415..7fb97fb0931 100644 --- a/arch/mips/powertv/asic/irq_asic.c +++ b/arch/mips/powertv/asic/irq_asic.c @@ -21,9 +21,10 @@ #include <asm/mach-powertv/asic_regs.h> -static inline void unmask_asic_irq(unsigned int irq) +static inline void unmask_asic_irq(struct irq_data *d) { unsigned long enable_bit; + unsigned int irq = d->irq; enable_bit = (1 << (irq & 0x1f)); @@ -45,9 +46,10 @@ static inline void unmask_asic_irq(unsigned int irq) } } -static inline void mask_asic_irq(unsigned int irq) +static inline void mask_asic_irq(struct irq_data *d) { unsigned long disable_mask; + unsigned int irq = d->irq; disable_mask = ~(1 << (irq & 0x1f)); @@ -71,11 +73,8 @@ static inline void mask_asic_irq(unsigned int irq) static struct irq_chip asic_irq_chip = { .name = "ASIC Level", - .ack = mask_asic_irq, - .mask = mask_asic_irq, - .mask_ack = mask_asic_irq, - .unmask = unmask_asic_irq, - .eoi = unmask_asic_irq, + .irq_mask = mask_asic_irq, + .irq_unmask = unmask_asic_irq, }; void __init asic_irq_init(void) @@ -113,5 +112,5 @@ void __init asic_irq_init(void) * Initialize interrupt handlers. */ for (i = 0; i < NR_IRQS; i++) - set_irq_chip_and_handler(i, &asic_irq_chip, handle_level_irq); + irq_set_chip_and_handler(i, &asic_irq_chip, handle_level_irq); } diff --git a/arch/mips/powertv/pci/Makefile b/arch/mips/powertv/pci/Makefile index f5c62462fc9..5783201cd2c 100644 --- a/arch/mips/powertv/pci/Makefile +++ b/arch/mips/powertv/pci/Makefile @@ -18,4 +18,4 @@ obj-$(CONFIG_PCI) += fixup-powertv.o -EXTRA_CFLAGS += -Wall -Werror +ccflags-y := -Wall -Werror diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c index ea6cec3c1e0..7c6db74e3fa 100644 --- a/arch/mips/rb532/irq.c +++ b/arch/mips/rb532/irq.c @@ -111,10 +111,10 @@ static inline void ack_local_irq(unsigned int ip) clear_c0_cause(ipnum); } -static void rb532_enable_irq(unsigned int irq_nr) +static void rb532_enable_irq(struct irq_data *d) { + unsigned int group, intr_bit, irq_nr = d->irq; int ip = irq_nr - GROUP0_IRQ_BASE; - unsigned int group, intr_bit; volatile unsigned int *addr; if (ip < 0) @@ -132,10 +132,10 @@ static void rb532_enable_irq(unsigned int irq_nr) } } -static void rb532_disable_irq(unsigned int irq_nr) +static void rb532_disable_irq(struct irq_data *d) { + unsigned int group, intr_bit, mask, irq_nr = d->irq; int ip = irq_nr - GROUP0_IRQ_BASE; - unsigned int group, intr_bit, mask; volatile unsigned int *addr; if (ip < 0) { @@ -163,18 +163,18 @@ static void rb532_disable_irq(unsigned int irq_nr) } } -static void rb532_mask_and_ack_irq(unsigned int irq_nr) +static void rb532_mask_and_ack_irq(struct irq_data *d) { - rb532_disable_irq(irq_nr); - ack_local_irq(group_to_ip(irq_to_group(irq_nr))); + rb532_disable_irq(d); + ack_local_irq(group_to_ip(irq_to_group(d->irq))); } -static int rb532_set_type(unsigned int irq_nr, unsigned type) +static int rb532_set_type(struct irq_data *d, unsigned type) { - int gpio = irq_nr - GPIO_MAPPED_IRQ_BASE; - int group = irq_to_group(irq_nr); + int gpio = d->irq - GPIO_MAPPED_IRQ_BASE; + int group = irq_to_group(d->irq); - if (group != GPIO_MAPPED_IRQ_GROUP || irq_nr > (GROUP4_IRQ_BASE + 13)) + if (group != GPIO_MAPPED_IRQ_GROUP || d->irq > (GROUP4_IRQ_BASE + 13)) return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL; switch (type) { @@ -193,11 +193,11 @@ static int rb532_set_type(unsigned int irq_nr, unsigned type) static struct irq_chip rc32434_irq_type = { .name = "RB532", - .ack = rb532_disable_irq, - .mask = rb532_disable_irq, - .mask_ack = rb532_mask_and_ack_irq, - .unmask = rb532_enable_irq, - .set_type = rb532_set_type, + .irq_ack = rb532_disable_irq, + .irq_mask = rb532_disable_irq, + .irq_mask_ack = rb532_mask_and_ack_irq, + .irq_unmask = rb532_enable_irq, + .irq_set_type = rb532_set_type, }; void __init arch_init_irq(void) @@ -207,8 +207,8 @@ void __init arch_init_irq(void) pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS); for (i = 0; i < RC32434_NR_IRQS; i++) - set_irq_chip_and_handler(i, &rc32434_irq_type, - handle_level_irq); + irq_set_chip_and_handler(i, &rc32434_irq_type, + handle_level_irq); } /* Main Interrupt dispatcher */ diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c index 383f11d7f44..476423a0129 100644 --- a/arch/mips/sgi-ip22/ip22-int.c +++ b/arch/mips/sgi-ip22/ip22-int.c @@ -31,88 +31,80 @@ static char lc3msk_to_irqnr[256]; extern int ip22_eisa_init(void); -static void enable_local0_irq(unsigned int irq) +static void enable_local0_irq(struct irq_data *d) { /* don't allow mappable interrupt to be enabled from setup_irq, * we have our own way to do so */ - if (irq != SGI_MAP_0_IRQ) - sgint->imask0 |= (1 << (irq - SGINT_LOCAL0)); + if (d->irq != SGI_MAP_0_IRQ) + sgint->imask0 |= (1 << (d->irq - SGINT_LOCAL0)); } -static void disable_local0_irq(unsigned int irq) +static void disable_local0_irq(struct irq_data *d) { - sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0)); + sgint->imask0 &= ~(1 << (d->irq - SGINT_LOCAL0)); } static struct irq_chip ip22_local0_irq_type = { .name = "IP22 local 0", - .ack = disable_local0_irq, - .mask = disable_local0_irq, - .mask_ack = disable_local0_irq, - .unmask = enable_local0_irq, + .irq_mask = disable_local0_irq, + .irq_unmask = enable_local0_irq, }; -static void enable_local1_irq(unsigned int irq) +static void enable_local1_irq(struct irq_data *d) { /* don't allow mappable interrupt to be enabled from setup_irq, * we have our own way to do so */ - if (irq != SGI_MAP_1_IRQ) - sgint->imask1 |= (1 << (irq - SGINT_LOCAL1)); + if (d->irq != SGI_MAP_1_IRQ) + sgint->imask1 |= (1 << (d->irq - SGINT_LOCAL1)); } -static void disable_local1_irq(unsigned int irq) +static void disable_local1_irq(struct irq_data *d) { - sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1)); + sgint->imask1 &= ~(1 << (d->irq - SGINT_LOCAL1)); } static struct irq_chip ip22_local1_irq_type = { .name = "IP22 local 1", - .ack = disable_local1_irq, - .mask = disable_local1_irq, - .mask_ack = disable_local1_irq, - .unmask = enable_local1_irq, + .irq_mask = disable_local1_irq, + .irq_unmask = enable_local1_irq, }; -static void enable_local2_irq(unsigned int irq) +static void enable_local2_irq(struct irq_data *d) { sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0)); - sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2)); + sgint->cmeimask0 |= (1 << (d->irq - SGINT_LOCAL2)); } -static void disable_local2_irq(unsigned int irq) +static void disable_local2_irq(struct irq_data *d) { - sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2)); + sgint->cmeimask0 &= ~(1 << (d->irq - SGINT_LOCAL2)); if (!sgint->cmeimask0) sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0)); } static struct irq_chip ip22_local2_irq_type = { .name = "IP22 local 2", - .ack = disable_local2_irq, - .mask = disable_local2_irq, - .mask_ack = disable_local2_irq, - .unmask = enable_local2_irq, + .irq_mask = disable_local2_irq, + .irq_unmask = enable_local2_irq, }; -static void enable_local3_irq(unsigned int irq) +static void enable_local3_irq(struct irq_data *d) { sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1)); - sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3)); + sgint->cmeimask1 |= (1 << (d->irq - SGINT_LOCAL3)); } -static void disable_local3_irq(unsigned int irq) +static void disable_local3_irq(struct irq_data *d) { - sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3)); + sgint->cmeimask1 &= ~(1 << (d->irq - SGINT_LOCAL3)); if (!sgint->cmeimask1) sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1)); } static struct irq_chip ip22_local3_irq_type = { .name = "IP22 local 3", - .ack = disable_local3_irq, - .mask = disable_local3_irq, - .mask_ack = disable_local3_irq, - .unmask = enable_local3_irq, + .irq_mask = disable_local3_irq, + .irq_unmask = enable_local3_irq, }; static void indy_local0_irqdispatch(void) @@ -320,7 +312,7 @@ void __init arch_init_irq(void) else handler = &ip22_local3_irq_type; - set_irq_chip_and_handler(i, handler, handle_level_irq); + irq_set_chip_and_handler(i, handler, handle_level_irq); } /* vector handler. this register the IRQ as non-sharable */ diff --git a/arch/mips/sgi-ip22/ip22-platform.c b/arch/mips/sgi-ip22/ip22-platform.c index deddbf0ebe5..698904daf90 100644 --- a/arch/mips/sgi-ip22/ip22-platform.c +++ b/arch/mips/sgi-ip22/ip22-platform.c @@ -132,7 +132,7 @@ static struct platform_device eth1_device = { */ static int __init sgiseeq_devinit(void) { - unsigned int tmp; + unsigned int pbdma __maybe_unused; int res, i; eth0_pd.hpc = hpc3c0; @@ -151,7 +151,7 @@ static int __init sgiseeq_devinit(void) /* Second HPC is missing? */ if (ip22_is_fullhouse() || - get_dbe(tmp, (unsigned int *)&hpc3c1->pbdma[1])) + get_dbe(pbdma, (unsigned int *)&hpc3c1->pbdma[1])) return 0; sgimc->giopar |= SGIMC_GIOPAR_MASTEREXP1 | SGIMC_GIOPAR_EXP164 | diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c index 603fc91c103..1a94c989418 100644 --- a/arch/mips/sgi-ip22/ip22-time.c +++ b/arch/mips/sgi-ip22/ip22-time.c @@ -32,7 +32,7 @@ static unsigned long dosample(void) { u32 ct0, ct1; - u8 msb, lsb; + u8 msb; /* Start the counter. */ sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | @@ -46,7 +46,7 @@ static unsigned long dosample(void) /* Latch and spin until top byte of counter2 is zero */ do { writeb(SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT, &sgint->tcword); - lsb = readb(&sgint->tcnt2); + (void) readb(&sgint->tcnt2); msb = readb(&sgint->tcnt2); ct1 = read_c0_count(); } while (msb); diff --git a/arch/mips/sgi-ip27/Kconfig b/arch/mips/sgi-ip27/Kconfig index 5e960ae9735..bc5e9769bb7 100644 --- a/arch/mips/sgi-ip27/Kconfig +++ b/arch/mips/sgi-ip27/Kconfig @@ -1,7 +1,7 @@ #config SGI_SN0_XXL # bool "IP27 XXL" # depends on SGI_IP27 -# This options adds support for userspace processes upto 16TB size. +# This options adds support for userspace processes up to 16TB size. # Normally the limit is just .5TB. choice diff --git a/arch/mips/sgi-ip27/TODO b/arch/mips/sgi-ip27/TODO index 19f1512c8f2..160857ff148 100644 --- a/arch/mips/sgi-ip27/TODO +++ b/arch/mips/sgi-ip27/TODO @@ -13,7 +13,7 @@ being invoked on all nodes in ip27-memory.c. 9. start_thread must turn off UX64 ... and define tlb_refill_debug. 10. Need a bad pmd table, bad pte table. __bad_pmd_table/__bad_pagetable does not agree with pgd_bad/pmd_bad. -11. All intrs (ip27_do_irq handlers) are targetted at cpu A on the node. +11. All intrs (ip27_do_irq handlers) are targeted at cpu A on the node. This might need to change later. Only the timer intr is set up to be received on both Cpu A and B. (ip27_do_irq()/bridge_startup()) 13. Cache flushing (specially the SMP version) has to be investigated. diff --git a/arch/mips/sgi-ip27/ip27-hubio.c b/arch/mips/sgi-ip27/ip27-hubio.c index a1fa4abb3f6..cd0d5b06cd8 100644 --- a/arch/mips/sgi-ip27/ip27-hubio.c +++ b/arch/mips/sgi-ip27/ip27-hubio.c @@ -29,7 +29,6 @@ unsigned long hub_pio_map(cnodeid_t cnode, xwidgetnum_t widget, unsigned long xtalk_addr, size_t size) { nasid_t nasid = COMPACT_TO_NASID_NODEID(cnode); - volatile hubreg_t junk; unsigned i; /* use small-window mapping if possible */ @@ -64,7 +63,7 @@ unsigned long hub_pio_map(cnodeid_t cnode, xwidgetnum_t widget, * after we write it. */ IIO_ITTE_PUT(nasid, i, HUB_PIO_MAP_TO_MEM, widget, xtalk_addr); - junk = HUB_L(IIO_ITTE_GET(nasid, i)); + (void) HUB_L(IIO_ITTE_GET(nasid, i)); return NODE_BWIN_BASE(nasid, widget) + (xtalk_addr % BWIN_SIZE); } diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c index 51d3a4f2d7e..923c080f77b 100644 --- a/arch/mips/sgi-ip27/ip27-init.c +++ b/arch/mips/sgi-ip27/ip27-init.c @@ -93,7 +93,7 @@ static void __cpuinit per_hub_init(cnodeid_t cnode) /* * Some interrupts are reserved by hardware or by software convention. - * Mark these as reserved right away so they won't be used accidently + * Mark these as reserved right away so they won't be used accidentally * later. */ for (i = 0; i <= BASE_PCI_IRQ; i++) { diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index 6a123ea72de..0a04603d577 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c @@ -41,7 +41,7 @@ * Linux has a controller-independent x86 interrupt architecture. * every controller has a 'controller-template', that is used * by the main code to do the right thing. Each driver-visible - * interrupt source is transparently wired to the apropriate + * interrupt source is transparently wired to the appropriate * controller. Thus drivers need not be aware of the * interrupt-controller. * @@ -240,7 +240,7 @@ static int intr_disconnect_level(int cpu, int bit) } /* Startup one of the (PCI ...) IRQs routes over a bridge. */ -static unsigned int startup_bridge_irq(unsigned int irq) +static unsigned int startup_bridge_irq(struct irq_data *d) { struct bridge_controller *bc; bridgereg_t device; @@ -248,16 +248,16 @@ static unsigned int startup_bridge_irq(unsigned int irq) int pin, swlevel; cpuid_t cpu; - pin = SLOT_FROM_PCI_IRQ(irq); - bc = IRQ_TO_BRIDGE(irq); + pin = SLOT_FROM_PCI_IRQ(d->irq); + bc = IRQ_TO_BRIDGE(d->irq); bridge = bc->base; - pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", irq, pin); + pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", d->irq, pin); /* * "map" irq to a swlevel greater than 6 since the first 6 bits * of INT_PEND0 are taken */ - swlevel = find_level(&cpu, irq); + swlevel = find_level(&cpu, d->irq); bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8)); bridge->b_int_enable |= (1 << pin); bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */ @@ -288,58 +288,56 @@ static unsigned int startup_bridge_irq(unsigned int irq) } /* Shutdown one of the (PCI ...) IRQs routes over a bridge. */ -static void shutdown_bridge_irq(unsigned int irq) +static void shutdown_bridge_irq(struct irq_data *d) { - struct bridge_controller *bc = IRQ_TO_BRIDGE(irq); + struct bridge_controller *bc = IRQ_TO_BRIDGE(d->irq); bridge_t *bridge = bc->base; int pin, swlevel; cpuid_t cpu; - pr_debug("bridge_shutdown: irq 0x%x\n", irq); - pin = SLOT_FROM_PCI_IRQ(irq); + pr_debug("bridge_shutdown: irq 0x%x\n", d->irq); + pin = SLOT_FROM_PCI_IRQ(d->irq); /* * map irq to a swlevel greater than 6 since the first 6 bits * of INT_PEND0 are taken */ - swlevel = find_level(&cpu, irq); + swlevel = find_level(&cpu, d->irq); intr_disconnect_level(cpu, swlevel); bridge->b_int_enable &= ~(1 << pin); bridge->b_wid_tflush; } -static inline void enable_bridge_irq(unsigned int irq) +static inline void enable_bridge_irq(struct irq_data *d) { cpuid_t cpu; int swlevel; - swlevel = find_level(&cpu, irq); /* Criminal offence */ + swlevel = find_level(&cpu, d->irq); /* Criminal offence */ intr_connect_level(cpu, swlevel); } -static inline void disable_bridge_irq(unsigned int irq) +static inline void disable_bridge_irq(struct irq_data *d) { cpuid_t cpu; int swlevel; - swlevel = find_level(&cpu, irq); /* Criminal offence */ + swlevel = find_level(&cpu, d->irq); /* Criminal offence */ intr_disconnect_level(cpu, swlevel); } static struct irq_chip bridge_irq_type = { .name = "bridge", - .startup = startup_bridge_irq, - .shutdown = shutdown_bridge_irq, - .ack = disable_bridge_irq, - .mask = disable_bridge_irq, - .mask_ack = disable_bridge_irq, - .unmask = enable_bridge_irq, + .irq_startup = startup_bridge_irq, + .irq_shutdown = shutdown_bridge_irq, + .irq_mask = disable_bridge_irq, + .irq_unmask = enable_bridge_irq, }; void __devinit register_bridge_irq(unsigned int irq) { - set_irq_chip_and_handler(irq, &bridge_irq_type, handle_level_irq); + irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq); } int __devinit request_bridge_irq(struct bridge_controller *bc) diff --git a/arch/mips/sgi-ip27/ip27-klnuma.c b/arch/mips/sgi-ip27/ip27-klnuma.c index c3d30a88daf..1d1919a44e8 100644 --- a/arch/mips/sgi-ip27/ip27-klnuma.c +++ b/arch/mips/sgi-ip27/ip27-klnuma.c @@ -54,11 +54,8 @@ void __init setup_replication_mask(void) static __init void set_ktext_source(nasid_t client_nasid, nasid_t server_nasid) { - cnodeid_t client_cnode; kern_vars_t *kvp; - client_cnode = NASID_TO_COMPACT_NODEID(client_nasid); - kvp = &hub_data(client_nasid)->kern_vars; KERN_VARS_ADDR(client_nasid) = (unsigned long)kvp; diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index d6802d6d1f8..a152538d3c9 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -36,21 +36,18 @@ #include <asm/sn/sn0/hubio.h> #include <asm/pci/bridge.h> -static void enable_rt_irq(unsigned int irq) +static void enable_rt_irq(struct irq_data *d) { } -static void disable_rt_irq(unsigned int irq) +static void disable_rt_irq(struct irq_data *d) { } static struct irq_chip rt_irq_type = { .name = "SN HUB RT timer", - .ack = disable_rt_irq, - .mask = disable_rt_irq, - .mask_ack = disable_rt_irq, - .unmask = enable_rt_irq, - .eoi = enable_rt_irq, + .irq_mask = disable_rt_irq, + .irq_unmask = enable_rt_irq, }; static int rt_next_event(unsigned long delta, struct clock_event_device *evt) @@ -156,7 +153,7 @@ static void __init hub_rt_clock_event_global_init(void) panic("Allocation of irq number for timer failed"); } while (xchg(&rt_timer_irq, irq)); - set_irq_chip_and_handler(irq, &rt_irq_type, handle_percpu_irq); + irq_set_chip_and_handler(irq, &rt_irq_type, handle_percpu_irq); setup_irq(irq, &hub_rt_irqaction); } diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index eb40824b172..c65ea76d56c 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c @@ -130,70 +130,48 @@ static struct irqaction cpuerr_irq = { static uint64_t crime_mask; -static inline void crime_enable_irq(unsigned int irq) +static inline void crime_enable_irq(struct irq_data *d) { - unsigned int bit = irq - CRIME_IRQ_BASE; + unsigned int bit = d->irq - CRIME_IRQ_BASE; crime_mask |= 1 << bit; crime->imask = crime_mask; } -static inline void crime_disable_irq(unsigned int irq) +static inline void crime_disable_irq(struct irq_data *d) { - unsigned int bit = irq - CRIME_IRQ_BASE; + unsigned int bit = d->irq - CRIME_IRQ_BASE; crime_mask &= ~(1 << bit); crime->imask = crime_mask; flush_crime_bus(); } -static void crime_level_mask_and_ack_irq(unsigned int irq) -{ - crime_disable_irq(irq); -} - -static void crime_level_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - crime_enable_irq(irq); -} - static struct irq_chip crime_level_interrupt = { .name = "IP32 CRIME", - .ack = crime_level_mask_and_ack_irq, - .mask = crime_disable_irq, - .mask_ack = crime_level_mask_and_ack_irq, - .unmask = crime_enable_irq, - .end = crime_level_end_irq, + .irq_mask = crime_disable_irq, + .irq_unmask = crime_enable_irq, }; -static void crime_edge_mask_and_ack_irq(unsigned int irq) +static void crime_edge_mask_and_ack_irq(struct irq_data *d) { - unsigned int bit = irq - CRIME_IRQ_BASE; + unsigned int bit = d->irq - CRIME_IRQ_BASE; uint64_t crime_int; /* Edge triggered interrupts must be cleared. */ - crime_int = crime->hard_int; crime_int &= ~(1 << bit); crime->hard_int = crime_int; - crime_disable_irq(irq); -} - -static void crime_edge_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - crime_enable_irq(irq); + crime_disable_irq(d); } static struct irq_chip crime_edge_interrupt = { .name = "IP32 CRIME", - .ack = crime_edge_mask_and_ack_irq, - .mask = crime_disable_irq, - .mask_ack = crime_edge_mask_and_ack_irq, - .unmask = crime_enable_irq, - .end = crime_edge_end_irq, + .irq_ack = crime_edge_mask_and_ack_irq, + .irq_mask = crime_disable_irq, + .irq_mask_ack = crime_edge_mask_and_ack_irq, + .irq_unmask = crime_enable_irq, }; /* @@ -204,37 +182,28 @@ static struct irq_chip crime_edge_interrupt = { static unsigned long macepci_mask; -static void enable_macepci_irq(unsigned int irq) +static void enable_macepci_irq(struct irq_data *d) { - macepci_mask |= MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ); + macepci_mask |= MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ); mace->pci.control = macepci_mask; - crime_mask |= 1 << (irq - CRIME_IRQ_BASE); + crime_mask |= 1 << (d->irq - CRIME_IRQ_BASE); crime->imask = crime_mask; } -static void disable_macepci_irq(unsigned int irq) +static void disable_macepci_irq(struct irq_data *d) { - crime_mask &= ~(1 << (irq - CRIME_IRQ_BASE)); + crime_mask &= ~(1 << (d->irq - CRIME_IRQ_BASE)); crime->imask = crime_mask; flush_crime_bus(); - macepci_mask &= ~MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ); + macepci_mask &= ~MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ); mace->pci.control = macepci_mask; flush_mace_bus(); } -static void end_macepci_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_macepci_irq(irq); -} - static struct irq_chip ip32_macepci_interrupt = { .name = "IP32 MACE PCI", - .ack = disable_macepci_irq, - .mask = disable_macepci_irq, - .mask_ack = disable_macepci_irq, - .unmask = enable_macepci_irq, - .end = end_macepci_irq, + .irq_mask = disable_macepci_irq, + .irq_unmask = enable_macepci_irq, }; /* This is used for MACE ISA interrupts. That means bits 4-6 in the @@ -276,13 +245,13 @@ static struct irq_chip ip32_macepci_interrupt = { static unsigned long maceisa_mask; -static void enable_maceisa_irq(unsigned int irq) +static void enable_maceisa_irq(struct irq_data *d) { unsigned int crime_int = 0; - pr_debug("maceisa enable: %u\n", irq); + pr_debug("maceisa enable: %u\n", d->irq); - switch (irq) { + switch (d->irq) { case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ: crime_int = MACE_AUDIO_INT; break; @@ -296,15 +265,15 @@ static void enable_maceisa_irq(unsigned int irq) pr_debug("crime_int %08x enabled\n", crime_int); crime_mask |= crime_int; crime->imask = crime_mask; - maceisa_mask |= 1 << (irq - MACEISA_AUDIO_SW_IRQ); + maceisa_mask |= 1 << (d->irq - MACEISA_AUDIO_SW_IRQ); mace->perif.ctrl.imask = maceisa_mask; } -static void disable_maceisa_irq(unsigned int irq) +static void disable_maceisa_irq(struct irq_data *d) { unsigned int crime_int = 0; - maceisa_mask &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ)); + maceisa_mask &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ)); if (!(maceisa_mask & MACEISA_AUDIO_INT)) crime_int |= MACE_AUDIO_INT; if (!(maceisa_mask & MACEISA_MISC_INT)) @@ -318,76 +287,57 @@ static void disable_maceisa_irq(unsigned int irq) flush_mace_bus(); } -static void mask_and_ack_maceisa_irq(unsigned int irq) +static void mask_and_ack_maceisa_irq(struct irq_data *d) { unsigned long mace_int; /* edge triggered */ mace_int = mace->perif.ctrl.istat; - mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ)); + mace_int &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ)); mace->perif.ctrl.istat = mace_int; - disable_maceisa_irq(irq); -} - -static void end_maceisa_irq(unsigned irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - enable_maceisa_irq(irq); + disable_maceisa_irq(d); } static struct irq_chip ip32_maceisa_level_interrupt = { .name = "IP32 MACE ISA", - .ack = disable_maceisa_irq, - .mask = disable_maceisa_irq, - .mask_ack = disable_maceisa_irq, - .unmask = enable_maceisa_irq, - .end = end_maceisa_irq, + .irq_mask = disable_maceisa_irq, + .irq_unmask = enable_maceisa_irq, }; static struct irq_chip ip32_maceisa_edge_interrupt = { .name = "IP32 MACE ISA", - .ack = mask_and_ack_maceisa_irq, - .mask = disable_maceisa_irq, - .mask_ack = mask_and_ack_maceisa_irq, - .unmask = enable_maceisa_irq, - .end = end_maceisa_irq, + .irq_ack = mask_and_ack_maceisa_irq, + .irq_mask = disable_maceisa_irq, + .irq_mask_ack = mask_and_ack_maceisa_irq, + .irq_unmask = enable_maceisa_irq, }; /* This is used for regular non-ISA, non-PCI MACE interrupts. That means * bits 0-3 and 7 in the CRIME register. */ -static void enable_mace_irq(unsigned int irq) +static void enable_mace_irq(struct irq_data *d) { - unsigned int bit = irq - CRIME_IRQ_BASE; + unsigned int bit = d->irq - CRIME_IRQ_BASE; crime_mask |= (1 << bit); crime->imask = crime_mask; } -static void disable_mace_irq(unsigned int irq) +static void disable_mace_irq(struct irq_data *d) { - unsigned int bit = irq - CRIME_IRQ_BASE; + unsigned int bit = d->irq - CRIME_IRQ_BASE; crime_mask &= ~(1 << bit); crime->imask = crime_mask; flush_crime_bus(); } -static void end_mace_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_mace_irq(irq); -} - static struct irq_chip ip32_mace_interrupt = { .name = "IP32 MACE", - .ack = disable_mace_irq, - .mask = disable_mace_irq, - .mask_ack = disable_mace_irq, - .unmask = enable_mace_irq, - .end = end_mace_irq, + .irq_mask = disable_mace_irq, + .irq_unmask = enable_mace_irq, }; static void ip32_unknown_interrupt(void) @@ -501,43 +451,51 @@ void __init arch_init_irq(void) for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) { switch (irq) { case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ: - set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt, - handle_level_irq, "level"); + irq_set_chip_and_handler_name(irq, + &ip32_mace_interrupt, + handle_level_irq, + "level"); break; case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ: - set_irq_chip_and_handler_name(irq, - &ip32_macepci_interrupt, handle_level_irq, - "level"); + irq_set_chip_and_handler_name(irq, + &ip32_macepci_interrupt, + handle_level_irq, + "level"); break; case CRIME_CPUERR_IRQ: case CRIME_MEMERR_IRQ: - set_irq_chip_and_handler_name(irq, - &crime_level_interrupt, handle_level_irq, - "level"); + irq_set_chip_and_handler_name(irq, + &crime_level_interrupt, + handle_level_irq, + "level"); break; case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ: case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ: case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ: case CRIME_VICE_IRQ: - set_irq_chip_and_handler_name(irq, - &crime_edge_interrupt, handle_edge_irq, "edge"); + irq_set_chip_and_handler_name(irq, + &crime_edge_interrupt, + handle_edge_irq, + "edge"); break; case MACEISA_PARALLEL_IRQ: case MACEISA_SERIAL1_TDMAPR_IRQ: case MACEISA_SERIAL2_TDMAPR_IRQ: - set_irq_chip_and_handler_name(irq, - &ip32_maceisa_edge_interrupt, handle_edge_irq, - "edge"); + irq_set_chip_and_handler_name(irq, + &ip32_maceisa_edge_interrupt, + handle_edge_irq, + "edge"); break; default: - set_irq_chip_and_handler_name(irq, - &ip32_maceisa_level_interrupt, handle_level_irq, - "level"); + irq_set_chip_and_handler_name(irq, + &ip32_maceisa_level_interrupt, + handle_level_irq, + "level"); break; } } diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c index 044bbe462c2..09740d60e18 100644 --- a/arch/mips/sibyte/bcm1480/irq.c +++ b/arch/mips/sibyte/bcm1480/irq.c @@ -44,31 +44,10 @@ * for interrupt lines */ - -static void end_bcm1480_irq(unsigned int irq); -static void enable_bcm1480_irq(unsigned int irq); -static void disable_bcm1480_irq(unsigned int irq); -static void ack_bcm1480_irq(unsigned int irq); -#ifdef CONFIG_SMP -static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask); -#endif - #ifdef CONFIG_PCI extern unsigned long ht_eoi_space; #endif -static struct irq_chip bcm1480_irq_type = { - .name = "BCM1480-IMR", - .ack = ack_bcm1480_irq, - .mask = disable_bcm1480_irq, - .mask_ack = ack_bcm1480_irq, - .unmask = enable_bcm1480_irq, - .end = end_bcm1480_irq, -#ifdef CONFIG_SMP - .set_affinity = bcm1480_set_affinity -#endif -}; - /* Store the CPU id (not the logical number) */ int bcm1480_irq_owner[BCM1480_NR_IRQS]; @@ -109,12 +88,13 @@ void bcm1480_unmask_irq(int cpu, int irq) } #ifdef CONFIG_SMP -static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask) +static int bcm1480_set_affinity(struct irq_data *d, const struct cpumask *mask, + bool force) { + unsigned int irq_dirty, irq = d->irq; int i = 0, old_cpu, cpu, int_on, k; u64 cur_ints; unsigned long flags; - unsigned int irq_dirty; i = cpumask_first(mask); @@ -156,21 +136,25 @@ static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask) /*****************************************************************************/ -static void disable_bcm1480_irq(unsigned int irq) +static void disable_bcm1480_irq(struct irq_data *d) { + unsigned int irq = d->irq; + bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); } -static void enable_bcm1480_irq(unsigned int irq) +static void enable_bcm1480_irq(struct irq_data *d) { + unsigned int irq = d->irq; + bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq); } -static void ack_bcm1480_irq(unsigned int irq) +static void ack_bcm1480_irq(struct irq_data *d) { + unsigned int irq_dirty, irq = d->irq; u64 pending; - unsigned int irq_dirty; int k; /* @@ -217,21 +201,23 @@ static void ack_bcm1480_irq(unsigned int irq) bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); } - -static void end_bcm1480_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { - bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq); - } -} - +static struct irq_chip bcm1480_irq_type = { + .name = "BCM1480-IMR", + .irq_mask_ack = ack_bcm1480_irq, + .irq_mask = disable_bcm1480_irq, + .irq_unmask = enable_bcm1480_irq, +#ifdef CONFIG_SMP + .irq_set_affinity = bcm1480_set_affinity +#endif +}; void __init init_bcm1480_irqs(void) { int i; for (i = 0; i < BCM1480_NR_IRQS; i++) { - set_irq_chip_and_handler(i, &bcm1480_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &bcm1480_irq_type, + handle_level_irq); bcm1480_irq_owner[i] = 0; } } diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index 12ac04a658e..be4460a5f6a 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c @@ -43,31 +43,10 @@ * for interrupt lines */ - -static void end_sb1250_irq(unsigned int irq); -static void enable_sb1250_irq(unsigned int irq); -static void disable_sb1250_irq(unsigned int irq); -static void ack_sb1250_irq(unsigned int irq); -#ifdef CONFIG_SMP -static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask); -#endif - #ifdef CONFIG_SIBYTE_HAS_LDT extern unsigned long ldt_eoi_space; #endif -static struct irq_chip sb1250_irq_type = { - .name = "SB1250-IMR", - .ack = ack_sb1250_irq, - .mask = disable_sb1250_irq, - .mask_ack = ack_sb1250_irq, - .unmask = enable_sb1250_irq, - .end = end_sb1250_irq, -#ifdef CONFIG_SMP - .set_affinity = sb1250_set_affinity -#endif -}; - /* Store the CPU id (not the logical number) */ int sb1250_irq_owner[SB1250_NR_IRQS]; @@ -102,9 +81,11 @@ void sb1250_unmask_irq(int cpu, int irq) } #ifdef CONFIG_SMP -static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask) +static int sb1250_set_affinity(struct irq_data *d, const struct cpumask *mask, + bool force) { int i = 0, old_cpu, cpu, int_on; + unsigned int irq = d->irq; u64 cur_ints; unsigned long flags; @@ -142,21 +123,17 @@ static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask) } #endif -/*****************************************************************************/ - -static void disable_sb1250_irq(unsigned int irq) +static void enable_sb1250_irq(struct irq_data *d) { - sb1250_mask_irq(sb1250_irq_owner[irq], irq); -} + unsigned int irq = d->irq; -static void enable_sb1250_irq(unsigned int irq) -{ sb1250_unmask_irq(sb1250_irq_owner[irq], irq); } -static void ack_sb1250_irq(unsigned int irq) +static void ack_sb1250_irq(struct irq_data *d) { + unsigned int irq = d->irq; #ifdef CONFIG_SIBYTE_HAS_LDT u64 pending; @@ -199,21 +176,22 @@ static void ack_sb1250_irq(unsigned int irq) sb1250_mask_irq(sb1250_irq_owner[irq], irq); } - -static void end_sb1250_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { - sb1250_unmask_irq(sb1250_irq_owner[irq], irq); - } -} - +static struct irq_chip sb1250_irq_type = { + .name = "SB1250-IMR", + .irq_mask_ack = ack_sb1250_irq, + .irq_unmask = enable_sb1250_irq, +#ifdef CONFIG_SMP + .irq_set_affinity = sb1250_set_affinity +#endif +}; void __init init_sb1250_irqs(void) { int i; for (i = 0; i < SB1250_NR_IRQS; i++) { - set_irq_chip_and_handler(i, &sb1250_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &sb1250_irq_type, + handle_level_irq); sb1250_irq_owner[i] = 0; } } diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c index bbe7187879f..c48194c3073 100644 --- a/arch/mips/sni/a20r.c +++ b/arch/mips/sni/a20r.c @@ -168,33 +168,22 @@ static u32 a20r_ack_hwint(void) return status; } -static inline void unmask_a20r_irq(unsigned int irq) +static inline void unmask_a20r_irq(struct irq_data *d) { - set_c0_status(0x100 << (irq - SNI_A20R_IRQ_BASE)); + set_c0_status(0x100 << (d->irq - SNI_A20R_IRQ_BASE)); irq_enable_hazard(); } -static inline void mask_a20r_irq(unsigned int irq) +static inline void mask_a20r_irq(struct irq_data *d) { - clear_c0_status(0x100 << (irq - SNI_A20R_IRQ_BASE)); + clear_c0_status(0x100 << (d->irq - SNI_A20R_IRQ_BASE)); irq_disable_hazard(); } -static void end_a20r_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { - a20r_ack_hwint(); - unmask_a20r_irq(irq); - } -} - static struct irq_chip a20r_irq_type = { .name = "A20R", - .ack = mask_a20r_irq, - .mask = mask_a20r_irq, - .mask_ack = mask_a20r_irq, - .unmask = unmask_a20r_irq, - .end = end_a20r_irq, + .irq_mask = mask_a20r_irq, + .irq_unmask = unmask_a20r_irq, }; /* @@ -220,7 +209,7 @@ void __init sni_a20r_irq_init(void) int i; for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++) - set_irq_chip_and_handler(i, &a20r_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &a20r_irq_type, handle_level_irq); sni_hwint = a20r_hwint; change_c0_status(ST0_IM, IE_IRQ0); setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq); diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c index 8c92c73bc71..ed3b3d31735 100644 --- a/arch/mips/sni/pcimt.c +++ b/arch/mips/sni/pcimt.c @@ -194,33 +194,24 @@ static struct pci_controller sni_controller = { .io_map_base = SNI_PORT_BASE }; -static void enable_pcimt_irq(unsigned int irq) +static void enable_pcimt_irq(struct irq_data *d) { - unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2); + unsigned int mask = 1 << (d->irq - PCIMT_IRQ_INT2); *(volatile u8 *) PCIMT_IRQSEL |= mask; } -void disable_pcimt_irq(unsigned int irq) +void disable_pcimt_irq(struct irq_data *d) { - unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2)); + unsigned int mask = ~(1 << (d->irq - PCIMT_IRQ_INT2)); *(volatile u8 *) PCIMT_IRQSEL &= mask; } -static void end_pcimt_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_pcimt_irq(irq); -} - static struct irq_chip pcimt_irq_type = { .name = "PCIMT", - .ack = disable_pcimt_irq, - .mask = disable_pcimt_irq, - .mask_ack = disable_pcimt_irq, - .unmask = enable_pcimt_irq, - .end = end_pcimt_irq, + .irq_mask = disable_pcimt_irq, + .irq_unmask = enable_pcimt_irq, }; /* @@ -305,7 +296,7 @@ void __init sni_pcimt_irq_init(void) mips_cpu_irq_init(); /* Actually we've got more interrupts to handle ... */ for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++) - set_irq_chip_and_handler(i, &pcimt_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &pcimt_irq_type, handle_level_irq); sni_hwint = sni_pcimt_hwint; change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3); } diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c index dc9874553be..b5246373d16 100644 --- a/arch/mips/sni/pcit.c +++ b/arch/mips/sni/pcit.c @@ -156,33 +156,24 @@ static struct pci_controller sni_pcit_controller = { .io_map_base = SNI_PORT_BASE }; -static void enable_pcit_irq(unsigned int irq) +static void enable_pcit_irq(struct irq_data *d) { - u32 mask = 1 << (irq - SNI_PCIT_INT_START + 24); + u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24); *(volatile u32 *)SNI_PCIT_INT_REG |= mask; } -void disable_pcit_irq(unsigned int irq) +void disable_pcit_irq(struct irq_data *d) { - u32 mask = 1 << (irq - SNI_PCIT_INT_START + 24); + u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24); *(volatile u32 *)SNI_PCIT_INT_REG &= ~mask; } -void end_pcit_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_pcit_irq(irq); -} - static struct irq_chip pcit_irq_type = { .name = "PCIT", - .ack = disable_pcit_irq, - .mask = disable_pcit_irq, - .mask_ack = disable_pcit_irq, - .unmask = enable_pcit_irq, - .end = end_pcit_irq, + .irq_mask = disable_pcit_irq, + .irq_unmask = enable_pcit_irq, }; static void pcit_hwint1(void) @@ -247,7 +238,7 @@ void __init sni_pcit_irq_init(void) mips_cpu_irq_init(); for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) - set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq); *(volatile u32 *)SNI_PCIT_INT_REG = 0; sni_hwint = sni_pcit_hwint; change_c0_status(ST0_IM, IE_IRQ1); @@ -260,7 +251,7 @@ void __init sni_pcit_cplus_irq_init(void) mips_cpu_irq_init(); for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) - set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq); *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000; sni_hwint = sni_pcit_hwint_cplus; change_c0_status(ST0_IM, IE_IRQ0); diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c index 0e6f42c2bbc..a7e5a6d917b 100644 --- a/arch/mips/sni/rm200.c +++ b/arch/mips/sni/rm200.c @@ -155,12 +155,11 @@ static __iomem u8 *rm200_pic_slave; #define cached_master_mask (rm200_cached_irq_mask) #define cached_slave_mask (rm200_cached_irq_mask >> 8) -static void sni_rm200_disable_8259A_irq(unsigned int irq) +static void sni_rm200_disable_8259A_irq(struct irq_data *d) { - unsigned int mask; + unsigned int mask, irq = d->irq - RM200_I8259A_IRQ_BASE; unsigned long flags; - irq -= RM200_I8259A_IRQ_BASE; mask = 1 << irq; raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); rm200_cached_irq_mask |= mask; @@ -171,12 +170,11 @@ static void sni_rm200_disable_8259A_irq(unsigned int irq) raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); } -static void sni_rm200_enable_8259A_irq(unsigned int irq) +static void sni_rm200_enable_8259A_irq(struct irq_data *d) { - unsigned int mask; + unsigned int mask, irq = d->irq - RM200_I8259A_IRQ_BASE; unsigned long flags; - irq -= RM200_I8259A_IRQ_BASE; mask = ~(1 << irq); raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); rm200_cached_irq_mask &= mask; @@ -210,12 +208,11 @@ static inline int sni_rm200_i8259A_irq_real(unsigned int irq) * first, _then_ send the EOI, and the order of EOI * to the two 8259s is important! */ -void sni_rm200_mask_and_ack_8259A(unsigned int irq) +void sni_rm200_mask_and_ack_8259A(struct irq_data *d) { - unsigned int irqmask; + unsigned int irqmask, irq = d->irq - RM200_I8259A_IRQ_BASE; unsigned long flags; - irq -= RM200_I8259A_IRQ_BASE; irqmask = 1 << irq; raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); /* @@ -285,9 +282,9 @@ spurious_8259A_irq: static struct irq_chip sni_rm200_i8259A_chip = { .name = "RM200-XT-PIC", - .mask = sni_rm200_disable_8259A_irq, - .unmask = sni_rm200_enable_8259A_irq, - .mask_ack = sni_rm200_mask_and_ack_8259A, + .irq_mask = sni_rm200_disable_8259A_irq, + .irq_unmask = sni_rm200_enable_8259A_irq, + .irq_mask_ack = sni_rm200_mask_and_ack_8259A, }; /* @@ -416,7 +413,7 @@ void __init sni_rm200_i8259_irqs(void) sni_rm200_init_8259A(); for (i = RM200_I8259A_IRQ_BASE; i < RM200_I8259A_IRQ_BASE + 16; i++) - set_irq_chip_and_handler(i, &sni_rm200_i8259A_chip, + irq_set_chip_and_handler(i, &sni_rm200_i8259A_chip, handle_level_irq); setup_irq(RM200_I8259A_IRQ_BASE + PIC_CASCADE_IR, &sni_rm200_irq2); @@ -429,33 +426,24 @@ void __init sni_rm200_i8259_irqs(void) #define SNI_RM200_INT_START 24 #define SNI_RM200_INT_END 28 -static void enable_rm200_irq(unsigned int irq) +static void enable_rm200_irq(struct irq_data *d) { - unsigned int mask = 1 << (irq - SNI_RM200_INT_START); + unsigned int mask = 1 << (d->irq - SNI_RM200_INT_START); *(volatile u8 *)SNI_RM200_INT_ENA_REG &= ~mask; } -void disable_rm200_irq(unsigned int irq) +void disable_rm200_irq(struct irq_data *d) { - unsigned int mask = 1 << (irq - SNI_RM200_INT_START); + unsigned int mask = 1 << (d->irq - SNI_RM200_INT_START); *(volatile u8 *)SNI_RM200_INT_ENA_REG |= mask; } -void end_rm200_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_rm200_irq(irq); -} - static struct irq_chip rm200_irq_type = { .name = "RM200", - .ack = disable_rm200_irq, - .mask = disable_rm200_irq, - .mask_ack = disable_rm200_irq, - .unmask = enable_rm200_irq, - .end = end_rm200_irq, + .irq_mask = disable_rm200_irq, + .irq_unmask = enable_rm200_irq, }; static void sni_rm200_hwint(void) @@ -489,7 +477,7 @@ void __init sni_rm200_irq_init(void) mips_cpu_irq_init(); /* Actually we've got more interrupts to handle ... */ for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++) - set_irq_chip_and_handler(i, &rm200_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &rm200_irq_type, handle_level_irq); sni_hwint = sni_rm200_hwint; change_c0_status(ST0_IM, IE_IRQ0); setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq); diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c index c76151b5656..0904d4d30cb 100644 --- a/arch/mips/sni/time.c +++ b/arch/mips/sni/time.c @@ -95,7 +95,7 @@ static void __init sni_a20r_timer_setup(void) static __init unsigned long dosample(void) { u32 ct0, ct1; - volatile u8 msb, lsb; + volatile u8 msb; /* Start the counter. */ outb_p(0x34, 0x43); @@ -108,7 +108,7 @@ static __init unsigned long dosample(void) /* Latch and spin until top byte of counter0 is zero */ do { outb(0x00, 0x43); - lsb = inb(0x40); + (void) inb(0x40); msb = inb(0x40); ct1 = read_c0_count(); } while (msb); diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c index e1828e8bcae..7e3ac5782da 100644 --- a/arch/mips/txx9/generic/irq_tx4927.c +++ b/arch/mips/txx9/generic/irq_tx4927.c @@ -35,7 +35,7 @@ void __init tx4927_irq_init(void) mips_cpu_irq_init(); txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL); - set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, + irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, handle_simple_irq); /* raise priority for errors, timers, SIO */ txx9_irq_set_pri(TX4927_IR_ECCERR, 7); diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c index a6e6e805097..aace8565332 100644 --- a/arch/mips/txx9/generic/irq_tx4938.c +++ b/arch/mips/txx9/generic/irq_tx4938.c @@ -23,7 +23,7 @@ void __init tx4938_irq_init(void) mips_cpu_irq_init(); txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL); - set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, + irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, handle_simple_irq); /* raise priority for errors, timers, SIO */ txx9_irq_set_pri(TX4938_IR_ECCERR, 7); diff --git a/arch/mips/txx9/generic/irq_tx4939.c b/arch/mips/txx9/generic/irq_tx4939.c index 3886ad77cba..6b067dbd2ae 100644 --- a/arch/mips/txx9/generic/irq_tx4939.c +++ b/arch/mips/txx9/generic/irq_tx4939.c @@ -50,9 +50,9 @@ static struct { unsigned char mode; } tx4939irq[TX4939_NUM_IR] __read_mostly; -static void tx4939_irq_unmask(unsigned int irq) +static void tx4939_irq_unmask(struct irq_data *d) { - unsigned int irq_nr = irq - TXX9_IRQ_BASE; + unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; u32 __iomem *lvlp; int ofs; if (irq_nr < 32) { @@ -68,9 +68,9 @@ static void tx4939_irq_unmask(unsigned int irq) lvlp); } -static inline void tx4939_irq_mask(unsigned int irq) +static inline void tx4939_irq_mask(struct irq_data *d) { - unsigned int irq_nr = irq - TXX9_IRQ_BASE; + unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; u32 __iomem *lvlp; int ofs; if (irq_nr < 32) { @@ -87,11 +87,11 @@ static inline void tx4939_irq_mask(unsigned int irq) mmiowb(); } -static void tx4939_irq_mask_ack(unsigned int irq) +static void tx4939_irq_mask_ack(struct irq_data *d) { - unsigned int irq_nr = irq - TXX9_IRQ_BASE; + unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; - tx4939_irq_mask(irq); + tx4939_irq_mask(d); if (TXx9_IRCR_EDGE(tx4939irq[irq_nr].mode)) { irq_nr--; /* clear edge detection */ @@ -101,9 +101,9 @@ static void tx4939_irq_mask_ack(unsigned int irq) } } -static int tx4939_irq_set_type(unsigned int irq, unsigned int flow_type) +static int tx4939_irq_set_type(struct irq_data *d, unsigned int flow_type) { - unsigned int irq_nr = irq - TXX9_IRQ_BASE; + unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; u32 cr; u32 __iomem *crp; int ofs; @@ -145,11 +145,11 @@ static int tx4939_irq_set_type(unsigned int irq, unsigned int flow_type) static struct irq_chip tx4939_irq_chip = { .name = "TX4939", - .ack = tx4939_irq_mask_ack, - .mask = tx4939_irq_mask, - .mask_ack = tx4939_irq_mask_ack, - .unmask = tx4939_irq_unmask, - .set_type = tx4939_irq_set_type, + .irq_ack = tx4939_irq_mask_ack, + .irq_mask = tx4939_irq_mask, + .irq_mask_ack = tx4939_irq_mask_ack, + .irq_unmask = tx4939_irq_unmask, + .irq_set_type = tx4939_irq_set_type, }; static int tx4939_irq_set_pri(int irc_irq, int new_pri) @@ -176,8 +176,8 @@ void __init tx4939_irq_init(void) for (i = 1; i < TX4939_NUM_IR; i++) { tx4939irq[i].level = 4; /* middle level */ tx4939irq[i].mode = TXx9_IRCR_LOW; - set_irq_chip_and_handler(TXX9_IRQ_BASE + i, - &tx4939_irq_chip, handle_level_irq); + irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &tx4939_irq_chip, + handle_level_irq); } /* mask all IRC interrupts */ @@ -193,7 +193,7 @@ void __init tx4939_irq_init(void) __raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r); __raw_writel(irc_elevel, &tx4939_ircptr->msk.r); - set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT, + irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT, handle_simple_irq); /* raise priority for errors, timers, sio */ diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c index 0a7f8e3b9fd..c22c859a2c4 100644 --- a/arch/mips/txx9/jmr3927/irq.c +++ b/arch/mips/txx9/jmr3927/irq.c @@ -47,20 +47,20 @@ * CP0_STATUS is a thread's resource (saved/restored on context switch). * So disable_irq/enable_irq MUST handle IOC/IRC registers. */ -static void mask_irq_ioc(unsigned int irq) +static void mask_irq_ioc(struct irq_data *d) { /* 0: mask */ - unsigned int irq_nr = irq - JMR3927_IRQ_IOC; + unsigned int irq_nr = d->irq - JMR3927_IRQ_IOC; unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); unsigned int bit = 1 << irq_nr; jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR); /* flush write buffer */ (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); } -static void unmask_irq_ioc(unsigned int irq) +static void unmask_irq_ioc(struct irq_data *d) { /* 0: mask */ - unsigned int irq_nr = irq - JMR3927_IRQ_IOC; + unsigned int irq_nr = d->irq - JMR3927_IRQ_IOC; unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); unsigned int bit = 1 << irq_nr; jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR); @@ -95,10 +95,8 @@ static int jmr3927_irq_dispatch(int pending) static struct irq_chip jmr3927_irq_ioc = { .name = "jmr3927_ioc", - .ack = mask_irq_ioc, - .mask = mask_irq_ioc, - .mask_ack = mask_irq_ioc, - .unmask = unmask_irq_ioc, + .irq_mask = mask_irq_ioc, + .irq_unmask = unmask_irq_ioc, }; void __init jmr3927_irq_setup(void) @@ -122,8 +120,9 @@ void __init jmr3927_irq_setup(void) tx3927_irq_init(); for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++) - set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq); + irq_set_chip_and_handler(i, &jmr3927_irq_ioc, + handle_level_irq); /* setup IOC interrupt 1 (PCI, MODEM) */ - set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq); + irq_set_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq); } diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c index c4b54d20efd..6c22c496090 100644 --- a/arch/mips/txx9/rbtx4927/irq.c +++ b/arch/mips/txx9/rbtx4927/irq.c @@ -117,18 +117,6 @@ #include <asm/txx9/generic.h> #include <asm/txx9/rbtx4927.h> -static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); -static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); - -#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC" -static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { - .name = TOSHIBA_RBTX4927_IOC_NAME, - .ack = toshiba_rbtx4927_irq_ioc_disable, - .mask = toshiba_rbtx4927_irq_ioc_disable, - .mask_ack = toshiba_rbtx4927_irq_ioc_disable, - .unmask = toshiba_rbtx4927_irq_ioc_enable, -}; - static int toshiba_rbtx4927_irq_nested(int sw_irq) { u8 level3; @@ -139,41 +127,47 @@ static int toshiba_rbtx4927_irq_nested(int sw_irq) return RBTX4927_IRQ_IOC + __fls8(level3); } -static void __init toshiba_rbtx4927_irq_ioc_init(void) -{ - int i; - - /* mask all IOC interrupts */ - writeb(0, rbtx4927_imask_addr); - /* clear SoftInt interrupts */ - writeb(0, rbtx4927_softint_addr); - - for (i = RBTX4927_IRQ_IOC; - i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++) - set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, - handle_level_irq); - set_irq_chained_handler(RBTX4927_IRQ_IOCINT, handle_simple_irq); -} - -static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) +static void toshiba_rbtx4927_irq_ioc_enable(struct irq_data *d) { unsigned char v; v = readb(rbtx4927_imask_addr); - v |= (1 << (irq - RBTX4927_IRQ_IOC)); + v |= (1 << (d->irq - RBTX4927_IRQ_IOC)); writeb(v, rbtx4927_imask_addr); } -static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) +static void toshiba_rbtx4927_irq_ioc_disable(struct irq_data *d) { unsigned char v; v = readb(rbtx4927_imask_addr); - v &= ~(1 << (irq - RBTX4927_IRQ_IOC)); + v &= ~(1 << (d->irq - RBTX4927_IRQ_IOC)); writeb(v, rbtx4927_imask_addr); mmiowb(); } +#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC" +static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { + .name = TOSHIBA_RBTX4927_IOC_NAME, + .irq_mask = toshiba_rbtx4927_irq_ioc_disable, + .irq_unmask = toshiba_rbtx4927_irq_ioc_enable, +}; + +static void __init toshiba_rbtx4927_irq_ioc_init(void) +{ + int i; + + /* mask all IOC interrupts */ + writeb(0, rbtx4927_imask_addr); + /* clear SoftInt interrupts */ + writeb(0, rbtx4927_softint_addr); + + for (i = RBTX4927_IRQ_IOC; + i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++) + irq_set_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, + handle_level_irq); + irq_set_chained_handler(RBTX4927_IRQ_IOCINT, handle_simple_irq); +} static int rbtx4927_irq_dispatch(int pending) { @@ -200,5 +194,5 @@ void __init rbtx4927_irq_setup(void) tx4927_irq_init(); toshiba_rbtx4927_irq_ioc_init(); /* Onboard 10M Ether: High Active */ - set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); + irq_set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); } diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c index 67a73a8065e..58cd7a9272c 100644 --- a/arch/mips/txx9/rbtx4938/irq.c +++ b/arch/mips/txx9/rbtx4938/irq.c @@ -69,18 +69,6 @@ #include <asm/txx9/generic.h> #include <asm/txx9/rbtx4938.h> -static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); -static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq); - -#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC" -static struct irq_chip toshiba_rbtx4938_irq_ioc_type = { - .name = TOSHIBA_RBTX4938_IOC_NAME, - .ack = toshiba_rbtx4938_irq_ioc_disable, - .mask = toshiba_rbtx4938_irq_ioc_disable, - .mask_ack = toshiba_rbtx4938_irq_ioc_disable, - .unmask = toshiba_rbtx4938_irq_ioc_enable, -}; - static int toshiba_rbtx4938_irq_nested(int sw_irq) { u8 level3; @@ -92,41 +80,33 @@ static int toshiba_rbtx4938_irq_nested(int sw_irq) return RBTX4938_IRQ_IOC + __fls8(level3); } -static void __init -toshiba_rbtx4938_irq_ioc_init(void) -{ - int i; - - for (i = RBTX4938_IRQ_IOC; - i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++) - set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type, - handle_level_irq); - - set_irq_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq); -} - -static void -toshiba_rbtx4938_irq_ioc_enable(unsigned int irq) +static void toshiba_rbtx4938_irq_ioc_enable(struct irq_data *d) { unsigned char v; v = readb(rbtx4938_imask_addr); - v |= (1 << (irq - RBTX4938_IRQ_IOC)); + v |= (1 << (d->irq - RBTX4938_IRQ_IOC)); writeb(v, rbtx4938_imask_addr); mmiowb(); } -static void -toshiba_rbtx4938_irq_ioc_disable(unsigned int irq) +static void toshiba_rbtx4938_irq_ioc_disable(struct irq_data *d) { unsigned char v; v = readb(rbtx4938_imask_addr); - v &= ~(1 << (irq - RBTX4938_IRQ_IOC)); + v &= ~(1 << (d->irq - RBTX4938_IRQ_IOC)); writeb(v, rbtx4938_imask_addr); mmiowb(); } +#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC" +static struct irq_chip toshiba_rbtx4938_irq_ioc_type = { + .name = TOSHIBA_RBTX4938_IOC_NAME, + .irq_mask = toshiba_rbtx4938_irq_ioc_disable, + .irq_unmask = toshiba_rbtx4938_irq_ioc_enable, +}; + static int rbtx4938_irq_dispatch(int pending) { int irq; @@ -146,6 +126,18 @@ static int rbtx4938_irq_dispatch(int pending) return irq; } +static void __init toshiba_rbtx4938_irq_ioc_init(void) +{ + int i; + + for (i = RBTX4938_IRQ_IOC; + i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++) + irq_set_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type, + handle_level_irq); + + irq_set_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq); +} + void __init rbtx4938_irq_setup(void) { txx9_irq_dispatch = rbtx4938_irq_dispatch; @@ -161,5 +153,5 @@ void __init rbtx4938_irq_setup(void) tx4938_irq_init(); toshiba_rbtx4938_irq_ioc_init(); /* Onboard 10M Ether: High Active */ - set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH); + irq_set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH); } diff --git a/arch/mips/txx9/rbtx4939/irq.c b/arch/mips/txx9/rbtx4939/irq.c index 57fa740a720..69a80616f0c 100644 --- a/arch/mips/txx9/rbtx4939/irq.c +++ b/arch/mips/txx9/rbtx4939/irq.c @@ -19,16 +19,16 @@ * RBTX4939 IOC controller definition */ -static void rbtx4939_ioc_irq_unmask(unsigned int irq) +static void rbtx4939_ioc_irq_unmask(struct irq_data *d) { - int ioc_nr = irq - RBTX4939_IRQ_IOC; + int ioc_nr = d->irq - RBTX4939_IRQ_IOC; writeb(readb(rbtx4939_ien_addr) | (1 << ioc_nr), rbtx4939_ien_addr); } -static void rbtx4939_ioc_irq_mask(unsigned int irq) +static void rbtx4939_ioc_irq_mask(struct irq_data *d) { - int ioc_nr = irq - RBTX4939_IRQ_IOC; + int ioc_nr = d->irq - RBTX4939_IRQ_IOC; writeb(readb(rbtx4939_ien_addr) & ~(1 << ioc_nr), rbtx4939_ien_addr); mmiowb(); @@ -36,10 +36,8 @@ static void rbtx4939_ioc_irq_mask(unsigned int irq) static struct irq_chip rbtx4939_ioc_irq_chip = { .name = "IOC", - .ack = rbtx4939_ioc_irq_mask, - .mask = rbtx4939_ioc_irq_mask, - .mask_ack = rbtx4939_ioc_irq_mask, - .unmask = rbtx4939_ioc_irq_unmask, + .irq_mask = rbtx4939_ioc_irq_mask, + .irq_unmask = rbtx4939_ioc_irq_unmask, }; @@ -90,8 +88,8 @@ void __init rbtx4939_irq_setup(void) tx4939_irq_init(); for (i = RBTX4939_IRQ_IOC; i < RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC; i++) - set_irq_chip_and_handler(i, &rbtx4939_ioc_irq_chip, + irq_set_chip_and_handler(i, &rbtx4939_ioc_irq_chip, handle_level_irq); - set_irq_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq); + irq_set_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq); } diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c index 6153b6a05cc..a39ef3207d7 100644 --- a/arch/mips/vr41xx/common/icu.c +++ b/arch/mips/vr41xx/common/icu.c @@ -154,7 +154,7 @@ static inline uint16_t icu2_clear(uint8_t offset, uint16_t clear) void vr41xx_enable_piuint(uint16_t mask) { - struct irq_desc *desc = irq_desc + PIU_IRQ; + struct irq_desc *desc = irq_to_desc(PIU_IRQ); unsigned long flags; if (current_cpu_type() == CPU_VR4111 || @@ -169,7 +169,7 @@ EXPORT_SYMBOL(vr41xx_enable_piuint); void vr41xx_disable_piuint(uint16_t mask) { - struct irq_desc *desc = irq_desc + PIU_IRQ; + struct irq_desc *desc = irq_to_desc(PIU_IRQ); unsigned long flags; if (current_cpu_type() == CPU_VR4111 || @@ -184,7 +184,7 @@ EXPORT_SYMBOL(vr41xx_disable_piuint); void vr41xx_enable_aiuint(uint16_t mask) { - struct irq_desc *desc = irq_desc + AIU_IRQ; + struct irq_desc *desc = irq_to_desc(AIU_IRQ); unsigned long flags; if (current_cpu_type() == CPU_VR4111 || @@ -199,7 +199,7 @@ EXPORT_SYMBOL(vr41xx_enable_aiuint); void vr41xx_disable_aiuint(uint16_t mask) { - struct irq_desc *desc = irq_desc + AIU_IRQ; + struct irq_desc *desc = irq_to_desc(AIU_IRQ); unsigned long flags; if (current_cpu_type() == CPU_VR4111 || @@ -214,7 +214,7 @@ EXPORT_SYMBOL(vr41xx_disable_aiuint); void vr41xx_enable_kiuint(uint16_t mask) { - struct irq_desc *desc = irq_desc + KIU_IRQ; + struct irq_desc *desc = irq_to_desc(KIU_IRQ); unsigned long flags; if (current_cpu_type() == CPU_VR4111 || @@ -229,7 +229,7 @@ EXPORT_SYMBOL(vr41xx_enable_kiuint); void vr41xx_disable_kiuint(uint16_t mask) { - struct irq_desc *desc = irq_desc + KIU_IRQ; + struct irq_desc *desc = irq_to_desc(KIU_IRQ); unsigned long flags; if (current_cpu_type() == CPU_VR4111 || @@ -244,7 +244,7 @@ EXPORT_SYMBOL(vr41xx_disable_kiuint); void vr41xx_enable_macint(uint16_t mask) { - struct irq_desc *desc = irq_desc + ETHERNET_IRQ; + struct irq_desc *desc = irq_to_desc(ETHERNET_IRQ); unsigned long flags; raw_spin_lock_irqsave(&desc->lock, flags); @@ -256,7 +256,7 @@ EXPORT_SYMBOL(vr41xx_enable_macint); void vr41xx_disable_macint(uint16_t mask) { - struct irq_desc *desc = irq_desc + ETHERNET_IRQ; + struct irq_desc *desc = irq_to_desc(ETHERNET_IRQ); unsigned long flags; raw_spin_lock_irqsave(&desc->lock, flags); @@ -268,7 +268,7 @@ EXPORT_SYMBOL(vr41xx_disable_macint); void vr41xx_enable_dsiuint(uint16_t mask) { - struct irq_desc *desc = irq_desc + DSIU_IRQ; + struct irq_desc *desc = irq_to_desc(DSIU_IRQ); unsigned long flags; raw_spin_lock_irqsave(&desc->lock, flags); @@ -280,7 +280,7 @@ EXPORT_SYMBOL(vr41xx_enable_dsiuint); void vr41xx_disable_dsiuint(uint16_t mask) { - struct irq_desc *desc = irq_desc + DSIU_IRQ; + struct irq_desc *desc = irq_to_desc(DSIU_IRQ); unsigned long flags; raw_spin_lock_irqsave(&desc->lock, flags); @@ -292,7 +292,7 @@ EXPORT_SYMBOL(vr41xx_disable_dsiuint); void vr41xx_enable_firint(uint16_t mask) { - struct irq_desc *desc = irq_desc + FIR_IRQ; + struct irq_desc *desc = irq_to_desc(FIR_IRQ); unsigned long flags; raw_spin_lock_irqsave(&desc->lock, flags); @@ -304,7 +304,7 @@ EXPORT_SYMBOL(vr41xx_enable_firint); void vr41xx_disable_firint(uint16_t mask) { - struct irq_desc *desc = irq_desc + FIR_IRQ; + struct irq_desc *desc = irq_to_desc(FIR_IRQ); unsigned long flags; raw_spin_lock_irqsave(&desc->lock, flags); @@ -316,7 +316,7 @@ EXPORT_SYMBOL(vr41xx_disable_firint); void vr41xx_enable_pciint(void) { - struct irq_desc *desc = irq_desc + PCI_IRQ; + struct irq_desc *desc = irq_to_desc(PCI_IRQ); unsigned long flags; if (current_cpu_type() == CPU_VR4122 || @@ -332,7 +332,7 @@ EXPORT_SYMBOL(vr41xx_enable_pciint); void vr41xx_disable_pciint(void) { - struct irq_desc *desc = irq_desc + PCI_IRQ; + struct irq_desc *desc = irq_to_desc(PCI_IRQ); unsigned long flags; if (current_cpu_type() == CPU_VR4122 || @@ -348,7 +348,7 @@ EXPORT_SYMBOL(vr41xx_disable_pciint); void vr41xx_enable_scuint(void) { - struct irq_desc *desc = irq_desc + SCU_IRQ; + struct irq_desc *desc = irq_to_desc(SCU_IRQ); unsigned long flags; if (current_cpu_type() == CPU_VR4122 || @@ -364,7 +364,7 @@ EXPORT_SYMBOL(vr41xx_enable_scuint); void vr41xx_disable_scuint(void) { - struct irq_desc *desc = irq_desc + SCU_IRQ; + struct irq_desc *desc = irq_to_desc(SCU_IRQ); unsigned long flags; if (current_cpu_type() == CPU_VR4122 || @@ -380,7 +380,7 @@ EXPORT_SYMBOL(vr41xx_disable_scuint); void vr41xx_enable_csiint(uint16_t mask) { - struct irq_desc *desc = irq_desc + CSI_IRQ; + struct irq_desc *desc = irq_to_desc(CSI_IRQ); unsigned long flags; if (current_cpu_type() == CPU_VR4122 || @@ -396,7 +396,7 @@ EXPORT_SYMBOL(vr41xx_enable_csiint); void vr41xx_disable_csiint(uint16_t mask) { - struct irq_desc *desc = irq_desc + CSI_IRQ; + struct irq_desc *desc = irq_to_desc(CSI_IRQ); unsigned long flags; if (current_cpu_type() == CPU_VR4122 || @@ -412,7 +412,7 @@ EXPORT_SYMBOL(vr41xx_disable_csiint); void vr41xx_enable_bcuint(void) { - struct irq_desc *desc = irq_desc + BCU_IRQ; + struct irq_desc *desc = irq_to_desc(BCU_IRQ); unsigned long flags; if (current_cpu_type() == CPU_VR4122 || @@ -428,7 +428,7 @@ EXPORT_SYMBOL(vr41xx_enable_bcuint); void vr41xx_disable_bcuint(void) { - struct irq_desc *desc = irq_desc + BCU_IRQ; + struct irq_desc *desc = irq_to_desc(BCU_IRQ); unsigned long flags; if (current_cpu_type() == CPU_VR4122 || @@ -442,45 +442,41 @@ void vr41xx_disable_bcuint(void) EXPORT_SYMBOL(vr41xx_disable_bcuint); -static void disable_sysint1_irq(unsigned int irq) +static void disable_sysint1_irq(struct irq_data *d) { - icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); + icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(d->irq)); } -static void enable_sysint1_irq(unsigned int irq) +static void enable_sysint1_irq(struct irq_data *d) { - icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); + icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(d->irq)); } static struct irq_chip sysint1_irq_type = { .name = "SYSINT1", - .ack = disable_sysint1_irq, - .mask = disable_sysint1_irq, - .mask_ack = disable_sysint1_irq, - .unmask = enable_sysint1_irq, + .irq_mask = disable_sysint1_irq, + .irq_unmask = enable_sysint1_irq, }; -static void disable_sysint2_irq(unsigned int irq) +static void disable_sysint2_irq(struct irq_data *d) { - icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); + icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(d->irq)); } -static void enable_sysint2_irq(unsigned int irq) +static void enable_sysint2_irq(struct irq_data *d) { - icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); + icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(d->irq)); } static struct irq_chip sysint2_irq_type = { .name = "SYSINT2", - .ack = disable_sysint2_irq, - .mask = disable_sysint2_irq, - .mask_ack = disable_sysint2_irq, - .unmask = enable_sysint2_irq, + .irq_mask = disable_sysint2_irq, + .irq_unmask = enable_sysint2_irq, }; static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) { - struct irq_desc *desc = irq_desc + irq; + struct irq_desc *desc = irq_to_desc(irq); uint16_t intassign0, intassign1; unsigned int pin; @@ -540,7 +536,7 @@ static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) static inline int set_sysint2_assign(unsigned int irq, unsigned char assign) { - struct irq_desc *desc = irq_desc + irq; + struct irq_desc *desc = irq_to_desc(irq); uint16_t intassign2, intassign3; unsigned int pin; @@ -714,11 +710,11 @@ static int __init vr41xx_icu_init(void) icu2_write(MGIUINTHREG, 0xffff); for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) - set_irq_chip_and_handler(i, &sysint1_irq_type, + irq_set_chip_and_handler(i, &sysint1_irq_type, handle_level_irq); for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) - set_irq_chip_and_handler(i, &sysint2_irq_type, + irq_set_chip_and_handler(i, &sysint2_irq_type, handle_level_irq); cascade_irq(INT0_IRQ, icu_get_irq); diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c index 0975eb72d38..70a3b85f375 100644 --- a/arch/mips/vr41xx/common/irq.c +++ b/arch/mips/vr41xx/common/irq.c @@ -62,7 +62,6 @@ EXPORT_SYMBOL_GPL(cascade_irq); static void irq_dispatch(unsigned int irq) { irq_cascade_t *cascade; - struct irq_desc *desc; if (irq >= NR_IRQS) { atomic_inc(&irq_err_count); @@ -71,14 +70,16 @@ static void irq_dispatch(unsigned int irq) cascade = irq_cascade + irq; if (cascade->get_irq != NULL) { - unsigned int source_irq = irq; + struct irq_desc *desc = irq_to_desc(irq); + struct irq_data *idata = irq_desc_get_irq_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); int ret; - desc = irq_desc + source_irq; - if (desc->chip->mask_ack) - desc->chip->mask_ack(source_irq); + + if (chip->irq_mask_ack) + chip->irq_mask_ack(idata); else { - desc->chip->mask(source_irq); - desc->chip->ack(source_irq); + chip->irq_mask(idata); + chip->irq_ack(idata); } ret = cascade->get_irq(irq); irq = ret; @@ -86,8 +87,8 @@ static void irq_dispatch(unsigned int irq) atomic_inc(&irq_err_count); else irq_dispatch(irq); - if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) - desc->chip->unmask(source_irq); + if (!irqd_irq_disabled(idata) && chip->irq_unmask) + chip->irq_unmask(idata); } else do_IRQ(irq); } diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig index 243bfa23fd5..feaf09cc863 100644 --- a/arch/mn10300/Kconfig +++ b/arch/mn10300/Kconfig @@ -1,7 +1,10 @@ config MN10300 def_bool y select HAVE_OPROFILE - select GENERIC_HARDIRQS + select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_SHOW + select HAVE_ARCH_TRACEHOOK + select HAVE_ARCH_KGDB config AM33_2 def_bool n @@ -53,21 +56,6 @@ config GENERIC_TIME config GENERIC_CLOCKEVENTS def_bool y -config GENERIC_CLOCKEVENTS_BUILD - def_bool y - depends on GENERIC_CLOCKEVENTS - -config GENERIC_CLOCKEVENTS_BROADCAST - bool - -config CEVT_MN10300 - def_bool y - depends on GENERIC_CLOCKEVENTS - -config CSRC_MN10300 - def_bool y - depends on GENERIC_TIME - config GENERIC_BUG def_bool y @@ -415,9 +403,9 @@ comment "[!] NOTE: A lower number/level indicates a higher priority (0 is highes comment "____Non-maskable interrupt levels____" comment "The following must be set to a higher priority than local_irq_disable() and on-chip serial" -config GDBSTUB_IRQ_LEVEL - int "GDBSTUB interrupt priority" - depends on GDBSTUB +config DEBUGGER_IRQ_LEVEL + int "DEBUGGER interrupt priority" + depends on KERNEL_DEBUGGER range 0 1 if LINUX_CLI_LEVEL = 2 range 0 2 if LINUX_CLI_LEVEL = 3 range 0 3 if LINUX_CLI_LEVEL = 4 @@ -451,7 +439,7 @@ config LINUX_CLI_LEVEL EPSW.IM from 7. Any interrupt is permitted for which the level is lower than EPSW.IM. - Certain interrupts, such as GDBSTUB and virtual MN10300 on-chip + Certain interrupts, such as DEBUGGER and virtual MN10300 on-chip serial DMA interrupts are allowed to interrupt normal disabled sections. diff --git a/arch/mn10300/Kconfig.debug b/arch/mn10300/Kconfig.debug index ce83c74b3fd..bdbfd444a9f 100644 --- a/arch/mn10300/Kconfig.debug +++ b/arch/mn10300/Kconfig.debug @@ -36,7 +36,7 @@ config KPROBES config GDBSTUB bool "Remote GDB kernel debugging" - depends on DEBUG_KERNEL + depends on DEBUG_KERNEL && DEPRECATED select DEBUG_INFO select FRAME_POINTER help @@ -46,6 +46,9 @@ config GDBSTUB RAM to avoid excessive linking time. This is only useful for kernel hackers. If unsure, say N. + This is deprecated in favour of KGDB and will be removed in a later + version. + config GDBSTUB_IMMEDIATE bool "Break into GDB stub immediately" depends on GDBSTUB @@ -54,6 +57,14 @@ config GDBSTUB_IMMEDIATE possible, leaving the program counter at the beginning of start_kernel() in init/main.c. +config GDBSTUB_ALLOW_SINGLE_STEP + bool "Allow software single-stepping in GDB stub" + depends on GDBSTUB && !SMP && !PREEMPT + help + Allow GDB stub to perform software single-stepping through the + kernel. This doesn't work very well on SMP or preemptible kernels as + it uses temporary breakpoints to emulate single-stepping. + config GDB_CONSOLE bool "Console output to GDB" depends on GDBSTUB @@ -142,3 +153,7 @@ config GDBSTUB_ON_TTYSx default y endmenu + +config KERNEL_DEBUGGER + def_bool y + depends on GDBSTUB || KGDB diff --git a/arch/mn10300/include/asm/bitops.h b/arch/mn10300/include/asm/bitops.h index 3b8a868188f..0939462967e 100644 --- a/arch/mn10300/include/asm/bitops.h +++ b/arch/mn10300/include/asm/bitops.h @@ -233,8 +233,7 @@ int ffs(int x) #define ext2_clear_bit_atomic(lock, nr, addr) \ test_and_clear_bit((nr), (addr)) -#include <asm-generic/bitops/ext2-non-atomic.h> -#include <asm-generic/bitops/minix-le.h> +#include <asm-generic/bitops/le.h> #endif /* __KERNEL__ */ #endif /* __ASM_BITOPS_H */ diff --git a/arch/mn10300/include/asm/cpu-regs.h b/arch/mn10300/include/asm/cpu-regs.h index 90ed4a365c9..c54effae220 100644 --- a/arch/mn10300/include/asm/cpu-regs.h +++ b/arch/mn10300/include/asm/cpu-regs.h @@ -49,7 +49,7 @@ asm(" .am33_2\n"); #define EPSW_IM_6 0x00000600 /* interrupt mode 6 */ #define EPSW_IM_7 0x00000700 /* interrupt mode 7 */ #define EPSW_IE 0x00000800 /* interrupt enable */ -#define EPSW_S 0x00003000 /* software auxilliary bits */ +#define EPSW_S 0x00003000 /* software auxiliary bits */ #define EPSW_T 0x00008000 /* trace enable */ #define EPSW_nSL 0x00010000 /* not supervisor level */ #define EPSW_NMID 0x00020000 /* nonmaskable interrupt disable */ diff --git a/arch/mn10300/include/asm/debugger.h b/arch/mn10300/include/asm/debugger.h new file mode 100644 index 00000000000..e1d3b083696 --- /dev/null +++ b/arch/mn10300/include/asm/debugger.h @@ -0,0 +1,43 @@ +/* Kernel debugger for MN10300 + * + * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_DEBUGGER_H +#define _ASM_DEBUGGER_H + +#if defined(CONFIG_KERNEL_DEBUGGER) + +extern int debugger_intercept(enum exception_code, int, int, struct pt_regs *); +extern int at_debugger_breakpoint(struct pt_regs *); + +#ifndef CONFIG_MN10300_DEBUGGER_CACHE_NO_FLUSH +extern void debugger_local_cache_flushinv(void); +extern void debugger_local_cache_flushinv_one(u8 *); +#else +static inline void debugger_local_cache_flushinv(void) {} +static inline void debugger_local_cache_flushinv_one(u8 *addr) {} +#endif + +#else /* CONFIG_KERNEL_DEBUGGER */ + +static inline int debugger_intercept(enum exception_code excep, + int signo, int si_code, + struct pt_regs *regs) +{ + return 0; +} + +static inline int at_debugger_breakpoint(struct pt_regs *regs) +{ + return 0; +} + +#endif /* CONFIG_KERNEL_DEBUGGER */ +#endif /* _ASM_DEBUGGER_H */ diff --git a/arch/mn10300/include/asm/div64.h b/arch/mn10300/include/asm/div64.h index 34dcb8e6830..503efab2a51 100644 --- a/arch/mn10300/include/asm/div64.h +++ b/arch/mn10300/include/asm/div64.h @@ -16,6 +16,19 @@ extern void ____unhandled_size_in_do_div___(void); /* + * Beginning with gcc 4.6, the MDR register is represented explicitly. We + * must, therefore, at least explicitly clobber the register when we make + * changes to it. The following assembly fragments *could* be rearranged in + * order to leave the moves to/from the MDR register to the compiler, but the + * gains would be minimal at best. + */ +#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6) +# define CLOBBER_MDR_CC "mdr", "cc" +#else +# define CLOBBER_MDR_CC "cc" +#endif + +/* * divide n by base, leaving the result in n and returning the remainder * - we can do this quite efficiently on the MN10300 by cascading the divides * through the MDR register @@ -29,7 +42,7 @@ extern void ____unhandled_size_in_do_div___(void); "mov mdr,%1 \n" \ : "+r"(n), "=d"(__rem) \ : "r"(base), "1"(__rem) \ - : "cc" \ + : CLOBBER_MDR_CC \ ); \ } else if (sizeof(n) <= 8) { \ union { \ @@ -48,7 +61,7 @@ extern void ____unhandled_size_in_do_div___(void); : "=d"(__rem), "=r"(__quot.w[1]), "=r"(__quot.w[0]) \ : "r"(base), "0"(__rem), "1"(__quot.w[1]), \ "2"(__quot.w[0]) \ - : "cc" \ + : CLOBBER_MDR_CC \ ); \ n = __quot.l; \ } else { \ @@ -72,7 +85,7 @@ unsigned __muldiv64u(unsigned val, unsigned mult, unsigned div) * MDR = MDR:val%div */ : "=r"(result) : "0"(val), "ir"(mult), "r"(div) - : "cc" + : CLOBBER_MDR_CC ); return result; @@ -93,7 +106,7 @@ signed __muldiv64s(signed val, signed mult, signed div) * MDR = MDR:val%div */ : "=r"(result) : "0"(val), "ir"(mult), "r"(div) - : "cc" + : CLOBBER_MDR_CC ); return result; diff --git a/arch/mn10300/include/asm/fpu.h b/arch/mn10300/include/asm/fpu.h index b7625de8ead..738ff72659d 100644 --- a/arch/mn10300/include/asm/fpu.h +++ b/arch/mn10300/include/asm/fpu.h @@ -55,7 +55,6 @@ static inline void clear_using_fpu(struct task_struct *tsk) extern asmlinkage void fpu_kill_state(struct task_struct *); extern asmlinkage void fpu_exception(struct pt_regs *, enum exception_code); -extern asmlinkage void fpu_invalid_op(struct pt_regs *, enum exception_code); extern asmlinkage void fpu_init_state(void); extern asmlinkage void fpu_save(struct fpu_state_struct *); extern int fpu_setup_sigcontext(struct fpucontext *buf); @@ -113,7 +112,6 @@ static inline void flush_fpu(void) extern asmlinkage void unexpected_fpu_exception(struct pt_regs *, enum exception_code); -#define fpu_invalid_op unexpected_fpu_exception #define fpu_exception unexpected_fpu_exception struct task_struct; diff --git a/arch/mn10300/include/asm/intctl-regs.h b/arch/mn10300/include/asm/intctl-regs.h index 585b708c2bc..d65bbeebe50 100644 --- a/arch/mn10300/include/asm/intctl-regs.h +++ b/arch/mn10300/include/asm/intctl-regs.h @@ -60,11 +60,6 @@ #ifndef __ASSEMBLY__ extern void set_intr_level(int irq, u16 level); -extern void mn10300_intc_set_level(unsigned int irq, unsigned int level); -extern void mn10300_intc_clear(unsigned int irq); -extern void mn10300_intc_set(unsigned int irq); -extern void mn10300_intc_enable(unsigned int irq); -extern void mn10300_intc_disable(unsigned int irq); extern void mn10300_set_lateack_irq_type(int irq); #endif diff --git a/arch/mn10300/include/asm/irqflags.h b/arch/mn10300/include/asm/irqflags.h index 7a7ae12c711..678f68d5f37 100644 --- a/arch/mn10300/include/asm/irqflags.h +++ b/arch/mn10300/include/asm/irqflags.h @@ -20,7 +20,7 @@ /* * interrupt control * - "disabled": run in IM1/2 - * - level 0 - GDB stub + * - level 0 - kernel debugger * - level 1 - virtual serial DMA (if present) * - level 5 - normal interrupt priority * - level 6 - timer interrupt diff --git a/arch/mn10300/include/asm/kgdb.h b/arch/mn10300/include/asm/kgdb.h new file mode 100644 index 00000000000..eb245f18a70 --- /dev/null +++ b/arch/mn10300/include/asm/kgdb.h @@ -0,0 +1,81 @@ +/* Kernel debugger for MN10300 + * + * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_KGDB_H +#define _ASM_KGDB_H + +/* + * BUFMAX defines the maximum number of characters in inbound/outbound + * buffers at least NUMREGBYTES*2 are needed for register packets + * Longer buffer is needed to list all threads + */ +#define BUFMAX 1024 + +/* + * Note that this register image is in a different order than the register + * image that Linux produces at interrupt time. + */ +enum regnames { + GDB_FR_D0 = 0, + GDB_FR_D1 = 1, + GDB_FR_D2 = 2, + GDB_FR_D3 = 3, + GDB_FR_A0 = 4, + GDB_FR_A1 = 5, + GDB_FR_A2 = 6, + GDB_FR_A3 = 7, + + GDB_FR_SP = 8, + GDB_FR_PC = 9, + GDB_FR_MDR = 10, + GDB_FR_EPSW = 11, + GDB_FR_LIR = 12, + GDB_FR_LAR = 13, + GDB_FR_MDRQ = 14, + + GDB_FR_E0 = 15, + GDB_FR_E1 = 16, + GDB_FR_E2 = 17, + GDB_FR_E3 = 18, + GDB_FR_E4 = 19, + GDB_FR_E5 = 20, + GDB_FR_E6 = 21, + GDB_FR_E7 = 22, + + GDB_FR_SSP = 23, + GDB_FR_MSP = 24, + GDB_FR_USP = 25, + GDB_FR_MCRH = 26, + GDB_FR_MCRL = 27, + GDB_FR_MCVF = 28, + + GDB_FR_FPCR = 29, + GDB_FR_DUMMY0 = 30, + GDB_FR_DUMMY1 = 31, + + GDB_FR_FS0 = 32, + + GDB_FR_SIZE = 64, +}; + +#define GDB_ORIG_D0 41 +#define NUMREGBYTES (GDB_FR_SIZE*4) + +static inline void arch_kgdb_breakpoint(void) +{ + asm(".globl __arch_kgdb_breakpoint; __arch_kgdb_breakpoint: break"); +} +extern u8 __arch_kgdb_breakpoint; + +#define BREAK_INSTR_SIZE 1 +#define CACHE_FLUSH_IS_SAFE 1 + +#endif /* _ASM_KGDB_H */ diff --git a/arch/mn10300/include/asm/smp.h b/arch/mn10300/include/asm/smp.h index a3930e43a95..6745dbe6494 100644 --- a/arch/mn10300/include/asm/smp.h +++ b/arch/mn10300/include/asm/smp.h @@ -34,7 +34,7 @@ #define LOCAL_TIMER_IPI 193 #define FLUSH_CACHE_IPI 194 #define CALL_FUNCTION_NMI_IPI 195 -#define GDB_NMI_IPI 196 +#define DEBUGGER_NMI_IPI 196 #define SMP_BOOT_IRQ 195 @@ -43,6 +43,7 @@ #define LOCAL_TIMER_GxICR_LV GxICR_LEVEL_4 #define FLUSH_CACHE_GxICR_LV GxICR_LEVEL_0 #define SMP_BOOT_GxICR_LV GxICR_LEVEL_0 +#define DEBUGGER_GxICR_LV CONFIG_DEBUGGER_IRQ_LEVEL #define TIME_OUT_COUNT_BOOT_IPI 100 #define DELAY_TIME_BOOT_IPI 75000 @@ -61,8 +62,9 @@ * An alternate way of dealing with this could be to use the EPSW.S bits to * cache this information for systems with up to four CPUs. */ +#define arch_smp_processor_id() (CPUID) #if 0 -#define raw_smp_processor_id() (CPUID) +#define raw_smp_processor_id() (arch_smp_processor_id()) #else #define raw_smp_processor_id() (current_thread_info()->cpu) #endif diff --git a/arch/mn10300/include/asm/thread_info.h b/arch/mn10300/include/asm/thread_info.h index aa07a4a5d79..87c213002d4 100644 --- a/arch/mn10300/include/asm/thread_info.h +++ b/arch/mn10300/include/asm/thread_info.h @@ -124,12 +124,18 @@ static inline unsigned long current_stack_pointer(void) /* thread information allocation */ #ifdef CONFIG_DEBUG_STACK_USAGE -#define alloc_thread_info(tsk) kzalloc(THREAD_SIZE, GFP_KERNEL) +#define alloc_thread_info_node(tsk, node) \ + kzalloc_node(THREAD_SIZE, GFP_KERNEL, node) #else -#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL) +#define alloc_thread_info_node(tsk, node) \ + kmalloc_node(THREAD_SIZE, GFP_KERNEL, node) #endif +#ifndef CONFIG_KGDB #define free_thread_info(ti) kfree((ti)) +#else +extern void free_thread_info(struct thread_info *); +#endif #define get_thread_info(ti) get_task_struct((ti)->task) #define put_thread_info(ti) put_task_struct((ti)->task) diff --git a/arch/mn10300/include/asm/types.h b/arch/mn10300/include/asm/types.h index 7b9f01042fd..c1833eb192e 100644 --- a/arch/mn10300/include/asm/types.h +++ b/arch/mn10300/include/asm/types.h @@ -26,13 +26,6 @@ typedef unsigned short umode_t; #define BITS_PER_LONG 32 -#ifndef __ASSEMBLY__ - -/* Dma addresses are 32-bits wide. */ -typedef u32 dma_addr_t; - -#endif /* __ASSEMBLY__ */ - #endif /* __KERNEL__ */ #endif /* _ASM_TYPES_H */ diff --git a/arch/mn10300/kernel/Makefile b/arch/mn10300/kernel/Makefile index 8f5f1e81baf..47ed30fe817 100644 --- a/arch/mn10300/kernel/Makefile +++ b/arch/mn10300/kernel/Makefile @@ -8,7 +8,8 @@ fpu-obj-$(CONFIG_FPU) := fpu.o fpu-low.o obj-y := process.o signal.o entry.o traps.o irq.o \ ptrace.o setup.o time.o sys_mn10300.o io.o kthread.o \ - switch_to.o mn10300_ksyms.o kernel_execve.o $(fpu-obj-y) + switch_to.o mn10300_ksyms.o kernel_execve.o $(fpu-obj-y) \ + csrc-mn10300.o cevt-mn10300.o obj-$(CONFIG_SMP) += smp.o smp-low.o @@ -20,13 +21,8 @@ obj-$(CONFIG_GDBSTUB) += gdb-stub.o gdb-low.o obj-$(CONFIG_GDBSTUB_ON_TTYSx) += gdb-io-serial.o gdb-io-serial-low.o obj-$(CONFIG_GDBSTUB_ON_TTYSMx) += gdb-io-ttysm.o gdb-io-ttysm-low.o -ifeq ($(CONFIG_MN10300_CACHE_ENABLED),y) -obj-$(CONFIG_GDBSTUB) += gdb-cache.o -endif - obj-$(CONFIG_MN10300_RTC) += rtc.o obj-$(CONFIG_PROFILE) += profile.o profile-low.o obj-$(CONFIG_MODULES) += module.o obj-$(CONFIG_KPROBES) += kprobes.o -obj-$(CONFIG_CSRC_MN10300) += csrc-mn10300.o -obj-$(CONFIG_CEVT_MN10300) += cevt-mn10300.o +obj-$(CONFIG_KGDB) += kgdb.o diff --git a/arch/mn10300/kernel/cevt-mn10300.c b/arch/mn10300/kernel/cevt-mn10300.c index d4cb535bf78..69cae026078 100644 --- a/arch/mn10300/kernel/cevt-mn10300.c +++ b/arch/mn10300/kernel/cevt-mn10300.c @@ -89,9 +89,10 @@ int __init init_clockevents(void) cd->name = "Timestamp"; cd->features = CLOCK_EVT_FEAT_ONESHOT; - /* Calculate the min / max delta */ - clockevent_set_clock(cd, MN10300_JCCLK); + /* Calculate shift/mult. We want to spawn at least 1 second */ + clockevents_calc_mult_shift(cd, MN10300_JCCLK, 1); + /* Calculate the min / max delta */ cd->max_delta_ns = clockevent_delta2ns(TMJCBR_MAX, cd); cd->min_delta_ns = clockevent_delta2ns(100, cd); @@ -110,9 +111,9 @@ int __init init_clockevents(void) #if defined(CONFIG_SMP) && !defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) /* setup timer irq affinity so it only runs on this cpu */ { - struct irq_desc *desc; - desc = irq_to_desc(cd->irq); - cpumask_copy(desc->affinity, cpumask_of(cpu)); + struct irq_data *data; + data = irq_get_irq_data(cd->irq); + cpumask_copy(data->affinity, cpumask_of(cpu)); iact->flags |= IRQF_NOBALANCING; } #endif diff --git a/arch/mn10300/kernel/csrc-mn10300.c b/arch/mn10300/kernel/csrc-mn10300.c index ba2f0c4d6e0..45644cf18c4 100644 --- a/arch/mn10300/kernel/csrc-mn10300.c +++ b/arch/mn10300/kernel/csrc-mn10300.c @@ -29,7 +29,6 @@ static struct clocksource clocksource_mn10300 = { int __init init_clocksource(void) { startup_timestamp_counter(); - clocksource_set_clock(&clocksource_mn10300, MN10300_TSCCLK); - clocksource_register(&clocksource_mn10300); + clocksource_register_hz(&clocksource_mn10300, MN10300_TSCCLK); return 0; } diff --git a/arch/mn10300/kernel/entry.S b/arch/mn10300/kernel/entry.S index f00b9bafcd3..fb93ad720b8 100644 --- a/arch/mn10300/kernel/entry.S +++ b/arch/mn10300/kernel/entry.S @@ -266,7 +266,11 @@ ENTRY(raw_bus_error) ############################################################################### # -# Miscellaneous exception entry points +# NMI exception entry points +# +# This is used by ordinary interrupt channels that have the GxICR_NMI bit set +# in addition to the main NMI and Watchdog channels. SMP NMI IPIs use this +# facility. # ############################################################################### ENTRY(nmi_handler) @@ -281,7 +285,7 @@ ENTRY(nmi_handler) and NMIAGR_GN,d0 lsr 0x2,d0 cmp CALL_FUNCTION_NMI_IPI,d0 - bne 5f # if not call function, jump + bne nmi_not_smp_callfunc # if not call function, jump # function call nmi ipi add 4,sp # no need to store TBR @@ -295,59 +299,38 @@ ENTRY(nmi_handler) call smp_nmi_call_function_interrupt[],0 RESTORE_ALL -5: -#ifdef CONFIG_GDBSTUB - cmp GDB_NMI_IPI,d0 - bne 3f # if not gdb nmi ipi, jump +nmi_not_smp_callfunc: +#ifdef CONFIG_KERNEL_DEBUGGER + cmp DEBUGGER_NMI_IPI,d0 + bne nmi_not_debugger # if not kernel debugger NMI IPI, jump - # gdb nmi ipi + # kernel debugger NMI IPI add 4,sp # no need to store TBR mov GxICR_DETECT,d0 # clear NMI - movbu d0,(GxICR(GDB_NMI_IPI)) - movhu (GxICR(GDB_NMI_IPI)),d0 + movbu d0,(GxICR(DEBUGGER_NMI_IPI)) + movhu (GxICR(DEBUGGER_NMI_IPI)),d0 and ~EPSW_NMID,epsw # enable NMI -#ifdef CONFIG_MN10300_CACHE_ENABLED - mov (gdbstub_nmi_opr_type),d0 - cmp GDBSTUB_NMI_CACHE_PURGE,d0 - bne 4f # if not gdb cache purge, jump - - # gdb cache purge nmi ipi - add -20,sp - mov d1,(4,sp) - mov a0,(8,sp) - mov a1,(12,sp) - mov mdr,d0 - mov d0,(16,sp) - call gdbstub_local_purge_cache[],0 - mov 0x1,d0 - mov (CPUID),d1 - asl d1,d0 - mov gdbstub_nmi_cpumask,a0 - bclr d0,(a0) - mov (4,sp),d1 - mov (8,sp),a0 - mov (12,sp),a1 - mov (16,sp),d0 - mov d0,mdr - add 20,sp - mov (sp),d0 - add 4,sp - rti -4: -#endif /* CONFIG_MN10300_CACHE_ENABLED */ - # gdb wait nmi ipi + mov (sp),d0 SAVE_ALL - call gdbstub_nmi_wait[],0 + mov fp,d0 # arg 0: stacked register file + mov a2,d1 # arg 1: exception number + call debugger_nmi_interrupt[],0 RESTORE_ALL -3: -#endif /* CONFIG_GDBSTUB */ + +nmi_not_debugger: +#endif /* CONFIG_KERNEL_DEBUGGER */ mov (sp),d0 # restore TBR to d0 add 4,sp #endif /* CONFIG_SMP */ bra __common_exception_nonmi +############################################################################### +# +# General exception entry point +# +############################################################################### ENTRY(__common_exception) add -4,sp mov d0,(sp) diff --git a/arch/mn10300/kernel/fpu.c b/arch/mn10300/kernel/fpu.c index 5f9c3fa19a8..bb5fa7df6c4 100644 --- a/arch/mn10300/kernel/fpu.c +++ b/arch/mn10300/kernel/fpu.c @@ -70,24 +70,6 @@ asmlinkage void fpu_exception(struct pt_regs *regs, enum exception_code code) } /* - * handle an FPU invalid_op exception - * - Derived from DO_EINFO() macro in arch/mn10300/kernel/traps.c - */ -asmlinkage void fpu_invalid_op(struct pt_regs *regs, enum exception_code code) -{ - siginfo_t info; - - if (!user_mode(regs)) - die_if_no_fixup("FPU invalid opcode", regs, code); - - info.si_signo = SIGILL; - info.si_errno = 0; - info.si_code = ILL_COPROC; - info.si_addr = (void *) regs->pc; - force_sig_info(info.si_signo, &info, current); -} - -/* * save the FPU state to a signal context */ int fpu_setup_sigcontext(struct fpucontext *fpucontext) diff --git a/arch/mn10300/kernel/gdb-cache.S b/arch/mn10300/kernel/gdb-cache.S deleted file mode 100644 index 1108badc3d3..00000000000 --- a/arch/mn10300/kernel/gdb-cache.S +++ /dev/null @@ -1,105 +0,0 @@ -############################################################################### -# -# MN10300 Low-level cache purging routines for gdbstub -# -# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. -# Written by David Howells (dhowells@redhat.com) -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public Licence -# as published by the Free Software Foundation; either version -# 2 of the Licence, or (at your option) any later version. -# -############################################################################### -#include <linux/sys.h> -#include <linux/linkage.h> -#include <asm/smp.h> -#include <asm/cache.h> -#include <asm/cpu-regs.h> -#include <asm/exceptions.h> -#include <asm/frame.inc> -#include <asm/serial-regs.h> - - .text - -############################################################################### -# -# GDB stub cache purge -# -############################################################################### - .type gdbstub_purge_cache,@function -ENTRY(gdbstub_purge_cache) - ####################################################################### - # read the addresses tagged in the cache's tag RAM and attempt to flush - # those addresses specifically - # - we rely on the hardware to filter out invalid tag entry addresses - mov DCACHE_TAG(0,0),a0 # dcache tag RAM access address - mov DCACHE_PURGE(0,0),a1 # dcache purge request address - mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,d1 # total number of entries - -mn10300_dcache_flush_loop: - mov (a0),d0 - and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0 - or L1_CACHE_TAG_VALID,d0 # retain valid entries in the - # cache - mov d0,(a1) # conditional purge - -mn10300_dcache_flush_skip: - add L1_CACHE_BYTES,a0 - add L1_CACHE_BYTES,a1 - add -1,d1 - bne mn10300_dcache_flush_loop - -;; # unconditionally flush and invalidate the dcache -;; mov DCACHE_PURGE(0,0),a1 # dcache purge request address -;; mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,d1 # total number of -;; # entries -;; -;; gdbstub_purge_cache__dcache_loop: -;; mov (a1),d0 # unconditional purge -;; -;; add L1_CACHE_BYTES,a1 -;; add -1,d1 -;; bne gdbstub_purge_cache__dcache_loop - - ####################################################################### - # now invalidate the icache - mov CHCTR,a0 - movhu (a0),a1 - - mov epsw,d1 - and ~EPSW_IE,epsw - nop - nop - - # disable the icache - and ~CHCTR_ICEN,d0 - movhu d0,(a0) - - # and wait for it to calm down - setlb - movhu (a0),d0 - btst CHCTR_ICBUSY,d0 - lne - - # invalidate - or CHCTR_ICINV,d0 - movhu d0,(a0) - - # wait for the cache to finish - mov CHCTR,a0 - setlb - movhu (a0),d0 - btst CHCTR_ICBUSY,d0 - lne - - # and reenable it - movhu a1,(a0) - movhu (a0),d0 # read back to flush - # (SIGILLs all over without this) - - mov d1,epsw - - ret [],0 - - .size gdbstub_purge_cache,.-gdbstub_purge_cache diff --git a/arch/mn10300/kernel/gdb-io-ttysm.c b/arch/mn10300/kernel/gdb-io-ttysm.c index abdeea153c8..c859cacbb9c 100644 --- a/arch/mn10300/kernel/gdb-io-ttysm.c +++ b/arch/mn10300/kernel/gdb-io-ttysm.c @@ -59,10 +59,10 @@ void __init gdbstub_io_init(void) /* we want to get serial receive interrupts */ set_intr_level(gdbstub_port->rx_irq, - NUM2GxICR_LEVEL(CONFIG_GDBSTUB_IRQ_LEVEL)); + NUM2GxICR_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL)); set_intr_level(gdbstub_port->tx_irq, - NUM2GxICR_LEVEL(CONFIG_GDBSTUB_IRQ_LEVEL)); - set_intr_stub(NUM2EXCEP_IRQ_LEVEL(CONFIG_GDBSTUB_IRQ_LEVEL), + NUM2GxICR_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL)); + set_intr_stub(NUM2EXCEP_IRQ_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL), gdbstub_io_rx_handler); *gdbstub_port->rx_icr |= GxICR_ENABLE; @@ -88,7 +88,7 @@ void __init gdbstub_io_init(void) /* permit level 0 IRQs only */ arch_local_change_intr_mask_level( - NUM2EPSW_IM(CONFIG_GDBSTUB_IRQ_LEVEL + 1)); + NUM2EPSW_IM(CONFIG_DEBUGGER_IRQ_LEVEL + 1)); } /* diff --git a/arch/mn10300/kernel/gdb-stub.c b/arch/mn10300/kernel/gdb-stub.c index b169d99d9f2..538266b2c9b 100644 --- a/arch/mn10300/kernel/gdb-stub.c +++ b/arch/mn10300/kernel/gdb-stub.c @@ -133,7 +133,7 @@ #include <asm/system.h> #include <asm/gdb-stub.h> #include <asm/exceptions.h> -#include <asm/cacheflush.h> +#include <asm/debugger.h> #include <asm/serial-regs.h> #include <asm/busctl-regs.h> #include <unit/leds.h> @@ -405,6 +405,7 @@ static int hexToInt(char **ptr, int *intValue) return (numChars); } +#ifdef CONFIG_GDBSTUB_ALLOW_SINGLE_STEP /* * We single-step by setting breakpoints. When an exception * is handled, we need to restore the instructions hoisted @@ -729,6 +730,7 @@ static int gdbstub_single_step(struct pt_regs *regs) __gdbstub_restore_bp(); return -EFAULT; } +#endif /* CONFIG_GDBSTUB_ALLOW_SINGLE_STEP */ #ifdef CONFIG_GDBSTUB_CONSOLE @@ -1171,7 +1173,7 @@ int gdbstub_clear_breakpoint(u8 *addr, int len) /* * This function does all command processing for interfacing to gdb - * - returns 1 if the exception should be skipped, 0 otherwise. + * - returns 0 if the exception should be skipped, -ERROR otherwise. */ static int gdbstub(struct pt_regs *regs, enum exception_code excep) { @@ -1186,7 +1188,7 @@ static int gdbstub(struct pt_regs *regs, enum exception_code excep) int loop; if (excep == EXCEP_FPU_DISABLED) - return 0; + return -ENOTSUPP; gdbstub_flush_caches = 0; @@ -1195,7 +1197,7 @@ static int gdbstub(struct pt_regs *regs, enum exception_code excep) asm volatile("mov mdr,%0" : "=d"(mdr)); local_save_flags(epsw); arch_local_change_intr_mask_level( - NUM2EPSW_IM(CONFIG_GDBSTUB_IRQ_LEVEL + 1)); + NUM2EPSW_IM(CONFIG_DEBUGGER_IRQ_LEVEL + 1)); gdbstub_store_fpu(); @@ -1208,11 +1210,13 @@ static int gdbstub(struct pt_regs *regs, enum exception_code excep) /* if we were single stepping, restore the opcodes hoisted for the * breakpoint[s] */ broke = 0; +#ifdef CONFIG_GDBSTUB_ALLOW_SINGLE_STEP if ((step_bp[0].addr && step_bp[0].addr == (u8 *) regs->pc) || (step_bp[1].addr && step_bp[1].addr == (u8 *) regs->pc)) broke = 1; __gdbstub_restore_bp(); +#endif if (gdbstub_rx_unget) { sigval = SIGINT; @@ -1548,17 +1552,21 @@ packet_waiting: * Step to next instruction */ case 's': - /* - * using the T flag doesn't seem to perform single + /* Using the T flag doesn't seem to perform single * stepping (it seems to wind up being caught by the * JTAG unit), so we have to use breakpoints and * continue instead. */ +#ifdef CONFIG_GDBSTUB_ALLOW_SINGLE_STEP if (gdbstub_single_step(regs) < 0) /* ignore any fault error for now */ gdbstub_printk("unable to set single-step" " bp\n"); goto done; +#else + gdbstub_strcpy(output_buffer, "E01"); + break; +#endif /* * Set baud rate (bBB) @@ -1657,7 +1665,7 @@ done: * NB: We flush both caches, just to be sure... */ if (gdbstub_flush_caches) - gdbstub_purge_cache(); + debugger_local_cache_flushinv(); gdbstub_load_fpu(); mn10300_set_gdbleds(0); @@ -1667,14 +1675,23 @@ done: touch_softlockup_watchdog(); local_irq_restore(epsw); - return 1; + return 0; +} + +/* + * Determine if we hit a debugger special breakpoint that needs skipping over + * automatically. + */ +int at_debugger_breakpoint(struct pt_regs *regs) +{ + return 0; } /* * handle event interception */ -asmlinkage int gdbstub_intercept(struct pt_regs *regs, - enum exception_code excep) +asmlinkage int debugger_intercept(enum exception_code excep, + int signo, int si_code, struct pt_regs *regs) { static u8 notfirst = 1; int ret; @@ -1688,7 +1705,7 @@ asmlinkage int gdbstub_intercept(struct pt_regs *regs, asm("mov mdr,%0" : "=d"(mdr)); gdbstub_entry( - "--> gdbstub_intercept(%p,%04x) [MDR=%lx PC=%lx]\n", + "--> debugger_intercept(%p,%04x) [MDR=%lx PC=%lx]\n", regs, excep, mdr, regs->pc); gdbstub_entry( @@ -1722,7 +1739,7 @@ asmlinkage int gdbstub_intercept(struct pt_regs *regs, ret = gdbstub(regs, excep); - gdbstub_entry("<-- gdbstub_intercept()\n"); + gdbstub_entry("<-- debugger_intercept()\n"); gdbstub_busy = 0; return ret; } diff --git a/arch/mn10300/kernel/internal.h b/arch/mn10300/kernel/internal.h index 6a064ab5af0..a5ac755dd69 100644 --- a/arch/mn10300/kernel/internal.h +++ b/arch/mn10300/kernel/internal.h @@ -30,16 +30,13 @@ extern void mn10300_low_ipi_handler(void); #endif /* - * time.c + * smp.c */ -extern irqreturn_t local_timer_interrupt(void); +#ifdef CONFIG_SMP +extern void smp_jump_to_debugger(void); +#endif /* * time.c */ -#ifdef CONFIG_CEVT_MN10300 -extern void clockevent_set_clock(struct clock_event_device *, unsigned int); -#endif -#ifdef CONFIG_CSRC_MN10300 -extern void clocksource_set_clock(struct clocksource *, unsigned int); -#endif +extern irqreturn_t local_timer_interrupt(void); diff --git a/arch/mn10300/kernel/irq.c b/arch/mn10300/kernel/irq.c index ac11754ecec..86af0d7d077 100644 --- a/arch/mn10300/kernel/irq.c +++ b/arch/mn10300/kernel/irq.c @@ -37,8 +37,9 @@ atomic_t irq_err_count; /* * MN10300 interrupt controller operations */ -static void mn10300_cpupic_ack(unsigned int irq) +static void mn10300_cpupic_ack(struct irq_data *d) { + unsigned int irq = d->irq; unsigned long flags; u16 tmp; @@ -61,13 +62,14 @@ static void __mask_and_set_icr(unsigned int irq, arch_local_irq_restore(flags); } -static void mn10300_cpupic_mask(unsigned int irq) +static void mn10300_cpupic_mask(struct irq_data *d) { - __mask_and_set_icr(irq, GxICR_LEVEL, 0); + __mask_and_set_icr(d->irq, GxICR_LEVEL, 0); } -static void mn10300_cpupic_mask_ack(unsigned int irq) +static void mn10300_cpupic_mask_ack(struct irq_data *d) { + unsigned int irq = d->irq; #ifdef CONFIG_SMP unsigned long flags; u16 tmp; @@ -85,7 +87,7 @@ static void mn10300_cpupic_mask_ack(unsigned int irq) tmp2 = GxICR(irq); irq_affinity_online[irq] = - any_online_cpu(*irq_desc[irq].affinity); + any_online_cpu(*d->affinity); CROSS_GxICR(irq, irq_affinity_online[irq]) = (tmp & (GxICR_LEVEL | GxICR_ENABLE)) | GxICR_DETECT; tmp = CROSS_GxICR(irq, irq_affinity_online[irq]); @@ -97,13 +99,14 @@ static void mn10300_cpupic_mask_ack(unsigned int irq) #endif /* CONFIG_SMP */ } -static void mn10300_cpupic_unmask(unsigned int irq) +static void mn10300_cpupic_unmask(struct irq_data *d) { - __mask_and_set_icr(irq, GxICR_LEVEL, GxICR_ENABLE); + __mask_and_set_icr(d->irq, GxICR_LEVEL, GxICR_ENABLE); } -static void mn10300_cpupic_unmask_clear(unsigned int irq) +static void mn10300_cpupic_unmask_clear(struct irq_data *d) { + unsigned int irq = d->irq; /* the MN10300 PIC latches its interrupt request bit, even after the * device has ceased to assert its interrupt line and the interrupt * channel has been disabled in the PIC, so for level-triggered @@ -121,7 +124,7 @@ static void mn10300_cpupic_unmask_clear(unsigned int irq) } else { tmp = GxICR(irq); - irq_affinity_online[irq] = any_online_cpu(*irq_desc[irq].affinity); + irq_affinity_online[irq] = any_online_cpu(*d->affinity); CROSS_GxICR(irq, irq_affinity_online[irq]) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT; tmp = CROSS_GxICR(irq, irq_affinity_online[irq]); } @@ -134,7 +137,8 @@ static void mn10300_cpupic_unmask_clear(unsigned int irq) #ifdef CONFIG_SMP static int -mn10300_cpupic_setaffinity(unsigned int irq, const struct cpumask *mask) +mn10300_cpupic_setaffinity(struct irq_data *d, const struct cpumask *mask, + bool force) { unsigned long flags; int err; @@ -142,14 +146,14 @@ mn10300_cpupic_setaffinity(unsigned int irq, const struct cpumask *mask) flags = arch_local_cli_save(); /* check irq no */ - switch (irq) { + switch (d->irq) { case TMJCIRQ: case RESCHEDULE_IPI: case CALL_FUNC_SINGLE_IPI: case LOCAL_TIMER_IPI: case FLUSH_CACHE_IPI: case CALL_FUNCTION_NMI_IPI: - case GDB_NMI_IPI: + case DEBUGGER_NMI_IPI: #ifdef CONFIG_MN10300_TTYSM0 case SC0RXIRQ: case SC0TXIRQ: @@ -181,7 +185,7 @@ mn10300_cpupic_setaffinity(unsigned int irq, const struct cpumask *mask) break; default: - set_bit(irq, irq_affinity_request); + set_bit(d->irq, irq_affinity_request); err = 0; break; } @@ -202,15 +206,15 @@ mn10300_cpupic_setaffinity(unsigned int irq, const struct cpumask *mask) * mask_ack() is provided), and mask_ack() just masks. */ static struct irq_chip mn10300_cpu_pic_level = { - .name = "cpu_l", - .disable = mn10300_cpupic_mask, - .enable = mn10300_cpupic_unmask_clear, - .ack = NULL, - .mask = mn10300_cpupic_mask, - .mask_ack = mn10300_cpupic_mask, - .unmask = mn10300_cpupic_unmask_clear, + .name = "cpu_l", + .irq_disable = mn10300_cpupic_mask, + .irq_enable = mn10300_cpupic_unmask_clear, + .irq_ack = NULL, + .irq_mask = mn10300_cpupic_mask, + .irq_mask_ack = mn10300_cpupic_mask, + .irq_unmask = mn10300_cpupic_unmask_clear, #ifdef CONFIG_SMP - .set_affinity = mn10300_cpupic_setaffinity, + .irq_set_affinity = mn10300_cpupic_setaffinity, #endif }; @@ -220,15 +224,15 @@ static struct irq_chip mn10300_cpu_pic_level = { * We use the latch clearing function of the PIC as the 'ACK' function. */ static struct irq_chip mn10300_cpu_pic_edge = { - .name = "cpu_e", - .disable = mn10300_cpupic_mask, - .enable = mn10300_cpupic_unmask, - .ack = mn10300_cpupic_ack, - .mask = mn10300_cpupic_mask, - .mask_ack = mn10300_cpupic_mask_ack, - .unmask = mn10300_cpupic_unmask, + .name = "cpu_e", + .irq_disable = mn10300_cpupic_mask, + .irq_enable = mn10300_cpupic_unmask, + .irq_ack = mn10300_cpupic_ack, + .irq_mask = mn10300_cpupic_mask, + .irq_mask_ack = mn10300_cpupic_mask_ack, + .irq_unmask = mn10300_cpupic_unmask, #ifdef CONFIG_SMP - .set_affinity = mn10300_cpupic_setaffinity, + .irq_set_affinity = mn10300_cpupic_setaffinity, #endif }; @@ -252,31 +256,6 @@ void set_intr_level(int irq, u16 level) __mask_and_set_icr(irq, GxICR_ENABLE, level); } -void mn10300_intc_set_level(unsigned int irq, unsigned int level) -{ - set_intr_level(irq, NUM2GxICR_LEVEL(level) & GxICR_LEVEL); -} - -void mn10300_intc_clear(unsigned int irq) -{ - __mask_and_set_icr(irq, GxICR_LEVEL | GxICR_ENABLE, GxICR_DETECT); -} - -void mn10300_intc_set(unsigned int irq) -{ - __mask_and_set_icr(irq, 0, GxICR_REQUEST | GxICR_DETECT); -} - -void mn10300_intc_enable(unsigned int irq) -{ - mn10300_cpupic_unmask(irq); -} - -void mn10300_intc_disable(unsigned int irq) -{ - mn10300_cpupic_mask(irq); -} - /* * mark an interrupt to be ACK'd after interrupt handlers have been run rather * than before @@ -284,7 +263,7 @@ void mn10300_intc_disable(unsigned int irq) */ void mn10300_set_lateack_irq_type(int irq) { - set_irq_chip_and_handler(irq, &mn10300_cpu_pic_level, + irq_set_chip_and_handler(irq, &mn10300_cpu_pic_level, handle_level_irq); } @@ -296,12 +275,12 @@ void __init init_IRQ(void) int irq; for (irq = 0; irq < NR_IRQS; irq++) - if (irq_desc[irq].chip == &no_irq_chip) + if (irq_get_chip(irq) == &no_irq_chip) /* due to the PIC latching interrupt requests, even * when the IRQ is disabled, IRQ_PENDING is superfluous * and we can use handle_level_irq() for edge-triggered * interrupts */ - set_irq_chip_and_handler(irq, &mn10300_cpu_pic_edge, + irq_set_chip_and_handler(irq, &mn10300_cpu_pic_edge, handle_level_irq); unit_init_IRQ(); @@ -356,91 +335,42 @@ asmlinkage void do_IRQ(void) /* * Display interrupt management information through /proc/interrupts */ -int show_interrupts(struct seq_file *p, void *v) +int arch_show_interrupts(struct seq_file *p, int prec) { - int i = *(loff_t *) v, j, cpu; - struct irqaction *action; - unsigned long flags; - - switch (i) { - /* display column title bar naming CPUs */ - case 0: - seq_printf(p, " "); - for (j = 0; j < NR_CPUS; j++) - if (cpu_online(j)) - seq_printf(p, "CPU%d ", j); - seq_putc(p, '\n'); - break; - - /* display information rows, one per active CPU */ - case 1 ... NR_IRQS - 1: - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); - - action = irq_desc[i].action; - if (action) { - seq_printf(p, "%3d: ", i); - for_each_present_cpu(cpu) - seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); - - if (i < NR_CPU_IRQS) - seq_printf(p, " %14s.%u", - irq_desc[i].chip->name, - (GxICR(i) & GxICR_LEVEL) >> - GxICR_LEVEL_SHIFT); - else - seq_printf(p, " %14s", - irq_desc[i].chip->name); - - seq_printf(p, " %s", action->name); - - for (action = action->next; - action; - action = action->next) - seq_printf(p, ", %s", action->name); - - seq_putc(p, '\n'); - } - - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); - break; - - /* polish off with NMI and error counters */ - case NR_IRQS: #ifdef CONFIG_MN10300_WD_TIMER - seq_printf(p, "NMI: "); - for (j = 0; j < NR_CPUS; j++) - if (cpu_online(j)) - seq_printf(p, "%10u ", nmi_count(j)); - seq_putc(p, '\n'); -#endif + int j; - seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count)); - break; - } + seq_printf(p, "%*s: ", prec, "NMI"); + for (j = 0; j < NR_CPUS; j++) + if (cpu_online(j)) + seq_printf(p, "%10u ", nmi_count(j)); + seq_putc(p, '\n'); +#endif + seq_printf(p, "%*s: ", prec, "ERR"); + seq_printf(p, "%10u\n", atomic_read(&irq_err_count)); return 0; } #ifdef CONFIG_HOTPLUG_CPU void migrate_irqs(void) { - irq_desc_t *desc; int irq; unsigned int self, new; unsigned long flags; self = smp_processor_id(); for (irq = 0; irq < NR_IRQS; irq++) { - desc = irq_desc + irq; + struct irq_data *data = irq_get_irq_data(irq); - if (desc->status == IRQ_PER_CPU) + if (irqd_is_per_cpu(data)) continue; - if (cpu_isset(self, irq_desc[irq].affinity) && + if (cpu_isset(self, data->affinity) && !cpus_intersects(irq_affinity[irq], cpu_online_map)) { int cpu_id; cpu_id = first_cpu(cpu_online_map); - cpu_set(cpu_id, irq_desc[irq].affinity); + cpu_set(cpu_id, data->affinity); } /* We need to operate irq_affinity_online atomically. */ arch_local_cli_save(flags); @@ -451,7 +381,7 @@ void migrate_irqs(void) GxICR(irq) = x & GxICR_LEVEL; tmp = GxICR(irq); - new = any_online_cpu(irq_desc[irq].affinity); + new = any_online_cpu(data->affinity); irq_affinity_online[irq] = new; CROSS_GxICR(irq, new) = diff --git a/arch/mn10300/kernel/kgdb.c b/arch/mn10300/kernel/kgdb.c new file mode 100644 index 00000000000..f6c981db2a3 --- /dev/null +++ b/arch/mn10300/kernel/kgdb.c @@ -0,0 +1,502 @@ +/* kgdb support for MN10300 + * + * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#include <linux/slab.h> +#include <linux/ptrace.h> +#include <linux/kgdb.h> +#include <linux/uaccess.h> +#include <unit/leds.h> +#include <unit/serial.h> +#include <asm/debugger.h> +#include <asm/serial-regs.h> +#include "internal.h" + +/* + * Software single-stepping breakpoint save (used by __switch_to()) + */ +static struct thread_info *kgdb_sstep_thread; +u8 *kgdb_sstep_bp_addr[2]; +u8 kgdb_sstep_bp[2]; + +/* + * Copy kernel exception frame registers to the GDB register file + */ +void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) +{ + unsigned long ssp = (unsigned long) (regs + 1); + + gdb_regs[GDB_FR_D0] = regs->d0; + gdb_regs[GDB_FR_D1] = regs->d1; + gdb_regs[GDB_FR_D2] = regs->d2; + gdb_regs[GDB_FR_D3] = regs->d3; + gdb_regs[GDB_FR_A0] = regs->a0; + gdb_regs[GDB_FR_A1] = regs->a1; + gdb_regs[GDB_FR_A2] = regs->a2; + gdb_regs[GDB_FR_A3] = regs->a3; + gdb_regs[GDB_FR_SP] = (regs->epsw & EPSW_nSL) ? regs->sp : ssp; + gdb_regs[GDB_FR_PC] = regs->pc; + gdb_regs[GDB_FR_MDR] = regs->mdr; + gdb_regs[GDB_FR_EPSW] = regs->epsw; + gdb_regs[GDB_FR_LIR] = regs->lir; + gdb_regs[GDB_FR_LAR] = regs->lar; + gdb_regs[GDB_FR_MDRQ] = regs->mdrq; + gdb_regs[GDB_FR_E0] = regs->e0; + gdb_regs[GDB_FR_E1] = regs->e1; + gdb_regs[GDB_FR_E2] = regs->e2; + gdb_regs[GDB_FR_E3] = regs->e3; + gdb_regs[GDB_FR_E4] = regs->e4; + gdb_regs[GDB_FR_E5] = regs->e5; + gdb_regs[GDB_FR_E6] = regs->e6; + gdb_regs[GDB_FR_E7] = regs->e7; + gdb_regs[GDB_FR_SSP] = ssp; + gdb_regs[GDB_FR_MSP] = 0; + gdb_regs[GDB_FR_USP] = regs->sp; + gdb_regs[GDB_FR_MCRH] = regs->mcrh; + gdb_regs[GDB_FR_MCRL] = regs->mcrl; + gdb_regs[GDB_FR_MCVF] = regs->mcvf; + gdb_regs[GDB_FR_DUMMY0] = 0; + gdb_regs[GDB_FR_DUMMY1] = 0; + gdb_regs[GDB_FR_FS0] = 0; +} + +/* + * Extracts kernel SP/PC values understandable by gdb from the values + * saved by switch_to(). + */ +void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p) +{ + gdb_regs[GDB_FR_SSP] = p->thread.sp; + gdb_regs[GDB_FR_PC] = p->thread.pc; + gdb_regs[GDB_FR_A3] = p->thread.a3; + gdb_regs[GDB_FR_USP] = p->thread.usp; + gdb_regs[GDB_FR_FPCR] = p->thread.fpu_state.fpcr; +} + +/* + * Fill kernel exception frame registers from the GDB register file + */ +void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs) +{ + regs->d0 = gdb_regs[GDB_FR_D0]; + regs->d1 = gdb_regs[GDB_FR_D1]; + regs->d2 = gdb_regs[GDB_FR_D2]; + regs->d3 = gdb_regs[GDB_FR_D3]; + regs->a0 = gdb_regs[GDB_FR_A0]; + regs->a1 = gdb_regs[GDB_FR_A1]; + regs->a2 = gdb_regs[GDB_FR_A2]; + regs->a3 = gdb_regs[GDB_FR_A3]; + regs->sp = gdb_regs[GDB_FR_SP]; + regs->pc = gdb_regs[GDB_FR_PC]; + regs->mdr = gdb_regs[GDB_FR_MDR]; + regs->epsw = gdb_regs[GDB_FR_EPSW]; + regs->lir = gdb_regs[GDB_FR_LIR]; + regs->lar = gdb_regs[GDB_FR_LAR]; + regs->mdrq = gdb_regs[GDB_FR_MDRQ]; + regs->e0 = gdb_regs[GDB_FR_E0]; + regs->e1 = gdb_regs[GDB_FR_E1]; + regs->e2 = gdb_regs[GDB_FR_E2]; + regs->e3 = gdb_regs[GDB_FR_E3]; + regs->e4 = gdb_regs[GDB_FR_E4]; + regs->e5 = gdb_regs[GDB_FR_E5]; + regs->e6 = gdb_regs[GDB_FR_E6]; + regs->e7 = gdb_regs[GDB_FR_E7]; + regs->sp = gdb_regs[GDB_FR_SSP]; + /* gdb_regs[GDB_FR_MSP]; */ + // regs->usp = gdb_regs[GDB_FR_USP]; + regs->mcrh = gdb_regs[GDB_FR_MCRH]; + regs->mcrl = gdb_regs[GDB_FR_MCRL]; + regs->mcvf = gdb_regs[GDB_FR_MCVF]; + /* gdb_regs[GDB_FR_DUMMY0]; */ + /* gdb_regs[GDB_FR_DUMMY1]; */ + + // regs->fpcr = gdb_regs[GDB_FR_FPCR]; + // regs->fs0 = gdb_regs[GDB_FR_FS0]; +} + +struct kgdb_arch arch_kgdb_ops = { + .gdb_bpt_instr = { 0xff }, + .flags = KGDB_HW_BREAKPOINT, +}; + +static const unsigned char mn10300_kgdb_insn_sizes[256] = +{ + /* 1 2 3 4 5 6 7 8 9 a b c d e f */ + 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, /* 0 */ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 1 */ + 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, /* 2 */ + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, /* 3 */ + 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, /* 4 */ + 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, /* 5 */ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 6 */ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 7 */ + 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* 8 */ + 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* 9 */ + 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* a */ + 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* b */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 2, /* c */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* d */ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* e */ + 0, 2, 2, 2, 2, 2, 2, 4, 0, 3, 0, 4, 0, 6, 7, 1 /* f */ +}; + +/* + * Attempt to emulate single stepping by means of breakpoint instructions. + * Although there is a single-step trace flag in EPSW, its use is not + * sufficiently documented and is only intended for use with the JTAG debugger. + */ +static int kgdb_arch_do_singlestep(struct pt_regs *regs) +{ + unsigned long arg; + unsigned size; + u8 *pc = (u8 *)regs->pc, *sp = (u8 *)(regs + 1), cur; + u8 *x = NULL, *y = NULL; + int ret; + + ret = probe_kernel_read(&cur, pc, 1); + if (ret < 0) + return ret; + + size = mn10300_kgdb_insn_sizes[cur]; + if (size > 0) { + x = pc + size; + goto set_x; + } + + switch (cur) { + /* Bxx (d8,PC) */ + case 0xc0 ... 0xca: + ret = probe_kernel_read(&arg, pc + 1, 1); + if (ret < 0) + return ret; + x = pc + 2; + if (arg >= 0 && arg <= 2) + goto set_x; + y = pc + (s8)arg; + goto set_x_and_y; + + /* LXX (d8,PC) */ + case 0xd0 ... 0xda: + x = pc + 1; + if (regs->pc == regs->lar) + goto set_x; + y = (u8 *)regs->lar; + goto set_x_and_y; + + /* SETLB - loads the next four bytes into the LIR register + * (which mustn't include a breakpoint instruction) */ + case 0xdb: + x = pc + 5; + goto set_x; + + /* JMP (d16,PC) or CALL (d16,PC) */ + case 0xcc: + case 0xcd: + ret = probe_kernel_read(&arg, pc + 1, 2); + if (ret < 0) + return ret; + x = pc + (s16)arg; + goto set_x; + + /* JMP (d32,PC) or CALL (d32,PC) */ + case 0xdc: + case 0xdd: + ret = probe_kernel_read(&arg, pc + 1, 4); + if (ret < 0) + return ret; + x = pc + (s32)arg; + goto set_x; + + /* RETF */ + case 0xde: + x = (u8 *)regs->mdr; + goto set_x; + + /* RET */ + case 0xdf: + ret = probe_kernel_read(&arg, pc + 2, 1); + if (ret < 0) + return ret; + ret = probe_kernel_read(&x, sp + (s8)arg, 4); + if (ret < 0) + return ret; + goto set_x; + + case 0xf0: + ret = probe_kernel_read(&cur, pc + 1, 1); + if (ret < 0) + return ret; + + if (cur >= 0xf0 && cur <= 0xf7) { + /* JMP (An) / CALLS (An) */ + switch (cur & 3) { + case 0: x = (u8 *)regs->a0; break; + case 1: x = (u8 *)regs->a1; break; + case 2: x = (u8 *)regs->a2; break; + case 3: x = (u8 *)regs->a3; break; + } + goto set_x; + } else if (cur == 0xfc) { + /* RETS */ + ret = probe_kernel_read(&x, sp, 4); + if (ret < 0) + return ret; + goto set_x; + } else if (cur == 0xfd) { + /* RTI */ + ret = probe_kernel_read(&x, sp + 4, 4); + if (ret < 0) + return ret; + goto set_x; + } else { + x = pc + 2; + goto set_x; + } + break; + + /* potential 3-byte conditional branches */ + case 0xf8: + ret = probe_kernel_read(&cur, pc + 1, 1); + if (ret < 0) + return ret; + x = pc + 3; + + if (cur >= 0xe8 && cur <= 0xeb) { + ret = probe_kernel_read(&arg, pc + 2, 1); + if (ret < 0) + return ret; + if (arg >= 0 && arg <= 3) + goto set_x; + y = pc + (s8)arg; + goto set_x_and_y; + } + goto set_x; + + case 0xfa: + ret = probe_kernel_read(&cur, pc + 1, 1); + if (ret < 0) + return ret; + + if (cur == 0xff) { + /* CALLS (d16,PC) */ + ret = probe_kernel_read(&arg, pc + 2, 2); + if (ret < 0) + return ret; + x = pc + (s16)arg; + goto set_x; + } + + x = pc + 4; + goto set_x; + + case 0xfc: + ret = probe_kernel_read(&cur, pc + 1, 1); + if (ret < 0) + return ret; + + if (cur == 0xff) { + /* CALLS (d32,PC) */ + ret = probe_kernel_read(&arg, pc + 2, 4); + if (ret < 0) + return ret; + x = pc + (s32)arg; + goto set_x; + } + + x = pc + 6; + goto set_x; + } + + return 0; + +set_x: + kgdb_sstep_bp_addr[0] = x; + kgdb_sstep_bp_addr[1] = NULL; + ret = probe_kernel_read(&kgdb_sstep_bp[0], x, 1); + if (ret < 0) + return ret; + ret = probe_kernel_write(x, &arch_kgdb_ops.gdb_bpt_instr, 1); + if (ret < 0) + return ret; + kgdb_sstep_thread = current_thread_info(); + debugger_local_cache_flushinv_one(x); + return ret; + +set_x_and_y: + kgdb_sstep_bp_addr[0] = x; + kgdb_sstep_bp_addr[1] = y; + ret = probe_kernel_read(&kgdb_sstep_bp[0], x, 1); + if (ret < 0) + return ret; + ret = probe_kernel_read(&kgdb_sstep_bp[1], y, 1); + if (ret < 0) + return ret; + ret = probe_kernel_write(x, &arch_kgdb_ops.gdb_bpt_instr, 1); + if (ret < 0) + return ret; + ret = probe_kernel_write(y, &arch_kgdb_ops.gdb_bpt_instr, 1); + if (ret < 0) { + probe_kernel_write(kgdb_sstep_bp_addr[0], + &kgdb_sstep_bp[0], 1); + } else { + kgdb_sstep_thread = current_thread_info(); + } + debugger_local_cache_flushinv_one(x); + debugger_local_cache_flushinv_one(y); + return ret; +} + +/* + * Remove emplaced single-step breakpoints, returning true if we hit one of + * them. + */ +static bool kgdb_arch_undo_singlestep(struct pt_regs *regs) +{ + bool hit = false; + u8 *x = kgdb_sstep_bp_addr[0], *y = kgdb_sstep_bp_addr[1]; + u8 opcode; + + if (kgdb_sstep_thread == current_thread_info()) { + if (x) { + if (x == (u8 *)regs->pc) + hit = true; + if (probe_kernel_read(&opcode, x, + 1) < 0 || + opcode != 0xff) + BUG(); + probe_kernel_write(x, &kgdb_sstep_bp[0], 1); + debugger_local_cache_flushinv_one(x); + } + if (y) { + if (y == (u8 *)regs->pc) + hit = true; + if (probe_kernel_read(&opcode, y, + 1) < 0 || + opcode != 0xff) + BUG(); + probe_kernel_write(y, &kgdb_sstep_bp[1], 1); + debugger_local_cache_flushinv_one(y); + } + } + + kgdb_sstep_bp_addr[0] = NULL; + kgdb_sstep_bp_addr[1] = NULL; + kgdb_sstep_thread = NULL; + return hit; +} + +/* + * Catch a single-step-pending thread being deleted and make sure the global + * single-step state is cleared. At this point the breakpoints should have + * been removed by __switch_to(). + */ +void free_thread_info(struct thread_info *ti) +{ + if (kgdb_sstep_thread == ti) { + kgdb_sstep_thread = NULL; + + /* However, we may now be running in degraded mode, with most + * of the CPUs disabled until such a time as KGDB is reentered, + * so force immediate reentry */ + kgdb_breakpoint(); + } + kfree(ti); +} + +/* + * Handle unknown packets and [CcsDk] packets + * - at this point breakpoints have been installed + */ +int kgdb_arch_handle_exception(int vector, int signo, int err_code, + char *remcom_in_buffer, char *remcom_out_buffer, + struct pt_regs *regs) +{ + long addr; + char *ptr; + + switch (remcom_in_buffer[0]) { + case 'c': + case 's': + /* try to read optional parameter, pc unchanged if no parm */ + ptr = &remcom_in_buffer[1]; + if (kgdb_hex2long(&ptr, &addr)) + regs->pc = addr; + case 'D': + case 'k': + atomic_set(&kgdb_cpu_doing_single_step, -1); + + if (remcom_in_buffer[0] == 's') { + kgdb_arch_do_singlestep(regs); + kgdb_single_step = 1; + atomic_set(&kgdb_cpu_doing_single_step, + raw_smp_processor_id()); + } + return 0; + } + return -1; /* this means that we do not want to exit from the handler */ +} + +/* + * Handle event interception + * - returns 0 if the exception should be skipped, -ERROR otherwise. + */ +int debugger_intercept(enum exception_code excep, int signo, int si_code, + struct pt_regs *regs) +{ + int ret; + + if (kgdb_arch_undo_singlestep(regs)) { + excep = EXCEP_TRAP; + signo = SIGTRAP; + si_code = TRAP_TRACE; + } + + ret = kgdb_handle_exception(excep, signo, si_code, regs); + + debugger_local_cache_flushinv(); + + return ret; +} + +/* + * Determine if we've hit a debugger special breakpoint + */ +int at_debugger_breakpoint(struct pt_regs *regs) +{ + return regs->pc == (unsigned long)&__arch_kgdb_breakpoint; +} + +/* + * Initialise kgdb + */ +int kgdb_arch_init(void) +{ + return 0; +} + +/* + * Do something, perhaps, but don't know what. + */ +void kgdb_arch_exit(void) +{ +} + +#ifdef CONFIG_SMP +void debugger_nmi_interrupt(struct pt_regs *regs, enum exception_code code) +{ + kgdb_nmicallback(arch_smp_processor_id(), regs); + debugger_local_cache_flushinv(); +} + +void kgdb_roundup_cpus(unsigned long flags) +{ + smp_jump_to_debugger(); +} +#endif diff --git a/arch/mn10300/kernel/mn10300-serial.c b/arch/mn10300/kernel/mn10300-serial.c index 996384dba45..94901c56baf 100644 --- a/arch/mn10300/kernel/mn10300-serial.c +++ b/arch/mn10300/kernel/mn10300-serial.c @@ -119,6 +119,10 @@ static int mn10300_serial_request_port(struct uart_port *); static void mn10300_serial_config_port(struct uart_port *, int); static int mn10300_serial_verify_port(struct uart_port *, struct serial_struct *); +#ifdef CONFIG_CONSOLE_POLL +static void mn10300_serial_poll_put_char(struct uart_port *, unsigned char); +static int mn10300_serial_poll_get_char(struct uart_port *); +#endif static const struct uart_ops mn10300_serial_ops = { .tx_empty = mn10300_serial_tx_empty, @@ -138,6 +142,10 @@ static const struct uart_ops mn10300_serial_ops = { .request_port = mn10300_serial_request_port, .config_port = mn10300_serial_config_port, .verify_port = mn10300_serial_verify_port, +#ifdef CONFIG_CONSOLE_POLL + .poll_put_char = mn10300_serial_poll_put_char, + .poll_get_char = mn10300_serial_poll_get_char, +#endif }; static irqreturn_t mn10300_serial_interrupt(int irq, void *dev_id); @@ -384,17 +392,21 @@ static void mn10300_serial_mask_ack(unsigned int irq) arch_local_irq_restore(flags); } -static void mn10300_serial_nop(unsigned int irq) +static void mn10300_serial_chip_mask_ack(struct irq_data *d) +{ + mn10300_serial_mask_ack(d->irq); +} + +static void mn10300_serial_nop(struct irq_data *d) { } static struct irq_chip mn10300_serial_pic = { .name = "mnserial", - .ack = mn10300_serial_mask_ack, - .mask = mn10300_serial_mask_ack, - .mask_ack = mn10300_serial_mask_ack, - .unmask = mn10300_serial_nop, - .end = mn10300_serial_nop, + .irq_ack = mn10300_serial_chip_mask_ack, + .irq_mask = mn10300_serial_chip_mask_ack, + .irq_mask_ack = mn10300_serial_chip_mask_ack, + .irq_unmask = mn10300_serial_nop, }; @@ -921,7 +933,7 @@ static int mn10300_serial_startup(struct uart_port *_port) NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL)); set_intr_level(port->tx_irq, NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL)); - set_irq_chip(port->tm_irq, &mn10300_serial_pic); + irq_set_chip(port->tm_irq, &mn10300_serial_pic); if (request_irq(port->rx_irq, mn10300_serial_interrupt, IRQF_DISABLED, port->rx_name, port) < 0) @@ -1630,3 +1642,70 @@ static int __init mn10300_serial_console_init(void) console_initcall(mn10300_serial_console_init); #endif + +#ifdef CONFIG_CONSOLE_POLL +/* + * Polled character reception for the kernel debugger + */ +static int mn10300_serial_poll_get_char(struct uart_port *_port) +{ + struct mn10300_serial_port *port = + container_of(_port, struct mn10300_serial_port, uart); + unsigned ix; + u8 st, ch; + + _enter("%s", port->name); + + do { + /* pull chars out of the hat */ + ix = port->rx_outp; + if (ix == port->rx_inp) + return NO_POLL_CHAR; + + ch = port->rx_buffer[ix++]; + st = port->rx_buffer[ix++]; + smp_rmb(); + port->rx_outp = ix & (MNSC_BUFFER_SIZE - 1); + + } while (st & (SC01STR_FEF | SC01STR_PEF | SC01STR_OEF)); + + return ch; +} + + +/* + * Polled character transmission for the kernel debugger + */ +static void mn10300_serial_poll_put_char(struct uart_port *_port, + unsigned char ch) +{ + struct mn10300_serial_port *port = + container_of(_port, struct mn10300_serial_port, uart); + u8 intr, tmp; + + /* wait for the transmitter to finish anything it might be doing (and + * this includes the virtual DMA handler, so it might take a while) */ + while (*port->_status & (SC01STR_TBF | SC01STR_TXF)) + continue; + + /* disable the Tx ready interrupt */ + intr = *port->_intr; + *port->_intr = intr & ~SC01ICR_TI; + tmp = *port->_intr; + + if (ch == 0x0a) { + *(u8 *) port->_txb = 0x0d; + while (*port->_status & SC01STR_TBF) + continue; + } + + *(u8 *) port->_txb = ch; + while (*port->_status & SC01STR_TBF) + continue; + + /* restore the Tx interrupt flag */ + *port->_intr = intr; + tmp = *port->_intr; +} + +#endif /* CONFIG_CONSOLE_POLL */ diff --git a/arch/mn10300/kernel/process.c b/arch/mn10300/kernel/process.c index e1b14a6ed54..28eec310253 100644 --- a/arch/mn10300/kernel/process.c +++ b/arch/mn10300/kernel/process.c @@ -135,7 +135,7 @@ void release_segments(struct mm_struct *mm) void machine_restart(char *cmd) { -#ifdef CONFIG_GDBSTUB +#ifdef CONFIG_KERNEL_DEBUGGER gdbstub_exit(0); #endif @@ -148,14 +148,14 @@ void machine_restart(char *cmd) void machine_halt(void) { -#ifdef CONFIG_GDBSTUB +#ifdef CONFIG_KERNEL_DEBUGGER gdbstub_exit(0); #endif } void machine_power_off(void) { -#ifdef CONFIG_GDBSTUB +#ifdef CONFIG_KERNEL_DEBUGGER gdbstub_exit(0); #endif } diff --git a/arch/mn10300/kernel/smp.c b/arch/mn10300/kernel/smp.c index 0dcd1c686ba..226c826a219 100644 --- a/arch/mn10300/kernel/smp.c +++ b/arch/mn10300/kernel/smp.c @@ -113,15 +113,17 @@ static void init_ipi(void); */ static void mn10300_ipi_disable(unsigned int irq); static void mn10300_ipi_enable(unsigned int irq); -static void mn10300_ipi_ack(unsigned int irq); -static void mn10300_ipi_nop(unsigned int irq); +static void mn10300_ipi_chip_disable(struct irq_data *d); +static void mn10300_ipi_chip_enable(struct irq_data *d); +static void mn10300_ipi_ack(struct irq_data *d); +static void mn10300_ipi_nop(struct irq_data *d); static struct irq_chip mn10300_ipi_type = { .name = "cpu_ipi", - .disable = mn10300_ipi_disable, - .enable = mn10300_ipi_enable, - .ack = mn10300_ipi_ack, - .eoi = mn10300_ipi_nop + .irq_disable = mn10300_ipi_chip_disable, + .irq_enable = mn10300_ipi_chip_enable, + .irq_ack = mn10300_ipi_ack, + .irq_eoi = mn10300_ipi_nop }; static irqreturn_t smp_reschedule_interrupt(int irq, void *dev_id); @@ -154,15 +156,15 @@ static void init_ipi(void) u16 tmp16; /* set up the reschedule IPI */ - set_irq_chip_and_handler(RESCHEDULE_IPI, - &mn10300_ipi_type, handle_percpu_irq); + irq_set_chip_and_handler(RESCHEDULE_IPI, &mn10300_ipi_type, + handle_percpu_irq); setup_irq(RESCHEDULE_IPI, &reschedule_ipi); set_intr_level(RESCHEDULE_IPI, RESCHEDULE_GxICR_LV); mn10300_ipi_enable(RESCHEDULE_IPI); /* set up the call function IPI */ - set_irq_chip_and_handler(CALL_FUNC_SINGLE_IPI, - &mn10300_ipi_type, handle_percpu_irq); + irq_set_chip_and_handler(CALL_FUNC_SINGLE_IPI, &mn10300_ipi_type, + handle_percpu_irq); setup_irq(CALL_FUNC_SINGLE_IPI, &call_function_ipi); set_intr_level(CALL_FUNC_SINGLE_IPI, CALL_FUNCTION_GxICR_LV); mn10300_ipi_enable(CALL_FUNC_SINGLE_IPI); @@ -170,8 +172,8 @@ static void init_ipi(void) /* set up the local timer IPI */ #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || \ defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) - set_irq_chip_and_handler(LOCAL_TIMER_IPI, - &mn10300_ipi_type, handle_percpu_irq); + irq_set_chip_and_handler(LOCAL_TIMER_IPI, &mn10300_ipi_type, + handle_percpu_irq); setup_irq(LOCAL_TIMER_IPI, &local_timer_ipi); set_intr_level(LOCAL_TIMER_IPI, LOCAL_TIMER_GxICR_LV); mn10300_ipi_enable(LOCAL_TIMER_IPI); @@ -236,6 +238,11 @@ static void mn10300_ipi_enable(unsigned int irq) arch_local_irq_restore(flags); } +static void mn10300_ipi_chip_enable(struct irq_data *d) +{ + mn10300_ipi_enable(d->irq); +} + /** * mn10300_ipi_disable - Disable an IPI * @irq: The IPI to be disabled. @@ -254,6 +261,12 @@ static void mn10300_ipi_disable(unsigned int irq) arch_local_irq_restore(flags); } +static void mn10300_ipi_chip_disable(struct irq_data *d) +{ + mn10300_ipi_disable(d->irq); +} + + /** * mn10300_ipi_ack - Acknowledge an IPI interrupt in the PIC * @irq: The IPI to be acknowledged. @@ -261,8 +274,9 @@ static void mn10300_ipi_disable(unsigned int irq) * Clear the interrupt detection flag for the IPI on the appropriate interrupt * channel in the PIC. */ -static void mn10300_ipi_ack(unsigned int irq) +static void mn10300_ipi_ack(struct irq_data *d) { + unsigned int irq = d->irq; unsigned long flags; u16 tmp; @@ -276,7 +290,7 @@ static void mn10300_ipi_ack(unsigned int irq) * mn10300_ipi_nop - Dummy IPI action * @irq: The IPI to be acted upon. */ -static void mn10300_ipi_nop(unsigned int irq) +static void mn10300_ipi_nop(struct irq_data *d) { } @@ -426,6 +440,22 @@ int smp_nmi_call_function(smp_call_func_t func, void *info, int wait) } /** + * smp_jump_to_debugger - Make other CPUs enter the debugger by sending an IPI + * + * Send a non-maskable request to all other CPUs in the system, instructing + * them to jump into the debugger. The caller is responsible for checking that + * the other CPUs responded to the instruction. + * + * The caller should make sure that this CPU's debugger IPI is disabled. + */ +void smp_jump_to_debugger(void) +{ + if (num_online_cpus() > 1) + /* Send a message to all other CPUs */ + send_IPI_allbutself(DEBUGGER_NMI_IPI); +} + +/** * stop_this_cpu - Callback to stop a CPU. * @unused: Callback context (ignored). */ @@ -589,7 +619,7 @@ static void __init smp_cpu_init(void) /** * smp_prepare_cpu_init - Initialise CPU in startup_secondary * - * Set interrupt level 0-6 setting and init ICR of gdbstub. + * Set interrupt level 0-6 setting and init ICR of the kernel debugger. */ void smp_prepare_cpu_init(void) { @@ -608,15 +638,15 @@ void smp_prepare_cpu_init(void) for (loop = 0; loop < GxICR_NUM_IRQS; loop++) GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; -#ifdef CONFIG_GDBSTUB - /* initialise GDB-stub */ +#ifdef CONFIG_KERNEL_DEBUGGER + /* initialise the kernel debugger interrupt */ do { unsigned long flags; u16 tmp16; flags = arch_local_cli_save(); - GxICR(GDB_NMI_IPI) = GxICR_NMI | GxICR_ENABLE | GxICR_DETECT; - tmp16 = GxICR(GDB_NMI_IPI); + GxICR(DEBUGGER_NMI_IPI) = GxICR_NMI | GxICR_ENABLE | GxICR_DETECT; + tmp16 = GxICR(DEBUGGER_NMI_IPI); arch_local_irq_restore(flags); } while (0); #endif diff --git a/arch/mn10300/kernel/switch_to.S b/arch/mn10300/kernel/switch_to.S index 9074d0fb878..de3e74fc9ea 100644 --- a/arch/mn10300/kernel/switch_to.S +++ b/arch/mn10300/kernel/switch_to.S @@ -39,11 +39,17 @@ ENTRY(__switch_to) # save prev context mov __switch_back,d0 - mov d0,(THREAD_PC,a0) mov sp,a2 mov a2,(THREAD_SP,a0) mov a3,(THREAD_A3,a0) +#ifdef CONFIG_KGDB + btst 0xff,(kgdb_single_step) + bne __switch_to__lift_sstep_bp +__switch_to__continue: +#endif + mov d0,(THREAD_PC,a0) + mov (THREAD_A3,a1),a3 mov (THREAD_SP,a1),a2 @@ -68,3 +74,106 @@ ENTRY(__switch_to) __switch_back: and ~EPSW_NMID,epsw ret [d2,d3,a2,a3,exreg1],32 + +#ifdef CONFIG_KGDB +############################################################################### +# +# Lift the single-step breakpoints when the task being traced is switched out +# A0 = prev +# A1 = next +# +############################################################################### +__switch_to__lift_sstep_bp: + add -12,sp + mov a0,e4 + mov a1,e5 + + # Clear the single-step flag to prevent us coming this way until we get + # switched back in + bclr 0xff,(kgdb_single_step) + + # Remove first breakpoint + mov (kgdb_sstep_bp_addr),a2 + cmp 0,a2 + beq 1f + movbu (kgdb_sstep_bp),d0 + movbu d0,(a2) +#if defined(CONFIG_MN10300_CACHE_FLUSH_ICACHE) || defined(CONFIG_MN10300_CACHE_INV_ICACHE) + mov a2,d0 + mov a2,d1 + add 1,d1 + calls flush_icache_range +#endif +1: + + # Remove second breakpoint + mov (kgdb_sstep_bp_addr+4),a2 + cmp 0,a2 + beq 2f + movbu (kgdb_sstep_bp+1),d0 + movbu d0,(a2) +#if defined(CONFIG_MN10300_CACHE_FLUSH_ICACHE) || defined(CONFIG_MN10300_CACHE_INV_ICACHE) + mov a2,d0 + mov a2,d1 + add 1,d1 + calls flush_icache_range +#endif +2: + + # Change the resumption address and return + mov __switch_back__reinstall_sstep_bp,d0 + mov e4,a0 + mov e5,a1 + add 12,sp + bra __switch_to__continue + +############################################################################### +# +# Reinstall the single-step breakpoints when the task being traced is switched +# back in (A1 points to the new thread_struct). +# +############################################################################### +__switch_back__reinstall_sstep_bp: + add -12,sp + mov a0,e4 # save the return value + mov 0xff,d3 + + # Reinstall first breakpoint + mov (kgdb_sstep_bp_addr),a2 + cmp 0,a2 + beq 1f + movbu (a2),d0 + movbu d0,(kgdb_sstep_bp) + movbu d3,(a2) +#if defined(CONFIG_MN10300_CACHE_FLUSH_ICACHE) || defined(CONFIG_MN10300_CACHE_INV_ICACHE) + mov a2,d0 + mov a2,d1 + add 1,d1 + calls flush_icache_range +#endif +1: + + # Reinstall second breakpoint + mov (kgdb_sstep_bp_addr+4),a2 + cmp 0,a2 + beq 2f + movbu (a2),d0 + movbu d0,(kgdb_sstep_bp+1) + movbu d3,(a2) +#if defined(CONFIG_MN10300_CACHE_FLUSH_ICACHE) || defined(CONFIG_MN10300_CACHE_INV_ICACHE) + mov a2,d0 + mov a2,d1 + add 1,d1 + calls flush_icache_range +#endif +2: + + mov d3,(kgdb_single_step) + + # Restore the return value (the previous thread_struct pointer) + mov e4,a0 + mov a0,d0 + add 12,sp + bra __switch_back + +#endif /* CONFIG_KGDB */ diff --git a/arch/mn10300/kernel/time.c b/arch/mn10300/kernel/time.c index 5b955000626..67c6416a58f 100644 --- a/arch/mn10300/kernel/time.c +++ b/arch/mn10300/kernel/time.c @@ -93,79 +93,6 @@ irqreturn_t local_timer_interrupt(void) return IRQ_HANDLED; } -#ifndef CONFIG_GENERIC_TIME -/* - * advance the kernel's time keeping clocks (xtime and jiffies) - * - we use Timer 0 & 1 cascaded as a clock to nudge us the next time - * there's a need to update - */ -static irqreturn_t timer_interrupt(int irq, void *dev_id) -{ - unsigned tsc, elapse; - irqreturn_t ret; - - while (tsc = get_cycles(), - elapse = tsc - mn10300_last_tsc, /* time elapsed since last - * tick */ - elapse > MN10300_TSC_PER_HZ - ) { - mn10300_last_tsc += MN10300_TSC_PER_HZ; - - /* advance the kernel's time tracking system */ - xtime_update(1); - } - - ret = local_timer_interrupt(); -#ifdef CONFIG_SMP - send_IPI_allbutself(LOCAL_TIMER_IPI); -#endif - return ret; -} - -static struct irqaction timer_irq = { - .handler = timer_interrupt, - .flags = IRQF_DISABLED | IRQF_SHARED | IRQF_TIMER, - .name = "timer", -}; -#endif /* CONFIG_GENERIC_TIME */ - -#ifdef CONFIG_CSRC_MN10300 -void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock) -{ - u64 temp; - u32 shift; - - /* Find a shift value */ - for (shift = 32; shift > 0; shift--) { - temp = (u64) NSEC_PER_SEC << shift; - do_div(temp, clock); - if ((temp >> 32) == 0) - break; - } - cs->shift = shift; - cs->mult = (u32) temp; -} -#endif - -#if CONFIG_CEVT_MN10300 -void __cpuinit clockevent_set_clock(struct clock_event_device *cd, - unsigned int clock) -{ - u64 temp; - u32 shift; - - /* Find a shift value */ - for (shift = 32; shift > 0; shift--) { - temp = (u64) clock << shift; - do_div(temp, NSEC_PER_SEC); - if ((temp >> 32) == 0) - break; - } - cd->shift = shift; - cd->mult = (u32) temp; -} -#endif - /* * initialise the various timers used by the main part of the kernel */ @@ -177,11 +104,7 @@ void __init time_init(void) */ TMPSCNT |= TMPSCNT_ENABLE; -#ifdef CONFIG_GENERIC_TIME init_clocksource(); -#else - startup_timestamp_counter(); -#endif printk(KERN_INFO "timestamp counter I/O clock running at %lu.%02lu" @@ -190,12 +113,7 @@ void __init time_init(void) mn10300_last_tsc = read_timestamp_counter(); -#ifdef CONFIG_GENERIC_CLOCKEVENTS init_clockevents(); -#else - reload_jiffies_counter(MN10300_JC_PER_HZ - 1); - setup_jiffies_interrupt(TMJCIRQ, &timer_irq, CONFIG_TIMER_IRQ_LEVEL); -#endif #ifdef CONFIG_MN10300_WD_TIMER /* start the watchdog timer */ diff --git a/arch/mn10300/kernel/traps.c b/arch/mn10300/kernel/traps.c index b90c3f160c7..f03cb278828 100644 --- a/arch/mn10300/kernel/traps.c +++ b/arch/mn10300/kernel/traps.c @@ -38,8 +38,9 @@ #include <asm/busctl-regs.h> #include <unit/leds.h> #include <asm/fpu.h> -#include <asm/gdb-stub.h> #include <asm/sections.h> +#include <asm/debugger.h> +#include "internal.h" #if (CONFIG_INTERRUPT_VECTOR_BASE & 0xffffff) #error "INTERRUPT_VECTOR_BASE not aligned to 16MiB boundary!" @@ -49,63 +50,169 @@ int kstack_depth_to_print = 24; spinlock_t die_lock = __SPIN_LOCK_UNLOCKED(die_lock); -ATOMIC_NOTIFIER_HEAD(mn10300_die_chain); +struct exception_to_signal_map { + u8 signo; + u32 si_code; +}; + +static const struct exception_to_signal_map exception_to_signal_map[256] = { + /* MMU exceptions */ + [EXCEP_ITLBMISS >> 3] = { 0, 0 }, + [EXCEP_DTLBMISS >> 3] = { 0, 0 }, + [EXCEP_IAERROR >> 3] = { 0, 0 }, + [EXCEP_DAERROR >> 3] = { 0, 0 }, + + /* system exceptions */ + [EXCEP_TRAP >> 3] = { SIGTRAP, TRAP_BRKPT }, + [EXCEP_ISTEP >> 3] = { SIGTRAP, TRAP_TRACE }, /* Monitor */ + [EXCEP_IBREAK >> 3] = { SIGTRAP, TRAP_HWBKPT }, /* Monitor */ + [EXCEP_OBREAK >> 3] = { SIGTRAP, TRAP_HWBKPT }, /* Monitor */ + [EXCEP_PRIVINS >> 3] = { SIGILL, ILL_PRVOPC }, + [EXCEP_UNIMPINS >> 3] = { SIGILL, ILL_ILLOPC }, + [EXCEP_UNIMPEXINS >> 3] = { SIGILL, ILL_ILLOPC }, + [EXCEP_MEMERR >> 3] = { SIGSEGV, SEGV_ACCERR }, + [EXCEP_MISALIGN >> 3] = { SIGBUS, BUS_ADRALN }, + [EXCEP_BUSERROR >> 3] = { SIGBUS, BUS_ADRERR }, + [EXCEP_ILLINSACC >> 3] = { SIGSEGV, SEGV_ACCERR }, + [EXCEP_ILLDATACC >> 3] = { SIGSEGV, SEGV_ACCERR }, + [EXCEP_IOINSACC >> 3] = { SIGSEGV, SEGV_ACCERR }, + [EXCEP_PRIVINSACC >> 3] = { SIGSEGV, SEGV_ACCERR }, /* userspace */ + [EXCEP_PRIVDATACC >> 3] = { SIGSEGV, SEGV_ACCERR }, /* userspace */ + [EXCEP_DATINSACC >> 3] = { SIGSEGV, SEGV_ACCERR }, + [EXCEP_DOUBLE_FAULT >> 3] = { SIGILL, ILL_BADSTK }, + + /* FPU exceptions */ + [EXCEP_FPU_DISABLED >> 3] = { SIGILL, ILL_COPROC }, + [EXCEP_FPU_UNIMPINS >> 3] = { SIGILL, ILL_COPROC }, + [EXCEP_FPU_OPERATION >> 3] = { SIGFPE, FPE_INTDIV }, + + /* interrupts */ + [EXCEP_WDT >> 3] = { SIGALRM, 0 }, + [EXCEP_NMI >> 3] = { SIGQUIT, 0 }, + [EXCEP_IRQ_LEVEL0 >> 3] = { SIGINT, 0 }, + [EXCEP_IRQ_LEVEL1 >> 3] = { 0, 0 }, + [EXCEP_IRQ_LEVEL2 >> 3] = { 0, 0 }, + [EXCEP_IRQ_LEVEL3 >> 3] = { 0, 0 }, + [EXCEP_IRQ_LEVEL4 >> 3] = { 0, 0 }, + [EXCEP_IRQ_LEVEL5 >> 3] = { 0, 0 }, + [EXCEP_IRQ_LEVEL6 >> 3] = { 0, 0 }, + + /* system calls */ + [EXCEP_SYSCALL0 >> 3] = { 0, 0 }, + [EXCEP_SYSCALL1 >> 3] = { SIGILL, ILL_ILLTRP }, + [EXCEP_SYSCALL2 >> 3] = { SIGILL, ILL_ILLTRP }, + [EXCEP_SYSCALL3 >> 3] = { SIGILL, ILL_ILLTRP }, + [EXCEP_SYSCALL4 >> 3] = { SIGILL, ILL_ILLTRP }, + [EXCEP_SYSCALL5 >> 3] = { SIGILL, ILL_ILLTRP }, + [EXCEP_SYSCALL6 >> 3] = { SIGILL, ILL_ILLTRP }, + [EXCEP_SYSCALL7 >> 3] = { SIGILL, ILL_ILLTRP }, + [EXCEP_SYSCALL8 >> 3] = { SIGILL, ILL_ILLTRP }, + [EXCEP_SYSCALL9 >> 3] = { SIGILL, ILL_ILLTRP }, + [EXCEP_SYSCALL10 >> 3] = { SIGILL, ILL_ILLTRP }, + [EXCEP_SYSCALL11 >> 3] = { SIGILL, ILL_ILLTRP }, + [EXCEP_SYSCALL12 >> 3] = { SIGILL, ILL_ILLTRP }, + [EXCEP_SYSCALL13 >> 3] = { SIGILL, ILL_ILLTRP }, + [EXCEP_SYSCALL14 >> 3] = { SIGILL, ILL_ILLTRP }, + [EXCEP_SYSCALL15 >> 3] = { SIGABRT, 0 }, +}; /* - * These constants are for searching for possible module text - * segments. MODULE_RANGE is a guess of how much space is likely - * to be vmalloced. + * Handle kernel exceptions. + * + * See if there's a fixup handler we can force a jump to when an exception + * happens due to something kernel code did */ -#define MODULE_RANGE (8 * 1024 * 1024) - -#define DO_ERROR(signr, prologue, str, name) \ -asmlinkage void name(struct pt_regs *regs, u32 intcode) \ -{ \ - prologue; \ - if (die_if_no_fixup(str, regs, intcode)) \ - return; \ - force_sig(signr, current); \ -} +int die_if_no_fixup(const char *str, struct pt_regs *regs, + enum exception_code code) +{ + u8 opcode; + int signo, si_code; + + if (user_mode(regs)) + return 0; + + peripheral_leds_display_exception(code); + + signo = exception_to_signal_map[code >> 3].signo; + si_code = exception_to_signal_map[code >> 3].si_code; + + switch (code) { + /* see if we can fixup the kernel accessing memory */ + case EXCEP_ITLBMISS: + case EXCEP_DTLBMISS: + case EXCEP_IAERROR: + case EXCEP_DAERROR: + case EXCEP_MEMERR: + case EXCEP_MISALIGN: + case EXCEP_BUSERROR: + case EXCEP_ILLDATACC: + case EXCEP_IOINSACC: + case EXCEP_PRIVINSACC: + case EXCEP_PRIVDATACC: + case EXCEP_DATINSACC: + if (fixup_exception(regs)) + return 1; + break; -#define DO_EINFO(signr, prologue, str, name, sicode) \ -asmlinkage void name(struct pt_regs *regs, u32 intcode) \ -{ \ - siginfo_t info; \ - prologue; \ - if (die_if_no_fixup(str, regs, intcode)) \ - return; \ - info.si_signo = signr; \ - if (signr == SIGILL && sicode == ILL_ILLOPC) { \ - uint8_t opcode; \ - if (get_user(opcode, (uint8_t __user *)regs->pc) == 0) \ - if (opcode == 0xff) \ - info.si_signo = SIGTRAP; \ - } \ - info.si_errno = 0; \ - info.si_code = sicode; \ - info.si_addr = (void *) regs->pc; \ - force_sig_info(info.si_signo, &info, current); \ + case EXCEP_TRAP: + case EXCEP_UNIMPINS: + if (get_user(opcode, (uint8_t __user *)regs->pc) != 0) + break; + if (opcode == 0xff) { + if (notify_die(DIE_BREAKPOINT, str, regs, code, 0, 0)) + return 1; + if (at_debugger_breakpoint(regs)) + regs->pc++; + signo = SIGTRAP; + si_code = TRAP_BRKPT; + } + break; + + case EXCEP_SYSCALL1 ... EXCEP_SYSCALL14: + /* syscall return addr is _after_ the instruction */ + regs->pc -= 2; + break; + + case EXCEP_SYSCALL15: + if (report_bug(regs->pc, regs) == BUG_TRAP_TYPE_WARN) + return 1; + + /* syscall return addr is _after_ the instruction */ + regs->pc -= 2; + break; + + default: + break; + } + + if (debugger_intercept(code, signo, si_code, regs) == 0) + return 1; + + if (notify_die(DIE_GPF, str, regs, code, 0, 0)) + return 1; + + /* make the process die as the last resort */ + die(str, regs, code); } -DO_ERROR(SIGTRAP, {}, "trap", trap); -DO_ERROR(SIGSEGV, {}, "ibreak", ibreak); -DO_ERROR(SIGSEGV, {}, "obreak", obreak); -DO_EINFO(SIGSEGV, {}, "access error", access_error, SEGV_ACCERR); -DO_EINFO(SIGSEGV, {}, "insn access error", insn_acc_error, SEGV_ACCERR); -DO_EINFO(SIGSEGV, {}, "data access error", data_acc_error, SEGV_ACCERR); -DO_EINFO(SIGILL, {}, "privileged opcode", priv_op, ILL_PRVOPC); -DO_EINFO(SIGILL, {}, "invalid opcode", invalid_op, ILL_ILLOPC); -DO_EINFO(SIGILL, {}, "invalid ex opcode", invalid_exop, ILL_ILLOPC); -DO_EINFO(SIGBUS, {}, "invalid address", mem_error, BUS_ADRERR); -DO_EINFO(SIGBUS, {}, "bus error", bus_error, BUS_ADRERR); - -DO_ERROR(SIGTRAP, -#ifndef CONFIG_MN10300_USING_JTAG - DCR &= ~0x0001, -#else - {}, -#endif - "single step", istep); +/* + * General exception handler + */ +asmlinkage void handle_exception(struct pt_regs *regs, u32 intcode) +{ + siginfo_t info; + + /* deal with kernel exceptions here */ + if (die_if_no_fixup(NULL, regs, intcode)) + return; + + /* otherwise it's a userspace exception */ + info.si_signo = exception_to_signal_map[intcode >> 3].signo; + info.si_code = exception_to_signal_map[intcode >> 3].si_code; + info.si_errno = 0; + info.si_addr = (void *) regs->pc; + force_sig_info(info.si_signo, &info, current); +} /* * handle NMI @@ -113,10 +220,8 @@ DO_ERROR(SIGTRAP, asmlinkage void nmi(struct pt_regs *regs, enum exception_code code) { /* see if gdbstub wants to deal with it */ -#ifdef CONFIG_GDBSTUB - if (gdbstub_intercept(regs, code)) + if (debugger_intercept(code, SIGQUIT, 0, regs)) return; -#endif printk(KERN_WARNING "--- Register Dump ---\n"); show_registers(regs); @@ -128,29 +233,36 @@ asmlinkage void nmi(struct pt_regs *regs, enum exception_code code) */ void show_trace(unsigned long *sp) { - unsigned long *stack, addr, module_start, module_end; - int i; - - printk(KERN_EMERG "\nCall Trace:"); - - stack = sp; - i = 0; - module_start = VMALLOC_START; - module_end = VMALLOC_END; + unsigned long bottom, stack, addr, fp, raslot; + + printk(KERN_EMERG "\nCall Trace:\n"); + + //stack = (unsigned long)sp; + asm("mov sp,%0" : "=a"(stack)); + asm("mov a3,%0" : "=r"(fp)); + + raslot = ULONG_MAX; + bottom = (stack + THREAD_SIZE) & ~(THREAD_SIZE - 1); + for (; stack < bottom; stack += sizeof(addr)) { + addr = *(unsigned long *)stack; + if (stack == fp) { + if (addr > stack && addr < bottom) { + fp = addr; + raslot = stack + sizeof(addr); + continue; + } + fp = 0; + raslot = ULONG_MAX; + } - while (((long) stack & (THREAD_SIZE - 1)) != 0) { - addr = *stack++; if (__kernel_text_address(addr)) { -#if 1 printk(" [<%08lx>]", addr); + if (stack >= raslot) + raslot = ULONG_MAX; + else + printk(" ?"); print_symbol(" %s", addr); printk("\n"); -#else - if ((i % 6) == 0) - printk(KERN_EMERG " "); - printk("[<%08lx>] ", addr); - i++; -#endif } } @@ -323,86 +435,6 @@ void die(const char *str, struct pt_regs *regs, enum exception_code code) } /* - * see if there's a fixup handler we can force a jump to when an exception - * happens due to something kernel code did - */ -int die_if_no_fixup(const char *str, struct pt_regs *regs, - enum exception_code code) -{ - if (user_mode(regs)) - return 0; - - peripheral_leds_display_exception(code); - - switch (code) { - /* see if we can fixup the kernel accessing memory */ - case EXCEP_ITLBMISS: - case EXCEP_DTLBMISS: - case EXCEP_IAERROR: - case EXCEP_DAERROR: - case EXCEP_MEMERR: - case EXCEP_MISALIGN: - case EXCEP_BUSERROR: - case EXCEP_ILLDATACC: - case EXCEP_IOINSACC: - case EXCEP_PRIVINSACC: - case EXCEP_PRIVDATACC: - case EXCEP_DATINSACC: - if (fixup_exception(regs)) - return 1; - case EXCEP_UNIMPINS: - if (regs->pc && *(uint8_t *)regs->pc == 0xff) - if (notify_die(DIE_BREAKPOINT, str, regs, code, 0, 0)) - return 1; - break; - default: - break; - } - - /* see if gdbstub wants to deal with it */ -#ifdef CONFIG_GDBSTUB - if (gdbstub_intercept(regs, code)) - return 1; -#endif - - if (notify_die(DIE_GPF, str, regs, code, 0, 0)) - return 1; - - /* make the process die as the last resort */ - die(str, regs, code); -} - -/* - * handle unsupported syscall instructions (syscall 1-15) - */ -static asmlinkage void unsupported_syscall(struct pt_regs *regs, - enum exception_code code) -{ - struct task_struct *tsk = current; - siginfo_t info; - - /* catch a kernel BUG() */ - if (code == EXCEP_SYSCALL15 && !user_mode(regs)) { - if (report_bug(regs->pc, regs) == BUG_TRAP_TYPE_BUG) { -#ifdef CONFIG_GDBSTUB - gdbstub_intercept(regs, code); -#endif - } - } - - regs->pc -= 2; /* syscall return addr is _after_ the instruction */ - - die_if_no_fixup("An unsupported syscall insn was used by the kernel\n", - regs, code); - - info.si_signo = SIGILL; - info.si_errno = ENOSYS; - info.si_code = ILL_ILLTRP; - info.si_addr = (void *) regs->pc; - force_sig_info(SIGILL, &info, tsk); -} - -/* * display the register file when the stack pointer gets clobbered */ asmlinkage void do_double_fault(struct pt_regs *regs) @@ -481,10 +513,8 @@ asmlinkage void uninitialised_exception(struct pt_regs *regs, { /* see if gdbstub wants to deal with it */ -#ifdef CONFIG_GDBSTUB - if (gdbstub_intercept(regs, code)) + if (debugger_intercept(code, SIGSYS, 0, regs) == 0) return; -#endif peripheral_leds_display_exception(code); printk(KERN_EMERG "Uninitialised Exception 0x%04x\n", code & 0xFFFF); @@ -549,43 +579,43 @@ void __init set_intr_stub(enum exception_code code, void *handler) */ void __init trap_init(void) { - set_excp_vector(EXCEP_TRAP, trap); - set_excp_vector(EXCEP_ISTEP, istep); - set_excp_vector(EXCEP_IBREAK, ibreak); - set_excp_vector(EXCEP_OBREAK, obreak); - - set_excp_vector(EXCEP_PRIVINS, priv_op); - set_excp_vector(EXCEP_UNIMPINS, invalid_op); - set_excp_vector(EXCEP_UNIMPEXINS, invalid_exop); - set_excp_vector(EXCEP_MEMERR, mem_error); + set_excp_vector(EXCEP_TRAP, handle_exception); + set_excp_vector(EXCEP_ISTEP, handle_exception); + set_excp_vector(EXCEP_IBREAK, handle_exception); + set_excp_vector(EXCEP_OBREAK, handle_exception); + + set_excp_vector(EXCEP_PRIVINS, handle_exception); + set_excp_vector(EXCEP_UNIMPINS, handle_exception); + set_excp_vector(EXCEP_UNIMPEXINS, handle_exception); + set_excp_vector(EXCEP_MEMERR, handle_exception); set_excp_vector(EXCEP_MISALIGN, misalignment); - set_excp_vector(EXCEP_BUSERROR, bus_error); - set_excp_vector(EXCEP_ILLINSACC, insn_acc_error); - set_excp_vector(EXCEP_ILLDATACC, data_acc_error); - set_excp_vector(EXCEP_IOINSACC, insn_acc_error); - set_excp_vector(EXCEP_PRIVINSACC, insn_acc_error); - set_excp_vector(EXCEP_PRIVDATACC, data_acc_error); - set_excp_vector(EXCEP_DATINSACC, insn_acc_error); - set_excp_vector(EXCEP_FPU_UNIMPINS, fpu_invalid_op); + set_excp_vector(EXCEP_BUSERROR, handle_exception); + set_excp_vector(EXCEP_ILLINSACC, handle_exception); + set_excp_vector(EXCEP_ILLDATACC, handle_exception); + set_excp_vector(EXCEP_IOINSACC, handle_exception); + set_excp_vector(EXCEP_PRIVINSACC, handle_exception); + set_excp_vector(EXCEP_PRIVDATACC, handle_exception); + set_excp_vector(EXCEP_DATINSACC, handle_exception); + set_excp_vector(EXCEP_FPU_UNIMPINS, handle_exception); set_excp_vector(EXCEP_FPU_OPERATION, fpu_exception); set_excp_vector(EXCEP_NMI, nmi); - set_excp_vector(EXCEP_SYSCALL1, unsupported_syscall); - set_excp_vector(EXCEP_SYSCALL2, unsupported_syscall); - set_excp_vector(EXCEP_SYSCALL3, unsupported_syscall); - set_excp_vector(EXCEP_SYSCALL4, unsupported_syscall); - set_excp_vector(EXCEP_SYSCALL5, unsupported_syscall); - set_excp_vector(EXCEP_SYSCALL6, unsupported_syscall); - set_excp_vector(EXCEP_SYSCALL7, unsupported_syscall); - set_excp_vector(EXCEP_SYSCALL8, unsupported_syscall); - set_excp_vector(EXCEP_SYSCALL9, unsupported_syscall); - set_excp_vector(EXCEP_SYSCALL10, unsupported_syscall); - set_excp_vector(EXCEP_SYSCALL11, unsupported_syscall); - set_excp_vector(EXCEP_SYSCALL12, unsupported_syscall); - set_excp_vector(EXCEP_SYSCALL13, unsupported_syscall); - set_excp_vector(EXCEP_SYSCALL14, unsupported_syscall); - set_excp_vector(EXCEP_SYSCALL15, unsupported_syscall); + set_excp_vector(EXCEP_SYSCALL1, handle_exception); + set_excp_vector(EXCEP_SYSCALL2, handle_exception); + set_excp_vector(EXCEP_SYSCALL3, handle_exception); + set_excp_vector(EXCEP_SYSCALL4, handle_exception); + set_excp_vector(EXCEP_SYSCALL5, handle_exception); + set_excp_vector(EXCEP_SYSCALL6, handle_exception); + set_excp_vector(EXCEP_SYSCALL7, handle_exception); + set_excp_vector(EXCEP_SYSCALL8, handle_exception); + set_excp_vector(EXCEP_SYSCALL9, handle_exception); + set_excp_vector(EXCEP_SYSCALL10, handle_exception); + set_excp_vector(EXCEP_SYSCALL11, handle_exception); + set_excp_vector(EXCEP_SYSCALL12, handle_exception); + set_excp_vector(EXCEP_SYSCALL13, handle_exception); + set_excp_vector(EXCEP_SYSCALL14, handle_exception); + set_excp_vector(EXCEP_SYSCALL15, handle_exception); } /* diff --git a/arch/mn10300/mm/Kconfig.cache b/arch/mn10300/mm/Kconfig.cache index c4fd923a55a..bfbe52691f2 100644 --- a/arch/mn10300/mm/Kconfig.cache +++ b/arch/mn10300/mm/Kconfig.cache @@ -99,3 +99,49 @@ config MN10300_CACHE_INV_ICACHE help Set if we need the icache to be invalidated, even if the dcache is in write-through mode and doesn't need flushing. + +# +# The kernel debugger gets its own separate cache flushing functions +# +config MN10300_DEBUGGER_CACHE_FLUSH_BY_TAG + def_bool y if KERNEL_DEBUGGER && \ + MN10300_CACHE_WBACK && \ + !MN10300_CACHE_SNOOP && \ + MN10300_CACHE_MANAGE_BY_TAG + help + Set if the debugger needs to flush the dcache and invalidate the + icache using the cache tag registers to make breakpoints work. + +config MN10300_DEBUGGER_CACHE_FLUSH_BY_REG + def_bool y if KERNEL_DEBUGGER && \ + MN10300_CACHE_WBACK && \ + !MN10300_CACHE_SNOOP && \ + MN10300_CACHE_MANAGE_BY_REG + help + Set if the debugger needs to flush the dcache and invalidate the + icache using automatic purge registers to make breakpoints work. + +config MN10300_DEBUGGER_CACHE_INV_BY_TAG + def_bool y if KERNEL_DEBUGGER && \ + MN10300_CACHE_WTHRU && \ + !MN10300_CACHE_SNOOP && \ + MN10300_CACHE_MANAGE_BY_TAG + help + Set if the debugger needs to invalidate the icache using the cache + tag registers to make breakpoints work. + +config MN10300_DEBUGGER_CACHE_INV_BY_REG + def_bool y if KERNEL_DEBUGGER && \ + MN10300_CACHE_WTHRU && \ + !MN10300_CACHE_SNOOP && \ + MN10300_CACHE_MANAGE_BY_REG + help + Set if the debugger needs to invalidate the icache using automatic + purge registers to make breakpoints work. + +config MN10300_DEBUGGER_CACHE_NO_FLUSH + def_bool y if KERNEL_DEBUGGER && \ + (MN10300_CACHE_DISABLED || MN10300_CACHE_SNOOP) + help + Set if the debugger does not need to flush the dcache and/or + invalidate the icache to make breakpoints work. diff --git a/arch/mn10300/mm/Makefile b/arch/mn10300/mm/Makefile index 203fee23f7d..11f38466ac2 100644 --- a/arch/mn10300/mm/Makefile +++ b/arch/mn10300/mm/Makefile @@ -13,6 +13,15 @@ cacheflush-$(CONFIG_MN10300_CACHE_INV_BY_REG) += cache-inv-by-reg.o cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_BY_TAG) += cache-flush-by-tag.o cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_BY_REG) += cache-flush-by-reg.o +cacheflush-$(CONFIG_MN10300_DEBUGGER_CACHE_FLUSH_BY_TAG) += \ + cache-dbg-flush-by-tag.o cache-dbg-inv-by-tag.o +cacheflush-$(CONFIG_MN10300_DEBUGGER_CACHE_FLUSH_BY_REG) += \ + cache-dbg-flush-by-reg.o +cacheflush-$(CONFIG_MN10300_DEBUGGER_CACHE_INV_BY_TAG) += \ + cache-dbg-inv-by-tag.o cache-dbg-inv.o +cacheflush-$(CONFIG_MN10300_DEBUGGER_CACHE_INV_BY_REG) += \ + cache-dbg-inv-by-reg.o cache-dbg-inv.o + cacheflush-$(CONFIG_MN10300_CACHE_DISABLED) := cache-disabled.o obj-y := \ diff --git a/arch/mn10300/mm/cache-dbg-flush-by-reg.S b/arch/mn10300/mm/cache-dbg-flush-by-reg.S new file mode 100644 index 00000000000..665919f2ab6 --- /dev/null +++ b/arch/mn10300/mm/cache-dbg-flush-by-reg.S @@ -0,0 +1,160 @@ +/* MN10300 CPU cache invalidation routines, using automatic purge registers + * + * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#include <linux/sys.h> +#include <linux/linkage.h> +#include <asm/smp.h> +#include <asm/page.h> +#include <asm/cache.h> +#include <asm/irqflags.h> +#include <asm/cacheflush.h> +#include "cache.inc" + + .am33_2 + +############################################################################### +# +# void debugger_local_cache_flushinv(void) +# Flush the entire data cache back to RAM and invalidate the icache +# +############################################################################### + ALIGN + .globl debugger_local_cache_flushinv + .type debugger_local_cache_flushinv,@function +debugger_local_cache_flushinv: + # + # firstly flush the dcache + # + movhu (CHCTR),d0 + btst CHCTR_DCEN|CHCTR_ICEN,d0 + beq debugger_local_cache_flushinv_end + + mov DCPGCR,a0 + + mov epsw,d1 + and ~EPSW_IE,epsw + or EPSW_NMID,epsw + nop + + btst CHCTR_DCEN,d0 + beq debugger_local_cache_flushinv_no_dcache + + # wait for busy bit of area purge + setlb + mov (a0),d0 + btst DCPGCR_DCPGBSY,d0 + lne + + # set mask + clr d0 + mov d0,(DCPGMR) + + # area purge + # + # DCPGCR = DCPGCR_DCP + # + mov DCPGCR_DCP,d0 + mov d0,(a0) + + # wait for busy bit of area purge + setlb + mov (a0),d0 + btst DCPGCR_DCPGBSY,d0 + lne + +debugger_local_cache_flushinv_no_dcache: + # + # secondly, invalidate the icache if it is enabled + # + mov CHCTR,a0 + movhu (a0),d0 + btst CHCTR_ICEN,d0 + beq debugger_local_cache_flushinv_done + + invalidate_icache 0 + +debugger_local_cache_flushinv_done: + mov d1,epsw + +debugger_local_cache_flushinv_end: + ret [],0 + .size debugger_local_cache_flushinv,.-debugger_local_cache_flushinv + +############################################################################### +# +# void debugger_local_cache_flushinv_one(u8 *addr) +# +# Invalidate one particular cacheline if it's in the icache +# +############################################################################### + ALIGN + .globl debugger_local_cache_flushinv_one + .type debugger_local_cache_flushinv_one,@function +debugger_local_cache_flushinv_one: + movhu (CHCTR),d1 + btst CHCTR_DCEN|CHCTR_ICEN,d1 + beq debugger_local_cache_flushinv_one_end + btst CHCTR_DCEN,d1 + beq debugger_local_cache_flushinv_one_no_dcache + + # round cacheline addr down + and L1_CACHE_TAG_MASK,d0 + mov d0,a1 + mov d0,d1 + + # determine the dcache purge control reg address + mov DCACHE_PURGE(0,0),a0 + and L1_CACHE_TAG_ENTRY,d0 + add d0,a0 + + # retain valid entries in the cache + or L1_CACHE_TAG_VALID,d1 + + # conditionally purge this line in all ways + mov d1,(L1_CACHE_WAYDISP*0,a0) + +debugger_local_cache_flushinv_no_dcache: + # + # now try to flush the icache + # + mov CHCTR,a0 + movhu (a0),d0 + btst CHCTR_ICEN,d0 + beq mn10300_local_icache_inv_range_reg_end + + LOCAL_CLI_SAVE(d1) + + mov ICIVCR,a0 + + # wait for the invalidator to quiesce + setlb + mov (a0),d0 + btst ICIVCR_ICIVBSY,d0 + lne + + # set the mask + mov L1_CACHE_TAG_MASK,d0 + mov d0,(ICIVMR) + + # invalidate the cache line at the given address + or ICIVCR_ICI,a1 + mov a1,(a0) + + # wait for the invalidator to quiesce again + setlb + mov (a0),d0 + btst ICIVCR_ICIVBSY,d0 + lne + + LOCAL_IRQ_RESTORE(d1) + +debugger_local_cache_flushinv_one_end: + ret [],0 + .size debugger_local_cache_flushinv_one,.-debugger_local_cache_flushinv_one diff --git a/arch/mn10300/mm/cache-dbg-flush-by-tag.S b/arch/mn10300/mm/cache-dbg-flush-by-tag.S new file mode 100644 index 00000000000..bf56930e6e7 --- /dev/null +++ b/arch/mn10300/mm/cache-dbg-flush-by-tag.S @@ -0,0 +1,114 @@ +/* MN10300 CPU cache invalidation routines, using direct tag flushing + * + * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#include <linux/sys.h> +#include <linux/linkage.h> +#include <asm/smp.h> +#include <asm/page.h> +#include <asm/cache.h> +#include <asm/irqflags.h> +#include <asm/cacheflush.h> +#include "cache.inc" + + .am33_2 + +############################################################################### +# +# void debugger_local_cache_flushinv(void) +# +# Flush the entire data cache back to RAM and invalidate the icache +# +############################################################################### + ALIGN + .globl debugger_local_cache_flushinv + .type debugger_local_cache_flushinv,@function +debugger_local_cache_flushinv: + # + # firstly flush the dcache + # + movhu (CHCTR),d0 + btst CHCTR_DCEN|CHCTR_ICEN,d0 + beq debugger_local_cache_flushinv_end + + btst CHCTR_DCEN,d0 + beq debugger_local_cache_flushinv_no_dcache + + # read the addresses tagged in the cache's tag RAM and attempt to flush + # those addresses specifically + # - we rely on the hardware to filter out invalid tag entry addresses + mov DCACHE_TAG(0,0),a0 # dcache tag RAM access address + mov DCACHE_PURGE(0,0),a1 # dcache purge request address + mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,e0 # total number of entries + +mn10300_local_dcache_flush_loop: + mov (a0),d0 + and L1_CACHE_TAG_MASK,d0 + or L1_CACHE_TAG_VALID,d0 # retain valid entries in the + # cache + mov d0,(a1) # conditional purge + + add L1_CACHE_BYTES,a0 + add L1_CACHE_BYTES,a1 + add -1,e0 + bne mn10300_local_dcache_flush_loop + +debugger_local_cache_flushinv_no_dcache: + # + # secondly, invalidate the icache if it is enabled + # + mov CHCTR,a0 + movhu (a0),d0 + btst CHCTR_ICEN,d0 + beq debugger_local_cache_flushinv_end + + invalidate_icache 1 + +debugger_local_cache_flushinv_end: + ret [],0 + .size debugger_local_cache_flushinv,.-debugger_local_cache_flushinv + +############################################################################### +# +# void debugger_local_cache_flushinv_one(u8 *addr) +# +# Invalidate one particular cacheline if it's in the icache +# +############################################################################### + ALIGN + .globl debugger_local_cache_flushinv_one + .type debugger_local_cache_flushinv_one,@function +debugger_local_cache_flushinv_one: + movhu (CHCTR),d1 + btst CHCTR_DCEN|CHCTR_ICEN,d1 + beq debugger_local_cache_flushinv_one_end + btst CHCTR_DCEN,d1 + beq debugger_local_cache_flushinv_one_icache + + # round cacheline addr down + and L1_CACHE_TAG_MASK,d0 + mov d0,a1 + + # determine the dcache purge control reg address + mov DCACHE_PURGE(0,0),a0 + and L1_CACHE_TAG_ENTRY,d0 + add d0,a0 + + # retain valid entries in the cache + or L1_CACHE_TAG_VALID,a1 + + # conditionally purge this line in all ways + mov a1,(L1_CACHE_WAYDISP*0,a0) + + # now go and do the icache + bra debugger_local_cache_flushinv_one_icache + +debugger_local_cache_flushinv_one_end: + ret [],0 + .size debugger_local_cache_flushinv_one,.-debugger_local_cache_flushinv_one diff --git a/arch/mn10300/mm/cache-dbg-inv-by-reg.S b/arch/mn10300/mm/cache-dbg-inv-by-reg.S new file mode 100644 index 00000000000..c4e6252941b --- /dev/null +++ b/arch/mn10300/mm/cache-dbg-inv-by-reg.S @@ -0,0 +1,69 @@ +/* MN10300 CPU cache invalidation routines, using automatic purge registers + * + * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#include <linux/sys.h> +#include <linux/linkage.h> +#include <asm/cache.h> +#include <asm/irqflags.h> +#include <asm/cacheflush.h> +#include "cache.inc" + + .am33_2 + + .globl debugger_local_cache_flushinv_one + +############################################################################### +# +# void debugger_local_cache_flushinv_one(u8 *addr) +# +# Invalidate one particular cacheline if it's in the icache +# +############################################################################### + ALIGN + .globl debugger_local_cache_flushinv_one + .type debugger_local_cache_flushinv_one,@function +debugger_local_cache_flushinv_one: + mov d0,a1 + + mov CHCTR,a0 + movhu (a0),d0 + btst CHCTR_ICEN,d0 + beq mn10300_local_icache_inv_range_reg_end + + LOCAL_CLI_SAVE(d1) + + mov ICIVCR,a0 + + # wait for the invalidator to quiesce + setlb + mov (a0),d0 + btst ICIVCR_ICIVBSY,d0 + lne + + # set the mask + mov ~L1_CACHE_TAG_MASK,d0 + mov d0,(ICIVMR) + + # invalidate the cache line at the given address + and ~L1_CACHE_TAG_MASK,a1 + or ICIVCR_ICI,a1 + mov a1,(a0) + + # wait for the invalidator to quiesce again + setlb + mov (a0),d0 + btst ICIVCR_ICIVBSY,d0 + lne + + LOCAL_IRQ_RESTORE(d1) + +mn10300_local_icache_inv_range_reg_end: + ret [],0 + .size debugger_local_cache_flushinv_one,.-debugger_local_cache_flushinv_one diff --git a/arch/mn10300/mm/cache-dbg-inv-by-tag.S b/arch/mn10300/mm/cache-dbg-inv-by-tag.S new file mode 100644 index 00000000000..d8ec821e5f8 --- /dev/null +++ b/arch/mn10300/mm/cache-dbg-inv-by-tag.S @@ -0,0 +1,120 @@ +/* MN10300 CPU cache invalidation routines, using direct tag flushing + * + * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#include <linux/sys.h> +#include <linux/linkage.h> +#include <asm/smp.h> +#include <asm/page.h> +#include <asm/cache.h> +#include <asm/irqflags.h> +#include <asm/cacheflush.h> +#include "cache.inc" + + .am33_2 + + .globl debugger_local_cache_flushinv_one_icache + +############################################################################### +# +# void debugger_local_cache_flushinv_one(u8 *addr) +# +# Invalidate one particular cacheline if it's in the icache +# +############################################################################### + ALIGN + .globl debugger_local_cache_flushinv_one_icache + .type debugger_local_cache_flushinv_one_icache,@function +debugger_local_cache_flushinv_one_icache: + movm [d3,a2],(sp) + + mov CHCTR,a2 + movhu (a2),d0 + btst CHCTR_ICEN,d0 + beq debugger_local_cache_flushinv_one_icache_end + + mov d0,a1 + and L1_CACHE_TAG_MASK,a1 + + # read the tags from the tag RAM, and if they indicate a matching valid + # cache line then we invalidate that line + mov ICACHE_TAG(0,0),a0 + mov a1,d0 + and L1_CACHE_TAG_ENTRY,d0 + add d0,a0 # starting icache tag RAM + # access address + + and ~(L1_CACHE_DISPARITY-1),a1 # determine comparator base + or L1_CACHE_TAG_VALID,a1 + mov L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_VALID,d1 + + LOCAL_CLI_SAVE(d3) + + # disable the icache + movhu (a2),d0 + and ~CHCTR_ICEN,d0 + movhu d0,(a2) + + # and wait for it to calm down + setlb + movhu (a2),d0 + btst CHCTR_ICBUSY,d0 + lne + + # check all the way tags for this cache entry + mov (a0),d0 # read the tag in the way 0 slot + xor a1,d0 + and d1,d0 + beq debugger_local_icache_kill # jump if matched + + add L1_CACHE_WAYDISP,a0 + mov (a0),d0 # read the tag in the way 1 slot + xor a1,d0 + and d1,d0 + beq debugger_local_icache_kill # jump if matched + + add L1_CACHE_WAYDISP,a0 + mov (a0),d0 # read the tag in the way 2 slot + xor a1,d0 + and d1,d0 + beq debugger_local_icache_kill # jump if matched + + add L1_CACHE_WAYDISP,a0 + mov (a0),d0 # read the tag in the way 3 slot + xor a1,d0 + and d1,d0 + bne debugger_local_icache_finish # jump if not matched + +debugger_local_icache_kill: + mov d0,(a0) # kill the tag (D0 is 0 at this point) + +debugger_local_icache_finish: + # wait for the cache to finish what it's doing + setlb + movhu (a2),d0 + btst CHCTR_ICBUSY,d0 + lne + + # and reenable it + or CHCTR_ICEN,d0 + movhu d0,(a2) + movhu (a2),d0 + + # re-enable interrupts + LOCAL_IRQ_RESTORE(d3) + +debugger_local_cache_flushinv_one_icache_end: + ret [d3,a2],8 + .size debugger_local_cache_flushinv_one_icache,.-debugger_local_cache_flushinv_one_icache + +#ifdef CONFIG_MN10300_DEBUGGER_CACHE_INV_BY_TAG + .globl debugger_local_cache_flushinv_one + .type debugger_local_cache_flushinv_one,@function +debugger_local_cache_flushinv_one = debugger_local_cache_flushinv_one_icache +#endif diff --git a/arch/mn10300/mm/cache-dbg-inv.S b/arch/mn10300/mm/cache-dbg-inv.S new file mode 100644 index 00000000000..eba2d6dca06 --- /dev/null +++ b/arch/mn10300/mm/cache-dbg-inv.S @@ -0,0 +1,47 @@ +/* MN10300 CPU cache invalidation routines + * + * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#include <linux/sys.h> +#include <linux/linkage.h> +#include <asm/smp.h> +#include <asm/page.h> +#include <asm/cache.h> +#include <asm/irqflags.h> +#include <asm/cacheflush.h> +#include "cache.inc" + + .am33_2 + + .globl debugger_local_cache_flushinv + +############################################################################### +# +# void debugger_local_cache_flushinv(void) +# +# Invalidate the entire icache +# +############################################################################### + ALIGN + .globl debugger_local_cache_flushinv + .type debugger_local_cache_flushinv,@function +debugger_local_cache_flushinv: + # + # we only need to invalidate the icache in this cache mode + # + mov CHCTR,a0 + movhu (a0),d0 + btst CHCTR_ICEN,d0 + beq debugger_local_cache_flushinv_end + + invalidate_icache 1 + +debugger_local_cache_flushinv_end: + ret [],0 + .size debugger_local_cache_flushinv,.-debugger_local_cache_flushinv diff --git a/arch/mn10300/mm/cache-flush-by-tag.S b/arch/mn10300/mm/cache-flush-by-tag.S index 5cd6a27dd63..1ddc0684924 100644 --- a/arch/mn10300/mm/cache-flush-by-tag.S +++ b/arch/mn10300/mm/cache-flush-by-tag.S @@ -62,7 +62,7 @@ mn10300_local_dcache_flush: mn10300_local_dcache_flush_loop: mov (a0),d0 - and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0 + and L1_CACHE_TAG_MASK,d0 or L1_CACHE_TAG_VALID,d0 # retain valid entries in the # cache mov d0,(a1) # conditional purge @@ -112,11 +112,11 @@ mn10300_local_dcache_flush_range: 1: # round start addr down - and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0 + and L1_CACHE_TAG_MASK,d0 mov d0,a1 add L1_CACHE_BYTES,d1 # round end addr up - and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d1 + and L1_CACHE_TAG_MASK,d1 # write a request to flush all instances of an address from the cache mov DCACHE_PURGE(0,0),a0 @@ -215,12 +215,11 @@ mn10300_local_dcache_flush_inv_range: bra mn10300_local_dcache_flush_inv 1: - and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0 # round start - # addr down + and L1_CACHE_TAG_MASK,d0 # round start addr down mov d0,a1 - add L1_CACHE_BYTES,d1 # round end addr up - and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d1 + add L1_CACHE_BYTES,d1 # round end addr up + and L1_CACHE_TAG_MASK,d1 # write a request to flush and invalidate all instances of an address # from the cache diff --git a/arch/mn10300/mm/cache-inv-by-reg.S b/arch/mn10300/mm/cache-inv-by-reg.S index c8950861ed7..a60825b91e7 100644 --- a/arch/mn10300/mm/cache-inv-by-reg.S +++ b/arch/mn10300/mm/cache-inv-by-reg.S @@ -15,6 +15,7 @@ #include <asm/cache.h> #include <asm/irqflags.h> #include <asm/cacheflush.h> +#include "cache.inc" #define mn10300_local_dcache_inv_range_intr_interval \ +((1 << MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL) - 1) @@ -62,10 +63,7 @@ mn10300_local_icache_inv: btst CHCTR_ICEN,d0 beq mn10300_local_icache_inv_end - # invalidate - or CHCTR_ICINV,d0 - movhu d0,(a0) - movhu (a0),d0 + invalidate_icache 1 mn10300_local_icache_inv_end: ret [],0 @@ -87,11 +85,8 @@ mn10300_local_dcache_inv: btst CHCTR_DCEN,d0 beq mn10300_local_dcache_inv_end - # invalidate - or CHCTR_DCINV,d0 - movhu d0,(a0) - movhu (a0),d0 - + invalidate_dcache 1 + mn10300_local_dcache_inv_end: ret [],0 .size mn10300_local_dcache_inv,.-mn10300_local_dcache_inv @@ -121,9 +116,9 @@ mn10300_local_dcache_inv_range: # and if they're not cacheline-aligned, we must flush any bits outside # the range that share cachelines with stuff inside the range #ifdef CONFIG_MN10300_CACHE_WBACK - btst ~(L1_CACHE_BYTES-1),d0 + btst ~L1_CACHE_TAG_MASK,d0 bne 1f - btst ~(L1_CACHE_BYTES-1),d1 + btst ~L1_CACHE_TAG_MASK,d1 beq 2f 1: bra mn10300_local_dcache_flush_inv_range @@ -141,12 +136,11 @@ mn10300_local_dcache_inv_range: # writeback mode, in which case we would be in flush and invalidate by # now #ifndef CONFIG_MN10300_CACHE_WBACK - and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0 # round start - # addr down + and L1_CACHE_TAG_MASK,d0 # round start addr down mov L1_CACHE_BYTES-1,d2 add d2,d1 - and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d1 # round end addr up + and L1_CACHE_TAG_MASK,d1 # round end addr up #endif /* !CONFIG_MN10300_CACHE_WBACK */ sub d0,d1,d2 # calculate the total size diff --git a/arch/mn10300/mm/cache-inv-by-tag.S b/arch/mn10300/mm/cache-inv-by-tag.S index e9713b40c0f..ccedce9c144 100644 --- a/arch/mn10300/mm/cache-inv-by-tag.S +++ b/arch/mn10300/mm/cache-inv-by-tag.S @@ -15,6 +15,7 @@ #include <asm/cache.h> #include <asm/irqflags.h> #include <asm/cacheflush.h> +#include "cache.inc" #define mn10300_local_dcache_inv_range_intr_interval \ +((1 << MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL) - 1) @@ -70,43 +71,7 @@ mn10300_local_icache_inv: btst CHCTR_ICEN,d0 beq mn10300_local_icache_inv_end -#if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3) - LOCAL_CLI_SAVE(d1) - - # disable the icache - and ~CHCTR_ICEN,d0 - movhu d0,(a0) - - # and wait for it to calm down - setlb - movhu (a0),d0 - btst CHCTR_ICBUSY,d0 - lne - - # invalidate - or CHCTR_ICINV,d0 - movhu d0,(a0) - - # wait for the cache to finish - mov CHCTR,a0 - setlb - movhu (a0),d0 - btst CHCTR_ICBUSY,d0 - lne - - # and reenable it - and ~CHCTR_ICINV,d0 - or CHCTR_ICEN,d0 - movhu d0,(a0) - movhu (a0),d0 - - LOCAL_IRQ_RESTORE(d1) -#else /* CONFIG_AM33_2 || CONFIG_AM33_3 */ - # invalidate - or CHCTR_ICINV,d0 - movhu d0,(a0) - movhu (a0),d0 -#endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */ + invalidate_icache 1 mn10300_local_icache_inv_end: ret [],0 @@ -128,43 +93,7 @@ mn10300_local_dcache_inv: btst CHCTR_DCEN,d0 beq mn10300_local_dcache_inv_end -#if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3) - LOCAL_CLI_SAVE(d1) - - # disable the dcache - and ~CHCTR_DCEN,d0 - movhu d0,(a0) - - # and wait for it to calm down - setlb - movhu (a0),d0 - btst CHCTR_DCBUSY,d0 - lne - - # invalidate - or CHCTR_DCINV,d0 - movhu d0,(a0) - - # wait for the cache to finish - mov CHCTR,a0 - setlb - movhu (a0),d0 - btst CHCTR_DCBUSY,d0 - lne - - # and reenable it - and ~CHCTR_DCINV,d0 - or CHCTR_DCEN,d0 - movhu d0,(a0) - movhu (a0),d0 - - LOCAL_IRQ_RESTORE(d1) -#else /* CONFIG_AM33_2 || CONFIG_AM33_3 */ - # invalidate - or CHCTR_DCINV,d0 - movhu d0,(a0) - movhu (a0),d0 -#endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */ + invalidate_dcache 1 mn10300_local_dcache_inv_end: ret [],0 @@ -195,9 +124,9 @@ mn10300_local_dcache_inv_range: # and if they're not cacheline-aligned, we must flush any bits outside # the range that share cachelines with stuff inside the range #ifdef CONFIG_MN10300_CACHE_WBACK - btst ~(L1_CACHE_BYTES-1),d0 + btst ~L1_CACHE_TAG_MASK,d0 bne 1f - btst ~(L1_CACHE_BYTES-1),d1 + btst ~L1_CACHE_TAG_MASK,d1 beq 2f 1: bra mn10300_local_dcache_flush_inv_range @@ -212,11 +141,10 @@ mn10300_local_dcache_inv_range: beq mn10300_local_dcache_inv_range_end #ifndef CONFIG_MN10300_CACHE_WBACK - and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0 # round start - # addr down + and L1_CACHE_TAG_MASK,d0 # round start addr down add L1_CACHE_BYTES,d1 # round end addr up - and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d1 + and L1_CACHE_TAG_MASK,d1 #endif /* !CONFIG_MN10300_CACHE_WBACK */ mov d0,a1 diff --git a/arch/mn10300/mm/cache.inc b/arch/mn10300/mm/cache.inc new file mode 100644 index 00000000000..394a119b9c7 --- /dev/null +++ b/arch/mn10300/mm/cache.inc @@ -0,0 +1,133 @@ +/* MN10300 CPU core caching macros -*- asm -*- + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + + +############################################################################### +# +# Invalidate the instruction cache. +# A0: Should hold CHCTR +# D0: Should have been read from CHCTR +# D1: Will be clobbered +# +# On some cores it is necessary to disable the icache whilst we do this. +# +############################################################################### + .macro invalidate_icache,disable_irq + +#if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3) + .if \disable_irq + # don't want an interrupt routine seeing a disabled cache + mov epsw,d1 + and ~EPSW_IE,epsw + or EPSW_NMID,epsw + nop + nop + .endif + + # disable the icache + and ~CHCTR_ICEN,d0 + movhu d0,(a0) + + # and wait for it to calm down + setlb + movhu (a0),d0 + btst CHCTR_ICBUSY,d0 + lne + + # invalidate + or CHCTR_ICINV,d0 + movhu d0,(a0) + + # wait for the cache to finish + setlb + movhu (a0),d0 + btst CHCTR_ICBUSY,d0 + lne + + # and reenable it + or CHCTR_ICEN,d0 + movhu d0,(a0) + movhu (a0),d0 + + .if \disable_irq + LOCAL_IRQ_RESTORE(d1) + .endif + +#else /* CONFIG_AM33_2 || CONFIG_AM33_3 */ + + # invalidate + or CHCTR_ICINV,d0 + movhu d0,(a0) + movhu (a0),d0 + +#endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */ + .endm + +############################################################################### +# +# Invalidate the data cache. +# A0: Should hold CHCTR +# D0: Should have been read from CHCTR +# D1: Will be clobbered +# +# On some cores it is necessary to disable the dcache whilst we do this. +# +############################################################################### + .macro invalidate_dcache,disable_irq + +#if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3) + .if \disable_irq + # don't want an interrupt routine seeing a disabled cache + mov epsw,d1 + and ~EPSW_IE,epsw + or EPSW_NMID,epsw + nop + nop + .endif + + # disable the dcache + and ~CHCTR_DCEN,d0 + movhu d0,(a0) + + # and wait for it to calm down + setlb + movhu (a0),d0 + btst CHCTR_DCBUSY,d0 + lne + + # invalidate + or CHCTR_DCINV,d0 + movhu d0,(a0) + + # wait for the cache to finish + setlb + movhu (a0),d0 + btst CHCTR_DCBUSY,d0 + lne + + # and reenable it + or CHCTR_DCEN,d0 + movhu d0,(a0) + movhu (a0),d0 + + .if \disable_irq + LOCAL_IRQ_RESTORE(d1) + .endif + +#else /* CONFIG_AM33_2 || CONFIG_AM33_3 */ + + # invalidate + or CHCTR_DCINV,d0 + movhu d0,(a0) + movhu (a0),d0 + +#endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */ + .endm diff --git a/arch/mn10300/mm/fault.c b/arch/mn10300/mm/fault.c index 59c3da49d9d..0945409a802 100644 --- a/arch/mn10300/mm/fault.c +++ b/arch/mn10300/mm/fault.c @@ -28,8 +28,9 @@ #include <asm/uaccess.h> #include <asm/pgalloc.h> #include <asm/hardirq.h> -#include <asm/gdb-stub.h> #include <asm/cpu-regs.h> +#include <asm/debugger.h> +#include <asm/gdb-stub.h> /* * Unlock any spinlocks which will prevent us from getting the @@ -306,10 +307,8 @@ no_context: printk(" printing pc:\n"); printk(KERN_ALERT "%08lx\n", regs->pc); -#ifdef CONFIG_GDBSTUB - gdbstub_intercept( - regs, fault_code & 0x00010000 ? EXCEP_IAERROR : EXCEP_DAERROR); -#endif + debugger_intercept(fault_code & 0x00010000 ? EXCEP_IAERROR : EXCEP_DAERROR, + SIGSEGV, SEGV_ACCERR, regs); page = PTBR; page = ((unsigned long *) __va(page))[address >> 22]; diff --git a/arch/mn10300/proc-mn103e010/include/proc/cache.h b/arch/mn10300/proc-mn103e010/include/proc/cache.h index c1528004163..967d144f307 100644 --- a/arch/mn10300/proc-mn103e010/include/proc/cache.h +++ b/arch/mn10300/proc-mn103e010/include/proc/cache.h @@ -23,6 +23,7 @@ #define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */ #define L1_CACHE_TAG_ENTRY 0x00000ff0 /* cache tag entry address mask */ #define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */ +#define L1_CACHE_TAG_MASK +(L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY) /* * specification of the interval between interrupt checking intervals whilst diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/cache.h b/arch/mn10300/proc-mn2ws0050/include/proc/cache.h index cafd7b5b55b..bcb5df2d892 100644 --- a/arch/mn10300/proc-mn2ws0050/include/proc/cache.h +++ b/arch/mn10300/proc-mn2ws0050/include/proc/cache.h @@ -29,6 +29,7 @@ #define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */ #define L1_CACHE_TAG_ENTRY 0x00000fe0 /* cache tag entry address mask */ #define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */ +#define L1_CACHE_TAG_MASK +(L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY) /* * specification of the interval between interrupt checking intervals whilst diff --git a/arch/mn10300/unit-asb2364/include/unit/fpga-regs.h b/arch/mn10300/unit-asb2364/include/unit/fpga-regs.h index 7cf12054db6..33f100f9b46 100644 --- a/arch/mn10300/unit-asb2364/include/unit/fpga-regs.h +++ b/arch/mn10300/unit-asb2364/include/unit/fpga-regs.h @@ -14,7 +14,7 @@ #define ASB2364_FPGA_REG_RESET_USB __SYSREG(0xa900130c, u16) #define ASB2364_FPGA_REG_RESET_AV __SYSREG(0xa9001310, u16) -#define ASB2364_FPGA_REG_IRQ(X) __SYSREG(0xa9001590+((X)*4), u16) +#define ASB2364_FPGA_REG_IRQ(X) __SYSREG(0xa9001510+((X)*4), u16) #define ASB2364_FPGA_REG_IRQ_LAN ASB2364_FPGA_REG_IRQ(0) #define ASB2364_FPGA_REG_IRQ_UART ASB2364_FPGA_REG_IRQ(1) #define ASB2364_FPGA_REG_IRQ_I2C ASB2364_FPGA_REG_IRQ(2) diff --git a/arch/mn10300/unit-asb2364/include/unit/serial.h b/arch/mn10300/unit-asb2364/include/unit/serial.h index 7f048bbfdfd..92f224a97ef 100644 --- a/arch/mn10300/unit-asb2364/include/unit/serial.h +++ b/arch/mn10300/unit-asb2364/include/unit/serial.h @@ -59,18 +59,18 @@ static inline void __debug_to_serial(const char *p, int n) #define SERIAL_PORT_DFNS /* stolen by gdb-stub */ #if defined(CONFIG_GDBSTUB_ON_TTYS0) -#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 4, u8) -#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8) -#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8) -#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8) -#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8) -#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8) -#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8) -#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8) -#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8) -#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8) -#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 4, u8) -#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 4, u8) +#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 2, u8) +#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 2, u8) +#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 2, u8) +#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 2, u8) +#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 2, u8) +#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 2, u8) +#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 2, u8) +#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 2, u8) +#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 2, u8) +#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 2, u8) +#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 2, u8) +#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 2, u8) #define GDBPORT_SERIAL_IRQ SERIAL_IRQ #elif defined(CONFIG_GDBSTUB_ON_TTYS1) diff --git a/arch/mn10300/unit-asb2364/irq-fpga.c b/arch/mn10300/unit-asb2364/irq-fpga.c index fcf29754e4d..e16c216f31d 100644 --- a/arch/mn10300/unit-asb2364/irq-fpga.c +++ b/arch/mn10300/unit-asb2364/irq-fpga.c @@ -17,38 +17,38 @@ /* * FPGA PIC operations */ -static void asb2364_fpga_mask(unsigned int irq) +static void asb2364_fpga_mask(struct irq_data *d) { - ASB2364_FPGA_REG_MASK(irq - NR_CPU_IRQS) = 0x0001; + ASB2364_FPGA_REG_MASK(d->irq - NR_CPU_IRQS) = 0x0001; SyncExBus(); } -static void asb2364_fpga_ack(unsigned int irq) +static void asb2364_fpga_ack(struct irq_data *d) { - ASB2364_FPGA_REG_IRQ(irq - NR_CPU_IRQS) = 0x0001; + ASB2364_FPGA_REG_IRQ(d->irq - NR_CPU_IRQS) = 0x0001; SyncExBus(); } -static void asb2364_fpga_mask_ack(unsigned int irq) +static void asb2364_fpga_mask_ack(struct irq_data *d) { - ASB2364_FPGA_REG_MASK(irq - NR_CPU_IRQS) = 0x0001; + ASB2364_FPGA_REG_MASK(d->irq - NR_CPU_IRQS) = 0x0001; SyncExBus(); - ASB2364_FPGA_REG_IRQ(irq - NR_CPU_IRQS) = 0x0001; + ASB2364_FPGA_REG_IRQ(d->irq - NR_CPU_IRQS) = 0x0001; SyncExBus(); } -static void asb2364_fpga_unmask(unsigned int irq) +static void asb2364_fpga_unmask(struct irq_data *d) { - ASB2364_FPGA_REG_MASK(irq - NR_CPU_IRQS) = 0x0000; + ASB2364_FPGA_REG_MASK(d->irq - NR_CPU_IRQS) = 0x0000; SyncExBus(); } static struct irq_chip asb2364_fpga_pic = { .name = "fpga", - .ack = asb2364_fpga_ack, - .mask = asb2364_fpga_mask, - .mask_ack = asb2364_fpga_mask_ack, - .unmask = asb2364_fpga_unmask, + .irq_ack = asb2364_fpga_ack, + .irq_mask = asb2364_fpga_mask, + .irq_mask_ack = asb2364_fpga_mask_ack, + .irq_unmask = asb2364_fpga_unmask, }; /* @@ -88,8 +88,20 @@ void __init irq_fpga_init(void) { int irq; + ASB2364_FPGA_REG_MASK_LAN = 0x0001; + SyncExBus(); + ASB2364_FPGA_REG_MASK_UART = 0x0001; + SyncExBus(); + ASB2364_FPGA_REG_MASK_I2C = 0x0001; + SyncExBus(); + ASB2364_FPGA_REG_MASK_USB = 0x0001; + SyncExBus(); + ASB2364_FPGA_REG_MASK_FPGA = 0x0001; + SyncExBus(); + for (irq = NR_CPU_IRQS; irq < NR_IRQS; irq++) - set_irq_chip_and_handler(irq, &asb2364_fpga_pic, handle_level_irq); + irq_set_chip_and_handler(irq, &asb2364_fpga_pic, + handle_level_irq); /* the FPGA drives the XIRQ1 input on the CPU PIC */ setup_irq(XIRQ1, &fpga_irq[0]); diff --git a/arch/mn10300/unit-asb2364/unit-init.c b/arch/mn10300/unit-asb2364/unit-init.c index 11440803db1..6359b41ce7e 100644 --- a/arch/mn10300/unit-asb2364/unit-init.c +++ b/arch/mn10300/unit-asb2364/unit-init.c @@ -20,13 +20,41 @@ #include <asm/processor.h> #include <asm/irq.h> #include <asm/intctl-regs.h> +#include <asm/serial-regs.h> #include <unit/fpga-regs.h> +#include <unit/serial.h> +#include <unit/smsc911x.h> + +#define TTYS0_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 2, u8) +#define LAN_IRQ_CFG __SYSREG(SMSC911X_BASE + 0x54, u32) +#define LAN_INT_EN __SYSREG(SMSC911X_BASE + 0x5c, u32) /* * initialise some of the unit hardware before gdbstub is set up */ asmlinkage void __init unit_init(void) { + /* Make sure we aren't going to get unexpected interrupts */ + TTYS0_SERIAL_IER = 0; + SC0RXICR = 0; + SC0TXICR = 0; + SC1RXICR = 0; + SC1TXICR = 0; + SC2RXICR = 0; + SC2TXICR = 0; + + /* Attempt to reset the FPGA attached peripherals */ + ASB2364_FPGA_REG_RESET_LAN = 0x0000; + SyncExBus(); + ASB2364_FPGA_REG_RESET_UART = 0x0000; + SyncExBus(); + ASB2364_FPGA_REG_RESET_I2C = 0x0000; + SyncExBus(); + ASB2364_FPGA_REG_RESET_USB = 0x0000; + SyncExBus(); + ASB2364_FPGA_REG_RESET_AV = 0x0000; + SyncExBus(); + /* set up the external interrupts */ /* XIRQ[0]: NAND RXBY */ @@ -56,7 +84,23 @@ asmlinkage void __init unit_init(void) */ asmlinkage void __init unit_setup(void) { + /* Release the reset on the SMSC911X so that it is ready by the time we + * need it */ + ASB2364_FPGA_REG_RESET_LAN = 0x0001; + SyncExBus(); + ASB2364_FPGA_REG_RESET_UART = 0x0001; + SyncExBus(); + ASB2364_FPGA_REG_RESET_I2C = 0x0001; + SyncExBus(); + ASB2364_FPGA_REG_RESET_USB = 0x0001; + SyncExBus(); + ASB2364_FPGA_REG_RESET_AV = 0x0001; + SyncExBus(); + /* Make sure the ethernet chipset isn't going to give us an interrupt + * storm from stuff it was doing pre-reset */ + LAN_IRQ_CFG = 0; + LAN_INT_EN = 0; } /* diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig index fed2946f733..69ff049c857 100644 --- a/arch/parisc/Kconfig +++ b/arch/parisc/Kconfig @@ -51,6 +51,10 @@ config GENERIC_FIND_NEXT_BIT bool default y +config GENERIC_FIND_BIT_LE + bool + default y + config GENERIC_BUG bool default y diff --git a/arch/parisc/include/asm/bitops.h b/arch/parisc/include/asm/bitops.h index 7a6ea10bd23..43c516fa17f 100644 --- a/arch/parisc/include/asm/bitops.h +++ b/arch/parisc/include/asm/bitops.h @@ -222,7 +222,7 @@ static __inline__ int fls(int x) #ifdef __KERNEL__ -#include <asm-generic/bitops/ext2-non-atomic.h> +#include <asm-generic/bitops/le.h> /* '3' is bits per byte */ #define LE_BYTE_ADDR ((sizeof(unsigned long) - 1) << 3) @@ -234,6 +234,4 @@ static __inline__ int fls(int x) #endif /* __KERNEL__ */ -#include <asm-generic/bitops/minix-le.h> - #endif /* _PARISC_BITOPS_H */ diff --git a/arch/parisc/include/asm/cacheflush.h b/arch/parisc/include/asm/cacheflush.h index f388a85bba1..d18328b3f93 100644 --- a/arch/parisc/include/asm/cacheflush.h +++ b/arch/parisc/include/asm/cacheflush.h @@ -26,8 +26,6 @@ void flush_user_dcache_range_asm(unsigned long, unsigned long); void flush_kernel_dcache_range_asm(unsigned long, unsigned long); void flush_kernel_dcache_page_asm(void *); void flush_kernel_icache_page(void *); -void flush_user_dcache_page(unsigned long); -void flush_user_icache_page(unsigned long); void flush_user_dcache_range(unsigned long, unsigned long); void flush_user_icache_range(unsigned long, unsigned long); @@ -37,6 +35,13 @@ void flush_cache_all_local(void); void flush_cache_all(void); void flush_cache_mm(struct mm_struct *mm); +#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE +void flush_kernel_dcache_page_addr(void *addr); +static inline void flush_kernel_dcache_page(struct page *page) +{ + flush_kernel_dcache_page_addr(page_address(page)); +} + #define flush_kernel_dcache_range(start,size) \ flush_kernel_dcache_range_asm((start), (start)+(size)); /* vmap range flushes and invalidates. Architecturally, we don't need @@ -50,6 +55,16 @@ static inline void flush_kernel_vmap_range(void *vaddr, int size) } static inline void invalidate_kernel_vmap_range(void *vaddr, int size) { + unsigned long start = (unsigned long)vaddr; + void *cursor = vaddr; + + for ( ; cursor < vaddr + size; cursor += PAGE_SIZE) { + struct page *page = vmalloc_to_page(cursor); + + if (test_and_clear_bit(PG_dcache_dirty, &page->flags)) + flush_kernel_dcache_page(page); + } + flush_kernel_dcache_range_asm(start, start + size); } #define flush_cache_vmap(start, end) flush_cache_all() @@ -90,19 +105,15 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); +/* defined in pacache.S exported in cache.c used by flush_anon_page */ +void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr); + #define ARCH_HAS_FLUSH_ANON_PAGE static inline void flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr) { if (PageAnon(page)) - flush_user_dcache_page(vmaddr); -} - -#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE -void flush_kernel_dcache_page_addr(void *addr); -static inline void flush_kernel_dcache_page(struct page *page) -{ - flush_kernel_dcache_page_addr(page_address(page)); + flush_dcache_page_asm(page_to_phys(page), vmaddr); } #ifdef CONFIG_DEBUG_RODATA diff --git a/arch/parisc/include/asm/eisa_eeprom.h b/arch/parisc/include/asm/eisa_eeprom.h index 9c9da980402..8ce8b85ca58 100644 --- a/arch/parisc/include/asm/eisa_eeprom.h +++ b/arch/parisc/include/asm/eisa_eeprom.h @@ -27,7 +27,7 @@ struct eeprom_header u_int8_t ver_maj; u_int8_t ver_min; u_int8_t num_slots; /* number of EISA slots in system */ - u_int16_t csum; /* checksum, I don't know how to calulate this */ + u_int16_t csum; /* checksum, I don't know how to calculate this */ u_int8_t pad[10]; } __attribute__ ((packed)); diff --git a/arch/parisc/include/asm/irq.h b/arch/parisc/include/asm/irq.h index c67dccf2e31..1073599a7be 100644 --- a/arch/parisc/include/asm/irq.h +++ b/arch/parisc/include/asm/irq.h @@ -32,15 +32,10 @@ static __inline__ int irq_canonicalize(int irq) } struct irq_chip; +struct irq_data; -/* - * Some useful "we don't have to do anything here" handlers. Should - * probably be provided by the generic code. - */ -void no_ack_irq(unsigned int irq); -void no_end_irq(unsigned int irq); -void cpu_ack_irq(unsigned int irq); -void cpu_eoi_irq(unsigned int irq); +void cpu_ack_irq(struct irq_data *d); +void cpu_eoi_irq(struct irq_data *d); extern int txn_alloc_irq(unsigned int nbits); extern int txn_claim_irq(int); @@ -49,7 +44,7 @@ extern unsigned long txn_alloc_addr(unsigned int); extern unsigned long txn_affinity_addr(unsigned int irq, int cpu); extern int cpu_claim_irq(unsigned int irq, struct irq_chip *, void *); -extern int cpu_check_affinity(unsigned int irq, const struct cpumask *dest); +extern int cpu_check_affinity(struct irq_data *d, const struct cpumask *dest); /* soft power switch support (power.c) */ extern struct tasklet_struct power_tasklet; diff --git a/arch/parisc/include/asm/pgtable.h b/arch/parisc/include/asm/pgtable.h index 6f1f65d3c0e..5d7b8ce9fdf 100644 --- a/arch/parisc/include/asm/pgtable.h +++ b/arch/parisc/include/asm/pgtable.h @@ -138,8 +138,7 @@ struct vm_area_struct; #define _PAGE_NO_CACHE_BIT 24 /* (0x080) Uncached Page (U bit) */ #define _PAGE_ACCESSED_BIT 23 /* (0x100) Software: Page Accessed */ #define _PAGE_PRESENT_BIT 22 /* (0x200) Software: translation valid */ -#define _PAGE_FLUSH_BIT 21 /* (0x400) Software: translation valid */ - /* for cache flushing only */ +/* bit 21 was formerly the FLUSH bit but is now unused */ #define _PAGE_USER_BIT 20 /* (0x800) Software: User accessible page */ /* N.B. The bits are defined in terms of a 32 bit word above, so the */ @@ -173,7 +172,6 @@ struct vm_area_struct; #define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT)) #define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT)) #define _PAGE_PRESENT (1 << xlate_pabit(_PAGE_PRESENT_BIT)) -#define _PAGE_FLUSH (1 << xlate_pabit(_PAGE_FLUSH_BIT)) #define _PAGE_USER (1 << xlate_pabit(_PAGE_USER_BIT)) #define _PAGE_FILE (1 << xlate_pabit(_PAGE_FILE_BIT)) @@ -213,7 +211,6 @@ struct vm_area_struct; #define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE) #define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE) #define PAGE_GATEWAY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_GATEWAY| _PAGE_READ) -#define PAGE_FLUSH __pgprot(_PAGE_FLUSH) /* @@ -261,7 +258,7 @@ extern unsigned long *empty_zero_page; #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) -#define pte_none(x) ((pte_val(x) == 0) || (pte_val(x) & _PAGE_FLUSH)) +#define pte_none(x) (pte_val(x) == 0) #define pte_present(x) (pte_val(x) & _PAGE_PRESENT) #define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0) @@ -444,13 +441,10 @@ struct mm_struct; static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { pte_t old_pte; - pte_t pte; spin_lock(&pa_dbit_lock); - pte = old_pte = *ptep; - pte_val(pte) &= ~_PAGE_PRESENT; - pte_val(pte) |= _PAGE_FLUSH; - set_pte_at(mm,addr,ptep,pte); + old_pte = *ptep; + pte_clear(mm,addr,ptep); spin_unlock(&pa_dbit_lock); return old_pte; diff --git a/arch/parisc/include/asm/types.h b/arch/parisc/include/asm/types.h index 20135cc8003..80e415c9936 100644 --- a/arch/parisc/include/asm/types.h +++ b/arch/parisc/include/asm/types.h @@ -9,20 +9,4 @@ typedef unsigned short umode_t; #endif /* __ASSEMBLY__ */ -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; -typedef u64 dma64_addr_t; - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - #endif diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c index d054f3da3ff..3f11331c277 100644 --- a/arch/parisc/kernel/cache.c +++ b/arch/parisc/kernel/cache.c @@ -27,12 +27,17 @@ #include <asm/pgalloc.h> #include <asm/processor.h> #include <asm/sections.h> +#include <asm/shmparam.h> int split_tlb __read_mostly; int dcache_stride __read_mostly; int icache_stride __read_mostly; EXPORT_SYMBOL(dcache_stride); +void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr); +EXPORT_SYMBOL(flush_dcache_page_asm); +void flush_icache_page_asm(unsigned long phys_addr, unsigned long vaddr); + /* On some machines (e.g. ones with the Merced bus), there can be * only a single PxTLB broadcast at a time; this must be guaranteed @@ -259,81 +264,13 @@ void disable_sr_hashing(void) panic("SpaceID hashing is still on!\n"); } -/* Simple function to work out if we have an existing address translation - * for a user space vma. */ -static inline int translation_exists(struct vm_area_struct *vma, - unsigned long addr, unsigned long pfn) -{ - pgd_t *pgd = pgd_offset(vma->vm_mm, addr); - pmd_t *pmd; - pte_t pte; - - if(pgd_none(*pgd)) - return 0; - - pmd = pmd_offset(pgd, addr); - if(pmd_none(*pmd) || pmd_bad(*pmd)) - return 0; - - /* We cannot take the pte lock here: flush_cache_page is usually - * called with pte lock already held. Whereas flush_dcache_page - * takes flush_dcache_mmap_lock, which is lower in the hierarchy: - * the vma itself is secure, but the pte might come or go racily. - */ - pte = *pte_offset_map(pmd, addr); - /* But pte_unmap() does nothing on this architecture */ - - /* Filter out coincidental file entries and swap entries */ - if (!(pte_val(pte) & (_PAGE_FLUSH|_PAGE_PRESENT))) - return 0; - - return pte_pfn(pte) == pfn; -} - -/* Private function to flush a page from the cache of a non-current - * process. cr25 contains the Page Directory of the current user - * process; we're going to hijack both it and the user space %sr3 to - * temporarily make the non-current process current. We have to do - * this because cache flushing may cause a non-access tlb miss which - * the handlers have to fill in from the pgd of the non-current - * process. */ static inline void -flush_user_cache_page_non_current(struct vm_area_struct *vma, - unsigned long vmaddr) +__flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, + unsigned long physaddr) { - /* save the current process space and pgd */ - unsigned long space = mfsp(3), pgd = mfctl(25); - - /* we don't mind taking interrupts since they may not - * do anything with user space, but we can't - * be preempted here */ - preempt_disable(); - - /* make us current */ - mtctl(__pa(vma->vm_mm->pgd), 25); - mtsp(vma->vm_mm->context, 3); - - flush_user_dcache_page(vmaddr); - if(vma->vm_flags & VM_EXEC) - flush_user_icache_page(vmaddr); - - /* put the old current process back */ - mtsp(space, 3); - mtctl(pgd, 25); - preempt_enable(); -} - - -static inline void -__flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr) -{ - if (likely(vma->vm_mm->context == mfsp(3))) { - flush_user_dcache_page(vmaddr); - if (vma->vm_flags & VM_EXEC) - flush_user_icache_page(vmaddr); - } else { - flush_user_cache_page_non_current(vma, vmaddr); - } + flush_dcache_page_asm(physaddr, vmaddr); + if (vma->vm_flags & VM_EXEC) + flush_icache_page_asm(physaddr, vmaddr); } void flush_dcache_page(struct page *page) @@ -342,10 +279,8 @@ void flush_dcache_page(struct page *page) struct vm_area_struct *mpnt; struct prio_tree_iter iter; unsigned long offset; - unsigned long addr; + unsigned long addr, old_addr = 0; pgoff_t pgoff; - unsigned long pfn = page_to_pfn(page); - if (mapping && !mapping_mapped(mapping)) { set_bit(PG_dcache_dirty, &page->flags); @@ -369,20 +304,11 @@ void flush_dcache_page(struct page *page) offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT; addr = mpnt->vm_start + offset; - /* Flush instructions produce non access tlb misses. - * On PA, we nullify these instructions rather than - * taking a page fault if the pte doesn't exist. - * This is just for speed. If the page translation - * isn't there, there's no point exciting the - * nadtlb handler into a nullification frenzy. - * - * Make sure we really have this page: the private - * mappings may cover this area but have COW'd this - * particular page. - */ - if (translation_exists(mpnt, addr, pfn)) { - __flush_cache_page(mpnt, addr); - break; + if (old_addr == 0 || (old_addr & (SHMLBA - 1)) != (addr & (SHMLBA - 1))) { + __flush_cache_page(mpnt, addr, page_to_phys(page)); + if (old_addr) + printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %s\n", old_addr, addr, mpnt->vm_file ? mpnt->vm_file->f_path.dentry->d_name.name : "(null)"); + old_addr = addr; } } flush_dcache_mmap_unlock(mapping); @@ -573,7 +499,6 @@ flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long { BUG_ON(!vma->vm_mm->context); - if (likely(translation_exists(vma, vmaddr, pfn))) - __flush_cache_page(vma, vmaddr); + __flush_cache_page(vma, vmaddr, page_to_phys(pfn_to_page(pfn))); } diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S index 6337adef30f..ead8d2a1034 100644 --- a/arch/parisc/kernel/entry.S +++ b/arch/parisc/kernel/entry.S @@ -187,8 +187,8 @@ /* Register definitions for tlb miss handler macros */ - va = r8 /* virtual address for which the trap occured */ - spc = r24 /* space for which the trap occured */ + va = r8 /* virtual address for which the trap occurred */ + spc = r24 /* space for which the trap occurred */ #ifndef CONFIG_64BIT @@ -225,22 +225,13 @@ #ifndef CONFIG_64BIT /* * naitlb miss interruption handler (parisc 1.1 - 32 bit) - * - * Note: naitlb misses will be treated - * as an ordinary itlb miss for now. - * However, note that naitlb misses - * have the faulting address in the - * IOR/ISR. */ .macro naitlb_11 code mfctl %isr,spc - b itlb_miss_11 + b naitlb_miss_11 mfctl %ior,va - /* FIXME: If user causes a naitlb miss, the priv level may not be in - * lower bits of va, where the itlb miss handler is expecting them - */ .align 32 .endm @@ -248,26 +239,17 @@ /* * naitlb miss interruption handler (parisc 2.0) - * - * Note: naitlb misses will be treated - * as an ordinary itlb miss for now. - * However, note that naitlb misses - * have the faulting address in the - * IOR/ISR. */ .macro naitlb_20 code mfctl %isr,spc #ifdef CONFIG_64BIT - b itlb_miss_20w + b naitlb_miss_20w #else - b itlb_miss_20 + b naitlb_miss_20 #endif mfctl %ior,va - /* FIXME: If user causes a naitlb miss, the priv level may not be in - * lower bits of va, where the itlb miss handler is expecting them - */ .align 32 .endm @@ -581,7 +563,24 @@ copy \va,\tmp1 depi 0,31,23,\tmp1 cmpb,COND(<>),n \tmp,\tmp1,\fault - ldi (_PAGE_DIRTY|_PAGE_WRITE|_PAGE_READ),\prot + mfctl %cr19,\tmp /* iir */ + /* get the opcode (first six bits) into \tmp */ + extrw,u \tmp,5,6,\tmp + /* + * Only setting the T bit prevents data cache movein + * Setting access rights to zero prevents instruction cache movein + * + * Note subtlety here: _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE go + * to type field and _PAGE_READ goes to top bit of PL1 + */ + ldi (_PAGE_REFTRAP|_PAGE_READ|_PAGE_WRITE),\prot + /* + * so if the opcode is one (i.e. this is a memory management + * instruction) nullify the next load so \prot is only T. + * Otherwise this is a normal data operation + */ + cmpiclr,= 0x01,\tmp,%r0 + ldi (_PAGE_DIRTY|_PAGE_READ|_PAGE_WRITE),\prot depd,z \prot,8,7,\prot /* * OK, it is in the temp alias region, check whether "from" or "to". @@ -631,11 +630,7 @@ ENTRY(fault_vector_20) def 13 def 14 dtlb_20 15 -#if 0 naitlb_20 16 -#else - def 16 -#endif nadtlb_20 17 def 18 def 19 @@ -678,11 +673,7 @@ ENTRY(fault_vector_11) def 13 def 14 dtlb_11 15 -#if 0 naitlb_11 16 -#else - def 16 -#endif nadtlb_11 17 def 18 def 19 @@ -891,7 +882,7 @@ ENTRY(syscall_exit_rfi) * (we don't store them in the sigcontext), so set them * to "proper" values now (otherwise we'll wind up restoring * whatever was last stored in the task structure, which might - * be inconsistent if an interrupt occured while on the gateway + * be inconsistent if an interrupt occurred while on the gateway * page). Note that we may be "trashing" values the user put in * them, but we don't support the user changing them. */ @@ -1165,11 +1156,11 @@ ENDPROC(intr_save) */ t0 = r1 /* temporary register 0 */ - va = r8 /* virtual address for which the trap occured */ + va = r8 /* virtual address for which the trap occurred */ t1 = r9 /* temporary register 1 */ pte = r16 /* pte/phys page # */ prot = r17 /* prot bits */ - spc = r24 /* space for which the trap occured */ + spc = r24 /* space for which the trap occurred */ ptp = r25 /* page directory/page table pointer */ #ifdef CONFIG_64BIT @@ -1203,7 +1194,7 @@ nadtlb_miss_20w: get_pgd spc,ptp space_check spc,t0,nadtlb_fault - L3_ptep ptp,pte,t0,va,nadtlb_check_flush_20w + L3_ptep ptp,pte,t0,va,nadtlb_check_alias_20w update_ptep ptp,pte,t0,t1 @@ -1214,16 +1205,8 @@ nadtlb_miss_20w: rfir nop -nadtlb_check_flush_20w: - bb,>=,n pte,_PAGE_FLUSH_BIT,nadtlb_emulate - - /* Insert a "flush only" translation */ - - depdi,z 7,7,3,prot - depdi 1,10,1,prot - - /* Drop prot bits from pte and convert to page addr for idtlbt */ - convert_for_tlb_insert20 pte +nadtlb_check_alias_20w: + do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate idtlbt pte,prot @@ -1255,25 +1238,7 @@ dtlb_miss_11: nop dtlb_check_alias_11: - - /* Check to see if fault is in the temporary alias region */ - - cmpib,<>,n 0,spc,dtlb_fault /* forward */ - ldil L%(TMPALIAS_MAP_START),t0 - copy va,t1 - depwi 0,31,23,t1 - cmpb,<>,n t0,t1,dtlb_fault /* forward */ - ldi (_PAGE_DIRTY|_PAGE_WRITE|_PAGE_READ),prot - depw,z prot,8,7,prot - - /* - * OK, it is in the temp alias region, check whether "from" or "to". - * Check "subtle" note in pacache.S re: r23/r26. - */ - - extrw,u,= va,9,1,r0 - or,tr %r23,%r0,pte /* If "from" use "from" page */ - or %r26,%r0,pte /* else "to", use "to" page */ + do_alias spc,t0,t1,va,pte,prot,dtlb_fault idtlba pte,(va) idtlbp prot,(va) @@ -1286,7 +1251,7 @@ nadtlb_miss_11: space_check spc,t0,nadtlb_fault - L2_ptep ptp,pte,t0,va,nadtlb_check_flush_11 + L2_ptep ptp,pte,t0,va,nadtlb_check_alias_11 update_ptep ptp,pte,t0,t1 @@ -1304,26 +1269,11 @@ nadtlb_miss_11: rfir nop -nadtlb_check_flush_11: - bb,>=,n pte,_PAGE_FLUSH_BIT,nadtlb_emulate - - /* Insert a "flush only" translation */ - - zdepi 7,7,3,prot - depi 1,10,1,prot +nadtlb_check_alias_11: + do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate - /* Get rid of prot bits and convert to page addr for idtlba */ - - depi 0,31,ASM_PFN_PTE_SHIFT,pte - SHRREG pte,(ASM_PFN_PTE_SHIFT-(31-26)),pte - - mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */ - mtsp spc,%sr1 - - idtlba pte,(%sr1,va) - idtlbp prot,(%sr1,va) - - mtsp t0, %sr1 /* Restore sr1 */ + idtlba pte,(va) + idtlbp prot,(va) rfir nop @@ -1359,7 +1309,7 @@ nadtlb_miss_20: space_check spc,t0,nadtlb_fault - L2_ptep ptp,pte,t0,va,nadtlb_check_flush_20 + L2_ptep ptp,pte,t0,va,nadtlb_check_alias_20 update_ptep ptp,pte,t0,t1 @@ -1372,21 +1322,14 @@ nadtlb_miss_20: rfir nop -nadtlb_check_flush_20: - bb,>=,n pte,_PAGE_FLUSH_BIT,nadtlb_emulate - - /* Insert a "flush only" translation */ - - depdi,z 7,7,3,prot - depdi 1,10,1,prot - - /* Drop prot bits from pte and convert to page addr for idtlbt */ - convert_for_tlb_insert20 pte +nadtlb_check_alias_20: + do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate idtlbt pte,prot rfir nop + #endif nadtlb_emulate: @@ -1484,6 +1427,36 @@ itlb_miss_20w: rfir nop +naitlb_miss_20w: + + /* + * I miss is a little different, since we allow users to fault + * on the gateway page which is in the kernel address space. + */ + + space_adjust spc,va,t0 + get_pgd spc,ptp + space_check spc,t0,naitlb_fault + + L3_ptep ptp,pte,t0,va,naitlb_check_alias_20w + + update_ptep ptp,pte,t0,t1 + + make_insert_tlb spc,pte,prot + + iitlbt pte,prot + + rfir + nop + +naitlb_check_alias_20w: + do_alias spc,t0,t1,va,pte,prot,naitlb_fault + + iitlbt pte,prot + + rfir + nop + #else itlb_miss_11: @@ -1508,6 +1481,38 @@ itlb_miss_11: rfir nop +naitlb_miss_11: + get_pgd spc,ptp + + space_check spc,t0,naitlb_fault + + L2_ptep ptp,pte,t0,va,naitlb_check_alias_11 + + update_ptep ptp,pte,t0,t1 + + make_insert_tlb_11 spc,pte,prot + + mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */ + mtsp spc,%sr1 + + iitlba pte,(%sr1,va) + iitlbp prot,(%sr1,va) + + mtsp t0, %sr1 /* Restore sr1 */ + + rfir + nop + +naitlb_check_alias_11: + do_alias spc,t0,t1,va,pte,prot,itlb_fault + + iitlba pte,(%sr0, va) + iitlbp prot,(%sr0, va) + + rfir + nop + + itlb_miss_20: get_pgd spc,ptp @@ -1526,6 +1531,32 @@ itlb_miss_20: rfir nop +naitlb_miss_20: + get_pgd spc,ptp + + space_check spc,t0,naitlb_fault + + L2_ptep ptp,pte,t0,va,naitlb_check_alias_20 + + update_ptep ptp,pte,t0,t1 + + make_insert_tlb spc,pte,prot + + f_extend pte,t0 + + iitlbt pte,prot + + rfir + nop + +naitlb_check_alias_20: + do_alias spc,t0,t1,va,pte,prot,naitlb_fault + + iitlbt pte,prot + + rfir + nop + #endif #ifdef CONFIG_64BIT @@ -1662,6 +1693,10 @@ nadtlb_fault: b intr_save ldi 17,%r8 +naitlb_fault: + b intr_save + ldi 16,%r8 + dtlb_fault: b intr_save ldi 15,%r8 diff --git a/arch/parisc/kernel/head.S b/arch/parisc/kernel/head.S index 4dbdf0ed6fa..145c5e4caaa 100644 --- a/arch/parisc/kernel/head.S +++ b/arch/parisc/kernel/head.S @@ -131,7 +131,7 @@ $pgt_fill_loop: ldo THREAD_SZ_ALGN(%r6),%sp #ifdef CONFIG_SMP - /* Set the smp rendevous address into page zero. + /* Set the smp rendezvous address into page zero. ** It would be safer to do this in init_smp_config() but ** it's just way easier to deal with here because ** of 64-bit function ptrs and the address is local to this file. diff --git a/arch/parisc/kernel/inventory.c b/arch/parisc/kernel/inventory.c index d228d823787..08324aac354 100644 --- a/arch/parisc/kernel/inventory.c +++ b/arch/parisc/kernel/inventory.c @@ -93,7 +93,7 @@ void __init setup_pdc(void) case 0x6: /* 705, 710 */ case 0x7: /* 715, 725 */ case 0x8: /* 745, 747, 742 */ - case 0xA: /* 712 and similiar */ + case 0xA: /* 712 and similar */ case 0xC: /* 715/64, at least */ pdc_type = PDC_TYPE_SNAKE; diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c index d7d94b845dc..c0b1affc06a 100644 --- a/arch/parisc/kernel/irq.c +++ b/arch/parisc/kernel/irq.c @@ -52,9 +52,9 @@ static volatile unsigned long cpu_eiem = 0; */ static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL; -static void cpu_mask_irq(unsigned int irq) +static void cpu_mask_irq(struct irq_data *d) { - unsigned long eirr_bit = EIEM_MASK(irq); + unsigned long eirr_bit = EIEM_MASK(d->irq); cpu_eiem &= ~eirr_bit; /* Do nothing on the other CPUs. If they get this interrupt, @@ -63,7 +63,7 @@ static void cpu_mask_irq(unsigned int irq) * then gets disabled */ } -static void cpu_unmask_irq(unsigned int irq) +static void __cpu_unmask_irq(unsigned int irq) { unsigned long eirr_bit = EIEM_MASK(irq); @@ -75,9 +75,14 @@ static void cpu_unmask_irq(unsigned int irq) smp_send_all_nop(); } -void cpu_ack_irq(unsigned int irq) +static void cpu_unmask_irq(struct irq_data *d) { - unsigned long mask = EIEM_MASK(irq); + __cpu_unmask_irq(d->irq); +} + +void cpu_ack_irq(struct irq_data *d) +{ + unsigned long mask = EIEM_MASK(d->irq); int cpu = smp_processor_id(); /* Clear in EIEM so we can no longer process */ @@ -90,9 +95,9 @@ void cpu_ack_irq(unsigned int irq) mtctl(mask, 23); } -void cpu_eoi_irq(unsigned int irq) +void cpu_eoi_irq(struct irq_data *d) { - unsigned long mask = EIEM_MASK(irq); + unsigned long mask = EIEM_MASK(d->irq); int cpu = smp_processor_id(); /* set it in the eiems---it's no longer in process */ @@ -103,17 +108,13 @@ void cpu_eoi_irq(unsigned int irq) } #ifdef CONFIG_SMP -int cpu_check_affinity(unsigned int irq, const struct cpumask *dest) +int cpu_check_affinity(struct irq_data *d, const struct cpumask *dest) { int cpu_dest; /* timer and ipi have to always be received on all CPUs */ - if (CHECK_IRQ_PER_CPU(irq)) { - /* Bad linux design decision. The mask has already - * been set; we must reset it */ - cpumask_setall(irq_desc[irq].affinity); + if (irqd_is_per_cpu(d)) return -EINVAL; - } /* whatever mask they set, we just allow one CPU */ cpu_dest = first_cpu(*dest); @@ -121,33 +122,34 @@ int cpu_check_affinity(unsigned int irq, const struct cpumask *dest) return cpu_dest; } -static int cpu_set_affinity_irq(unsigned int irq, const struct cpumask *dest) +static int cpu_set_affinity_irq(struct irq_data *d, const struct cpumask *dest, + bool force) { int cpu_dest; - cpu_dest = cpu_check_affinity(irq, dest); + cpu_dest = cpu_check_affinity(d, dest); if (cpu_dest < 0) return -1; - cpumask_copy(irq_desc[irq].affinity, dest); + cpumask_copy(d->affinity, dest); return 0; } #endif static struct irq_chip cpu_interrupt_type = { - .name = "CPU", - .mask = cpu_mask_irq, - .unmask = cpu_unmask_irq, - .ack = cpu_ack_irq, - .eoi = cpu_eoi_irq, + .name = "CPU", + .irq_mask = cpu_mask_irq, + .irq_unmask = cpu_unmask_irq, + .irq_ack = cpu_ack_irq, + .irq_eoi = cpu_eoi_irq, #ifdef CONFIG_SMP - .set_affinity = cpu_set_affinity_irq, + .irq_set_affinity = cpu_set_affinity_irq, #endif /* XXX: Needs to be written. We managed without it so far, but * we really ought to write it. */ - .retrigger = NULL, + .irq_retrigger = NULL, }; int show_interrupts(struct seq_file *p, void *v) @@ -167,10 +169,11 @@ int show_interrupts(struct seq_file *p, void *v) } if (i < NR_IRQS) { + struct irq_desc *desc = irq_to_desc(i); struct irqaction *action; - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); - action = irq_desc[i].action; + raw_spin_lock_irqsave(&desc->lock, flags); + action = desc->action; if (!action) goto skip; seq_printf(p, "%3d: ", i); @@ -181,7 +184,7 @@ int show_interrupts(struct seq_file *p, void *v) seq_printf(p, "%10u ", kstat_irqs(i)); #endif - seq_printf(p, " %14s", irq_desc[i].chip->name); + seq_printf(p, " %14s", irq_desc_get_chip(desc)->name); #ifndef PARISC_IRQ_CR16_COUNTS seq_printf(p, " %s", action->name); @@ -213,7 +216,7 @@ int show_interrupts(struct seq_file *p, void *v) seq_putc(p, '\n'); skip: - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); + raw_spin_unlock_irqrestore(&desc->lock, flags); } return 0; @@ -231,16 +234,16 @@ int show_interrupts(struct seq_file *p, void *v) int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data) { - if (irq_desc[irq].action) + if (irq_has_action(irq)) return -EBUSY; - if (irq_desc[irq].chip != &cpu_interrupt_type) + if (irq_get_chip(irq) != &cpu_interrupt_type) return -EBUSY; /* for iosapic interrupts */ if (type) { - set_irq_chip_and_handler(irq, type, handle_percpu_irq); - set_irq_chip_data(irq, data); - cpu_unmask_irq(irq); + irq_set_chip_and_handler(irq, type, handle_percpu_irq); + irq_set_chip_data(irq, data); + __cpu_unmask_irq(irq); } return 0; } @@ -289,7 +292,8 @@ int txn_alloc_irq(unsigned int bits_wide) unsigned long txn_affinity_addr(unsigned int irq, int cpu) { #ifdef CONFIG_SMP - cpumask_copy(irq_desc[irq].affinity, cpumask_of(cpu)); + struct irq_data *d = irq_get_irq_data(irq); + cpumask_copy(d->affinity, cpumask_of(cpu)); #endif return per_cpu(cpu_data, cpu).txn_addr; @@ -333,6 +337,7 @@ void do_cpu_irq_mask(struct pt_regs *regs) unsigned long eirr_val; int irq, cpu = smp_processor_id(); #ifdef CONFIG_SMP + struct irq_desc *desc; cpumask_t dest; #endif @@ -346,8 +351,9 @@ void do_cpu_irq_mask(struct pt_regs *regs) irq = eirr_to_irq(eirr_val); #ifdef CONFIG_SMP - cpumask_copy(&dest, irq_desc[irq].affinity); - if (CHECK_IRQ_PER_CPU(irq_desc[irq].status) && + desc = irq_to_desc(irq); + cpumask_copy(&dest, desc->irq_data.affinity); + if (irqd_is_per_cpu(&desc->irq_data) && !cpu_isset(smp_processor_id(), dest)) { int cpu = first_cpu(dest); @@ -388,14 +394,14 @@ static void claim_cpu_irqs(void) { int i; for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) { - set_irq_chip_and_handler(i, &cpu_interrupt_type, + irq_set_chip_and_handler(i, &cpu_interrupt_type, handle_percpu_irq); } - set_irq_handler(TIMER_IRQ, handle_percpu_irq); + irq_set_handler(TIMER_IRQ, handle_percpu_irq); setup_irq(TIMER_IRQ, &timer_action); #ifdef CONFIG_SMP - set_irq_handler(IPI_IRQ, handle_percpu_irq); + irq_set_handler(IPI_IRQ, handle_percpu_irq); setup_irq(IPI_IRQ, &ipi_action); #endif } diff --git a/arch/parisc/kernel/pacache.S b/arch/parisc/kernel/pacache.S index 09b77b2553c..a85823668cb 100644 --- a/arch/parisc/kernel/pacache.S +++ b/arch/parisc/kernel/pacache.S @@ -608,93 +608,131 @@ ENTRY(__clear_user_page_asm) .procend ENDPROC(__clear_user_page_asm) -ENTRY(flush_kernel_dcache_page_asm) +ENTRY(flush_dcache_page_asm) .proc .callinfo NO_CALLS .entry + ldil L%(TMPALIAS_MAP_START), %r28 +#ifdef CONFIG_64BIT +#if (TMPALIAS_MAP_START >= 0x80000000) + depdi 0, 31,32, %r28 /* clear any sign extension */ + /* FIXME: page size dependend */ +#endif + extrd,u %r26, 56,32, %r26 /* convert phys addr to tlb insert format */ + depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */ + depdi 0, 63,12, %r28 /* Clear any offset bits */ +#else + extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */ + depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */ + depwi 0, 31,12, %r28 /* Clear any offset bits */ +#endif + + /* Purge any old translation */ + + pdtlb 0(%r28) + ldil L%dcache_stride, %r1 - ldw R%dcache_stride(%r1), %r23 + ldw R%dcache_stride(%r1), %r1 #ifdef CONFIG_64BIT depdi,z 1, 63-PAGE_SHIFT,1, %r25 #else depwi,z 1, 31-PAGE_SHIFT,1, %r25 #endif - add %r26, %r25, %r25 - sub %r25, %r23, %r25 - - -1: fdc,m %r23(%r26) - fdc,m %r23(%r26) - fdc,m %r23(%r26) - fdc,m %r23(%r26) - fdc,m %r23(%r26) - fdc,m %r23(%r26) - fdc,m %r23(%r26) - fdc,m %r23(%r26) - fdc,m %r23(%r26) - fdc,m %r23(%r26) - fdc,m %r23(%r26) - fdc,m %r23(%r26) - fdc,m %r23(%r26) - fdc,m %r23(%r26) - fdc,m %r23(%r26) - cmpb,COND(<<) %r26, %r25,1b - fdc,m %r23(%r26) + add %r28, %r25, %r25 + sub %r25, %r1, %r25 + + +1: fdc,m %r1(%r28) + fdc,m %r1(%r28) + fdc,m %r1(%r28) + fdc,m %r1(%r28) + fdc,m %r1(%r28) + fdc,m %r1(%r28) + fdc,m %r1(%r28) + fdc,m %r1(%r28) + fdc,m %r1(%r28) + fdc,m %r1(%r28) + fdc,m %r1(%r28) + fdc,m %r1(%r28) + fdc,m %r1(%r28) + fdc,m %r1(%r28) + fdc,m %r1(%r28) + cmpb,COND(<<) %r28, %r25,1b + fdc,m %r1(%r28) sync bv %r0(%r2) - nop + pdtlb (%r25) .exit .procend -ENDPROC(flush_kernel_dcache_page_asm) - -ENTRY(flush_user_dcache_page) +ENDPROC(flush_dcache_page_asm) + +ENTRY(flush_icache_page_asm) .proc .callinfo NO_CALLS .entry - ldil L%dcache_stride, %r1 - ldw R%dcache_stride(%r1), %r23 - + ldil L%(TMPALIAS_MAP_START), %r28 #ifdef CONFIG_64BIT - depdi,z 1,63-PAGE_SHIFT,1, %r25 +#if (TMPALIAS_MAP_START >= 0x80000000) + depdi 0, 31,32, %r28 /* clear any sign extension */ + /* FIXME: page size dependend */ +#endif + extrd,u %r26, 56,32, %r26 /* convert phys addr to tlb insert format */ + depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */ + depdi 0, 63,12, %r28 /* Clear any offset bits */ #else - depwi,z 1,31-PAGE_SHIFT,1, %r25 + extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */ + depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */ + depwi 0, 31,12, %r28 /* Clear any offset bits */ #endif - add %r26, %r25, %r25 - sub %r25, %r23, %r25 + /* Purge any old translation */ -1: fdc,m %r23(%sr3, %r26) - fdc,m %r23(%sr3, %r26) - fdc,m %r23(%sr3, %r26) - fdc,m %r23(%sr3, %r26) - fdc,m %r23(%sr3, %r26) - fdc,m %r23(%sr3, %r26) - fdc,m %r23(%sr3, %r26) - fdc,m %r23(%sr3, %r26) - fdc,m %r23(%sr3, %r26) - fdc,m %r23(%sr3, %r26) - fdc,m %r23(%sr3, %r26) - fdc,m %r23(%sr3, %r26) - fdc,m %r23(%sr3, %r26) - fdc,m %r23(%sr3, %r26) - fdc,m %r23(%sr3, %r26) - cmpb,COND(<<) %r26, %r25,1b - fdc,m %r23(%sr3, %r26) + pitlb (%sr0,%r28) + + ldil L%icache_stride, %r1 + ldw R%icache_stride(%r1), %r1 + +#ifdef CONFIG_64BIT + depdi,z 1, 63-PAGE_SHIFT,1, %r25 +#else + depwi,z 1, 31-PAGE_SHIFT,1, %r25 +#endif + add %r28, %r25, %r25 + sub %r25, %r1, %r25 + + +1: fic,m %r1(%r28) + fic,m %r1(%r28) + fic,m %r1(%r28) + fic,m %r1(%r28) + fic,m %r1(%r28) + fic,m %r1(%r28) + fic,m %r1(%r28) + fic,m %r1(%r28) + fic,m %r1(%r28) + fic,m %r1(%r28) + fic,m %r1(%r28) + fic,m %r1(%r28) + fic,m %r1(%r28) + fic,m %r1(%r28) + fic,m %r1(%r28) + cmpb,COND(<<) %r28, %r25,1b + fic,m %r1(%r28) sync bv %r0(%r2) - nop + pitlb (%sr0,%r25) .exit .procend -ENDPROC(flush_user_dcache_page) +ENDPROC(flush_icache_page_asm) -ENTRY(flush_user_icache_page) +ENTRY(flush_kernel_dcache_page_asm) .proc .callinfo NO_CALLS .entry @@ -711,23 +749,23 @@ ENTRY(flush_user_icache_page) sub %r25, %r23, %r25 -1: fic,m %r23(%sr3, %r26) - fic,m %r23(%sr3, %r26) - fic,m %r23(%sr3, %r26) - fic,m %r23(%sr3, %r26) - fic,m %r23(%sr3, %r26) - fic,m %r23(%sr3, %r26) - fic,m %r23(%sr3, %r26) - fic,m %r23(%sr3, %r26) - fic,m %r23(%sr3, %r26) - fic,m %r23(%sr3, %r26) - fic,m %r23(%sr3, %r26) - fic,m %r23(%sr3, %r26) - fic,m %r23(%sr3, %r26) - fic,m %r23(%sr3, %r26) - fic,m %r23(%sr3, %r26) +1: fdc,m %r23(%r26) + fdc,m %r23(%r26) + fdc,m %r23(%r26) + fdc,m %r23(%r26) + fdc,m %r23(%r26) + fdc,m %r23(%r26) + fdc,m %r23(%r26) + fdc,m %r23(%r26) + fdc,m %r23(%r26) + fdc,m %r23(%r26) + fdc,m %r23(%r26) + fdc,m %r23(%r26) + fdc,m %r23(%r26) + fdc,m %r23(%r26) + fdc,m %r23(%r26) cmpb,COND(<<) %r26, %r25,1b - fic,m %r23(%sr3, %r26) + fdc,m %r23(%r26) sync bv %r0(%r2) @@ -735,8 +773,7 @@ ENTRY(flush_user_icache_page) .exit .procend -ENDPROC(flush_user_icache_page) - +ENDPROC(flush_kernel_dcache_page_asm) ENTRY(purge_kernel_dcache_page) .proc @@ -780,69 +817,6 @@ ENTRY(purge_kernel_dcache_page) .procend ENDPROC(purge_kernel_dcache_page) -#if 0 - /* Currently not used, but it still is a possible alternate - * solution. - */ - -ENTRY(flush_alias_page) - .proc - .callinfo NO_CALLS - .entry - - tophys_r1 %r26 - - ldil L%(TMPALIAS_MAP_START), %r28 -#ifdef CONFIG_64BIT - extrd,u %r26, 56,32, %r26 /* convert phys addr to tlb insert format */ - depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */ - depdi 0, 63,12, %r28 /* Clear any offset bits */ -#else - extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */ - depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */ - depwi 0, 31,12, %r28 /* Clear any offset bits */ -#endif - - /* Purge any old translation */ - - pdtlb 0(%r28) - - ldil L%dcache_stride, %r1 - ldw R%dcache_stride(%r1), %r23 - -#ifdef CONFIG_64BIT - depdi,z 1, 63-PAGE_SHIFT,1, %r29 -#else - depwi,z 1, 31-PAGE_SHIFT,1, %r29 -#endif - add %r28, %r29, %r29 - sub %r29, %r23, %r29 - -1: fdc,m %r23(%r28) - fdc,m %r23(%r28) - fdc,m %r23(%r28) - fdc,m %r23(%r28) - fdc,m %r23(%r28) - fdc,m %r23(%r28) - fdc,m %r23(%r28) - fdc,m %r23(%r28) - fdc,m %r23(%r28) - fdc,m %r23(%r28) - fdc,m %r23(%r28) - fdc,m %r23(%r28) - fdc,m %r23(%r28) - fdc,m %r23(%r28) - fdc,m %r23(%r28) - cmpb,COND(<<) %r28, %r29, 1b - fdc,m %r23(%r28) - - sync - bv %r0(%r2) - nop - .exit - - .procend -#endif .export flush_user_dcache_range_asm @@ -865,7 +839,6 @@ flush_user_dcache_range_asm: .exit .procend -ENDPROC(flush_alias_page) ENTRY(flush_kernel_dcache_range_asm) .proc diff --git a/arch/parisc/kernel/signal.c b/arch/parisc/kernel/signal.c index 609a331878e..12c1ed33dc1 100644 --- a/arch/parisc/kernel/signal.c +++ b/arch/parisc/kernel/signal.c @@ -291,7 +291,7 @@ setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, DBG(1,"setup_rt_frame: frame->uc = 0x%p\n", &frame->uc); DBG(1,"setup_rt_frame: frame->uc.uc_mcontext = 0x%p\n", &frame->uc.uc_mcontext); err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, in_syscall); - /* FIXME: Should probably be converted aswell for the compat case */ + /* FIXME: Should probably be converted as well for the compat case */ err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); } diff --git a/arch/parisc/kernel/syscall.S b/arch/parisc/kernel/syscall.S index 68e75ce838d..82a52b2fb13 100644 --- a/arch/parisc/kernel/syscall.S +++ b/arch/parisc/kernel/syscall.S @@ -605,7 +605,7 @@ cas_action: copy %r0, %r21 3: - /* Error occured on load or store */ + /* Error occurred on load or store */ /* Free lock */ stw %r20, 0(%sr2,%r20) #if ENABLE_LWS_DEBUG diff --git a/arch/parisc/kernel/syscall_table.S b/arch/parisc/kernel/syscall_table.S index 74867dfdabe..4be85ee10b8 100644 --- a/arch/parisc/kernel/syscall_table.S +++ b/arch/parisc/kernel/syscall_table.S @@ -34,7 +34,7 @@ /* Use ENTRY_SAME for 32-bit syscalls which are the same on wide and * narrow palinux. Use ENTRY_DIFF for those where a 32-bit specific * implementation is required on wide palinux. Use ENTRY_COMP where - * the compatability layer has a useful 32-bit implementation. + * the compatibility layer has a useful 32-bit implementation. */ #define ENTRY_SAME(_name_) .dword sys_##_name_ #define ENTRY_DIFF(_name_) .dword sys32_##_name_ diff --git a/arch/parisc/math-emu/dfadd.c b/arch/parisc/math-emu/dfadd.c index e147d7d3b0f..d37e2d2cb6f 100644 --- a/arch/parisc/math-emu/dfadd.c +++ b/arch/parisc/math-emu/dfadd.c @@ -303,7 +303,7 @@ dbl_fadd( if(Dbl_iszero_hidden(resultp1)) { /* Handle normalization */ - /* A straight foward algorithm would now shift the result + /* A straight forward algorithm would now shift the result * and extension left until the hidden bit becomes one. Not * all of the extension bits need participate in the shift. * Only the two most significant bits (round and guard) are diff --git a/arch/parisc/math-emu/dfsub.c b/arch/parisc/math-emu/dfsub.c index 87ebc60d465..2e8b5a79bff 100644 --- a/arch/parisc/math-emu/dfsub.c +++ b/arch/parisc/math-emu/dfsub.c @@ -306,7 +306,7 @@ dbl_fsub( if(Dbl_iszero_hidden(resultp1)) { /* Handle normalization */ - /* A straight foward algorithm would now shift the result + /* A straight forward algorithm would now shift the result * and extension left until the hidden bit becomes one. Not * all of the extension bits need participate in the shift. * Only the two most significant bits (round and guard) are diff --git a/arch/parisc/math-emu/fmpyfadd.c b/arch/parisc/math-emu/fmpyfadd.c index 5dd7f93a89b..b067c45c872 100644 --- a/arch/parisc/math-emu/fmpyfadd.c +++ b/arch/parisc/math-emu/fmpyfadd.c @@ -531,7 +531,7 @@ dbl_fmpyfadd( sign_save = Dbl_signextendedsign(resultp1); if (Dbl_iszero_hidden(resultp1)) { /* Handle normalization */ - /* A straight foward algorithm would now shift the + /* A straightforward algorithm would now shift the * result and extension left until the hidden bit * becomes one. Not all of the extension bits need * participate in the shift. Only the two most @@ -1191,7 +1191,7 @@ unsigned int *status; sign_save = Dbl_signextendedsign(resultp1); if (Dbl_iszero_hidden(resultp1)) { /* Handle normalization */ - /* A straight foward algorithm would now shift the + /* A straightforward algorithm would now shift the * result and extension left until the hidden bit * becomes one. Not all of the extension bits need * participate in the shift. Only the two most @@ -1841,7 +1841,7 @@ unsigned int *status; sign_save = Sgl_signextendedsign(resultp1); if (Sgl_iszero_hidden(resultp1)) { /* Handle normalization */ - /* A straight foward algorithm would now shift the + /* A straightforward algorithm would now shift the * result and extension left until the hidden bit * becomes one. Not all of the extension bits need * participate in the shift. Only the two most @@ -2483,7 +2483,7 @@ unsigned int *status; sign_save = Sgl_signextendedsign(resultp1); if (Sgl_iszero_hidden(resultp1)) { /* Handle normalization */ - /* A straight foward algorithm would now shift the + /* A straightforward algorithm would now shift the * result and extension left until the hidden bit * becomes one. Not all of the extension bits need * participate in the shift. Only the two most diff --git a/arch/parisc/math-emu/sfadd.c b/arch/parisc/math-emu/sfadd.c index 008d721b5d2..f802cd6c786 100644 --- a/arch/parisc/math-emu/sfadd.c +++ b/arch/parisc/math-emu/sfadd.c @@ -298,7 +298,7 @@ sgl_fadd( if(Sgl_iszero_hidden(result)) { /* Handle normalization */ - /* A straight foward algorithm would now shift the result + /* A straightforward algorithm would now shift the result * and extension left until the hidden bit becomes one. Not * all of the extension bits need participate in the shift. * Only the two most significant bits (round and guard) are diff --git a/arch/parisc/math-emu/sfsub.c b/arch/parisc/math-emu/sfsub.c index 24eef61c8e3..5f90d0f31a5 100644 --- a/arch/parisc/math-emu/sfsub.c +++ b/arch/parisc/math-emu/sfsub.c @@ -301,7 +301,7 @@ sgl_fsub( if(Sgl_iszero_hidden(result)) { /* Handle normalization */ - /* A straight foward algorithm would now shift the result + /* A straightforward algorithm would now shift the result * and extension left until the hidden bit becomes one. Not * all of the extension bits need participate in the shift. * Only the two most significant bits (round and guard) are diff --git a/arch/parisc/mm/init.c b/arch/parisc/mm/init.c index f4f4d700833..b1d126258de 100644 --- a/arch/parisc/mm/init.c +++ b/arch/parisc/mm/init.c @@ -266,8 +266,10 @@ static void __init setup_bootmem(void) } memset(pfnnid_map, 0xff, sizeof(pfnnid_map)); - for (i = 0; i < npmem_ranges; i++) + for (i = 0; i < npmem_ranges; i++) { + node_set_state(i, N_NORMAL_MEMORY); node_set_online(i); + } #endif /* @@ -544,7 +546,7 @@ void __init mem_init(void) unsigned long *empty_zero_page __read_mostly; EXPORT_SYMBOL(empty_zero_page); -void show_mem(void) +void show_mem(unsigned int filter) { int i,free = 0,total = 0,reserved = 0; int shared = 0, cached = 0; diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 71ba04721be..8f4d50b0adf 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -95,6 +95,10 @@ config GENERIC_FIND_NEXT_BIT bool default y +config GENERIC_FIND_BIT_LE + bool + default y + config GENERIC_GPIO bool help @@ -134,7 +138,8 @@ config PPC select HAVE_GENERIC_HARDIRQS select HAVE_SPARSE_IRQ select IRQ_PER_CPU - select GENERIC_HARDIRQS_NO_DEPRECATED + select GENERIC_IRQ_SHOW + select GENERIC_IRQ_SHOW_LEVEL config EARLY_PRINTK bool @@ -204,7 +209,7 @@ config ARCH_HIBERNATION_POSSIBLE config ARCH_SUSPEND_POSSIBLE def_bool y depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \ - PPC_85xx || PPC_86xx || PPC_PSERIES || 44x || 40x + (PPC_85xx && !SMP) || PPC_86xx || PPC_PSERIES || 44x || 40x config PPC_DCR_NATIVE bool @@ -768,11 +773,19 @@ config HAS_RAPIDIO config RAPIDIO bool "RapidIO support" - depends on HAS_RAPIDIO + depends on HAS_RAPIDIO || PCI help If you say Y here, the kernel will include drivers and infrastructure code to support RapidIO interconnect devices. +config FSL_RIO + bool "Freescale Embedded SRIO Controller support" + depends on RAPIDIO && HAS_RAPIDIO + default "n" + ---help--- + Include support for RapidIO controller on Freescale embedded + processors (MPC8548, MPC8641, etc). + source "drivers/rapidio/Kconfig" endmenu diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts index 22f64b62d7f..e0668f87779 100644 --- a/arch/powerpc/boot/dts/p1020rdb.dts +++ b/arch/powerpc/boot/dts/p1020rdb.dts @@ -1,7 +1,7 @@ /* * P1020 RDB Device Tree Source * - * Copyright 2009 Freescale Semiconductor Inc. + * Copyright 2009-2011 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -553,7 +553,7 @@ reg = <0 0xffe09000 0 0x1000>; bus-range = <0 255>; ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 - 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>; + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; interrupts = <16 2>; @@ -580,8 +580,8 @@ #address-cells = <3>; reg = <0 0xffe0a000 0 0x1000>; bus-range = <0 255>; - ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 - 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; interrupts = <16 2>; @@ -590,8 +590,8 @@ #size-cells = <2>; #address-cells = <3>; device_type = "pci"; - ranges = <0x2000000 0x0 0xc0000000 - 0x2000000 0x0 0xc0000000 + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts index da4cb0d8d21..e2d48fd4416 100644 --- a/arch/powerpc/boot/dts/p2020rdb.dts +++ b/arch/powerpc/boot/dts/p2020rdb.dts @@ -1,7 +1,7 @@ /* * P2020 RDB Device Tree Source * - * Copyright 2009 Freescale Semiconductor Inc. + * Copyright 2009-2011 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -537,7 +537,7 @@ reg = <0 0xffe09000 0 0x1000>; bus-range = <0 255>; ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 - 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>; + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; interrupts = <25 2>; @@ -564,8 +564,8 @@ #address-cells = <3>; reg = <0 0xffe0a000 0 0x1000>; bus-range = <0 255>; - ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 - 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; interrupts = <26 2>; @@ -574,8 +574,8 @@ #size-cells = <2>; #address-cells = <3>; device_type = "pci"; - ranges = <0x2000000 0x0 0xc0000000 - 0x2000000 0x0 0xc0000000 + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts index 0fe93d0c8b2..b69c3a5dc85 100644 --- a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts +++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts @@ -6,7 +6,7 @@ * This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb, * eth1, eth2, sdhc, crypto, global-util, pci0. * - * Copyright 2009 Freescale Semiconductor Inc. + * Copyright 2009-2011 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -342,7 +342,7 @@ reg = <0 0xffe09000 0 0x1000>; bus-range = <0 255>; ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 - 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>; + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; interrupts = <25 2>; diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts index e95a5128532..7a31d46c01b 100644 --- a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts +++ b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts @@ -7,7 +7,7 @@ * * Please note to add "-b 1" for core1's dts compiling. * - * Copyright 2009 Freescale Semiconductor Inc. + * Copyright 2009-2011 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -162,8 +162,8 @@ #address-cells = <3>; reg = <0 0xffe0a000 0 0x1000>; bus-range = <0 255>; - ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 - 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; interrupts = <26 2>; @@ -172,8 +172,8 @@ #size-cells = <2>; #address-cells = <3>; device_type = "pci"; - ranges = <0x2000000 0x0 0xc0000000 - 0x2000000 0x0 0xc0000000 + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 diff --git a/arch/powerpc/configs/44x/warp_defconfig b/arch/powerpc/configs/44x/warp_defconfig index 6cf9d661480..abf74dc1f79 100644 --- a/arch/powerpc/configs/44x/warp_defconfig +++ b/arch/powerpc/configs/44x/warp_defconfig @@ -47,6 +47,7 @@ CONFIG_MTD_NAND_NDFC=y CONFIG_MTD_UBI=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_RAM=y +CONFIG_MISC_DEVICES=y CONFIG_EEPROM_AT24=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y diff --git a/arch/powerpc/configs/52xx/motionpro_defconfig b/arch/powerpc/configs/52xx/motionpro_defconfig index 6828eda02bd..0c7de9620ea 100644 --- a/arch/powerpc/configs/52xx/motionpro_defconfig +++ b/arch/powerpc/configs/52xx/motionpro_defconfig @@ -43,6 +43,7 @@ CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=32768 +CONFIG_MISC_DEVICES=y CONFIG_EEPROM_LEGACY=y CONFIG_SCSI_TGT=y CONFIG_BLK_DEV_SD=y diff --git a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig index 4b2441244ea..d41857a5152 100644 --- a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig +++ b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig @@ -85,6 +85,7 @@ CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_MISC_DEVICES=y CONFIG_DS1682=y CONFIG_IDE=y CONFIG_BLK_DEV_IDECS=y diff --git a/arch/powerpc/configs/86xx/gef_sbc310_defconfig b/arch/powerpc/configs/86xx/gef_sbc310_defconfig index a360ba44b92..38303ec11bc 100644 --- a/arch/powerpc/configs/86xx/gef_sbc310_defconfig +++ b/arch/powerpc/configs/86xx/gef_sbc310_defconfig @@ -85,6 +85,7 @@ CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_MISC_DEVICES=y CONFIG_DS1682=y CONFIG_IDE=y CONFIG_BLK_DEV_IDECS=y diff --git a/arch/powerpc/configs/86xx/gef_sbc610_defconfig b/arch/powerpc/configs/86xx/gef_sbc610_defconfig index be2829dd129..98533973d20 100644 --- a/arch/powerpc/configs/86xx/gef_sbc610_defconfig +++ b/arch/powerpc/configs/86xx/gef_sbc610_defconfig @@ -138,6 +138,7 @@ CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_MISC_DEVICES=y CONFIG_DS1682=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=y diff --git a/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig b/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig index 0c9c7ed7ec7..b614508d6fd 100644 --- a/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig +++ b/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig @@ -63,6 +63,7 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_MISC_DEVICES=y CONFIG_EEPROM_LEGACY=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=y diff --git a/arch/powerpc/configs/e55xx_smp_defconfig b/arch/powerpc/configs/e55xx_smp_defconfig index 06f95492afc..9fa1613e5e2 100644 --- a/arch/powerpc/configs/e55xx_smp_defconfig +++ b/arch/powerpc/configs/e55xx_smp_defconfig @@ -32,6 +32,7 @@ CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_MISC_DEVICES=y CONFIG_EEPROM_LEGACY=y CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_MOUSEDEV is not set diff --git a/arch/powerpc/configs/linkstation_defconfig b/arch/powerpc/configs/linkstation_defconfig index f39d0cf876d..8a874b99986 100644 --- a/arch/powerpc/configs/linkstation_defconfig +++ b/arch/powerpc/configs/linkstation_defconfig @@ -78,6 +78,7 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=2 CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_MISC_DEVICES=y CONFIG_EEPROM_LEGACY=m CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y diff --git a/arch/powerpc/configs/mpc512x_defconfig b/arch/powerpc/configs/mpc512x_defconfig index 62db8a3df16..c02bbb2fddf 100644 --- a/arch/powerpc/configs/mpc512x_defconfig +++ b/arch/powerpc/configs/mpc512x_defconfig @@ -61,6 +61,7 @@ CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=1 CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_BLK_DEV_XIP=y +CONFIG_MISC_DEVICES=y CONFIG_EEPROM_AT24=y CONFIG_SCSI=y # CONFIG_SCSI_PROC_FS is not set diff --git a/arch/powerpc/configs/mpc5200_defconfig b/arch/powerpc/configs/mpc5200_defconfig index 7376e27b8ed..e63f537b854 100644 --- a/arch/powerpc/configs/mpc5200_defconfig +++ b/arch/powerpc/configs/mpc5200_defconfig @@ -52,6 +52,7 @@ CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=32768 +CONFIG_MISC_DEVICES=y CONFIG_EEPROM_AT24=y CONFIG_SCSI_TGT=y CONFIG_BLK_DEV_SD=y diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig index 99a19d1e9bf..c06a86c3309 100644 --- a/arch/powerpc/configs/mpc85xx_defconfig +++ b/arch/powerpc/configs/mpc85xx_defconfig @@ -82,6 +82,7 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_MISC_DEVICES=y CONFIG_EEPROM_LEGACY=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=y diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig index c636f23f8c9..942ced90557 100644 --- a/arch/powerpc/configs/mpc85xx_smp_defconfig +++ b/arch/powerpc/configs/mpc85xx_smp_defconfig @@ -84,6 +84,7 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_MISC_DEVICES=y CONFIG_EEPROM_LEGACY=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=y diff --git a/arch/powerpc/configs/mpc86xx_defconfig b/arch/powerpc/configs/mpc86xx_defconfig index 55b54318fef..038a308cbfc 100644 --- a/arch/powerpc/configs/mpc86xx_defconfig +++ b/arch/powerpc/configs/mpc86xx_defconfig @@ -66,6 +66,7 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_MISC_DEVICES=y CONFIG_EEPROM_LEGACY=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=y diff --git a/arch/powerpc/configs/pasemi_defconfig b/arch/powerpc/configs/pasemi_defconfig index edd2d54c819..f4deb0b78cf 100644 --- a/arch/powerpc/configs/pasemi_defconfig +++ b/arch/powerpc/configs/pasemi_defconfig @@ -59,6 +59,7 @@ CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_MISC_DEVICES=y CONFIG_EEPROM_LEGACY=y CONFIG_IDE=y CONFIG_BLK_DEV_IDECD=y diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig index 9d64a6822d8..0a10fb009ef 100644 --- a/arch/powerpc/configs/ppc6xx_defconfig +++ b/arch/powerpc/configs/ppc6xx_defconfig @@ -398,6 +398,7 @@ CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_CDROM_PKTCDVD=m CONFIG_VIRTIO_BLK=m CONFIG_BLK_DEV_HD=y +CONFIG_MISC_DEVICES=y CONFIG_ENCLOSURE_SERVICES=m CONFIG_SENSORS_TSL2550=m CONFIG_EEPROM_AT24=m diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig index 9c3f22c6cde..249ddd0a27c 100644 --- a/arch/powerpc/configs/pseries_defconfig +++ b/arch/powerpc/configs/pseries_defconfig @@ -189,6 +189,7 @@ CONFIG_TIGON3=y CONFIG_BNX2=m CONFIG_CHELSIO_T1=m CONFIG_CHELSIO_T3=m +CONFIG_CHELSIO_T4=m CONFIG_EHEA=y CONFIG_IXGBE=m CONFIG_IXGB=m @@ -255,6 +256,8 @@ CONFIG_INFINIBAND_USER_MAD=m CONFIG_INFINIBAND_USER_ACCESS=m CONFIG_INFINIBAND_MTHCA=m CONFIG_INFINIBAND_EHCA=m +CONFIG_INFINIBAND_CXGB3=m +CONFIG_INFINIBAND_CXGB4=m CONFIG_MLX4_INFINIBAND=m CONFIG_INFINIBAND_IPOIB=m CONFIG_INFINIBAND_IPOIB_CM=y diff --git a/arch/powerpc/include/asm/8xx_immap.h b/arch/powerpc/include/asm/8xx_immap.h index 6b6dc20b0be..bdf0563ba42 100644 --- a/arch/powerpc/include/asm/8xx_immap.h +++ b/arch/powerpc/include/asm/8xx_immap.h @@ -393,8 +393,8 @@ typedef struct fec { uint fec_addr_low; /* lower 32 bits of station address */ ushort fec_addr_high; /* upper 16 bits of station address */ ushort res1; /* reserved */ - uint fec_hash_table_high; /* upper 32-bits of hash table */ - uint fec_hash_table_low; /* lower 32-bits of hash table */ + uint fec_grp_hash_table_high; /* upper 32-bits of hash table */ + uint fec_grp_hash_table_low; /* lower 32-bits of hash table */ uint fec_r_des_start; /* beginning of Rx descriptor ring */ uint fec_x_des_start; /* beginning of Tx descriptor ring */ uint fec_r_buff_size; /* Rx buffer size */ diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h index 8a7e9314c68..f18c6d9b951 100644 --- a/arch/powerpc/include/asm/bitops.h +++ b/arch/powerpc/include/asm/bitops.h @@ -209,8 +209,8 @@ static __inline__ unsigned long ffz(unsigned long x) return BITS_PER_LONG; /* - * Calculate the bit position of the least signficant '1' bit in x - * (since x has been changed this will actually be the least signficant + * Calculate the bit position of the least significant '1' bit in x + * (since x has been changed this will actually be the least significant * '0' bit in * the original x). Note: (x & -x) gives us a mask that * is the least significant * (RIGHT-most) 1-bit of the value in x. */ @@ -281,68 +281,56 @@ unsigned long __arch_hweight64(__u64 w); /* Little-endian versions */ -static __inline__ int test_le_bit(unsigned long nr, - __const__ unsigned long *addr) +static __inline__ int test_bit_le(unsigned long nr, + __const__ void *addr) { __const__ unsigned char *tmp = (__const__ unsigned char *) addr; return (tmp[nr >> 3] >> (nr & 7)) & 1; } -#define __set_le_bit(nr, addr) \ - __set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr)) -#define __clear_le_bit(nr, addr) \ - __clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr)) +static inline void __set_bit_le(int nr, void *addr) +{ + __set_bit(nr ^ BITOP_LE_SWIZZLE, addr); +} + +static inline void __clear_bit_le(int nr, void *addr) +{ + __clear_bit(nr ^ BITOP_LE_SWIZZLE, addr); +} + +static inline int test_and_set_bit_le(int nr, void *addr) +{ + return test_and_set_bit(nr ^ BITOP_LE_SWIZZLE, addr); +} -#define test_and_set_le_bit(nr, addr) \ - test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr)) -#define test_and_clear_le_bit(nr, addr) \ - test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr)) +static inline int test_and_clear_bit_le(int nr, void *addr) +{ + return test_and_clear_bit(nr ^ BITOP_LE_SWIZZLE, addr); +} + +static inline int __test_and_set_bit_le(int nr, void *addr) +{ + return __test_and_set_bit(nr ^ BITOP_LE_SWIZZLE, addr); +} -#define __test_and_set_le_bit(nr, addr) \ - __test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr)) -#define __test_and_clear_le_bit(nr, addr) \ - __test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr)) +static inline int __test_and_clear_bit_le(int nr, void *addr) +{ + return __test_and_clear_bit(nr ^ BITOP_LE_SWIZZLE, addr); +} -#define find_first_zero_le_bit(addr, size) generic_find_next_zero_le_bit((addr), (size), 0) -unsigned long generic_find_next_zero_le_bit(const unsigned long *addr, +#define find_first_zero_bit_le(addr, size) \ + find_next_zero_bit_le((addr), (size), 0) +unsigned long find_next_zero_bit_le(const void *addr, unsigned long size, unsigned long offset); -unsigned long generic_find_next_le_bit(const unsigned long *addr, +unsigned long find_next_bit_le(const void *addr, unsigned long size, unsigned long offset); /* Bitmap functions for the ext2 filesystem */ -#define ext2_set_bit(nr,addr) \ - __test_and_set_le_bit((nr), (unsigned long*)addr) -#define ext2_clear_bit(nr, addr) \ - __test_and_clear_le_bit((nr), (unsigned long*)addr) - #define ext2_set_bit_atomic(lock, nr, addr) \ - test_and_set_le_bit((nr), (unsigned long*)addr) + test_and_set_bit_le((nr), (unsigned long*)addr) #define ext2_clear_bit_atomic(lock, nr, addr) \ - test_and_clear_le_bit((nr), (unsigned long*)addr) - -#define ext2_test_bit(nr, addr) test_le_bit((nr),(unsigned long*)addr) - -#define ext2_find_first_zero_bit(addr, size) \ - find_first_zero_le_bit((unsigned long*)addr, size) -#define ext2_find_next_zero_bit(addr, size, off) \ - generic_find_next_zero_le_bit((unsigned long*)addr, size, off) - -#define ext2_find_next_bit(addr, size, off) \ - generic_find_next_le_bit((unsigned long *)addr, size, off) -/* Bitmap functions for the minix filesystem. */ - -#define minix_test_and_set_bit(nr,addr) \ - __test_and_set_le_bit(nr, (unsigned long *)addr) -#define minix_set_bit(nr,addr) \ - __set_le_bit(nr, (unsigned long *)addr) -#define minix_test_and_clear_bit(nr,addr) \ - __test_and_clear_le_bit(nr, (unsigned long *)addr) -#define minix_test_bit(nr,addr) \ - test_le_bit(nr, (unsigned long *)addr) - -#define minix_find_first_zero_bit(addr,size) \ - find_first_zero_le_bit((unsigned long *)addr, size) + test_and_clear_bit_le((nr), (unsigned long*)addr) #include <asm-generic/bitops/sched.h> diff --git a/arch/powerpc/include/asm/compat.h b/arch/powerpc/include/asm/compat.h index 2296112e247..91010e8f847 100644 --- a/arch/powerpc/include/asm/compat.h +++ b/arch/powerpc/include/asm/compat.h @@ -140,7 +140,7 @@ static inline void __user *arch_compat_alloc_user_space(long len) unsigned long usp = regs->gpr[1]; /* - * We cant access below the stack pointer in the 32bit ABI and + * We can't access below the stack pointer in the 32bit ABI and * can access 288 bytes in the 64bit ABI */ if (!is_32bit_task()) diff --git a/arch/powerpc/include/asm/cpm.h b/arch/powerpc/include/asm/cpm.h index e50323fe941..4398a6cdcf5 100644 --- a/arch/powerpc/include/asm/cpm.h +++ b/arch/powerpc/include/asm/cpm.h @@ -98,7 +98,7 @@ typedef struct cpm_buf_desc { #define BD_SC_INTRPT (0x1000) /* Interrupt on change */ #define BD_SC_LAST (0x0800) /* Last buffer in frame */ #define BD_SC_TC (0x0400) /* Transmit CRC */ -#define BD_SC_CM (0x0200) /* Continous mode */ +#define BD_SC_CM (0x0200) /* Continuous mode */ #define BD_SC_ID (0x0100) /* Rec'd too many idles */ #define BD_SC_P (0x0100) /* xmt preamble */ #define BD_SC_BR (0x0020) /* Break received */ diff --git a/arch/powerpc/include/asm/cpm1.h b/arch/powerpc/include/asm/cpm1.h index bd07650dca5..8ee4211ca0c 100644 --- a/arch/powerpc/include/asm/cpm1.h +++ b/arch/powerpc/include/asm/cpm1.h @@ -4,7 +4,7 @@ * * This file contains structures and information for the communication * processor channels. Some CPM control and status is available - * throught the MPC8xx internal memory map. See immap.h for details. + * through the MPC8xx internal memory map. See immap.h for details. * This file only contains what I need for the moment, not the total * CPM capabilities. I (or someone else) will add definitions as they * are needed. -- Dan diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index be3cdf9134c..1833d1a07e7 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -382,10 +382,12 @@ extern const char *powerpc_base_platform; #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) -#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \ +#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ CPU_FTR_DBELL) +#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ + CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ + CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD) #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) /* 64-bit CPUs */ @@ -435,11 +437,15 @@ extern const char *powerpc_base_platform; #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) #ifdef __powerpc64__ +#ifdef CONFIG_PPC_BOOK3E +#define CPU_FTRS_POSSIBLE (CPU_FTRS_E5500) +#else #define CPU_FTRS_POSSIBLE \ (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \ CPU_FTR_1T_SEGMENT | CPU_FTR_VSX) +#endif #else enum { CPU_FTRS_POSSIBLE = @@ -473,16 +479,21 @@ enum { #endif #ifdef CONFIG_E500 CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC | + CPU_FTRS_E5500 | #endif 0, }; #endif /* __powerpc64__ */ #ifdef __powerpc64__ +#ifdef CONFIG_PPC_BOOK3E +#define CPU_FTRS_ALWAYS (CPU_FTRS_E5500) +#else #define CPU_FTRS_ALWAYS \ (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \ CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \ CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE) +#endif #else enum { CPU_FTRS_ALWAYS = @@ -513,6 +524,7 @@ enum { #endif #ifdef CONFIG_E500 CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC & + CPU_FTRS_E5500 & #endif CPU_FTRS_POSSIBLE, }; diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h index 6d2416a8570..dd70fac57ec 100644 --- a/arch/powerpc/include/asm/dma-mapping.h +++ b/arch/powerpc/include/asm/dma-mapping.h @@ -42,6 +42,7 @@ extern void __dma_free_coherent(size_t size, void *vaddr); extern void __dma_sync(void *vaddr, size_t size, int direction); extern void __dma_sync_page(struct page *page, unsigned long offset, size_t size, int direction); +extern unsigned long __dma_get_coherent_pfn(unsigned long cpu_addr); #else /* ! CONFIG_NOT_COHERENT_CACHE */ /* @@ -198,6 +199,11 @@ static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) +extern int dma_mmap_coherent(struct device *, struct vm_area_struct *, + void *, dma_addr_t, size_t); +#define ARCH_HAS_DMA_MMAP_COHERENT + + static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size, enum dma_data_direction direction) { diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h index ec089acfa56..8edec710cc6 100644 --- a/arch/powerpc/include/asm/hvcall.h +++ b/arch/powerpc/include/asm/hvcall.h @@ -122,7 +122,7 @@ #define H_DABRX_KERNEL (1UL<<(63-62)) #define H_DABRX_USER (1UL<<(63-63)) -/* Each control block has to be on a 4K bondary */ +/* Each control block has to be on a 4K boundary */ #define H_CB_ALIGNMENT 4096 /* pSeries hypervisor opcodes */ diff --git a/arch/powerpc/include/asm/kprobes.h b/arch/powerpc/include/asm/kprobes.h index d0e7701fa1f..be0171afdc0 100644 --- a/arch/powerpc/include/asm/kprobes.h +++ b/arch/powerpc/include/asm/kprobes.h @@ -50,7 +50,7 @@ typedef unsigned int kprobe_opcode_t; * Handle cases where: * - User passes a <.symbol> or <module:.symbol> * - User passes a <symbol> or <module:symbol> - * - User passes a non-existant symbol, kallsyms_lookup_name + * - User passes a non-existent symbol, kallsyms_lookup_name * returns 0. Don't deref the NULL pointer in that case */ #define kprobe_lookup_name(name, addr) \ diff --git a/arch/powerpc/include/asm/lppaca.h b/arch/powerpc/include/asm/lppaca.h index 26b8c807f8f..a077adc0b35 100644 --- a/arch/powerpc/include/asm/lppaca.h +++ b/arch/powerpc/include/asm/lppaca.h @@ -105,7 +105,7 @@ struct lppaca { // processing of external interrupts. Note that PLIC will store the // XIRR directly into the xXirrValue field so that another XIRR will // not be presented until this one clears. The layout of the low - // 4-bytes of this Dword is upto SLIC - PLIC just checks whether the + // 4-bytes of this Dword is up to SLIC - PLIC just checks whether the // entire Dword is zero or not. A non-zero value in the low order // 2-bytes will result in SLIC being granted the highest thread // priority upon return. A 0 will return to SLIC as medium priority. diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h index fe56a23e1ff..e4f01915fbb 100644 --- a/arch/powerpc/include/asm/machdep.h +++ b/arch/powerpc/include/asm/machdep.h @@ -35,9 +35,9 @@ struct smp_ops_t { int (*probe)(void); void (*kick_cpu)(int nr); void (*setup_cpu)(int nr); + void (*bringup_done)(void); void (*take_timebase)(void); void (*give_timebase)(void); - int (*cpu_enable)(unsigned int nr); int (*cpu_disable)(void); void (*cpu_die)(unsigned int nr); int (*cpu_bootable)(unsigned int nr); @@ -267,7 +267,6 @@ struct machdep_calls { extern void e500_idle(void); extern void power4_idle(void); -extern void power4_cpu_offline_powersave(void); extern void ppc6xx_idle(void); extern void book3e_idle(void); diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h index acac35d5b38..ae7b3efec8e 100644 --- a/arch/powerpc/include/asm/mmu-hash64.h +++ b/arch/powerpc/include/asm/mmu-hash64.h @@ -27,7 +27,7 @@ #define STE_VSID_SHIFT 12 /* Location of cpu0's segment table */ -#define STAB0_PAGE 0x6 +#define STAB0_PAGE 0x8 #define STAB0_OFFSET (STAB0_PAGE << 12) #define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START) diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h index 946ec4947da..7005ee0b074 100644 --- a/arch/powerpc/include/asm/mpic.h +++ b/arch/powerpc/include/asm/mpic.h @@ -367,6 +367,10 @@ struct mpic #define MPIC_SINGLE_DEST_CPU 0x00001000 /* Enable CoreInt delivery of interrupts */ #define MPIC_ENABLE_COREINT 0x00002000 +/* Disable resetting of the MPIC. + * NOTE: This flag trumps MPIC_WANTS_RESET. + */ +#define MPIC_NO_RESET 0x00004000 /* MPIC HW modification ID */ #define MPIC_REGSET_MASK 0xf0000000 diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h index da4b2000854..2cd664ef0a5 100644 --- a/arch/powerpc/include/asm/page.h +++ b/arch/powerpc/include/asm/page.h @@ -100,7 +100,7 @@ extern phys_addr_t kernstart_addr; #endif #ifdef CONFIG_FLATMEM -#define ARCH_PFN_OFFSET (MEMORY_START >> PAGE_SHIFT) +#define ARCH_PFN_OFFSET ((unsigned long)(MEMORY_START >> PAGE_SHIFT)) #define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr) #endif diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h index 932f88dcf6f..812b2cd80ae 100644 --- a/arch/powerpc/include/asm/page_64.h +++ b/arch/powerpc/include/asm/page_64.h @@ -169,7 +169,7 @@ do { \ /* * This is the default if a program doesn't have a PT_GNU_STACK * program header entry. The PPC64 ELF ABI has a non executable stack - * stack by default, so in the absense of a PT_GNU_STACK program header + * stack by default, so in the absence of a PT_GNU_STACK program header * we turn execute permission off. */ #define VM_STACK_DEFAULT_FLAGS32 (VM_READ | VM_WRITE | VM_EXEC | \ diff --git a/arch/powerpc/include/asm/pasemi_dma.h b/arch/powerpc/include/asm/pasemi_dma.h index 19fd7933e2d..eafa5a5f56d 100644 --- a/arch/powerpc/include/asm/pasemi_dma.h +++ b/arch/powerpc/include/asm/pasemi_dma.h @@ -522,7 +522,7 @@ extern void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size, extern void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size, dma_addr_t *handle); -/* Routines to allocate flags (events) for channel syncronization */ +/* Routines to allocate flags (events) for channel synchronization */ extern int pasemi_dma_alloc_flag(void); extern void pasemi_dma_free_flag(int flag); extern void pasemi_dma_set_flag(int flag); diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h index 5e156e034fe..b90dbf8e5cd 100644 --- a/arch/powerpc/include/asm/pci-bridge.h +++ b/arch/powerpc/include/asm/pci-bridge.h @@ -106,7 +106,7 @@ struct pci_controller { * Used for variants of PCI indirect handling and possible quirks: * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 * EXT_REG - provides access to PCI-e extended registers - * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS + * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS * to determine which bus number to match on when generating type0 * config cycles diff --git a/arch/powerpc/include/asm/pmac_feature.h b/arch/powerpc/include/asm/pmac_feature.h index 00eedc5a4e6..10902c9375d 100644 --- a/arch/powerpc/include/asm/pmac_feature.h +++ b/arch/powerpc/include/asm/pmac_feature.h @@ -53,8 +53,8 @@ /* Here is the infamous serie of OHare based machines */ -#define PMAC_TYPE_COMET 0x20 /* Beleived to be PowerBook 2400 */ -#define PMAC_TYPE_HOOPER 0x21 /* Beleived to be PowerBook 3400 */ +#define PMAC_TYPE_COMET 0x20 /* Believed to be PowerBook 2400 */ +#define PMAC_TYPE_HOOPER 0x21 /* Believed to be PowerBook 3400 */ #define PMAC_TYPE_KANGA 0x22 /* PowerBook 3500 (first G3) */ #define PMAC_TYPE_ALCHEMY 0x23 /* Alchemy motherboard base */ #define PMAC_TYPE_GAZELLE 0x24 /* Spartacus, some 5xxx/6xxx */ diff --git a/arch/powerpc/include/asm/pte-common.h b/arch/powerpc/include/asm/pte-common.h index 76bb195e4f2..8d1569c2904 100644 --- a/arch/powerpc/include/asm/pte-common.h +++ b/arch/powerpc/include/asm/pte-common.h @@ -86,7 +86,7 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void); #define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1)) #endif -/* _PAGE_CHG_MASK masks of bits that are to be preserved accross +/* _PAGE_CHG_MASK masks of bits that are to be preserved across * pgprot changes */ #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ @@ -162,7 +162,7 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void); * on platforms where such control is possible. */ #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\ - defined(CONFIG_KPROBES) + defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) #define PAGE_KERNEL_TEXT PAGE_KERNEL_X #else #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX @@ -174,7 +174,7 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void); /* * Don't just check for any non zero bits in __PAGE_USER, since for book3e * and PTE_64BIT, PAGE_KERNEL_X contains _PAGE_BAP_SR which is also in - * _PAGE_USER. Need to explictly match _PAGE_BAP_UR bit in that case too. + * _PAGE_USER. Need to explicitly match _PAGE_BAP_UR bit in that case too. */ #define pte_user(val) ((val & _PAGE_USER) == _PAGE_USER) diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h index 0175a676b34..48223f9b872 100644 --- a/arch/powerpc/include/asm/ptrace.h +++ b/arch/powerpc/include/asm/ptrace.h @@ -125,8 +125,10 @@ extern int ptrace_put_reg(struct task_struct *task, int regno, #endif /* ! __powerpc64__ */ #define TRAP(regs) ((regs)->trap & ~0xF) #ifdef __powerpc64__ +#define NV_REG_POISON 0xdeadbeefdeadbeefUL #define CHECK_FULL_REGS(regs) BUG_ON(regs->trap & 1) #else +#define NV_REG_POISON 0xdeadbeef #define CHECK_FULL_REGS(regs) \ do { \ if ((regs)->trap & 1) \ diff --git a/arch/powerpc/include/asm/qe_ic.h b/arch/powerpc/include/asm/qe_ic.h index 9e2cb201916..f706164b0bd 100644 --- a/arch/powerpc/include/asm/qe_ic.h +++ b/arch/powerpc/include/asm/qe_ic.h @@ -81,7 +81,7 @@ int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high); static inline void qe_ic_cascade_low_ipic(unsigned int irq, struct irq_desc *desc) { - struct qe_ic *qe_ic = get_irq_desc_data(desc); + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc); unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic); if (cascade_irq != NO_IRQ) @@ -91,7 +91,7 @@ static inline void qe_ic_cascade_low_ipic(unsigned int irq, static inline void qe_ic_cascade_high_ipic(unsigned int irq, struct irq_desc *desc) { - struct qe_ic *qe_ic = get_irq_desc_data(desc); + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc); unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic); if (cascade_irq != NO_IRQ) @@ -101,9 +101,9 @@ static inline void qe_ic_cascade_high_ipic(unsigned int irq, static inline void qe_ic_cascade_low_mpic(unsigned int irq, struct irq_desc *desc) { - struct qe_ic *qe_ic = get_irq_desc_data(desc); + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc); unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic); - struct irq_chip *chip = get_irq_desc_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); if (cascade_irq != NO_IRQ) generic_handle_irq(cascade_irq); @@ -114,9 +114,9 @@ static inline void qe_ic_cascade_low_mpic(unsigned int irq, static inline void qe_ic_cascade_high_mpic(unsigned int irq, struct irq_desc *desc) { - struct qe_ic *qe_ic = get_irq_desc_data(desc); + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc); unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic); - struct irq_chip *chip = get_irq_desc_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); if (cascade_irq != NO_IRQ) generic_handle_irq(cascade_irq); @@ -127,9 +127,9 @@ static inline void qe_ic_cascade_high_mpic(unsigned int irq, static inline void qe_ic_cascade_muxed_mpic(unsigned int irq, struct irq_desc *desc) { - struct qe_ic *qe_ic = get_irq_desc_data(desc); + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc); unsigned int cascade_irq; - struct irq_chip *chip = get_irq_desc_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); cascade_irq = qe_ic_get_high_irq(qe_ic); if (cascade_irq == NO_IRQ) diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 86ad8128963..b316794aa2b 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -2,7 +2,7 @@ * Contains register definitions common to the Book E PowerPC * specification. Notice that while the IBM-40x series of CPUs * are not true Book E PowerPCs, they borrowed a number of features - * before Book E was finalized, and are included here as well. Unfortunatly, + * before Book E was finalized, and are included here as well. Unfortunately, * they sometimes used different locations than true Book E CPUs did. * * This program is free software; you can redistribute it and/or @@ -110,7 +110,7 @@ #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ -#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ +#define SPRN_MAS5 0x153 /* MMU Assist Register 5 */ #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ #define SPRN_PID1 0x279 /* Process ID Register 1 */ #define SPRN_PID2 0x27A /* Process ID Register 2 */ diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h index 66e237bbe15..a902a0d3ae0 100644 --- a/arch/powerpc/include/asm/smp.h +++ b/arch/powerpc/include/asm/smp.h @@ -36,15 +36,16 @@ extern void cpu_die(void); extern void smp_send_debugger_break(int cpu); extern void smp_message_recv(int); +extern void start_secondary_resume(void); DECLARE_PER_CPU(unsigned int, cpu_pvr); #ifdef CONFIG_HOTPLUG_CPU -extern void fixup_irqs(const struct cpumask *map); +extern void migrate_irqs(void); int generic_cpu_disable(void); -int generic_cpu_enable(unsigned int cpu); void generic_cpu_die(unsigned int cpu); void generic_mach_cpu_die(void); +void generic_set_cpu_dead(unsigned int cpu); #endif #ifdef CONFIG_PPC64 diff --git a/arch/powerpc/include/asm/spu_priv1.h b/arch/powerpc/include/asm/spu_priv1.h index 25020a34ce7..d8f5c60f61c 100644 --- a/arch/powerpc/include/asm/spu_priv1.h +++ b/arch/powerpc/include/asm/spu_priv1.h @@ -223,7 +223,7 @@ spu_disable_spu (struct spu_context *ctx) } /* - * The declarations folowing are put here for convenience + * The declarations following are put here for convenience * and only intended to be used by the platform setup code. */ diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h index aa0f1ebb4aa..60f64b132bd 100644 --- a/arch/powerpc/include/asm/systbl.h +++ b/arch/powerpc/include/asm/systbl.h @@ -348,3 +348,7 @@ COMPAT_SYS_SPU(sendmsg) COMPAT_SYS_SPU(recvmsg) COMPAT_SYS_SPU(recvmmsg) SYSCALL_SPU(accept4) +SYSCALL_SPU(name_to_handle_at) +COMPAT_SYS_SPU(open_by_handle_at) +COMPAT_SYS_SPU(clock_adjtime) +SYSCALL_SPU(syncfs) diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h index 65eb85976a0..d8529ef13b2 100644 --- a/arch/powerpc/include/asm/thread_info.h +++ b/arch/powerpc/include/asm/thread_info.h @@ -72,7 +72,7 @@ struct thread_info { #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR -extern struct thread_info *alloc_thread_info(struct task_struct *tsk); +extern struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node); extern void free_thread_info(struct thread_info *ti); #endif /* THREAD_SHIFT < PAGE_SHIFT */ diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h index a5aea0ca34e..8947b9827bc 100644 --- a/arch/powerpc/include/asm/types.h +++ b/arch/powerpc/include/asm/types.h @@ -44,13 +44,6 @@ typedef struct { typedef __vector128 vector128; -#if defined(__powerpc64__) || defined(CONFIG_PHYS_64BIT) -typedef u64 dma_addr_t; -#else -typedef u32 dma_addr_t; -#endif -typedef u64 dma64_addr_t; - typedef struct { unsigned long entry; unsigned long toc; diff --git a/arch/powerpc/include/asm/uninorth.h b/arch/powerpc/include/asm/uninorth.h index f737732c386..d12b11d7641 100644 --- a/arch/powerpc/include/asm/uninorth.h +++ b/arch/powerpc/include/asm/uninorth.h @@ -60,7 +60,7 @@ * * Obviously, the GART is not cache coherent and so any change to it * must be flushed to memory (or maybe just make the GART space non - * cachable). AGP memory itself doens't seem to be cache coherent neither. + * cachable). AGP memory itself doesn't seem to be cache coherent neither. * * In order to invalidate the GART (which is probably necessary to inval * the bridge internal TLBs), the following sequence has to be written, diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h index 6151937657f..3c215648ce6 100644 --- a/arch/powerpc/include/asm/unistd.h +++ b/arch/powerpc/include/asm/unistd.h @@ -367,10 +367,14 @@ #define __NR_recvmsg 342 #define __NR_recvmmsg 343 #define __NR_accept4 344 +#define __NR_name_to_handle_at 345 +#define __NR_open_by_handle_at 346 +#define __NR_clock_adjtime 347 +#define __NR_syncfs 348 #ifdef __KERNEL__ -#define __NR_syscalls 345 +#define __NR_syscalls 349 #define __NR__exit __NR_exit #define NR_syscalls __NR_syscalls diff --git a/arch/powerpc/include/asm/vdso_datapage.h b/arch/powerpc/include/asm/vdso_datapage.h index 25e39220e89..b73a8199f16 100644 --- a/arch/powerpc/include/asm/vdso_datapage.h +++ b/arch/powerpc/include/asm/vdso_datapage.h @@ -57,7 +57,7 @@ struct vdso_data { } version; /* Note about the platform flags: it now only contains the lpar - * bit. The actual platform number is dead and burried + * bit. The actual platform number is dead and buried */ __u32 platform; /* Platform flags 0x18 */ __u32 processor; /* Processor type 0x1C */ diff --git a/arch/powerpc/kernel/btext.c b/arch/powerpc/kernel/btext.c index 625942ae558..60b3e377b1e 100644 --- a/arch/powerpc/kernel/btext.c +++ b/arch/powerpc/kernel/btext.c @@ -99,7 +99,7 @@ void __init btext_prepare_BAT(void) /* This function can be used to enable the early boot text when doing * OF booting or within bootx init. It must be followed by a btext_unmap() - * call before the logical address becomes unuseable + * call before the logical address becomes unusable */ void __init btext_setup_display(int width, int height, int depth, int pitch, unsigned long address) diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index 5c518ad3445..913611105c1 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -64,7 +64,7 @@ _GLOBAL(__setup_cpu_e500v2) bl __e500_icache_setup bl __e500_dcache_setup bl __setup_e500_ivors -#ifdef CONFIG_RAPIDIO +#ifdef CONFIG_FSL_RIO /* Ensure that RFXE is set */ mfspr r3,SPRN_HID1 oris r3,r3,HID1_RFXE@h diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index c9b68d07ac4..b9602ee06de 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -1973,7 +1973,7 @@ static struct cpu_spec __initdata cpu_specs[] = { .pvr_mask = 0xffff0000, .pvr_value = 0x80240000, .cpu_name = "e5500", - .cpu_features = CPU_FTRS_E500MC, + .cpu_features = CPU_FTRS_E5500, .cpu_user_features = COMMON_USER_BOOKE, .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | MMU_FTR_USE_TLBILX, diff --git a/arch/powerpc/kernel/crash.c b/arch/powerpc/kernel/crash.c index 3d569e2aff1..5b5e1f002a8 100644 --- a/arch/powerpc/kernel/crash.c +++ b/arch/powerpc/kernel/crash.c @@ -188,7 +188,7 @@ static void crash_kexec_wait_realmode(int cpu) } mb(); } -#endif +#endif /* CONFIG_PPC_STD_MMU_64 */ /* * This function will be called by secondary cpus or by kexec cpu @@ -233,7 +233,9 @@ void crash_kexec_secondary(struct pt_regs *regs) crash_ipi_callback(regs); } -#else +#else /* ! CONFIG_SMP */ +static inline void crash_kexec_wait_realmode(int cpu) {} + static void crash_kexec_prepare_cpus(int cpu) { /* @@ -253,7 +255,7 @@ void crash_kexec_secondary(struct pt_regs *regs) { cpus_in_sr = CPU_MASK_NONE; } -#endif +#endif /* CONFIG_SMP */ /* * Register a function to be called on shutdown. Only use this if you @@ -344,9 +346,7 @@ void default_machine_crash_shutdown(struct pt_regs *regs) crash_save_cpu(regs, crashing_cpu); crash_kexec_prepare_cpus(crashing_cpu); cpu_set(crashing_cpu, cpus_in_crash); -#if defined(CONFIG_PPC_STD_MMU_64) && defined(CONFIG_SMP) crash_kexec_wait_realmode(crashing_cpu); -#endif machine_kexec_mask_interrupts(); diff --git a/arch/powerpc/kernel/crash_dump.c b/arch/powerpc/kernel/crash_dump.c index 0a2af50243c..424afb6b8fb 100644 --- a/arch/powerpc/kernel/crash_dump.c +++ b/arch/powerpc/kernel/crash_dump.c @@ -28,9 +28,6 @@ #define DBG(fmt...) #endif -/* Stores the physical address of elf header of crash image. */ -unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX; - #ifndef CONFIG_RELOCATABLE void __init reserve_kdump_trampoline(void) { @@ -72,20 +69,6 @@ void __init setup_kdump_trampoline(void) } #endif /* CONFIG_RELOCATABLE */ -/* - * Note: elfcorehdr_addr is not just limited to vmcore. It is also used by - * is_kdump_kernel() to determine if we are booting after a panic. Hence - * ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE. - */ -static int __init parse_elfcorehdr(char *p) -{ - if (p) - elfcorehdr_addr = memparse(p, &p); - - return 1; -} -__setup("elfcorehdr=", parse_elfcorehdr); - static int __init parse_savemaxmem(char *p) { if (p) diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c index cf02cad62d9..d238c082c3c 100644 --- a/arch/powerpc/kernel/dma.c +++ b/arch/powerpc/kernel/dma.c @@ -179,3 +179,21 @@ static int __init dma_init(void) return 0; } fs_initcall(dma_init); + +int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, + void *cpu_addr, dma_addr_t handle, size_t size) +{ + unsigned long pfn; + +#ifdef CONFIG_NOT_COHERENT_CACHE + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + pfn = __dma_get_coherent_pfn((unsigned long)cpu_addr); +#else + pfn = page_to_pfn(virt_to_page(cpu_addr)); +#endif + return remap_pfn_range(vma, vma->vm_start, + pfn + vma->vm_pgoff, + vma->vm_end - vma->vm_start, + vma->vm_page_prot); +} +EXPORT_SYMBOL_GPL(dma_mmap_coherent); diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S index 5c43063d250..9651acc3504 100644 --- a/arch/powerpc/kernel/exceptions-64e.S +++ b/arch/powerpc/kernel/exceptions-64e.S @@ -379,7 +379,7 @@ interrupt_end_book3e: mfspr r13,SPRN_SPRG_PACA /* get our PACA */ b system_call_common -/* Auxillary Processor Unavailable Interrupt */ +/* Auxiliary Processor Unavailable Interrupt */ START_EXCEPTION(ap_unavailable); NORMAL_EXCEPTION_PROLOG(0xf20, PROLOG_ADDITION_NONE) EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_KEEP) diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index 8a817995b4c..aeb739e1876 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -5,7 +5,7 @@ * handling and other fixed offset specific things. * * This file is meant to be #included from head_64.S due to - * position dependant assembly. + * position dependent assembly. * * Most of this originates from head_64.S and thus has the same * copyright history. @@ -977,20 +977,6 @@ _GLOBAL(do_stab_bolted) rfid b . /* prevent speculative execution */ -/* - * Space for CPU0's segment table. - * - * On iSeries, the hypervisor must fill in at least one entry before - * we get control (with relocate on). The address is given to the hv - * as a page number (see xLparMap below), so this must be at a - * fixed address (the linker can't compute (u64)&initial_stab >> - * PAGE_SHIFT). - */ - . = STAB0_OFFSET /* 0x6000 */ - .globl initial_stab -initial_stab: - .space 4096 - #ifdef CONFIG_PPC_PSERIES /* * Data area reserved for FWNMI option. @@ -1027,3 +1013,17 @@ xLparMap: #ifdef CONFIG_PPC_PSERIES . = 0x8000 #endif /* CONFIG_PPC_PSERIES */ + +/* + * Space for CPU0's segment table. + * + * On iSeries, the hypervisor must fill in at least one entry before + * we get control (with relocate on). The address is given to the hv + * as a page number (see xLparMap above), so this must be at a + * fixed address (the linker can't compute (u64)&initial_stab >> + * PAGE_SHIFT). + */ + . = STAB0_OFFSET /* 0x8000 */ + .globl initial_stab +initial_stab: + .space 4096 diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index 98c4b29a56f..c5c24beb838 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -890,6 +890,15 @@ __secondary_start: mtspr SPRN_SRR1,r4 SYNC RFI + +_GLOBAL(start_secondary_resume) + /* Reset stack */ + rlwinm r1,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */ + addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD + li r3,0 + std r3,0(r1) /* Zero the stack frame pointer */ + bl start_secondary + b . #endif /* CONFIG_SMP */ #ifdef CONFIG_KVM_BOOK3S_HANDLER diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S index 9dd21a8c4d5..a91626d87fc 100644 --- a/arch/powerpc/kernel/head_40x.S +++ b/arch/powerpc/kernel/head_40x.S @@ -766,7 +766,7 @@ DataAccess: * miss get to this point to load the TLB. * r10 - TLB_TAG value * r11 - Linux PTE - * r12, r9 - avilable to use + * r12, r9 - available to use * PID - loaded with proper value when we get here * Upon exit, we reload everything and RFI. * Actually, it will fit now, but oh well.....a common place diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index cbb3436b592..5e12b741ba5 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -178,7 +178,7 @@ interrupt_base: NORMAL_EXCEPTION_PROLOG EXC_XFER_EE_LITE(0x0c00, DoSyscall) - /* Auxillary Processor Unavailable Interrupt */ + /* Auxiliary Processor Unavailable Interrupt */ EXCEPTION(0x2020, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE) /* Decrementer Interrupt */ diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index 782f23df7c8..3a319f9c9d3 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -40,7 +40,7 @@ #include <asm/kvm_book3s_asm.h> #include <asm/ptrace.h> -/* The physical memory is layed out such that the secondary processor +/* The physical memory is laid out such that the secondary processor * spin code sits at 0x0000...0x00ff. On server, the vectors follow * using the layout described in exceptions-64s.S */ @@ -536,6 +536,13 @@ _GLOBAL(pmac_secondary_start) add r13,r13,r4 /* for this processor. */ mtspr SPRN_SPRG_PACA,r13 /* Save vaddr of paca in an SPRG*/ + /* Mark interrupts soft and hard disabled (they might be enabled + * in the PACA when doing hotplug) + */ + li r0,0 + stb r0,PACASOFTIRQEN(r13) + stb r0,PACAHARDIRQEN(r13) + /* Create a temp kernel stack for use before relocation is on. */ ld r1,PACAEMERGSP(r13) subi r1,r1,STACK_FRAME_OVERHEAD diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index 3e02710d956..5ecf54cfa7d 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -326,7 +326,7 @@ interrupt_base: NORMAL_EXCEPTION_PROLOG EXC_XFER_EE_LITE(0x0c00, DoSyscall) - /* Auxillary Processor Unavailable Interrupt */ + /* Auxiliary Processor Unavailable Interrupt */ EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE) /* Decrementer Interrupt */ diff --git a/arch/powerpc/kernel/ibmebus.c b/arch/powerpc/kernel/ibmebus.c index c00d4ca1ee1..28581f1ad2c 100644 --- a/arch/powerpc/kernel/ibmebus.c +++ b/arch/powerpc/kernel/ibmebus.c @@ -527,7 +527,7 @@ static int ibmebus_bus_pm_resume_noirq(struct device *dev) #endif /* !CONFIG_SUSPEND */ -#ifdef CONFIG_HIBERNATION +#ifdef CONFIG_HIBERNATE_CALLBACKS static int ibmebus_bus_pm_freeze(struct device *dev) { @@ -665,7 +665,7 @@ static int ibmebus_bus_pm_restore_noirq(struct device *dev) return ret; } -#else /* !CONFIG_HIBERNATION */ +#else /* !CONFIG_HIBERNATE_CALLBACKS */ #define ibmebus_bus_pm_freeze NULL #define ibmebus_bus_pm_thaw NULL @@ -676,7 +676,7 @@ static int ibmebus_bus_pm_restore_noirq(struct device *dev) #define ibmebus_bus_pm_poweroff_noirq NULL #define ibmebus_bus_pm_restore_noirq NULL -#endif /* !CONFIG_HIBERNATION */ +#endif /* !CONFIG_HIBERNATE_CALLBACKS */ static struct dev_pm_ops ibmebus_bus_dev_pm_ops = { .prepare = ibmebus_bus_pm_prepare, diff --git a/arch/powerpc/kernel/idle_power4.S b/arch/powerpc/kernel/idle_power4.S index 5328709eeed..ba319547860 100644 --- a/arch/powerpc/kernel/idle_power4.S +++ b/arch/powerpc/kernel/idle_power4.S @@ -53,24 +53,3 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) isync b 1b -_GLOBAL(power4_cpu_offline_powersave) - /* Go to NAP now */ - mfmsr r7 - rldicl r0,r7,48,1 - rotldi r0,r0,16 - mtmsrd r0,1 /* hard-disable interrupts */ - li r0,1 - li r6,0 - stb r0,PACAHARDIRQEN(r13) /* we'll hard-enable shortly */ - stb r6,PACASOFTIRQEN(r13) /* soft-disable irqs */ -BEGIN_FTR_SECTION - DSSALL - sync -END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) - ori r7,r7,MSR_EE - oris r7,r7,MSR_POW@h - sync - isync - mtmsrd r7 - isync - blr diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index 0a5570338b9..f621b7d2d86 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c @@ -195,7 +195,7 @@ notrace void arch_local_irq_restore(unsigned long en) EXPORT_SYMBOL(arch_local_irq_restore); #endif /* CONFIG_PPC64 */ -static int show_other_interrupts(struct seq_file *p, int prec) +int arch_show_interrupts(struct seq_file *p, int prec) { int j; @@ -231,65 +231,6 @@ static int show_other_interrupts(struct seq_file *p, int prec) return 0; } -int show_interrupts(struct seq_file *p, void *v) -{ - unsigned long flags, any_count = 0; - int i = *(loff_t *) v, j, prec; - struct irqaction *action; - struct irq_desc *desc; - struct irq_chip *chip; - - if (i > nr_irqs) - return 0; - - for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec) - j *= 10; - - if (i == nr_irqs) - return show_other_interrupts(p, prec); - - /* print header */ - if (i == 0) { - seq_printf(p, "%*s", prec + 8, ""); - for_each_online_cpu(j) - seq_printf(p, "CPU%-8d", j); - seq_putc(p, '\n'); - } - - desc = irq_to_desc(i); - if (!desc) - return 0; - - raw_spin_lock_irqsave(&desc->lock, flags); - for_each_online_cpu(j) - any_count |= kstat_irqs_cpu(i, j); - action = desc->action; - if (!action && !any_count) - goto out; - - seq_printf(p, "%*d: ", prec, i); - for_each_online_cpu(j) - seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); - - chip = get_irq_desc_chip(desc); - if (chip) - seq_printf(p, " %-16s", chip->name); - else - seq_printf(p, " %-16s", "None"); - seq_printf(p, " %-8s", (desc->status & IRQ_LEVEL) ? "Level" : "Edge"); - - if (action) { - seq_printf(p, " %s", action->name); - while ((action = action->next) != NULL) - seq_printf(p, ", %s", action->name); - } - - seq_putc(p, '\n'); -out: - raw_spin_unlock_irqrestore(&desc->lock, flags); - return 0; -} - /* * /proc/stat helpers */ @@ -305,34 +246,37 @@ u64 arch_irq_stat_cpu(unsigned int cpu) } #ifdef CONFIG_HOTPLUG_CPU -void fixup_irqs(const struct cpumask *map) +void migrate_irqs(void) { struct irq_desc *desc; unsigned int irq; static int warned; cpumask_var_t mask; + const struct cpumask *map = cpu_online_mask; alloc_cpumask_var(&mask, GFP_KERNEL); for_each_irq(irq) { + struct irq_data *data; struct irq_chip *chip; desc = irq_to_desc(irq); if (!desc) continue; - if (desc->status & IRQ_PER_CPU) + data = irq_desc_get_irq_data(desc); + if (irqd_is_per_cpu(data)) continue; - chip = get_irq_desc_chip(desc); + chip = irq_data_get_irq_chip(data); - cpumask_and(mask, desc->irq_data.affinity, map); + cpumask_and(mask, data->affinity, map); if (cpumask_any(mask) >= nr_cpu_ids) { printk("Breaking affinity for irq %i\n", irq); cpumask_copy(mask, map); } if (chip->irq_set_affinity) - chip->irq_set_affinity(&desc->irq_data, mask, true); + chip->irq_set_affinity(data, mask, true); else if (desc->action && !(warned++)) printk("Cannot set affinity for irq %i\n", irq); } @@ -618,7 +562,7 @@ struct irq_host *irq_alloc_host(struct device_node *of_node, smp_wmb(); /* Clear norequest flags */ - irq_to_desc(i)->status &= ~IRQ_NOREQUEST; + irq_clear_status_flags(i, IRQ_NOREQUEST); /* Legacy flags are left to default at this point, * one can then use irq_create_mapping() to @@ -827,8 +771,8 @@ unsigned int irq_create_of_mapping(struct device_node *controller, /* Set type if specified and different than the current one */ if (type != IRQ_TYPE_NONE && - type != (irq_to_desc(virq)->status & IRQF_TRIGGER_MASK)) - set_irq_type(virq, type); + type != (irqd_get_trigger_type(irq_get_irq_data(virq)))) + irq_set_irq_type(virq, type); return virq; } EXPORT_SYMBOL_GPL(irq_create_of_mapping); @@ -851,7 +795,7 @@ void irq_dispose_mapping(unsigned int virq) return; /* remove chip and handler */ - set_irq_chip_and_handler(virq, NULL, NULL); + irq_set_chip_and_handler(virq, NULL, NULL); /* Make sure it's completed */ synchronize_irq(virq); @@ -1156,7 +1100,7 @@ static int virq_debug_show(struct seq_file *m, void *private) seq_printf(m, "%5d ", i); seq_printf(m, "0x%05lx ", virq_to_hw(i)); - chip = get_irq_desc_chip(desc); + chip = irq_desc_get_chip(desc); if (chip && chip->name) p = chip->name; else diff --git a/arch/powerpc/kernel/l2cr_6xx.S b/arch/powerpc/kernel/l2cr_6xx.S index 2a2f3c3f6d8..97ec8557f97 100644 --- a/arch/powerpc/kernel/l2cr_6xx.S +++ b/arch/powerpc/kernel/l2cr_6xx.S @@ -151,7 +151,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) /**** Might be a good idea to set L2DO here - to prevent instructions from getting into the cache. But since we invalidate the next time we enable the cache it doesn't really matter. - Don't do this unless you accomodate all processor variations. + Don't do this unless you accommodate all processor variations. The bit moved on the 7450..... ****/ diff --git a/arch/powerpc/kernel/legacy_serial.c b/arch/powerpc/kernel/legacy_serial.c index c834757bebc..2b97b80d6d7 100644 --- a/arch/powerpc/kernel/legacy_serial.c +++ b/arch/powerpc/kernel/legacy_serial.c @@ -330,9 +330,11 @@ void __init find_legacy_serial_ports(void) if (!parent) continue; if (of_match_node(legacy_serial_parents, parent) != NULL) { - index = add_legacy_soc_port(np, np); - if (index >= 0 && np == stdout) - legacy_serial_console = index; + if (of_device_is_available(np)) { + index = add_legacy_soc_port(np, np); + if (index >= 0 && np == stdout) + legacy_serial_console = index; + } } of_node_put(parent); } diff --git a/arch/powerpc/kernel/lparcfg.c b/arch/powerpc/kernel/lparcfg.c index 16468362ad5..301db65f05a 100644 --- a/arch/powerpc/kernel/lparcfg.c +++ b/arch/powerpc/kernel/lparcfg.c @@ -262,7 +262,7 @@ static void parse_ppp_data(struct seq_file *m) seq_printf(m, "system_active_processors=%d\n", ppp_data.active_system_procs); - /* pool related entries are apropriate for shared configs */ + /* pool related entries are appropriate for shared configs */ if (lppaca_of(0).shared_proc) { unsigned long pool_idle_time, pool_procs; diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c index bd1e1ff17b2..7ee50f0547c 100644 --- a/arch/powerpc/kernel/machine_kexec.c +++ b/arch/powerpc/kernel/machine_kexec.c @@ -31,17 +31,17 @@ void machine_kexec_mask_interrupts(void) { if (!desc) continue; - chip = get_irq_desc_chip(desc); + chip = irq_desc_get_chip(desc); if (!chip) continue; - if (chip->irq_eoi && desc->status & IRQ_INPROGRESS) + if (chip->irq_eoi && irqd_irq_inprogress(&desc->irq_data)) chip->irq_eoi(&desc->irq_data); if (chip->irq_mask) chip->irq_mask(&desc->irq_data); - if (chip->irq_disable && !(desc->status & IRQ_DISABLED)) + if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data)) chip->irq_disable(&desc->irq_data); } } diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c index f4adf89d761..10f0aadee95 100644 --- a/arch/powerpc/kernel/paca.c +++ b/arch/powerpc/kernel/paca.c @@ -203,7 +203,7 @@ void __init free_unused_pacas(void) { int new_size; - new_size = PAGE_ALIGN(sizeof(struct paca_struct) * num_possible_cpus()); + new_size = PAGE_ALIGN(sizeof(struct paca_struct) * nr_cpu_ids); if (new_size >= paca_size) return; diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c index 3cd85faa8ac..893af2a9cd0 100644 --- a/arch/powerpc/kernel/pci-common.c +++ b/arch/powerpc/kernel/pci-common.c @@ -261,7 +261,7 @@ int pci_read_irq_line(struct pci_dev *pci_dev) virq = irq_create_mapping(NULL, line); if (virq != NO_IRQ) - set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); } else { pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", oirq.size, oirq.specifier[0], oirq.specifier[1], diff --git a/arch/powerpc/kernel/pci_dn.c b/arch/powerpc/kernel/pci_dn.c index 29852688cea..d225d99fe39 100644 --- a/arch/powerpc/kernel/pci_dn.c +++ b/arch/powerpc/kernel/pci_dn.c @@ -176,11 +176,14 @@ static void *is_devfn_node(struct device_node *dn, void *data) */ struct device_node *fetch_dev_dn(struct pci_dev *dev) { - struct device_node *orig_dn = dev->dev.of_node; + struct pci_controller *phb = dev->sysdata; struct device_node *dn; unsigned long searchval = (dev->bus->number << 8) | dev->devfn; - dn = traverse_pci_devices(orig_dn, is_devfn_node, (void *)searchval); + if (WARN_ON(!phb)) + return NULL; + + dn = traverse_pci_devices(phb->dn, is_devfn_node, (void *)searchval); if (dn) dev->dev.of_node = dn; return dn; diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/kernel/perf_event.c index 97e0ae41494..822f63008ae 100644 --- a/arch/powerpc/kernel/perf_event.c +++ b/arch/powerpc/kernel/perf_event.c @@ -398,6 +398,25 @@ static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], return 0; } +static u64 check_and_compute_delta(u64 prev, u64 val) +{ + u64 delta = (val - prev) & 0xfffffffful; + + /* + * POWER7 can roll back counter values, if the new value is smaller + * than the previous value it will cause the delta and the counter to + * have bogus values unless we rolled a counter over. If a coutner is + * rolled back, it will be smaller, but within 256, which is the maximum + * number of events to rollback at once. If we dectect a rollback + * return 0. This can lead to a small lack of precision in the + * counters. + */ + if (prev > val && (prev - val) < 256) + delta = 0; + + return delta; +} + static void power_pmu_read(struct perf_event *event) { s64 val, delta, prev; @@ -416,10 +435,11 @@ static void power_pmu_read(struct perf_event *event) prev = local64_read(&event->hw.prev_count); barrier(); val = read_pmc(event->hw.idx); + delta = check_and_compute_delta(prev, val); + if (!delta) + return; } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); - /* The counters are only 32 bits wide */ - delta = (val - prev) & 0xfffffffful; local64_add(delta, &event->count); local64_sub(delta, &event->hw.period_left); } @@ -449,8 +469,9 @@ static void freeze_limited_counters(struct cpu_hw_events *cpuhw, val = (event->hw.idx == 5) ? pmc5 : pmc6; prev = local64_read(&event->hw.prev_count); event->hw.idx = 0; - delta = (val - prev) & 0xfffffffful; - local64_add(delta, &event->count); + delta = check_and_compute_delta(prev, val); + if (delta) + local64_add(delta, &event->count); } } @@ -458,14 +479,16 @@ static void thaw_limited_counters(struct cpu_hw_events *cpuhw, unsigned long pmc5, unsigned long pmc6) { struct perf_event *event; - u64 val; + u64 val, prev; int i; for (i = 0; i < cpuhw->n_limited; ++i) { event = cpuhw->limited_counter[i]; event->hw.idx = cpuhw->limited_hwidx[i]; val = (event->hw.idx == 5) ? pmc5 : pmc6; - local64_set(&event->hw.prev_count, val); + prev = local64_read(&event->hw.prev_count); + if (check_and_compute_delta(prev, val)) + local64_set(&event->hw.prev_count, val); perf_event_update_userpage(event); } } @@ -759,7 +782,7 @@ static int power_pmu_add(struct perf_event *event, int ef_flags) /* * If group events scheduling transaction was started, - * skip the schedulability test here, it will be peformed + * skip the schedulability test here, it will be performed * at commit time(->commit_txn) as a whole */ if (cpuhw->group_flag & PERF_EVENT_TXN) @@ -1197,7 +1220,7 @@ static void record_and_restart(struct perf_event *event, unsigned long val, /* we don't have to worry about interrupts here */ prev = local64_read(&event->hw.prev_count); - delta = (val - prev) & 0xfffffffful; + delta = check_and_compute_delta(prev, val); local64_add(delta, &event->count); /* diff --git a/arch/powerpc/kernel/ppc_save_regs.S b/arch/powerpc/kernel/ppc_save_regs.S index e83ba3f078e..1b1787d5289 100644 --- a/arch/powerpc/kernel/ppc_save_regs.S +++ b/arch/powerpc/kernel/ppc_save_regs.S @@ -15,7 +15,7 @@ /* * Grab the register values as they are now. - * This won't do a particularily good job because we really + * This won't do a particularly good job because we really * want our caller's caller's registers, and our caller has * already executed its prologue. * ToDo: We could reach back into the caller's save area to do diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 8303a6c65ef..f74f355a961 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -1218,11 +1218,11 @@ void __ppc64_runlatch_off(void) static struct kmem_cache *thread_info_cache; -struct thread_info *alloc_thread_info(struct task_struct *tsk) +struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node) { struct thread_info *ti; - ti = kmem_cache_alloc(thread_info_cache, GFP_KERNEL); + ti = kmem_cache_alloc_node(thread_info_cache, GFP_KERNEL, node); if (unlikely(ti == NULL)) return NULL; #ifdef CONFIG_DEBUG_STACK_USAGE diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index 05b7139d6a2..e74fa12afc8 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c @@ -683,7 +683,7 @@ void __init early_init_devtree(void *params) #endif #ifdef CONFIG_PHYP_DUMP - /* scan tree to see if dump occured during last boot */ + /* scan tree to see if dump occurred during last boot */ of_scan_flat_dt(early_init_dt_scan_phyp_dump, NULL); #endif @@ -739,7 +739,7 @@ void __init early_init_devtree(void *params) DBG("Scanning CPUs ...\n"); - /* Retreive CPU related informations from the flat tree + /* Retrieve CPU related informations from the flat tree * (altivec support, boot CPU ID, ...) */ of_scan_flat_dt(early_init_dt_scan_cpus, NULL); diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c index 90653699829..a6ae1cfad86 100644 --- a/arch/powerpc/kernel/ptrace.c +++ b/arch/powerpc/kernel/ptrace.c @@ -229,12 +229,16 @@ static int gpr_get(struct task_struct *target, const struct user_regset *regset, unsigned int pos, unsigned int count, void *kbuf, void __user *ubuf) { - int ret; + int i, ret; if (target->thread.regs == NULL) return -EIO; - CHECK_FULL_REGS(target->thread.regs); + if (!FULL_REGS(target->thread.regs)) { + /* We have a partial register set. Fill 14-31 with bogus values */ + for (i = 14; i < 32; i++) + target->thread.regs->gpr[i] = NV_REG_POISON; + } ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, target->thread.regs, @@ -459,7 +463,7 @@ static int vr_set(struct task_struct *target, const struct user_regset *regset, #ifdef CONFIG_VSX /* * Currently to set and and get all the vsx state, you need to call - * the fp and VMX calls aswell. This only get/sets the lower 32 + * the fp and VMX calls as well. This only get/sets the lower 32 * 128bit VSX registers. */ @@ -641,11 +645,16 @@ static int gpr32_get(struct task_struct *target, compat_ulong_t *k = kbuf; compat_ulong_t __user *u = ubuf; compat_ulong_t reg; + int i; if (target->thread.regs == NULL) return -EIO; - CHECK_FULL_REGS(target->thread.regs); + if (!FULL_REGS(target->thread.regs)) { + /* We have a partial register set. Fill 14-31 with bogus values */ + for (i = 14; i < 32; i++) + target->thread.regs->gpr[i] = NV_REG_POISON; + } pos /= sizeof(reg); count /= sizeof(reg); @@ -924,12 +933,16 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, if (data && !(data & DABR_TRANSLATION)) return -EIO; #ifdef CONFIG_HAVE_HW_BREAKPOINT + if (ptrace_get_breakpoints(task) < 0) + return -ESRCH; + bp = thread->ptrace_bps[0]; if ((!data) || !(data & (DABR_DATA_WRITE | DABR_DATA_READ))) { if (bp) { unregister_hw_breakpoint(bp); thread->ptrace_bps[0] = NULL; } + ptrace_put_breakpoints(task); return 0; } if (bp) { @@ -939,9 +952,12 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, (DABR_DATA_WRITE | DABR_DATA_READ), &attr.bp_type); ret = modify_user_hw_breakpoint(bp, &attr); - if (ret) + if (ret) { + ptrace_put_breakpoints(task); return ret; + } thread->ptrace_bps[0] = bp; + ptrace_put_breakpoints(task); thread->dabr = data; return 0; } @@ -956,9 +972,12 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, ptrace_triggered, task); if (IS_ERR(bp)) { thread->ptrace_bps[0] = NULL; + ptrace_put_breakpoints(task); return PTR_ERR(bp); } + ptrace_put_breakpoints(task); + #endif /* CONFIG_HAVE_HW_BREAKPOINT */ /* Move contents to the DABR register */ diff --git a/arch/powerpc/kernel/rtasd.c b/arch/powerpc/kernel/rtasd.c index 7980ec0e1e1..67f6c3b5135 100644 --- a/arch/powerpc/kernel/rtasd.c +++ b/arch/powerpc/kernel/rtasd.c @@ -465,7 +465,7 @@ static void start_event_scan(void) pr_debug("rtasd: will sleep for %d milliseconds\n", (30000 / rtas_event_scan_rate)); - /* Retreive errors from nvram if any */ + /* Retrieve errors from nvram if any */ retreive_nvram_error_log(); schedule_delayed_work_on(cpumask_first(cpu_online_mask), diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c index 9d4882a4664..21f30cb6807 100644 --- a/arch/powerpc/kernel/setup-common.c +++ b/arch/powerpc/kernel/setup-common.c @@ -509,6 +509,9 @@ void __init smp_setup_cpu_maps(void) */ cpu_init_thread_core_maps(nthreads); + /* Now that possible cpus are set, set nr_cpu_ids for later use */ + nr_cpu_ids = find_last_bit(cpumask_bits(cpu_possible_mask),NR_CPUS) + 1; + free_unused_pacas(); } #endif /* CONFIG_SMP */ diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index 98136050917..cbdbb14be4b 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -57,6 +57,25 @@ #define DBG(fmt...) #endif + +/* Store all idle threads, this can be reused instead of creating +* a new thread. Also avoids complicated thread destroy functionality +* for idle threads. +*/ +#ifdef CONFIG_HOTPLUG_CPU +/* + * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is + * removed after init for !CONFIG_HOTPLUG_CPU. + */ +static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); +#define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) +#define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) +#else +static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; +#define get_idle_for_cpu(x) (idle_thread_array[(x)]) +#define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) +#endif + struct thread_info *secondary_ti; DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); @@ -238,23 +257,6 @@ static void __devinit smp_store_cpu_info(int id) per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR); } -static void __init smp_create_idle(unsigned int cpu) -{ - struct task_struct *p; - - /* create a process for the processor */ - p = fork_idle(cpu); - if (IS_ERR(p)) - panic("failed fork for CPU %u: %li", cpu, PTR_ERR(p)); -#ifdef CONFIG_PPC64 - paca[cpu].__current = p; - paca[cpu].kstack = (unsigned long) task_thread_info(p) - + THREAD_SIZE - STACK_FRAME_OVERHEAD; -#endif - current_set[cpu] = task_thread_info(p); - task_thread_info(p)->cpu = cpu; -} - void __init smp_prepare_cpus(unsigned int max_cpus) { unsigned int cpu; @@ -288,10 +290,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus) max_cpus = NR_CPUS; else max_cpus = 1; - - for_each_possible_cpu(cpu) - if (cpu != boot_cpuid) - smp_create_idle(cpu); } void __devinit smp_prepare_boot_cpu(void) @@ -305,7 +303,7 @@ void __devinit smp_prepare_boot_cpu(void) #ifdef CONFIG_HOTPLUG_CPU /* State of each CPU during hotplug phases */ -DEFINE_PER_CPU(int, cpu_state) = { 0 }; +static DEFINE_PER_CPU(int, cpu_state) = { 0 }; int generic_cpu_disable(void) { @@ -317,30 +315,8 @@ int generic_cpu_disable(void) set_cpu_online(cpu, false); #ifdef CONFIG_PPC64 vdso_data->processorCount--; - fixup_irqs(cpu_online_mask); -#endif - return 0; -} - -int generic_cpu_enable(unsigned int cpu) -{ - /* Do the normal bootup if we haven't - * already bootstrapped. */ - if (system_state != SYSTEM_RUNNING) - return -ENOSYS; - - /* get the target out of it's holding state */ - per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; - smp_wmb(); - - while (!cpu_online(cpu)) - cpu_relax(); - -#ifdef CONFIG_PPC64 - fixup_irqs(cpu_online_mask); - /* counter the irq disable in fixup_irqs */ - local_irq_enable(); #endif + migrate_irqs(); return 0; } @@ -362,37 +338,89 @@ void generic_mach_cpu_die(void) unsigned int cpu; local_irq_disable(); + idle_task_exit(); cpu = smp_processor_id(); printk(KERN_DEBUG "CPU%d offline\n", cpu); __get_cpu_var(cpu_state) = CPU_DEAD; smp_wmb(); while (__get_cpu_var(cpu_state) != CPU_UP_PREPARE) cpu_relax(); - set_cpu_online(cpu, true); - local_irq_enable(); +} + +void generic_set_cpu_dead(unsigned int cpu) +{ + per_cpu(cpu_state, cpu) = CPU_DEAD; } #endif -static int __devinit cpu_enable(unsigned int cpu) +struct create_idle { + struct work_struct work; + struct task_struct *idle; + struct completion done; + int cpu; +}; + +static void __cpuinit do_fork_idle(struct work_struct *work) { - if (smp_ops && smp_ops->cpu_enable) - return smp_ops->cpu_enable(cpu); + struct create_idle *c_idle = + container_of(work, struct create_idle, work); + + c_idle->idle = fork_idle(c_idle->cpu); + complete(&c_idle->done); +} + +static int __cpuinit create_idle(unsigned int cpu) +{ + struct thread_info *ti; + struct create_idle c_idle = { + .cpu = cpu, + .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), + }; + INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle); + + c_idle.idle = get_idle_for_cpu(cpu); + + /* We can't use kernel_thread since we must avoid to + * reschedule the child. We use a workqueue because + * we want to fork from a kernel thread, not whatever + * userspace process happens to be trying to online us. + */ + if (!c_idle.idle) { + schedule_work(&c_idle.work); + wait_for_completion(&c_idle.done); + } else + init_idle(c_idle.idle, cpu); + if (IS_ERR(c_idle.idle)) { + pr_err("Failed fork for CPU %u: %li", cpu, PTR_ERR(c_idle.idle)); + return PTR_ERR(c_idle.idle); + } + ti = task_thread_info(c_idle.idle); + +#ifdef CONFIG_PPC64 + paca[cpu].__current = c_idle.idle; + paca[cpu].kstack = (unsigned long)ti + THREAD_SIZE - STACK_FRAME_OVERHEAD; +#endif + ti->cpu = cpu; + current_set[cpu] = ti; - return -ENOSYS; + return 0; } int __cpuinit __cpu_up(unsigned int cpu) { - int c; + int rc, c; secondary_ti = current_set[cpu]; - if (!cpu_enable(cpu)) - return 0; if (smp_ops == NULL || (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu))) return -EINVAL; + /* Make sure we have an idle thread */ + rc = create_idle(cpu); + if (rc) + return rc; + /* Make sure callin-map entry is 0 (can be leftover a CPU * hotplug */ @@ -502,7 +530,7 @@ static struct device_node *cpu_to_l2cache(int cpu) } /* Activate a secondary processor. */ -int __devinit start_secondary(void *unused) +void __devinit start_secondary(void *unused) { unsigned int cpu = smp_processor_id(); struct device_node *l2_cache; @@ -523,6 +551,10 @@ int __devinit start_secondary(void *unused) secondary_cpu_time_init(); +#ifdef CONFIG_PPC64 + if (system_state == SYSTEM_RUNNING) + vdso_data->processorCount++; +#endif ipi_call_lock(); notify_cpu_starting(cpu); set_cpu_online(cpu, true); @@ -558,7 +590,8 @@ int __devinit start_secondary(void *unused) local_irq_enable(); cpu_idle(); - return 0; + + BUG(); } int setup_profiling_timer(unsigned int multiplier) @@ -585,7 +618,11 @@ void __init smp_cpus_done(unsigned int max_cpus) free_cpumask_var(old_mask); + if (smp_ops && smp_ops->bringup_done) + smp_ops->bringup_done(); + dump_numa_cpu_topology(); + } int arch_sd_sibling_asym_packing(void) @@ -660,5 +697,9 @@ void cpu_die(void) { if (ppc_md.cpu_die) ppc_md.cpu_die(); + + /* If we return, we re-enter start_secondary */ + start_secondary_resume(); } + #endif diff --git a/arch/powerpc/kernel/swsusp_32.S b/arch/powerpc/kernel/swsusp_32.S index b0754e23743..ba4dee3d233 100644 --- a/arch/powerpc/kernel/swsusp_32.S +++ b/arch/powerpc/kernel/swsusp_32.S @@ -143,7 +143,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) /* Disable MSR:DR to make sure we don't take a TLB or * hash miss during the copy, as our hash table will - * for a while be unuseable. For .text, we assume we are + * for a while be unusable. For .text, we assume we are * covered by a BAT. This works only for non-G5 at this * point. G5 will need a better approach, possibly using * a small temporary hash table filled with large mappings, diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c index 09d31dbf43f..f33acfd872a 100644 --- a/arch/powerpc/kernel/time.c +++ b/arch/powerpc/kernel/time.c @@ -229,6 +229,9 @@ static u64 scan_dispatch_log(u64 stop_tb) u64 stolen = 0; u64 dtb; + if (!dtl) + return 0; + if (i == vpa->dtl_idx) return 0; while (i < vpa->dtl_idx) { @@ -356,7 +359,7 @@ void account_system_vtime(struct task_struct *tsk) } get_paca()->user_time_scaled += user_scaled; - if (in_irq() || idle_task(smp_processor_id()) != tsk) { + if (in_interrupt() || idle_task(smp_processor_id()) != tsk) { account_system_time(tsk, 0, delta, sys_scaled); if (stolen) account_steal_time(stolen); @@ -577,14 +580,21 @@ void timer_interrupt(struct pt_regs * regs) struct clock_event_device *evt = &decrementer->event; u64 now; + /* Ensure a positive value is written to the decrementer, or else + * some CPUs will continue to take decrementer exceptions. + */ + set_dec(DECREMENTER_MAX); + + /* Some implementations of hotplug will get timer interrupts while + * offline, just ignore these + */ + if (!cpu_online(smp_processor_id())) + return; + trace_timer_interrupt_entry(regs); __get_cpu_var(irq_stat).timer_irqs++; - /* Ensure a positive value is written to the decrementer, or else - * some CPUs will continuue to take decrementer exceptions */ - set_dec(DECREMENTER_MAX); - #if defined(CONFIG_PPC32) && defined(CONFIG_PMAC) if (atomic_read(&ppc_n_lost_interrupts) != 0) do_IRQ(regs); diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index bd74fac169b..5ddb801bc15 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c @@ -959,7 +959,7 @@ void __kprobes program_check_exception(struct pt_regs *regs) * ESR_DST (!?) or 0. In the process of chasing this with the * hardware people - not sure if it can happen on any illegal * instruction or only on FP instructions, whether there is a - * pattern to occurences etc. -dgibson 31/Mar/2003 */ + * pattern to occurrences etc. -dgibson 31/Mar/2003 */ switch (do_mathemu(regs)) { case 0: emulate_single_step(regs); diff --git a/arch/powerpc/kernel/udbg_16550.c b/arch/powerpc/kernel/udbg_16550.c index b4b167b3364..baa33a7517b 100644 --- a/arch/powerpc/kernel/udbg_16550.c +++ b/arch/powerpc/kernel/udbg_16550.c @@ -1,5 +1,5 @@ /* - * udbg for NS16550 compatable serial ports + * udbg for NS16550 compatible serial ports * * Copyright (C) 2001-2005 PPC 64 Team, IBM Corp * diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c index fd8728729ab..142ab1008c3 100644 --- a/arch/powerpc/kernel/vdso.c +++ b/arch/powerpc/kernel/vdso.c @@ -820,17 +820,17 @@ static int __init vdso_init(void) } arch_initcall(vdso_init); -int in_gate_area_no_task(unsigned long addr) +int in_gate_area_no_mm(unsigned long addr) { return 0; } -int in_gate_area(struct task_struct *task, unsigned long addr) +int in_gate_area(struct mm_struct *mm, unsigned long addr) { return 0; } -struct vm_area_struct *get_gate_vma(struct task_struct *tsk) +struct vm_area_struct *get_gate_vma(struct mm_struct *mm) { return NULL; } diff --git a/arch/powerpc/kernel/vdso32/sigtramp.S b/arch/powerpc/kernel/vdso32/sigtramp.S index 68d49dd71dc..cf0c9c9c24f 100644 --- a/arch/powerpc/kernel/vdso32/sigtramp.S +++ b/arch/powerpc/kernel/vdso32/sigtramp.S @@ -19,7 +19,7 @@ /* The nop here is a hack. The dwarf2 unwind routines subtract 1 from the return address to get an address in the middle of the presumed - call instruction. Since we don't have a call here, we artifically + call instruction. Since we don't have a call here, we artificially extend the range covered by the unwind info by adding a nop before the real start. */ nop diff --git a/arch/powerpc/kernel/vdso64/sigtramp.S b/arch/powerpc/kernel/vdso64/sigtramp.S index 59eb59bb408..45ea281e9a2 100644 --- a/arch/powerpc/kernel/vdso64/sigtramp.S +++ b/arch/powerpc/kernel/vdso64/sigtramp.S @@ -20,7 +20,7 @@ /* The nop here is a hack. The dwarf2 unwind routines subtract 1 from the return address to get an address in the middle of the presumed - call instruction. Since we don't have a call here, we artifically + call instruction. Since we don't have a call here, we artificially extend the range covered by the unwind info by padding before the real start. */ nop diff --git a/arch/powerpc/mm/dma-noncoherent.c b/arch/powerpc/mm/dma-noncoherent.c index 757c0bed9a9..b42f76c4948 100644 --- a/arch/powerpc/mm/dma-noncoherent.c +++ b/arch/powerpc/mm/dma-noncoherent.c @@ -399,3 +399,23 @@ void __dma_sync_page(struct page *page, unsigned long offset, #endif } EXPORT_SYMBOL(__dma_sync_page); + +/* + * Return the PFN for a given cpu virtual address returned by + * __dma_alloc_coherent. This is used by dma_mmap_coherent() + */ +unsigned long __dma_get_coherent_pfn(unsigned long cpu_addr) +{ + /* This should always be populated, so we don't test every + * level. If that fails, we'll have a nice crash which + * will be as good as a BUG_ON() + */ + pgd_t *pgd = pgd_offset_k(cpu_addr); + pud_t *pud = pud_offset(pgd, cpu_addr); + pmd_t *pmd = pmd_offset(pud, cpu_addr); + pte_t *ptep = pte_offset_kernel(pmd, cpu_addr); + + if (pte_none(*ptep) || !pte_present(*ptep)) + return 0; + return pte_pfn(*ptep); +} diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S index 3079f6b44cf..5b7dd4ea02b 100644 --- a/arch/powerpc/mm/hash_low_64.S +++ b/arch/powerpc/mm/hash_low_64.S @@ -192,8 +192,8 @@ htab_insert_pte: rldicr r3,r0,3,63-3 /* r3 = (hash & mask) << 3 */ /* Call ppc_md.hpte_insert */ - ld r6,STK_PARM(r4)(r1) /* Retreive new pp bits */ - mr r4,r29 /* Retreive va */ + ld r6,STK_PARM(r4)(r1) /* Retrieve new pp bits */ + mr r4,r29 /* Retrieve va */ li r7,0 /* !bolted, !secondary */ li r8,MMU_PAGE_4K /* page size */ ld r9,STK_PARM(r9)(r1) /* segment size */ @@ -215,8 +215,8 @@ _GLOBAL(htab_call_hpte_insert1) rldicr r3,r0,3,63-3 /* r0 = (~hash & mask) << 3 */ /* Call ppc_md.hpte_insert */ - ld r6,STK_PARM(r4)(r1) /* Retreive new pp bits */ - mr r4,r29 /* Retreive va */ + ld r6,STK_PARM(r4)(r1) /* Retrieve new pp bits */ + mr r4,r29 /* Retrieve va */ li r7,HPTE_V_SECONDARY /* !bolted, secondary */ li r8,MMU_PAGE_4K /* page size */ ld r9,STK_PARM(r9)(r1) /* segment size */ @@ -495,8 +495,8 @@ htab_special_pfn: rldicr r3,r0,3,63-3 /* r0 = (hash & mask) << 3 */ /* Call ppc_md.hpte_insert */ - ld r6,STK_PARM(r4)(r1) /* Retreive new pp bits */ - mr r4,r29 /* Retreive va */ + ld r6,STK_PARM(r4)(r1) /* Retrieve new pp bits */ + mr r4,r29 /* Retrieve va */ li r7,0 /* !bolted, !secondary */ li r8,MMU_PAGE_4K /* page size */ ld r9,STK_PARM(r9)(r1) /* segment size */ @@ -522,8 +522,8 @@ _GLOBAL(htab_call_hpte_insert1) rldicr r3,r0,3,63-3 /* r0 = (~hash & mask) << 3 */ /* Call ppc_md.hpte_insert */ - ld r6,STK_PARM(r4)(r1) /* Retreive new pp bits */ - mr r4,r29 /* Retreive va */ + ld r6,STK_PARM(r4)(r1) /* Retrieve new pp bits */ + mr r4,r29 /* Retrieve va */ li r7,HPTE_V_SECONDARY /* !bolted, secondary */ li r8,MMU_PAGE_4K /* page size */ ld r9,STK_PARM(r9)(r1) /* segment size */ @@ -813,8 +813,8 @@ ht64_insert_pte: rldicr r3,r0,3,63-3 /* r0 = (hash & mask) << 3 */ /* Call ppc_md.hpte_insert */ - ld r6,STK_PARM(r4)(r1) /* Retreive new pp bits */ - mr r4,r29 /* Retreive va */ + ld r6,STK_PARM(r4)(r1) /* Retrieve new pp bits */ + mr r4,r29 /* Retrieve va */ li r7,0 /* !bolted, !secondary */ li r8,MMU_PAGE_64K ld r9,STK_PARM(r9)(r1) /* segment size */ @@ -836,8 +836,8 @@ _GLOBAL(ht64_call_hpte_insert1) rldicr r3,r0,3,63-3 /* r0 = (~hash & mask) << 3 */ /* Call ppc_md.hpte_insert */ - ld r6,STK_PARM(r4)(r1) /* Retreive new pp bits */ - mr r4,r29 /* Retreive va */ + ld r6,STK_PARM(r4)(r1) /* Retrieve new pp bits */ + mr r4,r29 /* Retrieve va */ li r7,HPTE_V_SECONDARY /* !bolted, secondary */ li r8,MMU_PAGE_64K ld r9,STK_PARM(r9)(r1) /* segment size */ diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c index a5991facddc..58a022d0f46 100644 --- a/arch/powerpc/mm/hash_utils_64.c +++ b/arch/powerpc/mm/hash_utils_64.c @@ -753,7 +753,7 @@ void __cpuinit early_init_mmu_secondary(void) mtspr(SPRN_SDR1, _SDR1); /* Initialize STAB/SLB. We use a virtual address as it works - * in real mode on pSeries and we want a virutal address on + * in real mode on pSeries and we want a virtual address on * iSeries anyway */ if (cpu_has_feature(CPU_FTR_SLB)) diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c index a6649965090..57e545b84bf 100644 --- a/arch/powerpc/mm/mem.c +++ b/arch/powerpc/mm/mem.c @@ -424,7 +424,7 @@ void clear_user_page(void *page, unsigned long vaddr, struct page *pg) clear_page(page); /* - * We shouldnt have to do this, but some versions of glibc + * We shouldn't have to do this, but some versions of glibc * require it (ld.so assumes zero filled pages are icache clean) * - Anton */ diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c index 0dc95c0aa3b..5ec1dad2a19 100644 --- a/arch/powerpc/mm/numa.c +++ b/arch/powerpc/mm/numa.c @@ -440,11 +440,11 @@ static void read_drconf_cell(struct of_drconf_cell *drmem, const u32 **cellp) } /* - * Retreive and validate the ibm,dynamic-memory property of the device tree. + * Retrieve and validate the ibm,dynamic-memory property of the device tree. * * The layout of the ibm,dynamic-memory property is a number N of memblock * list entries followed by N memblock list entries. Each memblock list entry - * contains information as layed out in the of_drconf_cell struct above. + * contains information as laid out in the of_drconf_cell struct above. */ static int of_get_drconf_memory(struct device_node *memory, const u32 **dm) { @@ -468,7 +468,7 @@ static int of_get_drconf_memory(struct device_node *memory, const u32 **dm) } /* - * Retreive and validate the ibm,lmb-size property for drconf memory + * Retrieve and validate the ibm,lmb-size property for drconf memory * from the device tree. */ static u64 of_get_lmb_size(struct device_node *memory) @@ -490,7 +490,7 @@ struct assoc_arrays { }; /* - * Retreive and validate the list of associativity arrays for drconf + * Retrieve and validate the list of associativity arrays for drconf * memory from the ibm,associativity-lookup-arrays property of the * device tree.. * @@ -604,7 +604,7 @@ static int __cpuinit cpu_numa_callback(struct notifier_block *nfb, * Returns the size the region should have to enforce the memory limit. * This will either be the original value of size, a truncated value, * or zero. If the returned value of size is 0 the region should be - * discarded as it lies wholy above the memory limit. + * discarded as it lies wholly above the memory limit. */ static unsigned long __init numa_enforce_memory_limit(unsigned long start, unsigned long size) diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S index 8526bd9d2aa..af089220941 100644 --- a/arch/powerpc/mm/tlb_low_64e.S +++ b/arch/powerpc/mm/tlb_low_64e.S @@ -192,7 +192,7 @@ normal_tlb_miss: or r10,r15,r14 BEGIN_MMU_FTR_SECTION - /* Set the TLB reservation and seach for existing entry. Then load + /* Set the TLB reservation and search for existing entry. Then load * the entry. */ PPC_TLBSRX_DOT(0,r16) @@ -425,13 +425,13 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV) virt_page_table_tlb_miss_fault: /* If we fault here, things are a little bit tricky. We need to call - * either data or instruction store fault, and we need to retreive + * either data or instruction store fault, and we need to retrieve * the original fault address and ESR (for data). * * The thing is, we know that in normal circumstances, this is * always called as a second level tlb miss for SW load or as a first * level TLB miss for HW load, so we should be able to peek at the - * relevant informations in the first exception frame in the PACA. + * relevant information in the first exception frame in the PACA. * * However, we do need to double check that, because we may just hit * a stray kernel pointer or a userland attack trying to hit those diff --git a/arch/powerpc/oprofile/op_model_cell.c b/arch/powerpc/oprofile/op_model_cell.c index c4d2b716756..cb515cff745 100644 --- a/arch/powerpc/oprofile/op_model_cell.c +++ b/arch/powerpc/oprofile/op_model_cell.c @@ -67,7 +67,7 @@ #define MAX_SPU_COUNT 0xFFFFFF /* maximum 24 bit LFSR value */ -/* Minumum HW interval timer setting to send value to trace buffer is 10 cycle. +/* Minimum HW interval timer setting to send value to trace buffer is 10 cycle. * To configure counter to send value every N cycles set counter to * 2^32 - 1 - N. */ @@ -1470,7 +1470,7 @@ static int cell_global_start(struct op_counter_config *ctr) * trace buffer at the maximum rate possible. The trace buffer is configured * to store the PCs, wrapping when it is full. The performance counter is * initialized to the max hardware count minus the number of events, N, between - * samples. Once the N events have occured, a HW counter overflow occurs + * samples. Once the N events have occurred, a HW counter overflow occurs * causing the generation of a HW counter interrupt which also stops the * writing of the SPU PC values to the trace buffer. Hence the last PC * written to the trace buffer is the SPU PC that we want. Unfortunately, @@ -1656,7 +1656,7 @@ static void cell_handle_interrupt_ppu(struct pt_regs *regs, * The counters were frozen by the interrupt. * Reenable the interrupt and restart the counters. * If there was a race between the interrupt handler and - * the virtual counter routine. The virutal counter + * the virtual counter routine. The virtual counter * routine may have cleared the interrupts. Hence must * use the virt_cntr_inter_mask to re-enable the interrupts. */ diff --git a/arch/powerpc/oprofile/op_model_power4.c b/arch/powerpc/oprofile/op_model_power4.c index 80774092db7..8ee51a252cf 100644 --- a/arch/powerpc/oprofile/op_model_power4.c +++ b/arch/powerpc/oprofile/op_model_power4.c @@ -207,7 +207,7 @@ static unsigned long get_pc(struct pt_regs *regs) unsigned long mmcra; unsigned long slot; - /* Cant do much about it */ + /* Can't do much about it */ if (!cur_cpu_spec->oprofile_mmcra_sihv) return pc; diff --git a/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c b/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c index fde0ea50c97..cfc4b200998 100644 --- a/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c +++ b/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c @@ -132,8 +132,8 @@ static int cpld_pic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { - irq_to_desc(virq)->status |= IRQ_LEVEL; - set_irq_chip_and_handler(virq, &cpld_pic, handle_level_irq); + irq_set_status_flags(virq, IRQ_LEVEL); + irq_set_chip_and_handler(virq, &cpld_pic, handle_level_irq); return 0; } @@ -198,7 +198,7 @@ mpc5121_ads_cpld_pic_init(void) goto end; } - set_irq_chained_handler(cascade_irq, cpld_pic_cascade); + irq_set_chained_handler(cascade_irq, cpld_pic_cascade); end: of_node_put(np); } diff --git a/arch/powerpc/platforms/52xx/media5200.c b/arch/powerpc/platforms/52xx/media5200.c index 2bd1e6cf1f5..57a6a349e93 100644 --- a/arch/powerpc/platforms/52xx/media5200.c +++ b/arch/powerpc/platforms/52xx/media5200.c @@ -82,7 +82,7 @@ static struct irq_chip media5200_irq_chip = { void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); int sub_virq, val; u32 status, enable; @@ -107,7 +107,7 @@ void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc) /* Processing done; can reenable the cascade now */ raw_spin_lock(&desc->lock); chip->irq_ack(&desc->irq_data); - if (!(desc->status & IRQ_DISABLED)) + if (!irqd_irq_disabled(&desc->irq_data)) chip->irq_unmask(&desc->irq_data); raw_spin_unlock(&desc->lock); } @@ -115,15 +115,10 @@ void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc) static int media5200_irq_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { - struct irq_desc *desc = irq_to_desc(virq); - pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw); - set_irq_chip_data(virq, &media5200_irq); - set_irq_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq); - set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); - desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); - desc->status |= IRQ_TYPE_LEVEL_LOW | IRQ_LEVEL; - + irq_set_chip_data(virq, &media5200_irq); + irq_set_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq); + irq_set_status_flags(virq, IRQ_LEVEL); return 0; } @@ -187,8 +182,8 @@ static void __init media5200_init_irq(void) media5200_irq.irqhost->host_data = &media5200_irq; - set_irq_data(cascade_virq, &media5200_irq); - set_irq_chained_handler(cascade_virq, media5200_irq_cascade); + irq_set_handler_data(cascade_virq, &media5200_irq); + irq_set_chained_handler(cascade_virq, media5200_irq_cascade); return; diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c index 6da44f0f293..6c39b9cc2fa 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c @@ -192,7 +192,7 @@ static struct irq_chip mpc52xx_gpt_irq_chip = { void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc) { - struct mpc52xx_gpt_priv *gpt = get_irq_data(virq); + struct mpc52xx_gpt_priv *gpt = irq_get_handler_data(virq); int sub_virq; u32 status; @@ -209,8 +209,8 @@ static int mpc52xx_gpt_irq_map(struct irq_host *h, unsigned int virq, struct mpc52xx_gpt_priv *gpt = h->host_data; dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq); - set_irq_chip_data(virq, gpt); - set_irq_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq); + irq_set_chip_data(virq, gpt); + irq_set_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq); return 0; } @@ -259,8 +259,8 @@ mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node) } gpt->irqhost->host_data = gpt; - set_irq_data(cascade_virq, gpt); - set_irq_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade); + irq_set_handler_data(cascade_virq, gpt); + irq_set_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade); /* If the GPT is currently disabled, then change it to be in Input * Capture mode. If the mode is non-zero, then the pin could be diff --git a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c index 6385d883cb8..9940ce8a2d4 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c @@ -57,7 +57,7 @@ struct mpc52xx_lpbfifo { static struct mpc52xx_lpbfifo lpbfifo; /** - * mpc52xx_lpbfifo_kick - Trigger the next block of data to be transfered + * mpc52xx_lpbfifo_kick - Trigger the next block of data to be transferred */ static void mpc52xx_lpbfifo_kick(struct mpc52xx_lpbfifo_request *req) { @@ -179,7 +179,7 @@ static void mpc52xx_lpbfifo_kick(struct mpc52xx_lpbfifo_request *req) * * On transmit, the dma completion irq triggers before the fifo completion * triggers. Handle the dma completion here instead of the LPB FIFO Bestcomm - * task completion irq becuase everyting is not really done until the LPB FIFO + * task completion irq because everything is not really done until the LPB FIFO * completion irq triggers. * * In other words: @@ -195,7 +195,7 @@ static void mpc52xx_lpbfifo_kick(struct mpc52xx_lpbfifo_request *req) * Exit conditions: * 1) Transfer aborted * 2) FIFO complete without DMA; more data to do - * 3) FIFO complete without DMA; all data transfered + * 3) FIFO complete without DMA; all data transferred * 4) FIFO complete using DMA * * Condition 1 can occur regardless of whether or not DMA is used. diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pic.c b/arch/powerpc/platforms/52xx/mpc52xx_pic.c index 9f3ed582d08..1dd15400f6f 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_pic.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_pic.c @@ -214,7 +214,7 @@ static int mpc52xx_extirq_set_type(struct irq_data *d, unsigned int flow_type) ctrl_reg |= (type << (22 - (l2irq * 2))); out_be32(&intr->ctrl, ctrl_reg); - __set_irq_handler_unlocked(d->irq, handler); + __irq_set_handler_locked(d->irq, handler); return 0; } @@ -414,7 +414,7 @@ static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq, else hndlr = handle_level_irq; - set_irq_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr); + irq_set_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr); pr_debug("%s: External IRQ%i virq=%x, hw=%x. type=%x\n", __func__, l2irq, virq, (int)irq, type); return 0; @@ -431,7 +431,7 @@ static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq, return -EINVAL; } - set_irq_chip_and_handler(virq, irqchip, handle_level_irq); + irq_set_chip_and_handler(virq, irqchip, handle_level_irq); pr_debug("%s: virq=%x, l1=%i, l2=%i\n", __func__, virq, l1irq, l2irq); return 0; @@ -512,7 +512,7 @@ void __init mpc52xx_init_irq(void) /** * mpc52xx_get_irq - Get pending interrupt number hook function * - * Called by the interupt handler to determine what IRQ handler needs to be + * Called by the interrupt handler to determine what IRQ handler needs to be * executed. * * Status of pending interrupts is determined by reading the encoded status diff --git a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c index 926dfdaaf57..4a4eb6ffa12 100644 --- a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c +++ b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c @@ -81,7 +81,7 @@ static struct irq_chip pq2ads_pci_ic = { static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc) { - struct pq2ads_pci_pic *priv = get_irq_desc_data(desc); + struct pq2ads_pci_pic *priv = irq_desc_get_handler_data(desc); u32 stat, mask, pend; int bit; @@ -106,17 +106,17 @@ static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc) static int pci_pic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { - irq_to_desc(virq)->status |= IRQ_LEVEL; - set_irq_chip_data(virq, h->host_data); - set_irq_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq); + irq_set_status_flags(virq, IRQ_LEVEL); + irq_set_chip_data(virq, h->host_data); + irq_set_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq); return 0; } static void pci_host_unmap(struct irq_host *h, unsigned int virq) { /* remove chip and handler */ - set_irq_chip_data(virq, NULL); - set_irq_chip(virq, NULL); + irq_set_chip_data(virq, NULL); + irq_set_chip(virq, NULL); } static struct irq_host_ops pci_pic_host_ops = { @@ -175,8 +175,8 @@ int __init pq2ads_pci_init_irq(void) priv->host = host; host->host_data = priv; - set_irq_data(irq, priv); - set_irq_chained_handler(irq, pq2ads_pci_irq_demux); + irq_set_handler_data(irq, priv); + irq_set_chained_handler(irq, pq2ads_pci_irq_demux); of_node_put(np); return 0; diff --git a/arch/powerpc/platforms/85xx/ksi8560.c b/arch/powerpc/platforms/85xx/ksi8560.c index 64447e48f3d..c46f9359be1 100644 --- a/arch/powerpc/platforms/85xx/ksi8560.c +++ b/arch/powerpc/platforms/85xx/ksi8560.c @@ -56,7 +56,7 @@ static void machine_restart(char *cmd) static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); int cascade_irq; while ((cascade_irq = cpm2_get_irq()) >= 0) @@ -106,7 +106,7 @@ static void __init ksi8560_pic_init(void) cpm2_pic_init(np); of_node_put(np); - set_irq_chained_handler(irq, cpm2_cascade); + irq_set_chained_handler(irq, cpm2_cascade); #endif } diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c index 1352d1107bf..3b2c9bb6619 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c @@ -50,7 +50,7 @@ static int mpc85xx_exclude_device(struct pci_controller *hose, static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); int cascade_irq; while ((cascade_irq = cpm2_get_irq()) >= 0) @@ -101,7 +101,7 @@ static void __init mpc85xx_ads_pic_init(void) cpm2_pic_init(np); of_node_put(np); - set_irq_chained_handler(irq, cpm2_cascade); + irq_set_chained_handler(irq, cpm2_cascade); #endif } diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c index 458d91fba91..6299a2a51ae 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c @@ -255,7 +255,7 @@ static int mpc85xx_cds_8259_attach(void) } /* Success. Connect our low-level cascade handler. */ - set_irq_handler(cascade_irq, mpc85xx_8259_cascade_handler); + irq_set_handler(cascade_irq, mpc85xx_8259_cascade_handler); return 0; } diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c index 793ead7993a..c7b97f70312 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c @@ -47,7 +47,7 @@ #ifdef CONFIG_PPC_I8259 static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); unsigned int cascade_irq = i8259_irq(); if (cascade_irq != NO_IRQ) { @@ -122,7 +122,7 @@ void __init mpc85xx_ds_pic_init(void) i8259_init(cascade_node, 0); of_node_put(cascade_node); - set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade); + irq_set_chained_handler(cascade_irq, mpc85xx_8259_cascade); #endif /* CONFIG_PPC_I8259 */ } diff --git a/arch/powerpc/platforms/85xx/sbc8560.c b/arch/powerpc/platforms/85xx/sbc8560.c index d7e28ec3e07..d2dfd465fbf 100644 --- a/arch/powerpc/platforms/85xx/sbc8560.c +++ b/arch/powerpc/platforms/85xx/sbc8560.c @@ -41,7 +41,7 @@ static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); int cascade_irq; while ((cascade_irq = cpm2_get_irq()) >= 0) @@ -92,7 +92,7 @@ static void __init sbc8560_pic_init(void) cpm2_pic_init(np); of_node_put(np); - set_irq_chained_handler(irq, cpm2_cascade); + irq_set_chained_handler(irq, cpm2_cascade); #endif } diff --git a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c index 79d85aca476..db864623b4a 100644 --- a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c +++ b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c @@ -93,7 +93,7 @@ static inline unsigned int socrates_fpga_pic_get_irq(unsigned int irq) void socrates_fpga_pic_cascade(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); unsigned int cascade_irq; /* @@ -245,9 +245,9 @@ static int socrates_fpga_pic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hwirq) { /* All interrupts are LEVEL sensitive */ - irq_to_desc(virq)->status |= IRQ_LEVEL; - set_irq_chip_and_handler(virq, &socrates_fpga_pic_chip, - handle_fasteoi_irq); + irq_set_status_flags(virq, IRQ_LEVEL); + irq_set_chip_and_handler(virq, &socrates_fpga_pic_chip, + handle_fasteoi_irq); return 0; } @@ -308,8 +308,8 @@ void socrates_fpga_pic_init(struct device_node *pic) pr_warning("FPGA PIC: can't get irq%d.\n", i); continue; } - set_irq_chained_handler(socrates_fpga_irqs[i], - socrates_fpga_pic_cascade); + irq_set_chained_handler(socrates_fpga_irqs[i], + socrates_fpga_pic_cascade); } socrates_fpga_pic_iobase = of_iomap(pic, 0); diff --git a/arch/powerpc/platforms/85xx/stx_gp3.c b/arch/powerpc/platforms/85xx/stx_gp3.c index 2b62b064eac..5387e9f06bd 100644 --- a/arch/powerpc/platforms/85xx/stx_gp3.c +++ b/arch/powerpc/platforms/85xx/stx_gp3.c @@ -46,7 +46,7 @@ static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); int cascade_irq; while ((cascade_irq = cpm2_get_irq()) >= 0) @@ -102,7 +102,7 @@ static void __init stx_gp3_pic_init(void) cpm2_pic_init(np); of_node_put(np); - set_irq_chained_handler(irq, cpm2_cascade); + irq_set_chained_handler(irq, cpm2_cascade); #endif } diff --git a/arch/powerpc/platforms/85xx/tqm85xx.c b/arch/powerpc/platforms/85xx/tqm85xx.c index 2265b68e327..325de772725 100644 --- a/arch/powerpc/platforms/85xx/tqm85xx.c +++ b/arch/powerpc/platforms/85xx/tqm85xx.c @@ -44,7 +44,7 @@ static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); int cascade_irq; while ((cascade_irq = cpm2_get_irq()) >= 0) @@ -100,7 +100,7 @@ static void __init tqm85xx_pic_init(void) cpm2_pic_init(np); of_node_put(np); - set_irq_chained_handler(irq, cpm2_cascade); + irq_set_chained_handler(irq, cpm2_cascade); #endif } diff --git a/arch/powerpc/platforms/86xx/gef_pic.c b/arch/powerpc/platforms/86xx/gef_pic.c index 0adfe3b740c..0beec7d5566 100644 --- a/arch/powerpc/platforms/86xx/gef_pic.c +++ b/arch/powerpc/platforms/86xx/gef_pic.c @@ -95,7 +95,7 @@ static int gef_pic_cascade_irq; void gef_pic_cascade(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); unsigned int cascade_irq; /* @@ -163,8 +163,8 @@ static int gef_pic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hwirq) { /* All interrupts are LEVEL sensitive */ - irq_to_desc(virq)->status |= IRQ_LEVEL; - set_irq_chip_and_handler(virq, &gef_pic_chip, handle_level_irq); + irq_set_status_flags(virq, IRQ_LEVEL); + irq_set_chip_and_handler(virq, &gef_pic_chip, handle_level_irq); return 0; } @@ -225,7 +225,7 @@ void __init gef_pic_init(struct device_node *np) return; /* Chain with parent controller */ - set_irq_chained_handler(gef_pic_cascade_irq, gef_pic_cascade); + irq_set_chained_handler(gef_pic_cascade_irq, gef_pic_cascade); } /* diff --git a/arch/powerpc/platforms/86xx/pic.c b/arch/powerpc/platforms/86xx/pic.c index cbe33639b47..8ef8960abda 100644 --- a/arch/powerpc/platforms/86xx/pic.c +++ b/arch/powerpc/platforms/86xx/pic.c @@ -19,7 +19,7 @@ #ifdef CONFIG_PPC_I8259 static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); unsigned int cascade_irq = i8259_irq(); if (cascade_irq != NO_IRQ) @@ -77,6 +77,6 @@ void __init mpc86xx_init_irq(void) i8259_init(cascade_node, 0); of_node_put(cascade_node); - set_irq_chained_handler(cascade_irq, mpc86xx_8259_cascade); + irq_set_chained_handler(cascade_irq, mpc86xx_8259_cascade); #endif } diff --git a/arch/powerpc/platforms/8xx/m8xx_setup.c b/arch/powerpc/platforms/8xx/m8xx_setup.c index fabb108e874..9ecce995dd4 100644 --- a/arch/powerpc/platforms/8xx/m8xx_setup.c +++ b/arch/powerpc/platforms/8xx/m8xx_setup.c @@ -226,11 +226,11 @@ static void cpm_cascade(unsigned int irq, struct irq_desc *desc) generic_handle_irq(cascade_irq); - chip = get_irq_desc_chip(cdesc); + chip = irq_desc_get_chip(cdesc); chip->irq_eoi(&cdesc->irq_data); } - chip = get_irq_desc_chip(desc); + chip = irq_desc_get_chip(desc); chip->irq_eoi(&desc->irq_data); } @@ -251,5 +251,5 @@ void __init mpc8xx_pics_init(void) irq = cpm_pic_init(); if (irq != NO_IRQ) - set_irq_chained_handler(irq, cpm_cascade); + irq_set_chained_handler(irq, cpm_cascade); } diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig index 20576829eca..f7b07720aa3 100644 --- a/arch/powerpc/platforms/Kconfig +++ b/arch/powerpc/platforms/Kconfig @@ -46,7 +46,7 @@ config PPC_OF_BOOT_TRAMPOLINE help Support from booting from Open Firmware or yaboot using an Open Firmware client interface. This enables the kernel to - communicate with open firmware to retrieve system informations + communicate with open firmware to retrieve system information such as the device tree. In case of doubt, say Y diff --git a/arch/powerpc/platforms/cell/Kconfig b/arch/powerpc/platforms/cell/Kconfig index 48cd7d2e1b7..81239ebed83 100644 --- a/arch/powerpc/platforms/cell/Kconfig +++ b/arch/powerpc/platforms/cell/Kconfig @@ -9,6 +9,7 @@ config PPC_CELL_COMMON select PPC_INDIRECT_IO select PPC_NATIVE select PPC_RTAS + select IRQ_EDGE_EOI_HANDLER config PPC_CELL_NATIVE bool diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c index c48b66a67e4..bb5ebf8fa80 100644 --- a/arch/powerpc/platforms/cell/axon_msi.c +++ b/arch/powerpc/platforms/cell/axon_msi.c @@ -93,8 +93,8 @@ static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val) static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); - struct axon_msic *msic = get_irq_data(irq); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct axon_msic *msic = irq_get_handler_data(irq); u32 write_offset, msi; int idx; int retry = 0; @@ -287,7 +287,7 @@ static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) } dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq); - set_irq_msi(virq, entry); + irq_set_msi_desc(virq, entry); msg.data = virq; write_msi_msg(virq, &msg); } @@ -305,7 +305,7 @@ static void axon_msi_teardown_msi_irqs(struct pci_dev *dev) if (entry->irq == NO_IRQ) continue; - set_irq_msi(entry->irq, NULL); + irq_set_msi_desc(entry->irq, NULL); irq_dispose_mapping(entry->irq); } } @@ -320,7 +320,7 @@ static struct irq_chip msic_irq_chip = { static int msic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { - set_irq_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq); + irq_set_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq); return 0; } @@ -400,8 +400,8 @@ static int axon_msi_probe(struct platform_device *device) msic->irq_host->host_data = msic; - set_irq_data(virq, msic); - set_irq_chained_handler(virq, axon_msi_cascade); + irq_set_handler_data(virq, msic); + irq_set_chained_handler(virq, axon_msi_cascade); pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq); /* Enable the MSIC hardware */ diff --git a/arch/powerpc/platforms/cell/beat_interrupt.c b/arch/powerpc/platforms/cell/beat_interrupt.c index 0b8f7d7135c..4cb9e147c30 100644 --- a/arch/powerpc/platforms/cell/beat_interrupt.c +++ b/arch/powerpc/platforms/cell/beat_interrupt.c @@ -136,15 +136,14 @@ static void beatic_pic_host_unmap(struct irq_host *h, unsigned int virq) static int beatic_pic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { - struct irq_desc *desc = irq_to_desc(virq); int64_t err; err = beat_construct_and_connect_irq_plug(virq, hw); if (err < 0) return -EIO; - desc->status |= IRQ_LEVEL; - set_irq_chip_and_handler(virq, &beatic_pic, handle_fasteoi_irq); + irq_set_status_flags(virq, IRQ_LEVEL); + irq_set_chip_and_handler(virq, &beatic_pic, handle_fasteoi_irq); return 0; } diff --git a/arch/powerpc/platforms/cell/interrupt.c b/arch/powerpc/platforms/cell/interrupt.c index 624d26e72f1..44cfd1bef89 100644 --- a/arch/powerpc/platforms/cell/interrupt.c +++ b/arch/powerpc/platforms/cell/interrupt.c @@ -101,9 +101,9 @@ static void iic_ioexc_eoi(struct irq_data *d) static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); struct cbe_iic_regs __iomem *node_iic = - (void __iomem *)get_irq_desc_data(desc); + (void __iomem *)irq_desc_get_handler_data(desc); unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC; unsigned long bits, ack; int cascade; @@ -235,67 +235,19 @@ static int iic_host_match(struct irq_host *h, struct device_node *node) "IBM,CBEA-Internal-Interrupt-Controller"); } -extern int noirqdebug; - -static void handle_iic_irq(unsigned int irq, struct irq_desc *desc) -{ - struct irq_chip *chip = get_irq_desc_chip(desc); - - raw_spin_lock(&desc->lock); - - desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); - - /* - * If we're currently running this IRQ, or its disabled, - * we shouldn't process the IRQ. Mark it pending, handle - * the necessary masking and go out - */ - if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || - !desc->action)) { - desc->status |= IRQ_PENDING; - goto out_eoi; - } - - kstat_incr_irqs_this_cpu(irq, desc); - - /* Mark the IRQ currently in progress.*/ - desc->status |= IRQ_INPROGRESS; - - do { - struct irqaction *action = desc->action; - irqreturn_t action_ret; - - if (unlikely(!action)) - goto out_eoi; - - desc->status &= ~IRQ_PENDING; - raw_spin_unlock(&desc->lock); - action_ret = handle_IRQ_event(irq, action); - if (!noirqdebug) - note_interrupt(irq, desc, action_ret); - raw_spin_lock(&desc->lock); - - } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); - - desc->status &= ~IRQ_INPROGRESS; -out_eoi: - chip->irq_eoi(&desc->irq_data); - raw_spin_unlock(&desc->lock); -} - static int iic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { switch (hw & IIC_IRQ_TYPE_MASK) { case IIC_IRQ_TYPE_IPI: - set_irq_chip_and_handler(virq, &iic_chip, handle_percpu_irq); + irq_set_chip_and_handler(virq, &iic_chip, handle_percpu_irq); break; case IIC_IRQ_TYPE_IOEXC: - set_irq_chip_and_handler(virq, &iic_ioexc_chip, - handle_iic_irq); + irq_set_chip_and_handler(virq, &iic_ioexc_chip, + handle_edge_eoi_irq); break; default: - set_irq_chip_and_handler(virq, &iic_chip, handle_iic_irq); + irq_set_chip_and_handler(virq, &iic_chip, handle_edge_eoi_irq); } return 0; } @@ -412,8 +364,8 @@ static int __init setup_iic(void) * irq_data is a generic pointer that gets passed back * to us later, so the forced cast is fine. */ - set_irq_data(cascade, (void __force *)node_iic); - set_irq_chained_handler(cascade , iic_ioexc_cascade); + irq_set_handler_data(cascade, (void __force *)node_iic); + irq_set_chained_handler(cascade, iic_ioexc_cascade); out_be64(&node_iic->iic_ir, (1 << 12) /* priority */ | (node << 4) /* dest node */ | diff --git a/arch/powerpc/platforms/cell/setup.c b/arch/powerpc/platforms/cell/setup.c index 6a28d027d95..fd57bfe00ed 100644 --- a/arch/powerpc/platforms/cell/setup.c +++ b/arch/powerpc/platforms/cell/setup.c @@ -187,8 +187,8 @@ machine_subsys_initcall(cell, cell_publish_devices); static void cell_mpic_cascade(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); - struct mpic *mpic = get_irq_desc_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct mpic *mpic = irq_desc_get_handler_data(desc); unsigned int virq; virq = mpic_get_one_irq(mpic); @@ -223,8 +223,8 @@ static void __init mpic_init_IRQ(void) printk(KERN_INFO "%s : hooking up to IRQ %d\n", dn->full_name, virq); - set_irq_data(virq, mpic); - set_irq_chained_handler(virq, cell_mpic_cascade); + irq_set_handler_data(virq, mpic); + irq_set_chained_handler(virq, cell_mpic_cascade); } } diff --git a/arch/powerpc/platforms/cell/spider-pic.c b/arch/powerpc/platforms/cell/spider-pic.c index b38cdfc1deb..c5cf50e6b45 100644 --- a/arch/powerpc/platforms/cell/spider-pic.c +++ b/arch/powerpc/platforms/cell/spider-pic.c @@ -102,7 +102,7 @@ static void spider_ack_irq(struct irq_data *d) /* Reset edge detection logic if necessary */ - if (irq_to_desc(d->irq)->status & IRQ_LEVEL) + if (irqd_is_level_type(d)) return; /* Only interrupts 47 to 50 can be set to edge */ @@ -119,7 +119,6 @@ static int spider_set_irq_type(struct irq_data *d, unsigned int type) struct spider_pic *pic = spider_virq_to_pic(d->irq); unsigned int hw = irq_map[d->irq].hwirq; void __iomem *cfg = spider_get_irq_config(pic, hw); - struct irq_desc *desc = irq_to_desc(d->irq); u32 old_mask; u32 ic; @@ -147,12 +146,6 @@ static int spider_set_irq_type(struct irq_data *d, unsigned int type) return -EINVAL; } - /* Update irq_desc */ - desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); - desc->status |= type & IRQ_TYPE_SENSE_MASK; - if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) - desc->status |= IRQ_LEVEL; - /* Configure the source. One gross hack that was there before and * that I've kept around is the priority to the BE which I set to * be the same as the interrupt source number. I don't know wether @@ -178,10 +171,10 @@ static struct irq_chip spider_pic = { static int spider_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { - set_irq_chip_and_handler(virq, &spider_pic, handle_level_irq); + irq_set_chip_and_handler(virq, &spider_pic, handle_level_irq); /* Set default irq type */ - set_irq_type(virq, IRQ_TYPE_NONE); + irq_set_irq_type(virq, IRQ_TYPE_NONE); return 0; } @@ -207,8 +200,8 @@ static struct irq_host_ops spider_host_ops = { static void spider_irq_cascade(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); - struct spider_pic *pic = get_irq_desc_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct spider_pic *pic = irq_desc_get_handler_data(desc); unsigned int cs, virq; cs = in_be32(pic->regs + TIR_CS) >> 24; @@ -328,8 +321,8 @@ static void __init spider_init_one(struct device_node *of_node, int chip, virq = spider_find_cascade_and_node(pic); if (virq == NO_IRQ) return; - set_irq_data(virq, pic); - set_irq_chained_handler(virq, spider_irq_cascade); + irq_set_handler_data(virq, pic); + irq_set_chained_handler(virq, spider_irq_cascade); printk(KERN_INFO "spider_pic: node %d, addr: 0x%lx %s\n", pic->node_id, addr, of_node->full_name); diff --git a/arch/powerpc/platforms/cell/spufs/lscsa_alloc.c b/arch/powerpc/platforms/cell/spufs/lscsa_alloc.c index 3b894f58528..147069938cf 100644 --- a/arch/powerpc/platforms/cell/spufs/lscsa_alloc.c +++ b/arch/powerpc/platforms/cell/spufs/lscsa_alloc.c @@ -90,7 +90,7 @@ int spu_alloc_lscsa(struct spu_state *csa) */ for (i = 0; i < SPU_LSCSA_NUM_BIG_PAGES; i++) { /* XXX This is likely to fail, we should use a special pool - * similiar to what hugetlbfs does. + * similar to what hugetlbfs does. */ csa->lscsa_pages[i] = alloc_pages(GFP_KERNEL, SPU_64K_PAGE_ORDER); diff --git a/arch/powerpc/platforms/cell/spufs/sched.c b/arch/powerpc/platforms/cell/spufs/sched.c index 0b046628493..65203857b0c 100644 --- a/arch/powerpc/platforms/cell/spufs/sched.c +++ b/arch/powerpc/platforms/cell/spufs/sched.c @@ -846,7 +846,7 @@ static struct spu_context *grab_runnable_context(int prio, int node) struct list_head *rq = &spu_prio->runq[best]; list_for_each_entry(ctx, rq, rq) { - /* XXX(hch): check for affinity here aswell */ + /* XXX(hch): check for affinity here as well */ if (__node_allowed(ctx, node)) { __spu_del_from_rq(ctx); goto found; diff --git a/arch/powerpc/platforms/cell/spufs/spu_restore.c b/arch/powerpc/platforms/cell/spufs/spu_restore.c index 21a9c952d88..72c905f1ee7 100644 --- a/arch/powerpc/platforms/cell/spufs/spu_restore.c +++ b/arch/powerpc/platforms/cell/spufs/spu_restore.c @@ -284,7 +284,7 @@ static inline void restore_complete(void) exit_instrs[3] = BR_INSTR; break; default: - /* SPU_Status[R]=1. No additonal instructions. */ + /* SPU_Status[R]=1. No additional instructions. */ break; } spu_sync(); diff --git a/arch/powerpc/platforms/chrp/setup.c b/arch/powerpc/platforms/chrp/setup.c index 4c1288451a2..12278649841 100644 --- a/arch/powerpc/platforms/chrp/setup.c +++ b/arch/powerpc/platforms/chrp/setup.c @@ -365,7 +365,7 @@ void __init chrp_setup_arch(void) static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); unsigned int cascade_irq = i8259_irq(); if (cascade_irq != NO_IRQ) @@ -517,7 +517,7 @@ static void __init chrp_find_8259(void) if (cascade_irq == NO_IRQ) printk(KERN_ERR "i8259: failed to map cascade irq\n"); else - set_irq_chained_handler(cascade_irq, + irq_set_chained_handler(cascade_irq, chrp_8259_cascade); } } diff --git a/arch/powerpc/platforms/embedded6xx/flipper-pic.c b/arch/powerpc/platforms/embedded6xx/flipper-pic.c index 0aca0e28a8e..12aa62b6f22 100644 --- a/arch/powerpc/platforms/embedded6xx/flipper-pic.c +++ b/arch/powerpc/platforms/embedded6xx/flipper-pic.c @@ -101,16 +101,16 @@ static struct irq_host *flipper_irq_host; static int flipper_pic_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hwirq) { - set_irq_chip_data(virq, h->host_data); - irq_to_desc(virq)->status |= IRQ_LEVEL; - set_irq_chip_and_handler(virq, &flipper_pic, handle_level_irq); + irq_set_chip_data(virq, h->host_data); + irq_set_status_flags(virq, IRQ_LEVEL); + irq_set_chip_and_handler(virq, &flipper_pic, handle_level_irq); return 0; } static void flipper_pic_unmap(struct irq_host *h, unsigned int irq) { - set_irq_chip_data(irq, NULL); - set_irq_chip(irq, NULL); + irq_set_chip_data(irq, NULL); + irq_set_chip(irq, NULL); } static int flipper_pic_match(struct irq_host *h, struct device_node *np) diff --git a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c index 35e448bd847..2bdddfc9d52 100644 --- a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c +++ b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c @@ -94,16 +94,16 @@ static struct irq_host *hlwd_irq_host; static int hlwd_pic_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hwirq) { - set_irq_chip_data(virq, h->host_data); - irq_to_desc(virq)->status |= IRQ_LEVEL; - set_irq_chip_and_handler(virq, &hlwd_pic, handle_level_irq); + irq_set_chip_data(virq, h->host_data); + irq_set_status_flags(virq, IRQ_LEVEL); + irq_set_chip_and_handler(virq, &hlwd_pic, handle_level_irq); return 0; } static void hlwd_pic_unmap(struct irq_host *h, unsigned int irq) { - set_irq_chip_data(irq, NULL); - set_irq_chip(irq, NULL); + irq_set_chip_data(irq, NULL); + irq_set_chip(irq, NULL); } static struct irq_host_ops hlwd_irq_host_ops = { @@ -129,8 +129,8 @@ static unsigned int __hlwd_pic_get_irq(struct irq_host *h) static void hlwd_pic_irq_cascade(unsigned int cascade_virq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); - struct irq_host *irq_host = get_irq_data(cascade_virq); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct irq_host *irq_host = irq_get_handler_data(cascade_virq); unsigned int virq; raw_spin_lock(&desc->lock); @@ -145,7 +145,7 @@ static void hlwd_pic_irq_cascade(unsigned int cascade_virq, raw_spin_lock(&desc->lock); chip->irq_ack(&desc->irq_data); /* IRQ_LEVEL */ - if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask) + if (!irqd_irq_disabled(&desc->irq_data) && chip->irq_unmask) chip->irq_unmask(&desc->irq_data); raw_spin_unlock(&desc->lock); } @@ -218,8 +218,8 @@ void hlwd_pic_probe(void) host = hlwd_pic_init(np); BUG_ON(!host); cascade_virq = irq_of_parse_and_map(np, 0); - set_irq_data(cascade_virq, host); - set_irq_chained_handler(cascade_virq, + irq_set_handler_data(cascade_virq, host); + irq_set_chained_handler(cascade_virq, hlwd_pic_irq_cascade); hlwd_irq_host = host; break; diff --git a/arch/powerpc/platforms/embedded6xx/holly.c b/arch/powerpc/platforms/embedded6xx/holly.c index b21fde589ca..487bda0d18d 100644 --- a/arch/powerpc/platforms/embedded6xx/holly.c +++ b/arch/powerpc/platforms/embedded6xx/holly.c @@ -198,8 +198,8 @@ static void __init holly_init_IRQ(void) cascade_pci_irq = irq_of_parse_and_map(tsi_pci, 0); pr_debug("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__, (u32) cascade_pci_irq); tsi108_pci_int_init(cascade_node); - set_irq_data(cascade_pci_irq, mpic); - set_irq_chained_handler(cascade_pci_irq, tsi108_irq_cascade); + irq_set_handler_data(cascade_pci_irq, mpic); + irq_set_chained_handler(cascade_pci_irq, tsi108_irq_cascade); #endif /* Configure MPIC outputs to CPU0 */ tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0); diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c index 7a2ba39d781..1cb907c9435 100644 --- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c +++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c @@ -153,8 +153,8 @@ static void __init mpc7448_hpc2_init_IRQ(void) DBG("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__, (u32) cascade_pci_irq); tsi108_pci_int_init(cascade_node); - set_irq_data(cascade_pci_irq, mpic); - set_irq_chained_handler(cascade_pci_irq, tsi108_irq_cascade); + irq_set_handler_data(cascade_pci_irq, mpic); + irq_set_chained_handler(cascade_pci_irq, tsi108_irq_cascade); #endif /* Configure MPIC outputs to CPU0 */ tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0); diff --git a/arch/powerpc/platforms/iseries/irq.c b/arch/powerpc/platforms/iseries/irq.c index 4fb96f0b2df..52a6889832c 100644 --- a/arch/powerpc/platforms/iseries/irq.c +++ b/arch/powerpc/platforms/iseries/irq.c @@ -220,7 +220,7 @@ void __init iSeries_activate_IRQs() if (!desc) continue; - chip = get_irq_desc_chip(desc); + chip = irq_desc_get_chip(desc); if (chip && chip->irq_startup) { raw_spin_lock_irqsave(&desc->lock, flags); chip->irq_startup(&desc->irq_data); @@ -346,7 +346,7 @@ unsigned int iSeries_get_irq(void) static int iseries_irq_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { - set_irq_chip_and_handler(virq, &iseries_pic, handle_fasteoi_irq); + irq_set_chip_and_handler(virq, &iseries_pic, handle_fasteoi_irq); return 0; } diff --git a/arch/powerpc/platforms/iseries/mf.c b/arch/powerpc/platforms/iseries/mf.c index b5e026bdca2..62dabe3c2bf 100644 --- a/arch/powerpc/platforms/iseries/mf.c +++ b/arch/powerpc/platforms/iseries/mf.c @@ -51,7 +51,7 @@ static int mf_initialized; /* - * This is the structure layout for the Machine Facilites LPAR event + * This is the structure layout for the Machine Facilities LPAR event * flows. */ struct vsp_cmd_data { diff --git a/arch/powerpc/platforms/iseries/viopath.c b/arch/powerpc/platforms/iseries/viopath.c index b5f05d943a9..2376069cdc1 100644 --- a/arch/powerpc/platforms/iseries/viopath.c +++ b/arch/powerpc/platforms/iseries/viopath.c @@ -396,7 +396,7 @@ static void vio_handleEvent(struct HvLpEvent *event) viopathStatus[remoteLp].mTargetInst)) { printk(VIOPATH_KERN_WARN "message from invalid partition. " - "int msg rcvd, source inst (%d) doesnt match (%d)\n", + "int msg rcvd, source inst (%d) doesn't match (%d)\n", viopathStatus[remoteLp].mTargetInst, event->xSourceInstanceId); return; @@ -407,7 +407,7 @@ static void vio_handleEvent(struct HvLpEvent *event) viopathStatus[remoteLp].mSourceInst)) { printk(VIOPATH_KERN_WARN "message from invalid partition. " - "int msg rcvd, target inst (%d) doesnt match (%d)\n", + "int msg rcvd, target inst (%d) doesn't match (%d)\n", viopathStatus[remoteLp].mSourceInst, event->xTargetInstanceId); return; @@ -418,7 +418,7 @@ static void vio_handleEvent(struct HvLpEvent *event) viopathStatus[remoteLp].mSourceInst) { printk(VIOPATH_KERN_WARN "message from invalid partition. " - "ack msg rcvd, source inst (%d) doesnt match (%d)\n", + "ack msg rcvd, source inst (%d) doesn't match (%d)\n", viopathStatus[remoteLp].mSourceInst, event->xSourceInstanceId); return; @@ -428,7 +428,7 @@ static void vio_handleEvent(struct HvLpEvent *event) viopathStatus[remoteLp].mTargetInst) { printk(VIOPATH_KERN_WARN "message from invalid partition. " - "viopath: ack msg rcvd, target inst (%d) doesnt match (%d)\n", + "viopath: ack msg rcvd, target inst (%d) doesn't match (%d)\n", viopathStatus[remoteLp].mTargetInst, event->xTargetInstanceId); return; diff --git a/arch/powerpc/platforms/maple/pci.c b/arch/powerpc/platforms/maple/pci.c index 04296ffff8b..dd2e48b2850 100644 --- a/arch/powerpc/platforms/maple/pci.c +++ b/arch/powerpc/platforms/maple/pci.c @@ -498,7 +498,7 @@ void __devinit maple_pci_irq_fixup(struct pci_dev *dev) printk(KERN_DEBUG "Fixup U4 PCIe IRQ\n"); dev->irq = irq_create_mapping(NULL, 1); if (dev->irq != NO_IRQ) - set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); } /* Hide AMD8111 IDE interrupt when in legacy mode so diff --git a/arch/powerpc/platforms/pasemi/dma_lib.c b/arch/powerpc/platforms/pasemi/dma_lib.c index 09695ae50f9..321a9b3a2d0 100644 --- a/arch/powerpc/platforms/pasemi/dma_lib.c +++ b/arch/powerpc/platforms/pasemi/dma_lib.c @@ -379,9 +379,9 @@ void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size, } EXPORT_SYMBOL(pasemi_dma_free_buf); -/* pasemi_dma_alloc_flag - Allocate a flag (event) for channel syncronization +/* pasemi_dma_alloc_flag - Allocate a flag (event) for channel synchronization * - * Allocates a flag for use with channel syncronization (event descriptors). + * Allocates a flag for use with channel synchronization (event descriptors). * Returns allocated flag (0-63), < 0 on error. */ int pasemi_dma_alloc_flag(void) diff --git a/arch/powerpc/platforms/pasemi/setup.c b/arch/powerpc/platforms/pasemi/setup.c index a6067b38d2c..7c858e6f843 100644 --- a/arch/powerpc/platforms/pasemi/setup.c +++ b/arch/powerpc/platforms/pasemi/setup.c @@ -239,7 +239,7 @@ static __init void pas_init_IRQ(void) if (nmiprop) { nmi_virq = irq_create_mapping(NULL, *nmiprop); mpic_irq_set_priority(nmi_virq, 15); - set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING); mpic_unmask_irq(irq_get_irq_data(nmi_virq)); } diff --git a/arch/powerpc/platforms/powermac/Makefile b/arch/powerpc/platforms/powermac/Makefile index 50f16939255..ea47df66fee 100644 --- a/arch/powerpc/platforms/powermac/Makefile +++ b/arch/powerpc/platforms/powermac/Makefile @@ -11,7 +11,7 @@ obj-y += pic.o setup.o time.o feature.o pci.o \ obj-$(CONFIG_PMAC_BACKLIGHT) += backlight.o obj-$(CONFIG_CPU_FREQ_PMAC) += cpufreq_32.o obj-$(CONFIG_CPU_FREQ_PMAC64) += cpufreq_64.o -# CONFIG_NVRAM is an arch. independant tristate symbol, for pmac32 we really +# CONFIG_NVRAM is an arch. independent tristate symbol, for pmac32 we really # need this to be a bool. Cheat here and pretend CONFIG_NVRAM=m is really # CONFIG_NVRAM=y obj-$(CONFIG_NVRAM:m=y) += nvram.o diff --git a/arch/powerpc/platforms/powermac/low_i2c.c b/arch/powerpc/platforms/powermac/low_i2c.c index 480567e5fa9..e9c8a607268 100644 --- a/arch/powerpc/platforms/powermac/low_i2c.c +++ b/arch/powerpc/platforms/powermac/low_i2c.c @@ -904,7 +904,7 @@ static void __init smu_i2c_probe(void) printk(KERN_INFO "SMU i2c %s\n", controller->full_name); /* Look for childs, note that they might not be of the right - * type as older device trees mix i2c busses and other thigns + * type as older device trees mix i2c busses and other things * at the same level */ for (busnode = NULL; diff --git a/arch/powerpc/platforms/powermac/pci.c b/arch/powerpc/platforms/powermac/pci.c index 3bc075c788e..f33e08d573c 100644 --- a/arch/powerpc/platforms/powermac/pci.c +++ b/arch/powerpc/platforms/powermac/pci.c @@ -299,7 +299,7 @@ static void __init setup_chaos(struct pci_controller *hose, * This function deals with some "special cases" devices. * * 0 -> No special case - * 1 -> Skip the device but act as if the access was successfull + * 1 -> Skip the device but act as if the access was successful * (return 0xff's on reads, eventually, cache config space * accesses in a later version) * -1 -> Hide the device (unsuccessful access) @@ -988,7 +988,7 @@ void __devinit pmac_pci_irq_fixup(struct pci_dev *dev) dev->vendor == PCI_VENDOR_ID_DEC && dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) { dev->irq = irq_create_mapping(NULL, 60); - set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); } #endif /* CONFIG_PPC32 */ } diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c index c55812bb6a5..023f24086a0 100644 --- a/arch/powerpc/platforms/powermac/pic.c +++ b/arch/powerpc/platforms/powermac/pic.c @@ -157,7 +157,7 @@ static unsigned int pmac_startup_irq(struct irq_data *d) int i = src >> 5; raw_spin_lock_irqsave(&pmac_pic_lock, flags); - if ((irq_to_desc(d->irq)->status & IRQ_LEVEL) == 0) + if (!irqd_is_level_type(d)) out_le32(&pmac_irq_hw[i]->ack, bit); __set_bit(src, ppc_cached_irq_mask); __pmac_set_irq_mask(src, 0); @@ -289,7 +289,6 @@ static int pmac_pic_host_match(struct irq_host *h, struct device_node *node) static int pmac_pic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { - struct irq_desc *desc = irq_to_desc(virq); int level; if (hw >= max_irqs) @@ -300,9 +299,9 @@ static int pmac_pic_host_map(struct irq_host *h, unsigned int virq, */ level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f))); if (level) - desc->status |= IRQ_LEVEL; - set_irq_chip_and_handler(virq, &pmac_pic, level ? - handle_level_irq : handle_edge_irq); + irq_set_status_flags(virq, IRQ_LEVEL); + irq_set_chip_and_handler(virq, &pmac_pic, + level ? handle_level_irq : handle_edge_irq); return 0; } @@ -472,8 +471,8 @@ int of_irq_map_oldworld(struct device_node *device, int index, static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); - struct mpic *mpic = get_irq_desc_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct mpic *mpic = irq_desc_get_handler_data(desc); unsigned int cascade_irq = mpic_get_one_irq(mpic); if (cascade_irq != NO_IRQ) @@ -591,8 +590,8 @@ static int __init pmac_pic_probe_mpic(void) of_node_put(slave); return 0; } - set_irq_data(cascade, mpic2); - set_irq_chained_handler(cascade, pmac_u3_cascade); + irq_set_handler_data(cascade, mpic2); + irq_set_chained_handler(cascade, pmac_u3_cascade); of_node_put(slave); return 0; diff --git a/arch/powerpc/platforms/powermac/pmac.h b/arch/powerpc/platforms/powermac/pmac.h index f0bc08f6c1f..20468f49aec 100644 --- a/arch/powerpc/platforms/powermac/pmac.h +++ b/arch/powerpc/platforms/powermac/pmac.h @@ -33,7 +33,6 @@ extern void pmac_setup_pci_dma(void); extern void pmac_check_ht_link(void); extern void pmac_setup_smp(void); -extern void pmac32_cpu_die(void); extern void low_cpu_die(void) __attribute__((noreturn)); extern int pmac_nvram_init(void); diff --git a/arch/powerpc/platforms/powermac/setup.c b/arch/powerpc/platforms/powermac/setup.c index d5aceb7fb12..aa45281bd29 100644 --- a/arch/powerpc/platforms/powermac/setup.c +++ b/arch/powerpc/platforms/powermac/setup.c @@ -650,51 +650,6 @@ static int pmac_pci_probe_mode(struct pci_bus *bus) return PCI_PROBE_NORMAL; return PCI_PROBE_DEVTREE; } - -#ifdef CONFIG_HOTPLUG_CPU -/* access per cpu vars from generic smp.c */ -DECLARE_PER_CPU(int, cpu_state); - -static void pmac64_cpu_die(void) -{ - /* - * turn off as much as possible, we'll be - * kicked out as this will only be invoked - * on core99 platforms for now ... - */ - - printk(KERN_INFO "CPU#%d offline\n", smp_processor_id()); - __get_cpu_var(cpu_state) = CPU_DEAD; - smp_wmb(); - - /* - * during the path that leads here preemption is disabled, - * reenable it now so that when coming up preempt count is - * zero correctly - */ - preempt_enable(); - - /* - * hard-disable interrupts for the non-NAP case, the NAP code - * needs to re-enable interrupts (but soft-disables them) - */ - hard_irq_disable(); - - while (1) { - /* let's not take timer interrupts too often ... */ - set_dec(0x7fffffff); - - /* should always be true at this point */ - if (cpu_has_feature(CPU_FTR_CAN_NAP)) - power4_cpu_offline_powersave(); - else { - HMT_low(); - HMT_very_low(); - } - } -} -#endif /* CONFIG_HOTPLUG_CPU */ - #endif /* CONFIG_PPC64 */ define_machine(powermac) { @@ -726,15 +681,4 @@ define_machine(powermac) { .pcibios_after_init = pmac_pcibios_after_init, .phys_mem_access_prot = pci_phys_mem_access_prot, #endif -#ifdef CONFIG_HOTPLUG_CPU -#ifdef CONFIG_PPC64 - .cpu_die = pmac64_cpu_die, -#endif -#ifdef CONFIG_PPC32 - .cpu_die = pmac32_cpu_die, -#endif -#endif -#if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32) - .cpu_die = generic_mach_cpu_die, -#endif }; diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c index c95215f4f8b..bc5f0dc6ae1 100644 --- a/arch/powerpc/platforms/powermac/smp.c +++ b/arch/powerpc/platforms/powermac/smp.c @@ -840,92 +840,151 @@ static void __devinit smp_core99_setup_cpu(int cpu_nr) /* Setup openpic */ mpic_setup_this_cpu(); +} - if (cpu_nr == 0) { #ifdef CONFIG_PPC64 - extern void g5_phy_disable_cpu1(void); +#ifdef CONFIG_HOTPLUG_CPU +static int smp_core99_cpu_notify(struct notifier_block *self, + unsigned long action, void *hcpu) +{ + int rc; - /* Close i2c bus if it was used for tb sync */ + switch(action) { + case CPU_UP_PREPARE: + case CPU_UP_PREPARE_FROZEN: + /* Open i2c bus if it was used for tb sync */ if (pmac_tb_clock_chip_host) { - pmac_i2c_close(pmac_tb_clock_chip_host); - pmac_tb_clock_chip_host = NULL; + rc = pmac_i2c_open(pmac_tb_clock_chip_host, 1); + if (rc) { + pr_err("Failed to open i2c bus for time sync\n"); + return notifier_from_errno(rc); + } } + break; + case CPU_ONLINE: + case CPU_UP_CANCELED: + /* Close i2c bus if it was used for tb sync */ + if (pmac_tb_clock_chip_host) + pmac_i2c_close(pmac_tb_clock_chip_host); + break; + default: + break; + } + return NOTIFY_OK; +} - /* If we didn't start the second CPU, we must take - * it off the bus - */ - if (of_machine_is_compatible("MacRISC4") && - num_online_cpus() < 2) - g5_phy_disable_cpu1(); -#endif /* CONFIG_PPC64 */ +static struct notifier_block __cpuinitdata smp_core99_cpu_nb = { + .notifier_call = smp_core99_cpu_notify, +}; +#endif /* CONFIG_HOTPLUG_CPU */ + +static void __init smp_core99_bringup_done(void) +{ + extern void g5_phy_disable_cpu1(void); - if (ppc_md.progress) - ppc_md.progress("core99_setup_cpu 0 done", 0x349); + /* Close i2c bus if it was used for tb sync */ + if (pmac_tb_clock_chip_host) + pmac_i2c_close(pmac_tb_clock_chip_host); + + /* If we didn't start the second CPU, we must take + * it off the bus. + */ + if (of_machine_is_compatible("MacRISC4") && + num_online_cpus() < 2) { + set_cpu_present(1, false); + g5_phy_disable_cpu1(); } -} +#ifdef CONFIG_HOTPLUG_CPU + register_cpu_notifier(&smp_core99_cpu_nb); +#endif + if (ppc_md.progress) + ppc_md.progress("smp_core99_bringup_done", 0x349); +} +#endif /* CONFIG_PPC64 */ -#if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32) +#ifdef CONFIG_HOTPLUG_CPU -int smp_core99_cpu_disable(void) +static int smp_core99_cpu_disable(void) { - set_cpu_online(smp_processor_id(), false); + int rc = generic_cpu_disable(); + if (rc) + return rc; - /* XXX reset cpu affinity here */ mpic_cpu_set_priority(0xf); - asm volatile("mtdec %0" : : "r" (0x7fffffff)); - mb(); - udelay(20); - asm volatile("mtdec %0" : : "r" (0x7fffffff)); + return 0; } -static int cpu_dead[NR_CPUS]; +#ifdef CONFIG_PPC32 -void pmac32_cpu_die(void) +static void pmac_cpu_die(void) { + int cpu = smp_processor_id(); + local_irq_disable(); - cpu_dead[smp_processor_id()] = 1; + idle_task_exit(); + pr_debug("CPU%d offline\n", cpu); + generic_set_cpu_dead(cpu); + smp_wmb(); mb(); low_cpu_die(); } -void smp_core99_cpu_die(unsigned int cpu) +#else /* CONFIG_PPC32 */ + +static void pmac_cpu_die(void) { - int timeout; + int cpu = smp_processor_id(); - timeout = 1000; - while (!cpu_dead[cpu]) { - if (--timeout == 0) { - printk("CPU %u refused to die!\n", cpu); - break; - } - msleep(1); + local_irq_disable(); + idle_task_exit(); + + /* + * turn off as much as possible, we'll be + * kicked out as this will only be invoked + * on core99 platforms for now ... + */ + + printk(KERN_INFO "CPU#%d offline\n", cpu); + generic_set_cpu_dead(cpu); + smp_wmb(); + + /* + * Re-enable interrupts. The NAP code needs to enable them + * anyways, do it now so we deal with the case where one already + * happened while soft-disabled. + * We shouldn't get any external interrupts, only decrementer, and the + * decrementer handler is safe for use on offline CPUs + */ + local_irq_enable(); + + while (1) { + /* let's not take timer interrupts too often ... */ + set_dec(0x7fffffff); + + /* Enter NAP mode */ + power4_idle(); } - cpu_dead[cpu] = 0; } -#endif /* CONFIG_HOTPLUG_CPU && CONFIG_PP32 */ +#endif /* else CONFIG_PPC32 */ +#endif /* CONFIG_HOTPLUG_CPU */ /* Core99 Macs (dual G4s and G5s) */ struct smp_ops_t core99_smp_ops = { .message_pass = smp_mpic_message_pass, .probe = smp_core99_probe, +#ifdef CONFIG_PPC64 + .bringup_done = smp_core99_bringup_done, +#endif .kick_cpu = smp_core99_kick_cpu, .setup_cpu = smp_core99_setup_cpu, .give_timebase = smp_core99_give_timebase, .take_timebase = smp_core99_take_timebase, #if defined(CONFIG_HOTPLUG_CPU) -# if defined(CONFIG_PPC32) .cpu_disable = smp_core99_cpu_disable, - .cpu_die = smp_core99_cpu_die, -# endif -# if defined(CONFIG_PPC64) - .cpu_disable = generic_cpu_disable, .cpu_die = generic_cpu_die, - /* intentionally do *NOT* assign cpu_enable, - * the generic code will use kick_cpu then! */ -# endif #endif }; @@ -957,5 +1016,10 @@ void __init pmac_setup_smp(void) smp_ops = &psurge_smp_ops; } #endif /* CONFIG_PPC32 */ + +#ifdef CONFIG_HOTPLUG_CPU + ppc_md.cpu_die = pmac_cpu_die; +#endif } + diff --git a/arch/powerpc/platforms/ps3/interrupt.c b/arch/powerpc/platforms/ps3/interrupt.c index 3988c86682a..f2f6413b81d 100644 --- a/arch/powerpc/platforms/ps3/interrupt.c +++ b/arch/powerpc/platforms/ps3/interrupt.c @@ -194,7 +194,7 @@ static int ps3_virq_setup(enum ps3_cpu_binding cpu, unsigned long outlet, pr_debug("%s:%d: outlet %lu => cpu %u, virq %u\n", __func__, __LINE__, outlet, cpu, *virq); - result = set_irq_chip_data(*virq, pd); + result = irq_set_chip_data(*virq, pd); if (result) { pr_debug("%s:%d: set_irq_chip_data failed\n", @@ -221,12 +221,12 @@ fail_create: static int ps3_virq_destroy(unsigned int virq) { - const struct ps3_private *pd = get_irq_chip_data(virq); + const struct ps3_private *pd = irq_get_chip_data(virq); pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__, __LINE__, pd->ppe_id, pd->thread_id, virq); - set_irq_chip_data(virq, NULL); + irq_set_chip_data(virq, NULL); irq_dispose_mapping(virq); pr_debug("%s:%d <-\n", __func__, __LINE__); @@ -256,7 +256,7 @@ int ps3_irq_plug_setup(enum ps3_cpu_binding cpu, unsigned long outlet, goto fail_setup; } - pd = get_irq_chip_data(*virq); + pd = irq_get_chip_data(*virq); /* Binds outlet to cpu + virq. */ @@ -291,7 +291,7 @@ EXPORT_SYMBOL_GPL(ps3_irq_plug_setup); int ps3_irq_plug_destroy(unsigned int virq) { int result; - const struct ps3_private *pd = get_irq_chip_data(virq); + const struct ps3_private *pd = irq_get_chip_data(virq); pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__, __LINE__, pd->ppe_id, pd->thread_id, virq); @@ -661,7 +661,7 @@ static void dump_bmp(struct ps3_private* pd) {}; static void ps3_host_unmap(struct irq_host *h, unsigned int virq) { - set_irq_chip_data(virq, NULL); + irq_set_chip_data(virq, NULL); } static int ps3_host_map(struct irq_host *h, unsigned int virq, @@ -670,7 +670,7 @@ static int ps3_host_map(struct irq_host *h, unsigned int virq, pr_debug("%s:%d: hwirq %lu, virq %u\n", __func__, __LINE__, hwirq, virq); - set_irq_chip_and_handler(virq, &ps3_irq_chip, handle_fasteoi_irq); + irq_set_chip_and_handler(virq, &ps3_irq_chip, handle_fasteoi_irq); return 0; } diff --git a/arch/powerpc/platforms/pseries/dlpar.c b/arch/powerpc/platforms/pseries/dlpar.c index b74a9230edc..57ceb92b228 100644 --- a/arch/powerpc/platforms/pseries/dlpar.c +++ b/arch/powerpc/platforms/pseries/dlpar.c @@ -74,7 +74,7 @@ static struct device_node *dlpar_parse_cc_node(struct cc_workarea *ccwa) return NULL; /* The configure connector reported name does not contain a - * preceeding '/', so we allocate a buffer large enough to + * preceding '/', so we allocate a buffer large enough to * prepend this to the full_name. */ name = (char *)ccwa + ccwa->name_offset; diff --git a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/platforms/pseries/eeh.c index 3cc4d102b1f..89649173d3a 100644 --- a/arch/powerpc/platforms/pseries/eeh.c +++ b/arch/powerpc/platforms/pseries/eeh.c @@ -65,7 +65,7 @@ * with EEH. * * Ideally, a PCI device driver, when suspecting that an isolation - * event has occured (e.g. by reading 0xff's), will then ask EEH + * event has occurred (e.g. by reading 0xff's), will then ask EEH * whether this is the case, and then take appropriate steps to * reset the PCI slot, the PCI device, and then resume operations. * However, until that day, the checking is done here, with the diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c b/arch/powerpc/platforms/pseries/hotplug-cpu.c index fd50ccd4bac..ef8c45489e2 100644 --- a/arch/powerpc/platforms/pseries/hotplug-cpu.c +++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c @@ -216,7 +216,7 @@ static void pseries_cpu_die(unsigned int cpu) cpu, pcpu, cpu_status); } - /* Isolation and deallocation are definatly done by + /* Isolation and deallocation are definitely done by * drslot_chrp_cpu. If they were not they would be * done here. Change isolate state to Isolate and * change allocation-state to Unusable. diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c index 154c464cdca..6d5412a18b2 100644 --- a/arch/powerpc/platforms/pseries/iommu.c +++ b/arch/powerpc/platforms/pseries/iommu.c @@ -272,7 +272,7 @@ static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum) return tce_ret; } -/* this is compatable with cells for the device tree property */ +/* this is compatible with cells for the device tree property */ struct dynamic_dma_window_prop { __be32 liobn; /* tce table number */ __be64 dma_base; /* address hi,lo */ @@ -976,7 +976,7 @@ static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev) pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev)); /* dev setup for LPAR is a little tricky, since the device tree might - * contain the dma-window properties per-device and not neccesarily + * contain the dma-window properties per-device and not necessarily * for the bus. So we need to search upwards in the tree until we * either hit a dma-window property, OR find a parent with a table * already allocated. @@ -1033,7 +1033,7 @@ static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask) /* * the device tree might contain the dma-window properties - * per-device and not neccesarily for the bus. So we need to + * per-device and not necessarily for the bus. So we need to * search upwards in the tree until we either hit a dma-window * property, OR find a parent with a table already allocated. */ diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c index 18ac801f8e9..38d24e7e7bb 100644 --- a/arch/powerpc/platforms/pseries/msi.c +++ b/arch/powerpc/platforms/pseries/msi.c @@ -137,7 +137,7 @@ static void rtas_teardown_msi_irqs(struct pci_dev *pdev) if (entry->irq == NO_IRQ) continue; - set_irq_msi(entry->irq, NULL); + irq_set_msi_desc(entry->irq, NULL); irq_dispose_mapping(entry->irq); } @@ -437,7 +437,7 @@ static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) } dev_dbg(&pdev->dev, "rtas_msi: allocated virq %d\n", virq); - set_irq_msi(virq, entry); + irq_set_msi_desc(virq, entry); /* Read config space back so we can restore after reset */ read_msi_msg(virq, &msg); diff --git a/arch/powerpc/platforms/pseries/nvram.c b/arch/powerpc/platforms/pseries/nvram.c index 419707b0724..00cc3a09488 100644 --- a/arch/powerpc/platforms/pseries/nvram.c +++ b/arch/powerpc/platforms/pseries/nvram.c @@ -480,8 +480,32 @@ static void oops_to_nvram(struct kmsg_dumper *dumper, const char *new_msgs, unsigned long new_len) { static unsigned int oops_count = 0; + static bool panicking = false; size_t text_len; + switch (reason) { + case KMSG_DUMP_RESTART: + case KMSG_DUMP_HALT: + case KMSG_DUMP_POWEROFF: + /* These are almost always orderly shutdowns. */ + return; + case KMSG_DUMP_OOPS: + case KMSG_DUMP_KEXEC: + break; + case KMSG_DUMP_PANIC: + panicking = true; + break; + case KMSG_DUMP_EMERG: + if (panicking) + /* Panic report already captured. */ + return; + break; + default: + pr_err("%s: ignoring unrecognized KMSG_DUMP_* reason %d\n", + __FUNCTION__, (int) reason); + return; + } + if (clobbering_unread_rtas_event()) return; diff --git a/arch/powerpc/platforms/pseries/offline_states.h b/arch/powerpc/platforms/pseries/offline_states.h index 75a6f480d93..08672d9136a 100644 --- a/arch/powerpc/platforms/pseries/offline_states.h +++ b/arch/powerpc/platforms/pseries/offline_states.h @@ -34,6 +34,4 @@ static inline void set_default_offline_state(int cpu) #endif extern enum cpu_state_vals get_preferred_offline_state(int cpu); -extern int start_secondary(void); -extern void start_secondary_resume(void); #endif diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c index 2a0089a2c82..6c42cfde841 100644 --- a/arch/powerpc/platforms/pseries/setup.c +++ b/arch/powerpc/platforms/pseries/setup.c @@ -114,7 +114,7 @@ static void __init fwnmi_init(void) static void pseries_8259_cascade(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); unsigned int cascade_irq = i8259_irq(); if (cascade_irq != NO_IRQ) @@ -169,7 +169,7 @@ static void __init pseries_setup_i8259_cascade(void) printk(KERN_DEBUG "pic: PCI 8259 intack at 0x%016lx\n", intack); i8259_init(found, intack); of_node_put(found); - set_irq_chained_handler(cascade, pseries_8259_cascade); + irq_set_chained_handler(cascade, pseries_8259_cascade); } static void __init pseries_mpic_init_IRQ(void) @@ -287,14 +287,22 @@ static int alloc_dispatch_logs(void) int cpu, ret; struct paca_struct *pp; struct dtl_entry *dtl; + struct kmem_cache *dtl_cache; if (!firmware_has_feature(FW_FEATURE_SPLPAR)) return 0; + dtl_cache = kmem_cache_create("dtl", DISPATCH_LOG_BYTES, + DISPATCH_LOG_BYTES, 0, NULL); + if (!dtl_cache) { + pr_warn("Failed to create dispatch trace log buffer cache\n"); + pr_warn("Stolen time statistics will be unreliable\n"); + return 0; + } + for_each_possible_cpu(cpu) { pp = &paca[cpu]; - dtl = kmalloc_node(DISPATCH_LOG_BYTES, GFP_KERNEL, - cpu_to_node(cpu)); + dtl = kmem_cache_alloc(dtl_cache, GFP_KERNEL); if (!dtl) { pr_warn("Failed to allocate dispatch trace log for cpu %d\n", cpu); @@ -378,7 +386,7 @@ static int __init pSeries_init_panel(void) return 0; } -arch_initcall(pSeries_init_panel); +machine_arch_initcall(pseries, pSeries_init_panel); static int pseries_set_dabr(unsigned long dabr) { diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c index 0317cce877c..a509c5292a6 100644 --- a/arch/powerpc/platforms/pseries/smp.c +++ b/arch/powerpc/platforms/pseries/smp.c @@ -64,8 +64,8 @@ int smp_query_cpu_stopped(unsigned int pcpu) int qcss_tok = rtas_token("query-cpu-stopped-state"); if (qcss_tok == RTAS_UNKNOWN_SERVICE) { - printk(KERN_INFO "Firmware doesn't support " - "query-cpu-stopped-state\n"); + printk_once(KERN_INFO + "Firmware doesn't support query-cpu-stopped-state\n"); return QCSS_HARDWARE_ERROR; } @@ -112,10 +112,10 @@ static inline int __devinit smp_startup_cpu(unsigned int lcpu) /* Fixup atomic count: it exited inside IRQ handler. */ task_thread_info(paca[lcpu].__current)->preempt_count = 0; - +#ifdef CONFIG_HOTPLUG_CPU if (get_cpu_current_state(lcpu) == CPU_STATE_INACTIVE) goto out; - +#endif /* * If the RTAS start-cpu token does not exist then presume the * cpu is already spinning. @@ -130,7 +130,9 @@ static inline int __devinit smp_startup_cpu(unsigned int lcpu) return 0; } +#ifdef CONFIG_HOTPLUG_CPU out: +#endif return 1; } @@ -144,16 +146,15 @@ static void __devinit smp_xics_setup_cpu(int cpu) vpa_init(cpu); cpumask_clear_cpu(cpu, of_spin_mask); +#ifdef CONFIG_HOTPLUG_CPU set_cpu_current_state(cpu, CPU_STATE_ONLINE); set_default_offline_state(cpu); - +#endif } #endif /* CONFIG_XICS */ static void __devinit smp_pSeries_kick_cpu(int nr) { - long rc; - unsigned long hcpuid; BUG_ON(nr < 0 || nr >= NR_CPUS); if (!smp_startup_cpu(nr)) @@ -165,16 +166,20 @@ static void __devinit smp_pSeries_kick_cpu(int nr) * the processor will continue on to secondary_start */ paca[nr].cpu_start = 1; - +#ifdef CONFIG_HOTPLUG_CPU set_preferred_offline_state(nr, CPU_STATE_ONLINE); if (get_cpu_current_state(nr) == CPU_STATE_INACTIVE) { + long rc; + unsigned long hcpuid; + hcpuid = get_hard_smp_processor_id(nr); rc = plpar_hcall_norets(H_PROD, hcpuid); if (rc != H_SUCCESS) printk(KERN_ERR "Error: Prod to wake up processor %d " "Ret= %ld\n", nr, rc); } +#endif } static int smp_pSeries_cpu_bootable(unsigned int nr) diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c index 01fea46c033..d6901334d66 100644 --- a/arch/powerpc/platforms/pseries/xics.c +++ b/arch/powerpc/platforms/pseries/xics.c @@ -204,33 +204,33 @@ static int get_irq_server(unsigned int virq, const struct cpumask *cpumask, static void xics_unmask_irq(struct irq_data *d) { - unsigned int irq; + unsigned int hwirq; int call_status; int server; pr_devel("xics: unmask virq %d\n", d->irq); - irq = (unsigned int)irq_map[d->irq].hwirq; - pr_devel(" -> map to hwirq 0x%x\n", irq); - if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) + hwirq = (unsigned int)irq_map[d->irq].hwirq; + pr_devel(" -> map to hwirq 0x%x\n", hwirq); + if (hwirq == XICS_IPI || hwirq == XICS_IRQ_SPURIOUS) return; server = get_irq_server(d->irq, d->affinity, 0); - call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server, + call_status = rtas_call(ibm_set_xive, 3, 1, NULL, hwirq, server, DEFAULT_PRIORITY); if (call_status != 0) { printk(KERN_ERR "%s: ibm_set_xive irq %u server %x returned %d\n", - __func__, irq, server, call_status); + __func__, hwirq, server, call_status); return; } /* Now unmask the interrupt (often a no-op) */ - call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq); + call_status = rtas_call(ibm_int_on, 1, 1, NULL, hwirq); if (call_status != 0) { printk(KERN_ERR "%s: ibm_int_on irq=%u returned %d\n", - __func__, irq, call_status); + __func__, hwirq, call_status); return; } } @@ -250,46 +250,46 @@ static unsigned int xics_startup(struct irq_data *d) return 0; } -static void xics_mask_real_irq(struct irq_data *d) +static void xics_mask_real_irq(unsigned int hwirq) { int call_status; - if (d->irq == XICS_IPI) + if (hwirq == XICS_IPI) return; - call_status = rtas_call(ibm_int_off, 1, 1, NULL, d->irq); + call_status = rtas_call(ibm_int_off, 1, 1, NULL, hwirq); if (call_status != 0) { printk(KERN_ERR "%s: ibm_int_off irq=%u returned %d\n", - __func__, d->irq, call_status); + __func__, hwirq, call_status); return; } /* Have to set XIVE to 0xff to be able to remove a slot */ - call_status = rtas_call(ibm_set_xive, 3, 1, NULL, d->irq, + call_status = rtas_call(ibm_set_xive, 3, 1, NULL, hwirq, default_server, 0xff); if (call_status != 0) { printk(KERN_ERR "%s: ibm_set_xive(0xff) irq=%u returned %d\n", - __func__, d->irq, call_status); + __func__, hwirq, call_status); return; } } static void xics_mask_irq(struct irq_data *d) { - unsigned int irq; + unsigned int hwirq; pr_devel("xics: mask virq %d\n", d->irq); - irq = (unsigned int)irq_map[d->irq].hwirq; - if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) + hwirq = (unsigned int)irq_map[d->irq].hwirq; + if (hwirq == XICS_IPI || hwirq == XICS_IRQ_SPURIOUS) return; - xics_mask_real_irq(d); + xics_mask_real_irq(hwirq); } static void xics_mask_unknown_vec(unsigned int vec) { printk(KERN_ERR "Interrupt %u (real) is invalid, disabling it.\n", vec); - xics_mask_real_irq(irq_get_irq_data(vec)); + xics_mask_real_irq(vec); } static inline unsigned int xics_xirr_vector(unsigned int xirr) @@ -373,37 +373,37 @@ static unsigned char pop_cppr(void) static void xics_eoi_direct(struct irq_data *d) { - unsigned int irq = (unsigned int)irq_map[d->irq].hwirq; + unsigned int hwirq = (unsigned int)irq_map[d->irq].hwirq; iosync(); - direct_xirr_info_set((pop_cppr() << 24) | irq); + direct_xirr_info_set((pop_cppr() << 24) | hwirq); } static void xics_eoi_lpar(struct irq_data *d) { - unsigned int irq = (unsigned int)irq_map[d->irq].hwirq; + unsigned int hwirq = (unsigned int)irq_map[d->irq].hwirq; iosync(); - lpar_xirr_info_set((pop_cppr() << 24) | irq); + lpar_xirr_info_set((pop_cppr() << 24) | hwirq); } static int xics_set_affinity(struct irq_data *d, const struct cpumask *cpumask, bool force) { - unsigned int irq; + unsigned int hwirq; int status; int xics_status[2]; int irq_server; - irq = (unsigned int)irq_map[d->irq].hwirq; - if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) + hwirq = (unsigned int)irq_map[d->irq].hwirq; + if (hwirq == XICS_IPI || hwirq == XICS_IRQ_SPURIOUS) return -1; - status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq); + status = rtas_call(ibm_get_xive, 1, 3, xics_status, hwirq); if (status) { printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n", - __func__, irq, status); + __func__, hwirq, status); return -1; } @@ -418,11 +418,11 @@ xics_set_affinity(struct irq_data *d, const struct cpumask *cpumask, bool force) } status = rtas_call(ibm_set_xive, 3, 1, NULL, - irq, irq_server, xics_status[1]); + hwirq, irq_server, xics_status[1]); if (status) { printk(KERN_ERR "%s: ibm,set-xive irq=%u returns %d\n", - __func__, irq, status); + __func__, hwirq, status); return -1; } @@ -470,8 +470,8 @@ static int xics_host_map(struct irq_host *h, unsigned int virq, /* Insert the interrupt mapping into the radix tree for fast lookup */ irq_radix_revmap_insert(xics_host, virq, hw); - irq_to_desc(virq)->status |= IRQ_LEVEL; - set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq); + irq_set_status_flags(virq, IRQ_LEVEL); + irq_set_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq); return 0; } @@ -600,7 +600,7 @@ static void xics_request_ipi(void) * IPIs are marked IRQF_DISABLED as they must run with irqs * disabled */ - set_irq_handler(ipi, handle_percpu_irq); + irq_set_handler(ipi, handle_percpu_irq); if (firmware_has_feature(FW_FEATURE_LPAR)) rc = request_irq(ipi, xics_ipi_action_lpar, IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL); @@ -874,7 +874,7 @@ void xics_kexec_teardown_cpu(int secondary) void xics_migrate_irqs_away(void) { int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id(); - unsigned int irq, virq; + int virq; /* If we used to be the default server, move to the new "boot_cpuid" */ if (hw_cpu == default_server) @@ -892,18 +892,19 @@ void xics_migrate_irqs_away(void) for_each_irq(virq) { struct irq_desc *desc; struct irq_chip *chip; + unsigned int hwirq; int xics_status[2]; int status; unsigned long flags; - /* We cant set affinity on ISA interrupts */ + /* We can't set affinity on ISA interrupts */ if (virq < NUM_ISA_INTERRUPTS) continue; if (irq_map[virq].host != xics_host) continue; - irq = (unsigned int)irq_map[virq].hwirq; + hwirq = (unsigned int)irq_map[virq].hwirq; /* We need to get IPIs still. */ - if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) + if (hwirq == XICS_IPI || hwirq == XICS_IRQ_SPURIOUS) continue; desc = irq_to_desc(virq); @@ -912,16 +913,16 @@ void xics_migrate_irqs_away(void) if (desc == NULL || desc->action == NULL) continue; - chip = get_irq_desc_chip(desc); + chip = irq_desc_get_chip(desc); if (chip == NULL || chip->irq_set_affinity == NULL) continue; raw_spin_lock_irqsave(&desc->lock, flags); - status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq); + status = rtas_call(ibm_get_xive, 1, 3, xics_status, hwirq); if (status) { printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n", - __func__, irq, status); + __func__, hwirq, status); goto unlock; } diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile index 9c297347914..1e0c933ef77 100644 --- a/arch/powerpc/sysdev/Makefile +++ b/arch/powerpc/sysdev/Makefile @@ -20,7 +20,7 @@ obj-$(CONFIG_FSL_GTM) += fsl_gtm.o obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o -obj-$(CONFIG_RAPIDIO) += fsl_rio.o +obj-$(CONFIG_FSL_RIO) += fsl_rio.o obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/ diff --git a/arch/powerpc/sysdev/axonram.c b/arch/powerpc/sysdev/axonram.c index 27402c7d309..1636dd89670 100644 --- a/arch/powerpc/sysdev/axonram.c +++ b/arch/powerpc/sysdev/axonram.c @@ -95,7 +95,7 @@ axon_ram_irq_handler(int irq, void *dev) BUG_ON(!bank); - dev_err(&device->dev, "Correctable memory error occured\n"); + dev_err(&device->dev, "Correctable memory error occurred\n"); bank->ecc_counter++; return IRQ_HANDLED; } diff --git a/arch/powerpc/sysdev/bestcomm/bestcomm.h b/arch/powerpc/sysdev/bestcomm/bestcomm.h index 23a95f80dfd..a0e2e6b19b5 100644 --- a/arch/powerpc/sysdev/bestcomm/bestcomm.h +++ b/arch/powerpc/sysdev/bestcomm/bestcomm.h @@ -20,7 +20,7 @@ * struct bcom_bd - Structure describing a generic BestComm buffer descriptor * @status: The current status of this buffer. Exact meaning depends on the * task type - * @data: An array of u32 extra data. Size of array is task dependant. + * @data: An array of u32 extra data. Size of array is task dependent. * * Note: Don't dereference a bcom_bd pointer as an array. The size of the * bcom_bd is variable. Use bcom_get_bd() instead. diff --git a/arch/powerpc/sysdev/bestcomm/bestcomm_priv.h b/arch/powerpc/sysdev/bestcomm/bestcomm_priv.h index eb0d1c883c3..3b52f3ffbdf 100644 --- a/arch/powerpc/sysdev/bestcomm/bestcomm_priv.h +++ b/arch/powerpc/sysdev/bestcomm/bestcomm_priv.h @@ -97,7 +97,7 @@ struct bcom_task_header { u8 reserved[8]; }; -/* Descriptors stucture & co */ +/* Descriptors structure & co */ #define BCOM_DESC_NOP 0x000001f8 #define BCOM_LCD_MASK 0x80000000 #define BCOM_DRD_EXTENDED 0x40000000 diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c index 0476bcc7c3e..e0bc944eb23 100644 --- a/arch/powerpc/sysdev/cpm1.c +++ b/arch/powerpc/sysdev/cpm1.c @@ -103,8 +103,8 @@ static int cpm_pic_host_map(struct irq_host *h, unsigned int virq, { pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw); - irq_to_desc(virq)->status |= IRQ_LEVEL; - set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq); + irq_set_status_flags(virq, IRQ_LEVEL); + irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq); return 0; } @@ -223,7 +223,7 @@ void __init cpm_reset(void) /* Set SDMA Bus Request priority 5. * On 860T, this also enables FEC priority 6. I am not sure - * this is what we realy want for some applications, but the + * this is what we really want for some applications, but the * manual recommends it. * Bit 25, FAM can also be set to use FEC aggressive mode (860T). */ diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/cpm2_pic.c index 47303255671..5495c1be472 100644 --- a/arch/powerpc/sysdev/cpm2_pic.c +++ b/arch/powerpc/sysdev/cpm2_pic.c @@ -115,32 +115,25 @@ static void cpm2_ack(struct irq_data *d) static void cpm2_end_irq(struct irq_data *d) { - struct irq_desc *desc; int bit, word; unsigned int irq_nr = virq_to_hw(d->irq); - desc = irq_to_desc(irq_nr); - if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)) - && desc->action) { - - bit = irq_to_siubit[irq_nr]; - word = irq_to_siureg[irq_nr]; + bit = irq_to_siubit[irq_nr]; + word = irq_to_siureg[irq_nr]; - ppc_cached_irq_mask[word] |= 1 << bit; - out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]); + ppc_cached_irq_mask[word] |= 1 << bit; + out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]); - /* - * Work around large numbers of spurious IRQs on PowerPC 82xx - * systems. - */ - mb(); - } + /* + * Work around large numbers of spurious IRQs on PowerPC 82xx + * systems. + */ + mb(); } static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type) { unsigned int src = virq_to_hw(d->irq); - struct irq_desc *desc = irq_to_desc(d->irq); unsigned int vold, vnew, edibit; /* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or @@ -162,13 +155,11 @@ static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type) goto err_sense; } - desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); - desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; - if (flow_type & IRQ_TYPE_LEVEL_LOW) { - desc->status |= IRQ_LEVEL; - desc->handle_irq = handle_level_irq; - } else - desc->handle_irq = handle_edge_irq; + irqd_set_trigger_type(d, flow_type); + if (flow_type & IRQ_TYPE_LEVEL_LOW) + __irq_set_handler_locked(d->irq, handle_level_irq); + else + __irq_set_handler_locked(d->irq, handle_edge_irq); /* internal IRQ senses are LEVEL_LOW * EXT IRQ and Port C IRQ senses are programmable @@ -179,7 +170,8 @@ static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type) if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0) edibit = (31 - (CPM2_IRQ_PORTC0 - src)); else - return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL; + return (flow_type & IRQ_TYPE_LEVEL_LOW) ? + IRQ_SET_MASK_OK_NOCOPY : -EINVAL; vold = in_be32(&cpm2_intctl->ic_siexr); @@ -190,7 +182,7 @@ static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type) if (vold != vnew) out_be32(&cpm2_intctl->ic_siexr, vnew); - return 0; + return IRQ_SET_MASK_OK_NOCOPY; err_sense: pr_err("CPM2 PIC: sense type 0x%x not supported\n", flow_type); @@ -204,6 +196,7 @@ static struct irq_chip cpm2_pic = { .irq_ack = cpm2_ack, .irq_eoi = cpm2_end_irq, .irq_set_type = cpm2_set_irq_type, + .flags = IRQCHIP_EOI_IF_HANDLED, }; unsigned int cpm2_get_irq(void) @@ -226,8 +219,8 @@ static int cpm2_pic_host_map(struct irq_host *h, unsigned int virq, { pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw); - irq_to_desc(virq)->status |= IRQ_LEVEL; - set_irq_chip_and_handler(virq, &cpm2_pic, handle_level_irq); + irq_set_status_flags(virq, IRQ_LEVEL); + irq_set_chip_and_handler(virq, &cpm2_pic, handle_level_irq); return 0; } diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c index 58e09b2833f..d5679dc1e20 100644 --- a/arch/powerpc/sysdev/fsl_msi.c +++ b/arch/powerpc/sysdev/fsl_msi.c @@ -64,10 +64,10 @@ static int fsl_msi_host_map(struct irq_host *h, unsigned int virq, struct fsl_msi *msi_data = h->host_data; struct irq_chip *chip = &fsl_msi_chip; - irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING; + irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING); - set_irq_chip_data(virq, msi_data); - set_irq_chip_and_handler(virq, chip, handle_edge_irq); + irq_set_chip_data(virq, msi_data); + irq_set_chip_and_handler(virq, chip, handle_edge_irq); return 0; } @@ -110,8 +110,8 @@ static void fsl_teardown_msi_irqs(struct pci_dev *pdev) list_for_each_entry(entry, &pdev->msi_list, list) { if (entry->irq == NO_IRQ) continue; - msi_data = get_irq_data(entry->irq); - set_irq_msi(entry->irq, NULL); + msi_data = irq_get_handler_data(entry->irq); + irq_set_msi_desc(entry->irq, NULL); msi_bitmap_free_hwirqs(&msi_data->bitmap, virq_to_hw(entry->irq), 1); irq_dispose_mapping(entry->irq); @@ -168,8 +168,8 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) rc = -ENOSPC; goto out_free; } - set_irq_data(virq, msi_data); - set_irq_msi(virq, entry); + irq_set_handler_data(virq, msi_data); + irq_set_msi_desc(virq, entry); fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data); write_msi_msg(virq, &msg); @@ -183,7 +183,8 @@ out_free: static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct irq_data *idata = irq_desc_get_irq_data(desc); unsigned int cascade_irq; struct fsl_msi *msi_data; int msir_index = -1; @@ -192,20 +193,20 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) u32 have_shift = 0; struct fsl_msi_cascade_data *cascade_data; - cascade_data = (struct fsl_msi_cascade_data *)get_irq_data(irq); + cascade_data = (struct fsl_msi_cascade_data *)irq_get_handler_data(irq); msi_data = cascade_data->msi_data; raw_spin_lock(&desc->lock); if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) { if (chip->irq_mask_ack) - chip->irq_mask_ack(&desc->irq_data); + chip->irq_mask_ack(idata); else { - chip->irq_mask(&desc->irq_data); - chip->irq_ack(&desc->irq_data); + chip->irq_mask(idata); + chip->irq_ack(idata); } } - if (unlikely(desc->status & IRQ_INPROGRESS)) + if (unlikely(irqd_irq_inprogress(idata))) goto unlock; msir_index = cascade_data->index; @@ -213,7 +214,7 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) if (msir_index >= NR_MSI_REG) cascade_irq = NO_IRQ; - desc->status |= IRQ_INPROGRESS; + irqd_set_chained_irq_inprogress(idata); switch (msi_data->feature & FSL_PIC_IP_MASK) { case FSL_PIC_IP_MPIC: msir_value = fsl_msi_read(msi_data->msi_regs, @@ -235,15 +236,15 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) have_shift += intr_index + 1; msir_value = msir_value >> (intr_index + 1); } - desc->status &= ~IRQ_INPROGRESS; + irqd_clr_chained_irq_inprogress(idata); switch (msi_data->feature & FSL_PIC_IP_MASK) { case FSL_PIC_IP_MPIC: - chip->irq_eoi(&desc->irq_data); + chip->irq_eoi(idata); break; case FSL_PIC_IP_IPIC: - if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask) - chip->irq_unmask(&desc->irq_data); + if (!irqd_irq_disabled(idata) && chip->irq_unmask) + chip->irq_unmask(idata); break; } unlock: @@ -261,7 +262,7 @@ static int fsl_of_msi_remove(struct platform_device *ofdev) for (i = 0; i < NR_MSI_REG; i++) { virq = msi->msi_virqs[i]; if (virq != NO_IRQ) { - cascade_data = get_irq_data(virq); + cascade_data = irq_get_handler_data(virq); kfree(cascade_data); irq_dispose_mapping(virq); } @@ -297,8 +298,8 @@ static int __devinit fsl_msi_setup_hwirq(struct fsl_msi *msi, msi->msi_virqs[irq_index] = virt_msir; cascade_data->index = offset + irq_index; cascade_data->msi_data = msi; - set_irq_data(virt_msir, cascade_data); - set_irq_chained_handler(virt_msir, fsl_msi_cascade); + irq_set_handler_data(virt_msir, cascade_data); + irq_set_chained_handler(virt_msir, fsl_msi_cascade); return 0; } diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index f8f7f28c634..68ca9290df9 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -324,6 +324,11 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) struct resource rsrc; const int *bus_range; + if (!of_device_is_available(dev)) { + pr_warning("%s: disabled\n", dev->full_name); + return -ENODEV; + } + pr_debug("Adding PCI host bridge %s\n", dev->full_name); /* Fetch host bridge registers address */ diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c index 3eff2c3a9ad..49798532b47 100644 --- a/arch/powerpc/sysdev/fsl_rio.c +++ b/arch/powerpc/sysdev/fsl_rio.c @@ -482,7 +482,7 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid, } /** - * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue + * fsl_add_outb_message - Add message to the MPC85xx outbound message queue * @mport: Master port with outbound message queue * @rdev: Target of outbound message * @mbox: Outbound mailbox @@ -492,8 +492,8 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid, * Adds the @buffer message to the MPC85xx outbound message queue. Returns * %0 on success or %-EINVAL on failure. */ -int -rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, +static int +fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, void *buffer, size_t len) { struct rio_priv *priv = mport->priv; @@ -502,9 +502,8 @@ rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, + priv->msg_tx_ring.tx_slot; int ret = 0; - pr_debug - ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n", - rdev->destid, mbox, (int)buffer, len); + pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \ + "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len); if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) { ret = -EINVAL; @@ -554,8 +553,6 @@ rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, return ret; } -EXPORT_SYMBOL_GPL(rio_hw_add_outb_message); - /** * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler * @irq: Linux interrupt number @@ -600,7 +597,7 @@ fsl_rio_tx_handler(int irq, void *dev_instance) } /** - * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox + * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox * @mport: Master port implementing the outbound message unit * @dev_id: Device specific pointer to pass on event * @mbox: Mailbox to open @@ -610,7 +607,8 @@ fsl_rio_tx_handler(int irq, void *dev_instance) * and enables the outbound message unit. Returns %0 on success and * %-EINVAL or %-ENOMEM on failure. */ -int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) +static int +fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) { int i, j, rc = 0; struct rio_priv *priv = mport->priv; @@ -706,14 +704,14 @@ int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entr } /** - * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox + * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox * @mport: Master port implementing the outbound message unit * @mbox: Mailbox to close * * Disables the outbound message unit, free all buffers, and * frees the outbound message interrupt. */ -void rio_close_outb_mbox(struct rio_mport *mport, int mbox) +static void fsl_close_outb_mbox(struct rio_mport *mport, int mbox) { struct rio_priv *priv = mport->priv; /* Disable inbound message unit */ @@ -770,7 +768,7 @@ fsl_rio_rx_handler(int irq, void *dev_instance) } /** - * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox + * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox * @mport: Master port implementing the inbound message unit * @dev_id: Device specific pointer to pass on event * @mbox: Mailbox to open @@ -780,7 +778,8 @@ fsl_rio_rx_handler(int irq, void *dev_instance) * and enables the inbound message unit. Returns %0 on success * and %-EINVAL or %-ENOMEM on failure. */ -int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) +static int +fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) { int i, rc = 0; struct rio_priv *priv = mport->priv; @@ -844,14 +843,14 @@ int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entri } /** - * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox + * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox * @mport: Master port implementing the inbound message unit * @mbox: Mailbox to close * * Disables the inbound message unit, free all buffers, and * frees the inbound message interrupt. */ -void rio_close_inb_mbox(struct rio_mport *mport, int mbox) +static void fsl_close_inb_mbox(struct rio_mport *mport, int mbox) { struct rio_priv *priv = mport->priv; /* Disable inbound message unit */ @@ -866,7 +865,7 @@ void rio_close_inb_mbox(struct rio_mport *mport, int mbox) } /** - * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue + * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue * @mport: Master port implementing the inbound message unit * @mbox: Inbound mailbox number * @buf: Buffer to add to inbound queue @@ -874,12 +873,12 @@ void rio_close_inb_mbox(struct rio_mport *mport, int mbox) * Adds the @buf buffer to the MPC85xx inbound message queue. Returns * %0 on success or %-EINVAL on failure. */ -int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) +static int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) { int rc = 0; struct rio_priv *priv = mport->priv; - pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n", + pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n", priv->msg_rx_ring.rx_slot); if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) { @@ -898,17 +897,15 @@ int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) return rc; } -EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer); - /** - * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit + * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit * @mport: Master port implementing the inbound message unit * @mbox: Inbound mailbox number * * Gets the next available inbound message from the inbound message queue. * A pointer to the message is returned on success or NULL on failure. */ -void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox) +static void *fsl_get_inb_message(struct rio_mport *mport, int mbox) { struct rio_priv *priv = mport->priv; u32 phys_buf, virt_buf; @@ -945,8 +942,6 @@ void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox) return buf; } -EXPORT_SYMBOL_GPL(rio_hw_get_inb_message); - /** * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler * @irq: Linux interrupt number @@ -1293,28 +1288,6 @@ err_out: return rc; } -static char *cmdline = NULL; - -static int fsl_rio_get_hdid(int index) -{ - /* XXX Need to parse multiple entries in some format */ - if (!cmdline) - return -1; - - return simple_strtol(cmdline, NULL, 0); -} - -static int fsl_rio_get_cmdline(char *s) -{ - if (!s) - return 0; - - cmdline = s; - return 1; -} - -__setup("riohdid=", fsl_rio_get_cmdline); - static inline void fsl_rio_info(struct device *dev, u32 ccsr) { const char *str; @@ -1431,13 +1404,19 @@ int fsl_rio_setup(struct platform_device *dev) ops->cwrite = fsl_rio_config_write; ops->dsend = fsl_rio_doorbell_send; ops->pwenable = fsl_rio_pw_enable; + ops->open_outb_mbox = fsl_open_outb_mbox; + ops->open_inb_mbox = fsl_open_inb_mbox; + ops->close_outb_mbox = fsl_close_outb_mbox; + ops->close_inb_mbox = fsl_close_inb_mbox; + ops->add_outb_message = fsl_add_outb_message; + ops->add_inb_buffer = fsl_add_inb_buffer; + ops->get_inb_message = fsl_get_inb_message; port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL); if (!port) { rc = -ENOMEM; goto err_port; } - port->id = 0; port->index = 0; priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL); @@ -1453,6 +1432,14 @@ int fsl_rio_setup(struct platform_device *dev) port->iores.flags = IORESOURCE_MEM; port->iores.name = "rio_io_win"; + if (request_resource(&iomem_resource, &port->iores) < 0) { + dev_err(&dev->dev, "RIO: Error requesting master port region" + " 0x%016llx-0x%016llx\n", + (u64)port->iores.start, (u64)port->iores.end); + rc = -ENOMEM; + goto err_res; + } + priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0); priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2); priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3); @@ -1468,11 +1455,8 @@ int fsl_rio_setup(struct platform_device *dev) priv->dev = &dev->dev; port->ops = ops; - port->host_deviceid = fsl_rio_get_hdid(port->id); - port->priv = priv; port->phys_efptr = 0x100; - rio_register_mport(port); priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1); rio_regs_win = priv->regs_win; @@ -1519,6 +1503,9 @@ int fsl_rio_setup(struct platform_device *dev) dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n", port->sys_size ? 65536 : 256); + if (rio_register_mport(port)) + goto err; + if (port->host_deviceid >= 0) out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST | RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED); @@ -1559,6 +1546,7 @@ int fsl_rio_setup(struct platform_device *dev) return 0; err: iounmap(priv->regs_win); +err_res: kfree(priv); err_priv: kfree(port); @@ -1572,18 +1560,10 @@ err_ops: */ static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev) { - int rc; printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n", dev->dev.of_node->full_name); - rc = fsl_rio_setup(dev); - if (rc) - goto out; - - /* Enumerate all registered ports */ - rc = rio_init_mports(); -out: - return rc; + return fsl_rio_setup(dev); }; static const struct of_device_id fsl_of_rio_rpn_ids[] = { diff --git a/arch/powerpc/sysdev/i8259.c b/arch/powerpc/sysdev/i8259.c index aeda4c8d0a0..142770cb84b 100644 --- a/arch/powerpc/sysdev/i8259.c +++ b/arch/powerpc/sysdev/i8259.c @@ -175,13 +175,13 @@ static int i8259_host_map(struct irq_host *h, unsigned int virq, /* We block the internal cascade */ if (hw == 2) - irq_to_desc(virq)->status |= IRQ_NOREQUEST; + irq_set_status_flags(virq, IRQ_NOREQUEST); /* We use the level handler only for now, we might want to * be more cautious here but that works for now */ - irq_to_desc(virq)->status |= IRQ_LEVEL; - set_irq_chip_and_handler(virq, &i8259_pic, handle_level_irq); + irq_set_status_flags(virq, IRQ_LEVEL); + irq_set_chip_and_handler(virq, &i8259_pic, handle_level_irq); return 0; } @@ -191,7 +191,7 @@ static void i8259_host_unmap(struct irq_host *h, unsigned int virq) i8259_mask_irq(irq_get_irq_data(virq)); /* remove chip and handler */ - set_irq_chip_and_handler(virq, NULL, NULL); + irq_set_chip_and_handler(virq, NULL, NULL); /* Make sure it's completed */ synchronize_irq(virq); diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c index 7ed80967664..82fdad885d2 100644 --- a/arch/powerpc/sysdev/indirect_pci.c +++ b/arch/powerpc/sysdev/indirect_pci.c @@ -117,7 +117,7 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | (devfn << 8) | reg | cfg_type)); - /* surpress setting of PCI_PRIMARY_BUS */ + /* suppress setting of PCI_PRIMARY_BUS */ if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS) if ((offset == PCI_PRIMARY_BUS) && (bus->number == hose->first_busno)) diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c index 497047dc986..fa438be962b 100644 --- a/arch/powerpc/sysdev/ipic.c +++ b/arch/powerpc/sysdev/ipic.c @@ -605,7 +605,6 @@ static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type) { struct ipic *ipic = ipic_from_irq(d->irq); unsigned int src = ipic_irq_to_hw(d->irq); - struct irq_desc *desc = irq_to_desc(d->irq); unsigned int vold, vnew, edibit; if (flow_type == IRQ_TYPE_NONE) @@ -623,17 +622,16 @@ static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type) printk(KERN_ERR "ipic: edge sense not supported on internal " "interrupts\n"); return -EINVAL; + } - desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); - desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; + irqd_set_trigger_type(d, flow_type); if (flow_type & IRQ_TYPE_LEVEL_LOW) { - desc->status |= IRQ_LEVEL; - desc->handle_irq = handle_level_irq; - desc->irq_data.chip = &ipic_level_irq_chip; + __irq_set_handler_locked(d->irq, handle_level_irq); + d->chip = &ipic_level_irq_chip; } else { - desc->handle_irq = handle_edge_irq; - desc->irq_data.chip = &ipic_edge_irq_chip; + __irq_set_handler_locked(d->irq, handle_edge_irq); + d->chip = &ipic_edge_irq_chip; } /* only EXT IRQ senses are programmable on ipic @@ -655,7 +653,7 @@ static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type) } if (vold != vnew) ipic_write(ipic->regs, IPIC_SECNR, vnew); - return 0; + return IRQ_SET_MASK_OK_NOCOPY; } /* level interrupts and edge interrupts have different ack operations */ @@ -687,11 +685,11 @@ static int ipic_host_map(struct irq_host *h, unsigned int virq, { struct ipic *ipic = h->host_data; - set_irq_chip_data(virq, ipic); - set_irq_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq); + irq_set_chip_data(virq, ipic); + irq_set_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq); /* Set default irq type */ - set_irq_type(virq, IRQ_TYPE_NONE); + irq_set_irq_type(virq, IRQ_TYPE_NONE); return 0; } diff --git a/arch/powerpc/sysdev/mpc8xx_pic.c b/arch/powerpc/sysdev/mpc8xx_pic.c index 1a75a7fb4a9..a88800ff4d0 100644 --- a/arch/powerpc/sysdev/mpc8xx_pic.c +++ b/arch/powerpc/sysdev/mpc8xx_pic.c @@ -72,13 +72,6 @@ static void mpc8xx_end_irq(struct irq_data *d) static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type) { - struct irq_desc *desc = irq_to_desc(d->irq); - - desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); - desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; - if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) - desc->status |= IRQ_LEVEL; - if (flow_type & IRQ_TYPE_EDGE_FALLING) { irq_hw_number_t hw = (unsigned int)irq_map[d->irq].hwirq; unsigned int siel = in_be32(&siu_reg->sc_siel); @@ -87,7 +80,7 @@ static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type) if ((hw & 1) == 0) { siel |= (0x80000000 >> hw); out_be32(&siu_reg->sc_siel, siel); - desc->handle_irq = handle_edge_irq; + __irq_set_handler_locked(d->irq, handle_edge_irq); } } return 0; @@ -124,7 +117,7 @@ static int mpc8xx_pic_host_map(struct irq_host *h, unsigned int virq, pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw); /* Set default irq handle */ - set_irq_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq); + irq_set_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq); return 0; } diff --git a/arch/powerpc/sysdev/mpc8xxx_gpio.c b/arch/powerpc/sysdev/mpc8xxx_gpio.c index 232e701245d..0892a2841c2 100644 --- a/arch/powerpc/sysdev/mpc8xxx_gpio.c +++ b/arch/powerpc/sysdev/mpc8xxx_gpio.c @@ -145,7 +145,7 @@ static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc) { - struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_desc_data(desc); + struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc); struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; unsigned int mask; @@ -278,9 +278,9 @@ static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq, if (mpc8xxx_gc->of_dev_id_data) mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data; - set_irq_chip_data(virq, h->host_data); - set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq); - set_irq_type(virq, IRQ_TYPE_NONE); + irq_set_chip_data(virq, h->host_data); + irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq); + irq_set_irq_type(virq, IRQ_TYPE_NONE); return 0; } @@ -369,8 +369,8 @@ static void __init mpc8xxx_add_controller(struct device_node *np) out_be32(mm_gc->regs + GPIO_IER, 0xffffffff); out_be32(mm_gc->regs + GPIO_IMR, 0); - set_irq_data(hwirq, mpc8xxx_gc); - set_irq_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade); + irq_set_handler_data(hwirq, mpc8xxx_gc); + irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade); skip_irq: return; diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index eb7021815e2..f91c065bed5 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -147,6 +147,16 @@ static u32 mpic_infos[][MPIC_IDX_END] = { #endif /* CONFIG_MPIC_WEIRD */ +static inline unsigned int mpic_processor_id(struct mpic *mpic) +{ + unsigned int cpu = 0; + + if (mpic->flags & MPIC_PRIMARY) + cpu = hard_smp_processor_id(); + + return cpu; +} + /* * Register accessor functions */ @@ -210,19 +220,14 @@ static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 valu static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) { - unsigned int cpu = 0; + unsigned int cpu = mpic_processor_id(mpic); - if (mpic->flags & MPIC_PRIMARY) - cpu = hard_smp_processor_id(); return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); } static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) { - unsigned int cpu = 0; - - if (mpic->flags & MPIC_PRIMARY) - cpu = hard_smp_processor_id(); + unsigned int cpu = mpic_processor_id(mpic); _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); } @@ -356,7 +361,7 @@ static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) } static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, - unsigned int irqflags) + bool level) { struct mpic_irq_fixup *fixup = &mpic->fixups[source]; unsigned long flags; @@ -365,14 +370,14 @@ static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, if (fixup->base == NULL) return; - DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n", - source, irqflags, fixup->index); + DBG("startup_ht_interrupt(0x%x) index: %d\n", + source, fixup->index); raw_spin_lock_irqsave(&mpic->fixup_lock, flags); /* Enable and configure */ writeb(0x10 + 2 * fixup->index, fixup->base + 2); tmp = readl(fixup->base + 4); tmp &= ~(0x23U); - if (irqflags & IRQ_LEVEL) + if (level) tmp |= 0x22; writel(tmp, fixup->base + 4); raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); @@ -384,8 +389,7 @@ static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, #endif } -static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, - unsigned int irqflags) +static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source) { struct mpic_irq_fixup *fixup = &mpic->fixups[source]; unsigned long flags; @@ -394,7 +398,7 @@ static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, if (fixup->base == NULL) return; - DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags); + DBG("shutdown_ht_interrupt(0x%x)\n", source); /* Disable */ raw_spin_lock_irqsave(&mpic->fixup_lock, flags); @@ -611,7 +615,7 @@ static struct mpic *mpic_find(unsigned int irq) if (irq < NUM_ISA_INTERRUPTS) return NULL; - return get_irq_chip_data(irq); + return irq_get_chip_data(irq); } /* Determine if the linux irq is an IPI */ @@ -645,7 +649,7 @@ static inline struct mpic * mpic_from_ipi(struct irq_data *d) /* Get the mpic structure from the irq number */ static inline struct mpic * mpic_from_irq(unsigned int irq) { - return get_irq_chip_data(irq); + return irq_get_chip_data(irq); } /* Get the mpic structure from the irq data */ @@ -733,7 +737,7 @@ static void mpic_unmask_ht_irq(struct irq_data *d) mpic_unmask_irq(d); - if (irq_to_desc(d->irq)->status & IRQ_LEVEL) + if (irqd_is_level_type(d)) mpic_ht_end_irq(mpic, src); } @@ -743,7 +747,7 @@ static unsigned int mpic_startup_ht_irq(struct irq_data *d) unsigned int src = mpic_irq_to_hw(d->irq); mpic_unmask_irq(d); - mpic_startup_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status); + mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d)); return 0; } @@ -753,7 +757,7 @@ static void mpic_shutdown_ht_irq(struct irq_data *d) struct mpic *mpic = mpic_from_irq_data(d); unsigned int src = mpic_irq_to_hw(d->irq); - mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status); + mpic_shutdown_ht_interrupt(mpic, src); mpic_mask_irq(d); } @@ -770,7 +774,7 @@ static void mpic_end_ht_irq(struct irq_data *d) * latched another edge interrupt coming in anyway */ - if (irq_to_desc(d->irq)->status & IRQ_LEVEL) + if (irqd_is_level_type(d)) mpic_ht_end_irq(mpic, src); mpic_eoi(mpic); } @@ -859,7 +863,6 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) { struct mpic *mpic = mpic_from_irq_data(d); unsigned int src = mpic_irq_to_hw(d->irq); - struct irq_desc *desc = irq_to_desc(d->irq); unsigned int vecpri, vold, vnew; DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", @@ -874,10 +877,7 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) if (flow_type == IRQ_TYPE_NONE) flow_type = IRQ_TYPE_LEVEL_LOW; - desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); - desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; - if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) - desc->status |= IRQ_LEVEL; + irqd_set_trigger_type(d, flow_type); if (mpic_is_ht_interrupt(mpic, src)) vecpri = MPIC_VECPRI_POLARITY_POSITIVE | @@ -892,7 +892,7 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) if (vold != vnew) mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); - return 0; + return IRQ_SET_MASK_OK_NOCOPY;; } void mpic_set_vector(unsigned int virq, unsigned int vector) @@ -913,6 +913,20 @@ void mpic_set_vector(unsigned int virq, unsigned int vector) mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); } +void mpic_set_destination(unsigned int virq, unsigned int cpuid) +{ + struct mpic *mpic = mpic_from_irq(virq); + unsigned int src = mpic_irq_to_hw(virq); + + DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n", + mpic, virq, src, cpuid); + + if (src >= mpic->irq_count) + return; + + mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); +} + static struct irq_chip mpic_irq_chip = { .irq_mask = mpic_mask_irq, .irq_unmask = mpic_unmask_irq, @@ -964,8 +978,8 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq, WARN_ON(!(mpic->flags & MPIC_PRIMARY)); DBG("mpic: mapping as IPI\n"); - set_irq_chip_data(virq, mpic); - set_irq_chip_and_handler(virq, &mpic->hc_ipi, + irq_set_chip_data(virq, mpic); + irq_set_chip_and_handler(virq, &mpic->hc_ipi, handle_percpu_irq); return 0; } @@ -987,11 +1001,21 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq, DBG("mpic: mapping to irq chip @%p\n", chip); - set_irq_chip_data(virq, mpic); - set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq); + irq_set_chip_data(virq, mpic); + irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq); /* Set default irq type */ - set_irq_type(virq, IRQ_TYPE_NONE); + irq_set_irq_type(virq, IRQ_TYPE_NONE); + + /* If the MPIC was reset, then all vectors have already been + * initialized. Otherwise, a per source lazy initialization + * is done here. + */ + if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) { + mpic_set_vector(virq, hw); + mpic_set_destination(virq, mpic_processor_id(mpic)); + mpic_irq_set_priority(virq, 8); + } return 0; } @@ -1040,6 +1064,11 @@ static struct irq_host_ops mpic_host_ops = { .xlate = mpic_host_xlate, }; +static int mpic_reset_prohibited(struct device_node *node) +{ + return node && of_get_property(node, "pic-no-reset", NULL); +} + /* * Exported functions */ @@ -1160,7 +1189,15 @@ struct mpic * __init mpic_alloc(struct device_node *node, mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); /* Reset */ - if (flags & MPIC_WANTS_RESET) { + + /* When using a device-node, reset requests are only honored if the MPIC + * is allowed to reset. + */ + if (mpic_reset_prohibited(node)) + mpic->flags |= MPIC_NO_RESET; + + if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) { + printk(KERN_DEBUG "mpic: Resetting\n"); mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | MPIC_GREG_GCONF_RESET); @@ -1320,22 +1357,21 @@ void __init mpic_init(struct mpic *mpic) mpic_pasemi_msi_init(mpic); - if (mpic->flags & MPIC_PRIMARY) - cpu = hard_smp_processor_id(); - else - cpu = 0; + cpu = mpic_processor_id(mpic); - for (i = 0; i < mpic->num_sources; i++) { - /* start with vector = source number, and masked */ - u32 vecpri = MPIC_VECPRI_MASK | i | - (8 << MPIC_VECPRI_PRIORITY_SHIFT); + if (!(mpic->flags & MPIC_NO_RESET)) { + for (i = 0; i < mpic->num_sources; i++) { + /* start with vector = source number, and masked */ + u32 vecpri = MPIC_VECPRI_MASK | i | + (8 << MPIC_VECPRI_PRIORITY_SHIFT); - /* check if protected */ - if (mpic->protected && test_bit(i, mpic->protected)) - continue; - /* init hw */ - mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); - mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); + /* check if protected */ + if (mpic->protected && test_bit(i, mpic->protected)) + continue; + /* init hw */ + mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); + mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); + } } /* Init spurious vector */ diff --git a/arch/powerpc/sysdev/mpic_pasemi_msi.c b/arch/powerpc/sysdev/mpic_pasemi_msi.c index 0b7794acfce..38e62382070 100644 --- a/arch/powerpc/sysdev/mpic_pasemi_msi.c +++ b/arch/powerpc/sysdev/mpic_pasemi_msi.c @@ -81,7 +81,7 @@ static void pasemi_msi_teardown_msi_irqs(struct pci_dev *pdev) if (entry->irq == NO_IRQ) continue; - set_irq_msi(entry->irq, NULL); + irq_set_msi_desc(entry->irq, NULL); msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, virq_to_hw(entry->irq), ALLOC_CHUNK); irq_dispose_mapping(entry->irq); @@ -131,9 +131,9 @@ static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) */ mpic_set_vector(virq, 0); - set_irq_msi(virq, entry); - set_irq_chip(virq, &mpic_pasemi_msi_chip); - set_irq_type(virq, IRQ_TYPE_EDGE_RISING); + irq_set_msi_desc(virq, entry); + irq_set_chip(virq, &mpic_pasemi_msi_chip); + irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING); pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \ "addr 0x%x\n", virq, hwirq, msg.address_lo); diff --git a/arch/powerpc/sysdev/mpic_u3msi.c b/arch/powerpc/sysdev/mpic_u3msi.c index 71900ac7827..9a7aa0ed9c1 100644 --- a/arch/powerpc/sysdev/mpic_u3msi.c +++ b/arch/powerpc/sysdev/mpic_u3msi.c @@ -129,7 +129,7 @@ static void u3msi_teardown_msi_irqs(struct pci_dev *pdev) if (entry->irq == NO_IRQ) continue; - set_irq_msi(entry->irq, NULL); + irq_set_msi_desc(entry->irq, NULL); msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, virq_to_hw(entry->irq), 1); irq_dispose_mapping(entry->irq); @@ -166,9 +166,9 @@ static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) return -ENOSPC; } - set_irq_msi(virq, entry); - set_irq_chip(virq, &mpic_u3msi_chip); - set_irq_type(virq, IRQ_TYPE_EDGE_RISING); + irq_set_msi_desc(virq, entry); + irq_set_chip(virq, &mpic_u3msi_chip); + irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING); pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n", virq, hwirq, (unsigned long)addr); diff --git a/arch/powerpc/sysdev/mv64x60_pic.c b/arch/powerpc/sysdev/mv64x60_pic.c index bc61ebb8987..e9c633c7c08 100644 --- a/arch/powerpc/sysdev/mv64x60_pic.c +++ b/arch/powerpc/sysdev/mv64x60_pic.c @@ -213,11 +213,12 @@ static int mv64x60_host_map(struct irq_host *h, unsigned int virq, { int level1; - irq_to_desc(virq)->status |= IRQ_LEVEL; + irq_set_status_flags(virq, IRQ_LEVEL); level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET; BUG_ON(level1 > MV64x60_LEVEL1_GPP); - set_irq_chip_and_handler(virq, mv64x60_chips[level1], handle_level_irq); + irq_set_chip_and_handler(virq, mv64x60_chips[level1], + handle_level_irq); return 0; } diff --git a/arch/powerpc/sysdev/ppc4xx_pci.h b/arch/powerpc/sysdev/ppc4xx_pci.h index 56d9e5deccb..c39a134e868 100644 --- a/arch/powerpc/sysdev/ppc4xx_pci.h +++ b/arch/powerpc/sysdev/ppc4xx_pci.h @@ -324,7 +324,7 @@ #define PESDR0_460EX_IHS2 0x036D /* - * 460SX addtional DCRs + * 460SX additional DCRs */ #define PESDRn_460SX_RCEI 0x02 diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c index 8c9ded8ea07..832d6924ad1 100644 --- a/arch/powerpc/sysdev/qe_lib/qe_ic.c +++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c @@ -189,7 +189,7 @@ static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg static inline struct qe_ic *qe_ic_from_irq(unsigned int virq) { - return get_irq_chip_data(virq); + return irq_get_chip_data(virq); } static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d) @@ -267,10 +267,10 @@ static int qe_ic_host_map(struct irq_host *h, unsigned int virq, /* Default chip */ chip = &qe_ic->hc_irq; - set_irq_chip_data(virq, qe_ic); - irq_to_desc(virq)->status |= IRQ_LEVEL; + irq_set_chip_data(virq, qe_ic); + irq_set_status_flags(virq, IRQ_LEVEL); - set_irq_chip_and_handler(virq, chip, handle_level_irq); + irq_set_chip_and_handler(virq, chip, handle_level_irq); return 0; } @@ -386,13 +386,13 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags, qe_ic_write(qe_ic->regs, QEIC_CICR, temp); - set_irq_data(qe_ic->virq_low, qe_ic); - set_irq_chained_handler(qe_ic->virq_low, low_handler); + irq_set_handler_data(qe_ic->virq_low, qe_ic); + irq_set_chained_handler(qe_ic->virq_low, low_handler); if (qe_ic->virq_high != NO_IRQ && qe_ic->virq_high != qe_ic->virq_low) { - set_irq_data(qe_ic->virq_high, qe_ic); - set_irq_chained_handler(qe_ic->virq_high, high_handler); + irq_set_handler_data(qe_ic->virq_high, qe_ic); + irq_set_chained_handler(qe_ic->virq_high, high_handler); } } diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c index 02c91db9003..4d18658116e 100644 --- a/arch/powerpc/sysdev/tsi108_pci.c +++ b/arch/powerpc/sysdev/tsi108_pci.c @@ -391,8 +391,8 @@ static int pci_irq_host_map(struct irq_host *h, unsigned int virq, DBG("%s(%d, 0x%lx)\n", __func__, virq, hw); if ((virq >= 1) && (virq <= 4)){ irq = virq + IRQ_PCI_INTAD_BASE - 1; - irq_to_desc(irq)->status |= IRQ_LEVEL; - set_irq_chip(irq, &tsi108_pci_irq); + irq_set_status_flags(irq, IRQ_LEVEL); + irq_set_chip(irq, &tsi108_pci_irq); } return 0; } @@ -431,7 +431,7 @@ void __init tsi108_pci_int_init(struct device_node *node) void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); unsigned int cascade_irq = get_pci_source(); if (cascade_irq != NO_IRQ) diff --git a/arch/powerpc/sysdev/uic.c b/arch/powerpc/sysdev/uic.c index 835f7958b23..5d913851662 100644 --- a/arch/powerpc/sysdev/uic.c +++ b/arch/powerpc/sysdev/uic.c @@ -57,7 +57,6 @@ struct uic { static void uic_unmask_irq(struct irq_data *d) { - struct irq_desc *desc = irq_to_desc(d->irq); struct uic *uic = irq_data_get_irq_chip_data(d); unsigned int src = uic_irq_to_hw(d->irq); unsigned long flags; @@ -66,7 +65,7 @@ static void uic_unmask_irq(struct irq_data *d) sr = 1 << (31-src); spin_lock_irqsave(&uic->lock, flags); /* ack level-triggered interrupts here */ - if (desc->status & IRQ_LEVEL) + if (irqd_is_level_type(d)) mtdcr(uic->dcrbase + UIC_SR, sr); er = mfdcr(uic->dcrbase + UIC_ER); er |= sr; @@ -101,7 +100,6 @@ static void uic_ack_irq(struct irq_data *d) static void uic_mask_ack_irq(struct irq_data *d) { - struct irq_desc *desc = irq_to_desc(d->irq); struct uic *uic = irq_data_get_irq_chip_data(d); unsigned int src = uic_irq_to_hw(d->irq); unsigned long flags; @@ -120,7 +118,7 @@ static void uic_mask_ack_irq(struct irq_data *d) * level interrupts are ack'ed after the actual * isr call in the uic_unmask_irq() */ - if (!(desc->status & IRQ_LEVEL)) + if (!irqd_is_level_type(d)) mtdcr(uic->dcrbase + UIC_SR, sr); spin_unlock_irqrestore(&uic->lock, flags); } @@ -129,7 +127,6 @@ static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type) { struct uic *uic = irq_data_get_irq_chip_data(d); unsigned int src = uic_irq_to_hw(d->irq); - struct irq_desc *desc = irq_to_desc(d->irq); unsigned long flags; int trigger, polarity; u32 tr, pr, mask; @@ -166,11 +163,6 @@ static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type) mtdcr(uic->dcrbase + UIC_PR, pr); mtdcr(uic->dcrbase + UIC_TR, tr); - desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); - desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; - if (!trigger) - desc->status |= IRQ_LEVEL; - spin_unlock_irqrestore(&uic->lock, flags); return 0; @@ -190,13 +182,13 @@ static int uic_host_map(struct irq_host *h, unsigned int virq, { struct uic *uic = h->host_data; - set_irq_chip_data(virq, uic); + irq_set_chip_data(virq, uic); /* Despite the name, handle_level_irq() works for both level * and edge irqs on UIC. FIXME: check this is correct */ - set_irq_chip_and_handler(virq, &uic_irq_chip, handle_level_irq); + irq_set_chip_and_handler(virq, &uic_irq_chip, handle_level_irq); /* Set default irq type */ - set_irq_type(virq, IRQ_TYPE_NONE); + irq_set_irq_type(virq, IRQ_TYPE_NONE); return 0; } @@ -220,17 +212,18 @@ static struct irq_host_ops uic_host_ops = { void uic_irq_cascade(unsigned int virq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); - struct uic *uic = get_irq_data(virq); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct irq_data *idata = irq_desc_get_irq_data(desc); + struct uic *uic = irq_get_handler_data(virq); u32 msr; int src; int subvirq; raw_spin_lock(&desc->lock); - if (desc->status & IRQ_LEVEL) - chip->irq_mask(&desc->irq_data); + if (irqd_is_level_type(idata)) + chip->irq_mask(idata); else - chip->irq_mask_ack(&desc->irq_data); + chip->irq_mask_ack(idata); raw_spin_unlock(&desc->lock); msr = mfdcr(uic->dcrbase + UIC_MSR); @@ -244,10 +237,10 @@ void uic_irq_cascade(unsigned int virq, struct irq_desc *desc) uic_irq_ret: raw_spin_lock(&desc->lock); - if (desc->status & IRQ_LEVEL) - chip->irq_ack(&desc->irq_data); - if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask) - chip->irq_unmask(&desc->irq_data); + if (irqd_is_level_type(idata)) + chip->irq_ack(idata); + if (!irqd_irq_disabled(idata) && chip->irq_unmask) + chip->irq_unmask(idata); raw_spin_unlock(&desc->lock); } @@ -336,8 +329,8 @@ void __init uic_init_tree(void) cascade_virq = irq_of_parse_and_map(np, 0); - set_irq_data(cascade_virq, uic); - set_irq_chained_handler(cascade_virq, uic_irq_cascade); + irq_set_handler_data(cascade_virq, uic); + irq_set_chained_handler(cascade_virq, uic_irq_cascade); /* FIXME: setup critical cascade?? */ } diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c index 7436f3ed4df..0a13fc19e28 100644 --- a/arch/powerpc/sysdev/xilinx_intc.c +++ b/arch/powerpc/sysdev/xilinx_intc.c @@ -79,12 +79,6 @@ static void xilinx_intc_mask(struct irq_data *d) static int xilinx_intc_set_type(struct irq_data *d, unsigned int flow_type) { - struct irq_desc *desc = irq_to_desc(d->irq); - - desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); - desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; - if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) - desc->status |= IRQ_LEVEL; return 0; } @@ -170,15 +164,15 @@ static int xilinx_intc_xlate(struct irq_host *h, struct device_node *ct, static int xilinx_intc_map(struct irq_host *h, unsigned int virq, irq_hw_number_t irq) { - set_irq_chip_data(virq, h->host_data); + irq_set_chip_data(virq, h->host_data); if (xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_HIGH || xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_LOW) { - set_irq_chip_and_handler(virq, &xilinx_intc_level_irqchip, - handle_level_irq); + irq_set_chip_and_handler(virq, &xilinx_intc_level_irqchip, + handle_level_irq); } else { - set_irq_chip_and_handler(virq, &xilinx_intc_edge_irqchip, - handle_edge_irq); + irq_set_chip_and_handler(virq, &xilinx_intc_edge_irqchip, + handle_edge_irq); } return 0; } @@ -229,7 +223,7 @@ int xilinx_intc_get_irq(void) */ static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = get_irq_desc_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); unsigned int cascade_irq = i8259_irq(); if (cascade_irq) @@ -256,7 +250,7 @@ static void __init xilinx_i8259_setup_cascade(void) } i8259_init(cascade_node, 0); - set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade); + irq_set_chained_handler(cascade_irq, xilinx_i8259_cascade); /* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */ /* This looks like a dirty hack to me --gcl */ diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index d17d04cfb2c..33794c1d92c 100644 --- a/arch/powerpc/xmon/xmon.c +++ b/arch/powerpc/xmon/xmon.c @@ -821,7 +821,7 @@ cmds(struct pt_regs *excp) memzcan(); break; case 'i': - show_mem(); + show_mem(0); break; default: termch = cmd; diff --git a/arch/s390/boot/Makefile b/arch/s390/boot/Makefile index 8800cf09069..635d677d328 100644 --- a/arch/s390/boot/Makefile +++ b/arch/s390/boot/Makefile @@ -6,7 +6,7 @@ COMPILE_VERSION := __linux_compile_version_id__`hostname | \ tr -c '[0-9A-Za-z]' '_'`__`date | \ tr -c '[0-9A-Za-z]' '_'`_t -EXTRA_CFLAGS := -DCOMPILE_VERSION=$(COMPILE_VERSION) -gstabs -I. +ccflags-y := -DCOMPILE_VERSION=$(COMPILE_VERSION) -gstabs -I. targets := image targets += bzImage diff --git a/arch/s390/crypto/prng.c b/arch/s390/crypto/prng.c index 975e3ab13cb..8b16c479585 100644 --- a/arch/s390/crypto/prng.c +++ b/arch/s390/crypto/prng.c @@ -76,7 +76,7 @@ static void prng_seed(int nbytes) /* Add the entropy */ while (nbytes >= 8) { - *((__u64 *)parm_block) ^= *((__u64 *)buf+i*8); + *((__u64 *)parm_block) ^= *((__u64 *)(buf+i)); prng_add_entropy(); i += 8; nbytes -= 8; diff --git a/arch/s390/include/asm/atomic.h b/arch/s390/include/asm/atomic.h index 5c5ba10384c..d9db13810d1 100644 --- a/arch/s390/include/asm/atomic.h +++ b/arch/s390/include/asm/atomic.h @@ -9,7 +9,7 @@ * * Atomic operations that C can't guarantee us. * Useful for resource counting etc. - * s390 uses 'Compare And Swap' for atomicity in SMP enviroment. + * s390 uses 'Compare And Swap' for atomicity in SMP environment. * */ diff --git a/arch/s390/include/asm/bitops.h b/arch/s390/include/asm/bitops.h index 2e05972c508..e1c8f3a4988 100644 --- a/arch/s390/include/asm/bitops.h +++ b/arch/s390/include/asm/bitops.h @@ -742,18 +742,42 @@ static inline int sched_find_first_bit(unsigned long *b) * 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24 */ -#define ext2_set_bit(nr, addr) \ - __test_and_set_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr) -#define ext2_set_bit_atomic(lock, nr, addr) \ - test_and_set_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr) -#define ext2_clear_bit(nr, addr) \ - __test_and_clear_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr) -#define ext2_clear_bit_atomic(lock, nr, addr) \ - test_and_clear_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr) -#define ext2_test_bit(nr, addr) \ - test_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr) - -static inline int ext2_find_first_zero_bit(void *vaddr, unsigned int size) +static inline void __set_bit_le(unsigned long nr, void *addr) +{ + __set_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr); +} + +static inline void __clear_bit_le(unsigned long nr, void *addr) +{ + __clear_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr); +} + +static inline int __test_and_set_bit_le(unsigned long nr, void *addr) +{ + return __test_and_set_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr); +} + +static inline int test_and_set_bit_le(unsigned long nr, void *addr) +{ + return test_and_set_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr); +} + +static inline int __test_and_clear_bit_le(unsigned long nr, void *addr) +{ + return __test_and_clear_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr); +} + +static inline int test_and_clear_bit_le(unsigned long nr, void *addr) +{ + return test_and_clear_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr); +} + +static inline int test_bit_le(unsigned long nr, const void *addr) +{ + return test_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr); +} + +static inline int find_first_zero_bit_le(void *vaddr, unsigned int size) { unsigned long bytes, bits; @@ -764,7 +788,7 @@ static inline int ext2_find_first_zero_bit(void *vaddr, unsigned int size) return (bits < size) ? bits : size; } -static inline int ext2_find_next_zero_bit(void *vaddr, unsigned long size, +static inline int find_next_zero_bit_le(void *vaddr, unsigned long size, unsigned long offset) { unsigned long *addr = vaddr, *p; @@ -790,11 +814,10 @@ static inline int ext2_find_next_zero_bit(void *vaddr, unsigned long size, size -= __BITOPS_WORDSIZE; p++; } - return offset + ext2_find_first_zero_bit(p, size); + return offset + find_first_zero_bit_le(p, size); } -static inline unsigned long ext2_find_first_bit(void *vaddr, - unsigned long size) +static inline unsigned long find_first_bit_le(void *vaddr, unsigned long size) { unsigned long bytes, bits; @@ -805,7 +828,7 @@ static inline unsigned long ext2_find_first_bit(void *vaddr, return (bits < size) ? bits : size; } -static inline int ext2_find_next_bit(void *vaddr, unsigned long size, +static inline int find_next_bit_le(void *vaddr, unsigned long size, unsigned long offset) { unsigned long *addr = vaddr, *p; @@ -831,10 +854,14 @@ static inline int ext2_find_next_bit(void *vaddr, unsigned long size, size -= __BITOPS_WORDSIZE; p++; } - return offset + ext2_find_first_bit(p, size); + return offset + find_first_bit_le(p, size); } -#include <asm-generic/bitops/minix.h> +#define ext2_set_bit_atomic(lock, nr, addr) \ + test_and_set_bit_le(nr, addr) +#define ext2_clear_bit_atomic(lock, nr, addr) \ + test_and_clear_bit_le(nr, addr) + #endif /* __KERNEL__ */ diff --git a/arch/s390/include/asm/ccwdev.h b/arch/s390/include/asm/ccwdev.h index ff6f62e0ec3..623f2fb7177 100644 --- a/arch/s390/include/asm/ccwdev.h +++ b/arch/s390/include/asm/ccwdev.h @@ -112,7 +112,6 @@ enum uc_todo { /** * struct ccw driver - device driver for channel attached devices - * @owner: owning module * @ids: ids supported by this driver * @probe: function called on probe * @remove: function called on remove @@ -128,10 +127,8 @@ enum uc_todo { * @restore: callback for restoring after hibernation * @uc_handler: callback for unit check handler * @driver: embedded device driver structure - * @name: device driver name */ struct ccw_driver { - struct module *owner; struct ccw_device_id *ids; int (*probe) (struct ccw_device *); void (*remove) (struct ccw_device *); @@ -147,7 +144,6 @@ struct ccw_driver { int (*restore)(struct ccw_device *); enum uc_todo (*uc_handler) (struct ccw_device *, struct irb *); struct device_driver driver; - char *name; }; extern struct ccw_device *get_ccwdev_by_busid(struct ccw_driver *cdrv, diff --git a/arch/s390/include/asm/ccwgroup.h b/arch/s390/include/asm/ccwgroup.h index c79c1e787b8..f2ea2c56a7e 100644 --- a/arch/s390/include/asm/ccwgroup.h +++ b/arch/s390/include/asm/ccwgroup.h @@ -29,8 +29,6 @@ struct ccwgroup_device { /** * struct ccwgroup_driver - driver for ccw group devices - * @owner: driver owner - * @name: driver name * @max_slaves: maximum number of slave devices * @driver_id: unique id * @probe: function called on probe @@ -46,8 +44,6 @@ struct ccwgroup_device { * @driver: embedded driver structure */ struct ccwgroup_driver { - struct module *owner; - char *name; int max_slaves; unsigned long driver_id; diff --git a/arch/s390/include/asm/cio.h b/arch/s390/include/asm/cio.h index e34347d567a..fc50a3342da 100644 --- a/arch/s390/include/asm/cio.h +++ b/arch/s390/include/asm/cio.h @@ -183,7 +183,7 @@ struct esw3 { * The irb that is handed to the device driver when an interrupt occurs. For * solicited interrupts, the common I/O layer already performs checks whether * a field is valid; a field not being valid is always passed as %0. - * If a unit check occured, @ecw may contain sense data; this is retrieved + * If a unit check occurred, @ecw may contain sense data; this is retrieved * by the common I/O layer itself if the device doesn't support concurrent * sense (so that the device driver never needs to perform basic sene itself). * For unsolicited interrupts, the irb is passed as-is (expect for sense data, diff --git a/arch/s390/include/asm/cmpxchg.h b/arch/s390/include/asm/cmpxchg.h new file mode 100644 index 00000000000..7488e52efa9 --- /dev/null +++ b/arch/s390/include/asm/cmpxchg.h @@ -0,0 +1,225 @@ +/* + * Copyright IBM Corp. 1999, 2011 + * + * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>, + */ + +#ifndef __ASM_CMPXCHG_H +#define __ASM_CMPXCHG_H + +#include <linux/types.h> + +extern void __xchg_called_with_bad_pointer(void); + +static inline unsigned long __xchg(unsigned long x, void *ptr, int size) +{ + unsigned long addr, old; + int shift; + + switch (size) { + case 1: + addr = (unsigned long) ptr; + shift = (3 ^ (addr & 3)) << 3; + addr ^= addr & 3; + asm volatile( + " l %0,%4\n" + "0: lr 0,%0\n" + " nr 0,%3\n" + " or 0,%2\n" + " cs %0,0,%4\n" + " jl 0b\n" + : "=&d" (old), "=Q" (*(int *) addr) + : "d" (x << shift), "d" (~(255 << shift)), + "Q" (*(int *) addr) : "memory", "cc", "0"); + return old >> shift; + case 2: + addr = (unsigned long) ptr; + shift = (2 ^ (addr & 2)) << 3; + addr ^= addr & 2; + asm volatile( + " l %0,%4\n" + "0: lr 0,%0\n" + " nr 0,%3\n" + " or 0,%2\n" + " cs %0,0,%4\n" + " jl 0b\n" + : "=&d" (old), "=Q" (*(int *) addr) + : "d" (x << shift), "d" (~(65535 << shift)), + "Q" (*(int *) addr) : "memory", "cc", "0"); + return old >> shift; + case 4: + asm volatile( + " l %0,%3\n" + "0: cs %0,%2,%3\n" + " jl 0b\n" + : "=&d" (old), "=Q" (*(int *) ptr) + : "d" (x), "Q" (*(int *) ptr) + : "memory", "cc"); + return old; +#ifdef CONFIG_64BIT + case 8: + asm volatile( + " lg %0,%3\n" + "0: csg %0,%2,%3\n" + " jl 0b\n" + : "=&d" (old), "=m" (*(long *) ptr) + : "d" (x), "Q" (*(long *) ptr) + : "memory", "cc"); + return old; +#endif /* CONFIG_64BIT */ + } + __xchg_called_with_bad_pointer(); + return x; +} + +#define xchg(ptr, x) \ +({ \ + __typeof__(*(ptr)) __ret; \ + __ret = (__typeof__(*(ptr))) \ + __xchg((unsigned long)(x), (void *)(ptr), sizeof(*(ptr)));\ + __ret; \ +}) + +/* + * Atomic compare and exchange. Compare OLD with MEM, if identical, + * store NEW in MEM. Return the initial value in MEM. Success is + * indicated by comparing RETURN with OLD. + */ + +#define __HAVE_ARCH_CMPXCHG + +extern void __cmpxchg_called_with_bad_pointer(void); + +static inline unsigned long __cmpxchg(void *ptr, unsigned long old, + unsigned long new, int size) +{ + unsigned long addr, prev, tmp; + int shift; + + switch (size) { + case 1: + addr = (unsigned long) ptr; + shift = (3 ^ (addr & 3)) << 3; + addr ^= addr & 3; + asm volatile( + " l %0,%2\n" + "0: nr %0,%5\n" + " lr %1,%0\n" + " or %0,%3\n" + " or %1,%4\n" + " cs %0,%1,%2\n" + " jnl 1f\n" + " xr %1,%0\n" + " nr %1,%5\n" + " jnz 0b\n" + "1:" + : "=&d" (prev), "=&d" (tmp), "=Q" (*(int *) ptr) + : "d" (old << shift), "d" (new << shift), + "d" (~(255 << shift)), "Q" (*(int *) ptr) + : "memory", "cc"); + return prev >> shift; + case 2: + addr = (unsigned long) ptr; + shift = (2 ^ (addr & 2)) << 3; + addr ^= addr & 2; + asm volatile( + " l %0,%2\n" + "0: nr %0,%5\n" + " lr %1,%0\n" + " or %0,%3\n" + " or %1,%4\n" + " cs %0,%1,%2\n" + " jnl 1f\n" + " xr %1,%0\n" + " nr %1,%5\n" + " jnz 0b\n" + "1:" + : "=&d" (prev), "=&d" (tmp), "=Q" (*(int *) ptr) + : "d" (old << shift), "d" (new << shift), + "d" (~(65535 << shift)), "Q" (*(int *) ptr) + : "memory", "cc"); + return prev >> shift; + case 4: + asm volatile( + " cs %0,%3,%1\n" + : "=&d" (prev), "=Q" (*(int *) ptr) + : "0" (old), "d" (new), "Q" (*(int *) ptr) + : "memory", "cc"); + return prev; +#ifdef CONFIG_64BIT + case 8: + asm volatile( + " csg %0,%3,%1\n" + : "=&d" (prev), "=Q" (*(long *) ptr) + : "0" (old), "d" (new), "Q" (*(long *) ptr) + : "memory", "cc"); + return prev; +#endif /* CONFIG_64BIT */ + } + __cmpxchg_called_with_bad_pointer(); + return old; +} + +#define cmpxchg(ptr, o, n) \ + ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \ + (unsigned long)(n), sizeof(*(ptr)))) + +#ifdef CONFIG_64BIT +#define cmpxchg64(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ + cmpxchg((ptr), (o), (n)); \ +}) +#else /* CONFIG_64BIT */ +static inline unsigned long long __cmpxchg64(void *ptr, + unsigned long long old, + unsigned long long new) +{ + register_pair rp_old = {.pair = old}; + register_pair rp_new = {.pair = new}; + + asm volatile( + " cds %0,%2,%1" + : "+&d" (rp_old), "=Q" (ptr) + : "d" (rp_new), "Q" (ptr) + : "cc"); + return rp_old.pair; +} +#define cmpxchg64(ptr, o, n) \ + ((__typeof__(*(ptr)))__cmpxchg64((ptr), \ + (unsigned long long)(o), \ + (unsigned long long)(n))) +#endif /* CONFIG_64BIT */ + +#include <asm-generic/cmpxchg-local.h> + +static inline unsigned long __cmpxchg_local(void *ptr, + unsigned long old, + unsigned long new, int size) +{ + switch (size) { + case 1: + case 2: + case 4: +#ifdef CONFIG_64BIT + case 8: +#endif + return __cmpxchg(ptr, old, new, size); + default: + return __cmpxchg_local_generic(ptr, old, new, size); + } + + return old; +} + +/* + * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make + * them available. + */ +#define cmpxchg_local(ptr, o, n) \ + ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \ + (unsigned long)(n), sizeof(*(ptr)))) + +#define cmpxchg64_local(ptr, o, n) cmpxchg64((ptr), (o), (n)) + +#endif /* __ASM_CMPXCHG_H */ diff --git a/arch/s390/include/asm/diag.h b/arch/s390/include/asm/diag.h index 72b2e2f2d32..7e91c58072e 100644 --- a/arch/s390/include/asm/diag.h +++ b/arch/s390/include/asm/diag.h @@ -9,9 +9,22 @@ #define _ASM_S390_DIAG_H /* - * Diagnose 10: Release pages + * Diagnose 10: Release page range */ -extern void diag10(unsigned long addr); +static inline void diag10_range(unsigned long start_pfn, unsigned long num_pfn) +{ + unsigned long start_addr, end_addr; + + start_addr = start_pfn << PAGE_SHIFT; + end_addr = (start_pfn + num_pfn - 1) << PAGE_SHIFT; + + asm volatile( + "0: diag %0,%1,0x10\n" + "1:\n" + EX_TABLE(0b, 1b) + EX_TABLE(1b, 1b) + : : "a" (start_addr), "a" (end_addr)); +} /* * Diagnose 14: Input spool file manipulation diff --git a/arch/s390/include/asm/mmu_context.h b/arch/s390/include/asm/mmu_context.h index a6f0e7cc9cd..8c277caa8d3 100644 --- a/arch/s390/include/asm/mmu_context.h +++ b/arch/s390/include/asm/mmu_context.h @@ -23,7 +23,7 @@ static inline int init_new_context(struct task_struct *tsk, #ifdef CONFIG_64BIT mm->context.asce_bits |= _ASCE_TYPE_REGION3; #endif - if (current->mm->context.alloc_pgste) { + if (current->mm && current->mm->context.alloc_pgste) { /* * alloc_pgste indicates, that any NEW context will be created * with extended page tables. The old context is unchanged. The diff --git a/arch/s390/include/asm/system.h b/arch/s390/include/asm/system.h index 8f8d759f6a7..d382629a017 100644 --- a/arch/s390/include/asm/system.h +++ b/arch/s390/include/asm/system.h @@ -14,6 +14,7 @@ #include <asm/setup.h> #include <asm/processor.h> #include <asm/lowcore.h> +#include <asm/cmpxchg.h> #ifdef __KERNEL__ @@ -120,161 +121,6 @@ extern int memcpy_real(void *, void *, size_t); #define nop() asm volatile("nop") -#define xchg(ptr,x) \ -({ \ - __typeof__(*(ptr)) __ret; \ - __ret = (__typeof__(*(ptr))) \ - __xchg((unsigned long)(x), (void *)(ptr),sizeof(*(ptr))); \ - __ret; \ -}) - -extern void __xchg_called_with_bad_pointer(void); - -static inline unsigned long __xchg(unsigned long x, void * ptr, int size) -{ - unsigned long addr, old; - int shift; - - switch (size) { - case 1: - addr = (unsigned long) ptr; - shift = (3 ^ (addr & 3)) << 3; - addr ^= addr & 3; - asm volatile( - " l %0,%4\n" - "0: lr 0,%0\n" - " nr 0,%3\n" - " or 0,%2\n" - " cs %0,0,%4\n" - " jl 0b\n" - : "=&d" (old), "=Q" (*(int *) addr) - : "d" (x << shift), "d" (~(255 << shift)), - "Q" (*(int *) addr) : "memory", "cc", "0"); - return old >> shift; - case 2: - addr = (unsigned long) ptr; - shift = (2 ^ (addr & 2)) << 3; - addr ^= addr & 2; - asm volatile( - " l %0,%4\n" - "0: lr 0,%0\n" - " nr 0,%3\n" - " or 0,%2\n" - " cs %0,0,%4\n" - " jl 0b\n" - : "=&d" (old), "=Q" (*(int *) addr) - : "d" (x << shift), "d" (~(65535 << shift)), - "Q" (*(int *) addr) : "memory", "cc", "0"); - return old >> shift; - case 4: - asm volatile( - " l %0,%3\n" - "0: cs %0,%2,%3\n" - " jl 0b\n" - : "=&d" (old), "=Q" (*(int *) ptr) - : "d" (x), "Q" (*(int *) ptr) - : "memory", "cc"); - return old; -#ifdef __s390x__ - case 8: - asm volatile( - " lg %0,%3\n" - "0: csg %0,%2,%3\n" - " jl 0b\n" - : "=&d" (old), "=m" (*(long *) ptr) - : "d" (x), "Q" (*(long *) ptr) - : "memory", "cc"); - return old; -#endif /* __s390x__ */ - } - __xchg_called_with_bad_pointer(); - return x; -} - -/* - * Atomic compare and exchange. Compare OLD with MEM, if identical, - * store NEW in MEM. Return the initial value in MEM. Success is - * indicated by comparing RETURN with OLD. - */ - -#define __HAVE_ARCH_CMPXCHG 1 - -#define cmpxchg(ptr, o, n) \ - ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \ - (unsigned long)(n), sizeof(*(ptr)))) - -extern void __cmpxchg_called_with_bad_pointer(void); - -static inline unsigned long -__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) -{ - unsigned long addr, prev, tmp; - int shift; - - switch (size) { - case 1: - addr = (unsigned long) ptr; - shift = (3 ^ (addr & 3)) << 3; - addr ^= addr & 3; - asm volatile( - " l %0,%2\n" - "0: nr %0,%5\n" - " lr %1,%0\n" - " or %0,%3\n" - " or %1,%4\n" - " cs %0,%1,%2\n" - " jnl 1f\n" - " xr %1,%0\n" - " nr %1,%5\n" - " jnz 0b\n" - "1:" - : "=&d" (prev), "=&d" (tmp), "=Q" (*(int *) ptr) - : "d" (old << shift), "d" (new << shift), - "d" (~(255 << shift)), "Q" (*(int *) ptr) - : "memory", "cc"); - return prev >> shift; - case 2: - addr = (unsigned long) ptr; - shift = (2 ^ (addr & 2)) << 3; - addr ^= addr & 2; - asm volatile( - " l %0,%2\n" - "0: nr %0,%5\n" - " lr %1,%0\n" - " or %0,%3\n" - " or %1,%4\n" - " cs %0,%1,%2\n" - " jnl 1f\n" - " xr %1,%0\n" - " nr %1,%5\n" - " jnz 0b\n" - "1:" - : "=&d" (prev), "=&d" (tmp), "=Q" (*(int *) ptr) - : "d" (old << shift), "d" (new << shift), - "d" (~(65535 << shift)), "Q" (*(int *) ptr) - : "memory", "cc"); - return prev >> shift; - case 4: - asm volatile( - " cs %0,%3,%1\n" - : "=&d" (prev), "=Q" (*(int *) ptr) - : "0" (old), "d" (new), "Q" (*(int *) ptr) - : "memory", "cc"); - return prev; -#ifdef __s390x__ - case 8: - asm volatile( - " csg %0,%3,%1\n" - : "=&d" (prev), "=Q" (*(long *) ptr) - : "0" (old), "d" (new), "Q" (*(long *) ptr) - : "memory", "cc"); - return prev; -#endif /* __s390x__ */ - } - __cmpxchg_called_with_bad_pointer(); - return old; -} - /* * Force strict CPU ordering. * And yes, this is required on UP too when we're talking @@ -353,46 +199,6 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) __ctl_load(__dummy, cr, cr); \ }) -#include <linux/irqflags.h> - -#include <asm-generic/cmpxchg-local.h> - -static inline unsigned long __cmpxchg_local(volatile void *ptr, - unsigned long old, - unsigned long new, int size) -{ - switch (size) { - case 1: - case 2: - case 4: -#ifdef __s390x__ - case 8: -#endif - return __cmpxchg(ptr, old, new, size); - default: - return __cmpxchg_local_generic(ptr, old, new, size); - } - - return old; -} - -/* - * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make - * them available. - */ -#define cmpxchg_local(ptr, o, n) \ - ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \ - (unsigned long)(n), sizeof(*(ptr)))) -#ifdef __s390x__ -#define cmpxchg64_local(ptr, o, n) \ - ({ \ - BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ - cmpxchg_local((ptr), (o), (n)); \ - }) -#else -#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) -#endif - /* * Use to set psw mask except for the first byte which * won't be changed by this function. diff --git a/arch/s390/include/asm/types.h b/arch/s390/include/asm/types.h index 04d6b95a89c..eeb52ccf499 100644 --- a/arch/s390/include/asm/types.h +++ b/arch/s390/include/asm/types.h @@ -30,14 +30,6 @@ typedef __signed__ long saddr_t; #ifndef __ASSEMBLY__ -typedef u64 dma64_addr_t; -#ifdef __s390x__ -/* DMA addresses come in 32-bit and 64-bit flavours. */ -typedef u64 dma_addr_t; -#else -typedef u32 dma_addr_t; -#endif - #ifndef __s390x__ typedef union { unsigned long long pair; diff --git a/arch/s390/include/asm/unistd.h b/arch/s390/include/asm/unistd.h index 1049ef27c15..e8215257237 100644 --- a/arch/s390/include/asm/unistd.h +++ b/arch/s390/include/asm/unistd.h @@ -272,7 +272,11 @@ #define __NR_fanotify_init 332 #define __NR_fanotify_mark 333 #define __NR_prlimit64 334 -#define NR_syscalls 335 +#define __NR_name_to_handle_at 335 +#define __NR_open_by_handle_at 336 +#define __NR_clock_adjtime 337 +#define __NR_syncfs 338 +#define NR_syscalls 339 /* * There are some system calls that are not present on 64 bit, some diff --git a/arch/s390/kernel/compat_wrapper.S b/arch/s390/kernel/compat_wrapper.S index 8e60fb23b90..1dc96ea08fa 100644 --- a/arch/s390/kernel/compat_wrapper.S +++ b/arch/s390/kernel/compat_wrapper.S @@ -1877,3 +1877,30 @@ sys_prlimit64_wrapper: llgtr %r4,%r4 # const struct rlimit64 __user * llgtr %r5,%r5 # struct rlimit64 __user * jg sys_prlimit64 # branch to system call + + .globl sys_name_to_handle_at_wrapper +sys_name_to_handle_at_wrapper: + lgfr %r2,%r2 # int + llgtr %r3,%r3 # const char __user * + llgtr %r4,%r4 # struct file_handle __user * + llgtr %r5,%r5 # int __user * + lgfr %r6,%r6 # int + jg sys_name_to_handle_at + + .globl compat_sys_open_by_handle_at_wrapper +compat_sys_open_by_handle_at_wrapper: + lgfr %r2,%r2 # int + llgtr %r3,%r3 # struct file_handle __user * + lgfr %r4,%r4 # int + jg compat_sys_open_by_handle_at + + .globl compat_sys_clock_adjtime_wrapper +compat_sys_clock_adjtime_wrapper: + lgfr %r2,%r2 # clockid_t (int) + llgtr %r3,%r3 # struct compat_timex __user * + jg compat_sys_clock_adjtime + + .globl sys_syncfs_wrapper +sys_syncfs_wrapper: + lgfr %r2,%r2 # int + jg sys_syncfs diff --git a/arch/s390/kernel/diag.c b/arch/s390/kernel/diag.c index c032d11da8a..8237fc07ac7 100644 --- a/arch/s390/kernel/diag.c +++ b/arch/s390/kernel/diag.c @@ -9,27 +9,6 @@ #include <asm/diag.h> /* - * Diagnose 10: Release pages - */ -void diag10(unsigned long addr) -{ - if (addr >= 0x7ff00000) - return; - asm volatile( -#ifdef CONFIG_64BIT - " sam31\n" - " diag %0,%0,0x10\n" - "0: sam64\n" -#else - " diag %0,%0,0x10\n" - "0:\n" -#endif - EX_TABLE(0b, 0b) - : : "a" (addr)); -} -EXPORT_SYMBOL(diag10); - -/* * Diagnose 14: Input spool file manipulation */ int diag14(unsigned long rx, unsigned long ry1, unsigned long subcode) diff --git a/arch/s390/kernel/dis.c b/arch/s390/kernel/dis.c index c83726c9fe0..3d4a78fc1ad 100644 --- a/arch/s390/kernel/dis.c +++ b/arch/s390/kernel/dis.c @@ -672,6 +672,7 @@ static struct insn opcode_b2[] = { { "rp", 0x77, INSTR_S_RD }, { "stcke", 0x78, INSTR_S_RD }, { "sacf", 0x79, INSTR_S_RD }, + { "spp", 0x80, INSTR_S_RD }, { "stsi", 0x7d, INSTR_S_RD }, { "srnm", 0x99, INSTR_S_RD }, { "stfpc", 0x9c, INSTR_S_RD }, diff --git a/arch/s390/kernel/early.c b/arch/s390/kernel/early.c index 3b7e7dddc32..068f8465c4e 100644 --- a/arch/s390/kernel/early.c +++ b/arch/s390/kernel/early.c @@ -94,6 +94,7 @@ static noinline __init void create_kernel_nss(void) unsigned int sinitrd_pfn, einitrd_pfn; #endif int response; + int hlen; size_t len; char *savesys_ptr; char defsys_cmd[DEFSYS_CMD_SIZE]; @@ -124,24 +125,27 @@ static noinline __init void create_kernel_nss(void) end_pfn = PFN_UP(__pa(&_end)); min_size = end_pfn << 2; - sprintf(defsys_cmd, "DEFSYS %s 00000-%.5X EW %.5X-%.5X SR %.5X-%.5X", - kernel_nss_name, stext_pfn - 1, stext_pfn, eshared_pfn - 1, - eshared_pfn, end_pfn); + hlen = snprintf(defsys_cmd, DEFSYS_CMD_SIZE, + "DEFSYS %s 00000-%.5X EW %.5X-%.5X SR %.5X-%.5X", + kernel_nss_name, stext_pfn - 1, stext_pfn, + eshared_pfn - 1, eshared_pfn, end_pfn); #ifdef CONFIG_BLK_DEV_INITRD if (INITRD_START && INITRD_SIZE) { sinitrd_pfn = PFN_DOWN(__pa(INITRD_START)); einitrd_pfn = PFN_UP(__pa(INITRD_START + INITRD_SIZE)); min_size = einitrd_pfn << 2; - sprintf(defsys_cmd, "%s EW %.5X-%.5X", defsys_cmd, - sinitrd_pfn, einitrd_pfn); + hlen += snprintf(defsys_cmd + hlen, DEFSYS_CMD_SIZE - hlen, + " EW %.5X-%.5X", sinitrd_pfn, einitrd_pfn); } #endif - sprintf(defsys_cmd, "%s EW MINSIZE=%.7iK PARMREGS=0-13", - defsys_cmd, min_size); - sprintf(savesys_cmd, "SAVESYS %s \n IPL %s", - kernel_nss_name, kernel_nss_name); + snprintf(defsys_cmd + hlen, DEFSYS_CMD_SIZE - hlen, + " EW MINSIZE=%.7iK PARMREGS=0-13", min_size); + defsys_cmd[DEFSYS_CMD_SIZE - 1] = '\0'; + snprintf(savesys_cmd, SAVESYS_CMD_SIZE, "SAVESYS %s \n IPL %s", + kernel_nss_name, kernel_nss_name); + savesys_cmd[SAVESYS_CMD_SIZE - 1] = '\0'; __cpcmd(defsys_cmd, NULL, 0, &response); diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S index 648f64239a9..1b67fc6ebdc 100644 --- a/arch/s390/kernel/entry.S +++ b/arch/s390/kernel/entry.S @@ -836,7 +836,7 @@ restart_base: stosm __SF_EMPTY(%r15),0x04 # now we can turn dat on basr %r14,0 l %r14,restart_addr-.(%r14) - br %r14 # branch to start_secondary + basr %r14,%r14 # branch to start_secondary restart_addr: .long start_secondary .align 8 diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S index 9d3603d6c51..9fd86456349 100644 --- a/arch/s390/kernel/entry64.S +++ b/arch/s390/kernel/entry64.S @@ -841,7 +841,7 @@ restart_base: mvc __LC_SYSTEM_TIMER(8),__TI_system_timer(%r1) xc __LC_STEAL_TIMER(8),__LC_STEAL_TIMER stosm __SF_EMPTY(%r15),0x04 # now we can turn dat on - jg start_secondary + brasl %r14,start_secondary .align 8 restart_vtime: .long 0x7fffffff,0xffffffff diff --git a/arch/s390/kernel/head.S b/arch/s390/kernel/head.S index 7061398341d..fb317bf2c37 100644 --- a/arch/s390/kernel/head.S +++ b/arch/s390/kernel/head.S @@ -460,7 +460,7 @@ startup: #ifndef CONFIG_MARCH_G5 # check capabilities against MARCH_{G5,Z900,Z990,Z9_109,Z10} xc __LC_STFL_FAC_LIST(8),__LC_STFL_FAC_LIST - stfl __LC_STFL_FAC_LIST # store facility list + .insn s,0xb2b10000,__LC_STFL_FAC_LIST # store facility list tm __LC_STFL_FAC_LIST,0x01 # stfle available ? jz 0f la %r0,0 diff --git a/arch/s390/kernel/reipl64.S b/arch/s390/kernel/reipl64.S index 5e73dee63ba..9eabbc90795 100644 --- a/arch/s390/kernel/reipl64.S +++ b/arch/s390/kernel/reipl64.S @@ -78,7 +78,7 @@ do_reipl_asm: basr %r13,0 * in the ESA psw. * Bit 31 of the addresses has to be 0 for the * 31bit lpswe instruction a fact they appear to have - * ommited from the pop. + * omitted from the pop. */ .Lnewpsw: .quad 0x0000000080000000 .quad .Lpg1 diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c index 6f6350826c8..f5434d1ecb3 100644 --- a/arch/s390/kernel/setup.c +++ b/arch/s390/kernel/setup.c @@ -102,16 +102,6 @@ EXPORT_SYMBOL(lowcore_ptr); #include <asm/setup.h> -static struct resource code_resource = { - .name = "Kernel code", - .flags = IORESOURCE_BUSY | IORESOURCE_MEM, -}; - -static struct resource data_resource = { - .name = "Kernel data", - .flags = IORESOURCE_BUSY | IORESOURCE_MEM, -}; - /* * condev= and conmode= setup parameter. */ @@ -436,21 +426,43 @@ setup_lowcore(void) lowcore_ptr[0] = lc; } -static void __init -setup_resources(void) +static struct resource code_resource = { + .name = "Kernel code", + .flags = IORESOURCE_BUSY | IORESOURCE_MEM, +}; + +static struct resource data_resource = { + .name = "Kernel data", + .flags = IORESOURCE_BUSY | IORESOURCE_MEM, +}; + +static struct resource bss_resource = { + .name = "Kernel bss", + .flags = IORESOURCE_BUSY | IORESOURCE_MEM, +}; + +static struct resource __initdata *standard_resources[] = { + &code_resource, + &data_resource, + &bss_resource, +}; + +static void __init setup_resources(void) { - struct resource *res, *sub_res; - int i; + struct resource *res, *std_res, *sub_res; + int i, j; code_resource.start = (unsigned long) &_text; code_resource.end = (unsigned long) &_etext - 1; data_resource.start = (unsigned long) &_etext; data_resource.end = (unsigned long) &_edata - 1; + bss_resource.start = (unsigned long) &__bss_start; + bss_resource.end = (unsigned long) &__bss_stop - 1; for (i = 0; i < MEMORY_CHUNKS; i++) { if (!memory_chunk[i].size) continue; - res = alloc_bootmem_low(sizeof(struct resource)); + res = alloc_bootmem_low(sizeof(*res)); res->flags = IORESOURCE_BUSY | IORESOURCE_MEM; switch (memory_chunk[i].type) { case CHUNK_READ_WRITE: @@ -464,40 +476,24 @@ setup_resources(void) res->name = "reserved"; } res->start = memory_chunk[i].addr; - res->end = memory_chunk[i].addr + memory_chunk[i].size - 1; + res->end = res->start + memory_chunk[i].size - 1; request_resource(&iomem_resource, res); - if (code_resource.start >= res->start && - code_resource.start <= res->end && - code_resource.end > res->end) { - sub_res = alloc_bootmem_low(sizeof(struct resource)); - memcpy(sub_res, &code_resource, - sizeof(struct resource)); - sub_res->end = res->end; - code_resource.start = res->end + 1; - request_resource(res, sub_res); - } - - if (code_resource.start >= res->start && - code_resource.start <= res->end && - code_resource.end <= res->end) - request_resource(res, &code_resource); - - if (data_resource.start >= res->start && - data_resource.start <= res->end && - data_resource.end > res->end) { - sub_res = alloc_bootmem_low(sizeof(struct resource)); - memcpy(sub_res, &data_resource, - sizeof(struct resource)); - sub_res->end = res->end; - data_resource.start = res->end + 1; - request_resource(res, sub_res); + for (j = 0; j < ARRAY_SIZE(standard_resources); j++) { + std_res = standard_resources[j]; + if (std_res->start < res->start || + std_res->start > res->end) + continue; + if (std_res->end > res->end) { + sub_res = alloc_bootmem_low(sizeof(*sub_res)); + *sub_res = *std_res; + sub_res->end = res->end; + std_res->start = res->end + 1; + request_resource(res, sub_res); + } else { + request_resource(res, std_res); + } } - - if (data_resource.start >= res->start && - data_resource.start <= res->end && - data_resource.end <= res->end) - request_resource(res, &data_resource); } } @@ -712,7 +708,7 @@ static void __init setup_hwcaps(void) * and 1ULL<<0 as bit 63. Bits 0-31 contain the same information * as stored by stfl, bits 32-xxx contain additional facilities. * How many facility words are stored depends on the number of - * doublewords passed to the instruction. The additional facilites + * doublewords passed to the instruction. The additional facilities * are: * Bit 42: decimal floating point facility is installed * Bit 44: perform floating point operation facility is installed diff --git a/arch/s390/kernel/switch_cpu.S b/arch/s390/kernel/switch_cpu.S index 469f11b574f..20530dd2eab 100644 --- a/arch/s390/kernel/switch_cpu.S +++ b/arch/s390/kernel/switch_cpu.S @@ -46,7 +46,9 @@ smp_restart_cpu: ltr %r4,%r4 /* New stack ? */ jz 1f lr %r15,%r4 -1: basr %r14,%r2 +1: lr %r14,%r2 /* r14: Function to call */ + lr %r2,%r3 /* r2 : Parameter for function*/ + basr %r14,%r14 /* Call function */ .gprregs_addr: .long .gprregs diff --git a/arch/s390/kernel/switch_cpu64.S b/arch/s390/kernel/switch_cpu64.S index d94aacc898c..5be3f43898f 100644 --- a/arch/s390/kernel/switch_cpu64.S +++ b/arch/s390/kernel/switch_cpu64.S @@ -42,7 +42,9 @@ smp_restart_cpu: ltgr %r4,%r4 /* New stack ? */ jz 1f lgr %r15,%r4 -1: basr %r14,%r2 +1: lgr %r14,%r2 /* r14: Function to call */ + lgr %r2,%r3 /* r2 : Parameter for function*/ + basr %r14,%r14 /* Call function */ .section .data,"aw",@progbits .gprregs: diff --git a/arch/s390/kernel/syscalls.S b/arch/s390/kernel/syscalls.S index a8fee1b1439..9c65fd4ddce 100644 --- a/arch/s390/kernel/syscalls.S +++ b/arch/s390/kernel/syscalls.S @@ -343,3 +343,7 @@ SYSCALL(sys_perf_event_open,sys_perf_event_open,sys_perf_event_open_wrapper) SYSCALL(sys_fanotify_init,sys_fanotify_init,sys_fanotify_init_wrapper) SYSCALL(sys_fanotify_mark,sys_fanotify_mark,sys_fanotify_mark_wrapper) SYSCALL(sys_prlimit64,sys_prlimit64,sys_prlimit64_wrapper) +SYSCALL(sys_name_to_handle_at,sys_name_to_handle_at,sys_name_to_handle_at_wrapper) /* 335 */ +SYSCALL(sys_open_by_handle_at,sys_open_by_handle_at,compat_sys_open_by_handle_at_wrapper) +SYSCALL(sys_clock_adjtime,sys_clock_adjtime,compat_sys_clock_adjtime_wrapper) +SYSCALL(sys_syncfs,sys_syncfs,sys_syncfs_wrapper) diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c index 9e7b039458d..87be655557a 100644 --- a/arch/s390/kernel/time.c +++ b/arch/s390/kernel/time.c @@ -724,7 +724,7 @@ static void clock_sync_cpu(struct clock_sync_data *sync) } /* - * Sync the TOD clock using the port refered to by aibp. This port + * Sync the TOD clock using the port referred to by aibp. This port * has to be enabled and the other port has to be disabled. The * last eacr update has to be more than 1.6 seconds in the past. */ @@ -1012,7 +1012,7 @@ static void etr_work_fn(struct work_struct *work) eacr = etr_handle_update(&aib, eacr); /* - * Select ports to enable. The prefered synchronization mode is PPS. + * Select ports to enable. The preferred synchronization mode is PPS. * If a port can be enabled depends on a number of things: * 1) The port needs to be online and uptodate. A port is not * disabled just because it is not uptodate, but it is only @@ -1091,7 +1091,7 @@ static void etr_work_fn(struct work_struct *work) /* * Update eacr and try to synchronize the clock. If the update * of eacr caused a stepping port switch (or if we have to - * assume that a stepping port switch has occured) or the + * assume that a stepping port switch has occurred) or the * clock syncing failed, reset the sync check control bit * and set up a timer to try again after 0.5 seconds */ diff --git a/arch/s390/kernel/vdso.c b/arch/s390/kernel/vdso.c index f438d74dedb..d73630b4fe1 100644 --- a/arch/s390/kernel/vdso.c +++ b/arch/s390/kernel/vdso.c @@ -337,17 +337,17 @@ static int __init vdso_init(void) } arch_initcall(vdso_init); -int in_gate_area_no_task(unsigned long addr) +int in_gate_area_no_mm(unsigned long addr) { return 0; } -int in_gate_area(struct task_struct *task, unsigned long addr) +int in_gate_area(struct mm_struct *mm, unsigned long addr) { return 0; } -struct vm_area_struct *get_gate_vma(struct task_struct *tsk) +struct vm_area_struct *get_gate_vma(struct mm_struct *mm) { return NULL; } diff --git a/arch/s390/kernel/vtime.c b/arch/s390/kernel/vtime.c index 1ccdf4d8aa8..5e8ead4b4ab 100644 --- a/arch/s390/kernel/vtime.c +++ b/arch/s390/kernel/vtime.c @@ -44,7 +44,7 @@ static inline void set_vtimer(__u64 expires) __u64 timer; asm volatile (" STPT %0\n" /* Store current cpu timer value */ - " SPT %1" /* Set new value immediatly afterwards */ + " SPT %1" /* Set new value immediately afterwards */ : "=m" (timer) : "m" (expires) ); S390_lowcore.system_timer += S390_lowcore.last_update_timer - timer; S390_lowcore.last_update_timer = expires; diff --git a/arch/s390/kvm/Makefile b/arch/s390/kvm/Makefile index e5221ec0b8e..860d26514c0 100644 --- a/arch/s390/kvm/Makefile +++ b/arch/s390/kvm/Makefile @@ -8,7 +8,7 @@ common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o) -EXTRA_CFLAGS += -Ivirt/kvm -Iarch/s390/kvm +ccflags-y := -Ivirt/kvm -Iarch/s390/kvm kvm-objs := $(common-objs) kvm-s390.o sie64a.o intercept.o interrupt.o priv.o sigp.o diag.o obj-$(CONFIG_KVM) += kvm.o diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index bade533ba28..30ca85cce31 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -721,7 +721,7 @@ static int __init kvm_s390_init(void) /* * guests can ask for up to 255+1 double words, we need a full page - * to hold the maximum amount of facilites. On the other hand, we + * to hold the maximum amount of facilities. On the other hand, we * only set facilities that are known to work in KVM. */ facilities = (unsigned long long *) get_zeroed_page(GFP_KERNEL|GFP_DMA); diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index 9194a4b52b2..73c47bd95db 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -311,7 +311,7 @@ int kvm_s390_handle_b2(struct kvm_vcpu *vcpu) /* * a lot of B2 instructions are priviledged. We first check for - * the priviledges ones, that we can handle in the kernel. If the + * the privileged ones, that we can handle in the kernel. If the * kernel can handle this instruction, we check for the problem * state bit and (a) handle the instruction or (b) send a code 2 * program check. diff --git a/arch/s390/kvm/sie64a.S b/arch/s390/kvm/sie64a.S index 7e9d30d567b..ab0e041ac54 100644 --- a/arch/s390/kvm/sie64a.S +++ b/arch/s390/kvm/sie64a.S @@ -48,10 +48,10 @@ sie_irq_handler: tm __TI_flags+7(%r2),_TIF_EXIT_SIE jz 0f larl %r2,sie_exit # work pending, leave sie - stg %r2,__LC_RETURN_PSW+8 + stg %r2,SPI_PSW+8(0,%r15) br %r14 0: larl %r2,sie_reenter # re-enter with guest id - stg %r2,__LC_RETURN_PSW+8 + stg %r2,SPI_PSW+8(0,%r15) 1: br %r14 /* diff --git a/arch/s390/math-emu/Makefile b/arch/s390/math-emu/Makefile index c8489034105..51d399549f6 100644 --- a/arch/s390/math-emu/Makefile +++ b/arch/s390/math-emu/Makefile @@ -4,4 +4,4 @@ obj-$(CONFIG_MATHEMU) := math.o -EXTRA_CFLAGS := -I$(src) -Iinclude/math-emu -w +ccflags-y := -I$(src) -Iinclude/math-emu -w diff --git a/arch/s390/mm/cmm.c b/arch/s390/mm/cmm.c index c66ffd8dbbb..1f1dba9dcf5 100644 --- a/arch/s390/mm/cmm.c +++ b/arch/s390/mm/cmm.c @@ -91,7 +91,7 @@ static long cmm_alloc_pages(long nr, long *counter, } else free_page((unsigned long) npa); } - diag10(addr); + diag10_range(addr >> PAGE_SHIFT, 1); pa->pages[pa->index++] = addr; (*counter)++; spin_unlock(&cmm_lock); diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c index 2c57806c085..ab988135e5c 100644 --- a/arch/s390/mm/fault.c +++ b/arch/s390/mm/fault.c @@ -392,7 +392,7 @@ void __kprobes do_protection_exception(struct pt_regs *regs, long pgm_int_code, { int fault; - /* Protection exception is supressing, decrement psw address. */ + /* Protection exception is suppressing, decrement psw address. */ regs->psw.addr -= (pgm_int_code >> 16); /* * Check for low-address protection. This needs to be treated @@ -543,7 +543,6 @@ static void pfault_interrupt(unsigned int ext_int_code, struct task_struct *tsk; __u16 subcode; - kstat_cpu(smp_processor_id()).irqs[EXTINT_PFL]++; /* * Get the external interruption subcode & pfault * initial/completion signal bit. VM stores this @@ -553,14 +552,15 @@ static void pfault_interrupt(unsigned int ext_int_code, subcode = ext_int_code >> 16; if ((subcode & 0xff00) != __SUBCODE_MASK) return; + kstat_cpu(smp_processor_id()).irqs[EXTINT_PFL]++; /* * Get the token (= address of the task structure of the affected task). */ #ifdef CONFIG_64BIT - tsk = *(struct task_struct **) param64; + tsk = (struct task_struct *) param64; #else - tsk = *(struct task_struct **) param32; + tsk = (struct task_struct *) param32; #endif if (subcode & 0x0080) { diff --git a/arch/s390/mm/pageattr.c b/arch/s390/mm/pageattr.c index 122ffbd08ce..0607e4b14b2 100644 --- a/arch/s390/mm/pageattr.c +++ b/arch/s390/mm/pageattr.c @@ -24,12 +24,13 @@ static void change_page_attr(unsigned long addr, int numpages, WARN_ON_ONCE(1); continue; } - ptep = pte_offset_kernel(pmdp, addr + i * PAGE_SIZE); + ptep = pte_offset_kernel(pmdp, addr); pte = *ptep; pte = set(pte); - ptep_invalidate(&init_mm, addr + i * PAGE_SIZE, ptep); + ptep_invalidate(&init_mm, addr, ptep); *ptep = pte; + addr += PAGE_SIZE; } } diff --git a/arch/s390/oprofile/Makefile b/arch/s390/oprofile/Makefile index d698cddcfbd..524c4b61582 100644 --- a/arch/s390/oprofile/Makefile +++ b/arch/s390/oprofile/Makefile @@ -6,4 +6,5 @@ DRIVER_OBJS = $(addprefix ../../../drivers/oprofile/, \ oprofilefs.o oprofile_stats.o \ timer_int.o ) -oprofile-y := $(DRIVER_OBJS) init.o backtrace.o hwsampler.o +oprofile-y := $(DRIVER_OBJS) init.o backtrace.o +oprofile-$(CONFIG_64BIT) += hwsampler.o diff --git a/arch/s390/oprofile/hwsampler.c b/arch/s390/oprofile/hwsampler.c index 3d48f4db246..33cbd373cce 100644 --- a/arch/s390/oprofile/hwsampler.c +++ b/arch/s390/oprofile/hwsampler.c @@ -517,12 +517,8 @@ stop_exit: static int check_hardware_prerequisites(void) { - unsigned long long facility_bits[2]; - - memcpy(facility_bits, S390_lowcore.stfle_fac_list, 32); - if (!(facility_bits[1] & (1ULL << 59))) + if (!test_facility(68)) return -EOPNOTSUPP; - return 0; } /* @@ -1025,20 +1021,14 @@ deallocate_exit: return rc; } -long hwsampler_query_min_interval(void) +unsigned long hwsampler_query_min_interval(void) { - if (min_sampler_rate) - return min_sampler_rate; - else - return -EINVAL; + return min_sampler_rate; } -long hwsampler_query_max_interval(void) +unsigned long hwsampler_query_max_interval(void) { - if (max_sampler_rate) - return max_sampler_rate; - else - return -EINVAL; + return max_sampler_rate; } unsigned long hwsampler_get_sample_overflow_count(unsigned int cpu) diff --git a/arch/s390/oprofile/hwsampler.h b/arch/s390/oprofile/hwsampler.h index 8c72b59316b..1912f3bb190 100644 --- a/arch/s390/oprofile/hwsampler.h +++ b/arch/s390/oprofile/hwsampler.h @@ -102,8 +102,8 @@ int hwsampler_setup(void); int hwsampler_shutdown(void); int hwsampler_allocate(unsigned long sdbt, unsigned long sdb); int hwsampler_deallocate(void); -long hwsampler_query_min_interval(void); -long hwsampler_query_max_interval(void); +unsigned long hwsampler_query_min_interval(void); +unsigned long hwsampler_query_max_interval(void); int hwsampler_start_all(unsigned long interval); int hwsampler_stop_all(void); int hwsampler_deactivate(unsigned int cpu); diff --git a/arch/s390/oprofile/init.c b/arch/s390/oprofile/init.c index 16c76def4a9..5995e9bc72d 100644 --- a/arch/s390/oprofile/init.c +++ b/arch/s390/oprofile/init.c @@ -18,6 +18,11 @@ #include <linux/fs.h> #include "../../../drivers/oprofile/oprof.h" + +extern void s390_backtrace(struct pt_regs * const regs, unsigned int depth); + +#ifdef CONFIG_64BIT + #include "hwsampler.h" #define DEFAULT_INTERVAL 4096 @@ -37,8 +42,6 @@ static int hwsampler_running; /* start_mutex must be held to change */ static struct oprofile_operations timer_ops; -extern void s390_backtrace(struct pt_regs * const regs, unsigned int depth); - static int oprofile_hwsampler_start(void) { int retval; @@ -142,15 +145,11 @@ static int oprofile_hwsampler_init(struct oprofile_operations *ops) * create hwsampler files only if hwsampler_setup() succeeds. */ oprofile_min_interval = hwsampler_query_min_interval(); - if (oprofile_min_interval < 0) { - oprofile_min_interval = 0; + if (oprofile_min_interval == 0) return -ENODEV; - } oprofile_max_interval = hwsampler_query_max_interval(); - if (oprofile_max_interval < 0) { - oprofile_max_interval = 0; + if (oprofile_max_interval == 0) return -ENODEV; - } if (oprofile_timer_init(ops)) return -ENODEV; @@ -172,14 +171,22 @@ static void oprofile_hwsampler_exit(void) hwsampler_shutdown(); } +#endif /* CONFIG_64BIT */ + int __init oprofile_arch_init(struct oprofile_operations *ops) { ops->backtrace = s390_backtrace; +#ifdef CONFIG_64BIT return oprofile_hwsampler_init(ops); +#else + return -ENODEV; +#endif } void oprofile_arch_exit(void) { +#ifdef CONFIG_64BIT oprofile_hwsampler_exit(); +#endif } diff --git a/arch/score/Kconfig b/arch/score/Kconfig index 27b2295f41f..e73bc781cc1 100644 --- a/arch/score/Kconfig +++ b/arch/score/Kconfig @@ -3,6 +3,7 @@ menu "Machine selection" config SCORE def_bool y select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_SHOW choice prompt "System type" diff --git a/arch/score/Makefile b/arch/score/Makefile index d77dc639d8e..974aefe8612 100644 --- a/arch/score/Makefile +++ b/arch/score/Makefile @@ -40,5 +40,5 @@ archclean: define archhelp echo ' vmlinux.bin - Raw binary boot image' echo - echo ' These will be default as apropriate for a configured platform.' + echo ' These will be default as appropriate for a configured platform.' endef diff --git a/arch/score/include/asm/irqflags.h b/arch/score/include/asm/irqflags.h index 5c7563891e2..37c6ac9dd6e 100644 --- a/arch/score/include/asm/irqflags.h +++ b/arch/score/include/asm/irqflags.h @@ -29,7 +29,7 @@ static inline unsigned long arch_local_save_flags(void) static inline unsigned long arch_local_irq_save(void) { - unsigned long flags + unsigned long flags; asm volatile( " mfcr r8, cr0 \n" diff --git a/arch/score/include/asm/thread_info.h b/arch/score/include/asm/thread_info.h index 8570d08f58c..2205c62284d 100644 --- a/arch/score/include/asm/thread_info.h +++ b/arch/score/include/asm/thread_info.h @@ -71,7 +71,7 @@ struct thread_info { register struct thread_info *__current_thread_info __asm__("r28"); #define current_thread_info() __current_thread_info -#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL) +#define alloc_thread_info_node(tsk, node) kmalloc_node(THREAD_SIZE, GFP_KERNEL, node) #define free_thread_info(info) kfree(info) #endif /* !__ASSEMBLY__ */ diff --git a/arch/score/kernel/irq.c b/arch/score/kernel/irq.c index 47647dde09c..d4196732c65 100644 --- a/arch/score/kernel/irq.c +++ b/arch/score/kernel/irq.c @@ -52,9 +52,9 @@ asmlinkage void do_IRQ(int irq) irq_exit(); } -static void score_mask(unsigned int irq_nr) +static void score_mask(struct irq_data *d) { - unsigned int irq_source = 63 - irq_nr; + unsigned int irq_source = 63 - d->irq; if (irq_source < 32) __raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) | \ @@ -64,9 +64,9 @@ static void score_mask(unsigned int irq_nr) (1 << (irq_source - 32))), SCORE_PIC + INT_MASKH); } -static void score_unmask(unsigned int irq_nr) +static void score_unmask(struct irq_data *d) { - unsigned int irq_source = 63 - irq_nr; + unsigned int irq_source = 63 - d->irq; if (irq_source < 32) __raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) & \ @@ -78,9 +78,9 @@ static void score_unmask(unsigned int irq_nr) struct irq_chip score_irq_chip = { .name = "Score7-level", - .mask = score_mask, - .mask_ack = score_mask, - .unmask = score_unmask, + .irq_mask = score_mask, + .irq_mask_ack = score_mask, + .irq_unmask = score_unmask, }; /* @@ -92,7 +92,7 @@ void __init init_IRQ(void) unsigned long target_addr; for (index = 0; index < NR_IRQS; ++index) - set_irq_chip_and_handler(index, &score_irq_chip, + irq_set_chip_and_handler(index, &score_irq_chip, handle_level_irq); for (target_addr = IRQ_VECTOR_BASE_ADDR; @@ -109,40 +109,3 @@ void __init init_IRQ(void) : : "r" (EXCEPTION_VECTOR_BASE_ADDR | \ VECTOR_ADDRESS_OFFSET_MODE16)); } - -/* - * Generic, controller-independent functions: - */ -int show_interrupts(struct seq_file *p, void *v) -{ - int i = *(loff_t *)v, cpu; - struct irqaction *action; - unsigned long flags; - - if (i == 0) { - seq_puts(p, " "); - for_each_online_cpu(cpu) - seq_printf(p, "CPU%d ", cpu); - seq_putc(p, '\n'); - } - - if (i < NR_IRQS) { - spin_lock_irqsave(&irq_desc[i].lock, flags); - action = irq_desc[i].action; - if (!action) - goto unlock; - - seq_printf(p, "%3d: ", i); - seq_printf(p, "%10u ", kstat_irqs(i)); - seq_printf(p, " %8s", irq_desc[i].chip->name ? : "-"); - seq_printf(p, " %s", action->name); - for (action = action->next; action; action = action->next) - seq_printf(p, ", %s", action->name); - - seq_putc(p, '\n'); -unlock: - spin_unlock_irqrestore(&irq_desc[i].lock, flags); - } - - return 0; -} diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 2d264fa8495..4b89da248d1 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -23,9 +23,8 @@ config SUPERH select HAVE_SPARSE_IRQ select RTC_LIB select GENERIC_ATOMIC64 - # Support the deprecated APIs until MFD and GPIOLIB catch up. - select GENERIC_HARDIRQS_NO_DEPRECATED if !MFD_SUPPORT && !GPIOLIB select GENERIC_IRQ_SHOW + select ARCH_NO_SYSDEV_OPS help The SuperH is a RISC processor targeted for use in embedded systems and consumer electronics; it was also used in the Sega Dreamcast @@ -75,6 +74,9 @@ config GENERIC_CSUM config GENERIC_FIND_NEXT_BIT def_bool y +config GENERIC_FIND_BIT_LE + def_bool y + config GENERIC_HWEIGHT def_bool y diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug index 12fec72fec5..1553d56cf4e 100644 --- a/arch/sh/Kconfig.debug +++ b/arch/sh/Kconfig.debug @@ -82,7 +82,7 @@ config SH_NO_BSS_INIT help If running in painfully slow environments, such as an RTL simulation or from remote memory via SHdebug, where the memory - can already be gauranteed to ber zeroed on boot, say Y. + can already be guaranteed to ber zeroed on boot, say Y. For all other cases, say N. If this option seems perplexing, or you aren't sure, say N. diff --git a/arch/sh/boards/board-edosk7760.c b/arch/sh/boards/board-edosk7760.c index f47ac82da87..e9656a2cc4c 100644 --- a/arch/sh/boards/board-edosk7760.c +++ b/arch/sh/boards/board-edosk7760.c @@ -56,7 +56,7 @@ static struct mtd_partition edosk7760_nor_flash_partitions[] = { }, { .name = "fs", .offset = MTDPART_OFS_APPEND, - .size = SZ_26M, + .size = (26 << 20), }, { .name = "other", .offset = MTDPART_OFS_APPEND, diff --git a/arch/sh/boards/board-magicpanelr2.c b/arch/sh/boards/board-magicpanelr2.c index efba450a051..93f5039099b 100644 --- a/arch/sh/boards/board-magicpanelr2.c +++ b/arch/sh/boards/board-magicpanelr2.c @@ -388,12 +388,12 @@ static void __init init_mpr2_IRQ(void) { plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */ - set_irq_type(32, IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */ - set_irq_type(33, IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */ - set_irq_type(34, IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */ - set_irq_type(35, IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */ - set_irq_type(36, IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */ - set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */ + irq_set_irq_type(32, IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */ + irq_set_irq_type(33, IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */ + irq_set_irq_type(34, IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */ + irq_set_irq_type(35, IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */ + irq_set_irq_type(36, IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */ + irq_set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */ intc_set_priority(32, 13); /* IRQ0 CAN1 */ intc_set_priority(33, 13); /* IRQ0 CAN2 */ diff --git a/arch/sh/boards/board-sh7757lcr.c b/arch/sh/boards/board-sh7757lcr.c index a9e33569ad3..fa2a208ec6c 100644 --- a/arch/sh/boards/board-sh7757lcr.c +++ b/arch/sh/boards/board-sh7757lcr.c @@ -17,7 +17,7 @@ #include <linux/io.h> #include <linux/mmc/host.h> #include <linux/mmc/sh_mmcif.h> -#include <linux/mfd/sh_mobile_sdhi.h> +#include <linux/mmc/sh_mobile_sdhi.h> #include <cpu/sh7757.h> #include <asm/sh_eth.h> #include <asm/heartbeat.h> diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c index 3e5fc3bbf3e..618bd566cf5 100644 --- a/arch/sh/boards/mach-ap325rxa/setup.c +++ b/arch/sh/boards/mach-ap325rxa/setup.c @@ -14,8 +14,8 @@ #include <linux/device.h> #include <linux/interrupt.h> #include <linux/platform_device.h> -#include <linux/mfd/sh_mobile_sdhi.h> #include <linux/mmc/host.h> +#include <linux/mmc/sh_mobile_sdhi.h> #include <linux/mtd/physmap.h> #include <linux/mtd/sh_flctl.h> #include <linux/delay.h> @@ -156,24 +156,34 @@ static struct platform_device nand_flash_device = { #define PORT_DRVCRA 0xA405018A #define PORT_DRVCRB 0xA405018C +static int ap320_wvga_set_brightness(void *board_data, int brightness) +{ + if (brightness) { + gpio_set_value(GPIO_PTS3, 0); + __raw_writew(0x100, FPGA_BKLREG); + } else { + __raw_writew(0, FPGA_BKLREG); + gpio_set_value(GPIO_PTS3, 1); + } + + return 0; +} + +static int ap320_wvga_get_brightness(void *board_data) +{ + return gpio_get_value(GPIO_PTS3); +} + static void ap320_wvga_power_on(void *board_data, struct fb_info *info) { msleep(100); /* ASD AP-320/325 LCD ON */ __raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG); - - /* backlight */ - gpio_set_value(GPIO_PTS3, 0); - __raw_writew(0x100, FPGA_BKLREG); } static void ap320_wvga_power_off(void *board_data) { - /* backlight */ - __raw_writew(0, FPGA_BKLREG); - gpio_set_value(GPIO_PTS3, 1); - /* ASD AP-320/325 LCD OFF */ __raw_writew(0, FPGA_LCDREG); } @@ -209,6 +219,12 @@ static struct sh_mobile_lcdc_info lcdc_info = { .board_cfg = { .display_on = ap320_wvga_power_on, .display_off = ap320_wvga_power_off, + .set_brightness = ap320_wvga_set_brightness, + .get_brightness = ap320_wvga_get_brightness, + }, + .bl_info = { + .name = "sh_mobile_lcdc_bl", + .max_brightness = 1, }, } }; @@ -423,7 +439,7 @@ static struct resource sdhi0_cn3_resources[] = { [0] = { .name = "SDHI0", .start = 0x04ce0000, - .end = 0x04ce01ff, + .end = 0x04ce00ff, .flags = IORESOURCE_MEM, }, [1] = { @@ -453,7 +469,7 @@ static struct resource sdhi1_cn7_resources[] = { [0] = { .name = "SDHI1", .start = 0x04cf0000, - .end = 0x04cf01ff, + .end = 0x04cf00ff, .flags = IORESOURCE_MEM, }, [1] = { diff --git a/arch/sh/boards/mach-cayman/irq.c b/arch/sh/boards/mach-cayman/irq.c index d7ac5af9d10..311bcebdbd0 100644 --- a/arch/sh/boards/mach-cayman/irq.c +++ b/arch/sh/boards/mach-cayman/irq.c @@ -149,8 +149,8 @@ void init_cayman_irq(void) } for (i = 0; i < NR_EXT_IRQS; i++) { - set_irq_chip_and_handler(START_EXT_IRQS + i, &cayman_irq_type, - handle_level_irq); + irq_set_chip_and_handler(START_EXT_IRQS + i, + &cayman_irq_type, handle_level_irq); } /* Setup the SMSC interrupt */ diff --git a/arch/sh/boards/mach-dreamcast/irq.c b/arch/sh/boards/mach-dreamcast/irq.c index 72e7ac9549d..f63d323f411 100644 --- a/arch/sh/boards/mach-dreamcast/irq.c +++ b/arch/sh/boards/mach-dreamcast/irq.c @@ -51,7 +51,7 @@ */ #define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32) -/* Return the hardware event's bit positon within the EMR/ESR */ +/* Return the hardware event's bit position within the EMR/ESR */ #define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31) /* @@ -161,7 +161,6 @@ void systemasic_irq_init(void) return; } - set_irq_chip_and_handler(i, &systemasic_int, - handle_level_irq); + irq_set_chip_and_handler(i, &systemasic_int, handle_level_irq); } } diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c index e44480ce2ea..86a0d565ade 100644 --- a/arch/sh/boards/mach-ecovec24/setup.c +++ b/arch/sh/boards/mach-ecovec24/setup.c @@ -11,9 +11,9 @@ #include <linux/init.h> #include <linux/device.h> #include <linux/platform_device.h> -#include <linux/mfd/sh_mobile_sdhi.h> #include <linux/mmc/host.h> #include <linux/mmc/sh_mmcif.h> +#include <linux/mmc/sh_mobile_sdhi.h> #include <linux/mtd/physmap.h> #include <linux/gpio.h> #include <linux/interrupt.h> @@ -263,6 +263,18 @@ const static struct fb_videomode ecovec_dvi_modes[] = { }, }; +static int ecovec24_set_brightness(void *board_data, int brightness) +{ + gpio_set_value(GPIO_PTR1, brightness); + + return 0; +} + +static int ecovec24_get_brightness(void *board_data) +{ + return gpio_get_value(GPIO_PTR1); +} + static struct sh_mobile_lcdc_info lcdc_info = { .ch[0] = { .interface_type = RGB18, @@ -273,6 +285,12 @@ static struct sh_mobile_lcdc_info lcdc_info = { .height = 91, }, .board_cfg = { + .set_brightness = ecovec24_set_brightness, + .get_brightness = ecovec24_get_brightness, + }, + .bl_info = { + .name = "sh_mobile_lcdc_bl", + .max_brightness = 1, }, } }; @@ -464,7 +482,7 @@ static struct i2c_board_info ts_i2c_clients = { .irq = IRQ0, }; -#ifdef CONFIG_MFD_SH_MOBILE_SDHI +#if defined(CONFIG_MMC_TMIO) || defined(CONFIG_MMC_TMIO_MODULE) /* SDHI0 */ static void sdhi0_set_pwr(struct platform_device *pdev, int state) { @@ -482,7 +500,7 @@ static struct resource sdhi0_resources[] = { [0] = { .name = "SDHI0", .start = 0x04ce0000, - .end = 0x04ce01ff, + .end = 0x04ce00ff, .flags = IORESOURCE_MEM, }, [1] = { @@ -522,7 +540,7 @@ static struct resource sdhi1_resources[] = { [0] = { .name = "SDHI1", .start = 0x04cf0000, - .end = 0x04cf01ff, + .end = 0x04cf00ff, .flags = IORESOURCE_MEM, }, [1] = { @@ -880,7 +898,7 @@ static struct platform_device *ecovec_devices[] __initdata = { &ceu0_device, &ceu1_device, &keysc_device, -#ifdef CONFIG_MFD_SH_MOBILE_SDHI +#if defined(CONFIG_MMC_TMIO) || defined(CONFIG_MMC_TMIO_MODULE) &sdhi0_device, #if !defined(CONFIG_MMC_SH_MMCIF) &sdhi1_device, @@ -936,7 +954,7 @@ static void __init sh_eth_init(struct sh_eth_plat_data *pd) return; } - /* read MAC address frome EEPROM */ + /* read MAC address from EEPROM */ for (i = 0; i < sizeof(pd->mac_addr); i++) { pd->mac_addr[i] = mac_read(a, 0x10 + i); msleep(10); @@ -1102,7 +1120,7 @@ static int __init arch_setup(void) /* enable TouchScreen */ i2c_register_board_info(0, &ts_i2c_clients, 1); - set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW); } /* enable CEU0 */ @@ -1162,7 +1180,7 @@ static int __init arch_setup(void) gpio_direction_input(GPIO_PTR5); gpio_direction_input(GPIO_PTR6); -#ifdef CONFIG_MFD_SH_MOBILE_SDHI +#if defined(CONFIG_MMC_TMIO) || defined(CONFIG_MMC_TMIO_MODULE) /* enable SDHI0 on CN11 (needs DS2.4 set to ON) */ gpio_request(GPIO_FN_SDHI0CD, NULL); gpio_request(GPIO_FN_SDHI0WP, NULL); diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c index 7504daaa85d..8b4abbbd147 100644 --- a/arch/sh/boards/mach-kfr2r09/setup.c +++ b/arch/sh/boards/mach-kfr2r09/setup.c @@ -10,8 +10,8 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/interrupt.h> -#include <linux/mfd/sh_mobile_sdhi.h> #include <linux/mmc/host.h> +#include <linux/mmc/sh_mobile_sdhi.h> #include <linux/mfd/tmio.h> #include <linux/mtd/physmap.h> #include <linux/mtd/onenand.h> @@ -354,7 +354,7 @@ static struct resource kfr2r09_sh_sdhi0_resources[] = { [0] = { .name = "SDHI0", .start = 0x04ce0000, - .end = 0x04ce01ff, + .end = 0x04ce00ff, .flags = IORESOURCE_MEM, }, [1] = { diff --git a/arch/sh/boards/mach-landisk/setup.c b/arch/sh/boards/mach-landisk/setup.c index 94186cf079b..f1147caebac 100644 --- a/arch/sh/boards/mach-landisk/setup.c +++ b/arch/sh/boards/mach-landisk/setup.c @@ -23,7 +23,7 @@ static void landisk_power_off(void) { - __raw_writeb(0x01, PA_SHUTDOWN); + __raw_writeb(0x01, PA_SHUTDOWN); } static struct resource cf_ide_resources[3]; @@ -85,7 +85,7 @@ device_initcall(landisk_devices_setup); static void __init landisk_setup(char **cmdline_p) { - /* LED ON */ + /* LED ON */ __raw_writeb(__raw_readb(PA_LED) | 0x03, PA_LED); printk(KERN_INFO "I-O DATA DEVICE, INC. \"LANDISK Series\" support.\n"); @@ -97,7 +97,6 @@ static void __init landisk_setup(char **cmdline_p) */ static struct sh_machine_vector mv_landisk __initmv = { .mv_name = "LANDISK", - .mv_nr_irqs = 72, .mv_setup = landisk_setup, .mv_init_irq = init_landisk_IRQ, }; diff --git a/arch/sh/boards/mach-microdev/irq.c b/arch/sh/boards/mach-microdev/irq.c index c35001fd903..4fb00369f0e 100644 --- a/arch/sh/boards/mach-microdev/irq.c +++ b/arch/sh/boards/mach-microdev/irq.c @@ -117,7 +117,7 @@ static struct irq_chip microdev_irq_type = { static void __init make_microdev_irq(unsigned int irq) { disable_irq_nosync(irq); - set_irq_chip_and_handler(irq, µdev_irq_type, handle_level_irq); + irq_set_chip_and_handler(irq, µdev_irq_type, handle_level_irq); disable_microdev_irq(irq_get_irq_data(irq)); } diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c index 03a7ffe729d..184fde16913 100644 --- a/arch/sh/boards/mach-migor/setup.c +++ b/arch/sh/boards/mach-migor/setup.c @@ -12,8 +12,8 @@ #include <linux/interrupt.h> #include <linux/input.h> #include <linux/input/sh_keysc.h> -#include <linux/mfd/sh_mobile_sdhi.h> #include <linux/mmc/host.h> +#include <linux/mmc/sh_mobile_sdhi.h> #include <linux/mtd/physmap.h> #include <linux/mtd/nand.h> #include <linux/i2c.h> @@ -399,7 +399,7 @@ static struct resource sdhi_cn9_resources[] = { [0] = { .name = "SDHI", .start = 0x04ce0000, - .end = 0x04ce01ff, + .end = 0x04ce00ff, .flags = IORESOURCE_MEM, }, [1] = { diff --git a/arch/sh/boards/mach-se/7206/irq.c b/arch/sh/boards/mach-se/7206/irq.c index 9070d7e6070..0db058e709e 100644 --- a/arch/sh/boards/mach-se/7206/irq.c +++ b/arch/sh/boards/mach-se/7206/irq.c @@ -92,9 +92,8 @@ static void eoi_se7206_irq(struct irq_data *data) { unsigned short sts0,sts1; unsigned int irq = data->irq; - struct irq_desc *desc = irq_to_desc(irq); - if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) + if (!irqd_irq_disabled(data) && !irqd_irq_inprogress(data)) enable_se7206_irq(data); /* FPGA isr clear */ sts0 = __raw_readw(INTSTS0); @@ -126,7 +125,7 @@ static struct irq_chip se7206_irq_chip __read_mostly = { static void make_se7206_irq(unsigned int irq) { disable_irq_nosync(irq); - set_irq_chip_and_handler_name(irq, &se7206_irq_chip, + irq_set_chip_and_handler_name(irq, &se7206_irq_chip, handle_level_irq, "level"); disable_se7206_irq(irq_get_irq_data(irq)); } diff --git a/arch/sh/boards/mach-se/7343/irq.c b/arch/sh/boards/mach-se/7343/irq.c index 76255a19417..fd45ffc4834 100644 --- a/arch/sh/boards/mach-se/7343/irq.c +++ b/arch/sh/boards/mach-se/7343/irq.c @@ -67,19 +67,20 @@ void __init init_7343se_IRQ(void) return; se7343_fpga_irq[i] = irq; - set_irq_chip_and_handler_name(se7343_fpga_irq[i], + irq_set_chip_and_handler_name(se7343_fpga_irq[i], &se7343_irq_chip, - handle_level_irq, "level"); + handle_level_irq, + "level"); - set_irq_chip_data(se7343_fpga_irq[i], (void *)i); + irq_set_chip_data(se7343_fpga_irq[i], (void *)i); } - set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux); - set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); - set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux); - set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); - set_irq_chained_handler(IRQ4_IRQ, se7343_irq_demux); - set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW); - set_irq_chained_handler(IRQ5_IRQ, se7343_irq_demux); - set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW); + irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux); + irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); + irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux); + irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); + irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux); + irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW); + irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux); + irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW); } diff --git a/arch/sh/boards/mach-se/7722/irq.c b/arch/sh/boards/mach-se/7722/irq.c index c013f95628e..aac92f21ebd 100644 --- a/arch/sh/boards/mach-se/7722/irq.c +++ b/arch/sh/boards/mach-se/7722/irq.c @@ -67,16 +67,17 @@ void __init init_se7722_IRQ(void) return; se7722_fpga_irq[i] = irq; - set_irq_chip_and_handler_name(se7722_fpga_irq[i], + irq_set_chip_and_handler_name(se7722_fpga_irq[i], &se7722_irq_chip, - handle_level_irq, "level"); + handle_level_irq, + "level"); - set_irq_chip_data(se7722_fpga_irq[i], (void *)i); + irq_set_chip_data(se7722_fpga_irq[i], (void *)i); } - set_irq_chained_handler(IRQ0_IRQ, se7722_irq_demux); - set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); + irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux); + irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); - set_irq_chained_handler(IRQ1_IRQ, se7722_irq_demux); - set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); + irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux); + irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); } diff --git a/arch/sh/boards/mach-se/7724/irq.c b/arch/sh/boards/mach-se/7724/irq.c index 5bd87c22b65..c6342ce7768 100644 --- a/arch/sh/boards/mach-se/7724/irq.c +++ b/arch/sh/boards/mach-se/7724/irq.c @@ -140,17 +140,16 @@ void __init init_se7724_IRQ(void) return; } - set_irq_chip_and_handler_name(irq, - &se7724_irq_chip, + irq_set_chip_and_handler_name(irq, &se7724_irq_chip, handle_level_irq, "level"); } - set_irq_chained_handler(IRQ0_IRQ, se7724_irq_demux); - set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); + irq_set_chained_handler(IRQ0_IRQ, se7724_irq_demux); + irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); - set_irq_chained_handler(IRQ1_IRQ, se7724_irq_demux); - set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); + irq_set_chained_handler(IRQ1_IRQ, se7724_irq_demux); + irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); - set_irq_chained_handler(IRQ2_IRQ, se7724_irq_demux); - set_irq_type(IRQ2_IRQ, IRQ_TYPE_LEVEL_LOW); + irq_set_chained_handler(IRQ2_IRQ, se7724_irq_demux); + irq_set_irq_type(IRQ2_IRQ, IRQ_TYPE_LEVEL_LOW); } diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c index c8bcf6a19b5..12357671023 100644 --- a/arch/sh/boards/mach-se/7724/setup.c +++ b/arch/sh/boards/mach-se/7724/setup.c @@ -14,8 +14,8 @@ #include <linux/device.h> #include <linux/interrupt.h> #include <linux/platform_device.h> -#include <linux/mfd/sh_mobile_sdhi.h> #include <linux/mmc/host.h> +#include <linux/mmc/sh_mobile_sdhi.h> #include <linux/mtd/physmap.h> #include <linux/delay.h> #include <linux/smc91x.h> @@ -456,7 +456,7 @@ static struct resource sdhi0_cn7_resources[] = { [0] = { .name = "SDHI0", .start = 0x04ce0000, - .end = 0x04ce01ff, + .end = 0x04ce00ff, .flags = IORESOURCE_MEM, }, [1] = { @@ -488,7 +488,7 @@ static struct resource sdhi1_cn8_resources[] = { [0] = { .name = "SDHI1", .start = 0x04cf0000, - .end = 0x04cf01ff, + .end = 0x04cf00ff, .flags = IORESOURCE_MEM, }, [1] = { diff --git a/arch/sh/boards/mach-x3proto/gpio.c b/arch/sh/boards/mach-x3proto/gpio.c index 239e7406625..f33b2b57019 100644 --- a/arch/sh/boards/mach-x3proto/gpio.c +++ b/arch/sh/boards/mach-x3proto/gpio.c @@ -102,8 +102,8 @@ int __init x3proto_gpio_setup(void) spin_lock_irqsave(&x3proto_gpio_lock, flags); x3proto_gpio_irq_map[i] = irq; - set_irq_chip_and_handler_name(irq, &dummy_irq_chip, - handle_simple_irq, "gpio"); + irq_set_chip_and_handler_name(irq, &dummy_irq_chip, + handle_simple_irq, "gpio"); spin_unlock_irqrestore(&x3proto_gpio_lock, flags); } @@ -113,8 +113,8 @@ int __init x3proto_gpio_setup(void) x3proto_gpio_chip.base + x3proto_gpio_chip.ngpio, ilsel); - set_irq_chained_handler(ilsel, x3proto_gpio_irq_handler); - set_irq_wake(ilsel, 1); + irq_set_chained_handler(ilsel, x3proto_gpio_irq_handler); + irq_set_irq_wake(ilsel, 1); return 0; diff --git a/arch/sh/boot/romimage/mmcif-sh7724.c b/arch/sh/boot/romimage/mmcif-sh7724.c index c84e7831018..16b122510c8 100644 --- a/arch/sh/boot/romimage/mmcif-sh7724.c +++ b/arch/sh/boot/romimage/mmcif-sh7724.c @@ -9,6 +9,7 @@ */ #include <linux/mmc/sh_mmcif.h> +#include <linux/mmc/boot.h> #include <mach/romimage.h> #define MMCIF_BASE (void __iomem *)0xa4ca0000 @@ -29,7 +30,7 @@ */ asmlinkage void mmcif_loader(unsigned char *buf, unsigned long no_bytes) { - mmcif_update_progress(MMCIF_PROGRESS_ENTER); + mmcif_update_progress(MMC_PROGRESS_ENTER); /* enable clock to the MMCIF hardware block */ __raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2); @@ -52,12 +53,12 @@ asmlinkage void mmcif_loader(unsigned char *buf, unsigned long no_bytes) /* high drive capability for MMC pins */ __raw_writew(__raw_readw(DRVCRA) | 0x3000, DRVCRA); - mmcif_update_progress(MMCIF_PROGRESS_INIT); + mmcif_update_progress(MMC_PROGRESS_INIT); /* setup MMCIF hardware */ sh_mmcif_boot_init(MMCIF_BASE); - mmcif_update_progress(MMCIF_PROGRESS_LOAD); + mmcif_update_progress(MMC_PROGRESS_LOAD); /* load kernel via MMCIF interface */ sh_mmcif_boot_do_read(MMCIF_BASE, 512, @@ -67,5 +68,5 @@ asmlinkage void mmcif_loader(unsigned char *buf, unsigned long no_bytes) /* disable clock to the MMCIF hardware block */ __raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2); - mmcif_update_progress(MMCIF_PROGRESS_DONE); + mmcif_update_progress(MMC_PROGRESS_DONE); } diff --git a/arch/sh/cchips/hd6446x/hd64461.c b/arch/sh/cchips/hd6446x/hd64461.c index 177a10b25ca..eb4ea4d44d5 100644 --- a/arch/sh/cchips/hd6446x/hd64461.c +++ b/arch/sh/cchips/hd6446x/hd64461.c @@ -107,12 +107,12 @@ int __init setup_hd64461(void) return -EINVAL; } - set_irq_chip_and_handler(i, &hd64461_irq_chip, + irq_set_chip_and_handler(i, &hd64461_irq_chip, handle_level_irq); } - set_irq_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux); - set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW); + irq_set_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux); + irq_set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW); #ifdef CONFIG_HD64461_ENABLER printk(KERN_INFO "HD64461: enabling PCMCIA devices\n"); diff --git a/arch/sh/drivers/pci/pci-sh7751.h b/arch/sh/drivers/pci/pci-sh7751.h index 4983a4d2035..5ede38c330d 100644 --- a/arch/sh/drivers/pci/pci-sh7751.h +++ b/arch/sh/drivers/pci/pci-sh7751.h @@ -61,7 +61,7 @@ #define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */ #define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */ #define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */ - #define SH7751_PCICONF3_HD7 0x00800000 /* Single Funtion device */ + #define SH7751_PCICONF3_HD7 0x00800000 /* Single Function device */ #define SH7751_PCICONF3_HD6_0 0x007F0000 /* Configuration Layout */ #define SH7751_PCICONF3_LAT 0x0000FF00 /* Latency Timer */ #define SH7751_PCICONF3_CLS 0x000000FF /* Cache Line Size */ diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c index a09c77dd09d..194231cb5a7 100644 --- a/arch/sh/drivers/pci/pci.c +++ b/arch/sh/drivers/pci/pci.c @@ -84,7 +84,7 @@ int __devinit register_pci_controller(struct pci_channel *hose) hose_tail = &hose->next; /* - * Do not panic here but later - this might hapen before console init. + * Do not panic here but later - this might happen before console init. */ if (!hose->io_map_base) { printk(KERN_WARNING diff --git a/arch/sh/include/asm/bitops.h b/arch/sh/include/asm/bitops.h index 98511e4d28c..90fa3e48b4d 100644 --- a/arch/sh/include/asm/bitops.h +++ b/arch/sh/include/asm/bitops.h @@ -94,9 +94,8 @@ static inline unsigned long ffz(unsigned long word) #include <asm-generic/bitops/hweight.h> #include <asm-generic/bitops/lock.h> #include <asm-generic/bitops/sched.h> -#include <asm-generic/bitops/ext2-non-atomic.h> +#include <asm-generic/bitops/le.h> #include <asm-generic/bitops/ext2-atomic.h> -#include <asm-generic/bitops/minix.h> #include <asm-generic/bitops/fls.h> #include <asm-generic/bitops/__fls.h> #include <asm-generic/bitops/fls64.h> diff --git a/arch/sh/include/asm/page.h b/arch/sh/include/asm/page.h index c4e0b3d472b..822d6084195 100644 --- a/arch/sh/include/asm/page.h +++ b/arch/sh/include/asm/page.h @@ -186,7 +186,7 @@ typedef struct page *pgtable_t; /* * While BYTES_PER_WORD == 4 on the current sh64 ABI, GCC will still * happily generate {ld/st}.q pairs, requiring us to have 8-byte - * alignment to avoid traps. The kmalloc alignment is gauranteed by + * alignment to avoid traps. The kmalloc alignment is guaranteed by * virtue of L1_CACHE_BYTES, requiring this to only be special cased * for slab caches. */ diff --git a/arch/sh/include/asm/pgtable_32.h b/arch/sh/include/asm/pgtable_32.h index b799fe71114..0bce3d81569 100644 --- a/arch/sh/include/asm/pgtable_32.h +++ b/arch/sh/include/asm/pgtable_32.h @@ -167,7 +167,7 @@ static inline unsigned long copy_ptea_attributes(unsigned long x) #endif /* - * Mask of bits that are to be preserved accross pgprot changes. + * Mask of bits that are to be preserved across pgprot changes. */ #define _PAGE_CHG_MASK \ (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | \ diff --git a/arch/sh/include/asm/sizes.h b/arch/sh/include/asm/sizes.h index 0b9fe2d5c36..dd248c2e108 100644 --- a/arch/sh/include/asm/sizes.h +++ b/arch/sh/include/asm/sizes.h @@ -1,62 +1 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* DO NOT EDIT!! - this file automatically generated - * from .s file by awk -f s2h.awk - */ -/* Size definitions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_16 0x00000010 -#define SZ_32 0x00000020 -#define SZ_64 0x00000040 -#define SZ_128 0x00000080 -#define SZ_256 0x00000100 -#define SZ_512 0x00000200 - -#define SZ_1K 0x00000400 -#define SZ_2K 0x00000800 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_26M 0x01a00000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif - -/* END */ +#include <asm-generic/sizes.h> diff --git a/arch/sh/include/asm/thread_info.h b/arch/sh/include/asm/thread_info.h index c228946926e..ea2d5089de1 100644 --- a/arch/sh/include/asm/thread_info.h +++ b/arch/sh/include/asm/thread_info.h @@ -95,7 +95,7 @@ static inline struct thread_info *current_thread_info(void) #endif -extern struct thread_info *alloc_thread_info(struct task_struct *tsk); +extern struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node); extern void free_thread_info(struct thread_info *ti); extern void arch_task_cache_init(void); #define arch_task_cache_init arch_task_cache_init diff --git a/arch/sh/include/asm/unaligned-sh4a.h b/arch/sh/include/asm/unaligned-sh4a.h index c48a9c3420d..95adc500cab 100644 --- a/arch/sh/include/asm/unaligned-sh4a.h +++ b/arch/sh/include/asm/unaligned-sh4a.h @@ -9,7 +9,7 @@ * struct. * * The same note as with the movli.l/movco.l pair applies here, as long - * as the load is gauranteed to be inlined, nothing else will hook in to + * as the load is guaranteed to be inlined, nothing else will hook in to * r0 and we get the return value for free. * * NOTE: Due to the fact we require r0 encoding, care should be taken to diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h index b5a74e88028..ca7765e5f96 100644 --- a/arch/sh/include/asm/unistd_32.h +++ b/arch/sh/include/asm/unistd_32.h @@ -372,8 +372,9 @@ #define __NR_name_to_handle_at 359 #define __NR_open_by_handle_at 360 #define __NR_clock_adjtime 361 +#define __NR_syncfs 362 -#define NR_syscalls 362 +#define NR_syscalls 363 #ifdef __KERNEL__ diff --git a/arch/sh/include/asm/unistd_64.h b/arch/sh/include/asm/unistd_64.h index 953da4a5219..a694009bb81 100644 --- a/arch/sh/include/asm/unistd_64.h +++ b/arch/sh/include/asm/unistd_64.h @@ -393,10 +393,11 @@ #define __NR_name_to_handle_at 370 #define __NR_open_by_handle_at 371 #define __NR_clock_adjtime 372 +#define __NR_syncfs 373 #ifdef __KERNEL__ -#define NR_syscalls 373 +#define NR_syscalls 374 #define __ARCH_WANT_IPC_PARSE_VERSION #define __ARCH_WANT_OLD_READDIR diff --git a/arch/sh/include/mach-common/mach/highlander.h b/arch/sh/include/mach-common/mach/highlander.h index 5d9d4d5154b..6ce944e33e5 100644 --- a/arch/sh/include/mach-common/mach/highlander.h +++ b/arch/sh/include/mach-common/mach/highlander.h @@ -24,7 +24,7 @@ #define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */ #define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */ #define PA_AUDIOSEL (PA_BCR+0x0020) /* Sound Interface Select control */ -#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */ +#define PA_EXTPLR (PA_BCR+0x001e) /* Extension Pin Polarity control */ #define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */ #define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */ #define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */ @@ -89,7 +89,7 @@ #define PA_OBLED (PA_BCR+0x0018) /* On Board LED control */ #define PA_OBSW (PA_BCR+0x001a) /* On Board Switch control */ #define PA_AUDIOSEL (PA_BCR+0x001c) /* Sound Interface Select control */ -#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */ +#define PA_EXTPLR (PA_BCR+0x001e) /* Extension Pin Polarity control */ #define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */ #define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */ #define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */ diff --git a/arch/sh/include/mach-common/mach/r2d.h b/arch/sh/include/mach-common/mach/r2d.h index 0a800157b82..e04f75eaa15 100644 --- a/arch/sh/include/mach-common/mach/r2d.h +++ b/arch/sh/include/mach-common/mach/r2d.h @@ -18,18 +18,18 @@ #define PA_DISPCTL 0xa4000008 /* Display Timing control */ #define PA_SDMPOW 0xa400000a /* SD Power control */ #define PA_RTCCE 0xa400000c /* RTC(9701) Enable control */ -#define PA_PCICD 0xa400000e /* PCI Extention detect control */ +#define PA_PCICD 0xa400000e /* PCI Extension detect control */ #define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */ #define PA_R2D1_AXRST 0xa4000022 /* AX_LAN Reset control */ #define PA_R2D1_CFRST 0xa4000024 /* CF Reset control */ #define PA_R2D1_ADMRTS 0xa4000026 /* SD Reset control */ -#define PA_R2D1_EXTRST 0xa4000028 /* Extention Reset control */ +#define PA_R2D1_EXTRST 0xa4000028 /* Extension Reset control */ #define PA_R2D1_CFCDINTCLR 0xa400002a /* CF Insert Interrupt clear */ #define PA_R2DPLUS_CFRST 0xa4000022 /* CF Reset control */ #define PA_R2DPLUS_ADMRTS 0xa4000024 /* SD Reset control */ -#define PA_R2DPLUS_EXTRST 0xa4000026 /* Extention Reset control */ +#define PA_R2DPLUS_EXTRST 0xa4000026 /* Extension Reset control */ #define PA_R2DPLUS_CFCDINTCLR 0xa4000028 /* CF Insert Interrupt clear */ #define PA_R2DPLUS_KEYCTLCLR 0xa400002a /* Key Interrupt clear */ diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c index dd0e0f21135..8f63a264a84 100644 --- a/arch/sh/kernel/cpu/clock-cpg.c +++ b/arch/sh/kernel/cpu/clock-cpg.c @@ -67,7 +67,7 @@ int __init __deprecated cpg_clk_init(void) } /* - * Placeholder for compatability, until the lazy CPUs do this + * Placeholder for compatibility, until the lazy CPUs do this * on their own. */ int __init __weak arch_clk_init(void) diff --git a/arch/sh/kernel/cpu/irq/imask.c b/arch/sh/kernel/cpu/irq/imask.c index 32c825c9488..39b6a24c159 100644 --- a/arch/sh/kernel/cpu/irq/imask.c +++ b/arch/sh/kernel/cpu/irq/imask.c @@ -80,6 +80,6 @@ static struct irq_chip imask_irq_chip = { void make_imask_irq(unsigned int irq) { - set_irq_chip_and_handler_name(irq, &imask_irq_chip, - handle_level_irq, "level"); + irq_set_chip_and_handler_name(irq, &imask_irq_chip, handle_level_irq, + "level"); } diff --git a/arch/sh/kernel/cpu/irq/intc-sh5.c b/arch/sh/kernel/cpu/irq/intc-sh5.c index 5af48f8357e..9e056a3a0c7 100644 --- a/arch/sh/kernel/cpu/irq/intc-sh5.c +++ b/arch/sh/kernel/cpu/irq/intc-sh5.c @@ -135,7 +135,7 @@ void __init plat_irq_setup(void) /* Set default: per-line enable/disable, priority driven ack/eoi */ for (i = 0; i < NR_INTC_IRQS; i++) - set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq); /* Disable all interrupts and set all priorities to 0 to avoid trouble */ diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c index 7516c35ee51..5de6dff5c21 100644 --- a/arch/sh/kernel/cpu/irq/ipr.c +++ b/arch/sh/kernel/cpu/irq/ipr.c @@ -74,9 +74,9 @@ void register_ipr_controller(struct ipr_desc *desc) } disable_irq_nosync(p->irq); - set_irq_chip_and_handler_name(p->irq, &desc->chip, - handle_level_irq, "level"); - set_irq_chip_data(p->irq, p); + irq_set_chip_and_handler_name(p->irq, &desc->chip, + handle_level_irq, "level"); + irq_set_chip_data(p->irq, p); disable_ipr_irq(irq_get_irq_data(p->irq)); } } diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c index 1656b8c91fa..beba32beb6d 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c @@ -648,7 +648,7 @@ static void __init sh7786_usb_setup(void) * The following settings are necessary * for using the USB modules. * - * see "USB Inital Settings" for detail + * see "USB Initial Settings" for detail */ __raw_writel(USBINITVAL1, USBINITREG1); __raw_writel(USBINITVAL2, USBINITREG2); diff --git a/arch/sh/kernel/crash_dump.c b/arch/sh/kernel/crash_dump.c index 37c97d44457..569e7b171c0 100644 --- a/arch/sh/kernel/crash_dump.c +++ b/arch/sh/kernel/crash_dump.c @@ -9,28 +9,6 @@ #include <linux/io.h> #include <asm/uaccess.h> -/* Stores the physical address of elf header of crash image. */ -unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX; - -/* - * Note: elfcorehdr_addr is not just limited to vmcore. It is also used by - * is_kdump_kernel() to determine if we are booting after a panic. Hence - * ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE. - * - * elfcorehdr= specifies the location of elf core header - * stored by the crashed kernel. - */ -static int __init parse_elfcorehdr(char *arg) -{ - if (!arg) - return -EINVAL; - - elfcorehdr_addr = memparse(arg, &arg); - - return 0; -} -early_param("elfcorehdr", parse_elfcorehdr); - /** * copy_oldmem_page - copy one page from "oldmem" * @pfn: page frame number to be copied diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c index 64ea0b16539..91971103b62 100644 --- a/arch/sh/kernel/irq.c +++ b/arch/sh/kernel/irq.c @@ -183,7 +183,7 @@ asmlinkage void do_softirq(void) ); /* - * Shouldnt happen, we returned above if in_interrupt(): + * Shouldn't happen, we returned above if in_interrupt(): */ WARN_ON_ONCE(softirq_count()); } diff --git a/arch/sh/kernel/process.c b/arch/sh/kernel/process.c index dcb126dc76f..325f98b1736 100644 --- a/arch/sh/kernel/process.c +++ b/arch/sh/kernel/process.c @@ -32,16 +32,16 @@ void free_thread_xstate(struct task_struct *tsk) #if THREAD_SHIFT < PAGE_SHIFT static struct kmem_cache *thread_info_cache; -struct thread_info *alloc_thread_info(struct task_struct *tsk) +struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node) { struct thread_info *ti; - - ti = kmem_cache_alloc(thread_info_cache, GFP_KERNEL); - if (unlikely(ti == NULL)) - return NULL; #ifdef CONFIG_DEBUG_STACK_USAGE - memset(ti, 0, THREAD_SIZE); + gfp_t mask = GFP_KERNEL | __GFP_ZERO; +#else + gfp_t mask = GFP_KERNEL; #endif + + ti = kmem_cache_alloc_node(thread_info_cache, mask, node); return ti; } @@ -57,14 +57,16 @@ void thread_info_cache_init(void) THREAD_SIZE, SLAB_PANIC, NULL); } #else -struct thread_info *alloc_thread_info(struct task_struct *tsk) +struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node) { #ifdef CONFIG_DEBUG_STACK_USAGE gfp_t mask = GFP_KERNEL | __GFP_ZERO; #else gfp_t mask = GFP_KERNEL; #endif - return (struct thread_info *)__get_free_pages(mask, THREAD_SIZE_ORDER); + struct page *page = alloc_pages_node(node, mask, THREAD_SIZE_ORDER); + + return page ? page_address(page) : NULL; } void free_thread_info(struct thread_info *ti) diff --git a/arch/sh/kernel/ptrace_32.c b/arch/sh/kernel/ptrace_32.c index 90a15d29fee..3d7b209b217 100644 --- a/arch/sh/kernel/ptrace_32.c +++ b/arch/sh/kernel/ptrace_32.c @@ -101,6 +101,8 @@ static int set_single_step(struct task_struct *tsk, unsigned long addr) attr = bp->attr; attr.bp_addr = addr; + /* reenable breakpoint */ + attr.disabled = false; err = modify_user_hw_breakpoint(bp, &attr); if (unlikely(err)) return err; @@ -115,7 +117,11 @@ void user_enable_single_step(struct task_struct *child) set_tsk_thread_flag(child, TIF_SINGLESTEP); + if (ptrace_get_breakpoints(child) < 0) + return; + set_single_step(child, pc); + ptrace_put_breakpoints(child); } void user_disable_single_step(struct task_struct *child) @@ -392,6 +398,9 @@ long arch_ptrace(struct task_struct *child, long request, tmp = 0; } else { unsigned long index; + ret = init_fpu(child); + if (ret) + break; index = addr - offsetof(struct user, fpu); tmp = ((unsigned long *)child->thread.xstate) [index >> 2]; @@ -423,6 +432,9 @@ long arch_ptrace(struct task_struct *child, long request, else if (addr >= offsetof(struct user, fpu) && addr < offsetof(struct user, u_fpvalid)) { unsigned long index; + ret = init_fpu(child); + if (ret) + break; index = addr - offsetof(struct user, fpu); set_stopped_child_used_math(child); ((unsigned long *)child->thread.xstate) diff --git a/arch/sh/kernel/ptrace_64.c b/arch/sh/kernel/ptrace_64.c index 4436eacddb1..c8f97649f35 100644 --- a/arch/sh/kernel/ptrace_64.c +++ b/arch/sh/kernel/ptrace_64.c @@ -403,6 +403,9 @@ long arch_ptrace(struct task_struct *child, long request, else if ((addr >= offsetof(struct user, fpu)) && (addr < offsetof(struct user, u_fpvalid))) { unsigned long index; + ret = init_fpu(child); + if (ret) + break; index = addr - offsetof(struct user, fpu); tmp = get_fpu_long(child, index); } else if (addr == offsetof(struct user, u_fpvalid)) { @@ -442,6 +445,9 @@ long arch_ptrace(struct task_struct *child, long request, else if ((addr >= offsetof(struct user, fpu)) && (addr < offsetof(struct user, u_fpvalid))) { unsigned long index; + ret = init_fpu(child); + if (ret) + break; index = addr - offsetof(struct user, fpu); ret = put_fpu_long(child, index, data); } diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index 4f267160c51..58bff45d115 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -150,7 +150,7 @@ void __init check_for_initrd(void) } /* - * If we got this far inspite of the boot loader's best efforts + * If we got this far in spite of the boot loader's best efforts * to the contrary, assume we actually have a valid initrd and * fix up the root dev. */ diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S index 768fb33fdd3..030966a9305 100644 --- a/arch/sh/kernel/syscalls_32.S +++ b/arch/sh/kernel/syscalls_32.S @@ -379,3 +379,4 @@ ENTRY(sys_call_table) .long sys_name_to_handle_at .long sys_open_by_handle_at /* 360 */ .long sys_clock_adjtime + .long sys_syncfs diff --git a/arch/sh/kernel/syscalls_64.S b/arch/sh/kernel/syscalls_64.S index 44e7b00c806..ca0a6142ab6 100644 --- a/arch/sh/kernel/syscalls_64.S +++ b/arch/sh/kernel/syscalls_64.S @@ -399,3 +399,4 @@ sys_call_table: .long sys_name_to_handle_at /* 370 */ .long sys_open_by_handle_at .long sys_clock_adjtime + .long sys_syncfs diff --git a/arch/sh/kernel/vsyscall/vsyscall.c b/arch/sh/kernel/vsyscall/vsyscall.c index 242117cbad6..1d6d51a1ce7 100644 --- a/arch/sh/kernel/vsyscall/vsyscall.c +++ b/arch/sh/kernel/vsyscall/vsyscall.c @@ -94,17 +94,17 @@ const char *arch_vma_name(struct vm_area_struct *vma) return NULL; } -struct vm_area_struct *get_gate_vma(struct task_struct *task) +struct vm_area_struct *get_gate_vma(struct mm_struct *mm) { return NULL; } -int in_gate_area(struct task_struct *task, unsigned long address) +int in_gate_area(struct mm_struct *mm, unsigned long address) { return 0; } -int in_gate_area_no_task(unsigned long address) +int in_gate_area_no_mm(unsigned long address) { return 0; } diff --git a/arch/sh/lib64/copy_user_memcpy.S b/arch/sh/lib64/copy_user_memcpy.S index 2a62816d2dd..49aeabeba2c 100644 --- a/arch/sh/lib64/copy_user_memcpy.S +++ b/arch/sh/lib64/copy_user_memcpy.S @@ -27,7 +27,7 @@ ! 2.: When there are two or three bytes in the last word of an 11-or-more ! bytes memory chunk to b copied, the rest of the word can be read ! without side effects. -! This could be easily changed by increasing the minumum size of +! This could be easily changed by increasing the minimum size of ! a fast memcpy and the amount subtracted from r7 before L_2l_loop be 2, ! however, this would cost a few extra cyles on average. ! For SHmedia, the assumption is that any quadword can be read in its diff --git a/arch/sh/lib64/memcpy.S b/arch/sh/lib64/memcpy.S index dd300c372ce..5d682e0ee24 100644 --- a/arch/sh/lib64/memcpy.S +++ b/arch/sh/lib64/memcpy.S @@ -29,7 +29,7 @@ ! 2.: When there are two or three bytes in the last word of an 11-or-more ! bytes memory chunk to b copied, the rest of the word can be read ! without side effects. -! This could be easily changed by increasing the minumum size of +! This could be easily changed by increasing the minimum size of ! a fast memcpy and the amount subtracted from r7 before L_2l_loop be 2, ! however, this would cost a few extra cyles on average. ! For SHmedia, the assumption is that any quadword can be read in its diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c index b20b1b3eee4..fad52f1f681 100644 --- a/arch/sh/mm/pmb.c +++ b/arch/sh/mm/pmb.c @@ -3,7 +3,7 @@ * * Privileged Space Mapping Buffer (PMB) Support. * - * Copyright (C) 2005 - 2010 Paul Mundt + * Copyright (C) 2005 - 2011 Paul Mundt * Copyright (C) 2010 Matt Fleming * * This file is subject to the terms and conditions of the GNU General Public @@ -12,7 +12,7 @@ */ #include <linux/init.h> #include <linux/kernel.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/cpu.h> #include <linux/module.h> #include <linux/bitops.h> @@ -874,46 +874,31 @@ static int __init pmb_debugfs_init(void) subsys_initcall(pmb_debugfs_init); #ifdef CONFIG_PM -static int pmb_sysdev_suspend(struct sys_device *dev, pm_message_t state) +static void pmb_syscore_resume(void) { - static pm_message_t prev_state; + struct pmb_entry *pmbe; int i; - /* Restore the PMB after a resume from hibernation */ - if (state.event == PM_EVENT_ON && - prev_state.event == PM_EVENT_FREEZE) { - struct pmb_entry *pmbe; - - read_lock(&pmb_rwlock); + read_lock(&pmb_rwlock); - for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) { - if (test_bit(i, pmb_map)) { - pmbe = &pmb_entry_list[i]; - set_pmb_entry(pmbe); - } + for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) { + if (test_bit(i, pmb_map)) { + pmbe = &pmb_entry_list[i]; + set_pmb_entry(pmbe); } - - read_unlock(&pmb_rwlock); } - prev_state = state; - - return 0; -} - -static int pmb_sysdev_resume(struct sys_device *dev) -{ - return pmb_sysdev_suspend(dev, PMSG_ON); + read_unlock(&pmb_rwlock); } -static struct sysdev_driver pmb_sysdev_driver = { - .suspend = pmb_sysdev_suspend, - .resume = pmb_sysdev_resume, +static struct syscore_ops pmb_syscore_ops = { + .resume = pmb_syscore_resume, }; static int __init pmb_sysdev_init(void) { - return sysdev_driver_register(&cpu_sysdev_class, &pmb_sysdev_driver); + register_syscore_ops(&pmb_syscore_ops); + return 0; } subsys_initcall(pmb_sysdev_init); #endif diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index e48f471be54..e560d102215 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -51,7 +51,8 @@ config SPARC64 select HAVE_PERF_EVENTS select PERF_USE_VMALLOC select HAVE_GENERIC_HARDIRQS - select GENERIC_HARDIRQS_NO_DEPRECATED + select GENERIC_IRQ_SHOW + select IRQ_PREFLOW_FASTEOI config ARCH_DEFCONFIG string @@ -192,6 +193,10 @@ config GENERIC_FIND_NEXT_BIT bool default y +config GENERIC_FIND_BIT_LE + bool + default y + config GENERIC_HWEIGHT bool default y if !ULTRA_HAS_POPULATION_COUNT diff --git a/arch/sparc/include/asm/bitops_32.h b/arch/sparc/include/asm/bitops_32.h index 9cf4ae0cd7b..25a676653d4 100644 --- a/arch/sparc/include/asm/bitops_32.h +++ b/arch/sparc/include/asm/bitops_32.h @@ -103,9 +103,8 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) #include <asm-generic/bitops/hweight.h> #include <asm-generic/bitops/lock.h> #include <asm-generic/bitops/find.h> -#include <asm-generic/bitops/ext2-non-atomic.h> +#include <asm-generic/bitops/le.h> #include <asm-generic/bitops/ext2-atomic.h> -#include <asm-generic/bitops/minix.h> #endif /* __KERNEL__ */ diff --git a/arch/sparc/include/asm/bitops_64.h b/arch/sparc/include/asm/bitops_64.h index 766121a67a2..38e9aa1b2ce 100644 --- a/arch/sparc/include/asm/bitops_64.h +++ b/arch/sparc/include/asm/bitops_64.h @@ -89,15 +89,13 @@ static inline unsigned int __arch_hweight8(unsigned int w) #ifdef __KERNEL__ -#include <asm-generic/bitops/ext2-non-atomic.h> +#include <asm-generic/bitops/le.h> #define ext2_set_bit_atomic(lock,nr,addr) \ test_and_set_bit((nr) ^ 0x38,(unsigned long *)(addr)) #define ext2_clear_bit_atomic(lock,nr,addr) \ test_and_clear_bit((nr) ^ 0x38,(unsigned long *)(addr)) -#include <asm-generic/bitops/minix.h> - #endif /* __KERNEL__ */ #endif /* defined(_SPARC64_BITOPS_H) */ diff --git a/arch/sparc/include/asm/hypervisor.h b/arch/sparc/include/asm/hypervisor.h index bafe5a631b6..75686409be2 100644 --- a/arch/sparc/include/asm/hypervisor.h +++ b/arch/sparc/include/asm/hypervisor.h @@ -654,7 +654,7 @@ extern unsigned long sun4v_mmu_tsb_ctx0(unsigned long num_descriptions, * ARG3: mmu context * ARG4: flags (HV_MMU_{IMMU,DMMU}) * RET0: status - * ERRORS: EINVAL Invalid virutal address, context, or + * ERRORS: EINVAL Invalid virtual address, context, or * flags value * ENOTSUPPORTED ARG0 or ARG1 is non-zero * @@ -721,7 +721,7 @@ extern void sun4v_mmu_demap_all(void); * ARG2: TTE * ARG3: flags (HV_MMU_{IMMU,DMMU}) * RET0: status - * ERRORS: EINVAL Invalid virutal address or flags value + * ERRORS: EINVAL Invalid virtual address or flags value * EBADPGSZ Invalid page size value * ENORADDR Invalid real address in TTE * ETOOMANY Too many mappings (max of 8 reached) @@ -800,7 +800,7 @@ extern unsigned long sun4v_mmu_map_perm_addr(unsigned long vaddr, * ARG1: reserved, must be zero * ARG2: flags (HV_MMU_{IMMU,DMMU}) * RET0: status - * ERRORS: EINVAL Invalid virutal address or flags value + * ERRORS: EINVAL Invalid virtual address or flags value * ENOMAP Specified mapping was not found * * Demaps any permanent page mapping (established via @@ -1205,7 +1205,7 @@ struct hv_trap_trace_control { * structure contents. Attempts to do so will result in undefined * behavior for the guest. * - * Each trap trace buffer entry is layed out as follows: + * Each trap trace buffer entry is laid out as follows: */ #ifndef __ASSEMBLY__ struct hv_trap_trace_entry { @@ -1300,7 +1300,7 @@ struct hv_trap_trace_entry { * state in RET1. Future systems may define various flags for the * enable argument (ARG0), for the moment a guest should pass * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all - * tracing - which will ensure future compatability. + * tracing - which will ensure future compatibility. */ #define HV_FAST_TTRACE_ENABLE 0x92 @@ -1880,7 +1880,7 @@ extern unsigned long sun4v_vintr_set_target(unsigned long dev_handle, * pci_device, at pci_config_offset from the beginning of the device's * configuration space. If there was no error, RET1 is set to zero and * RET2 is set to the data read. Insignificant bits in RET2 are not - * guarenteed to have any specific value and therefore must be ignored. + * guaranteed to have any specific value and therefore must be ignored. * * The data returned in RET2 is size based byte swapped. * @@ -1941,9 +1941,9 @@ extern unsigned long sun4v_vintr_set_target(unsigned long dev_handle, * and return the actual data read in RET2. The data returned is size based * byte swapped. * - * Non-significant bits in RET2 are not guarenteed to have any specific value + * Non-significant bits in RET2 are not guaranteed to have any specific value * and therefore must be ignored. If RET1 is returned as non-zero, the data - * value is not guarenteed to have any specific value and should be ignored. + * value is not guaranteed to have any specific value and should be ignored. * * The caller must have permission to read from the given devhandle, real * address, which must be an IO address. The argument real address must be a @@ -2456,9 +2456,9 @@ extern unsigned long sun4v_vintr_set_target(unsigned long dev_handle, * * As receive queue configuration causes a reset of the queue's head and * tail pointers there is no way for a gues to determine how many entries - * have been received between a preceeding ldc_get_rx_state() API call + * have been received between a preceding ldc_get_rx_state() API call * and the completion of the configuration operation. It should be noted - * that datagram delivery is not guarenteed via domain channels anyway, + * that datagram delivery is not guaranteed via domain channels anyway, * and therefore any higher protocol should be resilient to datagram * loss if necessary. However, to overcome this specific race potential * it is recommended, for example, that a higher level protocol be employed diff --git a/arch/sparc/include/asm/irq_32.h b/arch/sparc/include/asm/irq_32.h index cbf4801deaa..eced3e3ebd3 100644 --- a/arch/sparc/include/asm/irq_32.h +++ b/arch/sparc/include/asm/irq_32.h @@ -13,4 +13,7 @@ #define irq_canonicalize(irq) (irq) extern void __init init_IRQ(void); + +#define NO_IRQ 0xffffffff + #endif diff --git a/arch/sparc/include/asm/irq_64.h b/arch/sparc/include/asm/irq_64.h index 4f09666f079..16dcae6d56e 100644 --- a/arch/sparc/include/asm/irq_64.h +++ b/arch/sparc/include/asm/irq_64.h @@ -97,4 +97,6 @@ extern void *softirq_stack[NR_CPUS]; #define __ARCH_HAS_DO_SOFTIRQ #define ARCH_HAS_NMI_WATCHDOG +#define NO_IRQ 0xffffffff + #endif diff --git a/arch/sparc/include/asm/ns87303.h b/arch/sparc/include/asm/ns87303.h index 686defe6aaa..af755483e17 100644 --- a/arch/sparc/include/asm/ns87303.h +++ b/arch/sparc/include/asm/ns87303.h @@ -37,7 +37,7 @@ /* Power and Test Register (PTR) bits */ #define PTR_LPTB_IRQ7 0x08 #define PTR_LEVEL_IRQ 0x80 /* When not ECP/EPP: Use level IRQ */ -#define PTR_LPT_REG_DIR 0x80 /* When ECP/EPP: LPT CTR controlls direction */ +#define PTR_LPT_REG_DIR 0x80 /* When ECP/EPP: LPT CTR controls direction */ /* of the parallel port */ /* Function Control Register (FCR) bits */ diff --git a/arch/sparc/include/asm/pcr.h b/arch/sparc/include/asm/pcr.h index 843e4faf6a5..288d7beba05 100644 --- a/arch/sparc/include/asm/pcr.h +++ b/arch/sparc/include/asm/pcr.h @@ -31,7 +31,7 @@ extern unsigned int picl_shift; /* In order to commonize as much of the implementation as * possible, we use PICH as our counter. Mostly this is - * to accomodate Niagara-1 which can only count insn cycles + * to accommodate Niagara-1 which can only count insn cycles * in PICH. */ static inline u64 picl_value(unsigned int nmi_hz) diff --git a/arch/sparc/include/asm/ptrace.h b/arch/sparc/include/asm/ptrace.h index 30b0b797dc0..c7ad3fe2b25 100644 --- a/arch/sparc/include/asm/ptrace.h +++ b/arch/sparc/include/asm/ptrace.h @@ -33,7 +33,7 @@ struct pt_regs { * things like "in a system call" etc. for an arbitray * process. * - * The PT_REGS_MAGIC is choosen such that it can be + * The PT_REGS_MAGIC is chosen such that it can be * loaded completely using just a sethi instruction. */ unsigned int magic; diff --git a/arch/sparc/include/asm/thread_info_32.h b/arch/sparc/include/asm/thread_info_32.h index 9dd0318d3dd..fa575323341 100644 --- a/arch/sparc/include/asm/thread_info_32.h +++ b/arch/sparc/include/asm/thread_info_32.h @@ -82,8 +82,8 @@ register struct thread_info *current_thread_info_reg asm("g6"); #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR -BTFIXUPDEF_CALL(struct thread_info *, alloc_thread_info, void) -#define alloc_thread_info(tsk) BTFIXUP_CALL(alloc_thread_info)() +BTFIXUPDEF_CALL(struct thread_info *, alloc_thread_info_node, int) +#define alloc_thread_info_node(tsk, node) BTFIXUP_CALL(alloc_thread_info_node)(node) BTFIXUPDEF_CALL(void, free_thread_info, struct thread_info *) #define free_thread_info(ti) BTFIXUP_CALL(free_thread_info)(ti) @@ -92,7 +92,7 @@ BTFIXUPDEF_CALL(void, free_thread_info, struct thread_info *) /* * Size of kernel stack for each process. - * Observe the order of get_free_pages() in alloc_thread_info(). + * Observe the order of get_free_pages() in alloc_thread_info_node(). * The sun4 has 8K stack too, because it's short on memory, and 16K is a waste. */ #define THREAD_SIZE 8192 diff --git a/arch/sparc/include/asm/thread_info_64.h b/arch/sparc/include/asm/thread_info_64.h index fb2ea7705a4..60d86be1a53 100644 --- a/arch/sparc/include/asm/thread_info_64.h +++ b/arch/sparc/include/asm/thread_info_64.h @@ -146,21 +146,21 @@ register struct thread_info *current_thread_info_reg asm("g6"); #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR #ifdef CONFIG_DEBUG_STACK_USAGE -#define alloc_thread_info(tsk) \ -({ \ - struct thread_info *ret; \ - \ - ret = (struct thread_info *) \ - __get_free_pages(GFP_KERNEL, __THREAD_INFO_ORDER); \ - if (ret) \ - memset(ret, 0, PAGE_SIZE<<__THREAD_INFO_ORDER); \ - ret; \ -}) +#define THREAD_FLAGS (GFP_KERNEL | __GFP_ZERO) #else -#define alloc_thread_info(tsk) \ - ((struct thread_info *)__get_free_pages(GFP_KERNEL, __THREAD_INFO_ORDER)) +#define THREAD_FLAGS (GFP_KERNEL) #endif +#define alloc_thread_info_node(tsk, node) \ +({ \ + struct page *page = alloc_pages_node(node, THREAD_FLAGS, \ + __THREAD_INFO_ORDER); \ + struct thread_info *ret; \ + \ + ret = page ? page_address(page) : NULL; \ + ret; \ +}) + #define free_thread_info(ti) \ free_pages((unsigned long)(ti),__THREAD_INFO_ORDER) diff --git a/arch/sparc/include/asm/types.h b/arch/sparc/include/asm/types.h index 09c79a9c851..91e5a034f98 100644 --- a/arch/sparc/include/asm/types.h +++ b/arch/sparc/include/asm/types.h @@ -18,28 +18,6 @@ typedef unsigned short umode_t; #endif /* __ASSEMBLY__ */ -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ - -/* Dma addresses come in generic and 64-bit flavours. */ - -typedef u32 dma_addr_t; - -#if defined(__arch64__) - -/*** SPARC 64 bit ***/ -typedef u64 dma64_addr_t; -#else -/*** SPARC 32 bit ***/ -typedef u32 dma64_addr_t; - -#endif /* defined(__arch64__) */ - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - #endif /* defined(__sparc__) */ #endif /* defined(_SPARC_TYPES_H) */ diff --git a/arch/sparc/include/asm/unistd.h b/arch/sparc/include/asm/unistd.h index 03eb5a8f6f9..9d897b6db98 100644 --- a/arch/sparc/include/asm/unistd.h +++ b/arch/sparc/include/asm/unistd.h @@ -400,8 +400,12 @@ #define __NR_fanotify_init 329 #define __NR_fanotify_mark 330 #define __NR_prlimit64 331 +#define __NR_name_to_handle_at 332 +#define __NR_open_by_handle_at 333 +#define __NR_clock_adjtime 334 +#define __NR_syncfs 335 -#define NR_syscalls 332 +#define NR_syscalls 336 #ifdef __32bit_syscall_numbers__ /* Sparc 32-bit only has the "setresuid32", "getresuid32" variants, diff --git a/arch/sparc/kernel/apc.c b/arch/sparc/kernel/apc.c index f679c57644d..1e34f29e58b 100644 --- a/arch/sparc/kernel/apc.c +++ b/arch/sparc/kernel/apc.c @@ -165,7 +165,7 @@ static int __devinit apc_probe(struct platform_device *op) return 0; } -static struct of_device_id __initdata apc_match[] = { +static struct of_device_id apc_match[] = { { .name = APC_OBPNAME, }, diff --git a/arch/sparc/kernel/auxio_64.c b/arch/sparc/kernel/auxio_64.c index 2abace076c7..773091ac71a 100644 --- a/arch/sparc/kernel/auxio_64.c +++ b/arch/sparc/kernel/auxio_64.c @@ -93,7 +93,7 @@ void auxio_set_lte(int on) } EXPORT_SYMBOL(auxio_set_lte); -static struct of_device_id __initdata auxio_match[] = { +static const struct of_device_id auxio_match[] = { { .name = "auxio", }, diff --git a/arch/sparc/kernel/central.c b/arch/sparc/kernel/central.c index 136d3718a74..7eef3f74196 100644 --- a/arch/sparc/kernel/central.c +++ b/arch/sparc/kernel/central.c @@ -140,7 +140,7 @@ out_free: goto out; } -static struct of_device_id __initdata clock_board_match[] = { +static const struct of_device_id clock_board_match[] = { { .name = "clock-board", }, @@ -245,7 +245,7 @@ out_free: goto out; } -static struct of_device_id __initdata fhc_match[] = { +static const struct of_device_id fhc_match[] = { { .name = "fhc", }, diff --git a/arch/sparc/kernel/ds.c b/arch/sparc/kernel/ds.c index 4a700f4b79c..3add4de8a1a 100644 --- a/arch/sparc/kernel/ds.c +++ b/arch/sparc/kernel/ds.c @@ -1218,7 +1218,7 @@ static int ds_remove(struct vio_dev *vdev) return 0; } -static struct vio_device_id __initdata ds_match[] = { +static const struct vio_device_id ds_match[] = { { .type = "domain-services-port", }, diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S index 1504df8ddf7..6da784a5612 100644 --- a/arch/sparc/kernel/entry.S +++ b/arch/sparc/kernel/entry.S @@ -801,7 +801,7 @@ vac_linesize_patch_32: subcc %l7, 32, %l7 .globl vac_hwflush_patch1_on, vac_hwflush_patch2_on /* - * Ugly, but we cant use hardware flushing on the sun4 and we'd require + * Ugly, but we can't use hardware flushing on the sun4 and we'd require * two instructions (Anton) */ vac_hwflush_patch1_on: addcc %l7, -PAGE_SIZE, %l7 @@ -851,7 +851,7 @@ sun4c_fault: sethi %hi(~((1 << SUN4C_REAL_PGDIR_SHIFT) - 1)), %l4 /* If the kernel references a bum kernel pointer, or a pte which - * points to a non existant page in ram, we will run this code + * points to a non existent page in ram, we will run this code * _forever_ and lock up the machine!!!!! So we must check for * this condition, the AC_SYNC_ERR bits are what we must examine. * Also a parity error would make this happen as well. So we just @@ -1283,7 +1283,7 @@ linux_syscall_trace: .globl ret_from_fork ret_from_fork: call schedule_tail - mov %g3, %o0 + ld [%g3 + TI_TASK], %o0 b ret_sys_call ld [%sp + STACKFRAME_SZ + PT_I0], %o0 diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S index f8f21050448..aa594c792d1 100644 --- a/arch/sparc/kernel/head_64.S +++ b/arch/sparc/kernel/head_64.S @@ -85,7 +85,7 @@ sparc_ramdisk_image64: sparc64_boot: mov %o4, %l7 - /* We need to remap the kernel. Use position independant + /* We need to remap the kernel. Use position independent * code to remap us to KERNBASE. * * SILO can invoke us with 32-bit address masking enabled, diff --git a/arch/sparc/kernel/init_task.c b/arch/sparc/kernel/init_task.c index 5fe3d65581f..35f141a9f50 100644 --- a/arch/sparc/kernel/init_task.c +++ b/arch/sparc/kernel/init_task.c @@ -15,7 +15,7 @@ EXPORT_SYMBOL(init_task); /* .text section in head.S is aligned at 8k boundary and this gets linked * right after that so that the init_thread_union is aligned properly as well. - * If this is not aligned on a 8k boundry, then you should change code + * If this is not aligned on a 8k boundary, then you should change code * in etrap.S which assumes it. */ union thread_union init_thread_union __init_task_data = diff --git a/arch/sparc/kernel/irq_64.c b/arch/sparc/kernel/irq_64.c index eb16e3b8a2d..b1d275ce343 100644 --- a/arch/sparc/kernel/irq_64.c +++ b/arch/sparc/kernel/irq_64.c @@ -162,47 +162,14 @@ void irq_free(unsigned int irq) /* * /proc/interrupts printing: */ - -int show_interrupts(struct seq_file *p, void *v) +int arch_show_interrupts(struct seq_file *p, int prec) { - int i = *(loff_t *) v, j; - struct irqaction * action; - unsigned long flags; + int j; - if (i == 0) { - seq_printf(p, " "); - for_each_online_cpu(j) - seq_printf(p, "CPU%d ",j); - seq_putc(p, '\n'); - } - - if (i < NR_IRQS) { - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); - action = irq_desc[i].action; - if (!action) - goto skip; - seq_printf(p, "%3d: ",i); -#ifndef CONFIG_SMP - seq_printf(p, "%10u ", kstat_irqs(i)); -#else - for_each_online_cpu(j) - seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); -#endif - seq_printf(p, " %9s", irq_desc[i].irq_data.chip->name); - seq_printf(p, " %s", action->name); - - for (action=action->next; action; action = action->next) - seq_printf(p, ", %s", action->name); - - seq_putc(p, '\n'); -skip: - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); - } else if (i == NR_IRQS) { - seq_printf(p, "NMI: "); - for_each_online_cpu(j) - seq_printf(p, "%10u ", cpu_data(j).__nmi_count); - seq_printf(p, " Non-maskable interrupts\n"); - } + seq_printf(p, "NMI: "); + for_each_online_cpu(j) + seq_printf(p, "%10u ", cpu_data(j).__nmi_count); + seq_printf(p, " Non-maskable interrupts\n"); return 0; } @@ -344,10 +311,6 @@ static void sun4u_irq_disable(struct irq_data *data) static void sun4u_irq_eoi(struct irq_data *data) { struct irq_handler_data *handler_data = data->handler_data; - struct irq_desc *desc = irq_desc + data->irq; - - if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) - return; if (likely(handler_data)) upa_writeq(ICLR_IDLE, handler_data->iclr); @@ -402,12 +365,8 @@ static void sun4v_irq_disable(struct irq_data *data) static void sun4v_irq_eoi(struct irq_data *data) { unsigned int ino = irq_table[data->irq].dev_ino; - struct irq_desc *desc = irq_desc + data->irq; int err; - if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) - return; - err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); if (err != HV_EOK) printk(KERN_ERR "sun4v_intr_setstate(%x): " @@ -481,13 +440,9 @@ static void sun4v_virq_disable(struct irq_data *data) static void sun4v_virq_eoi(struct irq_data *data) { - struct irq_desc *desc = irq_desc + data->irq; unsigned long dev_handle, dev_ino; int err; - if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) - return; - dev_handle = irq_table[data->irq].dev_handle; dev_ino = irq_table[data->irq].dev_ino; @@ -505,6 +460,7 @@ static struct irq_chip sun4u_irq = { .irq_disable = sun4u_irq_disable, .irq_eoi = sun4u_irq_eoi, .irq_set_affinity = sun4u_set_affinity, + .flags = IRQCHIP_EOI_IF_HANDLED, }; static struct irq_chip sun4v_irq = { @@ -513,6 +469,7 @@ static struct irq_chip sun4v_irq = { .irq_disable = sun4v_irq_disable, .irq_eoi = sun4v_irq_eoi, .irq_set_affinity = sun4v_set_affinity, + .flags = IRQCHIP_EOI_IF_HANDLED, }; static struct irq_chip sun4v_virq = { @@ -521,30 +478,28 @@ static struct irq_chip sun4v_virq = { .irq_disable = sun4v_virq_disable, .irq_eoi = sun4v_virq_eoi, .irq_set_affinity = sun4v_virt_set_affinity, + .flags = IRQCHIP_EOI_IF_HANDLED, }; -static void pre_flow_handler(unsigned int irq, struct irq_desc *desc) +static void pre_flow_handler(struct irq_data *d) { - struct irq_handler_data *handler_data = get_irq_data(irq); - unsigned int ino = irq_table[irq].dev_ino; + struct irq_handler_data *handler_data = irq_data_get_irq_handler_data(d); + unsigned int ino = irq_table[d->irq].dev_ino; handler_data->pre_handler(ino, handler_data->arg1, handler_data->arg2); - - handle_fasteoi_irq(irq, desc); } void irq_install_pre_handler(int irq, void (*func)(unsigned int, void *, void *), void *arg1, void *arg2) { - struct irq_handler_data *handler_data = get_irq_data(irq); - struct irq_desc *desc = irq_desc + irq; + struct irq_handler_data *handler_data = irq_get_handler_data(irq); handler_data->pre_handler = func; handler_data->arg1 = arg1; handler_data->arg2 = arg2; - desc->handle_irq = pre_flow_handler; + __irq_set_preflow_handler(irq, pre_flow_handler); } unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) @@ -562,13 +517,11 @@ unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) if (!irq) { irq = irq_alloc(0, ino); bucket_set_irq(__pa(bucket), irq); - set_irq_chip_and_handler_name(irq, - &sun4u_irq, - handle_fasteoi_irq, - "IVEC"); + irq_set_chip_and_handler_name(irq, &sun4u_irq, + handle_fasteoi_irq, "IVEC"); } - handler_data = get_irq_data(irq); + handler_data = irq_get_handler_data(irq); if (unlikely(handler_data)) goto out; @@ -577,7 +530,7 @@ unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); prom_halt(); } - set_irq_data(irq, handler_data); + irq_set_handler_data(irq, handler_data); handler_data->imap = imap; handler_data->iclr = iclr; @@ -600,12 +553,11 @@ static unsigned int sun4v_build_common(unsigned long sysino, if (!irq) { irq = irq_alloc(0, sysino); bucket_set_irq(__pa(bucket), irq); - set_irq_chip_and_handler_name(irq, chip, - handle_fasteoi_irq, + irq_set_chip_and_handler_name(irq, chip, handle_fasteoi_irq, "IVEC"); } - handler_data = get_irq_data(irq); + handler_data = irq_get_handler_data(irq); if (unlikely(handler_data)) goto out; @@ -614,7 +566,7 @@ static unsigned int sun4v_build_common(unsigned long sysino, prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); prom_halt(); } - set_irq_data(irq, handler_data); + irq_set_handler_data(irq, handler_data); /* Catch accidental accesses to these things. IMAP/ICLR handling * is done by hypervisor calls on sun4v platforms, not by direct @@ -639,7 +591,6 @@ unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) struct irq_handler_data *handler_data; unsigned long hv_err, cookie; struct ino_bucket *bucket; - struct irq_desc *desc; unsigned int irq; bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC); @@ -660,8 +611,7 @@ unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) irq = irq_alloc(devhandle, devino); bucket_set_irq(__pa(bucket), irq); - set_irq_chip_and_handler_name(irq, &sun4v_virq, - handle_fasteoi_irq, + irq_set_chip_and_handler_name(irq, &sun4v_virq, handle_fasteoi_irq, "IVEC"); handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); @@ -672,10 +622,8 @@ unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) * especially wrt. locking, we do not let request_irq() enable * the interrupt. */ - desc = irq_desc + irq; - desc->status |= IRQ_NOAUTOEN; - - set_irq_data(irq, handler_data); + irq_set_status_flags(irq, IRQ_NOAUTOEN); + irq_set_handler_data(irq, handler_data); /* Catch accidental accesses to these things. IMAP/ICLR handling * is done by hypervisor calls on sun4v platforms, not by direct @@ -734,7 +682,6 @@ void __irq_entry handler_irq(int pil, struct pt_regs *regs) orig_sp = set_hardirq_stack(); while (bucket_pa) { - struct irq_desc *desc; unsigned long next_pa; unsigned int irq; @@ -742,10 +689,7 @@ void __irq_entry handler_irq(int pil, struct pt_regs *regs) irq = bucket_get_irq(bucket_pa); bucket_clear_chain_pa(bucket_pa); - desc = irq_desc + irq; - - if (!(desc->status & IRQ_DISABLED)) - desc->handle_irq(irq, desc); + generic_handle_irq(irq); bucket_pa = next_pa; } @@ -788,19 +732,18 @@ void fixup_irqs(void) unsigned int irq; for (irq = 0; irq < NR_IRQS; irq++) { + struct irq_desc *desc = irq_to_desc(irq); + struct irq_data *data = irq_desc_get_irq_data(desc); unsigned long flags; - raw_spin_lock_irqsave(&irq_desc[irq].lock, flags); - if (irq_desc[irq].action && - !(irq_desc[irq].status & IRQ_PER_CPU)) { - struct irq_data *data = irq_get_irq_data(irq); - + raw_spin_lock_irqsave(&desc->lock, flags); + if (desc->action && !irqd_is_per_cpu(data)) { if (data->chip->irq_set_affinity) data->chip->irq_set_affinity(data, - data->affinity, - false); + data->affinity, + false); } - raw_spin_unlock_irqrestore(&irq_desc[irq].lock, flags); + raw_spin_unlock_irqrestore(&desc->lock, flags); } tick_ops->disable_irq(); @@ -1038,5 +981,5 @@ void __init init_IRQ(void) : "i" (PSTATE_IE) : "g1"); - irq_desc[0].action = &timer_irq_action; + irq_to_desc(0)->action = &timer_irq_action; } diff --git a/arch/sparc/kernel/mdesc.c b/arch/sparc/kernel/mdesc.c index 6addb914fcc..56db06432ce 100644 --- a/arch/sparc/kernel/mdesc.c +++ b/arch/sparc/kernel/mdesc.c @@ -107,7 +107,7 @@ static struct mdesc_handle * __init mdesc_memblock_alloc(unsigned int mdesc_size return hp; } -static void mdesc_memblock_free(struct mdesc_handle *hp) +static void __init mdesc_memblock_free(struct mdesc_handle *hp) { unsigned int alloc_size; unsigned long start; diff --git a/arch/sparc/kernel/of_device_64.c b/arch/sparc/kernel/of_device_64.c index 63cd4e5d47c..5c149689bb2 100644 --- a/arch/sparc/kernel/of_device_64.c +++ b/arch/sparc/kernel/of_device_64.c @@ -459,7 +459,7 @@ apply_interrupt_map(struct device_node *dp, struct device_node *pp, * * Handle this by deciding that, if we didn't get a * match in the parent's 'interrupt-map', and the - * parent is an IRQ translater, then use the parent as + * parent is an IRQ translator, then use the parent as * our IRQ controller. */ if (pp->irq_trans) diff --git a/arch/sparc/kernel/of_device_common.c b/arch/sparc/kernel/of_device_common.c index 49ddff56cb0..cb15bbf8a20 100644 --- a/arch/sparc/kernel/of_device_common.c +++ b/arch/sparc/kernel/of_device_common.c @@ -22,6 +22,33 @@ unsigned int irq_of_parse_and_map(struct device_node *node, int index) } EXPORT_SYMBOL(irq_of_parse_and_map); +int of_address_to_resource(struct device_node *node, int index, + struct resource *r) +{ + struct platform_device *op = of_find_device_by_node(node); + + if (!op || index >= op->num_resources) + return -EINVAL; + + memcpy(r, &op->archdata.resource[index], sizeof(*r)); + return 0; +} +EXPORT_SYMBOL_GPL(of_address_to_resource); + +void __iomem *of_iomap(struct device_node *node, int index) +{ + struct platform_device *op = of_find_device_by_node(node); + struct resource *r; + + if (!op || index >= op->num_resources) + return NULL; + + r = &op->archdata.resource[index]; + + return of_ioremap(r, 0, resource_size(r), (char *) r->name); +} +EXPORT_SYMBOL(of_iomap); + /* Take the archdata values for IOMMU, STC, and HOSTDATA found in * BUS and propagate to all child platform_device objects. */ diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c index 44f41e312f7..713dc91020a 100644 --- a/arch/sparc/kernel/pci.c +++ b/arch/sparc/kernel/pci.c @@ -1012,7 +1012,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) void arch_teardown_msi_irq(unsigned int irq) { - struct msi_desc *entry = get_irq_msi(irq); + struct msi_desc *entry = irq_get_msi_desc(irq); struct pci_dev *pdev = entry->dev; struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; diff --git a/arch/sparc/kernel/pci_fire.c b/arch/sparc/kernel/pci_fire.c index 3d70f8326ef..d29a32fcc5e 100644 --- a/arch/sparc/kernel/pci_fire.c +++ b/arch/sparc/kernel/pci_fire.c @@ -496,7 +496,7 @@ out_err: return err; } -static struct of_device_id __initdata fire_match[] = { +static const struct of_device_id fire_match[] = { { .name = "pci", .compatible = "pciex108e,80f0", diff --git a/arch/sparc/kernel/pci_msi.c b/arch/sparc/kernel/pci_msi.c index 550e937720e..30982e9ab62 100644 --- a/arch/sparc/kernel/pci_msi.c +++ b/arch/sparc/kernel/pci_msi.c @@ -30,13 +30,10 @@ static irqreturn_t sparc64_msiq_interrupt(int irq, void *cookie) err = ops->dequeue_msi(pbm, msiqid, &head, &msi); if (likely(err > 0)) { - struct irq_desc *desc; unsigned int irq; irq = pbm->msi_irq_table[msi - pbm->msi_first]; - desc = irq_desc + irq; - - desc->handle_irq(irq, desc); + generic_handle_irq(irq); } if (unlikely(err < 0)) @@ -136,8 +133,8 @@ static int sparc64_setup_msi_irq(unsigned int *irq_p, if (!*irq_p) goto out_err; - set_irq_chip_and_handler_name(*irq_p, &msi_irq, - handle_simple_irq, "MSI"); + irq_set_chip_and_handler_name(*irq_p, &msi_irq, handle_simple_irq, + "MSI"); err = alloc_msi(pbm); if (unlikely(err < 0)) @@ -163,7 +160,7 @@ static int sparc64_setup_msi_irq(unsigned int *irq_p, } msg.data = msi; - set_irq_msi(*irq_p, entry); + irq_set_msi_desc(*irq_p, entry); write_msi_msg(*irq_p, &msg); return 0; @@ -172,7 +169,7 @@ out_msi_free: free_msi(pbm, msi); out_irq_free: - set_irq_chip(*irq_p, NULL); + irq_set_chip(*irq_p, NULL); irq_free(*irq_p); *irq_p = 0; @@ -211,7 +208,7 @@ static void sparc64_teardown_msi_irq(unsigned int irq, free_msi(pbm, msi_num); - set_irq_chip(irq, NULL); + irq_set_chip(irq, NULL); irq_free(irq); } diff --git a/arch/sparc/kernel/pci_psycho.c b/arch/sparc/kernel/pci_psycho.c index 56ee745064d..86ae08d9b6e 100644 --- a/arch/sparc/kernel/pci_psycho.c +++ b/arch/sparc/kernel/pci_psycho.c @@ -592,7 +592,7 @@ out_err: return err; } -static struct of_device_id __initdata psycho_match[] = { +static const struct of_device_id psycho_match[] = { { .name = "pci", .compatible = "pci108e,8000", diff --git a/arch/sparc/kernel/pci_sabre.c b/arch/sparc/kernel/pci_sabre.c index 2857073342d..948068a083f 100644 --- a/arch/sparc/kernel/pci_sabre.c +++ b/arch/sparc/kernel/pci_sabre.c @@ -581,7 +581,7 @@ out_err: return err; } -static struct of_device_id __initdata sabre_match[] = { +static const struct of_device_id sabre_match[] = { { .name = "pci", .compatible = "pci108e,a001", diff --git a/arch/sparc/kernel/pci_schizo.c b/arch/sparc/kernel/pci_schizo.c index 1d41af73a92..fecfcb2063c 100644 --- a/arch/sparc/kernel/pci_schizo.c +++ b/arch/sparc/kernel/pci_schizo.c @@ -1470,7 +1470,7 @@ static int __devinit schizo_probe(struct platform_device *op) * and pci108e,8001. So list the chips in reverse chronological * order. */ -static struct of_device_id __initdata schizo_match[] = { +static const struct of_device_id schizo_match[] = { { .name = "pci", .compatible = "pci108e,a801", diff --git a/arch/sparc/kernel/pci_sun4v.c b/arch/sparc/kernel/pci_sun4v.c index 6cf53468178..b01a06e9ae4 100644 --- a/arch/sparc/kernel/pci_sun4v.c +++ b/arch/sparc/kernel/pci_sun4v.c @@ -998,7 +998,7 @@ out_err: return err; } -static struct of_device_id __initdata pci_sun4v_match[] = { +static const struct of_device_id pci_sun4v_match[] = { { .name = "pci", .compatible = "SUNW,sun4v-pci", diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index 760578687e7..ee8426ede7c 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c @@ -1027,7 +1027,7 @@ static int sparc_pmu_add(struct perf_event *event, int ef_flags) /* * If group events scheduling transaction was started, - * skip the schedulability test here, it will be peformed + * skip the schedulability test here, it will be performed * at commit time(->commit_txn) as a whole */ if (cpuc->group_flag & PERF_EVENT_TXN) diff --git a/arch/sparc/kernel/pmc.c b/arch/sparc/kernel/pmc.c index 93d7b4465f8..6a585d39358 100644 --- a/arch/sparc/kernel/pmc.c +++ b/arch/sparc/kernel/pmc.c @@ -69,7 +69,7 @@ static int __devinit pmc_probe(struct platform_device *op) return 0; } -static struct of_device_id __initdata pmc_match[] = { +static struct of_device_id pmc_match[] = { { .name = PMC_OBPNAME, }, diff --git a/arch/sparc/kernel/power.c b/arch/sparc/kernel/power.c index cd725fe238b..cb4c0f57c02 100644 --- a/arch/sparc/kernel/power.c +++ b/arch/sparc/kernel/power.c @@ -52,7 +52,7 @@ static int __devinit power_probe(struct platform_device *op) return 0; } -static struct of_device_id __initdata power_match[] = { +static const struct of_device_id power_match[] = { { .name = "power", }, diff --git a/arch/sparc/kernel/smp_32.c b/arch/sparc/kernel/smp_32.c index 91c10fb7085..850a1360c0d 100644 --- a/arch/sparc/kernel/smp_32.c +++ b/arch/sparc/kernel/smp_32.c @@ -53,6 +53,7 @@ cpumask_t smp_commenced_mask = CPU_MASK_NONE; void __cpuinit smp_store_cpu_info(int id) { int cpu_node; + int mid; cpu_data(id).udelay_val = loops_per_jiffy; @@ -60,10 +61,13 @@ void __cpuinit smp_store_cpu_info(int id) cpu_data(id).clock_tick = prom_getintdefault(cpu_node, "clock-frequency", 0); cpu_data(id).prom_node = cpu_node; - cpu_data(id).mid = cpu_get_hwmid(cpu_node); + mid = cpu_get_hwmid(cpu_node); - if (cpu_data(id).mid < 0) - panic("No MID found for CPU%d at node 0x%08d", id, cpu_node); + if (mid < 0) { + printk(KERN_NOTICE "No MID found for CPU%d at node 0x%08d", id, cpu_node); + mid = 0; + } + cpu_data(id).mid = mid; } void __init smp_cpus_done(unsigned int max_cpus) diff --git a/arch/sparc/kernel/systbls_32.S b/arch/sparc/kernel/systbls_32.S index ec396e1916b..47ac73c32e8 100644 --- a/arch/sparc/kernel/systbls_32.S +++ b/arch/sparc/kernel/systbls_32.S @@ -83,5 +83,5 @@ sys_call_table: /*315*/ .long sys_timerfd_settime, sys_timerfd_gettime, sys_signalfd4, sys_eventfd2, sys_epoll_create1 /*320*/ .long sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, sys_preadv /*325*/ .long sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_event_open, sys_recvmmsg, sys_fanotify_init -/*330*/ .long sys_fanotify_mark, sys_prlimit64 - +/*330*/ .long sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime +/*335*/ .long sys_syncfs diff --git a/arch/sparc/kernel/systbls_64.S b/arch/sparc/kernel/systbls_64.S index 8cfcaa54958..4f3170c1ef4 100644 --- a/arch/sparc/kernel/systbls_64.S +++ b/arch/sparc/kernel/systbls_64.S @@ -84,7 +84,8 @@ sys_call_table32: .word compat_sys_timerfd_settime, compat_sys_timerfd_gettime, compat_sys_signalfd4, sys_eventfd2, sys_epoll_create1 /*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, compat_sys_preadv .word compat_sys_pwritev, compat_sys_rt_tgsigqueueinfo, sys_perf_event_open, compat_sys_recvmmsg, sys_fanotify_init -/*330*/ .word sys32_fanotify_mark, sys_prlimit64 +/*330*/ .word sys32_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, compat_sys_open_by_handle_at, compat_sys_clock_adjtime + .word sys_syncfs #endif /* CONFIG_COMPAT */ @@ -160,4 +161,5 @@ sys_call_table: .word sys_timerfd_settime, sys_timerfd_gettime, sys_signalfd4, sys_eventfd2, sys_epoll_create1 /*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, sys_preadv .word sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_event_open, sys_recvmmsg, sys_fanotify_init -/*330*/ .word sys_fanotify_mark, sys_prlimit64 +/*330*/ .word sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime + .word sys_syncfs diff --git a/arch/sparc/kernel/time_32.c b/arch/sparc/kernel/time_32.c index 8237dd4dfeb..96046a4024c 100644 --- a/arch/sparc/kernel/time_32.c +++ b/arch/sparc/kernel/time_32.c @@ -145,6 +145,10 @@ static int __devinit clock_probe(struct platform_device *op) if (!model) return -ENODEV; + /* Only the primary RTC has an address property */ + if (!of_find_property(dp, "address", NULL)) + return -ENODEV; + m48t59_rtc.resource = &op->resource[0]; if (!strcmp(model, "mk48t02")) { /* Map the clock register io area read-only */ @@ -164,7 +168,7 @@ static int __devinit clock_probe(struct platform_device *op) return 0; } -static struct of_device_id __initdata clock_match[] = { +static struct of_device_id clock_match[] = { { .name = "eeprom", }, diff --git a/arch/sparc/kernel/time_64.c b/arch/sparc/kernel/time_64.c index 95ec25faba3..2b8d54b2d85 100644 --- a/arch/sparc/kernel/time_64.c +++ b/arch/sparc/kernel/time_64.c @@ -442,7 +442,7 @@ static int __devinit rtc_probe(struct platform_device *op) return platform_device_register(&rtc_cmos_device); } -static struct of_device_id __initdata rtc_match[] = { +static const struct of_device_id rtc_match[] = { { .name = "rtc", .compatible = "m5819", @@ -487,7 +487,7 @@ static int __devinit bq4802_probe(struct platform_device *op) return platform_device_register(&rtc_bq4802_device); } -static struct of_device_id __initdata bq4802_match[] = { +static const struct of_device_id bq4802_match[] = { { .name = "rtc", .compatible = "bq4802", @@ -552,7 +552,7 @@ static int __devinit mostek_probe(struct platform_device *op) return platform_device_register(&m48t59_rtc); } -static struct of_device_id __initdata mostek_match[] = { +static const struct of_device_id mostek_match[] = { { .name = "eeprom", }, diff --git a/arch/sparc/lib/checksum_32.S b/arch/sparc/lib/checksum_32.S index 3632cb34e91..0084c3361e1 100644 --- a/arch/sparc/lib/checksum_32.S +++ b/arch/sparc/lib/checksum_32.S @@ -289,10 +289,16 @@ cc_end_cruft: /* Also, handle the alignment code out of band. */ cc_dword_align: - cmp %g1, 6 - bl,a ccte + cmp %g1, 16 + bge 1f + srl %g1, 1, %o3 +2: cmp %o3, 0 + be,a ccte andcc %g1, 0xf, %o3 - andcc %o0, 0x1, %g0 + andcc %o3, %o0, %g0 ! Check %o0 only (%o1 has the same last 2 bits) + be,a 2b + srl %o3, 1, %o3 +1: andcc %o0, 0x1, %g0 bne ccslow andcc %o0, 0x2, %g0 be 1f diff --git a/arch/sparc/math-emu/Makefile b/arch/sparc/math-emu/Makefile index b9085ecbb27..825dbee94d8 100644 --- a/arch/sparc/math-emu/Makefile +++ b/arch/sparc/math-emu/Makefile @@ -2,7 +2,7 @@ # Makefile for the FPU instruction emulation. # -# supress all warnings - as math.c produces a lot! +# suppress all warnings - as math.c produces a lot! ccflags-y := -w obj-y := math_$(BITS).o diff --git a/arch/sparc/mm/init_32.c b/arch/sparc/mm/init_32.c index 6d0e02c4fe0..4c31e2b6e71 100644 --- a/arch/sparc/mm/init_32.c +++ b/arch/sparc/mm/init_32.c @@ -75,7 +75,7 @@ void __init kmap_init(void) kmap_prot = __pgprot(SRMMU_ET_PTE | SRMMU_PRIV | SRMMU_CACHE); } -void show_mem(void) +void show_mem(unsigned int filter) { printk("Mem-info:\n"); show_free_areas(); diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c index 92319aa8b66..fe09fd8be69 100644 --- a/arch/sparc/mm/srmmu.c +++ b/arch/sparc/mm/srmmu.c @@ -650,7 +650,7 @@ static void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len) * mappings on the kernel stack without any special code as we did * need on the sun4c. */ -static struct thread_info *srmmu_alloc_thread_info(void) +static struct thread_info *srmmu_alloc_thread_info_node(int node) { struct thread_info *ret; @@ -2271,7 +2271,7 @@ void __init ld_mmu_srmmu(void) BTFIXUPSET_CALL(mmu_info, srmmu_mmu_info, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(alloc_thread_info, srmmu_alloc_thread_info, BTFIXUPCALL_NORM); + BTFIXUPSET_CALL(alloc_thread_info_node, srmmu_alloc_thread_info_node, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(free_thread_info, srmmu_free_thread_info, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(pte_to_pgoff, srmmu_pte_to_pgoff, BTFIXUPCALL_NORM); diff --git a/arch/sparc/mm/sun4c.c b/arch/sparc/mm/sun4c.c index b5137cc2aba..a2350b5e68a 100644 --- a/arch/sparc/mm/sun4c.c +++ b/arch/sparc/mm/sun4c.c @@ -922,7 +922,7 @@ static inline void garbage_collect(int entry) free_locked_segment(BUCKET_ADDR(entry)); } -static struct thread_info *sun4c_alloc_thread_info(void) +static struct thread_info *sun4c_alloc_thread_info_node(int node) { unsigned long addr, pages; int entry; @@ -2155,7 +2155,7 @@ void __init ld_mmu_sun4c(void) BTFIXUPSET_CALL(__swp_offset, sun4c_swp_offset, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(__swp_entry, sun4c_swp_entry, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(alloc_thread_info, sun4c_alloc_thread_info, BTFIXUPCALL_NORM); + BTFIXUPSET_CALL(alloc_thread_info_node, sun4c_alloc_thread_info_node, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(free_thread_info, sun4c_free_thread_info, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(mmu_info, sun4c_mmu_info, BTFIXUPCALL_NORM); diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig index f3b78701c21..e32b0c23c4c 100644 --- a/arch/tile/Kconfig +++ b/arch/tile/Kconfig @@ -11,7 +11,7 @@ config TILE select HAVE_GENERIC_HARDIRQS select GENERIC_IRQ_PROBE select GENERIC_PENDING_IRQ if SMP - select GENERIC_HARDIRQS_NO_DEPRECATED + select GENERIC_IRQ_SHOW # FIXME: investigate whether we need/want these options. # select HAVE_IOREMAP_PROT @@ -51,7 +51,7 @@ config GENERIC_TIME config GENERIC_CLOCKEVENTS def_bool y -# FIXME: tilegx can implement a more efficent rwsem. +# FIXME: tilegx can implement a more efficient rwsem. config RWSEM_GENERIC_SPINLOCK def_bool y diff --git a/arch/tile/include/asm/bitops.h b/arch/tile/include/asm/bitops.h index 6d4f0ff2c68..132e6bbd07e 100644 --- a/arch/tile/include/asm/bitops.h +++ b/arch/tile/include/asm/bitops.h @@ -122,7 +122,6 @@ static inline unsigned long __arch_hweight64(__u64 w) #include <asm-generic/bitops/lock.h> #include <asm-generic/bitops/find.h> #include <asm-generic/bitops/sched.h> -#include <asm-generic/bitops/ext2-non-atomic.h> -#include <asm-generic/bitops/minix.h> +#include <asm-generic/bitops/le.h> #endif /* _ASM_TILE_BITOPS_H */ diff --git a/arch/tile/include/asm/thread_info.h b/arch/tile/include/asm/thread_info.h index 9e8e9c4dfa2..3405b52853b 100644 --- a/arch/tile/include/asm/thread_info.h +++ b/arch/tile/include/asm/thread_info.h @@ -84,7 +84,7 @@ register unsigned long stack_pointer __asm__("sp"); ((struct thread_info *)(stack_pointer & -THREAD_SIZE)) #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR -extern struct thread_info *alloc_thread_info(struct task_struct *task); +extern struct thread_info *alloc_thread_info_node(struct task_struct *task, int node); extern void free_thread_info(struct thread_info *info); /* Sit on a nap instruction until interrupted. */ diff --git a/arch/tile/include/hv/drv_xgbe_intf.h b/arch/tile/include/hv/drv_xgbe_intf.h index 146e47d5334..f13188ac281 100644 --- a/arch/tile/include/hv/drv_xgbe_intf.h +++ b/arch/tile/include/hv/drv_xgbe_intf.h @@ -319,7 +319,7 @@ typedef union * is an error code, or zero if no error. The val0 member is the * updated value of seqno; it has been incremented by 1 for each * packet sent. That increment may be less than nentries if an - * error occured, or if some of the entries in the vector contain + * error occurred, or if some of the entries in the vector contain * handles equal to NETIO_PKT_HANDLE_NONE. The val1 member is the * updated value of nentries; it has been decremented by 1 for each * vector entry processed. Again, that decrement may be less than diff --git a/arch/tile/include/hv/hypervisor.h b/arch/tile/include/hv/hypervisor.h index 1b8bf03d62a..ee41bca4c8c 100644 --- a/arch/tile/include/hv/hypervisor.h +++ b/arch/tile/include/hv/hypervisor.h @@ -1340,7 +1340,7 @@ typedef struct * this operation. If any permanent delivery errors were encountered, * the routine returns HV_ERECIP. In the event of permanent delivery * errors, it may be the case that delivery was not attempted to all - * recipients; if any messages were succesfully delivered, however, + * recipients; if any messages were successfully delivered, however, * recipients' state values will be updated appropriately. * * It is explicitly legal to specify a recipient structure whose state @@ -1359,7 +1359,7 @@ typedef struct * never call hv_receive_message, or could register a different state * buffer, losing the message. * - * Specifiying the same recipient more than once in the recipient list + * Specifying the same recipient more than once in the recipient list * is an error, which will not result in an error return but which may * or may not result in more than one message being delivered to the * recipient tile. diff --git a/arch/tile/kernel/irq.c b/arch/tile/kernel/irq.c index 0baa7580121..aa0134db2dd 100644 --- a/arch/tile/kernel/irq.c +++ b/arch/tile/kernel/irq.c @@ -241,14 +241,14 @@ void tile_irq_activate(unsigned int irq, int tile_irq_type) irq_flow_handler_t handle = handle_level_irq; if (tile_irq_type == TILE_IRQ_PERCPU) handle = handle_percpu_irq; - set_irq_chip_and_handler(irq, &tile_irq_chip, handle); + irq_set_chip_and_handler(irq, &tile_irq_chip, handle); /* * Flag interrupts that are hardware-cleared so that ack() * won't clear them. */ if (tile_irq_type == TILE_IRQ_HW_CLEAR) - set_irq_chip_data(irq, (void *)IS_HW_CLEARED); + irq_set_chip_data(irq, (void *)IS_HW_CLEARED); } EXPORT_SYMBOL(tile_irq_activate); @@ -262,47 +262,6 @@ void ack_bad_irq(unsigned int irq) * Generic, controller-independent functions: */ -int show_interrupts(struct seq_file *p, void *v) -{ - int i = *(loff_t *) v, j; - struct irqaction *action; - unsigned long flags; - - if (i == 0) { - seq_printf(p, " "); - for (j = 0; j < NR_CPUS; j++) - if (cpu_online(j)) - seq_printf(p, "CPU%-8d", j); - seq_putc(p, '\n'); - } - - if (i < NR_IRQS) { - struct irq_desc *desc = irq_to_desc(i); - - raw_spin_lock_irqsave(&desc->lock, flags); - action = desc->action; - if (!action) - goto skip; - seq_printf(p, "%3d: ", i); -#ifndef CONFIG_SMP - seq_printf(p, "%10u ", kstat_irqs(i)); -#else - for_each_online_cpu(j) - seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); -#endif - seq_printf(p, " %14s", get_irq_desc_chip(desc)->name); - seq_printf(p, " %s", action->name); - - for (action = action->next; action; action = action->next) - seq_printf(p, ", %s", action->name); - - seq_putc(p, '\n'); -skip: - raw_spin_unlock_irqrestore(&desc->lock, flags); - } - return 0; -} - #if CHIP_HAS_IPI() int create_irq(void) { diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c index a1ee25be9ad..ea38f0c9ec7 100644 --- a/arch/tile/kernel/pci.c +++ b/arch/tile/kernel/pci.c @@ -36,7 +36,7 @@ * Initialization flow and process * ------------------------------- * - * This files containes the routines to search for PCI buses, + * This files contains the routines to search for PCI buses, * enumerate the buses, and configure any attached devices. * * There are two entry points here: @@ -519,7 +519,7 @@ static int __devinit tile_cfg_read(struct pci_bus *bus, /* - * See tile_cfg_read() for relevent comments. + * See tile_cfg_read() for relevant comments. * Note that "val" is the value to write, not a pointer to that value. */ static int __devinit tile_cfg_write(struct pci_bus *bus, diff --git a/arch/tile/kernel/process.c b/arch/tile/kernel/process.c index b9cd962e1d3..d0065103eb7 100644 --- a/arch/tile/kernel/process.c +++ b/arch/tile/kernel/process.c @@ -109,7 +109,7 @@ void cpu_idle(void) } } -struct thread_info *alloc_thread_info(struct task_struct *task) +struct thread_info *alloc_thread_info_node(struct task_struct *task, int node) { struct page *page; gfp_t flags = GFP_KERNEL; @@ -118,7 +118,7 @@ struct thread_info *alloc_thread_info(struct task_struct *task) flags |= __GFP_ZERO; #endif - page = alloc_pages(flags, THREAD_SIZE_ORDER); + page = alloc_pages_node(node, flags, THREAD_SIZE_ORDER); if (!page) return NULL; diff --git a/arch/tile/lib/atomic_32.c b/arch/tile/lib/atomic_32.c index f02040d3614..46570211df5 100644 --- a/arch/tile/lib/atomic_32.c +++ b/arch/tile/lib/atomic_32.c @@ -202,32 +202,32 @@ static inline int *__futex_setup(int __user *v) return __atomic_hashed_lock((int __force *)v); } -struct __get_user futex_set(int __user *v, int i) +struct __get_user futex_set(u32 __user *v, int i) { return __atomic_xchg((int __force *)v, __futex_setup(v), i); } -struct __get_user futex_add(int __user *v, int n) +struct __get_user futex_add(u32 __user *v, int n) { return __atomic_xchg_add((int __force *)v, __futex_setup(v), n); } -struct __get_user futex_or(int __user *v, int n) +struct __get_user futex_or(u32 __user *v, int n) { return __atomic_or((int __force *)v, __futex_setup(v), n); } -struct __get_user futex_andn(int __user *v, int n) +struct __get_user futex_andn(u32 __user *v, int n) { return __atomic_andn((int __force *)v, __futex_setup(v), n); } -struct __get_user futex_xor(int __user *v, int n) +struct __get_user futex_xor(u32 __user *v, int n) { return __atomic_xor((int __force *)v, __futex_setup(v), n); } -struct __get_user futex_cmpxchg(int __user *v, int o, int n) +struct __get_user futex_cmpxchg(u32 __user *v, int o, int n) { return __atomic_cmpxchg((int __force *)v, __futex_setup(v), o, n); } diff --git a/arch/tile/mm/fault.c b/arch/tile/mm/fault.c index 758f597f488..51f8663bf07 100644 --- a/arch/tile/mm/fault.c +++ b/arch/tile/mm/fault.c @@ -290,7 +290,7 @@ static int handle_page_fault(struct pt_regs *regs, /* * Early on, we need to check for migrating PTE entries; * see homecache.c. If we find a migrating PTE, we wait until - * the backing page claims to be done migrating, then we procede. + * the backing page claims to be done migrating, then we proceed. * For kernel PTEs, we rewrite the PTE and return and retry. * Otherwise, we treat the fault like a normal "no PTE" fault, * rather than trying to patch up the existing PTE. diff --git a/arch/tile/mm/hugetlbpage.c b/arch/tile/mm/hugetlbpage.c index 201a582c413..42cfcba4e1e 100644 --- a/arch/tile/mm/hugetlbpage.c +++ b/arch/tile/mm/hugetlbpage.c @@ -219,7 +219,7 @@ try_again: if (mm->free_area_cache < len) goto fail; - /* either no address requested or cant fit in requested address hole */ + /* either no address requested or can't fit in requested address hole */ addr = (mm->free_area_cache - len) & huge_page_mask(h); do { /* diff --git a/arch/tile/mm/pgtable.c b/arch/tile/mm/pgtable.c index 1a2b36f8866..de7d8e21e01 100644 --- a/arch/tile/mm/pgtable.c +++ b/arch/tile/mm/pgtable.c @@ -41,7 +41,7 @@ * The normal show_free_areas() is too verbose on Tile, with dozens * of processors and often four NUMA zones each with high and lowmem. */ -void show_mem(void) +void show_mem(unsigned int filter) { struct zone *zone; diff --git a/arch/um/Kconfig.common b/arch/um/Kconfig.common index 1e78940218c..a9234838e8a 100644 --- a/arch/um/Kconfig.common +++ b/arch/um/Kconfig.common @@ -7,7 +7,7 @@ config UML bool default y select HAVE_GENERIC_HARDIRQS - select GENERIC_HARDIRQS_NO_DEPRECATED + select GENERIC_IRQ_SHOW config MMU bool diff --git a/arch/um/Kconfig.net b/arch/um/Kconfig.net index 9e9a4aaa703..3160b1a5adb 100644 --- a/arch/um/Kconfig.net +++ b/arch/um/Kconfig.net @@ -186,7 +186,7 @@ config UML_NET_SLIRP other transports, SLiRP works without the need of root level privleges, setuid binaries, or SLIP devices on the host. This also means not every type of connection is possible, but most - situations can be accomodated with carefully crafted slirp + situations can be accommodated with carefully crafted slirp commands that can be passed along as part of the network device's setup string. The effect of this transport on the UML is similar that of a host behind a firewall that masquerades all network diff --git a/arch/um/Kconfig.um b/arch/um/Kconfig.um index 90a438acbfa..b5e675e370c 100644 --- a/arch/um/Kconfig.um +++ b/arch/um/Kconfig.um @@ -47,7 +47,7 @@ config HOSTFS config HPPFS tristate "HoneyPot ProcFS (EXPERIMENTAL)" - depends on EXPERIMENTAL + depends on EXPERIMENTAL && PROC_FS help hppfs (HoneyPot ProcFS) is a filesystem which allows UML /proc entries to be overridden, removed, or fabricated from the host. diff --git a/arch/um/Kconfig.x86 b/arch/um/Kconfig.x86 index 02fb017fed4..a9da516a527 100644 --- a/arch/um/Kconfig.x86 +++ b/arch/um/Kconfig.x86 @@ -4,6 +4,10 @@ menu "UML-specific options" menu "Host processor type and features" +config CMPXCHG_LOCAL + bool + default n + source "arch/x86/Kconfig.cpu" endmenu diff --git a/arch/um/drivers/line.c b/arch/um/drivers/line.c index 050e4ddbbb6..35dd0b86401 100644 --- a/arch/um/drivers/line.c +++ b/arch/um/drivers/line.c @@ -255,8 +255,8 @@ static const struct { { KDSIGACCEPT, KERN_INFO, "KDSIGACCEPT" }, }; -int line_ioctl(struct tty_struct *tty, struct file * file, - unsigned int cmd, unsigned long arg) +int line_ioctl(struct tty_struct *tty, unsigned int cmd, + unsigned long arg) { int ret; int i; diff --git a/arch/um/include/asm/bug.h b/arch/um/include/asm/bug.h new file mode 100644 index 00000000000..9e33b864c35 --- /dev/null +++ b/arch/um/include/asm/bug.h @@ -0,0 +1,6 @@ +#ifndef __UM_BUG_H +#define __UM_BUG_H + +#include <asm-generic/bug.h> + +#endif diff --git a/arch/um/include/asm/processor-generic.h b/arch/um/include/asm/processor-generic.h index bed668824b5..d1d1b0d8a0c 100644 --- a/arch/um/include/asm/processor-generic.h +++ b/arch/um/include/asm/processor-generic.h @@ -66,7 +66,7 @@ struct thread_struct { .request = { 0 } \ } -extern struct task_struct *alloc_task_struct(void); +extern struct task_struct *alloc_task_struct_node(int node); static inline void release_thread(struct task_struct *task) { diff --git a/arch/um/include/asm/thread_info.h b/arch/um/include/asm/thread_info.h index e2cf786bda0..5bd1bad33fa 100644 --- a/arch/um/include/asm/thread_info.h +++ b/arch/um/include/asm/thread_info.h @@ -49,7 +49,10 @@ static inline struct thread_info *current_thread_info(void) { struct thread_info *ti; unsigned long mask = THREAD_SIZE - 1; - ti = (struct thread_info *) (((unsigned long) &ti) & ~mask); + void *p; + + asm volatile ("" : "=r" (p) : "0" (&ti)); + ti = (struct thread_info *) (((unsigned long)p) & ~mask); return ti; } diff --git a/arch/um/include/shared/line.h b/arch/um/include/shared/line.h index 311a0d3d93a..72f4f25af24 100644 --- a/arch/um/include/shared/line.h +++ b/arch/um/include/shared/line.h @@ -77,8 +77,8 @@ extern int line_chars_in_buffer(struct tty_struct *tty); extern void line_flush_buffer(struct tty_struct *tty); extern void line_flush_chars(struct tty_struct *tty); extern int line_write_room(struct tty_struct *tty); -extern int line_ioctl(struct tty_struct *tty, struct file * file, - unsigned int cmd, unsigned long arg); +extern int line_ioctl(struct tty_struct *tty, unsigned int cmd, + unsigned long arg); extern void line_throttle(struct tty_struct *tty); extern void line_unthrottle(struct tty_struct *tty); diff --git a/arch/um/kernel/irq.c b/arch/um/kernel/irq.c index 64cfea80cfe..9e485c77030 100644 --- a/arch/um/kernel/irq.c +++ b/arch/um/kernel/irq.c @@ -18,52 +18,6 @@ #include "os.h" /* - * Generic, controller-independent functions: - */ - -int show_interrupts(struct seq_file *p, void *v) -{ - int i = *(loff_t *) v, j; - struct irqaction * action; - unsigned long flags; - - if (i == 0) { - seq_printf(p, " "); - for_each_online_cpu(j) - seq_printf(p, "CPU%d ",j); - seq_putc(p, '\n'); - } - - if (i < NR_IRQS) { - struct irq_desc *desc = irq_to_desc(i); - - raw_spin_lock_irqsave(&desc->lock, flags); - action = desc->action; - if (!action) - goto skip; - seq_printf(p, "%3d: ",i); -#ifndef CONFIG_SMP - seq_printf(p, "%10u ", kstat_irqs(i)); -#else - for_each_online_cpu(j) - seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); -#endif - seq_printf(p, " %14s", get_irq_desc_chip(desc)->name); - seq_printf(p, " %s", action->name); - - for (action=action->next; action; action = action->next) - seq_printf(p, ", %s", action->name); - - seq_putc(p, '\n'); -skip: - raw_spin_unlock_irqrestore(&desc->lock, flags); - } else if (i == NR_IRQS) - seq_putc(p, '\n'); - - return 0; -} - -/* * This list is accessed under irq_lock, except in sigio_handler, * where it is safe from being modified. IRQ handlers won't change it - * if an IRQ source has vanished, it will be freed by free_irqs just @@ -390,11 +344,10 @@ void __init init_IRQ(void) { int i; - set_irq_chip_and_handler(TIMER_IRQ, &SIGVTALRM_irq_type, handle_edge_irq); + irq_set_chip_and_handler(TIMER_IRQ, &SIGVTALRM_irq_type, handle_edge_irq); - for (i = 1; i < NR_IRQS; i++) { - set_irq_chip_and_handler(i, &normal_irq_type, handle_edge_irq); - } + for (i = 1; i < NR_IRQS; i++) + irq_set_chip_and_handler(i, &normal_irq_type, handle_edge_irq); } /* diff --git a/arch/um/sys-i386/Makefile b/arch/um/sys-i386/Makefile index 804b28dd032..b1da91c1b20 100644 --- a/arch/um/sys-i386/Makefile +++ b/arch/um/sys-i386/Makefile @@ -4,7 +4,7 @@ obj-y = bug.o bugs.o checksum.o delay.o fault.o ksyms.o ldt.o ptrace.o \ ptrace_user.o setjmp.o signal.o stub.o stub_segv.o syscalls.o sysrq.o \ - sys_call_table.o tls.o + sys_call_table.o tls.o atomic64_cx8_32.o obj-$(CONFIG_BINFMT_ELF) += elfcore.o diff --git a/arch/um/sys-i386/asm/elf.h b/arch/um/sys-i386/asm/elf.h index a979a22a8d9..d964a4111ac 100644 --- a/arch/um/sys-i386/asm/elf.h +++ b/arch/um/sys-i386/asm/elf.h @@ -75,6 +75,8 @@ typedef struct user_i387_struct elf_fpregset_t; pr_reg[16] = PT_REGS_SS(regs); \ } while (0); +#define task_pt_regs(t) (&(t)->thread.regs) + struct task_struct; extern int elf_core_copy_fpregs(struct task_struct *t, elf_fpregset_t *fpu); diff --git a/arch/um/sys-i386/atomic64_cx8_32.S b/arch/um/sys-i386/atomic64_cx8_32.S new file mode 100644 index 00000000000..1e901d3d4a9 --- /dev/null +++ b/arch/um/sys-i386/atomic64_cx8_32.S @@ -0,0 +1,225 @@ +/* + * atomic64_t for 586+ + * + * Copied from arch/x86/lib/atomic64_cx8_32.S + * + * Copyright © 2010 Luca Barbieri + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#include <linux/linkage.h> +#include <asm/alternative-asm.h> +#include <asm/dwarf2.h> + +.macro SAVE reg + pushl_cfi %\reg + CFI_REL_OFFSET \reg, 0 +.endm + +.macro RESTORE reg + popl_cfi %\reg + CFI_RESTORE \reg +.endm + +.macro read64 reg + movl %ebx, %eax + movl %ecx, %edx +/* we need LOCK_PREFIX since otherwise cmpxchg8b always does the write */ + LOCK_PREFIX + cmpxchg8b (\reg) +.endm + +ENTRY(atomic64_read_cx8) + CFI_STARTPROC + + read64 %ecx + ret + CFI_ENDPROC +ENDPROC(atomic64_read_cx8) + +ENTRY(atomic64_set_cx8) + CFI_STARTPROC + +1: +/* we don't need LOCK_PREFIX since aligned 64-bit writes + * are atomic on 586 and newer */ + cmpxchg8b (%esi) + jne 1b + + ret + CFI_ENDPROC +ENDPROC(atomic64_set_cx8) + +ENTRY(atomic64_xchg_cx8) + CFI_STARTPROC + + movl %ebx, %eax + movl %ecx, %edx +1: + LOCK_PREFIX + cmpxchg8b (%esi) + jne 1b + + ret + CFI_ENDPROC +ENDPROC(atomic64_xchg_cx8) + +.macro addsub_return func ins insc +ENTRY(atomic64_\func\()_return_cx8) + CFI_STARTPROC + SAVE ebp + SAVE ebx + SAVE esi + SAVE edi + + movl %eax, %esi + movl %edx, %edi + movl %ecx, %ebp + + read64 %ebp +1: + movl %eax, %ebx + movl %edx, %ecx + \ins\()l %esi, %ebx + \insc\()l %edi, %ecx + LOCK_PREFIX + cmpxchg8b (%ebp) + jne 1b + +10: + movl %ebx, %eax + movl %ecx, %edx + RESTORE edi + RESTORE esi + RESTORE ebx + RESTORE ebp + ret + CFI_ENDPROC +ENDPROC(atomic64_\func\()_return_cx8) +.endm + +addsub_return add add adc +addsub_return sub sub sbb + +.macro incdec_return func ins insc +ENTRY(atomic64_\func\()_return_cx8) + CFI_STARTPROC + SAVE ebx + + read64 %esi +1: + movl %eax, %ebx + movl %edx, %ecx + \ins\()l $1, %ebx + \insc\()l $0, %ecx + LOCK_PREFIX + cmpxchg8b (%esi) + jne 1b + +10: + movl %ebx, %eax + movl %ecx, %edx + RESTORE ebx + ret + CFI_ENDPROC +ENDPROC(atomic64_\func\()_return_cx8) +.endm + +incdec_return inc add adc +incdec_return dec sub sbb + +ENTRY(atomic64_dec_if_positive_cx8) + CFI_STARTPROC + SAVE ebx + + read64 %esi +1: + movl %eax, %ebx + movl %edx, %ecx + subl $1, %ebx + sbb $0, %ecx + js 2f + LOCK_PREFIX + cmpxchg8b (%esi) + jne 1b + +2: + movl %ebx, %eax + movl %ecx, %edx + RESTORE ebx + ret + CFI_ENDPROC +ENDPROC(atomic64_dec_if_positive_cx8) + +ENTRY(atomic64_add_unless_cx8) + CFI_STARTPROC + SAVE ebp + SAVE ebx +/* these just push these two parameters on the stack */ + SAVE edi + SAVE esi + + movl %ecx, %ebp + movl %eax, %esi + movl %edx, %edi + + read64 %ebp +1: + cmpl %eax, 0(%esp) + je 4f +2: + movl %eax, %ebx + movl %edx, %ecx + addl %esi, %ebx + adcl %edi, %ecx + LOCK_PREFIX + cmpxchg8b (%ebp) + jne 1b + + movl $1, %eax +3: + addl $8, %esp + CFI_ADJUST_CFA_OFFSET -8 + RESTORE ebx + RESTORE ebp + ret +4: + cmpl %edx, 4(%esp) + jne 2b + xorl %eax, %eax + jmp 3b + CFI_ENDPROC +ENDPROC(atomic64_add_unless_cx8) + +ENTRY(atomic64_inc_not_zero_cx8) + CFI_STARTPROC + SAVE ebx + + read64 %esi +1: + testl %eax, %eax + je 4f +2: + movl %eax, %ebx + movl %edx, %ecx + addl $1, %ebx + adcl $0, %ecx + LOCK_PREFIX + cmpxchg8b (%esi) + jne 1b + + movl $1, %eax +3: + RESTORE ebx + ret +4: + testl %edx, %edx + jne 2b + jmp 3b + CFI_ENDPROC +ENDPROC(atomic64_inc_not_zero_cx8) diff --git a/arch/um/sys-ppc/Makefile b/arch/um/sys-ppc/Makefile index b8bc844fd2c..20d363bd700 100644 --- a/arch/um/sys-ppc/Makefile +++ b/arch/um/sys-ppc/Makefile @@ -6,7 +6,7 @@ OBJ = built-in.o OBJS = ptrace.o sigcontext.o checksum.o miscthings.o misc.o \ ptrace_user.o sysrq.o -EXTRA_AFLAGS := -DCONFIG_PPC32 -I. -I$(srctree)/arch/ppc/kernel +asflags-y := -DCONFIG_PPC32 -I. -I$(srctree)/arch/ppc/kernel all: $(OBJ) @@ -15,10 +15,10 @@ $(OBJ): $(OBJS) $(LD) $(LINKFLAGS) --start-group $^ --end-group -o $@ ptrace_user.o: ptrace_user.c - $(CC) -D__KERNEL__ $(USER_CFLAGS) $(EXTRA_CFLAGS) -c -o $@ $< + $(CC) -D__KERNEL__ $(USER_CFLAGS) $(ccflags-y) -c -o $@ $< sigcontext.o: sigcontext.c - $(CC) $(USER_CFLAGS) $(EXTRA_CFLAGS) -c -o $@ $< + $(CC) $(USER_CFLAGS) $(ccflags-y) -c -o $@ $< checksum.S: rm -f $@ @@ -53,13 +53,13 @@ ppc_defs.h: mk_defs.c ppc_defs.head \ checksum.o: checksum.S rm -f asm ln -s $(srctree)/include/asm-ppc asm - $(CC) $(EXTRA_AFLAGS) $(KBUILD_AFLAGS) -D__ASSEMBLY__ -D__UM_PPC__ -c $< -o $*.o + $(CC) $(asflags-y) $(KBUILD_AFLAGS) -D__ASSEMBLY__ -D__UM_PPC__ -c $< -o $*.o rm -f asm misc.o: misc.S ppc_defs.h rm -f asm ln -s $(srctree)/include/asm-ppc asm - $(CC) $(EXTRA_AFLAGS) $(KBUILD_AFLAGS) -D__ASSEMBLY__ -D__UM_PPC__ -c $< -o $*.o + $(CC) $(asflags-y) $(KBUILD_AFLAGS) -D__ASSEMBLY__ -D__UM_PPC__ -c $< -o $*.o rm -f asm clean-files := $(OBJS) ppc_defs.h checksum.S mk_defs.c diff --git a/arch/um/sys-x86_64/asm/elf.h b/arch/um/sys-x86_64/asm/elf.h index d760967f33a..d6d5af37625 100644 --- a/arch/um/sys-x86_64/asm/elf.h +++ b/arch/um/sys-x86_64/asm/elf.h @@ -95,6 +95,8 @@ typedef struct user_i387_struct elf_fpregset_t; (pr_reg)[25] = 0; \ (pr_reg)[26] = 0; +#define task_pt_regs(t) (&(t)->thread.regs) + struct task_struct; extern int elf_core_copy_fpregs(struct task_struct *t, elf_fpregset_t *fpu); diff --git a/arch/unicore32/Kconfig b/arch/unicore32/Kconfig index 4a36db45fb3..d3a303246c9 100644 --- a/arch/unicore32/Kconfig +++ b/arch/unicore32/Kconfig @@ -10,7 +10,7 @@ config UNICORE32 select HAVE_KERNEL_LZMA select GENERIC_FIND_FIRST_BIT select GENERIC_IRQ_PROBE - select GENERIC_HARDIRQS_NO_DEPRECATED + select GENERIC_IRQ_SHOW select ARCH_WANT_FRAME_POINTERS help UniCore-32 is 32-bit Instruction Set Architecture, diff --git a/arch/unicore32/Makefile b/arch/unicore32/Makefile index e08d6d370a8..76a8beec7d0 100644 --- a/arch/unicore32/Makefile +++ b/arch/unicore32/Makefile @@ -48,7 +48,7 @@ ASM_GENERIC_HEADERS += bitsperlong.h bug.h bugs.h ASM_GENERIC_HEADERS += cputime.h current.h ASM_GENERIC_HEADERS += device.h div64.h ASM_GENERIC_HEADERS += emergency-restart.h errno.h -ASM_GENERIC_HEADERS += fb.h fcntl.h ftrace.h +ASM_GENERIC_HEADERS += fb.h fcntl.h ftrace.h futex.h ASM_GENERIC_HEADERS += hardirq.h hw_irq.h ASM_GENERIC_HEADERS += ioctl.h ioctls.h ipcbuf.h irq_regs.h ASM_GENERIC_HEADERS += kdebug.h kmap_types.h diff --git a/arch/unicore32/include/asm/futex.h b/arch/unicore32/include/asm/futex.h deleted file mode 100644 index 07dea617055..00000000000 --- a/arch/unicore32/include/asm/futex.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * linux/arch/unicore32/include/asm/futex.h - * - * Code specific to PKUnity SoC and UniCore ISA - * - * Copyright (C) 2001-2010 GUAN Xue-tao - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __UNICORE_FUTEX_H__ -#define __UNICORE_FUTEX_H__ - -#ifdef __KERNEL__ - -#include <linux/futex.h> -#include <linux/preempt.h> -#include <linux/uaccess.h> -#include <linux/errno.h> - -#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ - __asm__ __volatile__( \ - "1: ldw.u %1, [%2]\n" \ - " " insn "\n" \ - "2: stw.u %0, [%2]\n" \ - " mov %0, #0\n" \ - "3:\n" \ - " .pushsection __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .long 1b, 4f, 2b, 4f\n" \ - " .popsection\n" \ - " .pushsection .fixup,\"ax\"\n" \ - "4: mov %0, %4\n" \ - " b 3b\n" \ - " .popsection" \ - : "=&r" (ret), "=&r" (oldval) \ - : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ - : "cc", "memory") - -static inline int -futex_atomic_op_inuser(int encoded_op, int __user *uaddr) -{ - int op = (encoded_op >> 28) & 7; - int cmp = (encoded_op >> 24) & 15; - int oparg = (encoded_op << 8) >> 20; - int cmparg = (encoded_op << 20) >> 20; - int oldval = 0, ret; - - if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) - oparg = 1 << oparg; - - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) - return -EFAULT; - - pagefault_disable(); /* implies preempt_disable() */ - - switch (op) { - case FUTEX_OP_SET: - __futex_atomic_op("mov %0, %3", ret, oldval, uaddr, oparg); - break; - case FUTEX_OP_ADD: - __futex_atomic_op("add %0, %1, %3", ret, oldval, uaddr, oparg); - break; - case FUTEX_OP_OR: - __futex_atomic_op("or %0, %1, %3", ret, oldval, uaddr, oparg); - break; - case FUTEX_OP_ANDN: - __futex_atomic_op("and %0, %1, %3", - ret, oldval, uaddr, ~oparg); - break; - case FUTEX_OP_XOR: - __futex_atomic_op("xor %0, %1, %3", ret, oldval, uaddr, oparg); - break; - default: - ret = -ENOSYS; - } - - pagefault_enable(); /* subsumes preempt_enable() */ - - if (!ret) { - switch (cmp) { - case FUTEX_OP_CMP_EQ: - ret = (oldval == cmparg); - break; - case FUTEX_OP_CMP_NE: - ret = (oldval != cmparg); - break; - case FUTEX_OP_CMP_LT: - ret = (oldval < cmparg); - break; - case FUTEX_OP_CMP_GE: - ret = (oldval >= cmparg); - break; - case FUTEX_OP_CMP_LE: - ret = (oldval <= cmparg); - break; - case FUTEX_OP_CMP_GT: - ret = (oldval > cmparg); - break; - default: - ret = -ENOSYS; - } - } - return ret; -} - -static inline int -futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) -{ - int val; - - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) - return -EFAULT; - - pagefault_disable(); /* implies preempt_disable() */ - - __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" - "1: ldw.u %0, [%3]\n" - " cmpxor.a %0, %1\n" - " bne 3f\n" - "2: stw.u %2, [%3]\n" - "3:\n" - " .pushsection __ex_table,\"a\"\n" - " .align 3\n" - " .long 1b, 4f, 2b, 4f\n" - " .popsection\n" - " .pushsection .fixup,\"ax\"\n" - "4: mov %0, %4\n" - " b 3b\n" - " .popsection" - : "=&r" (val) - : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT) - : "cc", "memory"); - - pagefault_enable(); /* subsumes preempt_enable() */ - - return val; -} - -#endif /* __KERNEL__ */ -#endif /* __UNICORE_FUTEX_H__ */ diff --git a/arch/unicore32/include/mach/PKUnity.h b/arch/unicore32/include/mach/PKUnity.h index a18bdc3810e..8040d575ddd 100644 --- a/arch/unicore32/include/mach/PKUnity.h +++ b/arch/unicore32/include/mach/PKUnity.h @@ -24,16 +24,6 @@ #define PKUNITY_MMIO_BASE 0x80000000 /* 0x80000000 - 0xFFFFFFFF 2GB */ /* - * PKUNITY Memory Map Addresses: 0x0D000000 - 0x0EFFFFFF (32MB) - * 0x0D000000 - 0x0DFFFFFF 16MB: for UVC - * 0x0E000000 - 0x0EFFFFFF 16MB: for UNIGFX - */ -#define PKUNITY_UVC_MMAP_BASE 0x0D000000 -#define PKUNITY_UVC_MMAP_SIZE 0x01000000 /* 16MB */ -#define PKUNITY_UNIGFX_MMAP_BASE 0x0E000000 -#define PKUNITY_UNIGFX_MMAP_SIZE 0x01000000 /* 16MB */ - -/* * PKUNITY System Bus Addresses (PCI): 0x80000000 - 0xBFFFFFFF (1GB) * 0x80000000 - 0x8000000B 12B PCI Configuration regs * 0x80010000 - 0x80010250 592B PCI Bridge Base diff --git a/arch/unicore32/include/mach/memory.h b/arch/unicore32/include/mach/memory.h index 0bf21c94471..4be72c21d49 100644 --- a/arch/unicore32/include/mach/memory.h +++ b/arch/unicore32/include/mach/memory.h @@ -50,7 +50,6 @@ void puv3_pci_adjust_zones(unsigned long *size, unsigned long *holes); /* kuser area */ #define KUSER_VECPAGE_BASE (KUSER_BASE + UL(0x3fff0000)) -#define KUSER_UNIGFX_BASE (PAGE_OFFSET + PKUNITY_UNIGFX_MMAP_BASE) /* kuser_vecpage (0xbfff0000) is ro, and vectors page (0xffff0000) is rw */ #define kuser_vecpage_to_vectors(x) ((x) - (KUSER_VECPAGE_BASE) \ + (VECTORS_BASE)) diff --git a/arch/unicore32/include/mach/regs-umal.h b/arch/unicore32/include/mach/regs-umal.h index 885bb62fee7..aa22df74e11 100644 --- a/arch/unicore32/include/mach/regs-umal.h +++ b/arch/unicore32/include/mach/regs-umal.h @@ -52,7 +52,7 @@ */ #define UMAL_MIISTATUS (PKUNITY_UMAL_BASE + 0x0030) /* - * MII Managment Indicator UMAL_MIIIDCT + * MII Management Indicator UMAL_MIIIDCT */ #define UMAL_MIIIDCT (PKUNITY_UMAL_BASE + 0x0034) /* @@ -91,7 +91,7 @@ #define UMAL_FIFORAM6 (PKUNITY_UMAL_BASE + 0x0078) #define UMAL_FIFORAM7 (PKUNITY_UMAL_BASE + 0x007c) -/* MAHBE MODUEL OF UMAL */ +/* MAHBE MODULE OF UMAL */ /* UMAL's MAHBE module interfaces to the host system through 32-bit AHB Master * and Slave ports.Registers within the M-AHBE provide Control and Status * information concerning these transfers. diff --git a/arch/unicore32/kernel/head.S b/arch/unicore32/kernel/head.S index 92255f3ab6a..8caf322e110 100644 --- a/arch/unicore32/kernel/head.S +++ b/arch/unicore32/kernel/head.S @@ -164,7 +164,7 @@ ENTRY(stext) ENDPROC(stext) /* - * Enable the MMU. This completely changes the stucture of the visible + * Enable the MMU. This completely changes the structure of the visible * memory space. You will not be able to trace execution through this. * * r0 = cp#0 control register diff --git a/arch/unicore32/kernel/irq.c b/arch/unicore32/kernel/irq.c index b23624cf306..2aa30a364bb 100644 --- a/arch/unicore32/kernel/irq.c +++ b/arch/unicore32/kernel/irq.c @@ -321,24 +321,24 @@ void __init init_IRQ(void) writel(1, INTC_ICCR); for (irq = 0; irq < IRQ_GPIOHIGH; irq++) { - set_irq_chip(irq, &puv3_low_gpio_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip(irq, &puv3_low_gpio_chip); + irq_set_handler(irq, handle_edge_irq); irq_modify_status(irq, IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN, 0); } for (irq = IRQ_GPIOHIGH + 1; irq < IRQ_GPIO0; irq++) { - set_irq_chip(irq, &puv3_normal_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip(irq, &puv3_normal_chip); + irq_set_handler(irq, handle_level_irq); irq_modify_status(irq, IRQ_NOREQUEST | IRQ_NOAUTOEN, IRQ_NOPROBE); } for (irq = IRQ_GPIO0; irq <= IRQ_GPIO27; irq++) { - set_irq_chip(irq, &puv3_high_gpio_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip(irq, &puv3_high_gpio_chip); + irq_set_handler(irq, handle_edge_irq); irq_modify_status(irq, IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN, 0); @@ -347,56 +347,14 @@ void __init init_IRQ(void) /* * Install handler for GPIO 0-27 edge detect interrupts */ - set_irq_chip(IRQ_GPIOHIGH, &puv3_normal_chip); - set_irq_chained_handler(IRQ_GPIOHIGH, puv3_gpio_handler); + irq_set_chip(IRQ_GPIOHIGH, &puv3_normal_chip); + irq_set_chained_handler(IRQ_GPIOHIGH, puv3_gpio_handler); #ifdef CONFIG_PUV3_GPIO puv3_init_gpio(); #endif } -int show_interrupts(struct seq_file *p, void *v) -{ - int i = *(loff_t *) v, cpu; - struct irq_desc *desc; - struct irqaction *action; - unsigned long flags; - - if (i == 0) { - char cpuname[12]; - - seq_printf(p, " "); - for_each_present_cpu(cpu) { - sprintf(cpuname, "CPU%d", cpu); - seq_printf(p, " %10s", cpuname); - } - seq_putc(p, '\n'); - } - - if (i < nr_irqs) { - desc = irq_to_desc(i); - raw_spin_lock_irqsave(&desc->lock, flags); - action = desc->action; - if (!action) - goto unlock; - - seq_printf(p, "%3d: ", i); - for_each_present_cpu(cpu) - seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); - seq_printf(p, " %10s", desc->irq_data.chip->name ? : "-"); - seq_printf(p, " %s", action->name); - for (action = action->next; action; action = action->next) - seq_printf(p, ", %s", action->name); - - seq_putc(p, '\n'); -unlock: - raw_spin_unlock_irqrestore(&desc->lock, flags); - } else if (i == nr_irqs) { - seq_printf(p, "Error in interrupt!\n"); - } - return 0; -} - /* * do_IRQ handles all hardware IRQ's. Decoded IRQs should not * come via this function. Instead, they should provide their diff --git a/arch/unicore32/kernel/puv3-core.c b/arch/unicore32/kernel/puv3-core.c index 8b1b6beb858..1a505a78776 100644 --- a/arch/unicore32/kernel/puv3-core.c +++ b/arch/unicore32/kernel/puv3-core.c @@ -99,11 +99,6 @@ static struct resource puv3_unigfx_resources[] = { .end = io_v2p(PKUNITY_UNIGFX_BASE) + 0xfff, .flags = IORESOURCE_MEM, }, - [1] = { - .start = PKUNITY_UNIGFX_MMAP_BASE, - .end = PKUNITY_UNIGFX_MMAP_BASE + PKUNITY_UNIGFX_MMAP_SIZE, - .flags = IORESOURCE_MEM, - }, }; static struct resource puv3_rtc_resources[] = { diff --git a/arch/unicore32/kernel/rtc.c b/arch/unicore32/kernel/rtc.c index c5f068295b5..8cad70b3302 100644 --- a/arch/unicore32/kernel/rtc.c +++ b/arch/unicore32/kernel/rtc.c @@ -88,11 +88,6 @@ static int puv3_rtc_setpie(struct device *dev, int enabled) return 0; } -static int puv3_rtc_setfreq(struct device *dev, int freq) -{ - return 0; -} - /* Time read/write */ static int puv3_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) @@ -214,8 +209,6 @@ static const struct rtc_class_ops puv3_rtcops = { .set_time = puv3_rtc_settime, .read_alarm = puv3_rtc_getalarm, .set_alarm = puv3_rtc_setalarm, - .irq_set_freq = puv3_rtc_setfreq, - .irq_set_state = puv3_rtc_setpie, .proc = puv3_rtc_proc, }; @@ -294,8 +287,6 @@ static int puv3_rtc_probe(struct platform_device *pdev) puv3_rtc_enable(pdev, 1); - puv3_rtc_setfreq(&pdev->dev, 1); - /* register RTC and exit */ rtc = rtc_device_register("pkunity", &pdev->dev, &puv3_rtcops, diff --git a/arch/unicore32/kernel/setup.c b/arch/unicore32/kernel/setup.c index 1e175a82844..471b6bca8da 100644 --- a/arch/unicore32/kernel/setup.c +++ b/arch/unicore32/kernel/setup.c @@ -64,12 +64,6 @@ static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE; */ static struct resource mem_res[] = { { - .name = "Video RAM", - .start = 0, - .end = 0, - .flags = IORESOURCE_MEM - }, - { .name = "Kernel text", .start = 0, .end = 0, @@ -83,9 +77,8 @@ static struct resource mem_res[] = { } }; -#define video_ram mem_res[0] -#define kernel_code mem_res[1] -#define kernel_data mem_res[2] +#define kernel_code mem_res[0] +#define kernel_data mem_res[1] /* * These functions re-use the assembly code in head.S, which @@ -224,10 +217,6 @@ request_standard_resources(struct meminfo *mi) kernel_data.end <= res->end) request_resource(res, &kernel_data); } - - video_ram.start = PKUNITY_UNIGFX_MMAP_BASE; - video_ram.end = PKUNITY_UNIGFX_MMAP_BASE + PKUNITY_UNIGFX_MMAP_SIZE; - request_resource(&iomem_resource, &video_ram); } static void (*init_machine)(void) __initdata; diff --git a/arch/unicore32/kernel/traps.c b/arch/unicore32/kernel/traps.c index 25abbb10172..254e36fa951 100644 --- a/arch/unicore32/kernel/traps.c +++ b/arch/unicore32/kernel/traps.c @@ -22,7 +22,6 @@ #include <linux/delay.h> #include <linux/hardirq.h> #include <linux/init.h> -#include <linux/uaccess.h> #include <linux/atomic.h> #include <linux/unistd.h> diff --git a/arch/unicore32/kernel/vmlinux.lds.S b/arch/unicore32/kernel/vmlinux.lds.S index 0b4eb89729e..9bf7f7af52c 100644 --- a/arch/unicore32/kernel/vmlinux.lds.S +++ b/arch/unicore32/kernel/vmlinux.lds.S @@ -14,6 +14,7 @@ #include <asm/thread_info.h> #include <asm/memory.h> #include <asm/page.h> +#include <asm/cache.h> OUTPUT_ARCH(unicore32) ENTRY(stext) @@ -29,7 +30,7 @@ SECTIONS HEAD_TEXT_SECTION INIT_TEXT_SECTION(PAGE_SIZE) INIT_DATA_SECTION(16) - PERCPU(PAGE_SIZE) + PERCPU(L1_CACHE_BYTES, PAGE_SIZE) __init_end = .; _stext = .; @@ -45,10 +46,10 @@ SECTIONS _sdata = .; RO_DATA_SECTION(PAGE_SIZE) - RW_DATA_SECTION(32, PAGE_SIZE, THREAD_SIZE) + RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE) _edata = .; - EXCEPTION_TABLE(32) + EXCEPTION_TABLE(L1_CACHE_BYTES) NOTES BSS_SECTION(0, 0, 0) diff --git a/arch/unicore32/mm/init.c b/arch/unicore32/mm/init.c index 3dbe3709b69..1fc02633f70 100644 --- a/arch/unicore32/mm/init.c +++ b/arch/unicore32/mm/init.c @@ -55,7 +55,7 @@ early_param("initrd", early_initrd); */ struct meminfo meminfo; -void show_mem(void) +void show_mem(unsigned int filter) { int free = 0, total = 0, reserved = 0; int shared = 0, cached = 0, slab = 0, i; diff --git a/arch/unicore32/mm/mmu.c b/arch/unicore32/mm/mmu.c index 7bf3d588631..db2d334941b 100644 --- a/arch/unicore32/mm/mmu.c +++ b/arch/unicore32/mm/mmu.c @@ -338,15 +338,6 @@ void __init uc32_mm_memblock_reserve(void) * and can only be in node 0. */ memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t)); - -#ifdef CONFIG_PUV3_UNIGFX - /* - * These should likewise go elsewhere. They pre-reserve the - * screen/video memory region at the 48M~64M of main system memory. - */ - memblock_reserve(PKUNITY_UNIGFX_MMAP_BASE, PKUNITY_UNIGFX_MMAP_SIZE); - memblock_reserve(PKUNITY_UVC_MMAP_BASE, PKUNITY_UVC_MMAP_SIZE); -#endif } /* @@ -371,17 +362,6 @@ static void __init devicemaps_init(void) pmd_clear(pmd_off_k(addr)); /* - * Create a mapping for UniGFX VRAM - */ -#ifdef CONFIG_PUV3_UNIGFX - map.pfn = __phys_to_pfn(PKUNITY_UNIGFX_MMAP_BASE); - map.virtual = KUSER_UNIGFX_BASE; - map.length = PKUNITY_UNIGFX_MMAP_SIZE; - map.type = MT_KUSER; - create_mapping(&map); -#endif - - /* * Create a mapping for the machine vectors at the high-vectors * location (0xffff0000). If we aren't using high-vectors, also * create a mapping at the low-vectors virtual address. diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index e1f65c46bc9..cc6c53a95bf 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -71,6 +71,7 @@ config X86 select GENERIC_IRQ_SHOW select IRQ_FORCED_THREADING select USE_GENERIC_SMP_HELPERS if SMP + select ARCH_NO_SYSDEV_OPS config INSTRUCTION_DECODER def_bool (KPROBES || PERF_EVENTS) @@ -123,7 +124,7 @@ config NEED_SG_DMA_LENGTH def_bool y config GENERIC_ISA_DMA - def_bool y + def_bool ISA_DMA_API config GENERIC_IOMAP def_bool y @@ -143,7 +144,7 @@ config GENERIC_GPIO bool config ARCH_MAY_HAVE_PC_FDC - def_bool y + def_bool ISA_DMA_API config RWSEM_GENERIC_SPINLOCK def_bool !X86_XADD @@ -2002,9 +2003,13 @@ source "drivers/pci/pcie/Kconfig" source "drivers/pci/Kconfig" -# x86_64 have no ISA slots, but do have ISA-style DMA. +# x86_64 have no ISA slots, but can have ISA-style DMA. config ISA_DMA_API - def_bool y + bool "ISA-style DMA support" if (X86_64 && EXPERT) + default y + help + Enables ISA-style DMA support for devices requiring such controllers. + If unsure, say Y. if X86_32 @@ -2092,6 +2097,16 @@ source "drivers/pcmcia/Kconfig" source "drivers/pci/hotplug/Kconfig" +config RAPIDIO + bool "RapidIO support" + depends on PCI + default n + help + If you say Y here, the kernel will include drivers and + infrastructure code to support RapidIO interconnect devices. + +source "drivers/rapidio/Kconfig" + endmenu diff --git a/arch/x86/boot/memory.c b/arch/x86/boot/memory.c index cae3feb1035..db75d07c364 100644 --- a/arch/x86/boot/memory.c +++ b/arch/x86/boot/memory.c @@ -91,7 +91,7 @@ static int detect_memory_e801(void) if (oreg.ax > 15*1024) { return -1; /* Bogus! */ } else if (oreg.ax == 15*1024) { - boot_params.alt_mem_k = (oreg.dx << 6) + oreg.ax; + boot_params.alt_mem_k = (oreg.bx << 6) + oreg.ax; } else { /* * This ignores memory above 16MB if we have a memory diff --git a/arch/x86/crypto/aesni-intel_asm.S b/arch/x86/crypto/aesni-intel_asm.S index adcf794b22e..be6d9e365a8 100644 --- a/arch/x86/crypto/aesni-intel_asm.S +++ b/arch/x86/crypto/aesni-intel_asm.S @@ -1612,6 +1612,7 @@ _zero_cipher_left_encrypt: movdqa SHUF_MASK(%rip), %xmm10 PSHUFB_XMM %xmm10, %xmm0 + ENCRYPT_SINGLE_BLOCK %xmm0, %xmm1 # Encrypt(K, Yn) sub $16, %r11 add %r13, %r11 @@ -1634,7 +1635,9 @@ _zero_cipher_left_encrypt: # GHASH computation for the last <16 byte block sub %r13, %r11 add $16, %r11 - PSHUFB_XMM %xmm10, %xmm1 + + movdqa SHUF_MASK(%rip), %xmm10 + PSHUFB_XMM %xmm10, %xmm0 # shuffle xmm0 back to output as ciphertext diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c index e0e6340c8da..2577613fb32 100644 --- a/arch/x86/crypto/aesni-intel_glue.c +++ b/arch/x86/crypto/aesni-intel_glue.c @@ -828,9 +828,15 @@ static int rfc4106_init(struct crypto_tfm *tfm) struct cryptd_aead *cryptd_tfm; struct aesni_rfc4106_gcm_ctx *ctx = (struct aesni_rfc4106_gcm_ctx *) PTR_ALIGN((u8 *)crypto_tfm_ctx(tfm), AESNI_ALIGN); + struct crypto_aead *cryptd_child; + struct aesni_rfc4106_gcm_ctx *child_ctx; cryptd_tfm = cryptd_alloc_aead("__driver-gcm-aes-aesni", 0, 0); if (IS_ERR(cryptd_tfm)) return PTR_ERR(cryptd_tfm); + + cryptd_child = cryptd_aead_child(cryptd_tfm); + child_ctx = aesni_rfc4106_gcm_ctx_get(cryptd_child); + memcpy(child_ctx, ctx, sizeof(*ctx)); ctx->cryptd_tfm = cryptd_tfm; tfm->crt_aead.reqsize = sizeof(struct aead_request) + crypto_aead_reqsize(&cryptd_tfm->base); @@ -923,6 +929,9 @@ static int rfc4106_set_key(struct crypto_aead *parent, const u8 *key, int ret = 0; struct crypto_tfm *tfm = crypto_aead_tfm(parent); struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(parent); + struct crypto_aead *cryptd_child = cryptd_aead_child(ctx->cryptd_tfm); + struct aesni_rfc4106_gcm_ctx *child_ctx = + aesni_rfc4106_gcm_ctx_get(cryptd_child); u8 *new_key_mem = NULL; if (key_len < 4) { @@ -966,6 +975,7 @@ static int rfc4106_set_key(struct crypto_aead *parent, const u8 *key, goto exit; } ret = rfc4106_set_hash_subkey(ctx->hash_subkey, key, key_len); + memcpy(child_ctx, ctx, sizeof(*ctx)); exit: kfree(new_key_mem); return ret; @@ -997,7 +1007,6 @@ static int rfc4106_encrypt(struct aead_request *req) int ret; struct crypto_aead *tfm = crypto_aead_reqtfm(req); struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(tfm); - struct crypto_aead *cryptd_child = cryptd_aead_child(ctx->cryptd_tfm); if (!irq_fpu_usable()) { struct aead_request *cryptd_req = @@ -1006,6 +1015,7 @@ static int rfc4106_encrypt(struct aead_request *req) aead_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base); return crypto_aead_encrypt(cryptd_req); } else { + struct crypto_aead *cryptd_child = cryptd_aead_child(ctx->cryptd_tfm); kernel_fpu_begin(); ret = cryptd_child->base.crt_aead.encrypt(req); kernel_fpu_end(); @@ -1018,7 +1028,6 @@ static int rfc4106_decrypt(struct aead_request *req) int ret; struct crypto_aead *tfm = crypto_aead_reqtfm(req); struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(tfm); - struct crypto_aead *cryptd_child = cryptd_aead_child(ctx->cryptd_tfm); if (!irq_fpu_usable()) { struct aead_request *cryptd_req = @@ -1027,6 +1036,7 @@ static int rfc4106_decrypt(struct aead_request *req) aead_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base); return crypto_aead_decrypt(cryptd_req); } else { + struct crypto_aead *cryptd_child = cryptd_aead_child(ctx->cryptd_tfm); kernel_fpu_begin(); ret = cryptd_child->base.crt_aead.decrypt(req); kernel_fpu_end(); diff --git a/arch/x86/ia32/ia32_aout.c b/arch/x86/ia32/ia32_aout.c index 2d93bdbc9ac..fd843877e84 100644 --- a/arch/x86/ia32/ia32_aout.c +++ b/arch/x86/ia32/ia32_aout.c @@ -298,6 +298,7 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs) /* OK, This is the point of no return */ set_personality(PER_LINUX); set_thread_flag(TIF_IA32); + current->mm->context.ia32_compat = 1; setup_new_exec(bprm); diff --git a/arch/x86/ia32/ia32entry.S b/arch/x86/ia32/ia32entry.S index 430312ba6e3..849a9d23c71 100644 --- a/arch/x86/ia32/ia32entry.S +++ b/arch/x86/ia32/ia32entry.S @@ -847,4 +847,5 @@ ia32_sys_call_table: .quad sys_name_to_handle_at .quad compat_sys_open_by_handle_at .quad compat_sys_clock_adjtime + .quad sys_syncfs ia32_syscall_end: diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index 448d73a371b..12e0e7dd869 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -114,9 +114,8 @@ static inline void acpi_disable_pci(void) acpi_noirq_set(); } -/* routines for saving/restoring kernel state */ -extern int acpi_save_state_mem(void); -extern void acpi_restore_state_mem(void); +/* Low-level suspend routine. */ +extern int acpi_suspend_lowlevel(void); extern const unsigned char acpi_wakeup_code[]; #define acpi_wakeup_address (__pa(TRAMPOLINE_SYM(acpi_wakeup_code))) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index a279d98ea95..2b7d573be54 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -2,7 +2,6 @@ #define _ASM_X86_APIC_H #include <linux/cpumask.h> -#include <linux/delay.h> #include <linux/pm.h> #include <asm/alternative.h> diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h index 903683b07e4..69d58131bc8 100644 --- a/arch/x86/include/asm/bitops.h +++ b/arch/x86/include/asm/bitops.h @@ -456,14 +456,12 @@ static inline int fls(int x) #ifdef __KERNEL__ -#include <asm-generic/bitops/ext2-non-atomic.h> +#include <asm-generic/bitops/le.h> #define ext2_set_bit_atomic(lock, nr, addr) \ test_and_set_bit((nr), (unsigned long *)(addr)) #define ext2_clear_bit_atomic(lock, nr, addr) \ test_and_clear_bit((nr), (unsigned long *)(addr)) -#include <asm-generic/bitops/minix.h> - #endif /* __KERNEL__ */ #endif /* _ASM_X86_BITOPS_H */ diff --git a/arch/x86/include/asm/dma.h b/arch/x86/include/asm/dma.h index ca1098a7e58..057099e5fab 100644 --- a/arch/x86/include/asm/dma.h +++ b/arch/x86/include/asm/dma.h @@ -10,7 +10,6 @@ #include <linux/spinlock.h> /* And spinlocks */ #include <asm/io.h> /* need byte IO */ -#include <linux/delay.h> #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER #define dma_outb outb_p @@ -151,6 +150,7 @@ #define DMA_AUTOINIT 0x10 +#ifdef CONFIG_ISA_DMA_API extern spinlock_t dma_spin_lock; static inline unsigned long claim_dma_lock(void) @@ -164,6 +164,7 @@ static inline void release_dma_lock(unsigned long flags) { spin_unlock_irqrestore(&dma_spin_lock, flags); } +#endif /* CONFIG_ISA_DMA_API */ /* enable/disable a specific DMA channel */ static inline void enable_dma(unsigned int dmanr) @@ -303,9 +304,11 @@ static inline int get_dma_residue(unsigned int dmanr) } -/* These are in kernel/dma.c: */ +/* These are in kernel/dma.c because x86 uses CONFIG_GENERIC_ISA_DMA */ +#ifdef CONFIG_ISA_DMA_API extern int request_dma(unsigned int dmanr, const char *device_id); extern void free_dma(unsigned int dmanr); +#endif /* From PCI */ diff --git a/arch/x86/include/asm/gart.h b/arch/x86/include/asm/gart.h index 43085bfc99c..156cd5d18d2 100644 --- a/arch/x86/include/asm/gart.h +++ b/arch/x86/include/asm/gart.h @@ -66,7 +66,7 @@ static inline void gart_set_size_and_enable(struct pci_dev *dev, u32 order) * Don't enable translation but enable GART IO and CPU accesses. * Also, set DISTLBWALKPRB since GART tables memory is UC. */ - ctl = DISTLBWALKPRB | order << 1; + ctl = order << 1; pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); } @@ -75,17 +75,17 @@ static inline void enable_gart_translation(struct pci_dev *dev, u64 addr) { u32 tmp, ctl; - /* address of the mappings table */ - addr >>= 12; - tmp = (u32) addr<<4; - tmp &= ~0xf; - pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp); - - /* Enable GART translation for this hammer. */ - pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); - ctl |= GARTEN; - ctl &= ~(DISGARTCPU | DISGARTIO); - pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); + /* address of the mappings table */ + addr >>= 12; + tmp = (u32) addr<<4; + tmp &= ~0xf; + pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp); + + /* Enable GART translation for this hammer. */ + pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); + ctl |= GARTEN | DISTLBWALKPRB; + ctl &= ~(DISGARTCPU | DISGARTIO); + pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); } static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size) diff --git a/arch/x86/include/asm/i387.h b/arch/x86/include/asm/i387.h index ef328901c80..c9e09ea0564 100644 --- a/arch/x86/include/asm/i387.h +++ b/arch/x86/include/asm/i387.h @@ -237,7 +237,7 @@ static inline void fpu_save_init(struct fpu *fpu) } else if (use_fxsr()) { fpu_fxsave(fpu); } else { - asm volatile("fsave %[fx]; fwait" + asm volatile("fnsave %[fx]; fwait" : [fx] "=m" (fpu->state->fsave)); return; } diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h index c4bd267dfc5..a97a240f67f 100644 --- a/arch/x86/include/asm/io_apic.h +++ b/arch/x86/include/asm/io_apic.h @@ -150,7 +150,7 @@ void setup_IO_APIC_irq_extra(u32 gsi); extern void ioapic_and_gsi_init(void); extern void ioapic_insert_resources(void); -int io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr); +int io_apic_setup_irq_pin_once(unsigned int irq, int node, struct io_apic_irq_attr *attr); extern struct IO_APIC_route_entry **alloc_ioapic_entries(void); extern void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries); diff --git a/arch/x86/include/asm/mmu.h b/arch/x86/include/asm/mmu.h index 80a1dee5bea..aeff3e89b22 100644 --- a/arch/x86/include/asm/mmu.h +++ b/arch/x86/include/asm/mmu.h @@ -13,6 +13,12 @@ typedef struct { int size; struct mutex lock; void *vdso; + +#ifdef CONFIG_X86_64 + /* True if mm supports a task running in 32 bit compatibility mode. */ + unsigned short ia32_compat; +#endif + } mm_context_t; #ifdef CONFIG_SMP diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index fd5a1f365c9..3cce71413d0 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -96,11 +96,15 @@ #define MSR_IA32_MC0_ADDR 0x00000402 #define MSR_IA32_MC0_MISC 0x00000403 +#define MSR_AMD64_MC0_MASK 0xc0010044 + #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) +#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) + /* These are consecutive and not in the normal 4er MCE bank block */ #define MSR_IA32_MC0_CTL2 0x00000280 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) diff --git a/arch/x86/include/asm/numa.h b/arch/x86/include/asm/numa.h index 3d4dab43c99..a50fc9f493b 100644 --- a/arch/x86/include/asm/numa.h +++ b/arch/x86/include/asm/numa.h @@ -51,7 +51,7 @@ static inline void numa_remove_cpu(int cpu) { } #endif /* CONFIG_NUMA */ #ifdef CONFIG_DEBUG_PER_CPU_MAPS -struct cpumask __cpuinit *debug_cpumask_set_cpu(int cpu, int enable); +void debug_cpumask_set_cpu(int cpu, int node, bool enable); #endif #endif /* _ASM_X86_NUMA_H */ diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h index a09e1f052d8..d475b4398d8 100644 --- a/arch/x86/include/asm/percpu.h +++ b/arch/x86/include/asm/percpu.h @@ -45,7 +45,7 @@ #include <linux/stringify.h> #ifdef CONFIG_SMP -#define __percpu_arg(x) "%%"__stringify(__percpu_seg)":%P" #x +#define __percpu_prefix "%%"__stringify(__percpu_seg)":" #define __my_cpu_offset percpu_read(this_cpu_off) /* @@ -62,9 +62,11 @@ (typeof(*(ptr)) __kernel __force *)tcp_ptr__; \ }) #else -#define __percpu_arg(x) "%P" #x +#define __percpu_prefix "" #endif +#define __percpu_arg(x) __percpu_prefix "%P" #x + /* * Initialized pointers to per-cpu variables needed for the boot * processor need to use these macros to get the proper address @@ -516,11 +518,11 @@ do { \ typeof(o2) __n2 = n2; \ typeof(o2) __dummy; \ alternative_io("call this_cpu_cmpxchg16b_emu\n\t" P6_NOP4, \ - "cmpxchg16b %%gs:(%%rsi)\n\tsetz %0\n\t", \ + "cmpxchg16b " __percpu_prefix "(%%rsi)\n\tsetz %0\n\t", \ X86_FEATURE_CX16, \ ASM_OUTPUT2("=a"(__ret), "=d"(__dummy)), \ "S" (&pcp1), "b"(__n1), "c"(__n2), \ - "a"(__o1), "d"(__o2)); \ + "a"(__o1), "d"(__o2) : "memory"); \ __ret; \ }) diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h index 7db7723d1f3..d56187c6b83 100644 --- a/arch/x86/include/asm/pgtable_types.h +++ b/arch/x86/include/asm/pgtable_types.h @@ -299,6 +299,7 @@ int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, /* Install a pte for a particular vaddr in kernel space. */ void set_pte_vaddr(unsigned long vaddr, pte_t pte); +extern void native_pagetable_reserve(u64 start, u64 end); #ifdef CONFIG_X86_32 extern void native_pagetable_setup_start(pgd_t *base); extern void native_pagetable_setup_done(pgd_t *base); diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h index f0b6e5dbc5a..1f2e61e2898 100644 --- a/arch/x86/include/asm/thread_info.h +++ b/arch/x86/include/asm/thread_info.h @@ -161,8 +161,14 @@ struct thread_info { #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR -#define alloc_thread_info(tsk) \ - ((struct thread_info *)__get_free_pages(THREAD_FLAGS, THREAD_ORDER)) +#define alloc_thread_info_node(tsk, node) \ +({ \ + struct page *page = alloc_pages_node(node, THREAD_FLAGS, \ + THREAD_ORDER); \ + struct thread_info *ret = page ? page_address(page) : NULL; \ + \ + ret; \ +}) #ifdef CONFIG_X86_32 diff --git a/arch/x86/include/asm/types.h b/arch/x86/include/asm/types.h index df1da20f453..8e8c23fef08 100644 --- a/arch/x86/include/asm/types.h +++ b/arch/x86/include/asm/types.h @@ -1,22 +1,6 @@ #ifndef _ASM_X86_TYPES_H #define _ASM_X86_TYPES_H -#define dma_addr_t dma_addr_t - #include <asm-generic/types.h> -#ifdef __KERNEL__ -#ifndef __ASSEMBLY__ - -typedef u64 dma64_addr_t; -#if defined(CONFIG_X86_64) || defined(CONFIG_HIGHMEM64G) -/* DMA addresses come in 32-bit and 64-bit flavours. */ -typedef u64 dma_addr_t; -#else -typedef u32 dma_addr_t; -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL__ */ - #endif /* _ASM_X86_TYPES_H */ diff --git a/arch/x86/include/asm/unistd_32.h b/arch/x86/include/asm/unistd_32.h index ffaf183c619..a755ef5e597 100644 --- a/arch/x86/include/asm/unistd_32.h +++ b/arch/x86/include/asm/unistd_32.h @@ -349,10 +349,11 @@ #define __NR_name_to_handle_at 341 #define __NR_open_by_handle_at 342 #define __NR_clock_adjtime 343 +#define __NR_syncfs 344 #ifdef __KERNEL__ -#define NR_syscalls 344 +#define NR_syscalls 345 #define __ARCH_WANT_IPC_PARSE_VERSION #define __ARCH_WANT_OLD_READDIR diff --git a/arch/x86/include/asm/unistd_64.h b/arch/x86/include/asm/unistd_64.h index 5466bea670e..160fa76bd57 100644 --- a/arch/x86/include/asm/unistd_64.h +++ b/arch/x86/include/asm/unistd_64.h @@ -675,6 +675,8 @@ __SYSCALL(__NR_name_to_handle_at, sys_name_to_handle_at) __SYSCALL(__NR_open_by_handle_at, sys_open_by_handle_at) #define __NR_clock_adjtime 305 __SYSCALL(__NR_clock_adjtime, sys_clock_adjtime) +#define __NR_syncfs 306 +__SYSCALL(__NR_syncfs, sys_syncfs) #ifndef __NO_STUBS #define __ARCH_WANT_OLD_READDIR diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h index 643ebf2e2ad..d3d859035af 100644 --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -68,6 +68,17 @@ struct x86_init_oem { }; /** + * struct x86_init_mapping - platform specific initial kernel pagetable setup + * @pagetable_reserve: reserve a range of addresses for kernel pagetable usage + * + * For more details on the purpose of this hook, look in + * init_memory_mapping and the commit that added it. + */ +struct x86_init_mapping { + void (*pagetable_reserve)(u64 start, u64 end); +}; + +/** * struct x86_init_paging - platform specific paging functions * @pagetable_setup_start: platform specific pre paging_init() call * @pagetable_setup_done: platform specific post paging_init() call @@ -123,6 +134,7 @@ struct x86_init_ops { struct x86_init_mpparse mpparse; struct x86_init_irqs irqs; struct x86_init_oem oem; + struct x86_init_mapping mapping; struct x86_init_paging paging; struct x86_init_timers timers; struct x86_init_iommu iommu; diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index 743642f1a36..7338ef2218b 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -41,7 +41,7 @@ obj-$(CONFIG_X86_32) += sys_i386_32.o i386_ksyms_32.o obj-$(CONFIG_X86_64) += sys_x86_64.o x8664_ksyms_64.o obj-$(CONFIG_X86_64) += syscall_64.o vsyscall_64.o obj-y += bootflag.o e820.o -obj-y += pci-dma.o quirks.o i8237.o topology.o kdebugfs.o +obj-y += pci-dma.o quirks.o topology.o kdebugfs.o obj-y += alternative.o i8253.o pci-nommu.o hw_breakpoint.o obj-y += tsc.o io_delay.o rtc.o obj-y += pci-iommu_table.o @@ -55,6 +55,7 @@ obj-$(CONFIG_X86_32) += tls.o obj-$(CONFIG_IA32_EMULATION) += tls.o obj-y += step.o obj-$(CONFIG_INTEL_TXT) += tboot.o +obj-$(CONFIG_ISA_DMA_API) += i8237.o obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-y += cpu/ obj-y += acpi/ diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c index 4572c58e66d..ff93bc1b09c 100644 --- a/arch/x86/kernel/acpi/sleep.c +++ b/arch/x86/kernel/acpi/sleep.c @@ -25,12 +25,12 @@ static char temp_stack[4096]; #endif /** - * acpi_save_state_mem - save kernel state + * acpi_suspend_lowlevel - save kernel state * * Create an identity mapped page table and copy the wakeup routine to * low memory. */ -int acpi_save_state_mem(void) +int acpi_suspend_lowlevel(void) { struct wakeup_header *header; /* address in low memory of the wakeup routine. */ @@ -96,16 +96,10 @@ int acpi_save_state_mem(void) saved_magic = 0x123456789abcdef0L; #endif /* CONFIG_64BIT */ + do_suspend_lowlevel(); return 0; } -/* - * acpi_restore_state - undo effects of acpi_save_state_mem - */ -void acpi_restore_state_mem(void) -{ -} - static int __init acpi_sleep_setup(char *str) { while ((str != NULL) && (*str != '\0')) { diff --git a/arch/x86/kernel/acpi/sleep.h b/arch/x86/kernel/acpi/sleep.h index 86ba1c87165..416d4be13fe 100644 --- a/arch/x86/kernel/acpi/sleep.h +++ b/arch/x86/kernel/acpi/sleep.h @@ -11,3 +11,5 @@ extern int wakeup_pmode_return; extern unsigned long acpi_copy_wakeup_routine(unsigned long); extern void wakeup_long64(void); + +extern void do_suspend_lowlevel(void); diff --git a/arch/x86/kernel/amd_iommu_init.c b/arch/x86/kernel/amd_iommu_init.c index 6e11c813415..246d727b65b 100644 --- a/arch/x86/kernel/amd_iommu_init.c +++ b/arch/x86/kernel/amd_iommu_init.c @@ -21,7 +21,7 @@ #include <linux/acpi.h> #include <linux/list.h> #include <linux/slab.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/interrupt.h> #include <linux/msi.h> #include <asm/pci-direct.h> @@ -1260,7 +1260,7 @@ static void disable_iommus(void) * disable suspend until real resume implemented */ -static int amd_iommu_resume(struct sys_device *dev) +static void amd_iommu_resume(void) { struct amd_iommu *iommu; @@ -1276,11 +1276,9 @@ static int amd_iommu_resume(struct sys_device *dev) */ amd_iommu_flush_all_devices(); amd_iommu_flush_all_domains(); - - return 0; } -static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state) +static int amd_iommu_suspend(void) { /* disable IOMMUs to go out of the way for BIOS */ disable_iommus(); @@ -1288,17 +1286,11 @@ static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state) return 0; } -static struct sysdev_class amd_iommu_sysdev_class = { - .name = "amd_iommu", +static struct syscore_ops amd_iommu_syscore_ops = { .suspend = amd_iommu_suspend, .resume = amd_iommu_resume, }; -static struct sys_device device_amd_iommu = { - .id = 0, - .cls = &amd_iommu_sysdev_class, -}; - /* * This is the core init function for AMD IOMMU hardware in the system. * This function is called from the generic x86 DMA layer initialization @@ -1415,14 +1407,6 @@ static int __init amd_iommu_init(void) goto free; } - ret = sysdev_class_register(&amd_iommu_sysdev_class); - if (ret) - goto free; - - ret = sysdev_register(&device_amd_iommu); - if (ret) - goto free; - ret = amd_iommu_init_devices(); if (ret) goto free; @@ -1441,6 +1425,8 @@ static int __init amd_iommu_init(void) amd_iommu_init_notifier(); + register_syscore_ops(&amd_iommu_syscore_ops); + if (iommu_pass_through) goto out; diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 6801959a8b2..4c39baa8fac 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -21,7 +21,7 @@ const struct pci_device_id amd_nb_misc_ids[] = { EXPORT_SYMBOL(amd_nb_misc_ids); static struct pci_device_id amd_nb_link_ids[] = { - { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_LINK) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) }, {} }; diff --git a/arch/x86/kernel/apb_timer.c b/arch/x86/kernel/apb_timer.c index 1293c709ee8..cd1ffed4ee2 100644 --- a/arch/x86/kernel/apb_timer.c +++ b/arch/x86/kernel/apb_timer.c @@ -316,7 +316,7 @@ static void apbt_setup_irq(struct apbt_dev *adev) irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT); irq_set_affinity(adev->irq, cpumask_of(adev->cpu)); /* APB timer irqs are set up as mp_irqs, timer is edge type */ - __set_irq_handler(adev->irq, handle_edge_irq, 0, "edge"); + __irq_set_handler(adev->irq, handle_edge_irq, 0, "edge"); if (system_state == SYSTEM_BOOTING) { if (request_irq(adev->irq, apbt_interrupt_handler, diff --git a/arch/x86/kernel/aperture_64.c b/arch/x86/kernel/aperture_64.c index 86d1ad4962a..73fb469908c 100644 --- a/arch/x86/kernel/aperture_64.c +++ b/arch/x86/kernel/aperture_64.c @@ -499,7 +499,7 @@ out: * Don't enable translation yet but enable GART IO and CPU * accesses and set DISTLBWALKPRB since GART table memory is UC. */ - u32 ctl = DISTLBWALKPRB | aper_order << 1; + u32 ctl = aper_order << 1; bus = amd_nb_bus_dev_ranges[i].bus; dev_base = amd_nb_bus_dev_ranges[i].dev_base; diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 966673f4414..fabf01eff77 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -24,7 +24,7 @@ #include <linux/ftrace.h> #include <linux/ioport.h> #include <linux/module.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/delay.h> #include <linux/timex.h> #include <linux/dmar.h> @@ -2046,7 +2046,7 @@ static struct { unsigned int apic_thmr; } apic_pm_state; -static int lapic_suspend(struct sys_device *dev, pm_message_t state) +static int lapic_suspend(void) { unsigned long flags; int maxlvt; @@ -2084,23 +2084,21 @@ static int lapic_suspend(struct sys_device *dev, pm_message_t state) return 0; } -static int lapic_resume(struct sys_device *dev) +static void lapic_resume(void) { unsigned int l, h; unsigned long flags; - int maxlvt; - int ret = 0; + int maxlvt, ret; struct IO_APIC_route_entry **ioapic_entries = NULL; if (!apic_pm_state.active) - return 0; + return; local_irq_save(flags); if (intr_remapping_enabled) { ioapic_entries = alloc_ioapic_entries(); if (!ioapic_entries) { WARN(1, "Alloc ioapic_entries in lapic resume failed."); - ret = -ENOMEM; goto restore; } @@ -2162,8 +2160,6 @@ static int lapic_resume(struct sys_device *dev) } restore: local_irq_restore(flags); - - return ret; } /* @@ -2171,17 +2167,11 @@ restore: * are needed on every CPU up until machine_halt/restart/poweroff. */ -static struct sysdev_class lapic_sysclass = { - .name = "lapic", +static struct syscore_ops lapic_syscore_ops = { .resume = lapic_resume, .suspend = lapic_suspend, }; -static struct sys_device device_lapic = { - .id = 0, - .cls = &lapic_sysclass, -}; - static void __cpuinit apic_pm_activate(void) { apic_pm_state.active = 1; @@ -2189,16 +2179,11 @@ static void __cpuinit apic_pm_activate(void) static int __init init_lapic_sysfs(void) { - int error; - - if (!cpu_has_apic) - return 0; /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ + if (cpu_has_apic) + register_syscore_ops(&lapic_syscore_ops); - error = sysdev_class_register(&lapic_sysclass); - if (!error) - error = sysdev_register(&device_lapic); - return error; + return 0; } /* local apic needs to resume before other devices access its registers. */ diff --git a/arch/x86/kernel/apic/hw_nmi.c b/arch/x86/kernel/apic/hw_nmi.c index c4e557a1ebb..5260fe91bcb 100644 --- a/arch/x86/kernel/apic/hw_nmi.c +++ b/arch/x86/kernel/apic/hw_nmi.c @@ -16,6 +16,7 @@ #include <linux/kprobes.h> #include <linux/nmi.h> #include <linux/module.h> +#include <linux/delay.h> #ifdef CONFIG_HARDLOCKUP_DETECTOR u64 hw_nmi_get_sample_period(void) diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 180ca240e03..45fd33d1fd3 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -30,7 +30,7 @@ #include <linux/compiler.h> #include <linux/acpi.h> #include <linux/module.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/msi.h> #include <linux/htirq.h> #include <linux/freezer.h> @@ -128,8 +128,8 @@ static int __init parse_noapic(char *str) } early_param("noapic", parse_noapic); -static int io_apic_setup_irq_pin_once(unsigned int irq, int node, - struct io_apic_irq_attr *attr); +static int io_apic_setup_irq_pin(unsigned int irq, int node, + struct io_apic_irq_attr *attr); /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ void mp_save_irq(struct mpc_intsrc *m) @@ -2918,89 +2918,84 @@ static int __init io_apic_bug_finalize(void) late_initcall(io_apic_bug_finalize); -struct sysfs_ioapic_data { - struct sys_device dev; - struct IO_APIC_route_entry entry[0]; -}; -static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; +static struct IO_APIC_route_entry *ioapic_saved_data[MAX_IO_APICS]; -static int ioapic_suspend(struct sys_device *dev, pm_message_t state) +static void suspend_ioapic(int ioapic_id) { - struct IO_APIC_route_entry *entry; - struct sysfs_ioapic_data *data; + struct IO_APIC_route_entry *saved_data = ioapic_saved_data[ioapic_id]; int i; - data = container_of(dev, struct sysfs_ioapic_data, dev); - entry = data->entry; - for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) - *entry = ioapic_read_entry(dev->id, i); + if (!saved_data) + return; + + for (i = 0; i < nr_ioapic_registers[ioapic_id]; i++) + saved_data[i] = ioapic_read_entry(ioapic_id, i); +} + +static int ioapic_suspend(void) +{ + int ioapic_id; + + for (ioapic_id = 0; ioapic_id < nr_ioapics; ioapic_id++) + suspend_ioapic(ioapic_id); return 0; } -static int ioapic_resume(struct sys_device *dev) +static void resume_ioapic(int ioapic_id) { - struct IO_APIC_route_entry *entry; - struct sysfs_ioapic_data *data; + struct IO_APIC_route_entry *saved_data = ioapic_saved_data[ioapic_id]; unsigned long flags; union IO_APIC_reg_00 reg_00; int i; - data = container_of(dev, struct sysfs_ioapic_data, dev); - entry = data->entry; + if (!saved_data) + return; raw_spin_lock_irqsave(&ioapic_lock, flags); - reg_00.raw = io_apic_read(dev->id, 0); - if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { - reg_00.bits.ID = mp_ioapics[dev->id].apicid; - io_apic_write(dev->id, 0, reg_00.raw); + reg_00.raw = io_apic_read(ioapic_id, 0); + if (reg_00.bits.ID != mp_ioapics[ioapic_id].apicid) { + reg_00.bits.ID = mp_ioapics[ioapic_id].apicid; + io_apic_write(ioapic_id, 0, reg_00.raw); } raw_spin_unlock_irqrestore(&ioapic_lock, flags); - for (i = 0; i < nr_ioapic_registers[dev->id]; i++) - ioapic_write_entry(dev->id, i, entry[i]); + for (i = 0; i < nr_ioapic_registers[ioapic_id]; i++) + ioapic_write_entry(ioapic_id, i, saved_data[i]); +} - return 0; +static void ioapic_resume(void) +{ + int ioapic_id; + + for (ioapic_id = nr_ioapics - 1; ioapic_id >= 0; ioapic_id--) + resume_ioapic(ioapic_id); } -static struct sysdev_class ioapic_sysdev_class = { - .name = "ioapic", +static struct syscore_ops ioapic_syscore_ops = { .suspend = ioapic_suspend, .resume = ioapic_resume, }; -static int __init ioapic_init_sysfs(void) +static int __init ioapic_init_ops(void) { - struct sys_device * dev; - int i, size, error; + int i; - error = sysdev_class_register(&ioapic_sysdev_class); - if (error) - return error; + for (i = 0; i < nr_ioapics; i++) { + unsigned int size; - for (i = 0; i < nr_ioapics; i++ ) { - size = sizeof(struct sys_device) + nr_ioapic_registers[i] + size = nr_ioapic_registers[i] * sizeof(struct IO_APIC_route_entry); - mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); - if (!mp_ioapic_data[i]) { - printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); - continue; - } - dev = &mp_ioapic_data[i]->dev; - dev->id = i; - dev->cls = &ioapic_sysdev_class; - error = sysdev_register(dev); - if (error) { - kfree(mp_ioapic_data[i]); - mp_ioapic_data[i] = NULL; - printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); - continue; - } + ioapic_saved_data[i] = kzalloc(size, GFP_KERNEL); + if (!ioapic_saved_data[i]) + pr_err("IOAPIC %d: suspend/resume impossible!\n", i); } + register_syscore_ops(&ioapic_syscore_ops); + return 0; } -device_initcall(ioapic_init_sysfs); +device_initcall(ioapic_init_ops); /* * Dynamic irq allocate and deallocation @@ -3575,7 +3570,7 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) } #endif /* CONFIG_HT_IRQ */ -int +static int io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr) { struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node); @@ -3590,8 +3585,8 @@ io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr) return ret; } -static int io_apic_setup_irq_pin_once(unsigned int irq, int node, - struct io_apic_irq_attr *attr) +int io_apic_setup_irq_pin_once(unsigned int irq, int node, + struct io_apic_irq_attr *attr) { unsigned int id = attr->ioapic, pin = attr->ioapic_pin; int ret; diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c index 3c289281394..33b10a0fc09 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -23,6 +23,8 @@ #include <linux/io.h> #include <linux/pci.h> #include <linux/kdebug.h> +#include <linux/delay.h> +#include <linux/crash_dump.h> #include <asm/uv/uv_mmrs.h> #include <asm/uv/uv_hub.h> @@ -34,6 +36,7 @@ #include <asm/ipi.h> #include <asm/smp.h> #include <asm/x86_init.h> +#include <asm/emergency-restart.h> DEFINE_PER_CPU(int, x2apic_extra_bits); @@ -810,4 +813,11 @@ void __init uv_system_init(void) /* register Legacy VGA I/O redirection handler */ pci_register_set_vga_state(uv_set_vga_state); + + /* + * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as + * EFI is not enabled in the kdump kernel. + */ + if (is_kdump_kernel()) + reboot_type = BOOT_ACPI; } diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c index 0b4be431c62..adee12e0da1 100644 --- a/arch/x86/kernel/apm_32.c +++ b/arch/x86/kernel/apm_32.c @@ -228,6 +228,7 @@ #include <linux/kthread.h> #include <linux/jiffies.h> #include <linux/acpi.h> +#include <linux/syscore_ops.h> #include <asm/system.h> #include <asm/uaccess.h> @@ -1238,6 +1239,7 @@ static int suspend(int vetoable) local_irq_disable(); sysdev_suspend(PMSG_SUSPEND); + syscore_suspend(); local_irq_enable(); @@ -1255,6 +1257,7 @@ static int suspend(int vetoable) apm_error("suspend", err); err = (err == APM_SUCCESS) ? 0 : -EIO; + syscore_resume(); sysdev_resume(); local_irq_enable(); @@ -1280,6 +1283,7 @@ static void standby(void) local_irq_disable(); sysdev_suspend(PMSG_SUSPEND); + syscore_suspend(); local_irq_enable(); err = set_system_power_state(APM_STATE_STANDBY); @@ -1287,6 +1291,7 @@ static void standby(void) apm_error("standby", err); local_irq_disable(); + syscore_resume(); sysdev_resume(); local_irq_enable(); diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 3ecece0217e..bb9eb29a52d 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -615,6 +615,25 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) /* As a rule processors have APIC timer running in deep C states */ if (c->x86 >= 0xf && !cpu_has_amd_erratum(amd_erratum_400)) set_cpu_cap(c, X86_FEATURE_ARAT); + + /* + * Disable GART TLB Walk Errors on Fam10h. We do this here + * because this is always needed when GART is enabled, even in a + * kernel which has no MCE support built in. + */ + if (c->x86 == 0x10) { + /* + * BIOS should disable GartTlbWlk Errors themself. If + * it doesn't do it here as suggested by the BKDG. + * + * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 + */ + u64 mask; + + rdmsrl(MSR_AMD64_MCx_MASK(4), mask); + mask |= (1 << 10); + wrmsrl(MSR_AMD64_MCx_MASK(4), mask); + } } #ifdef CONFIG_X86_32 @@ -679,7 +698,7 @@ cpu_dev_register(amd_cpu_dev); */ const int amd_erratum_400[] = - AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), + AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0x0f, 0x4, 0x2, 0xff, 0xf), AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); EXPORT_SYMBOL_GPL(amd_erratum_400); diff --git a/arch/x86/kernel/cpu/mcheck/mce-apei.c b/arch/x86/kernel/cpu/mcheck/mce-apei.c index 8209472b27a..83930deec3c 100644 --- a/arch/x86/kernel/cpu/mcheck/mce-apei.c +++ b/arch/x86/kernel/cpu/mcheck/mce-apei.c @@ -106,24 +106,34 @@ int apei_write_mce(struct mce *m) ssize_t apei_read_mce(struct mce *m, u64 *record_id) { struct cper_mce_record rcd; - ssize_t len; - - len = erst_read_next(&rcd.hdr, sizeof(rcd)); - if (len <= 0) - return len; - /* Can not skip other records in storage via ERST unless clear them */ - else if (len != sizeof(rcd) || - uuid_le_cmp(rcd.hdr.creator_id, CPER_CREATOR_MCE)) { - if (printk_ratelimit()) - pr_warning( - "MCE-APEI: Can not skip the unknown record in ERST"); - return -EIO; - } - + int rc, pos; + + rc = erst_get_record_id_begin(&pos); + if (rc) + return rc; +retry: + rc = erst_get_record_id_next(&pos, record_id); + if (rc) + goto out; + /* no more record */ + if (*record_id == APEI_ERST_INVALID_RECORD_ID) + goto out; + rc = erst_read(*record_id, &rcd.hdr, sizeof(rcd)); + /* someone else has cleared the record, try next one */ + if (rc == -ENOENT) + goto retry; + else if (rc < 0) + goto out; + /* try to skip other type records in storage */ + else if (rc != sizeof(rcd) || + uuid_le_cmp(rcd.hdr.creator_id, CPER_CREATOR_MCE)) + goto retry; memcpy(m, &rcd.mce, sizeof(*m)); - *record_id = rcd.hdr.record_id; + rc = sizeof(*m); +out: + erst_get_record_id_end(); - return sizeof(*m); + return rc; } /* Check whether there is record in ERST */ diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index ab1122998db..3385ea26f68 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -21,6 +21,7 @@ #include <linux/percpu.h> #include <linux/string.h> #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/delay.h> #include <linux/ctype.h> #include <linux/sched.h> @@ -1625,7 +1626,7 @@ out: static unsigned int mce_poll(struct file *file, poll_table *wait) { poll_wait(file, &mce_wait, wait); - if (rcu_dereference_check_mce(mcelog.next)) + if (rcu_access_index(mcelog.next)) return POLLIN | POLLRDNORM; if (!mce_apei_read_done && apei_check_mce()) return POLLIN | POLLRDNORM; @@ -1749,14 +1750,14 @@ static int mce_disable_error_reporting(void) return 0; } -static int mce_suspend(struct sys_device *dev, pm_message_t state) +static int mce_suspend(void) { return mce_disable_error_reporting(); } -static int mce_shutdown(struct sys_device *dev) +static void mce_shutdown(void) { - return mce_disable_error_reporting(); + mce_disable_error_reporting(); } /* @@ -1764,14 +1765,18 @@ static int mce_shutdown(struct sys_device *dev) * Only one CPU is active at this time, the others get re-added later using * CPU hotplug: */ -static int mce_resume(struct sys_device *dev) +static void mce_resume(void) { __mcheck_cpu_init_generic(); __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info)); - - return 0; } +static struct syscore_ops mce_syscore_ops = { + .suspend = mce_suspend, + .shutdown = mce_shutdown, + .resume = mce_resume, +}; + static void mce_cpu_restart(void *data) { del_timer_sync(&__get_cpu_var(mce_timer)); @@ -1808,9 +1813,6 @@ static void mce_enable_ce(void *all) } static struct sysdev_class mce_sysclass = { - .suspend = mce_suspend, - .shutdown = mce_shutdown, - .resume = mce_resume, .name = "machinecheck", }; @@ -2139,6 +2141,7 @@ static __init int mcheck_init_device(void) return err; } + register_syscore_ops(&mce_syscore_ops); register_hotcpu_notifier(&mce_cpu_notifier); misc_register(&mce_log_device); diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c index bebabec5b44..929739a653d 100644 --- a/arch/x86/kernel/cpu/mtrr/main.c +++ b/arch/x86/kernel/cpu/mtrr/main.c @@ -45,6 +45,7 @@ #include <linux/cpu.h> #include <linux/pci.h> #include <linux/smp.h> +#include <linux/syscore_ops.h> #include <asm/processor.h> #include <asm/e820.h> @@ -292,14 +293,24 @@ set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type typ /* * HACK! - * We use this same function to initialize the mtrrs on boot. - * The state of the boot cpu's mtrrs has been saved, and we want - * to replicate across all the APs. - * If we're doing that @reg is set to something special... + * + * We use this same function to initialize the mtrrs during boot, + * resume, runtime cpu online and on an explicit request to set a + * specific MTRR. + * + * During boot or suspend, the state of the boot cpu's mtrrs has been + * saved, and we want to replicate that across all the cpus that come + * online (either at the end of boot or resume or during a runtime cpu + * online). If we're doing that, @reg is set to something special and on + * this cpu we still do mtrr_if->set_all(). During boot/resume, this + * is unnecessary if at this point we are still on the cpu that started + * the boot/resume sequence. But there is no guarantee that we are still + * on the same cpu. So we do mtrr_if->set_all() on this cpu aswell to be + * sure that we are in sync with everyone else. */ if (reg != ~0U) mtrr_if->set(reg, base, size, type); - else if (!mtrr_aps_delayed_init) + else mtrr_if->set_all(); /* Wait for the others */ @@ -630,7 +641,7 @@ struct mtrr_value { static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES]; -static int mtrr_save(struct sys_device *sysdev, pm_message_t state) +static int mtrr_save(void) { int i; @@ -642,7 +653,7 @@ static int mtrr_save(struct sys_device *sysdev, pm_message_t state) return 0; } -static int mtrr_restore(struct sys_device *sysdev) +static void mtrr_restore(void) { int i; @@ -653,12 +664,11 @@ static int mtrr_restore(struct sys_device *sysdev) mtrr_value[i].ltype); } } - return 0; } -static struct sysdev_driver mtrr_sysdev_driver = { +static struct syscore_ops mtrr_syscore_ops = { .suspend = mtrr_save, .resume = mtrr_restore, }; @@ -839,7 +849,7 @@ static int __init mtrr_init_finialize(void) * TBD: is there any system with such CPU which supports * suspend/resume? If no, we should remove the code. */ - sysdev_driver_register(&cpu_sysdev_class, &mtrr_sysdev_driver); + register_syscore_ops(&mtrr_syscore_ops); return 0; } diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index 87eab4a27df..e638689279d 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -500,12 +500,17 @@ static bool check_hw_exists(void) return true; bios_fail: - printk(KERN_CONT "Broken BIOS detected, using software events only.\n"); + /* + * We still allow the PMU driver to operate: + */ + printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n"); printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val); - return false; + + return true; msr_fail: printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); + return false; } @@ -581,8 +586,12 @@ static int x86_setup_perfctr(struct perf_event *event) return -EOPNOTSUPP; } + /* + * Do not allow config1 (extended registers) to propagate, + * there's no sane user-space generalization yet: + */ if (attr->type == PERF_TYPE_RAW) - return x86_pmu_extra_regs(event->attr.config, event); + return 0; if (attr->type == PERF_TYPE_HW_CACHE) return set_ext_hw_attr(hwc, event); @@ -604,8 +613,8 @@ static int x86_setup_perfctr(struct perf_event *event) /* * Branch tracing: */ - if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) && - (hwc->sample_period == 1)) { + if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && + !attr->freq && hwc->sample_period == 1) { /* BTS is not supported by this architecture. */ if (!x86_pmu.bts_active) return -EOPNOTSUPP; @@ -912,7 +921,7 @@ static inline void x86_assign_hw_event(struct perf_event *event, hwc->event_base = 0; } else if (hwc->idx >= X86_PMC_IDX_FIXED) { hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; - hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0; + hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED); } else { hwc->config_base = x86_pmu_config_addr(hwc->idx); hwc->event_base = x86_pmu_event_addr(hwc->idx); @@ -1279,6 +1288,16 @@ static int x86_pmu_handle_irq(struct pt_regs *regs) cpuc = &__get_cpu_var(cpu_hw_events); + /* + * Some chipsets need to unmask the LVTPC in a particular spot + * inside the nmi handler. As a result, the unmasking was pushed + * into all the nmi handlers. + * + * This generic handler doesn't seem to have any issues where the + * unmasking occurs so it was left at the top. + */ + apic_write(APIC_LVTPC, APIC_DM_NMI); + for (idx = 0; idx < x86_pmu.num_counters; idx++) { if (!test_bit(idx, cpuc->active_mask)) { /* @@ -1365,8 +1384,6 @@ perf_event_nmi_handler(struct notifier_block *self, return NOTIFY_DONE; } - apic_write(APIC_LVTPC, APIC_DM_NMI); - handled = x86_pmu.handle_irq(args->regs); if (!handled) return NOTIFY_DONE; diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c index 461f62bbd77..cf4e369cea6 100644 --- a/arch/x86/kernel/cpu/perf_event_amd.c +++ b/arch/x86/kernel/cpu/perf_event_amd.c @@ -8,7 +8,7 @@ static __initconst const u64 amd_hw_cache_event_ids [ C(L1D) ] = { [ C(OP_READ) ] = { [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ - [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */ + [ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */ }, [ C(OP_WRITE) ] = { [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */ @@ -427,7 +427,9 @@ static __initconst const struct x86_pmu amd_pmu = { * * Exceptions: * + * 0x000 FP PERF_CTL[3], PERF_CTL[5:3] (*) * 0x003 FP PERF_CTL[3] + * 0x004 FP PERF_CTL[3], PERF_CTL[5:3] (*) * 0x00B FP PERF_CTL[3] * 0x00D FP PERF_CTL[3] * 0x023 DE PERF_CTL[2:0] @@ -448,6 +450,8 @@ static __initconst const struct x86_pmu amd_pmu = { * 0x0DF LS PERF_CTL[5:0] * 0x1D6 EX PERF_CTL[5:0] * 0x1D8 EX PERF_CTL[5:0] + * + * (*) depending on the umask all FPU counters may be used */ static struct event_constraint amd_f15_PMC0 = EVENT_CONSTRAINT(0, 0x01, 0); @@ -460,18 +464,28 @@ static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0); static struct event_constraint * amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *event) { - unsigned int event_code = amd_get_event_code(&event->hw); + struct hw_perf_event *hwc = &event->hw; + unsigned int event_code = amd_get_event_code(hwc); switch (event_code & AMD_EVENT_TYPE_MASK) { case AMD_EVENT_FP: switch (event_code) { + case 0x000: + if (!(hwc->config & 0x0000F000ULL)) + break; + if (!(hwc->config & 0x00000F00ULL)) + break; + return &amd_f15_PMC3; + case 0x004: + if (hweight_long(hwc->config & ARCH_PERFMON_EVENTSEL_UMASK) <= 1) + break; + return &amd_f15_PMC3; case 0x003: case 0x00B: case 0x00D: return &amd_f15_PMC3; - default: - return &amd_f15_PMC53; } + return &amd_f15_PMC53; case AMD_EVENT_LS: case AMD_EVENT_DC: case AMD_EVENT_EX_LS: diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 8fc2b2cee1d..447a28de6f0 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -25,7 +25,7 @@ struct intel_percore { /* * Intel PerfMon, used on Core and later. */ -static const u64 intel_perfmon_event_map[] = +static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = { [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, @@ -184,26 +184,23 @@ static __initconst const u64 snb_hw_cache_event_ids }, }, [ C(LL ) ] = { - /* - * TBD: Need Off-core Response Performance Monitoring support - */ [ C(OP_READ) ] = { - /* OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE */ + /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ [ C(RESULT_ACCESS) ] = 0x01b7, - /* OFFCORE_RESPONSE_1.ANY_DATA.ANY_LLC_MISS */ - [ C(RESULT_MISS) ] = 0x01bb, + /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ + [ C(RESULT_MISS) ] = 0x01b7, }, [ C(OP_WRITE) ] = { - /* OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE */ + /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ [ C(RESULT_ACCESS) ] = 0x01b7, - /* OFFCORE_RESPONSE_1.ANY_RFO.ANY_LLC_MISS */ - [ C(RESULT_MISS) ] = 0x01bb, + /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ + [ C(RESULT_MISS) ] = 0x01b7, }, [ C(OP_PREFETCH) ] = { - /* OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE */ + /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ [ C(RESULT_ACCESS) ] = 0x01b7, - /* OFFCORE_RESPONSE_1.PREFETCH.ANY_LLC_MISS */ - [ C(RESULT_MISS) ] = 0x01bb, + /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ + [ C(RESULT_MISS) ] = 0x01b7, }, }, [ C(DTLB) ] = { @@ -285,26 +282,26 @@ static __initconst const u64 westmere_hw_cache_event_ids }, [ C(LL ) ] = { [ C(OP_READ) ] = { - /* OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE */ + /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ [ C(RESULT_ACCESS) ] = 0x01b7, - /* OFFCORE_RESPONSE_1.ANY_DATA.ANY_LLC_MISS */ - [ C(RESULT_MISS) ] = 0x01bb, + /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ + [ C(RESULT_MISS) ] = 0x01b7, }, /* * Use RFO, not WRITEBACK, because a write miss would typically occur * on RFO. */ [ C(OP_WRITE) ] = { - /* OFFCORE_RESPONSE_1.ANY_RFO.LOCAL_CACHE */ - [ C(RESULT_ACCESS) ] = 0x01bb, - /* OFFCORE_RESPONSE_0.ANY_RFO.ANY_LLC_MISS */ + /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ + [ C(RESULT_ACCESS) ] = 0x01b7, + /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ [ C(RESULT_MISS) ] = 0x01b7, }, [ C(OP_PREFETCH) ] = { - /* OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE */ + /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ [ C(RESULT_ACCESS) ] = 0x01b7, - /* OFFCORE_RESPONSE_1.PREFETCH.ANY_LLC_MISS */ - [ C(RESULT_MISS) ] = 0x01bb, + /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ + [ C(RESULT_MISS) ] = 0x01b7, }, }, [ C(DTLB) ] = { @@ -352,16 +349,36 @@ static __initconst const u64 westmere_hw_cache_event_ids }; /* - * OFFCORE_RESPONSE MSR bits (subset), See IA32 SDM Vol 3 30.6.1.3 + * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; + * See IA32 SDM Vol 3B 30.6.1.3 */ -#define DMND_DATA_RD (1 << 0) -#define DMND_RFO (1 << 1) -#define DMND_WB (1 << 3) -#define PF_DATA_RD (1 << 4) -#define PF_DATA_RFO (1 << 5) -#define RESP_UNCORE_HIT (1 << 8) -#define RESP_MISS (0xf600) /* non uncore hit */ +#define NHM_DMND_DATA_RD (1 << 0) +#define NHM_DMND_RFO (1 << 1) +#define NHM_DMND_IFETCH (1 << 2) +#define NHM_DMND_WB (1 << 3) +#define NHM_PF_DATA_RD (1 << 4) +#define NHM_PF_DATA_RFO (1 << 5) +#define NHM_PF_IFETCH (1 << 6) +#define NHM_OFFCORE_OTHER (1 << 7) +#define NHM_UNCORE_HIT (1 << 8) +#define NHM_OTHER_CORE_HIT_SNP (1 << 9) +#define NHM_OTHER_CORE_HITM (1 << 10) + /* reserved */ +#define NHM_REMOTE_CACHE_FWD (1 << 12) +#define NHM_REMOTE_DRAM (1 << 13) +#define NHM_LOCAL_DRAM (1 << 14) +#define NHM_NON_DRAM (1 << 15) + +#define NHM_ALL_DRAM (NHM_REMOTE_DRAM|NHM_LOCAL_DRAM) + +#define NHM_DMND_READ (NHM_DMND_DATA_RD) +#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) +#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) + +#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) +#define NHM_L3_MISS (NHM_NON_DRAM|NHM_ALL_DRAM|NHM_REMOTE_CACHE_FWD) +#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) static __initconst const u64 nehalem_hw_cache_extra_regs [PERF_COUNT_HW_CACHE_MAX] @@ -370,16 +387,16 @@ static __initconst const u64 nehalem_hw_cache_extra_regs { [ C(LL ) ] = { [ C(OP_READ) ] = { - [ C(RESULT_ACCESS) ] = DMND_DATA_RD|RESP_UNCORE_HIT, - [ C(RESULT_MISS) ] = DMND_DATA_RD|RESP_MISS, + [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, + [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, }, [ C(OP_WRITE) ] = { - [ C(RESULT_ACCESS) ] = DMND_RFO|DMND_WB|RESP_UNCORE_HIT, - [ C(RESULT_MISS) ] = DMND_RFO|DMND_WB|RESP_MISS, + [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, + [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, }, [ C(OP_PREFETCH) ] = { - [ C(RESULT_ACCESS) ] = PF_DATA_RD|PF_DATA_RFO|RESP_UNCORE_HIT, - [ C(RESULT_MISS) ] = PF_DATA_RD|PF_DATA_RFO|RESP_MISS, + [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, + [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, }, } }; @@ -391,12 +408,12 @@ static __initconst const u64 nehalem_hw_cache_event_ids { [ C(L1D) ] = { [ C(OP_READ) ] = { - [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ - [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ + [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ + [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ }, [ C(OP_WRITE) ] = { - [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ - [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ + [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ + [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ }, [ C(OP_PREFETCH) ] = { [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ @@ -933,6 +950,16 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) cpuc = &__get_cpu_var(cpu_hw_events); + /* + * Some chipsets need to unmask the LVTPC in a particular spot + * inside the nmi handler. As a result, the unmasking was pushed + * into all the nmi handlers. + * + * This handler doesn't seem to have any issues with the unmasking + * so it was left at the top. + */ + apic_write(APIC_LVTPC, APIC_DM_NMI); + intel_pmu_disable_all(); handled = intel_pmu_drain_bts_buffer(); status = intel_pmu_get_status(); @@ -998,6 +1025,9 @@ intel_bts_constraints(struct perf_event *event) struct hw_perf_event *hwc = &event->hw; unsigned int hw_event, bts_event; + if (event->attr.freq) + return NULL; + hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); @@ -1305,7 +1335,7 @@ static void intel_clovertown_quirks(void) * AJ106 could possibly be worked around by not allowing LBR * usage from PEBS, including the fixup. * AJ68 could possibly be worked around by always programming - * a pebs_event_reset[0] value and coping with the lost events. + * a pebs_event_reset[0] value and coping with the lost events. * * But taken together it might just make sense to not enable PEBS on * these chips. @@ -1409,6 +1439,18 @@ static __init int intel_pmu_init(void) x86_pmu.percore_constraints = intel_nehalem_percore_constraints; x86_pmu.enable_all = intel_pmu_nhm_enable_all; x86_pmu.extra_regs = intel_nehalem_extra_regs; + + if (ebx & 0x40) { + /* + * Erratum AAJ80 detected, we work it around by using + * the BR_MISP_EXEC.ANY event. This will over-count + * branch-misses, but it's still much better than the + * architectural event which is often completely bogus: + */ + intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; + + pr_cont("erratum AAJ80 worked around, "); + } pr_cont("Nehalem events, "); break; @@ -1425,6 +1467,7 @@ static __init int intel_pmu_init(void) case 37: /* 32 nm nehalem, "Clarkdale" */ case 44: /* 32 nm nehalem, "Gulftown" */ + case 47: /* 32 nm Xeon E7 */ memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c index 0811f5ebfba..e93fcd55fae 100644 --- a/arch/x86/kernel/cpu/perf_event_p4.c +++ b/arch/x86/kernel/cpu/perf_event_p4.c @@ -777,6 +777,7 @@ static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc) * the counter has reached zero value and continued counting before * real NMI signal was received: */ + rdmsrl(hwc->event_base, v); if (!(v & ARCH_P4_UNFLAGGED_BIT)) return 1; @@ -946,14 +947,23 @@ static int p4_pmu_handle_irq(struct pt_regs *regs) if (!x86_perf_event_set_period(event)) continue; if (perf_event_overflow(event, 1, &data, regs)) - p4_pmu_disable_event(event); + x86_pmu_stop(event, 0); } - if (handled) { - /* p4 quirk: unmask it again */ - apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED); + if (handled) inc_irq_stat(apic_perf_irqs); - } + + /* + * When dealing with the unmasking of the LVTPC on P4 perf hw, it has + * been observed that the OVF bit flag has to be cleared first _before_ + * the LVTPC can be unmasked. + * + * The reason is the NMI line will continue to be asserted while the OVF + * bit is set. This causes a second NMI to generate if the LVTPC is + * unmasked before the OVF bit is cleared, leading to unknown NMI + * messages. + */ + apic_write(APIC_LVTPC, APIC_DM_NMI); return handled; } diff --git a/arch/x86/kernel/crash_dump_32.c b/arch/x86/kernel/crash_dump_32.c index d5cd13945d5..642f75a68cd 100644 --- a/arch/x86/kernel/crash_dump_32.c +++ b/arch/x86/kernel/crash_dump_32.c @@ -14,9 +14,6 @@ static void *kdump_buf_page; -/* Stores the physical address of elf header of crash image. */ -unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX; - static inline bool is_crashed_pfn_valid(unsigned long pfn) { #ifndef CONFIG_X86_PAE diff --git a/arch/x86/kernel/crash_dump_64.c b/arch/x86/kernel/crash_dump_64.c index 994828899e0..afa64adb75e 100644 --- a/arch/x86/kernel/crash_dump_64.c +++ b/arch/x86/kernel/crash_dump_64.c @@ -10,9 +10,6 @@ #include <linux/uaccess.h> #include <linux/io.h> -/* Stores the physical address of elf header of crash image. */ -unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX; - /** * copy_oldmem_page - copy one page from "oldmem" * @pfn: page frame number to be copied diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index 7a8cebc9ff2..e90f08458e6 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -65,12 +65,10 @@ unsigned int irq_create_of_mapping(struct device_node *controller, return 0; ret = ih->xlate(ih, intspec, intsize, &virq, &type); if (ret) - return ret; + return 0; if (type == IRQ_TYPE_NONE) return virq; - /* set the mask if it is different from current */ - if (type == (irq_to_desc(virq)->status & IRQF_TRIGGER_MASK)) - set_irq_type(virq, type); + irq_set_irq_type(virq, type); return virq; } EXPORT_SYMBOL_GPL(irq_create_of_mapping); @@ -393,7 +391,7 @@ static int ioapic_xlate(struct irq_domain *id, const u32 *intspec, u32 intsize, set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity); - return io_apic_setup_irq_pin(*out_hwirq, cpu_to_node(0), &attr); + return io_apic_setup_irq_pin_once(*out_hwirq, cpu_to_node(0), &attr); } static void __init ioapic_add_ofnode(struct device_node *np) diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c index 999e2793590..e2a3f0606da 100644 --- a/arch/x86/kernel/dumpstack.c +++ b/arch/x86/kernel/dumpstack.c @@ -27,7 +27,7 @@ static int die_counter; void printk_address(unsigned long address, int reliable) { - printk(" [<%p>] %s%pS\n", (void *) address, + printk(" [<%p>] %s%pB\n", (void *) address, reliable ? "" : "? ", (void *) address); } @@ -322,16 +322,6 @@ void die(const char *str, struct pt_regs *regs, long err) oops_end(flags, regs, sig); } -static int __init oops_setup(char *s) -{ - if (!s) - return -EINVAL; - if (!strcmp(s, "panic")) - panic_on_oops = 1; - return 0; -} -early_param("oops", oops_setup); - static int __init kstack_setup(char *s) { if (!s) diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c index cdf5bfd9d4d..3e2ef842531 100644 --- a/arch/x86/kernel/e820.c +++ b/arch/x86/kernel/e820.c @@ -11,6 +11,7 @@ #include <linux/kernel.h> #include <linux/types.h> #include <linux/init.h> +#include <linux/crash_dump.h> #include <linux/bootmem.h> #include <linux/pfn.h> #include <linux/suspend.h> diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c index 2d2673c28af..5655c2272ad 100644 --- a/arch/x86/kernel/head64.c +++ b/arch/x86/kernel/head64.c @@ -77,9 +77,6 @@ void __init x86_64_start_kernel(char * real_mode_data) /* Make NULL pointers segfault */ zap_identity_mappings(); - /* Cleanup the over mapped high alias */ - cleanup_highmap(); - max_pfn_mapped = KERNEL_IMAGE_SIZE >> PAGE_SHIFT; for (i = 0; i < NUM_EXCEPTION_VECTORS; i++) { diff --git a/arch/x86/kernel/i8237.c b/arch/x86/kernel/i8237.c index b42ca694dc6..8eeaa81de06 100644 --- a/arch/x86/kernel/i8237.c +++ b/arch/x86/kernel/i8237.c @@ -10,7 +10,7 @@ */ #include <linux/init.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <asm/dma.h> @@ -21,7 +21,7 @@ * in asm/dma.h. */ -static int i8237A_resume(struct sys_device *dev) +static void i8237A_resume(void) { unsigned long flags; int i; @@ -41,31 +41,15 @@ static int i8237A_resume(struct sys_device *dev) enable_dma(4); release_dma_lock(flags); - - return 0; } -static int i8237A_suspend(struct sys_device *dev, pm_message_t state) -{ - return 0; -} - -static struct sysdev_class i8237_sysdev_class = { - .name = "i8237", - .suspend = i8237A_suspend, +static struct syscore_ops i8237_syscore_ops = { .resume = i8237A_resume, }; -static struct sys_device device_i8237A = { - .id = 0, - .cls = &i8237_sysdev_class, -}; - -static int __init i8237A_init_sysfs(void) +static int __init i8237A_init_ops(void) { - int error = sysdev_class_register(&i8237_sysdev_class); - if (!error) - error = sysdev_register(&device_i8237A); - return error; + register_syscore_ops(&i8237_syscore_ops); + return 0; } -device_initcall(i8237A_init_sysfs); +device_initcall(i8237A_init_ops); diff --git a/arch/x86/kernel/i8259.c b/arch/x86/kernel/i8259.c index d9ca749c123..65b8f5c2eeb 100644 --- a/arch/x86/kernel/i8259.c +++ b/arch/x86/kernel/i8259.c @@ -8,7 +8,7 @@ #include <linux/random.h> #include <linux/init.h> #include <linux/kernel_stat.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/bitops.h> #include <linux/acpi.h> #include <linux/io.h> @@ -245,20 +245,19 @@ static void save_ELCR(char *trigger) trigger[1] = inb(0x4d1) & 0xDE; } -static int i8259A_resume(struct sys_device *dev) +static void i8259A_resume(void) { init_8259A(i8259A_auto_eoi); restore_ELCR(irq_trigger); - return 0; } -static int i8259A_suspend(struct sys_device *dev, pm_message_t state) +static int i8259A_suspend(void) { save_ELCR(irq_trigger); return 0; } -static int i8259A_shutdown(struct sys_device *dev) +static void i8259A_shutdown(void) { /* Put the i8259A into a quiescent state that * the kernel initialization code can get it @@ -266,21 +265,14 @@ static int i8259A_shutdown(struct sys_device *dev) */ outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */ - return 0; } -static struct sysdev_class i8259_sysdev_class = { - .name = "i8259", +static struct syscore_ops i8259_syscore_ops = { .suspend = i8259A_suspend, .resume = i8259A_resume, .shutdown = i8259A_shutdown, }; -static struct sys_device device_i8259A = { - .id = 0, - .cls = &i8259_sysdev_class, -}; - static void mask_8259A(void) { unsigned long flags; @@ -399,17 +391,12 @@ struct legacy_pic default_legacy_pic = { struct legacy_pic *legacy_pic = &default_legacy_pic; -static int __init i8259A_init_sysfs(void) +static int __init i8259A_init_ops(void) { - int error; - - if (legacy_pic != &default_legacy_pic) - return 0; + if (legacy_pic == &default_legacy_pic) + register_syscore_ops(&i8259_syscore_ops); - error = sysdev_class_register(&i8259_sysdev_class); - if (!error) - error = sysdev_register(&device_i8259A); - return error; + return 0; } -device_initcall(i8259A_init_sysfs); +device_initcall(i8259A_init_ops); diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c index 948a31eae75..1cb0b9fc78d 100644 --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c @@ -8,6 +8,7 @@ #include <linux/seq_file.h> #include <linux/smp.h> #include <linux/ftrace.h> +#include <linux/delay.h> #include <asm/apic.h> #include <asm/io_apic.h> diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c index dba0b36941a..5f9ecff328b 100644 --- a/arch/x86/kernel/kgdb.c +++ b/arch/x86/kernel/kgdb.c @@ -121,8 +121,8 @@ char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs) memcpy(mem, (void *)regs + dbg_reg_def[regno].offset, dbg_reg_def[regno].size); - switch (regno) { #ifdef CONFIG_X86_32 + switch (regno) { case GDB_SS: if (!user_mode_vm(regs)) *(unsigned long *)mem = __KERNEL_DS; @@ -135,8 +135,8 @@ char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs) case GDB_FS: *(unsigned long *)mem = 0xFFFF; break; -#endif } +#endif return dbg_reg_def[regno].name; } diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c index 87af68e0e1e..f9242800bc8 100644 --- a/arch/x86/kernel/microcode_core.c +++ b/arch/x86/kernel/microcode_core.c @@ -82,6 +82,7 @@ #include <linux/cpu.h> #include <linux/fs.h> #include <linux/mm.h> +#include <linux/syscore_ops.h> #include <asm/microcode.h> #include <asm/processor.h> @@ -438,33 +439,25 @@ static int mc_sysdev_remove(struct sys_device *sys_dev) return 0; } -static int mc_sysdev_resume(struct sys_device *dev) +static struct sysdev_driver mc_sysdev_driver = { + .add = mc_sysdev_add, + .remove = mc_sysdev_remove, +}; + +/** + * mc_bp_resume - Update boot CPU microcode during resume. + */ +static void mc_bp_resume(void) { - int cpu = dev->id; + int cpu = smp_processor_id(); struct ucode_cpu_info *uci = ucode_cpu_info + cpu; - if (!cpu_online(cpu)) - return 0; - - /* - * All non-bootup cpus are still disabled, - * so only CPU 0 will apply ucode here. - * - * Moreover, there can be no concurrent - * updates from any other places at this point. - */ - WARN_ON(cpu != 0); - if (uci->valid && uci->mc) microcode_ops->apply_microcode(cpu); - - return 0; } -static struct sysdev_driver mc_sysdev_driver = { - .add = mc_sysdev_add, - .remove = mc_sysdev_remove, - .resume = mc_sysdev_resume, +static struct syscore_ops mc_syscore_ops = { + .resume = mc_bp_resume, }; static __cpuinit int @@ -542,6 +535,7 @@ static int __init microcode_init(void) if (error) return error; + register_syscore_ops(&mc_syscore_ops); register_hotcpu_notifier(&mc_cpu_notifier); pr_info("Microcode Update Driver: v" MICROCODE_VERSION @@ -556,6 +550,7 @@ static void __exit microcode_exit(void) microcode_dev_exit(); unregister_hotcpu_notifier(&mc_cpu_notifier); + unregister_syscore_ops(&mc_syscore_ops); get_online_cpus(); mutex_lock(µcode_mutex); diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c index 6f789a887c0..5a532ce646b 100644 --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -714,10 +714,6 @@ static void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare) *nr_m_spare += 1; } } -#else /* CONFIG_X86_IO_APIC */ -static -inline void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare) {} -#endif /* CONFIG_X86_IO_APIC */ static int check_slot(unsigned long mpc_new_phys, unsigned long mpc_new_length, int count) @@ -731,6 +727,10 @@ check_slot(unsigned long mpc_new_phys, unsigned long mpc_new_length, int count) return ret; } +#else /* CONFIG_X86_IO_APIC */ +static +inline void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare) {} +#endif /* CONFIG_X86_IO_APIC */ static int __init replace_intsrc_all(struct mpc_table *mpc, unsigned long mpc_new_phys, diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c index c01ffa5b9b8..b117efd24f7 100644 --- a/arch/x86/kernel/pci-gart_64.c +++ b/arch/x86/kernel/pci-gart_64.c @@ -27,7 +27,7 @@ #include <linux/kdebug.h> #include <linux/scatterlist.h> #include <linux/iommu-helper.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/io.h> #include <linux/gfp.h> #include <asm/atomic.h> @@ -81,6 +81,9 @@ static u32 gart_unmapped_entry; #define AGPEXTERN #endif +/* GART can only remap to physical addresses < 1TB */ +#define GART_MAX_PHYS_ADDR (1ULL << 40) + /* backdoor interface to AGP driver */ AGPEXTERN int agp_memory_reserved; AGPEXTERN __u32 *agp_gatt_table; @@ -212,9 +215,13 @@ static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem, size_t size, int dir, unsigned long align_mask) { unsigned long npages = iommu_num_pages(phys_mem, size, PAGE_SIZE); - unsigned long iommu_page = alloc_iommu(dev, npages, align_mask); + unsigned long iommu_page; int i; + if (unlikely(phys_mem + size > GART_MAX_PHYS_ADDR)) + return bad_dma_addr; + + iommu_page = alloc_iommu(dev, npages, align_mask); if (iommu_page == -1) { if (!nonforced_iommu(dev, phys_mem, size)) return phys_mem; @@ -589,7 +596,7 @@ void set_up_gart_resume(u32 aper_order, u32 aper_alloc) aperture_alloc = aper_alloc; } -static void gart_fixup_northbridges(struct sys_device *dev) +static void gart_fixup_northbridges(void) { int i; @@ -613,33 +620,20 @@ static void gart_fixup_northbridges(struct sys_device *dev) } } -static int gart_resume(struct sys_device *dev) +static void gart_resume(void) { pr_info("PCI-DMA: Resuming GART IOMMU\n"); - gart_fixup_northbridges(dev); + gart_fixup_northbridges(); enable_gart_translations(); - - return 0; } -static int gart_suspend(struct sys_device *dev, pm_message_t state) -{ - return 0; -} - -static struct sysdev_class gart_sysdev_class = { - .name = "gart", - .suspend = gart_suspend, +static struct syscore_ops gart_syscore_ops = { .resume = gart_resume, }; -static struct sys_device device_gart = { - .cls = &gart_sysdev_class, -}; - /* * Private Northbridge GATT initialization in case we cannot use the * AGP driver for some reason. @@ -650,7 +644,7 @@ static __init int init_amd_gatt(struct agp_kern_info *info) unsigned aper_base, new_aper_base; struct pci_dev *dev; void *gatt; - int i, error; + int i; pr_info("PCI-DMA: Disabling AGP.\n"); @@ -685,12 +679,7 @@ static __init int init_amd_gatt(struct agp_kern_info *info) agp_gatt_table = gatt; - error = sysdev_class_register(&gart_sysdev_class); - if (!error) - error = sysdev_register(&device_gart); - if (error) - panic("Could not register gart_sysdev -- " - "would corrupt data on next suspend"); + register_syscore_ops(&gart_syscore_ops); flush_gart(); diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index bd387e8f73b..6c9dd922ac0 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -501,6 +501,10 @@ void set_personality_64bit(void) /* Make sure to be in 64bit mode */ clear_thread_flag(TIF_IA32); + /* Ensure the corresponding mm is not marked. */ + if (current->mm) + current->mm->context.ia32_compat = 0; + /* TBD: overwrites user setup. Should have two bits. But 64bit processes have always behaved this way, so it's not too bad. The main problem is just that @@ -516,6 +520,10 @@ void set_personality_ia32(void) set_thread_flag(TIF_IA32); current->personality |= force_personality32; + /* Mark the associated mm as containing 32-bit tasks. */ + if (current->mm) + current->mm->context.ia32_compat = 1; + /* Prepare the first "return" to user space */ current_thread_info()->status |= TS_COMPAT; } diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c index 45892dc4b72..f65e5b521db 100644 --- a/arch/x86/kernel/ptrace.c +++ b/arch/x86/kernel/ptrace.c @@ -608,6 +608,9 @@ static int ptrace_write_dr7(struct task_struct *tsk, unsigned long data) unsigned len, type; struct perf_event *bp; + if (ptrace_get_breakpoints(tsk) < 0) + return -ESRCH; + data &= ~DR_CONTROL_RESERVED; old_dr7 = ptrace_get_dr7(thread->ptrace_bps); restore: @@ -655,6 +658,9 @@ restore: } goto restore; } + + ptrace_put_breakpoints(tsk); + return ((orig_ret < 0) ? orig_ret : rc); } @@ -668,10 +674,17 @@ static unsigned long ptrace_get_debugreg(struct task_struct *tsk, int n) if (n < HBP_NUM) { struct perf_event *bp; + + if (ptrace_get_breakpoints(tsk) < 0) + return -ESRCH; + bp = thread->ptrace_bps[n]; if (!bp) - return 0; - val = bp->hw.info.address; + val = 0; + else + val = bp->hw.info.address; + + ptrace_put_breakpoints(tsk); } else if (n == 6) { val = thread->debugreg6; } else if (n == 7) { @@ -686,6 +699,10 @@ static int ptrace_set_breakpoint_addr(struct task_struct *tsk, int nr, struct perf_event *bp; struct thread_struct *t = &tsk->thread; struct perf_event_attr attr; + int err = 0; + + if (ptrace_get_breakpoints(tsk) < 0) + return -ESRCH; if (!t->ptrace_bps[nr]) { ptrace_breakpoint_init(&attr); @@ -709,24 +726,23 @@ static int ptrace_set_breakpoint_addr(struct task_struct *tsk, int nr, * writing for the user. And anyway this is the previous * behaviour. */ - if (IS_ERR(bp)) - return PTR_ERR(bp); + if (IS_ERR(bp)) { + err = PTR_ERR(bp); + goto put; + } t->ptrace_bps[nr] = bp; } else { - int err; - bp = t->ptrace_bps[nr]; attr = bp->attr; attr.bp_addr = addr; err = modify_user_hw_breakpoint(bp, &attr); - if (err) - return err; } - - return 0; +put: + ptrace_put_breakpoints(tsk); + return err; } /* diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index d3ce37edb54..08c44b08bf5 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c @@ -6,6 +6,7 @@ #include <linux/dmi.h> #include <linux/sched.h> #include <linux/tboot.h> +#include <linux/delay.h> #include <acpi/reboot.h> #include <asm/io.h> #include <asm/apic.h> diff --git a/arch/x86/kernel/reboot_32.S b/arch/x86/kernel/reboot_32.S index 29092b38d81..1d5c46df0d7 100644 --- a/arch/x86/kernel/reboot_32.S +++ b/arch/x86/kernel/reboot_32.S @@ -21,26 +21,26 @@ r_base = . /* Get our own relocated address */ call 1f 1: popl %ebx - subl $1b, %ebx + subl $(1b - r_base), %ebx /* Compute the equivalent real-mode segment */ movl %ebx, %ecx shrl $4, %ecx /* Patch post-real-mode segment jump */ - movw dispatch_table(%ebx,%eax,2),%ax - movw %ax, 101f(%ebx) - movw %cx, 102f(%ebx) + movw (dispatch_table - r_base)(%ebx,%eax,2),%ax + movw %ax, (101f - r_base)(%ebx) + movw %cx, (102f - r_base)(%ebx) /* Set up the IDT for real mode. */ - lidtl machine_real_restart_idt(%ebx) + lidtl (machine_real_restart_idt - r_base)(%ebx) /* * Set up a GDT from which we can load segment descriptors for real * mode. The GDT is not used in real mode; it is just needed here to * prepare the descriptors. */ - lgdtl machine_real_restart_gdt(%ebx) + lgdtl (machine_real_restart_gdt - r_base)(%ebx) /* * Load the data segment registers with 16-bit compatible values diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index 9d43b28e072..4be9b398470 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -294,30 +294,11 @@ static void __init init_gbpages(void) else direct_gbpages = 0; } - -static void __init cleanup_highmap_brk_end(void) -{ - pud_t *pud; - pmd_t *pmd; - - mmu_cr4_features = read_cr4(); - - /* - * _brk_end cannot change anymore, but it and _end may be - * located on different 2M pages. cleanup_highmap(), however, - * can only consider _end when it runs, so destroy any - * mappings beyond _brk_end here. - */ - pud = pud_offset(pgd_offset_k(_brk_end), _brk_end); - pmd = pmd_offset(pud, _brk_end - 1); - while (++pmd <= pmd_offset(pud, (unsigned long)_end - 1)) - pmd_clear(pmd); -} #else static inline void init_gbpages(void) { } -static inline void cleanup_highmap_brk_end(void) +static void __init cleanup_highmap(void) { } #endif @@ -330,8 +311,6 @@ static void __init reserve_brk(void) /* Mark brk area as locked down and no longer taking any new allocations */ _brk_start = 0; - - cleanup_highmap_brk_end(); } #ifdef CONFIG_BLK_DEV_INITRD @@ -640,28 +619,6 @@ void __init reserve_standard_io_resources(void) } -/* - * Note: elfcorehdr_addr is not just limited to vmcore. It is also used by - * is_kdump_kernel() to determine if we are booting after a panic. Hence - * ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE. - */ - -#ifdef CONFIG_CRASH_DUMP -/* elfcorehdr= specifies the location of elf core header - * stored by the crashed kernel. This option will be passed - * by kexec loader to the capture kernel. - */ -static int __init setup_elfcorehdr(char *arg) -{ - char *end; - if (!arg) - return -EINVAL; - elfcorehdr_addr = memparse(arg, &end); - return end > arg ? 0 : -EINVAL; -} -early_param("elfcorehdr", setup_elfcorehdr); -#endif - static __init void reserve_ibft_region(void) { unsigned long addr, size = 0; @@ -950,6 +907,8 @@ void __init setup_arch(char **cmdline_p) */ reserve_brk(); + cleanup_highmap(); + memblock.current_limit = get_max_mapped(); memblock_x86_fill(); @@ -1017,6 +976,11 @@ void __init setup_arch(char **cmdline_p) paging_init(); x86_init.paging.pagetable_setup_done(swapper_pg_dir); + if (boot_cpu_data.cpuid_level >= 0) { + /* A CPU has %cr4 if and only if it has CPUID */ + mmu_cr4_features = read_cr4(); + } + #ifdef CONFIG_X86_32 /* sync back kernel address range */ clone_pgd_range(initial_page_table + KERNEL_PGD_BOUNDARY, diff --git a/arch/x86/kernel/syscall_table_32.S b/arch/x86/kernel/syscall_table_32.S index 5f181742e8f..abce34d5c79 100644 --- a/arch/x86/kernel/syscall_table_32.S +++ b/arch/x86/kernel/syscall_table_32.S @@ -343,3 +343,4 @@ ENTRY(sys_call_table) .long sys_name_to_handle_at .long sys_open_by_handle_at .long sys_clock_adjtime + .long sys_syncfs diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index c11514e9128..75ef4b18e9b 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -61,6 +61,10 @@ struct x86_init_ops x86_init __initdata = { .banner = default_banner, }, + .mapping = { + .pagetable_reserve = native_pagetable_reserve, + }, + .paging = { .pagetable_setup_start = native_pagetable_setup_start, .pagetable_setup_done = native_pagetable_setup_done, diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 58f517b5964..934b4c6b0bf 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -2395,9 +2395,9 @@ static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, int i; entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; - for (i = 1; *nent < maxnent; ++i) { - if (entry[i - 1].eax == 0 && i != 2) - break; + for (i = 1; *nent < maxnent && i < 64; ++i) { + if (entry[i].eax == 0) + continue; do_cpuid_1_ent(&entry[i], function, i); entry[i].flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; @@ -4958,12 +4958,6 @@ struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, best = e; break; } - /* - * Both basic or both extended? - */ - if (((e->function ^ function) & 0x80000000) == 0) - if (!best || e->function > best->function) - best = e; } return best; } @@ -4983,6 +4977,27 @@ not_found: return 36; } +/* + * If no match is found, check whether we exceed the vCPU's limit + * and return the content of the highest valid _standard_ leaf instead. + * This is to satisfy the CPUID specification. + */ +static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu, + u32 function, u32 index) +{ + struct kvm_cpuid_entry2 *maxlevel; + + maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0); + if (!maxlevel || maxlevel->eax >= function) + return NULL; + if (function & 0x80000000) { + maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0); + if (!maxlevel) + return NULL; + } + return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index); +} + void kvm_emulate_cpuid(struct kvm_vcpu *vcpu) { u32 function, index; @@ -4995,6 +5010,10 @@ void kvm_emulate_cpuid(struct kvm_vcpu *vcpu) kvm_register_write(vcpu, VCPU_REGS_RCX, 0); kvm_register_write(vcpu, VCPU_REGS_RDX, 0); best = kvm_find_cpuid_entry(vcpu, function, index); + + if (!best) + best = check_cpuid_limit(vcpu, function, index); + if (best) { kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax); kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx); diff --git a/arch/x86/lib/cmpxchg16b_emu.S b/arch/x86/lib/cmpxchg16b_emu.S index 3e8b08a6de2..1e572c507d0 100644 --- a/arch/x86/lib/cmpxchg16b_emu.S +++ b/arch/x86/lib/cmpxchg16b_emu.S @@ -10,6 +10,12 @@ #include <asm/frame.h> #include <asm/dwarf2.h> +#ifdef CONFIG_SMP +#define SEG_PREFIX %gs: +#else +#define SEG_PREFIX +#endif + .text /* @@ -37,13 +43,13 @@ this_cpu_cmpxchg16b_emu: pushf cli - cmpq %gs:(%rsi), %rax + cmpq SEG_PREFIX(%rsi), %rax jne not_same - cmpq %gs:8(%rsi), %rdx + cmpq SEG_PREFIX 8(%rsi), %rdx jne not_same - movq %rbx, %gs:(%rsi) - movq %rcx, %gs:8(%rsi) + movq %rbx, SEG_PREFIX(%rsi) + movq %rcx, SEG_PREFIX 8(%rsi) popf mov $1, %al diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index 286d289b039..37b8b0fe832 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -81,6 +81,11 @@ static void __init find_early_table_space(unsigned long end, int use_pse, end, pgt_buf_start << PAGE_SHIFT, pgt_buf_top << PAGE_SHIFT); } +void __init native_pagetable_reserve(u64 start, u64 end) +{ + memblock_x86_reserve_range(start, end, "PGTABLE"); +} + struct map_range { unsigned long start; unsigned long end; @@ -272,9 +277,24 @@ unsigned long __init_refok init_memory_mapping(unsigned long start, __flush_tlb_all(); + /* + * Reserve the kernel pagetable pages we used (pgt_buf_start - + * pgt_buf_end) and free the other ones (pgt_buf_end - pgt_buf_top) + * so that they can be reused for other purposes. + * + * On native it just means calling memblock_x86_reserve_range, on Xen it + * also means marking RW the pagetable pages that we allocated before + * but that haven't been used. + * + * In fact on xen we mark RO the whole range pgt_buf_start - + * pgt_buf_top, because we have to make sure that when + * init_memory_mapping reaches the pagetable pages area, it maps + * RO all the pagetable pages, including the ones that are beyond + * pgt_buf_end at that time. + */ if (!after_bootmem && pgt_buf_end > pgt_buf_start) - memblock_x86_reserve_range(pgt_buf_start << PAGE_SHIFT, - pgt_buf_end << PAGE_SHIFT, "PGTABLE"); + x86_init.mapping.pagetable_reserve(PFN_PHYS(pgt_buf_start), + PFN_PHYS(pgt_buf_end)); if (!after_bootmem) early_memtest(start, end); diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index 0aa34669ed3..79423358728 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -52,6 +52,7 @@ #include <asm/cacheflush.h> #include <asm/init.h> #include <asm/uv/uv.h> +#include <asm/setup.h> static int __init parse_direct_gbpages_off(char *arg) { @@ -294,18 +295,18 @@ void __init init_extra_mapping_uc(unsigned long phys, unsigned long size) * to the compile time generated pmds. This results in invalid pmds up * to the point where we hit the physaddr 0 mapping. * - * We limit the mappings to the region from _text to _end. _end is - * rounded up to the 2MB boundary. This catches the invalid pmds as + * We limit the mappings to the region from _text to _brk_end. _brk_end + * is rounded up to the 2MB boundary. This catches the invalid pmds as * well, as they are located before _text: */ void __init cleanup_highmap(void) { unsigned long vaddr = __START_KERNEL_map; - unsigned long end = roundup((unsigned long)_end, PMD_SIZE) - 1; + unsigned long vaddr_end = __START_KERNEL_map + (max_pfn_mapped << PAGE_SHIFT); + unsigned long end = roundup((unsigned long)_brk_end, PMD_SIZE) - 1; pmd_t *pmd = level2_kernel_pgt; - pmd_t *last_pmd = pmd + PTRS_PER_PMD; - for (; pmd < last_pmd; pmd++, vaddr += PMD_SIZE) { + for (; vaddr + PMD_SIZE - 1 < vaddr_end; pmd++, vaddr += PMD_SIZE) { if (pmd_none(*pmd)) continue; if (vaddr < (unsigned long) _text || vaddr > end) @@ -861,18 +862,18 @@ static struct vm_area_struct gate_vma = { .vm_flags = VM_READ | VM_EXEC }; -struct vm_area_struct *get_gate_vma(struct task_struct *tsk) +struct vm_area_struct *get_gate_vma(struct mm_struct *mm) { #ifdef CONFIG_IA32_EMULATION - if (test_tsk_thread_flag(tsk, TIF_IA32)) + if (!mm || mm->context.ia32_compat) return NULL; #endif return &gate_vma; } -int in_gate_area(struct task_struct *task, unsigned long addr) +int in_gate_area(struct mm_struct *mm, unsigned long addr) { - struct vm_area_struct *vma = get_gate_vma(task); + struct vm_area_struct *vma = get_gate_vma(mm); if (!vma) return 0; @@ -881,11 +882,11 @@ int in_gate_area(struct task_struct *task, unsigned long addr) } /* - * Use this when you have no reliable task/vma, typically from interrupt - * context. It is less reliable than using the task's vma and may give - * false positives: + * Use this when you have no reliable mm, typically from interrupt + * context. It is less reliable than using a task's mm and may give + * false positives. */ -int in_gate_area_no_task(unsigned long addr) +int in_gate_area_no_mm(unsigned long addr) { return (addr >= VSYSCALL_START) && (addr < VSYSCALL_END); } diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c index 9559d360fde..745258dfc4d 100644 --- a/arch/x86/mm/numa.c +++ b/arch/x86/mm/numa.c @@ -213,53 +213,48 @@ int early_cpu_to_node(int cpu) return per_cpu(x86_cpu_to_node_map, cpu); } -struct cpumask __cpuinit *debug_cpumask_set_cpu(int cpu, int enable) +void debug_cpumask_set_cpu(int cpu, int node, bool enable) { - int node = early_cpu_to_node(cpu); struct cpumask *mask; char buf[64]; if (node == NUMA_NO_NODE) { /* early_cpu_to_node() already emits a warning and trace */ - return NULL; + return; } mask = node_to_cpumask_map[node]; if (!mask) { pr_err("node_to_cpumask_map[%i] NULL\n", node); dump_stack(); - return NULL; + return; } + if (enable) + cpumask_set_cpu(cpu, mask); + else + cpumask_clear_cpu(cpu, mask); + cpulist_scnprintf(buf, sizeof(buf), mask); printk(KERN_DEBUG "%s cpu %d node %d: mask now %s\n", enable ? "numa_add_cpu" : "numa_remove_cpu", cpu, node, buf); - return mask; + return; } # ifndef CONFIG_NUMA_EMU -static void __cpuinit numa_set_cpumask(int cpu, int enable) +static void __cpuinit numa_set_cpumask(int cpu, bool enable) { - struct cpumask *mask; - - mask = debug_cpumask_set_cpu(cpu, enable); - if (!mask) - return; - - if (enable) - cpumask_set_cpu(cpu, mask); - else - cpumask_clear_cpu(cpu, mask); + debug_cpumask_set_cpu(cpu, early_cpu_to_node(cpu), enable); } void __cpuinit numa_add_cpu(int cpu) { - numa_set_cpumask(cpu, 1); + numa_set_cpumask(cpu, true); } void __cpuinit numa_remove_cpu(int cpu) { - numa_set_cpumask(cpu, 0); + numa_set_cpumask(cpu, false); } # endif /* !CONFIG_NUMA_EMU */ diff --git a/arch/x86/mm/numa_64.c b/arch/x86/mm/numa_64.c index e8c00cc7203..85b52fc0308 100644 --- a/arch/x86/mm/numa_64.c +++ b/arch/x86/mm/numa_64.c @@ -306,7 +306,7 @@ int __init numa_cleanup_meminfo(struct numa_meminfo *mi) bi->end = min(bi->end, high); /* and there's no empty block */ - if (bi->start == bi->end) { + if (bi->start >= bi->end) { numa_remove_memblk_from(i--, mi); continue; } diff --git a/arch/x86/mm/numa_emulation.c b/arch/x86/mm/numa_emulation.c index ad091e4cff1..de84cc14037 100644 --- a/arch/x86/mm/numa_emulation.c +++ b/arch/x86/mm/numa_emulation.c @@ -454,10 +454,9 @@ void __cpuinit numa_remove_cpu(int cpu) cpumask_clear_cpu(cpu, node_to_cpumask_map[i]); } #else /* !CONFIG_DEBUG_PER_CPU_MAPS */ -static void __cpuinit numa_set_cpumask(int cpu, int enable) +static void __cpuinit numa_set_cpumask(int cpu, bool enable) { - struct cpumask *mask; - int nid, physnid, i; + int nid, physnid; nid = early_cpu_to_node(cpu); if (nid == NUMA_NO_NODE) { @@ -467,28 +466,21 @@ static void __cpuinit numa_set_cpumask(int cpu, int enable) physnid = emu_nid_to_phys[nid]; - for_each_online_node(i) { + for_each_online_node(nid) { if (emu_nid_to_phys[nid] != physnid) continue; - mask = debug_cpumask_set_cpu(cpu, enable); - if (!mask) - return; - - if (enable) - cpumask_set_cpu(cpu, mask); - else - cpumask_clear_cpu(cpu, mask); + debug_cpumask_set_cpu(cpu, nid, enable); } } void __cpuinit numa_add_cpu(int cpu) { - numa_set_cpumask(cpu, 1); + numa_set_cpumask(cpu, true); } void __cpuinit numa_remove_cpu(int cpu) { - numa_set_cpumask(cpu, 0); + numa_set_cpumask(cpu, false); } #endif /* !CONFIG_DEBUG_PER_CPU_MAPS */ diff --git a/arch/x86/mm/srat_32.c b/arch/x86/mm/srat_32.c index 48651c6f657..364f36bdfad 100644 --- a/arch/x86/mm/srat_32.c +++ b/arch/x86/mm/srat_32.c @@ -211,10 +211,12 @@ int __init get_memcfg_from_srat(void) { int i, j, nid; - if (srat_disabled()) goto out_fail; + if (acpi_numa_init() < 0) + goto out_fail; + if (num_memory_chunks == 0) { printk(KERN_DEBUG "could not find any ACPI SRAT memory areas.\n"); diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c index e2b7b0c06cd..cf9750004a0 100644 --- a/arch/x86/oprofile/nmi_int.c +++ b/arch/x86/oprofile/nmi_int.c @@ -15,7 +15,7 @@ #include <linux/notifier.h> #include <linux/smp.h> #include <linux/oprofile.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/slab.h> #include <linux/moduleparam.h> #include <linux/kdebug.h> @@ -49,6 +49,10 @@ u64 op_x86_get_ctrl(struct op_x86_model_spec const *model, val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0; val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0; val |= (counter_config->unit_mask & 0xFF) << 8; + counter_config->extra &= (ARCH_PERFMON_EVENTSEL_INV | + ARCH_PERFMON_EVENTSEL_EDGE | + ARCH_PERFMON_EVENTSEL_CMASK); + val |= counter_config->extra; event &= model->event_mask ? model->event_mask : 0xFF; val |= event & 0xFF; val |= (event & 0x0F00) << 24; @@ -440,6 +444,7 @@ static int nmi_create_files(struct super_block *sb, struct dentry *root) oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask); oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel); oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user); + oprofilefs_create_ulong(sb, dir, "extra", &counter_config[i].extra); } return 0; @@ -536,7 +541,7 @@ static void nmi_shutdown(void) #ifdef CONFIG_PM -static int nmi_suspend(struct sys_device *dev, pm_message_t state) +static int nmi_suspend(void) { /* Only one CPU left, just stop that one */ if (nmi_enabled == 1) @@ -544,49 +549,31 @@ static int nmi_suspend(struct sys_device *dev, pm_message_t state) return 0; } -static int nmi_resume(struct sys_device *dev) +static void nmi_resume(void) { if (nmi_enabled == 1) nmi_cpu_start(NULL); - return 0; } -static struct sysdev_class oprofile_sysclass = { - .name = "oprofile", +static struct syscore_ops oprofile_syscore_ops = { .resume = nmi_resume, .suspend = nmi_suspend, }; -static struct sys_device device_oprofile = { - .id = 0, - .cls = &oprofile_sysclass, -}; - -static int __init init_sysfs(void) +static void __init init_suspend_resume(void) { - int error; - - error = sysdev_class_register(&oprofile_sysclass); - if (error) - return error; - - error = sysdev_register(&device_oprofile); - if (error) - sysdev_class_unregister(&oprofile_sysclass); - - return error; + register_syscore_ops(&oprofile_syscore_ops); } -static void exit_sysfs(void) +static void exit_suspend_resume(void) { - sysdev_unregister(&device_oprofile); - sysdev_class_unregister(&oprofile_sysclass); + unregister_syscore_ops(&oprofile_syscore_ops); } #else -static inline int init_sysfs(void) { return 0; } -static inline void exit_sysfs(void) { } +static inline void init_suspend_resume(void) { } +static inline void exit_suspend_resume(void) { } #endif /* CONFIG_PM */ @@ -789,9 +776,7 @@ int __init op_nmi_init(struct oprofile_operations *ops) mux_init(ops); - ret = init_sysfs(); - if (ret) - return ret; + init_suspend_resume(); printk(KERN_INFO "oprofile: using NMI interrupt.\n"); return 0; @@ -799,5 +784,5 @@ int __init op_nmi_init(struct oprofile_operations *ops) void op_nmi_exit(void) { - exit_sysfs(); + exit_suspend_resume(); } diff --git a/arch/x86/oprofile/op_counter.h b/arch/x86/oprofile/op_counter.h index e28398df0df..0b7b7b179cb 100644 --- a/arch/x86/oprofile/op_counter.h +++ b/arch/x86/oprofile/op_counter.h @@ -22,6 +22,7 @@ struct op_counter_config { unsigned long kernel; unsigned long user; unsigned long unit_mask; + unsigned long extra; }; extern struct op_counter_config counter_config[]; diff --git a/arch/x86/platform/ce4100/falconfalls.dts b/arch/x86/platform/ce4100/falconfalls.dts index dc701ea5854..e70be38ce03 100644 --- a/arch/x86/platform/ce4100/falconfalls.dts +++ b/arch/x86/platform/ce4100/falconfalls.dts @@ -74,6 +74,7 @@ compatible = "intel,ce4100-pci", "pci"; device_type = "pci"; bus-range = <1 1>; + reg = <0x0800 0x0 0x0 0x0 0x0>; ranges = <0x2000000 0 0xdffe0000 0x2000000 0 0xdffe0000 0 0x1000>; interrupt-parent = <&ioapic2>; @@ -346,7 +347,7 @@ "pciclass0c03"; reg = <0x16800 0x0 0x0 0x0 0x0>; - interrupts = <22 3>; + interrupts = <22 1>; }; usb@d,1 { @@ -356,7 +357,7 @@ "pciclass0c03"; reg = <0x16900 0x0 0x0 0x0 0x0>; - interrupts = <22 3>; + interrupts = <22 1>; }; sata@e,0 { @@ -366,7 +367,7 @@ "pciclass0106"; reg = <0x17000 0x0 0x0 0x0 0x0>; - interrupts = <23 3>; + interrupts = <23 1>; }; flash@f,0 { @@ -412,6 +413,7 @@ #address-cells = <2>; #size-cells = <1>; compatible = "isa"; + reg = <0xf800 0x0 0x0 0x0 0x0>; ranges = <1 0 0 0 0 0x100>; rtc@70 { diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c index 5c0207bf959..275dbc19e2c 100644 --- a/arch/x86/platform/mrst/mrst.c +++ b/arch/x86/platform/mrst/mrst.c @@ -97,11 +97,11 @@ static int __init sfi_parse_mtmr(struct sfi_table_header *table) pentry->freq_hz, pentry->irq); if (!pentry->irq) continue; - mp_irq.type = MP_IOAPIC; + mp_irq.type = MP_INTSRC; mp_irq.irqtype = mp_INT; /* triggering mode edge bit 2-3, active high polarity bit 0-1 */ mp_irq.irqflag = 5; - mp_irq.srcbus = 0; + mp_irq.srcbus = MP_BUS_ISA; mp_irq.srcbusirq = pentry->irq; /* IRQ */ mp_irq.dstapic = MP_APIC_ALL; mp_irq.dstirq = pentry->irq; @@ -168,10 +168,10 @@ int __init sfi_parse_mrtc(struct sfi_table_header *table) for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) { pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n", totallen, (u32)pentry->phys_addr, pentry->irq); - mp_irq.type = MP_IOAPIC; + mp_irq.type = MP_INTSRC; mp_irq.irqtype = mp_INT; mp_irq.irqflag = 0xf; /* level trigger and active low */ - mp_irq.srcbus = 0; + mp_irq.srcbus = MP_BUS_ISA; mp_irq.srcbusirq = pentry->irq; /* IRQ */ mp_irq.dstapic = MP_APIC_ALL; mp_irq.dstirq = pentry->irq; @@ -282,7 +282,7 @@ void __init x86_mrst_early_setup(void) /* Avoid searching for BIOS MP tables */ x86_init.mpparse.find_smp_config = x86_init_noop; x86_init.mpparse.get_smp_config = x86_init_uint_noop; - + set_bit(MP_BUS_ISA, mp_bus_not_pci); } /* diff --git a/arch/x86/platform/mrst/vrtc.c b/arch/x86/platform/mrst/vrtc.c index 04cf645feb9..73d70d65e76 100644 --- a/arch/x86/platform/mrst/vrtc.c +++ b/arch/x86/platform/mrst/vrtc.c @@ -100,9 +100,11 @@ int vrtc_set_mmss(unsigned long nowtime) void __init mrst_rtc_init(void) { - unsigned long vrtc_paddr = sfi_mrtc_array[0].phys_addr; + unsigned long vrtc_paddr; sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc); + + vrtc_paddr = sfi_mrtc_array[0].phys_addr; if (!sfi_mrtc_num || !vrtc_paddr) return; diff --git a/arch/x86/platform/olpc/olpc-xo1.c b/arch/x86/platform/olpc/olpc-xo1.c index 127775696d6..ab81fb27176 100644 --- a/arch/x86/platform/olpc/olpc-xo1.c +++ b/arch/x86/platform/olpc/olpc-xo1.c @@ -15,6 +15,7 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm.h> +#include <linux/mfd/core.h> #include <asm/io.h> #include <asm/olpc.h> @@ -56,25 +57,24 @@ static void xo1_power_off(void) static int __devinit olpc_xo1_probe(struct platform_device *pdev) { struct resource *res; + int err; /* don't run on non-XOs */ if (!machine_is_olpc()) return -ENODEV; + err = mfd_cell_enable(pdev); + if (err) + return err; + res = platform_get_resource(pdev, IORESOURCE_IO, 0); if (!res) { dev_err(&pdev->dev, "can't fetch device resource info\n"); return -EIO; } - - if (!request_region(res->start, resource_size(res), DRV_NAME)) { - dev_err(&pdev->dev, "can't request region\n"); - return -EIO; - } - if (strcmp(pdev->name, "cs5535-pms") == 0) pms_base = res->start; - else if (strcmp(pdev->name, "cs5535-acpi") == 0) + else if (strcmp(pdev->name, "olpc-xo1-pm-acpi") == 0) acpi_base = res->start; /* If we have both addresses, we can override the poweroff hook */ @@ -88,14 +88,11 @@ static int __devinit olpc_xo1_probe(struct platform_device *pdev) static int __devexit olpc_xo1_remove(struct platform_device *pdev) { - struct resource *r; - - r = platform_get_resource(pdev, IORESOURCE_IO, 0); - release_region(r->start, resource_size(r)); + mfd_cell_disable(pdev); if (strcmp(pdev->name, "cs5535-pms") == 0) pms_base = 0; - else if (strcmp(pdev->name, "cs5535-acpi") == 0) + else if (strcmp(pdev->name, "olpc-xo1-pm-acpi") == 0) acpi_base = 0; pm_power_off = NULL; @@ -113,7 +110,7 @@ static struct platform_driver cs5535_pms_drv = { static struct platform_driver cs5535_acpi_drv = { .driver = { - .name = "cs5535-acpi", + .name = "olpc-xo1-pm-acpi", .owner = THIS_MODULE, }, .probe = olpc_xo1_probe, @@ -143,7 +140,7 @@ static void __exit olpc_xo1_exit(void) MODULE_AUTHOR("Daniel Drake <dsd@laptop.org>"); MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:olpc-xo1"); +MODULE_ALIAS("platform:cs5535-pms"); module_init(olpc_xo1_init); module_exit(olpc_xo1_exit); diff --git a/arch/x86/platform/uv/tlb_uv.c b/arch/x86/platform/uv/tlb_uv.c index a7b38d35c29..7cb6424317f 100644 --- a/arch/x86/platform/uv/tlb_uv.c +++ b/arch/x86/platform/uv/tlb_uv.c @@ -11,6 +11,7 @@ #include <linux/debugfs.h> #include <linux/kernel.h> #include <linux/slab.h> +#include <linux/delay.h> #include <asm/mmu_context.h> #include <asm/uv/uv.h> diff --git a/arch/x86/platform/visws/visws_quirks.c b/arch/x86/platform/visws/visws_quirks.c index fe4cf829487..c7abf13a213 100644 --- a/arch/x86/platform/visws/visws_quirks.c +++ b/arch/x86/platform/visws/visws_quirks.c @@ -471,15 +471,7 @@ static unsigned int startup_piix4_master_irq(struct irq_data *data) { legacy_pic->init(0); enable_cobalt_irq(data); -} - -static void end_piix4_master_irq(struct irq_data *data) -{ - unsigned long flags; - - spin_lock_irqsave(&cobalt_lock, flags); - enable_cobalt_irq(data); - spin_unlock_irqrestore(&cobalt_lock, flags); + return 0; } static struct irq_chip piix4_master_irq_type = { @@ -492,7 +484,7 @@ static void pii4_mask(struct irq_data *data) { } static struct irq_chip piix4_virtual_irq_type = { .name = "PIIX4-virtual", - .mask = pii4_mask, + .irq_mask = pii4_mask, }; /* @@ -580,9 +572,9 @@ static struct irqaction cascade_action = { static inline void set_piix4_virtual_irq_type(void) { - piix4_virtual_irq_type.enable = i8259A_chip.unmask; - piix4_virtual_irq_type.disable = i8259A_chip.mask; - piix4_virtual_irq_type.unmask = i8259A_chip.unmask; + piix4_virtual_irq_type.irq_enable = i8259A_chip.irq_unmask; + piix4_virtual_irq_type.irq_disable = i8259A_chip.irq_mask; + piix4_virtual_irq_type.irq_unmask = i8259A_chip.irq_unmask; } static void __init visws_pre_intr_init(void) @@ -599,7 +591,7 @@ static void __init visws_pre_intr_init(void) else if (i == CO_IRQ_IDE0) chip = &cobalt_irq_type; else if (i == CO_IRQ_IDE1) - >chip = &cobalt_irq_type; + chip = &cobalt_irq_type; else if (i == CO_IRQ_8259) chip = &piix4_master_irq_type; else if (i < CO_IRQ_APIC0) diff --git a/arch/x86/vdso/vdso32-setup.c b/arch/x86/vdso/vdso32-setup.c index 36df991985b..468d591dde3 100644 --- a/arch/x86/vdso/vdso32-setup.c +++ b/arch/x86/vdso/vdso32-setup.c @@ -417,24 +417,25 @@ const char *arch_vma_name(struct vm_area_struct *vma) return NULL; } -struct vm_area_struct *get_gate_vma(struct task_struct *tsk) +struct vm_area_struct *get_gate_vma(struct mm_struct *mm) { - struct mm_struct *mm = tsk->mm; - - /* Check to see if this task was created in compat vdso mode */ + /* + * Check to see if the corresponding task was created in compat vdso + * mode. + */ if (mm && mm->context.vdso == (void *)VDSO_HIGH_BASE) return &gate_vma; return NULL; } -int in_gate_area(struct task_struct *task, unsigned long addr) +int in_gate_area(struct mm_struct *mm, unsigned long addr) { - const struct vm_area_struct *vma = get_gate_vma(task); + const struct vm_area_struct *vma = get_gate_vma(mm); return vma && addr >= vma->vm_start && addr < vma->vm_end; } -int in_gate_area_no_task(unsigned long addr) +int in_gate_area_no_mm(unsigned long addr) { return 0; } diff --git a/arch/x86/xen/Kconfig b/arch/x86/xen/Kconfig index 1c7121ba18f..5cc821cb2e0 100644 --- a/arch/x86/xen/Kconfig +++ b/arch/x86/xen/Kconfig @@ -39,6 +39,7 @@ config XEN_MAX_DOMAIN_MEMORY config XEN_SAVE_RESTORE bool depends on XEN + select HIBERNATE_CALLBACKS default y config XEN_DEBUG_FS diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index 49dbd78ec3c..e3c6a06cf72 100644 --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c @@ -238,6 +238,7 @@ static void xen_cpuid(unsigned int *ax, unsigned int *bx, static __init void xen_init_cpuid_mask(void) { unsigned int ax, bx, cx, dx; + unsigned int xsave_mask; cpuid_leaf1_edx_mask = ~((1 << X86_FEATURE_MCE) | /* disable MCE */ @@ -249,24 +250,16 @@ static __init void xen_init_cpuid_mask(void) cpuid_leaf1_edx_mask &= ~((1 << X86_FEATURE_APIC) | /* disable local APIC */ (1 << X86_FEATURE_ACPI)); /* disable ACPI */ - ax = 1; - cx = 0; xen_cpuid(&ax, &bx, &cx, &dx); - /* cpuid claims we support xsave; try enabling it to see what happens */ - if (cx & (1 << (X86_FEATURE_XSAVE % 32))) { - unsigned long cr4; - - set_in_cr4(X86_CR4_OSXSAVE); - - cr4 = read_cr4(); + xsave_mask = + (1 << (X86_FEATURE_XSAVE % 32)) | + (1 << (X86_FEATURE_OSXSAVE % 32)); - if ((cr4 & X86_CR4_OSXSAVE) == 0) - cpuid_leaf1_ecx_mask &= ~(1 << (X86_FEATURE_XSAVE % 32)); - - clear_in_cr4(X86_CR4_OSXSAVE); - } + /* Xen will set CR4.OSXSAVE if supported and not disabled by force */ + if ((cx & xsave_mask) != xsave_mask) + cpuid_leaf1_ecx_mask &= ~xsave_mask; /* disable XSAVE & OSXSAVE */ } static void xen_set_debugreg(int reg, unsigned long val) diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c index 39ee7182fd1..0684f3c74d5 100644 --- a/arch/x86/xen/mmu.c +++ b/arch/x86/xen/mmu.c @@ -565,13 +565,13 @@ pte_t xen_make_pte_debug(pteval_t pte) if (io_page && (xen_initial_domain() || addr >= ISA_END_ADDRESS)) { other_addr = pfn_to_mfn(addr >> PAGE_SHIFT) << PAGE_SHIFT; - WARN(addr != other_addr, + WARN_ONCE(addr != other_addr, "0x%lx is using VM_IO, but it is 0x%lx!\n", (unsigned long)addr, (unsigned long)other_addr); } else { pteval_t iomap_set = (_pte.pte & PTE_FLAGS_MASK) & _PAGE_IOMAP; other_addr = (_pte.pte & PTE_PFN_MASK); - WARN((addr == other_addr) && (!io_page) && (!iomap_set), + WARN_ONCE((addr == other_addr) && (!io_page) && (!iomap_set), "0x%lx is missing VM_IO (and wasn't fixed)!\n", (unsigned long)addr); } @@ -1275,6 +1275,20 @@ static __init void xen_pagetable_setup_start(pgd_t *base) { } +static __init void xen_mapping_pagetable_reserve(u64 start, u64 end) +{ + /* reserve the range used */ + native_pagetable_reserve(start, end); + + /* set as RW the rest */ + printk(KERN_DEBUG "xen: setting RW the range %llx - %llx\n", end, + PFN_PHYS(pgt_buf_top)); + while (end < PFN_PHYS(pgt_buf_top)) { + make_lowmem_page_readwrite(__va(end)); + end += PAGE_SIZE; + } +} + static void xen_post_allocator_init(void); static __init void xen_pagetable_setup_done(pgd_t *base) @@ -1473,28 +1487,35 @@ static void xen_pgd_free(struct mm_struct *mm, pgd_t *pgd) #endif } +#ifdef CONFIG_X86_32 static __init pte_t mask_rw_pte(pte_t *ptep, pte_t pte) { - unsigned long pfn = pte_pfn(pte); - -#ifdef CONFIG_X86_32 /* If there's an existing pte, then don't allow _PAGE_RW to be set */ if (pte_val_ma(*ptep) & _PAGE_PRESENT) pte = __pte_ma(((pte_val_ma(*ptep) & _PAGE_RW) | ~_PAGE_RW) & pte_val_ma(pte)); -#endif + + return pte; +} +#else /* CONFIG_X86_64 */ +static __init pte_t mask_rw_pte(pte_t *ptep, pte_t pte) +{ + unsigned long pfn = pte_pfn(pte); /* * If the new pfn is within the range of the newly allocated * kernel pagetable, and it isn't being mapped into an - * early_ioremap fixmap slot, make sure it is RO. + * early_ioremap fixmap slot as a freshly allocated page, make sure + * it is RO. */ - if (!is_early_ioremap_ptep(ptep) && - pfn >= pgt_buf_start && pfn < pgt_buf_end) + if (((!is_early_ioremap_ptep(ptep) && + pfn >= pgt_buf_start && pfn < pgt_buf_top)) || + (is_early_ioremap_ptep(ptep) && pfn != (pgt_buf_end - 1))) pte = pte_wrprotect(pte); return pte; } +#endif /* CONFIG_X86_64 */ /* Init-time set_pte while constructing initial pagetables, which doesn't allow RO pagetable pages to be remapped RW */ @@ -1700,9 +1721,6 @@ static __init void xen_map_identity_early(pmd_t *pmd, unsigned long max_pfn) for (pteidx = 0; pteidx < PTRS_PER_PTE; pteidx++, pfn++) { pte_t pte; - if (pfn > max_pfn_mapped) - max_pfn_mapped = pfn; - if (!pte_none(pte_page[pteidx])) continue; @@ -1760,6 +1778,12 @@ __init pgd_t *xen_setup_kernel_pagetable(pgd_t *pgd, pud_t *l3; pmd_t *l2; + /* max_pfn_mapped is the last pfn mapped in the initial memory + * mappings. Considering that on Xen after the kernel mappings we + * have the mappings of some pages that don't exist in pfn space, we + * set max_pfn_mapped to the last real pfn mapped. */ + max_pfn_mapped = PFN_DOWN(__pa(xen_start_info->mfn_list)); + /* Zap identity mapping */ init_level4_pgt[0] = __pgd(0); @@ -1864,9 +1888,7 @@ __init pgd_t *xen_setup_kernel_pagetable(pgd_t *pgd, initial_kernel_pmd = extend_brk(sizeof(pmd_t) * PTRS_PER_PMD, PAGE_SIZE); - max_pfn_mapped = PFN_DOWN(__pa(xen_start_info->pt_base) + - xen_start_info->nr_pt_frames * PAGE_SIZE + - 512*1024); + max_pfn_mapped = PFN_DOWN(__pa(xen_start_info->mfn_list)); kernel_pmd = m2v(pgd[KERNEL_PGD_BOUNDARY].pgd); memcpy(initial_kernel_pmd, kernel_pmd, sizeof(pmd_t) * PTRS_PER_PMD); @@ -2097,6 +2119,7 @@ static const struct pv_mmu_ops xen_mmu_ops __initdata = { void __init xen_init_mmu_ops(void) { + x86_init.mapping.pagetable_reserve = xen_mapping_pagetable_reserve; x86_init.paging.pagetable_setup_start = xen_pagetable_setup_start; x86_init.paging.pagetable_setup_done = xen_pagetable_setup_done; pv_mmu_ops = xen_mmu_ops; diff --git a/arch/x86/xen/p2m.c b/arch/x86/xen/p2m.c index 215a3ce6106..141eb0de8b0 100644 --- a/arch/x86/xen/p2m.c +++ b/arch/x86/xen/p2m.c @@ -497,7 +497,7 @@ static bool alloc_p2m(unsigned long pfn) return true; } -bool __early_alloc_p2m(unsigned long pfn) +static bool __init __early_alloc_p2m(unsigned long pfn) { unsigned topidx, mididx, idx; @@ -530,7 +530,7 @@ bool __early_alloc_p2m(unsigned long pfn) } return idx != 0; } -unsigned long set_phys_range_identity(unsigned long pfn_s, +unsigned long __init set_phys_range_identity(unsigned long pfn_s, unsigned long pfn_e) { unsigned long pfn; @@ -671,7 +671,9 @@ int m2p_add_override(unsigned long mfn, struct page *page) page->private = mfn; page->index = pfn_to_mfn(pfn); - __set_phys_to_machine(pfn, FOREIGN_FRAME(mfn)); + if (unlikely(!set_phys_to_machine(pfn, FOREIGN_FRAME(mfn)))) + return -ENOMEM; + if (!PageHighMem(page)) /* Just zap old mapping for now */ pte_clear(&init_mm, address, ptep); @@ -709,7 +711,7 @@ int m2p_remove_override(struct page *page) spin_lock_irqsave(&m2p_override_lock, flags); list_del(&page->lru); spin_unlock_irqrestore(&m2p_override_lock, flags); - __set_phys_to_machine(pfn, page->index); + set_phys_to_machine(pfn, page->index); if (!PageHighMem(page)) set_pte_at(&init_mm, address, ptep, diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c index fa0269a9937..90bac0aac3a 100644 --- a/arch/x86/xen/setup.c +++ b/arch/x86/xen/setup.c @@ -227,7 +227,7 @@ char * __init xen_memory_setup(void) memcpy(map_raw, map, sizeof(map)); e820.nr_map = 0; - xen_extra_mem_start = mem_end; + xen_extra_mem_start = max((1ULL << 32), mem_end); for (i = 0; i < memmap.nr_entries; i++) { unsigned long long end; diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index d373d159e75..7c275f5d0df 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -7,6 +7,8 @@ config ZONE_DMA config XTENSA def_bool y select HAVE_IDE + select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_SHOW help Xtensa processors are 32-bit RISC machines designed by Tensilica primarily for embedded systems. These processors are both @@ -21,10 +23,10 @@ config RWSEM_XCHGADD_ALGORITHM config GENERIC_FIND_NEXT_BIT def_bool y -config GENERIC_HWEIGHT +config GENERIC_FIND_BIT_LE def_bool y -config GENERIC_HARDIRQS +config GENERIC_HWEIGHT def_bool y config GENERIC_GPIO diff --git a/arch/xtensa/boot/Makefile b/arch/xtensa/boot/Makefile index 40aa55b485b..70fd1453e17 100644 --- a/arch/xtensa/boot/Makefile +++ b/arch/xtensa/boot/Makefile @@ -14,7 +14,7 @@ HOSTFLAGS += -Iarch/$(ARCH)/boot/include BIG_ENDIAN := $(shell echo -e __XTENSA_EB__ | $(CC) -E - | grep -v "\#") -export EXTRA_CFLAGS +export ccflags-y export BIG_ENDIAN subdir-y := lib diff --git a/arch/xtensa/boot/lib/Makefile b/arch/xtensa/boot/lib/Makefile index d3d2aa2d883..ad8952e8a07 100644 --- a/arch/xtensa/boot/lib/Makefile +++ b/arch/xtensa/boot/lib/Makefile @@ -6,7 +6,7 @@ zlib := inffast.c inflate.c inftrees.c lib-y += $(zlib:.c=.o) zmem.o -EXTRA_CFLAGS += -Ilib/zlib_inflate +ccflags-y := -Ilib/zlib_inflate quiet_cmd_copy_zlib = COPY $@ cmd_copy_zlib = cat $< > $@ diff --git a/arch/xtensa/include/asm/bitops.h b/arch/xtensa/include/asm/bitops.h index 6c3930397bd..c8fac8d8190 100644 --- a/arch/xtensa/include/asm/bitops.h +++ b/arch/xtensa/include/asm/bitops.h @@ -106,7 +106,7 @@ static inline unsigned long __fls(unsigned long word) #include <asm-generic/bitops/fls64.h> #include <asm-generic/bitops/find.h> -#include <asm-generic/bitops/ext2-non-atomic.h> +#include <asm-generic/bitops/le.h> #ifdef __XTENSA_EL__ # define ext2_set_bit_atomic(lock,nr,addr) \ @@ -125,7 +125,6 @@ static inline unsigned long __fls(unsigned long word) #include <asm-generic/bitops/hweight.h> #include <asm-generic/bitops/lock.h> #include <asm-generic/bitops/sched.h> -#include <asm-generic/bitops/minix.h> #endif /* __KERNEL__ */ diff --git a/arch/xtensa/include/asm/dma.h b/arch/xtensa/include/asm/dma.h index 137ca3945b0..bb099a373b5 100644 --- a/arch/xtensa/include/asm/dma.h +++ b/arch/xtensa/include/asm/dma.h @@ -37,7 +37,7 @@ * the size of the statically mapped kernel segment * (XCHAL_KSEG_{CACHED,BYPASS}_SIZE), ie. 128 MB. * - * NOTE: When the entire KSEG area is DMA capable, we substract + * NOTE: When the entire KSEG area is DMA capable, we subtract * one from the max address so that the virt_to_phys() macro * works correctly on the address (otherwise the address * enters another area, and virt_to_phys() may not return diff --git a/arch/xtensa/include/asm/types.h b/arch/xtensa/include/asm/types.h index c89569a8da0..b1c981e39b5 100644 --- a/arch/xtensa/include/asm/types.h +++ b/arch/xtensa/include/asm/types.h @@ -32,10 +32,6 @@ typedef unsigned short umode_t; #define BITS_PER_LONG 32 -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - #endif /* __KERNEL__ */ #endif diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S index 5fd01f6aaf3..6223f3346b5 100644 --- a/arch/xtensa/kernel/entry.S +++ b/arch/xtensa/kernel/entry.S @@ -1026,7 +1026,7 @@ ENTRY(fast_syscall_unrecoverable) * TRY adds an entry to the __ex_table fixup table for the immediately * following instruction. * - * CATCH catches any exception that occurred at one of the preceeding TRY + * CATCH catches any exception that occurred at one of the preceding TRY * statements and continues from there * * Usage TRY l32i a0, a1, 0 diff --git a/arch/xtensa/kernel/irq.c b/arch/xtensa/kernel/irq.c index 87508886cbb..4340ee076bd 100644 --- a/arch/xtensa/kernel/irq.c +++ b/arch/xtensa/kernel/irq.c @@ -35,7 +35,6 @@ atomic_t irq_err_count; asmlinkage void do_IRQ(int irq, struct pt_regs *regs) { struct pt_regs *old_regs = set_irq_regs(regs); - struct irq_desc *desc = irq_desc + irq; if (irq >= NR_IRQS) { printk(KERN_EMERG "%s: cannot handle IRQ %d\n", @@ -57,104 +56,63 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs) sp - sizeof(struct thread_info)); } #endif - desc->handle_irq(irq, desc); + generic_handle_irq(irq); irq_exit(); set_irq_regs(old_regs); } -/* - * Generic, controller-independent functions: - */ - -int show_interrupts(struct seq_file *p, void *v) +int arch_show_interrupts(struct seq_file *p, int prec) { - int i = *(loff_t *) v, j; - struct irqaction * action; - unsigned long flags; - - if (i == 0) { - seq_printf(p, " "); - for_each_online_cpu(j) - seq_printf(p, "CPU%d ",j); - seq_putc(p, '\n'); - } - - if (i < NR_IRQS) { - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); - action = irq_desc[i].action; - if (!action) - goto skip; - seq_printf(p, "%3d: ",i); -#ifndef CONFIG_SMP - seq_printf(p, "%10u ", kstat_irqs(i)); -#else - for_each_online_cpu(j) - seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); -#endif - seq_printf(p, " %14s", irq_desc[i].chip->name); - seq_printf(p, " %s", action->name); - - for (action=action->next; action; action = action->next) - seq_printf(p, ", %s", action->name); - - seq_putc(p, '\n'); -skip: - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); - } else if (i == NR_IRQS) { - seq_printf(p, "NMI: "); - for_each_online_cpu(j) - seq_printf(p, "%10u ", nmi_count(j)); - seq_putc(p, '\n'); - seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count)); - } + seq_printf(p, "%*s: ", prec, "ERR"); + seq_printf(p, "%10u\n", atomic_read(&irq_err_count)); return 0; } -static void xtensa_irq_mask(unsigned int irq) +static void xtensa_irq_mask(struct irq_data *d) { - cached_irq_mask &= ~(1 << irq); + cached_irq_mask &= ~(1 << d->irq); set_sr (cached_irq_mask, INTENABLE); } -static void xtensa_irq_unmask(unsigned int irq) +static void xtensa_irq_unmask(struct irq_data *d) { - cached_irq_mask |= 1 << irq; + cached_irq_mask |= 1 << d->irq; set_sr (cached_irq_mask, INTENABLE); } -static void xtensa_irq_enable(unsigned int irq) +static void xtensa_irq_enable(struct irq_data *d) { - variant_irq_enable(irq); - xtensa_irq_unmask(irq); + variant_irq_enable(d->irq); + xtensa_irq_unmask(d->irq); } -static void xtensa_irq_disable(unsigned int irq) +static void xtensa_irq_disable(struct irq_data *d) { - xtensa_irq_mask(irq); - variant_irq_disable(irq); + xtensa_irq_mask(d->irq); + variant_irq_disable(d->irq); } -static void xtensa_irq_ack(unsigned int irq) +static void xtensa_irq_ack(struct irq_data *d) { - set_sr(1 << irq, INTCLEAR); + set_sr(1 << d->irq, INTCLEAR); } -static int xtensa_irq_retrigger(unsigned int irq) +static int xtensa_irq_retrigger(struct irq_data *d) { - set_sr (1 << irq, INTSET); + set_sr (1 << d->irq, INTSET); return 1; } static struct irq_chip xtensa_irq_chip = { .name = "xtensa", - .enable = xtensa_irq_enable, - .disable = xtensa_irq_disable, - .mask = xtensa_irq_mask, - .unmask = xtensa_irq_unmask, - .ack = xtensa_irq_ack, - .retrigger = xtensa_irq_retrigger, + .irq_enable = xtensa_irq_enable, + .irq_disable = xtensa_irq_disable, + .irq_mask = xtensa_irq_mask, + .irq_unmask = xtensa_irq_unmask, + .irq_ack = xtensa_irq_ack, + .irq_retrigger = xtensa_irq_retrigger, }; void __init init_IRQ(void) @@ -165,25 +123,25 @@ void __init init_IRQ(void) int mask = 1 << index; if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) - set_irq_chip_and_handler(index, &xtensa_irq_chip, + irq_set_chip_and_handler(index, &xtensa_irq_chip, handle_simple_irq); else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) - set_irq_chip_and_handler(index, &xtensa_irq_chip, + irq_set_chip_and_handler(index, &xtensa_irq_chip, handle_edge_irq); else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) - set_irq_chip_and_handler(index, &xtensa_irq_chip, + irq_set_chip_and_handler(index, &xtensa_irq_chip, handle_level_irq); else if (mask & XCHAL_INTTYPE_MASK_TIMER) - set_irq_chip_and_handler(index, &xtensa_irq_chip, + irq_set_chip_and_handler(index, &xtensa_irq_chip, handle_edge_irq); else /* XCHAL_INTTYPE_MASK_WRITE_ERROR */ /* XCHAL_INTTYPE_MASK_NMI */ - set_irq_chip_and_handler(index, &xtensa_irq_chip, + irq_set_chip_and_handler(index, &xtensa_irq_chip, handle_level_irq); } diff --git a/arch/xtensa/platforms/s6105/device.c b/arch/xtensa/platforms/s6105/device.c index 65333ffefb0..4f4fc971042 100644 --- a/arch/xtensa/platforms/s6105/device.c +++ b/arch/xtensa/platforms/s6105/device.c @@ -120,7 +120,7 @@ static int __init prepare_phy_irq(int pin) irq = gpio_to_irq(pin); if (irq < 0) goto free; - if (set_irq_type(irq, IRQ_TYPE_LEVEL_LOW) < 0) + if (irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW) < 0) goto free; return irq; free: diff --git a/arch/xtensa/variants/s6000/gpio.c b/arch/xtensa/variants/s6000/gpio.c index 380a70fff75..7af0757e001 100644 --- a/arch/xtensa/variants/s6000/gpio.c +++ b/arch/xtensa/variants/s6000/gpio.c @@ -85,30 +85,29 @@ int s6_gpio_init(u32 afsel) return gpiochip_add(&gpiochip); } -static void ack(unsigned int irq) +static void ack(struct irq_data *d) { - writeb(1 << (irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC); + writeb(1 << (d->irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC); } -static void mask(unsigned int irq) +static void mask(struct irq_data *d) { u8 r = readb(S6_REG_GPIO + S6_GPIO_IE); - r &= ~(1 << (irq - IRQ_BASE)); + r &= ~(1 << (d->irq - IRQ_BASE)); writeb(r, S6_REG_GPIO + S6_GPIO_IE); } -static void unmask(unsigned int irq) +static void unmask(struct irq_data *d) { u8 m = readb(S6_REG_GPIO + S6_GPIO_IE); - m |= 1 << (irq - IRQ_BASE); + m |= 1 << (d->irq - IRQ_BASE); writeb(m, S6_REG_GPIO + S6_GPIO_IE); } -static int set_type(unsigned int irq, unsigned int type) +static int set_type(struct irq_data *d, unsigned int type) { - const u8 m = 1 << (irq - IRQ_BASE); + const u8 m = 1 << (d->irq - IRQ_BASE); irq_flow_handler_t handler; - struct irq_desc *desc; u8 reg; if (type == IRQ_TYPE_PROBE) { @@ -129,8 +128,7 @@ static int set_type(unsigned int irq, unsigned int type) handler = handle_edge_irq; } writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS); - desc = irq_to_desc(irq); - desc->handle_irq = handler; + __irq_set_handler_locked(irq, handler); reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV); if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)) @@ -150,22 +148,23 @@ static int set_type(unsigned int irq, unsigned int type) static struct irq_chip gpioirqs = { .name = "GPIO", - .ack = ack, - .mask = mask, - .unmask = unmask, - .set_type = set_type, + .irq_ack = ack, + .irq_mask = mask, + .irq_unmask = unmask, + .irq_set_type = set_type, }; static u8 demux_masks[4]; static void demux_irqs(unsigned int irq, struct irq_desc *desc) { - u8 *mask = get_irq_desc_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + u8 *mask = irq_desc_get_handler_data(desc); u8 pending; int cirq; - desc->chip->mask(irq); - desc->chip->ack(irq); + chip->irq_mask(&desc->irq_data); + chip->irq_ack(&desc->irq_data)); pending = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_MIS) & *mask; cirq = IRQ_BASE - 1; while (pending) { @@ -174,7 +173,7 @@ static void demux_irqs(unsigned int irq, struct irq_desc *desc) pending >>= n; generic_handle_irq(cirq); } - desc->chip->unmask(irq); + chip->irq_unmask(&desc->irq_data)); } extern const signed char *platform_irq_mappings[XTENSA_NR_IRQS]; @@ -219,11 +218,11 @@ void __init variant_init_irq(void) i = ffs(mask); cirq += i; mask >>= i; - set_irq_chip(cirq, &gpioirqs); - set_irq_type(irq, IRQ_TYPE_LEVEL_LOW); + irq_set_chip(cirq, &gpioirqs); + irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW); } while (mask); - set_irq_data(irq, demux_masks + n); - set_irq_chained_handler(irq, demux_irqs); + irq_set_handler_data(irq, demux_masks + n); + irq_set_chained_handler(irq, demux_irqs); if (++n == ARRAY_SIZE(demux_masks)) break; } |