diff options
Diffstat (limited to 'arch')
66 files changed, 1370 insertions, 920 deletions
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts index aeb1a7578fa..305635bd45c 100644 --- a/arch/arm/boot/dts/highbank.dts +++ b/arch/arm/boot/dts/highbank.dts @@ -194,5 +194,17 @@ reg = <0xfff3d000 0x1000>; interrupts = <0 92 4>; }; + + ethernet@fff50000 { + compatible = "calxeda,hb-xgmac"; + reg = <0xfff50000 0x1000>; + interrupts = <0 77 4 0 78 4 0 79 4>; + }; + + ethernet@fff51000 { + compatible = "calxeda,hb-xgmac"; + reg = <0xfff51000 0x1000>; + interrupts = <0 80 4 0 81 4 0 82 4>; + }; }; }; diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig index 945a34f2a34..dde2a1af7b3 100644 --- a/arch/arm/configs/omap1_defconfig +++ b/arch/arm/configs/omap1_defconfig @@ -48,7 +48,6 @@ CONFIG_MACH_SX1=y CONFIG_MACH_NOKIA770=y CONFIG_MACH_AMS_DELTA=y CONFIG_MACH_OMAP_GENERIC=y -CONFIG_OMAP_ARM_182MHZ=y # CONFIG_ARM_THUMB is not set CONFIG_PCCARD=y CONFIG_OMAP_CF=y diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 00861139101..008772e3b84 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -31,19 +31,12 @@ static LIST_HEAD(clocks); static DEFINE_MUTEX(clocks_mutex); static DEFINE_SPINLOCK(clockfw_lock); -static unsigned psc_domain(struct clk *clk) -{ - return (clk->flags & PSC_DSP) - ? DAVINCI_GPSC_DSPDOMAIN - : DAVINCI_GPSC_ARMDOMAIN; -} - static void __clk_enable(struct clk *clk) { if (clk->parent) __clk_enable(clk->parent); if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) - davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, + davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, true, clk->flags); } @@ -53,7 +46,7 @@ static void __clk_disable(struct clk *clk) return; if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) && (clk->flags & CLK_PSC)) - davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, + davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, false, clk->flags); if (clk->parent) __clk_disable(clk->parent); @@ -237,7 +230,7 @@ static int __init clk_disable_unused(void) pr_debug("Clocks: disable unused %s\n", ck->name); - davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, + davinci_psc_config(ck->domain, ck->gpsc, ck->lpsc, false, ck->flags); } spin_unlock_irq(&clockfw_lock); diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index a705f367a84..46f0f1bf1a4 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -93,6 +93,7 @@ struct clk { u8 usecount; u8 lpsc; u8 gpsc; + u8 domain; u32 flags; struct clk *parent; struct list_head children; /* list of children */ @@ -107,11 +108,10 @@ struct clk { /* Clock flags: SoC-specific flags start at BIT(16) */ #define ALWAYS_ENABLED BIT(1) #define CLK_PSC BIT(2) -#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */ -#define CLK_PLL BIT(4) /* PLL-derived clock */ -#define PRE_PLL BIT(5) /* source is before PLL mult/div */ -#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */ -#define PSC_FORCE BIT(7) /* Force module state transtition */ +#define CLK_PLL BIT(3) /* PLL-derived clock */ +#define PRE_PLL BIT(4) /* source is before PLL mult/div */ +#define PSC_SWRSTDISABLE BIT(5) /* Disable state is SwRstDisable */ +#define PSC_FORCE BIT(6) /* Force module state transtition */ #define CLK(dev, con, ck) \ { \ diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 0800f9cf33b..43a48ee1917 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -130,7 +130,7 @@ static struct clk dsp_clk = { .name = "dsp", .parent = &pll1_sysclk1, .lpsc = DAVINCI_LPSC_GEM, - .flags = PSC_DSP, + .domain = DAVINCI_GPSC_DSPDOMAIN, .usecount = 1, /* REVISIT how to disable? */ }; @@ -145,7 +145,7 @@ static struct clk vicp_clk = { .name = "vicp", .parent = &pll1_sysclk2, .lpsc = DAVINCI_LPSC_IMCOP, - .flags = PSC_DSP, + .domain = DAVINCI_GPSC_DSPDOMAIN, .usecount = 1, /* REVISIT how to disable? */ }; diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c index 00be4fc26dd..98b8c83b09a 100644 --- a/arch/arm/mach-dove/addr-map.c +++ b/arch/arm/mach-dove/addr-map.c @@ -14,6 +14,7 @@ #include <linux/io.h> #include <asm/mach/arch.h> #include <asm/setup.h> +#include <plat/addr-map.h> #include "common.h" /* @@ -34,98 +35,72 @@ #define ATTR_PCIE_MEM 0xe8 #define ATTR_SCRATCHPAD 0x0 -/* - * CPU Address Decode Windows registers - */ -#define WIN_CTRL(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x0) -#define WIN_BASE(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x4) -#define WIN_REMAP_LO(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x8) -#define WIN_REMAP_HI(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0xc) - -struct mbus_dram_target_info dove_mbus_dram_info; - static inline void __iomem *ddr_map_sc(int i) { return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4)); } -static int cpu_win_can_remap(int win) -{ - if (win < 4) - return 1; - - return 0; -} - -static void __init setup_cpu_win(int win, u32 base, u32 size, - u8 target, u8 attr, int remap) -{ - u32 ctrl; - - base &= 0xffff0000; - ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; - - writel(base, WIN_BASE(win)); - writel(ctrl, WIN_CTRL(win)); - if (cpu_win_can_remap(win)) { - if (remap < 0) - remap = base; - writel(remap & 0xffff0000, WIN_REMAP_LO(win)); - writel(0, WIN_REMAP_HI(win)); - } -} - -void __init dove_setup_cpu_mbus(void) -{ - int i; - int cs; +/* + * Description of the windows needed by the platform code + */ +static struct __initdata orion_addr_map_cfg addr_map_cfg = { + .num_wins = 8, + .remappable_wins = 4, + .bridge_virt_base = BRIDGE_VIRT_BASE, +}; +static const struct __initdata orion_addr_map_info addr_map_info[] = { /* - * First, disable and clear windows. + * Windows for PCIe IO+MEM space. */ - for (i = 0; i < 8; i++) { - writel(0, WIN_BASE(i)); - writel(0, WIN_CTRL(i)); - if (cpu_win_can_remap(i)) { - writel(0, WIN_REMAP_LO(i)); - writel(0, WIN_REMAP_HI(i)); - } - } - + { 0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE, + TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE + }, + { 1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE, + TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE + }, + { 2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE, + TARGET_PCIE0, ATTR_PCIE_MEM, -1 + }, + { 3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE, + TARGET_PCIE1, ATTR_PCIE_MEM, -1 + }, /* - * Setup windows for PCIe IO+MEM space. + * Window for CESA engine. */ - setup_cpu_win(0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE, - TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE); - setup_cpu_win(1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE, - TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE); - setup_cpu_win(2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE, - TARGET_PCIE0, ATTR_PCIE_MEM, -1); - setup_cpu_win(3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE, - TARGET_PCIE1, ATTR_PCIE_MEM, -1); - + { 4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE, + TARGET_CESA, ATTR_CESA, -1 + }, /* - * Setup window for CESA engine. + * Window to the BootROM for Standby and Sleep Resume */ - setup_cpu_win(4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE, - TARGET_CESA, ATTR_CESA, -1); - + { 5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE, + TARGET_BOOTROM, ATTR_BOOTROM, -1 + }, /* - * Setup the Window to the BootROM for Standby and Sleep Resume + * Window to the PMU Scratch Pad space */ - setup_cpu_win(5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE, - TARGET_BOOTROM, ATTR_BOOTROM, -1); + { 6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE, + TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1 + }, + /* End marker */ + { -1, 0, 0, 0, 0, 0 } +}; + +void __init dove_setup_cpu_mbus(void) +{ + int i; + int cs; /* - * Setup the Window to the PMU Scratch Pad space + * Disable, clear and configure windows. */ - setup_cpu_win(6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE, - TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1); + orion_config_wins(&addr_map_cfg, addr_map_info); /* * Setup MBUS dram target info. */ - dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; for (i = 0, cs = 0; i < 2; i++) { u32 map = readl(ddr_map_sc(i)); @@ -136,7 +111,7 @@ void __init dove_setup_cpu_mbus(void) if (map & 1) { struct mbus_dram_window *w; - w = &dove_mbus_dram_info.cs[cs++]; + w = &orion_mbus_dram_info.cs[cs++]; w->cs_index = i; w->mbus_attr = 0; /* CS address decoding done inside */ /* the DDR controller, no need to */ @@ -145,5 +120,5 @@ void __init dove_setup_cpu_mbus(void) w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); } } - dove_mbus_dram_info.num_cs = cs; + orion_mbus_dram_info.num_cs = cs; } diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 13bb236cd0c..dd1429ae640 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -14,7 +14,6 @@ #include <linux/platform_device.h> #include <linux/pci.h> #include <linux/clk.h> -#include <linux/mbus.h> #include <linux/ata_platform.h> #include <linux/gpio.h> #include <asm/page.h> @@ -30,6 +29,7 @@ #include <linux/irq.h> #include <plat/time.h> #include <plat/common.h> +#include <plat/addr-map.h> #include "common.h" static int get_tclk(void); @@ -71,8 +71,7 @@ void __init dove_map_io(void) ****************************************************************************/ void __init dove_ehci0_init(void) { - orion_ehci_init(&dove_mbus_dram_info, - DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0); + orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0); } /***************************************************************************** @@ -80,8 +79,7 @@ void __init dove_ehci0_init(void) ****************************************************************************/ void __init dove_ehci1_init(void) { - orion_ehci_1_init(&dove_mbus_dram_info, - DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); + orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); } /***************************************************************************** @@ -89,7 +87,7 @@ void __init dove_ehci1_init(void) ****************************************************************************/ void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) { - orion_ge00_init(eth_data, &dove_mbus_dram_info, + orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM, 0, get_tclk()); } @@ -107,8 +105,7 @@ void __init dove_rtc_init(void) ****************************************************************************/ void __init dove_sata_init(struct mv_sata_platform_data *sata_data) { - orion_sata_init(sata_data, &dove_mbus_dram_info, - DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); + orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); } @@ -198,8 +195,7 @@ struct sys_timer dove_timer = { ****************************************************************************/ void __init dove_xor0_init(void) { - orion_xor0_init(&dove_mbus_dram_info, - DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, + orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); } diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h index 42027305c10..6432a3ba864 100644 --- a/arch/arm/mach-dove/common.h +++ b/arch/arm/mach-dove/common.h @@ -15,7 +15,6 @@ struct mv643xx_eth_platform_data; struct mv_sata_platform_data; extern struct sys_timer dove_timer; -extern struct mbus_dram_target_info dove_mbus_dram_info; /* * Basic Dove init functions used early by machine-setup. diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c index aa2b3a09a51..6c11a4df717 100644 --- a/arch/arm/mach-dove/pcie.c +++ b/arch/arm/mach-dove/pcie.c @@ -10,7 +10,6 @@ #include <linux/kernel.h> #include <linux/pci.h> -#include <linux/mbus.h> #include <video/vga.h> #include <asm/mach/pci.h> #include <asm/mach/arch.h> @@ -19,6 +18,7 @@ #include <plat/pcie.h> #include <mach/irqs.h> #include <mach/bridge-regs.h> +#include <plat/addr-map.h> #include "common.h" struct pcie_port { @@ -50,7 +50,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) */ orion_pcie_set_local_bus_nr(pp->base, sys->busnr); - orion_pcie_setup(pp->base, &dove_mbus_dram_info); + orion_pcie_setup(pp->base); /* * IORESOURCE_IO diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c index 8d03bcef518..e9a7180863d 100644 --- a/arch/arm/mach-kirkwood/addr-map.c +++ b/arch/arm/mach-kirkwood/addr-map.c @@ -13,12 +13,12 @@ #include <linux/mbus.h> #include <linux/io.h> #include <mach/hardware.h> +#include <plat/addr-map.h> #include "common.h" /* * Generic Address Decode Windows bit settings */ -#define TARGET_DDR 0 #define TARGET_DEV_BUS 1 #define TARGET_SRAM 3 #define TARGET_PCIE 4 @@ -36,118 +36,55 @@ #define ATTR_SRAM 0x01 /* - * Helpers to get DDR bank info + * Description of the windows needed by the platform code */ -#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) -#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) - -/* - * CPU Address Decode Windows registers - */ -#define WIN_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) -#define WIN_CTRL_OFF 0x0000 -#define WIN_BASE_OFF 0x0004 -#define WIN_REMAP_LO_OFF 0x0008 -#define WIN_REMAP_HI_OFF 0x000c - - -struct mbus_dram_target_info kirkwood_mbus_dram_info; - -static int __init cpu_win_can_remap(int win) -{ - if (win < 4) - return 1; - - return 0; -} - -static void __init setup_cpu_win(int win, u32 base, u32 size, - u8 target, u8 attr, int remap) -{ - void __iomem *addr = (void __iomem *)WIN_OFF(win); - u32 ctrl; - - base &= 0xffff0000; - ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; - - writel(base, addr + WIN_BASE_OFF); - writel(ctrl, addr + WIN_CTRL_OFF); - if (cpu_win_can_remap(win)) { - if (remap < 0) - remap = base; - - writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF); - writel(0, addr + WIN_REMAP_HI_OFF); - } -} - -void __init kirkwood_setup_cpu_mbus(void) -{ - void __iomem *addr; - int i; - int cs; +static struct __initdata orion_addr_map_cfg addr_map_cfg = { + .num_wins = 8, + .remappable_wins = 4, + .bridge_virt_base = BRIDGE_VIRT_BASE, +}; +static const struct __initdata orion_addr_map_info addr_map_info[] = { /* - * First, disable and clear windows. + * Windows for PCIe IO+MEM space. */ - for (i = 0; i < 8; i++) { - addr = (void __iomem *)WIN_OFF(i); - - writel(0, addr + WIN_BASE_OFF); - writel(0, addr + WIN_CTRL_OFF); - if (cpu_win_can_remap(i)) { - writel(0, addr + WIN_REMAP_LO_OFF); - writel(0, addr + WIN_REMAP_HI_OFF); - } - } - + { 0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE, + TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE + }, + { 1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, + TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE + }, + { 2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE, + TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE + }, + { 3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE, + TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE + }, /* - * Setup windows for PCIe IO+MEM space. + * Window for NAND controller. */ - setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE, - TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE); - setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, - TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE); - setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE, - TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE); - setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE, - TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE); - + { 4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, + TARGET_DEV_BUS, ATTR_DEV_NAND, -1 + }, /* - * Setup window for NAND controller. + * Window for SRAM. */ - setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, - TARGET_DEV_BUS, ATTR_DEV_NAND, -1); + { 5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, + TARGET_SRAM, ATTR_SRAM, -1 + }, + /* End marker */ + { -1, 0, 0, 0, 0, 0 } +}; +void __init kirkwood_setup_cpu_mbus(void) +{ /* - * Setup window for SRAM. + * Disable, clear and configure windows. */ - setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, - TARGET_SRAM, ATTR_SRAM, -1); + orion_config_wins(&addr_map_cfg, addr_map_info); /* * Setup MBUS dram target info. */ - kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; - - addr = (void __iomem *)DDR_WINDOW_CPU_BASE; - - for (i = 0, cs = 0; i < 4; i++) { - u32 base = readl(addr + DDR_BASE_CS_OFF(i)); - u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); - - /* - * Chip select enabled? - */ - if (size & 1) { - struct mbus_dram_window *w; - - w = &kirkwood_mbus_dram_info.cs[cs++]; - w->cs_index = i; - w->mbus_attr = 0xf & ~(1 << i); - w->base = base & 0xffff0000; - w->size = (size | 0x0000ffff) + 1; - } - } - kirkwood_mbus_dram_info.num_cs = cs; + orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE); } diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 0bff4a91623..cc15426787b 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -12,7 +12,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/serial_8250.h> -#include <linux/mbus.h> #include <linux/ata_platform.h> #include <linux/mtd/nand.h> #include <linux/dma-mapping.h> @@ -30,6 +29,7 @@ #include <plat/orion_nand.h> #include <plat/common.h> #include <plat/time.h> +#include <plat/addr-map.h> #include "common.h" /***************************************************************************** @@ -73,8 +73,7 @@ unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED; void __init kirkwood_ehci_init(void) { kirkwood_clk_ctrl |= CGC_USB0; - orion_ehci_init(&kirkwood_mbus_dram_info, - USB_PHYS_BASE, IRQ_KIRKWOOD_USB); + orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB); } @@ -85,7 +84,7 @@ void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) { kirkwood_clk_ctrl |= CGC_GE0; - orion_ge00_init(eth_data, &kirkwood_mbus_dram_info, + orion_ge00_init(eth_data, GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM, IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk); } @@ -99,7 +98,7 @@ void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) kirkwood_clk_ctrl |= CGC_GE1; - orion_ge01_init(eth_data, &kirkwood_mbus_dram_info, + orion_ge01_init(eth_data, GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk); } @@ -178,8 +177,7 @@ void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data) if (sata_data->n_ports > 1) kirkwood_clk_ctrl |= CGC_SATA1; - orion_sata_init(sata_data, &kirkwood_mbus_dram_info, - SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA); + orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA); } @@ -221,7 +219,6 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data) mvsdio_data->clock = 100000000; else mvsdio_data->clock = 200000000; - mvsdio_data->dram = &kirkwood_mbus_dram_info; kirkwood_clk_ctrl |= CGC_SDIO; kirkwood_sdio.dev.platform_data = mvsdio_data; platform_device_register(&kirkwood_sdio); @@ -285,8 +282,7 @@ static void __init kirkwood_xor0_init(void) { kirkwood_clk_ctrl |= CGC_XOR0; - orion_xor0_init(&kirkwood_mbus_dram_info, - XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE, + orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE, IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01); } @@ -364,7 +360,6 @@ static struct resource kirkwood_i2s_resources[] = { }; static struct kirkwood_asoc_platform_data kirkwood_i2s_data = { - .dram = &kirkwood_mbus_dram_info, .burst = 128, }; @@ -430,6 +425,8 @@ static char * __init kirkwood_id(void) } else if (dev == MV88F6282_DEV_ID) { if (rev == MV88F6282_REV_A0) return "MV88F6282-Rev-A0"; + else if (rev == MV88F6282_REV_A1) + return "MV88F6282-Rev-A1"; else return "MV88F6282-Rev-Unsupported"; } else { diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 1529280246d..9071a397136 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -30,7 +30,6 @@ void kirkwood_init(void); void kirkwood_init_early(void); void kirkwood_init_irq(void); -extern struct mbus_dram_target_info kirkwood_mbus_dram_info; void kirkwood_setup_cpu_mbus(void); void kirkwood_enable_pcie(void); diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index 010bdeb4ac5..fede3d503ef 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -135,4 +135,5 @@ #define MV88F6282_DEV_ID 0x6282 #define MV88F6282_REV_A0 0 +#define MV88F6282_REV_A1 1 #endif diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c index cc431fa22cc..0c6ad63f10c 100644 --- a/arch/arm/mach-kirkwood/mpp.c +++ b/arch/arm/mach-kirkwood/mpp.c @@ -10,7 +10,6 @@ #include <linux/gpio.h> #include <linux/kernel.h> #include <linux/init.h> -#include <linux/mbus.h> #include <linux/io.h> #include <mach/hardware.h> #include <plat/mpp.h> diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h index ac787957e2d..e8fda45c073 100644 --- a/arch/arm/mach-kirkwood/mpp.h +++ b/arch/arm/mach-kirkwood/mpp.h @@ -102,6 +102,7 @@ #define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 ) #define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP12_GPIO MPP( 12, 0x0, 1, 1, 0, 0, 0, 1, 0 ) #define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 ) #define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 ) #define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 ) diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index 74b992d810e..fb451bfe478 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -11,12 +11,12 @@ #include <linux/kernel.h> #include <linux/pci.h> #include <linux/slab.h> -#include <linux/mbus.h> #include <video/vga.h> #include <asm/irq.h> #include <asm/mach/pci.h> #include <plat/pcie.h> #include <mach/bridge-regs.h> +#include <plat/addr-map.h> #include "common.h" void kirkwood_enable_pcie(void) @@ -208,7 +208,7 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) */ orion_pcie_set_local_bus_nr(pp->base, sys->busnr); - orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info); + orion_pcie_setup(pp->base); return 1; } diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c index 311d5b0e9bc..62b53d710ef 100644 --- a/arch/arm/mach-mv78xx0/addr-map.c +++ b/arch/arm/mach-mv78xx0/addr-map.c @@ -12,12 +12,12 @@ #include <linux/init.h> #include <linux/mbus.h> #include <linux/io.h> +#include <plat/addr-map.h> #include "common.h" /* * Generic Address Decode Windows bit settings */ -#define TARGET_DDR 0 #define TARGET_DEV_BUS 1 #define TARGET_PCIE0 4 #define TARGET_PCIE1 8 @@ -32,23 +32,10 @@ #define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l))) /* - * Helpers to get DDR bank info - */ -#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) -#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) - -/* * CPU Address Decode Windows registers */ #define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) #define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4)) -#define WIN_CTRL_OFF 0x0000 -#define WIN_BASE_OFF 0x0004 -#define WIN_REMAP_LO_OFF 0x0008 -#define WIN_REMAP_HI_OFF 0x000c - - -struct mbus_dram_target_info mv78xx0_mbus_dram_info; static void __init __iomem *win_cfg_base(int win) { @@ -63,94 +50,43 @@ static void __init __iomem *win_cfg_base(int win) return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win)); } -static int __init cpu_win_can_remap(int win) -{ - if (win < 8) - return 1; - - return 0; -} - -static void __init setup_cpu_win(int win, u32 base, u32 size, - u8 target, u8 attr, int remap) -{ - void __iomem *addr = win_cfg_base(win); - u32 ctrl; - - base &= 0xffff0000; - ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; - - writel(base, addr + WIN_BASE_OFF); - writel(ctrl, addr + WIN_CTRL_OFF); - if (cpu_win_can_remap(win)) { - if (remap < 0) - remap = base; - - writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF); - writel(0, addr + WIN_REMAP_HI_OFF); - } -} +/* + * Description of the windows needed by the platform code + */ +static struct __initdata orion_addr_map_cfg addr_map_cfg = { + .num_wins = 14, + .remappable_wins = 8, + .win_cfg_base = win_cfg_base, +}; void __init mv78xx0_setup_cpu_mbus(void) { - void __iomem *addr; - int i; - int cs; - /* - * First, disable and clear windows. + * Disable, clear and configure windows. */ - for (i = 0; i < 14; i++) { - addr = win_cfg_base(i); - - writel(0, addr + WIN_BASE_OFF); - writel(0, addr + WIN_CTRL_OFF); - if (cpu_win_can_remap(i)) { - writel(0, addr + WIN_REMAP_LO_OFF); - writel(0, addr + WIN_REMAP_HI_OFF); - } - } + orion_config_wins(&addr_map_cfg, NULL); /* * Setup MBUS dram target info. */ - mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; - if (mv78xx0_core_index() == 0) - addr = (void __iomem *)DDR_WINDOW_CPU0_BASE; + orion_setup_cpu_mbus_target(&addr_map_cfg, + DDR_WINDOW_CPU0_BASE); else - addr = (void __iomem *)DDR_WINDOW_CPU1_BASE; - - for (i = 0, cs = 0; i < 4; i++) { - u32 base = readl(addr + DDR_BASE_CS_OFF(i)); - u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); - - /* - * Chip select enabled? - */ - if (size & 1) { - struct mbus_dram_window *w; - - w = &mv78xx0_mbus_dram_info.cs[cs++]; - w->cs_index = i; - w->mbus_attr = 0xf & ~(1 << i); - w->base = base & 0xffff0000; - w->size = (size | 0x0000ffff) + 1; - } - } - mv78xx0_mbus_dram_info.num_cs = cs; + orion_setup_cpu_mbus_target(&addr_map_cfg, + DDR_WINDOW_CPU1_BASE); } void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, int maj, int min) { - setup_cpu_win(window, base, size, TARGET_PCIE(maj), - ATTR_PCIE_IO(min), -1); + orion_setup_cpu_win(&addr_map_cfg, window, base, size, + TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1); } void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, int maj, int min) { - setup_cpu_win(window, base, size, TARGET_PCIE(maj), - ATTR_PCIE_MEM(min), -1); + orion_setup_cpu_win(&addr_map_cfg, window, base, size, + TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1); } diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 5b9632b0116..0cdd41004ad 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -12,7 +12,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/serial_8250.h> -#include <linux/mbus.h> #include <linux/ata_platform.h> #include <linux/ethtool.h> #include <asm/mach/map.h> @@ -23,6 +22,7 @@ #include <plat/orion_nand.h> #include <plat/time.h> #include <plat/common.h> +#include <plat/addr-map.h> #include "common.h" static int get_tclk(void); @@ -169,8 +169,7 @@ void __init mv78xx0_map_io(void) ****************************************************************************/ void __init mv78xx0_ehci0_init(void) { - orion_ehci_init(&mv78xx0_mbus_dram_info, - USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); + orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); } @@ -179,8 +178,7 @@ void __init mv78xx0_ehci0_init(void) ****************************************************************************/ void __init mv78xx0_ehci1_init(void) { - orion_ehci_1_init(&mv78xx0_mbus_dram_info, - USB1_PHYS_BASE, IRQ_MV78XX0_USB_1); + orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1); } @@ -189,8 +187,7 @@ void __init mv78xx0_ehci1_init(void) ****************************************************************************/ void __init mv78xx0_ehci2_init(void) { - orion_ehci_2_init(&mv78xx0_mbus_dram_info, - USB2_PHYS_BASE, IRQ_MV78XX0_USB_2); + orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2); } @@ -199,7 +196,7 @@ void __init mv78xx0_ehci2_init(void) ****************************************************************************/ void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) { - orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info, + orion_ge00_init(eth_data, GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, IRQ_MV78XX0_GE_ERR, get_tclk()); } @@ -210,7 +207,7 @@ void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) ****************************************************************************/ void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) { - orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info, + orion_ge01_init(eth_data, GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, NO_IRQ, get_tclk()); } @@ -234,7 +231,7 @@ void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) eth_data->duplex = DUPLEX_FULL; } - orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info, + orion_ge10_init(eth_data, GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM, NO_IRQ, get_tclk()); } @@ -258,7 +255,7 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) eth_data->duplex = DUPLEX_FULL; } - orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info, + orion_ge11_init(eth_data, GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM, NO_IRQ, get_tclk()); } @@ -277,8 +274,7 @@ void __init mv78xx0_i2c_init(void) ****************************************************************************/ void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) { - orion_sata_init(sata_data, &mv78xx0_mbus_dram_info, - SATA_PHYS_BASE, IRQ_MV78XX0_SATA); + orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA); } diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h index 07d5f8f6be7..507c767d49e 100644 --- a/arch/arm/mach-mv78xx0/common.h +++ b/arch/arm/mach-mv78xx0/common.h @@ -23,7 +23,6 @@ void mv78xx0_init(void); void mv78xx0_init_early(void); void mv78xx0_init_irq(void); -extern struct mbus_dram_target_info mv78xx0_mbus_dram_info; void mv78xx0_setup_cpu_mbus(void); void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, int maj, int min); diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c index cf4e494d44b..df50342179e 100644 --- a/arch/arm/mach-mv78xx0/mpp.c +++ b/arch/arm/mach-mv78xx0/mpp.c @@ -10,7 +10,6 @@ #include <linux/gpio.h> #include <linux/kernel.h> #include <linux/init.h> -#include <linux/mbus.h> #include <linux/io.h> #include <plat/mpp.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index c51af1cac30..12fcb108b0e 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -10,11 +10,11 @@ #include <linux/kernel.h> #include <linux/pci.h> -#include <linux/mbus.h> #include <video/vga.h> #include <asm/irq.h> #include <asm/mach/pci.h> #include <plat/pcie.h> +#include <plat/addr-map.h> #include "common.h" struct pcie_port { @@ -153,7 +153,7 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys) * Generic PCIe unit setup. */ orion_pcie_set_local_bus_nr(pp->base, sys->busnr); - orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info); + orion_pcie_setup(pp->base); sys->resource[0] = &pp->res[0]; sys->resource[1] = &pp->res[1]; diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 73f287d6429..4f8d66f044e 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -168,70 +168,6 @@ config MACH_OMAP_GENERIC custom OMAP boards. Say Y here if you have a custom board. -comment "OMAP CPU Speed" - depends on ARCH_OMAP1 - -config OMAP_ARM_216MHZ - bool "OMAP ARM 216 MHz CPU (1710 only)" - depends on ARCH_OMAP1 && ARCH_OMAP16XX - help - Enable 216 MHz clock for OMAP1710 CPU. If unsure, say N. - -config OMAP_ARM_195MHZ - bool "OMAP ARM 195 MHz CPU" - depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850) - help - Enable 195MHz clock for OMAP CPU. If unsure, say N. - -config OMAP_ARM_192MHZ - bool "OMAP ARM 192 MHz CPU" - depends on ARCH_OMAP1 && ARCH_OMAP16XX - help - Enable 192MHz clock for OMAP CPU. If unsure, say N. - -config OMAP_ARM_182MHZ - bool "OMAP ARM 182 MHz CPU" - depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850) - help - Enable 182MHz clock for OMAP CPU. If unsure, say N. - -config OMAP_ARM_168MHZ - bool "OMAP ARM 168 MHz CPU" - depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) - help - Enable 168MHz clock for OMAP CPU. If unsure, say N. - -config OMAP_ARM_150MHZ - bool "OMAP ARM 150 MHz CPU" - depends on ARCH_OMAP1 && ARCH_OMAP15XX - help - Enable 150MHz clock for OMAP CPU. If unsure, say N. - -config OMAP_ARM_120MHZ - bool "OMAP ARM 120 MHz CPU" - depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) - help - Enable 120MHz clock for OMAP CPU. If unsure, say N. - -config OMAP_ARM_96MHZ - bool "OMAP ARM 96 MHz CPU" - depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) - help - Enable 96MHz clock for OMAP CPU. If unsure, say N. - -config OMAP_ARM_60MHZ - bool "OMAP ARM 60 MHz CPU" - depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) - default y - help - Enable 60MHz clock for OMAP CPU. If unsure, say Y. - -config OMAP_ARM_30MHZ - bool "OMAP ARM 30 MHz CPU" - depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) - help - Enable 30MHz clock for OMAP CPU. If unsure, say N. - endmenu endif diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 84ef70476b5..0c50df05d13 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -197,11 +197,10 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate) ref_rate = ck_ref_p->rate; for (ptr = omap1_rate_table; ptr->rate; ptr++) { - if (ptr->xtal != ref_rate) + if (!(ptr->flags & cpu_mask)) continue; - /* DPLL1 cannot be reprogrammed without risking system crash */ - if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate) + if (ptr->xtal != ref_rate) continue; /* Can check only after xtal frequency check */ @@ -215,12 +214,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate) /* * In most cases we should not need to reprogram DPLL. * Reprogramming the DPLL is tricky, it must be done from SRAM. - * (on 730, bit 13 must always be 1) */ - if (cpu_is_omap7xx()) - omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000); - else - omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); + omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); /* XXX Do we need to recalculate the tree below DPLL1 at this point? */ ck_dpll1_p->rate = ptr->pll_rate; @@ -290,6 +285,9 @@ long omap1_round_to_table_rate(struct clk *clk, unsigned long rate) highest_rate = -EINVAL; for (ptr = omap1_rate_table; ptr->rate; ptr++) { + if (!(ptr->flags & cpu_mask)) + continue; + if (ptr->xtal != ref_rate) continue; diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index 16b1423b454..3d04f4f6767 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h @@ -111,4 +111,7 @@ extern const struct clkops clkops_dummy; extern const struct clkops clkops_uart_16xx; extern const struct clkops clkops_generic; +/* used for passing SoC type to omap1_{select,round_to}_table_rate() */ +extern u32 cpu_mask; + #endif diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index 9ff90a744a2..94699a82a73 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -25,6 +25,7 @@ #include <plat/clock.h> #include <plat/cpu.h> #include <plat/clkdev_omap.h> +#include <plat/sram.h> /* for omap_sram_reprogram_clock() */ #include <plat/usb.h> /* for OTG_BASE */ #include "clock.h" @@ -778,12 +779,14 @@ static void __init omap1_show_rates(void) arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); } +u32 cpu_mask; + int __init omap1_clk_init(void) { struct omap_clk *c; const struct omap_clock_config *info; int crystal_type = 0; /* Default 12 MHz */ - u32 reg, cpu_mask; + u32 reg; #ifdef CONFIG_DEBUG_LL /* @@ -808,6 +811,8 @@ int __init omap1_clk_init(void) clk_preinit(c->lk.clk); cpu_mask = 0; + if (cpu_is_omap1710()) + cpu_mask |= CK_1710; if (cpu_is_omap16xx()) cpu_mask |= CK_16XX; if (cpu_is_omap1510()) @@ -931,17 +936,13 @@ void __init omap1_clk_late_init(void) { unsigned long rate = ck_dpll1.rate; - if (rate >= OMAP1_DPLL1_SANE_VALUE) - return; - - /* System booting at unusable rate, force reprogramming of DPLL1 */ - ck_dpll1_p->rate = 0; - /* Find the highest supported frequency and enable it */ if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { pr_err("System frequencies not set, using default. Check your config.\n"); - omap_writew(0x2290, DPLL_CTL); - omap_writew(cpu_is_omap7xx() ? 0x2005 : 0x0005, ARM_CKCTL); + /* + * Reprogramming the DPLL is tricky, it must be done from SRAM. + */ + omap_sram_reprogram_clock(0x2290, 0x0005); ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE; } propagate_rate(&ck_dpll1); diff --git a/arch/arm/mach-omap1/opp.h b/arch/arm/mach-omap1/opp.h index 07074d79adc..79a683864a5 100644 --- a/arch/arm/mach-omap1/opp.h +++ b/arch/arm/mach-omap1/opp.h @@ -21,6 +21,7 @@ struct mpu_rate { unsigned long pll_rate; __u16 ckctl_val; __u16 dpllctl_val; + u32 flags; }; extern struct mpu_rate omap1_rate_table[]; diff --git a/arch/arm/mach-omap1/opp_data.c b/arch/arm/mach-omap1/opp_data.c index 75a54651499..9cd4ddb5139 100644 --- a/arch/arm/mach-omap1/opp_data.c +++ b/arch/arm/mach-omap1/opp_data.c @@ -10,6 +10,7 @@ * published by the Free Software Foundation. */ +#include <plat/clkdev_omap.h> #include "opp.h" /*------------------------------------------------------------------------- @@ -20,40 +21,34 @@ struct mpu_rate omap1_rate_table[] = { * NOTE: Comment order here is different from bits in CKCTL value: * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv */ -#if defined(CONFIG_OMAP_ARM_216MHZ) - { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_195MHZ) - { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_192MHZ) - { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */ - { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */ - { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */ - { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */ - { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_182MHZ) - { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_168MHZ) - { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_150MHZ) - { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */ -#endif -#if defined(CONFIG_OMAP_ARM_120MHZ) - { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */ -#endif -#if defined(CONFIG_OMAP_ARM_96MHZ) - { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */ -#endif -#if defined(CONFIG_OMAP_ARM_60MHZ) - { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */ -#endif -#if defined(CONFIG_OMAP_ARM_30MHZ) - { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */ -#endif + { 216000000, 12000000, 216000000, 0x050d, 0x2910, /* 1/1/2/2/2/8 */ + CK_1710 }, + { 195000000, 13000000, 195000000, 0x050e, 0x2790, /* 1/1/2/2/4/8 */ + CK_7XX }, + { 192000000, 19200000, 192000000, 0x050f, 0x2510, /* 1/1/2/2/8/8 */ + CK_16XX }, + { 192000000, 12000000, 192000000, 0x050f, 0x2810, /* 1/1/2/2/8/8 */ + CK_16XX }, + { 96000000, 12000000, 192000000, 0x055f, 0x2810, /* 2/2/2/2/8/8 */ + CK_16XX }, + { 48000000, 12000000, 192000000, 0x0baf, 0x2810, /* 4/4/4/8/8/8 */ + CK_16XX }, + { 24000000, 12000000, 192000000, 0x0fff, 0x2810, /* 8/8/8/8/8/8 */ + CK_16XX }, + { 182000000, 13000000, 182000000, 0x050e, 0x2710, /* 1/1/2/2/4/8 */ + CK_7XX }, + { 168000000, 12000000, 168000000, 0x010f, 0x2710, /* 1/1/1/2/8/8 */ + CK_16XX|CK_7XX }, + { 150000000, 12000000, 150000000, 0x010a, 0x2cb0, /* 1/1/1/2/4/4 */ + CK_1510 }, + { 120000000, 12000000, 120000000, 0x010a, 0x2510, /* 1/1/1/2/4/4 */ + CK_16XX|CK_1510|CK_310|CK_7XX }, + { 96000000, 12000000, 96000000, 0x0005, 0x2410, /* 1/1/1/1/2/2 */ + CK_16XX|CK_1510|CK_310|CK_7XX }, + { 60000000, 12000000, 60000000, 0x0005, 0x2290, /* 1/1/1/1/2/2 */ + CK_16XX|CK_1510|CK_310|CK_7XX }, + { 30000000, 12000000, 60000000, 0x0555, 0x2290, /* 2/2/2/2/2/2 */ + CK_16XX|CK_1510|CK_310|CK_7XX }, { 0, 0, 0, 0, 0 }, }; diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 60424f41156..039cadf84c1 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -2480,6 +2480,16 @@ static struct clk uart4_fck = { .recalc = &followparent_recalc, }; +static struct clk uart4_fck_am35xx = { + .name = "uart4_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_48m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_UART4_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + static struct clk gpt2_fck = { .name = "gpt2_fck", .ops = &clkops_omap2_dflt_wait, @@ -3403,6 +3413,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX), + CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_3505 | CK_3517), CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 126cb49c0de..5324e8d93bc 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -84,6 +84,8 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod; static struct omap_hwmod omap3xxx_mcbsp5_hwmod; static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod; static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod; +static struct omap_hwmod omap3xxx_usb_host_hs_hwmod; +static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { @@ -164,6 +166,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod; static struct omap_hwmod omap3xxx_uart2_hwmod; static struct omap_hwmod omap3xxx_uart3_hwmod; static struct omap_hwmod omap3xxx_uart4_hwmod; +static struct omap_hwmod am35xx_uart4_hwmod; static struct omap_hwmod omap3xxx_usbhsotg_hwmod; /* l3_core -> usbhsotg interface */ @@ -299,6 +302,23 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* AM35xx: L4 CORE -> UART4 interface */ +static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { + { + .pa_start = OMAP3_UART4_AM35XX_BASE, + .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &am35xx_uart4_hwmod, + .clk = "uart4_ick", + .addr = am35xx_uart4_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* L4 CORE -> I2C1 interface */ static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { .master = &omap3xxx_l4_core_hwmod, @@ -1162,6 +1182,7 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = { SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .clockact = CLOCKACT_TEST_ICLK, .sysc_fields = &omap_hwmod_sysc_type1, }; @@ -1309,6 +1330,39 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = { .class = &omap2_uart_class, }; +static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { + { .irq = INT_35XX_UART4_IRQ, }, +}; + +static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { + { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, + { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, +}; + +static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = { + &am35xx_l4_core__uart4, +}; + +static struct omap_hwmod am35xx_uart4_hwmod = { + .name = "uart4", + .mpu_irqs = am35xx_uart4_mpu_irqs, + .sdma_reqs = am35xx_uart4_sdma_reqs, + .main_clk = "uart4_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_UART4_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT, + }, + }, + .slaves = am35xx_uart4_slaves, + .slaves_cnt = ARRAY_SIZE(am35xx_uart4_slaves), + .class = &omap2_uart_class, +}; + + static struct omap_hwmod_class i2c_class = { .name = "i2c", .sysc = &i2c_sysc, @@ -1636,7 +1690,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { static struct omap_hwmod omap3xxx_i2c1_hwmod = { .name = "i2c1", - .flags = HWMOD_16BIT_REG, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap2_i2c1_mpu_irqs, .sdma_reqs = omap2_i2c1_sdma_reqs, .main_clk = "i2c1_fck", @@ -1670,7 +1724,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { static struct omap_hwmod omap3xxx_i2c2_hwmod = { .name = "i2c2", - .flags = HWMOD_16BIT_REG, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap2_i2c2_mpu_irqs, .sdma_reqs = omap2_i2c2_sdma_reqs, .main_clk = "i2c2_fck", @@ -1715,7 +1769,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { static struct omap_hwmod omap3xxx_i2c3_hwmod = { .name = "i2c3", - .flags = HWMOD_16BIT_REG, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = i2c3_mpu_irqs, .sdma_reqs = i2c3_sdma_reqs, .main_clk = "i2c3_fck", @@ -3072,7 +3126,35 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = { .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, }; -static struct omap_hwmod omap3xxx_mmc1_hwmod = { +/* See 35xx errata 2.1.1.128 in SPRZ278F */ +static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = { + .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | + OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), +}; + +static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { + .name = "mmc1", + .mpu_irqs = omap34xx_mmc1_mpu_irqs, + .sdma_reqs = omap34xx_mmc1_sdma_reqs, + .opt_clks = omap34xx_mmc1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), + .main_clk = "mmchs1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MMC1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, + }, + }, + .dev_attr = &mmc1_pre_es3_dev_attr, + .slaves = omap3xxx_mmc1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), + .class = &omap34xx_mmc_class, +}; + +static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { .name = "mmc1", .mpu_irqs = omap34xx_mmc1_mpu_irqs, .sdma_reqs = omap34xx_mmc1_sdma_reqs, @@ -3115,7 +3197,34 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = { &omap3xxx_l4_core__mmc2, }; -static struct omap_hwmod omap3xxx_mmc2_hwmod = { +/* See 35xx errata 2.1.1.128 in SPRZ278F */ +static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { + .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, +}; + +static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { + .name = "mmc2", + .mpu_irqs = omap34xx_mmc2_mpu_irqs, + .sdma_reqs = omap34xx_mmc2_sdma_reqs, + .opt_clks = omap34xx_mmc2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), + .main_clk = "mmchs2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MMC2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, + }, + }, + .dev_attr = &mmc2_pre_es3_dev_attr, + .slaves = omap3xxx_mmc2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves), + .class = &omap34xx_mmc_class, +}; + +static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { .name = "mmc2", .mpu_irqs = omap34xx_mmc2_mpu_irqs, .sdma_reqs = omap34xx_mmc2_sdma_reqs, @@ -3177,13 +3286,223 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = { .class = &omap34xx_mmc_class, }; +/* + * 'usb_host_hs' class + * high-speed multi-port usb host controller + */ +static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { + .master = &omap3xxx_usb_host_hs_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { + .name = "usb_host_hs", + .sysc = &omap3xxx_usb_host_hs_sysc, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = { + &omap3xxx_usb_host_hs__l3_main_2, +}; + +static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { + { + .name = "uhh", + .pa_start = 0x48064000, + .pa_end = 0x480643ff, + .flags = ADDR_TYPE_RT + }, + { + .name = "ohci", + .pa_start = 0x48064400, + .pa_end = 0x480647ff, + }, + { + .name = "ehci", + .pa_start = 0x48064800, + .pa_end = 0x48064cff, + }, + {} +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_usb_host_hs_hwmod, + .clk = "usbhost_ick", + .addr = omap3xxx_usb_host_hs_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = { + &omap3xxx_l4_core__usb_host_hs, +}; + +static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { + { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, +}; + +static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { + { .name = "ohci-irq", .irq = 76 }, + { .name = "ehci-irq", .irq = 77 }, + { .irq = -1 } +}; + +static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { + .name = "usb_host_hs", + .class = &omap3xxx_usb_host_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .mpu_irqs = omap3xxx_usb_host_hs_irqs, + .main_clk = "usbhost_48m_fck", + .prcm = { + .omap2 = { + .module_offs = OMAP3430ES2_USBHOST_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, + .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, + }, + }, + .opt_clks = omap3xxx_usb_host_hs_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), + .slaves = omap3xxx_usb_host_hs_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves), + .masters = omap3xxx_usb_host_hs_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_masters), + + /* + * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock + * id: i660 + * + * Description: + * In the following configuration : + * - USBHOST module is set to smart-idle mode + * - PRCM asserts idle_req to the USBHOST module ( This typically + * happens when the system is going to a low power mode : all ports + * have been suspended, the master part of the USBHOST module has + * entered the standby state, and SW has cut the functional clocks) + * - an USBHOST interrupt occurs before the module is able to answer + * idle_ack, typically a remote wakeup IRQ. + * Then the USB HOST module will enter a deadlock situation where it + * is no more accessible nor functional. + * + * Workaround: + * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE + */ + + /* + * Errata: USB host EHCI may stall when entering smart-standby mode + * Id: i571 + * + * Description: + * When the USBHOST module is set to smart-standby mode, and when it is + * ready to enter the standby state (i.e. all ports are suspended and + * all attached devices are in suspend mode), then it can wrongly assert + * the Mstandby signal too early while there are still some residual OCP + * transactions ongoing. If this condition occurs, the internal state + * machine may go to an undefined state and the USB link may be stuck + * upon the next resume. + * + * Workaround: + * Don't use smart standby; use only force standby, + * hence HWMOD_SWSUP_MSTANDBY + */ + + /* + * During system boot; If the hwmod framework resets the module + * the module will have smart idle settings; which can lead to deadlock + * (above Errata Id:i660); so, dont reset the module during boot; + * Use HWMOD_INIT_NO_RESET. + */ + + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | + HWMOD_INIT_NO_RESET, +}; + +/* + * 'usb_tll_hs' class + * usb_tll_hs module is the adapter on the usb_host_hs ports + */ +static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { + .name = "usb_tll_hs", + .sysc = &omap3xxx_usb_tll_hs_sysc, +}; + +static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { + { .name = "tll-irq", .irq = 78 }, + { .irq = -1 } +}; + +static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { + { + .name = "tll", + .pa_start = 0x48062000, + .pa_end = 0x48062fff, + .flags = ADDR_TYPE_RT + }, + {} +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_usb_tll_hs_hwmod, + .clk = "usbtll_ick", + .addr = omap3xxx_usb_tll_hs_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = { + &omap3xxx_l4_core__usb_tll_hs, +}; + +static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { + .name = "usb_tll_hs", + .class = &omap3xxx_usb_tll_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .mpu_irqs = omap3xxx_usb_tll_hs_irqs, + .main_clk = "usbtll_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 3, + .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, + .idlest_reg_id = 3, + .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, + }, + }, + .slaves = omap3xxx_usb_tll_hs_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves), +}; + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l3_main_hwmod, &omap3xxx_l4_core_hwmod, &omap3xxx_l4_per_hwmod, &omap3xxx_l4_wkup_hwmod, - &omap3xxx_mmc1_hwmod, - &omap3xxx_mmc2_hwmod, &omap3xxx_mmc3_hwmod, &omap3xxx_mpu_hwmod, @@ -3203,6 +3522,7 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_uart1_hwmod, &omap3xxx_uart2_hwmod, &omap3xxx_uart3_hwmod, + /* dss class */ &omap3xxx_dss_dispc_hwmod, &omap3xxx_dss_dsi1_hwmod, @@ -3260,6 +3580,22 @@ static __initdata struct omap_hwmod *omap3430es1_hwmods[] = { static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = { &omap3xxx_dss_core_hwmod, &omap3xxx_usbhsotg_hwmod, + &omap3xxx_usb_host_hs_hwmod, + &omap3xxx_usb_tll_hs_hwmod, + NULL +}; + +/* <= 3430ES3-only hwmods */ +static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = { + &omap3xxx_pre_es3_mmc1_hwmod, + &omap3xxx_pre_es3_mmc2_hwmod, + NULL +}; + +/* 3430ES3+-only hwmods */ +static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = { + &omap3xxx_es3plus_mmc1_hwmod, + &omap3xxx_es3plus_mmc2_hwmod, NULL }; @@ -3281,12 +3617,21 @@ static __initdata struct omap_hwmod *omap36xx_hwmods[] = { &omap36xx_sr2_hwmod, &omap3xxx_usbhsotg_hwmod, &omap3xxx_mailbox_hwmod, + &omap3xxx_usb_host_hs_hwmod, + &omap3xxx_usb_tll_hs_hwmod, + &omap3xxx_es3plus_mmc1_hwmod, + &omap3xxx_es3plus_mmc2_hwmod, NULL }; static __initdata struct omap_hwmod *am35xx_hwmods[] = { &omap3xxx_dss_core_hwmod, /* XXX ??? */ &am35xx_usbhsotg_hwmod, + &am35xx_uart4_hwmod, + &omap3xxx_usb_host_hs_hwmod, + &omap3xxx_usb_tll_hs_hwmod, + &omap3xxx_es3plus_mmc1_hwmod, + &omap3xxx_es3plus_mmc2_hwmod, NULL }; @@ -3346,6 +3691,21 @@ int __init omap3xxx_hwmod_init(void) h = omap3430es2plus_hwmods; }; + if (h) { + r = omap_hwmod_register(h); + if (r < 0) + return r; + } + + h = NULL; + if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || + rev == OMAP3430_REV_ES2_1) { + h = omap3430_pre_es3_hwmods; + } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || + rev == OMAP3430_REV_ES3_1_2) { + h = omap3430_es3plus_hwmods; + }; + if (h) r = omap_hwmod_register(h); diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index daaf165af69..f9f15108176 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -70,6 +70,8 @@ static struct omap_hwmod omap44xx_mmc2_hwmod; static struct omap_hwmod omap44xx_mpu_hwmod; static struct omap_hwmod omap44xx_mpu_private_hwmod; static struct omap_hwmod omap44xx_usb_otg_hs_hwmod; +static struct omap_hwmod omap44xx_usb_host_hs_hwmod; +static struct omap_hwmod omap44xx_usb_tll_hs_hwmod; /* * Interconnects omap_hwmod structures @@ -2246,6 +2248,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | SIDLE_SMART_WKUP), + .clockact = CLOCKACT_TEST_ICLK, .sysc_fields = &omap_hwmod_sysc_type1, }; @@ -2300,7 +2303,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = { .name = "i2c1", .class = &omap44xx_i2c_hwmod_class, .clkdm_name = "l4_per_clkdm", - .flags = HWMOD_16BIT_REG, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap44xx_i2c1_irqs, .sdma_reqs = omap44xx_i2c1_sdma_reqs, .main_clk = "i2c1_fck", @@ -2356,7 +2359,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = { .name = "i2c2", .class = &omap44xx_i2c_hwmod_class, .clkdm_name = "l4_per_clkdm", - .flags = HWMOD_16BIT_REG, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap44xx_i2c2_irqs, .sdma_reqs = omap44xx_i2c2_sdma_reqs, .main_clk = "i2c2_fck", @@ -2412,7 +2415,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = { .name = "i2c3", .class = &omap44xx_i2c_hwmod_class, .clkdm_name = "l4_per_clkdm", - .flags = HWMOD_16BIT_REG, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap44xx_i2c3_irqs, .sdma_reqs = omap44xx_i2c3_sdma_reqs, .main_clk = "i2c3_fck", @@ -2468,7 +2471,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = { .name = "i2c4", .class = &omap44xx_i2c_hwmod_class, .clkdm_name = "l4_per_clkdm", - .flags = HWMOD_16BIT_REG, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap44xx_i2c4_irqs, .sdma_reqs = omap44xx_i2c4_sdma_reqs, .main_clk = "i2c4_fck", @@ -5276,6 +5279,207 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = { .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), }; +/* + * 'usb_host_hs' class + * high-speed multi-port usb host controller + */ +static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { + .master = &omap44xx_usb_host_hs_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { + .name = "usb_host_hs", + .sysc = &omap44xx_usb_host_hs_sysc, +}; + +static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = { + &omap44xx_usb_host_hs__l3_main_2, +}; + +static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { + { + .name = "uhh", + .pa_start = 0x4a064000, + .pa_end = 0x4a0647ff, + .flags = ADDR_TYPE_RT + }, + { + .name = "ohci", + .pa_start = 0x4a064800, + .pa_end = 0x4a064bff, + }, + { + .name = "ehci", + .pa_start = 0x4a064c00, + .pa_end = 0x4a064fff, + }, + {} +}; + +static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { + { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, + { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_usb_host_hs_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_usb_host_hs_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = { + &omap44xx_l4_cfg__usb_host_hs, +}; + +static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { + .name = "usb_host_hs", + .class = &omap44xx_usb_host_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .main_clk = "usb_host_hs_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .mpu_irqs = omap44xx_usb_host_hs_irqs, + .slaves = omap44xx_usb_host_hs_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_slaves), + .masters = omap44xx_usb_host_hs_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_masters), + + /* + * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock + * id: i660 + * + * Description: + * In the following configuration : + * - USBHOST module is set to smart-idle mode + * - PRCM asserts idle_req to the USBHOST module ( This typically + * happens when the system is going to a low power mode : all ports + * have been suspended, the master part of the USBHOST module has + * entered the standby state, and SW has cut the functional clocks) + * - an USBHOST interrupt occurs before the module is able to answer + * idle_ack, typically a remote wakeup IRQ. + * Then the USB HOST module will enter a deadlock situation where it + * is no more accessible nor functional. + * + * Workaround: + * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE + */ + + /* + * Errata: USB host EHCI may stall when entering smart-standby mode + * Id: i571 + * + * Description: + * When the USBHOST module is set to smart-standby mode, and when it is + * ready to enter the standby state (i.e. all ports are suspended and + * all attached devices are in suspend mode), then it can wrongly assert + * the Mstandby signal too early while there are still some residual OCP + * transactions ongoing. If this condition occurs, the internal state + * machine may go to an undefined state and the USB link may be stuck + * upon the next resume. + * + * Workaround: + * Don't use smart standby; use only force standby, + * hence HWMOD_SWSUP_MSTANDBY + */ + + /* + * During system boot; If the hwmod framework resets the module + * the module will have smart idle settings; which can lead to deadlock + * (above Errata Id:i660); so, dont reset the module during boot; + * Use HWMOD_INIT_NO_RESET. + */ + + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | + HWMOD_INIT_NO_RESET, +}; + +/* + * 'usb_tll_hs' class + * usb_tll_hs module is the adapter on the usb_host_hs ports + */ +static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { + .name = "usb_tll_hs", + .sysc = &omap44xx_usb_tll_hs_sysc, +}; + +static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { + { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { + { + .name = "tll", + .pa_start = 0x4a062000, + .pa_end = 0x4a063fff, + .flags = ADDR_TYPE_RT + }, + {} +}; + +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_usb_tll_hs_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_usb_tll_hs_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = { + &omap44xx_l4_cfg__usb_tll_hs, +}; + +static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { + .name = "usb_tll_hs", + .class = &omap44xx_usb_tll_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .main_clk = "usb_tll_hs_ick", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .mpu_irqs = omap44xx_usb_tll_hs_irqs, + .slaves = omap44xx_usb_tll_hs_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves), +}; + static __initdata struct omap_hwmod *omap44xx_hwmods[] = { /* dmm class */ @@ -5415,13 +5619,16 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { &omap44xx_uart3_hwmod, &omap44xx_uart4_hwmod, + /* usb host class */ + &omap44xx_usb_host_hs_hwmod, + &omap44xx_usb_tll_hs_hwmod, + /* usb_otg_hs class */ &omap44xx_usb_otg_hs_hwmod, /* wd_timer class */ &omap44xx_wd_timer2_hwmod, &omap44xx_wd_timer3_hwmod, - NULL, }; diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 0363dcb0ef9..da2d80f5fcb 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -201,6 +201,8 @@ #define OMAP3430_EN_MMC2_SHIFT 25 #define OMAP3430_EN_MMC1_MASK (1 << 24) #define OMAP3430_EN_MMC1_SHIFT 24 +#define OMAP3430_EN_UART4_MASK (1 << 23) +#define OMAP3430_EN_UART4_SHIFT 23 #define OMAP3430_EN_MCSPI4_MASK (1 << 21) #define OMAP3430_EN_MCSPI4_SHIFT 21 #define OMAP3430_EN_MCSPI3_MASK (1 << 20) diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index 5ceafdccc45..3638e5c12b7 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c @@ -14,8 +14,8 @@ #include <linux/init.h> #include <linux/mbus.h> #include <linux/io.h> -#include <linux/errno.h> #include <mach/hardware.h> +#include <plat/addr-map.h> #include "common.h" /* @@ -41,7 +41,6 @@ /* * Generic Address Decode Windows bit settings */ -#define TARGET_DDR 0 #define TARGET_DEV_BUS 1 #define TARGET_PCI 3 #define TARGET_PCIE 4 @@ -57,27 +56,10 @@ #define ATTR_DEV_BOOT 0xf #define ATTR_SRAM 0x0 -/* - * Helpers to get DDR bank info - */ -#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x)) -#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) << 3)) -#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) << 3)) - -/* - * CPU Address Decode Windows registers - */ -#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x)) -#define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4)) -#define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4)) -#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4)) -#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4)) - - -struct mbus_dram_target_info orion5x_mbus_dram_info; static int __initdata win_alloc_count; -static int __init orion5x_cpu_win_can_remap(int win) +static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg, + const int win) { u32 dev, rev; @@ -91,116 +73,82 @@ static int __init orion5x_cpu_win_can_remap(int win) return 0; } -static int __init setup_cpu_win(int win, u32 base, u32 size, - u8 target, u8 attr, int remap) -{ - if (win >= 8) { - printk(KERN_ERR "setup_cpu_win: trying to allocate " - "window %d\n", win); - return -ENOSPC; - } - - writel(base & 0xffff0000, CPU_WIN_BASE(win)); - writel(((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1, - CPU_WIN_CTRL(win)); - - if (orion5x_cpu_win_can_remap(win)) { - if (remap < 0) - remap = base; - - writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win)); - writel(0, CPU_WIN_REMAP_HI(win)); - } - return 0; -} - -void __init orion5x_setup_cpu_mbus_bridge(void) -{ - int i; - int cs; +/* + * Description of the windows needed by the platform code + */ +static struct __initdata orion_addr_map_cfg addr_map_cfg = { + .num_wins = 8, + .cpu_win_can_remap = cpu_win_can_remap, + .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE, +}; +static const struct __initdata orion_addr_map_info addr_map_info[] = { /* - * First, disable and clear windows. + * Setup windows for PCI+PCIe IO+MEM space. */ - for (i = 0; i < 8; i++) { - writel(0, CPU_WIN_BASE(i)); - writel(0, CPU_WIN_CTRL(i)); - if (orion5x_cpu_win_can_remap(i)) { - writel(0, CPU_WIN_REMAP_LO(i)); - writel(0, CPU_WIN_REMAP_HI(i)); - } - } + { 0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, + TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE + }, + { 1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, + TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE + }, + { 2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE, + TARGET_PCIE, ATTR_PCIE_MEM, -1 + }, + { 3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, + TARGET_PCI, ATTR_PCI_MEM, -1 + }, + /* End marker */ + { -1, 0, 0, 0, 0, 0 } +}; +void __init orion5x_setup_cpu_mbus_bridge(void) +{ /* - * Setup windows for PCI+PCIe IO+MEM space. + * Disable, clear and configure windows. */ - setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, - TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE); - setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, - TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE); - setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE, - TARGET_PCIE, ATTR_PCIE_MEM, -1); - setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, - TARGET_PCI, ATTR_PCI_MEM, -1); + orion_config_wins(&addr_map_cfg, addr_map_info); win_alloc_count = 4; /* * Setup MBUS dram target info. */ - orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; - - for (i = 0, cs = 0; i < 4; i++) { - u32 base = readl(DDR_BASE_CS(i)); - u32 size = readl(DDR_SIZE_CS(i)); - - /* - * Chip select enabled? - */ - if (size & 1) { - struct mbus_dram_window *w; - - w = &orion5x_mbus_dram_info.cs[cs++]; - w->cs_index = i; - w->mbus_attr = 0xf & ~(1 << i); - w->base = base & 0xffff0000; - w->size = (size | 0x0000ffff) + 1; - } - } - orion5x_mbus_dram_info.num_cs = cs; + orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE); } void __init orion5x_setup_dev_boot_win(u32 base, u32 size) { - setup_cpu_win(win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); + orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, + TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); } void __init orion5x_setup_dev0_win(u32 base, u32 size) { - setup_cpu_win(win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_CS0, -1); + orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, + TARGET_DEV_BUS, ATTR_DEV_CS0, -1); } void __init orion5x_setup_dev1_win(u32 base, u32 size) { - setup_cpu_win(win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_CS1, -1); + orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, + TARGET_DEV_BUS, ATTR_DEV_CS1, -1); } void __init orion5x_setup_dev2_win(u32 base, u32 size) { - setup_cpu_win(win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_CS2, -1); + orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, + TARGET_DEV_BUS, ATTR_DEV_CS2, -1); } void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) { - setup_cpu_win(win_alloc_count++, base, size, - TARGET_PCIE, ATTR_PCIE_WA, -1); + orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, + TARGET_PCIE, ATTR_PCIE_WA, -1); } -int __init orion5x_setup_sram_win(void) +void __init orion5x_setup_sram_win(void) { - return setup_cpu_win(win_alloc_count++, ORION5X_SRAM_PHYS_BASE, - ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); + orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, + ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE, + TARGET_SRAM, ATTR_SRAM, -1); } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 41127e80cc1..0e28bae20bd 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -15,7 +15,6 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> #include <linux/serial_8250.h> -#include <linux/mbus.h> #include <linux/mv643xx_i2c.h> #include <linux/ata_platform.h> #include <linux/delay.h> @@ -32,6 +31,7 @@ #include <plat/orion_nand.h> #include <plat/time.h> #include <plat/common.h> +#include <plat/addr-map.h> #include "common.h" /***************************************************************************** @@ -72,8 +72,7 @@ void __init orion5x_map_io(void) ****************************************************************************/ void __init orion5x_ehci0_init(void) { - orion_ehci_init(&orion5x_mbus_dram_info, - ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); + orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); } @@ -82,8 +81,7 @@ void __init orion5x_ehci0_init(void) ****************************************************************************/ void __init orion5x_ehci1_init(void) { - orion_ehci_1_init(&orion5x_mbus_dram_info, - ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); + orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); } @@ -92,7 +90,7 @@ void __init orion5x_ehci1_init(void) ****************************************************************************/ void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) { - orion_ge00_init(eth_data, &orion5x_mbus_dram_info, + orion_ge00_init(eth_data, ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, IRQ_ORION5X_ETH_ERR, orion5x_tclk); } @@ -122,8 +120,7 @@ void __init orion5x_i2c_init(void) ****************************************************************************/ void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) { - orion_sata_init(sata_data, &orion5x_mbus_dram_info, - ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); + orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); } @@ -159,8 +156,7 @@ void __init orion5x_uart1_init(void) ****************************************************************************/ void __init orion5x_xor_init(void) { - orion_xor0_init(&orion5x_mbus_dram_info, - ORION5X_XOR_PHYS_BASE, + orion_xor0_init(ORION5X_XOR_PHYS_BASE, ORION5X_XOR_PHYS_BASE + 0x200, IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); } @@ -170,12 +166,7 @@ void __init orion5x_xor_init(void) ****************************************************************************/ static void __init orion5x_crypto_init(void) { - int ret; - - ret = orion5x_setup_sram_win(); - if (ret) - return; - + orion5x_setup_sram_win(); orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, SZ_8K, IRQ_ORION5X_CESA); } diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index 37ef18de61b..d2513ac79ff 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -20,14 +20,13 @@ extern struct sys_timer orion5x_timer; * functions to map its interfaces and by the machine-setup to map its on- * board devices. Details in /mach-orion/addr-map.c */ -extern struct mbus_dram_target_info orion5x_mbus_dram_info; void orion5x_setup_cpu_mbus_bridge(void); void orion5x_setup_dev_boot_win(u32 base, u32 size); void orion5x_setup_dev0_win(u32 base, u32 size); void orion5x_setup_dev1_win(u32 base, u32 size); void orion5x_setup_dev2_win(u32 base, u32 size); void orion5x_setup_pcie_wa_win(u32 base, u32 size); -int orion5x_setup_sram_win(void); +void orion5x_setup_sram_win(void); void orion5x_ehci0_init(void); void orion5x_ehci1_init(void); diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 0a28bbc7689..2745f5d95b3 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -69,7 +69,7 @@ ******************************************************************************/ #define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) - +#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE | 0x1500) #define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) #define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) #define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c index b6ddd7a5db6..5b70026f478 100644 --- a/arch/arm/mach-orion5x/mpp.c +++ b/arch/arm/mach-orion5x/mpp.c @@ -10,7 +10,6 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/mbus.h> #include <linux/io.h> #include <mach/hardware.h> #include <plat/mpp.h> diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index bc4a920e26e..a494c470e3e 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -18,6 +18,7 @@ #include <asm/irq.h> #include <asm/mach/pci.h> #include <plat/pcie.h> +#include <plat/addr-map.h> #include "common.h" /***************************************************************************** @@ -145,7 +146,7 @@ static int __init pcie_setup(struct pci_sys_data *sys) /* * Generic PCIe unit setup. */ - orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); + orion_pcie_setup(PCIE_BASE); /* * Check whether to apply Orion-1/Orion-NAS PCIe config @@ -477,7 +478,7 @@ static int __init pci_setup(struct pci_sys_data *sys) /* * Point PCI unit MBUS decode windows to DRAM space. */ - orion5x_setup_pci_wins(&orion5x_mbus_dram_info); + orion5x_setup_pci_wins(&orion_mbus_dram_info); /* * Master + Slave enable diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c index febee47bc11..a2e8ae8b582 100644 --- a/arch/arm/mach-picoxcell/common.c +++ b/arch/arm/mach-picoxcell/common.c @@ -7,6 +7,7 @@ * * All enquiries to support@picochip.com */ +#include <linux/delay.h> #include <linux/irq.h> #include <linux/irqdomain.h> #include <linux/of.h> @@ -23,6 +24,26 @@ #include "common.h" +#define WDT_CTRL_REG_EN_MASK (1 << 0) +#define WDT_CTRL_REG_OFFS (0x00) +#define WDT_TIMEOUT_REG_OFFS (0x04) +static void __iomem *wdt_regs; + +/* + * The machine restart method can be called from an atomic context so we won't + * be able to ioremap the regs then. + */ +static void picoxcell_setup_restart(void) +{ + struct device_node *np = of_find_compatible_node(NULL, NULL, + "snps,dw-apb-wdg"); + if (WARN(!np, "unable to setup watchdog restart")) + return; + + wdt_regs = of_iomap(np, 0); + WARN(!wdt_regs, "failed to remap watchdog regs"); +} + static struct map_desc io_map __initdata = { .virtual = PHYS_TO_IO(PICOXCELL_PERIPH_BASE), .pfn = __phys_to_pfn(PICOXCELL_PERIPH_BASE), @@ -38,6 +59,7 @@ static void __init picoxcell_map_io(void) static void __init picoxcell_init_machine(void) { of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + picoxcell_setup_restart(); } static const char *picoxcell_dt_match[] = { @@ -56,6 +78,20 @@ static void __init picoxcell_init_irq(void) of_irq_init(vic_of_match); } +static void picoxcell_wdt_restart(char mode, const char *cmd) +{ + /* + * Configure the watchdog to reset with the shortest possible timeout + * and give it chance to do the reset. + */ + if (wdt_regs) { + writel_relaxed(WDT_CTRL_REG_EN_MASK, wdt_regs + WDT_CTRL_REG_OFFS); + writel_relaxed(0, wdt_regs + WDT_TIMEOUT_REG_OFFS); + /* No sleeping, possibly atomic. */ + mdelay(500); + } +} + DT_MACHINE_START(PICOXCELL, "Picochip picoXcell") .map_io = picoxcell_map_io, .nr_irqs = NR_IRQS_LEGACY, @@ -64,4 +100,5 @@ DT_MACHINE_START(PICOXCELL, "Picochip picoXcell") .timer = &picoxcell_timer, .init_machine = picoxcell_init_machine, .dt_compat = picoxcell_dt_match, + .restart = picoxcell_wdt_restart, MACHINE_END diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 6826faeecc6..23be34b3bb6 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c @@ -22,6 +22,12 @@ #include "ste-dma40-db8500.h" /* + * v2 has a new version of this block that need to be forced, the number found + * in hardware is incorrect + */ +#define U8500_SDI_V2_PERIPHID 0x10480180 + +/* * SDI 0 (MicroSD slot) */ @@ -117,10 +123,7 @@ static void sdi0_configure(void) gpio_direction_output(sdi0_en, 1); /* Add the device, force v2 to subrevision 1 */ - if (cpu_is_u8500v2()) - db8500_add_sdi0(&mop500_sdi0_data, 0x10480180); - else - db8500_add_sdi0(&mop500_sdi0_data, 0); + db8500_add_sdi0(&mop500_sdi0_data, U8500_SDI_V2_PERIPHID); } void mop500_sdi_tc35892_init(void) @@ -132,6 +135,42 @@ void mop500_sdi_tc35892_init(void) } /* + * SDI1 (SDIO WLAN) + */ +#ifdef CONFIG_STE_DMA40 +static struct stedma40_chan_cfg sdi1_dma_cfg_rx = { + .mode = STEDMA40_MODE_LOGICAL, + .dir = STEDMA40_PERIPH_TO_MEM, + .src_dev_type = DB8500_DMA_DEV32_SD_MM1_RX, + .dst_dev_type = STEDMA40_DEV_DST_MEMORY, + .src_info.data_width = STEDMA40_WORD_WIDTH, + .dst_info.data_width = STEDMA40_WORD_WIDTH, +}; + +static struct stedma40_chan_cfg sdi1_dma_cfg_tx = { + .mode = STEDMA40_MODE_LOGICAL, + .dir = STEDMA40_MEM_TO_PERIPH, + .src_dev_type = STEDMA40_DEV_SRC_MEMORY, + .dst_dev_type = DB8500_DMA_DEV32_SD_MM1_TX, + .src_info.data_width = STEDMA40_WORD_WIDTH, + .dst_info.data_width = STEDMA40_WORD_WIDTH, +}; +#endif + +static struct mmci_platform_data mop500_sdi1_data = { + .ocr_mask = MMC_VDD_29_30, + .f_max = 50000000, + .capabilities = MMC_CAP_4_BIT_DATA, + .gpio_cd = -1, + .gpio_wp = -1, +#ifdef CONFIG_STE_DMA40 + .dma_filter = stedma40_filter, + .dma_rx_param = &sdi1_dma_cfg_rx, + .dma_tx_param = &sdi1_dma_cfg_tx, +#endif +}; + +/* * SDI 2 (POP eMMC, not on DB8500ed) */ @@ -158,7 +197,8 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = { static struct mmci_platform_data mop500_sdi2_data = { .ocr_mask = MMC_VDD_165_195, .f_max = 50000000, - .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | + MMC_CAP_MMC_HIGHSPEED, .gpio_cd = -1, .gpio_wp = -1, #ifdef CONFIG_STE_DMA40 @@ -208,20 +248,10 @@ static struct mmci_platform_data mop500_sdi4_data = { void __init mop500_sdi_init(void) { - u32 periphid = 0; - - /* v2 has a new version of this block that need to be forced */ - if (cpu_is_u8500v2()) - periphid = 0x10480180; - /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */ - if (!cpu_is_u8500v10()) - mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED; - - db8500_add_sdi2(&mop500_sdi2_data, periphid); - + /* PoP:ed eMMC */ + db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID); /* On-board eMMC */ - db8500_add_sdi4(&mop500_sdi4_data, periphid); - + db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); /* * On boards with the TC35892 GPIO expander, sdi0 will finally * be added when the TC35892 initializes and calls @@ -231,13 +261,9 @@ void __init mop500_sdi_init(void) void __init snowball_sdi_init(void) { - u32 periphid = 0x10480180; - - mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED; - /* On-board eMMC */ - db8500_add_sdi4(&mop500_sdi4_data, periphid); - + db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); + /* External Micro SD slot */ mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO; mop500_sdi0_data.cd_invert = true; sdi0_en = SNOWBALL_SDMMC_EN_GPIO; @@ -247,17 +273,15 @@ void __init snowball_sdi_init(void) void __init hrefv60_sdi_init(void) { - u32 periphid = 0x10480180; - - mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED; - - db8500_add_sdi2(&mop500_sdi2_data, periphid); - + /* PoP:ed eMMC */ + db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID); /* On-board eMMC */ - db8500_add_sdi4(&mop500_sdi4_data, periphid); - + db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); + /* External Micro SD slot */ mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO; sdi0_en = HREFV60_SDMMC_EN_GPIO; sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO; sdi0_configure(); + /* WLAN SDIO channel */ + db8500_add_sdi1(&mop500_sdi1_data, U8500_SDI_V2_PERIPHID); } diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index de1f5f8f733..9361a529017 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -673,7 +673,7 @@ static void __init hrefv60_init_machine(void) ARRAY_SIZE(mop500_platform_devs)); mop500_i2c_init(); - mop500_sdi_init(); + hrefv60_sdi_init(); mop500_spi_init(); mop500_uart_init(); diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index de18a2a23e6..f926d3db620 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -7,40 +7,77 @@ #ifndef __BOARD_MOP500_H #define __BOARD_MOP500_H -/* snowball GPIO for MMC card */ -#define SNOWBALL_SDMMC_EN_GPIO 217 -#define SNOWBALL_SDMMC_1V8_3V_GPIO 228 -#define SNOWBALL_SDMMC_CD_GPIO 218 +/* Snowball specific GPIO assignments, this board has no GPIO expander */ +#define SNOWBALL_ACCEL_INT1_GPIO 163 +#define SNOWBALL_ACCEL_INT2_GPIO 164 +#define SNOWBALL_MAGNET_DRDY_GPIO 165 +#define SNOWBALL_SDMMC_EN_GPIO 217 +#define SNOWBALL_SDMMC_1V8_3V_GPIO 228 +#define SNOWBALL_SDMMC_CD_GPIO 218 /* HREFv60-specific GPIO assignments, this board has no GPIO expander */ -#define HREFV60_TOUCH_RST_GPIO 143 -#define HREFV60_PROX_SENSE_GPIO 217 -#define HREFV60_HAL_SW_GPIO 145 -#define HREFV60_SDMMC_EN_GPIO 169 #define HREFV60_SDMMC_1V8_3V_GPIO 5 -#define HREFV60_SDMMC_CD_GPIO 95 -#define HREFV60_ACCEL_INT1_GPIO 82 -#define HREFV60_ACCEL_INT2_GPIO 83 +#define HREFV60_CAMERA_FLASH_ENABLE 21 #define HREFV60_MAGNET_DRDY_GPIO 32 #define HREFV60_DISP1_RST_GPIO 65 #define HREFV60_DISP2_RST_GPIO 66 +#define HREFV60_ACCEL_INT1_GPIO 82 +#define HREFV60_ACCEL_INT2_GPIO 83 +#define HREFV60_SDMMC_CD_GPIO 95 +#define HREFV60_XSHUTDOWN_SECONDARY_SENSOR 140 +#define HREFV60_TOUCH_RST_GPIO 143 +#define HREFV60_HAL_SW_GPIO 145 +#define HREFV60_SDMMC_EN_GPIO 169 +#define HREFV60_MMIO_XENON_CHARGE 170 +#define HREFV60_PROX_SENSE_GPIO 217 + +/* MOP500 generic GPIOs */ +#define CAMERA_FLASH_INT_PIN 7 +#define CYPRESS_TOUCH_INT_PIN 84 +#define XSHUTDOWN_PRIMARY_SENSOR 141 +#define XSHUTDOWN_SECONDARY_SENSOR 142 +#define CYPRESS_TOUCH_RST_GPIO 143 +#define MOP500_HDMI_RST_GPIO 196 +#define CYPRESS_SLAVE_SELECT_GPIO 216 /* GPIOs on the TC35892 expander */ #define MOP500_EGPIO(x) (NOMADIK_NR_GPIO + (x)) +#define GPIO_MAGNET_DRDY MOP500_EGPIO(1) #define GPIO_SDMMC_CD MOP500_EGPIO(3) +#define GPIO_CAMERA_FLASH_ENABLE MOP500_EGPIO(4) +#define GPIO_MMIO_XENON_CHARGE MOP500_EGPIO(5) #define GPIO_PROX_SENSOR MOP500_EGPIO(7) +#define GPIO_HAL_SENSOR MOP500_EGPIO(8) +#define GPIO_ACCEL_INT1 MOP500_EGPIO(10) +#define GPIO_ACCEL_INT2 MOP500_EGPIO(11) #define GPIO_BU21013_CS MOP500_EGPIO(13) +#define MOP500_DISP2_RST_GPIO MOP500_EGPIO(14) +#define MOP500_DISP1_RST_GPIO MOP500_EGPIO(15) #define GPIO_SDMMC_EN MOP500_EGPIO(17) #define GPIO_SDMMC_1V8_3V_SEL MOP500_EGPIO(18) #define MOP500_EGPIO_END MOP500_EGPIO(24) -/* GPIOs on the AB8500 mixed-signals circuit */ -#define MOP500_AB8500_GPIO(x) (MOP500_EGPIO_END + (x)) +/* + * GPIOs on the AB8500 mixed-signals circuit + * Notice that we subtract 1 from the number passed into the macro, this is + * because the AB8500 GPIO pins are enumbered starting from 1, so the value in + * parens matches the GPIO pin number in the data sheet. + */ +#define MOP500_AB8500_GPIO(x) (MOP500_EGPIO_END + (x) - 1) +/*Snowball AB8500 GPIO */ +#define SNOWBALL_VSMPS2_1V8_GPIO MOP500_AB8500_PIN_GPIO(1) /* SYSCLKREQ2/GPIO1 */ +#define SNOWBALL_PM_GPIO1_GPIO MOP500_AB8500_PIN_GPIO(2) /* SYSCLKREQ3/GPIO2 */ +#define SNOWBALL_WLAN_CLK_REQ_GPIO MOP500_AB8500_PIN_GPIO(3) /* SYSCLKREQ4/GPIO3 */ +#define SNOWBALL_PM_GPIO4_GPIO MOP500_AB8500_PIN_GPIO(4) /* SYSCLKREQ6/GPIO4 */ +#define SNOWBALL_EN_3V6_GPIO MOP500_AB8500_PIN_GPIO(16) /* PWMOUT3/GPIO16 */ +#define SNOWBALL_PME_ETH_GPIO MOP500_AB8500_PIN_GPIO(24) /* SYSCLKREQ7/GPIO24 */ +#define SNOWBALL_EN_3V3_ETH_GPIO MOP500_AB8500_PIN_GPIO(26) /* GPIO26 */ struct i2c_board_info; extern void mop500_sdi_init(void); extern void snowball_sdi_init(void); +extern void hrefv60_sdi_init(void); extern void mop500_sdi_tc35892_init(void); void __init mop500_u8500uib_init(void); void __init mop500_stuib_init(void); diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c index e832664d1bd..73790753700 100644 --- a/arch/arm/mach-ux500/clock.c +++ b/arch/arm/mach-ux500/clock.c @@ -239,23 +239,6 @@ static void clk_prcmu_disable(struct clk *clk) writel(1 << clk->prcmu_cg_bit, cg_clr_reg); } -/* ED doesn't have the combined set/clr registers */ -static void clk_prcmu_ed_enable(struct clk *clk) -{ - void __iomem *addr = __io_address(U8500_PRCMU_BASE) - + clk->prcmu_cg_mgt; - - writel(readl(addr) | PRCM_MGT_ENABLE, addr); -} - -static void clk_prcmu_ed_disable(struct clk *clk) -{ - void __iomem *addr = __io_address(U8500_PRCMU_BASE) - + clk->prcmu_cg_mgt; - - writel(readl(addr) & ~PRCM_MGT_ENABLE, addr); -} - static struct clkops clk_prcmu_ops = { .enable = clk_prcmu_enable, .disable = clk_prcmu_disable, @@ -267,7 +250,6 @@ static unsigned int clkrst_base[] = { [3] = U8500_CLKRST3_BASE, [5] = U8500_CLKRST5_BASE, [6] = U8500_CLKRST6_BASE, - [7] = U8500_CLKRST7_BASE_ED, }; static void clk_prcc_enable(struct clk *clk) @@ -321,7 +303,6 @@ static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK); static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK); static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK); static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000); -static DEFINE_PRCMU_CLK_RATE(per7clk, 0x0, 16, PER7CLK, 100000000); static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK); static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK); static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK); @@ -351,44 +332,28 @@ static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */ static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); -static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL); -static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL); +static DEFINE_PRCC_CLK(1, spi3, 7, -1, NULL); static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk); static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk); -static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk); +static DEFINE_PRCC_CLK(1, msp1, 4, 4, &clk_msp1clk); static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk); static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk); static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk); static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk); /* Peripheral Cluster #2 */ - -static DEFINE_PRCC_CLK(2, gpio1_ed, 12, -1, NULL); -static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL); -static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL); -static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL); -static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk); -static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, pwl_ed, 3, 1, NULL); -static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL); -static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL); -static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk); - -static DEFINE_PRCC_CLK(2, gpio1_v1, 11, -1, NULL); -static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL); -static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL); -static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL); -static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk); -static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, pwl_v1, 3, 1, NULL); -static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL); -static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL); -static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk); +static DEFINE_PRCC_CLK(2, gpio1, 11, -1, NULL); +static DEFINE_PRCC_CLK(2, ssitx, 10, 7, NULL); +static DEFINE_PRCC_CLK(2, ssirx, 9, 6, NULL); +static DEFINE_PRCC_CLK(2, spi0, 8, -1, NULL); +static DEFINE_PRCC_CLK(2, sdi3, 7, 5, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, sdi1, 6, 4, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, msp2, 5, 3, &clk_msp02clk); +static DEFINE_PRCC_CLK(2, sdi4, 4, 2, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, pwl, 3, 1, NULL); +static DEFINE_PRCC_CLK(2, spi1, 2, -1, NULL); +static DEFINE_PRCC_CLK(2, spi2, 1, -1, NULL); +static DEFINE_PRCC_CLK(2, i2c3, 0, 0, &clk_i2cclk); /* Peripheral Cluster #3 */ static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL); @@ -397,49 +362,34 @@ static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk); static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz); static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk); static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk); -static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk); -static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk); -static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk); -static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk); +static DEFINE_PRCC_CLK(3, ssp1, 2, 2, &clk_sspclk); +static DEFINE_PRCC_CLK(3, ssp0, 1, 1, &clk_sspclk); static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL); /* Peripheral Cluster #4 is in the always on domain */ /* Peripheral Cluster #5 */ static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL); -static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk); -static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL); +static DEFINE_PRCC_CLK(5, usb, 0, 0, NULL); /* Peripheral Cluster #6 */ /* MTU ID in data */ -static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1); -static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0); -static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL); -static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL); +static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 8, -1, NULL, clk_mtu_get_rate, 1); +static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 7, -1, NULL, clk_mtu_get_rate, 0); +static DEFINE_PRCC_CLK(6, cfgreg, 6, 6, NULL); static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); -static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk); -static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL); +static DEFINE_PRCC_CLK(6, unipro, 4, 1, &clk_uniproclk); static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL); static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL); static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL); -static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk); -static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk); - -/* Peripheral Cluster #7 */ - -static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL); -/* MTU ID in data */ -static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1); -static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0); -static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL); -static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL); +static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk); static struct clk clk_dummy_apb_pclk = { .name = "apb_pclk", }; -static struct clk_lookup u8500_common_clks[] = { +static struct clk_lookup u8500_clks[] = { CLK(dummy_apb_pclk, NULL, "apb_pclk"), /* Peripheral Cluster #1 */ @@ -494,83 +444,41 @@ static struct clk_lookup u8500_common_clks[] = { CLK(dmaclk, "dma40.0", NULL), CLK(b2r2clk, "b2r2", NULL), CLK(tvclk, "tv", NULL), -}; -static struct clk_lookup u8500_ed_clks[] = { - /* Peripheral Cluster #1 */ - CLK(spi3_ed, "spi3", NULL), - CLK(msp1_ed, "msp1", NULL), - - /* Peripheral Cluster #2 */ - CLK(gpio1_ed, "gpio.6", NULL), - CLK(gpio1_ed, "gpio.7", NULL), - CLK(ssitx_ed, "ssitx", NULL), - CLK(ssirx_ed, "ssirx", NULL), - CLK(spi0_ed, "spi0", NULL), - CLK(sdi3_ed, "sdi3", NULL), - CLK(sdi1_ed, "sdi1", NULL), - CLK(msp2_ed, "msp2", NULL), - CLK(sdi4_ed, "sdi4", NULL), - CLK(pwl_ed, "pwl", NULL), - CLK(spi1_ed, "spi1", NULL), - CLK(spi2_ed, "spi2", NULL), - CLK(i2c3_ed, "nmk-i2c.3", NULL), - - /* Peripheral Cluster #3 */ - CLK(ssp1_ed, "ssp1", NULL), - CLK(ssp0_ed, "ssp0", NULL), - - /* Peripheral Cluster #5 */ - CLK(usb_ed, "musb-ux500.0", "usb"), - - /* Peripheral Cluster #6 */ - CLK(dmc_ed, "dmc", NULL), - CLK(cryp1_ed, "cryp1", NULL), - CLK(rng_ed, "rng", NULL), - - /* Peripheral Cluster #7 */ - CLK(tzpc0_ed, "tzpc0", NULL), - CLK(mtu1_ed, "mtu1", NULL), - CLK(mtu0_ed, "mtu0", NULL), - CLK(wdg_ed, "wdg", NULL), - CLK(cfgreg_ed, "cfgreg", NULL), -}; - -static struct clk_lookup u8500_v1_clks[] = { /* Peripheral Cluster #1 */ CLK(i2c4, "nmk-i2c.4", NULL), - CLK(spi3_v1, "spi3", NULL), - CLK(msp1_v1, "msp1", NULL), + CLK(spi3, "spi3", NULL), + CLK(msp1, "msp1", NULL), /* Peripheral Cluster #2 */ - CLK(gpio1_v1, "gpio.6", NULL), - CLK(gpio1_v1, "gpio.7", NULL), - CLK(ssitx_v1, "ssitx", NULL), - CLK(ssirx_v1, "ssirx", NULL), - CLK(spi0_v1, "spi0", NULL), - CLK(sdi3_v1, "sdi3", NULL), - CLK(sdi1_v1, "sdi1", NULL), - CLK(msp2_v1, "msp2", NULL), - CLK(sdi4_v1, "sdi4", NULL), - CLK(pwl_v1, "pwl", NULL), - CLK(spi1_v1, "spi1", NULL), - CLK(spi2_v1, "spi2", NULL), - CLK(i2c3_v1, "nmk-i2c.3", NULL), + CLK(gpio1, "gpio.6", NULL), + CLK(gpio1, "gpio.7", NULL), + CLK(ssitx, "ssitx", NULL), + CLK(ssirx, "ssirx", NULL), + CLK(spi0, "spi0", NULL), + CLK(sdi3, "sdi3", NULL), + CLK(sdi1, "sdi1", NULL), + CLK(msp2, "msp2", NULL), + CLK(sdi4, "sdi4", NULL), + CLK(pwl, "pwl", NULL), + CLK(spi1, "spi1", NULL), + CLK(spi2, "spi2", NULL), + CLK(i2c3, "nmk-i2c.3", NULL), /* Peripheral Cluster #3 */ - CLK(ssp1_v1, "ssp1", NULL), - CLK(ssp0_v1, "ssp0", NULL), + CLK(ssp1, "ssp1", NULL), + CLK(ssp0, "ssp0", NULL), /* Peripheral Cluster #5 */ - CLK(usb_v1, "musb-ux500.0", "usb"), + CLK(usb, "musb-ux500.0", "usb"), /* Peripheral Cluster #6 */ - CLK(mtu1_v1, "mtu1", NULL), - CLK(mtu0_v1, "mtu0", NULL), - CLK(cfgreg_v1, "cfgreg", NULL), + CLK(mtu1, "mtu1", NULL), + CLK(mtu0, "mtu0", NULL), + CLK(cfgreg, "cfgreg", NULL), CLK(hash1, "hash1", NULL), - CLK(unipro_v1, "unipro", NULL), - CLK(rng_v1, "rng", NULL), + CLK(unipro, "unipro", NULL), + CLK(rng, "rng", NULL), /* PRCMU level clock gating */ @@ -743,7 +651,7 @@ err_out: late_initcall(clk_debugfs_init); #endif /* defined(CONFIG_DEBUG_FS) */ -unsigned long clk_smp_twd_rate = 400000000; +unsigned long clk_smp_twd_rate = 500000000; unsigned long clk_smp_twd_get_rate(struct clk *clk) { @@ -769,7 +677,7 @@ static int clk_twd_cpufreq_transition(struct notifier_block *nb, if (state == CPUFREQ_PRECHANGE) { /* Save frequency in simple Hz */ - clk_smp_twd_rate = f->new * 1000; + clk_smp_twd_rate = (f->new * 1000) / 2; } return NOTIFY_OK; @@ -790,11 +698,7 @@ late_initcall(clk_init_smp_twd_cpufreq); int __init clk_init(void) { - if (cpu_is_u8500ed()) { - clk_prcmu_ops.enable = clk_prcmu_ed_enable; - clk_prcmu_ops.disable = clk_prcmu_ed_disable; - clk_per6clk.rate = 100000000; - } else if (cpu_is_u5500()) { + if (cpu_is_u5500()) { /* Clock tree for U5500 not implemented yet */ clk_prcc_ops.enable = clk_prcc_ops.disable = NULL; clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL; @@ -802,20 +706,11 @@ int __init clk_init(void) clk_sdmmcclk.rate = 99900000; } - clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); - if (cpu_is_u8500ed()) - clkdev_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks)); - else - clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks)); - + clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); clkdev_add(&clk_smp_twd_lookup); #ifdef CONFIG_DEBUG_FS - clk_debugfs_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); - if (cpu_is_u8500ed()) - clk_debugfs_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks)); - else - clk_debugfs_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks)); + clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); #endif return 0; } diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c index 5323286b265..18aa5c05c69 100644 --- a/arch/arm/mach-ux500/cpu-db5500.c +++ b/arch/arm/mach-ux500/cpu-db5500.c @@ -46,26 +46,6 @@ static struct map_desc u5500_io_desc[] __initdata = { __IO_DEV_DESC(U5500_PRCMU_TCDM_BASE, SZ_4K), }; -static struct resource db5500_pmu_resources[] = { - [0] = { - .start = IRQ_DB5500_PMU0, - .end = IRQ_DB5500_PMU0, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = IRQ_DB5500_PMU1, - .end = IRQ_DB5500_PMU1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device db5500_pmu_device = { - .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, - .num_resources = ARRAY_SIZE(db5500_pmu_resources), - .resource = db5500_pmu_resources, -}; - static struct resource mbox0_resources[] = { { .name = "mbox_peer", @@ -151,7 +131,6 @@ static struct platform_device mbox2_device = { }; static struct platform_device *db5500_platform_devs[] __initdata = { - &db5500_pmu_device, &mbox0_device, &mbox1_device, &mbox2_device, @@ -192,6 +171,25 @@ void __init u5500_map_io(void) _PRCMU_BASE = __io_address(U5500_PRCMU_BASE); } +static void __init db5500_pmu_init(void) +{ + struct resource res[] = { + [0] = { + .start = IRQ_DB5500_PMU0, + .end = IRQ_DB5500_PMU0, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = IRQ_DB5500_PMU1, + .end = IRQ_DB5500_PMU1, + .flags = IORESOURCE_IRQ, + }, + }; + + platform_device_register_simple("arm-pmu", ARM_PMU_DEVICE_CPU, + res, ARRAY_SIZE(res)); +} + static int usb_db5500_rx_dma_cfg[] = { DB5500_DMA_DEV4_USB_OTG_IEP_1_9, DB5500_DMA_DEV5_USB_OTG_IEP_2_10, @@ -217,6 +215,7 @@ static int usb_db5500_tx_dma_cfg[] = { void __init u5500_init_devices(void) { db5500_add_gpios(); + db5500_pmu_init(); db5500_dma_init(); db5500_add_rtc(); db5500_add_usb(usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg); diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 7f2729c05db..7176ee7491a 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2008-2009 ST-Ericsson + * Copyright (C) 2008-2009 ST-Ericsson SA * * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> * @@ -53,19 +53,6 @@ static struct map_desc u8500_io_desc[] __initdata = { __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), -}; - -static struct map_desc u8500_ed_io_desc[] __initdata = { - __IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K), - __IO_DEV_DESC(U8500_CLKRST7_BASE_ED, SZ_8K), -}; - -static struct map_desc u8500_v1_io_desc[] __initdata = { - __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), - __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE_V1, SZ_4K), -}; - -static struct map_desc u8500_v2_io_desc[] __initdata = { __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), }; @@ -80,13 +67,6 @@ void __init u8500_map_io(void) iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); - if (cpu_is_u8500ed()) - iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc)); - else if (cpu_is_u8500v1()) - iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc)); - else if (cpu_is_u8500v2()) - iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc)); - _PRCMU_BASE = __io_address(U8500_PRCMU_BASE); } @@ -155,12 +135,9 @@ static resource_size_t __initdata db8500_gpio_base[] = { static void __init db8500_add_gpios(void) { struct nmk_gpio_platform_data pdata = { - /* No custom data yet */ + .supports_sleepmode = true, }; - if (cpu_is_u8500v2()) - pdata.supports_sleepmode = true; - dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base), IRQ_DB8500_GPIO0, &pdata); } @@ -192,9 +169,6 @@ static int usb_db8500_tx_dma_cfg[] = { */ void __init u8500_init_devices(void) { - if (cpu_is_u8500ed()) - dma40_u8500ed_fixup(); - db8500_add_rtc(); db8500_add_gpios(); db8500_add_usb(usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 73b17404b19..a7c6cdc9b11 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -166,16 +166,6 @@ struct platform_device u8500_dma40_device = { .resource = dma40_resources }; -void dma40_u8500ed_fixup(void) -{ - dma40_plat_data.memcpy = NULL; - dma40_plat_data.memcpy_len = 0; - dma40_resources[0].start = U8500_DMA_BASE_ED; - dma40_resources[0].end = U8500_DMA_BASE_ED + SZ_4K - 1; - dma40_resources[1].start = U8500_DMA_LCPA_BASE_ED; - dma40_resources[1].end = U8500_DMA_LCPA_BASE_ED + 2 * SZ_1K - 1; -} - struct resource keypad_resources[] = { [0] = { .start = U8500_SKE_BASE, diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c index d35122ebc67..15a0f63b2e2 100644 --- a/arch/arm/mach-ux500/id.c +++ b/arch/arm/mach-ux500/id.c @@ -65,6 +65,7 @@ static unsigned int partnumber(unsigned int asicid) * DB8500v1 0x411fc091 0x9001FFF4 0x008500A0 * DB8500v1.1 0x411fc091 0x9001FFF4 0x008500A1 * DB8500v2 0x412fc091 0x9001DBF4 0x008500B0 + * DB8520v2.2 0x412fc091 0x9001DBF4 0x008500B2 * DB5500v1 0x412fc091 0x9001FFF4 0x005500A0 */ @@ -80,9 +81,10 @@ void __init ux500_map_io(void) addr = 0x9001FFF4; break; - case 0x412fc091: /* DB8500v2 / DB5500v1 */ + case 0x412fc091: /* DB8520 / DB8500v2 / DB5500v1 */ asicid = ux500_read_asicid(0x9001DBF4); - if (partnumber(asicid) == 0x8500) + if (partnumber(asicid) == 0x8500 || + partnumber(asicid) == 0x8520) /* DB8500v2 */ break; diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h index 994b5fe6f85..8e714bcb099 100644 --- a/arch/arm/mach-ux500/include/mach/db5500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h @@ -65,8 +65,11 @@ #define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450) #define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000) #define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000) +#define U5500_MTIMER_BASE (U5500_PER4_BASE + 0xC000) #define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000) #define U5500_PRCMU_TCDM_BASE (U5500_PER4_BASE + 0x18000) +#define U5500_PRCMU_TCPM_BASE (U5500_PER4_BASE + 0x10000) +#define U5500_TPIU_BASE (U5500_PER4_BASE + 0x50000) #define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000) #define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000) @@ -125,6 +128,7 @@ #define U5500_ACCCON_BASE (0xBFFF1000) #define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020) #define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC) +#define U5500_INTCON_MBOX1_INT_RESET_ADDR (0xBFFD31A4) #define U5500_ESRAM_BASE 0x40000000 #define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000 diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h index 751b0e6938d..80e10f50282 100644 --- a/arch/arm/mach-ux500/include/mach/db8500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h @@ -22,7 +22,9 @@ #define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000 #define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET) -#define U8500_DMA_LCPA_BASE_ED (U8500_ESRAM_BANK4 + 0x4000) + +/* This address fulfills the 256k alignment requirement of the lcla base */ +#define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4 #define U8500_PER3_BASE 0x80000000 #define U8500_STM_BASE 0x80100000 @@ -40,15 +42,14 @@ #define U8500_ASIC_ID_BASE 0x9001D000 #define U8500_PER6_BASE 0xa03c0000 +#define U8500_PER7_BASE 0xa03d0000 #define U8500_PER5_BASE 0xa03e0000 -#define U8500_PER7_BASE_ED 0xa03d0000 #define U8500_SVA_BASE 0xa0100000 #define U8500_SIA_BASE 0xa0200000 #define U8500_SGA_BASE 0xa0300000 #define U8500_MCDE_BASE 0xa0350000 -#define U8500_DMA_BASE_ED 0xa0362000 #define U8500_DMA_BASE 0x801C0000 /* v1 */ #define U8500_SBAG_BASE 0xa0390000 @@ -66,13 +67,6 @@ #define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000) #define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000) -/* per7 base addresses */ -#define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000) -#define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000) -#define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000) -#define U8500_TZPC0_BASE_ED (U8500_PER7_BASE_ED + 0xc000) -#define U8500_CLKRST7_BASE_ED (U8500_PER7_BASE_ED + 0xf000) - #define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) #define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) @@ -102,12 +96,10 @@ #define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) #define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) #define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) -#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338) -#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450) -#define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000) #define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) #define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000) - +#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338) +#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450) /* per3 base addresses */ #define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h index 020b6369a30..5f6cb71fc62 100644 --- a/arch/arm/mach-ux500/include/mach/devices.h +++ b/arch/arm/mach-ux500/include/mach/devices.h @@ -18,6 +18,4 @@ extern struct amba_device ux500_pl031_device; extern struct platform_device u8500_dma40_device; extern struct platform_device ux500_ske_keypad_device; -void dma40_u8500ed_fixup(void); - #endif diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h index 470ac52663d..b6ba26a1367 100644 --- a/arch/arm/mach-ux500/include/mach/hardware.h +++ b/arch/arm/mach-ux500/include/mach/hardware.h @@ -10,20 +10,21 @@ #ifndef __MACH_HARDWARE_H #define __MACH_HARDWARE_H -/* macros to get at IO space when running virtually +/* + * Macros to get at IO space when running virtually * We dont map all the peripherals, let ioremap do * this for us. We map only very basic peripherals here. */ #define U8500_IO_VIRTUAL 0xf0000000 #define U8500_IO_PHYSICAL 0xa0000000 -/* this macro is used in assembly, so no cast */ +/* This macro is used in assembly, so no cast */ #define IO_ADDRESS(x) \ (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL) /* typesafe io address */ #define __io_address(n) __io(IO_ADDRESS(n)) -/* used by some plat-nomadik code */ +/* Used by some plat-nomadik code */ #define io_p2v(n) __io_address(n) #include <mach/db8500-regs.h> @@ -36,6 +37,5 @@ extern void __iomem *_PRCMU_BASE; #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) -#endif - +#endif /* __ASSEMBLY__ */ #endif /* __MACH_HARDWARE_H */ diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h index 02b541a37ee..833d6a6edc9 100644 --- a/arch/arm/mach-ux500/include/mach/id.h +++ b/arch/arm/mach-ux500/include/mach/id.h @@ -47,6 +47,30 @@ static inline bool __attribute_const__ cpu_is_u5500(void) } /* + * 5500 revisions + */ + +static inline bool __attribute_const__ cpu_is_u5500v1(void) +{ + return cpu_is_u5500() && (dbx500_revision() & 0xf0) == 0xA0; +} + +static inline bool __attribute_const__ cpu_is_u5500v2(void) +{ + return (dbx500_id.revision & 0xf0) == 0xB0; +} + +static inline bool __attribute_const__ cpu_is_u5500v20(void) +{ + return cpu_is_u5500() && ((dbx500_revision() & 0xf0) == 0xB0); +} + +static inline bool __attribute_const__ cpu_is_u5500v21(void) +{ + return cpu_is_u5500() && (dbx500_revision() == 0xB1); +} + +/* * 8500 revisions */ diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h index 387a9638991..b299b8d201c 100644 --- a/arch/arm/plat-omap/include/plat/clkdev_omap.h +++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h @@ -40,6 +40,7 @@ struct omap_clk { #define CK_443X (1 << 11) #define CK_TI816X (1 << 12) #define CK_446X (1 << 13) +#define CK_1710 (1 << 15) /* 1710 extra for rate selection */ #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h index ebda7382c65..2efd6454bce 100644 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ b/arch/arm/plat-omap/include/plat/irqs.h @@ -357,7 +357,7 @@ #define INT_35XX_EMAC_C0_TX_PULSE_IRQ 69 #define INT_35XX_EMAC_C0_MISC_PULSE_IRQ 70 #define INT_35XX_USBOTG_IRQ 71 -#define INT_35XX_UART4 84 +#define INT_35XX_UART4_IRQ 84 #define INT_35XX_CCDC_VD0_IRQ 88 #define INT_35XX_CCDC_VD1_IRQ 92 #define INT_35XX_CCDC_VD2_IRQ 93 diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index 581851df152..80b6d39c31e 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h @@ -44,6 +44,7 @@ #define OMAP3_UART2_BASE OMAP2_UART2_BASE #define OMAP3_UART3_BASE 0x49020000 #define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */ +#define OMAP3_UART4_AM35XX_BASE 0x4809E000 /* Only on AM35xx */ /* OMAP4 serial ports */ #define OMAP4_UART1_BASE OMAP2_UART1_BASE diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 8b28664d1c6..6b058a621e8 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -141,11 +141,9 @@ static void __init omap_detect_sram(void) omap_sram_size = 0x32000; /* 200K */ else if (cpu_is_omap15xx()) omap_sram_size = 0x30000; /* 192K */ - else if (cpu_is_omap1610() || cpu_is_omap1621() || - cpu_is_omap1710()) + else if (cpu_is_omap1610() || cpu_is_omap1611() || + cpu_is_omap1621() || cpu_is_omap1710()) omap_sram_size = 0x4000; /* 16K */ - else if (cpu_is_omap1611()) - omap_sram_size = SZ_256K; else { pr_err("Could not detect SRAM size\n"); omap_sram_size = 0x4000; @@ -224,6 +222,9 @@ static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl); void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) { BUG_ON(!_omap_sram_reprogram_clock); + /* On 730, bit 13 must always be 1 */ + if (cpu_is_omap7xx()) + ckctl |= 0x2000; _omap_sram_reprogram_clock(dpllctl, ckctl); } diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile index 95a5fc53b6d..c20ce0f5ce3 100644 --- a/arch/arm/plat-orion/Makefile +++ b/arch/arm/plat-orion/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := irq.o pcie.o time.o common.o mpp.o +obj-y := irq.o pcie.o time.o common.o mpp.o addr-map.o obj-m := obj-n := obj- := diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c new file mode 100644 index 00000000000..367ca89ac40 --- /dev/null +++ b/arch/arm/plat-orion/addr-map.c @@ -0,0 +1,174 @@ +/* + * arch/arm/plat-orion/addr-map.c + * + * Address map functions for Marvell Orion based SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/mbus.h> +#include <linux/io.h> +#include <plat/addr-map.h> + +struct mbus_dram_target_info orion_mbus_dram_info; + +const struct mbus_dram_target_info *mv_mbus_dram_info(void) +{ + return &orion_mbus_dram_info; +} +EXPORT_SYMBOL_GPL(mv_mbus_dram_info); + +/* + * DDR target is the same on all Orion platforms. + */ +#define TARGET_DDR 0 + +/* + * Helpers to get DDR bank info + */ +#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) +#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) + +/* + * CPU Address Decode Windows registers + */ +#define WIN_CTRL_OFF 0x0000 +#define WIN_BASE_OFF 0x0004 +#define WIN_REMAP_LO_OFF 0x0008 +#define WIN_REMAP_HI_OFF 0x000c + +/* + * Default implementation + */ +static void __init __iomem * +orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win) +{ + return (void __iomem *)(cfg->bridge_virt_base + (win << 4)); +} + +/* + * Default implementation + */ +static int __init orion_cpu_win_can_remap(const struct orion_addr_map_cfg *cfg, + const int win) +{ + if (win < cfg->remappable_wins) + return 1; + + return 0; +} + +void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg, + const int win, const u32 base, + const u32 size, const u8 target, + const u8 attr, const int remap) +{ + void __iomem *addr = cfg->win_cfg_base(cfg, win); + u32 ctrl, base_high, remap_addr; + + if (win >= cfg->num_wins) { + printk(KERN_ERR "setup_cpu_win: trying to allocate window " + "%d when only %d allowed\n", win, cfg->num_wins); + } + + base_high = base & 0xffff0000; + ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; + + writel(base_high, addr + WIN_BASE_OFF); + writel(ctrl, addr + WIN_CTRL_OFF); + if (cfg->cpu_win_can_remap(cfg, win)) { + if (remap < 0) + remap_addr = base; + else + remap_addr = remap; + writel(remap_addr & 0xffff0000, addr + WIN_REMAP_LO_OFF); + writel(0, addr + WIN_REMAP_HI_OFF); + } +} + +/* + * Configure a number of windows. + */ +static void __init orion_setup_cpu_wins(const struct orion_addr_map_cfg * cfg, + const struct orion_addr_map_info *info) +{ + while (info->win != -1) { + orion_setup_cpu_win(cfg, info->win, info->base, info->size, + info->target, info->attr, info->remap); + info++; + } +} + +static void __init orion_disable_wins(const struct orion_addr_map_cfg * cfg) +{ + void __iomem *addr; + int i; + + for (i = 0; i < cfg->num_wins; i++) { + addr = cfg->win_cfg_base(cfg, i); + + writel(0, addr + WIN_BASE_OFF); + writel(0, addr + WIN_CTRL_OFF); + if (cfg->cpu_win_can_remap(cfg, i)) { + writel(0, addr + WIN_REMAP_LO_OFF); + writel(0, addr + WIN_REMAP_HI_OFF); + } + } +} + +/* + * Disable, clear and configure windows. + */ +void __init orion_config_wins(struct orion_addr_map_cfg * cfg, + const struct orion_addr_map_info *info) +{ + if (!cfg->cpu_win_can_remap) + cfg->cpu_win_can_remap = orion_cpu_win_can_remap; + + if (!cfg->win_cfg_base) + cfg->win_cfg_base = orion_win_cfg_base; + + orion_disable_wins(cfg); + + if (info) + orion_setup_cpu_wins(cfg, info); +} + +/* + * Setup MBUS dram target info. + */ +void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, + const u32 ddr_window_cpu_base) +{ + void __iomem *addr; + int i; + int cs; + + orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + + addr = (void __iomem *)ddr_window_cpu_base; + + for (i = 0, cs = 0; i < 4; i++) { + u32 base = readl(addr + DDR_BASE_CS_OFF(i)); + u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); + + /* + * Chip select enabled? + */ + if (size & 1) { + struct mbus_dram_window *w; + + w = &orion_mbus_dram_info.cs[cs++]; + w->cs_index = i; + w->mbus_attr = 0xf & ~(1 << i); + w->base = base & 0xffff0000; + w->size = (size | 0x0000ffff) + 1; + } + } + orion_mbus_dram_info.num_cs = cs; +} diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 9e5451b3c8e..e5a2fde29b1 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -13,7 +13,6 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> #include <linux/serial_8250.h> -#include <linux/mbus.h> #include <linux/ata_platform.h> #include <linux/mv643xx_eth.h> #include <linux/mv643xx_i2c.h> @@ -203,13 +202,12 @@ void __init orion_rtc_init(unsigned long mapbase, ****************************************************************************/ static __init void ge_complete( struct mv643xx_eth_shared_platform_data *orion_ge_shared_data, - struct mbus_dram_target_info *mbus_dram_info, int tclk, + int tclk, struct resource *orion_ge_resource, unsigned long irq, struct platform_device *orion_ge_shared, struct mv643xx_eth_platform_data *eth_data, struct platform_device *orion_ge) { - orion_ge_shared_data->dram = mbus_dram_info; orion_ge_shared_data->t_clk = tclk; orion_ge_resource->start = irq; orion_ge_resource->end = irq; @@ -259,7 +257,6 @@ static struct platform_device orion_ge00 = { }; void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, @@ -267,7 +264,7 @@ void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, { fill_resources(&orion_ge00_shared, orion_ge00_shared_resources, mapbase + 0x2000, SZ_16K - 1, irq_err); - ge_complete(&orion_ge00_shared_data, mbus_dram_info, tclk, + ge_complete(&orion_ge00_shared_data, tclk, orion_ge00_resources, irq, &orion_ge00_shared, eth_data, &orion_ge00); } @@ -313,7 +310,6 @@ static struct platform_device orion_ge01 = { }; void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, @@ -321,7 +317,7 @@ void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, { fill_resources(&orion_ge01_shared, orion_ge01_shared_resources, mapbase + 0x2000, SZ_16K - 1, irq_err); - ge_complete(&orion_ge01_shared_data, mbus_dram_info, tclk, + ge_complete(&orion_ge01_shared_data, tclk, orion_ge01_resources, irq, &orion_ge01_shared, eth_data, &orion_ge01); } @@ -367,7 +363,6 @@ static struct platform_device orion_ge10 = { }; void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, @@ -375,7 +370,7 @@ void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, { fill_resources(&orion_ge10_shared, orion_ge10_shared_resources, mapbase + 0x2000, SZ_16K - 1, irq_err); - ge_complete(&orion_ge10_shared_data, mbus_dram_info, tclk, + ge_complete(&orion_ge10_shared_data, tclk, orion_ge10_resources, irq, &orion_ge10_shared, eth_data, &orion_ge10); } @@ -421,7 +416,6 @@ static struct platform_device orion_ge11 = { }; void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, @@ -429,7 +423,7 @@ void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, { fill_resources(&orion_ge11_shared, orion_ge11_shared_resources, mapbase + 0x2000, SZ_16K - 1, irq_err); - ge_complete(&orion_ge11_shared_data, mbus_dram_info, tclk, + ge_complete(&orion_ge11_shared_data, tclk, orion_ge11_resources, irq, &orion_ge11_shared, eth_data, &orion_ge11); } @@ -592,8 +586,6 @@ void __init orion_wdt_init(unsigned long tclk) /***************************************************************************** * XOR ****************************************************************************/ -static struct mv_xor_platform_shared_data orion_xor_shared_data; - static u64 orion_xor_dmamask = DMA_BIT_MASK(32); void __init orion_xor_init_channels( @@ -632,9 +624,6 @@ static struct resource orion_xor0_shared_resources[] = { static struct platform_device orion_xor0_shared = { .name = MV_XOR_SHARED_NAME, .id = 0, - .dev = { - .platform_data = &orion_xor_shared_data, - }, .num_resources = ARRAY_SIZE(orion_xor0_shared_resources), .resource = orion_xor0_shared_resources, }; @@ -687,14 +676,11 @@ static struct platform_device orion_xor01_channel = { }, }; -void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase_low, +void __init orion_xor0_init(unsigned long mapbase_low, unsigned long mapbase_high, unsigned long irq_0, unsigned long irq_1) { - orion_xor_shared_data.dram = mbus_dram_info; - orion_xor0_shared_resources[0].start = mapbase_low; orion_xor0_shared_resources[0].end = mapbase_low + 0xff; orion_xor0_shared_resources[1].start = mapbase_high; @@ -727,9 +713,6 @@ static struct resource orion_xor1_shared_resources[] = { static struct platform_device orion_xor1_shared = { .name = MV_XOR_SHARED_NAME, .id = 1, - .dev = { - .platform_data = &orion_xor_shared_data, - }, .num_resources = ARRAY_SIZE(orion_xor1_shared_resources), .resource = orion_xor1_shared_resources, }; @@ -828,11 +811,9 @@ static struct platform_device orion_ehci = { }, }; -void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase, +void __init orion_ehci_init(unsigned long mapbase, unsigned long irq) { - orion_ehci_data.dram = mbus_dram_info; fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1, irq); @@ -854,11 +835,9 @@ static struct platform_device orion_ehci_1 = { }, }; -void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase, +void __init orion_ehci_1_init(unsigned long mapbase, unsigned long irq) { - orion_ehci_data.dram = mbus_dram_info; fill_resources(&orion_ehci_1, orion_ehci_1_resources, mapbase, SZ_4K - 1, irq); @@ -880,11 +859,9 @@ static struct platform_device orion_ehci_2 = { }, }; -void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase, +void __init orion_ehci_2_init(unsigned long mapbase, unsigned long irq) { - orion_ehci_data.dram = mbus_dram_info; fill_resources(&orion_ehci_2, orion_ehci_2_resources, mapbase, SZ_4K - 1, irq); @@ -911,11 +888,9 @@ static struct platform_device orion_sata = { }; void __init orion_sata_init(struct mv_sata_platform_data *sata_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq) { - sata_data->dram = mbus_dram_info; orion_sata.dev.platform_data = sata_data; fill_resources(&orion_sata, orion_sata_resources, mapbase, 0x5000 - 1, irq); diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h new file mode 100644 index 00000000000..fd556f77562 --- /dev/null +++ b/arch/arm/plat-orion/include/plat/addr-map.h @@ -0,0 +1,53 @@ +/* + * arch/arm/plat-orion/include/plat/addr-map.h + * + * Marvell Orion SoC address map handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_ADDR_MAP_H +#define __PLAT_ADDR_MAP_H + +extern struct mbus_dram_target_info orion_mbus_dram_info; + +struct orion_addr_map_cfg { + const int num_wins; /* Total number of windows */ + const int remappable_wins; + const u32 bridge_virt_base; + + /* If NULL, the default cpu_win_can_remap will be used, using + the value in remappable_wins */ + int (*cpu_win_can_remap) (const struct orion_addr_map_cfg *cfg, + const int win); + /* If NULL, the default win_cfg_base will be used, using the + value in bridge_virt_base */ + void __iomem *(*win_cfg_base) (const struct orion_addr_map_cfg *cfg, + const int win); +}; + +/* + * Information needed to setup one address mapping. + */ +struct orion_addr_map_info { + const int win; + const u32 base; + const u32 size; + const u8 target; + const u8 attr; + const int remap; +}; + +void __init orion_config_wins(struct orion_addr_map_cfg *cfg, + const struct orion_addr_map_info *info); + +void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg, + const int win, const u32 base, + const u32 size, const u8 target, + const u8 attr, const int remap); + +void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, + const u32 ddr_window_cpu_base); +#endif diff --git a/arch/arm/plat-orion/include/plat/audio.h b/arch/arm/plat-orion/include/plat/audio.h index 9cf1f781329..885f8abd927 100644 --- a/arch/arm/plat-orion/include/plat/audio.h +++ b/arch/arm/plat-orion/include/plat/audio.h @@ -1,11 +1,8 @@ #ifndef __PLAT_AUDIO_H #define __PLAT_AUDIO_H -#include <linux/mbus.h> - struct kirkwood_asoc_platform_data { u32 tclk; - struct mbus_dram_target_info *dram; int burst; }; #endif diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index a63c357e2ab..0fe08d77e83 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -37,28 +37,24 @@ void __init orion_rtc_init(unsigned long mapbase, unsigned long irq); void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, int tclk); void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, int tclk); void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, int tclk); void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, @@ -82,8 +78,7 @@ void __init orion_spi_1_init(unsigned long mapbase, void __init orion_wdt_init(unsigned long tclk); -void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase_low, +void __init orion_xor0_init(unsigned long mapbase_low, unsigned long mapbase_high, unsigned long irq_0, unsigned long irq_1); @@ -93,20 +88,16 @@ void __init orion_xor1_init(unsigned long mapbase_low, unsigned long irq_0, unsigned long irq_1); -void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase, +void __init orion_ehci_init(unsigned long mapbase, unsigned long irq); -void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase, +void __init orion_ehci_1_init(unsigned long mapbase, unsigned long irq); -void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase, +void __init orion_ehci_2_init(unsigned long mapbase, unsigned long irq); void __init orion_sata_init(struct mv_sata_platform_data *sata_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq); diff --git a/arch/arm/plat-orion/include/plat/ehci-orion.h b/arch/arm/plat-orion/include/plat/ehci-orion.h index 4ec668e7746..6fc78e43042 100644 --- a/arch/arm/plat-orion/include/plat/ehci-orion.h +++ b/arch/arm/plat-orion/include/plat/ehci-orion.h @@ -19,7 +19,6 @@ enum orion_ehci_phy_ver { }; struct orion_ehci_data { - struct mbus_dram_target_info *dram; enum orion_ehci_phy_ver phy_version; }; diff --git a/arch/arm/plat-orion/include/plat/mv_xor.h b/arch/arm/plat-orion/include/plat/mv_xor.h index bd5f3bdb4ae..2ba1f7d76ee 100644 --- a/arch/arm/plat-orion/include/plat/mv_xor.h +++ b/arch/arm/plat-orion/include/plat/mv_xor.h @@ -13,12 +13,6 @@ #define MV_XOR_SHARED_NAME "mv_xor_shared" #define MV_XOR_NAME "mv_xor" -struct mbus_dram_target_info; - -struct mv_xor_platform_shared_data { - struct mbus_dram_target_info *dram; -}; - struct mv_xor_platform_data { struct platform_device *shared; int hw_id; diff --git a/arch/arm/plat-orion/include/plat/mvsdio.h b/arch/arm/plat-orion/include/plat/mvsdio.h index 14ca8867600..1190efedcb9 100644 --- a/arch/arm/plat-orion/include/plat/mvsdio.h +++ b/arch/arm/plat-orion/include/plat/mvsdio.h @@ -12,7 +12,6 @@ #include <linux/mbus.h> struct mvsdio_platform_data { - struct mbus_dram_target_info *dram; unsigned int clock; int gpio_card_detect; int gpio_write_protect; diff --git a/arch/arm/plat-orion/include/plat/pcie.h b/arch/arm/plat-orion/include/plat/pcie.h index cc99163e73f..fe5b9e86274 100644 --- a/arch/arm/plat-orion/include/plat/pcie.h +++ b/arch/arm/plat-orion/include/plat/pcie.h @@ -20,8 +20,7 @@ int orion_pcie_x4_mode(void __iomem *base); int orion_pcie_get_local_bus_nr(void __iomem *base); void orion_pcie_set_local_bus_nr(void __iomem *base, int nr); void orion_pcie_reset(void __iomem *base); -void orion_pcie_setup(void __iomem *base, - struct mbus_dram_target_info *dram); +void orion_pcie_setup(void __iomem *base); int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val); int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c index af2d733c50b..86dbb5bdb17 100644 --- a/arch/arm/plat-orion/pcie.c +++ b/arch/arm/plat-orion/pcie.c @@ -13,6 +13,7 @@ #include <linux/mbus.h> #include <asm/mach/pci.h> #include <plat/pcie.h> +#include <plat/addr-map.h> #include <linux/delay.h> /* @@ -175,8 +176,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base, writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1)); } -void __init orion_pcie_setup(void __iomem *base, - struct mbus_dram_target_info *dram) +void __init orion_pcie_setup(void __iomem *base) { u16 cmd; u32 mask; @@ -184,7 +184,7 @@ void __init orion_pcie_setup(void __iomem *base, /* * Point PCIe unit MBUS decode windows to DRAM space. */ - orion_pcie_setup_wins(base, dram); + orion_pcie_setup_wins(base, &orion_mbus_dram_info); /* * Master + slave enable. |