diff options
Diffstat (limited to 'arch')
515 files changed, 22449 insertions, 16112 deletions
diff --git a/arch/alpha/kernel/time.c b/arch/alpha/kernel/time.c index 0f1d8493cfc..c1f3e7cb82a 100644 --- a/arch/alpha/kernel/time.c +++ b/arch/alpha/kernel/time.c @@ -506,7 +506,7 @@ set_rtc_mmss(unsigned long nowtime) CMOS_WRITE(real_seconds,RTC_SECONDS); CMOS_WRITE(real_minutes,RTC_MINUTES); } else { - printk(KERN_WARNING + printk_once(KERN_NOTICE "set_rtc_mmss: can't update from %d to %d\n", cmos_minutes, real_minutes); retval = -1; diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a3fb23be87f..e2f80116759 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -632,9 +632,15 @@ config ARCH_MSM (clock and power control, etc). config ARCH_SHMOBILE - bool "Renesas SH-Mobile" + bool "Renesas SH-Mobile / R-Mobile" + select HAVE_CLK + select CLKDEV_LOOKUP + select GENERIC_CLOCKEVENTS + select NO_IOPORT + select SPARSE_IRQ + select MULTI_IRQ_HANDLER help - Support for Renesas's SH-Mobile ARM platforms + Support for Renesas's SH-Mobile and R-Mobile ARM platforms. config ARCH_RPC bool "RiscPC" @@ -1252,7 +1258,7 @@ config SMP depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ - ARCH_MSM_SCORPIONMP + ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE select USE_GENERIC_SMP_HELPERS select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP help diff --git a/arch/arm/configs/ag5evm_defconfig b/arch/arm/configs/ag5evm_defconfig new file mode 100644 index 00000000000..2b9cf56db36 --- /dev/null +++ b/arch/arm/configs/ag5evm_defconfig @@ -0,0 +1,83 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_SHMOBILE=y +CONFIG_ARCH_SH73A0=y +CONFIG_MACH_AG5EVM=y +CONFIG_MEMORY_SIZE=0x10000000 +CONFIG_CPU_BPREDICT_DISABLE=y +CONFIG_ARM_ERRATA_430973=y +CONFIG_ARM_ERRATA_458693=y +CONFIG_NO_HZ=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_HIGHMEM=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=tty0 console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel" +CONFIG_CMDLINE_FORCE=y +CONFIG_KEXEC=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM=y +# CONFIG_SUSPEND is not set +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_BLK_DEV is not set +CONFIG_NETDEVICES=y +CONFIG_NET_ETHERNET=y +CONFIG_SMSC911X=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +CONFIG_INPUT_SPARSEKMAP=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=9 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_SH_MOBILE=y +# CONFIG_HWMON is not set +# CONFIG_MFD_SUPPORT is not set +CONFIG_FB=y +CONFIG_FB_SH_MOBILE_LCDC=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_FTRACE is not set diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig new file mode 100644 index 00000000000..306a2e2d362 --- /dev/null +++ b/arch/arm/configs/mackerel_defconfig @@ -0,0 +1,138 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_SHMOBILE=y +CONFIG_ARCH_SH7372=y +CONFIG_MACH_MACKEREL=y +CONFIG_MEMORY_SIZE=0x10000000 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_FORCE_MAX_ZONEORDER=15 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=tty0, console=ttySC0,115200 earlyprintk=sh-sci.0,115200 root=/dev/nfs nfsroot=,tcp,v3 ip=dhcp memchunk.vpu=64m memchunk.veu0=8m memchunk.spu0=2m mem=240m" +CONFIG_KEXEC=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM=y +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_MTD=y +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_ARM_INTEGRATOR=y +CONFIG_MTD_BLOCK2MTD=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +CONFIG_NET_ETHERNET=y +CONFIG_SMSC911X=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=8 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_MFD_SUPPORT is not set +CONFIG_FB=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_SH_MOBILE_LCDC=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT2_FS_XIP=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=y +CONFIG_NLS_CODEPAGE_775=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_CODEPAGE_852=y +CONFIG_NLS_CODEPAGE_855=y +CONFIG_NLS_CODEPAGE_857=y +CONFIG_NLS_CODEPAGE_860=y +CONFIG_NLS_CODEPAGE_861=y +CONFIG_NLS_CODEPAGE_862=y +CONFIG_NLS_CODEPAGE_863=y +CONFIG_NLS_CODEPAGE_864=y +CONFIG_NLS_CODEPAGE_865=y +CONFIG_NLS_CODEPAGE_866=y +CONFIG_NLS_CODEPAGE_869=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_ISO8859_3=y +CONFIG_NLS_ISO8859_4=y +CONFIG_NLS_ISO8859_5=y +CONFIG_NLS_ISO8859_6=y +CONFIG_NLS_ISO8859_7=y +CONFIG_NLS_ISO8859_9=y +CONFIG_NLS_ISO8859_13=y +CONFIG_NLS_ISO8859_14=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_KOI8_R=y +CONFIG_NLS_KOI8_U=y +CONFIG_NLS_UTF8=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ANSI_CPRNG=y diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index be80f037f85..52d86c4485b 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig @@ -9,6 +9,10 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_LBDAF is not set # CONFIG_BLK_DEV_BSG is not set CONFIG_ARCH_U8500=y +CONFIG_UX500_SOC_DB5500=y +CONFIG_UX500_SOC_DB8500=y +CONFIG_MACH_U8500=y +CONFIG_MACH_U5500=y CONFIG_SMP=y CONFIG_NR_CPUS=2 CONFIG_PREEMPT=y diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 2652af124ac..a5f8a80c1f2 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -412,12 +412,7 @@ static struct resource dm355_spi0_resources[] = { static struct davinci_spi_platform_data dm355_spi0_pdata = { .version = SPI_VERSION_1, .num_chipselect = 2, - .clk_internal = 1, - .cs_hold = 1, - .intr_level = 0, - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ - .c2tdelay = 0, - .t2cdelay = 0, + .cshold_bug = true, }; static struct platform_device dm355_spi0_device = { .name = "spi_davinci", diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index c466d710d3c..02d2cc380df 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -625,12 +625,6 @@ static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32); static struct davinci_spi_platform_data dm365_spi0_pdata = { .version = SPI_VERSION_1, .num_chipselect = 2, - .clk_internal = 1, - .cs_hold = 1, - .intr_level = 0, - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ - .c2tdelay = 0, - .t2cdelay = 0, }; static struct resource dm365_spi0_resources[] = { diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h index 910efbf099c..38f4da5ca13 100644 --- a/arch/arm/mach-davinci/include/mach/spi.h +++ b/arch/arm/mach-davinci/include/mach/spi.h @@ -19,26 +19,66 @@ #ifndef __ARCH_ARM_DAVINCI_SPI_H #define __ARCH_ARM_DAVINCI_SPI_H +#define SPI_INTERN_CS 0xFF + enum { SPI_VERSION_1, /* For DM355/DM365/DM6467 */ SPI_VERSION_2, /* For DA8xx */ }; +/** + * davinci_spi_platform_data - Platform data for SPI master device on DaVinci + * + * @version: version of the SPI IP. Different DaVinci devices have slightly + * varying versions of the same IP. + * @num_chipselect: number of chipselects supported by this SPI master + * @intr_line: interrupt line used to connect the SPI IP to the ARM interrupt + * controller withn the SoC. Possible values are 0 and 1. + * @chip_sel: list of GPIOs which can act as chip-selects for the SPI. + * SPI_INTERN_CS denotes internal SPI chip-select. Not necessary + * to populate if all chip-selects are internal. + * @cshold_bug: set this to true if the SPI controller on your chip requires + * a write to CSHOLD bit in between transfers (like in DM355). + */ struct davinci_spi_platform_data { u8 version; u8 num_chipselect; + u8 intr_line; + u8 *chip_sel; + bool cshold_bug; +}; + +/** + * davinci_spi_config - Per-chip-select configuration for SPI slave devices + * + * @wdelay: amount of delay between transmissions. Measured in number of + * SPI module clocks. + * @odd_parity: polarity of parity flag at the end of transmit data stream. + * 0 - odd parity, 1 - even parity. + * @parity_enable: enable transmission of parity at end of each transmit + * data stream. + * @io_type: type of IO transfer. Choose between polled, interrupt and DMA. + * @timer_disable: disable chip-select timers (setup and hold) + * @c2tdelay: chip-select setup time. Measured in number of SPI module clocks. + * @t2cdelay: chip-select hold time. Measured in number of SPI module clocks. + * @t2edelay: transmit data finished to SPI ENAn pin inactive time. Measured + * in number of SPI clocks. + * @c2edelay: chip-select active to SPI ENAn signal active time. Measured in + * number of SPI clocks. + */ +struct davinci_spi_config { u8 wdelay; u8 odd_parity; u8 parity_enable; - u8 wait_enable; +#define SPI_IO_TYPE_INTR 0 +#define SPI_IO_TYPE_POLL 1 +#define SPI_IO_TYPE_DMA 2 + u8 io_type; u8 timer_disable; - u8 clk_internal; - u8 cs_hold; - u8 intr_level; - u8 poll_mode; - u8 use_dma; u8 c2tdelay; u8 t2cdelay; + u8 t2edelay; + u8 c2edelay; }; #endif /* __ARCH_ARM_DAVINCI_SPI_H */ diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index f7a12586a1f..fe627aba6da 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -770,7 +770,7 @@ static struct resource dove_sdio0_resources[] = { }; static struct platform_device dove_sdio0 = { - .name = "sdhci-mv", + .name = "sdhci-dove", .id = 0, .dev = { .dma_mask = &sdio_dmamask, @@ -798,7 +798,7 @@ static struct resource dove_sdio1_resources[] = { }; static struct platform_device dove_sdio1 = { - .name = "sdhci-mv", + .name = "sdhci-dove", .id = 1, .dev = { .dma_mask = &sdio_dmamask, diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index fae931ac2e5..5d3d9ade12f 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -40,11 +40,13 @@ config ARCH_MSM8X60 bool "MSM8X60" select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \ && !MACH_MSM8X60_FFA) + select ARCH_MSM_SCORPIONMP select ARM_GIC select CPU_V7 select MSM_V2_TLMM select MSM_GPIOMUX select IOMMU_API + select MSM_SCM if SMP endchoice @@ -172,4 +174,7 @@ config MSM_V2_TLMM config IOMMU_API bool + +config MSM_SCM + bool endif diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 59646bbd619..94195c190e1 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -18,6 +18,10 @@ obj-$(CONFIG_MSM_PROC_COMM) += clock.o obj-$(CONFIG_ARCH_QSD8X50) += sirc.o obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o obj-$(CONFIG_MSM_SMD) += last_radio_log.o +obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o + +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o +obj-$(CONFIG_SMP) += headsmp.o platsmp.o obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o diff --git a/arch/arm/mach-msm/headsmp.S b/arch/arm/mach-msm/headsmp.S new file mode 100644 index 00000000000..d0c214338df --- /dev/null +++ b/arch/arm/mach-msm/headsmp.S @@ -0,0 +1,40 @@ +/* + * linux/arch/arm/mach-realview/headsmp.S + * + * Copyright (c) 2003 ARM Limited + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <linux/init.h> + + __INIT + +/* + * MSM specific entry point for secondary CPUs. This provides + * a "holding pen" into which all secondary cores are held until we're + * ready for them to initialise. + */ +ENTRY(msm_secondary_startup) + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #15 + adr r4, 1f + ldmia r4, {r5, r6} + sub r4, r4, r5 + add r6, r6, r4 +pen: ldr r7, [r6] + cmp r7, r0 + bne pen + + /* + * we've been released from the holding pen: secondary_stack + * should now contain the SVC stack for this core + */ + b secondary_startup + + .align +1: .long . + .long pen_release diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c new file mode 100644 index 00000000000..5a31f70dfb8 --- /dev/null +++ b/arch/arm/mach-msm/hotplug.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/smp.h> + +#include <asm/cacheflush.h> + +extern volatile int pen_release; + +static inline void cpu_enter_lowpower(void) +{ + /* Just flush the cache. Changing the coherency is not yet + * available on msm. */ + flush_cache_all(); +} + +static inline void cpu_leave_lowpower(void) +{ +} + +static inline void platform_do_lowpower(unsigned int cpu) +{ + /* Just enter wfi for now. TODO: Properly shut off the cpu. */ + for (;;) { + /* + * here's the WFI + */ + asm("wfi" + : + : + : "memory", "cc"); + + if (pen_release == cpu) { + /* + * OK, proper wakeup, we're done + */ + break; + } + + /* + * getting here, means that we have come out of WFI without + * having been woken up - this shouldn't happen + * + * The trouble is, letting people know about this is not really + * possible, since we are currently running incoherently, and + * therefore cannot safely call printk() or anything else + */ + pr_debug("CPU%u: spurious wakeup call\n", cpu); + } +} + +int platform_cpu_kill(unsigned int cpu) +{ + return 1; +} + +/* + * platform-specific code to shutdown a CPU + * + * Called with IRQs disabled + */ +void platform_cpu_die(unsigned int cpu) +{ + /* + * we're ready for shutdown now, so do it + */ + cpu_enter_lowpower(); + platform_do_lowpower(cpu); + + /* + * bring this CPU back into the world of cache + * coherency, and then restore interrupts + */ + cpu_leave_lowpower(); +} + +int platform_cpu_disable(unsigned int cpu) +{ + /* + * we don't allow CPU 0 to be shutdown (it is still too special + * e.g. clock tick interrupts) + */ + return cpu == 0 ? -EPERM : 0; +} diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index 7c43a9bff1a..a54e33b0882 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h @@ -60,7 +60,11 @@ #define MSM_TMR_BASE IOMEM(0xF0200000) #define MSM_TMR_PHYS 0x02000000 -#define MSM_TMR_SIZE (SZ_1M) +#define MSM_TMR_SIZE SZ_4K + +#define MSM_TMR0_BASE IOMEM(0xF0201000) +#define MSM_TMR0_PHYS 0x02040000 +#define MSM_TMR0_SIZE SZ_4K #define MSM_GPT_BASE (MSM_TMR_BASE + 0x4) #define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index f912d7bf188..800f327a7ec 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c @@ -105,6 +105,7 @@ static struct map_desc msm8x60_io_desc[] __initdata = { MSM_DEVICE(QGIC_DIST), MSM_DEVICE(QGIC_CPU), MSM_DEVICE(TMR), + MSM_DEVICE(TMR0), MSM_DEVICE(ACC), MSM_DEVICE(GCC), }; diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c new file mode 100644 index 00000000000..0f427bc9444 --- /dev/null +++ b/arch/arm/mach-msm/platsmp.c @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/errno.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/jiffies.h> +#include <linux/smp.h> +#include <linux/io.h> + +#include <asm/hardware/gic.h> +#include <asm/cacheflush.h> +#include <asm/mach-types.h> + +#include <mach/msm_iomap.h> + +#include "scm-boot.h" + +#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 +#define SCSS_CPU1CORE_RESET 0xD80 +#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 + +/* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ +#define GIC_PPI_EDGE_MASK 0xFFFFD7FF + +extern void msm_secondary_startup(void); +/* + * control for which core is the next to come out of the secondary + * boot "holding pen". + */ +volatile int pen_release = -1; + +static DEFINE_SPINLOCK(boot_lock); + +void __cpuinit platform_secondary_init(unsigned int cpu) +{ + /* Configure edge-triggered PPIs */ + writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); + + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); + + /* + * let the primary processor know we're out of the + * pen, then head off into the C entry point + */ + pen_release = -1; + smp_wmb(); + + /* + * Synchronise with the boot thread. + */ + spin_lock(&boot_lock); + spin_unlock(&boot_lock); +} + +static __cpuinit void prepare_cold_cpu(unsigned int cpu) +{ + int ret; + ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup), + SCM_FLAG_COLDBOOT_CPU1); + if (ret == 0) { + void *sc1_base_ptr; + sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2); + if (sc1_base_ptr) { + writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL); + writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET); + writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP); + iounmap(sc1_base_ptr); + } + } else + printk(KERN_DEBUG "Failed to set secondary core boot " + "address\n"); +} + +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long timeout; + static int cold_boot_done; + + /* Only need to bring cpu out of reset this way once */ + if (cold_boot_done == false) { + prepare_cold_cpu(cpu); + cold_boot_done = true; + } + + /* + * set synchronisation state between this boot processor + * and the secondary one + */ + spin_lock(&boot_lock); + + /* + * The secondary processor is waiting to be released from + * the holding pen - release it, then wait for it to flag + * that it has been released by resetting pen_release. + * + * Note that "pen_release" is the hardware CPU ID, whereas + * "cpu" is Linux's internal ID. + */ + pen_release = cpu; + __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); + + /* + * Send the secondary CPU a soft interrupt, thereby causing + * the boot monitor to read the system wide flags register, + * and branch to the address found there. + */ + smp_cross_call(cpumask_of(cpu), 1); + + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) { + smp_rmb(); + if (pen_release == -1) + break; + + udelay(10); + } + + /* + * now the secondary core is starting up let it run its + * calibrations, then wait for it to finish + */ + spin_unlock(&boot_lock); + + return pen_release != -1 ? -ENOSYS : 0; +} + +/* + * Initialise the CPU possible map early - this describes the CPUs + * which may be present or become present in the system. The msm8x60 + * does not support the ARM SCU, so just set the possible cpu mask to + * NR_CPUS. + */ +void __init smp_init_cpus(void) +{ + unsigned int i; + + for (i = 0; i < NR_CPUS; i++) + set_cpu_possible(i, true); +} + +void __init platform_smp_prepare_cpus(unsigned int max_cpus) +{ + int i; + + /* + * Initialise the present map, which describes the set of CPUs + * actually populated at the present time. + */ + for (i = 0; i < max_cpus; i++) + set_cpu_present(i, true); +} diff --git a/arch/arm/mach-msm/scm-boot.c b/arch/arm/mach-msm/scm-boot.c new file mode 100644 index 00000000000..45cee3e469a --- /dev/null +++ b/arch/arm/mach-msm/scm-boot.c @@ -0,0 +1,39 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include <linux/module.h> +#include <linux/slab.h> + +#include "scm.h" +#include "scm-boot.h" + +/* + * Set the cold/warm boot address for one of the CPU cores. + */ +int scm_set_boot_addr(phys_addr_t addr, int flags) +{ + struct { + unsigned int flags; + phys_addr_t addr; + } cmd; + + cmd.addr = addr; + cmd.flags = flags; + return scm_call(SCM_SVC_BOOT, SCM_BOOT_ADDR, + &cmd, sizeof(cmd), NULL, 0); +} +EXPORT_SYMBOL(scm_set_boot_addr); diff --git a/arch/arm/mach-msm/scm-boot.h b/arch/arm/mach-msm/scm-boot.h new file mode 100644 index 00000000000..68f9b6153d7 --- /dev/null +++ b/arch/arm/mach-msm/scm-boot.h @@ -0,0 +1,38 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __MACH_SCM_BOOT_H +#define __MACH_SCM_BOOT_H + +#define SCM_BOOT_ADDR 0x1 +#define SCM_FLAG_COLDBOOT_CPU1 0x1 +#define SCM_FLAG_WARMBOOT_CPU1 0x2 +#define SCM_FLAG_WARMBOOT_CPU0 0x4 + +int scm_set_boot_addr(phys_addr_t addr, int flags); + +#endif diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-msm/scm.c new file mode 100644 index 00000000000..f4b9bc90d6a --- /dev/null +++ b/arch/arm/mach-msm/scm.c @@ -0,0 +1,287 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/errno.h> +#include <linux/err.h> + +#include <asm/cacheflush.h> + +#include "scm.h" + +/* Cache line size for msm8x60 */ +#define CACHELINESIZE 32 + +#define SCM_ENOMEM -5 +#define SCM_EOPNOTSUPP -4 +#define SCM_EINVAL_ADDR -3 +#define SCM_EINVAL_ARG -2 +#define SCM_ERROR -1 +#define SCM_INTERRUPTED 1 + +static DEFINE_MUTEX(scm_lock); + +/** + * struct scm_command - one SCM command buffer + * @len: total available memory for command and response + * @buf_offset: start of command buffer + * @resp_hdr_offset: start of response buffer + * @id: command to be executed + * @buf: buffer returned from scm_get_command_buffer() + * + * An SCM command is layed out in memory as follows: + * + * ------------------- <--- struct scm_command + * | command header | + * ------------------- <--- scm_get_command_buffer() + * | command buffer | + * ------------------- <--- struct scm_response and + * | response header | scm_command_to_response() + * ------------------- <--- scm_get_response_buffer() + * | response buffer | + * ------------------- + * + * There can be arbitrary padding between the headers and buffers so + * you should always use the appropriate scm_get_*_buffer() routines + * to access the buffers in a safe manner. + */ +struct scm_command { + u32 len; + u32 buf_offset; + u32 resp_hdr_offset; + u32 id; + u32 buf[0]; +}; + +/** + * struct scm_response - one SCM response buffer + * @len: total available memory for response + * @buf_offset: start of response data relative to start of scm_response + * @is_complete: indicates if the command has finished processing + */ +struct scm_response { + u32 len; + u32 buf_offset; + u32 is_complete; +}; + +/** + * alloc_scm_command() - Allocate an SCM command + * @cmd_size: size of the command buffer + * @resp_size: size of the response buffer + * + * Allocate an SCM command, including enough room for the command + * and response headers as well as the command and response buffers. + * + * Returns a valid &scm_command on success or %NULL if the allocation fails. + */ +static struct scm_command *alloc_scm_command(size_t cmd_size, size_t resp_size) +{ + struct scm_command *cmd; + size_t len = sizeof(*cmd) + sizeof(struct scm_response) + cmd_size + + resp_size; + + cmd = kzalloc(PAGE_ALIGN(len), GFP_KERNEL); + if (cmd) { + cmd->len = len; + cmd->buf_offset = offsetof(struct scm_command, buf); + cmd->resp_hdr_offset = cmd->buf_offset + cmd_size; + } + return cmd; +} + +/** + * free_scm_command() - Free an SCM command + * @cmd: command to free + * + * Free an SCM command. + */ +static inline void free_scm_command(struct scm_command *cmd) +{ + kfree(cmd); +} + +/** + * scm_command_to_response() - Get a pointer to a scm_response + * @cmd: command + * + * Returns a pointer to a response for a command. + */ +static inline struct scm_response *scm_command_to_response( + const struct scm_command *cmd) +{ + return (void *)cmd + cmd->resp_hdr_offset; +} + +/** + * scm_get_command_buffer() - Get a pointer to a command buffer + * @cmd: command + * + * Returns a pointer to the command buffer of a command. + */ +static inline void *scm_get_command_buffer(const struct scm_command *cmd) +{ + return (void *)cmd->buf; +} + +/** + * scm_get_response_buffer() - Get a pointer to a response buffer + * @rsp: response + * + * Returns a pointer to a response buffer of a response. + */ +static inline void *scm_get_response_buffer(const struct scm_response *rsp) +{ + return (void *)rsp + rsp->buf_offset; +} + +static int scm_remap_error(int err) +{ + switch (err) { + case SCM_ERROR: + return -EIO; + case SCM_EINVAL_ADDR: + case SCM_EINVAL_ARG: + return -EINVAL; + case SCM_EOPNOTSUPP: + return -EOPNOTSUPP; + case SCM_ENOMEM: + return -ENOMEM; + } + return -EINVAL; +} + +static u32 smc(u32 cmd_addr) +{ + int context_id; + register u32 r0 asm("r0") = 1; + register u32 r1 asm("r1") = (u32)&context_id; + register u32 r2 asm("r2") = cmd_addr; + asm( + __asmeq("%0", "r0") + __asmeq("%1", "r0") + __asmeq("%2", "r1") + __asmeq("%3", "r2") + "smc #0 @ switch to secure world\n" + : "=r" (r0) + : "r" (r0), "r" (r1), "r" (r2) + : "r3"); + return r0; +} + +static int __scm_call(const struct scm_command *cmd) +{ + int ret; + u32 cmd_addr = virt_to_phys(cmd); + + /* + * Flush the entire cache here so callers don't have to remember + * to flush the cache when passing physical addresses to the secure + * side in the buffer. + */ + flush_cache_all(); + do { + ret = smc(cmd_addr); + if (ret < 0) { + ret = scm_remap_error(ret); + break; + } + } while (ret == SCM_INTERRUPTED); + + return ret; +} + +/** + * scm_call() - Send an SCM command + * @svc_id: service identifier + * @cmd_id: command identifier + * @cmd_buf: command buffer + * @cmd_len: length of the command buffer + * @resp_buf: response buffer + * @resp_len: length of the response buffer + * + * Sends a command to the SCM and waits for the command to finish processing. + */ +int scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf, size_t cmd_len, + void *resp_buf, size_t resp_len) +{ + int ret; + struct scm_command *cmd; + struct scm_response *rsp; + + cmd = alloc_scm_command(cmd_len, resp_len); + if (!cmd) + return -ENOMEM; + + cmd->id = (svc_id << 10) | cmd_id; + if (cmd_buf) + memcpy(scm_get_command_buffer(cmd), cmd_buf, cmd_len); + + mutex_lock(&scm_lock); + ret = __scm_call(cmd); + mutex_unlock(&scm_lock); + if (ret) + goto out; + + rsp = scm_command_to_response(cmd); + do { + u32 start = (u32)rsp; + u32 end = (u32)scm_get_response_buffer(rsp) + resp_len; + start &= ~(CACHELINESIZE - 1); + while (start < end) { + asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start) + : "memory"); + start += CACHELINESIZE; + } + } while (!rsp->is_complete); + + if (resp_buf) + memcpy(resp_buf, scm_get_response_buffer(rsp), resp_len); +out: + free_scm_command(cmd); + return ret; +} +EXPORT_SYMBOL(scm_call); + +u32 scm_get_version(void) +{ + int context_id; + static u32 version = -1; + register u32 r0 asm("r0") = 0x1 << 8; + register u32 r1 asm("r1") = (u32)&context_id; + + if (version != -1) + return version; + + mutex_lock(&scm_lock); + asm( + __asmeq("%0", "r1") + __asmeq("%1", "r0") + __asmeq("%2", "r1") + "smc #0 @ switch to secure world\n" + : "=r" (r1) + : "r" (r0), "r" (r1) + : "r2", "r3"); + version = r1; + mutex_unlock(&scm_lock); + + return version; +} +EXPORT_SYMBOL(scm_get_version); diff --git a/arch/arm/mach-msm/scm.h b/arch/arm/mach-msm/scm.h new file mode 100644 index 00000000000..261786be11c --- /dev/null +++ b/arch/arm/mach-msm/scm.h @@ -0,0 +1,41 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __MACH_SCM_H +#define __MACH_SCM_H + +#define SCM_SVC_BOOT 0x1 +#define SCM_SVC_PIL 0x2 + +extern int scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf, size_t cmd_len, + void *resp_buf, size_t resp_len); + +#define SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF)) + +extern u32 scm_get_version(void); + +#endif diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 595be7fea31..c105d28b53e 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -47,6 +47,19 @@ enum { #define GPT_HZ 32768 +enum timer_location { + LOCAL_TIMER = 0, + GLOBAL_TIMER = 1, +}; + +#ifdef MSM_TMR0_BASE +#define MSM_TMR_GLOBAL (MSM_TMR0_BASE - MSM_TMR_BASE) +#else +#define MSM_TMR_GLOBAL 0 +#endif + +#define MSM_GLOBAL_TIMER MSM_CLOCK_DGT + #if defined(CONFIG_ARCH_QSD8X50) #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */ #define MSM_DGT_SHIFT (0) @@ -65,49 +78,67 @@ struct msm_clock { void __iomem *regbase; uint32_t freq; uint32_t shift; + void __iomem *global_counter; + void __iomem *local_counter; +}; + +enum { + MSM_CLOCK_GPT, + MSM_CLOCK_DGT, + NR_TIMERS, }; + +static struct msm_clock msm_clocks[]; +static struct clock_event_device *local_clock_event; + static irqreturn_t msm_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evt = dev_id; + if (smp_processor_id() != 0) + evt = local_clock_event; + if (evt->event_handler == NULL) + return IRQ_HANDLED; evt->event_handler(evt); return IRQ_HANDLED; } -static cycle_t msm_gpt_read(struct clocksource *cs) +static cycle_t msm_read_timer_count(struct clocksource *cs) { - return readl(MSM_GPT_BASE + TIMER_COUNT_VAL); + struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource); + + return readl(clk->global_counter); } -static cycle_t msm_dgt_read(struct clocksource *cs) +static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt) { - return readl(MSM_DGT_BASE + TIMER_COUNT_VAL) >> MSM_DGT_SHIFT; +#ifdef CONFIG_SMP + int i; + for (i = 0; i < NR_TIMERS; i++) + if (evt == &(msm_clocks[i].clockevent)) + return &msm_clocks[i]; + return &msm_clocks[MSM_GLOBAL_TIMER]; +#else + return container_of(evt, struct msm_clock, clockevent); +#endif } static int msm_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) { - struct msm_clock *clock = container_of(evt, struct msm_clock, clockevent); - uint32_t now = readl(clock->regbase + TIMER_COUNT_VAL); + struct msm_clock *clock = clockevent_to_clock(evt); + uint32_t now = readl(clock->local_counter); uint32_t alarm = now + (cycles << clock->shift); - int late; writel(alarm, clock->regbase + TIMER_MATCH_VAL); - now = readl(clock->regbase + TIMER_COUNT_VAL); - late = now - alarm; - if (late >= (-2 << clock->shift) && late < DGT_HZ*5) { - printk(KERN_NOTICE "msm_timer_set_next_event(%lu) clock %s, " - "alarm already expired, now %x, alarm %x, late %d\n", - cycles, clock->clockevent.name, now, alarm, late); - return -ETIME; - } return 0; } static void msm_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { - struct msm_clock *clock = container_of(evt, struct msm_clock, clockevent); + struct msm_clock *clock = clockevent_to_clock(evt); + switch (mode) { case CLOCK_EVT_MODE_RESUME: case CLOCK_EVT_MODE_PERIODIC: @@ -123,7 +154,7 @@ static void msm_timer_set_mode(enum clock_event_mode mode, } static struct msm_clock msm_clocks[] = { - { + [MSM_CLOCK_GPT] = { .clockevent = { .name = "gp_timer", .features = CLOCK_EVT_FEAT_ONESHOT, @@ -135,7 +166,7 @@ static struct msm_clock msm_clocks[] = { .clocksource = { .name = "gp_timer", .rating = 200, - .read = msm_gpt_read, + .read = msm_read_timer_count, .mask = CLOCKSOURCE_MASK(32), .flags = CLOCK_SOURCE_IS_CONTINUOUS, }, @@ -147,9 +178,12 @@ static struct msm_clock msm_clocks[] = { .irq = INT_GP_TIMER_EXP }, .regbase = MSM_GPT_BASE, - .freq = GPT_HZ + .freq = GPT_HZ, + .local_counter = MSM_GPT_BASE + TIMER_COUNT_VAL, + .global_counter = MSM_GPT_BASE + TIMER_COUNT_VAL + + MSM_TMR_GLOBAL, }, - { + [MSM_CLOCK_DGT] = { .clockevent = { .name = "dg_timer", .features = CLOCK_EVT_FEAT_ONESHOT, @@ -161,7 +195,7 @@ static struct msm_clock msm_clocks[] = { .clocksource = { .name = "dg_timer", .rating = 300, - .read = msm_dgt_read, + .read = msm_read_timer_count, .mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)), .flags = CLOCK_SOURCE_IS_CONTINUOUS, }, @@ -174,7 +208,10 @@ static struct msm_clock msm_clocks[] = { }, .regbase = MSM_DGT_BASE, .freq = DGT_HZ >> MSM_DGT_SHIFT, - .shift = MSM_DGT_SHIFT + .shift = MSM_DGT_SHIFT, + .local_counter = MSM_DGT_BASE + TIMER_COUNT_VAL, + .global_counter = MSM_DGT_BASE + TIMER_COUNT_VAL + + MSM_TMR_GLOBAL, } }; @@ -183,7 +220,7 @@ static void __init msm_timer_init(void) int i; int res; -#ifdef CONFIG_ARCH_MSM8X60 +#ifdef CONFIG_ARCH_MSM_SCORPIONMP writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); #endif @@ -217,6 +254,48 @@ static void __init msm_timer_init(void) } } +#ifdef CONFIG_SMP +void __cpuinit local_timer_setup(struct clock_event_device *evt) +{ + struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER]; + + /* Use existing clock_event for cpu 0 */ + if (!smp_processor_id()) + return; + + writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); + + if (!local_clock_event) { + writel(0, clock->regbase + TIMER_ENABLE); + writel(0, clock->regbase + TIMER_CLEAR); + writel(~0, clock->regbase + TIMER_MATCH_VAL); + } + evt->irq = clock->irq.irq; + evt->name = "local_timer"; + evt->features = CLOCK_EVT_FEAT_ONESHOT; + evt->rating = clock->clockevent.rating; + evt->set_mode = msm_timer_set_mode; + evt->set_next_event = msm_timer_set_next_event; + evt->shift = clock->clockevent.shift; + evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift); + evt->max_delta_ns = + clockevent_delta2ns(0xf0000000 >> clock->shift, evt); + evt->min_delta_ns = clockevent_delta2ns(4, evt); + + local_clock_event = evt; + + gic_enable_ppi(clock->irq.irq); + + clockevents_register_device(evt); +} + +inline int local_timer_ack(void) +{ + return 1; +} + +#endif + struct sys_timer msm_timer = { .init = msm_timer_init }; diff --git a/arch/arm/mach-pxa/cm-x255.c b/arch/arm/mach-pxa/cm-x255.c index f1a7703d771..93f59f877fc 100644 --- a/arch/arm/mach-pxa/cm-x255.c +++ b/arch/arm/mach-pxa/cm-x255.c @@ -17,13 +17,13 @@ #include <linux/mtd/nand-gpio.h> #include <linux/spi/spi.h> +#include <linux/spi/pxa2xx_spi.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> #include <asm/mach/map.h> #include <mach/pxa25x.h> -#include <mach/pxa2xx_spi.h> #include "generic.h" diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c index a9926bb7592..b88d601a809 100644 --- a/arch/arm/mach-pxa/cm-x270.c +++ b/arch/arm/mach-pxa/cm-x270.c @@ -19,12 +19,12 @@ #include <video/mbxfb.h> #include <linux/spi/spi.h> +#include <linux/spi/pxa2xx_spi.h> #include <linux/spi/libertas_spi.h> #include <mach/pxa27x.h> #include <mach/ohci.h> #include <mach/mmc.h> -#include <mach/pxa2xx_spi.h> #include "generic.h" diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 9f3e5af0a0d..a5452a3a276 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -28,6 +28,7 @@ #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> #include <linux/spi/corgi_lcd.h> +#include <linux/spi/pxa2xx_spi.h> #include <linux/mtd/sharpsl.h> #include <linux/input/matrix_keypad.h> #include <video/w100fb.h> @@ -48,7 +49,6 @@ #include <mach/irda.h> #include <mach/mmc.h> #include <mach/udc.h> -#include <mach/pxa2xx_spi.h> #include <mach/corgi.h> #include <mach/sharpsl_pm.h> diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 022c2fa4af0..4c766e3b4af 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -3,6 +3,7 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <linux/spi/pxa2xx_spi.h> #include <asm/pmu.h> #include <mach/udc.h> @@ -12,7 +13,6 @@ #include <mach/irda.h> #include <mach/ohci.h> #include <plat/pxa27x_keypad.h> -#include <mach/pxa2xx_spi.h> #include <mach/camera.h> #include <mach/audio.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index 4cefd1d18af..a78bb309773 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -26,6 +26,7 @@ #include <linux/spi/spi.h> #include <linux/spi/tdo24m.h> #include <linux/spi/libertas_spi.h> +#include <linux/spi/pxa2xx_spi.h> #include <linux/power_supply.h> #include <linux/apm-emulation.h> #include <linux/i2c.h> @@ -46,7 +47,6 @@ #include <plat/pxa27x_keypad.h> #include <plat/i2c.h> #include <mach/camera.h> -#include <mach/pxa2xx_spi.h> #include "generic.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index cacb21b7014..a908e0a5f39 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -33,6 +33,7 @@ #include <linux/regulator/max1586.h> #include <linux/spi/ads7846.h> #include <linux/spi/spi.h> +#include <linux/spi/pxa2xx_spi.h> #include <linux/usb/gpio_vbus.h> #include <mach/hardware.h> @@ -43,7 +44,6 @@ #include <mach/hx4700.h> #include <plat/i2c.h> #include <mach/irda.h> -#include <mach/pxa2xx_spi.h> #include <video/platform_lcd.h> #include <video/w100fb.h> diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c index ac6ee12e400..6cedc81da3b 100644 --- a/arch/arm/mach-pxa/icontrol.c +++ b/arch/arm/mach-pxa/icontrol.c @@ -24,7 +24,7 @@ #include <mach/mxm8x10.h> #include <linux/spi/spi.h> -#include <mach/pxa2xx_spi.h> +#include <linux/spi/pxa2xx_spi.h> #include <linux/can/platform/mcp251x.h> #include "generic.h" diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h b/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h deleted file mode 100644 index b87cecd9bbd..00000000000 --- a/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef PXA2XX_SPI_H_ -#define PXA2XX_SPI_H_ - -#define PXA2XX_CS_ASSERT (0x01) -#define PXA2XX_CS_DEASSERT (0x02) - -/* device.platform_data for SSP controller devices */ -struct pxa2xx_spi_master { - u32 clock_enable; - u16 num_chipselect; - u8 enable_dma; -}; - -/* spi_board_info.controller_data for SPI slave devices, - * copied to spi_device.platform_data ... mostly for dma tuning - */ -struct pxa2xx_spi_chip { - u8 tx_threshold; - u8 rx_threshold; - u8 dma_burst_size; - u32 timeout; - u8 enable_loopback; - int gpio_cs; - void (*cs_control)(u32 command); -}; - -extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info); - -#endif /*PXA2XX_SPI_H_*/ diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index 719c260597e..ccb7bfad17c 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -22,6 +22,7 @@ #include <linux/clk.h> #include <linux/gpio.h> #include <linux/spi/spi.h> +#include <linux/spi/pxa2xx_spi.h> #include <linux/smc91x.h> #include <linux/i2c.h> #include <linux/leds.h> @@ -42,7 +43,6 @@ #include <mach/pxa300.h> #include <mach/pxafb.h> #include <mach/mmc.h> -#include <mach/pxa2xx_spi.h> #include <plat/pxa27x_keypad.h> #include <mach/littleton.h> #include <plat/i2c.h> diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index d3375486c8c..3072dbea5c1 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -25,7 +25,7 @@ #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> -#include <mach/pxa2xx_spi.h> +#include <linux/spi/pxa2xx_spi.h> #include <asm/setup.h> #include <asm/memory.h> diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c index 8547c9abc40..1fc8a66407a 100644 --- a/arch/arm/mach-pxa/pcm027.c +++ b/arch/arm/mach-pxa/pcm027.c @@ -25,12 +25,12 @@ #include <linux/mtd/physmap.h> #include <linux/spi/spi.h> #include <linux/spi/max7301.h> +#include <linux/spi/pxa2xx_spi.h> #include <linux/leds.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <mach/pxa27x.h> -#include <mach/pxa2xx_spi.h> #include <mach/pcm027.h> #include "generic.h" diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 8451790cb48..4f0ff1ab623 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -25,6 +25,7 @@ #include <linux/i2c.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> +#include <linux/spi/pxa2xx_spi.h> #include <linux/mtd/sharpsl.h> #include <mach/hardware.h> @@ -43,7 +44,6 @@ #include <mach/irda.h> #include <mach/poodle.h> #include <mach/pxafb.h> -#include <mach/pxa2xx_spi.h> #include <plat/i2c.h> #include <asm/hardware/scoop.h> diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index 8fed027b12d..e68d46d415f 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c @@ -579,7 +579,8 @@ static int sharpsl_ac_check(void) static int sharpsl_pm_suspend(struct platform_device *pdev, pm_message_t state) { sharpsl_pm.flags |= SHARPSL_SUSPENDED; - flush_scheduled_work(); + flush_delayed_work_sync(&toggle_charger); + flush_delayed_work_sync(&sharpsl_bat); if (sharpsl_pm.charge_mode == CHRG_ON) sharpsl_pm.flags |= SHARPSL_DO_OFFLINE_CHRG; diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 0499a69e767..0bc938729c4 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -23,7 +23,7 @@ #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> #include <linux/spi/corgi_lcd.h> -#include <linux/mtd/physmap.h> +#include <linux/spi/pxa2xx_spi.h> #include <linux/mtd/sharpsl.h> #include <linux/input/matrix_keypad.h> #include <linux/regulator/machine.h> @@ -42,7 +42,6 @@ #include <mach/mmc.h> #include <mach/ohci.h> #include <mach/pxafb.h> -#include <mach/pxa2xx_spi.h> #include <mach/spitz.h> #include <mach/sharpsl_pm.h> #include <mach/smemc.h> diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c index 3498a142394..9a14fdb83c8 100644 --- a/arch/arm/mach-pxa/stargate2.c +++ b/arch/arm/mach-pxa/stargate2.c @@ -46,11 +46,11 @@ #include <plat/i2c.h> #include <mach/mmc.h> #include <mach/udc.h> -#include <mach/pxa2xx_spi.h> #include <mach/pxa27x-udc.h> #include <mach/smemc.h> #include <linux/spi/spi.h> +#include <linux/spi/pxa2xx_spi.h> #include <linux/mfd/da903x.h> #include <linux/sht15.h> diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 57d61ee9b22..af152e70cfc 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -32,6 +32,7 @@ #include <linux/gpio.h> #include <linux/pda_power.h> #include <linux/spi/spi.h> +#include <linux/spi/pxa2xx_spi.h> #include <linux/input/matrix_keypad.h> #include <asm/setup.h> @@ -44,7 +45,6 @@ #include <mach/mmc.h> #include <mach/udc.h> #include <mach/tosa_bt.h> -#include <mach/pxa2xx_spi.h> #include <mach/audio.h> #include <mach/smemc.h> diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index 43fc9ca1459..423261d63d0 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -40,7 +40,6 @@ #include <asm/mach/flash.h> #include <mach/pxa27x.h> -#include <mach/pxa2xx_spi.h> #include <mach/trizeps4.h> #include <mach/audio.h> #include <mach/pxafb.h> diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c index 527c2a1ed31..a323e076129 100644 --- a/arch/arm/mach-pxa/z2.c +++ b/arch/arm/mach-pxa/z2.c @@ -20,6 +20,7 @@ #include <linux/z2_battery.h> #include <linux/dma-mapping.h> #include <linux/spi/spi.h> +#include <linux/spi/pxa2xx_spi.h> #include <linux/spi/libertas_spi.h> #include <linux/spi/lms283gf05.h> #include <linux/power_supply.h> @@ -38,7 +39,6 @@ #include <mach/pxafb.h> #include <mach/mmc.h> #include <plat/pxa27x_keypad.h> -#include <mach/pxa2xx_spi.h> #include <plat/i2c.h> diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index c87f2b35ee0..bf034c7670d 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -20,6 +20,7 @@ #include <linux/dm9000.h> #include <linux/mmc/host.h> #include <linux/spi/spi.h> +#include <linux/spi/pxa2xx_spi.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> @@ -41,7 +42,6 @@ #include <mach/pxa27x-udc.h> #include <mach/udc.h> #include <mach/pxafb.h> -#include <mach/pxa2xx_spi.h> #include <mach/mfp-pxa27x.h> #include <mach/pm.h> #include <mach/audio.h> diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 63293335724..4d1b4c5c938 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -5,26 +5,27 @@ comment "SH-Mobile System Type" config ARCH_SH7367 bool "SH-Mobile G3 (SH7367)" select CPU_V6 - select HAVE_CLK - select CLKDEV_LOOKUP select SH_CLK_CPG - select GENERIC_CLOCKEVENTS + select ARCH_WANT_OPTIONAL_GPIOLIB config ARCH_SH7377 bool "SH-Mobile G4 (SH7377)" select CPU_V7 - select HAVE_CLK - select CLKDEV_LOOKUP select SH_CLK_CPG - select GENERIC_CLOCKEVENTS + select ARCH_WANT_OPTIONAL_GPIOLIB config ARCH_SH7372 bool "SH-Mobile AP4 (SH7372)" select CPU_V7 - select HAVE_CLK - select CLKDEV_LOOKUP select SH_CLK_CPG - select GENERIC_CLOCKEVENTS + select ARCH_WANT_OPTIONAL_GPIOLIB + +config ARCH_SH73A0 + bool "SH-Mobile AG5 (R8A73A00)" + select CPU_V7 + select SH_CLK_CPG + select ARCH_WANT_OPTIONAL_GPIOLIB + select ARM_GIC comment "SH-Mobile Board Type" @@ -57,6 +58,15 @@ config AP4EVB_WVGA endchoice +config MACH_AG5EVM + bool "AG5EVM board" + depends on ARCH_SH73A0 + +config MACH_MACKEREL + bool "mackerel board" + depends on ARCH_SH7372 + select ARCH_REQUIRE_GPIOLIB + comment "SH-Mobile System Configuration" menu "Memory configuration" @@ -64,8 +74,8 @@ menu "Memory configuration" config MEMORY_START hex "Physical memory start address" default "0x50000000" if MACH_G3EVM - default "0x40000000" if MACH_G4EVM - default "0x40000000" if MACH_AP4EVB + default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \ + MACH_MACKEREL default "0x00000000" ---help--- Tweak this only when porting to a new machine which does not @@ -76,7 +86,8 @@ config MEMORY_SIZE hex "Physical memory size" default "0x08000000" if MACH_G3EVM default "0x08000000" if MACH_G4EVM - default "0x10000000" if MACH_AP4EVB + default "0x20000000" if MACH_AG5EVM + default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL default "0x04000000" help This sets the default memory size assumed by your kernel. It can diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index ae416fe7daf..e2507f66f9d 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -9,14 +9,34 @@ obj-y := timer.o console.o clock.o pm_runtime.o obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o +obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o + +# SMP objects +smp-y := platsmp.o headsmp.o +smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o +smp-$(CONFIG_LOCAL_TIMERS) += localtimer.o +smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o # Pinmux setup -pfc-$(CONFIG_ARCH_SH7367) := pfc-sh7367.o -pfc-$(CONFIG_ARCH_SH7377) := pfc-sh7377.o -pfc-$(CONFIG_ARCH_SH7372) := pfc-sh7372.o -obj-$(CONFIG_GENERIC_GPIO) += $(pfc-y) +pfc-y := +pfc-$(CONFIG_ARCH_SH7367) += pfc-sh7367.o +pfc-$(CONFIG_ARCH_SH7377) += pfc-sh7377.o +pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o +pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o + +# IRQ objects +obj-$(CONFIG_ARCH_SH7367) += entry-intc.o +obj-$(CONFIG_ARCH_SH7377) += entry-intc.o +obj-$(CONFIG_ARCH_SH7372) += entry-intc.o +obj-$(CONFIG_ARCH_SH73A0) += entry-gic.o # Board objects obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o obj-$(CONFIG_MACH_G4EVM) += board-g4evm.o obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o +obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o +obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o + +# Framework support +obj-$(CONFIG_SMP) += $(smp-y) +obj-$(CONFIG_GENERIC_GPIO) += $(pfc-y) diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c new file mode 100644 index 00000000000..c18a740a415 --- /dev/null +++ b/arch/arm/mach-shmobile/board-ag5evm.c @@ -0,0 +1,315 @@ +/* + * arch/arm/mach-shmobile/board-ag5evm.c + * + * Copyright (C) 2010 Takashi Yoshii <yoshii.takashi.zj@renesas.com> + * Copyright (C) 2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/dma-mapping.h> +#include <linux/serial_sci.h> +#include <linux/smsc911x.h> +#include <linux/gpio.h> +#include <linux/input.h> +#include <linux/input/sh_keysc.h> +#include <linux/mmc/host.h> +#include <linux/mmc/sh_mmcif.h> + +#include <sound/sh_fsi.h> + +#include <mach/hardware.h> +#include <mach/sh73a0.h> +#include <mach/common.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/time.h> +#include <asm/hardware/gic.h> +#include <asm/hardware/cache-l2x0.h> +#include <asm/traps.h> + +static struct resource smsc9220_resources[] = { + [0] = { + .start = 0x14000000, + .end = 0x14000000 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(33), /* PINT1 */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc9220_platdata = { + .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +}; + +static struct platform_device eth_device = { + .name = "smsc911x", + .id = 0, + .dev = { + .platform_data = &smsc9220_platdata, + }, + .resource = smsc9220_resources, + .num_resources = ARRAY_SIZE(smsc9220_resources), +}; + +static struct sh_keysc_info keysc_platdata = { + .mode = SH_KEYSC_MODE_6, + .scan_timing = 3, + .delay = 100, + .keycodes = { + KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, KEY_G, + KEY_H, KEY_I, KEY_J, KEY_K, KEY_L, KEY_M, KEY_N, + KEY_O, KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T, KEY_U, + KEY_V, KEY_W, KEY_X, KEY_Y, KEY_Z, KEY_HOME, KEY_SLEEP, + KEY_SPACE, KEY_9, KEY_6, KEY_3, KEY_WAKEUP, KEY_RIGHT, \ + KEY_COFFEE, + KEY_0, KEY_8, KEY_5, KEY_2, KEY_DOWN, KEY_ENTER, KEY_UP, + KEY_KPASTERISK, KEY_7, KEY_4, KEY_1, KEY_STOP, KEY_LEFT, \ + KEY_COMPUTER, + }, +}; + +static struct resource keysc_resources[] = { + [0] = { + .name = "KEYSC", + .start = 0xe61b0000, + .end = 0xe61b0098 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(71), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device keysc_device = { + .name = "sh_keysc", + .id = 0, + .num_resources = ARRAY_SIZE(keysc_resources), + .resource = keysc_resources, + .dev = { + .platform_data = &keysc_platdata, + }, +}; + +/* FSI A */ +static struct sh_fsi_platform_info fsi_info = { + .porta_flags = SH_FSI_OUT_SLAVE_MODE | + SH_FSI_IN_SLAVE_MODE | + SH_FSI_OFMT(I2S) | + SH_FSI_IFMT(I2S), +}; + +static struct resource fsi_resources[] = { + [0] = { + .name = "FSI", + .start = 0xEC230000, + .end = 0xEC230400 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(146), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device fsi_device = { + .name = "sh_fsi2", + .id = -1, + .num_resources = ARRAY_SIZE(fsi_resources), + .resource = fsi_resources, + .dev = { + .platform_data = &fsi_info, + }, +}; + +static struct resource sh_mmcif_resources[] = { + [0] = { + .name = "MMCIF", + .start = 0xe6bd0000, + .end = 0xe6bd00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(141), + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = gic_spi(140), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_mmcif_plat_data sh_mmcif_platdata = { + .sup_pclk = 0, + .ocr = MMC_VDD_165_195, + .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, +}; + +static struct platform_device mmc_device = { + .name = "sh_mmcif", + .id = 0, + .dev = { + .dma_mask = NULL, + .coherent_dma_mask = 0xffffffff, + .platform_data = &sh_mmcif_platdata, + }, + .num_resources = ARRAY_SIZE(sh_mmcif_resources), + .resource = sh_mmcif_resources, +}; + +static struct platform_device *ag5evm_devices[] __initdata = { + ð_device, + &keysc_device, + &fsi_device, + &mmc_device, +}; + +static struct map_desc ag5evm_io_desc[] __initdata = { + /* create a 1:1 entity map for 0xe6xxxxxx + * used by CPGA, INTC and PFC. + */ + { + .virtual = 0xe6000000, + .pfn = __phys_to_pfn(0xe6000000), + .length = 256 << 20, + .type = MT_DEVICE_NONSHARED + }, +}; + +static void __init ag5evm_map_io(void) +{ + iotable_init(ag5evm_io_desc, ARRAY_SIZE(ag5evm_io_desc)); + + /* setup early devices and console here as well */ + sh73a0_add_early_devices(); + shmobile_setup_console(); +} + +#define PINTC_ADDR 0xe6900000 +#define PINTER0A (PINTC_ADDR + 0xa0) +#define PINTCR0A (PINTC_ADDR + 0xb0) + +void __init ag5evm_init_irq(void) +{ + sh73a0_init_irq(); + + /* setup PINT: enable PINTA2 as active low */ + __raw_writel(__raw_readl(PINTER0A) | (1<<29), PINTER0A); + __raw_writew(__raw_readw(PINTCR0A) | (2<<10), PINTCR0A); +} + +static void __init ag5evm_init(void) +{ + sh73a0_pinmux_init(); + + /* enable SCIFA2 */ + gpio_request(GPIO_FN_SCIFA2_TXD1, NULL); + gpio_request(GPIO_FN_SCIFA2_RXD1, NULL); + gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL); + gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL); + + /* enable KEYSC */ + gpio_request(GPIO_FN_KEYIN0_PU, NULL); + gpio_request(GPIO_FN_KEYIN1_PU, NULL); + gpio_request(GPIO_FN_KEYIN2_PU, NULL); + gpio_request(GPIO_FN_KEYIN3_PU, NULL); + gpio_request(GPIO_FN_KEYIN4_PU, NULL); + gpio_request(GPIO_FN_KEYIN5_PU, NULL); + gpio_request(GPIO_FN_KEYIN6_PU, NULL); + gpio_request(GPIO_FN_KEYIN7_PU, NULL); + gpio_request(GPIO_FN_KEYOUT0, NULL); + gpio_request(GPIO_FN_KEYOUT1, NULL); + gpio_request(GPIO_FN_KEYOUT2, NULL); + gpio_request(GPIO_FN_KEYOUT3, NULL); + gpio_request(GPIO_FN_KEYOUT4, NULL); + gpio_request(GPIO_FN_KEYOUT5, NULL); + gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL); + gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL); + gpio_request(GPIO_FN_KEYOUT8, NULL); + gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL); + + /* enable I2C channel 2 and 3 */ + gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL); + gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL); + gpio_request(GPIO_FN_PORT248_I2C_SCL3, NULL); + gpio_request(GPIO_FN_PORT249_I2C_SDA3, NULL); + + /* enable MMCIF */ + gpio_request(GPIO_FN_MMCCLK0, NULL); + gpio_request(GPIO_FN_MMCCMD0_PU, NULL); + gpio_request(GPIO_FN_MMCD0_0, NULL); + gpio_request(GPIO_FN_MMCD0_1, NULL); + gpio_request(GPIO_FN_MMCD0_2, NULL); + gpio_request(GPIO_FN_MMCD0_3, NULL); + gpio_request(GPIO_FN_MMCD0_4, NULL); + gpio_request(GPIO_FN_MMCD0_5, NULL); + gpio_request(GPIO_FN_MMCD0_6, NULL); + gpio_request(GPIO_FN_MMCD0_7, NULL); + gpio_request(GPIO_PORT208, NULL); /* Reset */ + gpio_direction_output(GPIO_PORT208, 1); + + /* enable SMSC911X */ + gpio_request(GPIO_PORT144, NULL); /* PINTA2 */ + gpio_direction_input(GPIO_PORT144); + gpio_request(GPIO_PORT145, NULL); /* RESET */ + gpio_direction_output(GPIO_PORT145, 1); + + /* FSI A */ + gpio_request(GPIO_FN_FSIACK, NULL); + gpio_request(GPIO_FN_FSIAILR, NULL); + gpio_request(GPIO_FN_FSIAIBT, NULL); + gpio_request(GPIO_FN_FSIAISLD, NULL); + gpio_request(GPIO_FN_FSIAOSLD, NULL); + +#ifdef CONFIG_CACHE_L2X0 + /* Shared attribute override enable, 64K*8way */ + l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff); +#endif + sh73a0_add_standard_devices(); + platform_add_devices(ag5evm_devices, ARRAY_SIZE(ag5evm_devices)); +} + +static void __init ag5evm_timer_init(void) +{ + sh73a0_clock_init(); + shmobile_timer.init(); + return; +} + +struct sys_timer ag5evm_timer = { + .init = ag5evm_timer_init, +}; + +MACHINE_START(AG5EVM, "ag5evm") + .map_io = ag5evm_map_io, + .init_irq = ag5evm_init_irq, + .handle_irq = shmobile_handle_irq_gic, + .init_machine = ag5evm_init, + .timer = &ag5evm_timer, +MACHINE_END diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index f92dbd0c06d..cd79d7c1ba0 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -273,6 +273,15 @@ static struct resource sh_mmcif_resources[] = { }, }; +static struct sh_mmcif_dma sh_mmcif_dma = { + .chan_priv_rx = { + .slave_id = SHDMA_SLAVE_MMCIF_RX, + }, + .chan_priv_tx = { + .slave_id = SHDMA_SLAVE_MMCIF_TX, + }, +}; + static struct sh_mmcif_plat_data sh_mmcif_plat = { .sup_pclk = 0, .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, @@ -280,6 +289,7 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = { MMC_CAP_8_BIT_DATA | MMC_CAP_NEEDS_POLL, .get_cd = slot_cn7_get_cd, + .dma = &sh_mmcif_dma, }; static struct platform_device sh_mmcif_device = { @@ -633,9 +643,8 @@ static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable) return -EIO; ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable); - clk_put(fsib_clk); if (ret < 0) - return ret; + goto fsi_set_rate_end; /* FSI DIV setting */ ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable); @@ -643,10 +652,14 @@ static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable) /* disable FSI B */ if (enable) __fsi_set_round_rate(fsib_clk, fsib_rate, 0); - return ret; + goto fsi_set_rate_end; } - return ackmd_bpfmd; + ret = ackmd_bpfmd; + +fsi_set_rate_end: + clk_put(fsib_clk); + return ret; } static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable) @@ -1174,7 +1187,7 @@ static void __init ap4evb_init(void) gpio_request(GPIO_FN_OVCN2_1, NULL); /* setup USB phy */ - __raw_writew(0x8a0a, 0xE6058130); /* USBCR2 */ + __raw_writew(0x8a0a, 0xE6058130); /* USBCR4 */ /* enable FSI2 port A (ak4643) */ gpio_request(GPIO_FN_FSIAIBT, NULL); @@ -1348,6 +1361,7 @@ static struct sys_timer ap4evb_timer = { MACHINE_START(AP4EVB, "ap4evb") .map_io = ap4evb_map_io, .init_irq = sh7372_init_irq, + .handle_irq = shmobile_handle_irq_intc, .init_machine = ap4evb_init, .timer = &ap4evb_timer, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c index 3b83d6320be..686b304a770 100644 --- a/arch/arm/mach-shmobile/board-g3evm.c +++ b/arch/arm/mach-shmobile/board-g3evm.c @@ -367,6 +367,7 @@ static struct sys_timer g3evm_timer = { MACHINE_START(G3EVM, "g3evm") .map_io = g3evm_map_io, .init_irq = sh7367_init_irq, + .handle_irq = shmobile_handle_irq_intc, .init_machine = g3evm_init, .timer = &g3evm_timer, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c index 5b3b582ef3f..c13f01280b7 100644 --- a/arch/arm/mach-shmobile/board-g4evm.c +++ b/arch/arm/mach-shmobile/board-g4evm.c @@ -394,6 +394,7 @@ static struct sys_timer g4evm_timer = { MACHINE_START(G4EVM, "g4evm") .map_io = g4evm_map_io, .init_irq = sh7377_init_irq, + .handle_irq = shmobile_handle_irq_intc, .init_machine = g4evm_init, .timer = &g4evm_timer, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c new file mode 100644 index 00000000000..5bcf5c1e139 --- /dev/null +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -0,0 +1,1200 @@ +/* + * mackerel board support + * + * Copyright (C) 2010 Renesas Solutions Corp. + * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * + * based on ap4evb + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <linux/delay.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/input.h> +#include <linux/io.h> +#include <linux/i2c.h> +#include <linux/leds.h> +#include <linux/mfd/sh_mobile_sdhi.h> +#include <linux/mfd/tmio.h> +#include <linux/mmc/host.h> +#include <linux/mmc/sh_mmcif.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/smsc911x.h> +#include <linux/sh_intc.h> +#include <linux/tca6416_keypad.h> +#include <linux/usb/r8a66597.h> + +#include <video/sh_mobile_hdmi.h> +#include <video/sh_mobile_lcdc.h> +#include <media/sh_mobile_ceu.h> +#include <media/soc_camera.h> +#include <media/soc_camera_platform.h> +#include <sound/sh_fsi.h> + +#include <mach/common.h> +#include <mach/sh7372.h> + +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/mach/map.h> +#include <asm/mach-types.h> + +/* + * Address Interface BusWidth note + * ------------------------------------------------------------------ + * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON + * 0x0800_0000 user area - + * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF + * 0x1400_0000 Ether (LAN9220) 16bit + * 0x1600_0000 user area - cannot use with NAND + * 0x1800_0000 user area - + * 0x1A00_0000 - + * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit + */ + +/* + * CPU mode + * + * SW4 | Boot Area| Master | Remarks + * 1 | 2 | 3 | 4 | 5 | 6 | 8 | | Processor| + * ----+-----+-----+-----+-----+-----+-----+----------+----------+-------------- + * ON | ON | OFF | ON | ON | OFF | OFF | External | System | External ROM + * ON | ON | ON | ON | ON | OFF | OFF | External | System | ROM Debug + * ON | ON | X | ON | OFF | OFF | OFF | Built-in | System | ROM Debug + * X | OFF | X | X | X | X | OFF | Built-in | System | MaskROM + * OFF | X | X | X | X | X | OFF | Built-in | System | MaskROM + * X | X | X | OFF | X | X | OFF | Built-in | System | MaskROM + * OFF | ON | OFF | X | X | OFF | ON | External | System | Standalone + * ON | OFF | OFF | X | X | OFF | ON | External | Realtime | Standalone +*/ + +/* + * NOR Flash ROM + * + * SW1 | SW2 | SW7 | NOR Flash ROM + * bit1 | bit1 bit2 | bit1 | Memory allocation + * ------+------------+------+------------------ + * OFF | ON OFF | ON | Area 0 + * OFF | ON OFF | OFF | Area 4 + */ + +/* + * SMSC 9220 + * + * SW1 SMSC 9220 + * ----------------------- + * ON access disable + * OFF access enable + */ + +/* + * NAND Flash ROM + * + * SW1 | SW2 | SW7 | NAND Flash ROM + * bit1 | bit1 bit2 | bit2 | Memory allocation + * ------+------------+------+------------------ + * OFF | ON OFF | ON | FCE 0 + * OFF | ON OFF | OFF | FCE 1 + */ + +/* + * External interrupt pin settings + * + * IRQX | pin setting | device | level + * ------+--------------------+--------------------+------- + * IRQ0 | ICR1A.IRQ0SA=0010 | SDHI2 card detect | Low + * IRQ6 | ICR1A.IRQ6SA=0011 | Ether(LAN9220) | High + * IRQ7 | ICR1A.IRQ7SA=0010 | LCD Tuch Panel | Low + * IRQ8 | ICR2A.IRQ8SA=0010 | MMC/SD card detect | Low + * IRQ9 | ICR2A.IRQ9SA=0010 | KEY(TCA6408) | Low + * IRQ21 | ICR4A.IRQ21SA=0011 | Sensor(ADXL345) | High + * IRQ22 | ICR4A.IRQ22SA=0011 | Sensor(AK8975) | High + */ + +/* + * USB + * + * USB0 : CN22 : Function + * USB1 : CN31 : Function/Host *1 + * + * J30 (for CN31) *1 + * ----------+---------------+------------- + * 1-2 short | VBUS 5V | Host + * open | external VBUS | Function + * + * *1 + * CN31 is used as Host in Linux. + */ + +/* + * SDHI0 (CN12) + * + * SW56 : OFF + * + */ + +/* MMC /SDHI1 (CN7) + * + * I/O voltage : 1.8v + * + * Power voltage : 1.8v or 3.3v + * J22 : select power voltage *1 + * 1-2 pin : 1.8v + * 2-3 pin : 3.3v + * + * *1 + * Please change J22 depends the card to be used. + * MMC's OCR field set to support either voltage for the card inserted. + * + * SW1 | SW33 + * | bit1 | bit2 | bit3 | bit4 + * -------------+------+------+------+------- + * MMC0 OFF | OFF | ON | ON | X + * MMC1 ON | OFF | ON | X | ON + * SDHI1 OFF | ON | X | OFF | ON + * + */ + +/* + * SDHI2 (CN23) + * + * microSD card sloct + * + */ + +/* + * FIXME !! + * + * gpio_no_direction + * are quick_hack. + * + * current gpio frame work doesn't have + * the method to control only pull up/down/free. + * this function should be replaced by correct gpio function + */ +static void __init gpio_no_direction(u32 addr) +{ + __raw_writeb(0x00, addr); +} + +/* MTD */ +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = 512 * 1024, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "bootenv", + .offset = MTDPART_OFS_APPEND, + .size = 512 * 1024, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel_ro", + .offset = MTDPART_OFS_APPEND, + .size = 8 * 1024 * 1024, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 8 * 1024 * 1024, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 2, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = 0x00000000, + .end = 0x08000000 - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + +/* SMSC */ +static struct resource smc911x_resources[] = { + { + .start = 0x14000000, + .end = 0x16000000 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = evt2irq(0x02c0) /* IRQ6A */, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, + }, +}; + +static struct smsc911x_platform_config smsc911x_info = { + .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +}; + +static struct platform_device smc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smc911x_resources), + .resource = smc911x_resources, + .dev = { + .platform_data = &smsc911x_info, + }, +}; + +/* LCDC */ +static struct fb_videomode mackerel_lcdc_modes[] = { + { + .name = "WVGA Panel", + .xres = 800, + .yres = 480, + .left_margin = 220, + .right_margin = 110, + .hsync_len = 70, + .upper_margin = 20, + .lower_margin = 5, + .vsync_len = 5, + .sync = 0, + }, +}; + +static struct sh_mobile_lcdc_info lcdc_info = { + .clock_source = LCDC_CLK_BUS, + .ch[0] = { + .chan = LCDC_CHAN_MAINLCD, + .bpp = 16, + .lcd_cfg = mackerel_lcdc_modes, + .num_cfg = ARRAY_SIZE(mackerel_lcdc_modes), + .interface_type = RGB24, + .clock_divider = 2, + .flags = 0, + .lcd_size_cfg.width = 152, + .lcd_size_cfg.height = 91, + } +}; + +static struct resource lcdc_resources[] = { + [0] = { + .name = "LCDC", + .start = 0xfe940000, + .end = 0xfe943fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = intcs_evt2irq(0x580), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device lcdc_device = { + .name = "sh_mobile_lcdc_fb", + .num_resources = ARRAY_SIZE(lcdc_resources), + .resource = lcdc_resources, + .dev = { + .platform_data = &lcdc_info, + .coherent_dma_mask = ~0, + }, +}; + +/* HDMI */ +static struct sh_mobile_lcdc_info hdmi_lcdc_info = { + .clock_source = LCDC_CLK_EXTERNAL, + .ch[0] = { + .chan = LCDC_CHAN_MAINLCD, + .bpp = 16, + .interface_type = RGB24, + .clock_divider = 1, + .flags = LCDC_FLAGS_DWPOL, + } +}; + +static struct resource hdmi_lcdc_resources[] = { + [0] = { + .name = "LCDC1", + .start = 0xfe944000, + .end = 0xfe947fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = intcs_evt2irq(0x1780), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device hdmi_lcdc_device = { + .name = "sh_mobile_lcdc_fb", + .num_resources = ARRAY_SIZE(hdmi_lcdc_resources), + .resource = hdmi_lcdc_resources, + .id = 1, + .dev = { + .platform_data = &hdmi_lcdc_info, + .coherent_dma_mask = ~0, + }, +}; + +static struct sh_mobile_hdmi_info hdmi_info = { + .lcd_chan = &hdmi_lcdc_info.ch[0], + .lcd_dev = &hdmi_lcdc_device.dev, + .flags = HDMI_SND_SRC_SPDIF, +}; + +static struct resource hdmi_resources[] = { + [0] = { + .name = "HDMI", + .start = 0xe6be0000, + .end = 0xe6be00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* There's also an HDMI interrupt on INTCS @ 0x18e0 */ + .start = evt2irq(0x17e0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device hdmi_device = { + .name = "sh-mobile-hdmi", + .num_resources = ARRAY_SIZE(hdmi_resources), + .resource = hdmi_resources, + .id = -1, + .dev = { + .platform_data = &hdmi_info, + }, +}; + +static int __init hdmi_init_pm_clock(void) +{ + struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick"); + int ret; + long rate; + + if (IS_ERR(hdmi_ick)) { + ret = PTR_ERR(hdmi_ick); + pr_err("Cannot get HDMI ICK: %d\n", ret); + goto out; + } + + ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk); + if (ret < 0) { + pr_err("Cannot set PLLC2 parent: %d, %d users\n", + ret, sh7372_pllc2_clk.usecount); + goto out; + } + + pr_debug("PLLC2 initial frequency %lu\n", + clk_get_rate(&sh7372_pllc2_clk)); + + rate = clk_round_rate(&sh7372_pllc2_clk, 594000000); + if (rate < 0) { + pr_err("Cannot get suitable rate: %ld\n", rate); + ret = rate; + goto out; + } + + ret = clk_set_rate(&sh7372_pllc2_clk, rate); + if (ret < 0) { + pr_err("Cannot set rate %ld: %d\n", rate, ret); + goto out; + } + + ret = clk_enable(&sh7372_pllc2_clk); + if (ret < 0) { + pr_err("Cannot enable pllc2 clock\n"); + goto out; + } + + pr_debug("PLLC2 set frequency %lu\n", rate); + + ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk); + if (ret < 0) { + pr_err("Cannot set HDMI parent: %d\n", ret); + goto out; + } + +out: + if (!IS_ERR(hdmi_ick)) + clk_put(hdmi_ick); + return ret; +} +device_initcall(hdmi_init_pm_clock); + +/* USB1 (Host) */ +static void usb1_host_port_power(int port, int power) +{ + if (!power) /* only power-on is supported for now */ + return; + + /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */ + __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008); +} + +static struct r8a66597_platdata usb1_host_data = { + .on_chip = 1, + .port_power = usb1_host_port_power, +}; + +static struct resource usb1_host_resources[] = { + [0] = { + .name = "USBHS", + .start = 0xE68B0000, + .end = 0xE68B00E6 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x1ce0) /* USB1_USB1I0 */, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device usb1_host_device = { + .name = "r8a66597_hcd", + .id = 1, + .dev = { + .dma_mask = NULL, /* not use dma */ + .coherent_dma_mask = 0xffffffff, + .platform_data = &usb1_host_data, + }, + .num_resources = ARRAY_SIZE(usb1_host_resources), + .resource = usb1_host_resources, +}; + +/* LED */ +static struct gpio_led mackerel_leds[] = { + { + .name = "led0", + .gpio = GPIO_PORT0, + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, + { + .name = "led1", + .gpio = GPIO_PORT1, + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, + { + .name = "led2", + .gpio = GPIO_PORT2, + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, + { + .name = "led3", + .gpio = GPIO_PORT159, + .default_state = LEDS_GPIO_DEFSTATE_ON, + } +}; + +static struct gpio_led_platform_data mackerel_leds_pdata = { + .leds = mackerel_leds, + .num_leds = ARRAY_SIZE(mackerel_leds), +}; + +static struct platform_device leds_device = { + .name = "leds-gpio", + .id = 0, + .dev = { + .platform_data = &mackerel_leds_pdata, + }, +}; + +/* FSI */ +#define IRQ_FSI evt2irq(0x1840) +static int __fsi_set_round_rate(struct clk *clk, long rate, int enable) +{ + int ret; + + if (rate <= 0) + return 0; + + if (!enable) { + clk_disable(clk); + return 0; + } + + ret = clk_set_rate(clk, clk_round_rate(clk, rate)); + if (ret < 0) + return ret; + + return clk_enable(clk); +} + +static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable) +{ + struct clk *fsib_clk; + struct clk *fdiv_clk = &sh7372_fsidivb_clk; + long fsib_rate = 0; + long fdiv_rate = 0; + int ackmd_bpfmd; + int ret; + + /* FSIA is slave mode. nothing to do here */ + if (is_porta) + return 0; + + /* clock start */ + switch (rate) { + case 44100: + fsib_rate = rate * 256; + ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64; + break; + case 48000: + fsib_rate = 85428000; /* around 48kHz x 256 x 7 */ + fdiv_rate = rate * 256; + ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64; + break; + default: + pr_err("unsupported rate in FSI2 port B\n"); + return -EINVAL; + } + + /* FSI B setting */ + fsib_clk = clk_get(dev, "ickb"); + if (IS_ERR(fsib_clk)) + return -EIO; + + /* fsib */ + ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable); + if (ret < 0) + goto fsi_set_rate_end; + + /* FSI DIV */ + ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable); + if (ret < 0) { + /* disable FSI B */ + if (enable) + __fsi_set_round_rate(fsib_clk, fsib_rate, 0); + goto fsi_set_rate_end; + } + + ret = ackmd_bpfmd; + +fsi_set_rate_end: + clk_put(fsib_clk); + return ret; +} + +static struct sh_fsi_platform_info fsi_info = { + .porta_flags = SH_FSI_BRS_INV | + SH_FSI_OUT_SLAVE_MODE | + SH_FSI_IN_SLAVE_MODE | + SH_FSI_OFMT(PCM) | + SH_FSI_IFMT(PCM), + + .portb_flags = SH_FSI_BRS_INV | + SH_FSI_BRM_INV | + SH_FSI_LRS_INV | + SH_FSI_OFMT(SPDIF), + + .set_rate = fsi_set_rate, +}; + +static struct resource fsi_resources[] = { + [0] = { + .name = "FSI", + .start = 0xFE3C0000, + .end = 0xFE3C0400 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_FSI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device fsi_device = { + .name = "sh_fsi2", + .id = -1, + .num_resources = ARRAY_SIZE(fsi_resources), + .resource = fsi_resources, + .dev = { + .platform_data = &fsi_info, + }, +}; + +static struct platform_device fsi_ak4643_device = { + .name = "sh_fsi2_a_ak4643", +}; + +/* + * The card detect pin of the top SD/MMC slot (CN7) is active low and is + * connected to GPIO A22 of SH7372 (GPIO_PORT41). + */ +static int slot_cn7_get_cd(struct platform_device *pdev) +{ + if (gpio_is_valid(GPIO_PORT41)) + return !gpio_get_value(GPIO_PORT41); + else + return -ENXIO; +} + +/* SDHI0 */ +static struct sh_mobile_sdhi_info sdhi0_info = { + .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, + .tmio_caps = MMC_CAP_SD_HIGHSPEED, +}; + +static struct resource sdhi0_resources[] = { + [0] = { + .name = "SDHI0", + .start = 0xe6850000, + .end = 0xe68501ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x0e00) /* SDHI0 */, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sdhi0_device = { + .name = "sh_mobile_sdhi", + .num_resources = ARRAY_SIZE(sdhi0_resources), + .resource = sdhi0_resources, + .id = 0, + .dev = { + .platform_data = &sdhi0_info, + }, +}; + +#if !defined(CONFIG_MMC_SH_MMCIF) +/* SDHI1 */ +static struct sh_mobile_sdhi_info sdhi1_info = { + .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, + .tmio_ocr_mask = MMC_VDD_165_195, + .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, + .tmio_caps = MMC_CAP_SD_HIGHSPEED | + MMC_CAP_NEEDS_POLL, + .get_cd = slot_cn7_get_cd, +}; + +static struct resource sdhi1_resources[] = { + [0] = { + .name = "SDHI1", + .start = 0xe6860000, + .end = 0xe68601ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x0e80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sdhi1_device = { + .name = "sh_mobile_sdhi", + .num_resources = ARRAY_SIZE(sdhi1_resources), + .resource = sdhi1_resources, + .id = 1, + .dev = { + .platform_data = &sdhi1_info, + }, +}; +#endif + +/* SDHI2 */ +static struct sh_mobile_sdhi_info sdhi2_info = { + .dma_slave_tx = SHDMA_SLAVE_SDHI2_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI2_RX, + .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, + .tmio_caps = MMC_CAP_SD_HIGHSPEED | + MMC_CAP_NEEDS_POLL, +}; + +static struct resource sdhi2_resources[] = { + [0] = { + .name = "SDHI2", + .start = 0xe6870000, + .end = 0xe68701ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x1200), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sdhi2_device = { + .name = "sh_mobile_sdhi", + .num_resources = ARRAY_SIZE(sdhi2_resources), + .resource = sdhi2_resources, + .id = 2, + .dev = { + .platform_data = &sdhi2_info, + }, +}; + +/* SH_MMCIF */ +static struct resource sh_mmcif_resources[] = { + [0] = { + .name = "MMCIF", + .start = 0xE6BD0000, + .end = 0xE6BD00FF, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* MMC ERR */ + .start = evt2irq(0x1ac0), + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* MMC NOR */ + .start = evt2irq(0x1ae0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_mmcif_plat_data sh_mmcif_plat = { + .sup_pclk = 0, + .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, + .caps = MMC_CAP_4_BIT_DATA | + MMC_CAP_8_BIT_DATA | + MMC_CAP_NEEDS_POLL, + .get_cd = slot_cn7_get_cd, +}; + +static struct platform_device sh_mmcif_device = { + .name = "sh_mmcif", + .id = 0, + .dev = { + .dma_mask = NULL, + .coherent_dma_mask = 0xffffffff, + .platform_data = &sh_mmcif_plat, + }, + .num_resources = ARRAY_SIZE(sh_mmcif_resources), + .resource = sh_mmcif_resources, +}; + + +static int mackerel_camera_add(struct soc_camera_link *icl, struct device *dev); +static void mackerel_camera_del(struct soc_camera_link *icl); + +static int camera_set_capture(struct soc_camera_platform_info *info, + int enable) +{ + return 0; /* camera sensor always enabled */ +} + +static struct soc_camera_platform_info camera_info = { + .format_name = "UYVY", + .format_depth = 16, + .format = { + .code = V4L2_MBUS_FMT_UYVY8_2X8, + .colorspace = V4L2_COLORSPACE_SMPTE170M, + .field = V4L2_FIELD_NONE, + .width = 640, + .height = 480, + }, + .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | + SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8 | + SOCAM_DATA_ACTIVE_HIGH, + .set_capture = camera_set_capture, +}; + +static struct soc_camera_link camera_link = { + .bus_id = 0, + .add_device = mackerel_camera_add, + .del_device = mackerel_camera_del, + .module_name = "soc_camera_platform", + .priv = &camera_info, +}; + +static void dummy_release(struct device *dev) +{ +} + +static struct platform_device camera_device = { + .name = "soc_camera_platform", + .dev = { + .platform_data = &camera_info, + .release = dummy_release, + }, +}; + +static int mackerel_camera_add(struct soc_camera_link *icl, + struct device *dev) +{ + if (icl != &camera_link) + return -ENODEV; + + camera_info.dev = dev; + + return platform_device_register(&camera_device); +} + +static void mackerel_camera_del(struct soc_camera_link *icl) +{ + if (icl != &camera_link) + return; + + platform_device_unregister(&camera_device); + memset(&camera_device.dev.kobj, 0, + sizeof(camera_device.dev.kobj)); +} + +static struct sh_mobile_ceu_info sh_mobile_ceu_info = { + .flags = SH_CEU_FLAG_USE_8BIT_BUS, +}; + +static struct resource ceu_resources[] = { + [0] = { + .name = "CEU", + .start = 0xfe910000, + .end = 0xfe91009f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = intcs_evt2irq(0x880), + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device ceu_device = { + .name = "sh_mobile_ceu", + .id = 0, /* "ceu0" clock */ + .num_resources = ARRAY_SIZE(ceu_resources), + .resource = ceu_resources, + .dev = { + .platform_data = &sh_mobile_ceu_info, + }, +}; + +static struct platform_device mackerel_camera = { + .name = "soc-camera-pdrv", + .id = 0, + .dev = { + .platform_data = &camera_link, + }, +}; + +static struct platform_device *mackerel_devices[] __initdata = { + &nor_flash_device, + &smc911x_device, + &lcdc_device, + &usb1_host_device, + &leds_device, + &fsi_device, + &fsi_ak4643_device, + &sdhi0_device, +#if !defined(CONFIG_MMC_SH_MMCIF) + &sdhi1_device, +#endif + &sdhi2_device, + &sh_mmcif_device, + &ceu_device, + &mackerel_camera, + &hdmi_lcdc_device, + &hdmi_device, +}; + +/* Keypad Initialization */ +#define KEYPAD_BUTTON(ev_type, ev_code, act_low) \ +{ \ + .type = ev_type, \ + .code = ev_code, \ + .active_low = act_low, \ +} + +#define KEYPAD_BUTTON_LOW(event_code) KEYPAD_BUTTON(EV_KEY, event_code, 1) + +static struct tca6416_button mackerel_gpio_keys[] = { + KEYPAD_BUTTON_LOW(KEY_HOME), + KEYPAD_BUTTON_LOW(KEY_MENU), + KEYPAD_BUTTON_LOW(KEY_BACK), + KEYPAD_BUTTON_LOW(KEY_POWER), +}; + +static struct tca6416_keys_platform_data mackerel_tca6416_keys_info = { + .buttons = mackerel_gpio_keys, + .nbuttons = ARRAY_SIZE(mackerel_gpio_keys), + .rep = 1, + .use_polling = 0, + .pinmask = 0x000F, +}; + +/* I2C */ +#define IRQ9 evt2irq(0x0320) + +static struct i2c_board_info i2c0_devices[] = { + { + I2C_BOARD_INFO("ak4643", 0x13), + }, + /* Keypad */ + { + I2C_BOARD_INFO("tca6408-keys", 0x20), + .platform_data = &mackerel_tca6416_keys_info, + .irq = IRQ9, + }, +}; + +#define IRQ21 evt2irq(0x32a0) + +static struct i2c_board_info i2c1_devices[] = { + /* Accelerometer */ + { + I2C_BOARD_INFO("adxl34x", 0x53), + .irq = IRQ21, + }, +}; + +static struct map_desc mackerel_io_desc[] __initdata = { + /* create a 1:1 entity map for 0xe6xxxxxx + * used by CPGA, INTC and PFC. + */ + { + .virtual = 0xe6000000, + .pfn = __phys_to_pfn(0xe6000000), + .length = 256 << 20, + .type = MT_DEVICE_NONSHARED + }, +}; + +static void __init mackerel_map_io(void) +{ + iotable_init(mackerel_io_desc, ARRAY_SIZE(mackerel_io_desc)); + + /* setup early devices and console here as well */ + sh7372_add_early_devices(); + shmobile_setup_console(); +} + +#define GPIO_PORT9CR 0xE6051009 +#define GPIO_PORT10CR 0xE605100A +#define SRCR4 0xe61580bc +#define USCCR1 0xE6058144 +static void __init mackerel_init(void) +{ + u32 srcr4; + struct clk *clk; + + sh7372_pinmux_init(); + + /* enable SCIFA0 */ + gpio_request(GPIO_FN_SCIFA0_TXD, NULL); + gpio_request(GPIO_FN_SCIFA0_RXD, NULL); + + /* enable SMSC911X */ + gpio_request(GPIO_FN_CS5A, NULL); + gpio_request(GPIO_FN_IRQ6_39, NULL); + + /* LCDC */ + gpio_request(GPIO_FN_LCDD23, NULL); + gpio_request(GPIO_FN_LCDD22, NULL); + gpio_request(GPIO_FN_LCDD21, NULL); + gpio_request(GPIO_FN_LCDD20, NULL); + gpio_request(GPIO_FN_LCDD19, NULL); + gpio_request(GPIO_FN_LCDD18, NULL); + gpio_request(GPIO_FN_LCDD17, NULL); + gpio_request(GPIO_FN_LCDD16, NULL); + gpio_request(GPIO_FN_LCDD15, NULL); + gpio_request(GPIO_FN_LCDD14, NULL); + gpio_request(GPIO_FN_LCDD13, NULL); + gpio_request(GPIO_FN_LCDD12, NULL); + gpio_request(GPIO_FN_LCDD11, NULL); + gpio_request(GPIO_FN_LCDD10, NULL); + gpio_request(GPIO_FN_LCDD9, NULL); + gpio_request(GPIO_FN_LCDD8, NULL); + gpio_request(GPIO_FN_LCDD7, NULL); + gpio_request(GPIO_FN_LCDD6, NULL); + gpio_request(GPIO_FN_LCDD5, NULL); + gpio_request(GPIO_FN_LCDD4, NULL); + gpio_request(GPIO_FN_LCDD3, NULL); + gpio_request(GPIO_FN_LCDD2, NULL); + gpio_request(GPIO_FN_LCDD1, NULL); + gpio_request(GPIO_FN_LCDD0, NULL); + gpio_request(GPIO_FN_LCDDISP, NULL); + gpio_request(GPIO_FN_LCDDCK, NULL); + + gpio_request(GPIO_PORT31, NULL); /* backlight */ + gpio_direction_output(GPIO_PORT31, 1); + + gpio_request(GPIO_PORT151, NULL); /* LCDDON */ + gpio_direction_output(GPIO_PORT151, 1); + + /* USB enable */ + gpio_request(GPIO_FN_VBUS0_1, NULL); + gpio_request(GPIO_FN_IDIN_1_18, NULL); + gpio_request(GPIO_FN_PWEN_1_115, NULL); + gpio_request(GPIO_FN_OVCN_1_114, NULL); + gpio_request(GPIO_FN_EXTLP_1, NULL); + gpio_request(GPIO_FN_OVCN2_1, NULL); + + /* setup USB phy */ + __raw_writew(0x8a0a, 0xE6058130); /* USBCR4 */ + + /* enable FSI2 port A (ak4643) */ + gpio_request(GPIO_FN_FSIAIBT, NULL); + gpio_request(GPIO_FN_FSIAILR, NULL); + gpio_request(GPIO_FN_FSIAISLD, NULL); + gpio_request(GPIO_FN_FSIAOSLD, NULL); + gpio_request(GPIO_PORT161, NULL); + gpio_direction_output(GPIO_PORT161, 0); /* slave */ + + gpio_request(GPIO_PORT9, NULL); + gpio_request(GPIO_PORT10, NULL); + gpio_no_direction(GPIO_PORT9CR); /* FSIAOBT needs no direction */ + gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */ + + intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */ + + /* setup FSI2 port B (HDMI) */ + gpio_request(GPIO_FN_FSIBCK, NULL); + __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */ + + /* set SPU2 clock to 119.6 MHz */ + clk = clk_get(NULL, "spu_clk"); + if (!IS_ERR(clk)) { + clk_set_rate(clk, clk_round_rate(clk, 119600000)); + clk_put(clk); + } + + /* enable Keypad */ + gpio_request(GPIO_FN_IRQ9_42, NULL); + set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH); + + /* enable Accelerometer */ + gpio_request(GPIO_FN_IRQ21, NULL); + set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); + + /* enable SDHI0 */ + gpio_request(GPIO_FN_SDHICD0, NULL); + gpio_request(GPIO_FN_SDHIWP0, NULL); + gpio_request(GPIO_FN_SDHICMD0, NULL); + gpio_request(GPIO_FN_SDHICLK0, NULL); + gpio_request(GPIO_FN_SDHID0_3, NULL); + gpio_request(GPIO_FN_SDHID0_2, NULL); + gpio_request(GPIO_FN_SDHID0_1, NULL); + gpio_request(GPIO_FN_SDHID0_0, NULL); + +#if !defined(CONFIG_MMC_SH_MMCIF) + /* enable SDHI1 */ + gpio_request(GPIO_FN_SDHICMD1, NULL); + gpio_request(GPIO_FN_SDHICLK1, NULL); + gpio_request(GPIO_FN_SDHID1_3, NULL); + gpio_request(GPIO_FN_SDHID1_2, NULL); + gpio_request(GPIO_FN_SDHID1_1, NULL); + gpio_request(GPIO_FN_SDHID1_0, NULL); +#endif + /* card detect pin for MMC slot (CN7) */ + gpio_request(GPIO_PORT41, NULL); + gpio_direction_input(GPIO_PORT41); + + /* enable SDHI2 */ + gpio_request(GPIO_FN_SDHICMD2, NULL); + gpio_request(GPIO_FN_SDHICLK2, NULL); + gpio_request(GPIO_FN_SDHID2_3, NULL); + gpio_request(GPIO_FN_SDHID2_2, NULL); + gpio_request(GPIO_FN_SDHID2_1, NULL); + gpio_request(GPIO_FN_SDHID2_0, NULL); + + /* MMCIF */ + gpio_request(GPIO_FN_MMCD0_0, NULL); + gpio_request(GPIO_FN_MMCD0_1, NULL); + gpio_request(GPIO_FN_MMCD0_2, NULL); + gpio_request(GPIO_FN_MMCD0_3, NULL); + gpio_request(GPIO_FN_MMCD0_4, NULL); + gpio_request(GPIO_FN_MMCD0_5, NULL); + gpio_request(GPIO_FN_MMCD0_6, NULL); + gpio_request(GPIO_FN_MMCD0_7, NULL); + gpio_request(GPIO_FN_MMCCMD0, NULL); + gpio_request(GPIO_FN_MMCCLK0, NULL); + + /* enable GPS module (GT-720F) */ + gpio_request(GPIO_FN_SCIFA2_TXD1, NULL); + gpio_request(GPIO_FN_SCIFA2_RXD1, NULL); + + /* CEU */ + gpio_request(GPIO_FN_VIO_CLK, NULL); + gpio_request(GPIO_FN_VIO_VD, NULL); + gpio_request(GPIO_FN_VIO_HD, NULL); + gpio_request(GPIO_FN_VIO_FIELD, NULL); + gpio_request(GPIO_FN_VIO_CKO, NULL); + gpio_request(GPIO_FN_VIO_D7, NULL); + gpio_request(GPIO_FN_VIO_D6, NULL); + gpio_request(GPIO_FN_VIO_D5, NULL); + gpio_request(GPIO_FN_VIO_D4, NULL); + gpio_request(GPIO_FN_VIO_D3, NULL); + gpio_request(GPIO_FN_VIO_D2, NULL); + gpio_request(GPIO_FN_VIO_D1, NULL); + gpio_request(GPIO_FN_VIO_D0, NULL); + + /* HDMI */ + gpio_request(GPIO_FN_HDMI_HPD, NULL); + gpio_request(GPIO_FN_HDMI_CEC, NULL); + + /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */ + srcr4 = __raw_readl(SRCR4); + __raw_writel(srcr4 | (1 << 13), SRCR4); + udelay(50); + __raw_writel(srcr4 & ~(1 << 13), SRCR4); + + i2c_register_board_info(0, i2c0_devices, + ARRAY_SIZE(i2c0_devices)); + i2c_register_board_info(1, i2c1_devices, + ARRAY_SIZE(i2c1_devices)); + + sh7372_add_standard_devices(); + + platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices)); +} + +static void __init mackerel_timer_init(void) +{ + sh7372_clock_init(); + shmobile_timer.init(); + + /* External clock source */ + clk_set_rate(&sh7372_dv_clki_clk, 27000000); +} + +static struct sys_timer mackerel_timer = { + .init = mackerel_timer_init, +}; + +MACHINE_START(MACKEREL, "mackerel") + .map_io = mackerel_map_io, + .init_irq = sh7372_init_irq, + .handle_irq = shmobile_handle_irq_intc, + .init_machine = mackerel_init, + .timer = &mackerel_timer, +MACHINE_END diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c new file mode 100644 index 00000000000..720a71433be --- /dev/null +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -0,0 +1,356 @@ +/* + * sh73a0 clock framework support + * + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/sh_clk.h> +#include <linux/clkdev.h> +#include <mach/common.h> + +#define FRQCRA 0xe6150000 +#define FRQCRB 0xe6150004 +#define FRQCRD 0xe61500e4 +#define VCLKCR1 0xe6150008 +#define VCLKCR2 0xe615000C +#define VCLKCR3 0xe615001C +#define ZBCKCR 0xe6150010 +#define FLCKCR 0xe6150014 +#define SD0CKCR 0xe6150074 +#define SD1CKCR 0xe6150078 +#define SD2CKCR 0xe615007C +#define FSIACKCR 0xe6150018 +#define FSIBCKCR 0xe6150090 +#define SUBCKCR 0xe6150080 +#define SPUACKCR 0xe6150084 +#define SPUVCKCR 0xe6150094 +#define MSUCKCR 0xe6150088 +#define HSICKCR 0xe615008C +#define MFCK1CR 0xe6150098 +#define MFCK2CR 0xe615009C +#define DSITCKCR 0xe6150060 +#define DSI0PCKCR 0xe6150064 +#define DSI1PCKCR 0xe6150068 +#define DSI0PHYCR 0xe615006C +#define DSI1PHYCR 0xe6150070 +#define PLLECR 0xe61500d0 +#define PLL0CR 0xe61500d8 +#define PLL1CR 0xe6150028 +#define PLL2CR 0xe615002c +#define PLL3CR 0xe61500dc +#define SMSTPCR0 0xe6150130 +#define SMSTPCR1 0xe6150134 +#define SMSTPCR2 0xe6150138 +#define SMSTPCR3 0xe615013c +#define SMSTPCR4 0xe6150140 +#define SMSTPCR5 0xe6150144 +#define CKSCR 0xe61500c0 + +/* Fixed 32 KHz root clock from EXTALR pin */ +static struct clk r_clk = { + .rate = 32768, +}; + +/* + * 26MHz default rate for the EXTAL1 root input clock. + * If needed, reset this with clk_set_rate() from the platform code. + */ +struct clk sh73a0_extal1_clk = { + .rate = 26000000, +}; + +/* + * 48MHz default rate for the EXTAL2 root input clock. + * If needed, reset this with clk_set_rate() from the platform code. + */ +struct clk sh73a0_extal2_clk = { + .rate = 48000000, +}; + +/* A fixed divide-by-2 block */ +static unsigned long div2_recalc(struct clk *clk) +{ + return clk->parent->rate / 2; +} + +static struct clk_ops div2_clk_ops = { + .recalc = div2_recalc, +}; + +/* Divide extal1 by two */ +static struct clk extal1_div2_clk = { + .ops = &div2_clk_ops, + .parent = &sh73a0_extal1_clk, +}; + +/* Divide extal2 by two */ +static struct clk extal2_div2_clk = { + .ops = &div2_clk_ops, + .parent = &sh73a0_extal2_clk, +}; + +static struct clk_ops main_clk_ops = { + .recalc = followparent_recalc, +}; + +/* Main clock */ +static struct clk main_clk = { + .ops = &main_clk_ops, +}; + +/* PLL0, PLL1, PLL2, PLL3 */ +static unsigned long pll_recalc(struct clk *clk) +{ + unsigned long mult = 1; + + if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) + mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1); + + return clk->parent->rate * mult; +} + +static struct clk_ops pll_clk_ops = { + .recalc = pll_recalc, +}; + +static struct clk pll0_clk = { + .ops = &pll_clk_ops, + .flags = CLK_ENABLE_ON_INIT, + .parent = &main_clk, + .enable_reg = (void __iomem *)PLL0CR, + .enable_bit = 0, +}; + +static struct clk pll1_clk = { + .ops = &pll_clk_ops, + .flags = CLK_ENABLE_ON_INIT, + .parent = &main_clk, + .enable_reg = (void __iomem *)PLL1CR, + .enable_bit = 1, +}; + +static struct clk pll2_clk = { + .ops = &pll_clk_ops, + .flags = CLK_ENABLE_ON_INIT, + .parent = &main_clk, + .enable_reg = (void __iomem *)PLL2CR, + .enable_bit = 2, +}; + +static struct clk pll3_clk = { + .ops = &pll_clk_ops, + .flags = CLK_ENABLE_ON_INIT, + .parent = &main_clk, + .enable_reg = (void __iomem *)PLL3CR, + .enable_bit = 3, +}; + +/* Divide PLL1 by two */ +static struct clk pll1_div2_clk = { + .ops = &div2_clk_ops, + .parent = &pll1_clk, +}; + +static struct clk *main_clks[] = { + &r_clk, + &sh73a0_extal1_clk, + &sh73a0_extal2_clk, + &extal1_div2_clk, + &extal2_div2_clk, + &main_clk, + &pll0_clk, + &pll1_clk, + &pll2_clk, + &pll3_clk, + &pll1_div2_clk, +}; + +static void div4_kick(struct clk *clk) +{ + unsigned long value; + + /* set KICK bit in FRQCRB to update hardware setting */ + value = __raw_readl(FRQCRB); + value |= (1 << 31); + __raw_writel(value, FRQCRB); +} + +static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, + 24, 0, 36, 48, 7 }; + +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = divisors, + .nr_divisors = ARRAY_SIZE(divisors), +}; + +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, + .kick = div4_kick, +}; + +enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, + DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR }; + +#define DIV4(_reg, _bit, _mask, _flags) \ + SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags) + +static struct clk div4_clks[DIV4_NR] = { + [DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT), + [DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT), + [DIV4_M3] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT), + [DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT), + [DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0), + [DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0), + [DIV4_Z] = DIV4(FRQCRB, 24, 0xbff, 0), + [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xfff, 0), + [DIV4_ZT] = DIV4(FRQCRB, 16, 0xfff, 0), + [DIV4_ZX] = DIV4(FRQCRB, 12, 0xfff, 0), + [DIV4_HP] = DIV4(FRQCRB, 4, 0xfff, 0), +}; + +enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1, + DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, + DIV6_FSIA, DIV6_FSIB, DIV6_SUB, + DIV6_SPUA, DIV6_SPUV, DIV6_MSU, + DIV6_HSI, DIV6_MFG1, DIV6_MFG2, + DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P, + DIV6_NR }; + +static struct clk div6_clks[DIV6_NR] = { + [DIV6_VCK1] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR1, 0), + [DIV6_VCK2] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR2, 0), + [DIV6_VCK3] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR3, 0), + [DIV6_ZB1] = SH_CLK_DIV6(&pll1_div2_clk, ZBCKCR, 0), + [DIV6_FLCTL] = SH_CLK_DIV6(&pll1_div2_clk, FLCKCR, 0), + [DIV6_SDHI0] = SH_CLK_DIV6(&pll1_div2_clk, SD0CKCR, 0), + [DIV6_SDHI1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0), + [DIV6_SDHI2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0), + [DIV6_FSIA] = SH_CLK_DIV6(&pll1_div2_clk, FSIACKCR, 0), + [DIV6_FSIB] = SH_CLK_DIV6(&pll1_div2_clk, FSIBCKCR, 0), + [DIV6_SUB] = SH_CLK_DIV6(&sh73a0_extal2_clk, SUBCKCR, 0), + [DIV6_SPUA] = SH_CLK_DIV6(&pll1_div2_clk, SPUACKCR, 0), + [DIV6_SPUV] = SH_CLK_DIV6(&pll1_div2_clk, SPUVCKCR, 0), + [DIV6_MSU] = SH_CLK_DIV6(&pll1_div2_clk, MSUCKCR, 0), + [DIV6_HSI] = SH_CLK_DIV6(&pll1_div2_clk, HSICKCR, 0), + [DIV6_MFG1] = SH_CLK_DIV6(&pll1_div2_clk, MFCK1CR, 0), + [DIV6_MFG2] = SH_CLK_DIV6(&pll1_div2_clk, MFCK2CR, 0), + [DIV6_DSIT] = SH_CLK_DIV6(&pll1_div2_clk, DSITCKCR, 0), + [DIV6_DSI0P] = SH_CLK_DIV6(&pll1_div2_clk, DSI0PCKCR, 0), + [DIV6_DSI1P] = SH_CLK_DIV6(&pll1_div2_clk, DSI1PCKCR, 0), +}; + +enum { MSTP001, + MSTP125, MSTP116, + MSTP219, + MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, + MSTP331, MSTP329, MSTP323, MSTP312, + MSTP411, MSTP410, MSTP403, + MSTP_NR }; + +#define MSTP(_parent, _reg, _bit, _flags) \ + SH_CLK_MSTP32(_parent, _reg, _bit, _flags) + +static struct clk mstp_clks[MSTP_NR] = { + [MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */ + [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ + [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */ + [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */ + [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */ + [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */ + [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */ + [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */ + [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */ + [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */ + [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */ + [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */ + [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */ + [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */ + [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */ + [MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */ + [MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */ + [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */ +}; + +#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } +#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } + +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("r_clk", &r_clk), + + /* MSTP32 clocks */ + CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */ + CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */ + CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */ + CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */ + CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */ + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */ + CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */ + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */ + CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */ + CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */ + CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */ + CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */ + CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */ + CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */ + CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */ + CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */ + CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */ +}; + +void __init sh73a0_clock_init(void) +{ + int k, ret = 0; + + /* detect main clock parent */ + switch ((__raw_readl(CKSCR) >> 24) & 0x03) { + case 0: + main_clk.parent = &sh73a0_extal1_clk; + break; + case 1: + main_clk.parent = &extal1_div2_clk; + break; + case 2: + main_clk.parent = &sh73a0_extal2_clk; + break; + case 3: + main_clk.parent = &extal2_div2_clk; + break; + } + + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) + ret = clk_register(main_clks[k]); + + if (!ret) + ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); + + if (!ret) + ret = sh_clk_div6_register(div6_clks, DIV6_NR); + + if (!ret) + ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + + if (!ret) + clk_init(); + else + panic("failed to setup sh73a0 clocks\n"); +} diff --git a/arch/arm/mach-shmobile/entry-gic.S b/arch/arm/mach-shmobile/entry-gic.S new file mode 100644 index 00000000000..e20239b08c8 --- /dev/null +++ b/arch/arm/mach-shmobile/entry-gic.S @@ -0,0 +1,18 @@ +/* + * ARM Interrupt demux handler using GIC + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2011 Paul Mundt + * Copyright (C) 2010 - 2011 Renesas Solutions Corp. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <asm/assembler.h> +#include <asm/entry-macro-multi.S> +#include <asm/hardware/gic.h> +#include <asm/hardware/entry-macro-gic.S> + + arch_irq_handler shmobile_handle_irq_gic diff --git a/arch/arm/mach-shmobile/entry-intc.S b/arch/arm/mach-shmobile/entry-intc.S new file mode 100644 index 00000000000..cac0a7ae208 --- /dev/null +++ b/arch/arm/mach-shmobile/entry-intc.S @@ -0,0 +1,57 @@ +/* + * ARM Interrupt demux handler using INTC + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2008 Renesas Solutions Corp. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <asm/entry-macro-multi.S> + +#define INTCA_BASE 0xe6980000 +#define INTFLGA_OFFS 0x00000018 /* accept pending interrupt */ +#define INTEVTA_OFFS 0x00000020 /* vector number of accepted interrupt */ +#define INTLVLA_OFFS 0x00000030 /* priority level of accepted interrupt */ +#define INTLVLB_OFFS 0x00000034 /* previous priority level */ + + .macro get_irqnr_preamble, base, tmp + ldr \base, =INTCA_BASE + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + /* The single INTFLGA read access below results in the following: + * + * 1. INTLVLB is updated with old priority value from INTLVLA + * 2. Highest priority interrupt is accepted + * 3. INTLVLA is updated to contain priority of accepted interrupt + * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA + */ + ldr \irqnr, [\base, #INTFLGA_OFFS] + + /* Restore INTLVLA with the value saved in INTLVLB. + * This is required to support interrupt priorities properly. + */ + ldrb \tmp, [\base, #INTLVLB_OFFS] + strb \tmp, [\base, #INTLVLA_OFFS] + + /* Handle invalid vector number case */ + cmp \irqnr, #0 + beq 1000f + + /* Convert vector to irq number, same as the evt2irq() macro */ + lsr \irqnr, \irqnr, #0x5 + subs \irqnr, \irqnr, #16 + +1000: + .endm + + .macro test_for_ipi, irqnr, irqstat, base, tmp + .endm + + .macro test_for_ltirq, irqnr, irqstat, base, tmp + .endm + + arch_irq_handler shmobile_handle_irq_intc diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S new file mode 100644 index 00000000000..d4cec6b4c7d --- /dev/null +++ b/arch/arm/mach-shmobile/headsmp.S @@ -0,0 +1,27 @@ +/* + * SMP support for R-Mobile / SH-Mobile + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2010 Takashi Yoshii + * + * Based on vexpress, Copyright (c) 2003 ARM Limited, All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <linux/init.h> +#include <asm/memory.h> + + __INIT + +/* + * Reset vector for secondary CPUs. + * This will be mapped at address 0 by SBAR register. + * We need _long_ jump to the physical address. + */ + .align 12 +ENTRY(shmobile_secondary_vector) + ldr pc, 1f +1: .long secondary_startup - PAGE_OFFSET + PHYS_OFFSET diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c new file mode 100644 index 00000000000..238a0d97d2d --- /dev/null +++ b/arch/arm/mach-shmobile/hotplug.c @@ -0,0 +1,41 @@ +/* + * SMP support for R-Mobile / SH-Mobile + * + * Copyright (C) 2010 Magnus Damm + * + * Based on realview, Copyright (C) 2002 ARM Ltd, All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/smp.h> + +int platform_cpu_kill(unsigned int cpu) +{ + return 1; +} + +void platform_cpu_die(unsigned int cpu) +{ + while (1) { + /* + * here's the WFI + */ + asm(".word 0xe320f003\n" + : + : + : "memory", "cc"); + } +} + +int platform_cpu_disable(unsigned int cpu) +{ + /* + * we don't allow CPU 0 to be shutdown (it is still too special + * e.g. clock tick interrupts) + */ + return cpu == 0 ? -EPERM : 0; +} diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index efeef778a87..013ac0ee825 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -3,8 +3,11 @@ extern struct sys_timer shmobile_timer; extern void shmobile_setup_console(void); +extern void shmobile_secondary_vector(void); struct clk; extern int clk_init(void); +extern void shmobile_handle_irq_intc(struct pt_regs *); +extern void shmobile_handle_irq_gic(struct pt_regs *); extern void sh7367_init_irq(void); extern void sh7367_add_early_devices(void); @@ -30,4 +33,17 @@ extern void sh7372_pinmux_init(void); extern struct clk sh7372_extal1_clk; extern struct clk sh7372_extal2_clk; +extern void sh73a0_init_irq(void); +extern void sh73a0_add_early_devices(void); +extern void sh73a0_add_standard_devices(void); +extern void sh73a0_clock_init(void); +extern void sh73a0_pinmux_init(void); +extern struct clk sh73a0_extal1_clk; +extern struct clk sh73a0_extal2_clk; + +extern unsigned int sh73a0_get_core_count(void); +extern void sh73a0_secondary_init(unsigned int cpu); +extern int sh73a0_boot_secondary(unsigned int cpu); +extern void sh73a0_smp_prepare_cpus(void); + #endif /* __ARCH_MACH_COMMON_H */ diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S index f428c4db2b6..d791f10eeac 100644 --- a/arch/arm/mach-shmobile/include/mach/entry-macro.S +++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S @@ -1,6 +1,5 @@ /* - * Copyright (C) 2010 Magnus Damm - * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2010 Paul Mundt * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,47 +14,21 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <mach/irqs.h> - -#define INTCA_BASE 0xe6980000 -#define INTFLGA_OFFS 0x00000018 /* accept pending interrupt */ -#define INTEVTA_OFFS 0x00000020 /* vector number of accepted interrupt */ -#define INTLVLA_OFFS 0x00000030 /* priority level of accepted interrupt */ -#define INTLVLB_OFFS 0x00000034 /* previous priority level */ .macro disable_fiq .endm .macro get_irqnr_preamble, base, tmp - ldr \base, =INTCA_BASE - .endm - - .macro arch_ret_to_user, tmp1, tmp2 .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - /* The single INTFLGA read access below results in the following: - * - * 1. INTLVLB is updated with old priority value from INTLVLA - * 2. Highest priority interrupt is accepted - * 3. INTLVLA is updated to contain priority of accepted interrupt - * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA - */ - ldr \irqnr, [\base, #INTFLGA_OFFS] - - /* Restore INTLVLA with the value saved in INTLVLB. - * This is required to support interrupt priorities properly. - */ - ldrb \tmp, [\base, #INTLVLB_OFFS] - strb \tmp, [\base, #INTLVLA_OFFS] + .endm - /* Handle invalid vector number case */ - cmp \irqnr, #0 - beq 1000f + .macro test_for_ipi, irqnr, irqstat, base, tmp + .endm - /* Convert vector to irq number, same as the evt2irq() macro */ - lsr \irqnr, \irqnr, #0x5 - subs \irqnr, \irqnr, #16 + .macro test_for_ltirq, irqnr, irqstat, base, tmp + .endm -1000: + .macro arch_ret_to_user, tmp1, tmp2 .endm diff --git a/arch/arm/mach-shmobile/include/mach/hardware.h b/arch/arm/mach-shmobile/include/mach/hardware.h index 3f0ef194603..99264a5ce5e 100644 --- a/arch/arm/mach-shmobile/include/mach/hardware.h +++ b/arch/arm/mach-shmobile/include/mach/hardware.h @@ -1,7 +1,4 @@ #ifndef __ASM_MACH_HARDWARE_H #define __ASM_MACH_HARDWARE_H -/* INTFLGA register - used by low level interrupt code in entry-macro.S */ -#define INTFLGA 0xe6980018 - #endif /* __ASM_MACH_HARDWARE_H */ diff --git a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt new file mode 100644 index 00000000000..e3ebfa73956 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt @@ -0,0 +1,87 @@ +LIST "partner-jet-setup.txt" +LIST "(C) Copyright 2010 Renesas Solutions Corp" +LIST "Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>" + +LIST "RWT Setting" +EW 0xE6020004, 0xA500 +EW 0xE6030004, 0xA500 + +DD 0x01001000, 0x01001000 + +LIST "GPIO Setting" +EB 0xE6051013, 0xA2 + +LIST "CPG" +ED 0xE6150080, 0x00000180 +ED 0xE61500C0, 0x00000002 + +WAIT 1, 0xFE40009C + +LIST "FRQCR" +ED 0xE6150000, 0x2D1305C3 +ED 0xE61500E0, 0x9E40358E +ED 0xE6150004, 0x80331050 + +WAIT 1, 0xFE40009C + +ED 0xE61500E4, 0x00002000 + +WAIT 1, 0xFE40009C + +LIST "PLL" +ED 0xE6150028, 0x00004000 + +WAIT 1, 0xFE40009C + +ED 0xE615002C, 0x93000040 + +WAIT 1, 0xFE40009C + +LIST "BSC" +ED 0xFEC10000, 0x00E0001B + +LIST "SBSC1" +ED 0xFE400354, 0x01AD8000 +ED 0xFE400354, 0x01AD8001 + +WAIT 5, 0xFE40009C + +ED 0xFE400008, 0xBCC90151 +ED 0xFE400040, 0x41774113 +ED 0xFE400044, 0x2712E229 +ED 0xFE400048, 0x20C18505 +ED 0xFE40004C, 0x00110209 +ED 0xFE400010, 0x00000087 + +WAIT 10, 0xFE40009C + +ED 0xFE400084, 0x0000003F +EB 0xFE500000, 0x00 + +WAIT 5, 0xFE40009C + +ED 0xFE400084, 0x0000FF0A +EB 0xFE500000, 0x00 + +WAIT 1, 0xFE40009C + +ED 0xFE400084, 0x00002201 +EB 0xFE500000, 0x00 +ED 0xFE400084, 0x00000302 +EB 0xFE500000, 0x00 +EB 0xFE5C0000, 0x00 +ED 0xFE400008, 0xBCC90159 +ED 0xFE40008C, 0x88800004 +ED 0xFE400094, 0x00000004 +ED 0xFE400028, 0xA55A0032 +ED 0xFE40002C, 0xA55A000C +ED 0xFE400020, 0xA55A2048 +ED 0xFE400008, 0xBCC90959 + +LIST "Change CPGA setting" +ED 0xE61500E0, 0x9E40352E +ED 0xE6150004, 0x80331050 + +WAIT 1, 0xFE40009C + +ED 0xE6150354, 0x00000002 diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h index fa15b5f8a00..dcb714f4d75 100644 --- a/arch/arm/mach-shmobile/include/mach/irqs.h +++ b/arch/arm/mach-shmobile/include/mach/irqs.h @@ -1,7 +1,10 @@ #ifndef __ASM_MACH_IRQS_H #define __ASM_MACH_IRQS_H -#define NR_IRQS 512 +#define NR_IRQS 1024 + +/* GIC */ +#define gic_spi(nr) ((nr) + 32) /* INTCA */ #define evt2irq(evt) (((evt) >> 5) - 16) diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h index e4f9004e710..5736efcca60 100644 --- a/arch/arm/mach-shmobile/include/mach/sh7372.h +++ b/arch/arm/mach-shmobile/include/mach/sh7372.h @@ -455,6 +455,8 @@ enum { SHDMA_SLAVE_SDHI1_TX, SHDMA_SLAVE_SDHI2_RX, SHDMA_SLAVE_SDHI2_TX, + SHDMA_SLAVE_MMCIF_RX, + SHDMA_SLAVE_MMCIF_TX, }; extern struct clk sh7372_extal1_clk; diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h new file mode 100644 index 00000000000..ceb2cdc92bf --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h @@ -0,0 +1,467 @@ +#ifndef __ASM_SH73A0_H__ +#define __ASM_SH73A0_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function and MSEL switch + * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU + */ +enum { + /* Hardware manual Table 25-1 (GPIO) */ + GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, + GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, + + GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, + GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, + + GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, + GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, + + GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, + GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, + + GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, + GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, + + GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, + GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, + + GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, + GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, + + GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, + GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, + + GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, + GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, + + GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, + GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, + + GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, + GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, + + GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, + GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, + + GPIO_PORT128, GPIO_PORT129, + + GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, + GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, + + GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, + GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, + + GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, + GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, + + GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, + + GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, + GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, + + GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, + GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, + + GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214, + GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219, + + GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224, + GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229, + + GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234, + GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239, + + GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244, + GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249, + + GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254, + GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259, + + GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264, + GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269, + + GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274, + GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279, + + GPIO_PORT280, GPIO_PORT281, GPIO_PORT282, + + GPIO_PORT288, GPIO_PORT289, + + GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294, + GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299, + + GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304, + GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309, + + /* Table 25-1 (Function 0-7) */ + GPIO_FN_VBUS_0, + GPIO_FN_GPI0, + GPIO_FN_GPI1, + GPIO_FN_GPI2, + GPIO_FN_GPI3, + GPIO_FN_GPI4, + GPIO_FN_GPI5, + GPIO_FN_GPI6, + GPIO_FN_GPI7, + GPIO_FN_SCIFA7_RXD, + GPIO_FN_SCIFA7_CTS_, + GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2, + GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2, + GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \ + GPIO_FN_PORT16_VIO_CKOR, + GPIO_FN_SCIFA0_TXD, + GPIO_FN_SCIFA7_TXD, + GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2, + GPIO_FN_GPO0, + GPIO_FN_GPO1, + GPIO_FN_GPO2, GPIO_FN_STATUS0, + GPIO_FN_GPO3, GPIO_FN_STATUS1, + GPIO_FN_GPO4, GPIO_FN_STATUS2, + GPIO_FN_VINT, + GPIO_FN_TCKON, + GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \ + GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT, + GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \ + GPIO_FN_PORT28_TPU1TO1, + GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1, + GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR, + GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT, + GPIO_FN_SCIFA4_TXD, + GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP, + GPIO_FN_SCIFA4_RTS_, + GPIO_FN_SCIFA4_CTS_, + GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT, + GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR, + GPIO_FN_FSIBOSLD, + GPIO_FN_FSIBISLD, + GPIO_FN_VACK, + GPIO_FN_XTAL1L, + GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2, + GPIO_FN_SCIFA0_RXD, + GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1, + GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT, + GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR, + GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF, + GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD, + GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \ + GPIO_FN_FSIAOMC, + GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR, + + GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT, + GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2, + GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \ + GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF, + GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \ + GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC, + GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0, + GPIO_FN_A0, GPIO_FN_BS_, + GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2, + GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1, + GPIO_FN_A14, GPIO_FN_KEYOUT5, + GPIO_FN_A15, GPIO_FN_KEYOUT4, + GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1, + GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC, + GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK, + GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD, + GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK, + GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC, + GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0, + GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1, + GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD, + GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2, + GPIO_FN_A26, GPIO_FN_KEYIN6, + GPIO_FN_KEYIN7, + GPIO_FN_D0_NAF0, + GPIO_FN_D1_NAF1, + GPIO_FN_D2_NAF2, + GPIO_FN_D3_NAF3, + GPIO_FN_D4_NAF4, + GPIO_FN_D5_NAF5, + GPIO_FN_D6_NAF6, + GPIO_FN_D7_NAF7, + GPIO_FN_D8_NAF8, + GPIO_FN_D9_NAF9, + GPIO_FN_D10_NAF10, + GPIO_FN_D11_NAF11, + GPIO_FN_D12_NAF12, + GPIO_FN_D13_NAF13, + GPIO_FN_D14_NAF14, + GPIO_FN_D15_NAF15, + GPIO_FN_CS4_, + GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR, + GPIO_FN_CS5B_, GPIO_FN_FCE1_, + GPIO_FN_CS6B_, GPIO_FN_DACK0, + GPIO_FN_FCE0_, GPIO_FN_CS6A_, + GPIO_FN_WAIT_, GPIO_FN_DREQ0, + GPIO_FN_RD__FSC, + GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE, + GPIO_FN_WE1_, + GPIO_FN_FRB, + GPIO_FN_CKO, + GPIO_FN_NBRSTOUT_, + GPIO_FN_NBRST_, + GPIO_FN_BBIF2_TXD, + GPIO_FN_BBIF2_RXD, + GPIO_FN_BBIF2_SYNC, + GPIO_FN_BBIF2_SCK, + GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2, + GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1, + GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1, + GPIO_FN_SCIFA3_TXD, + GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD, + GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK, + GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC, + GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD, + GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \ + GPIO_FN_PORT115_I2C_SCL3, + GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \ + GPIO_FN_PORT116_I2C_SDA3, + GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW, + GPIO_FN_HSI_TX_FLAG, + GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \ + GPIO_FN_LCD2D0, + + GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \ + GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1, + GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10, + GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \ + GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11, + GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \ + GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12, + GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13, + GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14, + GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15, + GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16, + GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17, + GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \ + GPIO_FN_LCD2D6, + GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \ + GPIO_FN_LCD2D7, + GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8, + GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9, + GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \ + GPIO_FN_LCD2D2, + GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \ + GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3, + GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \ + GPIO_FN_LCD2D4, + GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \ + GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5, + GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \ + GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18, + GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19, + GPIO_FN_VIO_CKO, + GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \ + GPIO_FN_PORT149_KEYOUT9, + GPIO_FN_MFG0_IN2, + GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK, + GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC, + GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1, + GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0, + GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1, + GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2, + GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD, + GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3, + GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI, + GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD, + GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_, + GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, + GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \ + GPIO_FN_TPU3TO0, + GPIO_FN_LCDD0, + GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1, + GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1, + GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1, + GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD, + GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \ + GPIO_FN_TPU2TO1, + GPIO_FN_LCDD6, + GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, + GPIO_FN_LCDD8, GPIO_FN_D16, + GPIO_FN_LCDD9, GPIO_FN_D17, + GPIO_FN_LCDD10, GPIO_FN_D18, + GPIO_FN_LCDD11, GPIO_FN_D19, + GPIO_FN_LCDD12, GPIO_FN_D20, + GPIO_FN_LCDD13, GPIO_FN_D21, + GPIO_FN_LCDD14, GPIO_FN_D22, + GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23, + GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24, + GPIO_FN_LCDD17, GPIO_FN_D25, + GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26, + GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, + GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28, + GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29, + GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30, + GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31, + GPIO_FN_LCDDCK, GPIO_FN_LCDWR_, + GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \ + GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP, + GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \ + GPIO_FN_PORT218_VIO_CKOR, + GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \ + GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \ + GPIO_FN_LCD2DCK_2, + GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2, + GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \ + GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \ + GPIO_FN_PORT221_LCD2HSYN, + GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \ + GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN, + + GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2, + GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2, + GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN, + GPIO_FN_SCIFA1_RXD, + GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1, + GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, + GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_, + GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, + GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, + GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \ + GPIO_FN_LCD2D20, + GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \ + GPIO_FN_LCD2D21, + GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2, + GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2, + GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22, + GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23, + GPIO_FN_SCIFA6_TXD, + GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \ + GPIO_FN_TPU4TO0, + GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2, + GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2, + GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \ + GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD, + GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \ + GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD, + GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \ + GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0, + GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \ + GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1, + GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \ + GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \ + GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK, + GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \ + GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC, + GPIO_FN_SDHICLK0, + GPIO_FN_SDHICD0, + GPIO_FN_SDHID0_0, + GPIO_FN_SDHID0_1, + GPIO_FN_SDHID0_2, + GPIO_FN_SDHID0_3, + GPIO_FN_SDHICMD0, + GPIO_FN_SDHIWP0, + GPIO_FN_SDHICLK1, + GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2, + GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2, + GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2, + GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2, + GPIO_FN_SDHICMD1, + GPIO_FN_SDHICLK2, + GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4, + GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4, + GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4, + GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4, + GPIO_FN_SDHICMD2, + GPIO_FN_MMCCLK0, + GPIO_FN_MMCD0_0, + GPIO_FN_MMCD0_1, + GPIO_FN_MMCD0_2, + GPIO_FN_MMCD0_3, + GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5, + GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5, + GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5, + GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5, + GPIO_FN_MMCCMD0, + GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT, + GPIO_FN_MCP_WAIT__MCP_FRB, + GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1, + GPIO_FN_MCP_D15_MCP_NAF15, + GPIO_FN_MCP_D14_MCP_NAF14, + GPIO_FN_MCP_D13_MCP_NAF13, + GPIO_FN_MCP_D12_MCP_NAF12, + GPIO_FN_MCP_D11_MCP_NAF11, + GPIO_FN_MCP_D10_MCP_NAF10, + GPIO_FN_MCP_D9_MCP_NAF9, + GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1, + GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7, + + GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6, + GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5, + GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4, + GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3, + GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2, + GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1, + GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0, + GPIO_FN_MCP_NBRSTOUT_, + GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE, + + /* MSEL2 special case */ + GPIO_FN_TSIF2_TS_XX1, + GPIO_FN_TSIF2_TS_XX2, + GPIO_FN_TSIF2_TS_XX3, + GPIO_FN_TSIF2_TS_XX4, + GPIO_FN_TSIF2_TS_XX5, + GPIO_FN_TSIF1_TS_XX1, + GPIO_FN_TSIF1_TS_XX2, + GPIO_FN_TSIF1_TS_XX3, + GPIO_FN_TSIF1_TS_XX4, + GPIO_FN_TSIF1_TS_XX5, + GPIO_FN_TSIF0_TS_XX1, + GPIO_FN_TSIF0_TS_XX2, + GPIO_FN_TSIF0_TS_XX3, + GPIO_FN_TSIF0_TS_XX4, + GPIO_FN_TSIF0_TS_XX5, + GPIO_FN_MST1_TS_XX1, + GPIO_FN_MST1_TS_XX2, + GPIO_FN_MST1_TS_XX3, + GPIO_FN_MST1_TS_XX4, + GPIO_FN_MST1_TS_XX5, + GPIO_FN_MST0_TS_XX1, + GPIO_FN_MST0_TS_XX2, + GPIO_FN_MST0_TS_XX3, + GPIO_FN_MST0_TS_XX4, + GPIO_FN_MST0_TS_XX5, + + /* MSEL3 special cases */ + GPIO_FN_SDHI0_VCCQ_MC0_ON, + GPIO_FN_SDHI0_VCCQ_MC0_OFF, + GPIO_FN_DEBUG_MON_VIO, + GPIO_FN_DEBUG_MON_LCDD, + GPIO_FN_LCDC_LCDC0, + GPIO_FN_LCDC_LCDC1, + + /* MSEL4 special cases */ + GPIO_FN_IRQ9_MEM_INT, + GPIO_FN_IRQ9_MCP_INT, + GPIO_FN_A11, + GPIO_FN_KEYOUT8, + GPIO_FN_TPU4TO3, + GPIO_FN_RESETA_N_PU_ON, + GPIO_FN_RESETA_N_PU_OFF, + GPIO_FN_EDBGREQ_PD, + GPIO_FN_EDBGREQ_PU, + + /* Functions with pull-ups */ + GPIO_FN_KEYIN0_PU, + GPIO_FN_KEYIN1_PU, + GPIO_FN_KEYIN2_PU, + GPIO_FN_KEYIN3_PU, + GPIO_FN_KEYIN4_PU, + GPIO_FN_KEYIN5_PU, + GPIO_FN_KEYIN6_PU, + GPIO_FN_KEYIN7_PU, + GPIO_FN_SDHID1_0_PU, + GPIO_FN_SDHID1_1_PU, + GPIO_FN_SDHID1_2_PU, + GPIO_FN_SDHID1_3_PU, + GPIO_FN_SDHICMD1_PU, + GPIO_FN_MMCCMD0_PU, + GPIO_FN_MMCCMD1_PU, + GPIO_FN_FSIACK_PU, + GPIO_FN_FSIAILR_PU, + GPIO_FN_FSIAIBT_PU, + GPIO_FN_FSIAISLD_PU, +}; + +#endif /* __ASM_SH73A0_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/smp.h b/arch/arm/mach-shmobile/include/mach/smp.h new file mode 100644 index 00000000000..50db94e927a --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/smp.h @@ -0,0 +1,16 @@ +#ifndef __MACH_SMP_H +#define __MACH_SMP_H + +#include <asm/hardware/gic.h> + +/* + * We use IRQ1 as the IPI + */ +static inline void smp_cross_call(const struct cpumask *mask, int ipi) +{ +#if defined(CONFIG_ARM_GIC) + gic_raise_softirq(mask, ipi); +#endif +} + +#endif diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h index 3ad86b7708e..6d6a205bcf9 100644 --- a/arch/arm/mach-shmobile/include/mach/zboot.h +++ b/arch/arm/mach-shmobile/include/mach/zboot.h @@ -13,6 +13,9 @@ #ifdef CONFIG_MACH_AP4EVB #define MACH_TYPE MACH_TYPE_AP4EVB #include "mach/head-ap4evb.txt" +#elif CONFIG_MACH_MACKEREL +#define MACH_TYPE MACH_TYPE_MACKEREL +#include "mach/head-mackerel.txt" #else #error "unsupported board." #endif diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c new file mode 100644 index 00000000000..322d8d57cbc --- /dev/null +++ b/arch/arm/mach-shmobile/intc-sh73a0.c @@ -0,0 +1,267 @@ +/* + * sh73a0 processor support - INTC hardware block + * + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/sh_intc.h> +#include <asm/hardware/gic.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +enum { + UNUSED = 0, + + /* interrupt sources INTCS */ + PINTCS_PINT1, PINTCS_PINT2, + RTDMAC_0_DEI0, RTDMAC_0_DEI1, RTDMAC_0_DEI2, RTDMAC_0_DEI3, + CEU, MFI, BBIF2, VPU, TSIF1, _3DG_SGX543, _2DDMAC_2DDM0, + RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR, + KEYSC_KEY, VINT, MSIOF, + TMU0_TUNI00, TMU0_TUNI01, TMU0_TUNI02, + CMT0, TSIF0, CMT2, LMB, MSUG, MSU_MSU, MSU_MSU2, + CTI, RWDT0, ICB, PEP, ASA, JPU_JPEG, LCDC, LCRC, + RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9, + RTDMAC_3_DEI10, RTDMAC_3_DEI11, + FRC, GCU, LCDC1, CSIRX, + DSITX0_DSITX00, DSITX0_DSITX01, + SPU2_SPU0, SPU2_SPU1, FSI, + TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, + TSIF2, CMT4, MFIS2, CPORTS2R, TSG, DMASCH1, SCUW, + VIO60, VIO61, CEU21, CSI21, DSITX1_DSITX10, DSITX1_DSITX11, + DISP, DSRV, EMUX2_EMUX20I, EMUX2_EMUX21I, + MSTIF0_MST00I, MSTIF0_MST01I, MSTIF1_MST10I, MSTIF1_MST11I, + SPUV, + + /* interrupt groups INTCS */ + RTDMAC_0, RTDMAC_1, RTDMAC_2, RTDMAC_3, + DSITX0, SPU2, TMU1, MSU, +}; + +static struct intc_vect intcs_vectors[] = { + INTCS_VECT(PINTCS_PINT1, 0x0600), INTCS_VECT(PINTCS_PINT2, 0x0620), + INTCS_VECT(RTDMAC_0_DEI0, 0x0800), INTCS_VECT(RTDMAC_0_DEI1, 0x0820), + INTCS_VECT(RTDMAC_0_DEI2, 0x0840), INTCS_VECT(RTDMAC_0_DEI3, 0x0860), + INTCS_VECT(CEU, 0x0880), INTCS_VECT(MFI, 0x0900), + INTCS_VECT(BBIF2, 0x0960), INTCS_VECT(VPU, 0x0980), + INTCS_VECT(TSIF1, 0x09a0), INTCS_VECT(_3DG_SGX543, 0x09e0), + INTCS_VECT(_2DDMAC_2DDM0, 0x0a00), + INTCS_VECT(RTDMAC_1_DEI4, 0x0b80), INTCS_VECT(RTDMAC_1_DEI5, 0x0ba0), + INTCS_VECT(RTDMAC_1_DADERR, 0x0bc0), + INTCS_VECT(KEYSC_KEY, 0x0be0), INTCS_VECT(VINT, 0x0c80), + INTCS_VECT(MSIOF, 0x0d20), + INTCS_VECT(TMU0_TUNI00, 0x0e80), INTCS_VECT(TMU0_TUNI01, 0x0ea0), + INTCS_VECT(TMU0_TUNI02, 0x0ec0), + INTCS_VECT(CMT0, 0x0f00), INTCS_VECT(TSIF0, 0x0f20), + INTCS_VECT(CMT2, 0x0f40), INTCS_VECT(LMB, 0x0f60), + INTCS_VECT(MSUG, 0x0f80), + INTCS_VECT(MSU_MSU, 0x0fa0), INTCS_VECT(MSU_MSU2, 0x0fc0), + INTCS_VECT(CTI, 0x0400), INTCS_VECT(RWDT0, 0x0440), + INTCS_VECT(ICB, 0x0480), INTCS_VECT(PEP, 0x04a0), + INTCS_VECT(ASA, 0x04c0), INTCS_VECT(JPU_JPEG, 0x0560), + INTCS_VECT(LCDC, 0x0580), INTCS_VECT(LCRC, 0x05a0), + INTCS_VECT(RTDMAC_2_DEI6, 0x1300), INTCS_VECT(RTDMAC_2_DEI7, 0x1320), + INTCS_VECT(RTDMAC_2_DEI8, 0x1340), INTCS_VECT(RTDMAC_2_DEI9, 0x1360), + INTCS_VECT(RTDMAC_3_DEI10, 0x1380), INTCS_VECT(RTDMAC_3_DEI11, 0x13a0), + INTCS_VECT(FRC, 0x1700), INTCS_VECT(GCU, 0x1760), + INTCS_VECT(LCDC1, 0x1780), INTCS_VECT(CSIRX, 0x17a0), + INTCS_VECT(DSITX0_DSITX00, 0x17c0), INTCS_VECT(DSITX0_DSITX01, 0x17e0), + INTCS_VECT(SPU2_SPU0, 0x1800), INTCS_VECT(SPU2_SPU1, 0x1820), + INTCS_VECT(FSI, 0x1840), + INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920), + INTCS_VECT(TMU1_TUNI12, 0x1940), + INTCS_VECT(TSIF2, 0x1960), INTCS_VECT(CMT4, 0x1980), + INTCS_VECT(MFIS2, 0x1a00), INTCS_VECT(CPORTS2R, 0x1a20), + INTCS_VECT(TSG, 0x1ae0), INTCS_VECT(DMASCH1, 0x1b00), + INTCS_VECT(SCUW, 0x1b40), + INTCS_VECT(VIO60, 0x1b60), INTCS_VECT(VIO61, 0x1b80), + INTCS_VECT(CEU21, 0x1ba0), INTCS_VECT(CSI21, 0x1be0), + INTCS_VECT(DSITX1_DSITX10, 0x1c00), INTCS_VECT(DSITX1_DSITX11, 0x1c20), + INTCS_VECT(DISP, 0x1c40), INTCS_VECT(DSRV, 0x1c60), + INTCS_VECT(EMUX2_EMUX20I, 0x1c80), INTCS_VECT(EMUX2_EMUX21I, 0x1ca0), + INTCS_VECT(MSTIF0_MST00I, 0x1cc0), INTCS_VECT(MSTIF0_MST01I, 0x1ce0), + INTCS_VECT(MSTIF1_MST10I, 0x1d00), INTCS_VECT(MSTIF1_MST11I, 0x1d20), + INTCS_VECT(SPUV, 0x2300), +}; + +static struct intc_group intcs_groups[] __initdata = { + INTC_GROUP(RTDMAC_0, RTDMAC_0_DEI0, RTDMAC_0_DEI1, + RTDMAC_0_DEI2, RTDMAC_0_DEI3), + INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR), + INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI6, RTDMAC_2_DEI7, + RTDMAC_2_DEI8, RTDMAC_2_DEI9), + INTC_GROUP(RTDMAC_3, RTDMAC_3_DEI10, RTDMAC_3_DEI11), + INTC_GROUP(TMU1, TMU1_TUNI12, TMU1_TUNI11, TMU1_TUNI10), + INTC_GROUP(DSITX0, DSITX0_DSITX00, DSITX0_DSITX01), + INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1), + INTC_GROUP(MSU, MSU_MSU, MSU_MSU2), +}; + +static struct intc_mask_reg intcs_mask_registers[] = { + { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */ + { 0, 0, 0, CEU, + 0, 0, 0, 0 } }, + { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */ + { 0, 0, 0, VPU, + BBIF2, 0, 0, MFI } }, + { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */ + { 0, 0, 0, _2DDMAC_2DDM0, + 0, ASA, PEP, ICB } }, + { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */ + { 0, 0, 0, CTI, + JPU_JPEG, 0, LCRC, LCDC } }, + { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */ + { KEYSC_KEY, RTDMAC_1_DADERR, RTDMAC_1_DEI5, RTDMAC_1_DEI4, + RTDMAC_0_DEI3, RTDMAC_0_DEI2, RTDMAC_0_DEI1, RTDMAC_0_DEI0 } }, + { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */ + { 0, 0, MSIOF, 0, + _3DG_SGX543, 0, 0, 0 } }, + { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */ + { 0, TMU0_TUNI02, TMU0_TUNI01, TMU0_TUNI00, + 0, 0, 0, 0 } }, + { 0xffd201a0, 0xffd201e0, 8, /* IMR8SA / IMCR8SA */ + { 0, 0, 0, 0, + 0, MSU_MSU, MSU_MSU2, MSUG } }, + { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */ + { 0, RWDT0, CMT2, CMT0, + 0, 0, 0, 0 } }, + { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */ + { 0, 0, 0, 0, + 0, TSIF1, LMB, TSIF0 } }, + { 0xffd201b0, 0xffd201f0, 8, /* IMR12SA / IMCR12SA */ + { 0, 0, 0, 0, + 0, 0, PINTCS_PINT2, PINTCS_PINT1 } }, + { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */ + { RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9, + RTDMAC_3_DEI10, RTDMAC_3_DEI11, 0, 0 } }, + { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */ + { FRC, 0, 0, GCU, + LCDC1, CSIRX, DSITX0_DSITX00, DSITX0_DSITX01 } }, + { 0xffd50194, 0xffd501d4, 8, /* IMR5SA3 / IMCR5SA3 */ + { SPU2_SPU0, SPU2_SPU1, FSI, 0, + 0, 0, 0, 0 } }, + { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */ + { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, 0, + TSIF2, CMT4, 0, 0 } }, + { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */ + { MFIS2, CPORTS2R, 0, 0, + 0, 0, 0, TSG } }, + { 0xffd501a0, 0xffd501e0, 8, /* IMR8SA3 / IMCR8SA3 */ + { DMASCH1, 0, SCUW, VIO60, + VIO61, CEU21, 0, CSI21 } }, + { 0xffd501a4, 0xffd501e4, 8, /* IMR9SA3 / IMCR9SA3 */ + { DSITX1_DSITX10, DSITX1_DSITX11, DISP, DSRV, + EMUX2_EMUX20I, EMUX2_EMUX21I, MSTIF0_MST00I, MSTIF0_MST01I } }, + { 0xffd501a8, 0xffd501e8, 8, /* IMR10SA3 / IMCR10SA3 */ + { MSTIF0_MST00I, MSTIF0_MST01I, 0, 0, + 0, 0, 0, 0 } }, + { 0xffd60180, 0xffd601c0, 8, /* IMR0SA4 / IMCR0SA4 */ + { SPUV, 0, 0, 0, + 0, 0, 0, 0 } }, +}; + +/* Priority is needed for INTCA to receive the INTCS interrupt */ +static struct intc_prio_reg intcs_prio_registers[] = { + { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC_2DDM0, ICB } }, + { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } }, + { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } }, + { 0xffd2000c, 0, 16, 4, /* IPRDS */ { PINTCS_PINT1, PINTCS_PINT2, + 0, 0 } }, + { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_0, CEU, MFI, VPU } }, + { 0xffd20014, 0, 16, 4, /* IPRFS */ { KEYSC_KEY, RTDMAC_1, + CMT2, CMT0 } }, + { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_TUNI00, TMU0_TUNI01, + TMU0_TUNI02, TSIF1 } }, + { 0xffd2001c, 0, 16, 4, /* IPRHS */ { VINT, 0, 0, 0 } }, + { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, 0 } }, + { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX543, MSUG, MSU } }, + { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, ASA, LMB, PEP } }, + { 0xffd20030, 0, 16, 4, /* IPRMS */ { 0, 0, 0, RWDT0 } }, + { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC_2, 0, 0, 0 } }, + { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC_3, 0, 0, 0 } }, + { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { FRC, 0, 0, 0 } }, + { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX0, 0 } }, + { 0xffd50028, 0, 16, 4, /* IPRKS3 */ { SPU2, 0, FSI, 0 } }, + { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, TSIF2 } }, + { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, 0, 0, 0 } }, + { 0xffd50038, 0, 16, 4, /* IPROS3 */ { MFIS2, CPORTS2R, 0, 0 } }, + { 0xffd50040, 0, 16, 4, /* IPRQS3 */ { DMASCH1, 0, SCUW, VIO60 } }, + { 0xffd50044, 0, 16, 4, /* IPRRS3 */ { VIO61, CEU21, 0, CSI21 } }, + { 0xffd50048, 0, 16, 4, /* IPRSS3 */ { DSITX1_DSITX10, DSITX1_DSITX11, + DISP, DSRV } }, + { 0xffd5004c, 0, 16, 4, /* IPRTS3 */ { EMUX2_EMUX20I, EMUX2_EMUX21I, + MSTIF0_MST00I, MSTIF0_MST01I } }, + { 0xffd50050, 0, 16, 4, /* IPRUS3 */ { MSTIF1_MST10I, MSTIF1_MST11I, + 0, 0 } }, + { 0xffd60000, 0, 16, 4, /* IPRAS4 */ { SPUV, 0, 0, 0 } }, +}; + +static struct resource intcs_resources[] __initdata = { + [0] = { + .start = 0xffd20000, + .end = 0xffd201ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 0xffd50000, + .end = 0xffd501ff, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = 0xffd60000, + .end = 0xffd601ff, + .flags = IORESOURCE_MEM, + } +}; + +static struct intc_desc intcs_desc __initdata = { + .name = "sh73a0-intcs", + .resource = intcs_resources, + .num_resources = ARRAY_SIZE(intcs_resources), + .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, + intcs_prio_registers, NULL, NULL), +}; + +static struct irqaction sh73a0_intcs_cascade; + +static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id) +{ + unsigned int evtcodeas = ioread32((void __iomem *)dev_id); + + generic_handle_irq(intcs_evt2irq(evtcodeas)); + + return IRQ_HANDLED; +} + +void __init sh73a0_init_irq(void) +{ + void __iomem *gic_base = __io(0xf0001000); + void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); + + gic_init(0, 29, gic_base, gic_base); + + register_intc_controller(&intcs_desc); + + /* demux using INTEVTSA */ + sh73a0_intcs_cascade.name = "INTCS cascade"; + sh73a0_intcs_cascade.handler = sh73a0_intcs_demux; + sh73a0_intcs_cascade.dev_id = intevtsa; + setup_irq(gic_spi(50), &sh73a0_intcs_cascade); +} diff --git a/arch/arm/mach-shmobile/localtimer.c b/arch/arm/mach-shmobile/localtimer.c new file mode 100644 index 00000000000..2111c28b724 --- /dev/null +++ b/arch/arm/mach-shmobile/localtimer.c @@ -0,0 +1,25 @@ +/* + * SMP support for R-Mobile / SH-Mobile - local timer portion + * + * Copyright (C) 2010 Magnus Damm + * + * Based on vexpress, Copyright (C) 2002 ARM Ltd, All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/smp.h> +#include <linux/clockchips.h> +#include <asm/smp_twd.h> +#include <asm/localtimer.h> + +/* + * Setup the local clock events for a CPU. + */ +void __cpuinit local_timer_setup(struct clock_event_device *evt) +{ + evt->irq = 29; + twd_timer_setup(evt); +} diff --git a/arch/arm/mach-shmobile/pfc-sh73a0.c b/arch/arm/mach-shmobile/pfc-sh73a0.c new file mode 100644 index 00000000000..3eed44eb98b --- /dev/null +++ b/arch/arm/mach-shmobile/pfc-sh73a0.c @@ -0,0 +1,2746 @@ +/* + * sh73a0 processor support - PFC hardware block + * + * Copyright (C) 2010 Renesas Solutions Corp. + * Copyright (C) 2010 NISHIMOTO Hiroki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <mach/sh73a0.h> + +#define _1(fn, pfx, sfx) fn(pfx, sfx) + +#define _10(fn, pfx, sfx) \ + _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \ + _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \ + _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \ + _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \ + _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx) + +#define _310(fn, pfx, sfx) \ + _10(fn, pfx, sfx), _10(fn, pfx##1, sfx), \ + _10(fn, pfx##2, sfx), _10(fn, pfx##3, sfx), \ + _10(fn, pfx##4, sfx), _10(fn, pfx##5, sfx), \ + _10(fn, pfx##6, sfx), _10(fn, pfx##7, sfx), \ + _10(fn, pfx##8, sfx), _10(fn, pfx##9, sfx), \ + _10(fn, pfx##10, sfx), \ + _1(fn, pfx##110, sfx), _1(fn, pfx##111, sfx), \ + _1(fn, pfx##112, sfx), _1(fn, pfx##113, sfx), \ + _1(fn, pfx##114, sfx), _1(fn, pfx##115, sfx), \ + _1(fn, pfx##116, sfx), _1(fn, pfx##117, sfx), \ + _1(fn, pfx##118, sfx), \ + _1(fn, pfx##128, sfx), _1(fn, pfx##129, sfx), \ + _10(fn, pfx##13, sfx), _10(fn, pfx##14, sfx), \ + _10(fn, pfx##15, sfx), \ + _1(fn, pfx##160, sfx), _1(fn, pfx##161, sfx), \ + _1(fn, pfx##162, sfx), _1(fn, pfx##163, sfx), \ + _1(fn, pfx##164, sfx), \ + _1(fn, pfx##192, sfx), _1(fn, pfx##193, sfx), \ + _1(fn, pfx##194, sfx), _1(fn, pfx##195, sfx), \ + _1(fn, pfx##196, sfx), _1(fn, pfx##197, sfx), \ + _1(fn, pfx##198, sfx), _1(fn, pfx##199, sfx), \ + _10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx), \ + _10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx), \ + _10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx), \ + _10(fn, pfx##26, sfx), _10(fn, pfx##27, sfx), \ + _1(fn, pfx##280, sfx), _1(fn, pfx##281, sfx), \ + _1(fn, pfx##282, sfx), \ + _1(fn, pfx##288, sfx), _1(fn, pfx##289, sfx), \ + _10(fn, pfx##29, sfx), _10(fn, pfx##30, sfx) + +#define _PORT(pfx, sfx) pfx##_##sfx +#define PORT_310(str) _310(_PORT, PORT, str) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + PORT_310(DATA), /* PORT0_DATA -> PORT309_DATA */ + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + PORT_310(IN), /* PORT0_IN -> PORT309_IN */ + PINMUX_INPUT_END, + + PINMUX_INPUT_PULLUP_BEGIN, + PORT_310(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */ + PINMUX_INPUT_PULLUP_END, + + PINMUX_INPUT_PULLDOWN_BEGIN, + PORT_310(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */ + PINMUX_INPUT_PULLDOWN_END, + + PINMUX_OUTPUT_BEGIN, + PORT_310(OUT), /* PORT0_OUT -> PORT309_OUT */ + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + PORT_310(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */ + PORT_310(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */ + PORT_310(FN0), /* PORT0_FN0 -> PORT309_FN0 */ + PORT_310(FN1), /* PORT0_FN1 -> PORT309_FN1 */ + PORT_310(FN2), /* PORT0_FN2 -> PORT309_FN2 */ + PORT_310(FN3), /* PORT0_FN3 -> PORT309_FN3 */ + PORT_310(FN4), /* PORT0_FN4 -> PORT309_FN4 */ + PORT_310(FN5), /* PORT0_FN5 -> PORT309_FN5 */ + PORT_310(FN6), /* PORT0_FN6 -> PORT309_FN6 */ + PORT_310(FN7), /* PORT0_FN7 -> PORT309_FN7 */ + + MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1, + MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1, + MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1, + MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1, + MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1, + MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1, + MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1, + MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1, + MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1, + MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1, + MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1, + MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1, + MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1, + MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1, + MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1, + MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1, + MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1, + MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1, + MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1, + MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1, + MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1, + MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1, + MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1, + MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1, + MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1, + MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1, + MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1, + MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1, + MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1, + MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1, + MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1, + MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1, + MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1, + MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1, + MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1, + MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1, + MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1, + MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1, + MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1, + MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1, + MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + /* Hardware manual Table 25-1 (Function 0-7) */ + VBUS_0_MARK, + GPI0_MARK, + GPI1_MARK, + GPI2_MARK, + GPI3_MARK, + GPI4_MARK, + GPI5_MARK, + GPI6_MARK, + GPI7_MARK, + SCIFA7_RXD_MARK, + SCIFA7_CTS__MARK, + GPO7_MARK, MFG0_OUT2_MARK, + GPO6_MARK, MFG1_OUT2_MARK, + GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK, + SCIFA0_TXD_MARK, + SCIFA7_TXD_MARK, + SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK, + GPO0_MARK, + GPO1_MARK, + GPO2_MARK, STATUS0_MARK, + GPO3_MARK, STATUS1_MARK, + GPO4_MARK, STATUS2_MARK, + VINT_MARK, + TCKON_MARK, + XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \ + MFG0_OUT1_MARK, PORT27_IROUT_MARK, + XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \ + PORT28_TPU1TO1_MARK, + SIM_RST_MARK, PORT29_TPU1TO1_MARK, + SIM_CLK_MARK, PORT30_VIO_CKOR_MARK, + SIM_D_MARK, PORT31_IROUT_MARK, + SCIFA4_TXD_MARK, + SCIFA4_RXD_MARK, XWUP_MARK, + SCIFA4_RTS__MARK, + SCIFA4_CTS__MARK, + FSIBOBT_MARK, FSIBIBT_MARK, + FSIBOLR_MARK, FSIBILR_MARK, + FSIBOSLD_MARK, + FSIBISLD_MARK, + VACK_MARK, + XTAL1L_MARK, + SCIFA0_RTS__MARK, FSICOSLDT2_MARK, + SCIFA0_RXD_MARK, + SCIFA0_CTS__MARK, FSICOSLDT1_MARK, + FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK, + FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK, + FSICOSLD_MARK, PORT47_FSICSPDIF_MARK, + FSICISLD_MARK, FSIDISLD_MARK, + FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK, + FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK, + + FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK, + FSIAOSLD_MARK, BBIF2_TXD2_MARK, + FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \ + PORT53_FSICSPDIF_MARK, + FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \ + FSICCK_MARK, FSICOMC_MARK, + FSIAISLD_MARK, TPU0TO0_MARK, + A0_MARK, BS__MARK, + A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK, + A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK, + A14_MARK, KEYOUT5_MARK, + A15_MARK, KEYOUT4_MARK, + A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK, + A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK, + A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK, + A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK, + A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK, + A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK, + A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK, + A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK, + A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK, + A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK, + A26_MARK, KEYIN6_MARK, + KEYIN7_MARK, + D0_NAF0_MARK, + D1_NAF1_MARK, + D2_NAF2_MARK, + D3_NAF3_MARK, + D4_NAF4_MARK, + D5_NAF5_MARK, + D6_NAF6_MARK, + D7_NAF7_MARK, + D8_NAF8_MARK, + D9_NAF9_MARK, + D10_NAF10_MARK, + D11_NAF11_MARK, + D12_NAF12_MARK, + D13_NAF13_MARK, + D14_NAF14_MARK, + D15_NAF15_MARK, + CS4__MARK, + CS5A__MARK, PORT91_RDWR_MARK, + CS5B__MARK, FCE1__MARK, + CS6B__MARK, DACK0_MARK, + FCE0__MARK, CS6A__MARK, + WAIT__MARK, DREQ0_MARK, + RD__FSC_MARK, + WE0__FWE_MARK, RDWR_FWE_MARK, + WE1__MARK, + FRB_MARK, + CKO_MARK, + NBRSTOUT__MARK, + NBRST__MARK, + BBIF2_TXD_MARK, + BBIF2_RXD_MARK, + BBIF2_SYNC_MARK, + BBIF2_SCK_MARK, + SCIFA3_CTS__MARK, MFG3_IN2_MARK, + SCIFA3_RXD_MARK, MFG3_IN1_MARK, + BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK, + SCIFA3_TXD_MARK, + HSI_RX_DATA_MARK, BBIF1_RXD_MARK, + HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK, + HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK, + HSI_TX_READY_MARK, BBIF1_TXD_MARK, + HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \ + PORT115_I2C_SCL3_MARK, + HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \ + PORT116_I2C_SDA3_MARK, + HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK, + HSI_TX_FLAG_MARK, + VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK, + + VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \ + VIO2_HD_MARK, LCD2D1_MARK, + VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK, + VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \ + PORT131_KEYOUT11_MARK, LCD2D11_MARK, + VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \ + PORT132_KEYOUT10_MARK, LCD2D12_MARK, + VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK, + VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK, + VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK, + VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK, + VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK, + VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK, + VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK, + VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK, + VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK, + VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK, + VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \ + VIO2_D5_MARK, LCD2D3_MARK, + VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK, + VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \ + PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK, + VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \ + LCD2D18_MARK, + VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK, + VIO_CKO_MARK, + A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK, + MFG0_IN2_MARK, + TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK, + TS_SDAT3_MARK, MSIOF2_RSYNC_MARK, + TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK, + SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK, + SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK, + SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK, + SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK, + DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK, + PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK, + PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK, + PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK, + PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK, + PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK, + LCDD0_MARK, + LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK, + LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK, + LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK, + LCDD4_MARK, PORT196_SCIFA5_TXD_MARK, + LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK, + LCDD6_MARK, + LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK, + LCDD8_MARK, D16_MARK, + LCDD9_MARK, D17_MARK, + LCDD10_MARK, D18_MARK, + LCDD11_MARK, D19_MARK, + LCDD12_MARK, D20_MARK, + LCDD13_MARK, D21_MARK, + LCDD14_MARK, D22_MARK, + LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK, + LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK, + LCDD17_MARK, D25_MARK, + LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK, + LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK, + LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK, + LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK, + LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK, + LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK, + LCDDCK_MARK, LCDWR__MARK, + LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \ + VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK, + LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \ + PORT218_VIO_CKOR_MARK, + LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \ + MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK, + LCDVSYN_MARK, LCDVSYN2_MARK, + LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \ + MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK, + LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \ + VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK, + + SCIFA1_TXD_MARK, OVCN2_MARK, + EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK, + SCIFA1_RTS__MARK, IDIN_MARK, + SCIFA1_RXD_MARK, + SCIFA1_CTS__MARK, MFG1_IN1_MARK, + MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK, + MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK, + MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK, + MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK, + MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK, + MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK, + MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK, + MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK, + MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK, + MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK, + SCIFA6_TXD_MARK, + PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK, + PORT242_IRDA_IN_MARK, MFG4_IN2_MARK, + PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK, + PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \ + MSIOF2R_RXD_MARK, + PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \ + MSIOF2R_TXD_MARK, + PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \ + TPU1TO0_MARK, + PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \ + TPU3TO1_MARK, + PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \ + TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK, + PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \ + MSIOF2R_TSYNC_MARK, + SDHICLK0_MARK, + SDHICD0_MARK, + SDHID0_0_MARK, + SDHID0_1_MARK, + SDHID0_2_MARK, + SDHID0_3_MARK, + SDHICMD0_MARK, + SDHIWP0_MARK, + SDHICLK1_MARK, + SDHID1_0_MARK, TS_SPSYNC2_MARK, + SDHID1_1_MARK, TS_SDAT2_MARK, + SDHID1_2_MARK, TS_SDEN2_MARK, + SDHID1_3_MARK, TS_SCK2_MARK, + SDHICMD1_MARK, + SDHICLK2_MARK, + SDHID2_0_MARK, TS_SPSYNC4_MARK, + SDHID2_1_MARK, TS_SDAT4_MARK, + SDHID2_2_MARK, TS_SDEN4_MARK, + SDHID2_3_MARK, TS_SCK4_MARK, + SDHICMD2_MARK, + MMCCLK0_MARK, + MMCD0_0_MARK, + MMCD0_1_MARK, + MMCD0_2_MARK, + MMCD0_3_MARK, + MMCD0_4_MARK, TS_SPSYNC5_MARK, + MMCD0_5_MARK, TS_SDAT5_MARK, + MMCD0_6_MARK, TS_SDEN5_MARK, + MMCD0_7_MARK, TS_SCK5_MARK, + MMCCMD0_MARK, + RESETOUTS__MARK, EXTAL2OUT_MARK, + MCP_WAIT__MCP_FRB_MARK, + MCP_CKO_MARK, MMCCLK1_MARK, + MCP_D15_MCP_NAF15_MARK, + MCP_D14_MCP_NAF14_MARK, + MCP_D13_MCP_NAF13_MARK, + MCP_D12_MCP_NAF12_MARK, + MCP_D11_MCP_NAF11_MARK, + MCP_D10_MCP_NAF10_MARK, + MCP_D9_MCP_NAF9_MARK, + MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK, + MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK, + + MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK, + MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK, + MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK, + MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK, + MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK, + MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK, + MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK, + MCP_NBRSTOUT__MARK, + MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK, + + /* MSEL2 special cases */ + TSIF2_TS_XX1_MARK, + TSIF2_TS_XX2_MARK, + TSIF2_TS_XX3_MARK, + TSIF2_TS_XX4_MARK, + TSIF2_TS_XX5_MARK, + TSIF1_TS_XX1_MARK, + TSIF1_TS_XX2_MARK, + TSIF1_TS_XX3_MARK, + TSIF1_TS_XX4_MARK, + TSIF1_TS_XX5_MARK, + TSIF0_TS_XX1_MARK, + TSIF0_TS_XX2_MARK, + TSIF0_TS_XX3_MARK, + TSIF0_TS_XX4_MARK, + TSIF0_TS_XX5_MARK, + MST1_TS_XX1_MARK, + MST1_TS_XX2_MARK, + MST1_TS_XX3_MARK, + MST1_TS_XX4_MARK, + MST1_TS_XX5_MARK, + MST0_TS_XX1_MARK, + MST0_TS_XX2_MARK, + MST0_TS_XX3_MARK, + MST0_TS_XX4_MARK, + MST0_TS_XX5_MARK, + + /* MSEL3 special cases */ + SDHI0_VCCQ_MC0_ON_MARK, + SDHI0_VCCQ_MC0_OFF_MARK, + DEBUG_MON_VIO_MARK, + DEBUG_MON_LCDD_MARK, + LCDC_LCDC0_MARK, + LCDC_LCDC1_MARK, + + /* MSEL4 special cases */ + IRQ9_MEM_INT_MARK, + IRQ9_MCP_INT_MARK, + A11_MARK, + KEYOUT8_MARK, + TPU4TO3_MARK, + RESETA_N_PU_ON_MARK, + RESETA_N_PU_OFF_MARK, + EDBGREQ_PD_MARK, + EDBGREQ_PU_MARK, + + /* Functions with pull-ups */ + KEYIN0_PU_MARK, + KEYIN1_PU_MARK, + KEYIN2_PU_MARK, + KEYIN3_PU_MARK, + KEYIN4_PU_MARK, + KEYIN5_PU_MARK, + KEYIN6_PU_MARK, + KEYIN7_PU_MARK, + SDHID1_0_PU_MARK, + SDHID1_1_PU_MARK, + SDHID1_2_PU_MARK, + SDHID1_3_PU_MARK, + SDHICMD1_PU_MARK, + MMCCMD0_PU_MARK, + MMCCMD1_PU_MARK, + FSIACK_PU_MARK, + FSIAILR_PU_MARK, + FSIAIBT_PU_MARK, + FSIAISLD_PU_MARK, + + PINMUX_MARK_END, +}; + +#define PORT_DATA_I(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN) + +#define PORT_DATA_I_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PD) + +#define PORT_DATA_I_PU(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PU) + +#define PORT_DATA_I_PU_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PD, \ + PORT##nr##_IN_PU) + +#define PORT_DATA_O(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_OUT) + +#define PORT_DATA_IO(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_OUT, PORT##nr##_IN) + +#define PORT_DATA_IO_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_OUT, PORT##nr##_IN, \ + PORT##nr##_IN_PD) + +#define PORT_DATA_IO_PU(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_OUT, PORT##nr##_IN, \ + PORT##nr##_IN_PU) + +#define PORT_DATA_IO_PU_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_OUT, PORT##nr##_IN, \ + PORT##nr##_IN_PD, PORT##nr##_IN_PU) + +static pinmux_enum_t pinmux_data[] = { + /* specify valid pin states for each pin in GPIO mode */ + + /* Table 25-1 (I/O and Pull U/D) */ + PORT_DATA_I_PD(0), + PORT_DATA_I_PU(1), + PORT_DATA_I_PU(2), + PORT_DATA_I_PU(3), + PORT_DATA_I_PU(4), + PORT_DATA_I_PU(5), + PORT_DATA_I_PU(6), + PORT_DATA_I_PU(7), + PORT_DATA_I_PU(8), + PORT_DATA_I_PD(9), + PORT_DATA_I_PD(10), + PORT_DATA_I_PU_PD(11), + PORT_DATA_IO_PU_PD(12), + PORT_DATA_IO_PU_PD(13), + PORT_DATA_IO_PU_PD(14), + PORT_DATA_IO_PU_PD(15), + PORT_DATA_IO_PD(16), + PORT_DATA_IO_PD(17), + PORT_DATA_IO_PU(18), + PORT_DATA_IO_PU(19), + PORT_DATA_O(20), + PORT_DATA_O(21), + PORT_DATA_O(22), + PORT_DATA_O(23), + PORT_DATA_O(24), + PORT_DATA_I_PD(25), + PORT_DATA_I_PD(26), + PORT_DATA_IO_PU(27), + PORT_DATA_IO_PU(28), + PORT_DATA_IO_PD(29), + PORT_DATA_IO_PD(30), + PORT_DATA_IO_PU(31), + PORT_DATA_IO_PD(32), + PORT_DATA_I_PU_PD(33), + PORT_DATA_IO_PD(34), + PORT_DATA_I_PU_PD(35), + PORT_DATA_IO_PD(36), + PORT_DATA_IO(37), + PORT_DATA_O(38), + PORT_DATA_I_PU(39), + PORT_DATA_I_PU_PD(40), + PORT_DATA_O(41), + PORT_DATA_IO_PD(42), + PORT_DATA_IO_PU_PD(43), + PORT_DATA_IO_PU_PD(44), + PORT_DATA_IO_PD(45), + PORT_DATA_IO_PD(46), + PORT_DATA_IO_PD(47), + PORT_DATA_I_PD(48), + PORT_DATA_IO_PU_PD(49), + PORT_DATA_IO_PD(50), + + PORT_DATA_IO_PD(51), + PORT_DATA_O(52), + PORT_DATA_IO_PU_PD(53), + PORT_DATA_IO_PU_PD(54), + PORT_DATA_IO_PD(55), + PORT_DATA_I_PU_PD(56), + PORT_DATA_IO(57), + PORT_DATA_IO(58), + PORT_DATA_IO(59), + PORT_DATA_IO(60), + PORT_DATA_IO(61), + PORT_DATA_IO_PD(62), + PORT_DATA_IO_PD(63), + PORT_DATA_IO_PU_PD(64), + PORT_DATA_IO_PD(65), + PORT_DATA_IO_PU_PD(66), + PORT_DATA_IO_PU_PD(67), + PORT_DATA_IO_PU_PD(68), + PORT_DATA_IO_PU_PD(69), + PORT_DATA_IO_PU_PD(70), + PORT_DATA_IO_PU_PD(71), + PORT_DATA_IO_PU_PD(72), + PORT_DATA_I_PU_PD(73), + PORT_DATA_IO_PU(74), + PORT_DATA_IO_PU(75), + PORT_DATA_IO_PU(76), + PORT_DATA_IO_PU(77), + PORT_DATA_IO_PU(78), + PORT_DATA_IO_PU(79), + PORT_DATA_IO_PU(80), + PORT_DATA_IO_PU(81), + PORT_DATA_IO_PU(82), + PORT_DATA_IO_PU(83), + PORT_DATA_IO_PU(84), + PORT_DATA_IO_PU(85), + PORT_DATA_IO_PU(86), + PORT_DATA_IO_PU(87), + PORT_DATA_IO_PU(88), + PORT_DATA_IO_PU(89), + PORT_DATA_O(90), + PORT_DATA_IO_PU(91), + PORT_DATA_O(92), + PORT_DATA_IO_PU(93), + PORT_DATA_O(94), + PORT_DATA_I_PU_PD(95), + PORT_DATA_IO(96), + PORT_DATA_IO(97), + PORT_DATA_IO(98), + PORT_DATA_I_PU(99), + PORT_DATA_O(100), + PORT_DATA_O(101), + PORT_DATA_I_PU(102), + PORT_DATA_IO_PD(103), + PORT_DATA_I_PU_PD(104), + PORT_DATA_I_PD(105), + PORT_DATA_I_PD(106), + PORT_DATA_I_PU_PD(107), + PORT_DATA_I_PU_PD(108), + PORT_DATA_IO_PD(109), + PORT_DATA_IO_PD(110), + PORT_DATA_IO_PU_PD(111), + PORT_DATA_IO_PU_PD(112), + PORT_DATA_IO_PU_PD(113), + PORT_DATA_IO_PD(114), + PORT_DATA_IO_PU(115), + PORT_DATA_IO_PU(116), + PORT_DATA_IO_PU_PD(117), + PORT_DATA_IO_PU_PD(118), + PORT_DATA_IO_PD(128), + + PORT_DATA_IO_PD(129), + PORT_DATA_IO_PU_PD(130), + PORT_DATA_IO_PD(131), + PORT_DATA_IO_PD(132), + PORT_DATA_IO_PD(133), + PORT_DATA_IO_PU_PD(134), + PORT_DATA_IO_PU_PD(135), + PORT_DATA_IO_PU_PD(136), + PORT_DATA_IO_PU_PD(137), + PORT_DATA_IO_PD(138), + PORT_DATA_IO_PD(139), + PORT_DATA_IO_PD(140), + PORT_DATA_IO_PD(141), + PORT_DATA_IO_PD(142), + PORT_DATA_IO_PD(143), + PORT_DATA_IO_PU_PD(144), + PORT_DATA_IO_PD(145), + PORT_DATA_IO_PU_PD(146), + PORT_DATA_IO_PU_PD(147), + PORT_DATA_IO_PU_PD(148), + PORT_DATA_IO_PU_PD(149), + PORT_DATA_I_PU_PD(150), + PORT_DATA_IO_PU_PD(151), + PORT_DATA_IO_PU_PD(152), + PORT_DATA_IO_PD(153), + PORT_DATA_IO_PD(154), + PORT_DATA_I_PU_PD(155), + PORT_DATA_IO_PU_PD(156), + PORT_DATA_I_PD(157), + PORT_DATA_IO_PD(158), + PORT_DATA_IO_PU_PD(159), + PORT_DATA_IO_PU_PD(160), + PORT_DATA_I_PU_PD(161), + PORT_DATA_I_PU_PD(162), + PORT_DATA_IO_PU_PD(163), + PORT_DATA_I_PU_PD(164), + PORT_DATA_IO_PD(192), + PORT_DATA_IO_PU_PD(193), + PORT_DATA_IO_PD(194), + PORT_DATA_IO_PU_PD(195), + PORT_DATA_IO_PD(196), + PORT_DATA_IO_PD(197), + PORT_DATA_IO_PD(198), + PORT_DATA_IO_PD(199), + PORT_DATA_IO_PU_PD(200), + PORT_DATA_IO_PU_PD(201), + PORT_DATA_IO_PU_PD(202), + PORT_DATA_IO_PU_PD(203), + PORT_DATA_IO_PU_PD(204), + PORT_DATA_IO_PU_PD(205), + PORT_DATA_IO_PU_PD(206), + PORT_DATA_IO_PD(207), + PORT_DATA_IO_PD(208), + PORT_DATA_IO_PD(209), + PORT_DATA_IO_PD(210), + PORT_DATA_IO_PD(211), + PORT_DATA_IO_PD(212), + PORT_DATA_IO_PD(213), + PORT_DATA_IO_PU_PD(214), + PORT_DATA_IO_PU_PD(215), + PORT_DATA_IO_PD(216), + PORT_DATA_IO_PD(217), + PORT_DATA_O(218), + PORT_DATA_IO_PD(219), + PORT_DATA_IO_PD(220), + PORT_DATA_IO_PU_PD(221), + PORT_DATA_IO_PU_PD(222), + PORT_DATA_I_PU_PD(223), + PORT_DATA_I_PU_PD(224), + + PORT_DATA_IO_PU_PD(225), + PORT_DATA_O(226), + PORT_DATA_IO_PU_PD(227), + PORT_DATA_I_PU_PD(228), + PORT_DATA_I_PD(229), + PORT_DATA_IO(230), + PORT_DATA_IO_PU_PD(231), + PORT_DATA_IO_PU_PD(232), + PORT_DATA_I_PU_PD(233), + PORT_DATA_IO_PU_PD(234), + PORT_DATA_IO_PU_PD(235), + PORT_DATA_IO_PU_PD(236), + PORT_DATA_IO_PD(237), + PORT_DATA_IO_PU_PD(238), + PORT_DATA_IO_PU_PD(239), + PORT_DATA_IO_PU_PD(240), + PORT_DATA_O(241), + PORT_DATA_I_PD(242), + PORT_DATA_IO_PU_PD(243), + PORT_DATA_IO_PU_PD(244), + PORT_DATA_IO_PU_PD(245), + PORT_DATA_IO_PU_PD(246), + PORT_DATA_IO_PU_PD(247), + PORT_DATA_IO_PU_PD(248), + PORT_DATA_IO_PU_PD(249), + PORT_DATA_IO_PU_PD(250), + PORT_DATA_IO_PU_PD(251), + PORT_DATA_IO_PU_PD(252), + PORT_DATA_IO_PU_PD(253), + PORT_DATA_IO_PU_PD(254), + PORT_DATA_IO_PU_PD(255), + PORT_DATA_IO_PU_PD(256), + PORT_DATA_IO_PU_PD(257), + PORT_DATA_IO_PU_PD(258), + PORT_DATA_IO_PU_PD(259), + PORT_DATA_IO_PU_PD(260), + PORT_DATA_IO_PU_PD(261), + PORT_DATA_IO_PU_PD(262), + PORT_DATA_IO_PU_PD(263), + PORT_DATA_IO_PU_PD(264), + PORT_DATA_IO_PU_PD(265), + PORT_DATA_IO_PU_PD(266), + PORT_DATA_IO_PU_PD(267), + PORT_DATA_IO_PU_PD(268), + PORT_DATA_IO_PU_PD(269), + PORT_DATA_IO_PU_PD(270), + PORT_DATA_IO_PU_PD(271), + PORT_DATA_IO_PU_PD(272), + PORT_DATA_IO_PU_PD(273), + PORT_DATA_IO_PU_PD(274), + PORT_DATA_IO_PU_PD(275), + PORT_DATA_IO_PU_PD(276), + PORT_DATA_IO_PU_PD(277), + PORT_DATA_IO_PU_PD(278), + PORT_DATA_IO_PU_PD(279), + PORT_DATA_IO_PU_PD(280), + PORT_DATA_O(281), + PORT_DATA_O(282), + PORT_DATA_I_PU(288), + PORT_DATA_IO_PU_PD(289), + PORT_DATA_IO_PU_PD(290), + PORT_DATA_IO_PU_PD(291), + PORT_DATA_IO_PU_PD(292), + PORT_DATA_IO_PU_PD(293), + PORT_DATA_IO_PU_PD(294), + PORT_DATA_IO_PU_PD(295), + PORT_DATA_IO_PU_PD(296), + PORT_DATA_IO_PU_PD(297), + PORT_DATA_IO_PU_PD(298), + + PORT_DATA_IO_PU_PD(299), + PORT_DATA_IO_PU_PD(300), + PORT_DATA_IO_PU_PD(301), + PORT_DATA_IO_PU_PD(302), + PORT_DATA_IO_PU_PD(303), + PORT_DATA_IO_PU_PD(304), + PORT_DATA_IO_PU_PD(305), + PORT_DATA_O(306), + PORT_DATA_O(307), + PORT_DATA_I_PU(308), + PORT_DATA_O(309), + + /* Table 25-1 (Function 0-7) */ + PINMUX_DATA(VBUS_0_MARK, PORT0_FN1), + PINMUX_DATA(GPI0_MARK, PORT1_FN1), + PINMUX_DATA(GPI1_MARK, PORT2_FN1), + PINMUX_DATA(GPI2_MARK, PORT3_FN1), + PINMUX_DATA(GPI3_MARK, PORT4_FN1), + PINMUX_DATA(GPI4_MARK, PORT5_FN1), + PINMUX_DATA(GPI5_MARK, PORT6_FN1), + PINMUX_DATA(GPI6_MARK, PORT7_FN1), + PINMUX_DATA(GPI7_MARK, PORT8_FN1), + PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2), + PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2), + PINMUX_DATA(GPO7_MARK, PORT14_FN1), \ + PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4), + PINMUX_DATA(GPO6_MARK, PORT15_FN1), \ + PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4), + PINMUX_DATA(GPO5_MARK, PORT16_FN1), \ + PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \ + PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \ + PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4), + PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2), + PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2), + PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \ + PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3), + PINMUX_DATA(GPO0_MARK, PORT20_FN1), + PINMUX_DATA(GPO1_MARK, PORT21_FN1), + PINMUX_DATA(GPO2_MARK, PORT22_FN1), \ + PINMUX_DATA(STATUS0_MARK, PORT22_FN2), + PINMUX_DATA(GPO3_MARK, PORT23_FN1), \ + PINMUX_DATA(STATUS1_MARK, PORT23_FN2), + PINMUX_DATA(GPO4_MARK, PORT24_FN1), \ + PINMUX_DATA(STATUS2_MARK, PORT24_FN2), + PINMUX_DATA(VINT_MARK, PORT25_FN1), + PINMUX_DATA(TCKON_MARK, PORT26_FN1), + PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \ + PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0, + MSEL2CR_MSEL16_1), \ + PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0, + MSEL2CR_MSEL18_0), \ + PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \ + PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7), + PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \ + PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0, + MSEL2CR_MSEL16_1), \ + PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0, + MSEL2CR_MSEL18_0), \ + PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7), + PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \ + PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4), + PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \ + PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4), + PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \ + PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4), + PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2), + PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \ + PINMUX_DATA(XWUP_MARK, PORT33_FN3), + PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2), + PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2), + PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \ + PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2), + PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \ + PINMUX_DATA(FSIBILR_MARK, PORT37_FN2), + PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1), + PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1), + PINMUX_DATA(VACK_MARK, PORT40_FN1), + PINMUX_DATA(XTAL1L_MARK, PORT41_FN1), + PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \ + PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3), + PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2), + PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \ + PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3), + PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \ + PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \ + PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \ + PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4), + PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \ + PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \ + PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \ + PINMUX_DATA(FSIDILR_MARK, PORT46_FN4), + PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \ + PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2), + PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \ + PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3), + PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \ + PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \ + PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \ + PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5), + PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \ + PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \ + PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \ + PINMUX_DATA(FSIAILR_MARK, PORT50_FN5), + + PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \ + PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \ + PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \ + PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5), + PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \ + PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2), + PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \ + PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \ + PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \ + PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \ + PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6), + PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \ + PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \ + PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \ + PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \ + PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \ + PINMUX_DATA(FSICOMC_MARK, PORT54_FN7), + PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \ + PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3), + PINMUX_DATA(A0_MARK, PORT57_FN1), \ + PINMUX_DATA(BS__MARK, PORT57_FN2), + PINMUX_DATA(A12_MARK, PORT58_FN1), \ + PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \ + PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4), + PINMUX_DATA(A13_MARK, PORT59_FN1), \ + PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \ + PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4), + PINMUX_DATA(A14_MARK, PORT60_FN1), \ + PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2), + PINMUX_DATA(A15_MARK, PORT61_FN1), \ + PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2), + PINMUX_DATA(A16_MARK, PORT62_FN1), \ + PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \ + PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A17_MARK, PORT63_FN1), \ + PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \ + PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A18_MARK, PORT64_FN1), \ + PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \ + PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A19_MARK, PORT65_FN1), \ + PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \ + PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A20_MARK, PORT66_FN1), \ + PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \ + PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A21_MARK, PORT67_FN1), \ + PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \ + PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A22_MARK, PORT68_FN1), \ + PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \ + PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A23_MARK, PORT69_FN1), \ + PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \ + PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A24_MARK, PORT70_FN1), \ + PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \ + PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A25_MARK, PORT71_FN1), \ + PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \ + PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A26_MARK, PORT72_FN1), \ + PINMUX_DATA(KEYIN6_MARK, PORT72_FN2), + PINMUX_DATA(KEYIN7_MARK, PORT73_FN2), + PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1), + PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1), + PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1), + PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1), + PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1), + PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1), + PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1), + PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1), + PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1), + PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1), + PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1), + PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1), + PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1), + PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1), + PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1), + PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1), + PINMUX_DATA(CS4__MARK, PORT90_FN1), + PINMUX_DATA(CS5A__MARK, PORT91_FN1), \ + PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2), + PINMUX_DATA(CS5B__MARK, PORT92_FN1), \ + PINMUX_DATA(FCE1__MARK, PORT92_FN2), + PINMUX_DATA(CS6B__MARK, PORT93_FN1), \ + PINMUX_DATA(DACK0_MARK, PORT93_FN4), + PINMUX_DATA(FCE0__MARK, PORT94_FN1), \ + PINMUX_DATA(CS6A__MARK, PORT94_FN2), + PINMUX_DATA(WAIT__MARK, PORT95_FN1), \ + PINMUX_DATA(DREQ0_MARK, PORT95_FN2), + PINMUX_DATA(RD__FSC_MARK, PORT96_FN1), + PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \ + PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2), + PINMUX_DATA(WE1__MARK, PORT98_FN1), + PINMUX_DATA(FRB_MARK, PORT99_FN1), + PINMUX_DATA(CKO_MARK, PORT100_FN1), + PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1), + PINMUX_DATA(NBRST__MARK, PORT102_FN1), + PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3), + PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3), + PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3), + PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3), + PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \ + PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4), + PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \ + PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4), + PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \ + PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \ + PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4), + PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3), + PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \ + PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3), + PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \ + PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3), + PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \ + PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3), + PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \ + PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3), + PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \ + PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \ + PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \ + PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1), + PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \ + PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \ + PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \ + PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1), + PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \ + PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \ + PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3), + PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1), + PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \ + PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \ + PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \ + PINMUX_DATA(LCD2D0_MARK, PORT128_FN7), + + PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \ + PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \ + PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \ + PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \ + PINMUX_DATA(LCD2D1_MARK, PORT129_FN7), + PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \ + PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0, + MSEL4CR_MSEL10_1), \ + PINMUX_DATA(LCD2D10_MARK, PORT130_FN7), + PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \ + PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \ + PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \ + PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \ + PINMUX_DATA(LCD2D11_MARK, PORT131_FN7), + PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \ + PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \ + PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \ + PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \ + PINMUX_DATA(LCD2D12_MARK, PORT132_FN7), + PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \ + PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \ + PINMUX_DATA(LCD2D13_MARK, PORT133_FN7), + PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \ + PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \ + PINMUX_DATA(LCD2D14_MARK, PORT134_FN7), + PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \ + PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \ + PINMUX_DATA(LCD2D15_MARK, PORT135_FN7), + PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \ + PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \ + PINMUX_DATA(LCD2D16_MARK, PORT136_FN7), + PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \ + PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \ + PINMUX_DATA(LCD2D17_MARK, PORT137_FN7), + PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \ + PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \ + PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \ + PINMUX_DATA(LCD2D6_MARK, PORT138_FN7), + PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \ + PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \ + PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \ + PINMUX_DATA(LCD2D7_MARK, PORT139_FN7), + PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \ + PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \ + PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \ + PINMUX_DATA(LCD2D8_MARK, PORT140_FN7), + PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \ + PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \ + PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \ + PINMUX_DATA(LCD2D9_MARK, PORT141_FN7), + PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \ + PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \ + PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \ + PINMUX_DATA(LCD2D2_MARK, PORT142_FN7), + PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \ + PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \ + PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \ + PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \ + PINMUX_DATA(LCD2D3_MARK, PORT143_FN7), + PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \ + PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \ + PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \ + PINMUX_DATA(LCD2D4_MARK, PORT144_FN7), + PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \ + PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \ + PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \ + PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \ + PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \ + PINMUX_DATA(LCD2D5_MARK, PORT145_FN7), + PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \ + PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \ + PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \ + PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \ + PINMUX_DATA(LCD2D18_MARK, PORT146_FN7), + PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \ + PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \ + PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \ + PINMUX_DATA(LCD2D19_MARK, PORT147_FN7), + PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1), + PINMUX_DATA(A27_MARK, PORT149_FN1), \ + PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \ + PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \ + PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4), + PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3), + PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \ + PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5), + PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \ + PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5), + PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \ + PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \ + PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5), + PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \ + PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5), + PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \ + PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5), + PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \ + PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5), + PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \ + PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0, + MSEL4CR_MSEL10_0), + PINMUX_DATA(DINT__MARK, PORT158_FN1), \ + PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \ + PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4), + PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \ + PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \ + PINMUX_DATA(NMI_MARK, PORT159_FN3), + PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \ + PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1), + PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \ + PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1), + PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \ + PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1), + PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \ + PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \ + PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5), + PINMUX_DATA(LCDD0_MARK, PORT192_FN1), + PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \ + PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_1), \ + PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5), + PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \ + PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_1), \ + PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5), + PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \ + PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_1), \ + PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5), + PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \ + PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_1), + PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \ + PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_1), \ + PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \ + PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7), + PINMUX_DATA(LCDD6_MARK, PORT198_FN1), + PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \ + PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \ + PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5), + PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \ + PINMUX_DATA(D16_MARK, PORT200_FN6), + PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \ + PINMUX_DATA(D17_MARK, PORT201_FN6), + PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \ + PINMUX_DATA(D18_MARK, PORT202_FN6), + PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \ + PINMUX_DATA(D19_MARK, PORT203_FN6), + PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \ + PINMUX_DATA(D20_MARK, PORT204_FN6), + PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \ + PINMUX_DATA(D21_MARK, PORT205_FN6), + PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \ + PINMUX_DATA(D22_MARK, PORT206_FN6), + PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \ + PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(D23_MARK, PORT207_FN6), + PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \ + PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(D24_MARK, PORT208_FN6), + PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \ + PINMUX_DATA(D25_MARK, PORT209_FN6), + PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \ + PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \ + PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(D26_MARK, PORT210_FN6), + PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \ + PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(D27_MARK, PORT211_FN6), + PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \ + PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \ + PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(D28_MARK, PORT212_FN6), + PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \ + PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \ + PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(D29_MARK, PORT213_FN6), + PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \ + PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \ + PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(D30_MARK, PORT214_FN6), + PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \ + PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \ + PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(D31_MARK, PORT215_FN6), + PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \ + PINMUX_DATA(LCDWR__MARK, PORT216_FN2), + PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \ + PINMUX_DATA(DACK2_MARK, PORT217_FN2), \ + PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \ + PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_1), \ + PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7), + PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \ + PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \ + PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \ + PINMUX_DATA(DACK3_MARK, PORT218_FN4), \ + PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5), + PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \ + PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \ + PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \ + PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \ + PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_1), \ + PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7), + PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \ + PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2), + PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \ + PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \ + PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \ + PINMUX_DATA(PWEN_MARK, PORT221_FN4), \ + PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_1), \ + PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7), + PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \ + PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \ + PINMUX_DATA(DACK1_MARK, PORT222_FN3), \ + PINMUX_DATA(OVCN_MARK, PORT222_FN4), \ + PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_1), \ + PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1), + + PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \ + PINMUX_DATA(OVCN2_MARK, PORT225_FN4), + PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \ + PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \ + PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5), + PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \ + PINMUX_DATA(IDIN_MARK, PORT227_FN4), + PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2), + PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \ + PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3), + PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \ + PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1), + PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \ + PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1), + PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \ + PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1), + PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \ + PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1), + PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \ + PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \ + PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_0), \ + PINMUX_DATA(LCD2D20_MARK, PORT234_FN7), + PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \ + PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \ + PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_0), \ + PINMUX_DATA(LCD2D21_MARK, PORT235_FN7), + PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \ + PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0, + MSEL2CR_MSEL16_0), + PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \ + PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0, + MSEL2CR_MSEL16_0), + PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \ + PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_0), \ + PINMUX_DATA(LCD2D22_MARK, PORT238_FN7), + PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \ + PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_0), \ + PINMUX_DATA(LCD2D23_MARK, PORT239_FN7), + PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1), + PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \ + PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \ + PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \ + PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4), + PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \ + PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3), + PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \ + PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2), + PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_0), \ + PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \ + PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \ + PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1), + PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_0), \ + PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \ + PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \ + PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1), + PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_0), \ + PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \ + PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \ + PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4), + PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_0), \ + PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \ + PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \ + PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4), + PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_0), \ + PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \ + PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \ + PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \ + PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0, + MSEL2CR_MSEL18_0), \ + PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1), + PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \ + PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \ + PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0, + MSEL2CR_MSEL18_0), \ + PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1), + PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1), + PINMUX_DATA(SDHICD0_MARK, PORT251_FN1), + PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1), + PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1), + PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1), + PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1), + PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1), + PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1), + PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1), + PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \ + PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3), + PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \ + PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3), + PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \ + PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3), + PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \ + PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3), + PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1), + PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1), + PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \ + PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3), + PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \ + PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3), + PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \ + PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3), + PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \ + PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3), + PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1), + PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0), \ + PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3), + PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0), \ + PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3), + PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0), \ + PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3), + PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0), \ + PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3), + PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \ + PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2), + PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1), + PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \ + PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1), + PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1), + PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1), + PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1), + PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1), + PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1), + PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1), + PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1), + PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \ + PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1), + PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \ + PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1), + + PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \ + PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1), + PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \ + PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1), + PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \ + PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1), + PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \ + PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1), + PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \ + PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1), + PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \ + PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1), + PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \ + PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1), + PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1), + PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \ + PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2), + + /* MSEL2 special cases */ + PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0, + MSEL2CR_MSEL12_0), + PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0, + MSEL2CR_MSEL12_1), + PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1, + MSEL2CR_MSEL12_0), + PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1, + MSEL2CR_MSEL12_1), + PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0, + MSEL2CR_MSEL12_0), + PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0, + MSEL2CR_MSEL9_0), + PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0, + MSEL2CR_MSEL9_1), + PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1, + MSEL2CR_MSEL9_0), + PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1, + MSEL2CR_MSEL9_1), + PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0, + MSEL2CR_MSEL9_0), + PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0, + MSEL2CR_MSEL6_0), + PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0, + MSEL2CR_MSEL6_1), + PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1, + MSEL2CR_MSEL6_0), + PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1, + MSEL2CR_MSEL6_1), + PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0, + MSEL2CR_MSEL6_0), + PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0, + MSEL2CR_MSEL3_0), + PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0, + MSEL2CR_MSEL3_1), + PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1, + MSEL2CR_MSEL3_0), + PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1, + MSEL2CR_MSEL3_1), + PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0, + MSEL2CR_MSEL3_0), + PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0, + MSEL2CR_MSEL0_0), + PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0, + MSEL2CR_MSEL0_1), + PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1, + MSEL2CR_MSEL0_0), + PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1, + MSEL2CR_MSEL0_1), + PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0, + MSEL2CR_MSEL0_0), + + /* MSEL3 special cases */ + PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1), + PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0), + PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0), + PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1), + PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0), + PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1), + + /* MSEL4 special cases */ + PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0), + PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1), + PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0), + PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1), + PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0), + PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0), + PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1), + PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0), + PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1), + + /* Functions with pull-ups */ + PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU), + PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU), + PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU), + PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU), + PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU), + PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU), + PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU), + PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU), + + PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_IN_PU, PORT259_FN1), + PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_IN_PU, PORT260_FN1), + PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_IN_PU, PORT261_FN1), + PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_IN_PU, PORT262_FN1), + PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_IN_PU, PORT263_FN1), + + PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU, + MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT279_IN_PU, + MSEL4CR_MSEL15_1), + PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU), + PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU), + PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU), + PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU), +}; + +#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA) +#define GPIO_PORT_310() _310(_GPIO_PORT, , unused) +#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK) + +static struct pinmux_gpio pinmux_gpios[] = { + GPIO_PORT_310(), + + /* Table 25-1 (Functions 0-7) */ + GPIO_FN(VBUS_0), + GPIO_FN(GPI0), + GPIO_FN(GPI1), + GPIO_FN(GPI2), + GPIO_FN(GPI3), + GPIO_FN(GPI4), + GPIO_FN(GPI5), + GPIO_FN(GPI6), + GPIO_FN(GPI7), + GPIO_FN(SCIFA7_RXD), + GPIO_FN(SCIFA7_CTS_), + GPIO_FN(GPO7), \ + GPIO_FN(MFG0_OUT2), + GPIO_FN(GPO6), \ + GPIO_FN(MFG1_OUT2), + GPIO_FN(GPO5), \ + GPIO_FN(SCIFA0_SCK), \ + GPIO_FN(FSICOSLDT3), \ + GPIO_FN(PORT16_VIO_CKOR), + GPIO_FN(SCIFA0_TXD), + GPIO_FN(SCIFA7_TXD), + GPIO_FN(SCIFA7_RTS_), \ + GPIO_FN(PORT19_VIO_CKO2), + GPIO_FN(GPO0), + GPIO_FN(GPO1), + GPIO_FN(GPO2), \ + GPIO_FN(STATUS0), + GPIO_FN(GPO3), \ + GPIO_FN(STATUS1), + GPIO_FN(GPO4), \ + GPIO_FN(STATUS2), + GPIO_FN(VINT), + GPIO_FN(TCKON), + GPIO_FN(XDVFS1), \ + GPIO_FN(PORT27_I2C_SCL2), \ + GPIO_FN(PORT27_I2C_SCL3), \ + GPIO_FN(MFG0_OUT1), \ + GPIO_FN(PORT27_IROUT), + GPIO_FN(XDVFS2), \ + GPIO_FN(PORT28_I2C_SDA2), \ + GPIO_FN(PORT28_I2C_SDA3), \ + GPIO_FN(PORT28_TPU1TO1), + GPIO_FN(SIM_RST), \ + GPIO_FN(PORT29_TPU1TO1), + GPIO_FN(SIM_CLK), \ + GPIO_FN(PORT30_VIO_CKOR), + GPIO_FN(SIM_D), \ + GPIO_FN(PORT31_IROUT), + GPIO_FN(SCIFA4_TXD), + GPIO_FN(SCIFA4_RXD), \ + GPIO_FN(XWUP), + GPIO_FN(SCIFA4_RTS_), + GPIO_FN(SCIFA4_CTS_), + GPIO_FN(FSIBOBT), \ + GPIO_FN(FSIBIBT), + GPIO_FN(FSIBOLR), \ + GPIO_FN(FSIBILR), + GPIO_FN(FSIBOSLD), + GPIO_FN(FSIBISLD), + GPIO_FN(VACK), + GPIO_FN(XTAL1L), + GPIO_FN(SCIFA0_RTS_), \ + GPIO_FN(FSICOSLDT2), + GPIO_FN(SCIFA0_RXD), + GPIO_FN(SCIFA0_CTS_), \ + GPIO_FN(FSICOSLDT1), + GPIO_FN(FSICOBT), \ + GPIO_FN(FSICIBT), \ + GPIO_FN(FSIDOBT), \ + GPIO_FN(FSIDIBT), + GPIO_FN(FSICOLR), \ + GPIO_FN(FSICILR), \ + GPIO_FN(FSIDOLR), \ + GPIO_FN(FSIDILR), + GPIO_FN(FSICOSLD), \ + GPIO_FN(PORT47_FSICSPDIF), + GPIO_FN(FSICISLD), \ + GPIO_FN(FSIDISLD), + GPIO_FN(FSIACK), \ + GPIO_FN(PORT49_IRDA_OUT), \ + GPIO_FN(PORT49_IROUT), \ + GPIO_FN(FSIAOMC), + GPIO_FN(FSIAOLR), \ + GPIO_FN(BBIF2_TSYNC2), \ + GPIO_FN(TPU2TO2), \ + GPIO_FN(FSIAILR), + + GPIO_FN(FSIAOBT), \ + GPIO_FN(BBIF2_TSCK2), \ + GPIO_FN(TPU2TO3), \ + GPIO_FN(FSIAIBT), + GPIO_FN(FSIAOSLD), \ + GPIO_FN(BBIF2_TXD2), + GPIO_FN(FSIASPDIF), \ + GPIO_FN(PORT53_IRDA_IN), \ + GPIO_FN(TPU3TO3), \ + GPIO_FN(FSIBSPDIF), \ + GPIO_FN(PORT53_FSICSPDIF), + GPIO_FN(FSIBCK), \ + GPIO_FN(PORT54_IRDA_FIRSEL), \ + GPIO_FN(TPU3TO2), \ + GPIO_FN(FSIBOMC), \ + GPIO_FN(FSICCK), \ + GPIO_FN(FSICOMC), + GPIO_FN(FSIAISLD), \ + GPIO_FN(TPU0TO0), + GPIO_FN(A0), \ + GPIO_FN(BS_), + GPIO_FN(A12), \ + GPIO_FN(PORT58_KEYOUT7), \ + GPIO_FN(TPU4TO2), + GPIO_FN(A13), \ + GPIO_FN(PORT59_KEYOUT6), \ + GPIO_FN(TPU0TO1), + GPIO_FN(A14), \ + GPIO_FN(KEYOUT5), + GPIO_FN(A15), \ + GPIO_FN(KEYOUT4), + GPIO_FN(A16), \ + GPIO_FN(KEYOUT3), \ + GPIO_FN(MSIOF0_SS1), + GPIO_FN(A17), \ + GPIO_FN(KEYOUT2), \ + GPIO_FN(MSIOF0_TSYNC), + GPIO_FN(A18), \ + GPIO_FN(KEYOUT1), \ + GPIO_FN(MSIOF0_TSCK), + GPIO_FN(A19), \ + GPIO_FN(KEYOUT0), \ + GPIO_FN(MSIOF0_TXD), + GPIO_FN(A20), \ + GPIO_FN(KEYIN0), \ + GPIO_FN(MSIOF0_RSCK), + GPIO_FN(A21), \ + GPIO_FN(KEYIN1), \ + GPIO_FN(MSIOF0_RSYNC), + GPIO_FN(A22), \ + GPIO_FN(KEYIN2), \ + GPIO_FN(MSIOF0_MCK0), + GPIO_FN(A23), \ + GPIO_FN(KEYIN3), \ + GPIO_FN(MSIOF0_MCK1), + GPIO_FN(A24), \ + GPIO_FN(KEYIN4), \ + GPIO_FN(MSIOF0_RXD), + GPIO_FN(A25), \ + GPIO_FN(KEYIN5), \ + GPIO_FN(MSIOF0_SS2), + GPIO_FN(A26), \ + GPIO_FN(KEYIN6), + GPIO_FN(KEYIN7), + GPIO_FN(D0_NAF0), + GPIO_FN(D1_NAF1), + GPIO_FN(D2_NAF2), + GPIO_FN(D3_NAF3), + GPIO_FN(D4_NAF4), + GPIO_FN(D5_NAF5), + GPIO_FN(D6_NAF6), + GPIO_FN(D7_NAF7), + GPIO_FN(D8_NAF8), + GPIO_FN(D9_NAF9), + GPIO_FN(D10_NAF10), + GPIO_FN(D11_NAF11), + GPIO_FN(D12_NAF12), + GPIO_FN(D13_NAF13), + GPIO_FN(D14_NAF14), + GPIO_FN(D15_NAF15), + GPIO_FN(CS4_), + GPIO_FN(CS5A_), \ + GPIO_FN(PORT91_RDWR), + GPIO_FN(CS5B_), \ + GPIO_FN(FCE1_), + GPIO_FN(CS6B_), \ + GPIO_FN(DACK0), + GPIO_FN(FCE0_), \ + GPIO_FN(CS6A_), + GPIO_FN(WAIT_), \ + GPIO_FN(DREQ0), + GPIO_FN(RD__FSC), + GPIO_FN(WE0__FWE), \ + GPIO_FN(RDWR_FWE), + GPIO_FN(WE1_), + GPIO_FN(FRB), + GPIO_FN(CKO), + GPIO_FN(NBRSTOUT_), + GPIO_FN(NBRST_), + GPIO_FN(BBIF2_TXD), + GPIO_FN(BBIF2_RXD), + GPIO_FN(BBIF2_SYNC), + GPIO_FN(BBIF2_SCK), + GPIO_FN(SCIFA3_CTS_), \ + GPIO_FN(MFG3_IN2), + GPIO_FN(SCIFA3_RXD), \ + GPIO_FN(MFG3_IN1), + GPIO_FN(BBIF1_SS2), \ + GPIO_FN(SCIFA3_RTS_), \ + GPIO_FN(MFG3_OUT1), + GPIO_FN(SCIFA3_TXD), + GPIO_FN(HSI_RX_DATA), \ + GPIO_FN(BBIF1_RXD), + GPIO_FN(HSI_TX_WAKE), \ + GPIO_FN(BBIF1_TSCK), + GPIO_FN(HSI_TX_DATA), \ + GPIO_FN(BBIF1_TSYNC), + GPIO_FN(HSI_TX_READY), \ + GPIO_FN(BBIF1_TXD), + GPIO_FN(HSI_RX_READY), \ + GPIO_FN(BBIF1_RSCK), \ + GPIO_FN(PORT115_I2C_SCL2), \ + GPIO_FN(PORT115_I2C_SCL3), + GPIO_FN(HSI_RX_WAKE), \ + GPIO_FN(BBIF1_RSYNC), \ + GPIO_FN(PORT116_I2C_SDA2), \ + GPIO_FN(PORT116_I2C_SDA3), + GPIO_FN(HSI_RX_FLAG), \ + GPIO_FN(BBIF1_SS1), \ + GPIO_FN(BBIF1_FLOW), + GPIO_FN(HSI_TX_FLAG), + GPIO_FN(VIO_VD), \ + GPIO_FN(PORT128_LCD2VSYN), \ + GPIO_FN(VIO2_VD), \ + GPIO_FN(LCD2D0), + + GPIO_FN(VIO_HD), \ + GPIO_FN(PORT129_LCD2HSYN), \ + GPIO_FN(PORT129_LCD2CS_), \ + GPIO_FN(VIO2_HD), \ + GPIO_FN(LCD2D1), + GPIO_FN(VIO_D0), \ + GPIO_FN(PORT130_MSIOF2_RXD), \ + GPIO_FN(LCD2D10), + GPIO_FN(VIO_D1), \ + GPIO_FN(PORT131_KEYOUT6), \ + GPIO_FN(PORT131_MSIOF2_SS1), \ + GPIO_FN(PORT131_KEYOUT11), \ + GPIO_FN(LCD2D11), + GPIO_FN(VIO_D2), \ + GPIO_FN(PORT132_KEYOUT7), \ + GPIO_FN(PORT132_MSIOF2_SS2), \ + GPIO_FN(PORT132_KEYOUT10), \ + GPIO_FN(LCD2D12), + GPIO_FN(VIO_D3), \ + GPIO_FN(MSIOF2_TSYNC), \ + GPIO_FN(LCD2D13), + GPIO_FN(VIO_D4), \ + GPIO_FN(MSIOF2_TXD), \ + GPIO_FN(LCD2D14), + GPIO_FN(VIO_D5), \ + GPIO_FN(MSIOF2_TSCK), \ + GPIO_FN(LCD2D15), + GPIO_FN(VIO_D6), \ + GPIO_FN(PORT136_KEYOUT8), \ + GPIO_FN(LCD2D16), + GPIO_FN(VIO_D7), \ + GPIO_FN(PORT137_KEYOUT9), \ + GPIO_FN(LCD2D17), + GPIO_FN(VIO_D8), \ + GPIO_FN(PORT138_KEYOUT8), \ + GPIO_FN(VIO2_D0), \ + GPIO_FN(LCD2D6), + GPIO_FN(VIO_D9), \ + GPIO_FN(PORT139_KEYOUT9), \ + GPIO_FN(VIO2_D1), \ + GPIO_FN(LCD2D7), + GPIO_FN(VIO_D10), \ + GPIO_FN(TPU0TO2), \ + GPIO_FN(VIO2_D2), \ + GPIO_FN(LCD2D8), + GPIO_FN(VIO_D11), \ + GPIO_FN(TPU0TO3), \ + GPIO_FN(VIO2_D3), \ + GPIO_FN(LCD2D9), + GPIO_FN(VIO_D12), \ + GPIO_FN(PORT142_KEYOUT10), \ + GPIO_FN(VIO2_D4), \ + GPIO_FN(LCD2D2), + GPIO_FN(VIO_D13), \ + GPIO_FN(PORT143_KEYOUT11), \ + GPIO_FN(PORT143_KEYOUT6), \ + GPIO_FN(VIO2_D5), \ + GPIO_FN(LCD2D3), + GPIO_FN(VIO_D14), \ + GPIO_FN(PORT144_KEYOUT7), \ + GPIO_FN(VIO2_D6), \ + GPIO_FN(LCD2D4), + GPIO_FN(VIO_D15), \ + GPIO_FN(TPU1TO3), \ + GPIO_FN(PORT145_LCD2DISP), \ + GPIO_FN(PORT145_LCD2RS), \ + GPIO_FN(VIO2_D7), \ + GPIO_FN(LCD2D5), + GPIO_FN(VIO_CLK), \ + GPIO_FN(LCD2DCK), \ + GPIO_FN(PORT146_LCD2WR_), \ + GPIO_FN(VIO2_CLK), \ + GPIO_FN(LCD2D18), + GPIO_FN(VIO_FIELD), \ + GPIO_FN(LCD2RD_), \ + GPIO_FN(VIO2_FIELD), \ + GPIO_FN(LCD2D19), + GPIO_FN(VIO_CKO), + GPIO_FN(A27), \ + GPIO_FN(PORT149_RDWR), \ + GPIO_FN(MFG0_IN1), \ + GPIO_FN(PORT149_KEYOUT9), + GPIO_FN(MFG0_IN2), + GPIO_FN(TS_SPSYNC3), \ + GPIO_FN(MSIOF2_RSCK), + GPIO_FN(TS_SDAT3), \ + GPIO_FN(MSIOF2_RSYNC), + GPIO_FN(TPU1TO2), \ + GPIO_FN(TS_SDEN3), \ + GPIO_FN(PORT153_MSIOF2_SS1), + GPIO_FN(SCIFA2_TXD1), \ + GPIO_FN(MSIOF2_MCK0), + GPIO_FN(SCIFA2_RXD1), \ + GPIO_FN(MSIOF2_MCK1), + GPIO_FN(SCIFA2_RTS1_), \ + GPIO_FN(PORT156_MSIOF2_SS2), + GPIO_FN(SCIFA2_CTS1_), \ + GPIO_FN(PORT157_MSIOF2_RXD), + GPIO_FN(DINT_), \ + GPIO_FN(SCIFA2_SCK1), \ + GPIO_FN(TS_SCK3), + GPIO_FN(PORT159_SCIFB_SCK), \ + GPIO_FN(PORT159_SCIFA5_SCK), \ + GPIO_FN(NMI), + GPIO_FN(PORT160_SCIFB_TXD), \ + GPIO_FN(PORT160_SCIFA5_TXD), + GPIO_FN(PORT161_SCIFB_CTS_), \ + GPIO_FN(PORT161_SCIFA5_CTS_), + GPIO_FN(PORT162_SCIFB_RXD), \ + GPIO_FN(PORT162_SCIFA5_RXD), + GPIO_FN(PORT163_SCIFB_RTS_), \ + GPIO_FN(PORT163_SCIFA5_RTS_), \ + GPIO_FN(TPU3TO0), + GPIO_FN(LCDD0), + GPIO_FN(LCDD1), \ + GPIO_FN(PORT193_SCIFA5_CTS_), \ + GPIO_FN(BBIF2_TSYNC1), + GPIO_FN(LCDD2), \ + GPIO_FN(PORT194_SCIFA5_RTS_), \ + GPIO_FN(BBIF2_TSCK1), + GPIO_FN(LCDD3), \ + GPIO_FN(PORT195_SCIFA5_RXD), \ + GPIO_FN(BBIF2_TXD1), + GPIO_FN(LCDD4), \ + GPIO_FN(PORT196_SCIFA5_TXD), + GPIO_FN(LCDD5), \ + GPIO_FN(PORT197_SCIFA5_SCK), \ + GPIO_FN(MFG2_OUT2), \ + GPIO_FN(TPU2TO1), + GPIO_FN(LCDD6), + GPIO_FN(LCDD7), \ + GPIO_FN(TPU4TO1), \ + GPIO_FN(MFG4_OUT2), + GPIO_FN(LCDD8), \ + GPIO_FN(D16), + GPIO_FN(LCDD9), \ + GPIO_FN(D17), + GPIO_FN(LCDD10), \ + GPIO_FN(D18), + GPIO_FN(LCDD11), \ + GPIO_FN(D19), + GPIO_FN(LCDD12), \ + GPIO_FN(D20), + GPIO_FN(LCDD13), \ + GPIO_FN(D21), + GPIO_FN(LCDD14), \ + GPIO_FN(D22), + GPIO_FN(LCDD15), \ + GPIO_FN(PORT207_MSIOF0L_SS1), \ + GPIO_FN(D23), + GPIO_FN(LCDD16), \ + GPIO_FN(PORT208_MSIOF0L_SS2), \ + GPIO_FN(D24), + GPIO_FN(LCDD17), \ + GPIO_FN(D25), + GPIO_FN(LCDD18), \ + GPIO_FN(DREQ2), \ + GPIO_FN(PORT210_MSIOF0L_SS1), \ + GPIO_FN(D26), + GPIO_FN(LCDD19), \ + GPIO_FN(PORT211_MSIOF0L_SS2), \ + GPIO_FN(D27), + GPIO_FN(LCDD20), \ + GPIO_FN(TS_SPSYNC1), \ + GPIO_FN(MSIOF0L_MCK0), \ + GPIO_FN(D28), + GPIO_FN(LCDD21), \ + GPIO_FN(TS_SDAT1), \ + GPIO_FN(MSIOF0L_MCK1), \ + GPIO_FN(D29), + GPIO_FN(LCDD22), \ + GPIO_FN(TS_SDEN1), \ + GPIO_FN(MSIOF0L_RSCK), \ + GPIO_FN(D30), + GPIO_FN(LCDD23), \ + GPIO_FN(TS_SCK1), \ + GPIO_FN(MSIOF0L_RSYNC), \ + GPIO_FN(D31), + GPIO_FN(LCDDCK), \ + GPIO_FN(LCDWR_), + GPIO_FN(LCDRD_), \ + GPIO_FN(DACK2), \ + GPIO_FN(PORT217_LCD2RS), \ + GPIO_FN(MSIOF0L_TSYNC), \ + GPIO_FN(VIO2_FIELD3), \ + GPIO_FN(PORT217_LCD2DISP), + GPIO_FN(LCDHSYN), \ + GPIO_FN(LCDCS_), \ + GPIO_FN(LCDCS2_), \ + GPIO_FN(DACK3), \ + GPIO_FN(PORT218_VIO_CKOR), + GPIO_FN(LCDDISP), \ + GPIO_FN(LCDRS), \ + GPIO_FN(PORT219_LCD2WR_), \ + GPIO_FN(DREQ3), \ + GPIO_FN(MSIOF0L_TSCK), \ + GPIO_FN(VIO2_CLK3), \ + GPIO_FN(LCD2DCK_2), + GPIO_FN(LCDVSYN), \ + GPIO_FN(LCDVSYN2), + GPIO_FN(LCDLCLK), \ + GPIO_FN(DREQ1), \ + GPIO_FN(PORT221_LCD2CS_), \ + GPIO_FN(PWEN), \ + GPIO_FN(MSIOF0L_RXD), \ + GPIO_FN(VIO2_HD3), \ + GPIO_FN(PORT221_LCD2HSYN), + GPIO_FN(LCDDON), \ + GPIO_FN(LCDDON2), \ + GPIO_FN(DACK1), \ + GPIO_FN(OVCN), \ + GPIO_FN(MSIOF0L_TXD), \ + GPIO_FN(VIO2_VD3), \ + GPIO_FN(PORT222_LCD2VSYN), + + GPIO_FN(SCIFA1_TXD), \ + GPIO_FN(OVCN2), + GPIO_FN(EXTLP), \ + GPIO_FN(SCIFA1_SCK), \ + GPIO_FN(PORT226_VIO_CKO2), + GPIO_FN(SCIFA1_RTS_), \ + GPIO_FN(IDIN), + GPIO_FN(SCIFA1_RXD), + GPIO_FN(SCIFA1_CTS_), \ + GPIO_FN(MFG1_IN1), + GPIO_FN(MSIOF1_TXD), \ + GPIO_FN(SCIFA2_TXD2), + GPIO_FN(MSIOF1_TSYNC), \ + GPIO_FN(SCIFA2_CTS2_), + GPIO_FN(MSIOF1_TSCK), \ + GPIO_FN(SCIFA2_SCK2), + GPIO_FN(MSIOF1_RXD), \ + GPIO_FN(SCIFA2_RXD2), + GPIO_FN(MSIOF1_RSCK), \ + GPIO_FN(SCIFA2_RTS2_), \ + GPIO_FN(VIO2_CLK2), \ + GPIO_FN(LCD2D20), + GPIO_FN(MSIOF1_RSYNC), \ + GPIO_FN(MFG1_IN2), \ + GPIO_FN(VIO2_VD2), \ + GPIO_FN(LCD2D21), + GPIO_FN(MSIOF1_MCK0), \ + GPIO_FN(PORT236_I2C_SDA2), + GPIO_FN(MSIOF1_MCK1), \ + GPIO_FN(PORT237_I2C_SCL2), + GPIO_FN(MSIOF1_SS1), \ + GPIO_FN(VIO2_FIELD2), \ + GPIO_FN(LCD2D22), + GPIO_FN(MSIOF1_SS2), \ + GPIO_FN(VIO2_HD2), \ + GPIO_FN(LCD2D23), + GPIO_FN(SCIFA6_TXD), + GPIO_FN(PORT241_IRDA_OUT), \ + GPIO_FN(PORT241_IROUT), \ + GPIO_FN(MFG4_OUT1), \ + GPIO_FN(TPU4TO0), + GPIO_FN(PORT242_IRDA_IN), \ + GPIO_FN(MFG4_IN2), + GPIO_FN(PORT243_IRDA_FIRSEL), \ + GPIO_FN(PORT243_VIO_CKO2), + GPIO_FN(PORT244_SCIFA5_CTS_), \ + GPIO_FN(MFG2_IN1), \ + GPIO_FN(PORT244_SCIFB_CTS_), \ + GPIO_FN(MSIOF2R_RXD), + GPIO_FN(PORT245_SCIFA5_RTS_), \ + GPIO_FN(MFG2_IN2), \ + GPIO_FN(PORT245_SCIFB_RTS_), \ + GPIO_FN(MSIOF2R_TXD), + GPIO_FN(PORT246_SCIFA5_RXD), \ + GPIO_FN(MFG1_OUT1), \ + GPIO_FN(PORT246_SCIFB_RXD), \ + GPIO_FN(TPU1TO0), + GPIO_FN(PORT247_SCIFA5_TXD), \ + GPIO_FN(MFG3_OUT2), \ + GPIO_FN(PORT247_SCIFB_TXD), \ + GPIO_FN(TPU3TO1), + GPIO_FN(PORT248_SCIFA5_SCK), \ + GPIO_FN(MFG2_OUT1), \ + GPIO_FN(PORT248_SCIFB_SCK), \ + GPIO_FN(TPU2TO0), \ + GPIO_FN(PORT248_I2C_SCL3), \ + GPIO_FN(MSIOF2R_TSCK), + GPIO_FN(PORT249_IROUT), \ + GPIO_FN(MFG4_IN1), \ + GPIO_FN(PORT249_I2C_SDA3), \ + GPIO_FN(MSIOF2R_TSYNC), + GPIO_FN(SDHICLK0), + GPIO_FN(SDHICD0), + GPIO_FN(SDHID0_0), + GPIO_FN(SDHID0_1), + GPIO_FN(SDHID0_2), + GPIO_FN(SDHID0_3), + GPIO_FN(SDHICMD0), + GPIO_FN(SDHIWP0), + GPIO_FN(SDHICLK1), + GPIO_FN(SDHID1_0), \ + GPIO_FN(TS_SPSYNC2), + GPIO_FN(SDHID1_1), \ + GPIO_FN(TS_SDAT2), + GPIO_FN(SDHID1_2), \ + GPIO_FN(TS_SDEN2), + GPIO_FN(SDHID1_3), \ + GPIO_FN(TS_SCK2), + GPIO_FN(SDHICMD1), + GPIO_FN(SDHICLK2), + GPIO_FN(SDHID2_0), \ + GPIO_FN(TS_SPSYNC4), + GPIO_FN(SDHID2_1), \ + GPIO_FN(TS_SDAT4), + GPIO_FN(SDHID2_2), \ + GPIO_FN(TS_SDEN4), + GPIO_FN(SDHID2_3), \ + GPIO_FN(TS_SCK4), + GPIO_FN(SDHICMD2), + GPIO_FN(MMCCLK0), + GPIO_FN(MMCD0_0), + GPIO_FN(MMCD0_1), + GPIO_FN(MMCD0_2), + GPIO_FN(MMCD0_3), + GPIO_FN(MMCD0_4), \ + GPIO_FN(TS_SPSYNC5), + GPIO_FN(MMCD0_5), \ + GPIO_FN(TS_SDAT5), + GPIO_FN(MMCD0_6), \ + GPIO_FN(TS_SDEN5), + GPIO_FN(MMCD0_7), \ + GPIO_FN(TS_SCK5), + GPIO_FN(MMCCMD0), + GPIO_FN(RESETOUTS_), \ + GPIO_FN(EXTAL2OUT), + GPIO_FN(MCP_WAIT__MCP_FRB), + GPIO_FN(MCP_CKO), \ + GPIO_FN(MMCCLK1), + GPIO_FN(MCP_D15_MCP_NAF15), + GPIO_FN(MCP_D14_MCP_NAF14), + GPIO_FN(MCP_D13_MCP_NAF13), + GPIO_FN(MCP_D12_MCP_NAF12), + GPIO_FN(MCP_D11_MCP_NAF11), + GPIO_FN(MCP_D10_MCP_NAF10), + GPIO_FN(MCP_D9_MCP_NAF9), + GPIO_FN(MCP_D8_MCP_NAF8), \ + GPIO_FN(MMCCMD1), + GPIO_FN(MCP_D7_MCP_NAF7), \ + GPIO_FN(MMCD1_7), + + GPIO_FN(MCP_D6_MCP_NAF6), \ + GPIO_FN(MMCD1_6), + GPIO_FN(MCP_D5_MCP_NAF5), \ + GPIO_FN(MMCD1_5), + GPIO_FN(MCP_D4_MCP_NAF4), \ + GPIO_FN(MMCD1_4), + GPIO_FN(MCP_D3_MCP_NAF3), \ + GPIO_FN(MMCD1_3), + GPIO_FN(MCP_D2_MCP_NAF2), \ + GPIO_FN(MMCD1_2), + GPIO_FN(MCP_D1_MCP_NAF1), \ + GPIO_FN(MMCD1_1), + GPIO_FN(MCP_D0_MCP_NAF0), \ + GPIO_FN(MMCD1_0), + GPIO_FN(MCP_NBRSTOUT_), + GPIO_FN(MCP_WE0__MCP_FWE), \ + GPIO_FN(MCP_RDWR_MCP_FWE), + + /* MSEL2 special cases */ + GPIO_FN(TSIF2_TS_XX1), + GPIO_FN(TSIF2_TS_XX2), + GPIO_FN(TSIF2_TS_XX3), + GPIO_FN(TSIF2_TS_XX4), + GPIO_FN(TSIF2_TS_XX5), + GPIO_FN(TSIF1_TS_XX1), + GPIO_FN(TSIF1_TS_XX2), + GPIO_FN(TSIF1_TS_XX3), + GPIO_FN(TSIF1_TS_XX4), + GPIO_FN(TSIF1_TS_XX5), + GPIO_FN(TSIF0_TS_XX1), + GPIO_FN(TSIF0_TS_XX2), + GPIO_FN(TSIF0_TS_XX3), + GPIO_FN(TSIF0_TS_XX4), + GPIO_FN(TSIF0_TS_XX5), + GPIO_FN(MST1_TS_XX1), + GPIO_FN(MST1_TS_XX2), + GPIO_FN(MST1_TS_XX3), + GPIO_FN(MST1_TS_XX4), + GPIO_FN(MST1_TS_XX5), + GPIO_FN(MST0_TS_XX1), + GPIO_FN(MST0_TS_XX2), + GPIO_FN(MST0_TS_XX3), + GPIO_FN(MST0_TS_XX4), + GPIO_FN(MST0_TS_XX5), + + /* MSEL3 special cases */ + GPIO_FN(SDHI0_VCCQ_MC0_ON), + GPIO_FN(SDHI0_VCCQ_MC0_OFF), + GPIO_FN(DEBUG_MON_VIO), + GPIO_FN(DEBUG_MON_LCDD), + GPIO_FN(LCDC_LCDC0), + GPIO_FN(LCDC_LCDC1), + + /* MSEL4 special cases */ + GPIO_FN(IRQ9_MEM_INT), + GPIO_FN(IRQ9_MCP_INT), + GPIO_FN(A11), + GPIO_FN(KEYOUT8), + GPIO_FN(TPU4TO3), + GPIO_FN(RESETA_N_PU_ON), + GPIO_FN(RESETA_N_PU_OFF), + GPIO_FN(EDBGREQ_PD), + GPIO_FN(EDBGREQ_PU), + + /* Functions with pull-ups */ + GPIO_FN(KEYIN0_PU), + GPIO_FN(KEYIN1_PU), + GPIO_FN(KEYIN2_PU), + GPIO_FN(KEYIN3_PU), + GPIO_FN(KEYIN4_PU), + GPIO_FN(KEYIN5_PU), + GPIO_FN(KEYIN6_PU), + GPIO_FN(KEYIN7_PU), + GPIO_FN(SDHID1_0_PU), + GPIO_FN(SDHID1_1_PU), + GPIO_FN(SDHID1_2_PU), + GPIO_FN(SDHID1_3_PU), + GPIO_FN(SDHICMD1_PU), + GPIO_FN(MMCCMD0_PU), + GPIO_FN(MMCCMD1_PU), + GPIO_FN(FSIACK_PU), + GPIO_FN(FSIAILR_PU), + GPIO_FN(FSIAIBT_PU), + GPIO_FN(FSIAISLD_PU), +}; + +#define PORTCR(nr, reg) \ + { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ + 0, \ + /*0001*/ PORT##nr##_OUT , \ + /*0010*/ PORT##nr##_IN , 0, 0, 0, 0, 0, 0, 0, \ + /*1010*/ PORT##nr##_IN_PD, 0, 0, 0, \ + /*1110*/ PORT##nr##_IN_PU, 0, \ + PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \ + PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \ + PORT##nr##_FN6, PORT##nr##_FN7, 0, 0, 0, 0, 0, 0, 0, 0 } \ + } + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + PORTCR(0, 0xe6050000), /* PORT0CR */ + PORTCR(1, 0xe6050001), /* PORT1CR */ + PORTCR(2, 0xe6050002), /* PORT2CR */ + PORTCR(3, 0xe6050003), /* PORT3CR */ + PORTCR(4, 0xe6050004), /* PORT4CR */ + PORTCR(5, 0xe6050005), /* PORT5CR */ + PORTCR(6, 0xe6050006), /* PORT6CR */ + PORTCR(7, 0xe6050007), /* PORT7CR */ + PORTCR(8, 0xe6050008), /* PORT8CR */ + PORTCR(9, 0xe6050009), /* PORT9CR */ + + PORTCR(10, 0xe605000a), /* PORT10CR */ + PORTCR(11, 0xe605000b), /* PORT11CR */ + PORTCR(12, 0xe605000c), /* PORT12CR */ + PORTCR(13, 0xe605000d), /* PORT13CR */ + PORTCR(14, 0xe605000e), /* PORT14CR */ + PORTCR(15, 0xe605000f), /* PORT15CR */ + PORTCR(16, 0xe6050010), /* PORT16CR */ + PORTCR(17, 0xe6050011), /* PORT17CR */ + PORTCR(18, 0xe6050012), /* PORT18CR */ + PORTCR(19, 0xe6050013), /* PORT19CR */ + + PORTCR(20, 0xe6050014), /* PORT20CR */ + PORTCR(21, 0xe6050015), /* PORT21CR */ + PORTCR(22, 0xe6050016), /* PORT22CR */ + PORTCR(23, 0xe6050017), /* PORT23CR */ + PORTCR(24, 0xe6050018), /* PORT24CR */ + PORTCR(25, 0xe6050019), /* PORT25CR */ + PORTCR(26, 0xe605001a), /* PORT26CR */ + PORTCR(27, 0xe605001b), /* PORT27CR */ + PORTCR(28, 0xe605001c), /* PORT28CR */ + PORTCR(29, 0xe605001d), /* PORT29CR */ + + PORTCR(30, 0xe605001e), /* PORT30CR */ + PORTCR(31, 0xe605001f), /* PORT31CR */ + PORTCR(32, 0xe6051020), /* PORT32CR */ + PORTCR(33, 0xe6051021), /* PORT33CR */ + PORTCR(34, 0xe6051022), /* PORT34CR */ + PORTCR(35, 0xe6051023), /* PORT35CR */ + PORTCR(36, 0xe6051024), /* PORT36CR */ + PORTCR(37, 0xe6051025), /* PORT37CR */ + PORTCR(38, 0xe6051026), /* PORT38CR */ + PORTCR(39, 0xe6051027), /* PORT39CR */ + + PORTCR(40, 0xe6051028), /* PORT40CR */ + PORTCR(41, 0xe6051029), /* PORT41CR */ + PORTCR(42, 0xe605102a), /* PORT42CR */ + PORTCR(43, 0xe605102b), /* PORT43CR */ + PORTCR(44, 0xe605102c), /* PORT44CR */ + PORTCR(45, 0xe605102d), /* PORT45CR */ + PORTCR(46, 0xe605102e), /* PORT46CR */ + PORTCR(47, 0xe605102f), /* PORT47CR */ + PORTCR(48, 0xe6051030), /* PORT48CR */ + PORTCR(49, 0xe6051031), /* PORT49CR */ + + PORTCR(50, 0xe6051032), /* PORT50CR */ + PORTCR(51, 0xe6051033), /* PORT51CR */ + PORTCR(52, 0xe6051034), /* PORT52CR */ + PORTCR(53, 0xe6051035), /* PORT53CR */ + PORTCR(54, 0xe6051036), /* PORT54CR */ + PORTCR(55, 0xe6051037), /* PORT55CR */ + PORTCR(56, 0xe6051038), /* PORT56CR */ + PORTCR(57, 0xe6051039), /* PORT57CR */ + PORTCR(58, 0xe605103a), /* PORT58CR */ + PORTCR(59, 0xe605103b), /* PORT59CR */ + + PORTCR(60, 0xe605103c), /* PORT60CR */ + PORTCR(61, 0xe605103d), /* PORT61CR */ + PORTCR(62, 0xe605103e), /* PORT62CR */ + PORTCR(63, 0xe605103f), /* PORT63CR */ + PORTCR(64, 0xe6051040), /* PORT64CR */ + PORTCR(65, 0xe6051041), /* PORT65CR */ + PORTCR(66, 0xe6051042), /* PORT66CR */ + PORTCR(67, 0xe6051043), /* PORT67CR */ + PORTCR(68, 0xe6051044), /* PORT68CR */ + PORTCR(69, 0xe6051045), /* PORT69CR */ + + PORTCR(70, 0xe6051046), /* PORT70CR */ + PORTCR(71, 0xe6051047), /* PORT71CR */ + PORTCR(72, 0xe6051048), /* PORT72CR */ + PORTCR(73, 0xe6051049), /* PORT73CR */ + PORTCR(74, 0xe605104a), /* PORT74CR */ + PORTCR(75, 0xe605104b), /* PORT75CR */ + PORTCR(76, 0xe605104c), /* PORT76CR */ + PORTCR(77, 0xe605104d), /* PORT77CR */ + PORTCR(78, 0xe605104e), /* PORT78CR */ + PORTCR(79, 0xe605104f), /* PORT79CR */ + + PORTCR(80, 0xe6051050), /* PORT80CR */ + PORTCR(81, 0xe6051051), /* PORT81CR */ + PORTCR(82, 0xe6051052), /* PORT82CR */ + PORTCR(83, 0xe6051053), /* PORT83CR */ + PORTCR(84, 0xe6051054), /* PORT84CR */ + PORTCR(85, 0xe6051055), /* PORT85CR */ + PORTCR(86, 0xe6051056), /* PORT86CR */ + PORTCR(87, 0xe6051057), /* PORT87CR */ + PORTCR(88, 0xe6051058), /* PORT88CR */ + PORTCR(89, 0xe6051059), /* PORT89CR */ + + PORTCR(90, 0xe605105a), /* PORT90CR */ + PORTCR(91, 0xe605105b), /* PORT91CR */ + PORTCR(92, 0xe605105c), /* PORT92CR */ + PORTCR(93, 0xe605105d), /* PORT93CR */ + PORTCR(94, 0xe605105e), /* PORT94CR */ + PORTCR(95, 0xe605105f), /* PORT95CR */ + PORTCR(96, 0xe6052060), /* PORT96CR */ + PORTCR(97, 0xe6052061), /* PORT97CR */ + PORTCR(98, 0xe6052062), /* PORT98CR */ + PORTCR(99, 0xe6052063), /* PORT99CR */ + + PORTCR(100, 0xe6052064), /* PORT100CR */ + PORTCR(101, 0xe6052065), /* PORT101CR */ + PORTCR(102, 0xe6052066), /* PORT102CR */ + PORTCR(103, 0xe6052067), /* PORT103CR */ + PORTCR(104, 0xe6052068), /* PORT104CR */ + PORTCR(105, 0xe6052069), /* PORT105CR */ + PORTCR(106, 0xe605206a), /* PORT106CR */ + PORTCR(107, 0xe605206b), /* PORT107CR */ + PORTCR(108, 0xe605206c), /* PORT108CR */ + PORTCR(109, 0xe605206d), /* PORT109CR */ + + PORTCR(110, 0xe605206e), /* PORT110CR */ + PORTCR(111, 0xe605206f), /* PORT111CR */ + PORTCR(112, 0xe6052070), /* PORT112CR */ + PORTCR(113, 0xe6052071), /* PORT113CR */ + PORTCR(114, 0xe6052072), /* PORT114CR */ + PORTCR(115, 0xe6052073), /* PORT115CR */ + PORTCR(116, 0xe6052074), /* PORT116CR */ + PORTCR(117, 0xe6052075), /* PORT117CR */ + PORTCR(118, 0xe6052076), /* PORT118CR */ + + PORTCR(128, 0xe6052080), /* PORT128CR */ + PORTCR(129, 0xe6052081), /* PORT129CR */ + + PORTCR(130, 0xe6052082), /* PORT130CR */ + PORTCR(131, 0xe6052083), /* PORT131CR */ + PORTCR(132, 0xe6052084), /* PORT132CR */ + PORTCR(133, 0xe6052085), /* PORT133CR */ + PORTCR(134, 0xe6052086), /* PORT134CR */ + PORTCR(135, 0xe6052087), /* PORT135CR */ + PORTCR(136, 0xe6052088), /* PORT136CR */ + PORTCR(137, 0xe6052089), /* PORT137CR */ + PORTCR(138, 0xe605208a), /* PORT138CR */ + PORTCR(139, 0xe605208b), /* PORT139CR */ + + PORTCR(140, 0xe605208c), /* PORT140CR */ + PORTCR(141, 0xe605208d), /* PORT141CR */ + PORTCR(142, 0xe605208e), /* PORT142CR */ + PORTCR(143, 0xe605208f), /* PORT143CR */ + PORTCR(144, 0xe6052090), /* PORT144CR */ + PORTCR(145, 0xe6052091), /* PORT145CR */ + PORTCR(146, 0xe6052092), /* PORT146CR */ + PORTCR(147, 0xe6052093), /* PORT147CR */ + PORTCR(148, 0xe6052094), /* PORT148CR */ + PORTCR(149, 0xe6052095), /* PORT149CR */ + + PORTCR(150, 0xe6052096), /* PORT150CR */ + PORTCR(151, 0xe6052097), /* PORT151CR */ + PORTCR(152, 0xe6052098), /* PORT152CR */ + PORTCR(153, 0xe6052099), /* PORT153CR */ + PORTCR(154, 0xe605209a), /* PORT154CR */ + PORTCR(155, 0xe605209b), /* PORT155CR */ + PORTCR(156, 0xe605209c), /* PORT156CR */ + PORTCR(157, 0xe605209d), /* PORT157CR */ + PORTCR(158, 0xe605209e), /* PORT158CR */ + PORTCR(159, 0xe605209f), /* PORT159CR */ + + PORTCR(160, 0xe60520a0), /* PORT160CR */ + PORTCR(161, 0xe60520a1), /* PORT161CR */ + PORTCR(162, 0xe60520a2), /* PORT162CR */ + PORTCR(163, 0xe60520a3), /* PORT163CR */ + PORTCR(164, 0xe60520a4), /* PORT164CR */ + + PORTCR(192, 0xe60520c0), /* PORT192CR */ + PORTCR(193, 0xe60520c1), /* PORT193CR */ + PORTCR(194, 0xe60520c2), /* PORT194CR */ + PORTCR(195, 0xe60520c3), /* PORT195CR */ + PORTCR(196, 0xe60520c4), /* PORT196CR */ + PORTCR(197, 0xe60520c5), /* PORT197CR */ + PORTCR(198, 0xe60520c6), /* PORT198CR */ + PORTCR(199, 0xe60520c7), /* PORT199CR */ + + PORTCR(200, 0xe60520c8), /* PORT200CR */ + PORTCR(201, 0xe60520c9), /* PORT201CR */ + PORTCR(202, 0xe60520ca), /* PORT202CR */ + PORTCR(203, 0xe60520cb), /* PORT203CR */ + PORTCR(204, 0xe60520cc), /* PORT204CR */ + PORTCR(205, 0xe60520cd), /* PORT205CR */ + PORTCR(206, 0xe60520ce), /* PORT206CR */ + PORTCR(207, 0xe60520cf), /* PORT207CR */ + PORTCR(208, 0xe60520d0), /* PORT208CR */ + PORTCR(209, 0xe60520d1), /* PORT209CR */ + + PORTCR(210, 0xe60520d2), /* PORT210CR */ + PORTCR(211, 0xe60520d3), /* PORT211CR */ + PORTCR(212, 0xe60520d4), /* PORT212CR */ + PORTCR(213, 0xe60520d5), /* PORT213CR */ + PORTCR(214, 0xe60520d6), /* PORT214CR */ + PORTCR(215, 0xe60520d7), /* PORT215CR */ + PORTCR(216, 0xe60520d8), /* PORT216CR */ + PORTCR(217, 0xe60520d9), /* PORT217CR */ + PORTCR(218, 0xe60520da), /* PORT218CR */ + PORTCR(219, 0xe60520db), /* PORT219CR */ + + PORTCR(220, 0xe60520dc), /* PORT220CR */ + PORTCR(221, 0xe60520dd), /* PORT221CR */ + PORTCR(222, 0xe60520de), /* PORT222CR */ + PORTCR(223, 0xe60520df), /* PORT223CR */ + PORTCR(224, 0xe60530e0), /* PORT224CR */ + PORTCR(225, 0xe60530e1), /* PORT225CR */ + PORTCR(226, 0xe60530e2), /* PORT226CR */ + PORTCR(227, 0xe60530e3), /* PORT227CR */ + PORTCR(228, 0xe60530e4), /* PORT228CR */ + PORTCR(229, 0xe60530e5), /* PORT229CR */ + + PORTCR(230, 0xe60530e6), /* PORT230CR */ + PORTCR(231, 0xe60530e7), /* PORT231CR */ + PORTCR(232, 0xe60530e8), /* PORT232CR */ + PORTCR(233, 0xe60530e9), /* PORT233CR */ + PORTCR(234, 0xe60530ea), /* PORT234CR */ + PORTCR(235, 0xe60530eb), /* PORT235CR */ + PORTCR(236, 0xe60530ec), /* PORT236CR */ + PORTCR(237, 0xe60530ed), /* PORT237CR */ + PORTCR(238, 0xe60530ee), /* PORT238CR */ + PORTCR(239, 0xe60530ef), /* PORT239CR */ + + PORTCR(240, 0xe60530f0), /* PORT240CR */ + PORTCR(241, 0xe60530f1), /* PORT241CR */ + PORTCR(242, 0xe60530f2), /* PORT242CR */ + PORTCR(243, 0xe60530f3), /* PORT243CR */ + PORTCR(244, 0xe60530f4), /* PORT244CR */ + PORTCR(245, 0xe60530f5), /* PORT245CR */ + PORTCR(246, 0xe60530f6), /* PORT246CR */ + PORTCR(247, 0xe60530f7), /* PORT247CR */ + PORTCR(248, 0xe60530f8), /* PORT248CR */ + PORTCR(249, 0xe60530f9), /* PORT249CR */ + + PORTCR(250, 0xe60530fa), /* PORT250CR */ + PORTCR(251, 0xe60530fb), /* PORT251CR */ + PORTCR(252, 0xe60530fc), /* PORT252CR */ + PORTCR(253, 0xe60530fd), /* PORT253CR */ + PORTCR(254, 0xe60530fe), /* PORT254CR */ + PORTCR(255, 0xe60530ff), /* PORT255CR */ + PORTCR(256, 0xe6053100), /* PORT256CR */ + PORTCR(257, 0xe6053101), /* PORT257CR */ + PORTCR(258, 0xe6053102), /* PORT258CR */ + PORTCR(259, 0xe6053103), /* PORT259CR */ + + PORTCR(260, 0xe6053104), /* PORT260CR */ + PORTCR(261, 0xe6053105), /* PORT261CR */ + PORTCR(262, 0xe6053106), /* PORT262CR */ + PORTCR(263, 0xe6053107), /* PORT263CR */ + PORTCR(264, 0xe6053108), /* PORT264CR */ + PORTCR(265, 0xe6053109), /* PORT265CR */ + PORTCR(266, 0xe605310a), /* PORT266CR */ + PORTCR(267, 0xe605310b), /* PORT267CR */ + PORTCR(268, 0xe605310c), /* PORT268CR */ + PORTCR(269, 0xe605310d), /* PORT269CR */ + + PORTCR(270, 0xe605310e), /* PORT270CR */ + PORTCR(271, 0xe605310f), /* PORT271CR */ + PORTCR(272, 0xe6053110), /* PORT272CR */ + PORTCR(273, 0xe6053111), /* PORT273CR */ + PORTCR(274, 0xe6053112), /* PORT274CR */ + PORTCR(275, 0xe6053113), /* PORT275CR */ + PORTCR(276, 0xe6053114), /* PORT276CR */ + PORTCR(277, 0xe6053115), /* PORT277CR */ + PORTCR(278, 0xe6053116), /* PORT278CR */ + PORTCR(279, 0xe6053117), /* PORT279CR */ + + PORTCR(280, 0xe6053118), /* PORT280CR */ + PORTCR(281, 0xe6053119), /* PORT281CR */ + PORTCR(282, 0xe605311a), /* PORT282CR */ + + PORTCR(288, 0xe6052120), /* PORT288CR */ + PORTCR(289, 0xe6052121), /* PORT289CR */ + + PORTCR(290, 0xe6052122), /* PORT290CR */ + PORTCR(291, 0xe6052123), /* PORT291CR */ + PORTCR(292, 0xe6052124), /* PORT292CR */ + PORTCR(293, 0xe6052125), /* PORT293CR */ + PORTCR(294, 0xe6052126), /* PORT294CR */ + PORTCR(295, 0xe6052127), /* PORT295CR */ + PORTCR(296, 0xe6052128), /* PORT296CR */ + PORTCR(297, 0xe6052129), /* PORT297CR */ + PORTCR(298, 0xe605212a), /* PORT298CR */ + PORTCR(299, 0xe605212b), /* PORT299CR */ + + PORTCR(300, 0xe605212c), /* PORT300CR */ + PORTCR(301, 0xe605212d), /* PORT301CR */ + PORTCR(302, 0xe605212e), /* PORT302CR */ + PORTCR(303, 0xe605212f), /* PORT303CR */ + PORTCR(304, 0xe6052130), /* PORT304CR */ + PORTCR(305, 0xe6052131), /* PORT305CR */ + PORTCR(306, 0xe6052132), /* PORT306CR */ + PORTCR(307, 0xe6052133), /* PORT307CR */ + PORTCR(308, 0xe6052134), /* PORT308CR */ + PORTCR(309, 0xe6052135), /* PORT309CR */ + + { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1, + MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1, + MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1, + MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1, + 0, 0, + MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1, + MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1, + MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1, + MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1, + MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1, + MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1, + MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1, + MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1, + MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1, + MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1, + MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1, + MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1, + MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1, + MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1, + MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1, + } + }, + { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1, + 0, 0, + 0, 0, + 0, 0, + MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1, + 0, 0, + MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1, + 0, 0, + 0, 0, + MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1, + 0, 0, + 0, 0, + 0, 0, + MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1, + 0, 0, + 0, 0, + } + }, + { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) { + 0, 0, + 0, 0, + MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1, + 0, 0, + MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1, + 0, 0, + 0, 0, + 0, 0, + MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1, + MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1, + MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1, + MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1, + 0, 0, + 0, 0, + 0, 0, + MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1, + 0, 0, + MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1, + MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1, + MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1, + MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1, + MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1, + MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1, + MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1, + 0, 0, + 0, 0, + MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1, + 0, 0, + 0, 0, + MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1, + 0, 0, + } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { + PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, + PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, + PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, + PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, + PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, + PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, + PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, + PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA } + }, + { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) { + PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, + PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, + PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, + PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA, + PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA, + PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, + PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, + PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA } + }, + { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) { + PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, + PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, + PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, + PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, + PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, + PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, + PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, + PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA } + }, + { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, PORT118_DATA, PORT117_DATA, PORT116_DATA, + PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA, + PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, + PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, + PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, + PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA } + }, + { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) { + PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, + PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, + PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, + PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA, + PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, + PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, + PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, + PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA } + }, + { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, PORT164_DATA, + PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA } + }, + { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) { + PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA, + PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA, + PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA, + PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA, + PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, + PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, + PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, + PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA } + }, + { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) { + PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA, + PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA, + PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA, + PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA, + PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA, + PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA, + PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA, + PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA } + }, + { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) { + 0, 0, 0, 0, + 0, PORT282_DATA, PORT281_DATA, PORT280_DATA, + PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA, + PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA, + PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA, + PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA, + PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA, + PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA } + }, + { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, PORT309_DATA, PORT308_DATA, + PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA, + PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA, + PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA, + PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA, + PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA } + }, + { }, +}; + +static struct pinmux_info sh73a0_pinmux_info = { + .name = "sh73a0_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_PORT0, + .last_gpio = GPIO_FN_FSIAISLD_PU, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void sh73a0_pinmux_init(void) +{ + register_pinmux(&sh73a0_pinmux_info); +} diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c new file mode 100644 index 00000000000..65e879bab4d --- /dev/null +++ b/arch/arm/mach-shmobile/platsmp.c @@ -0,0 +1,70 @@ +/* + * SMP support for R-Mobile / SH-Mobile + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2011 Paul Mundt + * + * Based on vexpress, Copyright (C) 2002 ARM Ltd, All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/errno.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/smp.h> +#include <linux/io.h> +#include <asm/localtimer.h> +#include <asm/mach-types.h> +#include <mach/common.h> + +static unsigned int __init shmobile_smp_get_core_count(void) +{ + if (machine_is_ag5evm()) + return sh73a0_get_core_count(); + + return 1; +} + +static void __init shmobile_smp_prepare_cpus(void) +{ + if (machine_is_ag5evm()) + sh73a0_smp_prepare_cpus(); +} + +void __cpuinit platform_secondary_init(unsigned int cpu) +{ + trace_hardirqs_off(); + + if (machine_is_ag5evm()) + sh73a0_secondary_init(cpu); +} + +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + if (machine_is_ag5evm()) + return sh73a0_boot_secondary(cpu); + + return -ENOSYS; +} + +void __init smp_init_cpus(void) +{ + unsigned int ncores = shmobile_smp_get_core_count(); + unsigned int i; + + for (i = 0; i < ncores; i++) + set_cpu_possible(i, true); +} + +void __init platform_smp_prepare_cpus(unsigned int max_cpus) +{ + int i; + + for (i = 0; i < max_cpus; i++) + set_cpu_present(i, true); + + shmobile_smp_prepare_cpus(); +} diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 564a6d0be47..2e3e11ee7c4 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -416,6 +416,16 @@ static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = { .addr = 0xe6870030, .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), .mid_rid = 0xce, + }, { + .slave_id = SHDMA_SLAVE_MMCIF_TX, + .addr = 0xe6bd0034, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0xd1, + }, { + .slave_id = SHDMA_SLAVE_MMCIF_RX, + .addr = 0xe6bd0034, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0xd2, }, }; diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c new file mode 100644 index 00000000000..f1eff8b37bd --- /dev/null +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -0,0 +1,412 @@ +/* + * sh73a0 processor support + * + * Copyright (C) 2010 Takashi Yoshii + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/input.h> +#include <linux/io.h> +#include <linux/serial_sci.h> +#include <linux/sh_intc.h> +#include <linux/sh_timer.h> +#include <mach/hardware.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +static struct plat_sci_port scif0_platform_data = { + .mapbase = 0xe6c40000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIFA, + .irqs = { gic_spi(72), gic_spi(72), + gic_spi(72), gic_spi(72) }, +}; + +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .dev = { + .platform_data = &scif0_platform_data, + }, +}; + +static struct plat_sci_port scif1_platform_data = { + .mapbase = 0xe6c50000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIFA, + .irqs = { gic_spi(73), gic_spi(73), + gic_spi(73), gic_spi(73) }, +}; + +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .dev = { + .platform_data = &scif1_platform_data, + }, +}; + +static struct plat_sci_port scif2_platform_data = { + .mapbase = 0xe6c60000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIFA, + .irqs = { gic_spi(74), gic_spi(74), + gic_spi(74), gic_spi(74) }, +}; + +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 2, + .dev = { + .platform_data = &scif2_platform_data, + }, +}; + +static struct plat_sci_port scif3_platform_data = { + .mapbase = 0xe6c70000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIFA, + .irqs = { gic_spi(75), gic_spi(75), + gic_spi(75), gic_spi(75) }, +}; + +static struct platform_device scif3_device = { + .name = "sh-sci", + .id = 3, + .dev = { + .platform_data = &scif3_platform_data, + }, +}; + +static struct plat_sci_port scif4_platform_data = { + .mapbase = 0xe6c80000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIFA, + .irqs = { gic_spi(78), gic_spi(78), + gic_spi(78), gic_spi(78) }, +}; + +static struct platform_device scif4_device = { + .name = "sh-sci", + .id = 4, + .dev = { + .platform_data = &scif4_platform_data, + }, +}; + +static struct plat_sci_port scif5_platform_data = { + .mapbase = 0xe6cb0000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIFA, + .irqs = { gic_spi(79), gic_spi(79), + gic_spi(79), gic_spi(79) }, +}; + +static struct platform_device scif5_device = { + .name = "sh-sci", + .id = 5, + .dev = { + .platform_data = &scif5_platform_data, + }, +}; + +static struct plat_sci_port scif6_platform_data = { + .mapbase = 0xe6cc0000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIFA, + .irqs = { gic_spi(156), gic_spi(156), + gic_spi(156), gic_spi(156) }, +}; + +static struct platform_device scif6_device = { + .name = "sh-sci", + .id = 6, + .dev = { + .platform_data = &scif6_platform_data, + }, +}; + +static struct plat_sci_port scif7_platform_data = { + .mapbase = 0xe6cd0000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIFA, + .irqs = { gic_spi(143), gic_spi(143), + gic_spi(143), gic_spi(143) }, +}; + +static struct platform_device scif7_device = { + .name = "sh-sci", + .id = 7, + .dev = { + .platform_data = &scif7_platform_data, + }, +}; + +static struct plat_sci_port scif8_platform_data = { + .mapbase = 0xe6c30000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIFB, + .irqs = { gic_spi(80), gic_spi(80), + gic_spi(80), gic_spi(80) }, +}; + +static struct platform_device scif8_device = { + .name = "sh-sci", + .id = 8, + .dev = { + .platform_data = &scif8_platform_data, + }, +}; + +static struct sh_timer_config cmt10_platform_data = { + .name = "CMT10", + .channel_offset = 0x10, + .timer_bit = 0, + .clockevent_rating = 125, + .clocksource_rating = 125, +}; + +static struct resource cmt10_resources[] = { + [0] = { + .name = "CMT10", + .start = 0xe6138010, + .end = 0xe613801b, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(65), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cmt10_device = { + .name = "sh_cmt", + .id = 10, + .dev = { + .platform_data = &cmt10_platform_data, + }, + .resource = cmt10_resources, + .num_resources = ARRAY_SIZE(cmt10_resources), +}; + +/* TMU */ +static struct sh_timer_config tmu00_platform_data = { + .name = "TMU00", + .channel_offset = 0x4, + .timer_bit = 0, + .clockevent_rating = 200, +}; + +static struct resource tmu00_resources[] = { + [0] = { + .name = "TMU00", + .start = 0xfff60008, + .end = 0xfff60013, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tmu00_device = { + .name = "sh_tmu", + .id = 0, + .dev = { + .platform_data = &tmu00_platform_data, + }, + .resource = tmu00_resources, + .num_resources = ARRAY_SIZE(tmu00_resources), +}; + +static struct sh_timer_config tmu01_platform_data = { + .name = "TMU01", + .channel_offset = 0x10, + .timer_bit = 1, + .clocksource_rating = 200, +}; + +static struct resource tmu01_resources[] = { + [0] = { + .name = "TMU01", + .start = 0xfff60014, + .end = 0xfff6001f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tmu01_device = { + .name = "sh_tmu", + .id = 1, + .dev = { + .platform_data = &tmu01_platform_data, + }, + .resource = tmu01_resources, + .num_resources = ARRAY_SIZE(tmu01_resources), +}; + +static struct resource i2c0_resources[] = { + [0] = { + .name = "IIC0", + .start = 0xe6820000, + .end = 0xe6820425 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(167), + .end = gic_spi(170), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource i2c1_resources[] = { + [0] = { + .name = "IIC1", + .start = 0xe6822000, + .end = 0xe6822425 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(51), + .end = gic_spi(54), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource i2c2_resources[] = { + [0] = { + .name = "IIC2", + .start = 0xe6824000, + .end = 0xe6824425 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(171), + .end = gic_spi(174), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource i2c3_resources[] = { + [0] = { + .name = "IIC3", + .start = 0xe6826000, + .end = 0xe6826425 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(183), + .end = gic_spi(186), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource i2c4_resources[] = { + [0] = { + .name = "IIC4", + .start = 0xe6828000, + .end = 0xe6828425 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(187), + .end = gic_spi(190), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device i2c0_device = { + .name = "i2c-sh_mobile", + .id = 0, + .resource = i2c0_resources, + .num_resources = ARRAY_SIZE(i2c0_resources), +}; + +static struct platform_device i2c1_device = { + .name = "i2c-sh_mobile", + .id = 1, + .resource = i2c1_resources, + .num_resources = ARRAY_SIZE(i2c1_resources), +}; + +static struct platform_device i2c2_device = { + .name = "i2c-sh_mobile", + .id = 2, + .resource = i2c2_resources, + .num_resources = ARRAY_SIZE(i2c2_resources), +}; + +static struct platform_device i2c3_device = { + .name = "i2c-sh_mobile", + .id = 3, + .resource = i2c3_resources, + .num_resources = ARRAY_SIZE(i2c3_resources), +}; + +static struct platform_device i2c4_device = { + .name = "i2c-sh_mobile", + .id = 4, + .resource = i2c4_resources, + .num_resources = ARRAY_SIZE(i2c4_resources), +}; + +static struct platform_device *sh73a0_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, + &scif6_device, + &scif7_device, + &scif8_device, + &cmt10_device, + &tmu00_device, + &tmu01_device, +}; + +static struct platform_device *sh73a0_late_devices[] __initdata = { + &i2c0_device, + &i2c1_device, + &i2c2_device, + &i2c3_device, + &i2c4_device, +}; + +void __init sh73a0_add_standard_devices(void) +{ + platform_add_devices(sh73a0_early_devices, + ARRAY_SIZE(sh73a0_early_devices)); + platform_add_devices(sh73a0_late_devices, + ARRAY_SIZE(sh73a0_late_devices)); +} + +void __init sh73a0_add_early_devices(void) +{ + early_platform_add_devices(sh73a0_early_devices, + ARRAY_SIZE(sh73a0_early_devices)); +} diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c new file mode 100644 index 00000000000..a156d2108df --- /dev/null +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -0,0 +1,97 @@ +/* + * SMP support for R-Mobile / SH-Mobile - sh73a0 portion + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2010 Takashi Yoshii + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/smp.h> +#include <linux/spinlock.h> +#include <linux/io.h> +#include <mach/common.h> +#include <asm/smp_scu.h> +#include <asm/smp_twd.h> +#include <asm/hardware/gic.h> + +#define WUPCR 0xe6151010 +#define SRESCR 0xe6151018 +#define PSTR 0xe6151040 +#define SBAR 0xe6180020 +#define APARMBAREA 0xe6f10020 + +static void __iomem *scu_base_addr(void) +{ + return (void __iomem *)0xf0000000; +} + +static DEFINE_SPINLOCK(scu_lock); +static unsigned long tmp; + +static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) +{ + void __iomem *scu_base = scu_base_addr(); + + spin_lock(&scu_lock); + tmp = __raw_readl(scu_base + 8); + tmp &= ~clr; + tmp |= set; + spin_unlock(&scu_lock); + + /* disable cache coherency after releasing the lock */ + __raw_writel(tmp, scu_base + 8); +} + +unsigned int __init sh73a0_get_core_count(void) +{ + void __iomem *scu_base = scu_base_addr(); + + return scu_get_core_count(scu_base); +} + +void __cpuinit sh73a0_secondary_init(unsigned int cpu) +{ + gic_secondary_init(0); +} + +int __cpuinit sh73a0_boot_secondary(unsigned int cpu) +{ + /* enable cache coherency */ + modify_scu_cpu_psr(0, 3 << (cpu * 8)); + + if (((__raw_readw(__io(PSTR)) >> (4 * cpu)) & 3) == 3) + __raw_writel(1 << cpu, __io(WUPCR)); /* wake up */ + else + __raw_writel(1 << cpu, __io(SRESCR)); /* reset */ + + return 0; +} + +void __init sh73a0_smp_prepare_cpus(void) +{ +#ifdef CONFIG_HAVE_ARM_TWD + twd_base = (void __iomem *)0xf0000600; +#endif + + scu_enable(scu_base_addr()); + + /* Map the reset vector (in headsmp.S) */ + __raw_writel(0, __io(APARMBAREA)); /* 4k */ + __raw_writel(__pa(shmobile_secondary_vector), __io(SBAR)); + + /* enable cache coherency on CPU0 */ + modify_scu_cpu_psr(0, 3 << (0 * 8)); +} diff --git a/arch/arm/mach-tegra/include/mach/sdhci.h b/arch/arm/mach-tegra/include/mach/sdhci.h new file mode 100644 index 00000000000..3ad086e859c --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/sdhci.h @@ -0,0 +1,29 @@ +/* + * include/asm-arm/arch-tegra/include/mach/sdhci.h + * + * Copyright (C) 2009 Palm, Inc. + * Author: Yvonne Yip <y@palm.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef __ASM_ARM_ARCH_TEGRA_SDHCI_H +#define __ASM_ARM_ARCH_TEGRA_SDHCI_H + +#include <linux/mmc/host.h> + +struct tegra_sdhci_platform_data { + int cd_gpio; + int wp_gpio; + int power_gpio; + int is_8bit; +}; + +#endif diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 2dd44a0b461..247caa3400d 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -7,28 +7,30 @@ config UX500_SOC_COMMON select HAS_MTU select NOMADIK_GPIO -config UX500_SOC_DB8500 - bool +menu "Ux500 SoC" config UX500_SOC_DB5500 - bool + bool "DB5500" + +config UX500_SOC_DB8500 + bool "DB8500" + +endmenu -choice - prompt "Ux500 target platform" - default MACH_U8500_MOP +menu "Ux500 target platform" -config MACH_U8500_MOP +config MACH_U8500 bool "U8500 Development platform" - select UX500_SOC_DB8500 + depends on UX500_SOC_DB8500 help Include support for the mop500 development platform. config MACH_U5500 bool "U5500 Development platform" - select UX500_SOC_DB5500 + depends on UX500_SOC_DB5500 help Include support for the U5500 development platform. -endchoice +endmenu config UX500_DEBUG_UART int "Ux500 UART to use for low-level debug" @@ -39,14 +41,14 @@ config UX500_DEBUG_UART config U5500_MODEM_IRQ bool "Modem IRQ support" - depends on MACH_U5500 + depends on UX500_SOC_DB5500 default y help Add support for handling IRQ:s from modem side config U5500_MBOX bool "Mailbox support" - depends on MACH_U5500 && U5500_MODEM_IRQ + depends on U5500_MODEM_IRQ default y help Add support for U5500 mailbox communication with modem side diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 12052e8e064..53ebb429e97 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -2,10 +2,11 @@ # Makefile for the linux kernel, U8500 machine. # -obj-y := clock.o cpu.o devices.o devices-common.o +obj-y := clock.o cpu.o devices.o devices-common.o \ + id.o obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o prcmu.o -obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o board-mop500-sdi.o \ +obj-$(CONFIG_MACH_U8500) += board-mop500.o board-mop500-sdi.o \ board-mop500-keypads.o obj-$(CONFIG_MACH_U5500) += board-u5500.o board-u5500-sdi.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c index ccff2dae167..b2b0a3b9be8 100644 --- a/arch/arm/mach-ux500/clock.c +++ b/arch/arm/mach-ux500/clock.c @@ -136,8 +136,7 @@ EXPORT_SYMBOL(clk_disable); */ static unsigned long clk_mtu_get_rate(struct clk *clk) { - void __iomem *addr = __io_address(UX500_PRCMU_BASE) - + PRCM_TCR; + void __iomem *addr; u32 tcr; int mtu = (int) clk->data; /* @@ -149,13 +148,20 @@ static unsigned long clk_mtu_get_rate(struct clk *clk) unsigned long mturate; unsigned long retclk; + if (cpu_is_u5500()) + addr = __io_address(U5500_PRCMU_BASE); + else if (cpu_is_u8500()) + addr = __io_address(U8500_PRCMU_BASE); + else + ux500_unknown_soc(); + /* * On a startup, always conifgure the TCR to the doze mode; * bootloaders do it for us. Do this in the kernel too. */ - writel(PRCM_TCR_DOZE_MODE, addr); + writel(PRCM_TCR_DOZE_MODE, addr + PRCM_TCR); - tcr = readl(addr); + tcr = readl(addr + PRCM_TCR); /* Get the rate from the parent as a default */ if (clk->parent_periph) diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c index acc841e48de..af04e0891a7 100644 --- a/arch/arm/mach-ux500/cpu-db5500.c +++ b/arch/arm/mach-ux500/cpu-db5500.c @@ -21,7 +21,20 @@ #include "devices-db5500.h" +static struct map_desc u5500_uart_io_desc[] __initdata = { + __IO_DEV_DESC(U5500_UART0_BASE, SZ_4K), + __IO_DEV_DESC(U5500_UART2_BASE, SZ_4K), +}; + static struct map_desc u5500_io_desc[] __initdata = { + __IO_DEV_DESC(U5500_GIC_CPU_BASE, SZ_4K), + __IO_DEV_DESC(U5500_GIC_DIST_BASE, SZ_4K), + __IO_DEV_DESC(U5500_L2CC_BASE, SZ_4K), + __IO_DEV_DESC(U5500_TWD_BASE, SZ_4K), + __IO_DEV_DESC(U5500_MTU0_BASE, SZ_4K), + __IO_DEV_DESC(U5500_SCU_BASE, SZ_4K), + __IO_DEV_DESC(U5500_BACKUPRAM0_BASE, SZ_8K), + __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K), __IO_DEV_DESC(U5500_GPIO1_BASE, SZ_4K), __IO_DEV_DESC(U5500_GPIO2_BASE, SZ_4K), @@ -143,6 +156,11 @@ static void __init db5500_add_gpios(void) void __init u5500_map_io(void) { + /* + * Map the UARTs early so that the DEBUG_LL stuff continues to work. + */ + iotable_init(u5500_uart_io_desc, ARRAY_SIZE(u5500_uart_io_desc)); + ux500_map_io(); iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc)); diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index c0f34a404c5..1748fbc5853 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -29,13 +29,31 @@ static struct platform_device *platform_devs[] __initdata = { }; /* minimum static i/o mapping required to boot U8500 platforms */ +static struct map_desc u8500_uart_io_desc[] __initdata = { + __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K), + __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K), +}; + static struct map_desc u8500_io_desc[] __initdata = { + __IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K), + __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K), + __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K), + __IO_DEV_DESC(U8500_TWD_BASE, SZ_4K), + __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), + __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K), + __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K), + + __IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K), + __IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K), + __IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K), + __IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K), + __IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K), + __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K), __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K), __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), - __MEM_DEV_DESC(U8500_BOOT_ROM_BASE, SZ_1M), }; static struct map_desc u8500_ed_io_desc[] __initdata = { @@ -52,71 +70,13 @@ static struct map_desc u8500_v2_io_desc[] __initdata = { __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), }; -/* - * Functions to differentiate between later ASICs - * We look into the end of the ROM to locate the hardcoded ASIC ID. - * This is only needed to differentiate between minor revisions and - * process variants of an ASIC, the major revisions are encoded in - * the cpuid. - */ -#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOT_ROM_BASE + 0x1FFF4) -#define U8500_ASIC_ID_LOC_V2 (U8500_BOOT_ROM_BASE + 0x1DBF4) -#define U8500_ASIC_REV_ED 0x01 -#define U8500_ASIC_REV_V10 0xA0 -#define U8500_ASIC_REV_V11 0xA1 -#define U8500_ASIC_REV_V20 0xB0 - -/** - * struct db8500_asic_id - fields of the ASIC ID - * @process: the manufacturing process, 0x40 is 40 nm - * 0x00 is "standard" - * @partnumber: hithereto 0x8500 for DB8500 - * @revision: version code in the series - * This field definion is not formally defined but makes - * sense. - */ -struct db8500_asic_id { - u8 process; - u16 partnumber; - u8 revision; -}; - -/* This isn't going to change at runtime */ -static struct db8500_asic_id db8500_id; - -static void __init get_db8500_asic_id(void) -{ - u32 asicid; - - if (cpu_is_u8500v1() || cpu_is_u8500ed()) - asicid = readl(__io_address(U8500_ASIC_ID_LOC_ED_V1)); - else if (cpu_is_u8500v2()) - asicid = readl(__io_address(U8500_ASIC_ID_LOC_V2)); - else - BUG(); - - db8500_id.process = (asicid >> 24); - db8500_id.partnumber = (asicid >> 16) & 0xFFFFU; - db8500_id.revision = asicid & 0xFFU; -} - -bool cpu_is_u8500v10(void) -{ - return (db8500_id.revision == U8500_ASIC_REV_V10); -} - -bool cpu_is_u8500v11(void) -{ - return (db8500_id.revision == U8500_ASIC_REV_V11); -} - -bool cpu_is_u8500v20(void) -{ - return (db8500_id.revision == U8500_ASIC_REV_V20); -} - void __init u8500_map_io(void) { + /* + * Map the UARTs early so that the DEBUG_LL stuff continues to work. + */ + iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc)); + ux500_map_io(); iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); @@ -127,9 +87,6 @@ void __init u8500_map_io(void) iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc)); else if (cpu_is_u8500v2()) iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc)); - - /* Read out the ASIC ID as early as we can */ - get_db8500_asic_id(); } static resource_size_t __initdata db8500_gpio_base[] = { @@ -159,20 +116,6 @@ static void __init db8500_add_gpios(void) */ void __init u8500_init_devices(void) { - /* Display some ASIC boilerplate */ - pr_info("DB8500: process: %02x, revision ID: 0x%02x\n", - db8500_id.process, db8500_id.revision); - if (cpu_is_u8500ed()) - pr_info("DB8500: Early Drop (ED)\n"); - else if (cpu_is_u8500v10()) - pr_info("DB8500: version 1.0\n"); - else if (cpu_is_u8500v11()) - pr_info("DB8500: version 1.1\n"); - else if (cpu_is_u8500v20()) - pr_info("DB8500: version 2.0\n"); - else - pr_warning("ASIC: UNKNOWN SILICON VERSION!\n"); - if (cpu_is_u8500ed()) dma40_u8500ed_fixup(); diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index 5730409c0f7..5a43107c623 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -23,37 +23,25 @@ #include "clock.h" -static struct map_desc ux500_io_desc[] __initdata = { - __IO_DEV_DESC(UX500_UART0_BASE, SZ_4K), - __IO_DEV_DESC(UX500_UART2_BASE, SZ_4K), - - __IO_DEV_DESC(UX500_GIC_CPU_BASE, SZ_4K), - __IO_DEV_DESC(UX500_GIC_DIST_BASE, SZ_4K), - __IO_DEV_DESC(UX500_L2CC_BASE, SZ_4K), - __IO_DEV_DESC(UX500_TWD_BASE, SZ_4K), - __IO_DEV_DESC(UX500_SCU_BASE, SZ_4K), - - __IO_DEV_DESC(UX500_CLKRST1_BASE, SZ_4K), - __IO_DEV_DESC(UX500_CLKRST2_BASE, SZ_4K), - __IO_DEV_DESC(UX500_CLKRST3_BASE, SZ_4K), - __IO_DEV_DESC(UX500_CLKRST5_BASE, SZ_4K), - __IO_DEV_DESC(UX500_CLKRST6_BASE, SZ_4K), - - __IO_DEV_DESC(UX500_MTU0_BASE, SZ_4K), - __IO_DEV_DESC(UX500_MTU1_BASE, SZ_4K), - - __IO_DEV_DESC(UX500_BACKUPRAM0_BASE, SZ_8K), -}; - -void __init ux500_map_io(void) -{ - iotable_init(ux500_io_desc, ARRAY_SIZE(ux500_io_desc)); -} +#ifdef CONFIG_CACHE_L2X0 +static void __iomem *l2x0_base; +#endif void __init ux500_init_irq(void) { - gic_init(0, 29, __io_address(UX500_GIC_DIST_BASE), - __io_address(UX500_GIC_CPU_BASE)); + void __iomem *dist_base; + void __iomem *cpu_base; + + if (cpu_is_u5500()) { + dist_base = __io_address(U5500_GIC_DIST_BASE); + cpu_base = __io_address(U5500_GIC_CPU_BASE); + } else if (cpu_is_u8500()) { + dist_base = __io_address(U8500_GIC_DIST_BASE); + cpu_base = __io_address(U8500_GIC_CPU_BASE); + } else + ux500_unknown_soc(); + + gic_init(0, 29, dist_base, cpu_base); /* * Init clocks here so that they are available for system timer @@ -74,7 +62,8 @@ static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask) static inline void ux500_cache_sync(void) { - void __iomem *base = __io_address(UX500_L2CC_BASE); + void __iomem *base = l2x0_base; + writel_relaxed(0, base + L2X0_CACHE_SYNC); ux500_cache_wait(base + L2X0_CACHE_SYNC, 1); } @@ -96,20 +85,23 @@ static void ux500_l2x0_disable(void) */ static void ux500_l2x0_inv_all(void) { - void __iomem *l2x0_base = __io_address(UX500_L2CC_BASE); + void __iomem *base = l2x0_base; uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */ /* invalidate all ways */ - writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); - ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask); + writel_relaxed(l2x0_way_mask, base + L2X0_INV_WAY); + ux500_cache_wait(base + L2X0_INV_WAY, l2x0_way_mask); ux500_cache_sync(); } static int ux500_l2x0_init(void) { - void __iomem *l2x0_base; - - l2x0_base = __io_address(UX500_L2CC_BASE); + if (cpu_is_u5500()) + l2x0_base = __io_address(U5500_L2CC_BASE); + else if (cpu_is_u8500()) + l2x0_base = __io_address(U8500_L2CC_BASE); + else + ux500_unknown_soc(); /* 64KB way size, 8 way associativity, force WA */ l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); @@ -127,13 +119,21 @@ static void __init ux500_timer_init(void) { #ifdef CONFIG_LOCAL_TIMERS /* Setup the local timer base */ - twd_base = __io_address(UX500_TWD_BASE); + if (cpu_is_u5500()) + twd_base = __io_address(U5500_TWD_BASE); + else if (cpu_is_u8500()) + twd_base = __io_address(U8500_TWD_BASE); + else + ux500_unknown_soc(); #endif - /* Setup the MTU base */ - if (cpu_is_u8500ed()) + if (cpu_is_u5500()) + mtu_base = __io_address(U5500_MTU0_BASE); + else if (cpu_is_u8500ed()) mtu_base = __io_address(U8500_MTU0_BASE_ED); + else if (cpu_is_u8500()) + mtu_base = __io_address(U8500_MTU0_BASE); else - mtu_base = __io_address(UX500_MTU0_BASE); + ux500_unknown_soc(); nmdk_timer_init(); } diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c new file mode 100644 index 00000000000..d35122ebc67 --- /dev/null +++ b/arch/arm/mach-ux500/id.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * License terms: GNU General Public License (GPL) version 2 + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> + +#include <asm/cputype.h> +#include <asm/tlbflush.h> +#include <asm/cacheflush.h> +#include <asm/mach/map.h> + +#include <mach/hardware.h> +#include <mach/setup.h> + +struct dbx500_asic_id dbx500_id; + +static unsigned int ux500_read_asicid(phys_addr_t addr) +{ + phys_addr_t base = addr & ~0xfff; + struct map_desc desc = { + .virtual = IO_ADDRESS(base), + .pfn = __phys_to_pfn(base), + .length = SZ_16K, + .type = MT_DEVICE, + }; + + iotable_init(&desc, 1); + + /* As in devicemaps_init() */ + local_flush_tlb_all(); + flush_cache_all(); + + return readl(__io_address(addr)); +} + +static void ux500_print_soc_info(unsigned int asicid) +{ + unsigned int rev = dbx500_revision(); + + pr_info("DB%4x ", dbx500_partnumber()); + + if (rev == 0x01) + pr_cont("Early Drop"); + else if (rev >= 0xA0) + pr_cont("v%d.%d" , (rev >> 4) - 0xA + 1, rev & 0xf); + else + pr_cont("Unknown"); + + pr_cont(" [%#010x]\n", asicid); +} + +static unsigned int partnumber(unsigned int asicid) +{ + return (asicid >> 8) & 0xffff; +} + +/* + * SOC MIDR ASICID ADDRESS ASICID VALUE + * DB8500ed 0x410fc090 0x9001FFF4 0x00850001 + * DB8500v1 0x411fc091 0x9001FFF4 0x008500A0 + * DB8500v1.1 0x411fc091 0x9001FFF4 0x008500A1 + * DB8500v2 0x412fc091 0x9001DBF4 0x008500B0 + * DB5500v1 0x412fc091 0x9001FFF4 0x005500A0 + */ + +void __init ux500_map_io(void) +{ + unsigned int cpuid = read_cpuid_id(); + unsigned int asicid = 0; + phys_addr_t addr = 0; + + switch (cpuid) { + case 0x410fc090: /* DB8500ed */ + case 0x411fc091: /* DB8500v1 */ + addr = 0x9001FFF4; + break; + + case 0x412fc091: /* DB8500v2 / DB5500v1 */ + asicid = ux500_read_asicid(0x9001DBF4); + if (partnumber(asicid) == 0x8500) + /* DB8500v2 */ + break; + + /* DB5500v1 */ + addr = 0x9001FFF4; + break; + } + + if (addr) + asicid = ux500_read_asicid(addr); + + if (!asicid) { + pr_err("Unable to identify SoC\n"); + ux500_unknown_soc(); + } + + dbx500_id.process = asicid >> 24; + dbx500_id.partnumber = partnumber(asicid); + dbx500_id.revision = asicid & 0xff; + + ux500_print_soc_info(asicid); +} diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S index be7c0f14e31..700fb05ee81 100644 --- a/arch/arm/mach-ux500/include/mach/debug-macro.S +++ b/arch/arm/mach-ux500/include/mach/debug-macro.S @@ -14,7 +14,24 @@ #error Invalid Ux500 debug UART #endif -#define __UX500_UART(n) UX500_UART##n##_BASE +/* + * DEBUG_LL only works if only one SOC is built in. We don't use #else below + * in order to get "__UX500_UART redefined" warnings if more than one SOC is + * built, so that there's some hint during the build that something is wrong. + */ + +#ifdef CONFIG_UX500_SOC_DB5500 +#define __UX500_UART(n) U5500_UART##n##_BASE +#endif + +#ifdef CONFIG_UX500_SOC_DB8500 +#define __UX500_UART(n) U8500_UART##n##_BASE +#endif + +#ifndef __UX500_UART +#error Unknown SOC +#endif + #define UX500_UART(n) __UX500_UART(n) #define UART_BASE UX500_UART(CONFIG_UX500_DEBUG_UART) diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S index a37f585a3ec..071bba94f72 100644 --- a/arch/arm/mach-ux500/include/mach/entry-macro.S +++ b/arch/arm/mach-ux500/include/mach/entry-macro.S @@ -11,15 +11,10 @@ * warranty of any kind, whether express or implied. */ #include <mach/hardware.h> -#define HAVE_GET_IRQNR_PREAMBLE #include <asm/hardware/entry-macro-gic.S> .macro disable_fiq .endm - .macro get_irqnr_preamble, base, tmp - ldr \base, =IO_ADDRESS(UX500_GIC_CPU_BASE) - .endm - .macro arch_ret_to_user, tmp1, tmp2 .endm diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h index 6295cc58135..bf63f2631ba 100644 --- a/arch/arm/mach-ux500/include/mach/hardware.h +++ b/arch/arm/mach-ux500/include/mach/hardware.h @@ -29,118 +29,12 @@ #include <mach/db8500-regs.h> #include <mach/db5500-regs.h> -#ifdef CONFIG_UX500_SOC_DB8500 -#define UX500(periph) U8500_##periph##_BASE -#elif defined(CONFIG_UX500_SOC_DB5500) -#define UX500(periph) U5500_##periph##_BASE -#endif - -#define UX500_BACKUPRAM0_BASE UX500(BACKUPRAM0) -#define UX500_BACKUPRAM1_BASE UX500(BACKUPRAM1) -#define UX500_B2R2_BASE UX500(B2R2) - -#define UX500_CLKRST1_BASE UX500(CLKRST1) -#define UX500_CLKRST2_BASE UX500(CLKRST2) -#define UX500_CLKRST3_BASE UX500(CLKRST3) -#define UX500_CLKRST5_BASE UX500(CLKRST5) -#define UX500_CLKRST6_BASE UX500(CLKRST6) - -#define UX500_DMA_BASE UX500(DMA) -#define UX500_FSMC_BASE UX500(FSMC) - -#define UX500_GIC_CPU_BASE UX500(GIC_CPU) -#define UX500_GIC_DIST_BASE UX500(GIC_DIST) - -#define UX500_I2C1_BASE UX500(I2C1) -#define UX500_I2C2_BASE UX500(I2C2) -#define UX500_I2C3_BASE UX500(I2C3) - -#define UX500_L2CC_BASE UX500(L2CC) -#define UX500_MCDE_BASE UX500(MCDE) -#define UX500_MTU0_BASE UX500(MTU0) -#define UX500_MTU1_BASE UX500(MTU1) -#define UX500_PRCMU_BASE UX500(PRCMU) - -#define UX500_RNG_BASE UX500(RNG) -#define UX500_RTC_BASE UX500(RTC) - -#define UX500_SCU_BASE UX500(SCU) - -#define UX500_SDI0_BASE UX500(SDI0) -#define UX500_SDI1_BASE UX500(SDI1) -#define UX500_SDI2_BASE UX500(SDI2) -#define UX500_SDI3_BASE UX500(SDI3) -#define UX500_SDI4_BASE UX500(SDI4) - -#define UX500_SPI0_BASE UX500(SPI0) -#define UX500_SPI1_BASE UX500(SPI1) -#define UX500_SPI2_BASE UX500(SPI2) -#define UX500_SPI3_BASE UX500(SPI3) - -#define UX500_SIA_BASE UX500(SIA) -#define UX500_SVA_BASE UX500(SVA) - -#define UX500_TWD_BASE UX500(TWD) - -#define UX500_UART0_BASE UX500(UART0) -#define UX500_UART1_BASE UX500(UART1) -#define UX500_UART2_BASE UX500(UART2) - -#define UX500_USBOTG_BASE UX500(USBOTG) - /* ST-Ericsson modified pl022 id */ #define SSP_PER_ID 0x01080022 #ifndef __ASSEMBLY__ -#include <asm/cputype.h> - -static inline bool cpu_is_u8500(void) -{ -#ifdef CONFIG_UX500_SOC_DB8500 - return 1; -#else - return 0; -#endif -} - -#define CPUID_DB8500ED 0x410fc090 -#define CPUID_DB8500V1 0x411fc091 -#define CPUID_DB8500V2 0x412fc091 - -static inline bool cpu_is_u8500ed(void) -{ - return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500ED); -} - -static inline bool cpu_is_u8500v1(void) -{ - return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500V1); -} - -static inline bool cpu_is_u8500v2(void) -{ - return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500V2); -} - -#ifdef CONFIG_UX500_SOC_DB8500 -bool cpu_is_u8500v10(void); -bool cpu_is_u8500v11(void); -bool cpu_is_u8500v20(void); -#else -static inline bool cpu_is_u8500v10(void) { return false; } -static inline bool cpu_is_u8500v11(void) { return false; } -static inline bool cpu_is_u8500v20(void) { return false; } -#endif - -static inline bool cpu_is_u5500(void) -{ -#ifdef CONFIG_UX500_SOC_DB5500 - return 1; -#else - return 0; -#endif -} +#include <mach/id.h> #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h new file mode 100644 index 00000000000..f1288d10b6a --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/id.h @@ -0,0 +1,80 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef __MACH_UX500_ID +#define __MACH_UX500_ID + +/** + * struct dbx500_asic_id - fields of the ASIC ID + * @process: the manufacturing process, 0x40 is 40 nm 0x00 is "standard" + * @partnumber: hithereto 0x8500 for DB8500 + * @revision: version code in the series + */ +struct dbx500_asic_id { + u16 partnumber; + u8 revision; + u8 process; +}; + +extern struct dbx500_asic_id dbx500_id; + +static inline unsigned int __attribute_const__ dbx500_partnumber(void) +{ + return dbx500_id.partnumber; +} + +static inline unsigned int __attribute_const__ dbx500_revision(void) +{ + return dbx500_id.revision; +} + +/* + * SOCs + */ + +static inline bool __attribute_const__ cpu_is_u8500(void) +{ + return dbx500_partnumber() == 0x8500; +} + +static inline bool __attribute_const__ cpu_is_u5500(void) +{ + return dbx500_partnumber() == 0x5500; +} + +/* + * 8500 revisions + */ + +static inline bool __attribute_const__ cpu_is_u8500ed(void) +{ + return cpu_is_u8500() && dbx500_revision() == 0x00; +} + +static inline bool __attribute_const__ cpu_is_u8500v1(void) +{ + return cpu_is_u8500() && (dbx500_revision() & 0xf0) == 0xA0; +} + +static inline bool __attribute_const__ cpu_is_u8500v10(void) +{ + return cpu_is_u8500() && dbx500_revision() == 0xA0; +} + +static inline bool __attribute_const__ cpu_is_u8500v11(void) +{ + return cpu_is_u8500() && dbx500_revision() == 0xA1; +} + +static inline bool __attribute_const__ cpu_is_u8500v2(void) +{ + return cpu_is_u8500() && ((dbx500_revision() & 0xf0) == 0xB0); +} + +#define ux500_unknown_soc() BUG() + +#endif diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h index 880ae45bc23..ba1294c13c4 100644 --- a/arch/arm/mach-ux500/include/mach/irqs.h +++ b/arch/arm/mach-ux500/include/mach/irqs.h @@ -36,7 +36,7 @@ /* This will be overridden by board-specific irq headers */ #define IRQ_BOARD_END IRQ_BOARD_START -#ifdef CONFIG_MACH_U8500_MOP +#ifdef CONFIG_MACH_U8500 #include <mach/irqs-board-mop500.h> #endif diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h index 469877e0de9..a7d363fdb4c 100644 --- a/arch/arm/mach-ux500/include/mach/setup.h +++ b/arch/arm/mach-ux500/include/mach/setup.h @@ -14,7 +14,7 @@ #include <asm/mach/time.h> #include <linux/init.h> -extern void __init ux500_map_io(void); +void __init ux500_map_io(void); extern void __init u5500_map_io(void); extern void __init u8500_map_io(void); diff --git a/arch/arm/mach-ux500/modem-irq-db5500.c b/arch/arm/mach-ux500/modem-irq-db5500.c index 3187f887116..e1296a7447c 100644 --- a/arch/arm/mach-ux500/modem-irq-db5500.c +++ b/arch/arm/mach-ux500/modem-irq-db5500.c @@ -12,6 +12,8 @@ #include <linux/io.h> #include <linux/slab.h> +#include <mach/id.h> + #define MODEM_INTCON_BASE_ADDR 0xBFFD3000 #define MODEM_INTCON_SIZE 0xFFF @@ -101,6 +103,9 @@ static int modem_irq_init(void) static struct irq_chip modem_irq_chip; struct modem_irq *mi; + if (!cpu_is_u5500()) + return -ENODEV; + pr_info("modem_irq: Set up IRQ handler for incoming modem IRQ %d\n", IRQ_DB5500_MODEM); diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index d77e76cb7ed..4fff4d40841 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -20,6 +20,7 @@ #include <asm/cacheflush.h> #include <asm/smp_scu.h> #include <mach/hardware.h> +#include <mach/setup.h> /* * control for which core is the next to come out of the secondary @@ -40,6 +41,18 @@ static void write_pen_release(int val) outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); } +static void __iomem *scu_base_addr(void) +{ + if (cpu_is_u5500()) + return __io_address(U5500_SCU_BASE); + else if (cpu_is_u8500()) + return __io_address(U8500_SCU_BASE); + else + ux500_unknown_soc(); + + return NULL; +} + static DEFINE_SPINLOCK(boot_lock); void __cpuinit platform_secondary_init(unsigned int cpu) @@ -100,21 +113,28 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) static void __init wakeup_secondary(void) { + void __iomem *backupram; + + if (cpu_is_u5500()) + backupram = __io_address(U5500_BACKUPRAM0_BASE); + else if (cpu_is_u8500()) + backupram = __io_address(U8500_BACKUPRAM0_BASE); + else + ux500_unknown_soc(); + /* * write the address of secondary startup into the backup ram register * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the * backup ram register at offset 0x1FF0, which is what boot rom code * is waiting for. This would wake up the secondary core from WFE */ -#define U8500_CPU1_JUMPADDR_OFFSET 0x1FF4 +#define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4 __raw_writel(virt_to_phys(u8500_secondary_startup), - __io_address(UX500_BACKUPRAM0_BASE) + - U8500_CPU1_JUMPADDR_OFFSET); + backupram + UX500_CPU1_JUMPADDR_OFFSET); -#define U8500_CPU1_WAKEMAGIC_OFFSET 0x1FF0 +#define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0 __raw_writel(0xA1FEED01, - __io_address(UX500_BACKUPRAM0_BASE) + - U8500_CPU1_WAKEMAGIC_OFFSET); + backupram + UX500_CPU1_WAKEMAGIC_OFFSET); /* make sure write buffer is drained */ mb(); @@ -126,9 +146,10 @@ static void __init wakeup_secondary(void) */ void __init smp_init_cpus(void) { + void __iomem *scu_base = scu_base_addr(); unsigned int i, ncores; - ncores = scu_get_core_count(__io_address(UX500_SCU_BASE)); + ncores = scu_base ? scu_get_core_count(scu_base) : 1; /* sanity check */ if (ncores > NR_CPUS) { @@ -154,6 +175,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) for (i = 0; i < max_cpus; i++) set_cpu_present(i, true); - scu_enable(__io_address(UX500_SCU_BASE)); + scu_enable(scu_base_addr()); wakeup_secondary(); } diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 49db8b3e4a4..fcc1e628e05 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -813,7 +813,7 @@ config CACHE_L2X0 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \ ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \ - ARCH_U8500 || ARCH_VEXPRESS_CA9X4 + ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE default y select OUTER_CACHE select OUTER_CACHE_SYNC diff --git a/arch/arm/plat-pxa/include/plat/ssp.h b/arch/arm/plat-pxa/include/plat/ssp.h deleted file mode 100644 index fe43150690e..00000000000 --- a/arch/arm/plat-pxa/include/plat/ssp.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * ssp.h - * - * Copyright (C) 2003 Russell King, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This driver supports the following PXA CPU/SSP ports:- - * - * PXA250 SSP - * PXA255 SSP, NSSP - * PXA26x SSP, NSSP, ASSP - * PXA27x SSP1, SSP2, SSP3 - * PXA3xx SSP1, SSP2, SSP3, SSP4 - */ - -#ifndef __ASM_ARCH_SSP_H -#define __ASM_ARCH_SSP_H - -#include <linux/list.h> -#include <linux/io.h> - -/* - * SSP Serial Port Registers - * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different. - * PXA255, PXA26x and PXA27x have extra ports, registers and bits. - */ - -#define SSCR0 (0x00) /* SSP Control Register 0 */ -#define SSCR1 (0x04) /* SSP Control Register 1 */ -#define SSSR (0x08) /* SSP Status Register */ -#define SSITR (0x0C) /* SSP Interrupt Test Register */ -#define SSDR (0x10) /* SSP Data Write/Data Read Register */ - -#define SSTO (0x28) /* SSP Time Out Register */ -#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */ -#define SSTSA (0x30) /* SSP Tx Timeslot Active */ -#define SSRSA (0x34) /* SSP Rx Timeslot Active */ -#define SSTSS (0x38) /* SSP Timeslot Status */ -#define SSACD (0x3C) /* SSP Audio Clock Divider */ -#define SSACDD (0x40) /* SSP Audio Clock Dither Divider */ - -/* Common PXA2xx bits first */ -#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ -#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ -#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */ -#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */ -#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */ -#define SSCR0_National (0x2 << 4) /* National Microwire */ -#define SSCR0_ECS (1 << 6) /* External clock select */ -#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ -#define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */ - -/* PXA27x, PXA3xx */ -#define SSCR0_EDSS (1 << 20) /* Extended data size select */ -#define SSCR0_NCS (1 << 21) /* Network clock select */ -#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */ -#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ -#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ -#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ -#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */ -#define SSCR0_ACS (1 << 30) /* Audio clock select */ -#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ - - -#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ -#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ -#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ -#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */ -#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ -#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ -#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */ -#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ -#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ -#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ - -#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ -#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ -#define SSSR_BSY (1 << 4) /* SSP Busy */ -#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ -#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ -#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ - - -/* extra bits in PXA255, PXA26x and PXA27x SSP ports */ -#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */ -#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */ -#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */ -#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */ -#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */ -#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */ -#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */ -#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */ -#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */ -#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */ -#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */ -#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */ -#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */ -#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */ -#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */ -#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */ -#define SSCR1_IFS (1 << 16) /* Invert Frame Signal */ -#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */ -#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */ - -#define SSSR_BCE (1 << 23) /* Bit Count Error */ -#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */ -#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */ -#define SSSR_EOC (1 << 20) /* End Of Chain */ -#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ -#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ - - -#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */ -#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */ -#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */ -#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */ -#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */ -#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */ -#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ -#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ -#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ - -/* PXA3xx */ -#define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */ -#define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */ -#define SSPSP_TIMING_MASK (0x7f8001f0) - -#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ -#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ -#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ -#define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */ - -enum pxa_ssp_type { - SSP_UNDEFINED = 0, - PXA25x_SSP, /* pxa 210, 250, 255, 26x */ - PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */ - PXA27x_SSP, - PXA168_SSP, -}; - -struct ssp_device { - struct platform_device *pdev; - struct list_head node; - - struct clk *clk; - void __iomem *mmio_base; - unsigned long phys_base; - - const char *label; - int port_id; - int type; - int use_count; - int irq; - int drcmr_rx; - int drcmr_tx; -}; - -/** - * pxa_ssp_write_reg - Write to a SSP register - * - * @dev: SSP device to access - * @reg: Register to write to - * @val: Value to be written. - */ -static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val) -{ - __raw_writel(val, dev->mmio_base + reg); -} - -/** - * pxa_ssp_read_reg - Read from a SSP register - * - * @dev: SSP device to access - * @reg: Register to read from - */ -static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg) -{ - return __raw_readl(dev->mmio_base + reg); -} - -struct ssp_device *pxa_ssp_request(int port, const char *label); -void pxa_ssp_free(struct ssp_device *); -#endif /* __ASM_ARCH_SSP_H */ diff --git a/arch/arm/plat-pxa/ssp.c b/arch/arm/plat-pxa/ssp.c index c6357e554ab..58b79809d20 100644 --- a/arch/arm/plat-pxa/ssp.c +++ b/arch/arm/plat-pxa/ssp.c @@ -28,11 +28,11 @@ #include <linux/clk.h> #include <linux/err.h> #include <linux/platform_device.h> +#include <linux/spi/pxa2xx_spi.h> #include <linux/io.h> #include <asm/irq.h> #include <mach/hardware.h> -#include <plat/ssp.h> static DEFINE_MUTEX(ssp_lock); static LIST_HEAD(ssp_list); diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/plat-s3c24xx/cpu-freq.c index 1ecc15bfe9d..25a8fc7f512 100644 --- a/arch/arm/plat-s3c24xx/cpu-freq.c +++ b/arch/arm/plat-s3c24xx/cpu-freq.c @@ -21,7 +21,6 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/sysdev.h> -#include <linux/kobject.h> #include <linux/sysfs.h> #include <linux/slab.h> diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile index 46738d49b7c..46f42b2066e 100644 --- a/arch/blackfin/Makefile +++ b/arch/blackfin/Makefile @@ -19,7 +19,7 @@ KBUILD_CFLAGS += -mlong-calls endif KBUILD_AFLAGS += $(call cc-option,-mno-fdpic) KBUILD_CFLAGS_MODULE += -mlong-calls -KBUILD_LDFLAGS_MODULE += -m elf32bfin +LDFLAGS += -m elf32bfin KALLSYMS += --symbol-prefix=_ KBUILD_DEFCONFIG := BF537-STAMP_defconfig @@ -97,8 +97,11 @@ rev-$(CONFIG_BF_REV_0_6) := 0.6 rev-$(CONFIG_BF_REV_NONE) := none rev-$(CONFIG_BF_REV_ANY) := any -KBUILD_CFLAGS += -mcpu=$(cpu-y)-$(rev-y) -KBUILD_AFLAGS += -mcpu=$(cpu-y)-$(rev-y) +CPU_REV := $(cpu-y)-$(rev-y) +export CPU_REV + +KBUILD_CFLAGS += -mcpu=$(CPU_REV) +KBUILD_AFLAGS += -mcpu=$(CPU_REV) # - we utilize the silicon rev from the toolchain, so move it over to the checkflags CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }') diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile index 13d2dbd658e..0a49279e342 100644 --- a/arch/blackfin/boot/Makefile +++ b/arch/blackfin/boot/Makefile @@ -17,7 +17,7 @@ UIMAGE_OPTS-$(CONFIG_ROMKERNEL) += -a $(CONFIG_ROM_BASE) -x quiet_cmd_uimage = UIMAGE $@ cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \ - -C $(2) -n '$(MACHINE)-$(KERNELRELEASE)' \ + -C $(2) -n '$(CPU_REV)-$(KERNELRELEASE)' \ -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \ $(UIMAGE_OPTS-y) -d $< $@ diff --git a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig new file mode 100644 index 00000000000..4cf451024fd --- /dev/null +++ b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig @@ -0,0 +1,113 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_EMBEDDED=y +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_ELF_CORE is not set +# CONFIG_FUTEX is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +CONFIG_SLAB=y +CONFIG_MMAP_ALLOW_UNINITIALIZED=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_BF561=y +CONFIG_SMP=y +CONFIG_IRQ_TIMER0=10 +CONFIG_CLKIN_HZ=30000000 +CONFIG_HIGH_RES_TIMERS=y +CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 +CONFIG_BFIN_GPTIMERS=m +CONFIG_C_CDPRIO=y +CONFIG_BANK_3=0xAAC2 +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_ZFLAT=y +CONFIG_PM=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +CONFIG_IRDA=m +CONFIG_IRLAN=m +CONFIG_IRCOMM=m +CONFIG_IRDA_CACHE_LAST_LSAP=y +CONFIG_IRTTY_SIR=m +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_FW_LOADER is not set +CONFIG_MTD=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=m +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=m +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_RAM=y +CONFIG_MTD_ROM=m +CONFIG_MTD_PHYSMAP=m +CONFIG_BLK_DEV_RAM=y +CONFIG_NETDEVICES=y +CONFIG_NET_ETHERNET=y +CONFIG_SMC91X=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +CONFIG_INPUT=m +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_DEVKMEM is not set +CONFIG_BFIN_JTAG_COMM=m +CONFIG_SERIAL_BFIN=y +CONFIG_SERIAL_BFIN_CONSOLE=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +CONFIG_SPI=y +CONFIG_SPI_BFIN=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_BFIN_WDT=y +# CONFIG_USB_SUPPORT is not set +# CONFIG_DNOTIFY is not set +CONFIG_JFFS2_FS=m +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +CONFIG_SMB_FS=m +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_SHIRQ=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEBUG_INFO=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_FTRACE is not set +CONFIG_DEBUG_MMRS=y +CONFIG_DEBUG_HWERR=y +CONFIG_EXACT_HWERR=y +CONFIG_DEBUG_DOUBLEFAULT=y +CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y +CONFIG_EARLY_PRINTK=y +CONFIG_CPLB_INFO=y +CONFIG_CRYPTO=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/DNP5370_defconfig b/arch/blackfin/configs/DNP5370_defconfig new file mode 100644 index 00000000000..0ebc7d9aa42 --- /dev/null +++ b/arch/blackfin/configs/DNP5370_defconfig @@ -0,0 +1,121 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_LOCALVERSION="DNP5370" +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_SLOB=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_BF537=y +CONFIG_BF_REV_0_3=y +CONFIG_DNP5370=y +CONFIG_IRQ_ERROR=7 +# CONFIG_CYCLES_CLOCKSOURCE is not set +CONFIG_C_CDPRIO=y +CONFIG_C_AMBEN_B0_B1_B2=y +CONFIG_PM=y +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_RARP=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +CONFIG_LLC2=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_DEBUG=y +CONFIG_MTD_DEBUG_VERBOSE=1 +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_ROM=y +CONFIG_MTD_ABSENT=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_UCLINUX=y +CONFIG_MTD_PLATRAM=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_BLOCK2MTD=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +# CONFIG_MISC_DEVICES is not set +CONFIG_NETDEVICES=y +CONFIG_DAVICOM_PHY=y +CONFIG_NET_ETHERNET=y +CONFIG_BFIN_MAC=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_BFIN_DMA_INTERFACE is not set +# CONFIG_VT is not set +# CONFIG_DEVKMEM is not set +CONFIG_BFIN_JTAG_COMM=y +CONFIG_BFIN_JTAG_COMM_CONSOLE=y +CONFIG_SERIAL_BFIN=y +CONFIG_SERIAL_BFIN_CONSOLE=y +CONFIG_SERIAL_BFIN_UART0=y +CONFIG_LEGACY_PTY_COUNT=64 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_BLACKFIN_TWI=y +CONFIG_SPI=y +CONFIG_SPI_BFIN=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_SENSORS_LM75=y +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_SPI=y +CONFIG_DMADEVICES=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_DNOTIFY is not set +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=850 +CONFIG_JFFS2_FS=y +CONFIG_CRAMFS=y +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_BOTH=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_SHIRQ=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEBUG_OBJECTS=y +CONFIG_DEBUG_LOCK_ALLOC=y +CONFIG_DEBUG_KOBJECT=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_VM=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DEBUG_LIST=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_PAGE_POISONING=y +# CONFIG_FTRACE is not set +CONFIG_DEBUG_DOUBLEFAULT=y +CONFIG_CPLB_INFO=y +CONFIG_CRC_CCITT=y diff --git a/arch/blackfin/include/asm/bfin_dma.h b/arch/blackfin/include/asm/bfin_dma.h new file mode 100644 index 00000000000..d5112074414 --- /dev/null +++ b/arch/blackfin/include/asm/bfin_dma.h @@ -0,0 +1,91 @@ +/* + * bfin_dma.h - Blackfin DMA defines/structures/etc... + * + * Copyright 2004-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_BFIN_DMA_H__ +#define __ASM_BFIN_DMA_H__ + +#include <linux/types.h> + +/* DMA_CONFIG Masks */ +#define DMAEN 0x0001 /* DMA Channel Enable */ +#define WNR 0x0002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ +#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ +#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ +#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ +#define RESTART 0x0020 /* DMA Buffer Clear */ +#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ +#define DI_EN 0x0080 /* Data Interrupt Enable */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ +#define NDSIZE 0x0f00 /* Next Descriptor Size */ +#define DMAFLOW 0x7000 /* Flow Control */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ + +/* DMA_IRQ_STATUS Masks */ +#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ +#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ +#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ +#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ + +/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +#define __BFP(m) u16 m; u16 __pad_##m + +/* + * bfin dma registers layout + */ +struct bfin_dma_regs { + u32 next_desc_ptr; + u32 start_addr; + __BFP(config); + u32 __pad0; + __BFP(x_count); + __BFP(x_modify); + __BFP(y_count); + __BFP(y_modify); + u32 curr_desc_ptr; + u32 curr_addr; + __BFP(irq_status); + __BFP(peripheral_map); + __BFP(curr_x_count); + u32 __pad1; + __BFP(curr_y_count); + u32 __pad2; +}; + +/* + * bfin handshake mdma registers layout + */ +struct bfin_hmdma_regs { + __BFP(control); + __BFP(ecinit); + __BFP(bcinit); + __BFP(ecurgent); + __BFP(ecoverflow); + __BFP(ecount); + __BFP(bcount); +}; + +#undef __BFP + +#endif diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h new file mode 100644 index 00000000000..1ff9f1468c0 --- /dev/null +++ b/arch/blackfin/include/asm/bfin_serial.h @@ -0,0 +1,275 @@ +/* + * bfin_serial.h - Blackfin UART/Serial definitions + * + * Copyright 2006-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_ASM_SERIAL_H__ +#define __BFIN_ASM_SERIAL_H__ + +#include <linux/serial_core.h> +#include <mach/anomaly.h> +#include <mach/bfin_serial.h> + +#if defined(CONFIG_BFIN_UART0_CTSRTS) || \ + defined(CONFIG_BFIN_UART1_CTSRTS) || \ + defined(CONFIG_BFIN_UART2_CTSRTS) || \ + defined(CONFIG_BFIN_UART3_CTSRTS) +# ifdef BFIN_UART_BF54X_STYLE +# define CONFIG_SERIAL_BFIN_HARD_CTSRTS +# else +# define CONFIG_SERIAL_BFIN_CTSRTS +# endif +#endif + +struct circ_buf; +struct timer_list; +struct work_struct; + +struct bfin_serial_port { + struct uart_port port; + unsigned int old_status; + int status_irq; +#ifndef BFIN_UART_BF54X_STYLE + unsigned int lsr; +#endif +#ifdef CONFIG_SERIAL_BFIN_DMA + int tx_done; + int tx_count; + struct circ_buf rx_dma_buf; + struct timer_list rx_dma_timer; + int rx_dma_nrows; + unsigned int tx_dma_channel; + unsigned int rx_dma_channel; + struct work_struct tx_dma_workqueue; +#elif ANOMALY_05000363 + unsigned int anomaly_threshold; +#endif +#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS + int scts; +#endif +#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ + defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) + int cts_pin; + int rts_pin; +#endif +}; + +/* UART_LCR Masks */ +#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ +#define STB 0x04 /* Stop Bits */ +#define PEN 0x08 /* Parity Enable */ +#define EPS 0x10 /* Even Parity Select */ +#define STP 0x20 /* Stick Parity */ +#define SB 0x40 /* Set Break */ +#define DLAB 0x80 /* Divisor Latch Access */ + +/* UART_LSR Masks */ +#define DR 0x01 /* Data Ready */ +#define OE 0x02 /* Overrun Error */ +#define PE 0x04 /* Parity Error */ +#define FE 0x08 /* Framing Error */ +#define BI 0x10 /* Break Interrupt */ +#define THRE 0x20 /* THR Empty */ +#define TEMT 0x40 /* TSR and UART_THR Empty */ +#define TFI 0x80 /* Transmission Finished Indicator */ + +/* UART_IER Masks */ +#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ +#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ +#define ELSI 0x04 /* Enable RX Status Interrupt */ +#define EDSSI 0x08 /* Enable Modem Status Interrupt */ +#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */ +#define ETFI 0x20 /* Enable Transmission Finished Interrupt */ +#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */ + +/* UART_MCR Masks */ +#define XOFF 0x01 /* Transmitter Off */ +#define MRTS 0x02 /* Manual Request To Send */ +#define RFIT 0x04 /* Receive FIFO IRQ Threshold */ +#define RFRT 0x08 /* Receive FIFO RTS Threshold */ +#define LOOP_ENA 0x10 /* Loopback Mode Enable */ +#define FCPOL 0x20 /* Flow Control Pin Polarity */ +#define ARTS 0x40 /* Automatic Request To Send */ +#define ACTS 0x80 /* Automatic Clear To Send */ + +/* UART_MSR Masks */ +#define SCTS 0x01 /* Sticky CTS */ +#define CTS 0x10 /* Clear To Send */ +#define RFCS 0x20 /* Receive FIFO Count Status */ + +/* UART_GCTL Masks */ +#define UCEN 0x01 /* Enable UARTx Clocks */ +#define IREN 0x02 /* Enable IrDA Mode */ +#define TPOLC 0x04 /* IrDA TX Polarity Change */ +#define RPOLC 0x08 /* IrDA RX Polarity Change */ +#define FPE 0x10 /* Force Parity Error On Transmit */ +#define FFE 0x20 /* Force Framing Error On Transmit */ + +#ifdef BFIN_UART_BF54X_STYLE +# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ +# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ +# define OFFSET_GCTL 0x08 /* Global Control Register */ +# define OFFSET_LCR 0x0C /* Line Control Register */ +# define OFFSET_MCR 0x10 /* Modem Control Register */ +# define OFFSET_LSR 0x14 /* Line Status Register */ +# define OFFSET_MSR 0x18 /* Modem Status Register */ +# define OFFSET_SCR 0x1C /* SCR Scratch Register */ +# define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */ +# define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */ +# define OFFSET_THR 0x28 /* Transmit Holding register */ +# define OFFSET_RBR 0x2C /* Receive Buffer register */ +#else /* BF533 style */ +# define OFFSET_THR 0x00 /* Transmit Holding register */ +# define OFFSET_RBR 0x00 /* Receive Buffer register */ +# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ +# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ +# define OFFSET_IER 0x04 /* Interrupt Enable Register */ +# define OFFSET_IIR 0x08 /* Interrupt Identification Register */ +# define OFFSET_LCR 0x0C /* Line Control Register */ +# define OFFSET_MCR 0x10 /* Modem Control Register */ +# define OFFSET_LSR 0x14 /* Line Status Register */ +# define OFFSET_MSR 0x18 /* Modem Status Register */ +# define OFFSET_SCR 0x1C /* SCR Scratch Register */ +# define OFFSET_GCTL 0x24 /* Global Control Register */ +/* code should not need IIR, so force build error if they use it */ +# undef OFFSET_IIR +#endif + +/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +#define __BFP(m) u16 m; u16 __pad_##m +struct bfin_uart_regs { +#ifdef BFIN_UART_BF54X_STYLE + __BFP(dll); + __BFP(dlh); + __BFP(gctl); + __BFP(lcr); + __BFP(mcr); + __BFP(lsr); + __BFP(msr); + __BFP(scr); + __BFP(ier_set); + __BFP(ier_clear); + __BFP(thr); + __BFP(rbr); +#else + union { + u16 dll; + u16 thr; + const u16 rbr; + }; + const u16 __pad0; + union { + u16 dlh; + u16 ier; + }; + const u16 __pad1; + const __BFP(iir); + __BFP(lcr); + __BFP(mcr); + __BFP(lsr); + __BFP(msr); + __BFP(scr); + const u32 __pad2; + __BFP(gctl); +#endif +}; +#undef __BFP + +#ifndef port_membase +# define port_membase(p) (((struct bfin_serial_port *)(p))->port.membase) +#endif + +#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR) +#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL) +#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH) +#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL) +#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR) +#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR) +#define UART_GET_MSR(p) bfin_read16(port_membase(p) + OFFSET_MSR) + +#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v) +#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v) +#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v) +#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v) +#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v) +#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v) + +#ifdef BFIN_UART_BF54X_STYLE + +#define UART_CLEAR_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v) +#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER_SET) +#define UART_SET_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_SET, v) + +#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF54x */ +#define UART_SET_DLAB(p) /* MMRs not muxed on BF54x */ + +#define UART_CLEAR_LSR(p) bfin_write16(port_membase(p) + OFFSET_LSR, -1) +#define UART_GET_LSR(p) bfin_read16(port_membase(p) + OFFSET_LSR) +#define UART_PUT_LSR(p, v) bfin_write16(port_membase(p) + OFFSET_LSR, v) + +/* This handles hard CTS/RTS */ +#define BFIN_UART_CTSRTS_HARD +#define UART_CLEAR_SCTS(p) bfin_write16((port_membase(p) + OFFSET_MSR), SCTS) +#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS) +#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS)) +#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS) +#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v) +#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF) + +#else /* BF533 style */ + +#define UART_CLEAR_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) & ~(v)) +#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER) +#define UART_PUT_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER, v) +#define UART_SET_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) | (v)) + +#define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0) +#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0) + +#ifndef put_lsr_cache +# define put_lsr_cache(p, v) (((struct bfin_serial_port *)(p))->lsr = (v)) +#endif +#ifndef get_lsr_cache +# define get_lsr_cache(p) (((struct bfin_serial_port *)(p))->lsr) +#endif + +/* The hardware clears the LSR bits upon read, so we need to cache + * some of the more fun bits in software so they don't get lost + * when checking the LSR in other code paths (TX). + */ +static inline void UART_CLEAR_LSR(void *p) +{ + put_lsr_cache(p, 0); + bfin_write16(port_membase(p) + OFFSET_LSR, -1); +} +static inline unsigned int UART_GET_LSR(void *p) +{ + unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR); + put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE))); + return lsr | get_lsr_cache(p); +} +static inline void UART_PUT_LSR(void *p, uint16_t val) +{ + put_lsr_cache(p, get_lsr_cache(p) & ~val); +} + +/* This handles soft CTS/RTS */ +#define UART_GET_CTS(x) gpio_get_value((x)->cts_pin) +#define UART_DISABLE_RTS(x) gpio_set_value((x)->rts_pin, 1) +#define UART_ENABLE_RTS(x) gpio_set_value((x)->rts_pin, 0) +#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) +#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) + +#endif + +#ifndef BFIN_UART_TX_FIFO_SIZE +# define BFIN_UART_TX_FIFO_SIZE 2 +#endif + +#endif /* __BFIN_ASM_SERIAL_H__ */ diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h index 3f7ef4d9779..29f4fd88617 100644 --- a/arch/blackfin/include/asm/bitops.h +++ b/arch/blackfin/include/asm/bitops.h @@ -108,7 +108,9 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr) #define smp_mb__before_clear_bit() barrier() #define smp_mb__after_clear_bit() barrier() +#define test_bit __skip_test_bit #include <asm-generic/bitops/non-atomic.h> +#undef test_bit #endif /* CONFIG_SMP */ diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h index bd0641a267f..568885a2c28 100644 --- a/arch/blackfin/include/asm/cache.h +++ b/arch/blackfin/include/asm/cache.h @@ -7,6 +7,8 @@ #ifndef __ARCH_BLACKFIN_CACHE_H #define __ARCH_BLACKFIN_CACHE_H +#include <linux/linkage.h> /* for asmlinkage */ + /* * Bytes per L1 cache line * Blackfin loads 32 bytes for cache diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h index 2666ff8ea95..77135b62818 100644 --- a/arch/blackfin/include/asm/cacheflush.h +++ b/arch/blackfin/include/asm/cacheflush.h @@ -11,6 +11,9 @@ #include <asm/blackfin.h> /* for SSYNC() */ #include <asm/sections.h> /* for _ramend */ +#ifdef CONFIG_SMP +#include <asm/smp.h> +#endif extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address); extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h index eedf3ca65ba..d9dbc1a5353 100644 --- a/arch/blackfin/include/asm/dma.h +++ b/arch/blackfin/include/asm/dma.h @@ -14,40 +14,7 @@ #include <asm/blackfin.h> #include <asm/page.h> #include <asm-generic/dma.h> - -/* DMA_CONFIG Masks */ -#define DMAEN 0x0001 /* DMA Channel Enable */ -#define WNR 0x0002 /* Channel Direction (W/R*) */ -#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ -#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ -#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ -#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ -#define RESTART 0x0020 /* DMA Buffer Clear */ -#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ -#define DI_EN 0x0080 /* Data Interrupt Enable */ -#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ -#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ -#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ -#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ -#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ -#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ -#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ -#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ -#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ -#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ -#define NDSIZE 0x0f00 /* Next Descriptor Size */ -#define DMAFLOW 0x7000 /* Flow Control */ -#define DMAFLOW_STOP 0x0000 /* Stop Mode */ -#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ -#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ -#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ -#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ - -/* DMA_IRQ_STATUS Masks */ -#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ -#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ -#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ -#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ +#include <asm/bfin_dma.h> /*------------------------- * config reg bits value @@ -149,7 +116,7 @@ void blackfin_dma_resume(void); * DMA API's *******************************************************************************/ extern struct dma_channel dma_ch[MAX_DMA_CHANNELS]; -extern struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS]; +extern struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS]; extern int channel2irq(unsigned int channel); static inline void set_dma_start_addr(unsigned int channel, unsigned long addr) diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h index efcc3aebeae..3047120cfcf 100644 --- a/arch/blackfin/include/asm/dpmc.h +++ b/arch/blackfin/include/asm/dpmc.h @@ -9,6 +9,8 @@ #ifndef _BLACKFIN_DPMC_H_ #define _BLACKFIN_DPMC_H_ +#include <mach/pll.h> + /* PLL_CTL Masks */ #define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ #define PLL_OFF 0x0002 /* PLL Not Powered */ diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h index 234fbac17ec..dccae26805b 100644 --- a/arch/blackfin/include/asm/io.h +++ b/arch/blackfin/include/asm/io.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2009 Analog Devices Inc. + * Copyright 2004-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -7,148 +7,48 @@ #ifndef _BFIN_IO_H #define _BFIN_IO_H -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ -#include <linux/types.h> -#endif #include <linux/compiler.h> - -/* - * These are for ISA/PCI shared memory _only_ and should never be used - * on any other type of memory, including Zorro memory. They are meant to - * access the bus in the bus byte order which is little-endian!. - * - * readX/writeX() are used to access memory mapped devices. On some - * architectures the memory mapped IO stuff needs to be accessed - * differently. On the bfin architecture, we just read/write the - * memory location directly. - */ -#ifndef __ASSEMBLY__ - -static inline unsigned char readb(const volatile void __iomem *addr) -{ - unsigned int val; - int tmp; - - __asm__ __volatile__ ( - "cli %1;" - "NOP; NOP; SSYNC;" - "%0 = b [%2] (z);" - "sti %1;" - : "=d"(val), "=d"(tmp) - : "a"(addr) - ); - - return (unsigned char) val; -} - -static inline unsigned short readw(const volatile void __iomem *addr) -{ - unsigned int val; - int tmp; - - __asm__ __volatile__ ( - "cli %1;" - "NOP; NOP; SSYNC;" - "%0 = w [%2] (z);" - "sti %1;" - : "=d"(val), "=d"(tmp) - : "a"(addr) - ); - - return (unsigned short) val; -} - -static inline unsigned int readl(const volatile void __iomem *addr) -{ - unsigned int val; - int tmp; - - __asm__ __volatile__ ( - "cli %1;" - "NOP; NOP; SSYNC;" - "%0 = [%2];" - "sti %1;" - : "=d"(val), "=d"(tmp) - : "a"(addr) - ); - - return val; +#include <linux/types.h> +#include <asm/byteorder.h> + +#define DECLARE_BFIN_RAW_READX(size, type, asm, asm_sign) \ +static inline type __raw_read##size(const volatile void __iomem *addr) \ +{ \ + unsigned int val; \ + int tmp; \ + __asm__ __volatile__ ( \ + "cli %1;" \ + "NOP; NOP; SSYNC;" \ + "%0 = "#asm" [%2] "#asm_sign";" \ + "sti %1;" \ + : "=d"(val), "=d"(tmp) \ + : "a"(addr) \ + ); \ + return (type) val; \ } - -#endif /* __ASSEMBLY__ */ - -#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b)) -#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b)) -#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b)) - -#define __raw_readb readb -#define __raw_readw readw -#define __raw_readl readl -#define __raw_writeb writeb -#define __raw_writew writew -#define __raw_writel writel -#define memset_io(a, b, c) memset((void *)(a), (b), (c)) -#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) -#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) - -/* Convert "I/O port addresses" to actual addresses. i.e. ugly casts. */ -#define __io(port) ((void *)(unsigned long)(port)) - -#define inb(port) readb(__io(port)) -#define inw(port) readw(__io(port)) -#define inl(port) readl(__io(port)) -#define outb(x, port) writeb(x, __io(port)) -#define outw(x, port) writew(x, __io(port)) -#define outl(x, port) writel(x, __io(port)) - -#define inb_p(port) inb(__io(port)) -#define inw_p(port) inw(__io(port)) -#define inl_p(port) inl(__io(port)) -#define outb_p(x, port) outb(x, __io(port)) -#define outw_p(x, port) outw(x, __io(port)) -#define outl_p(x, port) outl(x, __io(port)) - -#define ioread8_rep(a, d, c) readsb(a, d, c) -#define ioread16_rep(a, d, c) readsw(a, d, c) -#define ioread32_rep(a, d, c) readsl(a, d, c) -#define iowrite8_rep(a, s, c) writesb(a, s, c) -#define iowrite16_rep(a, s, c) writesw(a, s, c) -#define iowrite32_rep(a, s, c) writesl(a, s, c) - -#define ioread8(x) readb(x) -#define ioread16(x) readw(x) -#define ioread32(x) readl(x) -#define iowrite8(val, x) writeb(val, x) -#define iowrite16(val, x) writew(val, x) -#define iowrite32(val, x) writel(val, x) - -/** - * I/O write barrier - * - * Ensure ordering of I/O space writes. This will make sure that writes - * following the barrier will arrive after all previous writes. - */ -#define mmiowb() do { SSYNC(); wmb(); } while (0) - -#define IO_SPACE_LIMIT 0xffffffff - -/* Values for nocacheflag and cmode */ -#define IOMAP_NOCACHE_SER 1 - -#ifndef __ASSEMBLY__ +DECLARE_BFIN_RAW_READX(b, u8, b, (z)) +#define __raw_readb __raw_readb +DECLARE_BFIN_RAW_READX(w, u16, w, (z)) +#define __raw_readw __raw_readw +DECLARE_BFIN_RAW_READX(l, u32, , ) +#define __raw_readl __raw_readl extern void outsb(unsigned long port, const void *addr, unsigned long count); extern void outsw(unsigned long port, const void *addr, unsigned long count); extern void outsw_8(unsigned long port, const void *addr, unsigned long count); extern void outsl(unsigned long port, const void *addr, unsigned long count); +#define outsb outsb +#define outsw outsw +#define outsl outsl extern void insb(unsigned long port, void *addr, unsigned long count); extern void insw(unsigned long port, void *addr, unsigned long count); extern void insw_8(unsigned long port, void *addr, unsigned long count); extern void insl(unsigned long port, void *addr, unsigned long count); extern void insl_16(unsigned long port, void *addr, unsigned long count); +#define insb insb +#define insw insw +#define insl insl extern void dma_outsb(unsigned long port, const void *addr, unsigned short count); extern void dma_outsw(unsigned long port, const void *addr, unsigned short count); @@ -158,108 +58,14 @@ extern void dma_insb(unsigned long port, void *addr, unsigned short count); extern void dma_insw(unsigned long port, void *addr, unsigned short count); extern void dma_insl(unsigned long port, void *addr, unsigned short count); -static inline void readsl(const void __iomem *addr, void *buf, int len) -{ - insl((unsigned long)addr, buf, len); -} - -static inline void readsw(const void __iomem *addr, void *buf, int len) -{ - insw((unsigned long)addr, buf, len); -} - -static inline void readsb(const void __iomem *addr, void *buf, int len) -{ - insb((unsigned long)addr, buf, len); -} - -static inline void writesl(const void __iomem *addr, const void *buf, int len) -{ - outsl((unsigned long)addr, buf, len); -} - -static inline void writesw(const void __iomem *addr, const void *buf, int len) -{ - outsw((unsigned long)addr, buf, len); -} - -static inline void writesb(const void __iomem *addr, const void *buf, int len) -{ - outsb((unsigned long)addr, buf, len); -} - -/* - * Map some physical address range into the kernel address space. - */ -static inline void __iomem *__ioremap(unsigned long physaddr, unsigned long size, - int cacheflag) -{ - return (void __iomem *)physaddr; -} - -/* - * Unmap a ioremap()ed region again - */ -static inline void iounmap(void *addr) -{ -} - -/* - * __iounmap unmaps nearly everything, so be careful - * it doesn't free currently pointer/page tables anymore but it - * wans't used anyway and might be added later. - */ -static inline void __iounmap(void *addr, unsigned long size) -{ -} - -/* - * Set new cache mode for some kernel address space. - * The caller must push data for that range itself, if such data may already - * be in the cache. +/** + * I/O write barrier + * + * Ensure ordering of I/O space writes. This will make sure that writes + * following the barrier will arrive after all previous writes. */ -static inline void kernel_set_cachemode(void *addr, unsigned long size, - int cmode) -{ -} - -static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size) -{ - return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); -} -static inline void __iomem *ioremap_nocache(unsigned long physaddr, - unsigned long size) -{ - return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); -} +#define mmiowb() do { SSYNC(); wmb(); } while (0) -extern void blkfin_inv_cache_all(void); +#include <asm-generic/io.h> #endif - -#define ioport_map(port, nr) ((void __iomem*)(port)) -#define ioport_unmap(addr) - -/* Pages to physical address... */ -#define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT) - -#define phys_to_virt(vaddr) ((void *) (vaddr)) -#define virt_to_phys(vaddr) ((unsigned long) (vaddr)) - -#define virt_to_bus virt_to_phys -#define bus_to_virt phys_to_virt - -/* - * Convert a physical pointer to a virtual kernel pointer for /dev/mem - * access - */ -#define xlate_dev_mem_ptr(p) __va(p) - -/* - * Convert a virtual cached pointer to an uncached pointer - */ -#define xlate_dev_kmem_ptr(p) p - -#endif /* __KERNEL__ */ - -#endif /* _BFIN_IO_H */ diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h index 41c4d70544e..3365cb97f53 100644 --- a/arch/blackfin/include/asm/irqflags.h +++ b/arch/blackfin/include/asm/irqflags.h @@ -13,9 +13,6 @@ #ifdef CONFIG_SMP # include <asm/pda.h> # include <asm/processor.h> -/* Forward decl needed due to cdef inter dependencies */ -static inline uint32_t __pure bfin_dspid(void); -# define blackfin_core_id() (bfin_dspid() & 0xff) # define bfin_irq_flags cpu_pda[blackfin_core_id()].imask #else extern unsigned long bfin_irq_flags; diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h index aea880274de..8af7772e84c 100644 --- a/arch/blackfin/include/asm/processor.h +++ b/arch/blackfin/include/asm/processor.h @@ -14,7 +14,7 @@ #define current_text_addr() ({ __label__ _l; _l: &&_l;}) #include <asm/ptrace.h> -#include <asm/blackfin.h> +#include <mach/blackfin.h> static inline unsigned long rdusp(void) { @@ -134,6 +134,8 @@ static inline uint32_t __pure bfin_dspid(void) return bfin_read_DSPID(); } +#define blackfin_core_id() (bfin_dspid() & 0xff) + static inline uint32_t __pure bfin_compiled_revid(void) { #if defined(CONFIG_BF_REV_0_0) diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h index 1942ccfedbe..1f286e71c21 100644 --- a/arch/blackfin/include/asm/spinlock.h +++ b/arch/blackfin/include/asm/spinlock.h @@ -17,12 +17,12 @@ asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr); asmlinkage void __raw_spin_lock_asm(volatile int *ptr); asmlinkage int __raw_spin_trylock_asm(volatile int *ptr); asmlinkage void __raw_spin_unlock_asm(volatile int *ptr); -asmlinkage void arch_read_lock_asm(volatile int *ptr); -asmlinkage int arch_read_trylock_asm(volatile int *ptr); -asmlinkage void arch_read_unlock_asm(volatile int *ptr); -asmlinkage void arch_write_lock_asm(volatile int *ptr); -asmlinkage int arch_write_trylock_asm(volatile int *ptr); -asmlinkage void arch_write_unlock_asm(volatile int *ptr); +asmlinkage void __raw_read_lock_asm(volatile int *ptr); +asmlinkage int __raw_read_trylock_asm(volatile int *ptr); +asmlinkage void __raw_read_unlock_asm(volatile int *ptr); +asmlinkage void __raw_write_lock_asm(volatile int *ptr); +asmlinkage int __raw_write_trylock_asm(volatile int *ptr); +asmlinkage void __raw_write_unlock_asm(volatile int *ptr); static inline int arch_spin_is_locked(arch_spinlock_t *lock) { @@ -64,32 +64,36 @@ static inline int arch_write_can_lock(arch_rwlock_t *rw) static inline void arch_read_lock(arch_rwlock_t *rw) { - arch_read_lock_asm(&rw->lock); + __raw_read_lock_asm(&rw->lock); } +#define arch_read_lock_flags(lock, flags) arch_read_lock(lock) + static inline int arch_read_trylock(arch_rwlock_t *rw) { - return arch_read_trylock_asm(&rw->lock); + return __raw_read_trylock_asm(&rw->lock); } static inline void arch_read_unlock(arch_rwlock_t *rw) { - arch_read_unlock_asm(&rw->lock); + __raw_read_unlock_asm(&rw->lock); } static inline void arch_write_lock(arch_rwlock_t *rw) { - arch_write_lock_asm(&rw->lock); + __raw_write_lock_asm(&rw->lock); } +#define arch_write_lock_flags(lock, flags) arch_write_lock(lock) + static inline int arch_write_trylock(arch_rwlock_t *rw) { - return arch_write_trylock_asm(&rw->lock); + return __raw_write_trylock_asm(&rw->lock); } static inline void arch_write_unlock(arch_rwlock_t *rw) { - arch_write_unlock_asm(&rw->lock); + __raw_write_unlock_asm(&rw->lock); } #define arch_spin_relax(lock) cpu_relax() diff --git a/arch/blackfin/include/mach-common/pll.h b/arch/blackfin/include/mach-common/pll.h new file mode 100644 index 00000000000..382178b361a --- /dev/null +++ b/arch/blackfin/include/mach-common/pll.h @@ -0,0 +1,86 @@ +/* + * Copyright 2005-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _MACH_COMMON_PLL_H +#define _MACH_COMMON_PLL_H + +#ifndef __ASSEMBLY__ + +#include <asm/blackfin.h> +#include <asm/irqflags.h> + +#ifndef bfin_iwr_restore +static inline void +bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2) +{ +#ifdef SIC_IWR + bfin_write_SIC_IWR(iwr0); +#else + bfin_write_SIC_IWR0(iwr0); +# ifdef SIC_IWR1 + bfin_write_SIC_IWR1(iwr1); +# endif +# ifdef SIC_IWR2 + bfin_write_SIC_IWR2(iwr2); +# endif +#endif +} +#endif + +#ifndef bfin_iwr_save +static inline void +bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2, + unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2) +{ +#ifdef SIC_IWR + *iwr0 = bfin_read_SIC_IWR(); +#else + *iwr0 = bfin_read_SIC_IWR0(); +# ifdef SIC_IWR1 + *iwr1 = bfin_read_SIC_IWR1(); +# endif +# ifdef SIC_IWR2 + *iwr2 = bfin_read_SIC_IWR2(); +# endif +#endif + bfin_iwr_restore(niwr0, niwr1, niwr2); +} +#endif + +static inline void _bfin_write_pll_relock(u32 addr, unsigned int val) +{ + unsigned long flags, iwr0, iwr1, iwr2; + + if (val == bfin_read_PLL_CTL()) + return; + + flags = hard_local_irq_save(); + /* Enable the PLL Wakeup bit in SIC IWR */ + bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2); + + bfin_write16(addr, val); + SSYNC(); + asm("IDLE;"); + + bfin_iwr_restore(iwr0, iwr1, iwr2); + hard_local_irq_restore(flags); +} + +/* Writing to PLL_CTL initiates a PLL relock sequence */ +static inline void bfin_write_PLL_CTL(unsigned int val) +{ + _bfin_write_pll_relock(PLL_CTL, val); +} + +/* Writing to VR_CTL initiates a PLL relock sequence */ +static inline void bfin_write_VR_CTL(unsigned int val) +{ + _bfin_write_pll_relock(VR_CTL, val); +} + +#endif + +#endif diff --git a/arch/blackfin/include/mach-common/ports-a.h b/arch/blackfin/include/mach-common/ports-a.h new file mode 100644 index 00000000000..9f78a761c40 --- /dev/null +++ b/arch/blackfin/include/mach-common/ports-a.h @@ -0,0 +1,25 @@ +/* + * Port A Masks + */ + +#ifndef __BFIN_PERIPHERAL_PORT_A__ +#define __BFIN_PERIPHERAL_PORT_A__ + +#define PA0 (1 << 0) +#define PA1 (1 << 1) +#define PA2 (1 << 2) +#define PA3 (1 << 3) +#define PA4 (1 << 4) +#define PA5 (1 << 5) +#define PA6 (1 << 6) +#define PA7 (1 << 7) +#define PA8 (1 << 8) +#define PA9 (1 << 9) +#define PA10 (1 << 10) +#define PA11 (1 << 11) +#define PA12 (1 << 12) +#define PA13 (1 << 13) +#define PA14 (1 << 14) +#define PA15 (1 << 15) + +#endif diff --git a/arch/blackfin/include/mach-common/ports-b.h b/arch/blackfin/include/mach-common/ports-b.h new file mode 100644 index 00000000000..b81702f09ec --- /dev/null +++ b/arch/blackfin/include/mach-common/ports-b.h @@ -0,0 +1,25 @@ +/* + * Port B Masks + */ + +#ifndef __BFIN_PERIPHERAL_PORT_B__ +#define __BFIN_PERIPHERAL_PORT_B__ + +#define PB0 (1 << 0) +#define PB1 (1 << 1) +#define PB2 (1 << 2) +#define PB3 (1 << 3) +#define PB4 (1 << 4) +#define PB5 (1 << 5) +#define PB6 (1 << 6) +#define PB7 (1 << 7) +#define PB8 (1 << 8) +#define PB9 (1 << 9) +#define PB10 (1 << 10) +#define PB11 (1 << 11) +#define PB12 (1 << 12) +#define PB13 (1 << 13) +#define PB14 (1 << 14) +#define PB15 (1 << 15) + +#endif diff --git a/arch/blackfin/include/mach-common/ports-c.h b/arch/blackfin/include/mach-common/ports-c.h new file mode 100644 index 00000000000..3cc665e0ba0 --- /dev/null +++ b/arch/blackfin/include/mach-common/ports-c.h @@ -0,0 +1,25 @@ +/* + * Port C Masks + */ + +#ifndef __BFIN_PERIPHERAL_PORT_C__ +#define __BFIN_PERIPHERAL_PORT_C__ + +#define PC0 (1 << 0) +#define PC1 (1 << 1) +#define PC2 (1 << 2) +#define PC3 (1 << 3) +#define PC4 (1 << 4) +#define PC5 (1 << 5) +#define PC6 (1 << 6) +#define PC7 (1 << 7) +#define PC8 (1 << 8) +#define PC9 (1 << 9) +#define PC10 (1 << 10) +#define PC11 (1 << 11) +#define PC12 (1 << 12) +#define PC13 (1 << 13) +#define PC14 (1 << 14) +#define PC15 (1 << 15) + +#endif diff --git a/arch/blackfin/include/mach-common/ports-d.h b/arch/blackfin/include/mach-common/ports-d.h new file mode 100644 index 00000000000..868c6a01f1b --- /dev/null +++ b/arch/blackfin/include/mach-common/ports-d.h @@ -0,0 +1,25 @@ +/* + * Port D Masks + */ + +#ifndef __BFIN_PERIPHERAL_PORT_D__ +#define __BFIN_PERIPHERAL_PORT_D__ + +#define PD0 (1 << 0) +#define PD1 (1 << 1) +#define PD2 (1 << 2) +#define PD3 (1 << 3) +#define PD4 (1 << 4) +#define PD5 (1 << 5) +#define PD6 (1 << 6) +#define PD7 (1 << 7) +#define PD8 (1 << 8) +#define PD9 (1 << 9) +#define PD10 (1 << 10) +#define PD11 (1 << 11) +#define PD12 (1 << 12) +#define PD13 (1 << 13) +#define PD14 (1 << 14) +#define PD15 (1 << 15) + +#endif diff --git a/arch/blackfin/include/mach-common/ports-e.h b/arch/blackfin/include/mach-common/ports-e.h new file mode 100644 index 00000000000..c88b0d0dd44 --- /dev/null +++ b/arch/blackfin/include/mach-common/ports-e.h @@ -0,0 +1,25 @@ +/* + * Port E Masks + */ + +#ifndef __BFIN_PERIPHERAL_PORT_E__ +#define __BFIN_PERIPHERAL_PORT_E__ + +#define PE0 (1 << 0) +#define PE1 (1 << 1) +#define PE2 (1 << 2) +#define PE3 (1 << 3) +#define PE4 (1 << 4) +#define PE5 (1 << 5) +#define PE6 (1 << 6) +#define PE7 (1 << 7) +#define PE8 (1 << 8) +#define PE9 (1 << 9) +#define PE10 (1 << 10) +#define PE11 (1 << 11) +#define PE12 (1 << 12) +#define PE13 (1 << 13) +#define PE14 (1 << 14) +#define PE15 (1 << 15) + +#endif diff --git a/arch/blackfin/include/mach-common/ports-f.h b/arch/blackfin/include/mach-common/ports-f.h new file mode 100644 index 00000000000..d6af2063327 --- /dev/null +++ b/arch/blackfin/include/mach-common/ports-f.h @@ -0,0 +1,25 @@ +/* + * Port F Masks + */ + +#ifndef __BFIN_PERIPHERAL_PORT_F__ +#define __BFIN_PERIPHERAL_PORT_F__ + +#define PF0 (1 << 0) +#define PF1 (1 << 1) +#define PF2 (1 << 2) +#define PF3 (1 << 3) +#define PF4 (1 << 4) +#define PF5 (1 << 5) +#define PF6 (1 << 6) +#define PF7 (1 << 7) +#define PF8 (1 << 8) +#define PF9 (1 << 9) +#define PF10 (1 << 10) +#define PF11 (1 << 11) +#define PF12 (1 << 12) +#define PF13 (1 << 13) +#define PF14 (1 << 14) +#define PF15 (1 << 15) + +#endif diff --git a/arch/blackfin/include/mach-common/ports-g.h b/arch/blackfin/include/mach-common/ports-g.h new file mode 100644 index 00000000000..09355d333c0 --- /dev/null +++ b/arch/blackfin/include/mach-common/ports-g.h @@ -0,0 +1,25 @@ +/* + * Port G Masks + */ + +#ifndef __BFIN_PERIPHERAL_PORT_G__ +#define __BFIN_PERIPHERAL_PORT_G__ + +#define PG0 (1 << 0) +#define PG1 (1 << 1) +#define PG2 (1 << 2) +#define PG3 (1 << 3) +#define PG4 (1 << 4) +#define PG5 (1 << 5) +#define PG6 (1 << 6) +#define PG7 (1 << 7) +#define PG8 (1 << 8) +#define PG9 (1 << 9) +#define PG10 (1 << 10) +#define PG11 (1 << 11) +#define PG12 (1 << 12) +#define PG13 (1 << 13) +#define PG14 (1 << 14) +#define PG15 (1 << 15) + +#endif diff --git a/arch/blackfin/include/mach-common/ports-h.h b/arch/blackfin/include/mach-common/ports-h.h new file mode 100644 index 00000000000..fa3910c6fbd --- /dev/null +++ b/arch/blackfin/include/mach-common/ports-h.h @@ -0,0 +1,25 @@ +/* + * Port H Masks + */ + +#ifndef __BFIN_PERIPHERAL_PORT_H__ +#define __BFIN_PERIPHERAL_PORT_H__ + +#define PH0 (1 << 0) +#define PH1 (1 << 1) +#define PH2 (1 << 2) +#define PH3 (1 << 3) +#define PH4 (1 << 4) +#define PH5 (1 << 5) +#define PH6 (1 << 6) +#define PH7 (1 << 7) +#define PH8 (1 << 8) +#define PH9 (1 << 9) +#define PH10 (1 << 10) +#define PH11 (1 << 11) +#define PH12 (1 << 12) +#define PH13 (1 << 13) +#define PH14 (1 << 14) +#define PH15 (1 << 15) + +#endif diff --git a/arch/blackfin/include/mach-common/ports-i.h b/arch/blackfin/include/mach-common/ports-i.h new file mode 100644 index 00000000000..f176f08af62 --- /dev/null +++ b/arch/blackfin/include/mach-common/ports-i.h @@ -0,0 +1,25 @@ +/* + * Port I Masks + */ + +#ifndef __BFIN_PERIPHERAL_PORT_I__ +#define __BFIN_PERIPHERAL_PORT_I__ + +#define PI0 (1 << 0) +#define PI1 (1 << 1) +#define PI2 (1 << 2) +#define PI3 (1 << 3) +#define PI4 (1 << 4) +#define PI5 (1 << 5) +#define PI6 (1 << 6) +#define PI7 (1 << 7) +#define PI8 (1 << 8) +#define PI9 (1 << 9) +#define PI10 (1 << 10) +#define PI11 (1 << 11) +#define PI12 (1 << 12) +#define PI13 (1 << 13) +#define PI14 (1 << 14) +#define PI15 (1 << 15) + +#endif diff --git a/arch/blackfin/include/mach-common/ports-j.h b/arch/blackfin/include/mach-common/ports-j.h new file mode 100644 index 00000000000..924123ecec5 --- /dev/null +++ b/arch/blackfin/include/mach-common/ports-j.h @@ -0,0 +1,25 @@ +/* + * Port J Masks + */ + +#ifndef __BFIN_PERIPHERAL_PORT_J__ +#define __BFIN_PERIPHERAL_PORT_J__ + +#define PJ0 (1 << 0) +#define PJ1 (1 << 1) +#define PJ2 (1 << 2) +#define PJ3 (1 << 3) +#define PJ4 (1 << 4) +#define PJ5 (1 << 5) +#define PJ6 (1 << 6) +#define PJ7 (1 << 7) +#define PJ8 (1 << 8) +#define PJ9 (1 << 9) +#define PJ10 (1 << 10) +#define PJ11 (1 << 11) +#define PJ12 (1 << 12) +#define PJ13 (1 << 13) +#define PJ14 (1 << 14) +#define PJ15 (1 << 15) + +#endif diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c index bfe75af4e8b..886e00014d7 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c @@ -116,7 +116,7 @@ void __init generate_cplb_tables_all(void) ((_ramend - uncached_end) >= 1 * 1024 * 1024)) dcplb_bounds[i_d].eaddr = uncached_end; else - dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024); + dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024 - 1); dcplb_bounds[i_d++].data = SDRAM_DGENERIC; /* DMA uncached region. */ if (DMA_UNCACHED_REGION) { diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c index edae461b1c5..eb92592fd80 100644 --- a/arch/blackfin/kernel/kgdb.c +++ b/arch/blackfin/kernel/kgdb.c @@ -345,6 +345,23 @@ void kgdb_roundup_cpu(int cpu, unsigned long flags) } #endif +#ifdef CONFIG_IPIPE +static unsigned long kgdb_arch_imask; +#endif + +void kgdb_post_primary_code(struct pt_regs *regs, int e_vector, int err_code) +{ + if (kgdb_single_step) + preempt_enable(); + +#ifdef CONFIG_IPIPE + if (kgdb_arch_imask) { + cpu_pda[raw_smp_processor_id()].ex_imask = kgdb_arch_imask; + kgdb_arch_imask = 0; + } +#endif +} + int kgdb_arch_handle_exception(int vector, int signo, int err_code, char *remcom_in_buffer, char *remcom_out_buffer, @@ -388,6 +405,12 @@ int kgdb_arch_handle_exception(int vector, int signo, * kgdb_single_step > 0 means in single step mode */ kgdb_single_step = i + 1; + + preempt_disable(); +#ifdef CONFIG_IPIPE + kgdb_arch_imask = cpu_pda[raw_smp_processor_id()].ex_imask; + cpu_pda[raw_smp_processor_id()].ex_imask = 0; +#endif } bfin_correct_hw_break(); @@ -448,6 +471,9 @@ void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long ip) int kgdb_arch_init(void) { kgdb_single_step = 0; +#ifdef CONFIG_IPIPE + kgdb_arch_imask = 0; +#endif bfin_remove_all_hw_break(); return 0; diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c index 08c0236acf3..2a6e9dbb62a 100644 --- a/arch/blackfin/kernel/kgdb_test.c +++ b/arch/blackfin/kernel/kgdb_test.c @@ -95,6 +95,10 @@ static int __init kgdbtest_init(void) { struct proc_dir_entry *entry; +#if L2_LENGTH + num2 = 0; +#endif + entry = proc_create("kgdbtest", 0, NULL, &kgdb_test_proc_fops); if (entry == NULL) return -ENOMEM; diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c index b894c8abe7e..c0ccadcfa44 100644 --- a/arch/blackfin/mach-bf518/boards/ezbrd.c +++ b/arch/blackfin/mach-bf518/boards/ezbrd.c @@ -104,24 +104,23 @@ static const unsigned short bfin_mac_peripherals[] = { static struct bfin_phydev_platform_data bfin_phydev_data[] = { { - .addr = 1, - .irq = IRQ_MAC_PHYINT, - }, - { - .addr = 2, - .irq = IRQ_MAC_PHYINT, - }, - { +#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) .addr = 3, +#else + .addr = 1, +#endif .irq = IRQ_MAC_PHYINT, }, }; static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { - .phydev_number = 3, + .phydev_number = 1, .phydev_data = bfin_phydev_data, .phy_mode = PHY_INTERFACE_MODE_MII, .mac_peripherals = bfin_mac_peripherals, +#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) + .phy_mask = 0xfff7, /* Only probe the port phy connect to the on chip MAC */ +#endif }; static struct platform_device bfin_mii_bus = { @@ -453,7 +452,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -496,7 +495,7 @@ static struct resource bfin_uart1_resources[] = { }, }; -unsigned short bfin_uart1_peripherals[] = { +static unsigned short bfin_uart1_peripherals[] = { P_UART1_TX, P_UART1_RX, 0 }; @@ -636,9 +635,9 @@ static struct resource bfin_sport0_uart_resources[] = { }, }; -unsigned short bfin_sport0_peripherals[] = { +static unsigned short bfin_sport0_peripherals[] = { P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 }; static struct platform_device bfin_sport0_uart_device = { @@ -670,9 +669,9 @@ static struct resource bfin_sport1_uart_resources[] = { }, }; -unsigned short bfin_sport1_peripherals[] = { +static unsigned short bfin_sport1_peripherals[] = { P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c index e6ce1d7c523..50fc5c89e37 100644 --- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c +++ b/arch/blackfin/mach-bf518/boards/tcm-bf518.c @@ -377,7 +377,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -420,7 +420,7 @@ static struct resource bfin_uart1_resources[] = { }, }; -unsigned short bfin_uart1_peripherals[] = { +static unsigned short bfin_uart1_peripherals[] = { P_UART1_TX, P_UART1_RX, 0 }; @@ -547,9 +547,9 @@ static struct resource bfin_sport0_uart_resources[] = { }, }; -unsigned short bfin_sport0_peripherals[] = { +static unsigned short bfin_sport0_peripherals[] = { P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 }; static struct platform_device bfin_sport0_uart_device = { @@ -581,9 +581,9 @@ static struct resource bfin_sport1_uart_resources[] = { }, }; -unsigned short bfin_sport1_peripherals[] = { +static unsigned short bfin_sport1_peripherals[] = { P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { diff --git a/arch/blackfin/mach-bf518/dma.c b/arch/blackfin/mach-bf518/dma.c index 78b43605a0b..bcd1fbc8c54 100644 --- a/arch/blackfin/mach-bf518/dma.c +++ b/arch/blackfin/mach-bf518/dma.c @@ -11,7 +11,7 @@ #include <asm/blackfin.h> #include <asm/dma.h> -struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { +struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { (struct dma_register *) DMA0_NEXT_DESC_PTR, (struct dma_register *) DMA1_NEXT_DESC_PTR, (struct dma_register *) DMA2_NEXT_DESC_PTR, diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial.h new file mode 100644 index 00000000000..00c603fe821 --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial.h @@ -0,0 +1,14 @@ +/* + * mach/bfin_serial.h - Blackfin UART/Serial definitions + * + * Copyright 2006-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_MACH_SERIAL_H__ +#define __BFIN_MACH_SERIAL_H__ + +#define BFIN_UART_NR_PORTS 2 + +#endif diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h index 970d310021e..f6d924ac0c4 100644 --- a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h @@ -4,36 +4,9 @@ * Licensed under the GPL-2 or later */ -#include <linux/serial.h> #include <asm/dma.h> #include <asm/portmux.h> -#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) -#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) -#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) -#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) -#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) -#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) -#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) - -#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v) -#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v) -#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v) -#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) -#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) -#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v) -#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v) -#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v) - -#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) -#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) - -#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) -#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) -#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) -#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) -#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) - #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) # define CONFIG_SERIAL_BFIN_CTSRTS @@ -54,50 +27,6 @@ # endif #endif -#define BFIN_UART_TX_FIFO_SIZE 2 - -/* - * The pin configuration is different from schematic - */ -struct bfin_serial_port { - struct uart_port port; - unsigned int old_status; - int status_irq; - unsigned int lsr; -#ifdef CONFIG_SERIAL_BFIN_DMA - int tx_done; - int tx_count; - struct circ_buf rx_dma_buf; - struct timer_list rx_dma_timer; - int rx_dma_nrows; - unsigned int tx_dma_channel; - unsigned int rx_dma_channel; - struct work_struct tx_dma_workqueue; -#endif -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - struct timer_list cts_timer; - int cts_pin; - int rts_pin; -#endif -}; - -/* The hardware clears the LSR bits upon read, so we need to cache - * some of the more fun bits in software so they don't get lost - * when checking the LSR in other code paths (TX). - */ -static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart) -{ - unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR); - uart->lsr |= (lsr & (BI|FE|PE|OE)); - return lsr | uart->lsr; -} - -static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) -{ - uart->lsr = 0; - bfin_write16(uart->port.membase + OFFSET_LSR, -1); -} - struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; @@ -146,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = { }; #define DRIVER_NAME "bfin-uart" + +#include <asm/bfin_serial.h> diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h index 9053462be4b..a8828863226 100644 --- a/arch/blackfin/mach-bf518/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf518/include/mach/blackfin.h @@ -1,61 +1,43 @@ /* - * Copyright 2008-2009 Analog Devices Inc. + * Copyright 2008-2010 Analog Devices Inc. * - * Licensed under the GPL-2 or later + * Licensed under the GPL-2 or later. */ #ifndef _MACH_BLACKFIN_H_ #define _MACH_BLACKFIN_H_ #include "bf518.h" -#include "defBF512.h" #include "anomaly.h" -#if defined(CONFIG_BF518) -#include "defBF518.h" +#include <asm/def_LPBlackfin.h> +#ifdef CONFIG_BF512 +# include "defBF512.h" #endif - -#if defined(CONFIG_BF516) -#include "defBF516.h" -#endif - -#if defined(CONFIG_BF514) -#include "defBF514.h" +#ifdef CONFIG_BF514 +# include "defBF514.h" #endif - -#if defined(CONFIG_BF512) -#include "defBF512.h" +#ifdef CONFIG_BF516 +# include "defBF516.h" #endif - -#if !defined(__ASSEMBLY__) -#include "cdefBF512.h" - -#if defined(CONFIG_BF518) -#include "cdefBF518.h" +#ifdef CONFIG_BF518 +# include "defBF518.h" #endif -#if defined(CONFIG_BF516) -#include "cdefBF516.h" +#ifndef __ASSEMBLY__ +# include <asm/cdef_LPBlackfin.h> +# ifdef CONFIG_BF512 +# include "cdefBF512.h" +# endif +# ifdef CONFIG_BF514 +# include "cdefBF514.h" +# endif +# ifdef CONFIG_BF516 +# include "cdefBF516.h" +# endif +# ifdef CONFIG_BF518 +# include "cdefBF518.h" +# endif #endif -#if defined(CONFIG_BF514) -#include "cdefBF514.h" -#endif -#endif - -#define BFIN_UART_NR_PORTS 2 - -#define OFFSET_THR 0x00 /* Transmit Holding register */ -#define OFFSET_RBR 0x00 /* Receive Buffer register */ -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_IER 0x04 /* Interrupt Enable Register */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_GCTL 0x24 /* Global Control Register */ - #endif diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h index 493020d0a65..b657d37a340 100644 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h +++ b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Analog Devices Inc. + * Copyright 2008-2010 Analog Devices Inc. * * Licensed under the ADI BSD license or the GPL-2 (or later) */ @@ -7,15 +7,1037 @@ #ifndef _CDEF_BF512_H #define _CDEF_BF512_H -/* include all Core registers and bit definitions */ -#include "defBF512.h" +/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ +#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) +#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) +#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) +#define bfin_read_VR_CTL() bfin_read16(VR_CTL) +#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) +#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) +#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) +#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) +#define bfin_read_CHIPID() bfin_read32(CHIPID) +#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -/* include core specific register pointer definitions */ -#include <asm/cdef_LPBlackfin.h> -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */ +/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ +#define bfin_read_SWRST() bfin_read16(SWRST) +#define bfin_write_SWRST(val) bfin_write16(SWRST, val) +#define bfin_read_SYSCR() bfin_read16(SYSCR) +#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ -#include "cdefBF51x_base.h" +#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) +#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) +#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) +#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) +#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6)) +#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val) + +#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) +#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) +#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) +#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) +#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) +#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) +#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) +#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) + +#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) +#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) +#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6)) +#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val) + +#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) +#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) +#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6)) +#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val) + +/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */ + +#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) +#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) +#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) +#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) +#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) +#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) +#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) +#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) +#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) +#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) +#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) +#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) +#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) +#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) + +/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ +#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) +#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) +#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) +#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) +#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) +#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) + + +/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ +#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) +#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) +#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) +#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) +#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) +#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) +#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) +#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) +#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) +#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) +#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) +#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val) +#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) +#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) + + +/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ +#define bfin_read_UART0_THR() bfin_read16(UART0_THR) +#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) +#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) +#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) +#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) +#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) +#define bfin_read_UART0_IER() bfin_read16(UART0_IER) +#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) +#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) +#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) +#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) +#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) +#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) +#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) +#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) +#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) +#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) +#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) +#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) +#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) +#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) +#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) +#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) +#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) + + +/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ +#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) +#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) +#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) +#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) +#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) +#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) +#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) +#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) + +#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) +#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) +#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) +#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) +#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) +#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) +#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) +#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) + +#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) +#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) +#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) +#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) +#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) +#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) +#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) +#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) + +#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) +#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) +#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) +#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) +#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) +#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) +#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) +#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) + +#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) +#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) +#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) +#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) +#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) +#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) +#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) +#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) + +#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) +#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) +#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) +#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) +#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) +#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) +#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) +#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) + +#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) +#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) +#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) +#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) +#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) +#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) +#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) +#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) + +#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) +#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) +#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) +#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) +#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) +#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) +#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) +#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) + +#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) +#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) +#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) +#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) +#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) +#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) + + +/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ +#define bfin_read_PORTFIO() bfin_read16(PORTFIO) +#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) +#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) +#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) +#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) +#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) +#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) +#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) +#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) +#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) +#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) +#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) +#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) +#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) +#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) +#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) +#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) +#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) +#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) +#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) +#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) +#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) +#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) +#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) +#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) +#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) +#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) +#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) +#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) +#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) +#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) +#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) +#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) +#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) + + +/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ +#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) +#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) +#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) +#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) +#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) +#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) +#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) +#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) +#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) +#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) +#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) +#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val) +#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) +#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val) +#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) +#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) +#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) +#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) +#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) +#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) +#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) +#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) +#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) +#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) +#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) +#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) +#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) +#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) +#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) +#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) +#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) +#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) +#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) +#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) +#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) +#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) +#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) +#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) +#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) +#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) +#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) +#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) +#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) +#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) +#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) +#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) + + +/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ +#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) +#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) +#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) +#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) +#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) +#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) +#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) +#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) +#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) +#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) +#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) +#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) +#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) +#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val) +#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) +#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val) +#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) +#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val) +#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) +#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val) +#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) +#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) +#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) +#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) +#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) +#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) +#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) +#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) +#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) +#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) +#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) +#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) +#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) +#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) +#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) +#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) +#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) +#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) +#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) +#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) +#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) +#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) +#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) +#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) +#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) +#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) +#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) +#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) +#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) +#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) +#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) +#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) + + +/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ +#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) +#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) +#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) +#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) +#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) +#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) +#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) +#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) +#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) +#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) +#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) +#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) +#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) +#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) + + +/* DMA Traffic Control Registers */ +#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER) +#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val) +#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT) +#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val) + +/* DMA Controller */ +#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) +#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) +#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) +#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) +#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) +#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) +#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) +#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) +#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) +#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) +#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) +#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) +#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) +#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) +#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) +#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) +#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) +#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) +#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) +#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) +#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) +#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) +#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) +#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) +#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) +#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) + +#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) +#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) +#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) +#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) +#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) +#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) +#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) +#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) +#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) +#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) +#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) +#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) +#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) +#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) +#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) +#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) +#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) +#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) +#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) +#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) +#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) +#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) +#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) +#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) +#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) + +#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) +#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) +#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) +#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) +#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) +#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) +#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) +#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) +#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) +#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) +#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) +#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) +#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) +#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) +#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) +#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) +#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) +#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) +#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) +#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) +#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) +#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) +#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) +#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) +#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) + +#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) +#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) +#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) +#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) +#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) +#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) +#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) +#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) +#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) +#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) +#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) +#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) +#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) +#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) +#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) +#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) +#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) +#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) +#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) +#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) +#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) +#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) +#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) +#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) +#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) +#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) + +#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) +#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) +#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) +#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) +#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) +#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) +#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) +#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) +#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) +#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) +#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) +#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) +#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) +#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) +#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) +#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) +#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) +#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) +#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) +#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) +#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) +#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) +#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) +#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) +#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) +#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) + +#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) +#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) +#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) +#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) +#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) +#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) +#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) +#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) +#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) +#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) +#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) +#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) +#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) +#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) +#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) +#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) +#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) +#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) +#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) +#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) +#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) +#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) +#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) +#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) +#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) +#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) + +#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) +#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) +#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) +#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) +#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) +#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) +#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) +#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) +#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) +#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) +#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) +#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) +#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) +#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) +#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) +#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) +#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) +#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) +#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) +#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) +#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) +#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) +#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) +#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) +#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) +#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) + +#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) +#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) +#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) +#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) +#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) +#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) +#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) +#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) +#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) +#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) +#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) +#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) +#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) +#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) +#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) +#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) +#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) +#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) +#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) +#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) +#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) +#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) +#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) +#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) +#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) +#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) + +#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) +#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) +#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) +#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) +#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) +#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) +#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) +#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) +#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) +#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) +#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) +#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) +#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) +#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) +#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) +#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) +#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) +#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) +#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) +#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) +#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) +#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) +#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) +#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) +#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) +#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) + +#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) +#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) +#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) +#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) +#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) +#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) +#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) +#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) +#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) +#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) +#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) +#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) +#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) +#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) +#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) +#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) +#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) +#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) +#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) +#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) +#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) +#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) +#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) +#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) +#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) +#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) + +#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) +#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) +#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) +#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) +#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) +#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) +#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) +#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) +#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) +#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) +#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) +#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) +#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) +#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) +#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) +#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) +#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) +#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) +#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) +#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) +#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) +#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) +#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) +#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) +#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) +#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) + +#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) +#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) +#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) +#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) +#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) +#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) +#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) +#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) +#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) +#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) +#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) +#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) +#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) +#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) +#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) +#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) +#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) +#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) +#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) +#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) +#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) +#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) +#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) +#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) +#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) +#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) + +#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) +#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) +#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) +#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) +#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) +#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) +#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) +#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) +#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) +#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) +#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) +#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) +#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) +#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) +#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) +#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) +#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) +#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) +#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) +#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) +#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) +#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) +#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) +#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) + +#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) +#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) +#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) +#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) +#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) +#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) +#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) +#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) +#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) +#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) +#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) +#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) +#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) +#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) +#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) +#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) +#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) +#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) +#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) +#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) +#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) +#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) +#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) + +#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) +#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) +#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) +#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) +#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) +#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) +#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) +#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) +#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) +#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) +#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) +#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) +#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) +#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) +#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) +#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) +#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) +#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) +#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) +#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) +#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) +#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) +#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) +#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) + +#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) +#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) +#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) +#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) +#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) +#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) +#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) +#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) +#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) +#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) +#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) +#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) +#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) +#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) +#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) +#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) +#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) +#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) +#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) +#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) +#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) +#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) +#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) + + +/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ +#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) +#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) +#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) +#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) +#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF) +#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) +#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) +#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) +#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) +#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) +#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) + + +/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ + +/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ +#define bfin_read_PORTGIO() bfin_read16(PORTGIO) +#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) +#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) +#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) +#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) +#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) +#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) +#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) +#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) +#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) +#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) +#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) +#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) +#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) +#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) +#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) +#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) +#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) +#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) +#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) +#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) +#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) +#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) +#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) +#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) +#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) +#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) +#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) +#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) +#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) +#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) +#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) +#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) +#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) + + +/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ +#define bfin_read_PORTHIO() bfin_read16(PORTHIO) +#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) +#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) +#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) +#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) +#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) +#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) +#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) +#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) +#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) +#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) +#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) +#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) +#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) +#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) +#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) +#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) +#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) +#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) +#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) +#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) +#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) +#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) +#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) +#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) +#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) +#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) +#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) +#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) +#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) +#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) +#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) +#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) +#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) + + +/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ +#define bfin_read_UART1_THR() bfin_read16(UART1_THR) +#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) +#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) +#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) +#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) +#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) +#define bfin_read_UART1_IER() bfin_read16(UART1_IER) +#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) +#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) +#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) +#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) +#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) +#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) +#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) +#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) +#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) +#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) +#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) +#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) +#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) +#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) +#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) +#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) +#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) + +/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */ + +/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ +#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) +#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) +#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) +#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) +#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) +#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) +#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX) +#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val) + + +/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ +#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) +#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) +#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) +#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) +#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) +#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) +#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) +#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) +#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) +#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) +#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) +#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) +#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) +#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) + +#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) +#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) +#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) +#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) +#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) +#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) +#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) +#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) +#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) +#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) +#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) +#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) +#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) +#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) + +/* ==== end from cdefBF534.h ==== */ + +/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ + +#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) +#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) +#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) +#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) +#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) +#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) + +#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) +#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) +#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) +#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) +#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) +#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) +#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW) +#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val) +#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW) +#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) +#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) +#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) +#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS) +#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val) +#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS) +#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val) +#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS) +#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val) +#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE) +#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val) +#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW) +#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val) +#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS) +#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val) + +/* HOST Port Registers */ + +#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) +#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) +#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) +#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) +#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) +#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) + +/* Counter Registers */ + +#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) +#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) +#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) +#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) +#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) +#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) +#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) +#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) +#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) +#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) +#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) +#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) +#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) +#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) +#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) +#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) + +/* Security Registers */ + +#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) +#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) +#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) +#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) +#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) +#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) #endif /* _CDEF_BF512_H */ diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h index 108fa4bde27..dc988668203 100644 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h +++ b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Analog Devices Inc. + * Copyright 2008-2010 Analog Devices Inc. * * Licensed under the ADI BSD license or the GPL-2 (or later) */ @@ -7,9 +7,6 @@ #ifndef _CDEF_BF514_H #define _CDEF_BF514_H -/* include all Core registers and bit definitions */ -#include "defBF514.h" - /* BF514 is BF512 + RSI */ #include "cdefBF512.h" diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h index 2751592ef1c..142e45cbc25 100644 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h +++ b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Analog Devices Inc. + * Copyright 2008-2010 Analog Devices Inc. * * Licensed under the ADI BSD license or the GPL-2 (or later) */ @@ -7,9 +7,6 @@ #ifndef _CDEF_BF516_H #define _CDEF_BF516_H -/* include all Core registers and bit definitions */ -#include "defBF516.h" - /* BF516 is BF514 + EMAC */ #include "cdefBF514.h" diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h index 7fb7f0eab99..e638197bf8b 100644 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h +++ b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Analog Devices Inc. + * Copyright 2008-2010 Analog Devices Inc. * * Licensed under the ADI BSD license or the GPL-2 (or later) */ @@ -7,9 +7,6 @@ #ifndef _CDEF_BF518_H #define _CDEF_BF518_H -/* include all Core registers and bit definitions */ -#include "defBF518.h" - /* BF518 is BF516 + IEEE-1588 */ #include "cdefBF516.h" diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h deleted file mode 100644 index e16969f24ff..00000000000 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h +++ /dev/null @@ -1,1061 +0,0 @@ -/* - * Copyright 2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _CDEF_BF52X_H -#define _CDEF_BF52X_H - -#include <asm/blackfin.h> - -#include "defBF51x_base.h" - -/* Include core specific register pointer definitions */ -#include <asm/cdef_LPBlackfin.h> - -/* ==== begin from cdefBF534.h ==== */ - -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) - - -/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) - -#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) -#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) -#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) -#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) -#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6)) -#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val) - -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) - -#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) -#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) -#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6)) -#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val) - -#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) -#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) -#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6)) -#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val) - -/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */ - -#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) -#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) -#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) -#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) -#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) -#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) -#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) -#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) -#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) -#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) -#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) -#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) -#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) -#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) - -/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) - - -/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) -#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val) -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) - - -/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ -#define bfin_read_UART0_THR() bfin_read16(UART0_THR) -#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) -#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) -#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define bfin_read_UART0_IER() bfin_read16(UART0_IER) -#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) -#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) -#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) -#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) -#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) -#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) -#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) -#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) -#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) -#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) -#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) - - -/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) - -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) - -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) - -#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) -#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) -#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) -#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) -#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) - -#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) -#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) -#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) -#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) -#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) - -#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) -#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) -#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) -#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) -#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) - -#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) -#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) -#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) -#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) -#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) - -#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) -#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) -#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) -#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) -#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) - -#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) -#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) -#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) -#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) -#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) -#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) - - -/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ -#define bfin_read_PORTFIO() bfin_read16(PORTFIO) -#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) -#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) -#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) -#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) -#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) -#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) -#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) -#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) -#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) -#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) -#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) -#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) -#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) -#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) -#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) -#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) -#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) -#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) -#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) -#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) -#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) -#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) -#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) -#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) -#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) -#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) -#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) -#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) -#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) -#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) -#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) -#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) -#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) - - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val) -#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val) -#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) -#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val) -#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) -#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val) -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) -#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) -#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) -#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) -#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) -#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) -#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) -#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) -#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) - - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) -#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val) -#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val) -#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) -#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val) -#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) -#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val) -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) - - -/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) -#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) -#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) -#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) -#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) -#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) -#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) -#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) - - -/* DMA Traffic Control Registers */ -#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) -#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) -#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) -#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) - -/* Alternate deprecated register names (below) provided for backwards code compatibility */ -#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) -#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val) -#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) -#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val) - -/* DMA Controller */ -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) -#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) -#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) - -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) -#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) -#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) - -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) -#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) -#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) - -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) -#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) -#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) - -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) -#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) -#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) - -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) -#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) -#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) - -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) -#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) -#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) - -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) -#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) -#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) - -#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) -#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) -#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) -#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) -#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) -#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) -#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) -#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) -#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) -#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) -#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) -#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) -#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) -#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) -#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) -#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) -#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) -#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) - -#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) -#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) -#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) -#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) -#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) -#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) -#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) -#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) -#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) -#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) -#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) -#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) -#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) -#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) -#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) -#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) -#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) -#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) - -#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) -#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) -#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) -#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) -#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) -#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) -#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) -#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) -#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) -#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) -#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) -#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) -#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) -#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) -#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) -#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) -#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) -#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) - -#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) -#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) -#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) -#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) -#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) -#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) -#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) -#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) -#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) -#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) -#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) -#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) -#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) -#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) -#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) -#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) -#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) -#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) - -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) - -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) - -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) - -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) - - -/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ -#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) -#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) -#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) -#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) -#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF) -#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) -#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) -#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) -#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) -#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) -#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) - - -/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ - -/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ -#define bfin_read_PORTGIO() bfin_read16(PORTGIO) -#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) -#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) -#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) -#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) -#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) -#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) -#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) -#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) -#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) -#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) -#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) -#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) -#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) -#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) -#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) -#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) -#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) -#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) -#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) -#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) -#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) -#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) -#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) -#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) -#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) -#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) -#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) -#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) -#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) -#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) -#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) -#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) -#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) - - -/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ -#define bfin_read_PORTHIO() bfin_read16(PORTHIO) -#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) -#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) -#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) -#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) -#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) -#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) -#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) -#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) -#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) -#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) -#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) -#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) -#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) -#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) -#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) -#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) -#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) -#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) -#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) -#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) -#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) -#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) -#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) -#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) -#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) -#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) -#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) -#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) -#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) -#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) -#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) -#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) -#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) - - -/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ -#define bfin_read_UART1_THR() bfin_read16(UART1_THR) -#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) -#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) -#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define bfin_read_UART1_IER() bfin_read16(UART1_IER) -#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) -#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) -#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) -#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) -#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) -#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) -#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) -#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) -#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) -#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) -#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) - -/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */ - -/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ -#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) -#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) -#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) -#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX) -#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val) - - -/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ -#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) -#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) -#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) -#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) -#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) -#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) -#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) -#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) - -#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) -#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) -#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) -#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) -#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) -#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) -#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) -#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) - -/* ==== end from cdefBF534.h ==== */ - -/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ - -#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) -#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) -#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) -#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) -#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) -#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) - -#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) -#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) -#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) -#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) -#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) -#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) -#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW) -#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val) -#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW) -#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) -#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) -#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) -#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS) -#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val) -#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS) -#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val) -#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS) -#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val) -#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE) -#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val) -#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW) -#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val) -#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS) -#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val) - -/* HOST Port Registers */ - -#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) -#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) -#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) -#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) -#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) -#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) - -/* Counter Registers */ - -#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) -#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) -#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) -#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) -#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) -#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) -#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) -#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) -#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) -#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) -#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) -#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) -#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) -#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) -#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) -#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) - -/* Security Registers */ - -#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) -#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) -#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) -#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) -#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) -#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) - -/* These need to be last due to the cdef/linux inter-dependencies */ -#include <asm/irq.h> - -#endif /* _CDEF_BF52X_H */ diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h index 9b505bb0cb2..27285823fb2 100644 --- a/arch/blackfin/mach-bf518/include/mach/defBF512.h +++ b/arch/blackfin/mach-bf518/include/mach/defBF512.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Analog Devices Inc. + * Copyright 2008-2010 Analog Devices Inc. * * Licensed under the ADI BSD license or the GPL-2 (or later) */ @@ -7,12 +7,1388 @@ #ifndef _DEF_BF512_H #define _DEF_BF512_H -/* Include all Core registers and bit definitions */ -#include <asm/def_LPBlackfin.h> +/* ************************************************************** */ +/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x */ +/* ************************************************************** */ -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */ +/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ +#define PLL_CTL 0xFFC00000 /* PLL Control Register */ +#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ +#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ +#define PLL_STAT 0xFFC0000C /* PLL Status Register */ +#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ +#define CHIPID 0xFFC00014 /* Device ID Register */ -/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ -#include "defBF51x_base.h" +/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ +#define SWRST 0xFFC00100 /* Software Reset Register */ +#define SYSCR 0xFFC00104 /* System Configuration Register */ +#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ + +#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ +#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ +#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ +#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ +#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ + +/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */ +#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ +#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ +#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ +#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ +#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */ +#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */ +#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ + + +/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ +#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ +#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ +#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ + + +/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ +#define RTC_STAT 0xFFC00300 /* RTC Status Register */ +#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ +#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ +#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ +#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ +#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ +#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */ + + +/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ +#define UART0_THR 0xFFC00400 /* Transmit Holding register */ +#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ +#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ +#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ +#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ +#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ +#define UART0_LCR 0xFFC0040C /* Line Control Register */ +#define UART0_MCR 0xFFC00410 /* Modem Control Register */ +#define UART0_LSR 0xFFC00414 /* Line Status Register */ +#define UART0_MSR 0xFFC00418 /* Modem Status Register */ +#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ +#define UART0_GCTL 0xFFC00424 /* Global Control Register */ + +/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */ +#define SPI0_REGBASE 0xFFC00500 +#define SPI0_CTL 0xFFC00500 /* SPI Control Register */ +#define SPI0_FLG 0xFFC00504 /* SPI Flag register */ +#define SPI0_STAT 0xFFC00508 /* SPI Status register */ +#define SPI0_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ +#define SPI0_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ +#define SPI0_BAUD 0xFFC00514 /* SPI Baud rate Register */ +#define SPI0_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ + +/* SPI1 Controller (0xFFC03400 - 0xFFC034FF) */ +#define SPI1_REGBASE 0xFFC03400 +#define SPI1_CTL 0xFFC03400 /* SPI Control Register */ +#define SPI1_FLG 0xFFC03404 /* SPI Flag register */ +#define SPI1_STAT 0xFFC03408 /* SPI Status register */ +#define SPI1_TDBR 0xFFC0340C /* SPI Transmit Data Buffer Register */ +#define SPI1_RDBR 0xFFC03410 /* SPI Receive Data Buffer Register */ +#define SPI1_BAUD 0xFFC03414 /* SPI Baud rate Register */ +#define SPI1_SHADOW 0xFFC03418 /* SPI_RDBR Shadow Register */ + +/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ +#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ +#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ +#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ +#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ + +#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ +#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ +#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ +#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ + +#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ +#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ +#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ +#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ + +#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ +#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ +#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ +#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ + +#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ +#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ +#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ +#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ + +#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ +#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ +#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ +#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ + +#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ +#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ +#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ +#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */ + +#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ +#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ +#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ +#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ + +#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ +#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ +#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ + +/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ +#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ +#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ +#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ +#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ +#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ +#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ +#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ +#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ +#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ +#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ +#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ +#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ +#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ +#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ +#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ +#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ +#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ + +/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ +#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ +#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ +#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ +#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ +#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ +#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ +#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ + +/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ +#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ +#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ +#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ +#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ +#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ +#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ +#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ +#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ +#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ +#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ +#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ +#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ +#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ +#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ +#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ +#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ +#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ +#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ + +/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ +#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ +#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ +#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ +#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ +#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ +#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ +#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ + +/* DMA Traffic Control Registers */ +#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ +#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ + +/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ +#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ +#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ +#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ +#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ +#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ +#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ +#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ +#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ +#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ +#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ +#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ +#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ +#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ + +#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ +#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ +#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ +#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ +#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ +#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ +#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ +#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ +#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ +#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ +#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ +#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ +#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ + +#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ +#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ +#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ +#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ +#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ +#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ +#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ +#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ +#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ +#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ +#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ +#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ +#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ + +#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ +#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ +#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ +#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ +#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ +#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ +#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ +#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ +#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ +#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ +#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ +#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ +#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ + +#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ +#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ +#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ +#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ +#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ +#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ +#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ +#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ +#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ +#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ +#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ +#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ +#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ + +#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ +#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ +#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ +#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ +#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ +#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ +#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ +#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ +#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ +#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ +#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ +#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ +#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ + +#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ +#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ +#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ +#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ +#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ +#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ +#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ +#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ +#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ +#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ +#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ +#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ +#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ + +#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ +#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ +#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ +#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ +#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ +#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ +#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ +#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ +#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ +#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ +#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ +#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ +#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ + +#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ +#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ +#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ +#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ +#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ +#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ +#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ +#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ +#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ +#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ +#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ +#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ +#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ + +#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ +#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ +#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ +#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ +#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ +#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ +#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ +#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ +#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ +#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ +#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ +#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ +#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ + +#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ +#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ +#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ +#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ +#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ +#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ +#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ +#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ +#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ +#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ +#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ +#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ +#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ + +#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ +#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ +#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ +#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ +#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ +#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ +#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ +#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ +#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ +#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ +#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ +#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ +#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ + +#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ +#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ +#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ +#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ +#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ +#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ +#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ +#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ +#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ +#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ +#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ +#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ +#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ + +#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ +#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ +#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ +#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ +#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ +#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ +#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ +#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ +#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ +#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ +#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ +#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ +#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ + +#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ +#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ +#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ +#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ +#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ +#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ +#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ +#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ +#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ +#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ +#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ +#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ +#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ + +#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ +#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ +#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ +#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ +#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ +#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ +#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ +#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ +#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ +#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ +#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ +#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ +#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ + + +/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ +#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ +#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ +#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ +#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ +#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ + + +/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ +#define TWI0_REGBASE 0xFFC01400 +#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ +#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */ +#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ +#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ +#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ +#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ +#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ +#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ +#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ +#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ +#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ +#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ +#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ +#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ +#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ +#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ + + +/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ +#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ +#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ +#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ +#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ +#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ +#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ +#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ +#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ +#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ +#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ +#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ +#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ +#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ +#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ +#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ +#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ +#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ + + +/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ +#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ +#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ +#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ +#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ +#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ +#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ +#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ +#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ +#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ +#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ +#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ +#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ +#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ +#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ +#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ +#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ +#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ + + +/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ +#define UART1_THR 0xFFC02000 /* Transmit Holding register */ +#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ +#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ +#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ +#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ +#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ +#define UART1_LCR 0xFFC0200C /* Line Control Register */ +#define UART1_MCR 0xFFC02010 /* Modem Control Register */ +#define UART1_LSR 0xFFC02014 /* Line Status Register */ +#define UART1_MSR 0xFFC02018 /* Modem Status Register */ +#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ +#define UART1_GCTL 0xFFC02024 /* Global Control Register */ + + +/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ +#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ +#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ +#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ +#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ + + +/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ +#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ +#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ +#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ +#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */ +#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ +#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ +#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ + +#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ +#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ +#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ +#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */ +#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ +#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ +#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ + + +/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ +#define PORTF_MUX 0xFFC03210 /* Port F mux control */ +#define PORTG_MUX 0xFFC03214 /* Port G mux control */ +#define PORTH_MUX 0xFFC03218 /* Port H mux control */ +#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */ +#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */ +#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */ +#define PORTF_SLEW 0xFFC03230 /* Port F slew control */ +#define PORTG_SLEW 0xFFC03234 /* Port G slew control */ +#define PORTH_SLEW 0xFFC03238 /* Port H slew control */ +#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */ +#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */ +#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */ +#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */ +#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */ +#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */ + + +/*********************************************************************************** +** System MMR Register Bits And Macros +** +** Disclaimer: All macros are intended to make C and Assembly code more readable. +** Use these macros carefully, as any that do left shifts for field +** depositing will result in the lower order bits being destroyed. Any +** macro that shifts left to properly position the bit-field should be +** used as part of an OR to initialize a register and NOT as a dynamic +** modifier UNLESS the lower order bits are saved and ORed back in when +** the macro is used. +*************************************************************************************/ + +/* CHIPID Masks */ +#define CHIPID_VERSION 0xF0000000 +#define CHIPID_FAMILY 0x0FFFF000 +#define CHIPID_MANUFACTURE 0x00000FFE + +/* SWRST Masks */ +#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ +#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ +#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ +#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ +#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ + +/* SYSCR Masks */ +#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */ +#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ + + +/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ +/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ + +#if 0 +#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ + +#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ +#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */ +#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */ +#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */ +#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */ +#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */ +#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */ + +#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */ +#define IRQ_TWI 0x00000200 /* TWI Interrupt */ +#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */ +#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */ +#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */ +#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */ +#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */ +#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */ + +#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */ +#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */ +#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */ +#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */ +#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */ +#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */ +#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */ +#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */ +#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */ +#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */ + +#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */ +#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */ +#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */ +#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */ +#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */ +#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */ +#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */ +#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */ +#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */ +#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */ +#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */ +#endif + +/* SIC_IAR0 Macros */ +#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ +#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ +#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ +#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */ +#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ +#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ +#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ +#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ + +/* SIC_IAR1 Macros */ +#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */ +#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ +#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ +#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */ +#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ +#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ +#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ +#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ + +/* SIC_IAR2 Macros */ +#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */ +#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ +#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ +#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */ +#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ +#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ +#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ +#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ + +/* SIC_IAR3 Macros */ +#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */ +#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */ +#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */ +#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */ +#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */ +#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */ +#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */ +#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */ + + +/* SIC_IMASK Masks */ +#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ +#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ +#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ +#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ + +/* SIC_IWR Masks */ +#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ +#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ +#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ +#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ + +/* **************** GENERAL PURPOSE TIMER MASKS **********************/ +/* TIMER_ENABLE Masks */ +#define TIMEN0 0x0001 /* Enable Timer 0 */ +#define TIMEN1 0x0002 /* Enable Timer 1 */ +#define TIMEN2 0x0004 /* Enable Timer 2 */ +#define TIMEN3 0x0008 /* Enable Timer 3 */ +#define TIMEN4 0x0010 /* Enable Timer 4 */ +#define TIMEN5 0x0020 /* Enable Timer 5 */ +#define TIMEN6 0x0040 /* Enable Timer 6 */ +#define TIMEN7 0x0080 /* Enable Timer 7 */ + +/* TIMER_DISABLE Masks */ +#define TIMDIS0 TIMEN0 /* Disable Timer 0 */ +#define TIMDIS1 TIMEN1 /* Disable Timer 1 */ +#define TIMDIS2 TIMEN2 /* Disable Timer 2 */ +#define TIMDIS3 TIMEN3 /* Disable Timer 3 */ +#define TIMDIS4 TIMEN4 /* Disable Timer 4 */ +#define TIMDIS5 TIMEN5 /* Disable Timer 5 */ +#define TIMDIS6 TIMEN6 /* Disable Timer 6 */ +#define TIMDIS7 TIMEN7 /* Disable Timer 7 */ + +/* TIMER_STATUS Masks */ +#define TIMIL0 0x00000001 /* Timer 0 Interrupt */ +#define TIMIL1 0x00000002 /* Timer 1 Interrupt */ +#define TIMIL2 0x00000004 /* Timer 2 Interrupt */ +#define TIMIL3 0x00000008 /* Timer 3 Interrupt */ +#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ +#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ +#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ +#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ +#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ +#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ +#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ +#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ +#define TIMIL4 0x00010000 /* Timer 4 Interrupt */ +#define TIMIL5 0x00020000 /* Timer 5 Interrupt */ +#define TIMIL6 0x00040000 /* Timer 6 Interrupt */ +#define TIMIL7 0x00080000 /* Timer 7 Interrupt */ +#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ +#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ +#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ +#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ +#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ +#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ +#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ +#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ + +/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ +#define TOVL_ERR0 TOVF_ERR0 +#define TOVL_ERR1 TOVF_ERR1 +#define TOVL_ERR2 TOVF_ERR2 +#define TOVL_ERR3 TOVF_ERR3 +#define TOVL_ERR4 TOVF_ERR4 +#define TOVL_ERR5 TOVF_ERR5 +#define TOVL_ERR6 TOVF_ERR6 +#define TOVL_ERR7 TOVF_ERR7 + +/* TIMERx_CONFIG Masks */ +#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ +#define WDTH_CAP 0x0002 /* Width Capture Input Mode */ +#define EXT_CLK 0x0003 /* External Clock Mode */ +#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ +#define PERIOD_CNT 0x0008 /* Period Count */ +#define IRQ_ENA 0x0010 /* Interrupt Request Enable */ +#define TIN_SEL 0x0020 /* Timer Input Select */ +#define OUT_DIS 0x0040 /* Output Pad Disable */ +#define CLK_SEL 0x0080 /* Timer Clock Select */ +#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ +#define EMU_RUN 0x0200 /* Emulation Behavior Select */ +#define ERR_TYP 0xC000 /* Error Type */ + +/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ +/* EBIU_AMGCTL Masks */ +#define AMCKEN 0x0001 /* Enable CLKOUT */ +#define AMBEN_NONE 0x0000 /* All Banks Disabled */ +#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ +#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ +#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ +#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ + +/* EBIU_AMBCTL0 Masks */ +#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */ +#define B0RDYPOL 0x00000002 /* B0 RDY Active High */ +#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */ +#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */ +#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */ +#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */ +#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */ +#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */ +#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */ +#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */ +#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */ +#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */ +#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */ +#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */ +#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */ +#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */ +#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */ +#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */ +#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */ +#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */ +#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */ +#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */ +#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */ +#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */ +#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */ +#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */ +#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */ +#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */ +#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */ +#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */ +#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */ +#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */ +#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */ +#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */ +#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */ +#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */ +#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */ +#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */ +#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */ +#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */ +#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */ +#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */ +#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */ +#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */ + +#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */ +#define B1RDYPOL 0x00020000 /* B1 RDY Active High */ +#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */ +#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */ +#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */ +#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */ +#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */ +#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */ +#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */ +#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */ +#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */ +#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */ +#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */ +#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */ +#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */ +#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */ +#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */ +#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */ +#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */ +#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */ +#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */ +#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */ +#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */ +#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */ +#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */ +#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */ +#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */ +#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */ +#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */ +#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */ +#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */ +#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */ +#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */ +#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */ +#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */ +#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */ +#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */ +#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */ +#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */ +#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */ +#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */ +#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */ +#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */ +#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */ + +/* EBIU_AMBCTL1 Masks */ +#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */ +#define B2RDYPOL 0x00000002 /* B2 RDY Active High */ +#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */ +#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */ +#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */ +#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */ +#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */ +#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */ +#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */ +#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */ +#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */ +#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */ +#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */ +#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */ +#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */ +#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */ +#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */ +#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */ +#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */ +#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */ +#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */ +#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */ +#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */ +#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */ +#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */ +#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */ +#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */ +#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */ +#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */ +#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */ +#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */ +#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */ +#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */ +#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */ +#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */ +#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */ +#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */ +#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */ +#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */ +#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */ +#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */ +#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */ +#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */ +#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */ + +#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */ +#define B3RDYPOL 0x00020000 /* B3 RDY Active High */ +#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */ +#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */ +#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */ +#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */ +#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */ +#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */ +#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */ +#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */ +#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */ +#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */ +#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */ +#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */ +#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */ +#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */ +#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */ +#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */ +#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */ +#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */ +#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */ +#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */ +#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */ +#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */ +#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */ +#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */ +#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */ +#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */ +#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */ +#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */ +#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */ +#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */ +#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */ +#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */ +#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */ +#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */ +#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */ +#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */ +#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */ +#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */ +#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */ +#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */ +#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */ +#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */ + + +/* ********************** SDRAM CONTROLLER MASKS **********************************************/ +/* EBIU_SDGCTL Masks */ +#define SCTLE 0x00000001 /* Enable SDRAM Signals */ +#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */ +#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ +#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ +#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ +#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ +#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ +#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ +#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ +#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ +#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ +#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ +#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ +#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ +#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ +#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ +#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ +#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ +#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ +#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ +#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ +#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ +#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ +#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ +#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ +#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ +#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ +#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ +#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ +#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ +#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ +#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ +#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ +#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ +#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ +#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ +#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ +#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ +#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */ +#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */ +#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */ +#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */ +#define EBUFE 0x02000000 /* Enable External Buffering Timing */ +#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */ +#define EMREN 0x10000000 /* Extended Mode Register Enable */ +#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */ +#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */ + +/* EBIU_SDBCTL Masks */ +#define EBE 0x0001 /* Enable SDRAM External Bank */ +#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */ +#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ +#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ +#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ +#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */ +#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */ +#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ +#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ +#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ +#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */ + +/* EBIU_SDSTAT Masks */ +#define SDCI 0x0001 /* SDRAM Controller Idle */ +#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */ +#define SDPUA 0x0004 /* SDRAM Power-Up Active */ +#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */ +#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */ +#define BGSTAT 0x0020 /* Bus Grant Status */ + + +/* ************************** DMA CONTROLLER MASKS ********************************/ + +/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ +#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ +#define PMAP 0xF000 /* Peripheral Mapped To This Channel */ +#define PMAP_PPI 0x0000 /* PPI Port DMA */ +#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */ +#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */ +#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */ +#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */ +#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */ +#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */ +#define PMAP_SPI 0x7000 /* SPI Port DMA */ +#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */ +#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */ +#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ +#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ + +/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ +/* PPI_CONTROL Masks */ +#define PORT_EN 0x0001 /* PPI Port Enable */ +#define PORT_DIR 0x0002 /* PPI Port Direction */ +#define XFR_TYPE 0x000C /* PPI Transfer Type */ +#define PORT_CFG 0x0030 /* PPI Port Configuration */ +#define FLD_SEL 0x0040 /* PPI Active Field Select */ +#define PACK_EN 0x0080 /* PPI Packing Mode */ +#define DMA32 0x0100 /* PPI 32-bit DMA Enable */ +#define SKIP_EN 0x0200 /* PPI Skip Element Enable */ +#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ +#define DLEN_8 0x0000 /* Data Length = 8 Bits */ +#define DLEN_10 0x0800 /* Data Length = 10 Bits */ +#define DLEN_11 0x1000 /* Data Length = 11 Bits */ +#define DLEN_12 0x1800 /* Data Length = 12 Bits */ +#define DLEN_13 0x2000 /* Data Length = 13 Bits */ +#define DLEN_14 0x2800 /* Data Length = 14 Bits */ +#define DLEN_15 0x3000 /* Data Length = 15 Bits */ +#define DLEN_16 0x3800 /* Data Length = 16 Bits */ +#define DLENGTH 0x3800 /* PPI Data Length */ +#define POLC 0x4000 /* PPI Clock Polarity */ +#define POLS 0x8000 /* PPI Frame Sync Polarity */ + +/* PPI_STATUS Masks */ +#define FLD 0x0400 /* Field Indicator */ +#define FT_ERR 0x0800 /* Frame Track Error */ +#define OVR 0x1000 /* FIFO Overflow Error */ +#define UNDR 0x2000 /* FIFO Underrun Error */ +#define ERR_DET 0x4000 /* Error Detected Indicator */ +#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ + + +/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/ +/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ +#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ +#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ + +/* TWI_PRESCALE Masks */ +#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ +#define TWI_ENA 0x0080 /* TWI Enable */ +#define SCCB 0x0200 /* SCCB Compatibility Enable */ + +/* TWI_SLAVE_CTL Masks */ +#define SEN 0x0001 /* Slave Enable */ +#define SADD_LEN 0x0002 /* Slave Address Length */ +#define STDVAL 0x0004 /* Slave Transmit Data Valid */ +#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ +#define GEN 0x0010 /* General Call Adrress Matching Enabled */ + +/* TWI_SLAVE_STAT Masks */ +#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ +#define GCALL 0x0002 /* General Call Indicator */ + +/* TWI_MASTER_CTL Masks */ +#define MEN 0x0001 /* Master Mode Enable */ +#define MADD_LEN 0x0002 /* Master Address Length */ +#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ +#define FAST 0x0008 /* Use Fast Mode Timing Specs */ +#define STOP 0x0010 /* Issue Stop Condition */ +#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ +#define DCNT 0x3FC0 /* Data Bytes To Transfer */ +#define SDAOVR 0x4000 /* Serial Data Override */ +#define SCLOVR 0x8000 /* Serial Clock Override */ + +/* TWI_MASTER_STAT Masks */ +#define MPROG 0x0001 /* Master Transfer In Progress */ +#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ +#define ANAK 0x0004 /* Address Not Acknowledged */ +#define DNAK 0x0008 /* Data Not Acknowledged */ +#define BUFRDERR 0x0010 /* Buffer Read Error */ +#define BUFWRERR 0x0020 /* Buffer Write Error */ +#define SDASEN 0x0040 /* Serial Data Sense */ +#define SCLSEN 0x0080 /* Serial Clock Sense */ +#define BUSBUSY 0x0100 /* Bus Busy Indicator */ + +/* TWI_INT_SRC and TWI_INT_ENABLE Masks */ +#define SINIT 0x0001 /* Slave Transfer Initiated */ +#define SCOMP 0x0002 /* Slave Transfer Complete */ +#define SERR 0x0004 /* Slave Transfer Error */ +#define SOVF 0x0008 /* Slave Overflow */ +#define MCOMP 0x0010 /* Master Transfer Complete */ +#define MERR 0x0020 /* Master Transfer Error */ +#define XMTSERV 0x0040 /* Transmit FIFO Service */ +#define RCVSERV 0x0080 /* Receive FIFO Service */ + +/* TWI_FIFO_CTRL Masks */ +#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ +#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ +#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ +#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ + +/* TWI_FIFO_STAT Masks */ +#define XMTSTAT 0x0003 /* Transmit FIFO Status */ +#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ +#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ +#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ + +#define RCVSTAT 0x000C /* Receive FIFO Status */ +#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ +#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ +#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ + + +/* ******************* PIN CONTROL REGISTER MASKS ************************/ +/* PORT_MUX Masks */ +#define PJSE 0x0001 /* Port J SPI/SPORT Enable */ +#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */ +#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */ + +#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */ +#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */ +#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */ +#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */ + +#define PFDE 0x0008 /* Port F DMA Request Enable */ +#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */ +#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */ + +#define PFTE 0x0010 /* Port F Timer Enable */ +#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */ +#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */ + +#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */ +#define PFS6E_TIMER 0x0000 /* Enable TMR5 */ +#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */ + +#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */ +#define PFS5E_TIMER 0x0000 /* Enable TMR4 */ +#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */ + +#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */ +#define PFS4E_TIMER 0x0000 /* Enable TMR3 */ +#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */ + +#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */ +#define PFFE_TIMER 0x0000 /* Enable TMR2 */ +#define PFFE_PPI 0x0100 /* Enable PPI FS3 */ + +#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */ +#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */ +#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */ + +#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */ +#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */ +#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */ + +#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */ +#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ +#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ + + +/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/ +/* HDMAx_CTL Masks */ +#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */ +#define REP 0x0002 /* HDMA Request Polarity */ +#define UTE 0x0004 /* Urgency Threshold Enable */ +#define OIE 0x0010 /* Overflow Interrupt Enable */ +#define BDIE 0x0020 /* Block Done Interrupt Enable */ +#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */ +#define DRQ 0x0300 /* HDMA Request Type */ +#define DRQ_NONE 0x0000 /* No Request */ +#define DRQ_SINGLE 0x0100 /* Channels Request Single */ +#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */ +#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */ +#define RBC 0x1000 /* Reload BCNT With IBCNT */ +#define PS 0x2000 /* HDMA Pin Status */ +#define OI 0x4000 /* Overflow Interrupt Generated */ +#define BDI 0x8000 /* Block Done Interrupt Generated */ + +/* entry addresses of the user-callable Boot ROM functions */ + +#define _BOOTROM_RESET 0xEF000000 +#define _BOOTROM_FINAL_INIT 0xEF000002 +#define _BOOTROM_DO_MEMORY_DMA 0xEF000006 +#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 +#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A +#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C +#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 +#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 +#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 + +/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ +#define PGDE_UART PFDE_UART +#define PGDE_DMA PFDE_DMA +#define CKELOW SCKELOW + +/* HOST Port Registers */ + +#define HOST_CONTROL 0xffc03400 /* HOST Control Register */ +#define HOST_STATUS 0xffc03404 /* HOST Status Register */ +#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */ + +/* Counter Registers */ + +#define CNT_CONFIG 0xffc03500 /* Configuration Register */ +#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */ +#define CNT_STATUS 0xffc03508 /* Status Register */ +#define CNT_COMMAND 0xffc0350c /* Command Register */ +#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */ +#define CNT_COUNTER 0xffc03514 /* Counter Register */ +#define CNT_MAX 0xffc03518 /* Maximal Count Register */ +#define CNT_MIN 0xffc0351c /* Minimal Count Register */ + +/* OTP/FUSE Registers */ + +#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */ +#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */ +#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */ +#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */ + +/* Security Registers */ + +#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */ +#define SECURE_CONTROL 0xffc03624 /* Secure Control */ +#define SECURE_STATUS 0xffc03628 /* Secure Status */ + +/* OTP Read/Write Data Buffer Registers */ + +#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ +#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ +#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ +#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ + +/* Motor Control PWM Registers */ + +#define PWM_CTRL 0xffc03700 /* PWM Control Register */ +#define PWM_STAT 0xffc03704 /* PWM Status Register */ +#define PWM_TM 0xffc03708 /* PWM Period Register */ +#define PWM_DT 0xffc0370c /* PWM Dead Time Register */ +#define PWM_GATE 0xffc03710 /* PWM Chopping Control */ +#define PWM_CHA 0xffc03714 /* PWM Channel A Duty Control */ +#define PWM_CHB 0xffc03718 /* PWM Channel B Duty Control */ +#define PWM_CHC 0xffc0371c /* PWM Channel C Duty Control */ +#define PWM_SEG 0xffc03720 /* PWM Crossover and Output Enable */ +#define PWM_SYNCWT 0xffc03724 /* PWM Sync Pluse Width Control */ +#define PWM_CHAL 0xffc03728 /* PWM Channel AL Duty Control (SR mode only) */ +#define PWM_CHBL 0xffc0372c /* PWM Channel BL Duty Control (SR mode only) */ +#define PWM_CHCL 0xffc03730 /* PWM Channel CL Duty Control (SR mode only) */ +#define PWM_LSI 0xffc03734 /* PWM Low Side Invert (SR mode only) */ +#define PWM_STAT2 0xffc03738 /* PWM Status Register 2 */ + + +/* ********************************************************** */ +/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ +/* and MULTI BIT READ MACROS */ +/* ********************************************************** */ + +/* Bit masks for HOST_CONTROL */ + +#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */ +#define HOST_CNTR_nHOST_EN 0x0 +#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */ +#define HOST_CNTR_nHOST_END 0x0 +#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */ +#define HOST_CNTR_nDATA_SIZE 0x0 +#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */ +#define HOST_CNTR_nHOST_RST 0x0 +#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */ +#define HOST_CNTR_nHRDY_OVR 0x0 +#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */ +#define HOST_CNTR_nINT_MODE 0x0 +#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */ +#define HOST_CNTR_ nBT_EN 0x0 +#define HOST_CNTR_EHW 0x100 /* Enable Host Write */ +#define HOST_CNTR_nEHW 0x0 +#define HOST_CNTR_EHR 0x200 /* Enable Host Read */ +#define HOST_CNTR_nEHR 0x0 +#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */ +#define HOST_CNTR_nBDR 0x0 + +/* Bit masks for HOST_STATUS */ + +#define HOST_STAT_READY 0x1 /* DMA Ready */ +#define HOST_STAT_nREADY 0x0 +#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */ +#define HOST_STAT_nFIFOFULL 0x0 +#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */ +#define HOST_STAT_nFIFOEMPTY 0x0 +#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */ +#define HOST_STAT_nCOMPLETE 0x0 +#define HOST_STAT_HSHK 0x10 /* Host Handshake */ +#define HOST_STAT_nHSHK 0x0 +#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */ +#define HOST_STAT_nTIMEOUT 0x0 +#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */ +#define HOST_STAT_nHIRQ 0x0 +#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */ +#define HOST_STAT_nALLOW_CNFG 0x0 +#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */ +#define HOST_STAT_nDMA_DIR 0x0 +#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */ +#define HOST_STAT_nBTE 0x0 +#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */ +#define HOST_STAT_nHOSTRD_DONE 0x0 + +/* Bit masks for HOST_TIMEOUT */ + +#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */ + +/* Bit masks for SECURE_SYSSWT */ + +#define EMUDABL 0x1 /* Emulation Disable. */ +#define nEMUDABL 0x0 +#define RSTDABL 0x2 /* Reset Disable */ +#define nRSTDABL 0x0 +#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ +#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ +#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ +#define DMA0OVR 0x800 /* DMA0 Memory Access Override */ +#define nDMA0OVR 0x0 +#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ +#define nDMA1OVR 0x0 +#define EMUOVR 0x4000 /* Emulation Override */ +#define nEMUOVR 0x0 +#define OTPSEN 0x8000 /* OTP Secrets Enable. */ +#define nOTPSEN 0x0 +#define L2DABL 0x70000 /* L2 Memory Disable. */ + +/* Bit masks for SECURE_CONTROL */ + +#define SECURE0 0x1 /* SECURE 0 */ +#define nSECURE0 0x0 +#define SECURE1 0x2 /* SECURE 1 */ +#define nSECURE1 0x0 +#define SECURE2 0x4 /* SECURE 2 */ +#define nSECURE2 0x0 +#define SECURE3 0x8 /* SECURE 3 */ +#define nSECURE3 0x0 + +/* Bit masks for SECURE_STATUS */ + +#define SECMODE 0x3 /* Secured Mode Control State */ +#define NMI 0x4 /* Non Maskable Interrupt */ +#define nNMI 0x0 +#define AFVALID 0x8 /* Authentication Firmware Valid */ +#define nAFVALID 0x0 +#define AFEXIT 0x10 /* Authentication Firmware Exit */ +#define nAFEXIT 0x0 +#define SECSTAT 0xe0 /* Secure Status */ #endif /* _DEF_BF512_H */ diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h deleted file mode 100644 index 5f84913dcd9..00000000000 --- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h +++ /dev/null @@ -1,1495 +0,0 @@ -/* - * Copyright 2008 Analog Devices Inc. - * - * Licensed under the ADI BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF51X_H -#define _DEF_BF51X_H - - -/* ************************************************************** */ -/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x */ -/* ************************************************************** */ - -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define CHIPID 0xFFC00014 /* Device ID Register */ - -/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration Register */ -#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ - -#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ -#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ -#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ - -/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */ -#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ -#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ -#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ -#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ -#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */ -#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */ -#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ - - -/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ - - -/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ -#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */ - - -/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ -#define UART0_THR 0xFFC00400 /* Transmit Holding register */ -#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART0_LCR 0xFFC0040C /* Line Control Register */ -#define UART0_MCR 0xFFC00410 /* Modem Control Register */ -#define UART0_LSR 0xFFC00414 /* Line Status Register */ -#define UART0_MSR 0xFFC00418 /* Modem Status Register */ -#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART0_GCTL 0xFFC00424 /* Global Control Register */ - -/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */ -#define SPI0_REGBASE 0xFFC00500 -#define SPI0_CTL 0xFFC00500 /* SPI Control Register */ -#define SPI0_FLG 0xFFC00504 /* SPI Flag register */ -#define SPI0_STAT 0xFFC00508 /* SPI Status register */ -#define SPI0_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ -#define SPI0_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ -#define SPI0_BAUD 0xFFC00514 /* SPI Baud rate Register */ -#define SPI0_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ - -/* SPI1 Controller (0xFFC03400 - 0xFFC034FF) */ -#define SPI1_REGBASE 0xFFC03400 -#define SPI1_CTL 0xFFC03400 /* SPI Control Register */ -#define SPI1_FLG 0xFFC03404 /* SPI Flag register */ -#define SPI1_STAT 0xFFC03408 /* SPI Status register */ -#define SPI1_TDBR 0xFFC0340C /* SPI Transmit Data Buffer Register */ -#define SPI1_RDBR 0xFFC03410 /* SPI Receive Data Buffer Register */ -#define SPI1_BAUD 0xFFC03414 /* SPI Baud rate Register */ -#define SPI1_SHADOW 0xFFC03418 /* SPI_RDBR Shadow Register */ - -/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ -#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ - -#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ - -#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ - -#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ -#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ -#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ -#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ - -#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ -#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ -#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ -#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ - -#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ -#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ -#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ -#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ - -#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ -#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ -#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ -#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */ - -#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ -#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ -#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ -#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ - -#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ -#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ -#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ - -/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ -#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ -#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ -#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ -#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ -#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ -#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ -#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ -#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ -#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ -#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ -#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ -#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ -#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ -#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ -#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ -#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ -#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ - -/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ -#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ -#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ -#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ -#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ - -/* DMA Traffic Control Registers */ -#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ - -/* Alternate deprecated register names (below) provided for backwards code compatibility */ -#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ - -/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ - -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ - -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ - -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ - -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ - -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ - -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ - -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ - -#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ -#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ -#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ -#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ -#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ -#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ -#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ -#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ -#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ -#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ -#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ -#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ -#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ - -#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ -#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ -#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ -#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ -#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ -#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ -#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ -#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ -#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ -#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ -#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ -#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ -#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ - -#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ -#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ -#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ -#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ -#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ -#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ -#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ -#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ -#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ -#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ -#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ -#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ -#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ - -#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ -#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ -#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ -#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ -#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ -#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ -#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ -#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ -#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ -#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ -#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ -#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ -#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ - -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ - -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ -#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ -#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ - -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ - -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ -#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ -#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ - - -/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ -#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ -#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ -#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ -#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ -#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ - - -/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ -#define TWI0_REGBASE 0xFFC01400 -#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ -#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */ -#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ -#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ -#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ -#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ -#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ -#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ -#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ -#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ -#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ -#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ -#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ -#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ -#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ -#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ - - -/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ -#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ -#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ -#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ -#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ -#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ -#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ -#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ -#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ -#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ -#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ -#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ -#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ -#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ -#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ -#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ -#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ -#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ - - -/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ -#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ -#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ -#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ -#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ -#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ -#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ -#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ -#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ -#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ -#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ -#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ -#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ -#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ -#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ -#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ -#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ -#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ - - -/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ -#define UART1_THR 0xFFC02000 /* Transmit Holding register */ -#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ -#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ -#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ -#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ -#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ -#define UART1_LCR 0xFFC0200C /* Line Control Register */ -#define UART1_MCR 0xFFC02010 /* Modem Control Register */ -#define UART1_LSR 0xFFC02014 /* Line Status Register */ -#define UART1_MSR 0xFFC02018 /* Modem Status Register */ -#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ -#define UART1_GCTL 0xFFC02024 /* Global Control Register */ - - -/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ -#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ -#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ -#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ -#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ - - -/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ -#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ -#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ -#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ -#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */ -#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ -#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ -#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ - -#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ -#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ -#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ -#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */ -#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ -#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ -#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ - - -/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ -#define PORTF_MUX 0xFFC03210 /* Port F mux control */ -#define PORTG_MUX 0xFFC03214 /* Port G mux control */ -#define PORTH_MUX 0xFFC03218 /* Port H mux control */ -#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */ -#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */ -#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */ -#define PORTF_SLEW 0xFFC03230 /* Port F slew control */ -#define PORTG_SLEW 0xFFC03234 /* Port G slew control */ -#define PORTH_SLEW 0xFFC03238 /* Port H slew control */ -#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */ -#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */ -#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */ -#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */ -#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */ -#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */ - - -/*********************************************************************************** -** System MMR Register Bits And Macros -** -** Disclaimer: All macros are intended to make C and Assembly code more readable. -** Use these macros carefully, as any that do left shifts for field -** depositing will result in the lower order bits being destroyed. Any -** macro that shifts left to properly position the bit-field should be -** used as part of an OR to initialize a register and NOT as a dynamic -** modifier UNLESS the lower order bits are saved and ORed back in when -** the macro is used. -*************************************************************************************/ - -/* CHIPID Masks */ -#define CHIPID_VERSION 0xF0000000 -#define CHIPID_FAMILY 0x0FFFF000 -#define CHIPID_MANUFACTURE 0x00000FFE - -/* SWRST Masks */ -#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ -#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ -#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ -#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ -#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ - -/* SYSCR Masks */ -#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */ -#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ - - -/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ -/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ - -#if 0 -#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ - -#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ -#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */ -#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */ -#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */ -#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */ -#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */ -#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */ - -#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */ -#define IRQ_TWI 0x00000200 /* TWI Interrupt */ -#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */ -#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */ -#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */ -#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */ -#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */ -#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */ - -#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */ -#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */ -#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */ -#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */ -#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */ -#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */ -#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */ -#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */ -#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */ -#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */ - -#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */ -#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */ -#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */ -#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */ -#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */ -#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */ -#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */ -#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */ -#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */ -#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */ -#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */ -#endif - -/* SIC_IAR0 Macros */ -#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ -#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ -#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ -#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */ -#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ -#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ -#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ -#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ - -/* SIC_IAR1 Macros */ -#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */ -#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ -#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ -#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */ -#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ -#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ -#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ -#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ - -/* SIC_IAR2 Macros */ -#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */ -#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ -#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ -#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */ -#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ -#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ -#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ -#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ - -/* SIC_IAR3 Macros */ -#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */ -#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */ -#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */ -#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */ -#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */ -#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */ -#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */ -#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */ - - -/* SIC_IMASK Masks */ -#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ -#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ -#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ -#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ - -/* SIC_IWR Masks */ -#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ -#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ -#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ -#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ - - -/* ************** UART CONTROLLER MASKS *************************/ -/* UARTx_LCR Masks */ -#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ -#define STB 0x04 /* Stop Bits */ -#define PEN 0x08 /* Parity Enable */ -#define EPS 0x10 /* Even Parity Select */ -#define STP 0x20 /* Stick Parity */ -#define SB 0x40 /* Set Break */ -#define DLAB 0x80 /* Divisor Latch Access */ - -/* UARTx_MCR Mask */ -#define LOOP_ENA 0x10 /* Loopback Mode Enable */ -#define LOOP_ENA_P 0x04 - -/* UARTx_LSR Masks */ -#define DR 0x01 /* Data Ready */ -#define OE 0x02 /* Overrun Error */ -#define PE 0x04 /* Parity Error */ -#define FE 0x08 /* Framing Error */ -#define BI 0x10 /* Break Interrupt */ -#define THRE 0x20 /* THR Empty */ -#define TEMT 0x40 /* TSR and UART_THR Empty */ - -/* UARTx_IER Masks */ -#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ -#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ -#define ELSI 0x04 /* Enable RX Status Interrupt */ - -/* UARTx_IIR Masks */ -#define NINT 0x01 /* Pending Interrupt */ -#define IIR_TX_READY 0x02 /* UART_THR empty */ -#define IIR_RX_READY 0x04 /* Receive data ready */ -#define IIR_LINE_CHANGE 0x06 /* Receive line status */ -#define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */ - -/* UARTx_GCTL Masks */ -#define UCEN 0x01 /* Enable UARTx Clocks */ -#define IREN 0x02 /* Enable IrDA Mode */ -#define TPOLC 0x04 /* IrDA TX Polarity Change */ -#define RPOLC 0x08 /* IrDA RX Polarity Change */ -#define FPE 0x10 /* Force Parity Error On Transmit */ -#define FFE 0x20 /* Force Framing Error On Transmit */ - - -/* **************** GENERAL PURPOSE TIMER MASKS **********************/ -/* TIMER_ENABLE Masks */ -#define TIMEN0 0x0001 /* Enable Timer 0 */ -#define TIMEN1 0x0002 /* Enable Timer 1 */ -#define TIMEN2 0x0004 /* Enable Timer 2 */ -#define TIMEN3 0x0008 /* Enable Timer 3 */ -#define TIMEN4 0x0010 /* Enable Timer 4 */ -#define TIMEN5 0x0020 /* Enable Timer 5 */ -#define TIMEN6 0x0040 /* Enable Timer 6 */ -#define TIMEN7 0x0080 /* Enable Timer 7 */ - -/* TIMER_DISABLE Masks */ -#define TIMDIS0 TIMEN0 /* Disable Timer 0 */ -#define TIMDIS1 TIMEN1 /* Disable Timer 1 */ -#define TIMDIS2 TIMEN2 /* Disable Timer 2 */ -#define TIMDIS3 TIMEN3 /* Disable Timer 3 */ -#define TIMDIS4 TIMEN4 /* Disable Timer 4 */ -#define TIMDIS5 TIMEN5 /* Disable Timer 5 */ -#define TIMDIS6 TIMEN6 /* Disable Timer 6 */ -#define TIMDIS7 TIMEN7 /* Disable Timer 7 */ - -/* TIMER_STATUS Masks */ -#define TIMIL0 0x00000001 /* Timer 0 Interrupt */ -#define TIMIL1 0x00000002 /* Timer 1 Interrupt */ -#define TIMIL2 0x00000004 /* Timer 2 Interrupt */ -#define TIMIL3 0x00000008 /* Timer 3 Interrupt */ -#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ -#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ -#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ -#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ -#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ -#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ -#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ -#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ -#define TIMIL4 0x00010000 /* Timer 4 Interrupt */ -#define TIMIL5 0x00020000 /* Timer 5 Interrupt */ -#define TIMIL6 0x00040000 /* Timer 6 Interrupt */ -#define TIMIL7 0x00080000 /* Timer 7 Interrupt */ -#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ -#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ -#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ -#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ -#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ -#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ -#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ -#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ - -/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ -#define TOVL_ERR0 TOVF_ERR0 -#define TOVL_ERR1 TOVF_ERR1 -#define TOVL_ERR2 TOVF_ERR2 -#define TOVL_ERR3 TOVF_ERR3 -#define TOVL_ERR4 TOVF_ERR4 -#define TOVL_ERR5 TOVF_ERR5 -#define TOVL_ERR6 TOVF_ERR6 -#define TOVL_ERR7 TOVF_ERR7 - -/* TIMERx_CONFIG Masks */ -#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ -#define WDTH_CAP 0x0002 /* Width Capture Input Mode */ -#define EXT_CLK 0x0003 /* External Clock Mode */ -#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ -#define PERIOD_CNT 0x0008 /* Period Count */ -#define IRQ_ENA 0x0010 /* Interrupt Request Enable */ -#define TIN_SEL 0x0020 /* Timer Input Select */ -#define OUT_DIS 0x0040 /* Output Pad Disable */ -#define CLK_SEL 0x0080 /* Timer Clock Select */ -#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ -#define EMU_RUN 0x0200 /* Emulation Behavior Select */ -#define ERR_TYP 0xC000 /* Error Type */ - - -/* ****************** GPIO PORTS F, G, H MASKS ***********************/ -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ -/* Port F Masks */ -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - -/* Port G Masks */ -#define PG0 0x0001 -#define PG1 0x0002 -#define PG2 0x0004 -#define PG3 0x0008 -#define PG4 0x0010 -#define PG5 0x0020 -#define PG6 0x0040 -#define PG7 0x0080 -#define PG8 0x0100 -#define PG9 0x0200 -#define PG10 0x0400 -#define PG11 0x0800 -#define PG12 0x1000 -#define PG13 0x2000 -#define PG14 0x4000 -#define PG15 0x8000 - -/* Port H Masks */ -#define PH0 0x0001 -#define PH1 0x0002 -#define PH2 0x0004 -#define PH3 0x0008 -#define PH4 0x0010 -#define PH5 0x0020 -#define PH6 0x0040 -#define PH7 0x0080 - -/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ -/* EBIU_AMGCTL Masks */ -#define AMCKEN 0x0001 /* Enable CLKOUT */ -#define AMBEN_NONE 0x0000 /* All Banks Disabled */ -#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ -#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ -#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ -#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ - -/* EBIU_AMBCTL0 Masks */ -#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */ -#define B0RDYPOL 0x00000002 /* B0 RDY Active High */ -#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */ -#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */ -#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */ -#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */ -#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */ -#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */ -#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */ -#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */ -#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */ -#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */ -#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */ -#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */ -#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */ -#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */ -#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */ -#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */ -#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */ -#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */ -#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */ -#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */ -#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */ -#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */ -#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */ -#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */ -#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */ -#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */ -#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */ -#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */ -#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */ -#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */ -#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */ -#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */ -#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */ -#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */ - -#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */ -#define B1RDYPOL 0x00020000 /* B1 RDY Active High */ -#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */ -#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */ -#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */ -#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */ -#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */ -#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */ -#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */ -#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */ -#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */ -#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */ -#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */ -#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */ -#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */ -#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */ -#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */ -#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */ -#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */ -#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */ -#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */ -#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */ -#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */ -#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */ -#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */ -#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */ -#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */ -#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */ -#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */ -#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */ -#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */ -#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */ -#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */ -#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */ -#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */ -#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */ - -/* EBIU_AMBCTL1 Masks */ -#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */ -#define B2RDYPOL 0x00000002 /* B2 RDY Active High */ -#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */ -#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */ -#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */ -#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */ -#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */ -#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */ -#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */ -#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */ -#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */ -#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */ -#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */ -#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */ -#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */ -#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */ -#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */ -#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */ -#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */ -#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */ -#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */ -#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */ -#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */ -#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */ -#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */ -#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */ -#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */ -#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */ -#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */ -#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */ -#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */ -#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */ -#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */ -#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */ -#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */ -#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */ - -#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */ -#define B3RDYPOL 0x00020000 /* B3 RDY Active High */ -#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */ -#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */ -#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */ -#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */ -#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */ -#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */ -#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */ -#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */ -#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */ -#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */ -#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */ -#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */ -#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */ -#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */ -#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */ -#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */ -#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */ -#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */ -#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */ -#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */ -#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */ -#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */ -#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */ -#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */ -#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */ -#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */ -#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */ -#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */ -#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */ -#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */ -#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */ -#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */ -#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */ -#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */ - - -/* ********************** SDRAM CONTROLLER MASKS **********************************************/ -/* EBIU_SDGCTL Masks */ -#define SCTLE 0x00000001 /* Enable SDRAM Signals */ -#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */ -#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ -#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ -#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ -#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ -#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ -#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ -#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ -#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ -#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ -#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ -#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ -#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ -#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ -#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ -#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ -#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ -#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ -#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ -#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ -#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ -#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ -#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ -#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ -#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ -#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ -#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ -#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ -#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ -#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ -#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ -#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ -#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ -#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ -#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ -#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ -#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ -#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */ -#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */ -#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */ -#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */ -#define EBUFE 0x02000000 /* Enable External Buffering Timing */ -#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */ -#define EMREN 0x10000000 /* Extended Mode Register Enable */ -#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */ -#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */ - -/* EBIU_SDBCTL Masks */ -#define EBE 0x0001 /* Enable SDRAM External Bank */ -#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */ -#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ -#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ -#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ -#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */ -#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */ -#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ -#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ -#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ -#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */ - -/* EBIU_SDSTAT Masks */ -#define SDCI 0x0001 /* SDRAM Controller Idle */ -#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */ -#define SDPUA 0x0004 /* SDRAM Power-Up Active */ -#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */ -#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */ -#define BGSTAT 0x0020 /* Bus Grant Status */ - - -/* ************************** DMA CONTROLLER MASKS ********************************/ - -/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ -#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ -#define PMAP 0xF000 /* Peripheral Mapped To This Channel */ -#define PMAP_PPI 0x0000 /* PPI Port DMA */ -#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */ -#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */ -#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */ -#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */ -#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */ -#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */ -#define PMAP_SPI 0x7000 /* SPI Port DMA */ -#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */ -#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */ -#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ -#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ - -/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ -/* PPI_CONTROL Masks */ -#define PORT_EN 0x0001 /* PPI Port Enable */ -#define PORT_DIR 0x0002 /* PPI Port Direction */ -#define XFR_TYPE 0x000C /* PPI Transfer Type */ -#define PORT_CFG 0x0030 /* PPI Port Configuration */ -#define FLD_SEL 0x0040 /* PPI Active Field Select */ -#define PACK_EN 0x0080 /* PPI Packing Mode */ -#define DMA32 0x0100 /* PPI 32-bit DMA Enable */ -#define SKIP_EN 0x0200 /* PPI Skip Element Enable */ -#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ -#define DLEN_8 0x0000 /* Data Length = 8 Bits */ -#define DLEN_10 0x0800 /* Data Length = 10 Bits */ -#define DLEN_11 0x1000 /* Data Length = 11 Bits */ -#define DLEN_12 0x1800 /* Data Length = 12 Bits */ -#define DLEN_13 0x2000 /* Data Length = 13 Bits */ -#define DLEN_14 0x2800 /* Data Length = 14 Bits */ -#define DLEN_15 0x3000 /* Data Length = 15 Bits */ -#define DLEN_16 0x3800 /* Data Length = 16 Bits */ -#define DLENGTH 0x3800 /* PPI Data Length */ -#define POLC 0x4000 /* PPI Clock Polarity */ -#define POLS 0x8000 /* PPI Frame Sync Polarity */ - -/* PPI_STATUS Masks */ -#define FLD 0x0400 /* Field Indicator */ -#define FT_ERR 0x0800 /* Frame Track Error */ -#define OVR 0x1000 /* FIFO Overflow Error */ -#define UNDR 0x2000 /* FIFO Underrun Error */ -#define ERR_DET 0x4000 /* Error Detected Indicator */ -#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ - - -/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/ -/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ -#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ -#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ - -/* TWI_PRESCALE Masks */ -#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ -#define TWI_ENA 0x0080 /* TWI Enable */ -#define SCCB 0x0200 /* SCCB Compatibility Enable */ - -/* TWI_SLAVE_CTL Masks */ -#define SEN 0x0001 /* Slave Enable */ -#define SADD_LEN 0x0002 /* Slave Address Length */ -#define STDVAL 0x0004 /* Slave Transmit Data Valid */ -#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ -#define GEN 0x0010 /* General Call Adrress Matching Enabled */ - -/* TWI_SLAVE_STAT Masks */ -#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ -#define GCALL 0x0002 /* General Call Indicator */ - -/* TWI_MASTER_CTL Masks */ -#define MEN 0x0001 /* Master Mode Enable */ -#define MADD_LEN 0x0002 /* Master Address Length */ -#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ -#define FAST 0x0008 /* Use Fast Mode Timing Specs */ -#define STOP 0x0010 /* Issue Stop Condition */ -#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ -#define DCNT 0x3FC0 /* Data Bytes To Transfer */ -#define SDAOVR 0x4000 /* Serial Data Override */ -#define SCLOVR 0x8000 /* Serial Clock Override */ - -/* TWI_MASTER_STAT Masks */ -#define MPROG 0x0001 /* Master Transfer In Progress */ -#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ -#define ANAK 0x0004 /* Address Not Acknowledged */ -#define DNAK 0x0008 /* Data Not Acknowledged */ -#define BUFRDERR 0x0010 /* Buffer Read Error */ -#define BUFWRERR 0x0020 /* Buffer Write Error */ -#define SDASEN 0x0040 /* Serial Data Sense */ -#define SCLSEN 0x0080 /* Serial Clock Sense */ -#define BUSBUSY 0x0100 /* Bus Busy Indicator */ - -/* TWI_INT_SRC and TWI_INT_ENABLE Masks */ -#define SINIT 0x0001 /* Slave Transfer Initiated */ -#define SCOMP 0x0002 /* Slave Transfer Complete */ -#define SERR 0x0004 /* Slave Transfer Error */ -#define SOVF 0x0008 /* Slave Overflow */ -#define MCOMP 0x0010 /* Master Transfer Complete */ -#define MERR 0x0020 /* Master Transfer Error */ -#define XMTSERV 0x0040 /* Transmit FIFO Service */ -#define RCVSERV 0x0080 /* Receive FIFO Service */ - -/* TWI_FIFO_CTRL Masks */ -#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ -#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ -#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ -#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ - -/* TWI_FIFO_STAT Masks */ -#define XMTSTAT 0x0003 /* Transmit FIFO Status */ -#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ -#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ -#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ - -#define RCVSTAT 0x000C /* Receive FIFO Status */ -#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ -#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ -#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ - - -/* ******************* PIN CONTROL REGISTER MASKS ************************/ -/* PORT_MUX Masks */ -#define PJSE 0x0001 /* Port J SPI/SPORT Enable */ -#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */ -#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */ - -#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */ -#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */ -#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */ -#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */ - -#define PFDE 0x0008 /* Port F DMA Request Enable */ -#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */ -#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */ - -#define PFTE 0x0010 /* Port F Timer Enable */ -#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */ -#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */ - -#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */ -#define PFS6E_TIMER 0x0000 /* Enable TMR5 */ -#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */ - -#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */ -#define PFS5E_TIMER 0x0000 /* Enable TMR4 */ -#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */ - -#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */ -#define PFS4E_TIMER 0x0000 /* Enable TMR3 */ -#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */ - -#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */ -#define PFFE_TIMER 0x0000 /* Enable TMR2 */ -#define PFFE_PPI 0x0100 /* Enable PPI FS3 */ - -#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */ -#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */ -#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */ - -#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */ -#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */ -#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */ - -#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */ -#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ -#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ - - -/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/ -/* HDMAx_CTL Masks */ -#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */ -#define REP 0x0002 /* HDMA Request Polarity */ -#define UTE 0x0004 /* Urgency Threshold Enable */ -#define OIE 0x0010 /* Overflow Interrupt Enable */ -#define BDIE 0x0020 /* Block Done Interrupt Enable */ -#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */ -#define DRQ 0x0300 /* HDMA Request Type */ -#define DRQ_NONE 0x0000 /* No Request */ -#define DRQ_SINGLE 0x0100 /* Channels Request Single */ -#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */ -#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */ -#define RBC 0x1000 /* Reload BCNT With IBCNT */ -#define PS 0x2000 /* HDMA Pin Status */ -#define OI 0x4000 /* Overflow Interrupt Generated */ -#define BDI 0x8000 /* Block Done Interrupt Generated */ - -/* entry addresses of the user-callable Boot ROM functions */ - -#define _BOOTROM_RESET 0xEF000000 -#define _BOOTROM_FINAL_INIT 0xEF000002 -#define _BOOTROM_DO_MEMORY_DMA 0xEF000006 -#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 -#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A -#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C -#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 -#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 -#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 - -/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ -#define PGDE_UART PFDE_UART -#define PGDE_DMA PFDE_DMA -#define CKELOW SCKELOW - -/* HOST Port Registers */ - -#define HOST_CONTROL 0xffc03400 /* HOST Control Register */ -#define HOST_STATUS 0xffc03404 /* HOST Status Register */ -#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */ - -/* Counter Registers */ - -#define CNT_CONFIG 0xffc03500 /* Configuration Register */ -#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */ -#define CNT_STATUS 0xffc03508 /* Status Register */ -#define CNT_COMMAND 0xffc0350c /* Command Register */ -#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */ -#define CNT_COUNTER 0xffc03514 /* Counter Register */ -#define CNT_MAX 0xffc03518 /* Maximal Count Register */ -#define CNT_MIN 0xffc0351c /* Minimal Count Register */ - -/* OTP/FUSE Registers */ - -#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */ -#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */ -#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */ -#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */ - -/* Security Registers */ - -#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */ -#define SECURE_CONTROL 0xffc03624 /* Secure Control */ -#define SECURE_STATUS 0xffc03628 /* Secure Status */ - -/* OTP Read/Write Data Buffer Registers */ - -#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ - -/* Motor Control PWM Registers */ - -#define PWM_CTRL 0xffc03700 /* PWM Control Register */ -#define PWM_STAT 0xffc03704 /* PWM Status Register */ -#define PWM_TM 0xffc03708 /* PWM Period Register */ -#define PWM_DT 0xffc0370c /* PWM Dead Time Register */ -#define PWM_GATE 0xffc03710 /* PWM Chopping Control */ -#define PWM_CHA 0xffc03714 /* PWM Channel A Duty Control */ -#define PWM_CHB 0xffc03718 /* PWM Channel B Duty Control */ -#define PWM_CHC 0xffc0371c /* PWM Channel C Duty Control */ -#define PWM_SEG 0xffc03720 /* PWM Crossover and Output Enable */ -#define PWM_SYNCWT 0xffc03724 /* PWM Sync Pluse Width Control */ -#define PWM_CHAL 0xffc03728 /* PWM Channel AL Duty Control (SR mode only) */ -#define PWM_CHBL 0xffc0372c /* PWM Channel BL Duty Control (SR mode only) */ -#define PWM_CHCL 0xffc03730 /* PWM Channel CL Duty Control (SR mode only) */ -#define PWM_LSI 0xffc03734 /* PWM Low Side Invert (SR mode only) */ -#define PWM_STAT2 0xffc03738 /* PWM Status Register 2 */ - - -/* ********************************************************** */ -/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ -/* and MULTI BIT READ MACROS */ -/* ********************************************************** */ - -/* Bit masks for HOST_CONTROL */ - -#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */ -#define HOST_CNTR_nHOST_EN 0x0 -#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */ -#define HOST_CNTR_nHOST_END 0x0 -#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */ -#define HOST_CNTR_nDATA_SIZE 0x0 -#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */ -#define HOST_CNTR_nHOST_RST 0x0 -#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */ -#define HOST_CNTR_nHRDY_OVR 0x0 -#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */ -#define HOST_CNTR_nINT_MODE 0x0 -#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */ -#define HOST_CNTR_ nBT_EN 0x0 -#define HOST_CNTR_EHW 0x100 /* Enable Host Write */ -#define HOST_CNTR_nEHW 0x0 -#define HOST_CNTR_EHR 0x200 /* Enable Host Read */ -#define HOST_CNTR_nEHR 0x0 -#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */ -#define HOST_CNTR_nBDR 0x0 - -/* Bit masks for HOST_STATUS */ - -#define HOST_STAT_READY 0x1 /* DMA Ready */ -#define HOST_STAT_nREADY 0x0 -#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */ -#define HOST_STAT_nFIFOFULL 0x0 -#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */ -#define HOST_STAT_nFIFOEMPTY 0x0 -#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */ -#define HOST_STAT_nCOMPLETE 0x0 -#define HOST_STAT_HSHK 0x10 /* Host Handshake */ -#define HOST_STAT_nHSHK 0x0 -#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */ -#define HOST_STAT_nTIMEOUT 0x0 -#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */ -#define HOST_STAT_nHIRQ 0x0 -#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */ -#define HOST_STAT_nALLOW_CNFG 0x0 -#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */ -#define HOST_STAT_nDMA_DIR 0x0 -#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */ -#define HOST_STAT_nBTE 0x0 -#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */ -#define HOST_STAT_nHOSTRD_DONE 0x0 - -/* Bit masks for HOST_TIMEOUT */ - -#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */ - -/* Bit masks for SECURE_SYSSWT */ - -#define EMUDABL 0x1 /* Emulation Disable. */ -#define nEMUDABL 0x0 -#define RSTDABL 0x2 /* Reset Disable */ -#define nRSTDABL 0x0 -#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ -#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ -#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ -#define DMA0OVR 0x800 /* DMA0 Memory Access Override */ -#define nDMA0OVR 0x0 -#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ -#define nDMA1OVR 0x0 -#define EMUOVR 0x4000 /* Emulation Override */ -#define nEMUOVR 0x0 -#define OTPSEN 0x8000 /* OTP Secrets Enable. */ -#define nOTPSEN 0x0 -#define L2DABL 0x70000 /* L2 Memory Disable. */ - -/* Bit masks for SECURE_CONTROL */ - -#define SECURE0 0x1 /* SECURE 0 */ -#define nSECURE0 0x0 -#define SECURE1 0x2 /* SECURE 1 */ -#define nSECURE1 0x0 -#define SECURE2 0x4 /* SECURE 2 */ -#define nSECURE2 0x0 -#define SECURE3 0x8 /* SECURE 3 */ -#define nSECURE3 0x0 - -/* Bit masks for SECURE_STATUS */ - -#define SECMODE 0x3 /* Secured Mode Control State */ -#define NMI 0x4 /* Non Maskable Interrupt */ -#define nNMI 0x0 -#define AFVALID 0x8 /* Authentication Firmware Valid */ -#define nAFVALID 0x0 -#define AFEXIT 0x10 /* Authentication Firmware Exit */ -#define nAFEXIT 0x0 -#define SECSTAT 0xe0 /* Secure Status */ - - - -#endif /* _DEF_BF51X_H */ diff --git a/arch/blackfin/mach-bf518/include/mach/gpio.h b/arch/blackfin/mach-bf518/include/mach/gpio.h index 9af6ce0f632..b480705bfc2 100644 --- a/arch/blackfin/mach-bf518/include/mach/gpio.h +++ b/arch/blackfin/mach-bf518/include/mach/gpio.h @@ -55,4 +55,8 @@ #define PORT_G GPIO_PG0 #define PORT_H GPIO_PH0 +#include <mach-common/ports-f.h> +#include <mach-common/ports-g.h> +#include <mach-common/ports-h.h> + #endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf518/include/mach/pll.h b/arch/blackfin/mach-bf518/include/mach/pll.h index d5502988896..94cca674d83 100644 --- a/arch/blackfin/mach-bf518/include/mach/pll.h +++ b/arch/blackfin/mach-bf518/include/mach/pll.h @@ -1,63 +1 @@ -/* - * Copyright 2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _MACH_PLL_H -#define _MACH_PLL_H - -#include <asm/blackfin.h> -#include <asm/irqflags.h> - -/* Writing to PLL_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_PLL_CTL(unsigned int val) -{ - unsigned long flags, iwr0, iwr1; - - if (val == bfin_read_PLL_CTL()) - return; - - flags = hard_local_irq_save(); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SIC_IWR0); - iwr1 = bfin_read32(SIC_IWR1); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR0, IWR_ENABLE(0)); - bfin_write32(SIC_IWR1, 0); - - bfin_write16(PLL_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR0, iwr0); - bfin_write32(SIC_IWR1, iwr1); - hard_local_irq_restore(flags); -} - -/* Writing to VR_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_VR_CTL(unsigned int val) -{ - unsigned long flags, iwr0, iwr1; - - if (val == bfin_read_VR_CTL()) - return; - - flags = hard_local_irq_save(); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SIC_IWR0); - iwr1 = bfin_read32(SIC_IWR1); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR0, IWR_ENABLE(0)); - bfin_write32(SIC_IWR1, 0); - - bfin_write16(VR_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR0, iwr0); - bfin_write32(SIC_IWR1, iwr1); - hard_local_irq_restore(flags); -} - -#endif /* _MACH_PLL_H */ +#include <mach-common/pll.h> diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c index 52295fff557..ccab4c689dc 100644 --- a/arch/blackfin/mach-bf527/boards/ad7160eval.c +++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c @@ -67,6 +67,7 @@ static struct musb_hdrc_config musb_config = { * if it is the case. */ .gpio_vrsel_active = 1, + .clkin = 24, /* musb CLKIN in MHZ */ }; static struct musb_hdrc_platform_data musb_plat = { @@ -419,7 +420,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -474,7 +475,7 @@ static struct resource bfin_uart1_resources[] = { #endif }; -unsigned short bfin_uart1_peripherals[] = { +static unsigned short bfin_uart1_peripherals[] = { P_UART1_TX, P_UART1_RX, 0 }; @@ -627,9 +628,9 @@ static struct resource bfin_sport0_uart_resources[] = { }, }; -unsigned short bfin_sport0_peripherals[] = { +static unsigned short bfin_sport0_peripherals[] = { P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 }; static struct platform_device bfin_sport0_uart_device = { @@ -661,9 +662,9 @@ static struct resource bfin_sport1_uart_resources[] = { }, }; -unsigned short bfin_sport1_peripherals[] = { +static unsigned short bfin_sport1_peripherals[] = { P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c index 50533edc399..c9d6dc88f0e 100644 --- a/arch/blackfin/mach-bf527/boards/cm_bf527.c +++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c @@ -104,6 +104,7 @@ static struct musb_hdrc_config musb_config = { * if it is the case. */ .gpio_vrsel_active = 1, + .clkin = 24, /* musb CLKIN in MHZ */ }; static struct musb_hdrc_platform_data musb_plat = { @@ -614,7 +615,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -669,7 +670,7 @@ static struct resource bfin_uart1_resources[] = { #endif }; -unsigned short bfin_uart1_peripherals[] = { +static unsigned short bfin_uart1_peripherals[] = { P_UART1_TX, P_UART1_RX, 0 }; @@ -801,9 +802,9 @@ static struct resource bfin_sport0_uart_resources[] = { }, }; -unsigned short bfin_sport0_peripherals[] = { +static unsigned short bfin_sport0_peripherals[] = { P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 }; static struct platform_device bfin_sport0_uart_device = { @@ -835,9 +836,9 @@ static struct resource bfin_sport1_uart_resources[] = { }, }; -unsigned short bfin_sport1_peripherals[] = { +static unsigned short bfin_sport1_peripherals[] = { P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c index d06177b5fe2..b7101aa6e3a 100644 --- a/arch/blackfin/mach-bf527/boards/ezbrd.c +++ b/arch/blackfin/mach-bf527/boards/ezbrd.c @@ -68,6 +68,7 @@ static struct musb_hdrc_config musb_config = { * if it is the case. */ .gpio_vrsel_active = 1, + .clkin = 24, /* musb CLKIN in MHZ */ }; static struct musb_hdrc_platform_data musb_plat = { @@ -499,7 +500,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -554,7 +555,7 @@ static struct resource bfin_uart1_resources[] = { #endif }; -unsigned short bfin_uart1_peripherals[] = { +static unsigned short bfin_uart1_peripherals[] = { P_UART1_TX, P_UART1_RX, 0 }; @@ -681,9 +682,9 @@ static struct resource bfin_sport0_uart_resources[] = { }, }; -unsigned short bfin_sport0_peripherals[] = { +static unsigned short bfin_sport0_peripherals[] = { P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 }; static struct platform_device bfin_sport0_uart_device = { @@ -715,9 +716,9 @@ static struct resource bfin_sport1_uart_resources[] = { }, }; -unsigned short bfin_sport1_peripherals[] = { +static unsigned short bfin_sport1_peripherals[] = { P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index 35a88a5a501..2cd2ff6f304 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c @@ -108,6 +108,7 @@ static struct musb_hdrc_config musb_config = { * if it is the case. */ .gpio_vrsel_active = 1, + .clkin = 24, /* musb CLKIN in MHZ */ }; static struct musb_hdrc_platform_data musb_plat = { @@ -708,7 +709,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -763,7 +764,7 @@ static struct resource bfin_uart1_resources[] = { #endif }; -unsigned short bfin_uart1_peripherals[] = { +static unsigned short bfin_uart1_peripherals[] = { P_UART1_TX, P_UART1_RX, 0 }; @@ -962,6 +963,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { I2C_BOARD_INFO("ad5252", 0x2f), }, #endif +#if defined(CONFIG_SND_SOC_ADAU1373) || defined(CONFIG_SND_SOC_ADAU1373_MODULE) + { + I2C_BOARD_INFO("adau1373", 0x1A), + }, +#endif }; #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) @@ -984,9 +990,9 @@ static struct resource bfin_sport0_uart_resources[] = { }, }; -unsigned short bfin_sport0_peripherals[] = { +static unsigned short bfin_sport0_peripherals[] = { P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 }; static struct platform_device bfin_sport0_uart_device = { @@ -1018,9 +1024,9 @@ static struct resource bfin_sport1_uart_resources[] = { }, }; -unsigned short bfin_sport1_peripherals[] = { +static unsigned short bfin_sport1_peripherals[] = { P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c index 130861bd258..18d303dd562 100644 --- a/arch/blackfin/mach-bf527/boards/tll6527m.c +++ b/arch/blackfin/mach-bf527/boards/tll6527m.c @@ -193,7 +193,7 @@ static unsigned gpio_addr_inputs[] = { GPIO_PG1, GPIO_PH9, GPIO_PH10 }; -static struct gpio_decoder_platfrom_data spi_decoded_cs = { +static struct gpio_decoder_platform_data spi_decoded_cs = { .base = EXP_GPIO_SPISEL_BASE, .input_addrs = gpio_addr_inputs, .nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs), @@ -586,7 +586,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -642,7 +642,7 @@ static struct resource bfin_uart1_resources[] = { #endif }; -unsigned short bfin_uart1_peripherals[] = { +static unsigned short bfin_uart1_peripherals[] = { P_UART1_TX, P_UART1_RX, 0 }; @@ -799,9 +799,9 @@ static struct resource bfin_sport0_uart_resources[] = { }, }; -unsigned short bfin_sport0_peripherals[] = { +static unsigned short bfin_sport0_peripherals[] = { P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 }; static struct platform_device bfin_sport0_uart_device = { @@ -834,9 +834,9 @@ static struct resource bfin_sport1_uart_resources[] = { }, }; -unsigned short bfin_sport1_peripherals[] = { +static unsigned short bfin_sport1_peripherals[] = { P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { diff --git a/arch/blackfin/mach-bf527/dma.c b/arch/blackfin/mach-bf527/dma.c index 7bc7577d6c4..1fabdefea73 100644 --- a/arch/blackfin/mach-bf527/dma.c +++ b/arch/blackfin/mach-bf527/dma.c @@ -11,7 +11,7 @@ #include <asm/blackfin.h> #include <asm/dma.h> -struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { +struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { (struct dma_register *) DMA0_NEXT_DESC_PTR, (struct dma_register *) DMA1_NEXT_DESC_PTR, (struct dma_register *) DMA2_NEXT_DESC_PTR, diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial.h new file mode 100644 index 00000000000..00c603fe821 --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/bfin_serial.h @@ -0,0 +1,14 @@ +/* + * mach/bfin_serial.h - Blackfin UART/Serial definitions + * + * Copyright 2006-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_MACH_SERIAL_H__ +#define __BFIN_MACH_SERIAL_H__ + +#define BFIN_UART_NR_PORTS 2 + +#endif diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h index c1d55b878b4..960e08919de 100644 --- a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h @@ -4,36 +4,9 @@ * Licensed under the GPL-2 or later */ -#include <linux/serial.h> #include <asm/dma.h> #include <asm/portmux.h> -#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) -#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) -#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) -#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) -#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) -#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) -#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) - -#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v) -#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v) -#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v) -#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) -#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) -#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v) -#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v) -#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v) - -#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) -#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) - -#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) -#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) -#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) -#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) -#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) - #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) # define CONFIG_SERIAL_BFIN_CTSRTS @@ -54,50 +27,6 @@ # endif #endif -#define BFIN_UART_TX_FIFO_SIZE 2 - -/* - * The pin configuration is different from schematic - */ -struct bfin_serial_port { - struct uart_port port; - unsigned int old_status; - int status_irq; - unsigned int lsr; -#ifdef CONFIG_SERIAL_BFIN_DMA - int tx_done; - int tx_count; - struct circ_buf rx_dma_buf; - struct timer_list rx_dma_timer; - int rx_dma_nrows; - unsigned int tx_dma_channel; - unsigned int rx_dma_channel; - struct work_struct tx_dma_workqueue; -#endif -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - struct timer_list cts_timer; - int cts_pin; - int rts_pin; -#endif -}; - -/* The hardware clears the LSR bits upon read, so we need to cache - * some of the more fun bits in software so they don't get lost - * when checking the LSR in other code paths (TX). - */ -static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart) -{ - unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR); - uart->lsr |= (lsr & (BI|FE|PE|OE)); - return lsr | uart->lsr; -} - -static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) -{ - uart->lsr = 0; - bfin_write16(uart->port.membase + OFFSET_LSR, -1); -} - struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; @@ -146,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = { }; #define DRIVER_NAME "bfin-uart" + +#include <asm/bfin_serial.h> diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h index f714c5de307..e1d27927448 100644 --- a/arch/blackfin/mach-bf527/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf527/include/mach/blackfin.h @@ -1,49 +1,37 @@ /* - * Copyright 2007-2009 Analog Devices Inc. + * Copyright 2007-2010 Analog Devices Inc. * - * Licensed under the GPL-2 or later + * Licensed under the GPL-2 or later. */ #ifndef _MACH_BLACKFIN_H_ #define _MACH_BLACKFIN_H_ #include "bf527.h" -#include "defBF522.h" #include "anomaly.h" -#if defined(CONFIG_BF527) || defined(CONFIG_BF526) -#include "defBF527.h" +#include <asm/def_LPBlackfin.h> +#if defined(CONFIG_BF523) || defined(CONFIG_BF522) +# include "defBF522.h" #endif - #if defined(CONFIG_BF525) || defined(CONFIG_BF524) -#include "defBF525.h" +# include "defBF525.h" #endif - -#if !defined(__ASSEMBLY__) -#include "cdefBF522.h" - #if defined(CONFIG_BF527) || defined(CONFIG_BF526) -#include "cdefBF527.h" +# include "defBF527.h" #endif -#if defined(CONFIG_BF525) || defined(CONFIG_BF524) -#include "cdefBF525.h" -#endif +#if !defined(__ASSEMBLY__) +# include <asm/cdef_LPBlackfin.h> +# if defined(CONFIG_BF523) || defined(CONFIG_BF522) +# include "cdefBF522.h" +# endif +# if defined(CONFIG_BF525) || defined(CONFIG_BF524) +# include "cdefBF525.h" +# endif +# if defined(CONFIG_BF527) || defined(CONFIG_BF526) +# include "cdefBF527.h" +# endif #endif -#define BFIN_UART_NR_PORTS 2 - -#define OFFSET_THR 0x00 /* Transmit Holding register */ -#define OFFSET_RBR 0x00 /* Receive Buffer register */ -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_IER 0x04 /* Interrupt Enable Register */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_GCTL 0x24 /* Global Control Register */ - #endif diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h index 1079af8c7ae..618dfcdfa91 100644 --- a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h +++ b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h @@ -1,21 +1,1095 @@ /* - * Copyright 2007-2008 Analog Devices Inc. + * Copyright 2007-2010 Analog Devices Inc. * - * Licensed under the GPL-2 or later + * Licensed under the GPL-2 or later. */ #ifndef _CDEF_BF522_H #define _CDEF_BF522_H -/* include all Core registers and bit definitions */ -#include "defBF522.h" +/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ +#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) +#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) +#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) +#define bfin_read_VR_CTL() bfin_read16(VR_CTL) +#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) +#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) +#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) +#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) +#define bfin_read_CHIPID() bfin_read32(CHIPID) +#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -/* include core specific register pointer definitions */ -#include <asm/cdef_LPBlackfin.h> -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */ +/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ +#define bfin_read_SWRST() bfin_read16(SWRST) +#define bfin_write_SWRST(val) bfin_write16(SWRST, val) +#define bfin_read_SYSCR() bfin_read16(SYSCR) +#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ -#include "cdefBF52x_base.h" +#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) +#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) +#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) +#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) +#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6)) +#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val) + +#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) +#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) +#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) +#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) +#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) +#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) +#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) +#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) + +#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) +#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) +#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6)) +#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val) + +#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) +#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) +#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6)) +#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val) + +/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */ + +#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) +#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) +#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) +#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) +#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) +#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) +#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) +#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) +#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) +#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) +#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) +#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) +#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) +#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) + +/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ +#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) +#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) +#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) +#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) +#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) +#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) + + +/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ +#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) +#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) +#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) +#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) +#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) +#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) +#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) +#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) +#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) +#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) +#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) +#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val) +#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) +#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) + + +/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ +#define bfin_read_UART0_THR() bfin_read16(UART0_THR) +#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) +#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) +#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) +#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) +#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) +#define bfin_read_UART0_IER() bfin_read16(UART0_IER) +#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) +#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) +#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) +#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) +#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) +#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) +#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) +#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) +#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) +#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) +#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) +#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) +#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) +#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) +#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) +#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) +#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) + + +/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ +#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) +#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) +#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) +#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) +#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) +#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) +#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) +#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) +#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) +#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) +#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) +#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) +#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) +#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) + + +/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ +#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) +#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) +#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) +#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) +#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) +#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) +#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) +#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) + +#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) +#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) +#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) +#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) +#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) +#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) +#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) +#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) + +#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) +#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) +#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) +#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) +#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) +#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) +#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) +#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) + +#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) +#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) +#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) +#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) +#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) +#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) +#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) +#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) + +#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) +#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) +#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) +#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) +#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) +#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) +#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) +#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) + +#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) +#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) +#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) +#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) +#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) +#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) +#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) +#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) + +#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) +#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) +#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) +#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) +#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) +#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) +#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) +#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) + +#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) +#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) +#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) +#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) +#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) +#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) +#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) +#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) + +#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) +#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) +#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) +#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) +#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) +#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) + + +/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ +#define bfin_read_PORTFIO() bfin_read16(PORTFIO) +#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) +#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) +#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) +#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) +#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) +#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) +#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) +#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) +#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) +#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) +#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) +#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) +#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) +#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) +#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) +#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) +#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) +#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) +#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) +#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) +#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) +#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) +#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) +#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) +#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) +#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) +#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) +#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) +#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) +#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) +#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) +#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) +#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) + + +/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ +#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) +#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) +#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) +#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) +#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) +#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) +#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) +#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) +#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) +#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) +#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) +#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val) +#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) +#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val) +#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) +#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) +#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) +#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) +#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) +#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) +#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) +#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) +#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) +#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) +#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) +#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) +#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) +#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) +#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) +#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) +#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) +#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) +#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) +#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) +#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) +#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) +#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) +#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) +#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) +#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) +#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) +#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) +#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) +#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) +#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) +#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) + + +/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ +#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) +#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) +#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) +#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) +#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) +#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) +#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) +#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) +#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) +#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) +#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) +#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) +#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) +#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val) +#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) +#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val) +#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) +#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val) +#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) +#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val) +#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) +#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) +#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) +#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) +#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) +#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) +#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) +#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) +#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) +#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) +#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) +#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) +#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) +#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) +#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) +#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) +#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) +#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) +#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) +#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) +#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) +#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) +#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) +#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) +#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) +#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) +#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) +#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) +#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) +#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) +#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) +#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) + + +/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ +#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) +#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) +#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) +#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) +#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) +#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) +#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) +#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) +#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) +#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) +#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) +#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) +#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) +#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) + + +/* DMA Traffic Control Registers */ +#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER) +#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val) +#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT) +#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val) + +/* DMA Controller */ +#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) +#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) +#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) +#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) +#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) +#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) +#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) +#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) +#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) +#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) +#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) +#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) +#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) +#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) +#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) +#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) +#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) +#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) +#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) +#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) +#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) +#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) +#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) +#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) +#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) +#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) + +#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) +#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) +#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) +#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) +#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) +#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) +#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) +#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) +#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) +#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) +#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) +#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) +#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) +#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) +#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) +#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) +#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) +#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) +#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) +#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) +#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) +#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) +#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) +#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) +#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) + +#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) +#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) +#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) +#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) +#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) +#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) +#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) +#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) +#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) +#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) +#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) +#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) +#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) +#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) +#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) +#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) +#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) +#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) +#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) +#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) +#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) +#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) +#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) +#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) +#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) + +#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) +#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) +#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) +#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) +#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) +#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) +#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) +#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) +#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) +#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) +#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) +#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) +#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) +#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) +#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) +#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) +#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) +#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) +#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) +#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) +#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) +#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) +#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) +#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) +#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) +#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) + +#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) +#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) +#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) +#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) +#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) +#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) +#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) +#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) +#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) +#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) +#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) +#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) +#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) +#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) +#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) +#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) +#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) +#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) +#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) +#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) +#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) +#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) +#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) +#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) +#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) +#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) + +#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) +#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) +#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) +#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) +#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) +#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) +#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) +#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) +#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) +#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) +#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) +#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) +#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) +#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) +#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) +#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) +#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) +#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) +#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) +#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) +#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) +#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) +#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) +#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) +#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) +#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) + +#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) +#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) +#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) +#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) +#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) +#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) +#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) +#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) +#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) +#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) +#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) +#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) +#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) +#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) +#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) +#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) +#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) +#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) +#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) +#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) +#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) +#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) +#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) +#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) +#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) +#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) + +#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) +#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) +#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) +#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) +#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) +#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) +#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) +#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) +#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) +#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) +#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) +#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) +#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) +#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) +#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) +#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) +#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) +#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) +#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) +#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) +#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) +#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) +#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) +#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) +#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) +#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) + +#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) +#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) +#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) +#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) +#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) +#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) +#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) +#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) +#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) +#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) +#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) +#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) +#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) +#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) +#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) +#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) +#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) +#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) +#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) +#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) +#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) +#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) +#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) +#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) +#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) +#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) + +#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) +#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) +#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) +#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) +#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) +#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) +#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) +#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) +#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) +#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) +#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) +#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) +#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) +#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) +#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) +#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) +#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) +#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) +#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) +#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) +#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) +#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) +#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) +#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) +#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) +#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) + +#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) +#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) +#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) +#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) +#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) +#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) +#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) +#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) +#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) +#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) +#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) +#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) +#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) +#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) +#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) +#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) +#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) +#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) +#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) +#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) +#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) +#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) +#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) +#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) +#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) +#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) + +#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) +#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) +#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) +#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) +#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) +#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) +#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) +#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) +#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) +#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) +#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) +#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) +#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) +#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) +#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) +#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) +#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) +#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) +#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) +#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) +#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) +#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) +#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) +#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) +#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) +#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) + +#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) +#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) +#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) +#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) +#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) +#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) +#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) +#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) +#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) +#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) +#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) +#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) +#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) +#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) +#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) +#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) +#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) +#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) +#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) +#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) +#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) +#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) +#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) +#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) + +#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) +#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) +#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) +#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) +#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) +#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) +#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) +#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) +#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) +#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) +#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) +#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) +#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) +#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) +#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) +#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) +#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) +#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) +#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) +#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) +#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) +#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) +#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) + +#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) +#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) +#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) +#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) +#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) +#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) +#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) +#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) +#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) +#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) +#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) +#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) +#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) +#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) +#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) +#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) +#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) +#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) +#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) +#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) +#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) +#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) +#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) +#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) + +#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) +#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) +#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) +#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) +#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) +#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) +#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) +#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) +#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) +#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) +#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) +#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) +#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) +#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) +#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) +#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) +#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) +#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) +#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) +#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) +#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) +#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) +#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) + + +/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ +#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) +#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) +#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) +#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) +#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF) +#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) +#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) +#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) +#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) +#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) +#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) + + +/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ + +/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ +#define bfin_read_PORTGIO() bfin_read16(PORTGIO) +#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) +#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) +#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) +#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) +#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) +#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) +#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) +#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) +#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) +#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) +#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) +#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) +#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) +#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) +#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) +#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) +#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) +#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) +#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) +#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) +#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) +#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) +#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) +#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) +#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) +#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) +#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) +#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) +#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) +#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) +#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) +#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) +#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) + + +/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ +#define bfin_read_PORTHIO() bfin_read16(PORTHIO) +#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) +#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) +#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) +#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) +#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) +#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) +#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) +#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) +#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) +#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) +#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) +#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) +#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) +#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) +#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) +#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) +#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) +#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) +#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) +#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) +#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) +#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) +#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) +#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) +#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) +#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) +#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) +#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) +#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) +#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) +#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) +#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) +#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) + + +/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ +#define bfin_read_UART1_THR() bfin_read16(UART1_THR) +#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) +#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) +#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) +#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) +#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) +#define bfin_read_UART1_IER() bfin_read16(UART1_IER) +#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) +#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) +#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) +#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) +#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) +#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) +#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) +#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) +#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) +#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) +#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) +#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) +#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) +#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) +#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) +#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) +#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) + +/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */ + +/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ +#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) +#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) +#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) +#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) +#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) +#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) +#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX) +#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val) + + +/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ +#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) +#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) +#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) +#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) +#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) +#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) +#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) +#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) +#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) +#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) +#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) +#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) +#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) +#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) + +#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) +#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) +#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) +#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) +#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) +#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) +#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) +#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) +#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) +#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) +#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) +#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) +#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) +#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) + +/* ==== end from cdefBF534.h ==== */ + +/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ + +#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) +#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) +#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) +#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) +#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) +#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) + +#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) +#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) +#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) +#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) +#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) +#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) +#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW) +#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val) +#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW) +#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) +#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) +#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) +#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS) +#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val) +#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS) +#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val) +#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS) +#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val) +#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE) +#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val) +#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW) +#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val) +#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS) +#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val) + +/* HOST Port Registers */ + +#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) +#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) +#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) +#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) +#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) +#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) + +/* Counter Registers */ + +#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) +#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) +#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) +#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) +#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) +#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) +#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) +#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) +#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) +#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) +#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) +#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) +#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) +#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) +#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) +#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) + +/* Security Registers */ + +#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) +#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) +#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) +#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) +#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) +#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) + +/* NFC Registers */ + +#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) +#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) +#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) +#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) +#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) +#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) +#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) +#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) +#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) +#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) +#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) +#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) +#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) +#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) +#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) +#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) +#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) +#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) +#define bfin_read_NFC_RST() bfin_read16(NFC_RST) +#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) +#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) +#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) +#define bfin_read_NFC_READ() bfin_read16(NFC_READ) +#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) +#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) +#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) +#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) +#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) +#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) +#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) +#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) +#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) #endif /* _CDEF_BF522_H */ diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h index d7e2751c6bc..d90a85b6b6b 100644 --- a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h +++ b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h @@ -1,15 +1,12 @@ /* - * Copyright 2007-2008 Analog Devices Inc. + * Copyright 2007-2010 Analog Devices Inc. * - * Licensed under the GPL-2 or later + * Licensed under the GPL-2 or later. */ #ifndef _CDEF_BF525_H #define _CDEF_BF525_H -/* include all Core registers and bit definitions */ -#include "defBF525.h" - /* BF525 is BF522 + USB */ #include "cdefBF522.h" diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h index c7ba544d50b..eb22f586610 100644 --- a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h +++ b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h @@ -1,15 +1,12 @@ /* - * Copyright 2007-2008 Analog Devices Inc. + * Copyright 2007-2010 Analog Devices Inc. * - * Licensed under the GPL-2 or later + * Licensed under the GPL-2 or later. */ #ifndef _CDEF_BF527_H #define _CDEF_BF527_H -/* include all Core registers and bit definitions */ -#include "defBF527.h" - /* BF527 is BF525 + EMAC */ #include "cdefBF525.h" diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h deleted file mode 100644 index 3048b52bf46..00000000000 --- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h +++ /dev/null @@ -1,1113 +0,0 @@ -/* - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _CDEF_BF52X_H -#define _CDEF_BF52X_H - -#include <asm/blackfin.h> - -#include "defBF52x_base.h" - -/* Include core specific register pointer definitions */ -#include <asm/cdef_LPBlackfin.h> - -/* ==== begin from cdefBF534.h ==== */ - -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) - - -/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) - -#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) -#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) -#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) -#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) -#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6)) -#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val) - -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) - -#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) -#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) -#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6)) -#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val) - -#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) -#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) -#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6)) -#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val) - -/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */ - -#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) -#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) -#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) -#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) -#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) -#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) -#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) -#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) -#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) -#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) -#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) -#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) -#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) -#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) - -/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) - - -/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) -#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val) -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) - - -/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ -#define bfin_read_UART0_THR() bfin_read16(UART0_THR) -#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) -#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) -#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define bfin_read_UART0_IER() bfin_read16(UART0_IER) -#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) -#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) -#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) -#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) -#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) -#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) -#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) -#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) -#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) -#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) -#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) - - -/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ -#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) -#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) -#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) -#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) -#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) -#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) -#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) -#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) -#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) -#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) -#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) -#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) -#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) -#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) - - -/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) - -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) - -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) - -#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) -#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) -#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) -#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) -#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) - -#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) -#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) -#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) -#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) -#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) - -#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) -#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) -#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) -#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) -#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) - -#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) -#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) -#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) -#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) -#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) - -#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) -#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) -#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) -#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) -#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) - -#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) -#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) -#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) -#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) -#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) -#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) - - -/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ -#define bfin_read_PORTFIO() bfin_read16(PORTFIO) -#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) -#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) -#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) -#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) -#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) -#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) -#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) -#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) -#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) -#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) -#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) -#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) -#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) -#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) -#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) -#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) -#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) -#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) -#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) -#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) -#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) -#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) -#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) -#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) -#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) -#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) -#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) -#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) -#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) -#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) -#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) -#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) -#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) - - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val) -#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val) -#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) -#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val) -#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) -#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val) -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) -#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) -#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) -#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) -#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) -#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) -#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) -#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) -#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) - - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) -#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val) -#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val) -#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) -#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val) -#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) -#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val) -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) - - -/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) -#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) -#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) -#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) -#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) -#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) -#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) -#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) - - -/* DMA Traffic Control Registers */ -#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) -#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) -#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) -#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) - -/* Alternate deprecated register names (below) provided for backwards code compatibility */ -#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) -#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val) -#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) -#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val) - -/* DMA Controller */ -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) -#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) -#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) - -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) -#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) -#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) - -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) -#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) -#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) - -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) -#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) -#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) - -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) -#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) -#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) - -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) -#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) -#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) - -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) -#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) -#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) - -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) -#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) -#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) - -#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) -#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) -#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) -#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) -#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) -#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) -#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) -#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) -#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) -#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) -#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) -#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) -#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) -#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) -#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) -#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) -#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) -#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) - -#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) -#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) -#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) -#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) -#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) -#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) -#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) -#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) -#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) -#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) -#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) -#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) -#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) -#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) -#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) -#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) -#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) -#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) - -#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) -#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) -#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) -#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) -#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) -#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) -#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) -#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) -#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) -#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) -#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) -#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) -#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) -#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) -#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) -#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) -#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) -#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) - -#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) -#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) -#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) -#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) -#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) -#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) -#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) -#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) -#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) -#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) -#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) -#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) -#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) -#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) -#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) -#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) -#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) -#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) - -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) - -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) - -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) - -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) - - -/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ -#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) -#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) -#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) -#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) -#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF) -#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) -#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) -#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) -#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) -#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) -#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) - - -/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ - -/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ -#define bfin_read_PORTGIO() bfin_read16(PORTGIO) -#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) -#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) -#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) -#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) -#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) -#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) -#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) -#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) -#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) -#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) -#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) -#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) -#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) -#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) -#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) -#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) -#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) -#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) -#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) -#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) -#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) -#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) -#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) -#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) -#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) -#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) -#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) -#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) -#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) -#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) -#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) -#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) -#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) - - -/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ -#define bfin_read_PORTHIO() bfin_read16(PORTHIO) -#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) -#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) -#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) -#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) -#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) -#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) -#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) -#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) -#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) -#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) -#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) -#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) -#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) -#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) -#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) -#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) -#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) -#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) -#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) -#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) -#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) -#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) -#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) -#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) -#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) -#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) -#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) -#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) -#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) -#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) -#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) -#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) -#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) - - -/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ -#define bfin_read_UART1_THR() bfin_read16(UART1_THR) -#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) -#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) -#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define bfin_read_UART1_IER() bfin_read16(UART1_IER) -#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) -#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) -#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) -#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) -#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) -#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) -#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) -#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) -#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) -#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) -#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) - -/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */ - -/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ -#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) -#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) -#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) -#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX) -#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val) - - -/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ -#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) -#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) -#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) -#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) -#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) -#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) -#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) -#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) - -#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) -#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) -#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) -#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) -#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) -#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) -#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) -#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) - -/* ==== end from cdefBF534.h ==== */ - -/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ - -#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) -#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) -#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) -#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) -#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) -#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) - -#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) -#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) -#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) -#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) -#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) -#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) -#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW) -#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val) -#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW) -#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) -#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) -#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) -#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS) -#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val) -#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS) -#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val) -#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS) -#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val) -#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE) -#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val) -#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW) -#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val) -#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS) -#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val) - -/* HOST Port Registers */ - -#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) -#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) -#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) -#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) -#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) -#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) - -/* Counter Registers */ - -#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) -#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) -#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) -#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) -#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) -#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) -#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) -#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) -#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) -#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) -#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) -#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) -#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) -#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) -#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) -#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) - -/* Security Registers */ - -#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) -#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) -#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) -#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) -#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) -#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) - -/* NFC Registers */ - -#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) -#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) -#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) -#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) -#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) -#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) -#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) -#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) -#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) -#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) -#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) -#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) -#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) -#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) -#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) -#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) -#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) -#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) -#define bfin_read_NFC_RST() bfin_read16(NFC_RST) -#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) -#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) -#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) -#define bfin_read_NFC_READ() bfin_read16(NFC_READ) -#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) -#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) -#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) -#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) -#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) -#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) -#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) -#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) -#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) - -/* These need to be last due to the cdef/linux inter-dependencies */ -#include <asm/irq.h> - -#endif /* _CDEF_BF52X_H */ diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h index cb139a25481..89f5420ee6c 100644 --- a/arch/blackfin/mach-bf527/include/mach/defBF522.h +++ b/arch/blackfin/mach-bf527/include/mach/defBF522.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Analog Devices Inc. + * Copyright 2007-2010 Analog Devices Inc. * * Licensed under the ADI BSD license or the GPL-2 (or later) */ @@ -7,12 +7,1393 @@ #ifndef _DEF_BF522_H #define _DEF_BF522_H -/* Include all Core registers and bit definitions */ -#include <asm/def_LPBlackfin.h> +/* ************************************************************** */ +/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */ +/* ************************************************************** */ -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */ +/* ==== begin from defBF534.h ==== */ -/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ -#include "defBF52x_base.h" +/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ +#define PLL_CTL 0xFFC00000 /* PLL Control Register */ +#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ +#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ +#define PLL_STAT 0xFFC0000C /* PLL Status Register */ +#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ +#define CHIPID 0xFFC00014 /* Device ID Register */ + + +/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ +#define SWRST 0xFFC00100 /* Software Reset Register */ +#define SYSCR 0xFFC00104 /* System Configuration Register */ +#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ + +#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ +#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ +#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ +#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ +#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ + +/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */ +#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ +#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ +#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ +#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ +#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */ +#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */ +#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ + + +/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ +#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ +#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ +#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ + + +/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ +#define RTC_STAT 0xFFC00300 /* RTC Status Register */ +#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ +#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ +#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ +#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ +#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ +#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */ + + +/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ +#define UART0_THR 0xFFC00400 /* Transmit Holding register */ +#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ +#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ +#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ +#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ +#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ +#define UART0_LCR 0xFFC0040C /* Line Control Register */ +#define UART0_MCR 0xFFC00410 /* Modem Control Register */ +#define UART0_LSR 0xFFC00414 /* Line Status Register */ +#define UART0_MSR 0xFFC00418 /* Modem Status Register */ +#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ +#define UART0_GCTL 0xFFC00424 /* Global Control Register */ + + +/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ +#define SPI0_REGBASE 0xFFC00500 +#define SPI_CTL 0xFFC00500 /* SPI Control Register */ +#define SPI_FLG 0xFFC00504 /* SPI Flag register */ +#define SPI_STAT 0xFFC00508 /* SPI Status register */ +#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ +#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ +#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ +#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ + + +/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ +#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ +#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ +#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ +#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ + +#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ +#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ +#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ +#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ + +#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ +#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ +#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ +#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ + +#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ +#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ +#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ +#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ + +#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ +#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ +#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ +#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ + +#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ +#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ +#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ +#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ + +#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ +#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ +#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ +#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */ + +#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ +#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ +#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ +#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ + +#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ +#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ +#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ + + +/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ +#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ +#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ +#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ +#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ +#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ +#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ +#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ +#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ +#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ +#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ +#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ +#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ +#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ +#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ +#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ +#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ +#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ + + +/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ +#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ +#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ +#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ +#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ +#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ +#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ +#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ + + +/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ +#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ +#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ +#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ +#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ +#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ +#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ +#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ +#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ +#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ +#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ +#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ +#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ +#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ +#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ +#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ +#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ +#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ +#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ + + +/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ +#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ +#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ +#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ +#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ +#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ +#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ +#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ + + +/* DMA Traffic Control Registers */ +#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ +#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ + +/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ +#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ +#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ +#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ +#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ +#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ +#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ +#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ +#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ +#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ +#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ +#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ +#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ +#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ + +#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ +#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ +#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ +#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ +#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ +#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ +#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ +#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ +#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ +#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ +#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ +#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ +#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ + +#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ +#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ +#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ +#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ +#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ +#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ +#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ +#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ +#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ +#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ +#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ +#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ +#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ + +#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ +#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ +#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ +#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ +#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ +#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ +#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ +#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ +#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ +#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ +#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ +#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ +#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ + +#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ +#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ +#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ +#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ +#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ +#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ +#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ +#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ +#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ +#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ +#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ +#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ +#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ + +#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ +#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ +#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ +#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ +#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ +#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ +#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ +#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ +#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ +#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ +#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ +#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ +#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ + +#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ +#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ +#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ +#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ +#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ +#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ +#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ +#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ +#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ +#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ +#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ +#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ +#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ + +#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ +#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ +#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ +#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ +#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ +#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ +#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ +#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ +#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ +#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ +#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ +#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ +#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ + +#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ +#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ +#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ +#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ +#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ +#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ +#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ +#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ +#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ +#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ +#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ +#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ +#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ + +#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ +#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ +#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ +#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ +#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ +#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ +#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ +#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ +#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ +#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ +#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ +#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ +#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ + +#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ +#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ +#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ +#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ +#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ +#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ +#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ +#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ +#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ +#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ +#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ +#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ +#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ + +#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ +#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ +#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ +#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ +#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ +#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ +#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ +#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ +#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ +#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ +#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ +#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ +#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ + +#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ +#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ +#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ +#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ +#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ +#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ +#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ +#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ +#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ +#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ +#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ +#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ +#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ + +#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ +#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ +#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ +#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ +#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ +#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ +#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ +#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ +#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ +#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ +#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ +#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ +#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ + +#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ +#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ +#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ +#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ +#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ +#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ +#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ +#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ +#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ +#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ +#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ +#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ +#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ + +#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ +#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ +#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ +#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ +#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ +#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ +#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ +#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ +#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ +#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ +#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ +#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ +#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ + + +/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ +#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ +#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ +#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ +#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ +#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ + + +/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ +#define TWI0_REGBASE 0xFFC01400 +#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ +#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */ +#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ +#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ +#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ +#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ +#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ +#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ +#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ +#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ +#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ +#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ +#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ +#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ +#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ +#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ + + +/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ +#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ +#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ +#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ +#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ +#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ +#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ +#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ +#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ +#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ +#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ +#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ +#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ +#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ +#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ +#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ +#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ +#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ + + +/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ +#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ +#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ +#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ +#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ +#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ +#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ +#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ +#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ +#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ +#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ +#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ +#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ +#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ +#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ +#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ +#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ +#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ + + +/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ +#define UART1_THR 0xFFC02000 /* Transmit Holding register */ +#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ +#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ +#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ +#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ +#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ +#define UART1_LCR 0xFFC0200C /* Line Control Register */ +#define UART1_MCR 0xFFC02010 /* Modem Control Register */ +#define UART1_LSR 0xFFC02014 /* Line Status Register */ +#define UART1_MSR 0xFFC02018 /* Modem Status Register */ +#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ +#define UART1_GCTL 0xFFC02024 /* Global Control Register */ + + +/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */ + +/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ +#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ +#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ +#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ +#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ + + +/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ +#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ +#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ +#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ +#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */ +#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ +#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ +#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ + +#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ +#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ +#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ +#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */ +#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ +#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ +#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ + +/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ +#define PORTF_MUX 0xFFC03210 /* Port F mux control */ +#define PORTG_MUX 0xFFC03214 /* Port G mux control */ +#define PORTH_MUX 0xFFC03218 /* Port H mux control */ +#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */ +#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */ +#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */ +#define PORTF_SLEW 0xFFC03230 /* Port F slew control */ +#define PORTG_SLEW 0xFFC03234 /* Port G slew control */ +#define PORTH_SLEW 0xFFC03238 /* Port H slew control */ +#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */ +#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */ +#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */ +#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */ +#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */ +#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */ + + +/*********************************************************************************** +** System MMR Register Bits And Macros +** +** Disclaimer: All macros are intended to make C and Assembly code more readable. +** Use these macros carefully, as any that do left shifts for field +** depositing will result in the lower order bits being destroyed. Any +** macro that shifts left to properly position the bit-field should be +** used as part of an OR to initialize a register and NOT as a dynamic +** modifier UNLESS the lower order bits are saved and ORed back in when +** the macro is used. +*************************************************************************************/ + +/* CHIPID Masks */ +#define CHIPID_VERSION 0xF0000000 +#define CHIPID_FAMILY 0x0FFFF000 +#define CHIPID_MANUFACTURE 0x00000FFE + +/* SWRST Masks */ +#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ +#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ +#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ +#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ +#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ + +/* SYSCR Masks */ +#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */ +#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ + + +/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ +/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ + +#if 0 +#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ + +#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ +#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */ +#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */ +#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */ +#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */ +#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */ +#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */ + +#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */ +#define IRQ_TWI 0x00000200 /* TWI Interrupt */ +#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */ +#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */ +#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */ +#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */ +#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */ +#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */ + +#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */ +#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */ +#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */ +#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */ +#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */ +#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */ +#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */ +#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */ +#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */ +#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */ + +#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */ +#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */ +#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */ +#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */ +#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */ +#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */ +#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */ +#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */ +#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */ +#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */ +#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */ +#endif + +/* SIC_IAR0 Macros */ +#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ +#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ +#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ +#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */ +#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ +#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ +#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ +#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ + +/* SIC_IAR1 Macros */ +#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */ +#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ +#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ +#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */ +#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ +#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ +#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ +#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ + +/* SIC_IAR2 Macros */ +#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */ +#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ +#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ +#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */ +#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ +#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ +#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ +#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ + +/* SIC_IAR3 Macros */ +#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */ +#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */ +#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */ +#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */ +#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */ +#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */ +#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */ +#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */ + + +/* SIC_IMASK Masks */ +#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ +#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ +#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ +#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ + +/* SIC_IWR Masks */ +#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ +#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ +#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ +#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ + +/* **************** GENERAL PURPOSE TIMER MASKS **********************/ +/* TIMER_ENABLE Masks */ +#define TIMEN0 0x0001 /* Enable Timer 0 */ +#define TIMEN1 0x0002 /* Enable Timer 1 */ +#define TIMEN2 0x0004 /* Enable Timer 2 */ +#define TIMEN3 0x0008 /* Enable Timer 3 */ +#define TIMEN4 0x0010 /* Enable Timer 4 */ +#define TIMEN5 0x0020 /* Enable Timer 5 */ +#define TIMEN6 0x0040 /* Enable Timer 6 */ +#define TIMEN7 0x0080 /* Enable Timer 7 */ + +/* TIMER_DISABLE Masks */ +#define TIMDIS0 TIMEN0 /* Disable Timer 0 */ +#define TIMDIS1 TIMEN1 /* Disable Timer 1 */ +#define TIMDIS2 TIMEN2 /* Disable Timer 2 */ +#define TIMDIS3 TIMEN3 /* Disable Timer 3 */ +#define TIMDIS4 TIMEN4 /* Disable Timer 4 */ +#define TIMDIS5 TIMEN5 /* Disable Timer 5 */ +#define TIMDIS6 TIMEN6 /* Disable Timer 6 */ +#define TIMDIS7 TIMEN7 /* Disable Timer 7 */ + +/* TIMER_STATUS Masks */ +#define TIMIL0 0x00000001 /* Timer 0 Interrupt */ +#define TIMIL1 0x00000002 /* Timer 1 Interrupt */ +#define TIMIL2 0x00000004 /* Timer 2 Interrupt */ +#define TIMIL3 0x00000008 /* Timer 3 Interrupt */ +#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ +#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ +#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ +#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ +#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ +#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ +#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ +#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ +#define TIMIL4 0x00010000 /* Timer 4 Interrupt */ +#define TIMIL5 0x00020000 /* Timer 5 Interrupt */ +#define TIMIL6 0x00040000 /* Timer 6 Interrupt */ +#define TIMIL7 0x00080000 /* Timer 7 Interrupt */ +#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ +#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ +#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ +#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ +#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ +#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ +#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ +#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ + +/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ +#define TOVL_ERR0 TOVF_ERR0 +#define TOVL_ERR1 TOVF_ERR1 +#define TOVL_ERR2 TOVF_ERR2 +#define TOVL_ERR3 TOVF_ERR3 +#define TOVL_ERR4 TOVF_ERR4 +#define TOVL_ERR5 TOVF_ERR5 +#define TOVL_ERR6 TOVF_ERR6 +#define TOVL_ERR7 TOVF_ERR7 + +/* TIMERx_CONFIG Masks */ +#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ +#define WDTH_CAP 0x0002 /* Width Capture Input Mode */ +#define EXT_CLK 0x0003 /* External Clock Mode */ +#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ +#define PERIOD_CNT 0x0008 /* Period Count */ +#define IRQ_ENA 0x0010 /* Interrupt Request Enable */ +#define TIN_SEL 0x0020 /* Timer Input Select */ +#define OUT_DIS 0x0040 /* Output Pad Disable */ +#define CLK_SEL 0x0080 /* Timer Clock Select */ +#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ +#define EMU_RUN 0x0200 /* Emulation Behavior Select */ +#define ERR_TYP 0xC000 /* Error Type */ + +/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ +/* EBIU_AMGCTL Masks */ +#define AMCKEN 0x0001 /* Enable CLKOUT */ +#define AMBEN_NONE 0x0000 /* All Banks Disabled */ +#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ +#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ +#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ +#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ + +/* EBIU_AMBCTL0 Masks */ +#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */ +#define B0RDYPOL 0x00000002 /* B0 RDY Active High */ +#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */ +#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */ +#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */ +#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */ +#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */ +#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */ +#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */ +#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */ +#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */ +#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */ +#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */ +#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */ +#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */ +#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */ +#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */ +#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */ +#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */ +#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */ +#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */ +#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */ +#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */ +#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */ +#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */ +#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */ +#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */ +#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */ +#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */ +#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */ +#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */ +#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */ +#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */ +#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */ +#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */ +#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */ +#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */ +#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */ +#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */ +#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */ +#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */ +#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */ +#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */ +#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */ + +#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */ +#define B1RDYPOL 0x00020000 /* B1 RDY Active High */ +#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */ +#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */ +#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */ +#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */ +#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */ +#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */ +#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */ +#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */ +#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */ +#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */ +#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */ +#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */ +#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */ +#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */ +#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */ +#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */ +#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */ +#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */ +#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */ +#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */ +#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */ +#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */ +#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */ +#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */ +#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */ +#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */ +#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */ +#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */ +#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */ +#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */ +#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */ +#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */ +#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */ +#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */ +#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */ +#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */ +#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */ +#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */ +#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */ +#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */ +#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */ +#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */ + +/* EBIU_AMBCTL1 Masks */ +#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */ +#define B2RDYPOL 0x00000002 /* B2 RDY Active High */ +#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */ +#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */ +#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */ +#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */ +#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */ +#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */ +#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */ +#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */ +#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */ +#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */ +#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */ +#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */ +#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */ +#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */ +#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */ +#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */ +#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */ +#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */ +#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */ +#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */ +#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */ +#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */ +#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */ +#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */ +#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */ +#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */ +#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */ +#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */ +#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */ +#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */ +#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */ +#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */ +#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */ +#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */ +#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */ +#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */ +#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */ +#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */ +#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */ +#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */ +#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */ +#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */ + +#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */ +#define B3RDYPOL 0x00020000 /* B3 RDY Active High */ +#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */ +#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */ +#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */ +#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */ +#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */ +#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */ +#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */ +#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */ +#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */ +#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */ +#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */ +#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */ +#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */ +#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */ +#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */ +#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */ +#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */ +#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */ +#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */ +#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */ +#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */ +#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */ +#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */ +#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */ +#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */ +#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */ +#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */ +#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */ +#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */ +#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */ +#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */ +#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */ +#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */ +#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */ +#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */ +#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */ +#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */ +#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */ +#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */ +#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */ +#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */ +#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */ + + +/* ********************** SDRAM CONTROLLER MASKS **********************************************/ +/* EBIU_SDGCTL Masks */ +#define SCTLE 0x00000001 /* Enable SDRAM Signals */ +#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */ +#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ +#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ +#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ +#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ +#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ +#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ +#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ +#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ +#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ +#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ +#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ +#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ +#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ +#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ +#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ +#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ +#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ +#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ +#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ +#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ +#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ +#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ +#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ +#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ +#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ +#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ +#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ +#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ +#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ +#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ +#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ +#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ +#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ +#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ +#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ +#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ +#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */ +#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */ +#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */ +#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */ +#define EBUFE 0x02000000 /* Enable External Buffering Timing */ +#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */ +#define EMREN 0x10000000 /* Extended Mode Register Enable */ +#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */ +#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */ + +/* EBIU_SDBCTL Masks */ +#define EBE 0x0001 /* Enable SDRAM External Bank */ +#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */ +#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ +#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ +#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ +#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */ +#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */ +#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ +#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ +#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ +#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */ + +/* EBIU_SDSTAT Masks */ +#define SDCI 0x0001 /* SDRAM Controller Idle */ +#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */ +#define SDPUA 0x0004 /* SDRAM Power-Up Active */ +#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */ +#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */ +#define BGSTAT 0x0020 /* Bus Grant Status */ + + +/* ************************** DMA CONTROLLER MASKS ********************************/ + +/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ +#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ +#define PMAP 0xF000 /* Peripheral Mapped To This Channel */ +#define PMAP_PPI 0x0000 /* PPI Port DMA */ +#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */ +#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */ +#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */ +#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */ +#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */ +#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */ +#define PMAP_SPI 0x7000 /* SPI Port DMA */ +#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */ +#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */ +#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ +#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ + +/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ +/* PPI_CONTROL Masks */ +#define PORT_EN 0x0001 /* PPI Port Enable */ +#define PORT_DIR 0x0002 /* PPI Port Direction */ +#define XFR_TYPE 0x000C /* PPI Transfer Type */ +#define PORT_CFG 0x0030 /* PPI Port Configuration */ +#define FLD_SEL 0x0040 /* PPI Active Field Select */ +#define PACK_EN 0x0080 /* PPI Packing Mode */ +#define DMA32 0x0100 /* PPI 32-bit DMA Enable */ +#define SKIP_EN 0x0200 /* PPI Skip Element Enable */ +#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ +#define DLEN_8 0x0000 /* Data Length = 8 Bits */ +#define DLEN_10 0x0800 /* Data Length = 10 Bits */ +#define DLEN_11 0x1000 /* Data Length = 11 Bits */ +#define DLEN_12 0x1800 /* Data Length = 12 Bits */ +#define DLEN_13 0x2000 /* Data Length = 13 Bits */ +#define DLEN_14 0x2800 /* Data Length = 14 Bits */ +#define DLEN_15 0x3000 /* Data Length = 15 Bits */ +#define DLEN_16 0x3800 /* Data Length = 16 Bits */ +#define DLENGTH 0x3800 /* PPI Data Length */ +#define POLC 0x4000 /* PPI Clock Polarity */ +#define POLS 0x8000 /* PPI Frame Sync Polarity */ + +/* PPI_STATUS Masks */ +#define FLD 0x0400 /* Field Indicator */ +#define FT_ERR 0x0800 /* Frame Track Error */ +#define OVR 0x1000 /* FIFO Overflow Error */ +#define UNDR 0x2000 /* FIFO Underrun Error */ +#define ERR_DET 0x4000 /* Error Detected Indicator */ +#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ + + +/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/ +/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ +#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ +#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ + +/* TWI_PRESCALE Masks */ +#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ +#define TWI_ENA 0x0080 /* TWI Enable */ +#define SCCB 0x0200 /* SCCB Compatibility Enable */ + +/* TWI_SLAVE_CTL Masks */ +#define SEN 0x0001 /* Slave Enable */ +#define SADD_LEN 0x0002 /* Slave Address Length */ +#define STDVAL 0x0004 /* Slave Transmit Data Valid */ +#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ +#define GEN 0x0010 /* General Call Adrress Matching Enabled */ + +/* TWI_SLAVE_STAT Masks */ +#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ +#define GCALL 0x0002 /* General Call Indicator */ + +/* TWI_MASTER_CTL Masks */ +#define MEN 0x0001 /* Master Mode Enable */ +#define MADD_LEN 0x0002 /* Master Address Length */ +#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ +#define FAST 0x0008 /* Use Fast Mode Timing Specs */ +#define STOP 0x0010 /* Issue Stop Condition */ +#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ +#define DCNT 0x3FC0 /* Data Bytes To Transfer */ +#define SDAOVR 0x4000 /* Serial Data Override */ +#define SCLOVR 0x8000 /* Serial Clock Override */ + +/* TWI_MASTER_STAT Masks */ +#define MPROG 0x0001 /* Master Transfer In Progress */ +#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ +#define ANAK 0x0004 /* Address Not Acknowledged */ +#define DNAK 0x0008 /* Data Not Acknowledged */ +#define BUFRDERR 0x0010 /* Buffer Read Error */ +#define BUFWRERR 0x0020 /* Buffer Write Error */ +#define SDASEN 0x0040 /* Serial Data Sense */ +#define SCLSEN 0x0080 /* Serial Clock Sense */ +#define BUSBUSY 0x0100 /* Bus Busy Indicator */ + +/* TWI_INT_SRC and TWI_INT_ENABLE Masks */ +#define SINIT 0x0001 /* Slave Transfer Initiated */ +#define SCOMP 0x0002 /* Slave Transfer Complete */ +#define SERR 0x0004 /* Slave Transfer Error */ +#define SOVF 0x0008 /* Slave Overflow */ +#define MCOMP 0x0010 /* Master Transfer Complete */ +#define MERR 0x0020 /* Master Transfer Error */ +#define XMTSERV 0x0040 /* Transmit FIFO Service */ +#define RCVSERV 0x0080 /* Receive FIFO Service */ + +/* TWI_FIFO_CTRL Masks */ +#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ +#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ +#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ +#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ + +/* TWI_FIFO_STAT Masks */ +#define XMTSTAT 0x0003 /* Transmit FIFO Status */ +#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ +#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ +#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ + +#define RCVSTAT 0x000C /* Receive FIFO Status */ +#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ +#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ +#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ + + +/* Omit CAN masks from defBF534.h */ + +/* ******************* PIN CONTROL REGISTER MASKS ************************/ +/* PORT_MUX Masks */ +#define PJSE 0x0001 /* Port J SPI/SPORT Enable */ +#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */ +#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */ + +#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */ +#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */ +#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */ +#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */ + +#define PFDE 0x0008 /* Port F DMA Request Enable */ +#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */ +#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */ + +#define PFTE 0x0010 /* Port F Timer Enable */ +#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */ +#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */ + +#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */ +#define PFS6E_TIMER 0x0000 /* Enable TMR5 */ +#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */ + +#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */ +#define PFS5E_TIMER 0x0000 /* Enable TMR4 */ +#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */ + +#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */ +#define PFS4E_TIMER 0x0000 /* Enable TMR3 */ +#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */ + +#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */ +#define PFFE_TIMER 0x0000 /* Enable TMR2 */ +#define PFFE_PPI 0x0100 /* Enable PPI FS3 */ + +#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */ +#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */ +#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */ + +#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */ +#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */ +#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */ + +#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */ +#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ +#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ + + +/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/ +/* HDMAx_CTL Masks */ +#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */ +#define REP 0x0002 /* HDMA Request Polarity */ +#define UTE 0x0004 /* Urgency Threshold Enable */ +#define OIE 0x0010 /* Overflow Interrupt Enable */ +#define BDIE 0x0020 /* Block Done Interrupt Enable */ +#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */ +#define DRQ 0x0300 /* HDMA Request Type */ +#define DRQ_NONE 0x0000 /* No Request */ +#define DRQ_SINGLE 0x0100 /* Channels Request Single */ +#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */ +#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */ +#define RBC 0x1000 /* Reload BCNT With IBCNT */ +#define PS 0x2000 /* HDMA Pin Status */ +#define OI 0x4000 /* Overflow Interrupt Generated */ +#define BDI 0x8000 /* Block Done Interrupt Generated */ + +/* entry addresses of the user-callable Boot ROM functions */ + +#define _BOOTROM_RESET 0xEF000000 +#define _BOOTROM_FINAL_INIT 0xEF000002 +#define _BOOTROM_DO_MEMORY_DMA 0xEF000006 +#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 +#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A +#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C +#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 +#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 +#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 + +/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ +#define PGDE_UART PFDE_UART +#define PGDE_DMA PFDE_DMA +#define CKELOW SCKELOW + +/* ==== end from defBF534.h ==== */ + +/* HOST Port Registers */ + +#define HOST_CONTROL 0xffc03400 /* HOST Control Register */ +#define HOST_STATUS 0xffc03404 /* HOST Status Register */ +#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */ + +/* Counter Registers */ + +#define CNT_CONFIG 0xffc03500 /* Configuration Register */ +#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */ +#define CNT_STATUS 0xffc03508 /* Status Register */ +#define CNT_COMMAND 0xffc0350c /* Command Register */ +#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */ +#define CNT_COUNTER 0xffc03514 /* Counter Register */ +#define CNT_MAX 0xffc03518 /* Maximal Count Register */ +#define CNT_MIN 0xffc0351c /* Minimal Count Register */ + +/* OTP/FUSE Registers */ + +#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */ +#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */ +#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */ +#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */ + +/* Security Registers */ + +#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */ +#define SECURE_CONTROL 0xffc03624 /* Secure Control */ +#define SECURE_STATUS 0xffc03628 /* Secure Status */ + +/* OTP Read/Write Data Buffer Registers */ + +#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ +#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ +#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ +#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ + +/* NFC Registers */ + +#define NFC_CTL 0xffc03700 /* NAND Control Register */ +#define NFC_STAT 0xffc03704 /* NAND Status Register */ +#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */ +#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */ +#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */ +#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */ +#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */ +#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */ +#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */ +#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */ +#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */ +#define NFC_READ 0xffc0372c /* NAND Read Data Register */ +#define NFC_ADDR 0xffc03740 /* NAND Address Register */ +#define NFC_CMD 0xffc03744 /* NAND Command Register */ +#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */ +#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */ + +/* ********************************************************** */ +/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ +/* and MULTI BIT READ MACROS */ +/* ********************************************************** */ + +/* Bit masks for HOST_CONTROL */ + +#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */ +#define HOST_CNTR_nHOST_EN 0x0 +#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */ +#define HOST_CNTR_nHOST_END 0x0 +#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */ +#define HOST_CNTR_nDATA_SIZE 0x0 +#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */ +#define HOST_CNTR_nHOST_RST 0x0 +#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */ +#define HOST_CNTR_nHRDY_OVR 0x0 +#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */ +#define HOST_CNTR_nINT_MODE 0x0 +#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */ +#define HOST_CNTR_ nBT_EN 0x0 +#define HOST_CNTR_EHW 0x100 /* Enable Host Write */ +#define HOST_CNTR_nEHW 0x0 +#define HOST_CNTR_EHR 0x200 /* Enable Host Read */ +#define HOST_CNTR_nEHR 0x0 +#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */ +#define HOST_CNTR_nBDR 0x0 + +/* Bit masks for HOST_STATUS */ + +#define HOST_STAT_READY 0x1 /* DMA Ready */ +#define HOST_STAT_nREADY 0x0 +#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */ +#define HOST_STAT_nFIFOFULL 0x0 +#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */ +#define HOST_STAT_nFIFOEMPTY 0x0 +#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */ +#define HOST_STAT_nCOMPLETE 0x0 +#define HOST_STAT_HSHK 0x10 /* Host Handshake */ +#define HOST_STAT_nHSHK 0x0 +#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */ +#define HOST_STAT_nTIMEOUT 0x0 +#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */ +#define HOST_STAT_nHIRQ 0x0 +#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */ +#define HOST_STAT_nALLOW_CNFG 0x0 +#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */ +#define HOST_STAT_nDMA_DIR 0x0 +#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */ +#define HOST_STAT_nBTE 0x0 +#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */ +#define HOST_STAT_nHOSTRD_DONE 0x0 + +/* Bit masks for HOST_TIMEOUT */ + +#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */ + +/* Bit masks for SECURE_SYSSWT */ + +#define EMUDABL 0x1 /* Emulation Disable. */ +#define nEMUDABL 0x0 +#define RSTDABL 0x2 /* Reset Disable */ +#define nRSTDABL 0x0 +#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ +#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ +#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ +#define DMA0OVR 0x800 /* DMA0 Memory Access Override */ +#define nDMA0OVR 0x0 +#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ +#define nDMA1OVR 0x0 +#define EMUOVR 0x4000 /* Emulation Override */ +#define nEMUOVR 0x0 +#define OTPSEN 0x8000 /* OTP Secrets Enable. */ +#define nOTPSEN 0x0 +#define L2DABL 0x70000 /* L2 Memory Disable. */ + +/* Bit masks for SECURE_CONTROL */ + +#define SECURE0 0x1 /* SECURE 0 */ +#define nSECURE0 0x0 +#define SECURE1 0x2 /* SECURE 1 */ +#define nSECURE1 0x0 +#define SECURE2 0x4 /* SECURE 2 */ +#define nSECURE2 0x0 +#define SECURE3 0x8 /* SECURE 3 */ +#define nSECURE3 0x0 + +/* Bit masks for SECURE_STATUS */ + +#define SECMODE 0x3 /* Secured Mode Control State */ +#define NMI 0x4 /* Non Maskable Interrupt */ +#define nNMI 0x0 +#define AFVALID 0x8 /* Authentication Firmware Valid */ +#define nAFVALID 0x0 +#define AFEXIT 0x10 /* Authentication Firmware Exit */ +#define nAFEXIT 0x0 +#define SECSTAT 0xe0 /* Secure Status */ #endif /* _DEF_BF522_H */ diff --git a/arch/blackfin/mach-bf527/include/mach/defBF525.h b/arch/blackfin/mach-bf527/include/mach/defBF525.h index c136f703296..cc383adfdff 100644 --- a/arch/blackfin/mach-bf527/include/mach/defBF525.h +++ b/arch/blackfin/mach-bf527/include/mach/defBF525.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Analog Devices Inc. + * Copyright 2007-2010 Analog Devices Inc. * * Licensed under the ADI BSD license or the GPL-2 (or later) */ diff --git a/arch/blackfin/mach-bf527/include/mach/defBF527.h b/arch/blackfin/mach-bf527/include/mach/defBF527.h index 4dd58fb3315..05369a92fbc 100644 --- a/arch/blackfin/mach-bf527/include/mach/defBF527.h +++ b/arch/blackfin/mach-bf527/include/mach/defBF527.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Analog Devices Inc. + * Copyright 2007-2010 Analog Devices Inc. * * Licensed under the ADI BSD license or the GPL-2 (or later) */ diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h deleted file mode 100644 index 09475034c6a..00000000000 --- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h +++ /dev/null @@ -1,1506 +0,0 @@ -/* - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the ADI BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF52X_H -#define _DEF_BF52X_H - - -/* ************************************************************** */ -/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */ -/* ************************************************************** */ - -/* ==== begin from defBF534.h ==== */ - -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define CHIPID 0xFFC00014 /* Device ID Register */ - - -/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration Register */ -#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ - -#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ -#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ -#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ - -/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */ -#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ -#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ -#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ -#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ -#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */ -#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */ -#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ - - -/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ - - -/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ -#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */ - - -/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ -#define UART0_THR 0xFFC00400 /* Transmit Holding register */ -#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART0_LCR 0xFFC0040C /* Line Control Register */ -#define UART0_MCR 0xFFC00410 /* Modem Control Register */ -#define UART0_LSR 0xFFC00414 /* Line Status Register */ -#define UART0_MSR 0xFFC00418 /* Modem Status Register */ -#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART0_GCTL 0xFFC00424 /* Global Control Register */ - - -/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ -#define SPI0_REGBASE 0xFFC00500 -#define SPI_CTL 0xFFC00500 /* SPI Control Register */ -#define SPI_FLG 0xFFC00504 /* SPI Flag register */ -#define SPI_STAT 0xFFC00508 /* SPI Status register */ -#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ -#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ -#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ -#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ - - -/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ -#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ - -#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ - -#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ - -#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ -#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ -#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ -#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ - -#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ -#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ -#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ -#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ - -#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ -#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ -#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ -#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ - -#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ -#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ -#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ -#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */ - -#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ -#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ -#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ -#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ - -#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ -#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ -#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ - - -/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ -#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ -#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ -#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ -#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ -#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ -#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ -#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ -#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ -#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ -#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ -#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ -#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ -#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ -#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ -#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ -#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ -#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ - - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ - - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ - - -/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ -#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ -#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ -#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ -#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ - - -/* DMA Traffic Control Registers */ -#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ - -/* Alternate deprecated register names (below) provided for backwards code compatibility */ -#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ - -/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ - -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ - -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ - -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ - -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ - -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ - -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ - -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ - -#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ -#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ -#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ -#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ -#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ -#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ -#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ -#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ -#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ -#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ -#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ -#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ -#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ - -#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ -#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ -#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ -#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ -#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ -#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ -#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ -#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ -#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ -#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ -#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ -#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ -#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ - -#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ -#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ -#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ -#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ -#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ -#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ -#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ -#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ -#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ -#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ -#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ -#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ -#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ - -#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ -#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ -#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ -#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ -#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ -#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ -#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ -#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ -#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ -#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ -#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ -#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ -#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ - -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ - -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ -#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ -#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ - -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ - -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ -#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ -#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ - - -/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ -#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ -#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ -#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ -#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ -#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ - - -/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ -#define TWI0_REGBASE 0xFFC01400 -#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ -#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */ -#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ -#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ -#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ -#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ -#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ -#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ -#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ -#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ -#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ -#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ -#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ -#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ -#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ -#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ - - -/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ -#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ -#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ -#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ -#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ -#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ -#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ -#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ -#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ -#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ -#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ -#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ -#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ -#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ -#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ -#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ -#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ -#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ - - -/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ -#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ -#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ -#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ -#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ -#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ -#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ -#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ -#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ -#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ -#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ -#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ -#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ -#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ -#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ -#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ -#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ -#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ - - -/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ -#define UART1_THR 0xFFC02000 /* Transmit Holding register */ -#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ -#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ -#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ -#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ -#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ -#define UART1_LCR 0xFFC0200C /* Line Control Register */ -#define UART1_MCR 0xFFC02010 /* Modem Control Register */ -#define UART1_LSR 0xFFC02014 /* Line Status Register */ -#define UART1_MSR 0xFFC02018 /* Modem Status Register */ -#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ -#define UART1_GCTL 0xFFC02024 /* Global Control Register */ - - -/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */ - -/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ -#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ -#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ -#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ -#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ - - -/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ -#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ -#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ -#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ -#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */ -#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ -#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ -#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ - -#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ -#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ -#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ -#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */ -#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ -#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ -#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ - -/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ -#define PORTF_MUX 0xFFC03210 /* Port F mux control */ -#define PORTG_MUX 0xFFC03214 /* Port G mux control */ -#define PORTH_MUX 0xFFC03218 /* Port H mux control */ -#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */ -#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */ -#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */ -#define PORTF_SLEW 0xFFC03230 /* Port F slew control */ -#define PORTG_SLEW 0xFFC03234 /* Port G slew control */ -#define PORTH_SLEW 0xFFC03238 /* Port H slew control */ -#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */ -#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */ -#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */ -#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */ -#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */ -#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */ - - -/*********************************************************************************** -** System MMR Register Bits And Macros -** -** Disclaimer: All macros are intended to make C and Assembly code more readable. -** Use these macros carefully, as any that do left shifts for field -** depositing will result in the lower order bits being destroyed. Any -** macro that shifts left to properly position the bit-field should be -** used as part of an OR to initialize a register and NOT as a dynamic -** modifier UNLESS the lower order bits are saved and ORed back in when -** the macro is used. -*************************************************************************************/ - -/* CHIPID Masks */ -#define CHIPID_VERSION 0xF0000000 -#define CHIPID_FAMILY 0x0FFFF000 -#define CHIPID_MANUFACTURE 0x00000FFE - -/* SWRST Masks */ -#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ -#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ -#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ -#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ -#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ - -/* SYSCR Masks */ -#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */ -#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ - - -/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ -/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ - -#if 0 -#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ - -#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ -#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */ -#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */ -#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */ -#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */ -#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */ -#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */ - -#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */ -#define IRQ_TWI 0x00000200 /* TWI Interrupt */ -#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */ -#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */ -#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */ -#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */ -#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */ -#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */ - -#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */ -#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */ -#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */ -#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */ -#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */ -#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */ -#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */ -#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */ -#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */ -#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */ - -#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */ -#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */ -#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */ -#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */ -#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */ -#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */ -#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */ -#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */ -#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */ -#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */ -#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */ -#endif - -/* SIC_IAR0 Macros */ -#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ -#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ -#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ -#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */ -#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ -#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ -#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ -#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ - -/* SIC_IAR1 Macros */ -#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */ -#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ -#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ -#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */ -#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ -#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ -#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ -#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ - -/* SIC_IAR2 Macros */ -#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */ -#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ -#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ -#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */ -#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ -#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ -#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ -#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ - -/* SIC_IAR3 Macros */ -#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */ -#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */ -#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */ -#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */ -#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */ -#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */ -#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */ -#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */ - - -/* SIC_IMASK Masks */ -#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ -#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ -#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ -#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ - -/* SIC_IWR Masks */ -#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ -#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ -#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ -#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ - - -/* ************** UART CONTROLLER MASKS *************************/ -/* UARTx_LCR Masks */ -#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ -#define STB 0x04 /* Stop Bits */ -#define PEN 0x08 /* Parity Enable */ -#define EPS 0x10 /* Even Parity Select */ -#define STP 0x20 /* Stick Parity */ -#define SB 0x40 /* Set Break */ -#define DLAB 0x80 /* Divisor Latch Access */ - -/* UARTx_MCR Mask */ -#define LOOP_ENA 0x10 /* Loopback Mode Enable */ -#define LOOP_ENA_P 0x04 - -/* UARTx_LSR Masks */ -#define DR 0x01 /* Data Ready */ -#define OE 0x02 /* Overrun Error */ -#define PE 0x04 /* Parity Error */ -#define FE 0x08 /* Framing Error */ -#define BI 0x10 /* Break Interrupt */ -#define THRE 0x20 /* THR Empty */ -#define TEMT 0x40 /* TSR and UART_THR Empty */ - -/* UARTx_IER Masks */ -#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ -#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ -#define ELSI 0x04 /* Enable RX Status Interrupt */ - -/* UARTx_IIR Masks */ -#define NINT 0x01 /* Pending Interrupt */ -#define IIR_TX_READY 0x02 /* UART_THR empty */ -#define IIR_RX_READY 0x04 /* Receive data ready */ -#define IIR_LINE_CHANGE 0x06 /* Receive line status */ -#define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */ - -/* UARTx_GCTL Masks */ -#define UCEN 0x01 /* Enable UARTx Clocks */ -#define IREN 0x02 /* Enable IrDA Mode */ -#define TPOLC 0x04 /* IrDA TX Polarity Change */ -#define RPOLC 0x08 /* IrDA RX Polarity Change */ -#define FPE 0x10 /* Force Parity Error On Transmit */ -#define FFE 0x20 /* Force Framing Error On Transmit */ - - -/* **************** GENERAL PURPOSE TIMER MASKS **********************/ -/* TIMER_ENABLE Masks */ -#define TIMEN0 0x0001 /* Enable Timer 0 */ -#define TIMEN1 0x0002 /* Enable Timer 1 */ -#define TIMEN2 0x0004 /* Enable Timer 2 */ -#define TIMEN3 0x0008 /* Enable Timer 3 */ -#define TIMEN4 0x0010 /* Enable Timer 4 */ -#define TIMEN5 0x0020 /* Enable Timer 5 */ -#define TIMEN6 0x0040 /* Enable Timer 6 */ -#define TIMEN7 0x0080 /* Enable Timer 7 */ - -/* TIMER_DISABLE Masks */ -#define TIMDIS0 TIMEN0 /* Disable Timer 0 */ -#define TIMDIS1 TIMEN1 /* Disable Timer 1 */ -#define TIMDIS2 TIMEN2 /* Disable Timer 2 */ -#define TIMDIS3 TIMEN3 /* Disable Timer 3 */ -#define TIMDIS4 TIMEN4 /* Disable Timer 4 */ -#define TIMDIS5 TIMEN5 /* Disable Timer 5 */ -#define TIMDIS6 TIMEN6 /* Disable Timer 6 */ -#define TIMDIS7 TIMEN7 /* Disable Timer 7 */ - -/* TIMER_STATUS Masks */ -#define TIMIL0 0x00000001 /* Timer 0 Interrupt */ -#define TIMIL1 0x00000002 /* Timer 1 Interrupt */ -#define TIMIL2 0x00000004 /* Timer 2 Interrupt */ -#define TIMIL3 0x00000008 /* Timer 3 Interrupt */ -#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ -#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ -#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ -#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ -#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ -#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ -#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ -#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ -#define TIMIL4 0x00010000 /* Timer 4 Interrupt */ -#define TIMIL5 0x00020000 /* Timer 5 Interrupt */ -#define TIMIL6 0x00040000 /* Timer 6 Interrupt */ -#define TIMIL7 0x00080000 /* Timer 7 Interrupt */ -#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ -#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ -#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ -#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ -#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ -#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ -#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ -#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ - -/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ -#define TOVL_ERR0 TOVF_ERR0 -#define TOVL_ERR1 TOVF_ERR1 -#define TOVL_ERR2 TOVF_ERR2 -#define TOVL_ERR3 TOVF_ERR3 -#define TOVL_ERR4 TOVF_ERR4 -#define TOVL_ERR5 TOVF_ERR5 -#define TOVL_ERR6 TOVF_ERR6 -#define TOVL_ERR7 TOVF_ERR7 - -/* TIMERx_CONFIG Masks */ -#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ -#define WDTH_CAP 0x0002 /* Width Capture Input Mode */ -#define EXT_CLK 0x0003 /* External Clock Mode */ -#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ -#define PERIOD_CNT 0x0008 /* Period Count */ -#define IRQ_ENA 0x0010 /* Interrupt Request Enable */ -#define TIN_SEL 0x0020 /* Timer Input Select */ -#define OUT_DIS 0x0040 /* Output Pad Disable */ -#define CLK_SEL 0x0080 /* Timer Clock Select */ -#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ -#define EMU_RUN 0x0200 /* Emulation Behavior Select */ -#define ERR_TYP 0xC000 /* Error Type */ - - -/* ****************** GPIO PORTS F, G, H MASKS ***********************/ -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ -/* Port F Masks */ -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - -/* Port G Masks */ -#define PG0 0x0001 -#define PG1 0x0002 -#define PG2 0x0004 -#define PG3 0x0008 -#define PG4 0x0010 -#define PG5 0x0020 -#define PG6 0x0040 -#define PG7 0x0080 -#define PG8 0x0100 -#define PG9 0x0200 -#define PG10 0x0400 -#define PG11 0x0800 -#define PG12 0x1000 -#define PG13 0x2000 -#define PG14 0x4000 -#define PG15 0x8000 - -/* Port H Masks */ -#define PH0 0x0001 -#define PH1 0x0002 -#define PH2 0x0004 -#define PH3 0x0008 -#define PH4 0x0010 -#define PH5 0x0020 -#define PH6 0x0040 -#define PH7 0x0080 -#define PH8 0x0100 -#define PH9 0x0200 -#define PH10 0x0400 -#define PH11 0x0800 -#define PH12 0x1000 -#define PH13 0x2000 -#define PH14 0x4000 -#define PH15 0x8000 - -/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ -/* EBIU_AMGCTL Masks */ -#define AMCKEN 0x0001 /* Enable CLKOUT */ -#define AMBEN_NONE 0x0000 /* All Banks Disabled */ -#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ -#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ -#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ -#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ - -/* EBIU_AMBCTL0 Masks */ -#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */ -#define B0RDYPOL 0x00000002 /* B0 RDY Active High */ -#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */ -#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */ -#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */ -#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */ -#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */ -#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */ -#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */ -#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */ -#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */ -#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */ -#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */ -#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */ -#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */ -#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */ -#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */ -#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */ -#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */ -#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */ -#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */ -#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */ -#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */ -#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */ -#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */ -#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */ -#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */ -#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */ -#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */ -#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */ -#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */ -#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */ -#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */ -#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */ -#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */ -#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */ - -#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */ -#define B1RDYPOL 0x00020000 /* B1 RDY Active High */ -#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */ -#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */ -#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */ -#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */ -#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */ -#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */ -#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */ -#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */ -#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */ -#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */ -#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */ -#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */ -#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */ -#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */ -#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */ -#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */ -#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */ -#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */ -#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */ -#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */ -#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */ -#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */ -#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */ -#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */ -#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */ -#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */ -#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */ -#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */ -#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */ -#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */ -#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */ -#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */ -#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */ -#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */ - -/* EBIU_AMBCTL1 Masks */ -#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */ -#define B2RDYPOL 0x00000002 /* B2 RDY Active High */ -#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */ -#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */ -#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */ -#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */ -#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */ -#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */ -#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */ -#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */ -#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */ -#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */ -#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */ -#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */ -#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */ -#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */ -#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */ -#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */ -#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */ -#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */ -#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */ -#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */ -#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */ -#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */ -#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */ -#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */ -#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */ -#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */ -#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */ -#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */ -#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */ -#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */ -#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */ -#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */ -#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */ -#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */ - -#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */ -#define B3RDYPOL 0x00020000 /* B3 RDY Active High */ -#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */ -#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */ -#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */ -#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */ -#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */ -#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */ -#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */ -#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */ -#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */ -#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */ -#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */ -#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */ -#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */ -#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */ -#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */ -#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */ -#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */ -#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */ -#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */ -#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */ -#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */ -#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */ -#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */ -#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */ -#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */ -#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */ -#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */ -#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */ -#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */ -#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */ -#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */ -#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */ -#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */ -#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */ - - -/* ********************** SDRAM CONTROLLER MASKS **********************************************/ -/* EBIU_SDGCTL Masks */ -#define SCTLE 0x00000001 /* Enable SDRAM Signals */ -#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */ -#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ -#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ -#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ -#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ -#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ -#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ -#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ -#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ -#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ -#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ -#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ -#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ -#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ -#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ -#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ -#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ -#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ -#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ -#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ -#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ -#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ -#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ -#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ -#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ -#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ -#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ -#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ -#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ -#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ -#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ -#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ -#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ -#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ -#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ -#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ -#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ -#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */ -#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */ -#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */ -#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */ -#define EBUFE 0x02000000 /* Enable External Buffering Timing */ -#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */ -#define EMREN 0x10000000 /* Extended Mode Register Enable */ -#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */ -#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */ - -/* EBIU_SDBCTL Masks */ -#define EBE 0x0001 /* Enable SDRAM External Bank */ -#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */ -#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ -#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ -#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ -#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */ -#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */ -#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ -#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ -#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ -#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */ - -/* EBIU_SDSTAT Masks */ -#define SDCI 0x0001 /* SDRAM Controller Idle */ -#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */ -#define SDPUA 0x0004 /* SDRAM Power-Up Active */ -#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */ -#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */ -#define BGSTAT 0x0020 /* Bus Grant Status */ - - -/* ************************** DMA CONTROLLER MASKS ********************************/ - -/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ -#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ -#define PMAP 0xF000 /* Peripheral Mapped To This Channel */ -#define PMAP_PPI 0x0000 /* PPI Port DMA */ -#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */ -#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */ -#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */ -#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */ -#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */ -#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */ -#define PMAP_SPI 0x7000 /* SPI Port DMA */ -#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */ -#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */ -#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ -#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ - -/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ -/* PPI_CONTROL Masks */ -#define PORT_EN 0x0001 /* PPI Port Enable */ -#define PORT_DIR 0x0002 /* PPI Port Direction */ -#define XFR_TYPE 0x000C /* PPI Transfer Type */ -#define PORT_CFG 0x0030 /* PPI Port Configuration */ -#define FLD_SEL 0x0040 /* PPI Active Field Select */ -#define PACK_EN 0x0080 /* PPI Packing Mode */ -#define DMA32 0x0100 /* PPI 32-bit DMA Enable */ -#define SKIP_EN 0x0200 /* PPI Skip Element Enable */ -#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ -#define DLEN_8 0x0000 /* Data Length = 8 Bits */ -#define DLEN_10 0x0800 /* Data Length = 10 Bits */ -#define DLEN_11 0x1000 /* Data Length = 11 Bits */ -#define DLEN_12 0x1800 /* Data Length = 12 Bits */ -#define DLEN_13 0x2000 /* Data Length = 13 Bits */ -#define DLEN_14 0x2800 /* Data Length = 14 Bits */ -#define DLEN_15 0x3000 /* Data Length = 15 Bits */ -#define DLEN_16 0x3800 /* Data Length = 16 Bits */ -#define DLENGTH 0x3800 /* PPI Data Length */ -#define POLC 0x4000 /* PPI Clock Polarity */ -#define POLS 0x8000 /* PPI Frame Sync Polarity */ - -/* PPI_STATUS Masks */ -#define FLD 0x0400 /* Field Indicator */ -#define FT_ERR 0x0800 /* Frame Track Error */ -#define OVR 0x1000 /* FIFO Overflow Error */ -#define UNDR 0x2000 /* FIFO Underrun Error */ -#define ERR_DET 0x4000 /* Error Detected Indicator */ -#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ - - -/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/ -/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ -#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ -#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ - -/* TWI_PRESCALE Masks */ -#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ -#define TWI_ENA 0x0080 /* TWI Enable */ -#define SCCB 0x0200 /* SCCB Compatibility Enable */ - -/* TWI_SLAVE_CTL Masks */ -#define SEN 0x0001 /* Slave Enable */ -#define SADD_LEN 0x0002 /* Slave Address Length */ -#define STDVAL 0x0004 /* Slave Transmit Data Valid */ -#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ -#define GEN 0x0010 /* General Call Adrress Matching Enabled */ - -/* TWI_SLAVE_STAT Masks */ -#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ -#define GCALL 0x0002 /* General Call Indicator */ - -/* TWI_MASTER_CTL Masks */ -#define MEN 0x0001 /* Master Mode Enable */ -#define MADD_LEN 0x0002 /* Master Address Length */ -#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ -#define FAST 0x0008 /* Use Fast Mode Timing Specs */ -#define STOP 0x0010 /* Issue Stop Condition */ -#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ -#define DCNT 0x3FC0 /* Data Bytes To Transfer */ -#define SDAOVR 0x4000 /* Serial Data Override */ -#define SCLOVR 0x8000 /* Serial Clock Override */ - -/* TWI_MASTER_STAT Masks */ -#define MPROG 0x0001 /* Master Transfer In Progress */ -#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ -#define ANAK 0x0004 /* Address Not Acknowledged */ -#define DNAK 0x0008 /* Data Not Acknowledged */ -#define BUFRDERR 0x0010 /* Buffer Read Error */ -#define BUFWRERR 0x0020 /* Buffer Write Error */ -#define SDASEN 0x0040 /* Serial Data Sense */ -#define SCLSEN 0x0080 /* Serial Clock Sense */ -#define BUSBUSY 0x0100 /* Bus Busy Indicator */ - -/* TWI_INT_SRC and TWI_INT_ENABLE Masks */ -#define SINIT 0x0001 /* Slave Transfer Initiated */ -#define SCOMP 0x0002 /* Slave Transfer Complete */ -#define SERR 0x0004 /* Slave Transfer Error */ -#define SOVF 0x0008 /* Slave Overflow */ -#define MCOMP 0x0010 /* Master Transfer Complete */ -#define MERR 0x0020 /* Master Transfer Error */ -#define XMTSERV 0x0040 /* Transmit FIFO Service */ -#define RCVSERV 0x0080 /* Receive FIFO Service */ - -/* TWI_FIFO_CTRL Masks */ -#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ -#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ -#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ -#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ - -/* TWI_FIFO_STAT Masks */ -#define XMTSTAT 0x0003 /* Transmit FIFO Status */ -#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ -#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ -#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ - -#define RCVSTAT 0x000C /* Receive FIFO Status */ -#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ -#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ -#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ - - -/* Omit CAN masks from defBF534.h */ - -/* ******************* PIN CONTROL REGISTER MASKS ************************/ -/* PORT_MUX Masks */ -#define PJSE 0x0001 /* Port J SPI/SPORT Enable */ -#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */ -#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */ - -#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */ -#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */ -#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */ -#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */ - -#define PFDE 0x0008 /* Port F DMA Request Enable */ -#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */ -#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */ - -#define PFTE 0x0010 /* Port F Timer Enable */ -#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */ -#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */ - -#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */ -#define PFS6E_TIMER 0x0000 /* Enable TMR5 */ -#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */ - -#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */ -#define PFS5E_TIMER 0x0000 /* Enable TMR4 */ -#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */ - -#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */ -#define PFS4E_TIMER 0x0000 /* Enable TMR3 */ -#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */ - -#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */ -#define PFFE_TIMER 0x0000 /* Enable TMR2 */ -#define PFFE_PPI 0x0100 /* Enable PPI FS3 */ - -#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */ -#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */ -#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */ - -#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */ -#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */ -#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */ - -#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */ -#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ -#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ - - -/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/ -/* HDMAx_CTL Masks */ -#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */ -#define REP 0x0002 /* HDMA Request Polarity */ -#define UTE 0x0004 /* Urgency Threshold Enable */ -#define OIE 0x0010 /* Overflow Interrupt Enable */ -#define BDIE 0x0020 /* Block Done Interrupt Enable */ -#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */ -#define DRQ 0x0300 /* HDMA Request Type */ -#define DRQ_NONE 0x0000 /* No Request */ -#define DRQ_SINGLE 0x0100 /* Channels Request Single */ -#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */ -#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */ -#define RBC 0x1000 /* Reload BCNT With IBCNT */ -#define PS 0x2000 /* HDMA Pin Status */ -#define OI 0x4000 /* Overflow Interrupt Generated */ -#define BDI 0x8000 /* Block Done Interrupt Generated */ - -/* entry addresses of the user-callable Boot ROM functions */ - -#define _BOOTROM_RESET 0xEF000000 -#define _BOOTROM_FINAL_INIT 0xEF000002 -#define _BOOTROM_DO_MEMORY_DMA 0xEF000006 -#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 -#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A -#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C -#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 -#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 -#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 - -/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ -#define PGDE_UART PFDE_UART -#define PGDE_DMA PFDE_DMA -#define CKELOW SCKELOW - -/* ==== end from defBF534.h ==== */ - -/* HOST Port Registers */ - -#define HOST_CONTROL 0xffc03400 /* HOST Control Register */ -#define HOST_STATUS 0xffc03404 /* HOST Status Register */ -#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */ - -/* Counter Registers */ - -#define CNT_CONFIG 0xffc03500 /* Configuration Register */ -#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */ -#define CNT_STATUS 0xffc03508 /* Status Register */ -#define CNT_COMMAND 0xffc0350c /* Command Register */ -#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */ -#define CNT_COUNTER 0xffc03514 /* Counter Register */ -#define CNT_MAX 0xffc03518 /* Maximal Count Register */ -#define CNT_MIN 0xffc0351c /* Minimal Count Register */ - -/* OTP/FUSE Registers */ - -#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */ -#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */ -#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */ -#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */ - -/* Security Registers */ - -#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */ -#define SECURE_CONTROL 0xffc03624 /* Secure Control */ -#define SECURE_STATUS 0xffc03628 /* Secure Status */ - -/* OTP Read/Write Data Buffer Registers */ - -#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ - -/* NFC Registers */ - -#define NFC_CTL 0xffc03700 /* NAND Control Register */ -#define NFC_STAT 0xffc03704 /* NAND Status Register */ -#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */ -#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */ -#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */ -#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */ -#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */ -#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */ -#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */ -#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */ -#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */ -#define NFC_READ 0xffc0372c /* NAND Read Data Register */ -#define NFC_ADDR 0xffc03740 /* NAND Address Register */ -#define NFC_CMD 0xffc03744 /* NAND Command Register */ -#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */ -#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */ - -/* ********************************************************** */ -/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ -/* and MULTI BIT READ MACROS */ -/* ********************************************************** */ - -/* Bit masks for HOST_CONTROL */ - -#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */ -#define HOST_CNTR_nHOST_EN 0x0 -#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */ -#define HOST_CNTR_nHOST_END 0x0 -#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */ -#define HOST_CNTR_nDATA_SIZE 0x0 -#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */ -#define HOST_CNTR_nHOST_RST 0x0 -#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */ -#define HOST_CNTR_nHRDY_OVR 0x0 -#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */ -#define HOST_CNTR_nINT_MODE 0x0 -#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */ -#define HOST_CNTR_ nBT_EN 0x0 -#define HOST_CNTR_EHW 0x100 /* Enable Host Write */ -#define HOST_CNTR_nEHW 0x0 -#define HOST_CNTR_EHR 0x200 /* Enable Host Read */ -#define HOST_CNTR_nEHR 0x0 -#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */ -#define HOST_CNTR_nBDR 0x0 - -/* Bit masks for HOST_STATUS */ - -#define HOST_STAT_READY 0x1 /* DMA Ready */ -#define HOST_STAT_nREADY 0x0 -#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */ -#define HOST_STAT_nFIFOFULL 0x0 -#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */ -#define HOST_STAT_nFIFOEMPTY 0x0 -#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */ -#define HOST_STAT_nCOMPLETE 0x0 -#define HOST_STAT_HSHK 0x10 /* Host Handshake */ -#define HOST_STAT_nHSHK 0x0 -#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */ -#define HOST_STAT_nTIMEOUT 0x0 -#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */ -#define HOST_STAT_nHIRQ 0x0 -#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */ -#define HOST_STAT_nALLOW_CNFG 0x0 -#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */ -#define HOST_STAT_nDMA_DIR 0x0 -#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */ -#define HOST_STAT_nBTE 0x0 -#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */ -#define HOST_STAT_nHOSTRD_DONE 0x0 - -/* Bit masks for HOST_TIMEOUT */ - -#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */ - -/* Bit masks for SECURE_SYSSWT */ - -#define EMUDABL 0x1 /* Emulation Disable. */ -#define nEMUDABL 0x0 -#define RSTDABL 0x2 /* Reset Disable */ -#define nRSTDABL 0x0 -#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ -#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ -#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ -#define DMA0OVR 0x800 /* DMA0 Memory Access Override */ -#define nDMA0OVR 0x0 -#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ -#define nDMA1OVR 0x0 -#define EMUOVR 0x4000 /* Emulation Override */ -#define nEMUOVR 0x0 -#define OTPSEN 0x8000 /* OTP Secrets Enable. */ -#define nOTPSEN 0x0 -#define L2DABL 0x70000 /* L2 Memory Disable. */ - -/* Bit masks for SECURE_CONTROL */ - -#define SECURE0 0x1 /* SECURE 0 */ -#define nSECURE0 0x0 -#define SECURE1 0x2 /* SECURE 1 */ -#define nSECURE1 0x0 -#define SECURE2 0x4 /* SECURE 2 */ -#define nSECURE2 0x0 -#define SECURE3 0x8 /* SECURE 3 */ -#define nSECURE3 0x0 - -/* Bit masks for SECURE_STATUS */ - -#define SECMODE 0x3 /* Secured Mode Control State */ -#define NMI 0x4 /* Non Maskable Interrupt */ -#define nNMI 0x0 -#define AFVALID 0x8 /* Authentication Firmware Valid */ -#define nAFVALID 0x0 -#define AFEXIT 0x10 /* Authentication Firmware Exit */ -#define nAFEXIT 0x0 -#define SECSTAT 0xe0 /* Secure Status */ - -#endif /* _DEF_BF52X_H */ diff --git a/arch/blackfin/mach-bf527/include/mach/gpio.h b/arch/blackfin/mach-bf527/include/mach/gpio.h index f80c2995efd..fba606b699c 100644 --- a/arch/blackfin/mach-bf527/include/mach/gpio.h +++ b/arch/blackfin/mach-bf527/include/mach/gpio.h @@ -62,4 +62,8 @@ #define PORT_G GPIO_PG0 #define PORT_H GPIO_PH0 +#include <mach-common/ports-f.h> +#include <mach-common/ports-g.h> +#include <mach-common/ports-h.h> + #endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf527/include/mach/pll.h b/arch/blackfin/mach-bf527/include/mach/pll.h index 24f1d7c0232..94cca674d83 100644 --- a/arch/blackfin/mach-bf527/include/mach/pll.h +++ b/arch/blackfin/mach-bf527/include/mach/pll.h @@ -1,63 +1 @@ -/* - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _MACH_PLL_H -#define _MACH_PLL_H - -#include <asm/blackfin.h> -#include <asm/irqflags.h> - -/* Writing to PLL_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_PLL_CTL(unsigned int val) -{ - unsigned long flags, iwr0, iwr1; - - if (val == bfin_read_PLL_CTL()) - return; - - flags = hard_local_irq_save(); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SIC_IWR0); - iwr1 = bfin_read32(SIC_IWR1); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR0, IWR_ENABLE(0)); - bfin_write32(SIC_IWR1, 0); - - bfin_write16(PLL_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR0, iwr0); - bfin_write32(SIC_IWR1, iwr1); - hard_local_irq_restore(flags); -} - -/* Writing to VR_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_VR_CTL(unsigned int val) -{ - unsigned long flags, iwr0, iwr1; - - if (val == bfin_read_VR_CTL()) - return; - - flags = hard_local_irq_save(); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SIC_IWR0); - iwr1 = bfin_read32(SIC_IWR1); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR0, IWR_ENABLE(0)); - bfin_write32(SIC_IWR1, 0); - - bfin_write16(VR_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR0, iwr0); - bfin_write32(SIC_IWR1, iwr1); - hard_local_irq_restore(flags); -} - -#endif /* _MACH_PLL_H */ +#include <mach-common/pll.h> diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c index 2ce7b16faee..d4bfcea5682 100644 --- a/arch/blackfin/mach-bf533/boards/H8606.c +++ b/arch/blackfin/mach-bf533/boards/H8606.c @@ -286,7 +286,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c index 20c102285be..87b5af3693c 100644 --- a/arch/blackfin/mach-bf533/boards/blackstamp.c +++ b/arch/blackfin/mach-bf533/boards/blackstamp.c @@ -25,7 +25,6 @@ #include <asm/bfin5xx_spi.h> #include <asm/portmux.h> #include <asm/dpmc.h> -#include <mach/fio_flag.h> /* * Name the Board for the /proc/cpuinfo @@ -225,7 +224,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -290,9 +289,9 @@ static struct resource bfin_sport0_uart_resources[] = { }, }; -unsigned short bfin_sport0_peripherals[] = { +static unsigned short bfin_sport0_peripherals[] = { P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 }; static struct platform_device bfin_sport0_uart_device = { @@ -324,9 +323,9 @@ static struct resource bfin_sport1_uart_resources[] = { }, }; -unsigned short bfin_sport1_peripherals[] = { +static unsigned short bfin_sport1_peripherals[] = { P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { @@ -476,10 +475,16 @@ static int __init blackstamp_init(void) return ret; #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) - /* setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC */ - bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF0); - bfin_write_FIO_FLAG_S(PF0); - SSYNC(); + /* + * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC. + * the bfin-async-map driver takes care of flipping between + * flash and ethernet when necessary. + */ + ret = gpio_request(GPIO_PF0, "enet_cpld"); + if (!ret) { + gpio_direction_output(GPIO_PF0, 1); + gpio_free(GPIO_PF0); + } #endif spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c index adbe62a81e2..4d5604eaa7c 100644 --- a/arch/blackfin/mach-bf533/boards/cm_bf533.c +++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c @@ -271,7 +271,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -336,9 +336,9 @@ static struct resource bfin_sport0_uart_resources[] = { }, }; -unsigned short bfin_sport0_peripherals[] = { +static unsigned short bfin_sport0_peripherals[] = { P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 }; static struct platform_device bfin_sport0_uart_device = { @@ -370,9 +370,9 @@ static struct resource bfin_sport1_uart_resources[] = { }, }; -unsigned short bfin_sport1_peripherals[] = { +static unsigned short bfin_sport1_peripherals[] = { P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c index a1cb8e7c101..b67b91d8224 100644 --- a/arch/blackfin/mach-bf533/boards/ezkit.c +++ b/arch/blackfin/mach-bf533/boards/ezkit.c @@ -349,7 +349,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c index 5ba4b02a12e..f869a371148 100644 --- a/arch/blackfin/mach-bf533/boards/ip0x.c +++ b/arch/blackfin/mach-bf533/boards/ip0x.c @@ -22,7 +22,6 @@ #include <asm/dma.h> #include <asm/bfin5xx_spi.h> #include <asm/portmux.h> -#include <mach/fio_flag.h> /* * Name the Board for the /proc/cpuinfo @@ -174,7 +173,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -295,15 +294,7 @@ static int __init ip0x_init(void) printk(KERN_INFO "%s(): registering device resources\n", __func__); platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices)); -#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) - for (i = 0; i < ARRAY_SIZE(bfin_spi_board_info); ++i) { - int j = 1 << bfin_spi_board_info[i].chip_select; - /* set spi cs to 1 */ - bfin_write_FIO_DIR(bfin_read_FIO_DIR() | j); - bfin_write_FIO_FLAG_S(j); - } spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); -#endif return 0; } diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c index b3b1cdea270..43224ef00b8 100644 --- a/arch/blackfin/mach-bf533/boards/stamp.c +++ b/arch/blackfin/mach-bf533/boards/stamp.c @@ -24,7 +24,6 @@ #include <asm/reboot.h> #include <asm/portmux.h> #include <asm/dpmc.h> -#include <mach/fio_flag.h> /* * Name the Board for the /proc/cpuinfo @@ -354,7 +353,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -419,9 +418,9 @@ static struct resource bfin_sport0_uart_resources[] = { }, }; -unsigned short bfin_sport0_peripherals[] = { +static unsigned short bfin_sport0_peripherals[] = { P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 }; static struct platform_device bfin_sport0_uart_device = { @@ -453,9 +452,9 @@ static struct resource bfin_sport1_uart_resources[] = { }, }; -unsigned short bfin_sport1_peripherals[] = { +static unsigned short bfin_sport1_peripherals[] = { P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { @@ -674,10 +673,16 @@ static int __init stamp_init(void) return ret; #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) - /* setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC */ - bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF0); - bfin_write_FIO_FLAG_S(PF0); - SSYNC(); + /* + * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC. + * the bfin-async-map driver takes care of flipping between + * flash and ethernet when necessary. + */ + ret = gpio_request(GPIO_PF0, "enet_cpld"); + if (!ret) { + gpio_direction_output(GPIO_PF0, 1); + gpio_free(GPIO_PF0); + } #endif spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); @@ -713,7 +718,6 @@ void __init native_machine_early_platform_add_devices(void) void native_machine_restart(char *cmd) { /* workaround pull up on cpld / flash pin not being strong enough */ - bfin_write_FIO_INEN(~PF0); - bfin_write_FIO_DIR(PF0); - bfin_write_FIO_FLAG_C(PF0); + gpio_request(GPIO_PF0, "flash_cpld"); + gpio_direction_output(GPIO_PF0, 0); } diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c index 4a14a46a9a6..1f5988d4313 100644 --- a/arch/blackfin/mach-bf533/dma.c +++ b/arch/blackfin/mach-bf533/dma.c @@ -11,7 +11,7 @@ #include <asm/blackfin.h> #include <asm/dma.h> -struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { +struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { (struct dma_register *) DMA0_NEXT_DESC_PTR, (struct dma_register *) DMA1_NEXT_DESC_PTR, (struct dma_register *) DMA2_NEXT_DESC_PTR, diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial.h new file mode 100644 index 00000000000..08072c86d5d --- /dev/null +++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial.h @@ -0,0 +1,14 @@ +/* + * mach/bfin_serial.h - Blackfin UART/Serial definitions + * + * Copyright 2006-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_MACH_SERIAL_H__ +#define __BFIN_MACH_SERIAL_H__ + +#define BFIN_UART_NR_PORTS 1 + +#endif diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h index 9e1f3defb6b..45dcaa4f3e4 100644 --- a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h @@ -4,36 +4,9 @@ * Licensed under the GPL-2 or later */ -#include <linux/serial.h> #include <asm/dma.h> #include <asm/portmux.h> -#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) -#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) -#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) -#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) -#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) -#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) -#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) - -#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) -#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) -#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) -#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) -#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) -#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) -#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) -#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) - -#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) -#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) - -#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) -#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) -#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) -#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) -#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) - #ifdef CONFIG_BFIN_UART0_CTSRTS # define CONFIG_SERIAL_BFIN_CTSRTS # ifndef CONFIG_UART0_CTS_PIN @@ -44,51 +17,6 @@ # endif #endif -#define BFIN_UART_TX_FIFO_SIZE 2 - -struct bfin_serial_port { - struct uart_port port; - unsigned int old_status; - int status_irq; - unsigned int lsr; -#ifdef CONFIG_SERIAL_BFIN_DMA - int tx_done; - int tx_count; - struct circ_buf rx_dma_buf; - struct timer_list rx_dma_timer; - int rx_dma_nrows; - unsigned int tx_dma_channel; - unsigned int rx_dma_channel; - struct work_struct tx_dma_workqueue; -#else -# if ANOMALY_05000363 - unsigned int anomaly_threshold; -# endif -#endif -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - struct timer_list cts_timer; - int cts_pin; - int rts_pin; -#endif -}; - -/* The hardware clears the LSR bits upon read, so we need to cache - * some of the more fun bits in software so they don't get lost - * when checking the LSR in other code paths (TX). - */ -static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart) -{ - unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR); - uart->lsr |= (lsr & (BI|FE|PE|OE)); - return lsr | uart->lsr; -} - -static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) -{ - uart->lsr = 0; - bfin_write16(uart->port.membase + OFFSET_LSR, -1); -} - struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; @@ -120,3 +48,5 @@ struct bfin_serial_res bfin_serial_resource[] = { }; #define DRIVER_NAME "bfin-uart" + +#include <asm/bfin_serial.h> diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h index f4bd6df5d96..e366207fbf1 100644 --- a/arch/blackfin/mach-bf533/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf533/include/mach/blackfin.h @@ -1,7 +1,7 @@ /* - * Copyright 2005-2009 Analog Devices Inc. + * Copyright 2005-2010 Analog Devices Inc. * - * Licensed under the GPL-2 or later + * Licensed under the GPL-2 or later. */ #ifndef _MACH_BLACKFIN_H_ @@ -10,26 +10,14 @@ #define BF533_FAMILY #include "bf533.h" -#include "defBF532.h" #include "anomaly.h" -#if !defined(__ASSEMBLY__) -#include "cdefBF532.h" -#endif - -#define BFIN_UART_NR_PORTS 1 +#include <asm/def_LPBlackfin.h> +#include "defBF532.h" -#define OFFSET_THR 0x00 /* Transmit Holding register */ -#define OFFSET_RBR 0x00 /* Receive Buffer register */ -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_IER 0x04 /* Interrupt Enable Register */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_GCTL 0x24 /* Global Control Register */ +#ifndef __ASSEMBLY__ +# include <asm/cdef_LPBlackfin.h> +# include "cdefBF532.h" +#endif -#endif /* _MACH_BLACKFIN_H_ */ +#endif diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h index 401e524f532..fd0cbe4df21 100644 --- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h +++ b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h @@ -1,5 +1,5 @@ /* - * Copyright 2005-2008 Analog Devices Inc. + * Copyright 2005-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later */ @@ -7,9 +7,6 @@ #ifndef _CDEF_BF532_H #define _CDEF_BF532_H -/*include core specific register pointer definitions*/ -#include <asm/cdef_LPBlackfin.h> - /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) @@ -66,16 +63,10 @@ #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val) /* DMA Traffic controls */ -#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) -#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val) -#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) -#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val) - -/* Alternate deprecated register names (below) provided for backwards code compatibility */ -#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) -#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val) -#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) -#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val) +#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER) +#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val) +#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT) +#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val) /* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ #define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) @@ -105,6 +96,47 @@ #define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) #define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val) +#if ANOMALY_05000311 +/* Keep at the CPP expansion to avoid circular header dependency loops */ +#define BFIN_WRITE_FIO_FLAG(name, val) \ + do { \ + unsigned long __flags; \ + __flags = hard_local_irq_save(); \ + bfin_write16(FIO_FLAG_##name, val); \ + bfin_read_CHIPID(); \ + hard_local_irq_restore(__flags); \ + } while (0) +#define bfin_write_FIO_FLAG_D(val) BFIN_WRITE_FIO_FLAG(D, val) +#define bfin_write_FIO_FLAG_C(val) BFIN_WRITE_FIO_FLAG(C, val) +#define bfin_write_FIO_FLAG_S(val) BFIN_WRITE_FIO_FLAG(S, val) +#define bfin_write_FIO_FLAG_T(val) BFIN_WRITE_FIO_FLAG(T, val) + +#define BFIN_READ_FIO_FLAG(name) \ + ({ \ + unsigned long __flags; \ + u16 __ret; \ + __flags = hard_local_irq_save(); \ + __ret = bfin_read16(FIO_FLAG_##name); \ + bfin_read_CHIPID(); \ + hard_local_irq_restore(__flags); \ + __ret; \ + }) +#define bfin_read_FIO_FLAG_D() BFIN_READ_FIO_FLAG(D) +#define bfin_read_FIO_FLAG_C() BFIN_READ_FIO_FLAG(C) +#define bfin_read_FIO_FLAG_S() BFIN_READ_FIO_FLAG(S) +#define bfin_read_FIO_FLAG_T() BFIN_READ_FIO_FLAG(T) + +#else +#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val) +#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val) +#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val) +#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val) +#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) +#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) +#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) +#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) +#endif + /* DMA Controller */ #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) @@ -647,7 +679,4 @@ #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) -/* These need to be last due to the cdef/linux inter-dependencies */ -#include <asm/irq.h> - #endif /* _CDEF_BF532_H */ diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h index 3adb0b44e59..2376d539351 100644 --- a/arch/blackfin/mach-bf533/include/mach/defBF532.h +++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h @@ -1,7 +1,7 @@ /* * System & MMR bit and Address definitions for ADSP-BF532 * - * Copyright 2005-2008 Analog Devices Inc. + * Copyright 2005-2010 Analog Devices Inc. * * Licensed under the ADI BSD license or the GPL-2 (or later) */ @@ -9,9 +9,6 @@ #ifndef _DEF_BF532_H #define _DEF_BF532_H -/* include all Core registers and bit definitions */ -#include <asm/def_LPBlackfin.h> - /*********************************************************************************** */ /* System MMR Register Map */ /*********************************************************************************** */ @@ -182,12 +179,8 @@ #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ /* DMA Traffic controls */ -#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ - -/* Alternate deprecated register names (below) provided for backwards code compatibility */ -#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ +#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ +#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ @@ -432,83 +425,6 @@ #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ -/* ***************************** UART CONTROLLER MASKS ********************** */ - -/* UART_LCR Register */ - -#define DLAB 0x80 -#define SB 0x40 -#define STP 0x20 -#define EPS 0x10 -#define PEN 0x08 -#define STB 0x04 -#define WLS(x) ((x-5) & 0x03) - -#define DLAB_P 0x07 -#define SB_P 0x06 -#define STP_P 0x05 -#define EPS_P 0x04 -#define PEN_P 0x03 -#define STB_P 0x02 -#define WLS_P1 0x01 -#define WLS_P0 0x00 - -/* UART_MCR Register */ -#define LOOP_ENA 0x10 -#define LOOP_ENA_P 0x04 - -/* UART_LSR Register */ -#define TEMT 0x40 -#define THRE 0x20 -#define BI 0x10 -#define FE 0x08 -#define PE 0x04 -#define OE 0x02 -#define DR 0x01 - -#define TEMP_P 0x06 -#define THRE_P 0x05 -#define BI_P 0x04 -#define FE_P 0x03 -#define PE_P 0x02 -#define OE_P 0x01 -#define DR_P 0x00 - -/* UART_IER Register */ -#define ELSI 0x04 -#define ETBEI 0x02 -#define ERBFI 0x01 - -#define ELSI_P 0x02 -#define ETBEI_P 0x01 -#define ERBFI_P 0x00 - -/* UART_IIR Register */ -#define STATUS(x) ((x << 1) & 0x06) -#define NINT 0x01 -#define STATUS_P1 0x02 -#define STATUS_P0 0x01 -#define NINT_P 0x00 -#define IIR_TX_READY 0x02 /* UART_THR empty */ -#define IIR_RX_READY 0x04 /* Receive data ready */ -#define IIR_LINE_CHANGE 0x06 /* Receive line status */ -#define IIR_STATUS 0x06 - -/* UART_GCTL Register */ -#define FFE 0x20 -#define FPE 0x10 -#define RPOLC 0x08 -#define TPOLC 0x04 -#define IREN 0x02 -#define UCEN 0x01 - -#define FFE_P 0x05 -#define FPE_P 0x04 -#define RPOLC_P 0x03 -#define TPOLC_P 0x02 -#define IREN_P 0x01 -#define UCEN_P 0x00 - /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ /* PPI_CONTROL Masks */ @@ -643,44 +559,6 @@ #define ERR_TYP_P0 0x0E #define ERR_TYP_P1 0x0F -/*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */ - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */ -#define PF0_P 0 -#define PF1_P 1 -#define PF2_P 2 -#define PF3_P 3 -#define PF4_P 4 -#define PF5_P 5 -#define PF6_P 6 -#define PF7_P 7 -#define PF8_P 8 -#define PF9_P 9 -#define PF10_P 10 -#define PF11_P 11 -#define PF12_P 12 -#define PF13_P 13 -#define PF14_P 14 -#define PF15_P 15 - /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ /* AMGCTL Masks */ diff --git a/arch/blackfin/mach-bf533/include/mach/fio_flag.h b/arch/blackfin/mach-bf533/include/mach/fio_flag.h deleted file mode 100644 index d0bfba0b083..00000000000 --- a/arch/blackfin/mach-bf533/include/mach/fio_flag.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2005-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _MACH_FIO_FLAG_H -#define _MACH_FIO_FLAG_H - -#include <asm/blackfin.h> -#include <asm/irqflags.h> - -#if ANOMALY_05000311 -#define BFIN_WRITE_FIO_FLAG(name) \ -static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \ -{ \ - unsigned long flags; \ - flags = hard_local_irq_save(); \ - bfin_write16(FIO_FLAG_##name, val); \ - bfin_read_CHIPID(); \ - hard_local_irq_restore(flags); \ -} -BFIN_WRITE_FIO_FLAG(D) -BFIN_WRITE_FIO_FLAG(C) -BFIN_WRITE_FIO_FLAG(S) -BFIN_WRITE_FIO_FLAG(T) - -#define BFIN_READ_FIO_FLAG(name) \ -static inline u16 bfin_read_FIO_FLAG_##name(void) \ -{ \ - unsigned long flags; \ - u16 ret; \ - flags = hard_local_irq_save(); \ - ret = bfin_read16(FIO_FLAG_##name); \ - bfin_read_CHIPID(); \ - hard_local_irq_restore(flags); \ - return ret; \ -} -BFIN_READ_FIO_FLAG(D) -BFIN_READ_FIO_FLAG(C) -BFIN_READ_FIO_FLAG(S) -BFIN_READ_FIO_FLAG(T) - -#else -#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val) -#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val) -#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val) -#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val) -#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) -#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) -#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) -#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) -#endif - -#endif /* _MACH_FIO_FLAG_H */ diff --git a/arch/blackfin/mach-bf533/include/mach/gpio.h b/arch/blackfin/mach-bf533/include/mach/gpio.h index e02416db4b0..cce4f8fb378 100644 --- a/arch/blackfin/mach-bf533/include/mach/gpio.h +++ b/arch/blackfin/mach-bf533/include/mach/gpio.h @@ -28,4 +28,6 @@ #define PORT_F GPIO_PF0 +#include <mach-common/ports-f.h> + #endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf533/include/mach/pll.h b/arch/blackfin/mach-bf533/include/mach/pll.h index 169c106d0ed..94cca674d83 100644 --- a/arch/blackfin/mach-bf533/include/mach/pll.h +++ b/arch/blackfin/mach-bf533/include/mach/pll.h @@ -1,57 +1 @@ -/* - * Copyright 2005-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _MACH_PLL_H -#define _MACH_PLL_H - -#include <asm/blackfin.h> -#include <asm/irqflags.h> - -/* Writing to PLL_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_PLL_CTL(unsigned int val) -{ - unsigned long flags, iwr; - - if (val == bfin_read_PLL_CTL()) - return; - - flags = hard_local_irq_save(); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr = bfin_read32(SIC_IWR); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR, IWR_ENABLE(0)); - - bfin_write16(PLL_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR, iwr); - hard_local_irq_restore(flags); -} - -/* Writing to VR_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_VR_CTL(unsigned int val) -{ - unsigned long flags, iwr; - - if (val == bfin_read_VR_CTL()) - return; - - flags = hard_local_irq_save(); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr = bfin_read32(SIC_IWR); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR, IWR_ENABLE(0)); - - bfin_write16(VR_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR, iwr); - hard_local_irq_restore(flags); -} - -#endif /* _MACH_PLL_H */ +#include <mach-common/pll.h> diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig index 44132fda63b..a44bf3a1816 100644 --- a/arch/blackfin/mach-bf537/boards/Kconfig +++ b/arch/blackfin/mach-bf537/boards/Kconfig @@ -39,4 +39,10 @@ config CAMSIG_MINOTAUR help Board supply package for CSP Minotaur +config DNP5370 + bool "SSV Dil/NetPC DNP/5370" + depends on (BF537) + help + Board supply package for DNP/5370 DIL64 module + endchoice diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile index 7e6aa4e5b20..fe42258fe1f 100644 --- a/arch/blackfin/mach-bf537/boards/Makefile +++ b/arch/blackfin/mach-bf537/boards/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_U) += cm_bf537u.o obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o obj-$(CONFIG_PNAV10) += pnav10.o obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o +obj-$(CONFIG_DNP5370) += dnp5370.o diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c index 836698c4ee5..2c776e188a9 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c @@ -373,7 +373,7 @@ static struct resource bfin_uart0_resources[] = { #endif }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -434,7 +434,7 @@ static struct resource bfin_uart1_resources[] = { #endif }; -unsigned short bfin_uart1_peripherals[] = { +static unsigned short bfin_uart1_peripherals[] = { P_UART1_TX, P_UART1_RX, 0 }; @@ -545,9 +545,9 @@ static struct resource bfin_sport0_uart_resources[] = { }, }; -unsigned short bfin_sport0_peripherals[] = { +static unsigned short bfin_sport0_peripherals[] = { P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 }; static struct platform_device bfin_sport0_uart_device = { @@ -579,9 +579,9 @@ static struct resource bfin_sport1_uart_resources[] = { }, }; -unsigned short bfin_sport1_peripherals[] = { +static unsigned short bfin_sport1_peripherals[] = { P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c index 2a85670273c..085661175ec 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c @@ -356,7 +356,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -399,7 +399,7 @@ static struct resource bfin_uart1_resources[] = { }, }; -unsigned short bfin_uart1_peripherals[] = { +static unsigned short bfin_uart1_peripherals[] = { P_UART1_TX, P_UART1_RX, 0 }; @@ -510,9 +510,9 @@ static struct resource bfin_sport0_uart_resources[] = { }, }; -unsigned short bfin_sport0_peripherals[] = { +static unsigned short bfin_sport0_peripherals[] = { P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 }; static struct platform_device bfin_sport0_uart_device = { @@ -544,9 +544,9 @@ static struct resource bfin_sport1_uart_resources[] = { }, }; -unsigned short bfin_sport1_peripherals[] = { +static unsigned short bfin_sport1_peripherals[] = { P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c new file mode 100644 index 00000000000..e1e9ea02ad8 --- /dev/null +++ b/arch/blackfin/mach-bf537/boards/dnp5370.c @@ -0,0 +1,418 @@ +/* + * This is the configuration for SSV Dil/NetPC DNP/5370 board. + * + * DIL module: http://www.dilnetpc.com/dnp0086.htm + * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm + * + * Copyright 2010 3ality Digital Systems + * Copyright 2005 National ICT Australia (NICTA) + * Copyright 2004-2006 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/plat-ram.h> +#include <linux/mtd/physmap.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/i2c.h> +#include <linux/spi/mmc_spi.h> +#include <linux/phy.h> +#include <asm/dma.h> +#include <asm/bfin5xx_spi.h> +#include <asm/reboot.h> +#include <asm/portmux.h> +#include <asm/dpmc.h> + +/* + * Name the Board for the /proc/cpuinfo + */ +const char bfin_board_name[] = "DNP/5370"; +#define FLASH_MAC 0x202f0000 +#define CONFIG_MTD_PHYSMAP_LEN 0x300000 + +#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) +static struct platform_device rtc_device = { + .name = "rtc-bfin", + .id = -1, +}; +#endif + +#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) +#include <linux/bfin_mac.h> +static const unsigned short bfin_mac_peripherals[] = P_RMII0; + +static struct bfin_phydev_platform_data bfin_phydev_data[] = { + { + .addr = 1, + .irq = PHY_POLL, /* IRQ_MAC_PHYINT */ + }, +}; + +static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { + .phydev_number = 1, + .phydev_data = bfin_phydev_data, + .phy_mode = PHY_INTERFACE_MODE_RMII, + .mac_peripherals = bfin_mac_peripherals, +}; + +static struct platform_device bfin_mii_bus = { + .name = "bfin_mii_bus", + .dev = { + .platform_data = &bfin_mii_bus_data, + } +}; + +static struct platform_device bfin_mac_device = { + .name = "bfin_mac", + .dev = { + .platform_data = &bfin_mii_bus, + } +}; +#endif + +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) +static struct mtd_partition asmb_flash_partitions[] = { + { + .name = "bootloader(nor)", + .size = 0x30000, + .offset = 0, + }, { + .name = "linux kernel and rootfs(nor)", + .size = 0x300000 - 0x30000 - 0x10000, + .offset = MTDPART_OFS_APPEND, + }, { + .name = "MAC address(nor)", + .size = 0x10000, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, + } +}; + +static struct physmap_flash_data asmb_flash_data = { + .width = 1, + .parts = asmb_flash_partitions, + .nr_parts = ARRAY_SIZE(asmb_flash_partitions), +}; + +static struct resource asmb_flash_resource = { + .start = 0x20000000, + .end = 0x202fffff, + .flags = IORESOURCE_MEM, +}; + +/* 4 MB NOR flash attached to async memory banks 0-2, + * therefore only 3 MB visible. + */ +static struct platform_device asmb_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &asmb_flash_data, + }, + .num_resources = 1, + .resource = &asmb_flash_resource, +}; +#endif + +#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) + +#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) + +#define MMC_SPI_CARD_DETECT_INT IRQ_PF5 + +static int bfin_mmc_spi_init(struct device *dev, + irqreturn_t (*detect_int)(int, void *), void *data) +{ + return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int, + IRQF_TRIGGER_FALLING, "mmc-spi-detect", data); +} + +static void bfin_mmc_spi_exit(struct device *dev, void *data) +{ + free_irq(MMC_SPI_CARD_DETECT_INT, data); +} + +static struct bfin5xx_spi_chip mmc_spi_chip_info = { + .enable_dma = 0, /* use no dma transfer with this chip*/ + .bits_per_word = 8, +}; + +static struct mmc_spi_platform_data bfin_mmc_spi_pdata = { + .init = bfin_mmc_spi_init, + .exit = bfin_mmc_spi_exit, + .detect_delay = 100, /* msecs */ +}; +#endif + +#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE) +/* This mapping is for at45db642 it has 1056 page size, + * partition size and offset should be page aligned + */ +static struct mtd_partition bfin_spi_dataflash_partitions[] = { + { + .name = "JFFS2 dataflash(nor)", +#ifdef CONFIG_MTD_PAGESIZE_1024 + .offset = 0x40000, + .size = 0x7C0000, +#else + .offset = 0x0, + .size = 0x840000, +#endif + } +}; + +static struct flash_platform_data bfin_spi_dataflash_data = { + .name = "mtd_dataflash", + .parts = bfin_spi_dataflash_partitions, + .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions), + .type = "mtd_dataflash", +}; + +static struct bfin5xx_spi_chip spi_dataflash_chip_info = { + .enable_dma = 0, /* use no dma transfer with this chip*/ + .bits_per_word = 8, +}; +#endif + +static struct spi_board_info bfin_spi_board_info[] __initdata = { +/* SD/MMC card reader at SPI bus */ +#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) + { + .modalias = "mmc_spi", + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = 1, + .platform_data = &bfin_mmc_spi_pdata, + .controller_data = &mmc_spi_chip_info, + .mode = SPI_MODE_3, + }, +#endif + +/* 8 Megabyte Atmel NOR flash chip at SPI bus */ +#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE) + { + .modalias = "mtd_dataflash", + .max_speed_hz = 16700000, + .bus_num = 0, + .chip_select = 2, + .platform_data = &bfin_spi_dataflash_data, + .controller_data = &spi_dataflash_chip_info, + .mode = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */ + }, +#endif +}; + +/* SPI controller data */ +/* SPI (0) */ +static struct resource bfin_spi0_resource[] = { + [0] = { + .start = SPI0_REGBASE, + .end = SPI0_REGBASE + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = CH_SPI, + .end = CH_SPI, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = IRQ_SPI, + .end = IRQ_SPI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct bfin5xx_spi_master spi_bfin_master_info = { + .num_chipselect = 8, + .enable_dma = 1, /* master has the ability to do dma transfer */ + .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, +}; + +static struct platform_device spi_bfin_master_device = { + .name = "bfin-spi", + .id = 0, /* Bus number */ + .num_resources = ARRAY_SIZE(bfin_spi0_resource), + .resource = bfin_spi0_resource, + .dev = { + .platform_data = &spi_bfin_master_info, /* Passed to driver */ + }, +}; +#endif + +#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) +#ifdef CONFIG_SERIAL_BFIN_UART0 +static struct resource bfin_uart0_resources[] = { + { + .start = UART0_THR, + .end = UART0_GCTL+2, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART0_RX, + .end = IRQ_UART0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART0_ERROR, + .end = IRQ_UART0_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_TX, + .end = CH_UART0_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART0_RX, + .end = CH_UART0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static unsigned short bfin_uart0_peripherals[] = { + P_UART0_TX, P_UART0_RX, 0 +}; + +static struct platform_device bfin_uart0_device = { + .name = "bfin-uart", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_uart0_resources), + .resource = bfin_uart0_resources, + .dev = { + .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ + }, +}; +#endif + +#ifdef CONFIG_SERIAL_BFIN_UART1 +static struct resource bfin_uart1_resources[] = { + { + .start = UART1_THR, + .end = UART1_GCTL+2, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART1_RX, + .end = IRQ_UART1_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART1_ERROR, + .end = IRQ_UART1_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_TX, + .end = CH_UART1_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART1_RX, + .end = CH_UART1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static unsigned short bfin_uart1_peripherals[] = { + P_UART1_TX, P_UART1_RX, 0 +}; + +static struct platform_device bfin_uart1_device = { + .name = "bfin-uart", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_uart1_resources), + .resource = bfin_uart1_resources, + .dev = { + .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ + }, +}; +#endif +#endif + +#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static struct resource bfin_twi0_resource[] = { + [0] = { + .start = TWI0_REGBASE, + .end = TWI0_REGBASE + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TWI, + .end = IRQ_TWI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device i2c_bfin_twi_device = { + .name = "i2c-bfin-twi", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_twi0_resource), + .resource = bfin_twi0_resource, +}; +#endif + +static struct platform_device *dnp5370_devices[] __initdata = { + +#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif +#endif + +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) + &asmb_flash_device, +#endif + +#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) + &bfin_mii_bus, + &bfin_mac_device, +#endif + +#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) + &spi_bfin_master_device, +#endif + +#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) + &i2c_bfin_twi_device, +#endif + +#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) + &rtc_device, +#endif + +}; + +static int __init dnp5370_init(void) +{ + printk(KERN_INFO "DNP/5370: registering device resources\n"); + platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices)); + printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n", + ARRAY_SIZE(bfin_spi_board_info)); + spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); + printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC); + return 0; +} +arch_initcall(dnp5370_init); + +/* + * Currently the MAC address is saved in Flash by U-Boot + */ +void bfin_get_ether_addr(char *addr) +{ + *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC); + *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4); +} +EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c index 49800518412..bfb3671a78d 100644 --- a/arch/blackfin/mach-bf537/boards/minotaur.c +++ b/arch/blackfin/mach-bf537/boards/minotaur.c @@ -263,7 +263,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -306,7 +306,7 @@ static struct resource bfin_uart1_resources[] = { }, }; -unsigned short bfin_uart1_peripherals[] = { +static unsigned short bfin_uart1_peripherals[] = { P_UART1_TX, P_UART1_RX, 0 }; @@ -419,9 +419,9 @@ static struct resource bfin_sport0_uart_resources[] = { }, }; -unsigned short bfin_sport0_peripherals[] = { +static unsigned short bfin_sport0_peripherals[] = { P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 }; static struct platform_device bfin_sport0_uart_device = { @@ -453,9 +453,9 @@ static struct resource bfin_sport1_uart_resources[] = { }, }; -unsigned short bfin_sport1_peripherals[] = { +static unsigned short bfin_sport1_peripherals[] = { P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c index b95807894e2..9389f03e3b0 100644 --- a/arch/blackfin/mach-bf537/boards/pnav10.c +++ b/arch/blackfin/mach-bf537/boards/pnav10.c @@ -367,7 +367,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -410,7 +410,7 @@ static struct resource bfin_uart1_resources[] = { }, }; -unsigned short bfin_uart1_peripherals[] = { +static unsigned short bfin_uart1_peripherals[] = { P_UART1_TX, P_UART1_RX, 0 }; diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index 3aa344ce8e5..2c69785a7bb 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -289,7 +289,7 @@ static struct platform_device isp1362_hcd_device = { #endif #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) -unsigned short bfin_can_peripherals[] = { +static unsigned short bfin_can_peripherals[] = { P_CAN0_RX, P_CAN0_TX, 0 }; @@ -693,7 +693,7 @@ static struct bfin5xx_spi_chip ad2s90_spi_chip_info = { #endif #if defined(CONFIG_AD2S120X) || defined(CONFIG_AD2S120X_MODULE) -unsigned short ad2s120x_platform_data[] = { +static unsigned short ad2s120x_platform_data[] = { /* used as SAMPLE and RDVEL */ GPIO_PF5, GPIO_PF6, 0 }; @@ -705,7 +705,7 @@ static struct bfin5xx_spi_chip ad2s120x_spi_chip_info = { #endif #if defined(CONFIG_AD2S1210) || defined(CONFIG_AD2S1210_MODULE) -unsigned short ad2s1210_platform_data[] = { +static unsigned short ad2s1210_platform_data[] = { /* use as SAMPLE, A0, A1 */ GPIO_PF7, GPIO_PF8, GPIO_PF9, # if defined(CONFIG_AD2S1210_GPIO_INPUT) || defined(CONFIG_AD2S1210_GPIO_OUTPUT) @@ -1717,7 +1717,7 @@ static struct resource bfin_uart0_resources[] = { #endif }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -1760,7 +1760,7 @@ static struct resource bfin_uart1_resources[] = { }, }; -unsigned short bfin_uart1_peripherals[] = { +static unsigned short bfin_uart1_peripherals[] = { P_UART1_TX, P_UART1_RX, 0 }; @@ -2447,9 +2447,9 @@ static struct resource bfin_sport0_uart_resources[] = { }, }; -unsigned short bfin_sport0_peripherals[] = { +static unsigned short bfin_sport0_peripherals[] = { P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 }; static struct platform_device bfin_sport0_uart_device = { @@ -2481,9 +2481,9 @@ static struct resource bfin_sport1_uart_resources[] = { }, }; -unsigned short bfin_sport1_peripherals[] = { +static unsigned short bfin_sport1_peripherals[] = { P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c index 31498add1a4..0761b201abc 100644 --- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c @@ -356,7 +356,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -399,7 +399,7 @@ static struct resource bfin_uart1_resources[] = { }, }; -unsigned short bfin_uart1_peripherals[] = { +static unsigned short bfin_uart1_peripherals[] = { P_UART1_TX, P_UART1_RX, 0 }; @@ -512,9 +512,9 @@ static struct resource bfin_sport0_uart_resources[] = { }, }; -unsigned short bfin_sport0_peripherals[] = { +static unsigned short bfin_sport0_peripherals[] = { P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 }; static struct platform_device bfin_sport0_uart_device = { @@ -546,9 +546,9 @@ static struct resource bfin_sport1_uart_resources[] = { }, }; -unsigned short bfin_sport1_peripherals[] = { +static unsigned short bfin_sport1_peripherals[] = { P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c index 5c8c4ed517b..5c62e99c9fa 100644 --- a/arch/blackfin/mach-bf537/dma.c +++ b/arch/blackfin/mach-bf537/dma.c @@ -11,7 +11,7 @@ #include <asm/blackfin.h> #include <asm/dma.h> -struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { +struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { (struct dma_register *) DMA0_NEXT_DESC_PTR, (struct dma_register *) DMA1_NEXT_DESC_PTR, (struct dma_register *) DMA2_NEXT_DESC_PTR, diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h new file mode 100644 index 00000000000..00c603fe821 --- /dev/null +++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h @@ -0,0 +1,14 @@ +/* + * mach/bfin_serial.h - Blackfin UART/Serial definitions + * + * Copyright 2006-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_MACH_SERIAL_H__ +#define __BFIN_MACH_SERIAL_H__ + +#define BFIN_UART_NR_PORTS 2 + +#endif diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h index 635c91c526a..3e955dba895 100644 --- a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h @@ -4,36 +4,9 @@ * Licensed under the GPL-2 or later */ -#include <linux/serial.h> #include <asm/dma.h> #include <asm/portmux.h> -#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) -#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) -#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) -#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) -#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) -#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) -#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) - -#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) -#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) -#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) -#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) -#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) -#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) -#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) -#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) - -#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) -#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) - -#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) -#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) -#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) -#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) -#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) - #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) # define CONFIG_SERIAL_BFIN_CTSRTS @@ -54,49 +27,6 @@ # endif #endif -#define BFIN_UART_TX_FIFO_SIZE 2 - -/* - * The pin configuration is different from schematic - */ -struct bfin_serial_port { - struct uart_port port; - unsigned int old_status; - int status_irq; - unsigned int lsr; -#ifdef CONFIG_SERIAL_BFIN_DMA - int tx_done; - int tx_count; - struct circ_buf rx_dma_buf; - struct timer_list rx_dma_timer; - int rx_dma_nrows; - unsigned int tx_dma_channel; - unsigned int rx_dma_channel; - struct work_struct tx_dma_workqueue; -#endif -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - int cts_pin; - int rts_pin; -#endif -}; - -/* The hardware clears the LSR bits upon read, so we need to cache - * some of the more fun bits in software so they don't get lost - * when checking the LSR in other code paths (TX). - */ -static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart) -{ - unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR); - uart->lsr |= (lsr & (BI|FE|PE|OE)); - return lsr | uart->lsr; -} - -static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) -{ - uart->lsr = 0; - bfin_write16(uart->port.membase + OFFSET_LSR, -1); -} - struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; @@ -145,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = { }; #define DRIVER_NAME "bfin-uart" + +#include <asm/bfin_serial.h> diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h index a12d4b6a221..baa096fc724 100644 --- a/arch/blackfin/mach-bf537/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h @@ -1,7 +1,7 @@ /* - * Copyright 2005-2009 Analog Devices Inc. + * Copyright 2005-2010 Analog Devices Inc. * - * Licensed under the GPL-2 or later + * Licensed under the GPL-2 or later. */ #ifndef _MACH_BLACKFIN_H_ @@ -10,34 +10,24 @@ #define BF537_FAMILY #include "bf537.h" -#include "defBF534.h" #include "anomaly.h" +#include <asm/def_LPBlackfin.h> +#ifdef CONFIG_BF534 +# include "defBF534.h" +#endif #if defined(CONFIG_BF537) || defined(CONFIG_BF536) -#include "defBF537.h" +# include "defBF537.h" #endif #if !defined(__ASSEMBLY__) -#include "cdefBF534.h" - -#if defined(CONFIG_BF537) || defined(CONFIG_BF536) -#include "cdefBF537.h" +# include <asm/cdef_LPBlackfin.h> +# ifdef CONFIG_BF534 +# include "cdefBF534.h" +# endif +# if defined(CONFIG_BF537) || defined(CONFIG_BF536) +# include "cdefBF537.h" +# endif #endif -#endif - -#define BFIN_UART_NR_PORTS 2 - -#define OFFSET_THR 0x00 /* Transmit Holding register */ -#define OFFSET_RBR 0x00 /* Receive Buffer register */ -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_IER 0x04 /* Interrupt Enable Register */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_GCTL 0x24 /* Global Control Register */ #endif diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h index fbeb35e1413..563ede90733 100644 --- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h @@ -1,5 +1,5 @@ /* - * Copyright 2005-2008 Analog Devices Inc. + * Copyright 2005-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later */ @@ -7,14 +7,6 @@ #ifndef _CDEF_BF534_H #define _CDEF_BF534_H -#include <asm/blackfin.h> - -/* Include all Core registers and bit definitions */ -#include "defBF534.h" - -/* Include core specific register pointer definitions */ -#include <asm/cdef_LPBlackfin.h> - /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) @@ -355,16 +347,10 @@ #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) /* DMA Traffic Control Registers */ -#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) -#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val) -#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) -#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val) - -/* Alternate deprecated register names (below) provided for backwards code compatibility */ -#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) -#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val) -#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) -#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val) +#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER) +#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val) +#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT) +#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val) /* DMA Controller */ #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) @@ -1747,7 +1733,4 @@ #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val) -/* These need to be last due to the cdef/linux inter-dependencies */ -#include <asm/irq.h> - #endif /* _CDEF_BF534_H */ diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h index 9363c399042..19ec21ea150 100644 --- a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h +++ b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h @@ -1,5 +1,5 @@ /* - * Copyright 2005-2008 Analog Devices Inc. + * Copyright 2005-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later */ @@ -10,9 +10,6 @@ /* Include MMRs Common to BF534 */ #include "cdefBF534.h" -/* Include all Core registers and bit definitions */ -#include "defBF537.h" - /* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */ /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ #define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h index 0323e6bacda..32529a03b26 100644 --- a/arch/blackfin/mach-bf537/include/mach/defBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h @@ -1,5 +1,5 @@ /* - * Copyright 2005-2008 Analog Devices Inc. + * Copyright 2005-2010 Analog Devices Inc. * * Licensed under the ADI BSD license or the GPL-2 (or later) */ @@ -7,9 +7,6 @@ #ifndef _DEF_BF534_H #define _DEF_BF534_H -/* Include all Core registers and bit definitions */ -#include <asm/def_LPBlackfin.h> - /************************************************************************************ ** System MMR Register Map *************************************************************************************/ @@ -193,12 +190,8 @@ #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ /* DMA Traffic Control Registers */ -#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ - -/* Alternate deprecated register names (below) provided for backwards code compatibility */ -#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ +#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ +#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ @@ -1029,48 +1022,6 @@ #define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ -/* ************** UART CONTROLLER MASKS *************************/ -/* UARTx_LCR Masks */ -#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ -#define STB 0x04 /* Stop Bits */ -#define PEN 0x08 /* Parity Enable */ -#define EPS 0x10 /* Even Parity Select */ -#define STP 0x20 /* Stick Parity */ -#define SB 0x40 /* Set Break */ -#define DLAB 0x80 /* Divisor Latch Access */ - -/* UARTx_MCR Mask */ -#define LOOP_ENA 0x10 /* Loopback Mode Enable */ -#define LOOP_ENA_P 0x04 -/* UARTx_LSR Masks */ -#define DR 0x01 /* Data Ready */ -#define OE 0x02 /* Overrun Error */ -#define PE 0x04 /* Parity Error */ -#define FE 0x08 /* Framing Error */ -#define BI 0x10 /* Break Interrupt */ -#define THRE 0x20 /* THR Empty */ -#define TEMT 0x40 /* TSR and UART_THR Empty */ - -/* UARTx_IER Masks */ -#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ -#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ -#define ELSI 0x04 /* Enable RX Status Interrupt */ - -/* UARTx_IIR Masks */ -#define NINT 0x01 /* Pending Interrupt */ -#define IIR_TX_READY 0x02 /* UART_THR empty */ -#define IIR_RX_READY 0x04 /* Receive data ready */ -#define IIR_LINE_CHANGE 0x06 /* Receive line status */ -#define IIR_STATUS 0x06 - -/* UARTx_GCTL Masks */ -#define UCEN 0x01 /* Enable UARTx Clocks */ -#define IREN 0x02 /* Enable IrDA Mode */ -#define TPOLC 0x04 /* IrDA TX Polarity Change */ -#define RPOLC 0x08 /* IrDA RX Polarity Change */ -#define FPE 0x10 /* Force Parity Error On Transmit */ -#define FFE 0x20 /* Force Framing Error On Transmit */ - /* **************** GENERAL PURPOSE TIMER MASKS **********************/ /* TIMER_ENABLE Masks */ #define TIMEN0 0x0001 /* Enable Timer 0 */ @@ -1141,62 +1092,6 @@ #define EMU_RUN 0x0200 /* Emulation Behavior Select */ #define ERR_TYP 0xC000 /* Error Type */ -/* ****************** GPIO PORTS F, G, H MASKS ***********************/ -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ -/* Port F Masks */ -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - -/* Port G Masks */ -#define PG0 0x0001 -#define PG1 0x0002 -#define PG2 0x0004 -#define PG3 0x0008 -#define PG4 0x0010 -#define PG5 0x0020 -#define PG6 0x0040 -#define PG7 0x0080 -#define PG8 0x0100 -#define PG9 0x0200 -#define PG10 0x0400 -#define PG11 0x0800 -#define PG12 0x1000 -#define PG13 0x2000 -#define PG14 0x4000 -#define PG15 0x8000 - -/* Port H Masks */ -#define PH0 0x0001 -#define PH1 0x0002 -#define PH2 0x0004 -#define PH3 0x0008 -#define PH4 0x0010 -#define PH5 0x0020 -#define PH6 0x0040 -#define PH7 0x0080 -#define PH8 0x0100 -#define PH9 0x0200 -#define PH10 0x0400 -#define PH11 0x0800 -#define PH12 0x1000 -#define PH13 0x2000 -#define PH14 0x4000 -#define PH15 0x8000 - /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ /* EBIU_AMGCTL Masks */ #define AMCKEN 0x0001 /* Enable CLKOUT */ diff --git a/arch/blackfin/mach-bf537/include/mach/defBF537.h b/arch/blackfin/mach-bf537/include/mach/defBF537.h index 8cb5d5cf0c9..3d471d75268 100644 --- a/arch/blackfin/mach-bf537/include/mach/defBF537.h +++ b/arch/blackfin/mach-bf537/include/mach/defBF537.h @@ -1,5 +1,5 @@ /* - * Copyright 2005-2008 Analog Devices Inc. + * Copyright 2005-2010 Analog Devices Inc. * * Licensed under the ADI BSD license or the GPL-2 (or later) */ @@ -7,9 +7,6 @@ #ifndef _DEF_BF537_H #define _DEF_BF537_H -/* Include all Core registers and bit definitions*/ -#include <asm/cdef_LPBlackfin.h> - /* Include all MMR and bit defines common to BF534 */ #include "defBF534.h" diff --git a/arch/blackfin/mach-bf537/include/mach/gpio.h b/arch/blackfin/mach-bf537/include/mach/gpio.h index f80c2995efd..fba606b699c 100644 --- a/arch/blackfin/mach-bf537/include/mach/gpio.h +++ b/arch/blackfin/mach-bf537/include/mach/gpio.h @@ -62,4 +62,8 @@ #define PORT_G GPIO_PG0 #define PORT_H GPIO_PH0 +#include <mach-common/ports-f.h> +#include <mach-common/ports-g.h> +#include <mach-common/ports-h.h> + #endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf537/include/mach/pll.h b/arch/blackfin/mach-bf537/include/mach/pll.h index 169c106d0ed..94cca674d83 100644 --- a/arch/blackfin/mach-bf537/include/mach/pll.h +++ b/arch/blackfin/mach-bf537/include/mach/pll.h @@ -1,57 +1 @@ -/* - * Copyright 2005-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _MACH_PLL_H -#define _MACH_PLL_H - -#include <asm/blackfin.h> -#include <asm/irqflags.h> - -/* Writing to PLL_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_PLL_CTL(unsigned int val) -{ - unsigned long flags, iwr; - - if (val == bfin_read_PLL_CTL()) - return; - - flags = hard_local_irq_save(); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr = bfin_read32(SIC_IWR); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR, IWR_ENABLE(0)); - - bfin_write16(PLL_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR, iwr); - hard_local_irq_restore(flags); -} - -/* Writing to VR_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_VR_CTL(unsigned int val) -{ - unsigned long flags, iwr; - - if (val == bfin_read_VR_CTL()) - return; - - flags = hard_local_irq_save(); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr = bfin_read32(SIC_IWR); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR, IWR_ENABLE(0)); - - bfin_write16(VR_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR, iwr); - hard_local_irq_restore(flags); -} - -#endif /* _MACH_PLL_H */ +#include <mach-common/pll.h> diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c index c6fb0a52f84..e61424ef35e 100644 --- a/arch/blackfin/mach-bf538/boards/ezkit.c +++ b/arch/blackfin/mach-bf538/boards/ezkit.c @@ -82,7 +82,7 @@ static struct resource bfin_uart0_resources[] = { #endif }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -125,7 +125,7 @@ static struct resource bfin_uart1_resources[] = { }, }; -unsigned short bfin_uart1_peripherals[] = { +static unsigned short bfin_uart1_peripherals[] = { P_UART1_TX, P_UART1_RX, 0 }; @@ -168,7 +168,7 @@ static struct resource bfin_uart2_resources[] = { }, }; -unsigned short bfin_uart2_peripherals[] = { +static unsigned short bfin_uart2_peripherals[] = { P_UART2_TX, P_UART2_RX, 0 }; @@ -282,9 +282,9 @@ static struct resource bfin_sport0_uart_resources[] = { }, }; -unsigned short bfin_sport0_peripherals[] = { +static unsigned short bfin_sport0_peripherals[] = { P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 }; static struct platform_device bfin_sport0_uart_device = { @@ -316,9 +316,9 @@ static struct resource bfin_sport1_uart_resources[] = { }, }; -unsigned short bfin_sport1_peripherals[] = { +static unsigned short bfin_sport1_peripherals[] = { P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { @@ -350,7 +350,7 @@ static struct resource bfin_sport2_uart_resources[] = { }, }; -unsigned short bfin_sport2_peripherals[] = { +static unsigned short bfin_sport2_peripherals[] = { P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0 }; @@ -384,7 +384,7 @@ static struct resource bfin_sport3_uart_resources[] = { }, }; -unsigned short bfin_sport3_peripherals[] = { +static unsigned short bfin_sport3_peripherals[] = { P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0 }; @@ -402,7 +402,7 @@ static struct platform_device bfin_sport3_uart_device = { #endif #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) -unsigned short bfin_can_peripherals[] = { +static unsigned short bfin_can_peripherals[] = { P_CAN0_RX, P_CAN0_TX, 0 }; diff --git a/arch/blackfin/mach-bf538/dma.c b/arch/blackfin/mach-bf538/dma.c index 5dc02258921..cce8ef5a5ce 100644 --- a/arch/blackfin/mach-bf538/dma.c +++ b/arch/blackfin/mach-bf538/dma.c @@ -11,7 +11,7 @@ #include <asm/blackfin.h> #include <asm/dma.h> -struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { +struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { (struct dma_register *) DMA0_NEXT_DESC_PTR, (struct dma_register *) DMA1_NEXT_DESC_PTR, (struct dma_register *) DMA2_NEXT_DESC_PTR, @@ -32,14 +32,14 @@ struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { (struct dma_register *) DMA17_NEXT_DESC_PTR, (struct dma_register *) DMA18_NEXT_DESC_PTR, (struct dma_register *) DMA19_NEXT_DESC_PTR, - (struct dma_register *) MDMA0_D0_NEXT_DESC_PTR, - (struct dma_register *) MDMA0_S0_NEXT_DESC_PTR, - (struct dma_register *) MDMA0_D1_NEXT_DESC_PTR, - (struct dma_register *) MDMA0_S1_NEXT_DESC_PTR, - (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR, - (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR, - (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR, - (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR, + (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, + (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, + (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, + (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, + (struct dma_register *) MDMA_D2_NEXT_DESC_PTR, + (struct dma_register *) MDMA_S2_NEXT_DESC_PTR, + (struct dma_register *) MDMA_D3_NEXT_DESC_PTR, + (struct dma_register *) MDMA_S3_NEXT_DESC_PTR, }; EXPORT_SYMBOL(dma_io_base_addr); diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial.h new file mode 100644 index 00000000000..c66e2760aad --- /dev/null +++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial.h @@ -0,0 +1,14 @@ +/* + * mach/bfin_serial.h - Blackfin UART/Serial definitions + * + * Copyright 2006-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_MACH_SERIAL_H__ +#define __BFIN_MACH_SERIAL_H__ + +#define BFIN_UART_NR_PORTS 3 + +#endif diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h index 5c148142f04..beb502e9cb3 100644 --- a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h @@ -4,36 +4,9 @@ * Licensed under the GPL-2 or later. */ -#include <linux/serial.h> #include <asm/dma.h> #include <asm/portmux.h> -#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) -#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) -#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) -#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) -#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) -#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) -#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) - -#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v) -#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v) -#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v) -#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) -#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) -#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v) -#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v) -#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v) - -#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) -#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) - -#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) -#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) -#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) -#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) -#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) - #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) # define CONFIG_SERIAL_BFIN_CTSRTS @@ -54,50 +27,6 @@ # endif #endif -#define BFIN_UART_TX_FIFO_SIZE 2 - -/* - * The pin configuration is different from schematic - */ -struct bfin_serial_port { - struct uart_port port; - unsigned int old_status; - int status_irq; - unsigned int lsr; -#ifdef CONFIG_SERIAL_BFIN_DMA - int tx_done; - int tx_count; - struct circ_buf rx_dma_buf; - struct timer_list rx_dma_timer; - int rx_dma_nrows; - unsigned int tx_dma_channel; - unsigned int rx_dma_channel; - struct work_struct tx_dma_workqueue; -#endif -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - struct timer_list cts_timer; - int cts_pin; - int rts_pin; -#endif -}; - -/* The hardware clears the LSR bits upon read, so we need to cache - * some of the more fun bits in software so they don't get lost - * when checking the LSR in other code paths (TX). - */ -static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart) -{ - unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR); - uart->lsr |= (lsr & (BI|FE|PE|OE)); - return lsr | uart->lsr; -} - -static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) -{ - uart->lsr = 0; - bfin_write16(uart->port.membase + OFFSET_LSR, -1); -} - struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; @@ -160,3 +89,5 @@ struct bfin_serial_res bfin_serial_resource[] = { }; #define DRIVER_NAME "bfin-uart" + +#include <asm/bfin_serial.h> diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h index 08b5eabb1ed..791d08400cf 100644 --- a/arch/blackfin/mach-bf538/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Analog Devices Inc. + * Copyright 2008-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -10,31 +10,24 @@ #define BF538_FAMILY #include "bf538.h" -#include "defBF539.h" #include "anomaly.h" - -#if !defined(__ASSEMBLY__) -#include "cdefBF538.h" - -#if defined(CONFIG_BF539) -#include "cdefBF539.h" +#include <asm/def_LPBlackfin.h> +#ifdef CONFIG_BF538 +# include "defBF538.h" #endif +#ifdef CONFIG_BF539 +# include "defBF539.h" #endif -#define BFIN_UART_NR_PORTS 3 - -#define OFFSET_THR 0x00 /* Transmit Holding register */ -#define OFFSET_RBR 0x00 /* Receive Buffer register */ -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_IER 0x04 /* Interrupt Enable Register */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_GCTL 0x24 /* Global Control Register */ +#ifndef __ASSEMBLY__ +# include <asm/cdef_LPBlackfin.h> +# ifdef CONFIG_BF538 +# include "cdefBF538.h" +# endif +# ifdef CONFIG_BF539 +# include "cdefBF539.h" +# endif +#endif #endif diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h index 085b06b8c0a..f6a56792180 100644 --- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h +++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Analog Devices Inc. + * Copyright 2008-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -7,14 +7,6 @@ #ifndef _CDEF_BF538_H #define _CDEF_BF538_H -#include <asm/blackfin.h> - -/*include all Core registers and bit definitions*/ -#include "defBF539.h" - -/*include core specific register pointer definitions*/ -#include <asm/cdef_LPBlackfin.h> - #define bfin_writePTR(addr, val) bfin_write32(addr, val) #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) @@ -487,10 +479,10 @@ #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) -#define bfin_read_DMA0_TC_PER() bfin_read16(DMA0_TC_PER) -#define bfin_write_DMA0_TC_PER(val) bfin_write16(DMA0_TC_PER, val) -#define bfin_read_DMA0_TC_CNT() bfin_read16(DMA0_TC_CNT) -#define bfin_write_DMA0_TC_CNT(val) bfin_write16(DMA0_TC_CNT, val) +#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER) +#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val) +#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT) +#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val) #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) #define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) @@ -699,10 +691,10 @@ #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER) -#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER, val) -#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT) -#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT, val) +#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER) +#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val) +#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT) +#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val) #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) #define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) @@ -1015,273 +1007,214 @@ #define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val) #define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT) #define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val) -#define bfin_read_MDMA0_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA0_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA0_D0_START_ADDR() bfin_readPTR(MDMA0_D0_START_ADDR) -#define bfin_write_MDMA0_D0_START_ADDR(val) bfin_writePTR(MDMA0_D0_START_ADDR, val) -#define bfin_read_MDMA0_D0_CONFIG() bfin_read16(MDMA0_D0_CONFIG) -#define bfin_write_MDMA0_D0_CONFIG(val) bfin_write16(MDMA0_D0_CONFIG, val) -#define bfin_read_MDMA0_D0_X_COUNT() bfin_read16(MDMA0_D0_X_COUNT) -#define bfin_write_MDMA0_D0_X_COUNT(val) bfin_write16(MDMA0_D0_X_COUNT, val) -#define bfin_read_MDMA0_D0_X_MODIFY() bfin_read16(MDMA0_D0_X_MODIFY) -#define bfin_write_MDMA0_D0_X_MODIFY(val) bfin_write16(MDMA0_D0_X_MODIFY, val) -#define bfin_read_MDMA0_D0_Y_COUNT() bfin_read16(MDMA0_D0_Y_COUNT) -#define bfin_write_MDMA0_D0_Y_COUNT(val) bfin_write16(MDMA0_D0_Y_COUNT, val) -#define bfin_read_MDMA0_D0_Y_MODIFY() bfin_read16(MDMA0_D0_Y_MODIFY) -#define bfin_write_MDMA0_D0_Y_MODIFY(val) bfin_write16(MDMA0_D0_Y_MODIFY, val) -#define bfin_read_MDMA0_D0_CURR_DESC_PTR() bfin_readPTR(MDMA0_D0_CURR_DESC_PTR) -#define bfin_write_MDMA0_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D0_CURR_DESC_PTR, val) -#define bfin_read_MDMA0_D0_CURR_ADDR() bfin_readPTR(MDMA0_D0_CURR_ADDR) -#define bfin_write_MDMA0_D0_CURR_ADDR(val) bfin_writePTR(MDMA0_D0_CURR_ADDR, val) -#define bfin_read_MDMA0_D0_IRQ_STATUS() bfin_read16(MDMA0_D0_IRQ_STATUS) -#define bfin_write_MDMA0_D0_IRQ_STATUS(val) bfin_write16(MDMA0_D0_IRQ_STATUS, val) -#define bfin_read_MDMA0_D0_PERIPHERAL_MAP() bfin_read16(MDMA0_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA0_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D0_PERIPHERAL_MAP, val) -#define bfin_read_MDMA0_D0_CURR_X_COUNT() bfin_read16(MDMA0_D0_CURR_X_COUNT) -#define bfin_write_MDMA0_D0_CURR_X_COUNT(val) bfin_write16(MDMA0_D0_CURR_X_COUNT, val) -#define bfin_read_MDMA0_D0_CURR_Y_COUNT() bfin_read16(MDMA0_D0_CURR_Y_COUNT) -#define bfin_write_MDMA0_D0_CURR_Y_COUNT(val) bfin_write16(MDMA0_D0_CURR_Y_COUNT, val) -#define bfin_read_MDMA0_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA0_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA0_S0_START_ADDR() bfin_readPTR(MDMA0_S0_START_ADDR) -#define bfin_write_MDMA0_S0_START_ADDR(val) bfin_writePTR(MDMA0_S0_START_ADDR, val) -#define bfin_read_MDMA0_S0_CONFIG() bfin_read16(MDMA0_S0_CONFIG) -#define bfin_write_MDMA0_S0_CONFIG(val) bfin_write16(MDMA0_S0_CONFIG, val) -#define bfin_read_MDMA0_S0_X_COUNT() bfin_read16(MDMA0_S0_X_COUNT) -#define bfin_write_MDMA0_S0_X_COUNT(val) bfin_write16(MDMA0_S0_X_COUNT, val) -#define bfin_read_MDMA0_S0_X_MODIFY() bfin_read16(MDMA0_S0_X_MODIFY) -#define bfin_write_MDMA0_S0_X_MODIFY(val) bfin_write16(MDMA0_S0_X_MODIFY, val) -#define bfin_read_MDMA0_S0_Y_COUNT() bfin_read16(MDMA0_S0_Y_COUNT) -#define bfin_write_MDMA0_S0_Y_COUNT(val) bfin_write16(MDMA0_S0_Y_COUNT, val) -#define bfin_read_MDMA0_S0_Y_MODIFY() bfin_read16(MDMA0_S0_Y_MODIFY) -#define bfin_write_MDMA0_S0_Y_MODIFY(val) bfin_write16(MDMA0_S0_Y_MODIFY, val) -#define bfin_read_MDMA0_S0_CURR_DESC_PTR() bfin_readPTR(MDMA0_S0_CURR_DESC_PTR) -#define bfin_write_MDMA0_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S0_CURR_DESC_PTR, val) -#define bfin_read_MDMA0_S0_CURR_ADDR() bfin_readPTR(MDMA0_S0_CURR_ADDR) -#define bfin_write_MDMA0_S0_CURR_ADDR(val) bfin_writePTR(MDMA0_S0_CURR_ADDR, val) -#define bfin_read_MDMA0_S0_IRQ_STATUS() bfin_read16(MDMA0_S0_IRQ_STATUS) -#define bfin_write_MDMA0_S0_IRQ_STATUS(val) bfin_write16(MDMA0_S0_IRQ_STATUS, val) -#define bfin_read_MDMA0_S0_PERIPHERAL_MAP() bfin_read16(MDMA0_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA0_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S0_PERIPHERAL_MAP, val) -#define bfin_read_MDMA0_S0_CURR_X_COUNT() bfin_read16(MDMA0_S0_CURR_X_COUNT) -#define bfin_write_MDMA0_S0_CURR_X_COUNT(val) bfin_write16(MDMA0_S0_CURR_X_COUNT, val) -#define bfin_read_MDMA0_S0_CURR_Y_COUNT() bfin_read16(MDMA0_S0_CURR_Y_COUNT) -#define bfin_write_MDMA0_S0_CURR_Y_COUNT(val) bfin_write16(MDMA0_S0_CURR_Y_COUNT, val) -#define bfin_read_MDMA0_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA0_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA0_D1_START_ADDR() bfin_readPTR(MDMA0_D1_START_ADDR) -#define bfin_write_MDMA0_D1_START_ADDR(val) bfin_writePTR(MDMA0_D1_START_ADDR, val) -#define bfin_read_MDMA0_D1_CONFIG() bfin_read16(MDMA0_D1_CONFIG) -#define bfin_write_MDMA0_D1_CONFIG(val) bfin_write16(MDMA0_D1_CONFIG, val) -#define bfin_read_MDMA0_D1_X_COUNT() bfin_read16(MDMA0_D1_X_COUNT) -#define bfin_write_MDMA0_D1_X_COUNT(val) bfin_write16(MDMA0_D1_X_COUNT, val) -#define bfin_read_MDMA0_D1_X_MODIFY() bfin_read16(MDMA0_D1_X_MODIFY) -#define bfin_write_MDMA0_D1_X_MODIFY(val) bfin_write16(MDMA0_D1_X_MODIFY, val) -#define bfin_read_MDMA0_D1_Y_COUNT() bfin_read16(MDMA0_D1_Y_COUNT) -#define bfin_write_MDMA0_D1_Y_COUNT(val) bfin_write16(MDMA0_D1_Y_COUNT, val) -#define bfin_read_MDMA0_D1_Y_MODIFY() bfin_read16(MDMA0_D1_Y_MODIFY) -#define bfin_write_MDMA0_D1_Y_MODIFY(val) bfin_write16(MDMA0_D1_Y_MODIFY, val) -#define bfin_read_MDMA0_D1_CURR_DESC_PTR() bfin_readPTR(MDMA0_D1_CURR_DESC_PTR) -#define bfin_write_MDMA0_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D1_CURR_DESC_PTR, val) -#define bfin_read_MDMA0_D1_CURR_ADDR() bfin_readPTR(MDMA0_D1_CURR_ADDR) -#define bfin_write_MDMA0_D1_CURR_ADDR(val) bfin_writePTR(MDMA0_D1_CURR_ADDR, val) -#define bfin_read_MDMA0_D1_IRQ_STATUS() bfin_read16(MDMA0_D1_IRQ_STATUS) -#define bfin_write_MDMA0_D1_IRQ_STATUS(val) bfin_write16(MDMA0_D1_IRQ_STATUS, val) -#define bfin_read_MDMA0_D1_PERIPHERAL_MAP() bfin_read16(MDMA0_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA0_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D1_PERIPHERAL_MAP, val) -#define bfin_read_MDMA0_D1_CURR_X_COUNT() bfin_read16(MDMA0_D1_CURR_X_COUNT) -#define bfin_write_MDMA0_D1_CURR_X_COUNT(val) bfin_write16(MDMA0_D1_CURR_X_COUNT, val) -#define bfin_read_MDMA0_D1_CURR_Y_COUNT() bfin_read16(MDMA0_D1_CURR_Y_COUNT) -#define bfin_write_MDMA0_D1_CURR_Y_COUNT(val) bfin_write16(MDMA0_D1_CURR_Y_COUNT, val) -#define bfin_read_MDMA0_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA0_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA0_S1_START_ADDR() bfin_readPTR(MDMA0_S1_START_ADDR) -#define bfin_write_MDMA0_S1_START_ADDR(val) bfin_writePTR(MDMA0_S1_START_ADDR, val) -#define bfin_read_MDMA0_S1_CONFIG() bfin_read16(MDMA0_S1_CONFIG) -#define bfin_write_MDMA0_S1_CONFIG(val) bfin_write16(MDMA0_S1_CONFIG, val) -#define bfin_read_MDMA0_S1_X_COUNT() bfin_read16(MDMA0_S1_X_COUNT) -#define bfin_write_MDMA0_S1_X_COUNT(val) bfin_write16(MDMA0_S1_X_COUNT, val) -#define bfin_read_MDMA0_S1_X_MODIFY() bfin_read16(MDMA0_S1_X_MODIFY) -#define bfin_write_MDMA0_S1_X_MODIFY(val) bfin_write16(MDMA0_S1_X_MODIFY, val) -#define bfin_read_MDMA0_S1_Y_COUNT() bfin_read16(MDMA0_S1_Y_COUNT) -#define bfin_write_MDMA0_S1_Y_COUNT(val) bfin_write16(MDMA0_S1_Y_COUNT, val) -#define bfin_read_MDMA0_S1_Y_MODIFY() bfin_read16(MDMA0_S1_Y_MODIFY) -#define bfin_write_MDMA0_S1_Y_MODIFY(val) bfin_write16(MDMA0_S1_Y_MODIFY, val) -#define bfin_read_MDMA0_S1_CURR_DESC_PTR() bfin_readPTR(MDMA0_S1_CURR_DESC_PTR) -#define bfin_write_MDMA0_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S1_CURR_DESC_PTR, val) -#define bfin_read_MDMA0_S1_CURR_ADDR() bfin_readPTR(MDMA0_S1_CURR_ADDR) -#define bfin_write_MDMA0_S1_CURR_ADDR(val) bfin_writePTR(MDMA0_S1_CURR_ADDR, val) -#define bfin_read_MDMA0_S1_IRQ_STATUS() bfin_read16(MDMA0_S1_IRQ_STATUS) -#define bfin_write_MDMA0_S1_IRQ_STATUS(val) bfin_write16(MDMA0_S1_IRQ_STATUS, val) -#define bfin_read_MDMA0_S1_PERIPHERAL_MAP() bfin_read16(MDMA0_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA0_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S1_PERIPHERAL_MAP, val) -#define bfin_read_MDMA0_S1_CURR_X_COUNT() bfin_read16(MDMA0_S1_CURR_X_COUNT) -#define bfin_write_MDMA0_S1_CURR_X_COUNT(val) bfin_write16(MDMA0_S1_CURR_X_COUNT, val) -#define bfin_read_MDMA0_S1_CURR_Y_COUNT() bfin_read16(MDMA0_S1_CURR_Y_COUNT) -#define bfin_write_MDMA0_S1_CURR_Y_COUNT(val) bfin_write16(MDMA0_S1_CURR_Y_COUNT, val) -#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR) -#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val) -#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG) -#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val) -#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT) -#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val) -#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY) -#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val) -#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT) -#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val) -#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY) -#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val) -#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR) -#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val) -#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR) -#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val) -#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS) -#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val) -#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val) -#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT) -#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val) -#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT) -#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val) -#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR) -#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val) -#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG) -#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val) -#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT) -#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val) -#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY) -#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val) -#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT) -#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val) -#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY) -#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val) -#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR) -#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val) -#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR) -#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val) -#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS) -#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val) -#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val) -#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT) -#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val) -#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT) -#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val) -#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR) -#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val) -#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG) -#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val) -#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT) -#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val) -#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY) -#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val) -#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT) -#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val) -#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY) -#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val) -#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR) -#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val) -#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR) -#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val) -#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS) -#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val) -#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val) -#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT) -#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val) -#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT) -#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val) -#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR) -#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val) -#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG) -#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val) -#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT) -#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val) -#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY) -#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val) -#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT) -#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val) -#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY) -#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val) -#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR) -#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val) -#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR) -#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val) -#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS) -#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val) -#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val) -#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT) -#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val) -#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT) -#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val) - -#define bfin_read_MDMA_S0_CONFIG() bfin_read_MDMA0_S0_CONFIG() -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA0_S0_CONFIG(val) -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read_MDMA0_S0_IRQ_STATUS() -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA0_S0_IRQ_STATUS(val) -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read_MDMA0_S0_X_MODIFY() -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA0_S0_X_MODIFY(val) -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read_MDMA0_S0_Y_MODIFY() -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA0_S0_Y_MODIFY(val) -#define bfin_read_MDMA_S0_X_COUNT() bfin_read_MDMA0_S0_X_COUNT() -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA0_S0_X_COUNT(val) -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read_MDMA0_S0_Y_COUNT() -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA0_S0_Y_COUNT(val) -#define bfin_read_MDMA_S0_START_ADDR() bfin_read_MDMA0_S0_START_ADDR() -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA0_S0_START_ADDR(val) -#define bfin_read_MDMA_D0_CONFIG() bfin_read_MDMA0_D0_CONFIG() -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA0_D0_CONFIG(val) -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read_MDMA0_D0_IRQ_STATUS() -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA0_D0_IRQ_STATUS(val) -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read_MDMA0_D0_X_MODIFY() -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA0_D0_X_MODIFY(val) -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read_MDMA0_D0_Y_MODIFY() -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA0_D0_Y_MODIFY(val) -#define bfin_read_MDMA_D0_X_COUNT() bfin_read_MDMA0_D0_X_COUNT() -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA0_D0_X_COUNT(val) -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read_MDMA0_D0_Y_COUNT() -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA0_D0_Y_COUNT(val) -#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA0_D0_START_ADDR() -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA0_D0_START_ADDR(val) - -#define bfin_read_MDMA_S1_CONFIG() bfin_read_MDMA0_S1_CONFIG() -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write_MDMA0_S1_CONFIG(val) -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read_MDMA0_S1_IRQ_STATUS() -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write_MDMA0_S1_IRQ_STATUS(val) -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read_MDMA0_S1_X_MODIFY() -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write_MDMA0_S1_X_MODIFY(val) -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read_MDMA0_S1_Y_MODIFY() -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write_MDMA0_S1_Y_MODIFY(val) -#define bfin_read_MDMA_S1_X_COUNT() bfin_read_MDMA0_S1_X_COUNT() -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write_MDMA0_S1_X_COUNT(val) -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read_MDMA0_S1_Y_COUNT() -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write_MDMA0_S1_Y_COUNT(val) -#define bfin_read_MDMA_S1_START_ADDR() bfin_read_MDMA0_S1_START_ADDR() -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write_MDMA0_S1_START_ADDR(val) -#define bfin_read_MDMA_D1_CONFIG() bfin_read_MDMA0_D1_CONFIG() -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write_MDMA0_D1_CONFIG(val) -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read_MDMA0_D1_IRQ_STATUS() -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write_MDMA0_D1_IRQ_STATUS(val) -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read_MDMA0_D1_X_MODIFY() -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write_MDMA0_D1_X_MODIFY(val) -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read_MDMA0_D1_Y_MODIFY() -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write_MDMA0_D1_Y_MODIFY(val) -#define bfin_read_MDMA_D1_X_COUNT() bfin_read_MDMA0_D1_X_COUNT() -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write_MDMA0_D1_X_COUNT(val) -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read_MDMA0_D1_Y_COUNT() -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write_MDMA0_D1_Y_COUNT(val) -#define bfin_read_MDMA_D1_START_ADDR() bfin_read_MDMA0_D1_START_ADDR() -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA0_D1_START_ADDR(val) - +#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) +#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) +#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) +#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) +#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) +#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) +#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) +#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) +#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) +#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) +#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) +#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) +#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) +#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) +#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) +#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) +#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) +#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) +#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) +#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) +#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) +#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) +#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) +#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) +#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) +#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) +#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) +#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) +#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) +#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) +#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) +#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) +#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) +#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) +#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) +#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) +#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) +#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) +#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) +#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) +#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) +#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) +#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) +#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) +#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) +#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) +#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) +#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) +#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) +#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) +#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) +#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) +#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) +#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) +#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) +#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) +#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) +#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) +#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) +#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) +#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) +#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) +#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) +#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) +#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) +#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) +#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) +#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) +#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) +#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) +#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) +#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) +#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) +#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) +#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) +#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) +#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) +#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) +#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) +#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) +#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) +#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) +#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) +#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) +#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) +#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) +#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) +#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) +#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) +#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) +#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR) +#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR) +#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val) +#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) +#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) +#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) +#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) +#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) +#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val) +#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) +#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) +#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) +#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val) +#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR) +#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR) +#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val) +#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) +#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) +#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) +#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT) +#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val) +#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) +#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR) +#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR) +#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val) +#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) +#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) +#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) +#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) +#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) +#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val) +#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) +#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) +#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) +#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val) +#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR) +#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR) +#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val) +#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) +#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) +#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) +#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT) +#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val) +#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT) +#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val) +#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR) +#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR) +#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val) +#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) +#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) +#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) +#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) +#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) +#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val) +#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) +#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) +#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) +#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val) +#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR) +#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR) +#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val) +#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) +#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) +#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) +#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT) +#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val) +#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) +#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR) +#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR) +#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val) +#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) +#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) +#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) +#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) +#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) +#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val) +#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) +#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) +#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) +#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val) +#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR) +#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR) +#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val) +#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) +#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) +#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) +#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT) +#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val) +#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT) +#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val) #define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) @@ -2024,7 +1957,4 @@ #define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1) #define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val) -/* These need to be last due to the cdef/linux inter-dependencies */ -#include <asm/irq.h> - #endif diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF539.h b/arch/blackfin/mach-bf538/include/mach/cdefBF539.h index 198c4bbc8e5..acc15f3aba3 100644 --- a/arch/blackfin/mach-bf538/include/mach/cdefBF539.h +++ b/arch/blackfin/mach-bf538/include/mach/cdefBF539.h @@ -1,6 +1,7 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE +/* + * Copyright 2008-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. */ #ifndef _CDEF_BF539_H @@ -9,7 +10,6 @@ /* Include MMRs Common to BF538 */ #include "cdefBF538.h" - #define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG) #define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val) #define bfin_read_MXVR_PLL_CTL_0() bfin_read32(MXVR_PLL_CTL_0) diff --git a/arch/blackfin/mach-bf538/include/mach/defBF538.h b/arch/blackfin/mach-bf538/include/mach/defBF538.h new file mode 100644 index 00000000000..d27f81d6c4b --- /dev/null +++ b/arch/blackfin/mach-bf538/include/mach/defBF538.h @@ -0,0 +1,1825 @@ +/* + * Copyright 2008-2010 Analog Devices Inc. + * + * Licensed under the ADI BSD license or the GPL-2 (or later) + */ + +#ifndef _DEF_BF538_H +#define _DEF_BF538_H + +/* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */ +#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ +#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ +#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ +#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ +#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ +#define CHIPID 0xFFC00014 /* Chip ID Register */ + +/* CHIPID Masks */ +#define CHIPID_VERSION 0xF0000000 +#define CHIPID_FAMILY 0x0FFFF000 +#define CHIPID_MANUFACTURE 0x00000FFE + +/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ +#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ +#define SYSCR 0xFFC00104 /* System Configuration registe */ +#define SIC_RVECT 0xFFC00108 +#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ +#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ +#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ +#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ +#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ +#define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */ +#define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */ +#define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */ +#define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */ +#define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */ +#define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */ + + +/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ +#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ +#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ +#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ + + +/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ +#define RTC_STAT 0xFFC00300 /* RTC Status Register */ +#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ +#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ +#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ +#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ +#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ +#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ + + +/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ +#define UART0_THR 0xFFC00400 /* Transmit Holding register */ +#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ +#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ +#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ +#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ +#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ +#define UART0_LCR 0xFFC0040C /* Line Control Register */ +#define UART0_MCR 0xFFC00410 /* Modem Control Register */ +#define UART0_LSR 0xFFC00414 /* Line Status Register */ +#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ +#define UART0_GCTL 0xFFC00424 /* Global Control Register */ + + +/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */ + +#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */ +#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */ +#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */ +#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */ +#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */ +#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */ +#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */ +#define SPI0_REGBASE SPI0_CTL + + +/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ +#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ +#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ +#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ +#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ + +#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ +#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ +#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ +#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ + +#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ +#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ +#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ +#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ + +#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ +#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ +#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ + + +/* Programmable Flags (0xFFC00700 - 0xFFC007FF) */ +#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ +#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ +#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ +#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ +#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ +#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ +#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ +#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ +#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ +#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ +#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ +#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ +#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ +#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ +#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ +#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ +#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ + + +/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ +#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ +#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ +#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ +#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ +#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ +#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ +#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ + + +/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ +#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ +#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ +#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ +#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ +#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ +#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ +#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ +#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ +#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ +#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ +#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ +#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ +#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ +#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ +#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ +#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ +#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ +#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ + + +/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ +/* Asynchronous Memory Controller */ +#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ +#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ +#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ + +/* SDRAM Controller */ +#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ +#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ +#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ +#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ + + + +/* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */ + +#define DMAC0_TC_PER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */ +#define DMAC0_TC_CNT 0xFFC00B10 /* DMA Controller 0 Traffic Control Current Counts Register */ + + + +/* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF) */ + +#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ +#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ +#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ +#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ +#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ +#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ +#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ +#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ +#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ +#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ +#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ +#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ +#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ + +#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ +#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ +#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ +#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ +#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ +#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ +#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ +#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ +#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ +#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ +#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ +#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ +#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ + +#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ +#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ +#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ +#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ +#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ +#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ +#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ +#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ +#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ +#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ +#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ +#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ +#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ + +#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ +#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ +#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ +#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ +#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ +#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ +#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ +#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ +#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ +#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ +#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ +#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ +#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ + +#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ +#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ +#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ +#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ +#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ +#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ +#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ +#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ +#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ +#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ +#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ +#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ +#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ + +#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ +#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ +#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ +#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ +#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ +#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ +#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ +#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ +#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ +#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ +#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ +#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ +#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ + +#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ +#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ +#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ +#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ +#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ +#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ +#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ +#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ +#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ +#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ +#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ +#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ +#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ + +#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ +#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ +#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ +#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ +#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ +#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ +#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ +#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ +#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ +#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ +#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ +#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ +#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ + +#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */ +#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA0 Stream 0 Destination Start Address Register */ +#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA0 Stream 0 Destination Configuration Register */ +#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA0 Stream 0 Destination X Count Register */ +#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA0 Stream 0 Destination X Modify Register */ +#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA0 Stream 0 Destination Y Count Register */ +#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA0 Stream 0 Destination Y Modify Register */ +#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */ +#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA0 Stream 0 Destination Current Address Register */ +#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA0 Stream 0 Destination Interrupt/Status Register */ +#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA0 Stream 0 Destination Peripheral Map Register */ +#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA0 Stream 0 Destination Current X Count Register */ +#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA0 Stream 0 Destination Current Y Count Register */ + +#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */ +#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA0 Stream 0 Source Start Address Register */ +#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA0 Stream 0 Source Configuration Register */ +#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA0 Stream 0 Source X Count Register */ +#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA0 Stream 0 Source X Modify Register */ +#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA0 Stream 0 Source Y Count Register */ +#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA0 Stream 0 Source Y Modify Register */ +#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */ +#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA0 Stream 0 Source Current Address Register */ +#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA0 Stream 0 Source Interrupt/Status Register */ +#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA0 Stream 0 Source Peripheral Map Register */ +#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA0 Stream 0 Source Current X Count Register */ +#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA0 Stream 0 Source Current Y Count Register */ + +#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */ +#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA0 Stream 1 Destination Start Address Register */ +#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA0 Stream 1 Destination Configuration Register */ +#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA0 Stream 1 Destination X Count Register */ +#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA0 Stream 1 Destination X Modify Register */ +#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA0 Stream 1 Destination Y Count Register */ +#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA0 Stream 1 Destination Y Modify Register */ +#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */ +#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA0 Stream 1 Destination Current Address Register */ +#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA0 Stream 1 Destination Interrupt/Status Register */ +#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA0 Stream 1 Destination Peripheral Map Register */ +#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA0 Stream 1 Destination Current X Count Register */ +#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA0 Stream 1 Destination Current Y Count Register */ + +#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */ +#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA0 Stream 1 Source Start Address Register */ +#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA0 Stream 1 Source Configuration Register */ +#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA0 Stream 1 Source X Count Register */ +#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA0 Stream 1 Source X Modify Register */ +#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA0 Stream 1 Source Y Count Register */ +#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA0 Stream 1 Source Y Modify Register */ +#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */ +#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA0 Stream 1 Source Current Address Register */ +#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA0 Stream 1 Source Interrupt/Status Register */ +#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA0 Stream 1 Source Peripheral Map Register */ +#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */ +#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */ + + +/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ +#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ +#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ +#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ +#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ +#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ + + +/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */ +#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ +#define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */ +#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ +#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ +#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ +#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ +#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ +#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ +#define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */ +#define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */ +#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ +#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ +#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ +#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ +#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ +#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ + +#define TWI0_REGBASE TWI0_CLKDIV + +/* the following are for backwards compatibility */ +#define TWI0_PRESCALE TWI0_CONTROL +#define TWI0_INT_SRC TWI0_INT_STAT +#define TWI0_INT_ENABLE TWI0_INT_MASK + + +/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */ + +/* GPIO Port C Register Names */ +#define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */ +#define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */ +#define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */ +#define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */ +#define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */ +#define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */ +#define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */ + +/* GPIO Port D Register Names */ +#define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */ +#define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */ +#define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */ +#define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */ +#define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */ +#define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */ +#define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */ + +/* GPIO Port E Register Names */ +#define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */ +#define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */ +#define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */ +#define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */ +#define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */ +#define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */ +#define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */ + +/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */ + +#define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */ +#define DMAC1_TC_CNT 0xFFC01B10 /* DMA Controller 1 Traffic Control Current Counts Register */ + + + +/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */ +#define DMA8_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 8 Next Descriptor Pointer Register */ +#define DMA8_START_ADDR 0xFFC01C04 /* DMA Channel 8 Start Address Register */ +#define DMA8_CONFIG 0xFFC01C08 /* DMA Channel 8 Configuration Register */ +#define DMA8_X_COUNT 0xFFC01C10 /* DMA Channel 8 X Count Register */ +#define DMA8_X_MODIFY 0xFFC01C14 /* DMA Channel 8 X Modify Register */ +#define DMA8_Y_COUNT 0xFFC01C18 /* DMA Channel 8 Y Count Register */ +#define DMA8_Y_MODIFY 0xFFC01C1C /* DMA Channel 8 Y Modify Register */ +#define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */ +#define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */ +#define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */ +#define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */ +#define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */ +#define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */ + +#define DMA9_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 9 Next Descriptor Pointer Register */ +#define DMA9_START_ADDR 0xFFC01C44 /* DMA Channel 9 Start Address Register */ +#define DMA9_CONFIG 0xFFC01C48 /* DMA Channel 9 Configuration Register */ +#define DMA9_X_COUNT 0xFFC01C50 /* DMA Channel 9 X Count Register */ +#define DMA9_X_MODIFY 0xFFC01C54 /* DMA Channel 9 X Modify Register */ +#define DMA9_Y_COUNT 0xFFC01C58 /* DMA Channel 9 Y Count Register */ +#define DMA9_Y_MODIFY 0xFFC01C5C /* DMA Channel 9 Y Modify Register */ +#define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */ +#define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */ +#define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */ +#define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */ +#define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */ +#define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */ + +#define DMA10_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 10 Next Descriptor Pointer Register */ +#define DMA10_START_ADDR 0xFFC01C84 /* DMA Channel 10 Start Address Register */ +#define DMA10_CONFIG 0xFFC01C88 /* DMA Channel 10 Configuration Register */ +#define DMA10_X_COUNT 0xFFC01C90 /* DMA Channel 10 X Count Register */ +#define DMA10_X_MODIFY 0xFFC01C94 /* DMA Channel 10 X Modify Register */ +#define DMA10_Y_COUNT 0xFFC01C98 /* DMA Channel 10 Y Count Register */ +#define DMA10_Y_MODIFY 0xFFC01C9C /* DMA Channel 10 Y Modify Register */ +#define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */ +#define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */ +#define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */ +#define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */ +#define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */ +#define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */ + +#define DMA11_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 11 Next Descriptor Pointer Register */ +#define DMA11_START_ADDR 0xFFC01CC4 /* DMA Channel 11 Start Address Register */ +#define DMA11_CONFIG 0xFFC01CC8 /* DMA Channel 11 Configuration Register */ +#define DMA11_X_COUNT 0xFFC01CD0 /* DMA Channel 11 X Count Register */ +#define DMA11_X_MODIFY 0xFFC01CD4 /* DMA Channel 11 X Modify Register */ +#define DMA11_Y_COUNT 0xFFC01CD8 /* DMA Channel 11 Y Count Register */ +#define DMA11_Y_MODIFY 0xFFC01CDC /* DMA Channel 11 Y Modify Register */ +#define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */ +#define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */ +#define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */ +#define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */ +#define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */ +#define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */ + +#define DMA12_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 12 Next Descriptor Pointer Register */ +#define DMA12_START_ADDR 0xFFC01D04 /* DMA Channel 12 Start Address Register */ +#define DMA12_CONFIG 0xFFC01D08 /* DMA Channel 12 Configuration Register */ +#define DMA12_X_COUNT 0xFFC01D10 /* DMA Channel 12 X Count Register */ +#define DMA12_X_MODIFY 0xFFC01D14 /* DMA Channel 12 X Modify Register */ +#define DMA12_Y_COUNT 0xFFC01D18 /* DMA Channel 12 Y Count Register */ +#define DMA12_Y_MODIFY 0xFFC01D1C /* DMA Channel 12 Y Modify Register */ +#define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */ +#define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */ +#define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */ +#define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */ +#define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */ +#define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */ + +#define DMA13_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 13 Next Descriptor Pointer Register */ +#define DMA13_START_ADDR 0xFFC01D44 /* DMA Channel 13 Start Address Register */ +#define DMA13_CONFIG 0xFFC01D48 /* DMA Channel 13 Configuration Register */ +#define DMA13_X_COUNT 0xFFC01D50 /* DMA Channel 13 X Count Register */ +#define DMA13_X_MODIFY 0xFFC01D54 /* DMA Channel 13 X Modify Register */ +#define DMA13_Y_COUNT 0xFFC01D58 /* DMA Channel 13 Y Count Register */ +#define DMA13_Y_MODIFY 0xFFC01D5C /* DMA Channel 13 Y Modify Register */ +#define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */ +#define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */ +#define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */ +#define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */ +#define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */ +#define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */ + +#define DMA14_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 14 Next Descriptor Pointer Register */ +#define DMA14_START_ADDR 0xFFC01D84 /* DMA Channel 14 Start Address Register */ +#define DMA14_CONFIG 0xFFC01D88 /* DMA Channel 14 Configuration Register */ +#define DMA14_X_COUNT 0xFFC01D90 /* DMA Channel 14 X Count Register */ +#define DMA14_X_MODIFY 0xFFC01D94 /* DMA Channel 14 X Modify Register */ +#define DMA14_Y_COUNT 0xFFC01D98 /* DMA Channel 14 Y Count Register */ +#define DMA14_Y_MODIFY 0xFFC01D9C /* DMA Channel 14 Y Modify Register */ +#define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */ +#define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */ +#define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */ +#define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */ +#define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */ +#define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */ + +#define DMA15_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 15 Next Descriptor Pointer Register */ +#define DMA15_START_ADDR 0xFFC01DC4 /* DMA Channel 15 Start Address Register */ +#define DMA15_CONFIG 0xFFC01DC8 /* DMA Channel 15 Configuration Register */ +#define DMA15_X_COUNT 0xFFC01DD0 /* DMA Channel 15 X Count Register */ +#define DMA15_X_MODIFY 0xFFC01DD4 /* DMA Channel 15 X Modify Register */ +#define DMA15_Y_COUNT 0xFFC01DD8 /* DMA Channel 15 Y Count Register */ +#define DMA15_Y_MODIFY 0xFFC01DDC /* DMA Channel 15 Y Modify Register */ +#define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */ +#define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */ +#define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */ +#define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */ +#define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */ +#define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */ + +#define DMA16_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 16 Next Descriptor Pointer Register */ +#define DMA16_START_ADDR 0xFFC01E04 /* DMA Channel 16 Start Address Register */ +#define DMA16_CONFIG 0xFFC01E08 /* DMA Channel 16 Configuration Register */ +#define DMA16_X_COUNT 0xFFC01E10 /* DMA Channel 16 X Count Register */ +#define DMA16_X_MODIFY 0xFFC01E14 /* DMA Channel 16 X Modify Register */ +#define DMA16_Y_COUNT 0xFFC01E18 /* DMA Channel 16 Y Count Register */ +#define DMA16_Y_MODIFY 0xFFC01E1C /* DMA Channel 16 Y Modify Register */ +#define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */ +#define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */ +#define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */ +#define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */ +#define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */ +#define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */ + +#define DMA17_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 17 Next Descriptor Pointer Register */ +#define DMA17_START_ADDR 0xFFC01E44 /* DMA Channel 17 Start Address Register */ +#define DMA17_CONFIG 0xFFC01E48 /* DMA Channel 17 Configuration Register */ +#define DMA17_X_COUNT 0xFFC01E50 /* DMA Channel 17 X Count Register */ +#define DMA17_X_MODIFY 0xFFC01E54 /* DMA Channel 17 X Modify Register */ +#define DMA17_Y_COUNT 0xFFC01E58 /* DMA Channel 17 Y Count Register */ +#define DMA17_Y_MODIFY 0xFFC01E5C /* DMA Channel 17 Y Modify Register */ +#define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */ +#define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */ +#define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */ +#define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */ +#define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */ +#define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */ + +#define DMA18_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 18 Next Descriptor Pointer Register */ +#define DMA18_START_ADDR 0xFFC01E84 /* DMA Channel 18 Start Address Register */ +#define DMA18_CONFIG 0xFFC01E88 /* DMA Channel 18 Configuration Register */ +#define DMA18_X_COUNT 0xFFC01E90 /* DMA Channel 18 X Count Register */ +#define DMA18_X_MODIFY 0xFFC01E94 /* DMA Channel 18 X Modify Register */ +#define DMA18_Y_COUNT 0xFFC01E98 /* DMA Channel 18 Y Count Register */ +#define DMA18_Y_MODIFY 0xFFC01E9C /* DMA Channel 18 Y Modify Register */ +#define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */ +#define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */ +#define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */ +#define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */ +#define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */ +#define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */ + +#define DMA19_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 19 Next Descriptor Pointer Register */ +#define DMA19_START_ADDR 0xFFC01EC4 /* DMA Channel 19 Start Address Register */ +#define DMA19_CONFIG 0xFFC01EC8 /* DMA Channel 19 Configuration Register */ +#define DMA19_X_COUNT 0xFFC01ED0 /* DMA Channel 19 X Count Register */ +#define DMA19_X_MODIFY 0xFFC01ED4 /* DMA Channel 19 X Modify Register */ +#define DMA19_Y_COUNT 0xFFC01ED8 /* DMA Channel 19 Y Count Register */ +#define DMA19_Y_MODIFY 0xFFC01EDC /* DMA Channel 19 Y Modify Register */ +#define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */ +#define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */ +#define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */ +#define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */ +#define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */ +#define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */ + +#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */ +#define MDMA_D2_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address Register */ +#define MDMA_D2_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration Register */ +#define MDMA_D2_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination X Count Register */ +#define MDMA_D2_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Destination X Modify Register */ +#define MDMA_D2_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Y Count Register */ +#define MDMA_D2_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Destination Y Modify Register */ +#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */ +#define MDMA_D2_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address Register */ +#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */ +#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map Register */ +#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Destination Current X Count Register */ +#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Destination Current Y Count Register */ + +#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */ +#define MDMA_S2_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address Register */ +#define MDMA_S2_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration Register */ +#define MDMA_S2_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source X Count Register */ +#define MDMA_S2_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source X Modify Register */ +#define MDMA_S2_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Y Count Register */ +#define MDMA_S2_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Y Modify Register */ +#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */ +#define MDMA_S2_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address Register */ +#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status Register */ +#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map Register */ +#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current X Count Register */ +#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Y Count Register */ + +#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */ +#define MDMA_D3_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address Register */ +#define MDMA_D3_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration Register */ +#define MDMA_D3_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination X Count Register */ +#define MDMA_D3_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Destination X Modify Register */ +#define MDMA_D3_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Y Count Register */ +#define MDMA_D3_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Destination Y Modify Register */ +#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */ +#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Destination Current Address Register */ +#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Destination Interrupt/Status Register */ +#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Destination Peripheral Map Register */ +#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Destination Current X Count Register */ +#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Destination Current Y Count Register */ + +#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */ +#define MDMA_S3_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address Register */ +#define MDMA_S3_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration Register */ +#define MDMA_S3_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source X Count Register */ +#define MDMA_S3_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source X Modify Register */ +#define MDMA_S3_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Y Count Register */ +#define MDMA_S3_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Y Modify Register */ +#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */ +#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address Register */ +#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status Register */ +#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map Register */ +#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current X Count Register */ +#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Y Count Register */ + + +/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ +#define UART1_THR 0xFFC02000 /* Transmit Holding register */ +#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ +#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ +#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ +#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ +#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ +#define UART1_LCR 0xFFC0200C /* Line Control Register */ +#define UART1_MCR 0xFFC02010 /* Modem Control Register */ +#define UART1_LSR 0xFFC02014 /* Line Status Register */ +#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ +#define UART1_GCTL 0xFFC02024 /* Global Control Register */ + + +/* UART2 Controller (0xFFC02100 - 0xFFC021FF) */ +#define UART2_THR 0xFFC02100 /* Transmit Holding register */ +#define UART2_RBR 0xFFC02100 /* Receive Buffer register */ +#define UART2_DLL 0xFFC02100 /* Divisor Latch (Low-Byte) */ +#define UART2_IER 0xFFC02104 /* Interrupt Enable Register */ +#define UART2_DLH 0xFFC02104 /* Divisor Latch (High-Byte) */ +#define UART2_IIR 0xFFC02108 /* Interrupt Identification Register */ +#define UART2_LCR 0xFFC0210C /* Line Control Register */ +#define UART2_MCR 0xFFC02110 /* Modem Control Register */ +#define UART2_LSR 0xFFC02114 /* Line Status Register */ +#define UART2_SCR 0xFFC0211C /* SCR Scratch Register */ +#define UART2_GCTL 0xFFC02124 /* Global Control Register */ + + +/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */ +#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */ +#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */ +#define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */ +#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */ +#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */ +#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */ +#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */ +#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */ +#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */ +#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */ +#define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */ +#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */ +#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */ +#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */ +#define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */ +#define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */ +#define TWI1_REGBASE TWI1_CLKDIV + + +/* the following are for backwards compatibility */ +#define TWI1_PRESCALE TWI1_CONTROL +#define TWI1_INT_SRC TWI1_INT_STAT +#define TWI1_INT_ENABLE TWI1_INT_MASK + + +/* SPI1 Controller (0xFFC02300 - 0xFFC023FF) */ +#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */ +#define SPI1_FLG 0xFFC02304 /* SPI1 Flag register */ +#define SPI1_STAT 0xFFC02308 /* SPI1 Status register */ +#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */ +#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */ +#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud rate Register */ +#define SPI1_SHADOW 0xFFC02318 /* SPI1_RDBR Shadow Register */ +#define SPI1_REGBASE SPI1_CTL + +/* SPI2 Controller (0xFFC02400 - 0xFFC024FF) */ +#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */ +#define SPI2_FLG 0xFFC02404 /* SPI2 Flag register */ +#define SPI2_STAT 0xFFC02408 /* SPI2 Status register */ +#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */ +#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */ +#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud rate Register */ +#define SPI2_SHADOW 0xFFC02418 /* SPI2_RDBR Shadow Register */ +#define SPI2_REGBASE SPI2_CTL + +/* SPORT2 Controller (0xFFC02500 - 0xFFC025FF) */ +#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */ +#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */ +#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Clock Divider */ +#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider */ +#define SPORT2_TX 0xFFC02510 /* SPORT2 TX Data Register */ +#define SPORT2_RX 0xFFC02518 /* SPORT2 RX Data Register */ +#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Transmit Configuration 1 Register */ +#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Transmit Configuration 2 Register */ +#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */ +#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider */ +#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */ +#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */ +#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi-Channel Configuration Register 1 */ +#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi-Channel Configuration Register 2 */ +#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi-Channel Transmit Select Register 0 */ +#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi-Channel Transmit Select Register 1 */ +#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi-Channel Transmit Select Register 2 */ +#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi-Channel Transmit Select Register 3 */ +#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */ +#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi-Channel Receive Select Register 1 */ +#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi-Channel Receive Select Register 2 */ +#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi-Channel Receive Select Register 3 */ + + +/* SPORT3 Controller (0xFFC02600 - 0xFFC026FF) */ +#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */ +#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */ +#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Clock Divider */ +#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider */ +#define SPORT3_TX 0xFFC02610 /* SPORT3 TX Data Register */ +#define SPORT3_RX 0xFFC02618 /* SPORT3 RX Data Register */ +#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Transmit Configuration 1 Register */ +#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Transmit Configuration 2 Register */ +#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Clock Divider */ +#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider */ +#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */ +#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */ +#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi-Channel Configuration Register 1 */ +#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi-Channel Configuration Register 2 */ +#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi-Channel Transmit Select Register 0 */ +#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi-Channel Transmit Select Register 1 */ +#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi-Channel Transmit Select Register 2 */ +#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi-Channel Transmit Select Register 3 */ +#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */ +#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi-Channel Receive Select Register 1 */ +#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi-Channel Receive Select Register 2 */ +#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi-Channel Receive Select Register 3 */ + + +/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */ +/* For Mailboxes 0-15 */ +#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */ +#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */ +#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */ +#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */ +#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */ +#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */ +#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */ +#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */ +#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */ +#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */ +#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */ +#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */ +#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */ + +/* For Mailboxes 16-31 */ +#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */ +#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */ +#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */ +#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */ +#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */ +#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */ +#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */ +#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */ +#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */ +#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */ +#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */ +#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */ +#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */ + +#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */ +#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */ + +#define CAN_DEBUG 0xFFC02A88 /* Debug Register */ +/* the following is for backwards compatibility */ +#define CAN_CNF CAN_DEBUG + +#define CAN_STATUS 0xFFC02A8C /* Global Status Register */ +#define CAN_CEC 0xFFC02A90 /* Error Counter Register */ +#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */ +#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */ +#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ +#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ +#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ +#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ +#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ +#define CAN_ESR 0xFFC02AB4 /* Error Status Register */ +#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */ +#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Reload/Capture Register */ +#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */ + +/* Mailbox Acceptance Masks */ +#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */ +#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */ +#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */ +#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */ +#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */ +#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */ +#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */ +#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */ +#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */ +#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */ +#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */ +#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */ +#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */ +#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */ +#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */ +#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */ +#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */ +#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */ +#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */ +#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */ +#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */ +#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */ +#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */ +#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */ +#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */ +#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */ +#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */ +#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */ +#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */ +#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */ +#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */ +#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */ + +#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */ +#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */ +#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */ +#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */ +#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */ +#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */ +#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */ +#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */ +#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */ +#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */ +#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */ +#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */ +#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */ +#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */ +#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */ +#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */ +#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */ +#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */ +#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */ +#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */ +#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */ +#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */ +#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */ +#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */ +#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */ +#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */ +#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */ +#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */ +#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */ +#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */ +#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */ +#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */ + +/* CAN Acceptance Mask Macros */ +#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8)) +#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8)) + +/* Mailbox Registers */ +#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */ +#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */ +#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */ +#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */ +#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */ +#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */ +#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */ +#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */ + +#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */ +#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */ +#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */ +#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */ +#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */ +#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */ +#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */ +#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */ + +#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */ +#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */ +#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */ +#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */ +#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */ +#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */ +#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */ +#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */ + +#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */ +#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */ +#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */ +#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */ +#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */ +#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */ +#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */ +#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */ + +#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */ +#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */ +#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */ +#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */ +#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */ +#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */ +#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */ +#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */ + +#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */ +#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */ +#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */ +#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */ +#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */ +#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */ +#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */ +#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */ + +#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */ +#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */ +#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */ +#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */ +#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */ +#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */ +#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */ +#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */ + +#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */ +#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */ +#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */ +#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */ +#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */ +#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */ +#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */ +#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */ + +#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */ +#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */ +#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */ +#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */ +#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */ +#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */ +#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */ +#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */ + +#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */ +#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */ +#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */ +#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */ +#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */ +#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */ +#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */ +#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */ + +#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */ +#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */ +#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */ +#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */ +#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */ +#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */ +#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */ +#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */ + +#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */ +#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */ +#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */ +#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */ +#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */ +#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */ +#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */ +#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */ + +#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */ +#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */ +#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */ +#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */ +#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */ +#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */ +#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */ +#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */ + +#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */ +#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */ +#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */ +#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */ +#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */ +#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */ +#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */ +#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */ + +#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */ +#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */ +#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */ +#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */ +#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */ +#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */ +#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */ +#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */ + +#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */ +#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */ +#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */ +#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */ +#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */ +#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */ +#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */ +#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */ + +#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */ +#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */ +#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */ +#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */ +#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */ +#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */ +#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */ +#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */ + +#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */ +#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */ +#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */ +#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */ +#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */ +#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */ +#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */ +#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */ + +#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */ +#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */ +#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */ +#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */ +#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */ +#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */ +#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */ +#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */ + +#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */ +#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */ +#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */ +#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */ +#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */ +#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */ +#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */ +#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */ + +#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */ +#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */ +#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */ +#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */ +#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */ +#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */ +#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */ +#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */ + +#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */ +#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */ +#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */ +#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */ +#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */ +#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */ +#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */ +#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */ + +#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */ +#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */ +#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */ +#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */ +#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */ +#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */ +#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */ +#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */ + +#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */ +#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */ +#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */ +#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */ +#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */ +#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */ +#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */ +#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */ + +#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */ +#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */ +#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */ +#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */ +#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */ +#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */ +#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */ +#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */ + +#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */ +#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */ +#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */ +#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */ +#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */ +#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */ +#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */ +#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */ + +#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */ +#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */ +#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */ +#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */ +#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */ +#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */ +#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */ +#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */ + +#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */ +#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */ +#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */ +#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */ +#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */ +#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */ +#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */ +#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */ + +#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */ +#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */ +#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */ +#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */ +#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */ +#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */ +#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */ +#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */ + +#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */ +#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */ +#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */ +#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */ +#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */ +#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */ +#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */ +#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */ + +#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */ +#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */ +#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */ +#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */ +#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */ +#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */ +#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */ +#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */ + +#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */ +#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */ +#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */ +#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */ +#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */ +#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */ +#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */ +#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */ + +/* CAN Mailbox Area Macros */ +#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20)) +#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20)) +#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20)) +#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20)) +#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20)) +#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20)) +#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20)) +#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20)) + + +/*********************************************************************************** */ +/* System MMR Register Bits and Macros */ +/******************************************************************************* */ + +/* SWRST Mask */ +#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ +#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ +#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ +#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ +#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ + +/* SYSCR Masks */ +#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */ +#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ + + +/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ + +/* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */ +#define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */ +#define DMAC0_ERR_IRQ 0x00000002 /* DMA Controller 0 Error Interrupt Request */ +#define PPI_ERR_IRQ 0x00000004 /* PPI Error Interrupt Request */ +#define SPORT0_ERR_IRQ 0x00000008 /* SPORT0 Error Interrupt Request */ +#define SPORT1_ERR_IRQ 0x00000010 /* SPORT1 Error Interrupt Request */ +#define SPI0_ERR_IRQ 0x00000020 /* SPI0 Error Interrupt Request */ +#define UART0_ERR_IRQ 0x00000040 /* UART0 Error Interrupt Request */ +#define RTC_IRQ 0x00000080 /* Real-Time Clock Interrupt Request */ +#define DMA0_IRQ 0x00000100 /* DMA Channel 0 (PPI) Interrupt Request */ +#define DMA1_IRQ 0x00000200 /* DMA Channel 1 (SPORT0 RX) Interrupt Request */ +#define DMA2_IRQ 0x00000400 /* DMA Channel 2 (SPORT0 TX) Interrupt Request */ +#define DMA3_IRQ 0x00000800 /* DMA Channel 3 (SPORT1 RX) Interrupt Request */ +#define DMA4_IRQ 0x00001000 /* DMA Channel 4 (SPORT1 TX) Interrupt Request */ +#define DMA5_IRQ 0x00002000 /* DMA Channel 5 (SPI) Interrupt Request */ +#define DMA6_IRQ 0x00004000 /* DMA Channel 6 (UART RX) Interrupt Request */ +#define DMA7_IRQ 0x00008000 /* DMA Channel 7 (UART TX) Interrupt Request */ +#define TIMER0_IRQ 0x00010000 /* Timer 0 Interrupt Request */ +#define TIMER1_IRQ 0x00020000 /* Timer 1 Interrupt Request */ +#define TIMER2_IRQ 0x00040000 /* Timer 2 Interrupt Request */ +#define PFA_IRQ 0x00080000 /* Programmable Flag Interrupt Request A */ +#define PFB_IRQ 0x00100000 /* Programmable Flag Interrupt Request B */ +#define MDMA0_0_IRQ 0x00200000 /* MemDMA0 Stream 0 Interrupt Request */ +#define MDMA0_1_IRQ 0x00400000 /* MemDMA0 Stream 1 Interrupt Request */ +#define WDOG_IRQ 0x00800000 /* Software Watchdog Timer Interrupt Request */ +#define DMAC1_ERR_IRQ 0x01000000 /* DMA Controller 1 Error Interrupt Request */ +#define SPORT2_ERR_IRQ 0x02000000 /* SPORT2 Error Interrupt Request */ +#define SPORT3_ERR_IRQ 0x04000000 /* SPORT3 Error Interrupt Request */ +#define MXVR_SD_IRQ 0x08000000 /* MXVR Synchronous Data Interrupt Request */ +#define SPI1_ERR_IRQ 0x10000000 /* SPI1 Error Interrupt Request */ +#define SPI2_ERR_IRQ 0x20000000 /* SPI2 Error Interrupt Request */ +#define UART1_ERR_IRQ 0x40000000 /* UART1 Error Interrupt Request */ +#define UART2_ERR_IRQ 0x80000000 /* UART2 Error Interrupt Request */ + +/* the following are for backwards compatibility */ +#define DMA0_ERR_IRQ DMAC0_ERR_IRQ +#define DMA1_ERR_IRQ DMAC1_ERR_IRQ + + +/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */ +#define CAN_ERR_IRQ 0x00000001 /* CAN Error Interrupt Request */ +#define DMA8_IRQ 0x00000002 /* DMA Channel 8 (SPORT2 RX) Interrupt Request */ +#define DMA9_IRQ 0x00000004 /* DMA Channel 9 (SPORT2 TX) Interrupt Request */ +#define DMA10_IRQ 0x00000008 /* DMA Channel 10 (SPORT3 RX) Interrupt Request */ +#define DMA11_IRQ 0x00000010 /* DMA Channel 11 (SPORT3 TX) Interrupt Request */ +#define DMA12_IRQ 0x00000020 /* DMA Channel 12 Interrupt Request */ +#define DMA13_IRQ 0x00000040 /* DMA Channel 13 Interrupt Request */ +#define DMA14_IRQ 0x00000080 /* DMA Channel 14 (SPI1) Interrupt Request */ +#define DMA15_IRQ 0x00000100 /* DMA Channel 15 (SPI2) Interrupt Request */ +#define DMA16_IRQ 0x00000200 /* DMA Channel 16 (UART1 RX) Interrupt Request */ +#define DMA17_IRQ 0x00000400 /* DMA Channel 17 (UART1 TX) Interrupt Request */ +#define DMA18_IRQ 0x00000800 /* DMA Channel 18 (UART2 RX) Interrupt Request */ +#define DMA19_IRQ 0x00001000 /* DMA Channel 19 (UART2 TX) Interrupt Request */ +#define TWI0_IRQ 0x00002000 /* TWI0 Interrupt Request */ +#define TWI1_IRQ 0x00004000 /* TWI1 Interrupt Request */ +#define CAN_RX_IRQ 0x00008000 /* CAN Receive Interrupt Request */ +#define CAN_TX_IRQ 0x00010000 /* CAN Transmit Interrupt Request */ +#define MDMA1_0_IRQ 0x00020000 /* MemDMA1 Stream 0 Interrupt Request */ +#define MDMA1_1_IRQ 0x00040000 /* MemDMA1 Stream 1 Interrupt Request */ +#define MXVR_STAT_IRQ 0x00080000 /* MXVR Status Interrupt Request */ +#define MXVR_CM_IRQ 0x00100000 /* MXVR Control Message Interrupt Request */ +#define MXVR_AP_IRQ 0x00200000 /* MXVR Asynchronous Packet Interrupt */ + +/* the following are for backwards compatibility */ +#define MDMA0_IRQ MDMA1_0_IRQ +#define MDMA1_IRQ MDMA1_1_IRQ + +#ifdef _MISRA_RULES +#define _MF15 0xFu +#define _MF7 7u +#else +#define _MF15 0xF +#define _MF7 7 +#endif /* _MISRA_RULES */ + +/* SIC_IMASKx Masks */ +#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ +#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ +#ifdef _MISRA_RULES +#define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */ +#define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */ +#else +#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ +#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ +#endif /* _MISRA_RULES */ + +/* SIC_IWRx Masks */ +#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ +#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ +#ifdef _MISRA_RULES +#define IWR_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */ +#define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */ +#else +#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ +#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ +#endif /* _MISRA_RULES */ + +/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ +/* PPI_CONTROL Masks */ +#define PORT_EN 0x0001 /* PPI Port Enable */ +#define PORT_DIR 0x0002 /* PPI Port Direction */ +#define XFR_TYPE 0x000C /* PPI Transfer Type */ +#define PORT_CFG 0x0030 /* PPI Port Configuration */ +#define FLD_SEL 0x0040 /* PPI Active Field Select */ +#define PACK_EN 0x0080 /* PPI Packing Mode */ +/* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */ +#define SKIP_EN 0x0200 /* PPI Skip Element Enable */ +#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ +#define DLENGTH 0x3800 /* PPI Data Length */ +#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ +#define DLEN_10 0x0800 /* Data Length = 10 Bits */ +#define DLEN_11 0x1000 /* Data Length = 11 Bits */ +#define DLEN_12 0x1800 /* Data Length = 12 Bits */ +#define DLEN_13 0x2000 /* Data Length = 13 Bits */ +#define DLEN_14 0x2800 /* Data Length = 14 Bits */ +#define DLEN_15 0x3000 /* Data Length = 15 Bits */ +#define DLEN_16 0x3800 /* Data Length = 16 Bits */ +#ifdef _MISRA_RULES +#define DLEN(x) ((((x)-9u) & 0x07u) << 11) /* PPI Data Length (only works for x=10-->x=16) */ +#else +#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ +#endif /* _MISRA_RULES */ +#define POL 0xC000 /* PPI Signal Polarities */ +#define POLC 0x4000 /* PPI Clock Polarity */ +#define POLS 0x8000 /* PPI Frame Sync Polarity */ + + +/* PPI_STATUS Masks */ +#define FLD 0x0400 /* Field Indicator */ +#define FT_ERR 0x0800 /* Frame Track Error */ +#define OVR 0x1000 /* FIFO Overflow Error */ +#define UNDR 0x2000 /* FIFO Underrun Error */ +#define ERR_DET 0x4000 /* Error Detected Indicator */ +#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ + + +/* ********** DMA CONTROLLER MASKS ***********************/ + +/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ + +#define CTYPE 0x0040 /* DMA Channel Type Indicator */ +#define CTYPE_P 0x6 /* DMA Channel Type Indicator BIT POSITION */ +#define PCAP8 0x0080 /* DMA 8-bit Operation Indicator */ +#define PCAP16 0x0100 /* DMA 16-bit Operation Indicator */ +#define PCAP32 0x0200 /* DMA 32-bit Operation Indicator */ +#define PCAPWR 0x0400 /* DMA Write Operation Indicator */ +#define PCAPRD 0x0800 /* DMA Read Operation Indicator */ +#define PMAP 0xF000 /* DMA Peripheral Map Field */ + +/* PMAP Encodings For DMA Controller 0 */ +#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */ +#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */ +#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */ +#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */ +#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */ +#define PMAP_SPI0 0x5000 /* PMAP SPI DMA */ +#define PMAP_UART0RX 0x6000 /* PMAP UART Receive DMA */ +#define PMAP_UART0TX 0x7000 /* PMAP UART Transmit DMA */ + +/* PMAP Encodings For DMA Controller 1 */ +#define PMAP_SPORT2RX 0x0000 /* PMAP SPORT2 Receive DMA */ +#define PMAP_SPORT2TX 0x1000 /* PMAP SPORT2 Transmit DMA */ +#define PMAP_SPORT3RX 0x2000 /* PMAP SPORT3 Receive DMA */ +#define PMAP_SPORT3TX 0x3000 /* PMAP SPORT3 Transmit DMA */ +#define PMAP_SPI1 0x6000 /* PMAP SPI1 DMA */ +#define PMAP_SPI2 0x7000 /* PMAP SPI2 DMA */ +#define PMAP_UART1RX 0x8000 /* PMAP UART1 Receive DMA */ +#define PMAP_UART1TX 0x9000 /* PMAP UART1 Transmit DMA */ +#define PMAP_UART2RX 0xA000 /* PMAP UART2 Receive DMA */ +#define PMAP_UART2TX 0xB000 /* PMAP UART2 Transmit DMA */ + + +/* ************* GENERAL PURPOSE TIMER MASKS ******************** */ +/* PWM Timer bit definitions */ +/* TIMER_ENABLE Register */ +#define TIMEN0 0x0001 /* Enable Timer 0 */ +#define TIMEN1 0x0002 /* Enable Timer 1 */ +#define TIMEN2 0x0004 /* Enable Timer 2 */ + +#define TIMEN0_P 0x00 +#define TIMEN1_P 0x01 +#define TIMEN2_P 0x02 + +/* TIMER_DISABLE Register */ +#define TIMDIS0 0x0001 /* Disable Timer 0 */ +#define TIMDIS1 0x0002 /* Disable Timer 1 */ +#define TIMDIS2 0x0004 /* Disable Timer 2 */ + +#define TIMDIS0_P 0x00 +#define TIMDIS1_P 0x01 +#define TIMDIS2_P 0x02 + +/* TIMER_STATUS Register */ +#define TIMIL0 0x0001 /* Timer 0 Interrupt */ +#define TIMIL1 0x0002 /* Timer 1 Interrupt */ +#define TIMIL2 0x0004 /* Timer 2 Interrupt */ +#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */ +#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */ +#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */ +#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */ +#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */ +#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */ + +#define TIMIL0_P 0x00 +#define TIMIL1_P 0x01 +#define TIMIL2_P 0x02 +#define TOVF_ERR0_P 0x04 +#define TOVF_ERR1_P 0x05 +#define TOVF_ERR2_P 0x06 +#define TRUN0_P 0x0C +#define TRUN1_P 0x0D +#define TRUN2_P 0x0E + +/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ +#define TOVL_ERR0 TOVF_ERR0 +#define TOVL_ERR1 TOVF_ERR1 +#define TOVL_ERR2 TOVF_ERR2 +#define TOVL_ERR0_P TOVF_ERR0_P +#define TOVL_ERR1_P TOVF_ERR1_P +#define TOVL_ERR2_P TOVF_ERR2_P + +/* TIMERx_CONFIG Registers */ +#define PWM_OUT 0x0001 +#define WDTH_CAP 0x0002 +#define EXT_CLK 0x0003 +#define PULSE_HI 0x0004 +#define PERIOD_CNT 0x0008 +#define IRQ_ENA 0x0010 +#define TIN_SEL 0x0020 +#define OUT_DIS 0x0040 +#define CLK_SEL 0x0080 +#define TOGGLE_HI 0x0100 +#define EMU_RUN 0x0200 +#ifdef _MISRA_RULES +#define ERR_TYP(x) (((x) & 0x03u) << 14) +#else +#define ERR_TYP(x) (((x) & 0x03) << 14) +#endif /* _MISRA_RULES */ + +#define TMODE_P0 0x00 +#define TMODE_P1 0x01 +#define PULSE_HI_P 0x02 +#define PERIOD_CNT_P 0x03 +#define IRQ_ENA_P 0x04 +#define TIN_SEL_P 0x05 +#define OUT_DIS_P 0x06 +#define CLK_SEL_P 0x07 +#define TOGGLE_HI_P 0x08 +#define EMU_RUN_P 0x09 +#define ERR_TYP_P0 0x0E +#define ERR_TYP_P1 0x0F + +/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ +/* EBIU_AMGCTL Masks */ +#define AMCKEN 0x0001 /* Enable CLKOUT */ +#define AMBEN_NONE 0x0000 /* All Banks Disabled */ +#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */ +#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */ +#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ +#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ +#define CDPRIO 0x0100 /* DMA has priority over core for external accesses */ + +/* EBIU_AMGCTL Bit Positions */ +#define AMCKEN_P 0x0000 /* Enable CLKOUT */ +#define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ +#define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ +#define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ + +/* EBIU_AMBCTL0 Masks */ +#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ +#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ +#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ +#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ +#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ +#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ +#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ +#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ +#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ +#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ +#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ +#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ +#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ +#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ +#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ +#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ +#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ +#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ +#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ +#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ +#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ +#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ +#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ +#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ +#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ +#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ +#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ +#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ +#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ +#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ +#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ +#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ +#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ +#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ +#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ +#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ +#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ +#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ +#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ +#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ +#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ +#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ +#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ +#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ +#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ +#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ +#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ +#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ +#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ +#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ +#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ +#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ +#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ +#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ +#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ +#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ +#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ +#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ +#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ +#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ +#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ +#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ +#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ +#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ +#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ +#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ +#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ +#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ +#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ +#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ +#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ +#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ +#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ +#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ +#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ +#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ +#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ +#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ +#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ +#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ +#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ +#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ +#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ +#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ +#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ +#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ +#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ +#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ + +/* EBIU_AMBCTL1 Masks */ +#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ +#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ +#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ +#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ +#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ +#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ +#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ +#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ +#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ +#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ +#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ +#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ +#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ +#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ +#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ +#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ +#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ +#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ +#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ +#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ +#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ +#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ +#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ +#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ +#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ +#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ +#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ +#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ +#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ +#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ +#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ +#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ +#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ +#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ +#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ +#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ +#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ +#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ +#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ +#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ +#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ +#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ +#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ +#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ +#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ +#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ +#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ +#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ +#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ +#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ +#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ +#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ +#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ +#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ +#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ +#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ +#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ +#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ +#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ +#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ +#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ +#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ +#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ +#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ +#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ +#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ +#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ +#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ +#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ +#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ +#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ +#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ +#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ +#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ +#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ +#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ +#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ +#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ +#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ +#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ +#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ +#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ +#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ +#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ +#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ +#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ +#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ +#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ + +/* ********************** SDRAM CONTROLLER MASKS *************************** */ +/* EBIU_SDGCTL Masks */ +#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ +#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ +#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ +#define PFE 0x00000010 /* Enable SDRAM prefetch */ +#define PFP 0x00000020 /* Prefetch has priority over AMC requests */ +#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ +#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ +#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ +#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ +#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ +#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ +#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ +#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ +#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ +#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ +#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ +#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ +#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ +#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ +#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ +#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ +#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ +#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ +#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ +#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ +#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ +#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ +#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ +#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ +#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ +#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ +#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ +#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ +#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ +#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ +#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ +#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ +#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ +#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ +#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ +#define PUPSD 0x00200000 /*Power-up start delay */ +#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ +#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ +#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ +#define EBUFE 0x02000000 /* Enable external buffering timing */ +#define FBBRW 0x04000000 /* Fast back-to-back read write enable */ +#define EMREN 0x10000000 /* Extended mode register enable */ +#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ +#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ + +/* EBIU_SDBCTL Masks */ +#define EBE 0x00000001 /* Enable SDRAM external bank */ +#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */ +#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */ +#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */ +#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */ +#define EBSZ_256 0x00000008 /* SDRAM External Bank Size = 256MB */ +#define EBSZ_512 0x0000000A /* SDRAM External Bank Size = 512MB */ +#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ +#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ +#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ +#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ + +/* EBIU_SDSTAT Masks */ +#define SDCI 0x00000001 /* SDRAM controller is idle */ +#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ +#define SDPUA 0x00000004 /* SDRAM power up active */ +#define SDRS 0x00000008 /* SDRAM is in reset state */ +#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ +#define BGSTAT 0x00000020 /* Bus granted */ + + +/* ******************** TWO-WIRE INTERFACE (TWIx) MASKS ***********************/ +/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ +#ifdef _MISRA_RULES +#define CLKLOW(x) ((x) & 0xFFu) /* Periods Clock Is Held Low */ +#define CLKHI(y) (((y)&0xFFu)<<0x8) /* Periods Before New Clock Low */ +#else +#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ +#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ +#endif /* _MISRA_RULES */ + +/* TWIx_PRESCALE Masks */ +#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ +#define TWI_ENA 0x0080 /* TWI Enable */ +#define SCCB 0x0200 /* SCCB Compatibility Enable */ + +/* TWIx_SLAVE_CTRL Masks */ +#define SEN 0x0001 /* Slave Enable */ +#define SADD_LEN 0x0002 /* Slave Address Length */ +#define STDVAL 0x0004 /* Slave Transmit Data Valid */ +#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ +#define GEN 0x0010 /* General Call Adrress Matching Enabled */ + +/* TWIx_SLAVE_STAT Masks */ +#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ +#define GCALL 0x0002 /* General Call Indicator */ + +/* TWIx_MASTER_CTRL Masks */ +#define MEN 0x0001 /* Master Mode Enable */ +#define MADD_LEN 0x0002 /* Master Address Length */ +#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ +#define FAST 0x0008 /* Use Fast Mode Timing Specs */ +#define STOP 0x0010 /* Issue Stop Condition */ +#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ +#define DCNT 0x3FC0 /* Data Bytes To Transfer */ +#define SDAOVR 0x4000 /* Serial Data Override */ +#define SCLOVR 0x8000 /* Serial Clock Override */ + +/* TWIx_MASTER_STAT Masks */ +#define MPROG 0x0001 /* Master Transfer In Progress */ +#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ +#define ANAK 0x0004 /* Address Not Acknowledged */ +#define DNAK 0x0008 /* Data Not Acknowledged */ +#define BUFRDERR 0x0010 /* Buffer Read Error */ +#define BUFWRERR 0x0020 /* Buffer Write Error */ +#define SDASEN 0x0040 /* Serial Data Sense */ +#define SCLSEN 0x0080 /* Serial Clock Sense */ +#define BUSBUSY 0x0100 /* Bus Busy Indicator */ + +/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */ +#define SINIT 0x0001 /* Slave Transfer Initiated */ +#define SCOMP 0x0002 /* Slave Transfer Complete */ +#define SERR 0x0004 /* Slave Transfer Error */ +#define SOVF 0x0008 /* Slave Overflow */ +#define MCOMP 0x0010 /* Master Transfer Complete */ +#define MERR 0x0020 /* Master Transfer Error */ +#define XMTSERV 0x0040 /* Transmit FIFO Service */ +#define RCVSERV 0x0080 /* Receive FIFO Service */ + +/* TWIx_FIFO_CTL Masks */ +#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ +#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ +#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ +#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ + +/* TWIx_FIFO_STAT Masks */ +#define XMTSTAT 0x0003 /* Transmit FIFO Status */ +#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ +#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ +#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ + +#define RCVSTAT 0x000C /* Receive FIFO Status */ +#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ +#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ +#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ + +#endif diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h index 7a8ac5f4420..8100bcd01a0 100644 --- a/arch/blackfin/mach-bf538/include/mach/defBF539.h +++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h @@ -1,859 +1,13 @@ /* - * Copyright 2008-2009 Analog Devices Inc. + * Copyright 2008-2010 Analog Devices Inc. * * Licensed under the ADI BSD license or the GPL-2 (or later) */ -/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF538/9 */ - #ifndef _DEF_BF539_H #define _DEF_BF539_H -/* include all Core registers and bit definitions */ -#include <asm/def_LPBlackfin.h> - - -/*********************************************************************************** */ -/* System MMR Register Map */ -/*********************************************************************************** */ -/* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */ -#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ -#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ -#define CHIPID 0xFFC00014 /* Chip ID Register */ - -/* CHIPID Masks */ -#define CHIPID_VERSION 0xF0000000 -#define CHIPID_FAMILY 0x0FFFF000 -#define CHIPID_MANUFACTURE 0x00000FFE - -/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ -#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ -#define SYSCR 0xFFC00104 /* System Configuration registe */ -#define SIC_RVECT 0xFFC00108 -#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ -#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ -#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ -#define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */ -#define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */ -#define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */ -#define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */ -#define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */ -#define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */ - - -/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ - - -/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ -#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ - - -/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ -#define UART0_THR 0xFFC00400 /* Transmit Holding register */ -#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART0_LCR 0xFFC0040C /* Line Control Register */ -#define UART0_MCR 0xFFC00410 /* Modem Control Register */ -#define UART0_LSR 0xFFC00414 /* Line Status Register */ -#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART0_GCTL 0xFFC00424 /* Global Control Register */ - - -/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */ - -#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */ -#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */ -#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */ -#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */ -#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */ -#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */ -#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */ -#define SPI0_REGBASE SPI0_CTL - - -/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ -#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ - -#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ - -#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ - -#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ -#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ -#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ - - -/* Programmable Flags (0xFFC00700 - 0xFFC007FF) */ -#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ -#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ -#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ -#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ -#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ -#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ -#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ -#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ -#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ -#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ -#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ -#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ -#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ -#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ -#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ -#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ -#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ - - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ - - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ - - -/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -/* Asynchronous Memory Controller */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ - -/* SDRAM Controller */ -#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ -#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ -#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ -#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ - - - -/* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */ - -#define DMAC0_TC_PER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */ -#define DMAC0_TC_CNT 0xFFC00B10 /* DMA Controller 0 Traffic Control Current Counts Register */ - -/* Alternate deprecated register names (below) provided for backwards code compatibility */ -#define DMA0_TCPER DMAC0_TC_PER -#define DMA0_TCCNT DMAC0_TC_CNT - - -/* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF) */ - -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ - -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ - -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ - -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ - -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ - -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ - -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ - -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ - -#define MDMA0_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA0_D0_START_ADDR 0xFFC00E04 /* MemDMA0 Stream 0 Destination Start Address Register */ -#define MDMA0_D0_CONFIG 0xFFC00E08 /* MemDMA0 Stream 0 Destination Configuration Register */ -#define MDMA0_D0_X_COUNT 0xFFC00E10 /* MemDMA0 Stream 0 Destination X Count Register */ -#define MDMA0_D0_X_MODIFY 0xFFC00E14 /* MemDMA0 Stream 0 Destination X Modify Register */ -#define MDMA0_D0_Y_COUNT 0xFFC00E18 /* MemDMA0 Stream 0 Destination Y Count Register */ -#define MDMA0_D0_Y_MODIFY 0xFFC00E1C /* MemDMA0 Stream 0 Destination Y Modify Register */ -#define MDMA0_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA0_D0_CURR_ADDR 0xFFC00E24 /* MemDMA0 Stream 0 Destination Current Address Register */ -#define MDMA0_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA0 Stream 0 Destination Interrupt/Status Register */ -#define MDMA0_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA0 Stream 0 Destination Peripheral Map Register */ -#define MDMA0_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA0 Stream 0 Destination Current X Count Register */ -#define MDMA0_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA0 Stream 0 Destination Current Y Count Register */ - -#define MDMA0_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA0_S0_START_ADDR 0xFFC00E44 /* MemDMA0 Stream 0 Source Start Address Register */ -#define MDMA0_S0_CONFIG 0xFFC00E48 /* MemDMA0 Stream 0 Source Configuration Register */ -#define MDMA0_S0_X_COUNT 0xFFC00E50 /* MemDMA0 Stream 0 Source X Count Register */ -#define MDMA0_S0_X_MODIFY 0xFFC00E54 /* MemDMA0 Stream 0 Source X Modify Register */ -#define MDMA0_S0_Y_COUNT 0xFFC00E58 /* MemDMA0 Stream 0 Source Y Count Register */ -#define MDMA0_S0_Y_MODIFY 0xFFC00E5C /* MemDMA0 Stream 0 Source Y Modify Register */ -#define MDMA0_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA0_S0_CURR_ADDR 0xFFC00E64 /* MemDMA0 Stream 0 Source Current Address Register */ -#define MDMA0_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA0 Stream 0 Source Interrupt/Status Register */ -#define MDMA0_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA0 Stream 0 Source Peripheral Map Register */ -#define MDMA0_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA0 Stream 0 Source Current X Count Register */ -#define MDMA0_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA0 Stream 0 Source Current Y Count Register */ - -#define MDMA0_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA0_D1_START_ADDR 0xFFC00E84 /* MemDMA0 Stream 1 Destination Start Address Register */ -#define MDMA0_D1_CONFIG 0xFFC00E88 /* MemDMA0 Stream 1 Destination Configuration Register */ -#define MDMA0_D1_X_COUNT 0xFFC00E90 /* MemDMA0 Stream 1 Destination X Count Register */ -#define MDMA0_D1_X_MODIFY 0xFFC00E94 /* MemDMA0 Stream 1 Destination X Modify Register */ -#define MDMA0_D1_Y_COUNT 0xFFC00E98 /* MemDMA0 Stream 1 Destination Y Count Register */ -#define MDMA0_D1_Y_MODIFY 0xFFC00E9C /* MemDMA0 Stream 1 Destination Y Modify Register */ -#define MDMA0_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA0_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA0 Stream 1 Destination Current Address Register */ -#define MDMA0_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA0 Stream 1 Destination Interrupt/Status Register */ -#define MDMA0_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA0 Stream 1 Destination Peripheral Map Register */ -#define MDMA0_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA0 Stream 1 Destination Current X Count Register */ -#define MDMA0_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA0 Stream 1 Destination Current Y Count Register */ - -#define MDMA0_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA0_S1_START_ADDR 0xFFC00EC4 /* MemDMA0 Stream 1 Source Start Address Register */ -#define MDMA0_S1_CONFIG 0xFFC00EC8 /* MemDMA0 Stream 1 Source Configuration Register */ -#define MDMA0_S1_X_COUNT 0xFFC00ED0 /* MemDMA0 Stream 1 Source X Count Register */ -#define MDMA0_S1_X_MODIFY 0xFFC00ED4 /* MemDMA0 Stream 1 Source X Modify Register */ -#define MDMA0_S1_Y_COUNT 0xFFC00ED8 /* MemDMA0 Stream 1 Source Y Count Register */ -#define MDMA0_S1_Y_MODIFY 0xFFC00EDC /* MemDMA0 Stream 1 Source Y Modify Register */ -#define MDMA0_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA0_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA0 Stream 1 Source Current Address Register */ -#define MDMA0_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA0 Stream 1 Source Interrupt/Status Register */ -#define MDMA0_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA0 Stream 1 Source Peripheral Map Register */ -#define MDMA0_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */ -#define MDMA0_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */ - -#define MDMA_D0_NEXT_DESC_PTR MDMA0_D0_NEXT_DESC_PTR -#define MDMA_D0_START_ADDR MDMA0_D0_START_ADDR -#define MDMA_D0_CONFIG MDMA0_D0_CONFIG -#define MDMA_D0_X_COUNT MDMA0_D0_X_COUNT -#define MDMA_D0_X_MODIFY MDMA0_D0_X_MODIFY -#define MDMA_D0_Y_COUNT MDMA0_D0_Y_COUNT -#define MDMA_D0_Y_MODIFY MDMA0_D0_Y_MODIFY -#define MDMA_D0_CURR_DESC_PTR MDMA0_D0_CURR_DESC_PTR -#define MDMA_D0_CURR_ADDR MDMA0_D0_CURR_ADDR -#define MDMA_D0_IRQ_STATUS MDMA0_D0_IRQ_STATUS -#define MDMA_D0_PERIPHERAL_MAP MDMA0_D0_PERIPHERAL_MAP -#define MDMA_D0_CURR_X_COUNT MDMA0_D0_CURR_X_COUNT -#define MDMA_D0_CURR_Y_COUNT MDMA0_D0_CURR_Y_COUNT - -#define MDMA_S0_NEXT_DESC_PTR MDMA0_S0_NEXT_DESC_PTR -#define MDMA_S0_START_ADDR MDMA0_S0_START_ADDR -#define MDMA_S0_CONFIG MDMA0_S0_CONFIG -#define MDMA_S0_X_COUNT MDMA0_S0_X_COUNT -#define MDMA_S0_X_MODIFY MDMA0_S0_X_MODIFY -#define MDMA_S0_Y_COUNT MDMA0_S0_Y_COUNT -#define MDMA_S0_Y_MODIFY MDMA0_S0_Y_MODIFY -#define MDMA_S0_CURR_DESC_PTR MDMA0_S0_CURR_DESC_PTR -#define MDMA_S0_CURR_ADDR MDMA0_S0_CURR_ADDR -#define MDMA_S0_IRQ_STATUS MDMA0_S0_IRQ_STATUS -#define MDMA_S0_PERIPHERAL_MAP MDMA0_S0_PERIPHERAL_MAP -#define MDMA_S0_CURR_X_COUNT MDMA0_S0_CURR_X_COUNT -#define MDMA_S0_CURR_Y_COUNT MDMA0_S0_CURR_Y_COUNT - -#define MDMA_D1_NEXT_DESC_PTR MDMA0_D1_NEXT_DESC_PTR -#define MDMA_D1_START_ADDR MDMA0_D1_START_ADDR -#define MDMA_D1_CONFIG MDMA0_D1_CONFIG -#define MDMA_D1_X_COUNT MDMA0_D1_X_COUNT -#define MDMA_D1_X_MODIFY MDMA0_D1_X_MODIFY -#define MDMA_D1_Y_COUNT MDMA0_D1_Y_COUNT -#define MDMA_D1_Y_MODIFY MDMA0_D1_Y_MODIFY -#define MDMA_D1_CURR_DESC_PTR MDMA0_D1_CURR_DESC_PTR -#define MDMA_D1_CURR_ADDR MDMA0_D1_CURR_ADDR -#define MDMA_D1_IRQ_STATUS MDMA0_D1_IRQ_STATUS -#define MDMA_D1_PERIPHERAL_MAP MDMA0_D1_PERIPHERAL_MAP -#define MDMA_D1_CURR_X_COUNT MDMA0_D1_CURR_X_COUNT -#define MDMA_D1_CURR_Y_COUNT MDMA0_D1_CURR_Y_COUNT - -#define MDMA_S1_NEXT_DESC_PTR MDMA0_S1_NEXT_DESC_PTR -#define MDMA_S1_START_ADDR MDMA0_S1_START_ADDR -#define MDMA_S1_CONFIG MDMA0_S1_CONFIG -#define MDMA_S1_X_COUNT MDMA0_S1_X_COUNT -#define MDMA_S1_X_MODIFY MDMA0_S1_X_MODIFY -#define MDMA_S1_Y_COUNT MDMA0_S1_Y_COUNT -#define MDMA_S1_Y_MODIFY MDMA0_S1_Y_MODIFY -#define MDMA_S1_CURR_DESC_PTR MDMA0_S1_CURR_DESC_PTR -#define MDMA_S1_CURR_ADDR MDMA0_S1_CURR_ADDR -#define MDMA_S1_IRQ_STATUS MDMA0_S1_IRQ_STATUS -#define MDMA_S1_PERIPHERAL_MAP MDMA0_S1_PERIPHERAL_MAP -#define MDMA_S1_CURR_X_COUNT MDMA0_S1_CURR_X_COUNT -#define MDMA_S1_CURR_Y_COUNT MDMA0_S1_CURR_Y_COUNT - - -/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ -#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ -#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ -#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ -#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ -#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ - - -/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */ -#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ -#define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */ -#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ -#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ -#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ -#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ -#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ -#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ -#define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */ -#define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */ -#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ -#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ -#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ -#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ -#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ -#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ - -#define TWI0_REGBASE TWI0_CLKDIV - -/* the following are for backwards compatibility */ -#define TWI0_PRESCALE TWI0_CONTROL -#define TWI0_INT_SRC TWI0_INT_STAT -#define TWI0_INT_ENABLE TWI0_INT_MASK - - -/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */ - -/* GPIO Port C Register Names */ -#define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */ -#define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */ -#define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */ -#define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */ -#define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */ -#define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */ -#define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */ - -/* GPIO Port D Register Names */ -#define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */ -#define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */ -#define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */ -#define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */ -#define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */ -#define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */ -#define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */ - -/* GPIO Port E Register Names */ -#define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */ -#define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */ -#define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */ -#define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */ -#define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */ -#define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */ -#define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */ - -/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */ - -#define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */ -#define DMAC1_TC_CNT 0xFFC01B10 /* DMA Controller 1 Traffic Control Current Counts Register */ - -/* Alternate deprecated register names (below) provided for backwards code compatibility */ -#define DMA1_TCPER DMAC1_TC_PER -#define DMA1_TCCNT DMAC1_TC_CNT - - -/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */ -#define DMA8_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 8 Next Descriptor Pointer Register */ -#define DMA8_START_ADDR 0xFFC01C04 /* DMA Channel 8 Start Address Register */ -#define DMA8_CONFIG 0xFFC01C08 /* DMA Channel 8 Configuration Register */ -#define DMA8_X_COUNT 0xFFC01C10 /* DMA Channel 8 X Count Register */ -#define DMA8_X_MODIFY 0xFFC01C14 /* DMA Channel 8 X Modify Register */ -#define DMA8_Y_COUNT 0xFFC01C18 /* DMA Channel 8 Y Count Register */ -#define DMA8_Y_MODIFY 0xFFC01C1C /* DMA Channel 8 Y Modify Register */ -#define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */ -#define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */ -#define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */ -#define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */ -#define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */ -#define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */ - -#define DMA9_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 9 Next Descriptor Pointer Register */ -#define DMA9_START_ADDR 0xFFC01C44 /* DMA Channel 9 Start Address Register */ -#define DMA9_CONFIG 0xFFC01C48 /* DMA Channel 9 Configuration Register */ -#define DMA9_X_COUNT 0xFFC01C50 /* DMA Channel 9 X Count Register */ -#define DMA9_X_MODIFY 0xFFC01C54 /* DMA Channel 9 X Modify Register */ -#define DMA9_Y_COUNT 0xFFC01C58 /* DMA Channel 9 Y Count Register */ -#define DMA9_Y_MODIFY 0xFFC01C5C /* DMA Channel 9 Y Modify Register */ -#define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */ -#define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */ -#define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */ -#define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */ -#define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */ -#define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */ - -#define DMA10_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 10 Next Descriptor Pointer Register */ -#define DMA10_START_ADDR 0xFFC01C84 /* DMA Channel 10 Start Address Register */ -#define DMA10_CONFIG 0xFFC01C88 /* DMA Channel 10 Configuration Register */ -#define DMA10_X_COUNT 0xFFC01C90 /* DMA Channel 10 X Count Register */ -#define DMA10_X_MODIFY 0xFFC01C94 /* DMA Channel 10 X Modify Register */ -#define DMA10_Y_COUNT 0xFFC01C98 /* DMA Channel 10 Y Count Register */ -#define DMA10_Y_MODIFY 0xFFC01C9C /* DMA Channel 10 Y Modify Register */ -#define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */ -#define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */ -#define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */ -#define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */ -#define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */ -#define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */ - -#define DMA11_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 11 Next Descriptor Pointer Register */ -#define DMA11_START_ADDR 0xFFC01CC4 /* DMA Channel 11 Start Address Register */ -#define DMA11_CONFIG 0xFFC01CC8 /* DMA Channel 11 Configuration Register */ -#define DMA11_X_COUNT 0xFFC01CD0 /* DMA Channel 11 X Count Register */ -#define DMA11_X_MODIFY 0xFFC01CD4 /* DMA Channel 11 X Modify Register */ -#define DMA11_Y_COUNT 0xFFC01CD8 /* DMA Channel 11 Y Count Register */ -#define DMA11_Y_MODIFY 0xFFC01CDC /* DMA Channel 11 Y Modify Register */ -#define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */ -#define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */ -#define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */ -#define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */ -#define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */ -#define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */ - -#define DMA12_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 12 Next Descriptor Pointer Register */ -#define DMA12_START_ADDR 0xFFC01D04 /* DMA Channel 12 Start Address Register */ -#define DMA12_CONFIG 0xFFC01D08 /* DMA Channel 12 Configuration Register */ -#define DMA12_X_COUNT 0xFFC01D10 /* DMA Channel 12 X Count Register */ -#define DMA12_X_MODIFY 0xFFC01D14 /* DMA Channel 12 X Modify Register */ -#define DMA12_Y_COUNT 0xFFC01D18 /* DMA Channel 12 Y Count Register */ -#define DMA12_Y_MODIFY 0xFFC01D1C /* DMA Channel 12 Y Modify Register */ -#define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */ -#define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */ -#define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */ -#define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */ -#define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */ -#define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */ - -#define DMA13_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 13 Next Descriptor Pointer Register */ -#define DMA13_START_ADDR 0xFFC01D44 /* DMA Channel 13 Start Address Register */ -#define DMA13_CONFIG 0xFFC01D48 /* DMA Channel 13 Configuration Register */ -#define DMA13_X_COUNT 0xFFC01D50 /* DMA Channel 13 X Count Register */ -#define DMA13_X_MODIFY 0xFFC01D54 /* DMA Channel 13 X Modify Register */ -#define DMA13_Y_COUNT 0xFFC01D58 /* DMA Channel 13 Y Count Register */ -#define DMA13_Y_MODIFY 0xFFC01D5C /* DMA Channel 13 Y Modify Register */ -#define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */ -#define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */ -#define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */ -#define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */ -#define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */ -#define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */ - -#define DMA14_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 14 Next Descriptor Pointer Register */ -#define DMA14_START_ADDR 0xFFC01D84 /* DMA Channel 14 Start Address Register */ -#define DMA14_CONFIG 0xFFC01D88 /* DMA Channel 14 Configuration Register */ -#define DMA14_X_COUNT 0xFFC01D90 /* DMA Channel 14 X Count Register */ -#define DMA14_X_MODIFY 0xFFC01D94 /* DMA Channel 14 X Modify Register */ -#define DMA14_Y_COUNT 0xFFC01D98 /* DMA Channel 14 Y Count Register */ -#define DMA14_Y_MODIFY 0xFFC01D9C /* DMA Channel 14 Y Modify Register */ -#define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */ -#define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */ -#define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */ -#define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */ -#define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */ -#define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */ - -#define DMA15_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 15 Next Descriptor Pointer Register */ -#define DMA15_START_ADDR 0xFFC01DC4 /* DMA Channel 15 Start Address Register */ -#define DMA15_CONFIG 0xFFC01DC8 /* DMA Channel 15 Configuration Register */ -#define DMA15_X_COUNT 0xFFC01DD0 /* DMA Channel 15 X Count Register */ -#define DMA15_X_MODIFY 0xFFC01DD4 /* DMA Channel 15 X Modify Register */ -#define DMA15_Y_COUNT 0xFFC01DD8 /* DMA Channel 15 Y Count Register */ -#define DMA15_Y_MODIFY 0xFFC01DDC /* DMA Channel 15 Y Modify Register */ -#define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */ -#define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */ -#define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */ -#define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */ -#define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */ -#define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */ - -#define DMA16_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 16 Next Descriptor Pointer Register */ -#define DMA16_START_ADDR 0xFFC01E04 /* DMA Channel 16 Start Address Register */ -#define DMA16_CONFIG 0xFFC01E08 /* DMA Channel 16 Configuration Register */ -#define DMA16_X_COUNT 0xFFC01E10 /* DMA Channel 16 X Count Register */ -#define DMA16_X_MODIFY 0xFFC01E14 /* DMA Channel 16 X Modify Register */ -#define DMA16_Y_COUNT 0xFFC01E18 /* DMA Channel 16 Y Count Register */ -#define DMA16_Y_MODIFY 0xFFC01E1C /* DMA Channel 16 Y Modify Register */ -#define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */ -#define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */ -#define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */ -#define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */ -#define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */ -#define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */ - -#define DMA17_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 17 Next Descriptor Pointer Register */ -#define DMA17_START_ADDR 0xFFC01E44 /* DMA Channel 17 Start Address Register */ -#define DMA17_CONFIG 0xFFC01E48 /* DMA Channel 17 Configuration Register */ -#define DMA17_X_COUNT 0xFFC01E50 /* DMA Channel 17 X Count Register */ -#define DMA17_X_MODIFY 0xFFC01E54 /* DMA Channel 17 X Modify Register */ -#define DMA17_Y_COUNT 0xFFC01E58 /* DMA Channel 17 Y Count Register */ -#define DMA17_Y_MODIFY 0xFFC01E5C /* DMA Channel 17 Y Modify Register */ -#define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */ -#define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */ -#define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */ -#define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */ -#define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */ -#define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */ - -#define DMA18_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 18 Next Descriptor Pointer Register */ -#define DMA18_START_ADDR 0xFFC01E84 /* DMA Channel 18 Start Address Register */ -#define DMA18_CONFIG 0xFFC01E88 /* DMA Channel 18 Configuration Register */ -#define DMA18_X_COUNT 0xFFC01E90 /* DMA Channel 18 X Count Register */ -#define DMA18_X_MODIFY 0xFFC01E94 /* DMA Channel 18 X Modify Register */ -#define DMA18_Y_COUNT 0xFFC01E98 /* DMA Channel 18 Y Count Register */ -#define DMA18_Y_MODIFY 0xFFC01E9C /* DMA Channel 18 Y Modify Register */ -#define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */ -#define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */ -#define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */ -#define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */ -#define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */ -#define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */ - -#define DMA19_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 19 Next Descriptor Pointer Register */ -#define DMA19_START_ADDR 0xFFC01EC4 /* DMA Channel 19 Start Address Register */ -#define DMA19_CONFIG 0xFFC01EC8 /* DMA Channel 19 Configuration Register */ -#define DMA19_X_COUNT 0xFFC01ED0 /* DMA Channel 19 X Count Register */ -#define DMA19_X_MODIFY 0xFFC01ED4 /* DMA Channel 19 X Modify Register */ -#define DMA19_Y_COUNT 0xFFC01ED8 /* DMA Channel 19 Y Count Register */ -#define DMA19_Y_MODIFY 0xFFC01EDC /* DMA Channel 19 Y Modify Register */ -#define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */ -#define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */ -#define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */ -#define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */ -#define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */ -#define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */ - -#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA1_D0_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address Register */ -#define MDMA1_D0_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration Register */ -#define MDMA1_D0_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination X Count Register */ -#define MDMA1_D0_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Destination X Modify Register */ -#define MDMA1_D0_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Y Count Register */ -#define MDMA1_D0_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Destination Y Modify Register */ -#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA1_D0_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address Register */ -#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */ -#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map Register */ -#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Destination Current X Count Register */ -#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Destination Current Y Count Register */ - -#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA1_S0_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address Register */ -#define MDMA1_S0_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration Register */ -#define MDMA1_S0_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source X Count Register */ -#define MDMA1_S0_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source X Modify Register */ -#define MDMA1_S0_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Y Count Register */ -#define MDMA1_S0_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Y Modify Register */ -#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA1_S0_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address Register */ -#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status Register */ -#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map Register */ -#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current X Count Register */ -#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Y Count Register */ - -#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA1_D1_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address Register */ -#define MDMA1_D1_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration Register */ -#define MDMA1_D1_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination X Count Register */ -#define MDMA1_D1_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Destination X Modify Register */ -#define MDMA1_D1_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Y Count Register */ -#define MDMA1_D1_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Destination Y Modify Register */ -#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Destination Current Address Register */ -#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Destination Interrupt/Status Register */ -#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Destination Peripheral Map Register */ -#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Destination Current X Count Register */ -#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Destination Current Y Count Register */ - -#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA1_S1_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address Register */ -#define MDMA1_S1_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration Register */ -#define MDMA1_S1_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source X Count Register */ -#define MDMA1_S1_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source X Modify Register */ -#define MDMA1_S1_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Y Count Register */ -#define MDMA1_S1_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Y Modify Register */ -#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address Register */ -#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status Register */ -#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map Register */ -#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current X Count Register */ -#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Y Count Register */ - - -/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ -#define UART1_THR 0xFFC02000 /* Transmit Holding register */ -#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ -#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ -#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ -#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ -#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ -#define UART1_LCR 0xFFC0200C /* Line Control Register */ -#define UART1_MCR 0xFFC02010 /* Modem Control Register */ -#define UART1_LSR 0xFFC02014 /* Line Status Register */ -#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ -#define UART1_GCTL 0xFFC02024 /* Global Control Register */ - - -/* UART2 Controller (0xFFC02100 - 0xFFC021FF) */ -#define UART2_THR 0xFFC02100 /* Transmit Holding register */ -#define UART2_RBR 0xFFC02100 /* Receive Buffer register */ -#define UART2_DLL 0xFFC02100 /* Divisor Latch (Low-Byte) */ -#define UART2_IER 0xFFC02104 /* Interrupt Enable Register */ -#define UART2_DLH 0xFFC02104 /* Divisor Latch (High-Byte) */ -#define UART2_IIR 0xFFC02108 /* Interrupt Identification Register */ -#define UART2_LCR 0xFFC0210C /* Line Control Register */ -#define UART2_MCR 0xFFC02110 /* Modem Control Register */ -#define UART2_LSR 0xFFC02114 /* Line Status Register */ -#define UART2_SCR 0xFFC0211C /* SCR Scratch Register */ -#define UART2_GCTL 0xFFC02124 /* Global Control Register */ - - -/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */ -#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */ -#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */ -#define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */ -#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */ -#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */ -#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */ -#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */ -#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */ -#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */ -#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */ -#define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */ -#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */ -#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */ -#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */ -#define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */ -#define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */ -#define TWI1_REGBASE TWI1_CLKDIV - - -/* the following are for backwards compatibility */ -#define TWI1_PRESCALE TWI1_CONTROL -#define TWI1_INT_SRC TWI1_INT_STAT -#define TWI1_INT_ENABLE TWI1_INT_MASK - - -/* SPI1 Controller (0xFFC02300 - 0xFFC023FF) */ -#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */ -#define SPI1_FLG 0xFFC02304 /* SPI1 Flag register */ -#define SPI1_STAT 0xFFC02308 /* SPI1 Status register */ -#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */ -#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */ -#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud rate Register */ -#define SPI1_SHADOW 0xFFC02318 /* SPI1_RDBR Shadow Register */ -#define SPI1_REGBASE SPI1_CTL - -/* SPI2 Controller (0xFFC02400 - 0xFFC024FF) */ -#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */ -#define SPI2_FLG 0xFFC02404 /* SPI2 Flag register */ -#define SPI2_STAT 0xFFC02408 /* SPI2 Status register */ -#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */ -#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */ -#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud rate Register */ -#define SPI2_SHADOW 0xFFC02418 /* SPI2_RDBR Shadow Register */ -#define SPI2_REGBASE SPI2_CTL - -/* SPORT2 Controller (0xFFC02500 - 0xFFC025FF) */ -#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */ -#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */ -#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Clock Divider */ -#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider */ -#define SPORT2_TX 0xFFC02510 /* SPORT2 TX Data Register */ -#define SPORT2_RX 0xFFC02518 /* SPORT2 RX Data Register */ -#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Transmit Configuration 1 Register */ -#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Transmit Configuration 2 Register */ -#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */ -#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider */ -#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */ -#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */ -#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi-Channel Configuration Register 1 */ -#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi-Channel Configuration Register 2 */ -#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi-Channel Transmit Select Register 0 */ -#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi-Channel Transmit Select Register 1 */ -#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi-Channel Transmit Select Register 2 */ -#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi-Channel Transmit Select Register 3 */ -#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */ -#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi-Channel Receive Select Register 1 */ -#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi-Channel Receive Select Register 2 */ -#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi-Channel Receive Select Register 3 */ - - -/* SPORT3 Controller (0xFFC02600 - 0xFFC026FF) */ -#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */ -#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */ -#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Clock Divider */ -#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider */ -#define SPORT3_TX 0xFFC02610 /* SPORT3 TX Data Register */ -#define SPORT3_RX 0xFFC02618 /* SPORT3 RX Data Register */ -#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Transmit Configuration 1 Register */ -#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Transmit Configuration 2 Register */ -#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Clock Divider */ -#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider */ -#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */ -#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */ -#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi-Channel Configuration Register 1 */ -#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi-Channel Configuration Register 2 */ -#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi-Channel Transmit Select Register 0 */ -#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi-Channel Transmit Select Register 1 */ -#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi-Channel Transmit Select Register 2 */ -#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi-Channel Transmit Select Register 3 */ -#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */ -#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi-Channel Receive Select Register 1 */ -#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi-Channel Receive Select Register 2 */ -#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi-Channel Receive Select Register 3 */ - +#include "defBF538.h" /* Media Transceiver (MXVR) (0xFFC02700 - 0xFFC028FF) */ @@ -995,1249 +149,4 @@ #define MXVR_BLOCK_CNT 0xFFC028C0 /* MXVR Block Counter */ #define MXVR_PLL_CTL_2 0xFFC028C4 /* MXVR Phase Lock Loop Control Register 2 */ - -/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */ -/* For Mailboxes 0-15 */ -#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */ -#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */ -#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */ -#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */ -#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */ -#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */ -#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */ -#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */ -#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */ -#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */ -#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */ -#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */ -#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */ - -/* For Mailboxes 16-31 */ -#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */ -#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */ -#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */ -#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */ -#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */ -#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */ -#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */ -#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */ -#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */ -#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */ -#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */ -#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */ -#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */ - -#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */ -#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */ - -#define CAN_DEBUG 0xFFC02A88 /* Debug Register */ -/* the following is for backwards compatibility */ -#define CAN_CNF CAN_DEBUG - -#define CAN_STATUS 0xFFC02A8C /* Global Status Register */ -#define CAN_CEC 0xFFC02A90 /* Error Counter Register */ -#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */ -#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */ -#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ -#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ -#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ -#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ -#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ -#define CAN_ESR 0xFFC02AB4 /* Error Status Register */ -#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */ -#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Reload/Capture Register */ -#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */ - -/* Mailbox Acceptance Masks */ -#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */ -#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */ -#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */ -#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */ -#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */ -#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */ -#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */ -#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */ -#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */ -#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */ -#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */ -#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */ -#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */ -#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */ -#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */ -#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */ -#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */ -#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */ -#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */ -#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */ -#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */ -#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */ -#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */ -#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */ -#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */ -#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */ -#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */ -#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */ -#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */ -#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */ -#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */ -#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */ - -#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */ -#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */ -#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */ -#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */ -#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */ -#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */ -#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */ -#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */ -#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */ -#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */ -#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */ -#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */ -#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */ -#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */ -#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */ -#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */ -#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */ -#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */ -#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */ -#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */ -#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */ -#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */ -#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */ -#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */ -#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */ -#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */ -#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */ -#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */ -#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */ -#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */ -#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */ -#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */ - -/* CAN Acceptance Mask Macros */ -#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8)) -#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8)) - -/* Mailbox Registers */ -#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */ -#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */ -#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */ -#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */ -#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */ -#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */ -#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */ -#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */ - -#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */ -#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */ -#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */ -#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */ -#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */ -#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */ -#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */ -#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */ - -#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */ -#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */ -#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */ -#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */ -#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */ -#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */ -#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */ -#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */ - -#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */ -#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */ -#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */ -#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */ -#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */ -#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */ -#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */ -#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */ - -#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */ -#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */ -#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */ -#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */ -#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */ -#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */ -#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */ -#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */ - -#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */ -#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */ -#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */ -#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */ -#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */ -#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */ -#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */ -#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */ - -#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */ -#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */ -#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */ -#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */ -#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */ -#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */ -#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */ -#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */ - -#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */ -#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */ -#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */ -#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */ -#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */ -#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */ -#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */ -#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */ - -#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */ -#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */ -#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */ -#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */ -#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */ -#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */ -#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */ -#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */ - -#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */ -#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */ -#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */ -#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */ -#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */ -#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */ -#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */ -#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */ - -#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */ -#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */ -#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */ -#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */ -#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */ -#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */ -#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */ -#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */ - -#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */ -#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */ -#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */ -#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */ -#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */ -#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */ -#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */ -#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */ - -#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */ -#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */ -#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */ -#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */ -#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */ -#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */ -#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */ -#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */ - -#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */ -#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */ -#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */ -#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */ -#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */ -#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */ -#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */ -#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */ - -#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */ -#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */ -#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */ -#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */ -#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */ -#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */ -#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */ -#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */ - -#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */ -#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */ -#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */ -#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */ -#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */ -#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */ -#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */ -#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */ - -#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */ -#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */ -#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */ -#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */ -#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */ -#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */ -#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */ -#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */ - -#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */ -#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */ -#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */ -#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */ -#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */ -#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */ -#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */ -#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */ - -#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */ -#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */ -#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */ -#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */ -#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */ -#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */ -#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */ -#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */ - -#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */ -#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */ -#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */ -#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */ -#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */ -#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */ -#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */ -#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */ - -#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */ -#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */ -#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */ -#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */ -#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */ -#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */ -#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */ -#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */ - -#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */ -#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */ -#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */ -#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */ -#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */ -#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */ -#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */ -#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */ - -#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */ -#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */ -#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */ -#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */ -#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */ -#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */ -#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */ -#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */ - -#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */ -#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */ -#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */ -#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */ -#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */ -#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */ -#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */ -#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */ - -#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */ -#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */ -#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */ -#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */ -#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */ -#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */ -#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */ -#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */ - -#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */ -#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */ -#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */ -#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */ -#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */ -#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */ -#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */ -#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */ - -#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */ -#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */ -#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */ -#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */ -#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */ -#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */ -#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */ -#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */ - -#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */ -#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */ -#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */ -#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */ -#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */ -#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */ -#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */ -#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */ - -#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */ -#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */ -#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */ -#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */ -#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */ -#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */ -#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */ -#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */ - -#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */ -#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */ -#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */ -#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */ -#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */ -#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */ -#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */ -#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */ - -#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */ -#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */ -#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */ -#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */ -#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */ -#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */ -#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */ -#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */ - -#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */ -#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */ -#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */ -#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */ -#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */ -#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */ -#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */ -#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */ - -/* CAN Mailbox Area Macros */ -#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20)) -#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20)) -#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20)) -#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20)) -#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20)) -#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20)) -#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20)) -#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20)) - - -/*********************************************************************************** */ -/* System MMR Register Bits and Macros */ -/******************************************************************************* */ - -/* SWRST Mask */ -#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ -#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ -#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ -#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ -#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ - -/* SYSCR Masks */ -#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */ -#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ - - -/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ - -/* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */ -#define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */ -#define DMAC0_ERR_IRQ 0x00000002 /* DMA Controller 0 Error Interrupt Request */ -#define PPI_ERR_IRQ 0x00000004 /* PPI Error Interrupt Request */ -#define SPORT0_ERR_IRQ 0x00000008 /* SPORT0 Error Interrupt Request */ -#define SPORT1_ERR_IRQ 0x00000010 /* SPORT1 Error Interrupt Request */ -#define SPI0_ERR_IRQ 0x00000020 /* SPI0 Error Interrupt Request */ -#define UART0_ERR_IRQ 0x00000040 /* UART0 Error Interrupt Request */ -#define RTC_IRQ 0x00000080 /* Real-Time Clock Interrupt Request */ -#define DMA0_IRQ 0x00000100 /* DMA Channel 0 (PPI) Interrupt Request */ -#define DMA1_IRQ 0x00000200 /* DMA Channel 1 (SPORT0 RX) Interrupt Request */ -#define DMA2_IRQ 0x00000400 /* DMA Channel 2 (SPORT0 TX) Interrupt Request */ -#define DMA3_IRQ 0x00000800 /* DMA Channel 3 (SPORT1 RX) Interrupt Request */ -#define DMA4_IRQ 0x00001000 /* DMA Channel 4 (SPORT1 TX) Interrupt Request */ -#define DMA5_IRQ 0x00002000 /* DMA Channel 5 (SPI) Interrupt Request */ -#define DMA6_IRQ 0x00004000 /* DMA Channel 6 (UART RX) Interrupt Request */ -#define DMA7_IRQ 0x00008000 /* DMA Channel 7 (UART TX) Interrupt Request */ -#define TIMER0_IRQ 0x00010000 /* Timer 0 Interrupt Request */ -#define TIMER1_IRQ 0x00020000 /* Timer 1 Interrupt Request */ -#define TIMER2_IRQ 0x00040000 /* Timer 2 Interrupt Request */ -#define PFA_IRQ 0x00080000 /* Programmable Flag Interrupt Request A */ -#define PFB_IRQ 0x00100000 /* Programmable Flag Interrupt Request B */ -#define MDMA0_0_IRQ 0x00200000 /* MemDMA0 Stream 0 Interrupt Request */ -#define MDMA0_1_IRQ 0x00400000 /* MemDMA0 Stream 1 Interrupt Request */ -#define WDOG_IRQ 0x00800000 /* Software Watchdog Timer Interrupt Request */ -#define DMAC1_ERR_IRQ 0x01000000 /* DMA Controller 1 Error Interrupt Request */ -#define SPORT2_ERR_IRQ 0x02000000 /* SPORT2 Error Interrupt Request */ -#define SPORT3_ERR_IRQ 0x04000000 /* SPORT3 Error Interrupt Request */ -#define MXVR_SD_IRQ 0x08000000 /* MXVR Synchronous Data Interrupt Request */ -#define SPI1_ERR_IRQ 0x10000000 /* SPI1 Error Interrupt Request */ -#define SPI2_ERR_IRQ 0x20000000 /* SPI2 Error Interrupt Request */ -#define UART1_ERR_IRQ 0x40000000 /* UART1 Error Interrupt Request */ -#define UART2_ERR_IRQ 0x80000000 /* UART2 Error Interrupt Request */ - -/* the following are for backwards compatibility */ -#define DMA0_ERR_IRQ DMAC0_ERR_IRQ -#define DMA1_ERR_IRQ DMAC1_ERR_IRQ - - -/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */ -#define CAN_ERR_IRQ 0x00000001 /* CAN Error Interrupt Request */ -#define DMA8_IRQ 0x00000002 /* DMA Channel 8 (SPORT2 RX) Interrupt Request */ -#define DMA9_IRQ 0x00000004 /* DMA Channel 9 (SPORT2 TX) Interrupt Request */ -#define DMA10_IRQ 0x00000008 /* DMA Channel 10 (SPORT3 RX) Interrupt Request */ -#define DMA11_IRQ 0x00000010 /* DMA Channel 11 (SPORT3 TX) Interrupt Request */ -#define DMA12_IRQ 0x00000020 /* DMA Channel 12 Interrupt Request */ -#define DMA13_IRQ 0x00000040 /* DMA Channel 13 Interrupt Request */ -#define DMA14_IRQ 0x00000080 /* DMA Channel 14 (SPI1) Interrupt Request */ -#define DMA15_IRQ 0x00000100 /* DMA Channel 15 (SPI2) Interrupt Request */ -#define DMA16_IRQ 0x00000200 /* DMA Channel 16 (UART1 RX) Interrupt Request */ -#define DMA17_IRQ 0x00000400 /* DMA Channel 17 (UART1 TX) Interrupt Request */ -#define DMA18_IRQ 0x00000800 /* DMA Channel 18 (UART2 RX) Interrupt Request */ -#define DMA19_IRQ 0x00001000 /* DMA Channel 19 (UART2 TX) Interrupt Request */ -#define TWI0_IRQ 0x00002000 /* TWI0 Interrupt Request */ -#define TWI1_IRQ 0x00004000 /* TWI1 Interrupt Request */ -#define CAN_RX_IRQ 0x00008000 /* CAN Receive Interrupt Request */ -#define CAN_TX_IRQ 0x00010000 /* CAN Transmit Interrupt Request */ -#define MDMA1_0_IRQ 0x00020000 /* MemDMA1 Stream 0 Interrupt Request */ -#define MDMA1_1_IRQ 0x00040000 /* MemDMA1 Stream 1 Interrupt Request */ -#define MXVR_STAT_IRQ 0x00080000 /* MXVR Status Interrupt Request */ -#define MXVR_CM_IRQ 0x00100000 /* MXVR Control Message Interrupt Request */ -#define MXVR_AP_IRQ 0x00200000 /* MXVR Asynchronous Packet Interrupt */ - -/* the following are for backwards compatibility */ -#define MDMA0_IRQ MDMA1_0_IRQ -#define MDMA1_IRQ MDMA1_1_IRQ - -#ifdef _MISRA_RULES -#define _MF15 0xFu -#define _MF7 7u -#else -#define _MF15 0xF -#define _MF7 7 -#endif /* _MISRA_RULES */ - -/* SIC_IMASKx Masks */ -#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ -#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ -#ifdef _MISRA_RULES -#define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */ -#define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */ -#else -#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ -#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ -#endif /* _MISRA_RULES */ - -/* SIC_IWRx Masks */ -#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ -#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ -#ifdef _MISRA_RULES -#define IWR_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */ -#define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */ -#else -#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ -#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ -#endif /* _MISRA_RULES */ - - -/* ***************************** UART CONTROLLER MASKS ********************** */ -/* UARTx_LCR Register */ -#ifdef _MISRA_RULES -#define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */ -#else -#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ -#endif /* _MISRA_RULES */ -#define STB 0x04 /* Stop Bits */ -#define PEN 0x08 /* Parity Enable */ -#define EPS 0x10 /* Even Parity Select */ -#define STP 0x20 /* Stick Parity */ -#define SB 0x40 /* Set Break */ -#define DLAB 0x80 /* Divisor Latch Access */ - -#define DLAB_P 0x07 -#define SB_P 0x06 -#define STP_P 0x05 -#define EPS_P 0x04 -#define PEN_P 0x03 -#define STB_P 0x02 -#define WLS_P1 0x01 -#define WLS_P0 0x00 - -/* UARTx_MCR Register */ -#define LOOP_ENA 0x10 /* Loopback Mode Enable */ -#define LOOP_ENA_P 0x04 -/* Deprecated UARTx_MCR Mask */ - -/* UARTx_LSR Register */ -#define DR 0x01 /* Data Ready */ -#define OE 0x02 /* Overrun Error */ -#define PE 0x04 /* Parity Error */ -#define FE 0x08 /* Framing Error */ -#define BI 0x10 /* Break Interrupt */ -#define THRE 0x20 /* THR Empty */ -#define TEMT 0x40 /* TSR and UART_THR Empty */ - -#define TEMP_P 0x06 -#define THRE_P 0x05 -#define BI_P 0x04 -#define FE_P 0x03 -#define PE_P 0x02 -#define OE_P 0x01 -#define DR_P 0x00 - -/* UARTx_IER Register */ -#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ -#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ -#define ELSI 0x04 /* Enable RX Status Interrupt */ - -#define ELSI_P 0x02 -#define ETBEI_P 0x01 -#define ERBFI_P 0x00 - -/* UARTx_IIR Register */ -#define NINT 0x01 -#define STATUS_P1 0x02 -#define STATUS_P0 0x01 -#define NINT_P 0x00 - -/* UARTx_GCTL Register */ -#define UCEN 0x01 /* Enable UARTx Clocks */ -#define IREN 0x02 /* Enable IrDA Mode */ -#define TPOLC 0x04 /* IrDA TX Polarity Change */ -#define RPOLC 0x08 /* IrDA RX Polarity Change */ -#define FPE 0x10 /* Force Parity Error On Transmit */ -#define FFE 0x20 /* Force Framing Error On Transmit */ - -#define FFE_P 0x05 -#define FPE_P 0x04 -#define RPOLC_P 0x03 -#define TPOLC_P 0x02 -#define IREN_P 0x01 -#define UCEN_P 0x00 - - -/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ -/* PPI_CONTROL Masks */ -#define PORT_EN 0x0001 /* PPI Port Enable */ -#define PORT_DIR 0x0002 /* PPI Port Direction */ -#define XFR_TYPE 0x000C /* PPI Transfer Type */ -#define PORT_CFG 0x0030 /* PPI Port Configuration */ -#define FLD_SEL 0x0040 /* PPI Active Field Select */ -#define PACK_EN 0x0080 /* PPI Packing Mode */ -/* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */ -#define SKIP_EN 0x0200 /* PPI Skip Element Enable */ -#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ -#define DLENGTH 0x3800 /* PPI Data Length */ -#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ -#define DLEN_10 0x0800 /* Data Length = 10 Bits */ -#define DLEN_11 0x1000 /* Data Length = 11 Bits */ -#define DLEN_12 0x1800 /* Data Length = 12 Bits */ -#define DLEN_13 0x2000 /* Data Length = 13 Bits */ -#define DLEN_14 0x2800 /* Data Length = 14 Bits */ -#define DLEN_15 0x3000 /* Data Length = 15 Bits */ -#define DLEN_16 0x3800 /* Data Length = 16 Bits */ -#ifdef _MISRA_RULES -#define DLEN(x) ((((x)-9u) & 0x07u) << 11) /* PPI Data Length (only works for x=10-->x=16) */ -#else -#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ -#endif /* _MISRA_RULES */ -#define POL 0xC000 /* PPI Signal Polarities */ -#define POLC 0x4000 /* PPI Clock Polarity */ -#define POLS 0x8000 /* PPI Frame Sync Polarity */ - - -/* PPI_STATUS Masks */ -#define FLD 0x0400 /* Field Indicator */ -#define FT_ERR 0x0800 /* Frame Track Error */ -#define OVR 0x1000 /* FIFO Overflow Error */ -#define UNDR 0x2000 /* FIFO Underrun Error */ -#define ERR_DET 0x4000 /* Error Detected Indicator */ -#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ - - -/* ********** DMA CONTROLLER MASKS ***********************/ - -/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ - -#define CTYPE 0x0040 /* DMA Channel Type Indicator */ -#define CTYPE_P 0x6 /* DMA Channel Type Indicator BIT POSITION */ -#define PCAP8 0x0080 /* DMA 8-bit Operation Indicator */ -#define PCAP16 0x0100 /* DMA 16-bit Operation Indicator */ -#define PCAP32 0x0200 /* DMA 32-bit Operation Indicator */ -#define PCAPWR 0x0400 /* DMA Write Operation Indicator */ -#define PCAPRD 0x0800 /* DMA Read Operation Indicator */ -#define PMAP 0xF000 /* DMA Peripheral Map Field */ - -/* PMAP Encodings For DMA Controller 0 */ -#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */ -#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */ -#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */ -#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */ -#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */ -#define PMAP_SPI0 0x5000 /* PMAP SPI DMA */ -#define PMAP_UART0RX 0x6000 /* PMAP UART Receive DMA */ -#define PMAP_UART0TX 0x7000 /* PMAP UART Transmit DMA */ - -/* PMAP Encodings For DMA Controller 1 */ -#define PMAP_SPORT2RX 0x0000 /* PMAP SPORT2 Receive DMA */ -#define PMAP_SPORT2TX 0x1000 /* PMAP SPORT2 Transmit DMA */ -#define PMAP_SPORT3RX 0x2000 /* PMAP SPORT3 Receive DMA */ -#define PMAP_SPORT3TX 0x3000 /* PMAP SPORT3 Transmit DMA */ -#define PMAP_SPI1 0x6000 /* PMAP SPI1 DMA */ -#define PMAP_SPI2 0x7000 /* PMAP SPI2 DMA */ -#define PMAP_UART1RX 0x8000 /* PMAP UART1 Receive DMA */ -#define PMAP_UART1TX 0x9000 /* PMAP UART1 Transmit DMA */ -#define PMAP_UART2RX 0xA000 /* PMAP UART2 Receive DMA */ -#define PMAP_UART2TX 0xB000 /* PMAP UART2 Transmit DMA */ - - -/* ************* GENERAL PURPOSE TIMER MASKS ******************** */ -/* PWM Timer bit definitions */ -/* TIMER_ENABLE Register */ -#define TIMEN0 0x0001 /* Enable Timer 0 */ -#define TIMEN1 0x0002 /* Enable Timer 1 */ -#define TIMEN2 0x0004 /* Enable Timer 2 */ - -#define TIMEN0_P 0x00 -#define TIMEN1_P 0x01 -#define TIMEN2_P 0x02 - -/* TIMER_DISABLE Register */ -#define TIMDIS0 0x0001 /* Disable Timer 0 */ -#define TIMDIS1 0x0002 /* Disable Timer 1 */ -#define TIMDIS2 0x0004 /* Disable Timer 2 */ - -#define TIMDIS0_P 0x00 -#define TIMDIS1_P 0x01 -#define TIMDIS2_P 0x02 - -/* TIMER_STATUS Register */ -#define TIMIL0 0x0001 /* Timer 0 Interrupt */ -#define TIMIL1 0x0002 /* Timer 1 Interrupt */ -#define TIMIL2 0x0004 /* Timer 2 Interrupt */ -#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */ -#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */ -#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */ -#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */ -#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */ -#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */ - -#define TIMIL0_P 0x00 -#define TIMIL1_P 0x01 -#define TIMIL2_P 0x02 -#define TOVF_ERR0_P 0x04 -#define TOVF_ERR1_P 0x05 -#define TOVF_ERR2_P 0x06 -#define TRUN0_P 0x0C -#define TRUN1_P 0x0D -#define TRUN2_P 0x0E - -/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ -#define TOVL_ERR0 TOVF_ERR0 -#define TOVL_ERR1 TOVF_ERR1 -#define TOVL_ERR2 TOVF_ERR2 -#define TOVL_ERR0_P TOVF_ERR0_P -#define TOVL_ERR1_P TOVF_ERR1_P -#define TOVL_ERR2_P TOVF_ERR2_P - -/* TIMERx_CONFIG Registers */ -#define PWM_OUT 0x0001 -#define WDTH_CAP 0x0002 -#define EXT_CLK 0x0003 -#define PULSE_HI 0x0004 -#define PERIOD_CNT 0x0008 -#define IRQ_ENA 0x0010 -#define TIN_SEL 0x0020 -#define OUT_DIS 0x0040 -#define CLK_SEL 0x0080 -#define TOGGLE_HI 0x0100 -#define EMU_RUN 0x0200 -#ifdef _MISRA_RULES -#define ERR_TYP(x) (((x) & 0x03u) << 14) -#else -#define ERR_TYP(x) (((x) & 0x03) << 14) -#endif /* _MISRA_RULES */ - -#define TMODE_P0 0x00 -#define TMODE_P1 0x01 -#define PULSE_HI_P 0x02 -#define PERIOD_CNT_P 0x03 -#define IRQ_ENA_P 0x04 -#define TIN_SEL_P 0x05 -#define OUT_DIS_P 0x06 -#define CLK_SEL_P 0x07 -#define TOGGLE_HI_P 0x08 -#define EMU_RUN_P 0x09 -#define ERR_TYP_P0 0x0E -#define ERR_TYP_P1 0x0F - - -/*/ ****************** GENERAL-PURPOSE I/O ********************* */ -/* Flag I/O (FIO_) Masks */ -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - -/* PORT F BIT POSITIONS */ -#define PF0_P 0x0 -#define PF1_P 0x1 -#define PF2_P 0x2 -#define PF3_P 0x3 -#define PF4_P 0x4 -#define PF5_P 0x5 -#define PF6_P 0x6 -#define PF7_P 0x7 -#define PF8_P 0x8 -#define PF9_P 0x9 -#define PF10_P 0xA -#define PF11_P 0xB -#define PF12_P 0xC -#define PF13_P 0xD -#define PF14_P 0xE -#define PF15_P 0xF - - -/******************* GPIO MASKS *********************/ -/* Port C Masks */ -#define PC0 0x0001 -#define PC1 0x0002 -#define PC4 0x0010 -#define PC5 0x0020 -#define PC6 0x0040 -#define PC7 0x0080 -#define PC8 0x0100 -#define PC9 0x0200 -/* Port C Bit Positions */ -#define PC0_P 0x0 -#define PC1_P 0x1 -#define PC4_P 0x4 -#define PC5_P 0x5 -#define PC6_P 0x6 -#define PC7_P 0x7 -#define PC8_P 0x8 -#define PC9_P 0x9 - -/* Port D */ -#define PD0 0x0001 -#define PD1 0x0002 -#define PD2 0x0004 -#define PD3 0x0008 -#define PD4 0x0010 -#define PD5 0x0020 -#define PD6 0x0040 -#define PD7 0x0080 -#define PD8 0x0100 -#define PD9 0x0200 -#define PD10 0x0400 -#define PD11 0x0800 -#define PD12 0x1000 -#define PD13 0x2000 -#define PD14 0x4000 -#define PD15 0x8000 -/* Port D Bit Positions */ -#define PD0_P 0x0 -#define PD1_P 0x1 -#define PD2_P 0x2 -#define PD3_P 0x3 -#define PD4_P 0x4 -#define PD5_P 0x5 -#define PD6_P 0x6 -#define PD7_P 0x7 -#define PD8_P 0x8 -#define PD9_P 0x9 -#define PD10_P 0xA -#define PD11_P 0xB -#define PD12_P 0xC -#define PD13_P 0xD -#define PD14_P 0xE -#define PD15_P 0xF - -/* Port E */ -#define PE0 0x0001 -#define PE1 0x0002 -#define PE2 0x0004 -#define PE3 0x0008 -#define PE4 0x0010 -#define PE5 0x0020 -#define PE6 0x0040 -#define PE7 0x0080 -#define PE8 0x0100 -#define PE9 0x0200 -#define PE10 0x0400 -#define PE11 0x0800 -#define PE12 0x1000 -#define PE13 0x2000 -#define PE14 0x4000 -#define PE15 0x8000 -/* Port E Bit Positions */ -#define PE0_P 0x0 -#define PE1_P 0x1 -#define PE2_P 0x2 -#define PE3_P 0x3 -#define PE4_P 0x4 -#define PE5_P 0x5 -#define PE6_P 0x6 -#define PE7_P 0x7 -#define PE8_P 0x8 -#define PE9_P 0x9 -#define PE10_P 0xA -#define PE11_P 0xB -#define PE12_P 0xC -#define PE13_P 0xD -#define PE14_P 0xE -#define PE15_P 0xF - -/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ -/* EBIU_AMGCTL Masks */ -#define AMCKEN 0x0001 /* Enable CLKOUT */ -#define AMBEN_NONE 0x0000 /* All Banks Disabled */ -#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */ -#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */ -#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ -#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ -#define CDPRIO 0x0100 /* DMA has priority over core for external accesses */ - -/* EBIU_AMGCTL Bit Positions */ -#define AMCKEN_P 0x0000 /* Enable CLKOUT */ -#define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ -#define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ -#define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ - -/* EBIU_AMBCTL0 Masks */ -#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ -#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ -#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ -#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ -#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ -#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ -#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ -#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ -#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ -#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ -#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ -#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ -#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ -#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ -#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ -#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ -#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ -#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ -#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ -#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ -#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ -#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ -#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ -#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ -#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ -#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ -#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ -#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ -#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ -#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ -#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ -#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ -#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ -#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ -#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ -#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ -#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ -#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ -#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ -#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ -#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ -#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ -#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ -#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ -#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ -#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ -#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ -#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ -#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ -#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ -#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ -#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ -#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ -#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ -#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ -#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ -#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ -#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ -#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ -#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ -#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ -#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ -#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ -#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ -#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ -#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ -#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ -#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ -#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ -#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ -#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ -#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ -#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ -#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ -#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ -#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ -#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ -#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ -#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ -#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ - -/* EBIU_AMBCTL1 Masks */ -#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ -#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ -#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ -#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ -#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ -#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ -#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ -#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ -#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ -#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ -#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ -#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ -#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ -#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ -#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ -#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ -#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ -#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ -#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ -#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ -#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ -#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ -#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ -#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ -#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ -#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ -#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ -#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ -#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ -#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ -#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ -#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ -#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ -#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ -#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ -#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ -#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ -#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ -#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ -#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ -#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ -#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ -#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ -#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ -#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ -#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ -#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ -#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ -#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ -#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ -#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ -#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ -#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ -#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ -#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ -#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ -#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ -#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ -#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ -#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ -#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ -#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ -#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ -#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ -#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ -#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ -#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ -#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ -#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ -#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ -#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ -#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ - -/* ********************** SDRAM CONTROLLER MASKS *************************** */ -/* EBIU_SDGCTL Masks */ -#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ -#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ -#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ -#define PFE 0x00000010 /* Enable SDRAM prefetch */ -#define PFP 0x00000020 /* Prefetch has priority over AMC requests */ -#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ -#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ -#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ -#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ -#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ -#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ -#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ -#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ -#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ -#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ -#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ -#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ -#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ -#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ -#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ -#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ -#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ -#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ -#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ -#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ -#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ -#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ -#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ -#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ -#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ -#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ -#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ -#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ -#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ -#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ -#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ -#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ -#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ -#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ -#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ -#define PUPSD 0x00200000 /*Power-up start delay */ -#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ -#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ -#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ -#define EBUFE 0x02000000 /* Enable external buffering timing */ -#define FBBRW 0x04000000 /* Fast back-to-back read write enable */ -#define EMREN 0x10000000 /* Extended mode register enable */ -#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ -#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ - -/* EBIU_SDBCTL Masks */ -#define EBE 0x00000001 /* Enable SDRAM external bank */ -#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */ -#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */ -#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */ -#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */ -#define EBSZ_256 0x00000008 /* SDRAM External Bank Size = 256MB */ -#define EBSZ_512 0x0000000A /* SDRAM External Bank Size = 512MB */ -#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ -#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ -#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ -#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ - -/* EBIU_SDSTAT Masks */ -#define SDCI 0x00000001 /* SDRAM controller is idle */ -#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ -#define SDPUA 0x00000004 /* SDRAM power up active */ -#define SDRS 0x00000008 /* SDRAM is in reset state */ -#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ -#define BGSTAT 0x00000020 /* Bus granted */ - - -/* ******************** TWO-WIRE INTERFACE (TWIx) MASKS ***********************/ -/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ -#ifdef _MISRA_RULES -#define CLKLOW(x) ((x) & 0xFFu) /* Periods Clock Is Held Low */ -#define CLKHI(y) (((y)&0xFFu)<<0x8) /* Periods Before New Clock Low */ -#else -#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ -#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ -#endif /* _MISRA_RULES */ - -/* TWIx_PRESCALE Masks */ -#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ -#define TWI_ENA 0x0080 /* TWI Enable */ -#define SCCB 0x0200 /* SCCB Compatibility Enable */ - -/* TWIx_SLAVE_CTRL Masks */ -#define SEN 0x0001 /* Slave Enable */ -#define SADD_LEN 0x0002 /* Slave Address Length */ -#define STDVAL 0x0004 /* Slave Transmit Data Valid */ -#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ -#define GEN 0x0010 /* General Call Adrress Matching Enabled */ - -/* TWIx_SLAVE_STAT Masks */ -#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ -#define GCALL 0x0002 /* General Call Indicator */ - -/* TWIx_MASTER_CTRL Masks */ -#define MEN 0x0001 /* Master Mode Enable */ -#define MADD_LEN 0x0002 /* Master Address Length */ -#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ -#define FAST 0x0008 /* Use Fast Mode Timing Specs */ -#define STOP 0x0010 /* Issue Stop Condition */ -#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ -#define DCNT 0x3FC0 /* Data Bytes To Transfer */ -#define SDAOVR 0x4000 /* Serial Data Override */ -#define SCLOVR 0x8000 /* Serial Clock Override */ - -/* TWIx_MASTER_STAT Masks */ -#define MPROG 0x0001 /* Master Transfer In Progress */ -#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ -#define ANAK 0x0004 /* Address Not Acknowledged */ -#define DNAK 0x0008 /* Data Not Acknowledged */ -#define BUFRDERR 0x0010 /* Buffer Read Error */ -#define BUFWRERR 0x0020 /* Buffer Write Error */ -#define SDASEN 0x0040 /* Serial Data Sense */ -#define SCLSEN 0x0080 /* Serial Clock Sense */ -#define BUSBUSY 0x0100 /* Bus Busy Indicator */ - -/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */ -#define SINIT 0x0001 /* Slave Transfer Initiated */ -#define SCOMP 0x0002 /* Slave Transfer Complete */ -#define SERR 0x0004 /* Slave Transfer Error */ -#define SOVF 0x0008 /* Slave Overflow */ -#define MCOMP 0x0010 /* Master Transfer Complete */ -#define MERR 0x0020 /* Master Transfer Error */ -#define XMTSERV 0x0040 /* Transmit FIFO Service */ -#define RCVSERV 0x0080 /* Receive FIFO Service */ - -/* TWIx_FIFO_CTL Masks */ -#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ -#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ -#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ -#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ - -/* TWIx_FIFO_STAT Masks */ -#define XMTSTAT 0x0003 /* Transmit FIFO Status */ -#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ -#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ -#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ - -#define RCVSTAT 0x000C /* Receive FIFO Status */ -#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ -#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ -#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ - #endif /* _DEF_BF539_H */ diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h index bd9adb7183d..8a5beeece99 100644 --- a/arch/blackfin/mach-bf538/include/mach/gpio.h +++ b/arch/blackfin/mach-bf538/include/mach/gpio.h @@ -70,4 +70,9 @@ #define PORT_D GPIO_PD0 #define PORT_E GPIO_PE0 +#include <mach-common/ports-c.h> +#include <mach-common/ports-d.h> +#include <mach-common/ports-e.h> +#include <mach-common/ports-f.h> + #endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf538/include/mach/pll.h b/arch/blackfin/mach-bf538/include/mach/pll.h index b30bbcd412a..94cca674d83 100644 --- a/arch/blackfin/mach-bf538/include/mach/pll.h +++ b/arch/blackfin/mach-bf538/include/mach/pll.h @@ -1,63 +1 @@ -/* - * Copyright 2008-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_PLL_H -#define _MACH_PLL_H - -#include <asm/blackfin.h> -#include <asm/irqflags.h> - -/* Writing to PLL_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_PLL_CTL(unsigned int val) -{ - unsigned long flags, iwr0, iwr1; - - if (val == bfin_read_PLL_CTL()) - return; - - flags = hard_local_irq_save(); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SIC_IWR0); - iwr1 = bfin_read32(SIC_IWR1); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR0, IWR_ENABLE(0)); - bfin_write32(SIC_IWR1, 0); - - bfin_write16(PLL_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR0, iwr0); - bfin_write32(SIC_IWR1, iwr1); - hard_local_irq_restore(flags); -} - -/* Writing to VR_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_VR_CTL(unsigned int val) -{ - unsigned long flags, iwr0, iwr1; - - if (val == bfin_read_VR_CTL()) - return; - - flags = hard_local_irq_save(); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SIC_IWR0); - iwr1 = bfin_read32(SIC_IWR1); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR0, IWR_ENABLE(0)); - bfin_write32(SIC_IWR1, 0); - - bfin_write16(VR_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR0, iwr0); - bfin_write32(SIC_IWR1, iwr1); - hard_local_irq_restore(flags); -} - -#endif /* _MACH_PLL_H */ +#include <mach-common/pll.h> diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c index 4c2ee678909..d11502ac562 100644 --- a/arch/blackfin/mach-bf548/boards/cm_bf548.c +++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c @@ -156,7 +156,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -211,7 +211,7 @@ static struct resource bfin_uart1_resources[] = { #endif }; -unsigned short bfin_uart1_peripherals[] = { +static unsigned short bfin_uart1_peripherals[] = { P_UART1_TX, P_UART1_RX, #ifdef CONFIG_BFIN_UART1_CTSRTS P_UART1_RTS, P_UART1_CTS, @@ -258,7 +258,7 @@ static struct resource bfin_uart2_resources[] = { }, }; -unsigned short bfin_uart2_peripherals[] = { +static unsigned short bfin_uart2_peripherals[] = { P_UART2_TX, P_UART2_RX, 0 }; @@ -313,7 +313,7 @@ static struct resource bfin_uart3_resources[] = { #endif }; -unsigned short bfin_uart3_peripherals[] = { +static unsigned short bfin_uart3_peripherals[] = { P_UART3_TX, P_UART3_RX, #ifdef CONFIG_BFIN_UART3_CTSRTS P_UART3_RTS, P_UART3_CTS, @@ -504,6 +504,7 @@ static struct musb_hdrc_config musb_config = { * if it is the case. */ .gpio_vrsel_active = 1, + .clkin = 24, /* musb CLKIN in MHZ */ }; static struct musb_hdrc_platform_data musb_plat = { @@ -552,9 +553,9 @@ static struct resource bfin_sport0_uart_resources[] = { }, }; -unsigned short bfin_sport0_peripherals[] = { +static unsigned short bfin_sport0_peripherals[] = { P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 }; static struct platform_device bfin_sport0_uart_device = { @@ -586,9 +587,9 @@ static struct resource bfin_sport1_uart_resources[] = { }, }; -unsigned short bfin_sport1_peripherals[] = { +static unsigned short bfin_sport1_peripherals[] = { P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { @@ -620,7 +621,7 @@ static struct resource bfin_sport2_uart_resources[] = { }, }; -unsigned short bfin_sport2_peripherals[] = { +static unsigned short bfin_sport2_peripherals[] = { P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0 }; @@ -654,7 +655,7 @@ static struct resource bfin_sport3_uart_resources[] = { }, }; -unsigned short bfin_sport3_peripherals[] = { +static unsigned short bfin_sport3_peripherals[] = { P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0 }; @@ -756,7 +757,7 @@ static struct platform_device bf54x_sdh_device = { #endif #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) -unsigned short bfin_can_peripherals[] = { +static unsigned short bfin_can_peripherals[] = { P_CAN0_RX, P_CAN0_TX, 0 }; diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 4f03fbc4c9b..ce5a2bb147d 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -261,7 +261,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; @@ -316,7 +316,7 @@ static struct resource bfin_uart1_resources[] = { #endif }; -unsigned short bfin_uart1_peripherals[] = { +static unsigned short bfin_uart1_peripherals[] = { P_UART1_TX, P_UART1_RX, #ifdef CONFIG_BFIN_UART1_CTSRTS P_UART1_RTS, P_UART1_CTS, @@ -363,7 +363,7 @@ static struct resource bfin_uart2_resources[] = { }, }; -unsigned short bfin_uart2_peripherals[] = { +static unsigned short bfin_uart2_peripherals[] = { P_UART2_TX, P_UART2_RX, 0 }; @@ -418,7 +418,7 @@ static struct resource bfin_uart3_resources[] = { #endif }; -unsigned short bfin_uart3_peripherals[] = { +static unsigned short bfin_uart3_peripherals[] = { P_UART3_TX, P_UART3_RX, #ifdef CONFIG_BFIN_UART3_CTSRTS P_UART3_RTS, P_UART3_CTS, @@ -609,6 +609,7 @@ static struct musb_hdrc_config musb_config = { * if it is the case. */ .gpio_vrsel_active = 1, + .clkin = 24, /* musb CLKIN in MHZ */ }; static struct musb_hdrc_platform_data musb_plat = { @@ -657,9 +658,9 @@ static struct resource bfin_sport0_uart_resources[] = { }, }; -unsigned short bfin_sport0_peripherals[] = { +static unsigned short bfin_sport0_peripherals[] = { P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 }; static struct platform_device bfin_sport0_uart_device = { @@ -691,9 +692,9 @@ static struct resource bfin_sport1_uart_resources[] = { }, }; -unsigned short bfin_sport1_peripherals[] = { +static unsigned short bfin_sport1_peripherals[] = { P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { @@ -725,7 +726,7 @@ static struct resource bfin_sport2_uart_resources[] = { }, }; -unsigned short bfin_sport2_peripherals[] = { +static unsigned short bfin_sport2_peripherals[] = { P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0 }; @@ -759,7 +760,7 @@ static struct resource bfin_sport3_uart_resources[] = { }, }; -unsigned short bfin_sport3_peripherals[] = { +static unsigned short bfin_sport3_peripherals[] = { P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0 }; @@ -777,7 +778,7 @@ static struct platform_device bfin_sport3_uart_device = { #endif #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) -unsigned short bfin_can_peripherals[] = { +static unsigned short bfin_can_peripherals[] = { P_CAN0_RX, P_CAN0_TX, 0 }; diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c index 888b9cc0b82..69ead33cbf9 100644 --- a/arch/blackfin/mach-bf548/dma.c +++ b/arch/blackfin/mach-bf548/dma.c @@ -11,7 +11,7 @@ #include <asm/blackfin.h> #include <asm/dma.h> -struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { +struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { (struct dma_register *) DMA0_NEXT_DESC_PTR, (struct dma_register *) DMA1_NEXT_DESC_PTR, (struct dma_register *) DMA2_NEXT_DESC_PTR, diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial.h new file mode 100644 index 00000000000..a77109f9972 --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial.h @@ -0,0 +1,16 @@ +/* + * mach/bfin_serial.h - Blackfin UART/Serial definitions + * + * Copyright 2006-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_MACH_SERIAL_H__ +#define __BFIN_MACH_SERIAL_H__ + +#define BFIN_UART_NR_PORTS 4 + +#define BFIN_UART_BF54X_STYLE + +#endif diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h index dd44aa75fe7..0d94edaaaa2 100644 --- a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h @@ -4,72 +4,14 @@ * Licensed under the GPL-2 or later. */ -#include <linux/serial.h> #include <asm/dma.h> #include <asm/portmux.h> -#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) -#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) -#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) -#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET)) -#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) -#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR)) -#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) -#define UART_GET_MSR(uart) bfin_read16(((uart)->port.membase + OFFSET_MSR)) -#define UART_GET_MCR(uart) bfin_read16(((uart)->port.membase + OFFSET_MCR)) - -#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) -#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) -#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v) -#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v) -#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) -#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v) -#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) -#define UART_CLEAR_LSR(uart) bfin_write16(((uart)->port.membase + OFFSET_LSR), -1) -#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) -#define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v) -#define UART_CLEAR_SCTS(uart) bfin_write16(((uart)->port.membase + OFFSET_MSR),SCTS) - -#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */ -#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */ - -#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS) -#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS|MRTS)) -#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS) -#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v) -#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF) - #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \ defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS) # define CONFIG_SERIAL_BFIN_HARD_CTSRTS #endif -#define BFIN_UART_TX_FIFO_SIZE 2 - -/* - * The pin configuration is different from schematic - */ -struct bfin_serial_port { - struct uart_port port; - unsigned int old_status; - int status_irq; -#ifdef CONFIG_SERIAL_BFIN_DMA - int tx_done; - int tx_count; - struct circ_buf rx_dma_buf; - struct timer_list rx_dma_timer; - int rx_dma_nrows; - unsigned int tx_dma_channel; - unsigned int rx_dma_channel; - struct work_struct tx_dma_workqueue; -#endif -#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS - int scts; - int cts_pin; - int rts_pin; -#endif -}; - struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; @@ -148,3 +90,5 @@ struct bfin_serial_res bfin_serial_resource[] = { }; #define DRIVER_NAME "bfin-uart" + +#include <asm/bfin_serial.h> diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h index 5684030ccc2..72da721a77f 100644 --- a/arch/blackfin/mach-bf548/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Analog Devices Inc. + * Copyright 2007-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -10,58 +10,40 @@ #include "bf548.h" #include "anomaly.h" +#include <asm/def_LPBlackfin.h> #ifdef CONFIG_BF542 -#include "defBF542.h" +# include "defBF542.h" #endif - #ifdef CONFIG_BF544 -#include "defBF544.h" +# include "defBF544.h" #endif - #ifdef CONFIG_BF547 -#include "defBF547.h" +# include "defBF547.h" #endif - #ifdef CONFIG_BF548 -#include "defBF548.h" +# include "defBF548.h" #endif - #ifdef CONFIG_BF549 -#include "defBF549.h" -#endif - -#if !defined(__ASSEMBLY__) -#ifdef CONFIG_BF542 -#include "cdefBF542.h" +# include "defBF549.h" +#endif + +#ifndef __ASSEMBLY__ +# include <asm/cdef_LPBlackfin.h> +# ifdef CONFIG_BF542 +# include "cdefBF542.h" +# endif +# ifdef CONFIG_BF544 +# include "cdefBF544.h" +# endif +# ifdef CONFIG_BF547 +# include "cdefBF547.h" +# endif +# ifdef CONFIG_BF548 +# include "cdefBF548.h" +# endif +# ifdef CONFIG_BF549 +# include "cdefBF549.h" +# endif #endif -#ifdef CONFIG_BF544 -#include "cdefBF544.h" -#endif -#ifdef CONFIG_BF547 -#include "cdefBF547.h" -#endif -#ifdef CONFIG_BF548 -#include "cdefBF548.h" -#endif -#ifdef CONFIG_BF549 -#include "cdefBF549.h" -#endif - -#endif - -#define BFIN_UART_NR_PORTS 4 - -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_GCTL 0x08 /* Global Control Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */ -#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */ -#define OFFSET_THR 0x28 /* Transmit Holding register */ -#define OFFSET_RBR 0x2C /* Receive Buffer register */ #endif diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h b/arch/blackfin/mach-bf548/include/mach/cdefBF542.h index 42f4a946954..d09c19cd1b7 100644 --- a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h +++ b/arch/blackfin/mach-bf548/include/mach/cdefBF542.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Analog Devices Inc. + * Copyright 2007-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -7,14 +7,6 @@ #ifndef _CDEF_BF542_H #define _CDEF_BF542_H -/* include all Core registers and bit definitions */ -#include "defBF542.h" - -/* include core sbfin_read_()ecific register pointer definitions */ -#include <asm/cdef_LPBlackfin.h> - -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */ - /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ #include "cdefBF54x_base.h" diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h b/arch/blackfin/mach-bf548/include/mach/cdefBF544.h index 2207799575f..33ec8102ced 100644 --- a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h +++ b/arch/blackfin/mach-bf548/include/mach/cdefBF544.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Analog Devices Inc. + * Copyright 2007-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -7,14 +7,6 @@ #ifndef _CDEF_BF544_H #define _CDEF_BF544_H -/* include all Core registers and bit definitions */ -#include "defBF544.h" - -/* include core sbfin_read_()ecific register pointer definitions */ -#include <asm/cdef_LPBlackfin.h> - -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */ - /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ #include "cdefBF54x_base.h" diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h index bc650e6ea48..bcb9726dea5 100644 --- a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h +++ b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Analog Devices Inc. + * Copyright 2008-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -7,14 +7,6 @@ #ifndef _CDEF_BF547_H #define _CDEF_BF547_H -/* include all Core registers and bit definitions */ -#include "defBF547.h" - -/* include core sbfin_read_()ecific register pointer definitions */ -#include <asm/cdef_LPBlackfin.h> - -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */ - /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ #include "cdefBF54x_base.h" diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h index 3523e08f796..bae67a65633 100644 --- a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h +++ b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Analog Devices Inc. + * Copyright 2007-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -7,14 +7,6 @@ #ifndef _CDEF_BF548_H #define _CDEF_BF548_H -/* include all Core registers and bit definitions */ -#include "defBF548.h" - -/* include core sbfin_read_()ecific register pointer definitions */ -#include <asm/cdef_LPBlackfin.h> - -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ - /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ #include "cdefBF54x_base.h" diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h index 80201ed41f8..002136ad5a4 100644 --- a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h +++ b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Analog Devices Inc. + * Copyright 2007-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -7,14 +7,6 @@ #ifndef _CDEF_BF549_H #define _CDEF_BF549_H -/* include all Core registers and bit definitions */ -#include "defBF549.h" - -/* include core sbfin_read_()ecific register pointer definitions */ -#include <asm/cdef_LPBlackfin.h> - -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */ - /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ #include "cdefBF54x_base.h" diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h index deaf5d6542d..50c89c8052f 100644 --- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h +++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Analog Devices Inc. + * Copyright 2007-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -7,10 +7,6 @@ #ifndef _CDEF_BF54X_H #define _CDEF_BF54X_H -#include <asm/blackfin.h> - -#include "defBF54x_base.h" - /* ************************************************************** */ /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ /* ************************************************************** */ @@ -2633,22 +2629,5 @@ /* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */ -/* legacy definitions */ -#define bfin_read_EBIU_AMCBCTL0 bfin_read_EBIU_AMBCTL0 -#define bfin_write_EBIU_AMCBCTL0 bfin_write_EBIU_AMBCTL0 -#define bfin_read_EBIU_AMCBCTL1 bfin_read_EBIU_AMBCTL1 -#define bfin_write_EBIU_AMCBCTL1 bfin_write_EBIU_AMBCTL1 -#define bfin_read_PINT0_IRQ bfin_read_PINT0_REQUEST -#define bfin_write_PINT0_IRQ bfin_write_PINT0_REQUEST -#define bfin_read_PINT1_IRQ bfin_read_PINT1_REQUEST -#define bfin_write_PINT1_IRQ bfin_write_PINT1_REQUEST -#define bfin_read_PINT2_IRQ bfin_read_PINT2_REQUEST -#define bfin_write_PINT2_IRQ bfin_write_PINT2_REQUEST -#define bfin_read_PINT3_IRQ bfin_read_PINT3_REQUEST -#define bfin_write_PINT3_IRQ bfin_write_PINT3_REQUEST - -/* These need to be last due to the cdef/linux inter-dependencies */ -#include <asm/irq.h> - #endif /* _CDEF_BF54X_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/defBF542.h b/arch/blackfin/mach-bf548/include/mach/defBF542.h index abf5f750dd8..629bf216e2b 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF542.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF542.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Analog Devices Inc. + * Copyright 2007-2010 Analog Devices Inc. * * Licensed under the ADI BSD license or the GPL-2 (or later) */ @@ -7,11 +7,6 @@ #ifndef _DEF_BF542_H #define _DEF_BF542_H -/* Include all Core registers and bit definitions */ -#include <asm/def_LPBlackfin.h> - -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */ - /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ #include "defBF54x_base.h" diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h index e2771094de0..642468c1bcb 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF544.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Analog Devices Inc. + * Copyright 2007-2010 Analog Devices Inc. * * Licensed under the ADI BSD license or the GPL-2 (or later) */ @@ -7,11 +7,6 @@ #ifndef _DEF_BF544_H #define _DEF_BF544_H -/* Include all Core registers and bit definitions */ -#include <asm/def_LPBlackfin.h> - -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */ - /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ #include "defBF54x_base.h" diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h index be21ba5b3aa..2f3337cd311 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF547.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Analog Devices Inc. + * Copyright 2008-2010 Analog Devices Inc. * * Licensed under the ADI BSD license or the GPL-2 (or later) */ @@ -7,11 +7,6 @@ #ifndef _DEF_BF547_H #define _DEF_BF547_H -/* Include all Core registers and bit definitions */ -#include <asm/def_LPBlackfin.h> - -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */ - /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ #include "defBF54x_base.h" diff --git a/arch/blackfin/mach-bf548/include/mach/defBF548.h b/arch/blackfin/mach-bf548/include/mach/defBF548.h index 3fb33b040ab..3c7f1b69349 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF548.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF548.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Analog Devices Inc. + * Copyright 2007-2010 Analog Devices Inc. * * Licensed under the ADI BSD license or the GPL-2 (or later) */ @@ -7,11 +7,6 @@ #ifndef _DEF_BF548_H #define _DEF_BF548_H -/* Include all Core registers and bit definitions */ -#include <asm/def_LPBlackfin.h> - -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ - /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ #include "defBF54x_base.h" diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h index 5a04e6d4017..9a45cb6b30d 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF549.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF549.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Analog Devices Inc. + * Copyright 2007-2010 Analog Devices Inc. * * Licensed under the ADI BSD license or the GPL-2 (or later) */ @@ -7,11 +7,6 @@ #ifndef _DEF_BF549_H #define _DEF_BF549_H -/* Include all Core registers and bit definitions */ -#include <asm/def_LPBlackfin.h> - -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */ - /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ #include "defBF54x_base.h" diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h index 78f91103f17..0867c2bedb4 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Analog Devices Inc. + * Copyright 2007-2010 Analog Devices Inc. * * Licensed under the ADI BSD license or the GPL-2 (or later) */ @@ -1615,14 +1615,14 @@ #define CTYPE 0x40 /* DMA Channel Type */ #define PMAP 0xf000 /* Peripheral Mapped To This Channel */ -/* Bit masks for DMACx_TCPER */ +/* Bit masks for DMACx_TC_PER */ #define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */ #define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */ #define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */ #define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */ -/* Bit masks for DMACx_TCCNT */ +/* Bit masks for DMACx_TC_CNT */ #define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */ #define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */ @@ -2172,68 +2172,6 @@ #define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */ -/* Bit masks for UARTx_LCR */ - -#if 0 -/* conflicts with legacy one in last section */ -#define WLS 0x3 /* Word Length Select */ -#endif -#define STB 0x4 /* Stop Bits */ -#define PEN 0x8 /* Parity Enable */ -#define EPS 0x10 /* Even Parity Select */ -#define STP 0x20 /* Sticky Parity */ -#define SB 0x40 /* Set Break */ - -/* Bit masks for UARTx_MCR */ - -#define XOFF 0x1 /* Transmitter Off */ -#define MRTS 0x2 /* Manual Request To Send */ -#define RFIT 0x4 /* Receive FIFO IRQ Threshold */ -#define RFRT 0x8 /* Receive FIFO RTS Threshold */ -#define LOOP_ENA 0x10 /* Loopback Mode Enable */ -#define FCPOL 0x20 /* Flow Control Pin Polarity */ -#define ARTS 0x40 /* Automatic Request To Send */ -#define ACTS 0x80 /* Automatic Clear To Send */ - -/* Bit masks for UARTx_LSR */ - -#define DR 0x1 /* Data Ready */ -#define OE 0x2 /* Overrun Error */ -#define PE 0x4 /* Parity Error */ -#define FE 0x8 /* Framing Error */ -#define BI 0x10 /* Break Interrupt */ -#define THRE 0x20 /* THR Empty */ -#define TEMT 0x40 /* Transmitter Empty */ -#define TFI 0x80 /* Transmission Finished Indicator */ - -/* Bit masks for UARTx_MSR */ - -#define SCTS 0x1 /* Sticky CTS */ -#define CTS 0x10 /* Clear To Send */ -#define RFCS 0x20 /* Receive FIFO Count Status */ - -/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */ - -#define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */ -#define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */ -#define ELSI 0x4 /* Enable Receive Status Interrupt */ -#define EDSSI 0x8 /* Enable Modem Status Interrupt */ -#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */ -#define ETFI 0x20 /* Enable Transmission Finished Interrupt */ -#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */ - -/* Bit masks for UARTx_GCTL */ - -#define UCEN 0x1 /* UART Enable */ -#define IREN 0x2 /* IrDA Mode Enable */ -#define TPOLC 0x4 /* IrDA TX Polarity Change */ -#define RPOLC 0x8 /* IrDA RX Polarity Change */ -#define FPE 0x10 /* Force Parity Error */ -#define FFE 0x20 /* Force Framing Error */ -#define EDBO 0x40 /* Enable Divide-by-One */ -#define EGLSI 0x80 /* Enable Global LS Interrupt */ - - /* ******************************************* */ /* MULTI BIT MACRO ENUMERATIONS */ /* ******************************************* */ @@ -2251,13 +2189,6 @@ #define WDTH_CAP 0x0002 #define EXT_CLK 0x0003 -/* UARTx_LCR bit field options */ - -#define WLS_5 0x0000 /* 5 data bits */ -#define WLS_6 0x0001 /* 6 data bits */ -#define WLS_7 0x0002 /* 7 data bits */ -#define WLS_8 0x0003 /* 8 data bits */ - /* PINTx Register Bit Definitions */ #define PIQ0 0x00000001 @@ -2300,240 +2231,6 @@ #define PIQ30 0x40000000 #define PIQ31 0x80000000 -/* PORT A Bit Definitions for the registers -PORTA, PORTA_SET, PORTA_CLEAR, -PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN, -PORTA_FER registers -*/ - -#define PA0 0x0001 -#define PA1 0x0002 -#define PA2 0x0004 -#define PA3 0x0008 -#define PA4 0x0010 -#define PA5 0x0020 -#define PA6 0x0040 -#define PA7 0x0080 -#define PA8 0x0100 -#define PA9 0x0200 -#define PA10 0x0400 -#define PA11 0x0800 -#define PA12 0x1000 -#define PA13 0x2000 -#define PA14 0x4000 -#define PA15 0x8000 - -/* PORT B Bit Definitions for the registers -PORTB, PORTB_SET, PORTB_CLEAR, -PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN, -PORTB_FER registers -*/ - -#define PB0 0x0001 -#define PB1 0x0002 -#define PB2 0x0004 -#define PB3 0x0008 -#define PB4 0x0010 -#define PB5 0x0020 -#define PB6 0x0040 -#define PB7 0x0080 -#define PB8 0x0100 -#define PB9 0x0200 -#define PB10 0x0400 -#define PB11 0x0800 -#define PB12 0x1000 -#define PB13 0x2000 -#define PB14 0x4000 - - -/* PORT C Bit Definitions for the registers -PORTC, PORTC_SET, PORTC_CLEAR, -PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN, -PORTC_FER registers -*/ - - -#define PC0 0x0001 -#define PC1 0x0002 -#define PC2 0x0004 -#define PC3 0x0008 -#define PC4 0x0010 -#define PC5 0x0020 -#define PC6 0x0040 -#define PC7 0x0080 -#define PC8 0x0100 -#define PC9 0x0200 -#define PC10 0x0400 -#define PC11 0x0800 -#define PC12 0x1000 -#define PC13 0x2000 - - -/* PORT D Bit Definitions for the registers -PORTD, PORTD_SET, PORTD_CLEAR, -PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN, -PORTD_FER registers -*/ - -#define PD0 0x0001 -#define PD1 0x0002 -#define PD2 0x0004 -#define PD3 0x0008 -#define PD4 0x0010 -#define PD5 0x0020 -#define PD6 0x0040 -#define PD7 0x0080 -#define PD8 0x0100 -#define PD9 0x0200 -#define PD10 0x0400 -#define PD11 0x0800 -#define PD12 0x1000 -#define PD13 0x2000 -#define PD14 0x4000 -#define PD15 0x8000 - -/* PORT E Bit Definitions for the registers -PORTE, PORTE_SET, PORTE_CLEAR, -PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN, -PORTE_FER registers -*/ - - -#define PE0 0x0001 -#define PE1 0x0002 -#define PE2 0x0004 -#define PE3 0x0008 -#define PE4 0x0010 -#define PE5 0x0020 -#define PE6 0x0040 -#define PE7 0x0080 -#define PE8 0x0100 -#define PE9 0x0200 -#define PE10 0x0400 -#define PE11 0x0800 -#define PE12 0x1000 -#define PE13 0x2000 -#define PE14 0x4000 -#define PE15 0x8000 - -/* PORT F Bit Definitions for the registers -PORTF, PORTF_SET, PORTF_CLEAR, -PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN, -PORTF_FER registers -*/ - - -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - -/* PORT G Bit Definitions for the registers -PORTG, PORTG_SET, PORTG_CLEAR, -PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN, -PORTG_FER registers -*/ - - -#define PG0 0x0001 -#define PG1 0x0002 -#define PG2 0x0004 -#define PG3 0x0008 -#define PG4 0x0010 -#define PG5 0x0020 -#define PG6 0x0040 -#define PG7 0x0080 -#define PG8 0x0100 -#define PG9 0x0200 -#define PG10 0x0400 -#define PG11 0x0800 -#define PG12 0x1000 -#define PG13 0x2000 -#define PG14 0x4000 -#define PG15 0x8000 - -/* PORT H Bit Definitions for the registers -PORTH, PORTH_SET, PORTH_CLEAR, -PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN, -PORTH_FER registers -*/ - - -#define PH0 0x0001 -#define PH1 0x0002 -#define PH2 0x0004 -#define PH3 0x0008 -#define PH4 0x0010 -#define PH5 0x0020 -#define PH6 0x0040 -#define PH7 0x0080 -#define PH8 0x0100 -#define PH9 0x0200 -#define PH10 0x0400 -#define PH11 0x0800 -#define PH12 0x1000 -#define PH13 0x2000 - - -/* PORT I Bit Definitions for the registers -PORTI, PORTI_SET, PORTI_CLEAR, -PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN, -PORTI_FER registers -*/ - - -#define PI0 0x0001 -#define PI1 0x0002 -#define PI2 0x0004 -#define PI3 0x0008 -#define PI4 0x0010 -#define PI5 0x0020 -#define PI6 0x0040 -#define PI7 0x0080 -#define PI8 0x0100 -#define PI9 0x0200 -#define PI10 0x0400 -#define PI11 0x0800 -#define PI12 0x1000 -#define PI13 0x2000 -#define PI14 0x4000 -#define PI15 0x8000 - -/* PORT J Bit Definitions for the registers -PORTJ, PORTJ_SET, PORTJ_CLEAR, -PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN, -PORTJ_FER registers -*/ - - -#define PJ0 0x0001 -#define PJ1 0x0002 -#define PJ2 0x0004 -#define PJ3 0x0008 -#define PJ4 0x0010 -#define PJ5 0x0020 -#define PJ6 0x0040 -#define PJ7 0x0080 -#define PJ8 0x0100 -#define PJ9 0x0200 -#define PJ10 0x0400 -#define PJ11 0x0800 -#define PJ12 0x1000 -#define PJ13 0x2000 - - /* Port Muxing Bit Fields for PORTx_MUX Registers */ #define MUX0 0x00000003 @@ -2703,16 +2400,4 @@ PORTJ_FER registers #define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */ #define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */ - -/* for legacy compatibility */ - -#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ -#define W1LMAX_MAX W1LMAX_MIN -#define EBIU_AMCBCTL0 EBIU_AMBCTL0 -#define EBIU_AMCBCTL1 EBIU_AMBCTL1 -#define PINT0_IRQ PINT0_REQUEST -#define PINT1_IRQ PINT1_REQUEST -#define PINT2_IRQ PINT2_REQUEST -#define PINT3_IRQ PINT3_REQUEST - #endif /* _DEF_BF54X_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h index 28037e33196..7db433514e3 100644 --- a/arch/blackfin/mach-bf548/include/mach/gpio.h +++ b/arch/blackfin/mach-bf548/include/mach/gpio.h @@ -200,4 +200,15 @@ struct gpio_port_s { #endif +#include <mach-common/ports-a.h> +#include <mach-common/ports-b.h> +#include <mach-common/ports-c.h> +#include <mach-common/ports-d.h> +#include <mach-common/ports-e.h> +#include <mach-common/ports-f.h> +#include <mach-common/ports-g.h> +#include <mach-common/ports-h.h> +#include <mach-common/ports-i.h> +#include <mach-common/ports-j.h> + #endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h index 1f99b51a3d5..99fd1b2c53d 100644 --- a/arch/blackfin/mach-bf548/include/mach/irq.h +++ b/arch/blackfin/mach-bf548/include/mach/irq.h @@ -474,4 +474,26 @@ Events (highest priority) EMU 0 #define IRQ_PINT2_POS 24 #define IRQ_PINT3_POS 28 +#ifndef __ASSEMBLY__ +#include <linux/types.h> + +/* + * bfin pint registers layout + */ +struct bfin_pint_regs { + u32 mask_set; + u32 mask_clear; + u32 irq; + u32 assign; + u32 edge_set; + u32 edge_clear; + u32 invert_set; + u32 invert_clear; + u32 pinstate; + u32 latch; + u32 __pad0[2]; +}; + +#endif + #endif /* _BF548_IRQ_H_ */ diff --git a/arch/blackfin/mach-bf548/include/mach/pll.h b/arch/blackfin/mach-bf548/include/mach/pll.h index 7865a090d33..94cca674d83 100644 --- a/arch/blackfin/mach-bf548/include/mach/pll.h +++ b/arch/blackfin/mach-bf548/include/mach/pll.h @@ -1,69 +1 @@ -/* - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_PLL_H -#define _MACH_PLL_H - -#include <asm/blackfin.h> -#include <asm/irqflags.h> - -/* Writing to PLL_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_PLL_CTL(unsigned int val) -{ - unsigned long flags, iwr0, iwr1, iwr2; - - if (val == bfin_read_PLL_CTL()) - return; - - flags = hard_local_irq_save(); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SIC_IWR0); - iwr1 = bfin_read32(SIC_IWR1); - iwr2 = bfin_read32(SIC_IWR2); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR0, IWR_ENABLE(0)); - bfin_write32(SIC_IWR1, 0); - bfin_write32(SIC_IWR2, 0); - - bfin_write16(PLL_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR0, iwr0); - bfin_write32(SIC_IWR1, iwr1); - bfin_write32(SIC_IWR2, iwr2); - hard_local_irq_restore(flags); -} - -/* Writing to VR_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_VR_CTL(unsigned int val) -{ - unsigned long flags, iwr0, iwr1, iwr2; - - if (val == bfin_read_VR_CTL()) - return; - - flags = hard_local_irq_save(); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SIC_IWR0); - iwr1 = bfin_read32(SIC_IWR1); - iwr2 = bfin_read32(SIC_IWR2); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR0, IWR_ENABLE(0)); - bfin_write32(SIC_IWR1, 0); - bfin_write32(SIC_IWR2, 0); - - bfin_write16(VR_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR0, iwr0); - bfin_write32(SIC_IWR1, iwr1); - bfin_write32(SIC_IWR2, iwr2); - hard_local_irq_restore(flags); -} - -#endif /* _MACH_PLL_H */ +#include <mach-common/pll.h> diff --git a/arch/blackfin/mach-bf561/atomic.S b/arch/blackfin/mach-bf561/atomic.S index f99f174b129..52d6f73fcce 100644 --- a/arch/blackfin/mach-bf561/atomic.S +++ b/arch/blackfin/mach-bf561/atomic.S @@ -49,6 +49,7 @@ ENTRY(_get_core_lock) jump .Lretry_corelock .Ldone_corelock: p0 = r1; + /* flush core internal write buffer before invalidate dcache */ CSYNC(r2); flushinv[p0]; SSYNC(r2); @@ -685,6 +686,8 @@ ENTRY(___raw_atomic_test_asm) r1 = -L1_CACHE_BYTES; r1 = r0 & r1; p0 = r1; + /* flush core internal write buffer before invalidate dcache */ + CSYNC(r2); flushinv[p0]; SSYNC(r2); r0 = [p1]; @@ -907,6 +910,8 @@ ENTRY(___raw_uncached_fetch_asm) r1 = -L1_CACHE_BYTES; r1 = r0 & r1; p0 = r1; + /* flush core internal write buffer before invalidate dcache */ + CSYNC(r2); flushinv[p0]; SSYNC(r2); r0 = [p1]; diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c index 0b1c20f14fe..3926cd909b6 100644 --- a/arch/blackfin/mach-bf561/boards/acvilon.c +++ b/arch/blackfin/mach-bf561/boards/acvilon.c @@ -224,7 +224,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c index 087b6b05cc7..3b67929d4c0 100644 --- a/arch/blackfin/mach-bf561/boards/cm_bf561.c +++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c @@ -334,7 +334,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index ab7a487975f..f667e770419 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c @@ -190,7 +190,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c index d3017e53686..bb056e60f6e 100644 --- a/arch/blackfin/mach-bf561/boards/tepla.c +++ b/arch/blackfin/mach-bf561/boards/tepla.c @@ -72,7 +72,7 @@ static struct resource bfin_uart0_resources[] = { }, }; -unsigned short bfin_uart0_peripherals[] = { +static unsigned short bfin_uart0_peripherals[] = { P_UART0_TX, P_UART0_RX, 0 }; diff --git a/arch/blackfin/mach-bf561/dma.c b/arch/blackfin/mach-bf561/dma.c index c938c3c7355..8ffdd6b4a24 100644 --- a/arch/blackfin/mach-bf561/dma.c +++ b/arch/blackfin/mach-bf561/dma.c @@ -11,7 +11,7 @@ #include <asm/blackfin.h> #include <asm/dma.h> -struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { +struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { (struct dma_register *) DMA1_0_NEXT_DESC_PTR, (struct dma_register *) DMA1_1_NEXT_DESC_PTR, (struct dma_register *) DMA1_2_NEXT_DESC_PTR, @@ -36,14 +36,14 @@ struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { (struct dma_register *) DMA2_9_NEXT_DESC_PTR, (struct dma_register *) DMA2_10_NEXT_DESC_PTR, (struct dma_register *) DMA2_11_NEXT_DESC_PTR, - (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR, - (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR, - (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR, - (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR, - (struct dma_register *) MDMA2_D0_NEXT_DESC_PTR, - (struct dma_register *) MDMA2_S0_NEXT_DESC_PTR, - (struct dma_register *) MDMA2_D1_NEXT_DESC_PTR, - (struct dma_register *) MDMA2_S1_NEXT_DESC_PTR, + (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, + (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, + (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, + (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, + (struct dma_register *) MDMA_D2_NEXT_DESC_PTR, + (struct dma_register *) MDMA_S2_NEXT_DESC_PTR, + (struct dma_register *) MDMA_D3_NEXT_DESC_PTR, + (struct dma_register *) MDMA_S3_NEXT_DESC_PTR, (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR, (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR, (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR, diff --git a/arch/blackfin/mach-bf561/hotplug.c b/arch/blackfin/mach-bf561/hotplug.c index c95169b612d..4cd3b28cd04 100644 --- a/arch/blackfin/mach-bf561/hotplug.c +++ b/arch/blackfin/mach-bf561/hotplug.c @@ -6,7 +6,9 @@ */ #include <asm/blackfin.h> +#include <asm/irq.h> #include <asm/smp.h> + #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) int hotplug_coreb; diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h index 4c108c99cb6..6a3499b0209 100644 --- a/arch/blackfin/mach-bf561/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h @@ -181,7 +181,11 @@ /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ #define ANOMALY_05000254 (__SILICON_REVISION__ > 3) /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ -#define ANOMALY_05000257 (__SILICON_REVISION__ < 5) +/* Tempoary work around for kgdb bug 6333 in SMP kernel. It looks coreb hangs in exception + * without handling anomaly 05000257 properly on bf561 v0.5. This work around may change + * after the behavior and the root cause are confirmed with hardware team. + */ +#define ANOMALY_05000257 (__SILICON_REVISION__ < 5 || (__SILICON_REVISION__ == 5 && CONFIG_SMP)) /* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ #define ANOMALY_05000258 (__SILICON_REVISION__ < 5) /* ICPLB_STATUS MMR Register May Be Corrupted */ diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h new file mode 100644 index 00000000000..08072c86d5d --- /dev/null +++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h @@ -0,0 +1,14 @@ +/* + * mach/bfin_serial.h - Blackfin UART/Serial definitions + * + * Copyright 2006-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_MACH_SERIAL_H__ +#define __BFIN_MACH_SERIAL_H__ + +#define BFIN_UART_NR_PORTS 1 + +#endif diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h index e33e158bc16..3a6947456cf 100644 --- a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h @@ -4,36 +4,9 @@ * Licensed under the GPL-2 or later. */ -#include <linux/serial.h> #include <asm/dma.h> #include <asm/portmux.h> -#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) -#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) -#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) -#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) -#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) -#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) -#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) - -#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) -#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) -#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) -#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) -#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) -#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) -#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) -#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) - -#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) -#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) - -#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) -#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) -#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) -#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) -#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) - #ifdef CONFIG_BFIN_UART0_CTSRTS # define CONFIG_SERIAL_BFIN_CTSRTS # ifndef CONFIG_UART0_CTS_PIN @@ -44,51 +17,6 @@ # endif #endif -#define BFIN_UART_TX_FIFO_SIZE 2 - -struct bfin_serial_port { - struct uart_port port; - unsigned int old_status; - int status_irq; - unsigned int lsr; -#ifdef CONFIG_SERIAL_BFIN_DMA - int tx_done; - int tx_count; - struct circ_buf rx_dma_buf; - struct timer_list rx_dma_timer; - int rx_dma_nrows; - unsigned int tx_dma_channel; - unsigned int rx_dma_channel; - struct work_struct tx_dma_workqueue; -#else -# if ANOMALY_05000363 - unsigned int anomaly_threshold; -# endif -#endif -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - struct timer_list cts_timer; - int cts_pin; - int rts_pin; -#endif -}; - -/* The hardware clears the LSR bits upon read, so we need to cache - * some of the more fun bits in software so they don't get lost - * when checking the LSR in other code paths (TX). - */ -static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart) -{ - unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR); - uart->lsr |= (lsr & (BI|FE|PE|OE)); - return lsr | uart->lsr; -} - -static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) -{ - uart->lsr = 0; - bfin_write16(uart->port.membase + OFFSET_LSR, -1); -} - struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; @@ -120,3 +48,5 @@ struct bfin_serial_res bfin_serial_resource[] = { }; #define DRIVER_NAME "bfin-uart" + +#include <asm/bfin_serial.h> diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h index 6c7dc58c018..dc470534c08 100644 --- a/arch/blackfin/mach-bf561/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h @@ -1,5 +1,5 @@ /* - * Copyright 2005-2009 Analog Devices Inc. + * Copyright 2005-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -10,11 +10,14 @@ #define BF561_FAMILY #include "bf561.h" -#include "defBF561.h" #include "anomaly.h" -#if !defined(__ASSEMBLY__) -#include "cdefBF561.h" +#include <asm/def_LPBlackfin.h> +#include "defBF561.h" + +#ifndef __ASSEMBLY__ +# include <asm/cdef_LPBlackfin.h> +# include "cdefBF561.h" #endif #define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D() @@ -35,19 +38,4 @@ #define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x)) #define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val) -#define BFIN_UART_NR_PORTS 1 - -#define OFFSET_THR 0x00 /* Transmit Holding register */ -#define OFFSET_RBR 0x00 /* Receive Buffer register */ -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_IER 0x04 /* Interrupt Enable Register */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_GCTL 0x24 /* Global Control Register */ - #endif /* _MACH_BLACKFIN_H_ */ diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h index 2bab9915249..75333159720 100644 --- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h @@ -1,5 +1,5 @@ /* - * Copyright 2005-2009 Analog Devices Inc. + * Copyright 2005-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -7,14 +7,6 @@ #ifndef _CDEF_BF561_H #define _CDEF_BF561_H -#include <asm/blackfin.h> - -/* include all Core registers and bit definitions */ -#include "defBF561.h" - -/*include core specific register pointer definitions*/ -#include <asm/cdef_LPBlackfin.h> - /*********************************************************************************** */ /* System MMR Register Map */ /*********************************************************************************** */ @@ -523,14 +515,14 @@ #define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME) #define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME,val) /*DMA traffic control registers */ -#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER) -#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER,val) -#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT) -#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT,val) -#define bfin_read_DMA2_TC_PER() bfin_read16(DMA2_TC_PER) -#define bfin_write_DMA2_TC_PER(val) bfin_write16(DMA2_TC_PER,val) -#define bfin_read_DMA2_TC_CNT() bfin_read16(DMA2_TC_CNT) -#define bfin_write_DMA2_TC_CNT(val) bfin_write16(DMA2_TC_CNT,val) +#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER) +#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER,val) +#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT) +#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT,val) +#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER) +#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER,val) +#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT) +#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT,val) /* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ #define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG) #define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG,val) @@ -845,110 +837,110 @@ #define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP) #define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val) /* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ -#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG) -#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG,val) -#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_read32(MDMA1_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D0_NEXT_DESC_PTR,val) -#define bfin_read_MDMA1_D0_START_ADDR() bfin_read32(MDMA1_D0_START_ADDR) -#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_write32(MDMA1_D0_START_ADDR,val) -#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT) -#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT,val) -#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT) -#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT,val) -#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY) -#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY,val) -#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY) -#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY,val) -#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_read32(MDMA1_D0_CURR_DESC_PTR) -#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_write32(MDMA1_D0_CURR_DESC_PTR,val) -#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_read32(MDMA1_D0_CURR_ADDR) -#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_write32(MDMA1_D0_CURR_ADDR,val) -#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT) -#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT,val) -#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT) -#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT,val) -#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS) -#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS,val) -#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP,val) -#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG) -#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG,val) -#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_read32(MDMA1_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S0_NEXT_DESC_PTR,val) -#define bfin_read_MDMA1_S0_START_ADDR() bfin_read32(MDMA1_S0_START_ADDR) -#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_write32(MDMA1_S0_START_ADDR,val) -#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT) -#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT,val) -#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT) -#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT,val) -#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY) -#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY,val) -#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY) -#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY,val) -#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_read32(MDMA1_S0_CURR_DESC_PTR) -#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_write32(MDMA1_S0_CURR_DESC_PTR,val) -#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_read32(MDMA1_S0_CURR_ADDR) -#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_write32(MDMA1_S0_CURR_ADDR,val) -#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT) -#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT,val) -#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT) -#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT,val) -#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS) -#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS,val) -#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP,val) -#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG) -#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG,val) -#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_read32(MDMA1_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D1_NEXT_DESC_PTR,val) -#define bfin_read_MDMA1_D1_START_ADDR() bfin_read32(MDMA1_D1_START_ADDR) -#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_write32(MDMA1_D1_START_ADDR,val) -#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT) -#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT,val) -#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT) -#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT,val) -#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY) -#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY,val) -#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY) -#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY,val) -#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_read32(MDMA1_D1_CURR_DESC_PTR) -#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_write32(MDMA1_D1_CURR_DESC_PTR,val) -#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_read32(MDMA1_D1_CURR_ADDR) -#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_write32(MDMA1_D1_CURR_ADDR,val) -#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT) -#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT,val) -#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT) -#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT,val) -#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS) -#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS,val) -#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP,val) -#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG) -#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG,val) -#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_read32(MDMA1_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S1_NEXT_DESC_PTR,val) -#define bfin_read_MDMA1_S1_START_ADDR() bfin_read32(MDMA1_S1_START_ADDR) -#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_write32(MDMA1_S1_START_ADDR,val) -#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT) -#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT,val) -#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT) -#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT,val) -#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY) -#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY,val) -#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY) -#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY,val) -#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_read32(MDMA1_S1_CURR_DESC_PTR) -#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_write32(MDMA1_S1_CURR_DESC_PTR,val) -#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_read32(MDMA1_S1_CURR_ADDR) -#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_write32(MDMA1_S1_CURR_ADDR,val) -#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT) -#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT,val) -#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT) -#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT,val) -#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS) -#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS,val) -#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP,val) +#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) +#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG,val) +#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR) +#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR,val) +#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR) +#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR,val) +#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) +#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT,val) +#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) +#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT,val) +#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) +#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY,val) +#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) +#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY,val) +#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR) +#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR,val) +#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR) +#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR,val) +#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT) +#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT,val) +#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) +#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT,val) +#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) +#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS,val) +#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) +#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP,val) +#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) +#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG,val) +#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR) +#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR,val) +#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR) +#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR,val) +#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) +#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT,val) +#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) +#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT,val) +#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) +#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY,val) +#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) +#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY,val) +#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR) +#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR,val) +#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR) +#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR,val) +#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT) +#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT,val) +#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT) +#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT,val) +#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) +#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS,val) +#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) +#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP,val) +#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) +#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG,val) +#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR) +#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR,val) +#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR) +#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR,val) +#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) +#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT,val) +#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) +#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT,val) +#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) +#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY,val) +#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) +#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY,val) +#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR) +#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR,val) +#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR) +#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR,val) +#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT) +#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT,val) +#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) +#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT,val) +#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) +#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS,val) +#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) +#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP,val) +#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) +#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG,val) +#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR) +#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR,val) +#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR) +#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR,val) +#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) +#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT,val) +#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) +#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT,val) +#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) +#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY,val) +#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) +#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY,val) +#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR) +#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR,val) +#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR) +#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR,val) +#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT) +#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT,val) +#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT) +#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT,val) +#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) +#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS,val) +#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) +#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP,val) /* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ #define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG) #define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG,val) @@ -1263,110 +1255,110 @@ #define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP) #define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val) /* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ -#define bfin_read_MDMA2_D0_CONFIG() bfin_read16(MDMA2_D0_CONFIG) -#define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG,val) -#define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_read32(MDMA2_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D0_NEXT_DESC_PTR,val) -#define bfin_read_MDMA2_D0_START_ADDR() bfin_read32(MDMA2_D0_START_ADDR) -#define bfin_write_MDMA2_D0_START_ADDR(val) bfin_write32(MDMA2_D0_START_ADDR,val) -#define bfin_read_MDMA2_D0_X_COUNT() bfin_read16(MDMA2_D0_X_COUNT) -#define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT,val) -#define bfin_read_MDMA2_D0_Y_COUNT() bfin_read16(MDMA2_D0_Y_COUNT) -#define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT,val) -#define bfin_read_MDMA2_D0_X_MODIFY() bfin_read16(MDMA2_D0_X_MODIFY) -#define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY,val) -#define bfin_read_MDMA2_D0_Y_MODIFY() bfin_read16(MDMA2_D0_Y_MODIFY) -#define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY,val) -#define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_read32(MDMA2_D0_CURR_DESC_PTR) -#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_write32(MDMA2_D0_CURR_DESC_PTR,val) -#define bfin_read_MDMA2_D0_CURR_ADDR() bfin_read32(MDMA2_D0_CURR_ADDR) -#define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_write32(MDMA2_D0_CURR_ADDR,val) -#define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT) -#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT,val) -#define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT) -#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT,val) -#define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS) -#define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS,val) -#define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP,val) -#define bfin_read_MDMA2_S0_CONFIG() bfin_read16(MDMA2_S0_CONFIG) -#define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG,val) -#define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_read32(MDMA2_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S0_NEXT_DESC_PTR,val) -#define bfin_read_MDMA2_S0_START_ADDR() bfin_read32(MDMA2_S0_START_ADDR) -#define bfin_write_MDMA2_S0_START_ADDR(val) bfin_write32(MDMA2_S0_START_ADDR,val) -#define bfin_read_MDMA2_S0_X_COUNT() bfin_read16(MDMA2_S0_X_COUNT) -#define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT,val) -#define bfin_read_MDMA2_S0_Y_COUNT() bfin_read16(MDMA2_S0_Y_COUNT) -#define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT,val) -#define bfin_read_MDMA2_S0_X_MODIFY() bfin_read16(MDMA2_S0_X_MODIFY) -#define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY,val) -#define bfin_read_MDMA2_S0_Y_MODIFY() bfin_read16(MDMA2_S0_Y_MODIFY) -#define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY,val) -#define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_read32(MDMA2_S0_CURR_DESC_PTR) -#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_write32(MDMA2_S0_CURR_DESC_PTR,val) -#define bfin_read_MDMA2_S0_CURR_ADDR() bfin_read32(MDMA2_S0_CURR_ADDR) -#define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_write32(MDMA2_S0_CURR_ADDR,val) -#define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT) -#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT,val) -#define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT) -#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT,val) -#define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS) -#define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS,val) -#define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP,val) -#define bfin_read_MDMA2_D1_CONFIG() bfin_read16(MDMA2_D1_CONFIG) -#define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG,val) -#define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_read32(MDMA2_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D1_NEXT_DESC_PTR,val) -#define bfin_read_MDMA2_D1_START_ADDR() bfin_read32(MDMA2_D1_START_ADDR) -#define bfin_write_MDMA2_D1_START_ADDR(val) bfin_write32(MDMA2_D1_START_ADDR,val) -#define bfin_read_MDMA2_D1_X_COUNT() bfin_read16(MDMA2_D1_X_COUNT) -#define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT,val) -#define bfin_read_MDMA2_D1_Y_COUNT() bfin_read16(MDMA2_D1_Y_COUNT) -#define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT,val) -#define bfin_read_MDMA2_D1_X_MODIFY() bfin_read16(MDMA2_D1_X_MODIFY) -#define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY,val) -#define bfin_read_MDMA2_D1_Y_MODIFY() bfin_read16(MDMA2_D1_Y_MODIFY) -#define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY,val) -#define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_read32(MDMA2_D1_CURR_DESC_PTR) -#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_write32(MDMA2_D1_CURR_DESC_PTR,val) -#define bfin_read_MDMA2_D1_CURR_ADDR() bfin_read32(MDMA2_D1_CURR_ADDR) -#define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_write32(MDMA2_D1_CURR_ADDR,val) -#define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT) -#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT,val) -#define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT) -#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT,val) -#define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS) -#define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS,val) -#define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP,val) -#define bfin_read_MDMA2_S1_CONFIG() bfin_read16(MDMA2_S1_CONFIG) -#define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG,val) -#define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_read32(MDMA2_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S1_NEXT_DESC_PTR,val) -#define bfin_read_MDMA2_S1_START_ADDR() bfin_read32(MDMA2_S1_START_ADDR) -#define bfin_write_MDMA2_S1_START_ADDR(val) bfin_write32(MDMA2_S1_START_ADDR,val) -#define bfin_read_MDMA2_S1_X_COUNT() bfin_read16(MDMA2_S1_X_COUNT) -#define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT,val) -#define bfin_read_MDMA2_S1_Y_COUNT() bfin_read16(MDMA2_S1_Y_COUNT) -#define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT,val) -#define bfin_read_MDMA2_S1_X_MODIFY() bfin_read16(MDMA2_S1_X_MODIFY) -#define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY,val) -#define bfin_read_MDMA2_S1_Y_MODIFY() bfin_read16(MDMA2_S1_Y_MODIFY) -#define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY,val) -#define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_read32(MDMA2_S1_CURR_DESC_PTR) -#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_write32(MDMA2_S1_CURR_DESC_PTR,val) -#define bfin_read_MDMA2_S1_CURR_ADDR() bfin_read32(MDMA2_S1_CURR_ADDR) -#define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_write32(MDMA2_S1_CURR_ADDR,val) -#define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT) -#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT,val) -#define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT) -#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT,val) -#define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS) -#define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS,val) -#define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP,val) +#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) +#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val) +#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) +#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val) +#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) +#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val) +#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) +#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val) +#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) +#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val) +#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) +#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val) +#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) +#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val) +#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) +#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val) +#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) +#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val) +#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) +#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val) +#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) +#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val) +#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) +#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val) +#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) +#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val) +#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) +#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val) +#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) +#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val) +#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) +#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val) +#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) +#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val) +#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) +#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val) +#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) +#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val) +#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) +#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val) +#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) +#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val) +#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) +#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val) +#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) +#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val) +#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) +#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val) +#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) +#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val) +#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) +#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val) +#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) +#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val) +#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) +#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val) +#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) +#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val) +#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) +#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val) +#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) +#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val) +#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) +#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val) +#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) +#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val) +#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) +#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val) +#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) +#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val) +#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) +#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val) +#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) +#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val) +#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) +#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val) +#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) +#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val) +#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) +#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val) +#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) +#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val) +#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) +#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val) +#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) +#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val) +#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) +#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val) +#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) +#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val) +#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) +#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val) +#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) +#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val) +#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) +#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val) +#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) +#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val) +#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) +#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val) +#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) +#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val) +#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) +#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val) /* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ #define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG) #define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG,val) @@ -1465,65 +1457,4 @@ #define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS) #define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS,val) -#define bfin_read_MDMA_S0_CONFIG() bfin_read_MDMA1_S0_CONFIG() -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA1_S0_CONFIG(val) -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read_MDMA1_S0_IRQ_STATUS() -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA1_S0_IRQ_STATUS(val) -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read_MDMA1_S0_X_MODIFY() -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA1_S0_X_MODIFY(val) -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read_MDMA1_S0_Y_MODIFY() -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA1_S0_Y_MODIFY(val) -#define bfin_read_MDMA_S0_X_COUNT() bfin_read_MDMA1_S0_X_COUNT() -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA1_S0_X_COUNT(val) -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read_MDMA1_S0_Y_COUNT() -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA1_S0_Y_COUNT(val) -#define bfin_read_MDMA_S0_START_ADDR() bfin_read_MDMA1_S0_START_ADDR() -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA1_S0_START_ADDR(val) -#define bfin_read_MDMA_D0_CONFIG() bfin_read_MDMA1_D0_CONFIG() -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA1_D0_CONFIG(val) -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read_MDMA1_D0_IRQ_STATUS() -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA1_D0_IRQ_STATUS(val) -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read_MDMA1_D0_X_MODIFY() -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA1_D0_X_MODIFY(val) -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read_MDMA1_D0_Y_MODIFY() -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA1_D0_Y_MODIFY(val) -#define bfin_read_MDMA_D0_X_COUNT() bfin_read_MDMA1_D0_X_COUNT() -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA1_D0_X_COUNT(val) -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read_MDMA1_D0_Y_COUNT() -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA1_D0_Y_COUNT(val) -#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR() -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val) - -#define bfin_read_MDMA_S1_CONFIG() bfin_read_MDMA1_S1_CONFIG() -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write_MDMA1_S1_CONFIG(val) -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read_MDMA1_S1_IRQ_STATUS() -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write_MDMA1_S1_IRQ_STATUS(val) -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read_MDMA1_S1_X_MODIFY() -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write_MDMA1_S1_X_MODIFY(val) -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read_MDMA1_S1_Y_MODIFY() -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write_MDMA1_S1_Y_MODIFY(val) -#define bfin_read_MDMA_S1_X_COUNT() bfin_read_MDMA1_S1_X_COUNT() -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write_MDMA1_S1_X_COUNT(val) -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read_MDMA1_S1_Y_COUNT() -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write_MDMA1_S1_Y_COUNT(val) -#define bfin_read_MDMA_S1_START_ADDR() bfin_read_MDMA1_S1_START_ADDR() -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write_MDMA1_S1_START_ADDR(val) -#define bfin_read_MDMA_D1_CONFIG() bfin_read_MDMA1_D1_CONFIG() -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write_MDMA1_D1_CONFIG(val) -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read_MDMA1_D1_IRQ_STATUS() -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write_MDMA1_D1_IRQ_STATUS(val) -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read_MDMA1_D1_X_MODIFY() -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write_MDMA1_D1_X_MODIFY(val) -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read_MDMA1_D1_Y_MODIFY() -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write_MDMA1_D1_Y_MODIFY(val) -#define bfin_read_MDMA_D1_X_COUNT() bfin_read_MDMA1_D1_X_COUNT() -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write_MDMA1_D1_X_COUNT(val) -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read_MDMA1_D1_Y_COUNT() -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write_MDMA1_D1_Y_COUNT(val) -#define bfin_read_MDMA_D1_START_ADDR() bfin_read_MDMA1_D1_START_ADDR() -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA1_D1_START_ADDR(val) - -/* These need to be last due to the cdef/linux inter-dependencies */ -#include <asm/irq.h> - #endif /* _CDEF_BF561_H */ diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h index 79e048d452e..71e805ea74e 100644 --- a/arch/blackfin/mach-bf561/include/mach/defBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h @@ -1,18 +1,11 @@ /* - * Copyright 2005-2009 Analog Devices Inc. + * Copyright 2005-2010 Analog Devices Inc. * * Licensed under the ADI BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF561_H #define _DEF_BF561_H -/* -#if !defined(__ADSPBF561__) -#warning defBF561.h should only be included for BF561 chip. -#endif -*/ -/* include all Core registers and bit definitions */ -#include <asm/def_LPBlackfin.h> /*********************************************************************************** */ /* System MMR Register Map */ @@ -311,10 +304,10 @@ #define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */ /*DMA traffic control registers */ -#define DMA1_TC_PER 0xFFC01B0C /* Traffic control periods */ -#define DMA1_TC_CNT 0xFFC01B10 /* Traffic control current counts */ -#define DMA2_TC_PER 0xFFC00B0C /* Traffic control periods */ -#define DMA2_TC_CNT 0xFFC00B10 /* Traffic control current counts */ +#define DMAC0_TC_PER 0xFFC00B0C /* Traffic control periods */ +#define DMAC0_TC_CNT 0xFFC00B10 /* Traffic control current counts */ +#define DMAC1_TC_PER 0xFFC01B0C /* Traffic control periods */ +#define DMAC1_TC_CNT 0xFFC01B10 /* Traffic control current counts */ /* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ #define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */ @@ -486,61 +479,61 @@ #define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */ /* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ -#define MDMA1_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */ -#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */ -#define MDMA1_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */ -#define MDMA1_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */ -#define MDMA1_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */ -#define MDMA1_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */ -#define MDMA1_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */ -#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */ -#define MDMA1_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */ -#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */ -#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */ -#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */ -#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */ - -#define MDMA1_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */ -#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */ -#define MDMA1_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */ -#define MDMA1_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */ -#define MDMA1_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */ -#define MDMA1_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */ -#define MDMA1_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */ -#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */ -#define MDMA1_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */ -#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */ -#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */ -#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */ -#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */ - -#define MDMA1_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */ -#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */ -#define MDMA1_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */ -#define MDMA1_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */ -#define MDMA1_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */ -#define MDMA1_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */ -#define MDMA1_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */ -#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */ -#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */ -#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */ -#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */ -#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */ -#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */ - -#define MDMA1_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */ -#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */ -#define MDMA1_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */ -#define MDMA1_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */ -#define MDMA1_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */ -#define MDMA1_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */ -#define MDMA1_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */ -#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */ -#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */ -#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */ -#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */ -#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */ -#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */ +#define MDMA_D2_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */ +#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */ +#define MDMA_D2_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */ +#define MDMA_D2_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */ +#define MDMA_D2_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */ +#define MDMA_D2_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */ +#define MDMA_D2_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */ +#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */ +#define MDMA_D2_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */ +#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */ +#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */ +#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */ +#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */ + +#define MDMA_S2_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */ +#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */ +#define MDMA_S2_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */ +#define MDMA_S2_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */ +#define MDMA_S2_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */ +#define MDMA_S2_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */ +#define MDMA_S2_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */ +#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */ +#define MDMA_S2_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */ +#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */ +#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */ +#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */ +#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */ + +#define MDMA_D3_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */ +#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */ +#define MDMA_D3_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */ +#define MDMA_D3_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */ +#define MDMA_D3_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */ +#define MDMA_D3_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */ +#define MDMA_D3_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */ +#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */ +#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */ +#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */ +#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */ +#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */ +#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */ + +#define MDMA_S3_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */ +#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */ +#define MDMA_S3_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */ +#define MDMA_S3_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */ +#define MDMA_S3_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */ +#define MDMA_S3_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */ +#define MDMA_S3_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */ +#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */ +#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */ +#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */ +#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */ +#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */ +#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */ /* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ #define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */ @@ -712,117 +705,61 @@ #define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */ /* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ -#define MDMA2_D0_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */ -#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */ -#define MDMA2_D0_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */ -#define MDMA2_D0_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */ -#define MDMA2_D0_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */ -#define MDMA2_D0_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */ -#define MDMA2_D0_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */ -#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */ -#define MDMA2_D0_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */ -#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */ -#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */ -#define MDMA2_D0_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */ -#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */ - -#define MDMA2_S0_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */ -#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */ -#define MDMA2_S0_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */ -#define MDMA2_S0_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */ -#define MDMA2_S0_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */ -#define MDMA2_S0_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */ -#define MDMA2_S0_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */ -#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */ -#define MDMA2_S0_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */ -#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */ -#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */ -#define MDMA2_S0_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */ -#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */ - -#define MDMA2_D1_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */ -#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */ -#define MDMA2_D1_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */ -#define MDMA2_D1_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */ -#define MDMA2_D1_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */ -#define MDMA2_D1_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */ -#define MDMA2_D1_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */ -#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */ -#define MDMA2_D1_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */ -#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */ -#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */ -#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */ -#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */ - -#define MDMA2_S1_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */ -#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */ -#define MDMA2_S1_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */ -#define MDMA2_S1_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */ -#define MDMA2_S1_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */ -#define MDMA2_S1_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */ -#define MDMA2_S1_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */ -#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */ -#define MDMA2_S1_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */ -#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */ -#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */ -#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */ -#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */ - -#define MDMA_D0_NEXT_DESC_PTR MDMA1_D0_NEXT_DESC_PTR -#define MDMA_D0_START_ADDR MDMA1_D0_START_ADDR -#define MDMA_D0_CONFIG MDMA1_D0_CONFIG -#define MDMA_D0_X_COUNT MDMA1_D0_X_COUNT -#define MDMA_D0_X_MODIFY MDMA1_D0_X_MODIFY -#define MDMA_D0_Y_COUNT MDMA1_D0_Y_COUNT -#define MDMA_D0_Y_MODIFY MDMA1_D0_Y_MODIFY -#define MDMA_D0_CURR_DESC_PTR MDMA1_D0_CURR_DESC_PTR -#define MDMA_D0_CURR_ADDR MDMA1_D0_CURR_ADDR -#define MDMA_D0_IRQ_STATUS MDMA1_D0_IRQ_STATUS -#define MDMA_D0_PERIPHERAL_MAP MDMA1_D0_PERIPHERAL_MAP -#define MDMA_D0_CURR_X_COUNT MDMA1_D0_CURR_X_COUNT -#define MDMA_D0_CURR_Y_COUNT MDMA1_D0_CURR_Y_COUNT - -#define MDMA_S0_NEXT_DESC_PTR MDMA1_S0_NEXT_DESC_PTR -#define MDMA_S0_START_ADDR MDMA1_S0_START_ADDR -#define MDMA_S0_CONFIG MDMA1_S0_CONFIG -#define MDMA_S0_X_COUNT MDMA1_S0_X_COUNT -#define MDMA_S0_X_MODIFY MDMA1_S0_X_MODIFY -#define MDMA_S0_Y_COUNT MDMA1_S0_Y_COUNT -#define MDMA_S0_Y_MODIFY MDMA1_S0_Y_MODIFY -#define MDMA_S0_CURR_DESC_PTR MDMA1_S0_CURR_DESC_PTR -#define MDMA_S0_CURR_ADDR MDMA1_S0_CURR_ADDR -#define MDMA_S0_IRQ_STATUS MDMA1_S0_IRQ_STATUS -#define MDMA_S0_PERIPHERAL_MAP MDMA1_S0_PERIPHERAL_MAP -#define MDMA_S0_CURR_X_COUNT MDMA1_S0_CURR_X_COUNT -#define MDMA_S0_CURR_Y_COUNT MDMA1_S0_CURR_Y_COUNT - -#define MDMA_D1_NEXT_DESC_PTR MDMA1_D1_NEXT_DESC_PTR -#define MDMA_D1_START_ADDR MDMA1_D1_START_ADDR -#define MDMA_D1_CONFIG MDMA1_D1_CONFIG -#define MDMA_D1_X_COUNT MDMA1_D1_X_COUNT -#define MDMA_D1_X_MODIFY MDMA1_D1_X_MODIFY -#define MDMA_D1_Y_COUNT MDMA1_D1_Y_COUNT -#define MDMA_D1_Y_MODIFY MDMA1_D1_Y_MODIFY -#define MDMA_D1_CURR_DESC_PTR MDMA1_D1_CURR_DESC_PTR -#define MDMA_D1_CURR_ADDR MDMA1_D1_CURR_ADDR -#define MDMA_D1_IRQ_STATUS MDMA1_D1_IRQ_STATUS -#define MDMA_D1_PERIPHERAL_MAP MDMA1_D1_PERIPHERAL_MAP -#define MDMA_D1_CURR_X_COUNT MDMA1_D1_CURR_X_COUNT -#define MDMA_D1_CURR_Y_COUNT MDMA1_D1_CURR_Y_COUNT - -#define MDMA_S1_NEXT_DESC_PTR MDMA1_S1_NEXT_DESC_PTR -#define MDMA_S1_START_ADDR MDMA1_S1_START_ADDR -#define MDMA_S1_CONFIG MDMA1_S1_CONFIG -#define MDMA_S1_X_COUNT MDMA1_S1_X_COUNT -#define MDMA_S1_X_MODIFY MDMA1_S1_X_MODIFY -#define MDMA_S1_Y_COUNT MDMA1_S1_Y_COUNT -#define MDMA_S1_Y_MODIFY MDMA1_S1_Y_MODIFY -#define MDMA_S1_CURR_DESC_PTR MDMA1_S1_CURR_DESC_PTR -#define MDMA_S1_CURR_ADDR MDMA1_S1_CURR_ADDR -#define MDMA_S1_IRQ_STATUS MDMA1_S1_IRQ_STATUS -#define MDMA_S1_PERIPHERAL_MAP MDMA1_S1_PERIPHERAL_MAP -#define MDMA_S1_CURR_X_COUNT MDMA1_S1_CURR_X_COUNT -#define MDMA_S1_CURR_Y_COUNT MDMA1_S1_CURR_Y_COUNT +#define MDMA_D0_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */ +#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */ +#define MDMA_D0_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */ +#define MDMA_D0_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */ +#define MDMA_D0_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */ +#define MDMA_D0_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */ +#define MDMA_D0_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */ +#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */ +#define MDMA_D0_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */ +#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */ +#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */ +#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */ +#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */ + +#define MDMA_S0_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */ +#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */ +#define MDMA_S0_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */ +#define MDMA_S0_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */ +#define MDMA_S0_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */ +#define MDMA_S0_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */ +#define MDMA_S0_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */ +#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */ +#define MDMA_S0_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */ +#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */ +#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */ +#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */ +#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */ + +#define MDMA_D1_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */ +#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */ +#define MDMA_D1_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */ +#define MDMA_D1_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */ +#define MDMA_D1_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */ +#define MDMA_D1_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */ +#define MDMA_D1_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */ +#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */ +#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */ +#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */ +#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */ +#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */ +#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */ + +#define MDMA_S1_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */ +#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */ +#define MDMA_S1_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */ +#define MDMA_S1_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */ +#define MDMA_S1_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */ +#define MDMA_S1_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */ +#define MDMA_S1_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */ +#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */ +#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */ +#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */ +#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */ +#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */ +#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */ /* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ #define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */ @@ -927,83 +864,6 @@ #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ -/* ***************************** UART CONTROLLER MASKS ********************** */ - -/* UART_LCR Register */ - -#define DLAB 0x80 -#define SB 0x40 -#define STP 0x20 -#define EPS 0x10 -#define PEN 0x08 -#define STB 0x04 -#define WLS(x) ((x-5) & 0x03) - -#define DLAB_P 0x07 -#define SB_P 0x06 -#define STP_P 0x05 -#define EPS_P 0x04 -#define PEN_P 0x03 -#define STB_P 0x02 -#define WLS_P1 0x01 -#define WLS_P0 0x00 - -/* UART_MCR Register */ -#define LOOP_ENA 0x10 -#define LOOP_ENA_P 0x04 - -/* UART_LSR Register */ -#define TEMT 0x40 -#define THRE 0x20 -#define BI 0x10 -#define FE 0x08 -#define PE 0x04 -#define OE 0x02 -#define DR 0x01 - -#define TEMP_P 0x06 -#define THRE_P 0x05 -#define BI_P 0x04 -#define FE_P 0x03 -#define PE_P 0x02 -#define OE_P 0x01 -#define DR_P 0x00 - -/* UART_IER Register */ -#define ELSI 0x04 -#define ETBEI 0x02 -#define ERBFI 0x01 - -#define ELSI_P 0x02 -#define ETBEI_P 0x01 -#define ERBFI_P 0x00 - -/* UART_IIR Register */ -#define STATUS(x) ((x << 1) & 0x06) -#define NINT 0x01 -#define STATUS_P1 0x02 -#define STATUS_P0 0x01 -#define NINT_P 0x00 -#define IIR_TX_READY 0x02 /* UART_THR empty */ -#define IIR_RX_READY 0x04 /* Receive data ready */ -#define IIR_LINE_CHANGE 0x06 /* Receive line status */ -#define IIR_STATUS 0x06 - -/* UART_GCTL Register */ -#define FFE 0x20 -#define FPE 0x10 -#define RPOLC 0x08 -#define TPOLC 0x04 -#define IREN 0x02 -#define UCEN 0x01 - -#define FFE_P 0x05 -#define FPE_P 0x04 -#define RPOLC_P 0x03 -#define TPOLC_P 0x02 -#define IREN_P 0x01 -#define UCEN_P 0x00 - /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ /* PPI_CONTROL Masks */ @@ -1230,44 +1090,6 @@ #define ERR_TYP_P0 0x0E #define ERR_TYP_P1 0x0F -/*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */ - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */ -#define PF0_P 0 -#define PF1_P 1 -#define PF2_P 2 -#define PF3_P 3 -#define PF4_P 4 -#define PF5_P 5 -#define PF6_P 6 -#define PF7_P 7 -#define PF8_P 8 -#define PF9_P 9 -#define PF10_P 10 -#define PF11_P 11 -#define PF12_P 12 -#define PF13_P 13 -#define PF14_P 14 -#define PF15_P 15 - /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ /* AMGCTL Masks */ diff --git a/arch/blackfin/mach-bf561/include/mach/gpio.h b/arch/blackfin/mach-bf561/include/mach/gpio.h index 4f8aa5d0880..57d5eab59fa 100644 --- a/arch/blackfin/mach-bf561/include/mach/gpio.h +++ b/arch/blackfin/mach-bf561/include/mach/gpio.h @@ -62,4 +62,6 @@ #define PORT_FIO1 GPIO_16 #define PORT_FIO2 GPIO_32 +#include <mach-common/ports-f.h> + #endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h index 5b96ea549a0..4cc91995f78 100644 --- a/arch/blackfin/mach-bf561/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h @@ -106,7 +106,7 @@ #define COREA_L1_SCRATCH_START 0xFFB00000 #define COREB_L1_SCRATCH_START 0xFF700000 -#ifdef __ASSEMBLY__ +#ifdef CONFIG_SMP /* * The following macros both return the address of the PDA for the @@ -121,8 +121,7 @@ * is allowed to use the specified Dreg for determining the PDA * address to be returned into Preg. */ -#ifdef CONFIG_SMP -#define GET_PDA_SAFE(preg) \ +# define GET_PDA_SAFE(preg) \ preg.l = lo(DSPID); \ preg.h = hi(DSPID); \ preg = [preg]; \ @@ -158,7 +157,7 @@ preg = [preg]; \ 4: -#define GET_PDA(preg, dreg) \ +# define GET_PDA(preg, dreg) \ preg.l = lo(DSPID); \ preg.h = hi(DSPID); \ dreg = [preg]; \ @@ -169,13 +168,17 @@ preg = [preg]; \ 1: \ -#define GET_CPUID(preg, dreg) \ +# define GET_CPUID(preg, dreg) \ preg.l = lo(DSPID); \ preg.h = hi(DSPID); \ dreg = [preg]; \ dreg = ROT dreg BY -1; \ dreg = CC; +# ifndef __ASSEMBLY__ + +# include <asm/processor.h> + static inline unsigned long get_l1_scratch_start_cpu(int cpu) { return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START; @@ -210,8 +213,7 @@ static inline unsigned long get_l1_data_b_start(void) return get_l1_data_b_start_cpu(blackfin_core_id()); } +# endif /* __ASSEMBLY__ */ #endif /* CONFIG_SMP */ -#endif /* __ASSEMBLY__ */ - #endif diff --git a/arch/blackfin/mach-bf561/include/mach/pll.h b/arch/blackfin/mach-bf561/include/mach/pll.h index f2b1fbdb8e7..7977db2f1c1 100644 --- a/arch/blackfin/mach-bf561/include/mach/pll.h +++ b/arch/blackfin/mach-bf561/include/mach/pll.h @@ -1,5 +1,5 @@ /* - * Copyright 2005-2009 Analog Devices Inc. + * Copyright 2005-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -7,57 +7,48 @@ #ifndef _MACH_PLL_H #define _MACH_PLL_H +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_SMP + #include <asm/blackfin.h> #include <asm/irqflags.h> +#include <mach/irq.h> + +#define SUPPLE_0_WAKEUP ((IRQ_SUPPLE_0 - (IRQ_CORETMR + 1)) % 32) -/* Writing to PLL_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_PLL_CTL(unsigned int val) +static inline void +bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2) { - unsigned long flags, iwr0, iwr1; - - if (val == bfin_read_PLL_CTL()) - return; - - flags = hard_local_irq_save(); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SICA_IWR0); - iwr1 = bfin_read32(SICA_IWR1); - /* Only allow PPL Wakeup) */ - bfin_write32(SICA_IWR0, IWR_ENABLE(0)); - bfin_write32(SICA_IWR1, 0); - - bfin_write16(PLL_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SICA_IWR0, iwr0); - bfin_write32(SICA_IWR1, iwr1); - hard_local_irq_restore(flags); + unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0); + + bfin_write32(SIC_IWR0 + SICA_SICB_OFF, iwr0); + bfin_write32(SIC_IWR1 + SICA_SICB_OFF, iwr1); } +#define bfin_iwr_restore bfin_iwr_restore -/* Writing to VR_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_VR_CTL(unsigned int val) +static inline void +bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2, + unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2) { - unsigned long flags, iwr0, iwr1; - - if (val == bfin_read_VR_CTL()) - return; - - flags = hard_local_irq_save(); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SICA_IWR0); - iwr1 = bfin_read32(SICA_IWR1); - /* Only allow PPL Wakeup) */ - bfin_write32(SICA_IWR0, IWR_ENABLE(0)); - bfin_write32(SICA_IWR1, 0); - - bfin_write16(VR_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SICA_IWR0, iwr0); - bfin_write32(SICA_IWR1, iwr1); - hard_local_irq_restore(flags); + unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0); + + *iwr0 = bfin_read32(SIC_IWR0 + SICA_SICB_OFF); + *iwr1 = bfin_read32(SIC_IWR1 + SICA_SICB_OFF); + bfin_iwr_restore(niwr0, niwr1, niwr2); } +#define bfin_iwr_save bfin_iwr_save + +static inline void +bfin_iwr_set_sup0(unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2) +{ + bfin_iwr_save(0, IWR_ENABLE(SUPPLE_0_WAKEUP), 0, iwr0, iwr1, iwr2); +} + +#endif + +#endif + +#include <mach-common/pll.h> -#endif /* _MACH_PLL_H */ +#endif diff --git a/arch/blackfin/mach-bf561/include/mach/smp.h b/arch/blackfin/mach-bf561/include/mach/smp.h index 2c8c514dd38..346c60589be 100644 --- a/arch/blackfin/mach-bf561/include/mach/smp.h +++ b/arch/blackfin/mach-bf561/include/mach/smp.h @@ -7,6 +7,8 @@ #ifndef _MACH_BF561_SMP #define _MACH_BF561_SMP +/* This header has to stand alone to avoid circular deps */ + struct task_struct; void platform_init_cpus(void); @@ -17,13 +19,13 @@ int platform_boot_secondary(unsigned int cpu, struct task_struct *idle); void platform_secondary_init(unsigned int cpu); -void platform_request_ipi(int (*handler)(int, void *)); +void platform_request_ipi(int irq, /*irq_handler_t*/ void *handler); -void platform_send_ipi(cpumask_t callmap); +void platform_send_ipi(cpumask_t callmap, int irq); -void platform_send_ipi_cpu(unsigned int cpu); +void platform_send_ipi_cpu(unsigned int cpu, int irq); -void platform_clear_ipi(unsigned int cpu); +void platform_clear_ipi(unsigned int cpu, int irq); void bfin_local_timer_setup(void); diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c index f540ed1257d..1074a7ef81c 100644 --- a/arch/blackfin/mach-bf561/smp.c +++ b/arch/blackfin/mach-bf561/smp.c @@ -86,12 +86,12 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle spin_lock(&boot_lock); - if ((bfin_read_SIC_SYSCR() & COREB_SRAM_INIT) == 0) { + if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) { /* CoreB already running, sending ipi to wakeup it */ platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); } else { /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */ - bfin_write_SIC_SYSCR(bfin_read_SIC_SYSCR() & ~COREB_SRAM_INIT); + bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT); SSYNC(); } @@ -111,41 +111,46 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle panic("CPU%u: processor failed to boot\n", cpu); } -void __init platform_request_ipi(irq_handler_t handler) +static const char supple0[] = "IRQ_SUPPLE_0"; +static const char supple1[] = "IRQ_SUPPLE_1"; +void __init platform_request_ipi(int irq, void *handler) { int ret; + const char *name = (irq == IRQ_SUPPLE_0) ? supple0 : supple1; - ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED, - "Supplemental Interrupt0", handler); + ret = request_irq(irq, handler, IRQF_DISABLED | IRQF_PERCPU, name, handler); if (ret) - panic("Cannot request supplemental interrupt 0 for IPI service"); + panic("Cannot request %s for IPI service", name); } -void platform_send_ipi(cpumask_t callmap) +void platform_send_ipi(cpumask_t callmap, int irq) { unsigned int cpu; + int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8; for_each_cpu_mask(cpu, callmap) { BUG_ON(cpu >= 2); SSYNC(); - bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu))); + bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu))); SSYNC(); } } -void platform_send_ipi_cpu(unsigned int cpu) +void platform_send_ipi_cpu(unsigned int cpu, int irq) { + int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8; BUG_ON(cpu >= 2); SSYNC(); - bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu))); + bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu))); SSYNC(); } -void platform_clear_ipi(unsigned int cpu) +void platform_clear_ipi(unsigned int cpu, int irq) { + int offset = (irq == IRQ_SUPPLE_0) ? 10 : 12; BUG_ON(cpu >= 2); SSYNC(); - bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + cpu))); + bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu))); SSYNC(); } diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index 2ca915ee181..bc08c98d008 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -615,7 +615,7 @@ ENTRY(_system_call) #ifdef CONFIG_IPIPE r0 = sp; SP += -12; - call ___ipipe_syscall_root; + pseudo_long_call ___ipipe_syscall_root, p0; SP += 12; cc = r0 == 1; if cc jump .Lsyscall_really_exit; @@ -692,7 +692,7 @@ ENTRY(_system_call) [--sp] = reti; SP += 4; /* don't merge with next insn to keep the pattern obvious */ SP += -12; - call ___ipipe_sync_root; + pseudo_long_call ___ipipe_sync_root, p4; SP += 12; jump .Lresume_userspace_1; .Lsyscall_no_irqsync: diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index da7e3c63746..a604f19d8dc 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c @@ -866,7 +866,6 @@ static void bfin_gpio_unmask_irq(unsigned int irq) u32 pintbit = PINT_BIT(pint_val); u32 bank = PINT_2_BANK(pint_val); - pint[bank]->request = pintbit; pint[bank]->mask_set = pintbit; } diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c index 80884b136a0..42fa87e8375 100644 --- a/arch/blackfin/mach-common/pm.c +++ b/arch/blackfin/mach-common/pm.c @@ -23,9 +23,6 @@ void bfin_pm_suspend_standby_enter(void) { - unsigned long flags; - - flags = hard_local_irq_save(); bfin_pm_standby_setup(); #ifdef CONFIG_PM_BFIN_SLEEP_DEEPER @@ -55,8 +52,6 @@ void bfin_pm_suspend_standby_enter(void) #else bfin_write_SIC_IWR(IWR_DISABLE_ALL); #endif - - hard_local_irq_restore(flags); } int bf53x_suspend_l1_mem(unsigned char *memptr) @@ -127,7 +122,6 @@ static void flushinv_all_dcache(void) int bfin_pm_suspend_mem_enter(void) { - unsigned long flags; int wakeup, ret; unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH @@ -149,12 +143,9 @@ int bfin_pm_suspend_mem_enter(void) wakeup |= GPWE; #endif - flags = hard_local_irq_save(); - ret = blackfin_dma_suspend(); if (ret) { - hard_local_irq_restore(flags); kfree(memptr); return ret; } @@ -178,7 +169,6 @@ int bfin_pm_suspend_mem_enter(void) bfin_gpio_pm_hibernate_restore(); blackfin_dma_resume(); - hard_local_irq_restore(flags); kfree(memptr); return 0; diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c index a17107a700d..9f251406a76 100644 --- a/arch/blackfin/mach-common/smp.c +++ b/arch/blackfin/mach-common/smp.c @@ -19,6 +19,7 @@ #include <linux/mm.h> #include <linux/cpu.h> #include <linux/smp.h> +#include <linux/cpumask.h> #include <linux/seq_file.h> #include <linux/irq.h> #include <linux/slab.h> @@ -43,12 +44,6 @@ void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb, *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb, *init_saved_dcplb_fault_addr_coreb; -cpumask_t cpu_possible_map; -EXPORT_SYMBOL(cpu_possible_map); - -cpumask_t cpu_online_map; -EXPORT_SYMBOL(cpu_online_map); - #define BFIN_IPI_RESCHEDULE 0 #define BFIN_IPI_CALL_FUNC 1 #define BFIN_IPI_CPU_STOP 2 @@ -65,8 +60,7 @@ struct smp_call_struct { void (*func)(void *info); void *info; int wait; - cpumask_t pending; - cpumask_t waitmask; + cpumask_t *waitmask; }; static struct blackfin_flush_data smp_flush_data; @@ -74,15 +68,19 @@ static struct blackfin_flush_data smp_flush_data; static DEFINE_SPINLOCK(stop_lock); struct ipi_message { - struct list_head list; unsigned long type; struct smp_call_struct call_struct; }; +/* A magic number - stress test shows this is safe for common cases */ +#define BFIN_IPI_MSGQ_LEN 5 + +/* Simple FIFO buffer, overflow leads to panic */ struct ipi_message_queue { - struct list_head head; spinlock_t lock; unsigned long count; + unsigned long head; /* head of the queue */ + struct ipi_message ipi_message[BFIN_IPI_MSGQ_LEN]; }; static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue); @@ -121,7 +119,6 @@ static void ipi_call_function(unsigned int cpu, struct ipi_message *msg) func = msg->call_struct.func; info = msg->call_struct.info; wait = msg->call_struct.wait; - cpu_clear(cpu, msg->call_struct.pending); func(info); if (wait) { #ifdef __ARCH_SYNC_CORE_DCACHE @@ -132,51 +129,57 @@ static void ipi_call_function(unsigned int cpu, struct ipi_message *msg) */ resync_core_dcache(); #endif - cpu_clear(cpu, msg->call_struct.waitmask); - } else - kfree(msg); + cpu_clear(cpu, *msg->call_struct.waitmask); + } +} + +/* Use IRQ_SUPPLE_0 to request reschedule. + * When returning from interrupt to user space, + * there is chance to reschedule */ +static irqreturn_t ipi_handler_int0(int irq, void *dev_instance) +{ + unsigned int cpu = smp_processor_id(); + + platform_clear_ipi(cpu, IRQ_SUPPLE_0); + return IRQ_HANDLED; } -static irqreturn_t ipi_handler(int irq, void *dev_instance) +static irqreturn_t ipi_handler_int1(int irq, void *dev_instance) { struct ipi_message *msg; struct ipi_message_queue *msg_queue; unsigned int cpu = smp_processor_id(); + unsigned long flags; - platform_clear_ipi(cpu); + platform_clear_ipi(cpu, IRQ_SUPPLE_1); msg_queue = &__get_cpu_var(ipi_msg_queue); - msg_queue->count++; - spin_lock(&msg_queue->lock); - while (!list_empty(&msg_queue->head)) { - msg = list_entry(msg_queue->head.next, typeof(*msg), list); - list_del(&msg->list); + spin_lock_irqsave(&msg_queue->lock, flags); + + while (msg_queue->count) { + msg = &msg_queue->ipi_message[msg_queue->head]; switch (msg->type) { - case BFIN_IPI_RESCHEDULE: - /* That's the easiest one; leave it to - * return_from_int. */ - kfree(msg); - break; case BFIN_IPI_CALL_FUNC: - spin_unlock(&msg_queue->lock); + spin_unlock_irqrestore(&msg_queue->lock, flags); ipi_call_function(cpu, msg); - spin_lock(&msg_queue->lock); + spin_lock_irqsave(&msg_queue->lock, flags); break; case BFIN_IPI_CPU_STOP: - spin_unlock(&msg_queue->lock); + spin_unlock_irqrestore(&msg_queue->lock, flags); ipi_cpu_stop(cpu); - spin_lock(&msg_queue->lock); - kfree(msg); + spin_lock_irqsave(&msg_queue->lock, flags); break; default: printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n", cpu, msg->type); - kfree(msg); break; } + msg_queue->head++; + msg_queue->head %= BFIN_IPI_MSGQ_LEN; + msg_queue->count--; } - spin_unlock(&msg_queue->lock); + spin_unlock_irqrestore(&msg_queue->lock, flags); return IRQ_HANDLED; } @@ -186,48 +189,47 @@ static void ipi_queue_init(void) struct ipi_message_queue *msg_queue; for_each_possible_cpu(cpu) { msg_queue = &per_cpu(ipi_msg_queue, cpu); - INIT_LIST_HEAD(&msg_queue->head); spin_lock_init(&msg_queue->lock); msg_queue->count = 0; + msg_queue->head = 0; } } -int smp_call_function(void (*func)(void *info), void *info, int wait) +static inline void smp_send_message(cpumask_t callmap, unsigned long type, + void (*func) (void *info), void *info, int wait) { unsigned int cpu; - cpumask_t callmap; - unsigned long flags; struct ipi_message_queue *msg_queue; struct ipi_message *msg; - - callmap = cpu_online_map; - cpu_clear(smp_processor_id(), callmap); - if (cpus_empty(callmap)) - return 0; - - msg = kmalloc(sizeof(*msg), GFP_ATOMIC); - if (!msg) - return -ENOMEM; - INIT_LIST_HEAD(&msg->list); - msg->call_struct.func = func; - msg->call_struct.info = info; - msg->call_struct.wait = wait; - msg->call_struct.pending = callmap; - msg->call_struct.waitmask = callmap; - msg->type = BFIN_IPI_CALL_FUNC; + unsigned long flags, next_msg; + cpumask_t waitmask = callmap; /* waitmask is shared by all cpus */ for_each_cpu_mask(cpu, callmap) { msg_queue = &per_cpu(ipi_msg_queue, cpu); spin_lock_irqsave(&msg_queue->lock, flags); - list_add_tail(&msg->list, &msg_queue->head); + if (msg_queue->count < BFIN_IPI_MSGQ_LEN) { + next_msg = (msg_queue->head + msg_queue->count) + % BFIN_IPI_MSGQ_LEN; + msg = &msg_queue->ipi_message[next_msg]; + msg->type = type; + if (type == BFIN_IPI_CALL_FUNC) { + msg->call_struct.func = func; + msg->call_struct.info = info; + msg->call_struct.wait = wait; + msg->call_struct.waitmask = &waitmask; + } + msg_queue->count++; + } else + panic("IPI message queue overflow\n"); spin_unlock_irqrestore(&msg_queue->lock, flags); - platform_send_ipi_cpu(cpu); + platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1); } + if (wait) { - while (!cpus_empty(msg->call_struct.waitmask)) + while (!cpus_empty(waitmask)) blackfin_dcache_invalidate_range( - (unsigned long)(&msg->call_struct.waitmask), - (unsigned long)(&msg->call_struct.waitmask)); + (unsigned long)(&waitmask), + (unsigned long)(&waitmask)); #ifdef __ARCH_SYNC_CORE_DCACHE /* * Invalidate D cache in case shared data was changed by @@ -235,8 +237,20 @@ int smp_call_function(void (*func)(void *info), void *info, int wait) */ resync_core_dcache(); #endif - kfree(msg); } +} + +int smp_call_function(void (*func)(void *info), void *info, int wait) +{ + cpumask_t callmap; + + callmap = cpu_online_map; + cpu_clear(smp_processor_id(), callmap); + if (cpus_empty(callmap)) + return 0; + + smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait); + return 0; } EXPORT_SYMBOL_GPL(smp_call_function); @@ -246,100 +260,39 @@ int smp_call_function_single(int cpuid, void (*func) (void *info), void *info, { unsigned int cpu = cpuid; cpumask_t callmap; - unsigned long flags; - struct ipi_message_queue *msg_queue; - struct ipi_message *msg; if (cpu_is_offline(cpu)) return 0; cpus_clear(callmap); cpu_set(cpu, callmap); - msg = kmalloc(sizeof(*msg), GFP_ATOMIC); - if (!msg) - return -ENOMEM; - INIT_LIST_HEAD(&msg->list); - msg->call_struct.func = func; - msg->call_struct.info = info; - msg->call_struct.wait = wait; - msg->call_struct.pending = callmap; - msg->call_struct.waitmask = callmap; - msg->type = BFIN_IPI_CALL_FUNC; - - msg_queue = &per_cpu(ipi_msg_queue, cpu); - spin_lock_irqsave(&msg_queue->lock, flags); - list_add_tail(&msg->list, &msg_queue->head); - spin_unlock_irqrestore(&msg_queue->lock, flags); - platform_send_ipi_cpu(cpu); + smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait); - if (wait) { - while (!cpus_empty(msg->call_struct.waitmask)) - blackfin_dcache_invalidate_range( - (unsigned long)(&msg->call_struct.waitmask), - (unsigned long)(&msg->call_struct.waitmask)); -#ifdef __ARCH_SYNC_CORE_DCACHE - /* - * Invalidate D cache in case shared data was changed by - * other processors to ensure cache coherence. - */ - resync_core_dcache(); -#endif - kfree(msg); - } return 0; } EXPORT_SYMBOL_GPL(smp_call_function_single); void smp_send_reschedule(int cpu) { - unsigned long flags; - struct ipi_message_queue *msg_queue; - struct ipi_message *msg; - + /* simply trigger an ipi */ if (cpu_is_offline(cpu)) return; - - msg = kzalloc(sizeof(*msg), GFP_ATOMIC); - if (!msg) - return; - INIT_LIST_HEAD(&msg->list); - msg->type = BFIN_IPI_RESCHEDULE; - - msg_queue = &per_cpu(ipi_msg_queue, cpu); - spin_lock_irqsave(&msg_queue->lock, flags); - list_add_tail(&msg->list, &msg_queue->head); - spin_unlock_irqrestore(&msg_queue->lock, flags); - platform_send_ipi_cpu(cpu); + platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); return; } void smp_send_stop(void) { - unsigned int cpu; cpumask_t callmap; - unsigned long flags; - struct ipi_message_queue *msg_queue; - struct ipi_message *msg; callmap = cpu_online_map; cpu_clear(smp_processor_id(), callmap); if (cpus_empty(callmap)) return; - msg = kzalloc(sizeof(*msg), GFP_ATOMIC); - if (!msg) - return; - INIT_LIST_HEAD(&msg->list); - msg->type = BFIN_IPI_CPU_STOP; + smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0); - for_each_cpu_mask(cpu, callmap) { - msg_queue = &per_cpu(ipi_msg_queue, cpu); - spin_lock_irqsave(&msg_queue->lock, flags); - list_add_tail(&msg->list, &msg_queue->head); - spin_unlock_irqrestore(&msg_queue->lock, flags); - platform_send_ipi_cpu(cpu); - } return; } @@ -446,7 +399,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus) { platform_prepare_cpus(max_cpus); ipi_queue_init(); - platform_request_ipi(&ipi_handler); + platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0); + platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1); } void __init smp_cpus_done(unsigned int max_cpus) diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c index 627e04b5ba9..dfd304a4a3e 100644 --- a/arch/blackfin/mm/sram-alloc.c +++ b/arch/blackfin/mm/sram-alloc.c @@ -704,18 +704,18 @@ int sram_free_with_lsl(const void *addr) { struct sram_list_struct *lsl, **tmp; struct mm_struct *mm = current->mm; + int ret = -1; for (tmp = &mm->context.sram_list; *tmp; tmp = &(*tmp)->next) - if ((*tmp)->addr == addr) - goto found; - return -1; -found: - lsl = *tmp; - sram_free(addr); - *tmp = lsl->next; - kfree(lsl); + if ((*tmp)->addr == addr) { + lsl = *tmp; + ret = sram_free(addr); + *tmp = lsl->next; + kfree(lsl); + break; + } - return 0; + return ret; } EXPORT_SYMBOL(sram_free_with_lsl); diff --git a/arch/cris/kernel/time.c b/arch/cris/kernel/time.c index b5096430ce1..4e73092e85c 100644 --- a/arch/cris/kernel/time.c +++ b/arch/cris/kernel/time.c @@ -86,7 +86,7 @@ int set_rtc_mmss(unsigned long nowtime) CMOS_WRITE(real_seconds,RTC_SECONDS); CMOS_WRITE(real_minutes,RTC_MINUTES); } else { - printk(KERN_WARNING + printk_once(KERN_NOTICE "set_rtc_mmss: can't update from %d to %d\n", cmos_minutes, real_minutes); retval = -1; diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c index c6c90f39f4d..7b897b7b0ae 100644 --- a/arch/ia64/kernel/acpi.c +++ b/arch/ia64/kernel/acpi.c @@ -477,6 +477,12 @@ acpi_numa_processor_affinity_init(struct acpi_srat_cpu_affinity *pa) if (!(pa->flags & ACPI_SRAT_CPU_ENABLED)) return; + if (srat_num_cpus >= ARRAY_SIZE(node_cpuid)) { + printk_once(KERN_WARNING + "node_cpuid[%d] is too small, may not be able to use all cpus\n", + ARRAY_SIZE(node_cpuid)); + return; + } pxm = get_processor_proximity_domain(pa); /* record this node in proximity bitmap */ diff --git a/arch/ia64/kernel/irq_ia64.c b/arch/ia64/kernel/irq_ia64.c index 9a26015c3e5..38c07b86690 100644 --- a/arch/ia64/kernel/irq_ia64.c +++ b/arch/ia64/kernel/irq_ia64.c @@ -633,7 +633,7 @@ ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action) BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL)); desc = irq_desc + irq; desc->status |= IRQ_PER_CPU; - desc->chip = &irq_type_ia64_lsapic; + set_irq_chip(irq, &irq_type_ia64_lsapic); if (action) setup_irq(irq, action); set_irq_handler(irq, handle_percpu_irq); diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c index f099b82703d..d92d5b5161f 100644 --- a/arch/ia64/kernel/perfmon.c +++ b/arch/ia64/kernel/perfmon.c @@ -829,10 +829,9 @@ pfm_rvmalloc(unsigned long size) unsigned long addr; size = PAGE_ALIGN(size); - mem = vmalloc(size); + mem = vzalloc(size); if (mem) { //printk("perfmon: CPU%d pfm_rvmalloc(%ld)=%p\n", smp_processor_id(), size, mem); - memset(mem, 0, size); addr = (unsigned long)mem; while (size > 0) { pfm_reserve_page(addr); diff --git a/arch/ia64/kernel/smp.c b/arch/ia64/kernel/smp.c index dabeefe2113..be450a3e987 100644 --- a/arch/ia64/kernel/smp.c +++ b/arch/ia64/kernel/smp.c @@ -293,6 +293,7 @@ smp_flush_tlb_all (void) void smp_flush_tlb_mm (struct mm_struct *mm) { + cpumask_var_t cpus; preempt_disable(); /* this happens for the common case of a single-threaded fork(): */ if (likely(mm == current->active_mm && atomic_read(&mm->mm_users) == 1)) @@ -301,9 +302,15 @@ smp_flush_tlb_mm (struct mm_struct *mm) preempt_enable(); return; } - - smp_call_function_many(mm_cpumask(mm), - (void (*)(void *))local_finish_flush_tlb_mm, mm, 1); + if (!alloc_cpumask_var(&cpus, GFP_ATOMIC)) { + smp_call_function((void (*)(void *))local_finish_flush_tlb_mm, + mm, 1); + } else { + cpumask_copy(cpus, mm_cpumask(mm)); + smp_call_function_many(cpus, + (void (*)(void *))local_finish_flush_tlb_mm, mm, 1); + free_cpumask_var(cpus); + } local_irq_disable(); local_finish_flush_tlb_mm(mm); local_irq_enable(); diff --git a/arch/ia64/kernel/time.c b/arch/ia64/kernel/time.c index ed6f22eb5b1..9702fa92489 100644 --- a/arch/ia64/kernel/time.c +++ b/arch/ia64/kernel/time.c @@ -168,7 +168,7 @@ timer_interrupt (int irq, void *dev_id) { unsigned long new_itm; - if (unlikely(cpu_is_offline(smp_processor_id()))) { + if (cpu_is_offline(smp_processor_id())) { return IRQ_HANDLED; } diff --git a/arch/m68k/include/asm/sun3_pgtable.h b/arch/m68k/include/asm/sun3_pgtable.h index cf5fad9b525..f55aa04161e 100644 --- a/arch/m68k/include/asm/sun3_pgtable.h +++ b/arch/m68k/include/asm/sun3_pgtable.h @@ -217,9 +217,8 @@ static inline pte_t pgoff_to_pte(unsigned off) /* Find an entry in the third-level pagetable. */ #define pte_index(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) #define pte_offset_kernel(pmd, address) ((pte_t *) __pmd_page(*pmd) + pte_index(address)) -/* FIXME: should we bother with kmap() here? */ -#define pte_offset_map(pmd, address) ((pte_t *)kmap(pmd_page(*pmd)) + pte_index(address)) -#define pte_unmap(pte) kunmap(pte) +#define pte_offset_map(pmd, address) ((pte_t *)page_address(pmd_page(*pmd)) + pte_index(address)) +#define pte_unmap(pte) do { } while (0) /* Macros to (de)construct the fake PTEs representing swap pages. */ #define __swp_type(x) ((x).val & 0x7F) diff --git a/arch/m68k/include/asm/thread_info.h b/arch/m68k/include/asm/thread_info.h index 1da5d53a00e..790988967ba 100644 --- a/arch/m68k/include/asm/thread_info.h +++ b/arch/m68k/include/asm/thread_info.h @@ -104,5 +104,6 @@ static inline struct thread_info *current_thread_info(void) #define TIF_SYSCALL_TRACE 15 /* syscall trace active */ #define TIF_MEMDIE 16 /* is terminating due to OOM killer */ #define TIF_FREEZE 17 /* thread is freezing for suspend */ +#define TIF_RESTORE_SIGMASK 18 /* restore signal mask in do_signal */ #endif /* _ASM_M68K_THREAD_INFO_H */ diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h index b43b36beafe..26d851d385b 100644 --- a/arch/m68k/include/asm/unistd.h +++ b/arch/m68k/include/asm/unistd.h @@ -373,6 +373,7 @@ #define __ARCH_WANT_SYS_SIGPENDING #define __ARCH_WANT_SYS_SIGPROCMASK #define __ARCH_WANT_SYS_RT_SIGACTION +#define __ARCH_WANT_SYS_RT_SIGSUSPEND /* * "Conditional" syscalls diff --git a/arch/m68k/kernel/entry.S b/arch/m68k/kernel/entry.S index 6360c437dcf..1559dea36e5 100644 --- a/arch/m68k/kernel/entry.S +++ b/arch/m68k/kernel/entry.S @@ -99,7 +99,10 @@ do_trace_exit: jra .Lret_from_exception ENTRY(ret_from_signal) - RESTORE_SWITCH_STACK + tstb %curptr@(TASK_INFO+TINFO_FLAGS+2) + jge 1f + jbsr syscall_trace +1: RESTORE_SWITCH_STACK addql #4,%sp /* on 68040 complete pending writebacks if any */ #ifdef CONFIG_M68040 @@ -174,16 +177,11 @@ do_signal_return: subql #4,%sp | dummy return address SAVE_SWITCH_STACK pea %sp@(SWITCH_STACK_SIZE) - clrl %sp@- bsrl do_signal - addql #8,%sp + addql #4,%sp RESTORE_SWITCH_STACK addql #4,%sp - tstl %d0 - jeq resume_userspace - | when single stepping into handler stop at the first insn - btst #6,%curptr@(TASK_INFO+TINFO_FLAGS+2) - jeq resume_userspace + jbra resume_userspace do_delayed_trace: bclr #7,%sp@(PT_OFF_SR) | clear trace bit in SR @@ -290,22 +288,6 @@ ENTRY(sys_vfork) RESTORE_SWITCH_STACK rts -ENTRY(sys_sigsuspend) - SAVE_SWITCH_STACK - pea %sp@(SWITCH_STACK_SIZE) - jbsr do_sigsuspend - addql #4,%sp - RESTORE_SWITCH_STACK - rts - -ENTRY(sys_rt_sigsuspend) - SAVE_SWITCH_STACK - pea %sp@(SWITCH_STACK_SIZE) - jbsr do_rt_sigsuspend - addql #4,%sp - RESTORE_SWITCH_STACK - rts - ENTRY(sys_sigreturn) SAVE_SWITCH_STACK jbsr do_sigreturn diff --git a/arch/m68k/kernel/signal.c b/arch/m68k/kernel/signal.c index 4b387538706..d12c3b0d9e4 100644 --- a/arch/m68k/kernel/signal.c +++ b/arch/m68k/kernel/signal.c @@ -51,8 +51,6 @@ #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) -asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs); - const int frame_extra_sizes[16] = { [1] = -1, /* sizeof(((struct frame *)0)->un.fmt1), */ [2] = sizeof(((struct frame *)0)->un.fmt2), @@ -74,51 +72,21 @@ const int frame_extra_sizes[16] = { /* * Atomically swap in the new signal mask, and wait for a signal. */ -asmlinkage int do_sigsuspend(struct pt_regs *regs) +asmlinkage int +sys_sigsuspend(int unused0, int unused1, old_sigset_t mask) { - old_sigset_t mask = regs->d3; - sigset_t saveset; - mask &= _BLOCKABLE; - saveset = current->blocked; + spin_lock_irq(¤t->sighand->siglock); + current->saved_sigmask = current->blocked; siginitset(¤t->blocked, mask); recalc_sigpending(); + spin_unlock_irq(¤t->sighand->siglock); - regs->d0 = -EINTR; - while (1) { - current->state = TASK_INTERRUPTIBLE; - schedule(); - if (do_signal(&saveset, regs)) - return -EINTR; - } -} - -asmlinkage int -do_rt_sigsuspend(struct pt_regs *regs) -{ - sigset_t __user *unewset = (sigset_t __user *)regs->d1; - size_t sigsetsize = (size_t)regs->d2; - sigset_t saveset, newset; - - /* XXX: Don't preclude handling different sized sigset_t's. */ - if (sigsetsize != sizeof(sigset_t)) - return -EINVAL; + current->state = TASK_INTERRUPTIBLE; + schedule(); + set_restore_sigmask(); - if (copy_from_user(&newset, unewset, sizeof(newset))) - return -EFAULT; - sigdelsetmask(&newset, ~_BLOCKABLE); - - saveset = current->blocked; - current->blocked = newset; - recalc_sigpending(); - - regs->d0 = -EINTR; - while (1) { - current->state = TASK_INTERRUPTIBLE; - schedule(); - if (do_signal(&saveset, regs)) - return -EINTR; - } + return -ERESTARTNOHAND; } asmlinkage int @@ -132,10 +100,10 @@ sys_sigaction(int sig, const struct old_sigaction __user *act, old_sigset_t mask; if (!access_ok(VERIFY_READ, act, sizeof(*act)) || __get_user(new_ka.sa.sa_handler, &act->sa_handler) || - __get_user(new_ka.sa.sa_restorer, &act->sa_restorer)) + __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) || + __get_user(new_ka.sa.sa_flags, &act->sa_flags) || + __get_user(mask, &act->sa_mask)) return -EFAULT; - __get_user(new_ka.sa.sa_flags, &act->sa_flags); - __get_user(mask, &act->sa_mask); siginitset(&new_ka.sa.sa_mask, mask); } @@ -144,10 +112,10 @@ sys_sigaction(int sig, const struct old_sigaction __user *act, if (!ret && oact) { if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) || __put_user(old_ka.sa.sa_handler, &oact->sa_handler) || - __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer)) + __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) || + __put_user(old_ka.sa.sa_flags, &oact->sa_flags) || + __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask)) return -EFAULT; - __put_user(old_ka.sa.sa_flags, &oact->sa_flags); - __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask); } return ret; @@ -318,36 +286,10 @@ out: return err; } -static inline int -restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __user *fp, - int *pd0) +static int mangle_kernel_stack(struct pt_regs *regs, int formatvec, + void __user *fp) { - int fsize, formatvec; - struct sigcontext context; - int err; - - /* Always make any pending restarted system calls return -EINTR */ - current_thread_info()->restart_block.fn = do_no_restart_syscall; - - /* get previous context */ - if (copy_from_user(&context, usc, sizeof(context))) - goto badframe; - - /* restore passed registers */ - regs->d1 = context.sc_d1; - regs->a0 = context.sc_a0; - regs->a1 = context.sc_a1; - regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff); - regs->pc = context.sc_pc; - regs->orig_d0 = -1; /* disable syscall checks */ - wrusp(context.sc_usp); - formatvec = context.sc_formatvec; - regs->format = formatvec >> 12; - regs->vector = formatvec & 0xfff; - - err = restore_fpu_state(&context); - - fsize = frame_extra_sizes[regs->format]; + int fsize = frame_extra_sizes[formatvec >> 12]; if (fsize < 0) { /* * user process trying to return with weird frame format @@ -355,16 +297,22 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __u #ifdef DEBUG printk("user process returning with weird frame format\n"); #endif - goto badframe; + return 1; } + if (!fsize) { + regs->format = formatvec >> 12; + regs->vector = formatvec & 0xfff; + } else { + struct switch_stack *sw = (struct switch_stack *)regs - 1; + unsigned long buf[fsize / 2]; /* yes, twice as much */ - /* OK. Make room on the supervisor stack for the extra junk, - * if necessary. - */ + /* that'll make sure that expansion won't crap over data */ + if (copy_from_user(buf + fsize / 4, fp, fsize)) + return 1; - if (fsize) { - struct switch_stack *sw = (struct switch_stack *)regs - 1; - regs->d0 = context.sc_d0; + /* point of no return */ + regs->format = formatvec >> 12; + regs->vector = formatvec & 0xfff; #define frame_offset (sizeof(struct pt_regs)+sizeof(struct switch_stack)) __asm__ __volatile__ (" movel %0,%/a0\n\t" @@ -376,30 +324,50 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __u " lea %/sp@(%c3),%/a0\n\t" /* add offset of fmt */ " lsrl #2,%1\n\t" " subql #1,%1\n\t" - "2: movesl %4@+,%2\n\t" - "3: movel %2,%/a0@+\n\t" + /* copy to the gap we'd made */ + "2: movel %4@+,%/a0@+\n\t" " dbra %1,2b\n\t" " bral ret_from_signal\n" - "4:\n" - ".section __ex_table,\"a\"\n" - " .align 4\n" - " .long 2b,4b\n" - " .long 3b,4b\n" - ".previous" : /* no outputs, it doesn't ever return */ : "a" (sw), "d" (fsize), "d" (frame_offset/4-1), - "n" (frame_offset), "a" (fp) + "n" (frame_offset), "a" (buf + fsize/4) : "a0"); #undef frame_offset - /* - * If we ever get here an exception occurred while - * building the above stack-frame. - */ - goto badframe; } + return 0; +} - *pd0 = context.sc_d0; - return err; +static inline int +restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __user *fp) +{ + int formatvec; + struct sigcontext context; + int err; + + /* Always make any pending restarted system calls return -EINTR */ + current_thread_info()->restart_block.fn = do_no_restart_syscall; + + /* get previous context */ + if (copy_from_user(&context, usc, sizeof(context))) + goto badframe; + + /* restore passed registers */ + regs->d0 = context.sc_d0; + regs->d1 = context.sc_d1; + regs->a0 = context.sc_a0; + regs->a1 = context.sc_a1; + regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff); + regs->pc = context.sc_pc; + regs->orig_d0 = -1; /* disable syscall checks */ + wrusp(context.sc_usp); + formatvec = context.sc_formatvec; + + err = restore_fpu_state(&context); + + if (err || mangle_kernel_stack(regs, formatvec, fp)) + goto badframe; + + return 0; badframe: return 1; @@ -407,9 +375,9 @@ badframe: static inline int rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw, - struct ucontext __user *uc, int *pd0) + struct ucontext __user *uc) { - int fsize, temp; + int temp; greg_t __user *gregs = uc->uc_mcontext.gregs; unsigned long usp; int err; @@ -443,65 +411,16 @@ rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw, regs->sr = (regs->sr & 0xff00) | (temp & 0xff); regs->orig_d0 = -1; /* disable syscall checks */ err |= __get_user(temp, &uc->uc_formatvec); - regs->format = temp >> 12; - regs->vector = temp & 0xfff; err |= rt_restore_fpu_state(uc); - if (do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT) + if (err || do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT) goto badframe; - fsize = frame_extra_sizes[regs->format]; - if (fsize < 0) { - /* - * user process trying to return with weird frame format - */ -#ifdef DEBUG - printk("user process returning with weird frame format\n"); -#endif + if (mangle_kernel_stack(regs, temp, &uc->uc_extra)) goto badframe; - } - - /* OK. Make room on the supervisor stack for the extra junk, - * if necessary. - */ - if (fsize) { -#define frame_offset (sizeof(struct pt_regs)+sizeof(struct switch_stack)) - __asm__ __volatile__ - (" movel %0,%/a0\n\t" - " subl %1,%/a0\n\t" /* make room on stack */ - " movel %/a0,%/sp\n\t" /* set stack pointer */ - /* move switch_stack and pt_regs */ - "1: movel %0@+,%/a0@+\n\t" - " dbra %2,1b\n\t" - " lea %/sp@(%c3),%/a0\n\t" /* add offset of fmt */ - " lsrl #2,%1\n\t" - " subql #1,%1\n\t" - "2: movesl %4@+,%2\n\t" - "3: movel %2,%/a0@+\n\t" - " dbra %1,2b\n\t" - " bral ret_from_signal\n" - "4:\n" - ".section __ex_table,\"a\"\n" - " .align 4\n" - " .long 2b,4b\n" - " .long 3b,4b\n" - ".previous" - : /* no outputs, it doesn't ever return */ - : "a" (sw), "d" (fsize), "d" (frame_offset/4-1), - "n" (frame_offset), "a" (&uc->uc_extra) - : "a0"); -#undef frame_offset - /* - * If we ever get here an exception occurred while - * building the above stack-frame. - */ - goto badframe; - } - - *pd0 = regs->d0; - return err; + return 0; badframe: return 1; @@ -514,7 +433,6 @@ asmlinkage int do_sigreturn(unsigned long __unused) unsigned long usp = rdusp(); struct sigframe __user *frame = (struct sigframe __user *)(usp - 4); sigset_t set; - int d0; if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) goto badframe; @@ -528,9 +446,9 @@ asmlinkage int do_sigreturn(unsigned long __unused) current->blocked = set; recalc_sigpending(); - if (restore_sigcontext(regs, &frame->sc, frame + 1, &d0)) + if (restore_sigcontext(regs, &frame->sc, frame + 1)) goto badframe; - return d0; + return regs->d0; badframe: force_sig(SIGSEGV, current); @@ -544,7 +462,6 @@ asmlinkage int do_rt_sigreturn(unsigned long __unused) unsigned long usp = rdusp(); struct rt_sigframe __user *frame = (struct rt_sigframe __user *)(usp - 4); sigset_t set; - int d0; if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) goto badframe; @@ -555,9 +472,9 @@ asmlinkage int do_rt_sigreturn(unsigned long __unused) current->blocked = set; recalc_sigpending(); - if (rt_restore_ucontext(regs, sw, &frame->uc, &d0)) + if (rt_restore_ucontext(regs, sw, &frame->uc)) goto badframe; - return d0; + return regs->d0; badframe: force_sig(SIGSEGV, current); @@ -775,7 +692,7 @@ get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) return (void __user *)((usp - frame_size) & -8UL); } -static void setup_frame (int sig, struct k_sigaction *ka, +static int setup_frame (int sig, struct k_sigaction *ka, sigset_t *set, struct pt_regs *regs) { struct sigframe __user *frame; @@ -793,10 +710,8 @@ static void setup_frame (int sig, struct k_sigaction *ka, frame = get_sigframe(ka, regs, sizeof(*frame) + fsize); - if (fsize) { + if (fsize) err |= copy_to_user (frame + 1, regs + 1, fsize); - regs->stkadj = fsize; - } err |= __put_user((current_thread_info()->exec_domain && current_thread_info()->exec_domain->signal_invmap @@ -826,11 +741,21 @@ static void setup_frame (int sig, struct k_sigaction *ka, push_cache ((unsigned long) &frame->retcode); - /* Set up registers for signal handler */ + /* + * Set up registers for signal handler. All the state we are about + * to destroy is successfully copied to sigframe. + */ wrusp ((unsigned long) frame); regs->pc = (unsigned long) ka->sa.sa_handler; -adjust_stack: + /* + * This is subtle; if we build more than one sigframe, all but the + * first one will see frame format 0 and have fsize == 0, so we won't + * screw stkadj. + */ + if (fsize) + regs->stkadj = fsize; + /* Prepare to skip over the extra stuff in the exception frame. */ if (regs->stkadj) { struct pt_regs *tregs = @@ -845,14 +770,14 @@ adjust_stack: tregs->pc = regs->pc; tregs->sr = regs->sr; } - return; + return 0; give_sigsegv: force_sigsegv(sig, current); - goto adjust_stack; + return err; } -static void setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info, +static int setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info, sigset_t *set, struct pt_regs *regs) { struct rt_sigframe __user *frame; @@ -869,10 +794,8 @@ static void setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info, frame = get_sigframe(ka, regs, sizeof(*frame)); - if (fsize) { + if (fsize) err |= copy_to_user (&frame->uc.uc_extra, regs + 1, fsize); - regs->stkadj = fsize; - } err |= __put_user((current_thread_info()->exec_domain && current_thread_info()->exec_domain->signal_invmap @@ -914,11 +837,21 @@ static void setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info, push_cache ((unsigned long) &frame->retcode); - /* Set up registers for signal handler */ + /* + * Set up registers for signal handler. All the state we are about + * to destroy is successfully copied to sigframe. + */ wrusp ((unsigned long) frame); regs->pc = (unsigned long) ka->sa.sa_handler; -adjust_stack: + /* + * This is subtle; if we build more than one sigframe, all but the + * first one will see frame format 0 and have fsize == 0, so we won't + * screw stkadj. + */ + if (fsize) + regs->stkadj = fsize; + /* Prepare to skip over the extra stuff in the exception frame. */ if (regs->stkadj) { struct pt_regs *tregs = @@ -933,11 +866,11 @@ adjust_stack: tregs->pc = regs->pc; tregs->sr = regs->sr; } - return; + return 0; give_sigsegv: force_sigsegv(sig, current); - goto adjust_stack; + return err; } static inline void @@ -995,6 +928,7 @@ static void handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info, sigset_t *oldset, struct pt_regs *regs) { + int err; /* are we from a system call? */ if (regs->orig_d0 >= 0) /* If so, check system call restarting.. */ @@ -1002,17 +936,24 @@ handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info, /* set up the stack frame */ if (ka->sa.sa_flags & SA_SIGINFO) - setup_rt_frame(sig, ka, info, oldset, regs); + err = setup_rt_frame(sig, ka, info, oldset, regs); else - setup_frame(sig, ka, oldset, regs); + err = setup_frame(sig, ka, oldset, regs); - if (ka->sa.sa_flags & SA_ONESHOT) - ka->sa.sa_handler = SIG_DFL; + if (err) + return; sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); if (!(ka->sa.sa_flags & SA_NODEFER)) sigaddset(¤t->blocked,sig); recalc_sigpending(); + + if (test_thread_flag(TIF_DELAYED_TRACE)) { + regs->sr &= ~0x8000; + send_sig(SIGTRAP, current, 1); + } + + clear_thread_flag(TIF_RESTORE_SIGMASK); } /* @@ -1020,22 +961,25 @@ handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info, * want to handle. Thus you cannot kill init even with a SIGKILL even by * mistake. */ -asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs) +asmlinkage void do_signal(struct pt_regs *regs) { siginfo_t info; struct k_sigaction ka; int signr; + sigset_t *oldset; current->thread.esp0 = (unsigned long) regs; - if (!oldset) + if (test_thread_flag(TIF_RESTORE_SIGMASK)) + oldset = ¤t->saved_sigmask; + else oldset = ¤t->blocked; signr = get_signal_to_deliver(&info, &ka, regs, NULL); if (signr > 0) { /* Whee! Actually deliver the signal. */ handle_signal(signr, &ka, &info, oldset, regs); - return 1; + return; } /* Did we come from a system call? */ @@ -1043,5 +987,9 @@ asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs) /* Restart the system call - no handlers present */ handle_restart(regs, NULL, 0); - return 0; + /* If there's no signal to deliver, we just restore the saved mask. */ + if (test_thread_flag(TIF_RESTORE_SIGMASK)) { + clear_thread_flag(TIF_RESTORE_SIGMASK); + sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL); + } } diff --git a/arch/m68knommu/kernel/entry.S b/arch/m68knommu/kernel/entry.S index aff6f57ef8b..2783f25e38b 100644 --- a/arch/m68knommu/kernel/entry.S +++ b/arch/m68knommu/kernel/entry.S @@ -112,22 +112,6 @@ ENTRY(sys_clone) RESTORE_SWITCH_STACK rts -ENTRY(sys_sigsuspend) - SAVE_SWITCH_STACK - pea %sp@(SWITCH_STACK_SIZE) - jbsr do_sigsuspend - addql #4,%sp - RESTORE_SWITCH_STACK - rts - -ENTRY(sys_rt_sigsuspend) - SAVE_SWITCH_STACK - pea %sp@(SWITCH_STACK_SIZE) - jbsr do_rt_sigsuspend - addql #4,%sp - RESTORE_SWITCH_STACK - rts - ENTRY(sys_sigreturn) SAVE_SWITCH_STACK jbsr do_sigreturn diff --git a/arch/m68knommu/kernel/signal.c b/arch/m68knommu/kernel/signal.c index 5ab6a04af14..36a81bb6835 100644 --- a/arch/m68knommu/kernel/signal.c +++ b/arch/m68knommu/kernel/signal.c @@ -53,65 +53,30 @@ void ret_from_user_signal(void); void ret_from_user_rt_signal(void); -asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs); /* * Atomically swap in the new signal mask, and wait for a signal. */ -asmlinkage int do_sigsuspend(struct pt_regs *regs) +asmlinkage int +sys_sigsuspend(int unused0, int unused1, old_sigset_t mask) { - old_sigset_t mask = regs->d3; - sigset_t saveset; - mask &= _BLOCKABLE; spin_lock_irq(¤t->sighand->siglock); - saveset = current->blocked; + current->saved_sigmask = current->blocked; siginitset(¤t->blocked, mask); recalc_sigpending(); spin_unlock_irq(¤t->sighand->siglock); - regs->d0 = -EINTR; - while (1) { - current->state = TASK_INTERRUPTIBLE; - schedule(); - if (do_signal(&saveset, regs)) - return -EINTR; - } -} - -asmlinkage int -do_rt_sigsuspend(struct pt_regs *regs) -{ - sigset_t *unewset = (sigset_t *)regs->d1; - size_t sigsetsize = (size_t)regs->d2; - sigset_t saveset, newset; - - /* XXX: Don't preclude handling different sized sigset_t's. */ - if (sigsetsize != sizeof(sigset_t)) - return -EINVAL; + current->state = TASK_INTERRUPTIBLE; + schedule(); + set_restore_sigmask(); - if (copy_from_user(&newset, unewset, sizeof(newset))) - return -EFAULT; - sigdelsetmask(&newset, ~_BLOCKABLE); - - spin_lock_irq(¤t->sighand->siglock); - saveset = current->blocked; - current->blocked = newset; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - regs->d0 = -EINTR; - while (1) { - current->state = TASK_INTERRUPTIBLE; - schedule(); - if (do_signal(&saveset, regs)) - return -EINTR; - } + return -ERESTARTNOHAND; } -asmlinkage int -sys_sigaction(int sig, const struct old_sigaction *act, - struct old_sigaction *oact) +asmlinkage int +sys_sigaction(int sig, const struct old_sigaction __user *act, + struct old_sigaction __user *oact) { struct k_sigaction new_ka, old_ka; int ret; @@ -120,10 +85,10 @@ sys_sigaction(int sig, const struct old_sigaction *act, old_sigset_t mask; if (!access_ok(VERIFY_READ, act, sizeof(*act)) || __get_user(new_ka.sa.sa_handler, &act->sa_handler) || - __get_user(new_ka.sa.sa_restorer, &act->sa_restorer)) + __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) || + __get_user(new_ka.sa.sa_flags, &act->sa_flags) || + __get_user(mask, &act->sa_mask)) return -EFAULT; - __get_user(new_ka.sa.sa_flags, &act->sa_flags); - __get_user(mask, &act->sa_mask); siginitset(&new_ka.sa.sa_mask, mask); } @@ -132,17 +97,17 @@ sys_sigaction(int sig, const struct old_sigaction *act, if (!ret && oact) { if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) || __put_user(old_ka.sa.sa_handler, &oact->sa_handler) || - __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer)) + __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) || + __put_user(old_ka.sa.sa_flags, &oact->sa_flags) || + __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask)) return -EFAULT; - __put_user(old_ka.sa.sa_flags, &oact->sa_flags); - __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask); } return ret; } asmlinkage int -sys_sigaltstack(const stack_t *uss, stack_t *uoss) +sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss) { return do_sigaltstack(uss, uoss, rdusp()); } @@ -157,10 +122,10 @@ sys_sigaltstack(const stack_t *uss, stack_t *uoss) struct sigframe { - char *pretcode; + char __user *pretcode; int sig; int code; - struct sigcontext *psc; + struct sigcontext __user *psc; char retcode[8]; unsigned long extramask[_NSIG_WORDS-1]; struct sigcontext sc; @@ -168,10 +133,10 @@ struct sigframe struct rt_sigframe { - char *pretcode; + char __user *pretcode; int sig; - struct siginfo *pinfo; - void *puc; + struct siginfo __user *pinfo; + void __user *puc; char retcode[8]; struct siginfo info; struct ucontext uc; @@ -198,8 +163,8 @@ static inline int restore_fpu_state(struct sigcontext *sc) goto out; __asm__ volatile (".chip 68k/68881\n\t" - "fmovemx %0,%/fp0-%/fp1\n\t" - "fmoveml %1,%/fpcr/%/fpsr/%/fpiar\n\t" + "fmovemx %0,%%fp0-%%fp1\n\t" + "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t" ".chip 68k" : /* no outputs */ : "m" (*sc->sc_fpregs), "m" (*sc->sc_fpcntl)); @@ -218,7 +183,7 @@ out: #define uc_formatvec uc_filler[FPCONTEXT_SIZE/4] #define uc_extra uc_filler[FPCONTEXT_SIZE/4+1] -static inline int rt_restore_fpu_state(struct ucontext *uc) +static inline int rt_restore_fpu_state(struct ucontext __user *uc) { unsigned char fpstate[FPCONTEXT_SIZE]; int context_size = 0; @@ -228,7 +193,7 @@ static inline int rt_restore_fpu_state(struct ucontext *uc) if (FPU_IS_EMU) { /* restore fpu control register */ if (__copy_from_user(current->thread.fpcntl, - &uc->uc_mcontext.fpregs.f_pcr, 12)) + uc->uc_mcontext.fpregs.f_fpcntl, 12)) goto out; /* restore all other fpu register */ if (__copy_from_user(current->thread.fp, @@ -237,7 +202,7 @@ static inline int rt_restore_fpu_state(struct ucontext *uc) return 0; } - if (__get_user(*(long *)fpstate, (long *)&uc->uc_fpstate)) + if (__get_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate)) goto out; if (fpstate[0]) { context_size = fpstate[1]; @@ -249,15 +214,15 @@ static inline int rt_restore_fpu_state(struct ucontext *uc) sizeof(fpregs))) goto out; __asm__ volatile (".chip 68k/68881\n\t" - "fmovemx %0,%/fp0-%/fp7\n\t" - "fmoveml %1,%/fpcr/%/fpsr/%/fpiar\n\t" + "fmovemx %0,%%fp0-%%fp7\n\t" + "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t" ".chip 68k" : /* no outputs */ : "m" (*fpregs.f_fpregs), - "m" (fpregs.f_pcr)); + "m" (*fpregs.f_fpcntl)); } if (context_size && - __copy_from_user(fpstate + 4, (long *)&uc->uc_fpstate + 1, + __copy_from_user(fpstate + 4, (long __user *)&uc->uc_fpstate + 1, context_size)) goto out; __asm__ volatile (".chip 68k/68881\n\t" @@ -272,7 +237,7 @@ out: #endif static inline int -restore_sigcontext(struct pt_regs *regs, struct sigcontext *usc, void *fp, +restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __user *fp, int *pd0) { int formatvec; @@ -312,10 +277,10 @@ badframe: static inline int rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw, - struct ucontext *uc, int *pd0) + struct ucontext __user *uc, int *pd0) { int temp; - greg_t *gregs = uc->uc_mcontext.gregs; + greg_t __user *gregs = uc->uc_mcontext.gregs; unsigned long usp; int err; @@ -365,7 +330,7 @@ asmlinkage int do_sigreturn(unsigned long __unused) struct switch_stack *sw = (struct switch_stack *) &__unused; struct pt_regs *regs = (struct pt_regs *) (sw + 1); unsigned long usp = rdusp(); - struct sigframe *frame = (struct sigframe *)(usp - 4); + struct sigframe __user *frame = (struct sigframe __user *)(usp - 4); sigset_t set; int d0; @@ -397,7 +362,7 @@ asmlinkage int do_rt_sigreturn(unsigned long __unused) struct switch_stack *sw = (struct switch_stack *) &__unused; struct pt_regs *regs = (struct pt_regs *) (sw + 1); unsigned long usp = rdusp(); - struct rt_sigframe *frame = (struct rt_sigframe *)(usp - 4); + struct rt_sigframe __user *frame = (struct rt_sigframe __user *)(usp - 4); sigset_t set; int d0; @@ -443,17 +408,17 @@ static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs) if (sc->sc_fpstate[0]) { fpu_version = sc->sc_fpstate[0]; __asm__ volatile (".chip 68k/68881\n\t" - "fmovemx %/fp0-%/fp1,%0\n\t" - "fmoveml %/fpcr/%/fpsr/%/fpiar,%1\n\t" + "fmovemx %%fp0-%%fp1,%0\n\t" + "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t" ".chip 68k" - : /* no outputs */ - : "m" (*sc->sc_fpregs), - "m" (*sc->sc_fpcntl) + : "=m" (*sc->sc_fpregs), + "=m" (*sc->sc_fpcntl) + : /* no inputs */ : "memory"); } } -static inline int rt_save_fpu_state(struct ucontext *uc, struct pt_regs *regs) +static inline int rt_save_fpu_state(struct ucontext __user *uc, struct pt_regs *regs) { unsigned char fpstate[FPCONTEXT_SIZE]; int context_size = 0; @@ -461,7 +426,7 @@ static inline int rt_save_fpu_state(struct ucontext *uc, struct pt_regs *regs) if (FPU_IS_EMU) { /* save fpu control register */ - err |= copy_to_user(&uc->uc_mcontext.fpregs.f_pcr, + err |= copy_to_user(uc->uc_mcontext.fpregs.f_pcntl, current->thread.fpcntl, 12); /* save all other fpu register */ err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpregs, @@ -474,24 +439,24 @@ static inline int rt_save_fpu_state(struct ucontext *uc, struct pt_regs *regs) ".chip 68k" : : "m" (*fpstate) : "memory"); - err |= __put_user(*(long *)fpstate, (long *)&uc->uc_fpstate); + err |= __put_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate); if (fpstate[0]) { fpregset_t fpregs; context_size = fpstate[1]; fpu_version = fpstate[0]; __asm__ volatile (".chip 68k/68881\n\t" - "fmovemx %/fp0-%/fp7,%0\n\t" - "fmoveml %/fpcr/%/fpsr/%/fpiar,%1\n\t" + "fmovemx %%fp0-%%fp7,%0\n\t" + "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t" ".chip 68k" - : /* no outputs */ - : "m" (*fpregs.f_fpregs), - "m" (fpregs.f_pcr) + : "=m" (*fpregs.f_fpregs), + "=m" (*fpregs.f_fpcntl) + : /* no inputs */ : "memory"); err |= copy_to_user(&uc->uc_mcontext.fpregs, &fpregs, sizeof(fpregs)); } if (context_size) - err |= copy_to_user((long *)&uc->uc_fpstate + 1, fpstate + 4, + err |= copy_to_user((long __user *)&uc->uc_fpstate + 1, fpstate + 4, context_size); return err; } @@ -516,10 +481,10 @@ static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs, #endif } -static inline int rt_setup_ucontext(struct ucontext *uc, struct pt_regs *regs) +static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs *regs) { struct switch_stack *sw = (struct switch_stack *)regs - 1; - greg_t *gregs = uc->uc_mcontext.gregs; + greg_t __user *gregs = uc->uc_mcontext.gregs; int err = 0; err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version); @@ -547,7 +512,7 @@ static inline int rt_setup_ucontext(struct ucontext *uc, struct pt_regs *regs) return err; } -static inline void * +static inline void __user * get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) { unsigned long usp; @@ -560,13 +525,13 @@ get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) if (!sas_ss_flags(usp)) usp = current->sas_ss_sp + current->sas_ss_size; } - return (void *)((usp - frame_size) & -8UL); + return (void __user *)((usp - frame_size) & -8UL); } -static void setup_frame (int sig, struct k_sigaction *ka, +static int setup_frame (int sig, struct k_sigaction *ka, sigset_t *set, struct pt_regs *regs) { - struct sigframe *frame; + struct sigframe __user *frame; struct sigcontext context; int err = 0; @@ -617,17 +582,17 @@ adjust_stack: tregs->pc = regs->pc; tregs->sr = regs->sr; } - return; + return err; give_sigsegv: force_sigsegv(sig, current); goto adjust_stack; } -static void setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info, +static int setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info, sigset_t *set, struct pt_regs *regs) { - struct rt_sigframe *frame; + struct rt_sigframe __user *frame; int err = 0; frame = get_sigframe(ka, regs, sizeof(*frame)); @@ -644,8 +609,8 @@ static void setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info, /* Create the ucontext. */ err |= __put_user(0, &frame->uc.uc_flags); - err |= __put_user(0, &frame->uc.uc_link); - err |= __put_user((void *)current->sas_ss_sp, + err |= __put_user(NULL, &frame->uc.uc_link); + err |= __put_user((void __user *)current->sas_ss_sp, &frame->uc.uc_stack.ss_sp); err |= __put_user(sas_ss_flags(rdusp()), &frame->uc.uc_stack.ss_flags); @@ -681,7 +646,7 @@ adjust_stack: tregs->pc = regs->pc; tregs->sr = regs->sr; } - return; + return err; give_sigsegv: force_sigsegv(sig, current); @@ -728,6 +693,7 @@ static void handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info, sigset_t *oldset, struct pt_regs *regs) { + int err; /* are we from a system call? */ if (regs->orig_d0 >= 0) /* If so, check system call restarting.. */ @@ -735,12 +701,12 @@ handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info, /* set up the stack frame */ if (ka->sa.sa_flags & SA_SIGINFO) - setup_rt_frame(sig, ka, info, oldset, regs); + err = setup_rt_frame(sig, ka, info, oldset, regs); else - setup_frame(sig, ka, oldset, regs); + err = setup_frame(sig, ka, oldset, regs); - if (ka->sa.sa_flags & SA_ONESHOT) - ka->sa.sa_handler = SIG_DFL; + if (err) + return; spin_lock_irq(¤t->sighand->siglock); sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); @@ -748,6 +714,8 @@ handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info, sigaddset(¤t->blocked,sig); recalc_sigpending(); spin_unlock_irq(¤t->sighand->siglock); + + clear_thread_flag(TIF_RESTORE_SIGMASK); } /* @@ -755,11 +723,12 @@ handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info, * want to handle. Thus you cannot kill init even with a SIGKILL even by * mistake. */ -asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs) +asmlinkage void do_signal(struct pt_regs *regs) { struct k_sigaction ka; siginfo_t info; int signr; + sigset_t *oldset; /* * We want the common case to go fast, which @@ -768,16 +737,18 @@ asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs) * if so. */ if (!user_mode(regs)) - return 1; + return; - if (!oldset) + if (test_thread_flag(TIF_RESTORE_SIGMASK)) + oldset = ¤t->saved_sigmask; + else oldset = ¤t->blocked; signr = get_signal_to_deliver(&info, &ka, regs, NULL); if (signr > 0) { /* Whee! Actually deliver the signal. */ handle_signal(signr, &ka, &info, oldset, regs); - return 1; + return; } /* Did we come from a system call? */ @@ -785,5 +756,10 @@ asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs) /* Restart the system call - no handlers present */ handle_restart(regs, NULL, 0); } - return 0; + + /* If there's no signal to deliver, we just restore the saved mask. */ + if (test_thread_flag(TIF_RESTORE_SIGMASK)) { + clear_thread_flag(TIF_RESTORE_SIGMASK); + sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL); + } } diff --git a/arch/m68knommu/platform/68328/entry.S b/arch/m68knommu/platform/68328/entry.S index 27241e16a52..240a7a6e25c 100644 --- a/arch/m68knommu/platform/68328/entry.S +++ b/arch/m68knommu/platform/68328/entry.S @@ -106,6 +106,7 @@ Luser_return: movel %sp,%d1 /* get thread_info pointer */ andl #-THREAD_SIZE,%d1 movel %d1,%a2 +1: move %a2@(TI_FLAGS),%d1 /* thread_info->flags */ andl #_TIF_WORK_MASK,%d1 jne Lwork_to_do @@ -120,13 +121,11 @@ Lsignal_return: subql #4,%sp /* dummy return address*/ SAVE_SWITCH_STACK pea %sp@(SWITCH_STACK_SIZE) - clrl %sp@- bsrw do_signal - addql #8,%sp + addql #4,%sp RESTORE_SWITCH_STACK addql #4,%sp -Lreturn: - RESTORE_ALL + jra 1b /* * This is the main interrupt handler, responsible for calling process_int() diff --git a/arch/m68knommu/platform/68360/entry.S b/arch/m68knommu/platform/68360/entry.S index c131c6e1d92..8a28788c0ee 100644 --- a/arch/m68knommu/platform/68360/entry.S +++ b/arch/m68knommu/platform/68360/entry.S @@ -102,6 +102,7 @@ Luser_return: movel %sp,%d1 /* get thread_info pointer */ andl #-THREAD_SIZE,%d1 movel %d1,%a2 +1: move %a2@(TI_FLAGS),%d1 /* thread_info->flags */ andl #_TIF_WORK_MASK,%d1 jne Lwork_to_do @@ -116,13 +117,11 @@ Lsignal_return: subql #4,%sp /* dummy return address*/ SAVE_SWITCH_STACK pea %sp@(SWITCH_STACK_SIZE) - clrl %sp@- bsrw do_signal - addql #8,%sp + addql #4,%sp RESTORE_SWITCH_STACK addql #4,%sp -Lreturn: - RESTORE_ALL + jra 1b /* * This is the main interrupt handler, responsible for calling do_IRQ() diff --git a/arch/m68knommu/platform/coldfire/entry.S b/arch/m68knommu/platform/coldfire/entry.S index 5e92bed94b7..e1debc8285e 100644 --- a/arch/m68knommu/platform/coldfire/entry.S +++ b/arch/m68knommu/platform/coldfire/entry.S @@ -167,12 +167,11 @@ Lsignal_return: subql #4,%sp /* dummy return address */ SAVE_SWITCH_STACK pea %sp@(SWITCH_STACK_SIZE) - clrl %sp@- jsr do_signal - addql #8,%sp + addql #4,%sp RESTORE_SWITCH_STACK addql #4,%sp - jmp Lreturn + jmp Luser_return /* * This is the generic interrupt handler (for all hardware interrupt diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 387d5ffdfd3..5f5018a71a3 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -14,7 +14,7 @@ config MICROBLAZE select HAVE_DMA_API_DEBUG select TRACING_SUPPORT select OF - select OF_FLATTREE + select OF_EARLY_FLATTREE config SWAP def_bool n diff --git a/arch/microblaze/Kconfig.debug b/arch/microblaze/Kconfig.debug index e66e25c4b0b..012e377330c 100644 --- a/arch/microblaze/Kconfig.debug +++ b/arch/microblaze/Kconfig.debug @@ -23,8 +23,4 @@ config HEART_BEAT This option turns on/off heart beat kernel functionality. First GPIO node is taken. -config DEBUG_BOOTMEM - depends on DEBUG_KERNEL - bool "Debug BOOTMEM initialization" - endmenu diff --git a/arch/microblaze/Makefile b/arch/microblaze/Makefile index 15f1f1d1840..6f432e6df9a 100644 --- a/arch/microblaze/Makefile +++ b/arch/microblaze/Makefile @@ -17,7 +17,7 @@ export CPU_VER CPU_MAJOR CPU_MINOR CPU_REV # The various CONFIG_XILINX cpu features options are integers 0/1/2... # rather than bools y/n -# Work out HW multipler support. This is icky. +# Work out HW multipler support. This is tricky. # 1. Spartan2 has no HW multiplers. # 2. MicroBlaze v3.x always uses them, except in Spartan 2 # 3. All other FPGa/CPU ver combos, we can trust the CONFIG_ settings diff --git a/arch/microblaze/boot/Makefile b/arch/microblaze/boot/Makefile index be01d78750d..4c4e58ef0cb 100644 --- a/arch/microblaze/boot/Makefile +++ b/arch/microblaze/boot/Makefile @@ -10,9 +10,6 @@ targets := linux.bin linux.bin.gz simpleImage.% OBJCOPYFLAGS := -O binary -# Where the DTS files live -dtstree := $(srctree)/$(src)/dts - # Ensure system.dtb exists $(obj)/linked_dtb.o: $(obj)/system.dtb @@ -51,14 +48,11 @@ $(obj)/simpleImage.%: vmlinux FORCE $(call if_changed,strip) @echo 'Kernel: $@ is ready' ' (#'`cat .version`')' -# Rule to build device tree blobs -DTC = $(objtree)/scripts/dtc/dtc # Rule to build device tree blobs -quiet_cmd_dtc = DTC $@ - cmd_dtc = $(DTC) -O dtb -o $(obj)/$*.dtb -b 0 -p 1024 $(dtstree)/$*.dts +DTC_FLAGS := -p 1024 -$(obj)/%.dtb: $(dtstree)/%.dts FORCE - $(call if_changed,dtc) +$(obj)/%.dtb: $(src)/dts/%.dts FORCE + $(call cmd,dtc) clean-files += *.dtb simpleImage.*.unstrip linux.bin.ub diff --git a/arch/microblaze/configs/mmu_defconfig b/arch/microblaze/configs/mmu_defconfig index 8b422b12ef7..ab8fbe7ad90 100644 --- a/arch/microblaze/configs/mmu_defconfig +++ b/arch/microblaze/configs/mmu_defconfig @@ -66,5 +66,4 @@ CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_INFO=y # CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_EARLY_PRINTK=y -CONFIG_DEBUG_BOOTMEM=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/microblaze/include/asm/prom.h b/arch/microblaze/include/asm/prom.h index bdc38312ae4..2e72af078b0 100644 --- a/arch/microblaze/include/asm/prom.h +++ b/arch/microblaze/include/asm/prom.h @@ -64,9 +64,6 @@ extern void kdump_move_device_tree(void); /* CPU OF node matching */ struct device_node *of_get_cpu_node(int cpu, unsigned int *thread); -/* Get the MAC address */ -extern const void *of_get_mac_address(struct device_node *np); - /** * of_irq_map_pci - Resolve the interrupt for a PCI device * @pdev: the device whose interrupt is to be resolved diff --git a/arch/microblaze/include/asm/pvr.h b/arch/microblaze/include/asm/pvr.h index 37db96a15b4..a10bec62e85 100644 --- a/arch/microblaze/include/asm/pvr.h +++ b/arch/microblaze/include/asm/pvr.h @@ -1,9 +1,9 @@ /* * Support for the MicroBlaze PVR (Processor Version Register) * - * Copyright (C) 2009 Michal Simek <monstr@monstr.eu> + * Copyright (C) 2009 - 2011 Michal Simek <monstr@monstr.eu> * Copyright (C) 2007 John Williams <john.williams@petalogix.com> - * Copyright (C) 2007 - 2009 PetaLogix + * Copyright (C) 2007 - 2011 PetaLogix * * This file is subject to the terms and conditions of the GNU General * Public License. See the file COPYING in the main directory of this @@ -46,11 +46,11 @@ struct pvr_s { #define PVR2_I_LMB_MASK 0x10000000 #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000 #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000 -#define PVR2_D_PLB_MASK 0x02000000 /* new */ -#define PVR2_I_PLB_MASK 0x01000000 /* new */ -#define PVR2_INTERCONNECT 0x00800000 /* new */ -#define PVR2_USE_EXTEND_FSL 0x00080000 /* new */ -#define PVR2_USE_FSL_EXC 0x00040000 /* new */ +#define PVR2_D_PLB_MASK 0x02000000 /* new */ +#define PVR2_I_PLB_MASK 0x01000000 /* new */ +#define PVR2_INTERCONNECT 0x00800000 /* new */ +#define PVR2_USE_EXTEND_FSL 0x00080000 /* new */ +#define PVR2_USE_FSL_EXC 0x00040000 /* new */ #define PVR2_USE_MSR_INSTR 0x00020000 #define PVR2_USE_PCMP_INSTR 0x00010000 #define PVR2_AREA_OPTIMISED 0x00008000 @@ -59,7 +59,7 @@ struct pvr_s { #define PVR2_USE_HW_MUL_MASK 0x00001000 #define PVR2_USE_FPU_MASK 0x00000800 #define PVR2_USE_MUL64_MASK 0x00000400 -#define PVR2_USE_FPU2_MASK 0x00000200 /* new */ +#define PVR2_USE_FPU2_MASK 0x00000200 /* new */ #define PVR2_USE_IPLBEXC 0x00000100 #define PVR2_USE_DPLBEXC 0x00000080 #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040 @@ -122,96 +122,103 @@ struct pvr_s { /* PVR access macros */ -#define PVR_IS_FULL(pvr) (pvr.pvr[0] & PVR0_PVR_FULL_MASK) -#define PVR_USE_BARREL(pvr) (pvr.pvr[0] & PVR0_USE_BARREL_MASK) -#define PVR_USE_DIV(pvr) (pvr.pvr[0] & PVR0_USE_DIV_MASK) -#define PVR_USE_HW_MUL(pvr) (pvr.pvr[0] & PVR0_USE_HW_MUL_MASK) -#define PVR_USE_FPU(pvr) (pvr.pvr[0] & PVR0_USE_FPU_MASK) -#define PVR_USE_FPU2(pvr) (pvr.pvr[2] & PVR2_USE_FPU2_MASK) -#define PVR_USE_ICACHE(pvr) (pvr.pvr[0] & PVR0_USE_ICACHE_MASK) -#define PVR_USE_DCACHE(pvr) (pvr.pvr[0] & PVR0_USE_DCACHE_MASK) -#define PVR_VERSION(pvr) ((pvr.pvr[0] & PVR0_VERSION_MASK) >> 8) -#define PVR_USER1(pvr) (pvr.pvr[0] & PVR0_USER1_MASK) -#define PVR_USER2(pvr) (pvr.pvr[1] & PVR1_USER2_MASK) - -#define PVR_D_OPB(pvr) (pvr.pvr[2] & PVR2_D_OPB_MASK) -#define PVR_D_LMB(pvr) (pvr.pvr[2] & PVR2_D_LMB_MASK) -#define PVR_I_OPB(pvr) (pvr.pvr[2] & PVR2_I_OPB_MASK) -#define PVR_I_LMB(pvr) (pvr.pvr[2] & PVR2_I_LMB_MASK) -#define PVR_INTERRUPT_IS_EDGE(pvr) \ - (pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK) -#define PVR_EDGE_IS_POSITIVE(pvr) \ - (pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK) -#define PVR_USE_MSR_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_MSR_INSTR) -#define PVR_USE_PCMP_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_PCMP_INSTR) -#define PVR_AREA_OPTIMISED(pvr) (pvr.pvr[2] & PVR2_AREA_OPTIMISED) -#define PVR_USE_MUL64(pvr) (pvr.pvr[2] & PVR2_USE_MUL64_MASK) -#define PVR_OPCODE_0x0_ILLEGAL(pvr) \ - (pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK) -#define PVR_UNALIGNED_EXCEPTION(pvr) \ - (pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK) -#define PVR_ILL_OPCODE_EXCEPTION(pvr) \ - (pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK) -#define PVR_IOPB_BUS_EXCEPTION(pvr) \ - (pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK) -#define PVR_DOPB_BUS_EXCEPTION(pvr) \ - (pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK) -#define PVR_DIV_ZERO_EXCEPTION(pvr) \ - (pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK) -#define PVR_FPU_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_FPU_EXC_MASK) -#define PVR_FSL_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_USE_EXTEND_FSL) - -#define PVR_DEBUG_ENABLED(pvr) (pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK) -#define PVR_NUMBER_OF_PC_BRK(pvr) \ - ((pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25) -#define PVR_NUMBER_OF_RD_ADDR_BRK(pvr) \ - ((pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19) -#define PVR_NUMBER_OF_WR_ADDR_BRK(pvr) \ - ((pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13) -#define PVR_FSL_LINKS(pvr) ((pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7) - -#define PVR_ICACHE_ADDR_TAG_BITS(pvr) \ - ((pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26) -#define PVR_ICACHE_USE_FSL(pvr) (pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK) -#define PVR_ICACHE_ALLOW_WR(pvr) (pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK) -#define PVR_ICACHE_LINE_LEN(pvr) \ - (1 << ((pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21)) -#define PVR_ICACHE_BYTE_SIZE(pvr) \ - (1 << ((pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16)) - -#define PVR_DCACHE_ADDR_TAG_BITS(pvr) \ - ((pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26) -#define PVR_DCACHE_USE_FSL(pvr) (pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK) -#define PVR_DCACHE_ALLOW_WR(pvr) (pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK) +#define PVR_IS_FULL(_pvr) (_pvr.pvr[0] & PVR0_PVR_FULL_MASK) +#define PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & PVR0_USE_BARREL_MASK) +#define PVR_USE_DIV(_pvr) (_pvr.pvr[0] & PVR0_USE_DIV_MASK) +#define PVR_USE_HW_MUL(_pvr) (_pvr.pvr[0] & PVR0_USE_HW_MUL_MASK) +#define PVR_USE_FPU(_pvr) (_pvr.pvr[0] & PVR0_USE_FPU_MASK) +#define PVR_USE_FPU2(_pvr) (_pvr.pvr[2] & PVR2_USE_FPU2_MASK) +#define PVR_USE_ICACHE(_pvr) (_pvr.pvr[0] & PVR0_USE_ICACHE_MASK) +#define PVR_USE_DCACHE(_pvr) (_pvr.pvr[0] & PVR0_USE_DCACHE_MASK) +#define PVR_VERSION(_pvr) ((_pvr.pvr[0] & PVR0_VERSION_MASK) >> 8) +#define PVR_USER1(_pvr) (_pvr.pvr[0] & PVR0_USER1_MASK) +#define PVR_USER2(_pvr) (_pvr.pvr[1] & PVR1_USER2_MASK) + +#define PVR_D_OPB(_pvr) (_pvr.pvr[2] & PVR2_D_OPB_MASK) +#define PVR_D_LMB(_pvr) (_pvr.pvr[2] & PVR2_D_LMB_MASK) +#define PVR_I_OPB(_pvr) (_pvr.pvr[2] & PVR2_I_OPB_MASK) +#define PVR_I_LMB(_pvr) (_pvr.pvr[2] & PVR2_I_LMB_MASK) +#define PVR_INTERRUPT_IS_EDGE(_pvr) \ + (_pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK) +#define PVR_EDGE_IS_POSITIVE(_pvr) \ + (_pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK) +#define PVR_USE_MSR_INSTR(_pvr) (_pvr.pvr[2] & PVR2_USE_MSR_INSTR) +#define PVR_USE_PCMP_INSTR(_pvr) (_pvr.pvr[2] & PVR2_USE_PCMP_INSTR) +#define PVR_AREA_OPTIMISED(_pvr) (_pvr.pvr[2] & PVR2_AREA_OPTIMISED) +#define PVR_USE_MUL64(_pvr) (_pvr.pvr[2] & PVR2_USE_MUL64_MASK) +#define PVR_OPCODE_0x0_ILLEGAL(_pvr) \ + (_pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK) +#define PVR_UNALIGNED_EXCEPTION(_pvr) \ + (_pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK) +#define PVR_ILL_OPCODE_EXCEPTION(_pvr) \ + (_pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK) +#define PVR_IOPB_BUS_EXCEPTION(_pvr) \ + (_pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK) +#define PVR_DOPB_BUS_EXCEPTION(_pvr) \ + (_pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK) +#define PVR_DIV_ZERO_EXCEPTION(_pvr) \ + (_pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK) +#define PVR_FPU_EXCEPTION(_pvr) (_pvr.pvr[2] & PVR2_FPU_EXC_MASK) +#define PVR_FSL_EXCEPTION(_pvr) (_pvr.pvr[2] & PVR2_USE_EXTEND_FSL) + +#define PVR_DEBUG_ENABLED(_pvr) (_pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK) +#define PVR_NUMBER_OF_PC_BRK(_pvr) \ + ((_pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25) +#define PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) \ + ((_pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19) +#define PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) \ + ((_pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13) +#define PVR_FSL_LINKS(_pvr) ((_pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7) + +#define PVR_ICACHE_ADDR_TAG_BITS(_pvr) \ + ((_pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26) +#define PVR_ICACHE_USE_FSL(_pvr) \ + (_pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK) +#define PVR_ICACHE_ALLOW_WR(_pvr) \ + (_pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK) +#define PVR_ICACHE_LINE_LEN(_pvr) \ + (1 << ((_pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21)) +#define PVR_ICACHE_BYTE_SIZE(_pvr) \ + (1 << ((_pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16)) + +#define PVR_DCACHE_ADDR_TAG_BITS(_pvr) \ + ((_pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26) +#define PVR_DCACHE_USE_FSL(_pvr) (_pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK) +#define PVR_DCACHE_ALLOW_WR(_pvr) \ + (_pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK) /* FIXME two shifts on one line needs any comment */ -#define PVR_DCACHE_LINE_LEN(pvr) \ - (1 << ((pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21)) -#define PVR_DCACHE_BYTE_SIZE(pvr) \ - (1 << ((pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16)) +#define PVR_DCACHE_LINE_LEN(_pvr) \ + (1 << ((_pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21)) +#define PVR_DCACHE_BYTE_SIZE(_pvr) \ + (1 << ((_pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16)) -#define PVR_DCACHE_USE_WRITEBACK(pvr) \ - ((pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14) +#define PVR_DCACHE_USE_WRITEBACK(_pvr) \ + ((_pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14) -#define PVR_ICACHE_BASEADDR(pvr) (pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK) -#define PVR_ICACHE_HIGHADDR(pvr) (pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK) +#define PVR_ICACHE_BASEADDR(_pvr) \ + (_pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK) +#define PVR_ICACHE_HIGHADDR(_pvr) \ + (_pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK) +#define PVR_DCACHE_BASEADDR(_pvr) \ + (_pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK) +#define PVR_DCACHE_HIGHADDR(_pvr) \ + (_pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK) -#define PVR_DCACHE_BASEADDR(pvr) (pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK) -#define PVR_DCACHE_HIGHADDR(pvr) (pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK) +#define PVR_TARGET_FAMILY(_pvr) \ + ((_pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24) -#define PVR_TARGET_FAMILY(pvr) ((pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24) - -#define PVR_MSR_RESET_VALUE(pvr) \ - (pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK) +#define PVR_MSR_RESET_VALUE(_pvr) \ + (_pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK) /* mmu */ -#define PVR_USE_MMU(pvr) ((pvr.pvr[11] & PVR11_USE_MMU) >> 30) -#define PVR_MMU_ITLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_ITLB_SIZE) -#define PVR_MMU_DTLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_DTLB_SIZE) -#define PVR_MMU_TLB_ACCESS(pvr) (pvr.pvr[11] & PVR11_MMU_TLB_ACCESS) -#define PVR_MMU_ZONES(pvr) (pvr.pvr[11] & PVR11_MMU_ZONES) +#define PVR_USE_MMU(_pvr) ((_pvr.pvr[11] & PVR11_USE_MMU) >> 30) +#define PVR_MMU_ITLB_SIZE(_pvr) (_pvr.pvr[11] & PVR11_MMU_ITLB_SIZE) +#define PVR_MMU_DTLB_SIZE(_pvr) (_pvr.pvr[11] & PVR11_MMU_DTLB_SIZE) +#define PVR_MMU_TLB_ACCESS(_pvr) (_pvr.pvr[11] & PVR11_MMU_TLB_ACCESS) +#define PVR_MMU_ZONES(_pvr) (_pvr.pvr[11] & PVR11_MMU_ZONES) /* endian */ -#define PVR_ENDIAN(pvr) (pvr.pvr[0] & PVR0_ENDI) +#define PVR_ENDIAN(_pvr) (_pvr.pvr[0] & PVR0_ENDI) int cpu_has_pvr(void); void get_pvr(struct pvr_s *pvr); diff --git a/arch/microblaze/kernel/cpu/cpuinfo.c b/arch/microblaze/kernel/cpu/cpuinfo.c index 87c79fa275c..2c309fccf23 100644 --- a/arch/microblaze/kernel/cpu/cpuinfo.c +++ b/arch/microblaze/kernel/cpu/cpuinfo.c @@ -32,6 +32,7 @@ const struct cpu_ver_key cpu_ver_lookup[] = { {"7.30.a", 0x10}, {"7.30.b", 0x11}, {"8.00.a", 0x12}, + {"8.00.b", 0x13}, {NULL, 0}, }; diff --git a/arch/microblaze/kernel/entry.S b/arch/microblaze/kernel/entry.S index 819238b8a42..41c30cdb270 100644 --- a/arch/microblaze/kernel/entry.S +++ b/arch/microblaze/kernel/entry.S @@ -287,25 +287,44 @@ * are masked. This is nice, means we don't have to CLI before state save */ C_ENTRY(_user_exception): - addi r14, r14, 4 /* return address is 4 byte after call */ swi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */ + addi r14, r14, 4 /* return address is 4 byte after call */ + + mfs r1, rmsr + nop + andi r1, r1, MSR_UMS + bnei r1, 1f + +/* Kernel-mode state save - kernel execve */ + lwi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* Reload kernel stack-ptr*/ + tophys(r1,r1); + + addik r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack. */ + SAVE_REGS + swi r1, r1, PTO + PT_MODE; /* pt_regs -> kernel mode */ + brid 2f; + nop; /* Fill delay slot */ + +/* User-mode state save. */ +1: lwi r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */ tophys(r1,r1); lwi r1, r1, TS_THREAD_INFO; /* get stack from task_struct */ - /* MS these three instructions can be added to one */ - /* addik r1, r1, THREAD_SIZE; */ - /* tophys(r1,r1); */ - /* addik r1, r1, -STATE_SAVE_SIZE; */ - addik r1, r1, THREAD_SIZE + CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE; +/* calculate kernel stack pointer from task struct 8k */ + addik r1, r1, THREAD_SIZE; + tophys(r1,r1); + + addik r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack. */ SAVE_REGS swi r0, r1, PTO + PT_R3 swi r0, r1, PTO + PT_R4 + swi r0, r1, PTO + PT_MODE; /* Was in user-mode. */ lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); swi r11, r1, PTO+PT_R1; /* Store user SP. */ clear_ums; - lwi CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); +2: lwi CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* Save away the syscall number. */ swi r12, r1, PTO+PT_R0; tovirt(r1,r1) @@ -375,6 +394,9 @@ C_ENTRY(ret_from_trap): swi r3, r1, PTO + PT_R3 swi r4, r1, PTO + PT_R4 + lwi r11, r1, PTO + PT_MODE; +/* See if returning to kernel mode, if so, skip resched &c. */ + bnei r11, 2f; /* We're returning to user mode, so check for various conditions that * trigger rescheduling. */ /* FIXME: Restructure all these flag checks. */ @@ -417,6 +439,16 @@ C_ENTRY(ret_from_trap): RESTORE_REGS; addik r1, r1, STATE_SAVE_SIZE /* Clean up stack space. */ lwi r1, r1, PT_R1 - PT_SIZE;/* Restore user stack pointer. */ + bri 6f; + +/* Return to kernel state. */ +2: set_bip; /* Ints masked for state restore */ + VM_OFF; + tophys(r1,r1); + RESTORE_REGS; + addik r1, r1, STATE_SAVE_SIZE /* Clean up stack space. */ + tovirt(r1,r1); +6: TRAP_return: /* Make global symbol for debugging */ rtbd r14, 0; /* Instructions to return from an IRQ */ nop; diff --git a/arch/microblaze/kernel/exceptions.c b/arch/microblaze/kernel/exceptions.c index 478f2943ede..a7fa6ae76d8 100644 --- a/arch/microblaze/kernel/exceptions.c +++ b/arch/microblaze/kernel/exceptions.c @@ -25,6 +25,7 @@ #include <linux/errno.h> #include <linux/ptrace.h> #include <asm/current.h> +#include <asm/cacheflush.h> #define MICROBLAZE_ILL_OPCODE_EXCEPTION 0x02 #define MICROBLAZE_IBUS_EXCEPTION 0x03 @@ -52,6 +53,8 @@ void die(const char *str, struct pt_regs *fp, long err) void sw_exception(struct pt_regs *regs) { _exception(SIGTRAP, regs, TRAP_BRKPT, regs->r16); + flush_dcache_range(regs->r16, regs->r16 + 0x4); + flush_icache_range(regs->r16, regs->r16 + 0x4); } void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S index 781195438ee..25f6e07d8de 100644 --- a/arch/microblaze/kernel/hw_exception_handler.S +++ b/arch/microblaze/kernel/hw_exception_handler.S @@ -945,11 +945,20 @@ store3: sbi r3, r4, 2; store4: sbi r3, r4, 3; /* Delay slot */ ex_shw_vm: /* Store the lower half-word, byte-by-byte into destination address */ +#ifdef __MICROBLAZEEL__ + lbui r3, r5, 0; +store5: sbi r3, r4, 0; + lbui r3, r5, 1; + brid ret_from_exc; +store6: sbi r3, r4, 1; /* Delay slot */ +#else lbui r3, r5, 2; store5: sbi r3, r4, 0; lbui r3, r5, 3; brid ret_from_exc; store6: sbi r3, r4, 1; /* Delay slot */ +#endif + ex_sw_end_vm: /* Exception handling of store word, ends. */ /* We have to prevent cases that get/put_user macros get unaligned pointer diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/prom.c index a105301e2b7..c881393f07f 100644 --- a/arch/microblaze/kernel/prom.c +++ b/arch/microblaze/kernel/prom.c @@ -61,14 +61,12 @@ static int __init early_init_dt_scan_serial(unsigned long node, char *p; int *addr; - pr_debug("search \"chosen\", depth: %d, uname: %s\n", depth, uname); + pr_debug("search \"serial\", depth: %d, uname: %s\n", depth, uname); /* find all serial nodes */ if (strncmp(uname, "serial", 6) != 0) return 0; - early_init_dt_check_for_initrd(node); - /* find compatible node with uartlite */ p = of_get_flat_dt_prop(node, "compatible", &l); if ((strncmp(p, "xlnx,xps-uartlite", 17) != 0) && diff --git a/arch/microblaze/kernel/prom_parse.c b/arch/microblaze/kernel/prom_parse.c index 99d9b61cccb..9ae24f4b882 100644 --- a/arch/microblaze/kernel/prom_parse.c +++ b/arch/microblaze/kernel/prom_parse.c @@ -110,41 +110,3 @@ void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop, cells = prop ? *(u32 *)prop : of_n_size_cells(dn); *size = of_read_number(dma_window, cells); } - -/** - * Search the device tree for the best MAC address to use. 'mac-address' is - * checked first, because that is supposed to contain to "most recent" MAC - * address. If that isn't set, then 'local-mac-address' is checked next, - * because that is the default address. If that isn't set, then the obsolete - * 'address' is checked, just in case we're using an old device tree. - * - * Note that the 'address' property is supposed to contain a virtual address of - * the register set, but some DTS files have redefined that property to be the - * MAC address. - * - * All-zero MAC addresses are rejected, because those could be properties that - * exist in the device tree, but were not set by U-Boot. For example, the - * DTS could define 'mac-address' and 'local-mac-address', with zero MAC - * addresses. Some older U-Boots only initialized 'local-mac-address'. In - * this case, the real MAC is in 'local-mac-address', and 'mac-address' exists - * but is all zeros. -*/ -const void *of_get_mac_address(struct device_node *np) -{ - struct property *pp; - - pp = of_find_property(np, "mac-address", NULL); - if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value)) - return pp->value; - - pp = of_find_property(np, "local-mac-address", NULL); - if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value)) - return pp->value; - - pp = of_find_property(np, "address", NULL); - if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value)) - return pp->value; - - return NULL; -} -EXPORT_SYMBOL(of_get_mac_address); diff --git a/arch/microblaze/kernel/vmlinux.lds.S b/arch/microblaze/kernel/vmlinux.lds.S index 96a88c31fe4..3451bdec9f0 100644 --- a/arch/microblaze/kernel/vmlinux.lds.S +++ b/arch/microblaze/kernel/vmlinux.lds.S @@ -123,20 +123,10 @@ SECTIONS { __init_end_before_initramfs = .; - .init.ramfs ALIGN(PAGE_SIZE) : AT(ADDR(.init.ramfs) - LOAD_OFFSET) { - __initramfs_start = .; - *(.init.ramfs) - __initramfs_end = .; - . = ALIGN(4); - LONG(0); -/* - * FIXME this can break initramfs for MMU. - * Pad init.ramfs up to page boundary, - * so that __init_end == __bss_start. This will make image.elf - * consistent with the image.bin - */ - /* . = ALIGN(PAGE_SIZE); */ + .init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) { + INIT_RAM_FS } + __init_end = .; .bss ALIGN (PAGE_SIZE) : AT(ADDR(.bss) - LOAD_OFFSET) { diff --git a/arch/microblaze/lib/memmove.c b/arch/microblaze/lib/memmove.c index 123e3616f2d..810fd68775e 100644 --- a/arch/microblaze/lib/memmove.c +++ b/arch/microblaze/lib/memmove.c @@ -182,7 +182,7 @@ void *memmove(void *v_dst, const void *v_src, __kernel_size_t c) for (; c >= 4; c -= 4) { value = *--i_src; *--i_dst = buf_hold | ((value & 0xFF000000)>> 24); - buf_hold = (value & 0xFFFFFF) << 8;; + buf_hold = (value & 0xFFFFFF) << 8; } #endif /* Realign the source */ diff --git a/arch/microblaze/lib/muldi3.S b/arch/microblaze/lib/muldi3.S deleted file mode 100644 index ceeaa8c407f..00000000000 --- a/arch/microblaze/lib/muldi3.S +++ /dev/null @@ -1,121 +0,0 @@ -#include <linux/linkage.h> - -/* - * Multiply operation for 64 bit integers, for devices with hard multiply - * Input : Operand1[H] in Reg r5 - * Operand1[L] in Reg r6 - * Operand2[H] in Reg r7 - * Operand2[L] in Reg r8 - * Output: Result[H] in Reg r3 - * Result[L] in Reg r4 - * - * Explaination: - * - * Both the input numbers are divided into 16 bit number as follows - * op1 = A B C D - * op2 = E F G H - * result = D * H - * + (C * H + D * G) << 16 - * + (B * H + C * G + D * F) << 32 - * + (A * H + B * G + C * F + D * E) << 48 - * - * Only 64 bits of the output are considered - */ - - .text - .globl __muldi3 - .type __muldi3, @function - .ent __muldi3 - -__muldi3: - addi r1, r1, -40 - -/* Save the input operands on the caller's stack */ - swi r5, r1, 44 - swi r6, r1, 48 - swi r7, r1, 52 - swi r8, r1, 56 - -/* Store all the callee saved registers */ - sw r20, r1, r0 - swi r21, r1, 4 - swi r22, r1, 8 - swi r23, r1, 12 - swi r24, r1, 16 - swi r25, r1, 20 - swi r26, r1, 24 - swi r27, r1, 28 - -/* Load all the 16 bit values for A thru H */ - lhui r20, r1, 44 /* A */ - lhui r21, r1, 46 /* B */ - lhui r22, r1, 48 /* C */ - lhui r23, r1, 50 /* D */ - lhui r24, r1, 52 /* E */ - lhui r25, r1, 54 /* F */ - lhui r26, r1, 56 /* G */ - lhui r27, r1, 58 /* H */ - -/* D * H ==> LSB of the result on stack ==> Store1 */ - mul r9, r23, r27 - swi r9, r1, 36 /* Pos2 and Pos3 */ - -/* Hi (Store1) + C * H + D * G ==> Store2 ==> Pos1 and Pos2 */ -/* Store the carry generated in position 2 for Pos 3 */ - lhui r11, r1, 36 /* Pos2 */ - mul r9, r22, r27 /* C * H */ - mul r10, r23, r26 /* D * G */ - add r9, r9, r10 - addc r12, r0, r0 - add r9, r9, r11 - addc r12, r12, r0 /* Store the Carry */ - shi r9, r1, 36 /* Store Pos2 */ - swi r9, r1, 32 - lhui r11, r1, 32 - shi r11, r1, 34 /* Store Pos1 */ - -/* Hi (Store2) + B * H + C * G + D * F ==> Store3 ==> Pos0 and Pos1 */ - mul r9, r21, r27 /* B * H */ - mul r10, r22, r26 /* C * G */ - mul r7, r23, r25 /* D * F */ - add r9, r9, r11 - add r9, r9, r10 - add r9, r9, r7 - swi r9, r1, 32 /* Pos0 and Pos1 */ - -/* Hi (Store3) + A * H + B * G + C * F + D * E ==> Store3 ==> Pos0 */ - lhui r11, r1, 32 /* Pos0 */ - mul r9, r20, r27 /* A * H */ - mul r10, r21, r26 /* B * G */ - mul r7, r22, r25 /* C * F */ - mul r8, r23, r24 /* D * E */ - add r9, r9, r11 - add r9, r9, r10 - add r9, r9, r7 - add r9, r9, r8 - sext16 r9, r9 /* Sign extend the MSB */ - shi r9, r1, 32 - -/* Move results to r3 and r4 */ - lhui r3, r1, 32 - add r3, r3, r12 - shi r3, r1, 32 - lwi r3, r1, 32 /* Hi Part */ - lwi r4, r1, 36 /* Lo Part */ - -/* Restore Callee saved registers */ - lw r20, r1, r0 - lwi r21, r1, 4 - lwi r22, r1, 8 - lwi r23, r1, 12 - lwi r24, r1, 16 - lwi r25, r1, 20 - lwi r26, r1, 24 - lwi r27, r1, 28 - -/* Restore Frame and return */ - rtsd r15, 8 - addi r1, r1, 40 - -.size __muldi3, . - __muldi3 -.end __muldi3 diff --git a/arch/microblaze/lib/muldi3.c b/arch/microblaze/lib/muldi3.c new file mode 100644 index 00000000000..d4860e154d2 --- /dev/null +++ b/arch/microblaze/lib/muldi3.c @@ -0,0 +1,60 @@ +#include <linux/module.h> + +#include "libgcc.h" + +#define DWtype long long +#define UWtype unsigned long +#define UHWtype unsigned short + +#define W_TYPE_SIZE 32 + +#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2)) +#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1)) +#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2)) + +/* If we still don't have umul_ppmm, define it using plain C. */ +#if !defined(umul_ppmm) +#define umul_ppmm(w1, w0, u, v) \ + do { \ + UWtype __x0, __x1, __x2, __x3; \ + UHWtype __ul, __vl, __uh, __vh; \ + \ + __ul = __ll_lowpart(u); \ + __uh = __ll_highpart(u); \ + __vl = __ll_lowpart(v); \ + __vh = __ll_highpart(v); \ + \ + __x0 = (UWtype) __ul * __vl; \ + __x1 = (UWtype) __ul * __vh; \ + __x2 = (UWtype) __uh * __vl; \ + __x3 = (UWtype) __uh * __vh; \ + \ + __x1 += __ll_highpart(__x0); /* this can't give carry */\ + __x1 += __x2; /* but this indeed can */ \ + if (__x1 < __x2) /* did we get it? */ \ + __x3 += __ll_B; /* yes, add it in the proper pos */ \ + \ + (w1) = __x3 + __ll_highpart(__x1); \ + (w0) = __ll_lowpart(__x1) * __ll_B + __ll_lowpart(__x0);\ + } while (0) +#endif + +#if !defined(__umulsidi3) +#define __umulsidi3(u, v) ({ \ + DWunion __w; \ + umul_ppmm(__w.s.high, __w.s.low, u, v); \ + __w.ll; \ + }) +#endif + +DWtype __muldi3(DWtype u, DWtype v) +{ + const DWunion uu = {.ll = u}; + const DWunion vv = {.ll = v}; + DWunion w = {.ll = __umulsidi3(uu.s.low, vv.s.low)}; + + w.s.high += ((UWtype) uu.s.low * (UWtype) vv.s.high + + (UWtype) uu.s.high * (UWtype) vv.s.low); + + return w.ll; +} diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 0a9b5b8b2a1..f489ec30e07 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2218,7 +2218,7 @@ config SECCOMP config USE_OF bool "Flattened Device Tree support" select OF - select OF_FLATTREE + select OF_EARLY_FLATTREE help Include support for flattened device tree machine descriptions. diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c index 02f505f23c3..ea57f39e673 100644 --- a/arch/mips/dec/time.c +++ b/arch/mips/dec/time.c @@ -104,7 +104,7 @@ int rtc_mips_set_mmss(unsigned long nowtime) CMOS_WRITE(real_seconds, RTC_SECONDS); CMOS_WRITE(real_minutes, RTC_MINUTES); } else { - printk(KERN_WARNING + printk_once(KERN_NOTICE "set_rtc_mmss: can't update from %d to %d\n", cmos_minutes, real_minutes); retval = -1; diff --git a/arch/mips/include/asm/mc146818-time.h b/arch/mips/include/asm/mc146818-time.h index 199b45733a9..4a08dbe37db 100644 --- a/arch/mips/include/asm/mc146818-time.h +++ b/arch/mips/include/asm/mc146818-time.h @@ -66,7 +66,7 @@ static inline int mc146818_set_rtc_mmss(unsigned long nowtime) CMOS_WRITE(real_seconds, RTC_SECONDS); CMOS_WRITE(real_minutes, RTC_MINUTES); } else { - printk(KERN_WARNING + printk_once(KERN_NOTICE "set_rtc_mmss: can't update from %d to %d\n", cmos_minutes, real_minutes); retval = -1; diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig index 41ba38513c8..8ed41cf2b08 100644 --- a/arch/mn10300/Kconfig +++ b/arch/mn10300/Kconfig @@ -203,6 +203,7 @@ endmenu config SMP bool "Symmetric multi-processing support" default y + select USE_GENERIC_SMP_HELPERS depends on MN10300_PROC_MN2WS0038 || MN10300_PROC_MN2WS0050 ---help--- This enables support for systems with more than one CPU. If you have @@ -226,11 +227,6 @@ config NR_CPUS depends on SMP default "2" -config USE_GENERIC_SMP_HELPERS - bool - depends on SMP - default y - source "kernel/Kconfig.preempt" config MN10300_CURRENT_IN_E2 diff --git a/arch/mn10300/kernel/rtc.c b/arch/mn10300/kernel/rtc.c index e9e20f9a4dd..48d7058b329 100644 --- a/arch/mn10300/kernel/rtc.c +++ b/arch/mn10300/kernel/rtc.c @@ -89,7 +89,7 @@ static int set_rtc_mmss(unsigned long nowtime) CMOS_WRITE(real_seconds, RTC_SECONDS); CMOS_WRITE(real_minutes, RTC_MINUTES); } else { - printk(KERN_WARNING + printk_once(KERN_NOTICE "set_rtc_mmss: can't update from %d to %d\n", cmos_minutes, real_minutes); retval = -1; diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index e625e9e034a..959f38ccb9a 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -20,6 +20,9 @@ config WORD_SIZE config ARCH_PHYS_ADDR_T_64BIT def_bool PPC64 || PHYS_64BIT +config ARCH_DMA_ADDR_T_64BIT + def_bool ARCH_PHYS_ADDR_T_64BIT + config MMU bool default y @@ -116,7 +119,7 @@ config PPC bool default y select OF - select OF_FLATTREE + select OF_EARLY_FLATTREE select HAVE_FTRACE_MCOUNT_RECORD select HAVE_DYNAMIC_FTRACE select HAVE_FUNCTION_TRACER @@ -209,7 +212,7 @@ config ARCH_HIBERNATION_POSSIBLE config ARCH_SUSPEND_POSSIBLE def_bool y depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \ - PPC_85xx || PPC_86xx || PPC_PSERIES + PPC_85xx || PPC_86xx || PPC_PSERIES || 44x || 40x config PPC_DCR_NATIVE bool @@ -595,13 +598,11 @@ config EXTRA_TARGETS If unsure, leave blank -if !44x || BROKEN config ARCH_WANTS_FREEZER_CONTROL def_bool y depends on ADB_PMU source kernel/power/Kconfig -endif config SECCOMP bool "Enable seccomp to safely compute untrusted bytecode" @@ -682,6 +683,15 @@ config FSL_PMC Freescale MPC85xx/MPC86xx power management controller support (suspend/resume). For MPC83xx see platforms/83xx/suspend.c +config PPC4xx_CPM + bool + default y + depends on SUSPEND && (44x || 40x) + help + PPC4xx Clock Power Management (CPM) support (suspend/resume). + It also enables support for two different idle states (idle-wait + and idle-doze). + config 4xx_SOC bool diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index fae8192c8fc..96deec63bcf 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -35,7 +35,7 @@ endif BOOTCFLAGS += -I$(obj) -I$(srctree)/$(obj) -DTS_FLAGS ?= -p 1024 +DTC_FLAGS ?= -p 1024 $(obj)/4xx.o: BOOTCFLAGS += -mcpu=405 $(obj)/ebony.o: BOOTCFLAGS += -mcpu=405 @@ -332,10 +332,8 @@ $(obj)/treeImage.%: vmlinux $(obj)/%.dtb $(wrapperbits) $(call if_changed,wrap,treeboot-$*,,$(obj)/$*.dtb) # Rule to build device tree blobs -DTC = $(objtree)/scripts/dtc/dtc - -$(obj)/%.dtb: $(dtstree)/%.dts - $(DTC) -O dtb -o $(obj)/$*.dtb -b 0 $(DTS_FLAGS) $(dtstree)/$*.dts +$(obj)/%.dtb: $(src)/dts/%.dts + $(call cmd,dtc) # If there isn't a platform selected then just strip the vmlinux. ifeq (,$(image-y)) diff --git a/arch/powerpc/boot/dts/bluestone.dts b/arch/powerpc/boot/dts/bluestone.dts index 9bb3d72c0e5..2a56a0dbd1f 100644 --- a/arch/powerpc/boot/dts/bluestone.dts +++ b/arch/powerpc/boot/dts/bluestone.dts @@ -33,7 +33,7 @@ aliases { ethernet0 = &EMAC0; serial0 = &UART0; - serial1 = &UART1; + //serial1 = &UART1; --gcl missing UART1 label }; cpus { @@ -52,7 +52,7 @@ d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; - next-level-cache = <&L2C0>; + //next-level-cache = <&L2C0>; --gcl missing L2C0 label }; }; @@ -142,7 +142,7 @@ /*RXEOB*/ 0x7 0x4 /*SERR*/ 0x3 0x4 /*TXDE*/ 0x4 0x4 - /*RXDE*/ 0x5 0x4 + /*RXDE*/ 0x5 0x4>; }; POB0: opb { @@ -182,7 +182,7 @@ reg = <0x001a0000 0x00060000>; }; }; - } + }; UART0: serial@ef600300 { device_type = "serial"; diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts index a3037039625..5b27a4b74b7 100644 --- a/arch/powerpc/boot/dts/canyonlands.dts +++ b/arch/powerpc/boot/dts/canyonlands.dts @@ -105,6 +105,15 @@ dcr-reg = <0x00c 0x002>; }; + CPM0: cpm { + compatible = "ibm,cpm"; + dcr-access-method = "native"; + dcr-reg = <0x160 0x003>; + unused-units = <0x00000100>; + idle-doze = <0x02000000>; + standby = <0xfeff791d>; + }; + L2C0: l2c { compatible = "ibm,l2-cache-460ex", "ibm,l2-cache"; dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ @@ -270,28 +279,6 @@ interrupts = <0x1 0x4>; }; - UART2: serial@ef600500 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0xef600500 0x00000008>; - virtual-reg = <0xef600500>; - clock-frequency = <0>; /* Filled in by U-Boot */ - current-speed = <0>; /* Filled in by U-Boot */ - interrupt-parent = <&UIC1>; - interrupts = <28 0x4>; - }; - - UART3: serial@ef600600 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0xef600600 0x00000008>; - virtual-reg = <0xef600600>; - clock-frequency = <0>; /* Filled in by U-Boot */ - current-speed = <0>; /* Filled in by U-Boot */ - interrupt-parent = <&UIC1>; - interrupts = <29 0x4>; - }; - IIC0: i2c@ef600700 { compatible = "ibm,iic-460ex", "ibm,iic"; reg = <0xef600700 0x00000014>; diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts index dd3860846f1..ad3a4f4a2b0 100644 --- a/arch/powerpc/boot/dts/cm5200.dts +++ b/arch/powerpc/boot/dts/cm5200.dts @@ -10,220 +10,74 @@ * option) any later version. */ -/dts-v1/; +/include/ "mpc5200b.dtsi" / { model = "schindler,cm5200"; compatible = "schindler,cm5200"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&mpc5200_pic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - PowerPC,5200@0 { - device_type = "cpu"; - reg = <0>; - d-cache-line-size = <32>; - i-cache-line-size = <32>; - d-cache-size = <0x4000>; // L1, 16K - i-cache-size = <0x4000>; // L1, 16K - timebase-frequency = <0>; // from bootloader - bus-frequency = <0>; // from bootloader - clock-frequency = <0>; // from bootloader - }; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x04000000>; // 64MB - }; soc5200@f0000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc5200b-immr"; - ranges = <0 0xf0000000 0x0000c000>; - reg = <0xf0000000 0x00000100>; - bus-frequency = <0>; // from bootloader - system-frequency = <0>; // from bootloader - - cdm@200 { - compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; - reg = <0x200 0x38>; - }; - - mpc5200_pic: interrupt-controller@500 { - // 5200 interrupts are encoded into two levels; - interrupt-controller; - #interrupt-cells = <3>; - compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; - reg = <0x500 0x80>; - }; - timer@600 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x600 0x10>; - interrupts = <1 9 0>; fsl,has-wdt; }; - timer@610 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x610 0x10>; - interrupts = <1 10 0>; - }; - - timer@620 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x620 0x10>; - interrupts = <1 11 0>; - }; - - timer@630 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x630 0x10>; - interrupts = <1 12 0>; - }; - - timer@640 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x640 0x10>; - interrupts = <1 13 0>; - }; - - timer@650 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x650 0x10>; - interrupts = <1 14 0>; - }; - - timer@660 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x660 0x10>; - interrupts = <1 15 0>; - }; - - timer@670 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x670 0x10>; - interrupts = <1 16 0>; + can@900 { + status = "disabled"; }; - rtc@800 { // Real time clock - compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; - reg = <0x800 0x100>; - interrupts = <1 5 0 1 6 0>; + can@980 { + status = "disabled"; }; - gpio_simple: gpio@b00 { - compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; - reg = <0xb00 0x40>; - interrupts = <1 7 0>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio_wkup: gpio@c00 { - compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; - reg = <0xc00 0x40>; - interrupts = <1 8 0 0 3 0>; - gpio-controller; - #gpio-cells = <2>; - }; - - spi@f00 { - compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; - reg = <0xf00 0x20>; - interrupts = <2 13 0 2 14 0>; - }; - - usb@1000 { - compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; - reg = <0x1000 0xff>; - interrupts = <2 6 0>; - }; - - dma-controller@1200 { - compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; - reg = <0x1200 0x80>; - interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 - 3 4 0 3 5 0 3 6 0 3 7 0 - 3 8 0 3 9 0 3 10 0 3 11 0 - 3 12 0 3 13 0 3 14 0 3 15 0>; + psc@2000 { // PSC1 + compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; }; - xlb@1f00 { - compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; - reg = <0x1f00 0x100>; + psc@2200 { // PSC2 + compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; }; - serial@2000 { // PSC1 + psc@2400 { // PSC3 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - reg = <0x2000 0x100>; - interrupts = <2 1 0>; }; - serial@2200 { // PSC2 - compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - reg = <0x2200 0x100>; - interrupts = <2 2 0>; + psc@2600 { // PSC4 + status = "disabled"; }; - serial@2400 { // PSC3 - compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - reg = <0x2400 0x100>; - interrupts = <2 3 0>; + psc@2800 { // PSC5 + status = "disabled"; }; - serial@2c00 { // PSC6 + psc@2c00 { // PSC6 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - reg = <0x2c00 0x100>; - interrupts = <2 4 0>; }; ethernet@3000 { - compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; - reg = <0x3000 0x400>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <2 5 0>; phy-handle = <&phy0>; }; mdio@3000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; - reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts - interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. - phy0: ethernet-phy@0 { reg = <0>; }; }; - i2c@3d40 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; - reg = <0x3d40 0x40>; - interrupts = <2 16 0>; + ata@3a00 { + status = "disabled"; }; - sram@8000 { - compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; - reg = <0x8000 0x4000>; + i2c@3d00 { + status = "disabled"; }; + }; - localbus { - compatible = "fsl,mpc5200b-lpb","simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0xfc000000 0x2000000>; + pci@f0000d00 { + status = "disabled"; + }; + localbus { // 16-bit flash device at LocalPlus Bus CS0 flash@0,0 { compatible = "cfi-flash"; diff --git a/arch/powerpc/boot/dts/digsy_mtc.dts b/arch/powerpc/boot/dts/digsy_mtc.dts index 8e9be6bfe23..27bd267d631 100644 --- a/arch/powerpc/boot/dts/digsy_mtc.dts +++ b/arch/powerpc/boot/dts/digsy_mtc.dts @@ -11,195 +11,68 @@ * option) any later version. */ -/dts-v1/; +/include/ "mpc5200b.dtsi" / { model = "intercontrol,digsy-mtc"; compatible = "intercontrol,digsy-mtc"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&mpc5200_pic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - PowerPC,5200@0 { - device_type = "cpu"; - reg = <0>; - d-cache-line-size = <32>; - i-cache-line-size = <32>; - d-cache-size = <0x4000>; // L1, 16K - i-cache-size = <0x4000>; // L1, 16K - timebase-frequency = <0>; // from bootloader - bus-frequency = <0>; // from bootloader - clock-frequency = <0>; // from bootloader - }; - }; memory { - device_type = "memory"; reg = <0x00000000 0x02000000>; // 32MB }; soc5200@f0000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc5200b-immr"; - ranges = <0 0xf0000000 0x0000c000>; - reg = <0xf0000000 0x00000100>; - bus-frequency = <0>; // from bootloader - system-frequency = <0>; // from bootloader - - cdm@200 { - compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; - reg = <0x200 0x38>; - }; - - mpc5200_pic: interrupt-controller@500 { - // 5200 interrupts are encoded into two levels; - interrupt-controller; - #interrupt-cells = <3>; - compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; - reg = <0x500 0x80>; - }; - timer@600 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x600 0x10>; - interrupts = <1 9 0>; fsl,has-wdt; }; - timer@610 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x610 0x10>; - interrupts = <1 10 0>; - }; - - timer@620 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x620 0x10>; - interrupts = <1 11 0>; - }; - - timer@630 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x630 0x10>; - interrupts = <1 12 0>; - }; - - timer@640 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x640 0x10>; - interrupts = <1 13 0>; - }; - - timer@650 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x650 0x10>; - interrupts = <1 14 0>; + rtc@800 { + status = "disabled"; }; - timer@660 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x660 0x10>; - interrupts = <1 15 0>; + can@900 { + status = "disabled"; }; - timer@670 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x670 0x10>; - interrupts = <1 16 0>; + can@980 { + status = "disabled"; }; - gpio_simple: gpio@b00 { - compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; - reg = <0xb00 0x40>; - interrupts = <1 7 0>; - gpio-controller; - #gpio-cells = <2>; + psc@2000 { // PSC1 + status = "disabled"; }; - gpio_wkup: gpio@c00 { - compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; - reg = <0xc00 0x40>; - interrupts = <1 8 0 0 3 0>; - gpio-controller; - #gpio-cells = <2>; + psc@2200 { // PSC2 + status = "disabled"; }; - spi@f00 { - compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; - reg = <0xf00 0x20>; - interrupts = <2 13 0 2 14 0>; + psc@2400 { // PSC3 + status = "disabled"; }; - usb@1000 { - compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; - reg = <0x1000 0xff>; - interrupts = <2 6 0>; - }; - - dma-controller@1200 { - compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; - reg = <0x1200 0x80>; - interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 - 3 4 0 3 5 0 3 6 0 3 7 0 - 3 8 0 3 9 0 3 10 0 3 11 0 - 3 12 0 3 13 0 3 14 0 3 15 0>; - }; - - xlb@1f00 { - compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; - reg = <0x1f00 0x100>; + psc@2600 { // PSC4 + compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; }; - serial@2600 { // PSC4 + psc@2800 { // PSC5 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - reg = <0x2600 0x100>; - interrupts = <2 11 0>; }; - serial@2800 { // PSC5 - compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - reg = <0x2800 0x100>; - interrupts = <2 12 0>; + psc@2c00 { // PSC6 + status = "disabled"; }; ethernet@3000 { - compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; - reg = <0x3000 0x400>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <2 5 0>; phy-handle = <&phy0>; }; mdio@3000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; - reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts - interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. - phy0: ethernet-phy@0 { reg = <0>; }; }; - ata@3a00 { - compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; - reg = <0x3a00 0x100>; - interrupts = <2 7 0>; - }; - i2c@3d00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; - reg = <0x3d00 0x40>; - interrupts = <2 15 0>; - rtc@50 { compatible = "at,24c08"; reg = <0x50>; @@ -211,16 +84,16 @@ }; }; - sram@8000 { - compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; - reg = <0x8000 0x4000>; + i2c@3d40 { + status = "disabled"; }; }; - lpb { - compatible = "fsl,mpc5200b-lpb","simple-bus"; - #address-cells = <2>; - #size-cells = <1>; + pci@f0000d00 { + status = "disabled"; + }; + + localbus { ranges = <0 0 0xff000000 0x1000000>; // 16-bit flash device at LocalPlus Bus CS0 diff --git a/arch/powerpc/boot/dts/hotfoot.dts b/arch/powerpc/boot/dts/hotfoot.dts index cad9c3840af..71d3bb4931d 100644 --- a/arch/powerpc/boot/dts/hotfoot.dts +++ b/arch/powerpc/boot/dts/hotfoot.dts @@ -117,6 +117,8 @@ }; IIC: i2c@ef600500 { + #address-cells = <1>; + #size-cells = <0>; compatible = "ibm,iic-405ep", "ibm,iic"; reg = <0xef600500 0x00000011>; interrupt-parent = <&UIC0>; diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts index 083e68eeaca..89edb16649c 100644 --- a/arch/powerpc/boot/dts/kilauea.dts +++ b/arch/powerpc/boot/dts/kilauea.dts @@ -82,6 +82,15 @@ interrupt-parent = <&UIC0>; }; + CPM0: cpm { + compatible = "ibm,cpm"; + dcr-access-method = "native"; + dcr-reg = <0x0b0 0x003>; + unused-units = <0x00000000>; + idle-doze = <0x02000000>; + standby = <0xe3e74800>; + }; + plb { compatible = "ibm,plb-405ex", "ibm,plb4"; #address-cells = <1>; diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts index 59702ace900..fb288bb882b 100644 --- a/arch/powerpc/boot/dts/lite5200b.dts +++ b/arch/powerpc/boot/dts/lite5200b.dts @@ -10,256 +10,75 @@ * option) any later version. */ -/dts-v1/; +/include/ "mpc5200b.dtsi" / { model = "fsl,lite5200b"; compatible = "fsl,lite5200b"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&mpc5200_pic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - PowerPC,5200@0 { - device_type = "cpu"; - reg = <0>; - d-cache-line-size = <32>; - i-cache-line-size = <32>; - d-cache-size = <0x4000>; // L1, 16K - i-cache-size = <0x4000>; // L1, 16K - timebase-frequency = <0>; // from bootloader - bus-frequency = <0>; // from bootloader - clock-frequency = <0>; // from bootloader - }; - }; memory { - device_type = "memory"; reg = <0x00000000 0x10000000>; // 256MB }; soc5200@f0000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc5200b-immr"; - ranges = <0 0xf0000000 0x0000c000>; - reg = <0xf0000000 0x00000100>; - bus-frequency = <0>; // from bootloader - system-frequency = <0>; // from bootloader - - cdm@200 { - compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; - reg = <0x200 0x38>; - }; - - mpc5200_pic: interrupt-controller@500 { - // 5200 interrupts are encoded into two levels; - interrupt-controller; - #interrupt-cells = <3>; - compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; - reg = <0x500 0x80>; - }; - timer@600 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x600 0x10>; - interrupts = <1 9 0>; fsl,has-wdt; }; - timer@610 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x610 0x10>; - interrupts = <1 10 0>; - }; - - timer@620 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x620 0x10>; - interrupts = <1 11 0>; - }; - - timer@630 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x630 0x10>; - interrupts = <1 12 0>; - }; - - timer@640 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x640 0x10>; - interrupts = <1 13 0>; - }; - - timer@650 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x650 0x10>; - interrupts = <1 14 0>; - }; - - timer@660 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x660 0x10>; - interrupts = <1 15 0>; - }; - - timer@670 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x670 0x10>; - interrupts = <1 16 0>; - }; - - rtc@800 { // Real time clock - compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; - reg = <0x800 0x100>; - interrupts = <1 5 0 1 6 0>; - }; - - can@900 { - compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; - interrupts = <2 17 0>; - reg = <0x900 0x80>; - }; - - can@980 { - compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; - interrupts = <2 18 0>; - reg = <0x980 0x80>; - }; - - gpio_simple: gpio@b00 { - compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; - reg = <0xb00 0x40>; - interrupts = <1 7 0>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio_wkup: gpio@c00 { - compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; - reg = <0xc00 0x40>; - interrupts = <1 8 0 0 3 0>; - gpio-controller; - #gpio-cells = <2>; + psc@2000 { // PSC1 + compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; + cell-index = <0>; }; - spi@f00 { - compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; - reg = <0xf00 0x20>; - interrupts = <2 13 0 2 14 0>; + psc@2200 { // PSC2 + status = "disabled"; }; - usb@1000 { - compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; - reg = <0x1000 0xff>; - interrupts = <2 6 0>; + psc@2400 { // PSC3 + status = "disabled"; }; - dma-controller@1200 { - compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; - reg = <0x1200 0x80>; - interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 - 3 4 0 3 5 0 3 6 0 3 7 0 - 3 8 0 3 9 0 3 10 0 3 11 0 - 3 12 0 3 13 0 3 14 0 3 15 0>; + psc@2600 { // PSC4 + status = "disabled"; }; - xlb@1f00 { - compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; - reg = <0x1f00 0x100>; + psc@2800 { // PSC5 + status = "disabled"; }; - serial@2000 { // PSC1 - compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - cell-index = <0>; - reg = <0x2000 0x100>; - interrupts = <2 1 0>; + psc@2c00 { // PSC6 + status = "disabled"; }; // PSC2 in ac97 mode example //ac97@2200 { // PSC2 // compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; // cell-index = <1>; - // reg = <0x2200 0x100>; - // interrupts = <2 2 0>; //}; // PSC3 in CODEC mode example //i2s@2400 { // PSC3 // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible // cell-index = <2>; - // reg = <0x2400 0x100>; - // interrupts = <2 3 0>; - //}; - - // PSC4 in uart mode example - //serial@2600 { // PSC4 - // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - // cell-index = <3>; - // reg = <0x2600 0x100>; - // interrupts = <2 11 0>; - //}; - - // PSC5 in uart mode example - //serial@2800 { // PSC5 - // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - // cell-index = <4>; - // reg = <0x2800 0x100>; - // interrupts = <2 12 0>; //}; // PSC6 in spi mode example //spi@2c00 { // PSC6 // compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; // cell-index = <5>; - // reg = <0x2c00 0x100>; - // interrupts = <2 4 0>; //}; ethernet@3000 { - compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; - reg = <0x3000 0x400>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <2 5 0>; phy-handle = <&phy0>; }; mdio@3000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; - reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts - interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. - phy0: ethernet-phy@0 { reg = <0>; }; }; - ata@3a00 { - compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; - reg = <0x3a00 0x100>; - interrupts = <2 7 0>; - }; - - i2c@3d00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; - reg = <0x3d00 0x40>; - interrupts = <2 15 0>; - }; - i2c@3d40 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; - reg = <0x3d40 0x40>; - interrupts = <2 16 0>; - eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; @@ -273,12 +92,6 @@ }; pci@f0000d00 { - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; - reg = <0xf0000d00 0x100>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 0xc000 0 0 2 &mpc5200_pic 1 1 3 @@ -298,11 +111,6 @@ }; localbus { - compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0xfe000000 0x02000000>; flash@0,0 { diff --git a/arch/powerpc/boot/dts/media5200.dts b/arch/powerpc/boot/dts/media5200.dts index 0c3902bc5b6..48d72f38e5e 100644 --- a/arch/powerpc/boot/dts/media5200.dts +++ b/arch/powerpc/boot/dts/media5200.dts @@ -11,14 +11,11 @@ * option) any later version. */ -/dts-v1/; +/include/ "mpc5200b.dtsi" / { model = "fsl,media5200"; compatible = "fsl,media5200"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&mpc5200_pic>; aliases { console = &console; @@ -30,16 +27,7 @@ }; cpus { - #address-cells = <1>; - #size-cells = <0>; - PowerPC,5200@0 { - device_type = "cpu"; - reg = <0>; - d-cache-line-size = <32>; - i-cache-line-size = <32>; - d-cache-size = <0x4000>; // L1, 16K - i-cache-size = <0x4000>; // L1, 16K timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot bus-frequency = <132000000>; // 132 MHz clock-frequency = <396000000>; // 396 MHz @@ -47,205 +35,57 @@ }; memory { - device_type = "memory"; reg = <0x00000000 0x08000000>; // 128MB RAM }; - soc@f0000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc5200b-immr"; - ranges = <0 0xf0000000 0x0000c000>; - reg = <0xf0000000 0x00000100>; + soc5200@f0000000 { bus-frequency = <132000000>;// 132 MHz - system-frequency = <0>; // from bootloader - - cdm@200 { - compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; - reg = <0x200 0x38>; - }; - - mpc5200_pic: interrupt-controller@500 { - // 5200 interrupts are encoded into two levels; - interrupt-controller; - #interrupt-cells = <3>; - compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; - reg = <0x500 0x80>; - }; timer@600 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x600 0x10>; - interrupts = <1 9 0>; fsl,has-wdt; }; - timer@610 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x610 0x10>; - interrupts = <1 10 0>; - }; - - timer@620 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x620 0x10>; - interrupts = <1 11 0>; - }; - - timer@630 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x630 0x10>; - interrupts = <1 12 0>; - }; - - timer@640 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x640 0x10>; - interrupts = <1 13 0>; - }; - - timer@650 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x650 0x10>; - interrupts = <1 14 0>; - }; - - timer@660 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x660 0x10>; - interrupts = <1 15 0>; - }; - - timer@670 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x670 0x10>; - interrupts = <1 16 0>; - }; - - rtc@800 { // Real time clock - compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; - reg = <0x800 0x100>; - interrupts = <1 5 0 1 6 0>; - }; - - can@900 { - compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; - interrupts = <2 17 0>; - reg = <0x900 0x80>; + psc@2000 { // PSC1 + status = "disabled"; }; - can@980 { - compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; - interrupts = <2 18 0>; - reg = <0x980 0x80>; + psc@2200 { // PSC2 + status = "disabled"; }; - gpio_simple: gpio@b00 { - compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; - reg = <0xb00 0x40>; - interrupts = <1 7 0>; - gpio-controller; - #gpio-cells = <2>; + psc@2400 { // PSC3 + status = "disabled"; }; - gpio_wkup: gpio@c00 { - compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; - reg = <0xc00 0x40>; - interrupts = <1 8 0 0 3 0>; - gpio-controller; - #gpio-cells = <2>; + psc@2600 { // PSC4 + status = "disabled"; }; - spi@f00 { - compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; - reg = <0xf00 0x20>; - interrupts = <2 13 0 2 14 0>; - }; - - usb@1000 { - compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; - reg = <0x1000 0x100>; - interrupts = <2 6 0>; - }; - - dma-controller@1200 { - compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; - reg = <0x1200 0x80>; - interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 - 3 4 0 3 5 0 3 6 0 3 7 0 - 3 8 0 3 9 0 3 10 0 3 11 0 - 3 12 0 3 13 0 3 14 0 3 15 0>; - }; - - xlb@1f00 { - compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; - reg = <0x1f00 0x100>; + psc@2800 { // PSC5 + status = "disabled"; }; // PSC6 in uart mode - console: serial@2c00 { // PSC6 + console: psc@2c00 { // PSC6 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - cell-index = <5>; - port-number = <0>; // Logical port assignment - reg = <0x2c00 0x100>; - interrupts = <2 4 0>; }; - eth0: ethernet@3000 { - compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; - reg = <0x3000 0x400>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <2 5 0>; + ethernet@3000 { phy-handle = <&phy0>; }; mdio@3000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; - reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts - interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. - phy0: ethernet-phy@0 { reg = <0>; }; }; - ata@3a00 { - compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; - reg = <0x3a00 0x100>; - interrupts = <2 7 0>; - }; - - i2c@3d00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; - reg = <0x3d00 0x40>; - interrupts = <2 15 0>; - }; - - i2c@3d40 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; - reg = <0x3d40 0x40>; - interrupts = <2 16 0>; - }; - - sram@8000 { - compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; - reg = <0x8000 0x4000>; + usb@1000 { + reg = <0x1000 0x100>; }; }; pci@f0000d00 { - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; - reg = <0xf0000d00 0x100>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot 0xc000 0 0 2 &media5200_fpga 0 3 @@ -262,37 +102,29 @@ 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP >; - clock-frequency = <0>; // From boot loader - interrupts = <2 8 0 2 9 0 2 10 0>; - interrupt-parent = <&mpc5200_pic>; - bus-range = <0 0>; ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; + interrupt-parent = <&mpc5200_pic>; }; localbus { - compatible = "fsl,mpc5200b-lpb","simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = < 0 0 0xfc000000 0x02000000 1 0 0xfe000000 0x02000000 2 0 0xf0010000 0x00010000 3 0 0xf0020000 0x00010000 >; - flash@0,0 { compatible = "amd,am29lv28ml", "cfi-flash"; - reg = <0 0x0 0x2000000>; // 32 MB - bank-width = <4>; // Width in bytes of the flash bank - device-width = <2>; // Two devices on each bank + reg = <0 0x0 0x2000000>; // 32 MB + bank-width = <4>; // Width in bytes of the flash bank + device-width = <2>; // Two devices on each bank }; flash@1,0 { compatible = "amd,am29lv28ml", "cfi-flash"; - reg = <1 0 0x2000000>; // 32 MB - bank-width = <4>; // Width in bytes of the flash bank - device-width = <2>; // Two devices on each bank + reg = <1 0 0x2000000>; // 32 MB + bank-width = <4>; // Width in bytes of the flash bank + device-width = <2>; // Two devices on each bank }; media5200_fpga: fpga@2,0 { diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts index 6ca4fc144a3..0b78e89ac69 100644 --- a/arch/powerpc/boot/dts/motionpro.dts +++ b/arch/powerpc/boot/dts/motionpro.dts @@ -10,219 +10,73 @@ * option) any later version. */ -/dts-v1/; +/include/ "mpc5200b.dtsi" / { model = "promess,motionpro"; compatible = "promess,motionpro"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&mpc5200_pic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - PowerPC,5200@0 { - device_type = "cpu"; - reg = <0>; - d-cache-line-size = <32>; - i-cache-line-size = <32>; - d-cache-size = <0x4000>; // L1, 16K - i-cache-size = <0x4000>; // L1, 16K - timebase-frequency = <0>; // from bootloader - bus-frequency = <0>; // from bootloader - clock-frequency = <0>; // from bootloader - }; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x04000000>; // 64MB - }; soc5200@f0000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc5200b-immr"; - ranges = <0 0xf0000000 0x0000c000>; - reg = <0xf0000000 0x00000100>; - bus-frequency = <0>; // from bootloader - system-frequency = <0>; // from bootloader - - cdm@200 { - compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; - reg = <0x200 0x38>; - }; - - mpc5200_pic: interrupt-controller@500 { - // 5200 interrupts are encoded into two levels; - interrupt-controller; - #interrupt-cells = <3>; - compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; - reg = <0x500 0x80>; - }; - timer@600 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x600 0x10>; - interrupts = <1 9 0>; fsl,has-wdt; }; - timer@610 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x610 0x10>; - interrupts = <1 10 0>; - }; - - timer@620 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x620 0x10>; - interrupts = <1 11 0>; - }; - - timer@630 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x630 0x10>; - interrupts = <1 12 0>; - }; - - timer@640 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x640 0x10>; - interrupts = <1 13 0>; - }; - - timer@650 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x650 0x10>; - interrupts = <1 14 0>; - }; - - motionpro-led@660 { // Motion-PRO status LED + timer@660 { // Motion-PRO status LED compatible = "promess,motionpro-led"; label = "motionpro-statusled"; - reg = <0x660 0x10>; - interrupts = <1 15 0>; blink-delay = <100>; // 100 msec }; - motionpro-led@670 { // Motion-PRO ready LED + timer@670 { // Motion-PRO ready LED compatible = "promess,motionpro-led"; label = "motionpro-readyled"; - reg = <0x670 0x10>; - interrupts = <1 16 0>; - }; - - rtc@800 { // Real time clock - compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; - reg = <0x800 0x100>; - interrupts = <1 5 0 1 6 0>; - }; - - can@980 { - compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; - interrupts = <2 18 0>; - reg = <0x980 0x80>; }; - gpio_simple: gpio@b00 { - compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; - reg = <0xb00 0x40>; - interrupts = <1 7 0>; - gpio-controller; - #gpio-cells = <2>; + can@900 { + status = "disabled"; }; - gpio_wkup: gpio@c00 { - compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; - reg = <0xc00 0x40>; - interrupts = <1 8 0 0 3 0>; - gpio-controller; - #gpio-cells = <2>; - }; - - spi@f00 { - compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; - reg = <0xf00 0x20>; - interrupts = <2 13 0 2 14 0>; + psc@2000 { // PSC1 + compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; }; - usb@1000 { - compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; - reg = <0x1000 0xff>; - interrupts = <2 6 0>; + // PSC2 in spi master mode + psc@2200 { // PSC2 + compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; + cell-index = <1>; }; - dma-controller@1200 { - compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; - reg = <0x1200 0x80>; - interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 - 3 4 0 3 5 0 3 6 0 3 7 0 - 3 8 0 3 9 0 3 10 0 3 11 0 - 3 12 0 3 13 0 3 14 0 3 15 0>; + psc@2400 { // PSC3 + status = "disabled"; }; - xlb@1f00 { - compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; - reg = <0x1f00 0x100>; + psc@2600 { // PSC4 + status = "disabled"; }; - serial@2000 { // PSC1 + psc@2800 { // PSC5 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - reg = <0x2000 0x100>; - interrupts = <2 1 0>; - }; - - // PSC2 in spi master mode - spi@2200 { // PSC2 - compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; - cell-index = <1>; - reg = <0x2200 0x100>; - interrupts = <2 2 0>; }; - // PSC5 in uart mode - serial@2800 { // PSC5 - compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - reg = <0x2800 0x100>; - interrupts = <2 12 0>; + psc@2c00 { // PSC6 + status = "disabled"; }; ethernet@3000 { - compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; - reg = <0x3000 0x400>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <2 5 0>; phy-handle = <&phy0>; }; mdio@3000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; - reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts - interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. - phy0: ethernet-phy@2 { reg = <2>; }; }; - ata@3a00 { - compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; - reg = <0x3a00 0x100>; - interrupts = <2 7 0>; + i2c@3d00 { + status = "disabled"; }; i2c@3d40 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; - reg = <0x3d40 0x40>; - interrupts = <2 16 0>; - rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; @@ -235,10 +89,11 @@ }; }; + pci@f0000d00 { + status = "disabled"; + }; + localbus { - compatible = "fsl,mpc5200b-lpb","simple-bus"; - #address-cells = <2>; - #size-cells = <1>; ranges = <0 0 0xff000000 0x01000000 1 0 0x50000000 0x00010000 2 0 0x50010000 0x00010000 @@ -280,5 +135,6 @@ #size-cells = <1>; #address-cells = <1>; }; + }; }; diff --git a/arch/powerpc/boot/dts/mpc5200b.dtsi b/arch/powerpc/boot/dts/mpc5200b.dtsi new file mode 100644 index 00000000000..bc27548e895 --- /dev/null +++ b/arch/powerpc/boot/dts/mpc5200b.dtsi @@ -0,0 +1,275 @@ +/* + * base MPC5200b Device Tree Source + * + * Copyright (C) 2010 SecretLab + * Grant Likely <grant@secretlab.ca> + * John Bonesio <bones@secretlab.ca> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + model = "fsl,mpc5200b"; + compatible = "fsl,mpc5200b"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&mpc5200_pic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + powerpc: PowerPC,5200@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <0x4000>; // L1, 16K + i-cache-size = <0x4000>; // L1, 16K + timebase-frequency = <0>; // from bootloader + bus-frequency = <0>; // from bootloader + clock-frequency = <0>; // from bootloader + }; + }; + + memory: memory { + device_type = "memory"; + reg = <0x00000000 0x04000000>; // 64MB + }; + + soc: soc5200@f0000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc5200b-immr"; + ranges = <0 0xf0000000 0x0000c000>; + reg = <0xf0000000 0x00000100>; + bus-frequency = <0>; // from bootloader + system-frequency = <0>; // from bootloader + + cdm@200 { + compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; + reg = <0x200 0x38>; + }; + + mpc5200_pic: interrupt-controller@500 { + // 5200 interrupts are encoded into two levels; + interrupt-controller; + #interrupt-cells = <3>; + compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; + reg = <0x500 0x80>; + }; + + timer@600 { // General Purpose Timer + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; + reg = <0x600 0x10>; + interrupts = <1 9 0>; + }; + + timer@610 { // General Purpose Timer + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; + reg = <0x610 0x10>; + interrupts = <1 10 0>; + }; + + timer@620 { // General Purpose Timer + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; + reg = <0x620 0x10>; + interrupts = <1 11 0>; + }; + + timer@630 { // General Purpose Timer + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; + reg = <0x630 0x10>; + interrupts = <1 12 0>; + }; + + timer@640 { // General Purpose Timer + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; + reg = <0x640 0x10>; + interrupts = <1 13 0>; + }; + + timer@650 { // General Purpose Timer + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; + reg = <0x650 0x10>; + interrupts = <1 14 0>; + }; + + timer@660 { // General Purpose Timer + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; + reg = <0x660 0x10>; + interrupts = <1 15 0>; + }; + + timer@670 { // General Purpose Timer + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; + reg = <0x670 0x10>; + interrupts = <1 16 0>; + }; + + rtc@800 { // Real time clock + compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; + reg = <0x800 0x100>; + interrupts = <1 5 0 1 6 0>; + }; + + can@900 { + compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; + interrupts = <2 17 0>; + reg = <0x900 0x80>; + }; + + can@980 { + compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; + interrupts = <2 18 0>; + reg = <0x980 0x80>; + }; + + gpio_simple: gpio@b00 { + compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; + reg = <0xb00 0x40>; + interrupts = <1 7 0>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio_wkup: gpio@c00 { + compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; + reg = <0xc00 0x40>; + interrupts = <1 8 0 0 3 0>; + gpio-controller; + #gpio-cells = <2>; + }; + + spi@f00 { + compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; + reg = <0xf00 0x20>; + interrupts = <2 13 0 2 14 0>; + }; + + usb: usb@1000 { + compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; + reg = <0x1000 0xff>; + interrupts = <2 6 0>; + }; + + dma-controller@1200 { + compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; + reg = <0x1200 0x80>; + interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 + 3 4 0 3 5 0 3 6 0 3 7 0 + 3 8 0 3 9 0 3 10 0 3 11 0 + 3 12 0 3 13 0 3 14 0 3 15 0>; + }; + + xlb@1f00 { + compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; + reg = <0x1f00 0x100>; + }; + + psc1: psc@2000 { // PSC1 + compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc"; + reg = <0x2000 0x100>; + interrupts = <2 1 0>; + }; + + psc2: psc@2200 { // PSC2 + compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc"; + reg = <0x2200 0x100>; + interrupts = <2 2 0>; + }; + + psc3: psc@2400 { // PSC3 + compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc"; + reg = <0x2400 0x100>; + interrupts = <2 3 0>; + }; + + psc4: psc@2600 { // PSC4 + compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc"; + reg = <0x2600 0x100>; + interrupts = <2 11 0>; + }; + + psc5: psc@2800 { // PSC5 + compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc"; + reg = <0x2800 0x100>; + interrupts = <2 12 0>; + }; + + psc6: psc@2c00 { // PSC6 + compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc"; + reg = <0x2c00 0x100>; + interrupts = <2 4 0>; + }; + + eth0: ethernet@3000 { + compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; + reg = <0x3000 0x400>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <2 5 0>; + }; + + mdio@3000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; + reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts + interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. + }; + + ata@3a00 { + compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; + reg = <0x3a00 0x100>; + interrupts = <2 7 0>; + }; + + i2c@3d00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; + reg = <0x3d00 0x40>; + interrupts = <2 15 0>; + }; + + i2c@3d40 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; + reg = <0x3d40 0x40>; + interrupts = <2 16 0>; + }; + + sram@8000 { + compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; + reg = <0x8000 0x4000>; + }; + }; + + pci: pci@f0000d00 { + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; + reg = <0xf0000d00 0x100>; + // interrupt-map-mask = need to add + // interrupt-map = need to add + clock-frequency = <0>; // From boot loader + interrupts = <2 8 0 2 9 0 2 10 0>; + bus-range = <0 0>; + // ranges = need to add + }; + + localbus: localbus { + compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0xfc000000 0x2000000>; + }; +}; diff --git a/arch/powerpc/boot/dts/mpc8308_p1m.dts b/arch/powerpc/boot/dts/mpc8308_p1m.dts index 05a76ccfd49..697b3f6b78b 100644 --- a/arch/powerpc/boot/dts/mpc8308_p1m.dts +++ b/arch/powerpc/boot/dts/mpc8308_p1m.dts @@ -297,6 +297,14 @@ interrupt-parent = < &ipic >; }; + dma@2c000 { + compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma"; + reg = <0x2c000 0x1800>; + interrupts = <3 0x8 + 94 0x8>; + interrupt-parent = < &ipic >; + }; + }; pci0: pcie@e0009000 { diff --git a/arch/powerpc/boot/dts/mpc8308rdb.dts b/arch/powerpc/boot/dts/mpc8308rdb.dts index a97eb2db5a1..d3db02f98dd 100644 --- a/arch/powerpc/boot/dts/mpc8308rdb.dts +++ b/arch/powerpc/boot/dts/mpc8308rdb.dts @@ -265,6 +265,14 @@ interrupt-parent = < &ipic >; }; + dma@2c000 { + compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma"; + reg = <0x2c000 0x1800>; + interrupts = <3 0x8 + 94 0x8>; + interrupt-parent = < &ipic >; + }; + }; pci0: pcie@e0009000 { diff --git a/arch/powerpc/boot/dts/mucmc52.dts b/arch/powerpc/boot/dts/mucmc52.dts index b72a7581d79..21d34720fcc 100644 --- a/arch/powerpc/boot/dts/mucmc52.dts +++ b/arch/powerpc/boot/dts/mucmc52.dts @@ -11,172 +11,109 @@ * option) any later version. */ -/dts-v1/; +/include/ "mpc5200b.dtsi" / { model = "manroland,mucmc52"; compatible = "manroland,mucmc52"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&mpc5200_pic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - PowerPC,5200@0 { - device_type = "cpu"; - reg = <0>; - d-cache-line-size = <32>; - i-cache-line-size = <32>; - d-cache-size = <0x4000>; // L1, 16K - i-cache-size = <0x4000>; // L1, 16K - timebase-frequency = <0>; // from bootloader - bus-frequency = <0>; // from bootloader - clock-frequency = <0>; // from bootloader - }; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x04000000>; // 64MB - }; soc5200@f0000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc5200b-immr"; - ranges = <0 0xf0000000 0x0000c000>; - reg = <0xf0000000 0x00000100>; - bus-frequency = <0>; // from bootloader - system-frequency = <0>; // from bootloader - - cdm@200 { - compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; - reg = <0x200 0x38>; - }; - - mpc5200_pic: interrupt-controller@500 { - // 5200 interrupts are encoded into two levels; - interrupt-controller; - #interrupt-cells = <3>; - compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; - reg = <0x500 0x80>; - }; - gpt0: timer@600 { // GPT 0 in GPIO mode - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x600 0x10>; - interrupts = <1 9 0>; gpio-controller; #gpio-cells = <2>; }; gpt1: timer@610 { // General Purpose Timer in GPIO mode - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x610 0x10>; - interrupts = <1 10 0>; gpio-controller; #gpio-cells = <2>; }; gpt2: timer@620 { // General Purpose Timer in GPIO mode - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x620 0x10>; - interrupts = <1 11 0>; gpio-controller; #gpio-cells = <2>; }; gpt3: timer@630 { // General Purpose Timer in GPIO mode - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x630 0x10>; - interrupts = <1 12 0>; gpio-controller; #gpio-cells = <2>; }; - gpio_simple: gpio@b00 { - compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; - reg = <0xb00 0x40>; - interrupts = <1 7 0>; - gpio-controller; - #gpio-cells = <2>; + timer@640 { + status = "disabled"; }; - gpio_wkup: gpio@c00 { - compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; - reg = <0xc00 0x40>; - interrupts = <1 8 0 0 3 0>; - gpio-controller; - #gpio-cells = <2>; + timer@650 { + status = "disabled"; + }; + + timer@660 { + status = "disabled"; + }; + + timer@670 { + status = "disabled"; }; - dma-controller@1200 { - compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; - reg = <0x1200 0x80>; - interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 - 3 4 0 3 5 0 3 6 0 3 7 0 - 3 8 0 3 9 0 3 10 0 3 11 0 - 3 12 0 3 13 0 3 14 0 3 15 0>; + rtc@800 { + status = "disabled"; }; - xlb@1f00 { - compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; - reg = <0x1f00 0x100>; + can@900 { + status = "disabled"; }; - serial@2000 { /* PSC1 in UART mode */ + can@980 { + status = "disabled"; + }; + + spi@f00 { + status = "disabled"; + }; + + usb@1000 { + status = "disabled"; + }; + + psc@2000 { // PSC1 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - reg = <0x2000 0x100>; - interrupts = <2 1 0>; }; - serial@2200 { /* PSC2 in UART mode */ + psc@2200 { // PSC2 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - reg = <0x2200 0x100>; - interrupts = <2 2 0>; }; - serial@2c00 { /* PSC6 in UART mode */ + psc@2400 { // PSC3 + status = "disabled"; + }; + + psc@2600 { // PSC4 + status = "disabled"; + }; + + psc@2800 { // PSC5 + status = "disabled"; + }; + + psc@2c00 { // PSC6 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - reg = <0x2c00 0x100>; - interrupts = <2 4 0>; }; ethernet@3000 { - compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; - reg = <0x3000 0x400>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <2 5 0>; phy-handle = <&phy0>; }; mdio@3000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; - reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts - interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. - phy0: ethernet-phy@0 { compatible = "intel,lxt971"; reg = <0>; }; }; - ata@3a00 { - compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; - reg = <0x3a00 0x100>; - interrupts = <2 7 0>; + i2c@3d00 { + status = "disabled"; }; i2c@3d40 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; - reg = <0x3d40 0x40>; - interrupts = <2 16 0>; hwmon@2c { compatible = "ad,adm9240"; reg = <0x2c>; @@ -186,20 +123,9 @@ reg = <0x51>; }; }; - - sram@8000 { - compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; - reg = <0x8000 0x4000>; - }; }; pci@f0000d00 { - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; - reg = <0xf0000d00 0x100>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = < /* IDSEL 0x10 */ @@ -208,20 +134,12 @@ 0x8000 0 0 3 &mpc5200_pic 0 2 3 0x8000 0 0 4 &mpc5200_pic 0 1 3 >; - clock-frequency = <0>; // From boot loader - interrupts = <2 8 0 2 9 0 2 10 0>; - bus-range = <0 0>; ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000 0x02000000 0 0x90000000 0x90000000 0 0x10000000 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>; }; localbus { - compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0xff800000 0x00800000 1 0 0x80000000 0x00800000 3 0 0x80000000 0x00800000>; diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts index 8a4ec30b21a..9e354997eb7 100644 --- a/arch/powerpc/boot/dts/pcm030.dts +++ b/arch/powerpc/boot/dts/pcm030.dts @@ -12,246 +12,92 @@ * option) any later version. */ -/dts-v1/; +/include/ "mpc5200b.dtsi" / { model = "phytec,pcm030"; compatible = "phytec,pcm030"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&mpc5200_pic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - PowerPC,5200@0 { - device_type = "cpu"; - reg = <0>; - d-cache-line-size = <32>; - i-cache-line-size = <32>; - d-cache-size = <0x4000>; // L1, 16K - i-cache-size = <0x4000>; // L1, 16K - timebase-frequency = <0>; // from bootloader - bus-frequency = <0>; // from bootloader - clock-frequency = <0>; // from bootloader - }; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x04000000>; // 64MB - }; soc5200@f0000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc5200b-immr"; - ranges = <0 0xf0000000 0x0000c000>; - bus-frequency = <0>; // from bootloader - system-frequency = <0>; // from bootloader - - cdm@200 { - compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; - reg = <0x200 0x38>; - }; - - mpc5200_pic: interrupt-controller@500 { - // 5200 interrupts are encoded into two levels; - interrupt-controller; - #interrupt-cells = <3>; - compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; - reg = <0x500 0x80>; - }; - - timer@600 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x600 0x10>; - interrupts = <1 9 0>; + timer@600 { // General Purpose Timer fsl,has-wdt; }; - timer@610 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x610 0x10>; - interrupts = <1 10 0>; - }; - gpt2: timer@620 { // General Purpose Timer in GPIO mode compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; - reg = <0x620 0x10>; - interrupts = <1 11 0>; gpio-controller; #gpio-cells = <2>; }; gpt3: timer@630 { // General Purpose Timer in GPIO mode compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; - reg = <0x630 0x10>; - interrupts = <1 12 0>; gpio-controller; #gpio-cells = <2>; }; gpt4: timer@640 { // General Purpose Timer in GPIO mode compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; - reg = <0x640 0x10>; - interrupts = <1 13 0>; gpio-controller; #gpio-cells = <2>; }; gpt5: timer@650 { // General Purpose Timer in GPIO mode compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; - reg = <0x650 0x10>; - interrupts = <1 14 0>; gpio-controller; #gpio-cells = <2>; }; gpt6: timer@660 { // General Purpose Timer in GPIO mode compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; - reg = <0x660 0x10>; - interrupts = <1 15 0>; gpio-controller; #gpio-cells = <2>; }; gpt7: timer@670 { // General Purpose Timer in GPIO mode compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; - reg = <0x670 0x10>; - interrupts = <1 16 0>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc@800 { // Real time clock - compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; - reg = <0x800 0x100>; - interrupts = <1 5 0 1 6 0>; - }; - - can@900 { - compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; - interrupts = <2 17 0>; - reg = <0x900 0x80>; - }; - - can@980 { - compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; - interrupts = <2 18 0>; - reg = <0x980 0x80>; - }; - - gpio_simple: gpio@b00 { - compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; - reg = <0xb00 0x40>; - interrupts = <1 7 0>; gpio-controller; #gpio-cells = <2>; }; - gpio_wkup: gpio@c00 { - compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; - reg = <0xc00 0x40>; - interrupts = <1 8 0 0 3 0>; - gpio-controller; - #gpio-cells = <2>; - }; - - spi@f00 { - compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; - reg = <0xf00 0x20>; - interrupts = <2 13 0 2 14 0>; - }; - - usb@1000 { - compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; - reg = <0x1000 0xff>; - interrupts = <2 6 0>; - }; - - dma-controller@1200 { - compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; - reg = <0x1200 0x80>; - interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 - 3 4 0 3 5 0 3 6 0 3 7 0 - 3 8 0 3 9 0 3 10 0 3 11 0 - 3 12 0 3 13 0 3 14 0 3 15 0>; - }; - - xlb@1f00 { - compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; - reg = <0x1f00 0x100>; - }; - - ac97@2000 { /* PSC1 in ac97 mode */ + psc@2000 { /* PSC1 in ac97 mode */ compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97"; cell-index = <0>; - reg = <0x2000 0x100>; - interrupts = <2 1 0>; }; /* PSC2 port is used by CAN1/2 */ + psc@2200 { + status = "disabled"; + }; - serial@2400 { /* PSC3 in UART mode */ + psc@2400 { /* PSC3 in UART mode */ compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - cell-index = <2>; - reg = <0x2400 0x100>; - interrupts = <2 3 0>; }; /* PSC4 is ??? */ + psc@2600 { + status = "disabled"; + }; /* PSC5 is ??? */ + psc@2800 { + status = "disabled"; + }; - serial@2c00 { /* PSC6 in UART mode */ + psc@2c00 { /* PSC6 in UART mode */ compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - cell-index = <5>; - reg = <0x2c00 0x100>; - interrupts = <2 4 0>; }; ethernet@3000 { - compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; - reg = <0x3000 0x400>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <2 5 0>; phy-handle = <&phy0>; }; mdio@3000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; - reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts - interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. - phy0: ethernet-phy@0 { reg = <0>; }; }; - ata@3a00 { - compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; - reg = <0x3a00 0x100>; - interrupts = <2 7 0>; - }; - - i2c@3d00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; - reg = <0x3d00 0x40>; - interrupts = <2 15 0>; - }; - i2c@3d40 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; - reg = <0x3d40 0x40>; - interrupts = <2 16 0>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; @@ -259,6 +105,7 @@ eeprom@52 { compatible = "catalyst,24c32"; reg = <0x52>; + pagesize = <32>; }; }; @@ -269,12 +116,6 @@ }; pci@f0000d00 { - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; - reg = <0xf0000d00 0x100>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 0xc000 0 0 2 &mpc5200_pic 1 1 3 @@ -285,11 +126,12 @@ 0xc800 0 0 2 &mpc5200_pic 1 2 3 0xc800 0 0 3 &mpc5200_pic 1 3 3 0xc800 0 0 4 &mpc5200_pic 0 0 3>; - clock-frequency = <0>; // From boot loader - interrupts = <2 8 0 2 9 0 2 10 0>; - bus-range = <0 0>; ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; }; + + localbus { + status = "disabled"; + }; }; diff --git a/arch/powerpc/boot/dts/pcm032.dts b/arch/powerpc/boot/dts/pcm032.dts index 85d857a5d46..1dd478bfff9 100644 --- a/arch/powerpc/boot/dts/pcm032.dts +++ b/arch/powerpc/boot/dts/pcm032.dts @@ -12,99 +12,37 @@ * option) any later version. */ -/dts-v1/; +/include/ "mpc5200b.dtsi" / { model = "phytec,pcm032"; compatible = "phytec,pcm032"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&mpc5200_pic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - PowerPC,5200@0 { - device_type = "cpu"; - reg = <0>; - d-cache-line-size = <32>; - i-cache-line-size = <32>; - d-cache-size = <0x4000>; // L1, 16K - i-cache-size = <0x4000>; // L1, 16K - timebase-frequency = <0>; // from bootloader - bus-frequency = <0>; // from bootloader - clock-frequency = <0>; // from bootloader - }; - }; memory { - device_type = "memory"; reg = <0x00000000 0x08000000>; // 128MB }; soc5200@f0000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc5200b-immr"; - ranges = <0 0xf0000000 0x0000c000>; - bus-frequency = <0>; // from bootloader - system-frequency = <0>; // from bootloader - - cdm@200 { - compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; - reg = <0x200 0x38>; - }; - - mpc5200_pic: interrupt-controller@500 { - // 5200 interrupts are encoded into two levels; - interrupt-controller; - #interrupt-cells = <3>; - compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; - reg = <0x500 0x80>; - }; - - timer@600 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x600 0x10>; - interrupts = <1 9 0>; + timer@600 { // General Purpose Timer fsl,has-wdt; }; - timer@610 { // General Purpose Timer - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x610 0x10>; - interrupts = <1 10 0>; - }; - gpt2: timer@620 { // General Purpose Timer in GPIO mode - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x620 0x10>; - interrupts = <1 11 0>; gpio-controller; #gpio-cells = <2>; }; gpt3: timer@630 { // General Purpose Timer in GPIO mode - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x630 0x10>; - interrupts = <1 12 0>; gpio-controller; #gpio-cells = <2>; }; gpt4: timer@640 { // General Purpose Timer in GPIO mode - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x640 0x10>; - interrupts = <1 13 0>; gpio-controller; #gpio-cells = <2>; }; gpt5: timer@650 { // General Purpose Timer in GPIO mode - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x650 0x10>; - interrupts = <1 14 0>; gpio-controller; #gpio-cells = <2>; }; @@ -118,163 +56,62 @@ }; gpt7: timer@670 { // General Purpose Timer in GPIO mode - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x670 0x10>; - interrupts = <1 16 0>; gpio-controller; #gpio-cells = <2>; }; - rtc@800 { // Real time clock - compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; - reg = <0x800 0x100>; - interrupts = <1 5 0 1 6 0>; - }; - - can@900 { - compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; - interrupts = <2 17 0>; - reg = <0x900 0x80>; - }; - - can@980 { - compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; - interrupts = <2 18 0>; - reg = <0x980 0x80>; - }; - - gpio_simple: gpio@b00 { - compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; - reg = <0xb00 0x40>; - interrupts = <1 7 0>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio_wkup: gpio@c00 { - compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; - reg = <0xc00 0x40>; - interrupts = <1 8 0 0 3 0>; - gpio-controller; - #gpio-cells = <2>; - }; - - spi@f00 { - compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; - reg = <0xf00 0x20>; - interrupts = <2 13 0 2 14 0>; - }; - - usb@1000 { - compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; - reg = <0x1000 0xff>; - interrupts = <2 6 0>; - }; - - dma-controller@1200 { - compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; - reg = <0x1200 0x80>; - interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 - 3 4 0 3 5 0 3 6 0 3 7 0 - 3 8 0 3 9 0 3 10 0 3 11 0 - 3 12 0 3 13 0 3 14 0 3 15 0>; - }; - - xlb@1f00 { - compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; - reg = <0x1f00 0x100>; - }; - - ac97@2000 { /* PSC1 is ac97 */ + psc@2000 { /* PSC1 is ac97 */ compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; cell-index = <0>; - reg = <0x2000 0x100>; - interrupts = <2 1 0>; }; /* PSC2 port is used by CAN1/2 */ + psc@2200 { + status = "disabled"; + }; - serial@2400 { /* PSC3 in UART mode */ + psc@2400 { /* PSC3 in UART mode */ compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - cell-index = <2>; - reg = <0x2400 0x100>; - interrupts = <2 3 0>; }; /* PSC4 is ??? */ + psc@2600 { + status = "disabled"; + }; /* PSC5 is ??? */ + psc@2800 { + status = "disabled"; + }; - serial@2c00 { /* PSC6 in UART mode */ + psc@2c00 { /* PSC6 in UART mode */ compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - cell-index = <5>; - reg = <0x2c00 0x100>; - interrupts = <2 4 0>; }; ethernet@3000 { - compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; - reg = <0x3000 0x400>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <2 5 0>; phy-handle = <&phy0>; }; mdio@3000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; - reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts - interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. - phy0: ethernet-phy@0 { reg = <0>; }; }; - ata@3a00 { - compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; - reg = <0x3a00 0x100>; - interrupts = <2 7 0>; - }; - - i2c@3d00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; - reg = <0x3d00 0x40>; - interrupts = <2 15 0>; - }; - i2c@3d40 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; - reg = <0x3d40 0x40>; - interrupts = <2 16 0>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; eeprom@52 { - compatible = "at24,24c32"; + compatible = "catalyst,24c32"; reg = <0x52>; + pagesize = <32>; }; }; - - sram@8000 { - compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; - reg = <0x8000 0x4000>; - }; }; pci@f0000d00 { - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; - reg = <0xf0000d00 0x100>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 0xc000 0 0 2 &mpc5200_pic 1 1 3 @@ -285,20 +122,12 @@ 0xc800 0 0 2 &mpc5200_pic 1 2 3 0xc800 0 0 3 &mpc5200_pic 1 3 3 0xc800 0 0 4 &mpc5200_pic 0 0 3>; - clock-frequency = <0>; // From boot loader - interrupts = <2 8 0 2 9 0 2 10 0>; - bus-range = <0 0>; ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; }; localbus { - compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0xfe000000 0x02000000 1 0 0xfc000000 0x02000000 2 0 0xfbe00000 0x00200000 @@ -351,40 +180,39 @@ bank-width = <2>; }; - /* + /* * example snippets for FPGA * * fpga@3,0 { - * compatible = "fpga_driver"; - * reg = <3 0 0x02000000>; - * bank-width = <4>; + * compatible = "fpga_driver"; + * reg = <3 0 0x02000000>; + * bank-width = <4>; * }; * * fpga@4,0 { - * compatible = "fpga_driver"; - * reg = <4 0 0x02000000>; - * bank-width = <4>; + * compatible = "fpga_driver"; + * reg = <4 0 0x02000000>; + * bank-width = <4>; * }; - */ + */ - /* + /* * example snippets for free chipselects - * + * * device@5,0 { - * compatible = "custom_driver"; - * reg = <5 0 0x02000000>; + * compatible = "custom_driver"; + * reg = <5 0 0x02000000>; * }; - * + * * device@6,0 { - * compatible = "custom_driver"; - * reg = <6 0 0x02000000>; + * compatible = "custom_driver"; + * reg = <6 0 0x02000000>; * }; - * + * * device@7,0 { - * compatible = "custom_driver"; - * reg = <7 0 0x02000000>; + * compatible = "custom_driver"; + * reg = <7 0 0x02000000>; * }; - */ + */ }; }; - diff --git a/arch/powerpc/boot/dts/uc101.dts b/arch/powerpc/boot/dts/uc101.dts index 019264c6290..ba83d5488ec 100644 --- a/arch/powerpc/boot/dts/uc101.dts +++ b/arch/powerpc/boot/dts/uc101.dts @@ -11,79 +11,24 @@ * option) any later version. */ -/dts-v1/; +/include/ "mpc5200b.dtsi" / { model = "manroland,uc101"; compatible = "manroland,uc101"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&mpc5200_pic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - PowerPC,5200@0 { - device_type = "cpu"; - reg = <0>; - d-cache-line-size = <32>; - i-cache-line-size = <32>; - d-cache-size = <0x4000>; // L1, 16K - i-cache-size = <0x4000>; // L1, 16K - timebase-frequency = <0>; // from bootloader - bus-frequency = <0>; // from bootloader - clock-frequency = <0>; // from bootloader - }; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x04000000>; // 64MB - }; soc5200@f0000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc5200b-immr"; - ranges = <0 0xf0000000 0x0000c000>; - reg = <0xf0000000 0x00000100>; - bus-frequency = <0>; // from bootloader - system-frequency = <0>; // from bootloader - - cdm@200 { - compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; - reg = <0x200 0x38>; - }; - - mpc5200_pic: interrupt-controller@500 { - // 5200 interrupts are encoded into two levels; - interrupt-controller; - #interrupt-cells = <3>; - compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; - reg = <0x500 0x80>; - }; - gpt0: timer@600 { // General Purpose Timer in GPIO mode - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x600 0x10>; - interrupts = <1 9 0>; gpio-controller; #gpio-cells = <2>; }; gpt1: timer@610 { // General Purpose Timer in GPIO mode - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x610 0x10>; - interrupts = <1 10 0>; gpio-controller; #gpio-cells = <2>; }; gpt2: timer@620 { // General Purpose Timer in GPIO mode - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x620 0x10>; - interrupts = <1 11 0>; gpio-controller; #gpio-cells = <2>; }; @@ -97,118 +42,85 @@ }; gpt4: timer@640 { // General Purpose Timer in GPIO mode - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x640 0x10>; - interrupts = <1 13 0>; gpio-controller; #gpio-cells = <2>; }; gpt5: timer@650 { // General Purpose Timer in GPIO mode - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x650 0x10>; - interrupts = <1 14 0>; gpio-controller; #gpio-cells = <2>; }; gpt6: timer@660 { // General Purpose Timer in GPIO mode - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x660 0x10>; - interrupts = <1 15 0>; gpio-controller; #gpio-cells = <2>; }; gpt7: timer@670 { // General Purpose Timer in GPIO mode - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; - reg = <0x670 0x10>; - interrupts = <1 16 0>; gpio-controller; #gpio-cells = <2>; }; - gpio_simple: gpio@b00 { - compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; - reg = <0xb00 0x40>; - interrupts = <1 7 0>; - gpio-controller; - #gpio-cells = <2>; + rtc@800 { + status = "disabled"; }; - gpio_wkup: gpio@c00 { - compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; - reg = <0xc00 0x40>; - interrupts = <1 8 0 0 3 0>; - gpio-controller; - #gpio-cells = <2>; + can@900 { + status = "disabled"; + }; + + can@980 { + status = "disabled"; }; - dma-controller@1200 { - compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; - reg = <0x1200 0x80>; - interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 - 3 4 0 3 5 0 3 6 0 3 7 0 - 3 8 0 3 9 0 3 10 0 3 11 0 - 3 12 0 3 13 0 3 14 0 3 15 0>; + spi@f00 { + status = "disabled"; }; - xlb@1f00 { - compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; - reg = <0x1f00 0x100>; + usb@1000 { + status = "disabled"; }; - serial@2000 { /* PSC1 in UART mode */ + psc@2000 { // PSC1 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - reg = <0x2000 0x100>; - interrupts = <2 1 0>; }; - serial@2200 { /* PSC2 in UART mode */ + psc@2200 { // PSC2 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - reg = <0x2200 0x100>; - interrupts = <2 2 0>; }; - serial@2c00 { /* PSC6 in UART mode */ + psc@2400 { // PSC3 + status = "disabled"; + }; + + psc@2600 { // PSC4 + status = "disabled"; + }; + + psc@2800 { // PSC5 + status = "disabled"; + }; + + psc@2c00 { // PSC6 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; - reg = <0x2c00 0x100>; - interrupts = <2 4 0>; }; ethernet@3000 { - compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; - reg = <0x3000 0x400>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <2 5 0>; phy-handle = <&phy0>; }; mdio@3000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; - reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts - interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. - phy0: ethernet-phy@0 { compatible = "intel,lxt971"; reg = <0>; }; }; - ata@3a00 { - compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; - reg = <0x3a00 0x100>; - interrupts = <2 7 0>; + i2c@3d00 { + status = "disabled"; }; i2c@3d40 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; - reg = <0x3d40 0x40>; - interrupts = <2 16 0>; fsl,preserve-clocking; clock-frequency = <400000>; @@ -221,19 +133,13 @@ reg = <0x51>; }; }; + }; - sram@8000 { - compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; - reg = <0x8000 0x4000>; - }; + pci@f0000d00 { + status = "disabled"; }; localbus { - compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0xff800000 0x00800000 1 0 0x80000000 0x00800000 3 0 0x80000000 0x00800000>; diff --git a/arch/powerpc/configs/40x/kilauea_defconfig b/arch/powerpc/configs/40x/kilauea_defconfig index 4e19ee7ce4e..34b8c1a1e75 100644 --- a/arch/powerpc/configs/40x/kilauea_defconfig +++ b/arch/powerpc/configs/40x/kilauea_defconfig @@ -12,6 +12,8 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_KILAUEA=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y # CONFIG_WALNUT is not set CONFIG_SPARSE_IRQ=y CONFIG_PCI=y @@ -42,6 +44,9 @@ CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_NDFC=y CONFIG_PROC_DEVICETREE=y +CONFIG_PM=y +CONFIG_SUSPEND=y +CONFIG_PPC4xx_CPM=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=35000 # CONFIG_MISC_DEVICES is not set diff --git a/arch/powerpc/configs/44x/canyonlands_defconfig b/arch/powerpc/configs/44x/canyonlands_defconfig index 45c64d818b2..17e4dd98eed 100644 --- a/arch/powerpc/configs/44x/canyonlands_defconfig +++ b/arch/powerpc/configs/44x/canyonlands_defconfig @@ -42,6 +42,9 @@ CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_NDFC=y CONFIG_PROC_DEVICETREE=y +CONFIG_PM=y +CONFIG_SUSPEND=y +CONFIG_PPC4xx_CPM=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=35000 # CONFIG_MISC_DEVICES is not set diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h index 30964ae2d09..8a7e9314c68 100644 --- a/arch/powerpc/include/asm/bitops.h +++ b/arch/powerpc/include/asm/bitops.h @@ -267,7 +267,16 @@ static __inline__ int fls64(__u64 x) #include <asm-generic/bitops/fls64.h> #endif /* __powerpc64__ */ +#ifdef CONFIG_PPC64 +unsigned int __arch_hweight8(unsigned int w); +unsigned int __arch_hweight16(unsigned int w); +unsigned int __arch_hweight32(unsigned int w); +unsigned long __arch_hweight64(__u64 w); +#include <asm-generic/bitops/const_hweight.h> +#else #include <asm-generic/bitops/hweight.h> +#endif + #include <asm-generic/bitops/find.h> /* Little-endian versions */ diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index f3a1fdd9cf0..f0a211d9692 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -199,6 +199,8 @@ extern const char *powerpc_base_platform; #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0080000000000000) #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0100000000000000) #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0200000000000000) +#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0400000000000000) +#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0800000000000000) #ifndef __ASSEMBLY__ @@ -403,21 +405,22 @@ extern const char *powerpc_base_platform; CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ CPU_FTR_MMCRA | CPU_FTR_SMT | \ CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ - CPU_FTR_PURR | CPU_FTR_STCX_CHECKS_ADDRESS) + CPU_FTR_PURR | CPU_FTR_STCX_CHECKS_ADDRESS | \ + CPU_FTR_POPCNTB) #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ CPU_FTR_MMCRA | CPU_FTR_SMT | \ CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ - CPU_FTR_STCX_CHECKS_ADDRESS) + CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB) #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ CPU_FTR_MMCRA | CPU_FTR_SMT | \ CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ - CPU_FTR_STCX_CHECKS_ADDRESS) + CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD) #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ diff --git a/arch/powerpc/include/asm/cputhreads.h b/arch/powerpc/include/asm/cputhreads.h index a8e18447c62..f71bb4c118b 100644 --- a/arch/powerpc/include/asm/cputhreads.h +++ b/arch/powerpc/include/asm/cputhreads.h @@ -61,22 +61,25 @@ static inline cpumask_t cpu_online_cores_map(void) return cpu_thread_mask_to_cores(cpu_online_map); } -static inline int cpu_thread_to_core(int cpu) -{ - return cpu >> threads_shift; -} +#ifdef CONFIG_SMP +int cpu_core_index_of_thread(int cpu); +int cpu_first_thread_of_core(int core); +#else +static inline int cpu_core_index_of_thread(int cpu) { return cpu; } +static inline int cpu_first_thread_of_core(int core) { return core; } +#endif static inline int cpu_thread_in_core(int cpu) { return cpu & (threads_per_core - 1); } -static inline int cpu_first_thread_in_core(int cpu) +static inline int cpu_first_thread_sibling(int cpu) { return cpu & ~(threads_per_core - 1); } -static inline int cpu_last_thread_in_core(int cpu) +static inline int cpu_last_thread_sibling(int cpu) { return cpu | (threads_per_core - 1); } diff --git a/arch/powerpc/include/asm/device.h b/arch/powerpc/include/asm/device.h index a3954e4fcbe..16d25c0974b 100644 --- a/arch/powerpc/include/asm/device.h +++ b/arch/powerpc/include/asm/device.h @@ -9,6 +9,12 @@ struct dma_map_ops; struct device_node; +/* + * Arch extensions to struct device. + * + * When adding fields, consider macio_add_one_device in + * drivers/macintosh/macio_asic.c + */ struct dev_archdata { /* DMA operations on that device */ struct dma_map_ops *dma_ops; diff --git a/arch/powerpc/include/asm/firmware.h b/arch/powerpc/include/asm/firmware.h index 20778a405d7..4ef662e4a31 100644 --- a/arch/powerpc/include/asm/firmware.h +++ b/arch/powerpc/include/asm/firmware.h @@ -46,6 +46,7 @@ #define FW_FEATURE_PS3_LV1 ASM_CONST(0x0000000000800000) #define FW_FEATURE_BEAT ASM_CONST(0x0000000001000000) #define FW_FEATURE_CMO ASM_CONST(0x0000000002000000) +#define FW_FEATURE_VPHN ASM_CONST(0x0000000004000000) #ifndef __ASSEMBLY__ @@ -59,7 +60,7 @@ enum { FW_FEATURE_VIO | FW_FEATURE_RDMA | FW_FEATURE_LLAN | FW_FEATURE_BULK_REMOVE | FW_FEATURE_XDABR | FW_FEATURE_MULTITCE | FW_FEATURE_SPLPAR | FW_FEATURE_LPAR | - FW_FEATURE_CMO, + FW_FEATURE_CMO | FW_FEATURE_VPHN, FW_FEATURE_PSERIES_ALWAYS = 0, FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR, FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR, diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h index de03ca58db5..ec089acfa56 100644 --- a/arch/powerpc/include/asm/hvcall.h +++ b/arch/powerpc/include/asm/hvcall.h @@ -232,7 +232,9 @@ #define H_GET_EM_PARMS 0x2B8 #define H_SET_MPP 0x2D0 #define H_GET_MPP 0x2D4 -#define MAX_HCALL_OPCODE H_GET_MPP +#define H_HOME_NODE_ASSOCIATIVITY 0x2EC +#define H_BEST_ENERGY 0x2F4 +#define MAX_HCALL_OPCODE H_BEST_ENERGY #ifndef __ASSEMBLY__ diff --git a/arch/powerpc/include/asm/lppaca.h b/arch/powerpc/include/asm/lppaca.h index 7f5e0fefebb..380d48bacd1 100644 --- a/arch/powerpc/include/asm/lppaca.h +++ b/arch/powerpc/include/asm/lppaca.h @@ -62,7 +62,10 @@ struct lppaca { volatile u32 dyn_pir; // Dynamic ProcIdReg value x20-x23 u32 dsei_data; // DSEI data x24-x27 u64 sprg3; // SPRG3 value x28-x2F - u8 reserved3[80]; // Reserved x30-x7F + u8 reserved3[40]; // Reserved x30-x57 + volatile u8 vphn_assoc_counts[8]; // Virtual processor home node + // associativity change counters x58-x5F + u8 reserved4[32]; // Reserved x60-x7F //============================================================================= // CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h index d045b014553..8433d36619a 100644 --- a/arch/powerpc/include/asm/machdep.h +++ b/arch/powerpc/include/asm/machdep.h @@ -27,9 +27,7 @@ struct iommu_table; struct rtc_time; struct file; struct pci_controller; -#ifdef CONFIG_KEXEC struct kimage; -#endif #ifdef CONFIG_SMP struct smp_ops_t { @@ -72,7 +70,7 @@ struct machdep_calls { int psize, int ssize); void (*flush_hash_range)(unsigned long number, int local); - /* special for kexec, to be called in real mode, linar mapping is + /* special for kexec, to be called in real mode, linear mapping is * destroyed as well */ void (*hpte_clear_all)(void); @@ -324,8 +322,6 @@ extern sys_ctrler_t sys_ctrler; #endif /* CONFIG_PPC_PMAC */ -extern void setup_pci_ptrs(void); - #ifdef CONFIG_SMP /* Poor default implementations */ extern void __devinit smp_generic_give_timebase(void); diff --git a/arch/powerpc/include/asm/mmzone.h b/arch/powerpc/include/asm/mmzone.h index aac87cbceb5..fd3fd58bad8 100644 --- a/arch/powerpc/include/asm/mmzone.h +++ b/arch/powerpc/include/asm/mmzone.h @@ -33,6 +33,9 @@ extern int numa_cpu_lookup_table[]; extern cpumask_var_t node_to_cpumask_map[]; #ifdef CONFIG_MEMORY_HOTPLUG extern unsigned long max_pfn; +u64 memory_hotplug_max(void); +#else +#define memory_hotplug_max() memblock_end_of_DRAM() #endif /* @@ -42,6 +45,8 @@ extern unsigned long max_pfn; #define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn) #define node_end_pfn(nid) (NODE_DATA(nid)->node_end_pfn) +#else +#define memory_hotplug_max() memblock_end_of_DRAM() #endif /* CONFIG_NEED_MULTIPLE_NODES */ #endif /* __KERNEL__ */ diff --git a/arch/powerpc/include/asm/nvram.h b/arch/powerpc/include/asm/nvram.h index 850b72f2744..92efe67d1c5 100644 --- a/arch/powerpc/include/asm/nvram.h +++ b/arch/powerpc/include/asm/nvram.h @@ -10,31 +10,7 @@ #ifndef _ASM_POWERPC_NVRAM_H #define _ASM_POWERPC_NVRAM_H -#include <linux/errno.h> - -#define NVRW_CNT 0x20 -#define NVRAM_HEADER_LEN 16 /* sizeof(struct nvram_header) */ -#define NVRAM_BLOCK_LEN 16 -#define NVRAM_MAX_REQ (2080/NVRAM_BLOCK_LEN) -#define NVRAM_MIN_REQ (1056/NVRAM_BLOCK_LEN) - -#define NVRAM_AS0 0x74 -#define NVRAM_AS1 0x75 -#define NVRAM_DATA 0x77 - - -/* RTC Offsets */ - -#define MOTO_RTC_SECONDS 0x1FF9 -#define MOTO_RTC_MINUTES 0x1FFA -#define MOTO_RTC_HOURS 0x1FFB -#define MOTO_RTC_DAY_OF_WEEK 0x1FFC -#define MOTO_RTC_DAY_OF_MONTH 0x1FFD -#define MOTO_RTC_MONTH 0x1FFE -#define MOTO_RTC_YEAR 0x1FFF -#define MOTO_RTC_CONTROLA 0x1FF8 -#define MOTO_RTC_CONTROLB 0x1FF9 - +/* Signatures for nvram partitions */ #define NVRAM_SIG_SP 0x02 /* support processor */ #define NVRAM_SIG_OF 0x50 /* open firmware config */ #define NVRAM_SIG_FW 0x51 /* general firmware */ @@ -49,32 +25,19 @@ #define NVRAM_SIG_OS 0xa0 /* OS defined */ #define NVRAM_SIG_PANIC 0xa1 /* Apple OSX "panic" */ -/* If change this size, then change the size of NVNAME_LEN */ -struct nvram_header { - unsigned char signature; - unsigned char checksum; - unsigned short length; - char name[12]; -}; - #ifdef __KERNEL__ +#include <linux/errno.h> #include <linux/list.h> -struct nvram_partition { - struct list_head partition; - struct nvram_header header; - unsigned int index; -}; - - +#ifdef CONFIG_PPC_PSERIES extern int nvram_write_error_log(char * buff, int length, unsigned int err_type, unsigned int err_seq); extern int nvram_read_error_log(char * buff, int length, unsigned int * err_type, unsigned int *err_seq); extern int nvram_clear_error_log(void); - extern int pSeries_nvram_init(void); +#endif /* CONFIG_PPC_PSERIES */ #ifdef CONFIG_MMIO_NVRAM extern int mmio_nvram_init(void); @@ -85,6 +48,13 @@ static inline int mmio_nvram_init(void) } #endif +extern int __init nvram_scan_partitions(void); +extern loff_t nvram_create_partition(const char *name, int sig, + int req_size, int min_size); +extern int nvram_remove_partition(const char *name, int sig); +extern int nvram_get_partition_size(loff_t data_index); +extern loff_t nvram_find_partition(const char *name, int sig, int *out_size); + #endif /* __KERNEL__ */ /* PowerMac specific nvram stuffs */ diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 43adc8b819e..1255569387b 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -36,6 +36,8 @@ #define PPC_INST_NOP 0x60000000 #define PPC_INST_POPCNTB 0x7c0000f4 #define PPC_INST_POPCNTB_MASK 0xfc0007fe +#define PPC_INST_POPCNTD 0x7c0003f4 +#define PPC_INST_POPCNTW 0x7c0002f4 #define PPC_INST_RFCI 0x4c000066 #define PPC_INST_RFDI 0x4c00004e #define PPC_INST_RFMCI 0x4c00004c @@ -88,6 +90,12 @@ __PPC_RB(b) | __PPC_EH(eh)) #define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \ __PPC_RB(b)) +#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \ + __PPC_RA(a) | __PPC_RS(s)) +#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \ + __PPC_RA(a) | __PPC_RS(s)) +#define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \ + __PPC_RA(a) | __PPC_RS(s)) #define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI) #define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) #define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 4c14187ba02..de1967a1ff5 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -122,7 +122,6 @@ extern struct task_struct *last_task_used_spe; TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 ) #endif -#ifdef __KERNEL__ #ifdef __powerpc64__ #define STACK_TOP_USER64 TASK_SIZE_USER64 @@ -139,7 +138,6 @@ extern struct task_struct *last_task_used_spe; #define STACK_TOP_MAX STACK_TOP #endif /* __powerpc64__ */ -#endif /* __KERNEL__ */ typedef struct { unsigned long seg; diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h index ae26f2efd08..d7275758559 100644 --- a/arch/powerpc/include/asm/prom.h +++ b/arch/powerpc/include/asm/prom.h @@ -42,7 +42,7 @@ extern void pci_create_OF_bus_map(void); /* Translate a DMA address from device space to CPU space */ extern u64 of_translate_dma_address(struct device_node *dev, - const u32 *in_addr); + const __be32 *in_addr); #ifdef CONFIG_PCI extern unsigned long pci_address_to_pio(phys_addr_t address); @@ -63,9 +63,6 @@ struct device_node *of_get_cpu_node(int cpu, unsigned int *thread); /* cache lookup */ struct device_node *of_find_next_cache_node(struct device_node *np); -/* Get the MAC address */ -extern const void *of_get_mac_address(struct device_node *np); - #ifdef CONFIG_NUMA extern int of_node_to_nid(struct device_node *device); #else diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h index afe4aaa65c3..7ef0d90defc 100644 --- a/arch/powerpc/include/asm/topology.h +++ b/arch/powerpc/include/asm/topology.h @@ -106,9 +106,22 @@ static inline void sysfs_remove_device_from_node(struct sys_device *dev, int nid) { } - #endif /* CONFIG_NUMA */ +#if defined(CONFIG_NUMA) && defined(CONFIG_PPC_SPLPAR) +extern int start_topology_update(void); +extern int stop_topology_update(void); +#else +static inline int start_topology_update(void) +{ + return 0; +} +static inline int stop_topology_update(void) +{ + return 0; +} +#endif /* CONFIG_NUMA && CONFIG_PPC_SPLPAR */ + #include <asm-generic/topology.h> #ifdef CONFIG_SMP diff --git a/arch/powerpc/include/asm/vdso_datapage.h b/arch/powerpc/include/asm/vdso_datapage.h index 08679c5319b..25e39220e89 100644 --- a/arch/powerpc/include/asm/vdso_datapage.h +++ b/arch/powerpc/include/asm/vdso_datapage.h @@ -116,9 +116,7 @@ struct vdso_data { #endif /* CONFIG_PPC64 */ -#ifdef __KERNEL__ extern struct vdso_data *vdso_data; -#endif #endif /* __ASSEMBLY__ */ diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile index 36c30f31ec9..3bb2a3e6a33 100644 --- a/arch/powerpc/kernel/Makefile +++ b/arch/powerpc/kernel/Makefile @@ -29,8 +29,10 @@ endif obj-y := cputable.o ptrace.o syscalls.o \ irq.o align.o signal_32.o pmc.o vdso.o \ init_task.o process.o systbl.o idle.o \ - signal.o sysfs.o cacheinfo.o -obj-y += vdso32/ + signal.o sysfs.o cacheinfo.o time.o \ + prom.o traps.o setup-common.o \ + udbg.o misc.o io.o dma.o \ + misc_$(CONFIG_WORD_SIZE).o vdso32/ obj-$(CONFIG_PPC64) += setup_64.o sys_ppc32.o \ signal_64.o ptrace32.o \ paca.o nvram_64.o firmware.o @@ -80,9 +82,6 @@ extra-$(CONFIG_FSL_BOOKE) := head_fsl_booke.o extra-$(CONFIG_8xx) := head_8xx.o extra-y += vmlinux.lds -obj-y += time.o prom.o traps.o setup-common.o \ - udbg.o misc.o io.o dma.o \ - misc_$(CONFIG_WORD_SIZE).o obj-$(CONFIG_PPC32) += entry_32.o setup_32.o obj-$(CONFIG_PPC64) += dma-iommu.o iommu.o obj-$(CONFIG_KGDB) += kgdb.o diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c index bd0df2e6aa8..23e6a93145a 100644 --- a/arch/powerpc/kernel/asm-offsets.c +++ b/arch/powerpc/kernel/asm-offsets.c @@ -209,7 +209,6 @@ int main(void) DEFINE(RTASENTRY, offsetof(struct rtas_t, entry)); /* Interrupt register frame */ - DEFINE(STACK_FRAME_OVERHEAD, STACK_FRAME_OVERHEAD); DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE); DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs)); #ifdef CONFIG_PPC64 diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 96a908f1cd8..be5ab18b03b 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -457,16 +457,26 @@ static struct cpu_spec __initdata cpu_specs[] = { .dcache_bsize = 128, .num_pmcs = 6, .pmc_type = PPC_PMC_IBM, - .cpu_setup = __setup_cpu_power7, - .cpu_restore = __restore_cpu_power7, .oprofile_cpu_type = "ppc64/power7", .oprofile_type = PPC_OPROFILE_POWER4, - .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV, - .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR, - .oprofile_mmcra_clear = POWER6_MMCRA_THRM | - POWER6_MMCRA_OTHER, .platform = "power7", }, + { /* Power7+ */ + .pvr_mask = 0xffff0000, + .pvr_value = 0x004A0000, + .cpu_name = "POWER7+ (raw)", + .cpu_features = CPU_FTRS_POWER7, + .cpu_user_features = COMMON_USER_POWER7, + .mmu_features = MMU_FTR_HPTE_TABLE | + MMU_FTR_TLBIE_206, + .icache_bsize = 128, + .dcache_bsize = 128, + .num_pmcs = 6, + .pmc_type = PPC_PMC_IBM, + .oprofile_cpu_type = "ppc64/power7", + .oprofile_type = PPC_OPROFILE_POWER4, + .platform = "power7+", + }, { /* Cell Broadband Engine */ .pvr_mask = 0xffff0000, .pvr_value = 0x00700000, diff --git a/arch/powerpc/kernel/crash_dump.c b/arch/powerpc/kernel/crash_dump.c index 8e05c16344e..0a2af50243c 100644 --- a/arch/powerpc/kernel/crash_dump.c +++ b/arch/powerpc/kernel/crash_dump.c @@ -19,6 +19,7 @@ #include <asm/prom.h> #include <asm/firmware.h> #include <asm/uaccess.h> +#include <asm/rtas.h> #ifdef DEBUG #include <asm/udbg.h> @@ -141,3 +142,35 @@ ssize_t copy_oldmem_page(unsigned long pfn, char *buf, return csize; } + +#ifdef CONFIG_PPC_RTAS +/* + * The crashkernel region will almost always overlap the RTAS region, so + * we have to be careful when shrinking the crashkernel region. + */ +void crash_free_reserved_phys_range(unsigned long begin, unsigned long end) +{ + unsigned long addr; + const u32 *basep, *sizep; + unsigned int rtas_start = 0, rtas_end = 0; + + basep = of_get_property(rtas.dev, "linux,rtas-base", NULL); + sizep = of_get_property(rtas.dev, "rtas-size", NULL); + + if (basep && sizep) { + rtas_start = *basep; + rtas_end = *basep + *sizep; + } + + for (addr = begin; addr < end; addr += PAGE_SIZE) { + /* Does this page overlap with the RTAS region? */ + if (addr <= rtas_end && ((addr + PAGE_SIZE) > rtas_start)) + continue; + + ClearPageReserved(pfn_to_page(addr >> PAGE_SHIFT)); + init_page_count(pfn_to_page(addr >> PAGE_SHIFT)); + free_page((unsigned long)__va(addr)); + totalram_pages++; + } +} +#endif diff --git a/arch/powerpc/kernel/dma-iommu.c b/arch/powerpc/kernel/dma-iommu.c index 6e54a0fd31a..e7554154a6d 100644 --- a/arch/powerpc/kernel/dma-iommu.c +++ b/arch/powerpc/kernel/dma-iommu.c @@ -19,7 +19,7 @@ static void *dma_iommu_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag) { return iommu_alloc_coherent(dev, get_iommu_table_base(dev), size, - dma_handle, device_to_mask(dev), flag, + dma_handle, dev->coherent_dma_mask, flag, dev_to_node(dev)); } diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index ed4aeb96398..c22dc1ec1c9 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -31,6 +31,7 @@ #include <asm/asm-offsets.h> #include <asm/unistd.h> #include <asm/ftrace.h> +#include <asm/ptrace.h> #undef SHOW_SYSCALLS #undef SHOW_SYSCALLS_TASK diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index 9f8b01d6466..8a817995b4c 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -13,6 +13,7 @@ */ #include <asm/exception-64s.h> +#include <asm/ptrace.h> /* * We layout physical memory as follows: diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S index e86c040ae58..de369558bf0 100644 --- a/arch/powerpc/kernel/fpu.S +++ b/arch/powerpc/kernel/fpu.S @@ -23,6 +23,7 @@ #include <asm/thread_info.h> #include <asm/ppc_asm.h> #include <asm/asm-offsets.h> +#include <asm/ptrace.h> #ifdef CONFIG_VSX #define REST_32FPVSRS(n,c,base) \ diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S index 8278e8bad5a..9dd21a8c4d5 100644 --- a/arch/powerpc/kernel/head_40x.S +++ b/arch/powerpc/kernel/head_40x.S @@ -40,6 +40,7 @@ #include <asm/thread_info.h> #include <asm/ppc_asm.h> #include <asm/asm-offsets.h> +#include <asm/ptrace.h> /* As with the other PowerPC ports, it is expected that when code * execution begins here, the following registers contain valid, yet diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index 562305b40a8..cbb3436b592 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -37,6 +37,7 @@ #include <asm/thread_info.h> #include <asm/ppc_asm.h> #include <asm/asm-offsets.h> +#include <asm/ptrace.h> #include <asm/synch.h> #include "head_booke.h" diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index f0dd577e4a5..782f23df7c8 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -38,6 +38,7 @@ #include <asm/page_64.h> #include <asm/irqflags.h> #include <asm/kvm_book3s_asm.h> +#include <asm/ptrace.h> /* The physical memory is layed out such that the secondary processor * spin code sits at 0x0000...0x00ff. On server, the vectors follow @@ -96,7 +97,7 @@ __secondary_hold_acknowledge: .llong hvReleaseData-KERNELBASE #endif /* CONFIG_PPC_ISERIES */ -#ifdef CONFIG_CRASH_DUMP +#ifdef CONFIG_RELOCATABLE /* This flag is set to 1 by a loader if the kernel should run * at the loaded address instead of the linked address. This * is used by kexec-tools to keep the the kdump kernel in the @@ -384,12 +385,10 @@ _STATIC(__after_prom_start) /* process relocations for the final address of the kernel */ lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ sldi r25,r25,32 -#ifdef CONFIG_CRASH_DUMP lwz r7,__run_at_load-_stext(r26) - cmplwi cr0,r7,1 /* kdump kernel ? - stay where we are */ + cmplwi cr0,r7,1 /* flagged to stay where we are ? */ bne 1f add r25,r25,r26 -#endif 1: mr r3,r25 bl .relocate #endif diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 1f1a04b5c2a..1cbf64e6b41 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -29,6 +29,7 @@ #include <asm/thread_info.h> #include <asm/ppc_asm.h> #include <asm/asm-offsets.h> +#include <asm/ptrace.h> /* Macro to make the code more readable. */ #ifdef CONFIG_8xx_CPU6 diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index 529b817f473..3e02710d956 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -41,6 +41,7 @@ #include <asm/ppc_asm.h> #include <asm/asm-offsets.h> #include <asm/cache.h> +#include <asm/ptrace.h> #include "head_booke.h" /* As with the other PowerPC ports, it is expected that when code diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c index d5839179ec7..961bb03413f 100644 --- a/arch/powerpc/kernel/iommu.c +++ b/arch/powerpc/kernel/iommu.c @@ -311,8 +311,9 @@ int iommu_map_sg(struct device *dev, struct iommu_table *tbl, /* Handle failure */ if (unlikely(entry == DMA_ERROR_CODE)) { if (printk_ratelimit()) - printk(KERN_INFO "iommu_alloc failed, tbl %p vaddr %lx" - " npages %lx\n", tbl, vaddr, npages); + dev_info(dev, "iommu_alloc failed, tbl %p " + "vaddr %lx npages %lu\n", tbl, vaddr, + npages); goto failure; } @@ -579,9 +580,9 @@ dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl, attrs); if (dma_handle == DMA_ERROR_CODE) { if (printk_ratelimit()) { - printk(KERN_INFO "iommu_alloc failed, " - "tbl %p vaddr %p npages %d\n", - tbl, vaddr, npages); + dev_info(dev, "iommu_alloc failed, tbl %p " + "vaddr %p npages %d\n", tbl, vaddr, + npages); } } else dma_handle |= (uaddr & ~IOMMU_PAGE_MASK); @@ -627,7 +628,8 @@ void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl, * the tce tables. */ if (order >= IOMAP_MAX_ORDER) { - printk("iommu_alloc_consistent size too large: 0x%lx\n", size); + dev_info(dev, "iommu_alloc_consistent size too large: 0x%lx\n", + size); return NULL; } diff --git a/arch/powerpc/kernel/misc.S b/arch/powerpc/kernel/misc.S index 2d29752cbe1..b69463ec201 100644 --- a/arch/powerpc/kernel/misc.S +++ b/arch/powerpc/kernel/misc.S @@ -122,8 +122,3 @@ _GLOBAL(longjmp) mtlr r0 mr r3,r4 blr - -_GLOBAL(__setup_cpu_power7) -_GLOBAL(__restore_cpu_power7) - /* place holder */ - blr diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index a7a570dcdd5..094bd9821ad 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S @@ -30,6 +30,7 @@ #include <asm/processor.h> #include <asm/kexec.h> #include <asm/bug.h> +#include <asm/ptrace.h> .text diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S index e5144906a56..206a321a71d 100644 --- a/arch/powerpc/kernel/misc_64.S +++ b/arch/powerpc/kernel/misc_64.S @@ -25,6 +25,7 @@ #include <asm/cputable.h> #include <asm/thread_info.h> #include <asm/kexec.h> +#include <asm/ptrace.h> .text diff --git a/arch/powerpc/kernel/nvram_64.c b/arch/powerpc/kernel/nvram_64.c index 9cf197f01e9..bb12b3248f1 100644 --- a/arch/powerpc/kernel/nvram_64.c +++ b/arch/powerpc/kernel/nvram_64.c @@ -34,15 +34,26 @@ #undef DEBUG_NVRAM -static struct nvram_partition * nvram_part; -static long nvram_error_log_index = -1; -static long nvram_error_log_size = 0; +#define NVRAM_HEADER_LEN sizeof(struct nvram_header) +#define NVRAM_BLOCK_LEN NVRAM_HEADER_LEN + +/* If change this size, then change the size of NVNAME_LEN */ +struct nvram_header { + unsigned char signature; + unsigned char checksum; + unsigned short length; + /* Terminating null required only for names < 12 chars. */ + char name[12]; +}; -struct err_log_info { - int error_type; - unsigned int seq_num; +struct nvram_partition { + struct list_head partition; + struct nvram_header header; + unsigned int index; }; +static LIST_HEAD(nvram_partitions); + static loff_t dev_nvram_llseek(struct file *file, loff_t offset, int origin) { int size; @@ -186,14 +197,12 @@ static struct miscdevice nvram_dev = { #ifdef DEBUG_NVRAM static void __init nvram_print_partitions(char * label) { - struct list_head * p; struct nvram_partition * tmp_part; printk(KERN_WARNING "--------%s---------\n", label); printk(KERN_WARNING "indx\t\tsig\tchks\tlen\tname\n"); - list_for_each(p, &nvram_part->partition) { - tmp_part = list_entry(p, struct nvram_partition, partition); - printk(KERN_WARNING "%4d \t%02x\t%02x\t%d\t%s\n", + list_for_each_entry(tmp_part, &nvram_partitions, partition) { + printk(KERN_WARNING "%4d \t%02x\t%02x\t%d\t%12s\n", tmp_part->index, tmp_part->header.signature, tmp_part->header.checksum, tmp_part->header.length, tmp_part->header.name); @@ -228,95 +237,113 @@ static unsigned char __init nvram_checksum(struct nvram_header *p) return c_sum; } -static int __init nvram_remove_os_partition(void) +/** + * nvram_remove_partition - Remove one or more partitions in nvram + * @name: name of the partition to remove, or NULL for a + * signature only match + * @sig: signature of the partition(s) to remove + */ + +int __init nvram_remove_partition(const char *name, int sig) { - struct list_head *i; - struct list_head *j; - struct nvram_partition * part; - struct nvram_partition * cur_part; + struct nvram_partition *part, *prev, *tmp; int rc; - list_for_each(i, &nvram_part->partition) { - part = list_entry(i, struct nvram_partition, partition); - if (part->header.signature != NVRAM_SIG_OS) + list_for_each_entry(part, &nvram_partitions, partition) { + if (part->header.signature != sig) continue; - - /* Make os partition a free partition */ + if (name && strncmp(name, part->header.name, 12)) + continue; + + /* Make partition a free partition */ part->header.signature = NVRAM_SIG_FREE; - sprintf(part->header.name, "wwwwwwwwwwww"); + strncpy(part->header.name, "wwwwwwwwwwww", 12); part->header.checksum = nvram_checksum(&part->header); - - /* Merge contiguous free partitions backwards */ - list_for_each_prev(j, &part->partition) { - cur_part = list_entry(j, struct nvram_partition, partition); - if (cur_part == nvram_part || cur_part->header.signature != NVRAM_SIG_FREE) { - break; - } - - part->header.length += cur_part->header.length; - part->header.checksum = nvram_checksum(&part->header); - part->index = cur_part->index; - - list_del(&cur_part->partition); - kfree(cur_part); - j = &part->partition; /* fixup our loop */ - } - - /* Merge contiguous free partitions forwards */ - list_for_each(j, &part->partition) { - cur_part = list_entry(j, struct nvram_partition, partition); - if (cur_part == nvram_part || cur_part->header.signature != NVRAM_SIG_FREE) { - break; - } - - part->header.length += cur_part->header.length; - part->header.checksum = nvram_checksum(&part->header); - - list_del(&cur_part->partition); - kfree(cur_part); - j = &part->partition; /* fixup our loop */ - } - rc = nvram_write_header(part); if (rc <= 0) { - printk(KERN_ERR "nvram_remove_os_partition: nvram_write failed (%d)\n", rc); + printk(KERN_ERR "nvram_remove_partition: nvram_write failed (%d)\n", rc); return rc; } + } + /* Merge contiguous ones */ + prev = NULL; + list_for_each_entry_safe(part, tmp, &nvram_partitions, partition) { + if (part->header.signature != NVRAM_SIG_FREE) { + prev = NULL; + continue; + } + if (prev) { + prev->header.length += part->header.length; + prev->header.checksum = nvram_checksum(&part->header); + rc = nvram_write_header(part); + if (rc <= 0) { + printk(KERN_ERR "nvram_remove_partition: nvram_write failed (%d)\n", rc); + return rc; + } + list_del(&part->partition); + kfree(part); + } else + prev = part; } return 0; } -/* nvram_create_os_partition +/** + * nvram_create_partition - Create a partition in nvram + * @name: name of the partition to create + * @sig: signature of the partition to create + * @req_size: size of data to allocate in bytes + * @min_size: minimum acceptable size (0 means req_size) * - * Create a OS linux partition to buffer error logs. - * Will create a partition starting at the first free - * space found if space has enough room. + * Returns a negative error code or a positive nvram index + * of the beginning of the data area of the newly created + * partition. If you provided a min_size smaller than req_size + * you need to query for the actual size yourself after the + * call using nvram_partition_get_size(). */ -static int __init nvram_create_os_partition(void) +loff_t __init nvram_create_partition(const char *name, int sig, + int req_size, int min_size) { struct nvram_partition *part; struct nvram_partition *new_part; struct nvram_partition *free_part = NULL; - int seq_init[2] = { 0, 0 }; + static char nv_init_vals[16]; loff_t tmp_index; long size = 0; int rc; - + + /* Convert sizes from bytes to blocks */ + req_size = _ALIGN_UP(req_size, NVRAM_BLOCK_LEN) / NVRAM_BLOCK_LEN; + min_size = _ALIGN_UP(min_size, NVRAM_BLOCK_LEN) / NVRAM_BLOCK_LEN; + + /* If no minimum size specified, make it the same as the + * requested size + */ + if (min_size == 0) + min_size = req_size; + if (min_size > req_size) + return -EINVAL; + + /* Now add one block to each for the header */ + req_size += 1; + min_size += 1; + /* Find a free partition that will give us the maximum needed size If can't find one that will give us the minimum size needed */ - list_for_each_entry(part, &nvram_part->partition, partition) { + list_for_each_entry(part, &nvram_partitions, partition) { if (part->header.signature != NVRAM_SIG_FREE) continue; - if (part->header.length >= NVRAM_MAX_REQ) { - size = NVRAM_MAX_REQ; + if (part->header.length >= req_size) { + size = req_size; free_part = part; break; } - if (!size && part->header.length >= NVRAM_MIN_REQ) { - size = NVRAM_MIN_REQ; + if (part->header.length > size && + part->header.length >= min_size) { + size = part->header.length; free_part = part; } } @@ -326,136 +353,95 @@ static int __init nvram_create_os_partition(void) /* Create our OS partition */ new_part = kmalloc(sizeof(*new_part), GFP_KERNEL); if (!new_part) { - printk(KERN_ERR "nvram_create_os_partition: kmalloc failed\n"); + pr_err("nvram_create_os_partition: kmalloc failed\n"); return -ENOMEM; } new_part->index = free_part->index; - new_part->header.signature = NVRAM_SIG_OS; + new_part->header.signature = sig; new_part->header.length = size; - strcpy(new_part->header.name, "ppc64,linux"); + strncpy(new_part->header.name, name, 12); new_part->header.checksum = nvram_checksum(&new_part->header); rc = nvram_write_header(new_part); if (rc <= 0) { - printk(KERN_ERR "nvram_create_os_partition: nvram_write_header " - "failed (%d)\n", rc); - return rc; - } - - /* make sure and initialize to zero the sequence number and the error - type logged */ - tmp_index = new_part->index + NVRAM_HEADER_LEN; - rc = ppc_md.nvram_write((char *)&seq_init, sizeof(seq_init), &tmp_index); - if (rc <= 0) { - printk(KERN_ERR "nvram_create_os_partition: nvram_write " + pr_err("nvram_create_os_partition: nvram_write_header " "failed (%d)\n", rc); return rc; } - - nvram_error_log_index = new_part->index + NVRAM_HEADER_LEN; - nvram_error_log_size = ((part->header.length - 1) * - NVRAM_BLOCK_LEN) - sizeof(struct err_log_info); - list_add_tail(&new_part->partition, &free_part->partition); - if (free_part->header.length <= size) { + /* Adjust or remove the partition we stole the space from */ + if (free_part->header.length > size) { + free_part->index += size * NVRAM_BLOCK_LEN; + free_part->header.length -= size; + free_part->header.checksum = nvram_checksum(&free_part->header); + rc = nvram_write_header(free_part); + if (rc <= 0) { + pr_err("nvram_create_os_partition: nvram_write_header " + "failed (%d)\n", rc); + return rc; + } + } else { list_del(&free_part->partition); kfree(free_part); - return 0; } - /* Adjust the partition we stole the space from */ - free_part->index += size * NVRAM_BLOCK_LEN; - free_part->header.length -= size; - free_part->header.checksum = nvram_checksum(&free_part->header); - - rc = nvram_write_header(free_part); - if (rc <= 0) { - printk(KERN_ERR "nvram_create_os_partition: nvram_write_header " - "failed (%d)\n", rc); - return rc; + /* Clear the new partition */ + for (tmp_index = new_part->index + NVRAM_HEADER_LEN; + tmp_index < ((size - 1) * NVRAM_BLOCK_LEN); + tmp_index += NVRAM_BLOCK_LEN) { + rc = ppc_md.nvram_write(nv_init_vals, NVRAM_BLOCK_LEN, &tmp_index); + if (rc <= 0) { + pr_err("nvram_create_partition: nvram_write failed (%d)\n", rc); + return rc; + } } - - return 0; + + return new_part->index + NVRAM_HEADER_LEN; } - -/* nvram_setup_partition - * - * This will setup the partition we need for buffering the - * error logs and cleanup partitions if needed. - * - * The general strategy is the following: - * 1.) If there is ppc64,linux partition large enough then use it. - * 2.) If there is not a ppc64,linux partition large enough, search - * for a free partition that is large enough. - * 3.) If there is not a free partition large enough remove - * _all_ OS partitions and consolidate the space. - * 4.) Will first try getting a chunk that will satisfy the maximum - * error log size (NVRAM_MAX_REQ). - * 5.) If the max chunk cannot be allocated then try finding a chunk - * that will satisfy the minum needed (NVRAM_MIN_REQ). +/** + * nvram_get_partition_size - Get the data size of an nvram partition + * @data_index: This is the offset of the start of the data of + * the partition. The same value that is returned by + * nvram_create_partition(). */ -static int __init nvram_setup_partition(void) +int nvram_get_partition_size(loff_t data_index) { - struct list_head * p; - struct nvram_partition * part; - int rc; - - /* For now, we don't do any of this on pmac, until I - * have figured out if it's worth killing some unused stuffs - * in our nvram, as Apple defined partitions use pretty much - * all of the space - */ - if (machine_is(powermac)) - return -ENOSPC; - - /* see if we have an OS partition that meets our needs. - will try getting the max we need. If not we'll delete - partitions and try again. */ - list_for_each(p, &nvram_part->partition) { - part = list_entry(p, struct nvram_partition, partition); - if (part->header.signature != NVRAM_SIG_OS) - continue; + struct nvram_partition *part; + + list_for_each_entry(part, &nvram_partitions, partition) { + if (part->index + NVRAM_HEADER_LEN == data_index) + return (part->header.length - 1) * NVRAM_BLOCK_LEN; + } + return -1; +} - if (strcmp(part->header.name, "ppc64,linux")) - continue; - if (part->header.length >= NVRAM_MIN_REQ) { - /* found our partition */ - nvram_error_log_index = part->index + NVRAM_HEADER_LEN; - nvram_error_log_size = ((part->header.length - 1) * - NVRAM_BLOCK_LEN) - sizeof(struct err_log_info); - return 0; +/** + * nvram_find_partition - Find an nvram partition by signature and name + * @name: Name of the partition or NULL for any name + * @sig: Signature to test against + * @out_size: if non-NULL, returns the size of the data part of the partition + */ +loff_t nvram_find_partition(const char *name, int sig, int *out_size) +{ + struct nvram_partition *p; + + list_for_each_entry(p, &nvram_partitions, partition) { + if (p->header.signature == sig && + (!name || !strncmp(p->header.name, name, 12))) { + if (out_size) + *out_size = (p->header.length - 1) * + NVRAM_BLOCK_LEN; + return p->index + NVRAM_HEADER_LEN; } } - - /* try creating a partition with the free space we have */ - rc = nvram_create_os_partition(); - if (!rc) { - return 0; - } - - /* need to free up some space */ - rc = nvram_remove_os_partition(); - if (rc) { - return rc; - } - - /* create a partition in this new space */ - rc = nvram_create_os_partition(); - if (rc) { - printk(KERN_ERR "nvram_create_os_partition: Could not find a " - "NVRAM partition large enough\n"); - return rc; - } - return 0; } - -static int __init nvram_scan_partitions(void) +int __init nvram_scan_partitions(void) { loff_t cur_index = 0; struct nvram_header phead; @@ -465,7 +451,7 @@ static int __init nvram_scan_partitions(void) int total_size; int err; - if (ppc_md.nvram_size == NULL) + if (ppc_md.nvram_size == NULL || ppc_md.nvram_size() <= 0) return -ENODEV; total_size = ppc_md.nvram_size(); @@ -512,12 +498,16 @@ static int __init nvram_scan_partitions(void) memcpy(&tmp_part->header, &phead, NVRAM_HEADER_LEN); tmp_part->index = cur_index; - list_add_tail(&tmp_part->partition, &nvram_part->partition); + list_add_tail(&tmp_part->partition, &nvram_partitions); cur_index += phead.length * NVRAM_BLOCK_LEN; } err = 0; +#ifdef DEBUG_NVRAM + nvram_print_partitions("NVRAM Partitions"); +#endif + out: kfree(header); return err; @@ -525,9 +515,10 @@ static int __init nvram_scan_partitions(void) static int __init nvram_init(void) { - int error; int rc; + BUILD_BUG_ON(NVRAM_BLOCK_LEN != 16); + if (ppc_md.nvram_size == NULL || ppc_md.nvram_size() <= 0) return -ENODEV; @@ -537,29 +528,6 @@ static int __init nvram_init(void) return rc; } - /* initialize our anchor for the nvram partition list */ - nvram_part = kmalloc(sizeof(struct nvram_partition), GFP_KERNEL); - if (!nvram_part) { - printk(KERN_ERR "nvram_init: Failed kmalloc\n"); - return -ENOMEM; - } - INIT_LIST_HEAD(&nvram_part->partition); - - /* Get all the NVRAM partitions */ - error = nvram_scan_partitions(); - if (error) { - printk(KERN_ERR "nvram_init: Failed nvram_scan_partitions\n"); - return error; - } - - if(nvram_setup_partition()) - printk(KERN_WARNING "nvram_init: Could not find nvram partition" - " for nvram buffered error logging.\n"); - -#ifdef DEBUG_NVRAM - nvram_print_partitions("NVRAM Partitions"); -#endif - return rc; } @@ -568,135 +536,6 @@ void __exit nvram_cleanup(void) misc_deregister( &nvram_dev ); } - -#ifdef CONFIG_PPC_PSERIES - -/* nvram_write_error_log - * - * We need to buffer the error logs into nvram to ensure that we have - * the failure information to decode. If we have a severe error there - * is no way to guarantee that the OS or the machine is in a state to - * get back to user land and write the error to disk. For example if - * the SCSI device driver causes a Machine Check by writing to a bad - * IO address, there is no way of guaranteeing that the device driver - * is in any state that is would also be able to write the error data - * captured to disk, thus we buffer it in NVRAM for analysis on the - * next boot. - * - * In NVRAM the partition containing the error log buffer will looks like: - * Header (in bytes): - * +-----------+----------+--------+------------+------------------+ - * | signature | checksum | length | name | data | - * |0 |1 |2 3|4 15|16 length-1| - * +-----------+----------+--------+------------+------------------+ - * - * The 'data' section would look like (in bytes): - * +--------------+------------+-----------------------------------+ - * | event_logged | sequence # | error log | - * |0 3|4 7|8 nvram_error_log_size-1| - * +--------------+------------+-----------------------------------+ - * - * event_logged: 0 if event has not been logged to syslog, 1 if it has - * sequence #: The unique sequence # for each event. (until it wraps) - * error log: The error log from event_scan - */ -int nvram_write_error_log(char * buff, int length, - unsigned int err_type, unsigned int error_log_cnt) -{ - int rc; - loff_t tmp_index; - struct err_log_info info; - - if (nvram_error_log_index == -1) { - return -ESPIPE; - } - - if (length > nvram_error_log_size) { - length = nvram_error_log_size; - } - - info.error_type = err_type; - info.seq_num = error_log_cnt; - - tmp_index = nvram_error_log_index; - - rc = ppc_md.nvram_write((char *)&info, sizeof(struct err_log_info), &tmp_index); - if (rc <= 0) { - printk(KERN_ERR "nvram_write_error_log: Failed nvram_write (%d)\n", rc); - return rc; - } - - rc = ppc_md.nvram_write(buff, length, &tmp_index); - if (rc <= 0) { - printk(KERN_ERR "nvram_write_error_log: Failed nvram_write (%d)\n", rc); - return rc; - } - - return 0; -} - -/* nvram_read_error_log - * - * Reads nvram for error log for at most 'length' - */ -int nvram_read_error_log(char * buff, int length, - unsigned int * err_type, unsigned int * error_log_cnt) -{ - int rc; - loff_t tmp_index; - struct err_log_info info; - - if (nvram_error_log_index == -1) - return -1; - - if (length > nvram_error_log_size) - length = nvram_error_log_size; - - tmp_index = nvram_error_log_index; - - rc = ppc_md.nvram_read((char *)&info, sizeof(struct err_log_info), &tmp_index); - if (rc <= 0) { - printk(KERN_ERR "nvram_read_error_log: Failed nvram_read (%d)\n", rc); - return rc; - } - - rc = ppc_md.nvram_read(buff, length, &tmp_index); - if (rc <= 0) { - printk(KERN_ERR "nvram_read_error_log: Failed nvram_read (%d)\n", rc); - return rc; - } - - *error_log_cnt = info.seq_num; - *err_type = info.error_type; - - return 0; -} - -/* This doesn't actually zero anything, but it sets the event_logged - * word to tell that this event is safely in syslog. - */ -int nvram_clear_error_log(void) -{ - loff_t tmp_index; - int clear_word = ERR_FLAG_ALREADY_LOGGED; - int rc; - - if (nvram_error_log_index == -1) - return -1; - - tmp_index = nvram_error_log_index; - - rc = ppc_md.nvram_write((char *)&clear_word, sizeof(int), &tmp_index); - if (rc <= 0) { - printk(KERN_ERR "nvram_clear_error_log: Failed nvram_write (%d)\n", rc); - return rc; - } - - return 0; -} - -#endif /* CONFIG_PPC_PSERIES */ - module_init(nvram_init); module_exit(nvram_cleanup); MODULE_LICENSE("GPL"); diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c index d43fc65749c..851577608a7 100644 --- a/arch/powerpc/kernel/pci_64.c +++ b/arch/powerpc/kernel/pci_64.c @@ -193,8 +193,7 @@ int __devinit pcibios_map_io_space(struct pci_bus *bus) hose->io_resource.start += io_virt_offset; hose->io_resource.end += io_virt_offset; - pr_debug(" hose->io_resource=0x%016llx...0x%016llx\n", - hose->io_resource.start, hose->io_resource.end); + pr_debug(" hose->io_resource=%pR\n", &hose->io_resource); return 0; } diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c index ab3e392ac63..ef3ef566235 100644 --- a/arch/powerpc/kernel/ppc_ksyms.c +++ b/arch/powerpc/kernel/ppc_ksyms.c @@ -186,3 +186,10 @@ EXPORT_SYMBOL(__mtdcr); EXPORT_SYMBOL(__mfdcr); #endif EXPORT_SYMBOL(empty_zero_page); + +#ifdef CONFIG_PPC64 +EXPORT_SYMBOL(__arch_hweight8); +EXPORT_SYMBOL(__arch_hweight16); +EXPORT_SYMBOL(__arch_hweight32); +EXPORT_SYMBOL(__arch_hweight64); +#endif diff --git a/arch/powerpc/kernel/ppc_save_regs.S b/arch/powerpc/kernel/ppc_save_regs.S index 5113bd2285e..e83ba3f078e 100644 --- a/arch/powerpc/kernel/ppc_save_regs.S +++ b/arch/powerpc/kernel/ppc_save_regs.S @@ -11,6 +11,7 @@ #include <asm/processor.h> #include <asm/ppc_asm.h> #include <asm/asm-offsets.h> +#include <asm/ptrace.h> /* * Grab the register values as they are now. diff --git a/arch/powerpc/kernel/prom_parse.c b/arch/powerpc/kernel/prom_parse.c index 88334af038e..c2b7a07cc3d 100644 --- a/arch/powerpc/kernel/prom_parse.c +++ b/arch/powerpc/kernel/prom_parse.c @@ -117,41 +117,3 @@ void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop, cells = prop ? *(u32 *)prop : of_n_size_cells(dn); *size = of_read_number(dma_window, cells); } - -/** - * Search the device tree for the best MAC address to use. 'mac-address' is - * checked first, because that is supposed to contain to "most recent" MAC - * address. If that isn't set, then 'local-mac-address' is checked next, - * because that is the default address. If that isn't set, then the obsolete - * 'address' is checked, just in case we're using an old device tree. - * - * Note that the 'address' property is supposed to contain a virtual address of - * the register set, but some DTS files have redefined that property to be the - * MAC address. - * - * All-zero MAC addresses are rejected, because those could be properties that - * exist in the device tree, but were not set by U-Boot. For example, the - * DTS could define 'mac-address' and 'local-mac-address', with zero MAC - * addresses. Some older U-Boots only initialized 'local-mac-address'. In - * this case, the real MAC is in 'local-mac-address', and 'mac-address' exists - * but is all zeros. -*/ -const void *of_get_mac_address(struct device_node *np) -{ - struct property *pp; - - pp = of_find_property(np, "mac-address", NULL); - if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value)) - return pp->value; - - pp = of_find_property(np, "local-mac-address", NULL); - if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value)) - return pp->value; - - pp = of_find_property(np, "address", NULL); - if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value)) - return pp->value; - - return NULL; -} -EXPORT_SYMBOL(of_get_mac_address); diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c index a9b32967cff..90653699829 100644 --- a/arch/powerpc/kernel/ptrace.c +++ b/arch/powerpc/kernel/ptrace.c @@ -1316,6 +1316,10 @@ static int set_dac_range(struct task_struct *child, static long ppc_set_hwdebug(struct task_struct *child, struct ppc_hw_breakpoint *bp_info) { +#ifndef CONFIG_PPC_ADV_DEBUG_REGS + unsigned long dabr; +#endif + if (bp_info->version != 1) return -ENOTSUPP; #ifdef CONFIG_PPC_ADV_DEBUG_REGS @@ -1353,11 +1357,10 @@ static long ppc_set_hwdebug(struct task_struct *child, /* * We only support one data breakpoint */ - if (((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0) || - ((bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0) || - (bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_WRITE) || - (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) || - (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)) + if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 || + (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 || + bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT || + bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE) return -EINVAL; if (child->thread.dabr) @@ -1366,7 +1369,14 @@ static long ppc_set_hwdebug(struct task_struct *child, if ((unsigned long)bp_info->addr >= TASK_SIZE) return -EIO; - child->thread.dabr = (unsigned long)bp_info->addr; + dabr = (unsigned long)bp_info->addr & ~7UL; + dabr |= DABR_TRANSLATION; + if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) + dabr |= DABR_DATA_READ; + if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) + dabr |= DABR_DATA_WRITE; + + child->thread.dabr = dabr; return 1; #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */ diff --git a/arch/powerpc/kernel/ptrace32.c b/arch/powerpc/kernel/ptrace32.c index 8a6daf4129f..69c4be917d0 100644 --- a/arch/powerpc/kernel/ptrace32.c +++ b/arch/powerpc/kernel/ptrace32.c @@ -280,7 +280,11 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, /* We only support one DABR and no IABRS at the moment */ if (addr > 0) break; +#ifdef CONFIG_PPC_ADV_DEBUG_REGS + ret = put_user(child->thread.dac1, (u32 __user *)data); +#else ret = put_user(child->thread.dabr, (u32 __user *)data); +#endif break; } @@ -312,6 +316,9 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, case PTRACE_SET_DEBUGREG: case PTRACE_SYSCALL: case PTRACE_CONT: + case PPC_PTRACE_GETHWDBGINFO: + case PPC_PTRACE_SETHWDEBUG: + case PPC_PTRACE_DELHWDEBUG: ret = arch_ptrace(child, request, addr, data); break; diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c index 8fe8bc61c10..2097f2b3cba 100644 --- a/arch/powerpc/kernel/rtas.c +++ b/arch/powerpc/kernel/rtas.c @@ -41,6 +41,7 @@ #include <asm/atomic.h> #include <asm/time.h> #include <asm/mmu.h> +#include <asm/topology.h> struct rtas_t rtas = { .lock = __ARCH_SPIN_LOCK_UNLOCKED @@ -713,6 +714,7 @@ static int __rtas_suspend_last_cpu(struct rtas_suspend_me_data *data, int wake_w int cpu; slb_set_size(SLB_MIN_SIZE); + stop_topology_update(); printk(KERN_DEBUG "calling ibm,suspend-me on cpu %i\n", smp_processor_id()); while (rc == H_MULTI_THREADS_ACTIVE && !atomic_read(&data->done) && @@ -728,6 +730,7 @@ static int __rtas_suspend_last_cpu(struct rtas_suspend_me_data *data, int wake_w rc = atomic_read(&data->error); atomic_set(&data->error, rc); + start_topology_update(); if (wake_when_done) { atomic_set(&data->done, 1); diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c index ce6f61c6f87..5a0401fcaeb 100644 --- a/arch/powerpc/kernel/setup_64.c +++ b/arch/powerpc/kernel/setup_64.c @@ -437,8 +437,8 @@ static void __init irqstack_early_init(void) unsigned int i; /* - * interrupt stacks must be under 256MB, we cannot afford to take - * SLB misses on them. + * Interrupt stacks must be in the first segment since we + * cannot afford to take SLB misses on them. */ for_each_possible_cpu(i) { softirq_ctx[i] = (struct thread_info *) diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index 68034bbf2e4..98136050917 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -466,7 +466,20 @@ out: return id; } -/* Must be called when no change can occur to cpu_present_mask, +/* Helper routines for cpu to core mapping */ +int cpu_core_index_of_thread(int cpu) +{ + return cpu >> threads_shift; +} +EXPORT_SYMBOL_GPL(cpu_core_index_of_thread); + +int cpu_first_thread_of_core(int core) +{ + return core << threads_shift; +} +EXPORT_SYMBOL_GPL(cpu_first_thread_of_core); + +/* Must be called when no change can occur to cpu_present_map, * i.e. during cpu online or offline. */ static struct device_node *cpu_to_l2cache(int cpu) @@ -514,7 +527,7 @@ int __devinit start_secondary(void *unused) notify_cpu_starting(cpu); set_cpu_online(cpu, true); /* Update sibling maps */ - base = cpu_first_thread_in_core(cpu); + base = cpu_first_thread_sibling(cpu); for (i = 0; i < threads_per_core; i++) { if (cpu_is_offline(base + i)) continue; @@ -600,7 +613,7 @@ int __cpu_disable(void) return err; /* Update sibling maps */ - base = cpu_first_thread_in_core(cpu); + base = cpu_first_thread_sibling(cpu); for (i = 0; i < threads_per_core; i++) { cpumask_clear_cpu(cpu, cpu_sibling_mask(base + i)); cpumask_clear_cpu(base + i, cpu_sibling_mask(cpu)); diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c index 010406958d9..09e4dea4a85 100644 --- a/arch/powerpc/kernel/time.c +++ b/arch/powerpc/kernel/time.c @@ -155,7 +155,7 @@ EXPORT_SYMBOL_GPL(rtc_lock); static u64 tb_to_ns_scale __read_mostly; static unsigned tb_to_ns_shift __read_mostly; -static unsigned long boot_tb __read_mostly; +static u64 boot_tb __read_mostly; extern struct timezone sys_tz; static long timezone_offset; diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/kernel/vector.S index fe460482fa6..9de6f396cf8 100644 --- a/arch/powerpc/kernel/vector.S +++ b/arch/powerpc/kernel/vector.S @@ -5,6 +5,7 @@ #include <asm/cputable.h> #include <asm/thread_info.h> #include <asm/page.h> +#include <asm/ptrace.h> /* * load_up_altivec(unused, unused, tsk) diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c index 441d2a722f0..1b695fdc362 100644 --- a/arch/powerpc/kernel/vio.c +++ b/arch/powerpc/kernel/vio.c @@ -600,6 +600,11 @@ static void vio_dma_iommu_unmap_sg(struct device *dev, vio_cmo_dealloc(viodev, alloc_size); } +static int vio_dma_iommu_dma_supported(struct device *dev, u64 mask) +{ + return dma_iommu_ops.dma_supported(dev, mask); +} + struct dma_map_ops vio_dma_mapping_ops = { .alloc_coherent = vio_dma_iommu_alloc_coherent, .free_coherent = vio_dma_iommu_free_coherent, @@ -607,6 +612,7 @@ struct dma_map_ops vio_dma_mapping_ops = { .unmap_sg = vio_dma_iommu_unmap_sg, .map_page = vio_dma_iommu_map_page, .unmap_page = vio_dma_iommu_unmap_page, + .dma_supported = vio_dma_iommu_dma_supported, }; @@ -858,8 +864,7 @@ static void vio_cmo_bus_remove(struct vio_dev *viodev) static void vio_cmo_set_dma_ops(struct vio_dev *viodev) { - vio_dma_mapping_ops.dma_supported = dma_iommu_ops.dma_supported; - viodev->dev.archdata.dma_ops = &vio_dma_mapping_ops; + set_dma_ops(&viodev->dev, &vio_dma_mapping_ops); } /** @@ -1244,7 +1249,7 @@ struct vio_dev *vio_register_device_node(struct device_node *of_node) if (firmware_has_feature(FW_FEATURE_CMO)) vio_cmo_set_dma_ops(viodev); else - viodev->dev.archdata.dma_ops = &dma_iommu_ops; + set_dma_ops(&viodev->dev, &dma_iommu_ops); set_iommu_table_base(&viodev->dev, vio_build_iommu_table(viodev)); set_dev_node(&viodev->dev, of_node_to_nid(of_node)); @@ -1252,6 +1257,10 @@ struct vio_dev *vio_register_device_node(struct device_node *of_node) viodev->dev.parent = &vio_bus_device.dev; viodev->dev.bus = &vio_bus_type; viodev->dev.release = vio_dev_release; + /* needed to ensure proper operation of coherent allocations + * later, in case driver doesn't set it explicitly */ + dma_set_mask(&viodev->dev, DMA_BIT_MASK(64)); + dma_set_coherent_mask(&viodev->dev, DMA_BIT_MASK(64)); /* register with generic device framework */ if (device_register(&viodev->dev)) { diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 889f2bc106d..166a6a0ad54 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_HAS_IOMEM) += devres.o obj-$(CONFIG_PPC64) += copypage_64.o copyuser_64.o \ memcpy_64.o usercopy_64.o mem_64.o string.o \ - checksum_wrappers_64.o + checksum_wrappers_64.o hweight_64.o obj-$(CONFIG_XMON) += sstep.o ldstfp.o obj-$(CONFIG_KPROBES) += sstep.o ldstfp.o obj-$(CONFIG_HAVE_HW_BREAKPOINT) += sstep.o ldstfp.o diff --git a/arch/powerpc/lib/hweight_64.S b/arch/powerpc/lib/hweight_64.S new file mode 100644 index 00000000000..fda27868cf8 --- /dev/null +++ b/arch/powerpc/lib/hweight_64.S @@ -0,0 +1,110 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) IBM Corporation, 2010 + * + * Author: Anton Blanchard <anton@au.ibm.com> + */ +#include <asm/processor.h> +#include <asm/ppc_asm.h> + +/* Note: This code relies on -mminimal-toc */ + +_GLOBAL(__arch_hweight8) +BEGIN_FTR_SECTION + b .__sw_hweight8 + nop + nop +FTR_SECTION_ELSE + PPC_POPCNTB(r3,r3) + clrldi r3,r3,64-8 + blr +ALT_FTR_SECTION_END_IFCLR(CPU_FTR_POPCNTB) + +_GLOBAL(__arch_hweight16) +BEGIN_FTR_SECTION + b .__sw_hweight16 + nop + nop + nop + nop +FTR_SECTION_ELSE + BEGIN_FTR_SECTION_NESTED(50) + PPC_POPCNTB(r3,r3) + srdi r4,r3,8 + add r3,r4,r3 + clrldi r3,r3,64-8 + blr + FTR_SECTION_ELSE_NESTED(50) + clrlwi r3,r3,16 + PPC_POPCNTW(r3,r3) + clrldi r3,r3,64-8 + blr + ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_POPCNTD, 50) +ALT_FTR_SECTION_END_IFCLR(CPU_FTR_POPCNTB) + +_GLOBAL(__arch_hweight32) +BEGIN_FTR_SECTION + b .__sw_hweight32 + nop + nop + nop + nop + nop + nop +FTR_SECTION_ELSE + BEGIN_FTR_SECTION_NESTED(51) + PPC_POPCNTB(r3,r3) + srdi r4,r3,16 + add r3,r4,r3 + srdi r4,r3,8 + add r3,r4,r3 + clrldi r3,r3,64-8 + blr + FTR_SECTION_ELSE_NESTED(51) + PPC_POPCNTW(r3,r3) + clrldi r3,r3,64-8 + blr + ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_POPCNTD, 51) +ALT_FTR_SECTION_END_IFCLR(CPU_FTR_POPCNTB) + +_GLOBAL(__arch_hweight64) +BEGIN_FTR_SECTION + b .__sw_hweight64 + nop + nop + nop + nop + nop + nop + nop + nop +FTR_SECTION_ELSE + BEGIN_FTR_SECTION_NESTED(52) + PPC_POPCNTB(r3,r3) + srdi r4,r3,32 + add r3,r4,r3 + srdi r4,r3,16 + add r3,r4,r3 + srdi r4,r3,8 + add r3,r4,r3 + clrldi r3,r3,64-8 + blr + FTR_SECTION_ELSE_NESTED(52) + PPC_POPCNTD(r3,r3) + clrldi r3,r3,64-8 + blr + ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_POPCNTD, 52) +ALT_FTR_SECTION_END_IFCLR(CPU_FTR_POPCNTB) diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c index 5e9584405c4..a5991facddc 100644 --- a/arch/powerpc/mm/hash_utils_64.c +++ b/arch/powerpc/mm/hash_utils_64.c @@ -1070,7 +1070,7 @@ void hash_preload(struct mm_struct *mm, unsigned long ea, unsigned long access, unsigned long trap) { unsigned long vsid; - void *pgdir; + pgd_t *pgdir; pte_t *ptep; unsigned long flags; int rc, ssize, local = 0; diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm/mmu_context_nohash.c index 5ce99848d91..c0aab52da3a 100644 --- a/arch/powerpc/mm/mmu_context_nohash.c +++ b/arch/powerpc/mm/mmu_context_nohash.c @@ -111,8 +111,8 @@ static unsigned int steal_context_smp(unsigned int id) * a core map instead but this will do for now. */ for_each_cpu(cpu, mm_cpumask(mm)) { - for (i = cpu_first_thread_in_core(cpu); - i <= cpu_last_thread_in_core(cpu); i++) + for (i = cpu_first_thread_sibling(cpu); + i <= cpu_last_thread_sibling(cpu); i++) __set_bit(id, stale_map[i]); cpu = i - 1; } @@ -264,14 +264,14 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next) */ if (test_bit(id, stale_map[cpu])) { pr_hardcont(" | stale flush %d [%d..%d]", - id, cpu_first_thread_in_core(cpu), - cpu_last_thread_in_core(cpu)); + id, cpu_first_thread_sibling(cpu), + cpu_last_thread_sibling(cpu)); local_flush_tlb_mm(next); /* XXX This clear should ultimately be part of local_flush_tlb_mm */ - for (i = cpu_first_thread_in_core(cpu); - i <= cpu_last_thread_in_core(cpu); i++) { + for (i = cpu_first_thread_sibling(cpu); + i <= cpu_last_thread_sibling(cpu); i++) { __clear_bit(id, stale_map[i]); } } diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c index 74505b24537..bf5cb91f07d 100644 --- a/arch/powerpc/mm/numa.c +++ b/arch/powerpc/mm/numa.c @@ -20,10 +20,15 @@ #include <linux/memblock.h> #include <linux/of.h> #include <linux/pfn.h> +#include <linux/cpuset.h> +#include <linux/node.h> #include <asm/sparsemem.h> #include <asm/prom.h> #include <asm/system.h> #include <asm/smp.h> +#include <asm/firmware.h> +#include <asm/paca.h> +#include <asm/hvcall.h> static int numa_enabled = 1; @@ -163,7 +168,7 @@ static void __init get_node_active_region(unsigned long start_pfn, work_with_active_regions(nid, get_active_region_work_fn, node_ar); } -static void __cpuinit map_cpu_to_node(int cpu, int node) +static void map_cpu_to_node(int cpu, int node) { numa_cpu_lookup_table[cpu] = node; @@ -173,7 +178,7 @@ static void __cpuinit map_cpu_to_node(int cpu, int node) cpumask_set_cpu(cpu, node_to_cpumask_map[node]); } -#ifdef CONFIG_HOTPLUG_CPU +#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PPC_SPLPAR) static void unmap_cpu_from_node(unsigned long cpu) { int node = numa_cpu_lookup_table[cpu]; @@ -187,7 +192,7 @@ static void unmap_cpu_from_node(unsigned long cpu) cpu, node); } } -#endif /* CONFIG_HOTPLUG_CPU */ +#endif /* CONFIG_HOTPLUG_CPU || CONFIG_PPC_SPLPAR */ /* must hold reference to node during call */ static const int *of_get_associativity(struct device_node *dev) @@ -246,32 +251,41 @@ static void initialize_distance_lookup_table(int nid, /* Returns nid in the range [0..MAX_NUMNODES-1], or -1 if no useful numa * info is found. */ -static int of_node_to_nid_single(struct device_node *device) +static int associativity_to_nid(const unsigned int *associativity) { int nid = -1; - const unsigned int *tmp; if (min_common_depth == -1) goto out; - tmp = of_get_associativity(device); - if (!tmp) - goto out; - - if (tmp[0] >= min_common_depth) - nid = tmp[min_common_depth]; + if (associativity[0] >= min_common_depth) + nid = associativity[min_common_depth]; /* POWER4 LPAR uses 0xffff as invalid node */ if (nid == 0xffff || nid >= MAX_NUMNODES) nid = -1; - if (nid > 0 && tmp[0] >= distance_ref_points_depth) - initialize_distance_lookup_table(nid, tmp); + if (nid > 0 && associativity[0] >= distance_ref_points_depth) + initialize_distance_lookup_table(nid, associativity); out: return nid; } +/* Returns the nid associated with the given device tree node, + * or -1 if not found. + */ +static int of_node_to_nid_single(struct device_node *device) +{ + int nid = -1; + const unsigned int *tmp; + + tmp = of_get_associativity(device); + if (tmp) + nid = associativity_to_nid(tmp); + return nid; +} + /* Walk the device tree upwards, looking for an associativity id */ int of_node_to_nid(struct device_node *device) { @@ -1247,4 +1261,275 @@ int hot_add_scn_to_nid(unsigned long scn_addr) return nid; } +static u64 hot_add_drconf_memory_max(void) +{ + struct device_node *memory = NULL; + unsigned int drconf_cell_cnt = 0; + u64 lmb_size = 0; + const u32 *dm = 0; + + memory = of_find_node_by_path("/ibm,dynamic-reconfiguration-memory"); + if (memory) { + drconf_cell_cnt = of_get_drconf_memory(memory, &dm); + lmb_size = of_get_lmb_size(memory); + of_node_put(memory); + } + return lmb_size * drconf_cell_cnt; +} + +/* + * memory_hotplug_max - return max address of memory that may be added + * + * This is currently only used on systems that support drconfig memory + * hotplug. + */ +u64 memory_hotplug_max(void) +{ + return max(hot_add_drconf_memory_max(), memblock_end_of_DRAM()); +} #endif /* CONFIG_MEMORY_HOTPLUG */ + +/* Vrtual Processor Home Node (VPHN) support */ +#ifdef CONFIG_PPC_SPLPAR +#define VPHN_NR_CHANGE_CTRS (8) +static u8 vphn_cpu_change_counts[NR_CPUS][VPHN_NR_CHANGE_CTRS]; +static cpumask_t cpu_associativity_changes_mask; +static int vphn_enabled; +static void set_topology_timer(void); + +/* + * Store the current values of the associativity change counters in the + * hypervisor. + */ +static void setup_cpu_associativity_change_counters(void) +{ + int cpu = 0; + + for_each_possible_cpu(cpu) { + int i = 0; + u8 *counts = vphn_cpu_change_counts[cpu]; + volatile u8 *hypervisor_counts = lppaca[cpu].vphn_assoc_counts; + + for (i = 0; i < VPHN_NR_CHANGE_CTRS; i++) { + counts[i] = hypervisor_counts[i]; + } + } +} + +/* + * The hypervisor maintains a set of 8 associativity change counters in + * the VPA of each cpu that correspond to the associativity levels in the + * ibm,associativity-reference-points property. When an associativity + * level changes, the corresponding counter is incremented. + * + * Set a bit in cpu_associativity_changes_mask for each cpu whose home + * node associativity levels have changed. + * + * Returns the number of cpus with unhandled associativity changes. + */ +static int update_cpu_associativity_changes_mask(void) +{ + int cpu = 0, nr_cpus = 0; + cpumask_t *changes = &cpu_associativity_changes_mask; + + cpumask_clear(changes); + + for_each_possible_cpu(cpu) { + int i, changed = 0; + u8 *counts = vphn_cpu_change_counts[cpu]; + volatile u8 *hypervisor_counts = lppaca[cpu].vphn_assoc_counts; + + for (i = 0; i < VPHN_NR_CHANGE_CTRS; i++) { + if (hypervisor_counts[i] > counts[i]) { + counts[i] = hypervisor_counts[i]; + changed = 1; + } + } + if (changed) { + cpumask_set_cpu(cpu, changes); + nr_cpus++; + } + } + + return nr_cpus; +} + +/* 6 64-bit registers unpacked into 12 32-bit associativity values */ +#define VPHN_ASSOC_BUFSIZE (6*sizeof(u64)/sizeof(u32)) + +/* + * Convert the associativity domain numbers returned from the hypervisor + * to the sequence they would appear in the ibm,associativity property. + */ +static int vphn_unpack_associativity(const long *packed, unsigned int *unpacked) +{ + int i = 0; + int nr_assoc_doms = 0; + const u16 *field = (const u16*) packed; + +#define VPHN_FIELD_UNUSED (0xffff) +#define VPHN_FIELD_MSB (0x8000) +#define VPHN_FIELD_MASK (~VPHN_FIELD_MSB) + + for (i = 0; i < VPHN_ASSOC_BUFSIZE; i++) { + if (*field == VPHN_FIELD_UNUSED) { + /* All significant fields processed, and remaining + * fields contain the reserved value of all 1's. + * Just store them. + */ + unpacked[i] = *((u32*)field); + field += 2; + } + else if (*field & VPHN_FIELD_MSB) { + /* Data is in the lower 15 bits of this field */ + unpacked[i] = *field & VPHN_FIELD_MASK; + field++; + nr_assoc_doms++; + } + else { + /* Data is in the lower 15 bits of this field + * concatenated with the next 16 bit field + */ + unpacked[i] = *((u32*)field); + field += 2; + nr_assoc_doms++; + } + } + + return nr_assoc_doms; +} + +/* + * Retrieve the new associativity information for a virtual processor's + * home node. + */ +static long hcall_vphn(unsigned long cpu, unsigned int *associativity) +{ + long rc = 0; + long retbuf[PLPAR_HCALL9_BUFSIZE] = {0}; + u64 flags = 1; + int hwcpu = get_hard_smp_processor_id(cpu); + + rc = plpar_hcall9(H_HOME_NODE_ASSOCIATIVITY, retbuf, flags, hwcpu); + vphn_unpack_associativity(retbuf, associativity); + + return rc; +} + +static long vphn_get_associativity(unsigned long cpu, + unsigned int *associativity) +{ + long rc = 0; + + rc = hcall_vphn(cpu, associativity); + + switch (rc) { + case H_FUNCTION: + printk(KERN_INFO + "VPHN is not supported. Disabling polling...\n"); + stop_topology_update(); + break; + case H_HARDWARE: + printk(KERN_ERR + "hcall_vphn() experienced a hardware fault " + "preventing VPHN. Disabling polling...\n"); + stop_topology_update(); + } + + return rc; +} + +/* + * Update the node maps and sysfs entries for each cpu whose home node + * has changed. + */ +int arch_update_cpu_topology(void) +{ + int cpu = 0, nid = 0, old_nid = 0; + unsigned int associativity[VPHN_ASSOC_BUFSIZE] = {0}; + struct sys_device *sysdev = NULL; + + for_each_cpu_mask(cpu, cpu_associativity_changes_mask) { + vphn_get_associativity(cpu, associativity); + nid = associativity_to_nid(associativity); + + if (nid < 0 || !node_online(nid)) + nid = first_online_node; + + old_nid = numa_cpu_lookup_table[cpu]; + + /* Disable hotplug while we update the cpu + * masks and sysfs. + */ + get_online_cpus(); + unregister_cpu_under_node(cpu, old_nid); + unmap_cpu_from_node(cpu); + map_cpu_to_node(cpu, nid); + register_cpu_under_node(cpu, nid); + put_online_cpus(); + + sysdev = get_cpu_sysdev(cpu); + if (sysdev) + kobject_uevent(&sysdev->kobj, KOBJ_CHANGE); + } + + return 1; +} + +static void topology_work_fn(struct work_struct *work) +{ + rebuild_sched_domains(); +} +static DECLARE_WORK(topology_work, topology_work_fn); + +void topology_schedule_update(void) +{ + schedule_work(&topology_work); +} + +static void topology_timer_fn(unsigned long ignored) +{ + if (!vphn_enabled) + return; + if (update_cpu_associativity_changes_mask() > 0) + topology_schedule_update(); + set_topology_timer(); +} +static struct timer_list topology_timer = + TIMER_INITIALIZER(topology_timer_fn, 0, 0); + +static void set_topology_timer(void) +{ + topology_timer.data = 0; + topology_timer.expires = jiffies + 60 * HZ; + add_timer(&topology_timer); +} + +/* + * Start polling for VPHN associativity changes. + */ +int start_topology_update(void) +{ + int rc = 0; + + if (firmware_has_feature(FW_FEATURE_VPHN)) { + vphn_enabled = 1; + setup_cpu_associativity_change_counters(); + init_timer_deferrable(&topology_timer); + set_topology_timer(); + rc = 1; + } + + return rc; +} +__initcall(start_topology_update); + +/* + * Disable polling for VPHN associativity changes. + */ +int stop_topology_update(void) +{ + vphn_enabled = 0; + return del_timer_sync(&topology_timer); +} +#endif /* CONFIG_PPC_SPLPAR */ diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c index a87ead0138b..8dc41c0157f 100644 --- a/arch/powerpc/mm/pgtable_32.c +++ b/arch/powerpc/mm/pgtable_32.c @@ -78,7 +78,7 @@ pgd_t *pgd_alloc(struct mm_struct *mm) /* pgdir take page or two with 4K pages and a page fraction otherwise */ #ifndef CONFIG_PPC_4K_PAGES - ret = (pgd_t *)kzalloc(1 << PGDIR_ORDER, GFP_KERNEL); + ret = kzalloc(1 << PGDIR_ORDER, GFP_KERNEL); #else ret = (pgd_t *)__get_free_pages(GFP_KERNEL|__GFP_ZERO, PGDIR_ORDER - PAGE_SHIFT); @@ -230,6 +230,7 @@ __ioremap_caller(phys_addr_t addr, unsigned long size, unsigned long flags, area = get_vm_area_caller(size, VM_IOREMAP, caller); if (area == 0) return NULL; + area->phys_addr = p; v = (unsigned long) area->addr; } else { v = (ioremap_bot -= size); diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c index 21d6dfab794..88927a05cdc 100644 --- a/arch/powerpc/mm/pgtable_64.c +++ b/arch/powerpc/mm/pgtable_64.c @@ -223,6 +223,8 @@ void __iomem * __ioremap_caller(phys_addr_t addr, unsigned long size, caller); if (area == NULL) return NULL; + + area->phys_addr = paligned; ret = __ioremap_at(paligned, area->addr, size, flags); if (!ret) vunmap(area->addr); diff --git a/arch/powerpc/platforms/40x/ppc40x_simple.c b/arch/powerpc/platforms/40x/ppc40x_simple.c index 546bbc229d1..2521d93ef13 100644 --- a/arch/powerpc/platforms/40x/ppc40x_simple.c +++ b/arch/powerpc/platforms/40x/ppc40x_simple.c @@ -50,7 +50,7 @@ machine_device_initcall(ppc40x_simple, ppc40x_device_probe); * Again, if your board needs to do things differently then create a * board.c file for it rather than adding it to this list. */ -static char *board[] __initdata = { +static const char *board[] __initdata = { "amcc,acadia", "amcc,haleakala", "amcc,kilauea", @@ -60,14 +60,9 @@ static char *board[] __initdata = { static int __init ppc40x_probe(void) { - unsigned long root = of_get_flat_dt_root(); - int i = 0; - - for (i = 0; i < ARRAY_SIZE(board); i++) { - if (of_flat_dt_is_compatible(root, board[i])) { - ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC); - return 1; - } + if (of_flat_dt_match(of_get_flat_dt_root(), board)) { + ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC); + return 1; } return 0; diff --git a/arch/powerpc/platforms/44x/Makefile b/arch/powerpc/platforms/44x/Makefile index 82ff326e079..c04d16df848 100644 --- a/arch/powerpc/platforms/44x/Makefile +++ b/arch/powerpc/platforms/44x/Makefile @@ -1,4 +1,7 @@ -obj-$(CONFIG_44x) := misc_44x.o idle.o +obj-$(CONFIG_44x) += misc_44x.o +ifneq ($(CONFIG_PPC4xx_CPM),y) +obj-$(CONFIG_44x) += idle.o +endif obj-$(CONFIG_PPC44x_SIMPLE) += ppc44x_simple.o obj-$(CONFIG_EBONY) += ebony.o obj-$(CONFIG_SAM440EP) += sam440ep.o diff --git a/arch/powerpc/platforms/512x/mpc5121_generic.c b/arch/powerpc/platforms/512x/mpc5121_generic.c index e487eb06ec6..926731f1ff0 100644 --- a/arch/powerpc/platforms/512x/mpc5121_generic.c +++ b/arch/powerpc/platforms/512x/mpc5121_generic.c @@ -26,7 +26,7 @@ /* * list of supported boards */ -static char *board[] __initdata = { +static const char *board[] __initdata = { "prt,prtlvt", NULL }; @@ -36,16 +36,7 @@ static char *board[] __initdata = { */ static int __init mpc5121_generic_probe(void) { - unsigned long node = of_get_flat_dt_root(); - int i = 0; - - while (board[i]) { - if (of_flat_dt_is_compatible(node, board[i])) - break; - i++; - } - - return board[i] != NULL; + return of_flat_dt_match(of_get_flat_dt_root(), board); } define_machine(mpc5121_generic) { diff --git a/arch/powerpc/platforms/52xx/lite5200.c b/arch/powerpc/platforms/52xx/lite5200.c index de55bc0584b..01ffa64d2aa 100644 --- a/arch/powerpc/platforms/52xx/lite5200.c +++ b/arch/powerpc/platforms/52xx/lite5200.c @@ -172,20 +172,18 @@ static void __init lite5200_setup_arch(void) mpc52xx_setup_pci(); } +static const char *board[] __initdata = { + "fsl,lite5200", + "fsl,lite5200b", + NULL, +}; + /* * Called very early, MMU is off, device-tree isn't unflattened */ static int __init lite5200_probe(void) { - unsigned long node = of_get_flat_dt_root(); - const char *model = of_get_flat_dt_prop(node, "model", NULL); - - if (!of_flat_dt_is_compatible(node, "fsl,lite5200") && - !of_flat_dt_is_compatible(node, "fsl,lite5200b")) - return 0; - pr_debug("%s board found\n", model ? model : "unknown"); - - return 1; + return of_flat_dt_match(of_get_flat_dt_root(), board); } define_machine(lite5200) { diff --git a/arch/powerpc/platforms/52xx/media5200.c b/arch/powerpc/platforms/52xx/media5200.c index 0bac3a3dbec..2c7780cb68e 100644 --- a/arch/powerpc/platforms/52xx/media5200.c +++ b/arch/powerpc/platforms/52xx/media5200.c @@ -239,7 +239,7 @@ static void __init media5200_setup_arch(void) } /* list of the supported boards */ -static char *board[] __initdata = { +static const char *board[] __initdata = { "fsl,media5200", NULL }; @@ -249,16 +249,7 @@ static char *board[] __initdata = { */ static int __init media5200_probe(void) { - unsigned long node = of_get_flat_dt_root(); - int i = 0; - - while (board[i]) { - if (of_flat_dt_is_compatible(node, board[i])) - break; - i++; - } - - return (board[i] != NULL); + return of_flat_dt_match(of_get_flat_dt_root(), board); } define_machine(media5200_platform) { diff --git a/arch/powerpc/platforms/52xx/mpc5200_simple.c b/arch/powerpc/platforms/52xx/mpc5200_simple.c index d45be5b5ad4..e36d6e232ae 100644 --- a/arch/powerpc/platforms/52xx/mpc5200_simple.c +++ b/arch/powerpc/platforms/52xx/mpc5200_simple.c @@ -49,7 +49,7 @@ static void __init mpc5200_simple_setup_arch(void) } /* list of the supported boards */ -static char *board[] __initdata = { +static const char *board[] __initdata = { "intercontrol,digsy-mtc", "manroland,mucmc52", "manroland,uc101", @@ -66,16 +66,7 @@ static char *board[] __initdata = { */ static int __init mpc5200_simple_probe(void) { - unsigned long node = of_get_flat_dt_root(); - int i = 0; - - while (board[i]) { - if (of_flat_dt_is_compatible(node, board[i])) - break; - i++; - } - - return (board[i] != NULL); + return of_flat_dt_match(of_get_flat_dt_root(), board); } define_machine(mpc5200_simple_platform) { diff --git a/arch/powerpc/platforms/83xx/mpc830x_rdb.c b/arch/powerpc/platforms/83xx/mpc830x_rdb.c index 846831d495b..661d354e4ff 100644 --- a/arch/powerpc/platforms/83xx/mpc830x_rdb.c +++ b/arch/powerpc/platforms/83xx/mpc830x_rdb.c @@ -57,16 +57,19 @@ static void __init mpc830x_rdb_init_IRQ(void) ipic_set_default_priority(); } +struct const char *board[] __initdata = { + "MPC8308RDB", + "fsl,mpc8308rdb", + "denx,mpc8308_p1m", + NULL +} + /* * Called very early, MMU is off, device-tree isn't unflattened */ static int __init mpc830x_rdb_probe(void) { - unsigned long root = of_get_flat_dt_root(); - - return of_flat_dt_is_compatible(root, "MPC8308RDB") || - of_flat_dt_is_compatible(root, "fsl,mpc8308rdb") || - of_flat_dt_is_compatible(root, "denx,mpc8308_p1m"); + return of_flat_dt_match(of_get_flat_dt_root(), board); } static struct of_device_id __initdata of_bus_ids[] = { diff --git a/arch/powerpc/platforms/83xx/mpc831x_rdb.c b/arch/powerpc/platforms/83xx/mpc831x_rdb.c index ae525e4745d..b54cd736a89 100644 --- a/arch/powerpc/platforms/83xx/mpc831x_rdb.c +++ b/arch/powerpc/platforms/83xx/mpc831x_rdb.c @@ -60,15 +60,18 @@ static void __init mpc831x_rdb_init_IRQ(void) ipic_set_default_priority(); } +struct const char *board[] __initdata = { + "MPC8313ERDB", + "fsl,mpc8315erdb", + NULL +} + /* * Called very early, MMU is off, device-tree isn't unflattened */ static int __init mpc831x_rdb_probe(void) { - unsigned long root = of_get_flat_dt_root(); - - return of_flat_dt_is_compatible(root, "MPC8313ERDB") || - of_flat_dt_is_compatible(root, "fsl,mpc8315erdb"); + return of_flat_dt_match(of_get_flat_dt_root(), board); } static struct of_device_id __initdata of_bus_ids[] = { diff --git a/arch/powerpc/platforms/83xx/mpc837x_rdb.c b/arch/powerpc/platforms/83xx/mpc837x_rdb.c index 910caa6b581..7bafbf2ec0f 100644 --- a/arch/powerpc/platforms/83xx/mpc837x_rdb.c +++ b/arch/powerpc/platforms/83xx/mpc837x_rdb.c @@ -101,17 +101,20 @@ static void __init mpc837x_rdb_init_IRQ(void) ipic_set_default_priority(); } +static const char *board[] __initdata = { + "fsl,mpc8377rdb", + "fsl,mpc8378rdb", + "fsl,mpc8379rdb", + "fsl,mpc8377wlan", + NULL +}; + /* * Called very early, MMU is off, device-tree isn't unflattened */ static int __init mpc837x_rdb_probe(void) { - unsigned long root = of_get_flat_dt_root(); - - return of_flat_dt_is_compatible(root, "fsl,mpc8377rdb") || - of_flat_dt_is_compatible(root, "fsl,mpc8378rdb") || - of_flat_dt_is_compatible(root, "fsl,mpc8379rdb") || - of_flat_dt_is_compatible(root, "fsl,mpc8377wlan"); + return of_flat_dt_match(of_get_flat_dt_root(), board); } define_machine(mpc837x_rdb) { diff --git a/arch/powerpc/platforms/85xx/tqm85xx.c b/arch/powerpc/platforms/85xx/tqm85xx.c index 8f29bbce536..5e847d0b47c 100644 --- a/arch/powerpc/platforms/85xx/tqm85xx.c +++ b/arch/powerpc/platforms/85xx/tqm85xx.c @@ -186,21 +186,21 @@ static int __init declare_of_platform_devices(void) } machine_device_initcall(tqm85xx, declare_of_platform_devices); +static const char *board[] __initdata = { + "tqc,tqm8540", + "tqc,tqm8541", + "tqc,tqm8548", + "tqc,tqm8555", + "tqc,tqm8560", + NULL +}; + /* * Called very early, device-tree isn't unflattened */ static int __init tqm85xx_probe(void) { - unsigned long root = of_get_flat_dt_root(); - - if ((of_flat_dt_is_compatible(root, "tqc,tqm8540")) || - (of_flat_dt_is_compatible(root, "tqc,tqm8541")) || - (of_flat_dt_is_compatible(root, "tqc,tqm8548")) || - (of_flat_dt_is_compatible(root, "tqc,tqm8555")) || - (of_flat_dt_is_compatible(root, "tqc,tqm8560"))) - return 1; - - return 0; + return of_flat_dt_match(of_get_flat_dt_root(), board); } define_machine(tqm85xx) { diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig index 956154f32cf..20576829eca 100644 --- a/arch/powerpc/platforms/Kconfig +++ b/arch/powerpc/platforms/Kconfig @@ -313,13 +313,14 @@ config OF_RTC source "arch/powerpc/sysdev/bestcomm/Kconfig" config MPC8xxx_GPIO - bool "MPC8xxx GPIO support" - depends on PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || FSL_SOC_BOOKE || PPC_86xx + bool "MPC512x/MPC8xxx GPIO support" + depends on PPC_MPC512x || PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || \ + FSL_SOC_BOOKE || PPC_86xx select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB help Say Y here if you're going to use hardware that connects to the - MPC831x/834x/837x/8572/8610 GPIOs. + MPC512x/831x/834x/837x/8572/8610 GPIOs. config SIMPLE_GPIO bool "Support for simple, memory-mapped GPIO controllers" diff --git a/arch/powerpc/platforms/cell/beat_iommu.c b/arch/powerpc/platforms/cell/beat_iommu.c index beec405eb6f..3ce68556893 100644 --- a/arch/powerpc/platforms/cell/beat_iommu.c +++ b/arch/powerpc/platforms/cell/beat_iommu.c @@ -76,7 +76,7 @@ static void __init celleb_init_direct_mapping(void) static void celleb_dma_dev_setup(struct device *dev) { - dev->archdata.dma_ops = get_pci_dma_ops(); + set_dma_ops(dev, &dma_direct_ops); set_dma_offset(dev, celleb_dma_direct_offset); } @@ -106,7 +106,6 @@ static struct notifier_block celleb_of_bus_notifier = { static int __init celleb_init_iommu(void) { celleb_init_direct_mapping(); - set_pci_dma_ops(&dma_direct_ops); ppc_md.pci_dma_dev_setup = celleb_pci_dma_dev_setup; bus_register_notifier(&platform_bus_type, &celleb_of_bus_notifier); diff --git a/arch/powerpc/platforms/cell/spufs/lscsa_alloc.c b/arch/powerpc/platforms/cell/spufs/lscsa_alloc.c index a101abf1750..3b894f58528 100644 --- a/arch/powerpc/platforms/cell/spufs/lscsa_alloc.c +++ b/arch/powerpc/platforms/cell/spufs/lscsa_alloc.c @@ -36,10 +36,9 @@ static int spu_alloc_lscsa_std(struct spu_state *csa) struct spu_lscsa *lscsa; unsigned char *p; - lscsa = vmalloc(sizeof(struct spu_lscsa)); + lscsa = vzalloc(sizeof(struct spu_lscsa)); if (!lscsa) return -ENOMEM; - memset(lscsa, 0, sizeof(struct spu_lscsa)); csa->lscsa = lscsa; /* Set LS pages reserved to allow for user-space mapping. */ diff --git a/arch/powerpc/platforms/chrp/time.c b/arch/powerpc/platforms/chrp/time.c index 054dfe5b8e7..f803f4b8ab6 100644 --- a/arch/powerpc/platforms/chrp/time.c +++ b/arch/powerpc/platforms/chrp/time.c @@ -29,6 +29,10 @@ extern spinlock_t rtc_lock; +#define NVRAM_AS0 0x74 +#define NVRAM_AS1 0x75 +#define NVRAM_DATA 0x77 + static int nvram_as1 = NVRAM_AS1; static int nvram_as0 = NVRAM_AS0; static int nvram_data = NVRAM_DATA; diff --git a/arch/powerpc/platforms/iseries/mf.c b/arch/powerpc/platforms/iseries/mf.c index 42d0a886de0..b5e026bdca2 100644 --- a/arch/powerpc/platforms/iseries/mf.c +++ b/arch/powerpc/platforms/iseries/mf.c @@ -1045,71 +1045,9 @@ static const struct file_operations mf_side_proc_fops = { .write = mf_side_proc_write, }; -#if 0 -static void mf_getSrcHistory(char *buffer, int size) -{ - struct IplTypeReturnStuff return_stuff; - struct pending_event *ev = new_pending_event(); - int rc = 0; - char *pages[4]; - - pages[0] = kmalloc(4096, GFP_ATOMIC); - pages[1] = kmalloc(4096, GFP_ATOMIC); - pages[2] = kmalloc(4096, GFP_ATOMIC); - pages[3] = kmalloc(4096, GFP_ATOMIC); - if ((ev == NULL) || (pages[0] == NULL) || (pages[1] == NULL) - || (pages[2] == NULL) || (pages[3] == NULL)) - return -ENOMEM; - - return_stuff.xType = 0; - return_stuff.xRc = 0; - return_stuff.xDone = 0; - ev->event.hp_lp_event.xSubtype = 6; - ev->event.hp_lp_event.x.xSubtypeData = - subtype_data('M', 'F', 'V', 'I'); - ev->event.data.vsp_cmd.xEvent = &return_stuff; - ev->event.data.vsp_cmd.cmd = 4; - ev->event.data.vsp_cmd.lp_index = HvLpConfig_getLpIndex(); - ev->event.data.vsp_cmd.result_code = 0xFF; - ev->event.data.vsp_cmd.reserved = 0; - ev->event.data.vsp_cmd.sub_data.page[0] = iseries_hv_addr(pages[0]); - ev->event.data.vsp_cmd.sub_data.page[1] = iseries_hv_addr(pages[1]); - ev->event.data.vsp_cmd.sub_data.page[2] = iseries_hv_addr(pages[2]); - ev->event.data.vsp_cmd.sub_data.page[3] = iseries_hv_addr(pages[3]); - mb(); - if (signal_event(ev) != 0) - return; - - while (return_stuff.xDone != 1) - udelay(10); - if (return_stuff.xRc == 0) - memcpy(buffer, pages[0], size); - kfree(pages[0]); - kfree(pages[1]); - kfree(pages[2]); - kfree(pages[3]); -} -#endif - static int mf_src_proc_show(struct seq_file *m, void *v) { -#if 0 - int len; - - mf_getSrcHistory(page, count); - len = count; - len -= off; - if (len < count) { - *eof = 1; - if (len <= 0) - return 0; - } else - len = count; - *start = page + off; - return len; -#else return 0; -#endif } static int mf_src_proc_open(struct inode *inode, struct file *file) diff --git a/arch/powerpc/platforms/pasemi/iommu.c b/arch/powerpc/platforms/pasemi/iommu.c index 1f9fb2c5776..14943ef0191 100644 --- a/arch/powerpc/platforms/pasemi/iommu.c +++ b/arch/powerpc/platforms/pasemi/iommu.c @@ -156,20 +156,12 @@ static void iommu_table_iobmap_setup(void) static void pci_dma_bus_setup_pasemi(struct pci_bus *bus) { - struct device_node *dn; - pr_debug("pci_dma_bus_setup, bus %p, bus->self %p\n", bus, bus->self); if (!iommu_table_iobmap_inited) { iommu_table_iobmap_inited = 1; iommu_table_iobmap_setup(); } - - dn = pci_bus_to_OF_node(bus); - - if (dn) - PCI_DN(dn)->iommu_table = &iommu_table_iobmap; - } @@ -192,9 +184,6 @@ static void pci_dma_dev_setup_pasemi(struct pci_dev *dev) set_iommu_table_base(&dev->dev, &iommu_table_iobmap); } -static void pci_dma_bus_setup_null(struct pci_bus *b) { } -static void pci_dma_dev_setup_null(struct pci_dev *d) { } - int __init iob_init(struct device_node *dn) { unsigned long tmp; @@ -251,14 +240,8 @@ void __init iommu_init_early_pasemi(void) iommu_off = of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL); #endif - if (iommu_off) { - /* Direct I/O, IOMMU off */ - ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_null; - ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_null; - set_pci_dma_ops(&dma_direct_ops); - + if (iommu_off) return; - } iob_init(NULL); diff --git a/arch/powerpc/platforms/powermac/setup.c b/arch/powerpc/platforms/powermac/setup.c index 9deb274841f..d5aceb7fb12 100644 --- a/arch/powerpc/platforms/powermac/setup.c +++ b/arch/powerpc/platforms/powermac/setup.c @@ -506,6 +506,15 @@ static int __init pmac_declare_of_platform_devices(void) of_platform_device_create(np, "smu", NULL); of_node_put(np); } + np = of_find_node_by_type(NULL, "fcu"); + if (np == NULL) { + /* Some machines have strangely broken device-tree */ + np = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/fan@15e"); + } + if (np) { + of_platform_device_create(np, "temperature", NULL); + of_node_put(np); + } return 0; } diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig index 3139814f643..5d1b743dbe7 100644 --- a/arch/powerpc/platforms/pseries/Kconfig +++ b/arch/powerpc/platforms/pseries/Kconfig @@ -33,6 +33,16 @@ config PSERIES_MSI depends on PCI_MSI && EEH default y +config PSERIES_ENERGY + tristate "pSeries energy management capabilities driver" + depends on PPC_PSERIES + default y + help + Provides interface to platform energy management capabilities + on supported PSERIES platforms. + Provides: /sys/devices/system/cpu/pseries_(de)activation_hint_list + and /sys/devices/system/cpu/cpuN/pseries_(de)activation_hint + config SCANLOG tristate "Scanlog dump interface" depends on RTAS_PROC && PPC_PSERIES diff --git a/arch/powerpc/platforms/pseries/Makefile b/arch/powerpc/platforms/pseries/Makefile index 59eb8bdaa79..fc5237810ec 100644 --- a/arch/powerpc/platforms/pseries/Makefile +++ b/arch/powerpc/platforms/pseries/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_EEH) += eeh.o eeh_cache.o eeh_driver.o eeh_event.o eeh_sysfs.o obj-$(CONFIG_KEXEC) += kexec.o obj-$(CONFIG_PCI) += pci.o pci_dlpar.o obj-$(CONFIG_PSERIES_MSI) += msi.o +obj-$(CONFIG_PSERIES_ENERGY) += pseries_energy.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug-cpu.o obj-$(CONFIG_MEMORY_HOTPLUG) += hotplug-memory.o diff --git a/arch/powerpc/platforms/pseries/eeh_sysfs.c b/arch/powerpc/platforms/pseries/eeh_sysfs.c index 15e13b56890..23982c7892d 100644 --- a/arch/powerpc/platforms/pseries/eeh_sysfs.c +++ b/arch/powerpc/platforms/pseries/eeh_sysfs.c @@ -25,7 +25,6 @@ #include <linux/pci.h> #include <asm/ppc-pci.h> #include <asm/pci-bridge.h> -#include <linux/kobject.h> /** * EEH_SHOW_ATTR -- create sysfs entry for eeh statistic diff --git a/arch/powerpc/platforms/pseries/firmware.c b/arch/powerpc/platforms/pseries/firmware.c index 0a14d8cd314..0b0eff0cce3 100644 --- a/arch/powerpc/platforms/pseries/firmware.c +++ b/arch/powerpc/platforms/pseries/firmware.c @@ -55,6 +55,7 @@ firmware_features_table[FIRMWARE_MAX_FEATURES] = { {FW_FEATURE_XDABR, "hcall-xdabr"}, {FW_FEATURE_MULTITCE, "hcall-multi-tce"}, {FW_FEATURE_SPLPAR, "hcall-splpar"}, + {FW_FEATURE_VPHN, "hcall-vphn"}, }; /* Build up the firmware features bitmask using the contents of diff --git a/arch/powerpc/platforms/pseries/hvCall.S b/arch/powerpc/platforms/pseries/hvCall.S index 48d20573e4d..fd05fdee576 100644 --- a/arch/powerpc/platforms/pseries/hvCall.S +++ b/arch/powerpc/platforms/pseries/hvCall.S @@ -11,6 +11,7 @@ #include <asm/processor.h> #include <asm/ppc_asm.h> #include <asm/asm-offsets.h> +#include <asm/ptrace.h> #define STK_PARM(i) (48 + ((i)-3)*8) diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c index a77bcaed80a..edea60b7ee9 100644 --- a/arch/powerpc/platforms/pseries/iommu.c +++ b/arch/powerpc/platforms/pseries/iommu.c @@ -140,7 +140,7 @@ static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum, return ret; } -static DEFINE_PER_CPU(u64 *, tce_page) = NULL; +static DEFINE_PER_CPU(u64 *, tce_page); static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages, unsigned long uaddr, @@ -323,14 +323,13 @@ static void iommu_table_setparms(struct pci_controller *phb, static void iommu_table_setparms_lpar(struct pci_controller *phb, struct device_node *dn, struct iommu_table *tbl, - const void *dma_window, - int bussubno) + const void *dma_window) { unsigned long offset, size; - tbl->it_busno = bussubno; of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size); + tbl->it_busno = phb->bus->number; tbl->it_base = 0; tbl->it_blocksize = 16; tbl->it_type = TCE_PCI; @@ -450,14 +449,10 @@ static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus) if (!ppci->iommu_table) { tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, ppci->phb->node); - iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window, - bus->number); + iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window); ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node); pr_debug(" created table: %p\n", ppci->iommu_table); } - - if (pdn != dn) - PCI_DN(dn)->iommu_table = ppci->iommu_table; } @@ -533,21 +528,11 @@ static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev) } pr_debug(" parent is %s\n", pdn->full_name); - /* Check for parent == NULL so we don't try to setup the empty EADS - * slots on POWER4 machines. - */ - if (dma_window == NULL || pdn->parent == NULL) { - pr_debug(" no dma window for device, linking to parent\n"); - set_iommu_table_base(&dev->dev, PCI_DN(pdn)->iommu_table); - return; - } - pci = PCI_DN(pdn); if (!pci->iommu_table) { tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, pci->phb->node); - iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window, - pci->phb->bus->number); + iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window); pci->iommu_table = iommu_init_table(tbl, pci->phb->node); pr_debug(" created table: %p\n", pci->iommu_table); } else { @@ -571,8 +556,7 @@ static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long acti switch (action) { case PSERIES_RECONFIG_REMOVE: - if (pci && pci->iommu_table && - of_get_property(np, "ibm,dma-window", NULL)) + if (pci && pci->iommu_table) iommu_free_table(pci->iommu_table, np->full_name); break; default: @@ -589,13 +573,8 @@ static struct notifier_block iommu_reconfig_nb = { /* These are called very early. */ void iommu_init_early_pSeries(void) { - if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL)) { - /* Direct I/O, IOMMU off */ - ppc_md.pci_dma_dev_setup = NULL; - ppc_md.pci_dma_bus_setup = NULL; - set_pci_dma_ops(&dma_direct_ops); + if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL)) return; - } if (firmware_has_feature(FW_FEATURE_LPAR)) { if (firmware_has_feature(FW_FEATURE_MULTITCE)) { @@ -622,3 +601,17 @@ void iommu_init_early_pSeries(void) set_pci_dma_ops(&dma_iommu_ops); } +static int __init disable_multitce(char *str) +{ + if (strcmp(str, "off") == 0 && + firmware_has_feature(FW_FEATURE_LPAR) && + firmware_has_feature(FW_FEATURE_MULTITCE)) { + printk(KERN_INFO "Disabling MULTITCE firmware feature\n"); + ppc_md.tce_build = tce_build_pSeriesLP; + ppc_md.tce_free = tce_free_pSeriesLP; + powerpc_firmware_features &= ~FW_FEATURE_MULTITCE; + } + return 1; +} + +__setup("multitce=", disable_multitce); diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c index f129040d974..5d3ea9f60dd 100644 --- a/arch/powerpc/platforms/pseries/lpar.c +++ b/arch/powerpc/platforms/pseries/lpar.c @@ -627,6 +627,18 @@ static void pSeries_lpar_flush_hash_range(unsigned long number, int local) spin_unlock_irqrestore(&pSeries_lpar_tlbie_lock, flags); } +static int __init disable_bulk_remove(char *str) +{ + if (strcmp(str, "off") == 0 && + firmware_has_feature(FW_FEATURE_BULK_REMOVE)) { + printk(KERN_INFO "Disabling BULK_REMOVE firmware feature"); + powerpc_firmware_features &= ~FW_FEATURE_BULK_REMOVE; + } + return 1; +} + +__setup("bulk_remove=", disable_bulk_remove); + void __init hpte_init_lpar(void) { ppc_md.hpte_invalidate = pSeries_lpar_hpte_invalidate; diff --git a/arch/powerpc/platforms/pseries/nvram.c b/arch/powerpc/platforms/pseries/nvram.c index bc3c7f2abd7..7e828ba29bc 100644 --- a/arch/powerpc/platforms/pseries/nvram.c +++ b/arch/powerpc/platforms/pseries/nvram.c @@ -22,11 +22,25 @@ #include <asm/prom.h> #include <asm/machdep.h> +/* Max bytes to read/write in one go */ +#define NVRW_CNT 0x20 + static unsigned int nvram_size; static int nvram_fetch, nvram_store; static char nvram_buf[NVRW_CNT]; /* assume this is in the first 4GB */ static DEFINE_SPINLOCK(nvram_lock); +static long nvram_error_log_index = -1; +static long nvram_error_log_size = 0; + +struct err_log_info { + int error_type; + unsigned int seq_num; +}; +#define NVRAM_MAX_REQ 2079 +#define NVRAM_MIN_REQ 1055 + +#define NVRAM_LOG_PART_NAME "ibm,rtas-log" static ssize_t pSeries_nvram_read(char *buf, size_t count, loff_t *index) { @@ -119,6 +133,197 @@ static ssize_t pSeries_nvram_get_size(void) return nvram_size ? nvram_size : -ENODEV; } + +/* nvram_write_error_log + * + * We need to buffer the error logs into nvram to ensure that we have + * the failure information to decode. If we have a severe error there + * is no way to guarantee that the OS or the machine is in a state to + * get back to user land and write the error to disk. For example if + * the SCSI device driver causes a Machine Check by writing to a bad + * IO address, there is no way of guaranteeing that the device driver + * is in any state that is would also be able to write the error data + * captured to disk, thus we buffer it in NVRAM for analysis on the + * next boot. + * + * In NVRAM the partition containing the error log buffer will looks like: + * Header (in bytes): + * +-----------+----------+--------+------------+------------------+ + * | signature | checksum | length | name | data | + * |0 |1 |2 3|4 15|16 length-1| + * +-----------+----------+--------+------------+------------------+ + * + * The 'data' section would look like (in bytes): + * +--------------+------------+-----------------------------------+ + * | event_logged | sequence # | error log | + * |0 3|4 7|8 nvram_error_log_size-1| + * +--------------+------------+-----------------------------------+ + * + * event_logged: 0 if event has not been logged to syslog, 1 if it has + * sequence #: The unique sequence # for each event. (until it wraps) + * error log: The error log from event_scan + */ +int nvram_write_error_log(char * buff, int length, + unsigned int err_type, unsigned int error_log_cnt) +{ + int rc; + loff_t tmp_index; + struct err_log_info info; + + if (nvram_error_log_index == -1) { + return -ESPIPE; + } + + if (length > nvram_error_log_size) { + length = nvram_error_log_size; + } + + info.error_type = err_type; + info.seq_num = error_log_cnt; + + tmp_index = nvram_error_log_index; + + rc = ppc_md.nvram_write((char *)&info, sizeof(struct err_log_info), &tmp_index); + if (rc <= 0) { + printk(KERN_ERR "nvram_write_error_log: Failed nvram_write (%d)\n", rc); + return rc; + } + + rc = ppc_md.nvram_write(buff, length, &tmp_index); + if (rc <= 0) { + printk(KERN_ERR "nvram_write_error_log: Failed nvram_write (%d)\n", rc); + return rc; + } + + return 0; +} + +/* nvram_read_error_log + * + * Reads nvram for error log for at most 'length' + */ +int nvram_read_error_log(char * buff, int length, + unsigned int * err_type, unsigned int * error_log_cnt) +{ + int rc; + loff_t tmp_index; + struct err_log_info info; + + if (nvram_error_log_index == -1) + return -1; + + if (length > nvram_error_log_size) + length = nvram_error_log_size; + + tmp_index = nvram_error_log_index; + + rc = ppc_md.nvram_read((char *)&info, sizeof(struct err_log_info), &tmp_index); + if (rc <= 0) { + printk(KERN_ERR "nvram_read_error_log: Failed nvram_read (%d)\n", rc); + return rc; + } + + rc = ppc_md.nvram_read(buff, length, &tmp_index); + if (rc <= 0) { + printk(KERN_ERR "nvram_read_error_log: Failed nvram_read (%d)\n", rc); + return rc; + } + + *error_log_cnt = info.seq_num; + *err_type = info.error_type; + + return 0; +} + +/* This doesn't actually zero anything, but it sets the event_logged + * word to tell that this event is safely in syslog. + */ +int nvram_clear_error_log(void) +{ + loff_t tmp_index; + int clear_word = ERR_FLAG_ALREADY_LOGGED; + int rc; + + if (nvram_error_log_index == -1) + return -1; + + tmp_index = nvram_error_log_index; + + rc = ppc_md.nvram_write((char *)&clear_word, sizeof(int), &tmp_index); + if (rc <= 0) { + printk(KERN_ERR "nvram_clear_error_log: Failed nvram_write (%d)\n", rc); + return rc; + } + + return 0; +} + +/* pseries_nvram_init_log_partition + * + * This will setup the partition we need for buffering the + * error logs and cleanup partitions if needed. + * + * The general strategy is the following: + * 1.) If there is log partition large enough then use it. + * 2.) If there is none large enough, search + * for a free partition that is large enough. + * 3.) If there is not a free partition large enough remove + * _all_ OS partitions and consolidate the space. + * 4.) Will first try getting a chunk that will satisfy the maximum + * error log size (NVRAM_MAX_REQ). + * 5.) If the max chunk cannot be allocated then try finding a chunk + * that will satisfy the minum needed (NVRAM_MIN_REQ). + */ +static int __init pseries_nvram_init_log_partition(void) +{ + loff_t p; + int size; + + /* Scan nvram for partitions */ + nvram_scan_partitions(); + + /* Lookg for ours */ + p = nvram_find_partition(NVRAM_LOG_PART_NAME, NVRAM_SIG_OS, &size); + + /* Found one but too small, remove it */ + if (p && size < NVRAM_MIN_REQ) { + pr_info("nvram: Found too small "NVRAM_LOG_PART_NAME" partition" + ",removing it..."); + nvram_remove_partition(NVRAM_LOG_PART_NAME, NVRAM_SIG_OS); + p = 0; + } + + /* Create one if we didn't find */ + if (!p) { + p = nvram_create_partition(NVRAM_LOG_PART_NAME, NVRAM_SIG_OS, + NVRAM_MAX_REQ, NVRAM_MIN_REQ); + /* No room for it, try to get rid of any OS partition + * and try again + */ + if (p == -ENOSPC) { + pr_info("nvram: No room to create "NVRAM_LOG_PART_NAME + " partition, deleting all OS partitions..."); + nvram_remove_partition(NULL, NVRAM_SIG_OS); + p = nvram_create_partition(NVRAM_LOG_PART_NAME, + NVRAM_SIG_OS, NVRAM_MAX_REQ, + NVRAM_MIN_REQ); + } + } + + if (p <= 0) { + pr_err("nvram: Failed to find or create "NVRAM_LOG_PART_NAME + " partition, err %d\n", (int)p); + return 0; + } + + nvram_error_log_index = p; + nvram_error_log_size = nvram_get_partition_size(p) - + sizeof(struct err_log_info); + + return 0; +} +machine_arch_initcall(pseries, pseries_nvram_init_log_partition); + int __init pSeries_nvram_init(void) { struct device_node *nvram; diff --git a/arch/powerpc/platforms/pseries/pseries_energy.c b/arch/powerpc/platforms/pseries/pseries_energy.c new file mode 100644 index 00000000000..c8b3c69fe89 --- /dev/null +++ b/arch/powerpc/platforms/pseries/pseries_energy.c @@ -0,0 +1,326 @@ +/* + * POWER platform energy management driver + * Copyright (C) 2010 IBM Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This pseries platform device driver provides access to + * platform energy management capabilities. + */ + +#include <linux/module.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/seq_file.h> +#include <linux/sysdev.h> +#include <linux/cpu.h> +#include <linux/of.h> +#include <asm/cputhreads.h> +#include <asm/page.h> +#include <asm/hvcall.h> + + +#define MODULE_VERS "1.0" +#define MODULE_NAME "pseries_energy" + +/* Driver flags */ + +static int sysfs_entries; + +/* Helper routines */ + +/* + * Routine to detect firmware support for hcall + * return 1 if H_BEST_ENERGY is supported + * else return 0 + */ + +static int check_for_h_best_energy(void) +{ + struct device_node *rtas = NULL; + const char *hypertas, *s; + int length; + int rc = 0; + + rtas = of_find_node_by_path("/rtas"); + if (!rtas) + return 0; + + hypertas = of_get_property(rtas, "ibm,hypertas-functions", &length); + if (!hypertas) { + of_node_put(rtas); + return 0; + } + + /* hypertas will have list of strings with hcall names */ + for (s = hypertas; s < hypertas + length; s += strlen(s) + 1) { + if (!strncmp("hcall-best-energy-1", s, 19)) { + rc = 1; /* Found the string */ + break; + } + } + of_node_put(rtas); + return rc; +} + +/* Helper Routines to convert between drc_index to cpu numbers */ + +static u32 cpu_to_drc_index(int cpu) +{ + struct device_node *dn = NULL; + const int *indexes; + int i; + int rc = 1; + u32 ret = 0; + + dn = of_find_node_by_path("/cpus"); + if (dn == NULL) + goto err; + indexes = of_get_property(dn, "ibm,drc-indexes", NULL); + if (indexes == NULL) + goto err_of_node_put; + /* Convert logical cpu number to core number */ + i = cpu_core_index_of_thread(cpu); + /* + * The first element indexes[0] is the number of drc_indexes + * returned in the list. Hence i+1 will get the drc_index + * corresponding to core number i. + */ + WARN_ON(i > indexes[0]); + ret = indexes[i + 1]; + rc = 0; + +err_of_node_put: + of_node_put(dn); +err: + if (rc) + printk(KERN_WARNING "cpu_to_drc_index(%d) failed", cpu); + return ret; +} + +static int drc_index_to_cpu(u32 drc_index) +{ + struct device_node *dn = NULL; + const int *indexes; + int i, cpu = 0; + int rc = 1; + + dn = of_find_node_by_path("/cpus"); + if (dn == NULL) + goto err; + indexes = of_get_property(dn, "ibm,drc-indexes", NULL); + if (indexes == NULL) + goto err_of_node_put; + /* + * First element in the array is the number of drc_indexes + * returned. Search through the list to find the matching + * drc_index and get the core number + */ + for (i = 0; i < indexes[0]; i++) { + if (indexes[i + 1] == drc_index) + break; + } + /* Convert core number to logical cpu number */ + cpu = cpu_first_thread_of_core(i); + rc = 0; + +err_of_node_put: + of_node_put(dn); +err: + if (rc) + printk(KERN_WARNING "drc_index_to_cpu(%d) failed", drc_index); + return cpu; +} + +/* + * pseries hypervisor call H_BEST_ENERGY provides hints to OS on + * preferred logical cpus to activate or deactivate for optimized + * energy consumption. + */ + +#define FLAGS_MODE1 0x004E200000080E01 +#define FLAGS_MODE2 0x004E200000080401 +#define FLAGS_ACTIVATE 0x100 + +static ssize_t get_best_energy_list(char *page, int activate) +{ + int rc, cnt, i, cpu; + unsigned long retbuf[PLPAR_HCALL9_BUFSIZE]; + unsigned long flags = 0; + u32 *buf_page; + char *s = page; + + buf_page = (u32 *) get_zeroed_page(GFP_KERNEL); + if (!buf_page) + return -ENOMEM; + + flags = FLAGS_MODE1; + if (activate) + flags |= FLAGS_ACTIVATE; + + rc = plpar_hcall9(H_BEST_ENERGY, retbuf, flags, 0, __pa(buf_page), + 0, 0, 0, 0, 0, 0); + if (rc != H_SUCCESS) { + free_page((unsigned long) buf_page); + return -EINVAL; + } + + cnt = retbuf[0]; + for (i = 0; i < cnt; i++) { + cpu = drc_index_to_cpu(buf_page[2*i+1]); + if ((cpu_online(cpu) && !activate) || + (!cpu_online(cpu) && activate)) + s += sprintf(s, "%d,", cpu); + } + if (s > page) { /* Something to show */ + s--; /* Suppress last comma */ + s += sprintf(s, "\n"); + } + + free_page((unsigned long) buf_page); + return s-page; +} + +static ssize_t get_best_energy_data(struct sys_device *dev, + char *page, int activate) +{ + int rc; + unsigned long retbuf[PLPAR_HCALL9_BUFSIZE]; + unsigned long flags = 0; + + flags = FLAGS_MODE2; + if (activate) + flags |= FLAGS_ACTIVATE; + + rc = plpar_hcall9(H_BEST_ENERGY, retbuf, flags, + cpu_to_drc_index(dev->id), + 0, 0, 0, 0, 0, 0, 0); + + if (rc != H_SUCCESS) + return -EINVAL; + + return sprintf(page, "%lu\n", retbuf[1] >> 32); +} + +/* Wrapper functions */ + +static ssize_t cpu_activate_hint_list_show(struct sysdev_class *class, + struct sysdev_class_attribute *attr, char *page) +{ + return get_best_energy_list(page, 1); +} + +static ssize_t cpu_deactivate_hint_list_show(struct sysdev_class *class, + struct sysdev_class_attribute *attr, char *page) +{ + return get_best_energy_list(page, 0); +} + +static ssize_t percpu_activate_hint_show(struct sys_device *dev, + struct sysdev_attribute *attr, char *page) +{ + return get_best_energy_data(dev, page, 1); +} + +static ssize_t percpu_deactivate_hint_show(struct sys_device *dev, + struct sysdev_attribute *attr, char *page) +{ + return get_best_energy_data(dev, page, 0); +} + +/* + * Create sysfs interface: + * /sys/devices/system/cpu/pseries_activate_hint_list + * /sys/devices/system/cpu/pseries_deactivate_hint_list + * Comma separated list of cpus to activate or deactivate + * /sys/devices/system/cpu/cpuN/pseries_activate_hint + * /sys/devices/system/cpu/cpuN/pseries_deactivate_hint + * Per-cpu value of the hint + */ + +struct sysdev_class_attribute attr_cpu_activate_hint_list = + _SYSDEV_CLASS_ATTR(pseries_activate_hint_list, 0444, + cpu_activate_hint_list_show, NULL); + +struct sysdev_class_attribute attr_cpu_deactivate_hint_list = + _SYSDEV_CLASS_ATTR(pseries_deactivate_hint_list, 0444, + cpu_deactivate_hint_list_show, NULL); + +struct sysdev_attribute attr_percpu_activate_hint = + _SYSDEV_ATTR(pseries_activate_hint, 0444, + percpu_activate_hint_show, NULL); + +struct sysdev_attribute attr_percpu_deactivate_hint = + _SYSDEV_ATTR(pseries_deactivate_hint, 0444, + percpu_deactivate_hint_show, NULL); + +static int __init pseries_energy_init(void) +{ + int cpu, err; + struct sys_device *cpu_sys_dev; + + if (!check_for_h_best_energy()) { + printk(KERN_INFO "Hypercall H_BEST_ENERGY not supported\n"); + return 0; + } + /* Create the sysfs files */ + err = sysfs_create_file(&cpu_sysdev_class.kset.kobj, + &attr_cpu_activate_hint_list.attr); + if (!err) + err = sysfs_create_file(&cpu_sysdev_class.kset.kobj, + &attr_cpu_deactivate_hint_list.attr); + + if (err) + return err; + for_each_possible_cpu(cpu) { + cpu_sys_dev = get_cpu_sysdev(cpu); + err = sysfs_create_file(&cpu_sys_dev->kobj, + &attr_percpu_activate_hint.attr); + if (err) + break; + err = sysfs_create_file(&cpu_sys_dev->kobj, + &attr_percpu_deactivate_hint.attr); + if (err) + break; + } + + if (err) + return err; + + sysfs_entries = 1; /* Removed entries on cleanup */ + return 0; + +} + +static void __exit pseries_energy_cleanup(void) +{ + int cpu; + struct sys_device *cpu_sys_dev; + + if (!sysfs_entries) + return; + + /* Remove the sysfs files */ + sysfs_remove_file(&cpu_sysdev_class.kset.kobj, + &attr_cpu_activate_hint_list.attr); + + sysfs_remove_file(&cpu_sysdev_class.kset.kobj, + &attr_cpu_deactivate_hint_list.attr); + + for_each_possible_cpu(cpu) { + cpu_sys_dev = get_cpu_sysdev(cpu); + sysfs_remove_file(&cpu_sys_dev->kobj, + &attr_percpu_activate_hint.attr); + sysfs_remove_file(&cpu_sys_dev->kobj, + &attr_percpu_deactivate_hint.attr); + } +} + +module_init(pseries_energy_init); +module_exit(pseries_energy_cleanup); +MODULE_DESCRIPTION("Driver for pSeries platform energy management"); +MODULE_AUTHOR("Vaidyanathan Srinivasan"); +MODULE_LICENSE("GPL"); diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile index 0bef9dacb64..9c297347914 100644 --- a/arch/powerpc/sysdev/Makefile +++ b/arch/powerpc/sysdev/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_OF_RTC) += of_rtc.o ifeq ($(CONFIG_PCI),y) obj-$(CONFIG_4xx) += ppc4xx_pci.o endif +obj-$(CONFIG_PPC4xx_CPM) += ppc4xx_cpm.o obj-$(CONFIG_PPC4xx_GPIO) += ppc4xx_gpio.o obj-$(CONFIG_CPM) += cpm_common.o diff --git a/arch/powerpc/sysdev/dart_iommu.c b/arch/powerpc/sysdev/dart_iommu.c index 17cf15ec38b..8e9e06a7ca5 100644 --- a/arch/powerpc/sysdev/dart_iommu.c +++ b/arch/powerpc/sysdev/dart_iommu.c @@ -312,17 +312,10 @@ static void pci_dma_dev_setup_dart(struct pci_dev *dev) static void pci_dma_bus_setup_dart(struct pci_bus *bus) { - struct device_node *dn; - if (!iommu_table_dart_inited) { iommu_table_dart_inited = 1; iommu_table_dart_setup(); } - - dn = pci_bus_to_OF_node(bus); - - if (dn) - PCI_DN(dn)->iommu_table = &iommu_table_dart; } static bool dart_device_on_pcie(struct device *dev) @@ -373,7 +366,7 @@ void __init iommu_init_early_dart(void) if (dn == NULL) { dn = of_find_compatible_node(NULL, "dart", "u4-dart"); if (dn == NULL) - goto bail; + return; /* use default direct_dma_ops */ dart_is_u4 = 1; } diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c index 9725369d432..9f99bef2ade 100644 --- a/arch/powerpc/sysdev/fsl_rio.c +++ b/arch/powerpc/sysdev/fsl_rio.c @@ -973,7 +973,6 @@ fsl_rio_dbell_handler(int irq, void *dev_instance) if (dsr & DOORBELL_DSR_QFI) { pr_info("RIO: doorbell queue full\n"); out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI); - goto out; } /* XXX Need to check/dispatch until queue empty */ diff --git a/arch/powerpc/sysdev/mpc8xxx_gpio.c b/arch/powerpc/sysdev/mpc8xxx_gpio.c index c0ea05e87f1..c48cd817807 100644 --- a/arch/powerpc/sysdev/mpc8xxx_gpio.c +++ b/arch/powerpc/sysdev/mpc8xxx_gpio.c @@ -1,5 +1,5 @@ /* - * GPIOs on MPC8349/8572/8610 and compatible + * GPIOs on MPC512x/8349/8572/8610 and compatible * * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk> * @@ -26,6 +26,7 @@ #define GPIO_IER 0x0c #define GPIO_IMR 0x10 #define GPIO_ICR 0x14 +#define GPIO_ICR2 0x18 struct mpc8xxx_gpio_chip { struct of_mm_gpio_chip mm_gc; @@ -37,6 +38,7 @@ struct mpc8xxx_gpio_chip { */ u32 data; struct irq_host *irq; + void *of_dev_id_data; }; static inline u32 mpc8xxx_gpio2mask(unsigned int gpio) @@ -215,6 +217,51 @@ static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type) return 0; } +static int mpc512x_irq_set_type(unsigned int virq, unsigned int flow_type) +{ + struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq); + struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; + unsigned long gpio = virq_to_hw(virq); + void __iomem *reg; + unsigned int shift; + unsigned long flags; + + if (gpio < 16) { + reg = mm->regs + GPIO_ICR; + shift = (15 - gpio) * 2; + } else { + reg = mm->regs + GPIO_ICR2; + shift = (15 - (gpio % 16)) * 2; + } + + switch (flow_type) { + case IRQ_TYPE_EDGE_FALLING: + case IRQ_TYPE_LEVEL_LOW: + spin_lock_irqsave(&mpc8xxx_gc->lock, flags); + clrsetbits_be32(reg, 3 << shift, 2 << shift); + spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); + break; + + case IRQ_TYPE_EDGE_RISING: + case IRQ_TYPE_LEVEL_HIGH: + spin_lock_irqsave(&mpc8xxx_gc->lock, flags); + clrsetbits_be32(reg, 3 << shift, 1 << shift); + spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); + break; + + case IRQ_TYPE_EDGE_BOTH: + spin_lock_irqsave(&mpc8xxx_gc->lock, flags); + clrbits32(reg, 3 << shift); + spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); + break; + + default: + return -EINVAL; + } + + return 0; +} + static struct irq_chip mpc8xxx_irq_chip = { .name = "mpc8xxx-gpio", .unmask = mpc8xxx_irq_unmask, @@ -226,6 +273,11 @@ static struct irq_chip mpc8xxx_irq_chip = { static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { + struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data; + + if (mpc8xxx_gc->of_dev_id_data) + mpc8xxx_irq_chip.set_type = mpc8xxx_gc->of_dev_id_data; + set_irq_chip_data(virq, h->host_data); set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq); set_irq_type(virq, IRQ_TYPE_NONE); @@ -253,11 +305,20 @@ static struct irq_host_ops mpc8xxx_gpio_irq_ops = { .xlate = mpc8xxx_gpio_irq_xlate, }; +static struct of_device_id mpc8xxx_gpio_ids[] __initdata = { + { .compatible = "fsl,mpc8349-gpio", }, + { .compatible = "fsl,mpc8572-gpio", }, + { .compatible = "fsl,mpc8610-gpio", }, + { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, }, + {} +}; + static void __init mpc8xxx_add_controller(struct device_node *np) { struct mpc8xxx_gpio_chip *mpc8xxx_gc; struct of_mm_gpio_chip *mm_gc; struct gpio_chip *gc; + const struct of_device_id *id; unsigned hwirq; int ret; @@ -297,6 +358,10 @@ static void __init mpc8xxx_add_controller(struct device_node *np) if (!mpc8xxx_gc->irq) goto skip_irq; + id = of_match_node(mpc8xxx_gpio_ids, np); + if (id) + mpc8xxx_gc->of_dev_id_data = id->data; + mpc8xxx_gc->irq->host_data = mpc8xxx_gc; /* ack and mask all irqs */ @@ -321,13 +386,7 @@ static int __init mpc8xxx_add_gpiochips(void) { struct device_node *np; - for_each_compatible_node(np, NULL, "fsl,mpc8349-gpio") - mpc8xxx_add_controller(np); - - for_each_compatible_node(np, NULL, "fsl,mpc8572-gpio") - mpc8xxx_add_controller(np); - - for_each_compatible_node(np, NULL, "fsl,mpc8610-gpio") + for_each_matching_node(np, mpc8xxx_gpio_ids) mpc8xxx_add_controller(np); for_each_compatible_node(np, NULL, "fsl,qoriq-gpio") diff --git a/arch/powerpc/sysdev/mv64x60_dev.c b/arch/powerpc/sysdev/mv64x60_dev.c index 1398bc45499..feaee402e2d 100644 --- a/arch/powerpc/sysdev/mv64x60_dev.c +++ b/arch/powerpc/sysdev/mv64x60_dev.c @@ -16,6 +16,7 @@ #include <linux/mv643xx.h> #include <linux/platform_device.h> #include <linux/of_platform.h> +#include <linux/of_net.h> #include <linux/dma-mapping.h> #include <asm/prom.h> diff --git a/arch/powerpc/sysdev/ppc4xx_cpm.c b/arch/powerpc/sysdev/ppc4xx_cpm.c new file mode 100644 index 00000000000..73b86cc5ea7 --- /dev/null +++ b/arch/powerpc/sysdev/ppc4xx_cpm.c @@ -0,0 +1,346 @@ +/* + * PowerPC 4xx Clock and Power Management + * + * Copyright (C) 2010, Applied Micro Circuits Corporation + * Victor Gallardo (vgallardo@apm.com) + * + * Based on arch/powerpc/platforms/44x/idle.c: + * Jerone Young <jyoung5@us.ibm.com> + * Copyright 2008 IBM Corp. + * + * Based on arch/powerpc/sysdev/fsl_pmc.c: + * Anton Vorontsov <avorontsov@ru.mvista.com> + * Copyright 2009 MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <linux/kernel.h> +#include <linux/of_platform.h> +#include <linux/sysfs.h> +#include <linux/cpu.h> +#include <linux/suspend.h> +#include <asm/dcr.h> +#include <asm/dcr-native.h> +#include <asm/machdep.h> + +#define CPM_ER 0 +#define CPM_FR 1 +#define CPM_SR 2 + +#define CPM_IDLE_WAIT 0 +#define CPM_IDLE_DOZE 1 + +struct cpm { + dcr_host_t dcr_host; + unsigned int dcr_offset[3]; + unsigned int powersave_off; + unsigned int unused; + unsigned int idle_doze; + unsigned int standby; + unsigned int suspend; +}; + +static struct cpm cpm; + +struct cpm_idle_mode { + unsigned int enabled; + const char *name; +}; + +static struct cpm_idle_mode idle_mode[] = { + [CPM_IDLE_WAIT] = { 1, "wait" }, /* default */ + [CPM_IDLE_DOZE] = { 0, "doze" }, +}; + +static unsigned int cpm_set(unsigned int cpm_reg, unsigned int mask) +{ + unsigned int value; + + /* CPM controller supports 3 different types of sleep interface + * known as class 1, 2 and 3. For class 1 units, they are + * unconditionally put to sleep when the corresponding CPM bit is + * set. For class 2 and 3 units this is not case; if they can be + * put to to sleep, they will. Here we do not verify, we just + * set them and expect them to eventually go off when they can. + */ + value = dcr_read(cpm.dcr_host, cpm.dcr_offset[cpm_reg]); + dcr_write(cpm.dcr_host, cpm.dcr_offset[cpm_reg], value | mask); + + /* return old state, to restore later if needed */ + return value; +} + +static void cpm_idle_wait(void) +{ + unsigned long msr_save; + + /* save off initial state */ + msr_save = mfmsr(); + /* sync required when CPM0_ER[CPU] is set */ + mb(); + /* set wait state MSR */ + mtmsr(msr_save|MSR_WE|MSR_EE|MSR_CE|MSR_DE); + isync(); + /* return to initial state */ + mtmsr(msr_save); + isync(); +} + +static void cpm_idle_sleep(unsigned int mask) +{ + unsigned int er_save; + + /* update CPM_ER state */ + er_save = cpm_set(CPM_ER, mask); + + /* go to wait state so that CPM0_ER[CPU] can take effect */ + cpm_idle_wait(); + + /* restore CPM_ER state */ + dcr_write(cpm.dcr_host, cpm.dcr_offset[CPM_ER], er_save); +} + +static void cpm_idle_doze(void) +{ + cpm_idle_sleep(cpm.idle_doze); +} + +static void cpm_idle_config(int mode) +{ + int i; + + if (idle_mode[mode].enabled) + return; + + for (i = 0; i < ARRAY_SIZE(idle_mode); i++) + idle_mode[i].enabled = 0; + + idle_mode[mode].enabled = 1; +} + +static ssize_t cpm_idle_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + char *s = buf; + int i; + + for (i = 0; i < ARRAY_SIZE(idle_mode); i++) { + if (idle_mode[i].enabled) + s += sprintf(s, "[%s] ", idle_mode[i].name); + else + s += sprintf(s, "%s ", idle_mode[i].name); + } + + *(s-1) = '\n'; /* convert the last space to a newline */ + + return s - buf; +} + +static ssize_t cpm_idle_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + int i; + char *p; + int len; + + p = memchr(buf, '\n', n); + len = p ? p - buf : n; + + for (i = 0; i < ARRAY_SIZE(idle_mode); i++) { + if (strncmp(buf, idle_mode[i].name, len) == 0) { + cpm_idle_config(i); + return n; + } + } + + return -EINVAL; +} + +static struct kobj_attribute cpm_idle_attr = + __ATTR(idle, 0644, cpm_idle_show, cpm_idle_store); + +static void cpm_idle_config_sysfs(void) +{ + struct sys_device *sys_dev; + unsigned long ret; + + sys_dev = get_cpu_sysdev(0); + + ret = sysfs_create_file(&sys_dev->kobj, + &cpm_idle_attr.attr); + if (ret) + printk(KERN_WARNING + "cpm: failed to create idle sysfs entry\n"); +} + +static void cpm_idle(void) +{ + if (idle_mode[CPM_IDLE_DOZE].enabled) + cpm_idle_doze(); + else + cpm_idle_wait(); +} + +static int cpm_suspend_valid(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_STANDBY: + return !!cpm.standby; + case PM_SUSPEND_MEM: + return !!cpm.suspend; + default: + return 0; + } +} + +static void cpm_suspend_standby(unsigned int mask) +{ + unsigned long tcr_save; + + /* disable decrement interrupt */ + tcr_save = mfspr(SPRN_TCR); + mtspr(SPRN_TCR, tcr_save & ~TCR_DIE); + + /* go to sleep state */ + cpm_idle_sleep(mask); + + /* restore decrement interrupt */ + mtspr(SPRN_TCR, tcr_save); +} + +static int cpm_suspend_enter(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_STANDBY: + cpm_suspend_standby(cpm.standby); + break; + case PM_SUSPEND_MEM: + cpm_suspend_standby(cpm.suspend); + break; + } + + return 0; +} + +static struct platform_suspend_ops cpm_suspend_ops = { + .valid = cpm_suspend_valid, + .enter = cpm_suspend_enter, +}; + +static int cpm_get_uint_property(struct device_node *np, + const char *name) +{ + int len; + const unsigned int *prop = of_get_property(np, name, &len); + + if (prop == NULL || len < sizeof(u32)) + return 0; + + return *prop; +} + +static int __init cpm_init(void) +{ + struct device_node *np; + int dcr_base, dcr_len; + int ret = 0; + + if (!cpm.powersave_off) { + cpm_idle_config(CPM_IDLE_WAIT); + ppc_md.power_save = &cpm_idle; + } + + np = of_find_compatible_node(NULL, NULL, "ibm,cpm"); + if (!np) { + ret = -EINVAL; + goto out; + } + + dcr_base = dcr_resource_start(np, 0); + dcr_len = dcr_resource_len(np, 0); + + if (dcr_base == 0 || dcr_len == 0) { + printk(KERN_ERR "cpm: could not parse dcr property for %s\n", + np->full_name); + ret = -EINVAL; + goto out; + } + + cpm.dcr_host = dcr_map(np, dcr_base, dcr_len); + + if (!DCR_MAP_OK(cpm.dcr_host)) { + printk(KERN_ERR "cpm: failed to map dcr property for %s\n", + np->full_name); + ret = -EINVAL; + goto out; + } + + /* All 4xx SoCs with a CPM controller have one of two + * different order for the CPM registers. Some have the + * CPM registers in the following order (ER,FR,SR). The + * others have them in the following order (SR,ER,FR). + */ + + if (cpm_get_uint_property(np, "er-offset") == 0) { + cpm.dcr_offset[CPM_ER] = 0; + cpm.dcr_offset[CPM_FR] = 1; + cpm.dcr_offset[CPM_SR] = 2; + } else { + cpm.dcr_offset[CPM_ER] = 1; + cpm.dcr_offset[CPM_FR] = 2; + cpm.dcr_offset[CPM_SR] = 0; + } + + /* Now let's see what IPs to turn off for the following modes */ + + cpm.unused = cpm_get_uint_property(np, "unused-units"); + cpm.idle_doze = cpm_get_uint_property(np, "idle-doze"); + cpm.standby = cpm_get_uint_property(np, "standby"); + cpm.suspend = cpm_get_uint_property(np, "suspend"); + + /* If some IPs are unused let's turn them off now */ + + if (cpm.unused) { + cpm_set(CPM_ER, cpm.unused); + cpm_set(CPM_FR, cpm.unused); + } + + /* Now let's export interfaces */ + + if (!cpm.powersave_off && cpm.idle_doze) + cpm_idle_config_sysfs(); + + if (cpm.standby || cpm.suspend) + suspend_set_ops(&cpm_suspend_ops); +out: + if (np) + of_node_put(np); + return ret; +} + +late_initcall(cpm_init); + +static int __init cpm_powersave_off(char *arg) +{ + cpm.powersave_off = 1; + return 0; +} +__setup("powersave=off", cpm_powersave_off); diff --git a/arch/powerpc/sysdev/tsi108_dev.c b/arch/powerpc/sysdev/tsi108_dev.c index d4d15aaf18f..ee056807b52 100644 --- a/arch/powerpc/sysdev/tsi108_dev.c +++ b/arch/powerpc/sysdev/tsi108_dev.c @@ -19,6 +19,7 @@ #include <linux/module.h> #include <linux/device.h> #include <linux/platform_device.h> +#include <linux/of_net.h> #include <asm/tsi108.h> #include <asm/system.h> @@ -83,8 +84,8 @@ static int __init tsi108_eth_of_init(void) memset(&tsi_eth_data, 0, sizeof(tsi_eth_data)); ret = of_address_to_resource(np, 0, &r[0]); - DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n", - __func__,r[0].name, r[0].start, r[0].end); + DBG("%s: name:start->end = %s:%pR\n", + __func__, r[0].name, &r[0]); if (ret) goto err; @@ -92,8 +93,8 @@ static int __init tsi108_eth_of_init(void) r[1].start = irq_of_parse_and_map(np, 0); r[1].end = irq_of_parse_and_map(np, 0); r[1].flags = IORESOURCE_IRQ; - DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n", - __func__,r[1].name, r[1].start, r[1].end); + DBG("%s: name:start->end = %s:%pR\n", + __func__, r[1].name, &r[1]); tsi_eth_dev = platform_device_register_simple("tsi-ethernet", i++, &r[0], diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 6c6d7b339aa..ff19efdf6fe 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -1,13 +1,8 @@ -config SCHED_MC - def_bool y - depends on SMP - config MMU def_bool y config ZONE_DMA - def_bool y - depends on 64BIT + def_bool y if 64BIT config LOCKDEP_SUPPORT def_bool y @@ -25,12 +20,10 @@ config RWSEM_XCHGADD_ALGORITHM def_bool y config ARCH_HAS_ILOG2_U32 - bool - default n + def_bool n config ARCH_HAS_ILOG2_U64 - bool - default n + def_bool n config GENERIC_HWEIGHT def_bool y @@ -42,9 +35,7 @@ config GENERIC_CLOCKEVENTS def_bool y config GENERIC_BUG - bool - depends on BUG - default y + def_bool y if BUG config GENERIC_BUG_RELATIVE_POINTERS def_bool y @@ -59,13 +50,10 @@ config ARCH_DMA_ADDR_T_64BIT def_bool 64BIT config GENERIC_LOCKBREAK - bool - default y - depends on SMP && PREEMPT + def_bool y if SMP && PREEMPT config PGSTE - bool - default y if KVM + def_bool y if KVM config VIRT_CPU_ACCOUNTING def_bool y @@ -85,7 +73,6 @@ config S390 select HAVE_DYNAMIC_FTRACE select HAVE_FUNCTION_GRAPH_TRACER select HAVE_REGS_AND_STACK_ACCESS_API - select HAVE_DEFAULT_NO_SPIN_MUTEXES select HAVE_OPROFILE select HAVE_KPROBES select HAVE_KRETPROBES @@ -130,8 +117,7 @@ config S390 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE config SCHED_OMIT_FRAME_POINTER - bool - default y + def_bool y source "init/Kconfig" @@ -144,20 +130,21 @@ comment "Processor type and features" source "kernel/time/Kconfig" config 64BIT - bool "64 bit kernel" + def_bool y + prompt "64 bit kernel" help Select this option if you have an IBM z/Architecture machine and want to use the 64 bit addressing mode. config 32BIT - bool - default y if !64BIT + def_bool y if !64BIT config KTIME_SCALAR def_bool 32BIT config SMP - bool "Symmetric multi-processing support" + def_bool y + prompt "Symmetric multi-processing support" ---help--- This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If @@ -189,10 +176,10 @@ config NR_CPUS approximately sixteen kilobytes to the kernel image. config HOTPLUG_CPU - bool "Support for hot-pluggable CPUs" + def_bool y + prompt "Support for hot-pluggable CPUs" depends on SMP select HOTPLUG - default n help Say Y here to be able to turn CPUs off and on. CPUs can be controlled through /sys/devices/system/cpu/cpu#. @@ -208,14 +195,16 @@ config SCHED_MC increased overhead in some places. config SCHED_BOOK - bool "Book scheduler support" + def_bool y + prompt "Book scheduler support" depends on SMP && SCHED_MC help Book scheduler support improves the CPU scheduler's decision making when dealing with machines that have several books. config MATHEMU - bool "IEEE FPU emulation" + def_bool y + prompt "IEEE FPU emulation" depends on MARCH_G5 help This option is required for IEEE compliant floating point arithmetic @@ -223,7 +212,8 @@ config MATHEMU need this. config COMPAT - bool "Kernel support for 31 bit emulation" + def_bool y + prompt "Kernel support for 31 bit emulation" depends on 64BIT select COMPAT_BINFMT_ELF help @@ -233,16 +223,14 @@ config COMPAT executing 31 bit applications. It is safe to say "Y". config SYSVIPC_COMPAT - bool - depends on COMPAT && SYSVIPC - default y + def_bool y if COMPAT && SYSVIPC config AUDIT_ARCH - bool - default y + def_bool y config S390_EXEC_PROTECT - bool "Data execute protection" + def_bool y + prompt "Data execute protection" help This option allows to enable a buffer overflow protection for user space programs and it also selects the addressing mode option above. @@ -302,7 +290,8 @@ config MARCH_Z196 endchoice config PACK_STACK - bool "Pack kernel stack" + def_bool y + prompt "Pack kernel stack" help This option enables the compiler option -mkernel-backchain if it is available. If the option is available the compiler supports @@ -315,7 +304,8 @@ config PACK_STACK Say Y if you are unsure. config SMALL_STACK - bool "Use 8kb for kernel stack instead of 16kb" + def_bool n + prompt "Use 8kb for kernel stack instead of 16kb" depends on PACK_STACK && 64BIT && !LOCKDEP help If you say Y here and the compiler supports the -mkernel-backchain @@ -327,7 +317,8 @@ config SMALL_STACK Say N if you are unsure. config CHECK_STACK - bool "Detect kernel stack overflow" + def_bool y + prompt "Detect kernel stack overflow" help This option enables the compiler option -mstack-guard and -mstack-size if they are available. If the compiler supports them @@ -351,7 +342,8 @@ config STACK_GUARD 512 for 64 bit. config WARN_STACK - bool "Emit compiler warnings for function with broken stack usage" + def_bool n + prompt "Emit compiler warnings for function with broken stack usage" help This option enables the compiler options -mwarn-framesize and -mwarn-dynamicstack. If the compiler supports these options it @@ -386,24 +378,24 @@ config ARCH_SPARSEMEM_DEFAULT def_bool y config ARCH_SELECT_MEMORY_MODEL - def_bool y + def_bool y config ARCH_ENABLE_MEMORY_HOTPLUG - def_bool y - depends on SPARSEMEM + def_bool y if SPARSEMEM config ARCH_ENABLE_MEMORY_HOTREMOVE def_bool y config ARCH_HIBERNATION_POSSIBLE - def_bool y if 64BIT + def_bool y if 64BIT source "mm/Kconfig" comment "I/O subsystem configuration" config QDIO - tristate "QDIO support" + def_tristate y + prompt "QDIO support" ---help--- This driver provides the Queued Direct I/O base support for IBM System z. @@ -414,7 +406,8 @@ config QDIO If unsure, say Y. config CHSC_SCH - tristate "Support for CHSC subchannels" + def_tristate y + prompt "Support for CHSC subchannels" help This driver allows usage of CHSC subchannels. A CHSC subchannel is usually present on LPAR only. @@ -432,7 +425,8 @@ config CHSC_SCH comment "Misc" config IPL - bool "Builtin IPL record support" + def_bool y + prompt "Builtin IPL record support" help If you want to use the produced kernel to IPL directly from a device, you have to merge a bootsector specific to the device @@ -464,7 +458,8 @@ config FORCE_MAX_ZONEORDER default "9" config PFAULT - bool "Pseudo page fault support" + def_bool y + prompt "Pseudo page fault support" help Select this option, if you want to use PFAULT pseudo page fault handling under VM. If running native or in LPAR, this option @@ -476,7 +471,8 @@ config PFAULT this option. config SHARED_KERNEL - bool "VM shared kernel support" + def_bool y + prompt "VM shared kernel support" help Select this option, if you want to share the text segment of the Linux kernel between different VM guests. This reduces memory @@ -487,7 +483,8 @@ config SHARED_KERNEL doing and want to exploit this feature. config CMM - tristate "Cooperative memory management" + def_tristate n + prompt "Cooperative memory management" help Select this option, if you want to enable the kernel interface to reduce the memory size of the system. This is accomplished @@ -499,14 +496,16 @@ config CMM option. config CMM_IUCV - bool "IUCV special message interface to cooperative memory management" + def_bool y + prompt "IUCV special message interface to cooperative memory management" depends on CMM && (SMSGIUCV=y || CMM=SMSGIUCV) help Select this option to enable the special message interface to the cooperative memory management. config APPLDATA_BASE - bool "Linux - VM Monitor Stream, base infrastructure" + def_bool n + prompt "Linux - VM Monitor Stream, base infrastructure" depends on PROC_FS help This provides a kernel interface for creating and updating z/VM APPLDATA @@ -521,7 +520,8 @@ config APPLDATA_BASE The /proc entries can also be read from, showing the current settings. config APPLDATA_MEM - tristate "Monitor memory management statistics" + def_tristate m + prompt "Monitor memory management statistics" depends on APPLDATA_BASE && VM_EVENT_COUNTERS help This provides memory management related data to the Linux - VM Monitor @@ -537,7 +537,8 @@ config APPLDATA_MEM appldata_mem.o. config APPLDATA_OS - tristate "Monitor OS statistics" + def_tristate m + prompt "Monitor OS statistics" depends on APPLDATA_BASE help This provides OS related data to the Linux - VM Monitor Stream, like @@ -551,7 +552,8 @@ config APPLDATA_OS appldata_os.o. config APPLDATA_NET_SUM - tristate "Monitor overall network statistics" + def_tristate m + prompt "Monitor overall network statistics" depends on APPLDATA_BASE && NET help This provides network related data to the Linux - VM Monitor Stream, @@ -568,30 +570,32 @@ config APPLDATA_NET_SUM source kernel/Kconfig.hz config S390_HYPFS_FS - bool "s390 hypervisor file system support" + def_bool y + prompt "s390 hypervisor file system support" select SYS_HYPERVISOR - default y help This is a virtual file system intended to provide accounting information in an s390 hypervisor environment. config KEXEC - bool "kexec system call" + def_bool n + prompt "kexec system call" help kexec is a system call that implements the ability to shutdown your current kernel, and to start another kernel. It is like a reboot but is independent of hardware/microcode support. config ZFCPDUMP - bool "zfcpdump support" + def_bool n + prompt "zfcpdump support" select SMP - default n help Select this option if you want to build an zfcpdump enabled kernel. Refer to <file:Documentation/s390/zfcpdump.txt> for more details on this. config S390_GUEST -bool "s390 guest support for KVM (EXPERIMENTAL)" + def_bool y + prompt "s390 guest support for KVM (EXPERIMENTAL)" depends on 64BIT && EXPERIMENTAL select VIRTIO select VIRTIO_RING @@ -603,9 +607,9 @@ bool "s390 guest support for KVM (EXPERIMENTAL)" the default console. config SECCOMP - bool "Enable seccomp to safely compute untrusted bytecode" + def_bool y + prompt "Enable seccomp to safely compute untrusted bytecode" depends on PROC_FS - default y help This kernel feature is useful for number crunching applications that may need to compute untrusted bytecode during their diff --git a/arch/s390/Kconfig.debug b/arch/s390/Kconfig.debug index 05221b13ffb..2b380df9560 100644 --- a/arch/s390/Kconfig.debug +++ b/arch/s390/Kconfig.debug @@ -1,8 +1,7 @@ menu "Kernel hacking" config TRACE_IRQFLAGS_SUPPORT - bool - default y + def_bool y source "lib/Kconfig.debug" @@ -19,7 +18,8 @@ config STRICT_DEVMEM If you are unsure, say Y. config DEBUG_STRICT_USER_COPY_CHECKS - bool "Strict user copy size checks" + def_bool n + prompt "Strict user copy size checks" ---help--- Enabling this option turns a certain set of sanity checks for user copy operations into compile time warnings. diff --git a/arch/s390/defconfig b/arch/s390/defconfig index e40ac6ee652..d79697157ac 100644 --- a/arch/s390/defconfig +++ b/arch/s390/defconfig @@ -2,16 +2,12 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_AUDIT=y +CONFIG_RCU_TRACE=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y -CONFIG_CGROUPS=y -CONFIG_CGROUP_NS=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_UTS_NS=y -CONFIG_IPC_NS=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -# CONFIG_COMPAT_BRK is not set +CONFIG_PERF_EVENTS=y CONFIG_SLAB=y CONFIG_KPROBES=y CONFIG_MODULES=y @@ -20,24 +16,12 @@ CONFIG_MODVERSIONS=y CONFIG_DEFAULT_DEADLINE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y -CONFIG_64BIT=y -CONFIG_SMP=y -CONFIG_NR_CPUS=32 -CONFIG_COMPAT=y -CONFIG_S390_EXEC_PROTECT=y -CONFIG_PACK_STACK=y -CONFIG_CHECK_STACK=y CONFIG_PREEMPT=y CONFIG_MEMORY_HOTPLUG=y CONFIG_MEMORY_HOTREMOVE=y -CONFIG_QDIO=y -CONFIG_CHSC_SCH=m -CONFIG_IPL=y CONFIG_BINFMT_MISC=m -CONFIG_PFAULT=y CONFIG_HZ_100=y CONFIG_KEXEC=y -CONFIG_S390_GUEST=y CONFIG_PM=y CONFIG_HIBERNATION=y CONFIG_PACKET=y @@ -46,16 +30,15 @@ CONFIG_NET_KEY=y CONFIG_AFIUCV=m CONFIG_INET=y CONFIG_IP_MULTICAST=y +# CONFIG_INET_LRO is not set CONFIG_IPV6=y -CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NF_CONNTRACK=m -# CONFIG_NF_CT_PROTO_SCTP is not set +CONFIG_NET_SCTPPROBE=m +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_VLAN_8021Q=y CONFIG_NET_SCHED=y CONFIG_NET_SCH_CBQ=m CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_MULTIQ=y CONFIG_NET_SCH_RED=m CONFIG_NET_SCH_SFQ=m CONFIG_NET_SCH_TEQL=m @@ -69,28 +52,14 @@ CONFIG_NET_CLS_U32=m CONFIG_CLS_U32_MARK=y CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m -CONFIG_NET_CLS_FLOW=m CONFIG_NET_CLS_ACT=y CONFIG_NET_ACT_POLICE=y -CONFIG_NET_ACT_NAT=m -CONFIG_CAN=m -CONFIG_CAN_RAW=m -CONFIG_CAN_BCM=m -CONFIG_CAN_VCAN=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FIRMWARE_IN_KERNEL is not set CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_XIP=y -CONFIG_BLK_DEV_XPRAM=m -CONFIG_DASD=y -CONFIG_DASD_PROFILE=y -CONFIG_DASD_ECKD=y -CONFIG_DASD_FBA=y -CONFIG_DASD_DIAG=y -CONFIG_DASD_EER=y -CONFIG_VIRTIO_BLK=m +CONFIG_VIRTIO_BLK=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=y @@ -102,101 +71,92 @@ CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y CONFIG_ZFCP=y -CONFIG_SCSI_DH=m -CONFIG_SCSI_DH_RDAC=m -CONFIG_SCSI_DH_HP_SW=m -CONFIG_SCSI_DH_EMC=m -CONFIG_SCSI_DH_ALUA=m -CONFIG_SCSI_OSD_INITIATOR=m -CONFIG_SCSI_OSD_ULD=m -CONFIG_MD=y -CONFIG_BLK_DEV_MD=y -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_MULTIPATH=m -CONFIG_BLK_DEV_DM=y -CONFIG_DM_CRYPT=y -CONFIG_DM_SNAPSHOT=y -CONFIG_DM_MIRROR=y -CONFIG_DM_ZERO=y -CONFIG_DM_MULTIPATH=m +CONFIG_ZFCP_DIF=y CONFIG_NETDEVICES=y CONFIG_DUMMY=m CONFIG_BONDING=m CONFIG_EQUALIZER=m CONFIG_TUN=m -CONFIG_VETH=m CONFIG_NET_ETHERNET=y -CONFIG_LCS=m -CONFIG_CTCM=m -CONFIG_QETH=y -CONFIG_QETH_L2=y -CONFIG_QETH_L3=y -CONFIG_VIRTIO_NET=m -CONFIG_HW_RANDOM_VIRTIO=m +CONFIG_VIRTIO_NET=y CONFIG_RAW_DRIVER=m -CONFIG_TN3270=y -CONFIG_TN3270_TTY=y -CONFIG_TN3270_FS=m -CONFIG_TN3270_CONSOLE=y -CONFIG_TN3215=y -CONFIG_TN3215_CONSOLE=y -CONFIG_SCLP_TTY=y -CONFIG_SCLP_CONSOLE=y -CONFIG_SCLP_VT220_TTY=y -CONFIG_SCLP_VT220_CONSOLE=y -CONFIG_SCLP_CPI=m -CONFIG_SCLP_ASYNC=m -CONFIG_S390_TAPE=m -CONFIG_S390_TAPE_BLOCK=y -CONFIG_S390_TAPE_34XX=m -CONFIG_ACCESSIBILITY=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFSD=y -CONFIG_NFSD_V3=y +# CONFIG_NETWORK_FILESYSTEMS is not set CONFIG_PARTITION_ADVANCED=y CONFIG_IBM_PARTITION=y CONFIG_DLM=m CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_MUTEXES=y +CONFIG_TIMER_STATS=y +CONFIG_PROVE_LOCKING=y +CONFIG_PROVE_RCU=y +CONFIG_LOCK_STAT=y +CONFIG_DEBUG_LOCKDEP=y CONFIG_DEBUG_SPINLOCK_SLEEP=y +CONFIG_DEBUG_LIST=y +CONFIG_DEBUG_NOTIFIERS=y # CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y +CONFIG_KPROBES_SANITY_TEST=y +CONFIG_CPU_NOTIFIER_ERROR_INJECT=m +CONFIG_LATENCYTOP=y CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_SAMPLES=y -CONFIG_CRYPTO_FIPS=y +CONFIG_DEBUG_PAGEALLOC=y +# CONFIG_FTRACE is not set +# CONFIG_STRICT_DEVMEM is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m CONFIG_CRYPTO_CCM=m CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_XCBC=m CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_RMD256=m CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_SALSA20=m CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_ZLIB=m CONFIG_CRYPTO_LZO=m CONFIG_ZCRYPT=m +CONFIG_CRYPTO_SHA1_S390=m +CONFIG_CRYPTO_SHA256_S390=m CONFIG_CRYPTO_SHA512_S390=m -CONFIG_CRC_T10DIF=y -CONFIG_CRC32=m +CONFIG_CRYPTO_DES_S390=m +CONFIG_CRYPTO_AES_S390=m CONFIG_CRC7=m -CONFIG_KVM=m -CONFIG_VIRTIO_BALLOON=m +CONFIG_VIRTIO_BALLOON=y diff --git a/arch/s390/hypfs/Makefile b/arch/s390/hypfs/Makefile index b08d2abf617..2e671d5004c 100644 --- a/arch/s390/hypfs/Makefile +++ b/arch/s390/hypfs/Makefile @@ -4,4 +4,4 @@ obj-$(CONFIG_S390_HYPFS_FS) += s390_hypfs.o -s390_hypfs-objs := inode.o hypfs_diag.o hypfs_vm.o +s390_hypfs-objs := inode.o hypfs_diag.o hypfs_vm.o hypfs_dbfs.o diff --git a/arch/s390/hypfs/hypfs.h b/arch/s390/hypfs/hypfs.h index fa487d4cc08..80c1526f2af 100644 --- a/arch/s390/hypfs/hypfs.h +++ b/arch/s390/hypfs/hypfs.h @@ -12,6 +12,8 @@ #include <linux/fs.h> #include <linux/types.h> #include <linux/debugfs.h> +#include <linux/workqueue.h> +#include <linux/kref.h> #define REG_FILE_MODE 0440 #define UPDATE_FILE_MODE 0220 @@ -38,6 +40,33 @@ extern int hypfs_vm_init(void); extern void hypfs_vm_exit(void); extern int hypfs_vm_create_files(struct super_block *sb, struct dentry *root); -/* Directory for debugfs files */ -extern struct dentry *hypfs_dbfs_dir; +/* debugfs interface */ +struct hypfs_dbfs_file; + +struct hypfs_dbfs_data { + void *buf; + void *buf_free_ptr; + size_t size; + struct hypfs_dbfs_file *dbfs_file;; + struct kref kref; +}; + +struct hypfs_dbfs_file { + const char *name; + int (*data_create)(void **data, void **data_free_ptr, + size_t *size); + void (*data_free)(const void *buf_free_ptr); + + /* Private data for hypfs_dbfs.c */ + struct hypfs_dbfs_data *data; + struct delayed_work data_free_work; + struct mutex lock; + struct dentry *dentry; +}; + +extern int hypfs_dbfs_init(void); +extern void hypfs_dbfs_exit(void); +extern int hypfs_dbfs_create_file(struct hypfs_dbfs_file *df); +extern void hypfs_dbfs_remove_file(struct hypfs_dbfs_file *df); + #endif /* _HYPFS_H_ */ diff --git a/arch/s390/hypfs/hypfs_dbfs.c b/arch/s390/hypfs/hypfs_dbfs.c new file mode 100644 index 00000000000..b478013b7fe --- /dev/null +++ b/arch/s390/hypfs/hypfs_dbfs.c @@ -0,0 +1,116 @@ +/* + * Hypervisor filesystem for Linux on s390 - debugfs interface + * + * Copyright (C) IBM Corp. 2010 + * Author(s): Michael Holzheu <holzheu@linux.vnet.ibm.com> + */ + +#include <linux/slab.h> +#include "hypfs.h" + +static struct dentry *dbfs_dir; + +static struct hypfs_dbfs_data *hypfs_dbfs_data_alloc(struct hypfs_dbfs_file *f) +{ + struct hypfs_dbfs_data *data; + + data = kmalloc(sizeof(*data), GFP_KERNEL); + if (!data) + return NULL; + kref_init(&data->kref); + data->dbfs_file = f; + return data; +} + +static void hypfs_dbfs_data_free(struct kref *kref) +{ + struct hypfs_dbfs_data *data; + + data = container_of(kref, struct hypfs_dbfs_data, kref); + data->dbfs_file->data_free(data->buf_free_ptr); + kfree(data); +} + +static void data_free_delayed(struct work_struct *work) +{ + struct hypfs_dbfs_data *data; + struct hypfs_dbfs_file *df; + + df = container_of(work, struct hypfs_dbfs_file, data_free_work.work); + mutex_lock(&df->lock); + data = df->data; + df->data = NULL; + mutex_unlock(&df->lock); + kref_put(&data->kref, hypfs_dbfs_data_free); +} + +static ssize_t dbfs_read(struct file *file, char __user *buf, + size_t size, loff_t *ppos) +{ + struct hypfs_dbfs_data *data; + struct hypfs_dbfs_file *df; + ssize_t rc; + + if (*ppos != 0) + return 0; + + df = file->f_path.dentry->d_inode->i_private; + mutex_lock(&df->lock); + if (!df->data) { + data = hypfs_dbfs_data_alloc(df); + if (!data) { + mutex_unlock(&df->lock); + return -ENOMEM; + } + rc = df->data_create(&data->buf, &data->buf_free_ptr, + &data->size); + if (rc) { + mutex_unlock(&df->lock); + kfree(data); + return rc; + } + df->data = data; + schedule_delayed_work(&df->data_free_work, HZ); + } + data = df->data; + kref_get(&data->kref); + mutex_unlock(&df->lock); + + rc = simple_read_from_buffer(buf, size, ppos, data->buf, data->size); + kref_put(&data->kref, hypfs_dbfs_data_free); + return rc; +} + +static const struct file_operations dbfs_ops = { + .read = dbfs_read, + .llseek = no_llseek, +}; + +int hypfs_dbfs_create_file(struct hypfs_dbfs_file *df) +{ + df->dentry = debugfs_create_file(df->name, 0400, dbfs_dir, df, + &dbfs_ops); + if (IS_ERR(df->dentry)) + return PTR_ERR(df->dentry); + mutex_init(&df->lock); + INIT_DELAYED_WORK(&df->data_free_work, data_free_delayed); + return 0; +} + +void hypfs_dbfs_remove_file(struct hypfs_dbfs_file *df) +{ + debugfs_remove(df->dentry); +} + +int hypfs_dbfs_init(void) +{ + dbfs_dir = debugfs_create_dir("s390_hypfs", NULL); + if (IS_ERR(dbfs_dir)) + return PTR_ERR(dbfs_dir); + return 0; +} + +void hypfs_dbfs_exit(void) +{ + debugfs_remove(dbfs_dir); +} diff --git a/arch/s390/hypfs/hypfs_diag.c b/arch/s390/hypfs/hypfs_diag.c index cd4a81be9cf..6023c6dc1fb 100644 --- a/arch/s390/hypfs/hypfs_diag.c +++ b/arch/s390/hypfs/hypfs_diag.c @@ -555,81 +555,38 @@ struct dbfs_d204 { char buf[]; /* d204 buffer */ } __attribute__ ((packed)); -struct dbfs_d204_private { - struct dbfs_d204 *d204; /* Aligned d204 data with header */ - void *base; /* Base pointer (needed for vfree) */ -}; - -static int dbfs_d204_open(struct inode *inode, struct file *file) +static int dbfs_d204_create(void **data, void **data_free_ptr, size_t *size) { - struct dbfs_d204_private *data; struct dbfs_d204 *d204; int rc, buf_size; + void *base; - data = kzalloc(sizeof(*data), GFP_KERNEL); - if (!data) - return -ENOMEM; buf_size = PAGE_SIZE * (diag204_buf_pages + 1) + sizeof(d204->hdr); - data->base = vmalloc(buf_size); - if (!data->base) { - rc = -ENOMEM; - goto fail_kfree_data; + base = vmalloc(buf_size); + if (!base) + return -ENOMEM; + memset(base, 0, buf_size); + d204 = page_align_ptr(base + sizeof(d204->hdr)) - sizeof(d204->hdr); + rc = diag204_do_store(d204->buf, diag204_buf_pages); + if (rc) { + vfree(base); + return rc; } - memset(data->base, 0, buf_size); - d204 = page_align_ptr(data->base + sizeof(d204->hdr)) - - sizeof(d204->hdr); - rc = diag204_do_store(&d204->buf, diag204_buf_pages); - if (rc) - goto fail_vfree_base; d204->hdr.version = DBFS_D204_HDR_VERSION; d204->hdr.len = PAGE_SIZE * diag204_buf_pages; d204->hdr.sc = diag204_store_sc; - data->d204 = d204; - file->private_data = data; - return nonseekable_open(inode, file); - -fail_vfree_base: - vfree(data->base); -fail_kfree_data: - kfree(data); - return rc; -} - -static int dbfs_d204_release(struct inode *inode, struct file *file) -{ - struct dbfs_d204_private *data = file->private_data; - - vfree(data->base); - kfree(data); + *data = d204; + *data_free_ptr = base; + *size = d204->hdr.len + sizeof(struct dbfs_d204_hdr); return 0; } -static ssize_t dbfs_d204_read(struct file *file, char __user *buf, - size_t size, loff_t *ppos) -{ - struct dbfs_d204_private *data = file->private_data; - - return simple_read_from_buffer(buf, size, ppos, data->d204, - data->d204->hdr.len + - sizeof(data->d204->hdr)); -} - -static const struct file_operations dbfs_d204_ops = { - .open = dbfs_d204_open, - .read = dbfs_d204_read, - .release = dbfs_d204_release, - .llseek = no_llseek, +static struct hypfs_dbfs_file dbfs_file_d204 = { + .name = "diag_204", + .data_create = dbfs_d204_create, + .data_free = vfree, }; -static int hypfs_dbfs_init(void) -{ - dbfs_d204_file = debugfs_create_file("diag_204", 0400, hypfs_dbfs_dir, - NULL, &dbfs_d204_ops); - if (IS_ERR(dbfs_d204_file)) - return PTR_ERR(dbfs_d204_file); - return 0; -} - __init int hypfs_diag_init(void) { int rc; @@ -639,7 +596,7 @@ __init int hypfs_diag_init(void) return -ENODATA; } if (diag204_info_type == INFO_EXT) { - rc = hypfs_dbfs_init(); + rc = hypfs_dbfs_create_file(&dbfs_file_d204); if (rc) return rc; } @@ -660,6 +617,7 @@ void hypfs_diag_exit(void) debugfs_remove(dbfs_d204_file); diag224_delete_name_table(); diag204_free_buffer(); + hypfs_dbfs_remove_file(&dbfs_file_d204); } /* diff --git a/arch/s390/hypfs/hypfs_vm.c b/arch/s390/hypfs/hypfs_vm.c index 26cf177f6a3..e54796002f6 100644 --- a/arch/s390/hypfs/hypfs_vm.c +++ b/arch/s390/hypfs/hypfs_vm.c @@ -20,8 +20,6 @@ static char local_guest[] = " "; static char all_guests[] = "* "; static char *guest_query; -static struct dentry *dbfs_d2fc_file; - struct diag2fc_data { __u32 version; __u32 flags; @@ -104,7 +102,7 @@ static void *diag2fc_store(char *query, unsigned int *count, int offset) return data; } -static void diag2fc_free(void *data) +static void diag2fc_free(const void *data) { vfree(data); } @@ -239,43 +237,29 @@ struct dbfs_d2fc { char buf[]; /* d2fc buffer */ } __attribute__ ((packed)); -static int dbfs_d2fc_open(struct inode *inode, struct file *file) +static int dbfs_diag2fc_create(void **data, void **data_free_ptr, size_t *size) { - struct dbfs_d2fc *data; + struct dbfs_d2fc *d2fc; unsigned int count; - data = diag2fc_store(guest_query, &count, sizeof(data->hdr)); - if (IS_ERR(data)) - return PTR_ERR(data); - get_clock_ext(data->hdr.tod_ext); - data->hdr.len = count * sizeof(struct diag2fc_data); - data->hdr.version = DBFS_D2FC_HDR_VERSION; - data->hdr.count = count; - memset(&data->hdr.reserved, 0, sizeof(data->hdr.reserved)); - file->private_data = data; - return nonseekable_open(inode, file); -} - -static int dbfs_d2fc_release(struct inode *inode, struct file *file) -{ - diag2fc_free(file->private_data); + d2fc = diag2fc_store(guest_query, &count, sizeof(d2fc->hdr)); + if (IS_ERR(d2fc)) + return PTR_ERR(d2fc); + get_clock_ext(d2fc->hdr.tod_ext); + d2fc->hdr.len = count * sizeof(struct diag2fc_data); + d2fc->hdr.version = DBFS_D2FC_HDR_VERSION; + d2fc->hdr.count = count; + memset(&d2fc->hdr.reserved, 0, sizeof(d2fc->hdr.reserved)); + *data = d2fc; + *data_free_ptr = d2fc; + *size = d2fc->hdr.len + sizeof(struct dbfs_d2fc_hdr); return 0; } -static ssize_t dbfs_d2fc_read(struct file *file, char __user *buf, - size_t size, loff_t *ppos) -{ - struct dbfs_d2fc *data = file->private_data; - - return simple_read_from_buffer(buf, size, ppos, data, data->hdr.len + - sizeof(struct dbfs_d2fc_hdr)); -} - -static const struct file_operations dbfs_d2fc_ops = { - .open = dbfs_d2fc_open, - .read = dbfs_d2fc_read, - .release = dbfs_d2fc_release, - .llseek = no_llseek, +static struct hypfs_dbfs_file dbfs_file_2fc = { + .name = "diag_2fc", + .data_create = dbfs_diag2fc_create, + .data_free = diag2fc_free, }; int hypfs_vm_init(void) @@ -288,18 +272,12 @@ int hypfs_vm_init(void) guest_query = local_guest; else return -EACCES; - - dbfs_d2fc_file = debugfs_create_file("diag_2fc", 0400, hypfs_dbfs_dir, - NULL, &dbfs_d2fc_ops); - if (IS_ERR(dbfs_d2fc_file)) - return PTR_ERR(dbfs_d2fc_file); - - return 0; + return hypfs_dbfs_create_file(&dbfs_file_2fc); } void hypfs_vm_exit(void) { if (!MACHINE_IS_VM) return; - debugfs_remove(dbfs_d2fc_file); + hypfs_dbfs_remove_file(&dbfs_file_2fc); } diff --git a/arch/s390/hypfs/inode.c b/arch/s390/hypfs/inode.c index 47cc446dab8..6fe874fc5f8 100644 --- a/arch/s390/hypfs/inode.c +++ b/arch/s390/hypfs/inode.c @@ -46,8 +46,6 @@ static const struct super_operations hypfs_s_ops; /* start of list of all dentries, which have to be deleted on update */ static struct dentry *hypfs_last_dentry; -struct dentry *hypfs_dbfs_dir; - static void hypfs_update_update(struct super_block *sb) { struct hypfs_sb_info *sb_info = sb->s_fs_info; @@ -471,13 +469,12 @@ static int __init hypfs_init(void) { int rc; - hypfs_dbfs_dir = debugfs_create_dir("s390_hypfs", NULL); - if (IS_ERR(hypfs_dbfs_dir)) - return PTR_ERR(hypfs_dbfs_dir); - + rc = hypfs_dbfs_init(); + if (rc) + return rc; if (hypfs_diag_init()) { rc = -ENODATA; - goto fail_debugfs_remove; + goto fail_dbfs_exit; } if (hypfs_vm_init()) { rc = -ENODATA; @@ -499,9 +496,8 @@ fail_hypfs_vm_exit: hypfs_vm_exit(); fail_hypfs_diag_exit: hypfs_diag_exit(); -fail_debugfs_remove: - debugfs_remove(hypfs_dbfs_dir); - +fail_dbfs_exit: + hypfs_dbfs_exit(); pr_err("Initialization of hypfs failed with rc=%i\n", rc); return rc; } @@ -510,7 +506,7 @@ static void __exit hypfs_exit(void) { hypfs_diag_exit(); hypfs_vm_exit(); - debugfs_remove(hypfs_dbfs_dir); + hypfs_dbfs_exit(); unregister_filesystem(&hypfs_type); kobject_put(s390_kobj); } diff --git a/arch/s390/include/asm/ccwdev.h b/arch/s390/include/asm/ccwdev.h index e8501115eca..ff6f62e0ec3 100644 --- a/arch/s390/include/asm/ccwdev.h +++ b/arch/s390/include/asm/ccwdev.h @@ -204,6 +204,8 @@ int ccw_device_tm_start_timeout(struct ccw_device *, struct tcw *, unsigned long, u8, int); int ccw_device_tm_intrg(struct ccw_device *cdev); +int ccw_device_get_mdc(struct ccw_device *cdev, u8 mask); + extern int ccw_device_set_online(struct ccw_device *cdev); extern int ccw_device_set_offline(struct ccw_device *cdev); diff --git a/arch/s390/include/asm/cputime.h b/arch/s390/include/asm/cputime.h index 40e2ab0fa3f..08143487829 100644 --- a/arch/s390/include/asm/cputime.h +++ b/arch/s390/include/asm/cputime.h @@ -202,7 +202,7 @@ static inline void s390_idle_check(struct pt_regs *regs, __u64 int_clock, static inline int s390_nohz_delay(int cpu) { - return per_cpu(s390_idle, cpu).nohz_delay != 0; + return __get_cpu_var(s390_idle).nohz_delay != 0; } #define arch_needs_cpu(cpu) s390_nohz_delay(cpu) diff --git a/arch/s390/include/asm/dasd.h b/arch/s390/include/asm/dasd.h index b604a9186f8..0be28efe5b6 100644 --- a/arch/s390/include/asm/dasd.h +++ b/arch/s390/include/asm/dasd.h @@ -73,6 +73,7 @@ typedef struct dasd_information2_t { * 0x02: use diag discipline (diag) * 0x04: set the device initially online (internal use only) * 0x08: enable ERP related logging + * 0x20: give access to raw eckd data */ #define DASD_FEATURE_DEFAULT 0x00 #define DASD_FEATURE_READONLY 0x01 @@ -80,6 +81,8 @@ typedef struct dasd_information2_t { #define DASD_FEATURE_INITIAL_ONLINE 0x04 #define DASD_FEATURE_ERPLOG 0x08 #define DASD_FEATURE_FAILFAST 0x10 +#define DASD_FEATURE_FAILONSLCK 0x20 +#define DASD_FEATURE_USERAW 0x40 #define DASD_PARTN_BITS 2 diff --git a/arch/s390/include/asm/ftrace.h b/arch/s390/include/asm/ftrace.h index 96c14a9102b..3c29be4836e 100644 --- a/arch/s390/include/asm/ftrace.h +++ b/arch/s390/include/asm/ftrace.h @@ -4,20 +4,17 @@ #ifndef __ASSEMBLY__ extern void _mcount(void); -extern unsigned long ftrace_dyn_func; struct dyn_arch_ftrace { }; #define MCOUNT_ADDR ((long)_mcount) #ifdef CONFIG_64BIT -#define MCOUNT_OFFSET_RET 18 -#define MCOUNT_INSN_SIZE 24 -#define MCOUNT_OFFSET 14 -#else -#define MCOUNT_OFFSET_RET 26 -#define MCOUNT_INSN_SIZE 30 +#define MCOUNT_INSN_SIZE 12 #define MCOUNT_OFFSET 8 +#else +#define MCOUNT_INSN_SIZE 20 +#define MCOUNT_OFFSET 4 #endif static inline unsigned long ftrace_call_adjust(unsigned long addr) diff --git a/arch/s390/include/asm/hardirq.h b/arch/s390/include/asm/hardirq.h index 881d94590ae..e4155d3eb2c 100644 --- a/arch/s390/include/asm/hardirq.h +++ b/arch/s390/include/asm/hardirq.h @@ -21,20 +21,4 @@ #define HARDIRQ_BITS 8 -void clock_comparator_work(void); - -static inline unsigned long long local_tick_disable(void) -{ - unsigned long long old; - - old = S390_lowcore.clock_comparator; - S390_lowcore.clock_comparator = -1ULL; - return old; -} - -static inline void local_tick_enable(unsigned long long comp) -{ - S390_lowcore.clock_comparator = comp; -} - #endif /* __ASM_HARDIRQ_H */ diff --git a/arch/s390/include/asm/irq.h b/arch/s390/include/asm/irq.h index 7da991a858f..db14a311f1d 100644 --- a/arch/s390/include/asm/irq.h +++ b/arch/s390/include/asm/irq.h @@ -1,23 +1,33 @@ #ifndef _ASM_IRQ_H #define _ASM_IRQ_H -#ifdef __KERNEL__ #include <linux/hardirq.h> -/* - * the definition of irqs has changed in 2.5.46: - * NR_IRQS is no longer the number of i/o - * interrupts (65536), but rather the number - * of interrupt classes (2). - * Only external and i/o interrupts make much sense here (CH). - */ - enum interruption_class { EXTERNAL_INTERRUPT, IO_INTERRUPT, - + EXTINT_CLK, + EXTINT_IPI, + EXTINT_TMR, + EXTINT_TLA, + EXTINT_PFL, + EXTINT_DSD, + EXTINT_VRT, + EXTINT_SCP, + EXTINT_IUC, + IOINT_QAI, + IOINT_QDI, + IOINT_DAS, + IOINT_C15, + IOINT_C70, + IOINT_TAP, + IOINT_VMR, + IOINT_LCS, + IOINT_CLW, + IOINT_CTC, + IOINT_APB, + NMI_NMI, NR_IRQS, }; -#endif /* __KERNEL__ */ -#endif +#endif /* _ASM_IRQ_H */ diff --git a/arch/s390/include/asm/kprobes.h b/arch/s390/include/asm/kprobes.h index 330f68caffe..a231a9439c4 100644 --- a/arch/s390/include/asm/kprobes.h +++ b/arch/s390/include/asm/kprobes.h @@ -31,7 +31,6 @@ #include <linux/ptrace.h> #include <linux/percpu.h> -#define __ARCH_WANT_KPROBES_INSN_SLOT struct pt_regs; struct kprobe; @@ -58,23 +57,12 @@ typedef u16 kprobe_opcode_t; /* Architecture specific copy of original instruction */ struct arch_specific_insn { /* copy of original instruction */ - kprobe_opcode_t *insn; - int fixup; - int ilen; - int reg; + kprobe_opcode_t insn[MAX_INSN_SIZE]; }; -struct ins_replace_args { - kprobe_opcode_t *ptr; - kprobe_opcode_t old; - kprobe_opcode_t new; -}; struct prev_kprobe { struct kprobe *kp; unsigned long status; - unsigned long saved_psw; - unsigned long kprobe_saved_imask; - unsigned long kprobe_saved_ctl[3]; }; /* per-cpu kprobe control block */ @@ -82,17 +70,13 @@ struct kprobe_ctlblk { unsigned long kprobe_status; unsigned long kprobe_saved_imask; unsigned long kprobe_saved_ctl[3]; - struct pt_regs jprobe_saved_regs; - unsigned long jprobe_saved_r14; - unsigned long jprobe_saved_r15; struct prev_kprobe prev_kprobe; + struct pt_regs jprobe_saved_regs; kprobe_opcode_t jprobes_stack[MAX_STACK_SIZE]; }; void arch_remove_kprobe(struct kprobe *p); void kretprobe_trampoline(void); -int is_prohibited_opcode(kprobe_opcode_t *instruction); -void get_instruction_type(struct arch_specific_insn *ainsn); int kprobe_fault_handler(struct pt_regs *regs, int trapnr); int kprobe_exceptions_notify(struct notifier_block *self, diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h index 8d6f8716957..bf3de04170a 100644 --- a/arch/s390/include/asm/processor.h +++ b/arch/s390/include/asm/processor.h @@ -32,7 +32,6 @@ static inline void get_cpu_id(struct cpuid *ptr) } extern void s390_adjust_jiffies(void); -extern void print_cpu_info(void); extern int get_cpu_capability(unsigned int *); /* @@ -81,7 +80,8 @@ struct thread_struct { mm_segment_t mm_segment; unsigned long prot_addr; /* address of protection-excep. */ unsigned int trap_no; - per_struct per_info; + struct per_regs per_user; /* User specified PER registers */ + struct per_event per_event; /* Cause of the last PER trap */ /* pfault_wait is used to block the process on a pfault event */ unsigned long pfault_wait; }; diff --git a/arch/s390/include/asm/ptrace.h b/arch/s390/include/asm/ptrace.h index d9d42b1e46f..9ad628a8574 100644 --- a/arch/s390/include/asm/ptrace.h +++ b/arch/s390/include/asm/ptrace.h @@ -331,10 +331,60 @@ struct pt_regs unsigned short ilc; unsigned short svcnr; }; + +/* + * Program event recording (PER) register set. + */ +struct per_regs { + unsigned long control; /* PER control bits */ + unsigned long start; /* PER starting address */ + unsigned long end; /* PER ending address */ +}; + +/* + * PER event contains information about the cause of the last PER exception. + */ +struct per_event { + unsigned short cause; /* PER code, ATMID and AI */ + unsigned long address; /* PER address */ + unsigned char paid; /* PER access identification */ +}; + +/* + * Simplified per_info structure used to decode the ptrace user space ABI. + */ +struct per_struct_kernel { + unsigned long cr9; /* PER control bits */ + unsigned long cr10; /* PER starting address */ + unsigned long cr11; /* PER ending address */ + unsigned long bits; /* Obsolete software bits */ + unsigned long starting_addr; /* User specified start address */ + unsigned long ending_addr; /* User specified end address */ + unsigned short perc_atmid; /* PER trap ATMID */ + unsigned long address; /* PER trap instruction address */ + unsigned char access_id; /* PER trap access identification */ +}; + +#define PER_EVENT_MASK 0xE9000000UL + +#define PER_EVENT_BRANCH 0x80000000UL +#define PER_EVENT_IFETCH 0x40000000UL +#define PER_EVENT_STORE 0x20000000UL +#define PER_EVENT_STORE_REAL 0x08000000UL +#define PER_EVENT_NULLIFICATION 0x01000000UL + +#define PER_CONTROL_MASK 0x00a00000UL + +#define PER_CONTROL_BRANCH_ADDRESS 0x00800000UL +#define PER_CONTROL_ALTERATION 0x00200000UL + #endif /* - * Now for the program event recording (trace) definitions. + * Now for the user space program event recording (trace) definitions. + * The following structures are used only for the ptrace interface, don't + * touch or even look at it if you don't want to modify the user-space + * ptrace interface. In particular stay away from it for in-kernel PER. */ typedef struct { diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h index 46e96bc1f5a..350e7ee5952 100644 --- a/arch/s390/include/asm/qdio.h +++ b/arch/s390/include/asm/qdio.h @@ -361,6 +361,7 @@ struct qdio_initialize { qdio_handler_t *input_handler; qdio_handler_t *output_handler; void (*queue_start_poll) (struct ccw_device *, int, unsigned long); + int scan_threshold; unsigned long int_parm; void **input_sbal_addr_array; void **output_sbal_addr_array; diff --git a/arch/s390/include/asm/s390_ext.h b/arch/s390/include/asm/s390_ext.h index 1a9307e7084..080876d5f19 100644 --- a/arch/s390/include/asm/s390_ext.h +++ b/arch/s390/include/asm/s390_ext.h @@ -1,32 +1,17 @@ -#ifndef _S390_EXTINT_H -#define _S390_EXTINT_H - /* - * include/asm-s390/s390_ext.h - * - * S390 version - * Copyright IBM Corp. 1999,2007 - * Author(s): Holger Smolinski (Holger.Smolinski@de.ibm.com), - * Martin Schwidefsky (schwidefsky@de.ibm.com) + * Copyright IBM Corp. 1999,2010 + * Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>, + * Martin Schwidefsky <schwidefsky@de.ibm.com>, */ +#ifndef _S390_EXTINT_H +#define _S390_EXTINT_H + #include <linux/types.h> typedef void (*ext_int_handler_t)(unsigned int, unsigned int, unsigned long); -typedef struct ext_int_info_t { - struct ext_int_info_t *next; - ext_int_handler_t handler; - __u16 code; -} ext_int_info_t; - -extern ext_int_info_t *ext_int_hash[]; - int register_external_interrupt(__u16 code, ext_int_handler_t handler); -int register_early_external_interrupt(__u16 code, ext_int_handler_t handler, - ext_int_info_t *info); int unregister_external_interrupt(__u16 code, ext_int_handler_t handler); -int unregister_early_external_interrupt(__u16 code, ext_int_handler_t handler, - ext_int_info_t *info); -#endif +#endif /* _S390_EXTINT_H */ diff --git a/arch/s390/include/asm/smp.h b/arch/s390/include/asm/smp.h index edc03cb9cd7..045e009fc16 100644 --- a/arch/s390/include/asm/smp.h +++ b/arch/s390/include/asm/smp.h @@ -20,7 +20,6 @@ extern void machine_power_off_smp(void); extern int __cpu_disable (void); extern void __cpu_die (unsigned int cpu); -extern void cpu_die (void) __attribute__ ((noreturn)); extern int __cpu_up (unsigned int cpu); extern struct mutex smp_cpu_state_mutex; @@ -71,8 +70,10 @@ static inline void smp_switch_to_ipl_cpu(void (*func)(void *), void *data) #ifdef CONFIG_HOTPLUG_CPU extern int smp_rescan_cpus(void); +extern void __noreturn cpu_die(void); #else static inline int smp_rescan_cpus(void) { return 0; } +static inline void cpu_die(void) { } #endif #endif /* __ASM_SMP_H */ diff --git a/arch/s390/include/asm/system.h b/arch/s390/include/asm/system.h index 3ad16dbf622..6710b0eac16 100644 --- a/arch/s390/include/asm/system.h +++ b/arch/s390/include/asm/system.h @@ -20,6 +20,7 @@ struct task_struct; extern struct task_struct *__switch_to(void *, void *); +extern void update_per_regs(struct task_struct *task); static inline void save_fp_regs(s390_fp_regs *fpregs) { @@ -93,6 +94,7 @@ static inline void restore_access_regs(unsigned int *acrs) if (next->mm) { \ restore_fp_regs(&next->thread.fp_regs); \ restore_access_regs(&next->thread.acrs[0]); \ + update_per_regs(next); \ } \ prev = __switch_to(prev,next); \ } while (0) @@ -101,11 +103,9 @@ extern void account_vtime(struct task_struct *, struct task_struct *); extern void account_tick_vtime(struct task_struct *); #ifdef CONFIG_PFAULT -extern void pfault_irq_init(void); extern int pfault_init(void); extern void pfault_fini(void); #else /* CONFIG_PFAULT */ -#define pfault_irq_init() do { } while (0) #define pfault_init() ({-1;}) #define pfault_fini() do { } while (0) #endif /* CONFIG_PFAULT */ diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/thread_info.h index 5baf0230b29..ebc77091466 100644 --- a/arch/s390/include/asm/thread_info.h +++ b/arch/s390/include/asm/thread_info.h @@ -74,7 +74,7 @@ struct thread_info { /* how to get the thread information struct from C */ static inline struct thread_info *current_thread_info(void) { - return (struct thread_info *)(S390_lowcore.kernel_stack - THREAD_SIZE); + return (struct thread_info *) S390_lowcore.thread_info; } #define THREAD_SIZE_ORDER THREAD_ORDER @@ -88,7 +88,7 @@ static inline struct thread_info *current_thread_info(void) #define TIF_SIGPENDING 2 /* signal pending */ #define TIF_NEED_RESCHED 3 /* rescheduling necessary */ #define TIF_RESTART_SVC 4 /* restart svc with new svc number */ -#define TIF_SINGLE_STEP 6 /* deliver sigtrap on return to user */ +#define TIF_PER_TRAP 6 /* deliver sigtrap on return to user */ #define TIF_MCCK_PENDING 7 /* machine check handling is pending */ #define TIF_SYSCALL_TRACE 8 /* syscall trace active */ #define TIF_SYSCALL_AUDIT 9 /* syscall auditing active */ @@ -99,14 +99,15 @@ static inline struct thread_info *current_thread_info(void) #define TIF_31BIT 17 /* 32bit process */ #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ #define TIF_RESTORE_SIGMASK 19 /* restore signal mask in do_signal() */ -#define TIF_FREEZE 20 /* thread is freezing for suspend */ +#define TIF_SINGLE_STEP 20 /* This task is single stepped */ +#define TIF_FREEZE 21 /* thread is freezing for suspend */ #define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) #define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) #define _TIF_RESTART_SVC (1<<TIF_RESTART_SVC) -#define _TIF_SINGLE_STEP (1<<TIF_SINGLE_STEP) +#define _TIF_PER_TRAP (1<<TIF_PER_TRAP) #define _TIF_MCCK_PENDING (1<<TIF_MCCK_PENDING) #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) #define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) @@ -114,6 +115,7 @@ static inline struct thread_info *current_thread_info(void) #define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT) #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) #define _TIF_31BIT (1<<TIF_31BIT) +#define _TIF_SINGLE_STEP (1<<TIF_FREEZE) #define _TIF_FREEZE (1<<TIF_FREEZE) #endif /* __KERNEL__ */ diff --git a/arch/s390/include/asm/timex.h b/arch/s390/include/asm/timex.h index 09d345a701d..88829a40af6 100644 --- a/arch/s390/include/asm/timex.h +++ b/arch/s390/include/asm/timex.h @@ -11,6 +11,8 @@ #ifndef _ASM_S390_TIMEX_H #define _ASM_S390_TIMEX_H +#include <asm/lowcore.h> + /* The value of the TOD clock for 1.1.1970. */ #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL @@ -49,6 +51,24 @@ static inline void store_clock_comparator(__u64 *time) asm volatile("stckc %0" : "=Q" (*time)); } +void clock_comparator_work(void); + +static inline unsigned long long local_tick_disable(void) +{ + unsigned long long old; + + old = S390_lowcore.clock_comparator; + S390_lowcore.clock_comparator = -1ULL; + set_clock_comparator(S390_lowcore.clock_comparator); + return old; +} + +static inline void local_tick_enable(unsigned long long comp) +{ + S390_lowcore.clock_comparator = comp; + set_clock_comparator(S390_lowcore.clock_comparator); +} + #define CLOCK_TICK_RATE 1193180 /* Underlying HZ */ typedef unsigned long long cycles_t; diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c index 33982e7ce04..fe03c140002 100644 --- a/arch/s390/kernel/asm-offsets.c +++ b/arch/s390/kernel/asm-offsets.c @@ -23,14 +23,16 @@ int main(void) { DEFINE(__THREAD_info, offsetof(struct task_struct, stack)); DEFINE(__THREAD_ksp, offsetof(struct task_struct, thread.ksp)); - DEFINE(__THREAD_per, offsetof(struct task_struct, thread.per_info)); DEFINE(__THREAD_mm_segment, offsetof(struct task_struct, thread.mm_segment)); BLANK(); DEFINE(__TASK_pid, offsetof(struct task_struct, pid)); BLANK(); - DEFINE(__PER_atmid, offsetof(per_struct, lowcore.words.perc_atmid)); - DEFINE(__PER_address, offsetof(per_struct, lowcore.words.address)); - DEFINE(__PER_access_id, offsetof(per_struct, lowcore.words.access_id)); + DEFINE(__THREAD_per_cause, + offsetof(struct task_struct, thread.per_event.cause)); + DEFINE(__THREAD_per_address, + offsetof(struct task_struct, thread.per_event.address)); + DEFINE(__THREAD_per_paid, + offsetof(struct task_struct, thread.per_event.paid)); BLANK(); DEFINE(__TI_task, offsetof(struct thread_info, task)); DEFINE(__TI_domain, offsetof(struct thread_info, exec_domain)); @@ -85,9 +87,9 @@ int main(void) DEFINE(__LC_PGM_ILC, offsetof(struct _lowcore, pgm_ilc)); DEFINE(__LC_PGM_INT_CODE, offsetof(struct _lowcore, pgm_code)); DEFINE(__LC_TRANS_EXC_CODE, offsetof(struct _lowcore, trans_exc_code)); - DEFINE(__LC_PER_ATMID, offsetof(struct _lowcore, per_perc_atmid)); + DEFINE(__LC_PER_CAUSE, offsetof(struct _lowcore, per_perc_atmid)); DEFINE(__LC_PER_ADDRESS, offsetof(struct _lowcore, per_address)); - DEFINE(__LC_PER_ACCESS_ID, offsetof(struct _lowcore, per_access_id)); + DEFINE(__LC_PER_PAID, offsetof(struct _lowcore, per_access_id)); DEFINE(__LC_AR_MODE_ID, offsetof(struct _lowcore, ar_access_id)); DEFINE(__LC_SUBCHANNEL_ID, offsetof(struct _lowcore, subchannel_id)); DEFINE(__LC_SUBCHANNEL_NR, offsetof(struct _lowcore, subchannel_nr)); diff --git a/arch/s390/kernel/compat_ptrace.h b/arch/s390/kernel/compat_ptrace.h index 3141025724f..12b82383351 100644 --- a/arch/s390/kernel/compat_ptrace.h +++ b/arch/s390/kernel/compat_ptrace.h @@ -4,40 +4,19 @@ #include <asm/ptrace.h> /* needed for NUM_CR_WORDS */ #include "compat_linux.h" /* needed for psw_compat_t */ -typedef struct { - __u32 cr[NUM_CR_WORDS]; -} per_cr_words32; - -typedef struct { - __u16 perc_atmid; /* 0x096 */ - __u32 address; /* 0x098 */ - __u8 access_id; /* 0x0a1 */ -} per_lowcore_words32; - -typedef struct { - union { - per_cr_words32 words; - } control_regs; - /* - * Use these flags instead of setting em_instruction_fetch - * directly they are used so that single stepping can be - * switched on & off while not affecting other tracing - */ - unsigned single_step : 1; - unsigned instruction_fetch : 1; - unsigned : 30; - /* - * These addresses are copied into cr10 & cr11 if single - * stepping is switched off - */ - __u32 starting_addr; - __u32 ending_addr; - union { - per_lowcore_words32 words; - } lowcore; -} per_struct32; +struct compat_per_struct_kernel { + __u32 cr9; /* PER control bits */ + __u32 cr10; /* PER starting address */ + __u32 cr11; /* PER ending address */ + __u32 bits; /* Obsolete software bits */ + __u32 starting_addr; /* User specified start address */ + __u32 ending_addr; /* User specified end address */ + __u16 perc_atmid; /* PER trap ATMID */ + __u32 address; /* PER trap instruction address */ + __u8 access_id; /* PER trap access identification */ +}; -struct user_regs_struct32 +struct compat_user_regs_struct { psw_compat_t psw; u32 gprs[NUM_GPRS]; @@ -50,14 +29,14 @@ struct user_regs_struct32 * itself as there is no "official" ptrace interface for hardware * watchpoints. This is the way intel does it. */ - per_struct32 per_info; + struct compat_per_struct_kernel per_info; u32 ieee_instruction_pointer; /* obsolete, always 0 */ }; -struct user32 { +struct compat_user { /* We start with the registers, to mimic the way that "memory" is returned from the ptrace(3,...) function. */ - struct user_regs_struct32 regs; /* Where the registers are actually stored */ + struct compat_user_regs_struct regs; /* The rest of this junk is to help gdb figure out what goes where */ u32 u_tsize; /* Text segment size (pages). */ u32 u_dsize; /* Data segment size (pages). */ @@ -79,6 +58,6 @@ typedef struct __u32 len; __u32 kernel_addr; __u32 process_addr; -} ptrace_area_emu31; +} compat_ptrace_area; #endif /* _PTRACE32_H */ diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S index 1ecc337fb67..648f64239a9 100644 --- a/arch/s390/kernel/entry.S +++ b/arch/s390/kernel/entry.S @@ -9,7 +9,6 @@ * Heiko Carstens <heiko.carstens@de.ibm.com> */ -#include <linux/sys.h> #include <linux/linkage.h> #include <linux/init.h> #include <asm/cache.h> @@ -49,7 +48,7 @@ SP_SVCNR = STACK_FRAME_OVERHEAD + __PT_SVCNR SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \ - _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP ) + _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_PER_TRAP ) _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \ _TIF_MCCK_PENDING) _TIF_SYSCALL = (_TIF_SYSCALL_TRACE>>8 | _TIF_SYSCALL_AUDIT>>8 | \ @@ -110,31 +109,36 @@ STACK_SIZE = 1 << STACK_SHIFT 1: stm %r10,%r11,\lc_sum .endm - .macro SAVE_ALL_BASE savearea + .macro SAVE_ALL_SVC psworg,savearea stm %r12,%r15,\savearea l %r13,__LC_SVC_NEW_PSW+4 # load &system_call to %r13 + l %r15,__LC_KERNEL_STACK # problem state -> load ksp + s %r15,BASED(.Lc_spsize) # make room for registers & psw .endm - .macro SAVE_ALL_SVC psworg,savearea - la %r12,\psworg - l %r15,__LC_KERNEL_STACK # problem state -> load ksp + .macro SAVE_ALL_BASE savearea + stm %r12,%r15,\savearea + l %r13,__LC_SVC_NEW_PSW+4 # load &system_call to %r13 .endm - .macro SAVE_ALL_SYNC psworg,savearea - la %r12,\psworg + .macro SAVE_ALL_PGM psworg,savearea tm \psworg+1,0x01 # test problem state bit - bz BASED(2f) # skip stack setup save - l %r15,__LC_KERNEL_STACK # problem state -> load ksp #ifdef CONFIG_CHECK_STACK - b BASED(3f) -2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD - bz BASED(stack_overflow) -3: + bnz BASED(1f) + tml %r15,STACK_SIZE - CONFIG_STACK_GUARD + bnz BASED(2f) + la %r12,\psworg + b BASED(stack_overflow) +#else + bz BASED(2f) #endif -2: +1: l %r15,__LC_KERNEL_STACK # problem state -> load ksp +2: s %r15,BASED(.Lc_spsize) # make room for registers & psw .endm .macro SAVE_ALL_ASYNC psworg,savearea + stm %r12,%r15,\savearea + l %r13,__LC_SVC_NEW_PSW+4 # load &system_call to %r13 la %r12,\psworg tm \psworg+1,0x01 # test problem state bit bnz BASED(1f) # from user -> load async stack @@ -149,27 +153,23 @@ STACK_SIZE = 1 << STACK_SHIFT 0: l %r14,__LC_ASYNC_STACK # are we already on the async stack ? slr %r14,%r15 sra %r14,STACK_SHIFT - be BASED(2f) -1: l %r15,__LC_ASYNC_STACK #ifdef CONFIG_CHECK_STACK - b BASED(3f) -2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD - bz BASED(stack_overflow) -3: + bnz BASED(1f) + tml %r15,STACK_SIZE - CONFIG_STACK_GUARD + bnz BASED(2f) + b BASED(stack_overflow) +#else + bz BASED(2f) #endif -2: +1: l %r15,__LC_ASYNC_STACK +2: s %r15,BASED(.Lc_spsize) # make room for registers & psw .endm - .macro CREATE_STACK_FRAME psworg,savearea - s %r15,BASED(.Lc_spsize) # make room for registers & psw - mvc SP_PSW(8,%r15),0(%r12) # move user PSW to stack + .macro CREATE_STACK_FRAME savearea + xc __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15) st %r2,SP_ORIG_R2(%r15) # store original content of gpr 2 - icm %r12,12,__LC_SVC_ILC - stm %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack - st %r12,SP_ILC(%r15) mvc SP_R12(16,%r15),\savearea # move %r12-%r15 to stack - la %r12,0 - st %r12,__SF_BACKCHAIN(%r15) # clear back chain + stm %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack .endm .macro RESTORE_ALL psworg,sync @@ -188,6 +188,8 @@ STACK_SIZE = 1 << STACK_SHIFT ssm __SF_EMPTY(%r15) .endm + .section .kprobes.text, "ax" + /* * Scheduler resume function, called by switch_to * gpr2 = (task_struct *) prev @@ -198,31 +200,21 @@ STACK_SIZE = 1 << STACK_SHIFT .globl __switch_to __switch_to: basr %r1,0 -__switch_to_base: - tm __THREAD_per(%r3),0xe8 # new process is using per ? - bz __switch_to_noper-__switch_to_base(%r1) # if not we're fine - stctl %c9,%c11,__SF_EMPTY(%r15) # We are using per stuff - clc __THREAD_per(12,%r3),__SF_EMPTY(%r15) - be __switch_to_noper-__switch_to_base(%r1) # we got away w/o bashing TLB's - lctl %c9,%c11,__THREAD_per(%r3) # Nope we didn't -__switch_to_noper: - l %r4,__THREAD_info(%r2) # get thread_info of prev +0: l %r4,__THREAD_info(%r2) # get thread_info of prev + l %r5,__THREAD_info(%r3) # get thread_info of next tm __TI_flags+3(%r4),_TIF_MCCK_PENDING # machine check pending? - bz __switch_to_no_mcck-__switch_to_base(%r1) - ni __TI_flags+3(%r4),255-_TIF_MCCK_PENDING # clear flag in prev - l %r4,__THREAD_info(%r3) # get thread_info of next - oi __TI_flags+3(%r4),_TIF_MCCK_PENDING # set it in next -__switch_to_no_mcck: - stm %r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task - st %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp - l %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp - lm %r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task - st %r3,__LC_CURRENT # __LC_CURRENT = current task struct - lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4 - l %r3,__THREAD_info(%r3) # load thread_info from task struct - st %r3,__LC_THREAD_INFO - ahi %r3,STACK_SIZE - st %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack + bz 1f-0b(%r1) + ni __TI_flags+3(%r4),255-_TIF_MCCK_PENDING # clear flag in prev + oi __TI_flags+3(%r5),_TIF_MCCK_PENDING # set it in next +1: stm %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task + st %r15,__THREAD_ksp(%r2) # store kernel stack of prev + l %r15,__THREAD_ksp(%r3) # load kernel stack of next + lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4 + lm %r6,%r15,__SF_GPRS(%r15) # load gprs of next task + st %r3,__LC_CURRENT # store task struct of next + st %r5,__LC_THREAD_INFO # store thread info of next + ahi %r5,STACK_SIZE # end of kernel stack of next + st %r5,__LC_KERNEL_STACK # store end of kernel stack br %r14 __critical_start: @@ -235,10 +227,11 @@ __critical_start: system_call: stpt __LC_SYNC_ENTER_TIMER sysc_saveall: - SAVE_ALL_BASE __LC_SAVE_AREA SAVE_ALL_SVC __LC_SVC_OLD_PSW,__LC_SAVE_AREA - CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA - lh %r7,0x8a # get svc number from lowcore + CREATE_STACK_FRAME __LC_SAVE_AREA + mvc SP_PSW(8,%r15),__LC_SVC_OLD_PSW + mvc SP_ILC(4,%r15),__LC_SVC_ILC + l %r12,__LC_THREAD_INFO # load pointer to thread_info struct sysc_vtime: UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER sysc_stime: @@ -246,20 +239,20 @@ sysc_stime: sysc_update: mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER sysc_do_svc: - l %r9,__LC_THREAD_INFO # load pointer to thread_info struct - ltr %r7,%r7 # test for svc 0 + xr %r7,%r7 + icm %r7,3,SP_SVCNR(%r15) # load svc number and test for svc 0 bnz BASED(sysc_nr_ok) # svc number > 0 # svc 0: system call number in %r1 cl %r1,BASED(.Lnr_syscalls) bnl BASED(sysc_nr_ok) + sth %r1,SP_SVCNR(%r15) lr %r7,%r1 # copy svc number to %r7 sysc_nr_ok: - sth %r7,SP_SVCNR(%r15) sll %r7,2 # svc number *4 - l %r8,BASED(.Lsysc_table) - tm __TI_flags+2(%r9),_TIF_SYSCALL + l %r10,BASED(.Lsysc_table) + tm __TI_flags+2(%r12),_TIF_SYSCALL mvc SP_ARGS(4,%r15),SP_R7(%r15) - l %r8,0(%r7,%r8) # get system call addr. + l %r8,0(%r7,%r10) # get system call addr. bnz BASED(sysc_tracesys) basr %r14,%r8 # call sys_xxxx st %r2,SP_R2(%r15) # store return value (change R2 on stack) @@ -267,7 +260,7 @@ sysc_nr_ok: sysc_return: LOCKDEP_SYS_EXIT sysc_tif: - tm __TI_flags+3(%r9),_TIF_WORK_SVC + tm __TI_flags+3(%r12),_TIF_WORK_SVC bnz BASED(sysc_work) # there is work to do (signals etc.) sysc_restore: RESTORE_ALL __LC_RETURN_PSW,1 @@ -284,17 +277,17 @@ sysc_work: # One of the work bits is on. Find out which one. # sysc_work_tif: - tm __TI_flags+3(%r9),_TIF_MCCK_PENDING + tm __TI_flags+3(%r12),_TIF_MCCK_PENDING bo BASED(sysc_mcck_pending) - tm __TI_flags+3(%r9),_TIF_NEED_RESCHED + tm __TI_flags+3(%r12),_TIF_NEED_RESCHED bo BASED(sysc_reschedule) - tm __TI_flags+3(%r9),_TIF_SIGPENDING + tm __TI_flags+3(%r12),_TIF_SIGPENDING bo BASED(sysc_sigpending) - tm __TI_flags+3(%r9),_TIF_NOTIFY_RESUME + tm __TI_flags+3(%r12),_TIF_NOTIFY_RESUME bo BASED(sysc_notify_resume) - tm __TI_flags+3(%r9),_TIF_RESTART_SVC + tm __TI_flags+3(%r12),_TIF_RESTART_SVC bo BASED(sysc_restart) - tm __TI_flags+3(%r9),_TIF_SINGLE_STEP + tm __TI_flags+3(%r12),_TIF_PER_TRAP bo BASED(sysc_singlestep) b BASED(sysc_return) # beware of critical section cleanup @@ -318,13 +311,13 @@ sysc_mcck_pending: # _TIF_SIGPENDING is set, call do_signal # sysc_sigpending: - ni __TI_flags+3(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP + ni __TI_flags+3(%r12),255-_TIF_PER_TRAP # clear TIF_PER_TRAP la %r2,SP_PTREGS(%r15) # load pt_regs l %r1,BASED(.Ldo_signal) basr %r14,%r1 # call do_signal - tm __TI_flags+3(%r9),_TIF_RESTART_SVC + tm __TI_flags+3(%r12),_TIF_RESTART_SVC bo BASED(sysc_restart) - tm __TI_flags+3(%r9),_TIF_SINGLE_STEP + tm __TI_flags+3(%r12),_TIF_PER_TRAP bo BASED(sysc_singlestep) b BASED(sysc_return) @@ -342,23 +335,23 @@ sysc_notify_resume: # _TIF_RESTART_SVC is set, set up registers and restart svc # sysc_restart: - ni __TI_flags+3(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC + ni __TI_flags+3(%r12),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC l %r7,SP_R2(%r15) # load new svc number mvc SP_R2(4,%r15),SP_ORIG_R2(%r15) # restore first argument lm %r2,%r6,SP_R2(%r15) # load svc arguments + sth %r7,SP_SVCNR(%r15) b BASED(sysc_nr_ok) # restart svc # -# _TIF_SINGLE_STEP is set, call do_single_step +# _TIF_PER_TRAP is set, call do_per_trap # sysc_singlestep: - ni __TI_flags+3(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP - mvi SP_SVCNR(%r15),0xff # set trap indication to pgm check - mvi SP_SVCNR+1(%r15),0xff + ni __TI_flags+3(%r12),255-_TIF_PER_TRAP # clear TIF_PER_TRAP + xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number la %r2,SP_PTREGS(%r15) # address of register-save area l %r1,BASED(.Lhandle_per) # load adr. of per handler la %r14,BASED(sysc_return) # load adr. of system return - br %r1 # branch to do_single_step + br %r1 # branch to do_per_trap # # call tracehook_report_syscall_entry/tracehook_report_syscall_exit before @@ -368,15 +361,15 @@ sysc_tracesys: l %r1,BASED(.Ltrace_entry) la %r2,SP_PTREGS(%r15) # load pt_regs la %r3,0 - srl %r7,2 - st %r7,SP_R2(%r15) + xr %r0,%r0 + icm %r0,3,SP_SVCNR(%r15) + st %r0,SP_R2(%r15) basr %r14,%r1 cl %r2,BASED(.Lnr_syscalls) bnl BASED(sysc_tracenogo) - l %r8,BASED(.Lsysc_table) lr %r7,%r2 sll %r7,2 # svc number *4 - l %r8,0(%r7,%r8) + l %r8,0(%r7,%r10) sysc_tracego: lm %r3,%r6,SP_R3(%r15) mvc SP_ARGS(4,%r15),SP_R7(%r15) @@ -384,7 +377,7 @@ sysc_tracego: basr %r14,%r8 # call sys_xxx st %r2,SP_R2(%r15) # store return value sysc_tracenogo: - tm __TI_flags+2(%r9),_TIF_SYSCALL + tm __TI_flags+2(%r12),_TIF_SYSCALL bz BASED(sysc_return) l %r1,BASED(.Ltrace_exit) la %r2,SP_PTREGS(%r15) # load pt_regs @@ -397,7 +390,7 @@ sysc_tracenogo: .globl ret_from_fork ret_from_fork: l %r13,__LC_SVC_NEW_PSW+4 - l %r9,__LC_THREAD_INFO # load pointer to thread_info struct + l %r12,__LC_THREAD_INFO # load pointer to thread_info struct tm SP_PSW+1(%r15),0x01 # forking a kernel thread ? bo BASED(0f) st %r15,SP_R15(%r15) # store stack pointer for new kthread @@ -432,8 +425,8 @@ kernel_execve: 0: stnsm __SF_EMPTY(%r15),0xfc # disable interrupts l %r15,__LC_KERNEL_STACK # load ksp s %r15,BASED(.Lc_spsize) # make room for registers & psw - l %r9,__LC_THREAD_INFO mvc SP_PTREGS(__PT_SIZE,%r15),0(%r12) # copy pt_regs + l %r12,__LC_THREAD_INFO xc __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15) stosm __SF_EMPTY(%r15),0x03 # reenable interrupts l %r1,BASED(.Lexecve_tail) @@ -463,26 +456,27 @@ pgm_check_handler: SAVE_ALL_BASE __LC_SAVE_AREA tm __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception bnz BASED(pgm_per) # got per exception -> special case - SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA - CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA + SAVE_ALL_PGM __LC_PGM_OLD_PSW,__LC_SAVE_AREA + CREATE_STACK_FRAME __LC_SAVE_AREA + xc SP_ILC(4,%r15),SP_ILC(%r15) + mvc SP_PSW(8,%r15),__LC_PGM_OLD_PSW + l %r12,__LC_THREAD_INFO # load pointer to thread_info struct tm SP_PSW+1(%r15),0x01 # interrupting from user ? bz BASED(pgm_no_vtime) UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER pgm_no_vtime: - l %r9,__LC_THREAD_INFO # load pointer to thread_info struct l %r3,__LC_PGM_ILC # load program interruption code l %r4,__LC_TRANS_EXC_CODE REENABLE_IRQS la %r8,0x7f nr %r8,%r3 -pgm_do_call: - l %r7,BASED(.Ljump_table) sll %r8,2 - l %r7,0(%r8,%r7) # load address of handler routine + l %r1,BASED(.Ljump_table) + l %r1,0(%r8,%r1) # load address of handler routine la %r2,SP_PTREGS(%r15) # address of register-save area - basr %r14,%r7 # branch to interrupt-handler + basr %r14,%r1 # branch to interrupt-handler pgm_exit: b BASED(sysc_return) @@ -503,33 +497,34 @@ pgm_per: # Normal per exception # pgm_per_std: - SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA - CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA + SAVE_ALL_PGM __LC_PGM_OLD_PSW,__LC_SAVE_AREA + CREATE_STACK_FRAME __LC_SAVE_AREA + mvc SP_PSW(8,%r15),__LC_PGM_OLD_PSW + l %r12,__LC_THREAD_INFO # load pointer to thread_info struct tm SP_PSW+1(%r15),0x01 # interrupting from user ? bz BASED(pgm_no_vtime2) UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER pgm_no_vtime2: - l %r9,__LC_THREAD_INFO # load pointer to thread_info struct - l %r1,__TI_task(%r9) + l %r1,__TI_task(%r12) tm SP_PSW+1(%r15),0x01 # kernel per event ? bz BASED(kernel_per) - mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID - mvc __THREAD_per+__PER_address(4,%r1),__LC_PER_ADDRESS - mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID - oi __TI_flags+3(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP + mvc __THREAD_per_cause(2,%r1),__LC_PER_CAUSE + mvc __THREAD_per_address(4,%r1),__LC_PER_ADDRESS + mvc __THREAD_per_paid(1,%r1),__LC_PER_PAID + oi __TI_flags+3(%r12),_TIF_PER_TRAP # set TIF_PER_TRAP l %r3,__LC_PGM_ILC # load program interruption code l %r4,__LC_TRANS_EXC_CODE REENABLE_IRQS la %r8,0x7f nr %r8,%r3 # clear per-event-bit and ilc be BASED(pgm_exit2) # only per or per+check ? - l %r7,BASED(.Ljump_table) sll %r8,2 - l %r7,0(%r8,%r7) # load address of handler routine + l %r1,BASED(.Ljump_table) + l %r1,0(%r8,%r1) # load address of handler routine la %r2,SP_PTREGS(%r15) # address of register-save area - basr %r14,%r7 # branch to interrupt-handler + basr %r14,%r1 # branch to interrupt-handler pgm_exit2: b BASED(sysc_return) @@ -537,18 +532,19 @@ pgm_exit2: # it was a single stepped SVC that is causing all the trouble # pgm_svcper: - SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA - CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA + SAVE_ALL_PGM __LC_SVC_OLD_PSW,__LC_SAVE_AREA + CREATE_STACK_FRAME __LC_SAVE_AREA + mvc SP_PSW(8,%r15),__LC_SVC_OLD_PSW + mvc SP_ILC(4,%r15),__LC_SVC_ILC + l %r12,__LC_THREAD_INFO # load pointer to thread_info struct UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER - lh %r7,0x8a # get svc number from lowcore - l %r9,__LC_THREAD_INFO # load pointer to thread_info struct - l %r8,__TI_task(%r9) - mvc __THREAD_per+__PER_atmid(2,%r8),__LC_PER_ATMID - mvc __THREAD_per+__PER_address(4,%r8),__LC_PER_ADDRESS - mvc __THREAD_per+__PER_access_id(1,%r8),__LC_PER_ACCESS_ID - oi __TI_flags+3(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP + l %r8,__TI_task(%r12) + mvc __THREAD_per_cause(2,%r8),__LC_PER_CAUSE + mvc __THREAD_per_address(4,%r8),__LC_PER_ADDRESS + mvc __THREAD_per_paid(1,%r8),__LC_PER_PAID + oi __TI_flags+3(%r12),_TIF_PER_TRAP # set TIF_PER_TRAP stosm __SF_EMPTY(%r15),0x03 # reenable interrupts lm %r2,%r6,SP_R2(%r15) # load svc arguments b BASED(sysc_do_svc) @@ -558,8 +554,7 @@ pgm_svcper: # kernel_per: REENABLE_IRQS - mvi SP_SVCNR(%r15),0xff # set trap indication to pgm check - mvi SP_SVCNR+1(%r15),0xff + xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) la %r2,SP_PTREGS(%r15) # address of register-save area l %r1,BASED(.Lhandle_per) # load adr. of per handler basr %r14,%r1 # branch to do_single_step @@ -573,9 +568,10 @@ kernel_per: io_int_handler: stck __LC_INT_CLOCK stpt __LC_ASYNC_ENTER_TIMER - SAVE_ALL_BASE __LC_SAVE_AREA+16 SAVE_ALL_ASYNC __LC_IO_OLD_PSW,__LC_SAVE_AREA+16 - CREATE_STACK_FRAME __LC_IO_OLD_PSW,__LC_SAVE_AREA+16 + CREATE_STACK_FRAME __LC_SAVE_AREA+16 + mvc SP_PSW(8,%r15),0(%r12) # move user PSW to stack + l %r12,__LC_THREAD_INFO # load pointer to thread_info struct tm SP_PSW+1(%r15),0x01 # interrupting from user ? bz BASED(io_no_vtime) UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER @@ -583,7 +579,6 @@ io_int_handler: mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER io_no_vtime: TRACE_IRQS_OFF - l %r9,__LC_THREAD_INFO # load pointer to thread_info struct l %r1,BASED(.Ldo_IRQ) # load address of do_IRQ la %r2,SP_PTREGS(%r15) # address of register-save area basr %r14,%r1 # branch to standard irq handler @@ -591,7 +586,7 @@ io_return: LOCKDEP_SYS_EXIT TRACE_IRQS_ON io_tif: - tm __TI_flags+3(%r9),_TIF_WORK_INT + tm __TI_flags+3(%r12),_TIF_WORK_INT bnz BASED(io_work) # there is work to do (signals etc.) io_restore: RESTORE_ALL __LC_RETURN_PSW,0 @@ -609,9 +604,9 @@ io_work: bo BASED(io_work_user) # yes -> do resched & signal #ifdef CONFIG_PREEMPT # check for preemptive scheduling - icm %r0,15,__TI_precount(%r9) + icm %r0,15,__TI_precount(%r12) bnz BASED(io_restore) # preemption disabled - tm __TI_flags+3(%r9),_TIF_NEED_RESCHED + tm __TI_flags+3(%r12),_TIF_NEED_RESCHED bno BASED(io_restore) # switch to kernel stack l %r1,SP_R15(%r15) @@ -645,13 +640,13 @@ io_work_user: # and _TIF_MCCK_PENDING # io_work_tif: - tm __TI_flags+3(%r9),_TIF_MCCK_PENDING + tm __TI_flags+3(%r12),_TIF_MCCK_PENDING bo BASED(io_mcck_pending) - tm __TI_flags+3(%r9),_TIF_NEED_RESCHED + tm __TI_flags+3(%r12),_TIF_NEED_RESCHED bo BASED(io_reschedule) - tm __TI_flags+3(%r9),_TIF_SIGPENDING + tm __TI_flags+3(%r12),_TIF_SIGPENDING bo BASED(io_sigpending) - tm __TI_flags+3(%r9),_TIF_NOTIFY_RESUME + tm __TI_flags+3(%r12),_TIF_NOTIFY_RESUME bo BASED(io_notify_resume) b BASED(io_return) # beware of critical section cleanup @@ -711,16 +706,16 @@ io_notify_resume: ext_int_handler: stck __LC_INT_CLOCK stpt __LC_ASYNC_ENTER_TIMER - SAVE_ALL_BASE __LC_SAVE_AREA+16 SAVE_ALL_ASYNC __LC_EXT_OLD_PSW,__LC_SAVE_AREA+16 - CREATE_STACK_FRAME __LC_EXT_OLD_PSW,__LC_SAVE_AREA+16 + CREATE_STACK_FRAME __LC_SAVE_AREA+16 + mvc SP_PSW(8,%r15),0(%r12) # move user PSW to stack + l %r12,__LC_THREAD_INFO # load pointer to thread_info struct tm SP_PSW+1(%r15),0x01 # interrupting from user ? bz BASED(ext_no_vtime) UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER ext_no_vtime: - l %r9,__LC_THREAD_INFO # load pointer to thread_info struct TRACE_IRQS_OFF la %r2,SP_PTREGS(%r15) # address of register-save area l %r3,__LC_CPU_ADDRESS # get cpu address + interruption code @@ -775,7 +770,10 @@ mcck_int_main: sra %r14,PAGE_SHIFT be BASED(0f) l %r15,__LC_PANIC_STACK # load panic stack -0: CREATE_STACK_FRAME __LC_MCK_OLD_PSW,__LC_SAVE_AREA+32 +0: s %r15,BASED(.Lc_spsize) # make room for registers & psw + CREATE_STACK_FRAME __LC_SAVE_AREA+32 + mvc SP_PSW(8,%r15),0(%r12) + l %r12,__LC_THREAD_INFO # load pointer to thread_info struct tm __LC_MCCK_CODE+2,0x08 # mwp of old psw valid? bno BASED(mcck_no_vtime) # no -> skip cleanup critical tm SP_PSW+1(%r15),0x01 # interrupting from user ? @@ -784,7 +782,6 @@ mcck_int_main: UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER mvc __LC_LAST_UPDATE_TIMER(8),__LC_MCCK_ENTER_TIMER mcck_no_vtime: - l %r9,__LC_THREAD_INFO # load pointer to thread_info struct la %r2,SP_PTREGS(%r15) # load pt_regs l %r1,BASED(.Ls390_mcck) basr %r14,%r1 # call machine check handler @@ -796,7 +793,7 @@ mcck_no_vtime: xc __SF_BACKCHAIN(4,%r1),__SF_BACKCHAIN(%r1) # clear back chain lr %r15,%r1 stosm __SF_EMPTY(%r15),0x04 # turn dat on - tm __TI_flags+3(%r9),_TIF_MCCK_PENDING + tm __TI_flags+3(%r12),_TIF_MCCK_PENDING bno BASED(mcck_return) TRACE_IRQS_OFF l %r1,BASED(.Ls390_handle_mcck) @@ -861,6 +858,8 @@ restart_crash: restart_go: #endif + .section .kprobes.text, "ax" + #ifdef CONFIG_CHECK_STACK /* * The synchronous or the asynchronous stack overflowed. We are dead. @@ -943,12 +942,13 @@ cleanup_system_call: bh BASED(0f) mvc __LC_SAVE_AREA(16),0(%r12) 0: st %r13,4(%r12) - st %r12,__LC_SAVE_AREA+48 # argh - SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA - CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA - l %r12,__LC_SAVE_AREA+48 # argh + l %r15,__LC_KERNEL_STACK # problem state -> load ksp + s %r15,BASED(.Lc_spsize) # make room for registers & psw st %r15,12(%r12) - lh %r7,0x8a + CREATE_STACK_FRAME __LC_SAVE_AREA + mvc SP_PSW(8,%r15),__LC_SVC_OLD_PSW + mvc SP_ILC(4,%r15),__LC_SVC_ILC + mvc 0(4,%r12),__LC_THREAD_INFO cleanup_vtime: clc __LC_RETURN_PSW+4(4),BASED(cleanup_system_call_insn+12) bhe BASED(cleanup_stime) @@ -1046,7 +1046,7 @@ cleanup_io_restore_insn: .Ldo_signal: .long do_signal .Ldo_notify_resume: .long do_notify_resume -.Lhandle_per: .long do_single_step +.Lhandle_per: .long do_per_trap .Ldo_execve: .long do_execve .Lexecve_tail: .long execve_tail .Ljump_table: .long pgm_check_table diff --git a/arch/s390/kernel/entry.h b/arch/s390/kernel/entry.h index 95c1dfc4ef3..17a6f83a2d6 100644 --- a/arch/s390/kernel/entry.h +++ b/arch/s390/kernel/entry.h @@ -12,7 +12,7 @@ pgm_check_handler_t do_dat_exception; extern int sysctl_userprocess_debug; -void do_single_step(struct pt_regs *regs); +void do_per_trap(struct pt_regs *regs); void syscall_trace(struct pt_regs *regs, int entryexit); void kernel_stack_overflow(struct pt_regs * regs); void do_signal(struct pt_regs *regs); diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S index 8f3e802174d..9d3603d6c51 100644 --- a/arch/s390/kernel/entry64.S +++ b/arch/s390/kernel/entry64.S @@ -51,7 +51,7 @@ STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER STACK_SIZE = 1 << STACK_SHIFT _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \ - _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP ) + _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_PER_TRAP ) _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \ _TIF_MCCK_PENDING) _TIF_SYSCALL = (_TIF_SYSCALL_TRACE>>8 | _TIF_SYSCALL_AUDIT>>8 | \ @@ -197,6 +197,8 @@ _TIF_SYSCALL = (_TIF_SYSCALL_TRACE>>8 | _TIF_SYSCALL_AUDIT>>8 | \ ssm __SF_EMPTY(%r15) .endm + .section .kprobes.text, "ax" + /* * Scheduler resume function, called by switch_to * gpr2 = (task_struct *) prev @@ -206,30 +208,21 @@ _TIF_SYSCALL = (_TIF_SYSCALL_TRACE>>8 | _TIF_SYSCALL_AUDIT>>8 | \ */ .globl __switch_to __switch_to: - tm __THREAD_per+4(%r3),0xe8 # is the new process using per ? - jz __switch_to_noper # if not we're fine - stctg %c9,%c11,__SF_EMPTY(%r15)# We are using per stuff - clc __THREAD_per(24,%r3),__SF_EMPTY(%r15) - je __switch_to_noper # we got away without bashing TLB's - lctlg %c9,%c11,__THREAD_per(%r3) # Nope we didn't -__switch_to_noper: - lg %r4,__THREAD_info(%r2) # get thread_info of prev + lg %r4,__THREAD_info(%r2) # get thread_info of prev + lg %r5,__THREAD_info(%r3) # get thread_info of next tm __TI_flags+7(%r4),_TIF_MCCK_PENDING # machine check pending? - jz __switch_to_no_mcck - ni __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev - lg %r4,__THREAD_info(%r3) # get thread_info of next - oi __TI_flags+7(%r4),_TIF_MCCK_PENDING # set it in next -__switch_to_no_mcck: - stmg %r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task - stg %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp - lg %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp - lmg %r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task - stg %r3,__LC_CURRENT # __LC_CURRENT = current task struct - lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4 - lg %r3,__THREAD_info(%r3) # load thread_info from task struct - stg %r3,__LC_THREAD_INFO - aghi %r3,STACK_SIZE - stg %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack + jz 0f + ni __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev + oi __TI_flags+7(%r5),_TIF_MCCK_PENDING # set it in next +0: stmg %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task + stg %r15,__THREAD_ksp(%r2) # store kernel stack of prev + lg %r15,__THREAD_ksp(%r3) # load kernel stack of next + lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4 + lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task + stg %r3,__LC_CURRENT # store task struct of next + stg %r5,__LC_THREAD_INFO # store thread info of next + aghi %r5,STACK_SIZE # end of kernel stack of next + stg %r5,__LC_KERNEL_STACK # store end of kernel stack br %r14 __critical_start: @@ -309,7 +302,7 @@ sysc_work_tif: jo sysc_notify_resume tm __TI_flags+7(%r12),_TIF_RESTART_SVC jo sysc_restart - tm __TI_flags+7(%r12),_TIF_SINGLE_STEP + tm __TI_flags+7(%r12),_TIF_PER_TRAP jo sysc_singlestep j sysc_return # beware of critical section cleanup @@ -331,12 +324,12 @@ sysc_mcck_pending: # _TIF_SIGPENDING is set, call do_signal # sysc_sigpending: - ni __TI_flags+7(%r12),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP + ni __TI_flags+7(%r12),255-_TIF_PER_TRAP # clear TIF_PER_TRAP la %r2,SP_PTREGS(%r15) # load pt_regs brasl %r14,do_signal # call do_signal tm __TI_flags+7(%r12),_TIF_RESTART_SVC jo sysc_restart - tm __TI_flags+7(%r12),_TIF_SINGLE_STEP + tm __TI_flags+7(%r12),_TIF_PER_TRAP jo sysc_singlestep j sysc_return @@ -361,14 +354,14 @@ sysc_restart: j sysc_nr_ok # restart svc # -# _TIF_SINGLE_STEP is set, call do_single_step +# _TIF_PER_TRAP is set, call do_per_trap # sysc_singlestep: - ni __TI_flags+7(%r12),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP + ni __TI_flags+7(%r12),255-_TIF_PER_TRAP # clear TIF_PER_TRAP xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number la %r2,SP_PTREGS(%r15) # address of register-save area larl %r14,sysc_return # load adr. of system return - jg do_single_step # branch to do_sigtrap + jg do_per_trap # # call tracehook_report_syscall_entry/tracehook_report_syscall_exit before @@ -524,10 +517,10 @@ pgm_no_vtime2: lg %r1,__TI_task(%r12) tm SP_PSW+1(%r15),0x01 # kernel per event ? jz kernel_per - mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID - mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS - mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID - oi __TI_flags+7(%r12),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP + mvc __THREAD_per_cause(2,%r1),__LC_PER_CAUSE + mvc __THREAD_per_address(8,%r1),__LC_PER_ADDRESS + mvc __THREAD_per_paid(1,%r1),__LC_PER_PAID + oi __TI_flags+7(%r12),_TIF_PER_TRAP # set TIF_PER_TRAP lgf %r3,__LC_PGM_ILC # load program interruption code lg %r4,__LC_TRANS_EXC_CODE REENABLE_IRQS @@ -556,10 +549,10 @@ pgm_svcper: mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER LAST_BREAK lg %r8,__TI_task(%r12) - mvc __THREAD_per+__PER_atmid(2,%r8),__LC_PER_ATMID - mvc __THREAD_per+__PER_address(8,%r8),__LC_PER_ADDRESS - mvc __THREAD_per+__PER_access_id(1,%r8),__LC_PER_ACCESS_ID - oi __TI_flags+7(%r12),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP + mvc __THREAD_per_cause(2,%r8),__LC_PER_CAUSE + mvc __THREAD_per_address(8,%r8),__LC_PER_ADDRESS + mvc __THREAD_per_paid(1,%r8),__LC_PER_PAID + oi __TI_flags+7(%r12),_TIF_PER_TRAP # set TIF_PER_TRAP stosm __SF_EMPTY(%r15),0x03 # reenable interrupts lmg %r2,%r6,SP_R2(%r15) # load svc arguments j sysc_do_svc @@ -571,7 +564,7 @@ kernel_per: REENABLE_IRQS xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number la %r2,SP_PTREGS(%r15) # address of register-save area - brasl %r14,do_single_step + brasl %r14,do_per_trap j pgm_exit /* @@ -868,6 +861,8 @@ restart_crash: restart_go: #endif + .section .kprobes.text, "ax" + #ifdef CONFIG_CHECK_STACK /* * The synchronous or the asynchronous stack overflowed. We are dead. diff --git a/arch/s390/kernel/ftrace.c b/arch/s390/kernel/ftrace.c index 6a83d058131..78bdf0e5dff 100644 --- a/arch/s390/kernel/ftrace.c +++ b/arch/s390/kernel/ftrace.c @@ -4,7 +4,7 @@ * Copyright IBM Corp. 2009 * * Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>, - * + * Martin Schwidefsky <schwidefsky@de.ibm.com> */ #include <linux/hardirq.h> @@ -12,176 +12,144 @@ #include <linux/ftrace.h> #include <linux/kernel.h> #include <linux/types.h> +#include <linux/kprobes.h> #include <trace/syscall.h> #include <asm/asm-offsets.h> +#ifdef CONFIG_64BIT +#define MCOUNT_OFFSET_RET 12 +#else +#define MCOUNT_OFFSET_RET 22 +#endif + #ifdef CONFIG_DYNAMIC_FTRACE void ftrace_disable_code(void); -void ftrace_disable_return(void); -void ftrace_call_code(void); -void ftrace_nop_code(void); - -#define FTRACE_INSN_SIZE 4 +void ftrace_enable_insn(void); #ifdef CONFIG_64BIT - +/* + * The 64-bit mcount code looks like this: + * stg %r14,8(%r15) # offset 0 + * > larl %r1,<&counter> # offset 6 + * > brasl %r14,_mcount # offset 12 + * lg %r14,8(%r15) # offset 18 + * Total length is 24 bytes. The middle two instructions of the mcount + * block get overwritten by ftrace_make_nop / ftrace_make_call. + * The 64-bit enabled ftrace code block looks like this: + * stg %r14,8(%r15) # offset 0 + * > lg %r1,__LC_FTRACE_FUNC # offset 6 + * > lgr %r0,%r0 # offset 12 + * > basr %r14,%r1 # offset 16 + * lg %r14,8(%15) # offset 18 + * The return points of the mcount/ftrace function have the same offset 18. + * The 64-bit disable ftrace code block looks like this: + * stg %r14,8(%r15) # offset 0 + * > jg .+18 # offset 6 + * > lgr %r0,%r0 # offset 12 + * > basr %r14,%r1 # offset 16 + * lg %r14,8(%15) # offset 18 + * The jg instruction branches to offset 24 to skip as many instructions + * as possible. + */ asm( " .align 4\n" "ftrace_disable_code:\n" - " j 0f\n" - " .word 0x0024\n" - " lg %r1,"__stringify(__LC_FTRACE_FUNC)"\n" - " basr %r14,%r1\n" - "ftrace_disable_return:\n" - " lg %r14,8(15)\n" + " jg 0f\n" " lgr %r0,%r0\n" - "0:\n"); - -asm( + " basr %r14,%r1\n" + "0:\n" " .align 4\n" - "ftrace_nop_code:\n" - " j .+"__stringify(MCOUNT_INSN_SIZE)"\n"); + "ftrace_enable_insn:\n" + " lg %r1,"__stringify(__LC_FTRACE_FUNC)"\n"); -asm( - " .align 4\n" - "ftrace_call_code:\n" - " stg %r14,8(%r15)\n"); +#define FTRACE_INSN_SIZE 6 #else /* CONFIG_64BIT */ - +/* + * The 31-bit mcount code looks like this: + * st %r14,4(%r15) # offset 0 + * > bras %r1,0f # offset 4 + * > .long _mcount # offset 8 + * > .long <&counter> # offset 12 + * > 0: l %r14,0(%r1) # offset 16 + * > l %r1,4(%r1) # offset 20 + * basr %r14,%r14 # offset 24 + * l %r14,4(%r15) # offset 26 + * Total length is 30 bytes. The twenty bytes starting from offset 4 + * to offset 24 get overwritten by ftrace_make_nop / ftrace_make_call. + * The 31-bit enabled ftrace code block looks like this: + * st %r14,4(%r15) # offset 0 + * > l %r14,__LC_FTRACE_FUNC # offset 4 + * > j 0f # offset 8 + * > .fill 12,1,0x07 # offset 12 + * 0: basr %r14,%r14 # offset 24 + * l %r14,4(%r14) # offset 26 + * The return points of the mcount/ftrace function have the same offset 26. + * The 31-bit disabled ftrace code block looks like this: + * st %r14,4(%r15) # offset 0 + * > j .+26 # offset 4 + * > j 0f # offset 8 + * > .fill 12,1,0x07 # offset 12 + * 0: basr %r14,%r14 # offset 24 + * l %r14,4(%r14) # offset 26 + * The j instruction branches to offset 30 to skip as many instructions + * as possible. + */ asm( " .align 4\n" "ftrace_disable_code:\n" + " j 1f\n" " j 0f\n" - " l %r1,"__stringify(__LC_FTRACE_FUNC)"\n" - " basr %r14,%r1\n" - "ftrace_disable_return:\n" - " l %r14,4(%r15)\n" - " j 0f\n" - " bcr 0,%r7\n" - " bcr 0,%r7\n" - " bcr 0,%r7\n" - " bcr 0,%r7\n" - " bcr 0,%r7\n" - " bcr 0,%r7\n" - "0:\n"); - -asm( + " .fill 12,1,0x07\n" + "0: basr %r14,%r14\n" + "1:\n" " .align 4\n" - "ftrace_nop_code:\n" - " j .+"__stringify(MCOUNT_INSN_SIZE)"\n"); + "ftrace_enable_insn:\n" + " l %r14,"__stringify(__LC_FTRACE_FUNC)"\n"); -asm( - " .align 4\n" - "ftrace_call_code:\n" - " st %r14,4(%r15)\n"); +#define FTRACE_INSN_SIZE 4 #endif /* CONFIG_64BIT */ -static int ftrace_modify_code(unsigned long ip, - void *old_code, int old_size, - void *new_code, int new_size) -{ - unsigned char replaced[MCOUNT_INSN_SIZE]; - - /* - * Note: Due to modules code can disappear and change. - * We need to protect against faulting as well as code - * changing. We do this by using the probe_kernel_* - * functions. - * This however is just a simple sanity check. - */ - if (probe_kernel_read(replaced, (void *)ip, old_size)) - return -EFAULT; - if (memcmp(replaced, old_code, old_size) != 0) - return -EINVAL; - if (probe_kernel_write((void *)ip, new_code, new_size)) - return -EPERM; - return 0; -} - -static int ftrace_make_initial_nop(struct module *mod, struct dyn_ftrace *rec, - unsigned long addr) -{ - return ftrace_modify_code(rec->ip, - ftrace_call_code, FTRACE_INSN_SIZE, - ftrace_disable_code, MCOUNT_INSN_SIZE); -} int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec, unsigned long addr) { - if (addr == MCOUNT_ADDR) - return ftrace_make_initial_nop(mod, rec, addr); - return ftrace_modify_code(rec->ip, - ftrace_call_code, FTRACE_INSN_SIZE, - ftrace_nop_code, FTRACE_INSN_SIZE); + if (probe_kernel_write((void *) rec->ip, ftrace_disable_code, + MCOUNT_INSN_SIZE)) + return -EPERM; + return 0; } int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) { - return ftrace_modify_code(rec->ip, - ftrace_nop_code, FTRACE_INSN_SIZE, - ftrace_call_code, FTRACE_INSN_SIZE); + if (probe_kernel_write((void *) rec->ip, ftrace_enable_insn, + FTRACE_INSN_SIZE)) + return -EPERM; + return 0; } int ftrace_update_ftrace_func(ftrace_func_t func) { - ftrace_dyn_func = (unsigned long)func; return 0; } int __init ftrace_dyn_arch_init(void *data) { - *(unsigned long *)data = 0; + *(unsigned long *) data = 0; return 0; } #endif /* CONFIG_DYNAMIC_FTRACE */ #ifdef CONFIG_FUNCTION_GRAPH_TRACER -#ifdef CONFIG_DYNAMIC_FTRACE -/* - * Patch the kernel code at ftrace_graph_caller location: - * The instruction there is branch relative on condition. The condition mask - * is either all ones (always branch aka disable ftrace_graph_caller) or all - * zeroes (nop aka enable ftrace_graph_caller). - * Instruction format for brc is a7m4xxxx where m is the condition mask. - */ -int ftrace_enable_ftrace_graph_caller(void) -{ - unsigned short opcode = 0xa704; - - return probe_kernel_write(ftrace_graph_caller, &opcode, sizeof(opcode)); -} - -int ftrace_disable_ftrace_graph_caller(void) -{ - unsigned short opcode = 0xa7f4; - - return probe_kernel_write(ftrace_graph_caller, &opcode, sizeof(opcode)); -} - -static inline unsigned long ftrace_mcount_call_adjust(unsigned long addr) -{ - return addr - (ftrace_disable_return - ftrace_disable_code); -} - -#else /* CONFIG_DYNAMIC_FTRACE */ - -static inline unsigned long ftrace_mcount_call_adjust(unsigned long addr) -{ - return addr - MCOUNT_OFFSET_RET; -} - -#endif /* CONFIG_DYNAMIC_FTRACE */ - /* * Hook the return address and push it in the stack of return addresses * in current thread info. */ -unsigned long prepare_ftrace_return(unsigned long ip, unsigned long parent) +unsigned long __kprobes prepare_ftrace_return(unsigned long parent, + unsigned long ip) { struct ftrace_graph_ent trace; @@ -189,14 +157,42 @@ unsigned long prepare_ftrace_return(unsigned long ip, unsigned long parent) goto out; if (ftrace_push_return_trace(parent, ip, &trace.depth, 0) == -EBUSY) goto out; - trace.func = ftrace_mcount_call_adjust(ip) & PSW_ADDR_INSN; + trace.func = (ip & PSW_ADDR_INSN) - MCOUNT_OFFSET_RET; /* Only trace if the calling function expects to. */ if (!ftrace_graph_entry(&trace)) { current->curr_ret_stack--; goto out; } - parent = (unsigned long)return_to_handler; + parent = (unsigned long) return_to_handler; out: return parent; } + +#ifdef CONFIG_DYNAMIC_FTRACE +/* + * Patch the kernel code at ftrace_graph_caller location. The instruction + * there is branch relative and save to prepare_ftrace_return. To disable + * the call to prepare_ftrace_return we patch the bras offset to point + * directly after the instructions. To enable the call we calculate + * the original offset to prepare_ftrace_return and put it back. + */ +int ftrace_enable_ftrace_graph_caller(void) +{ + unsigned short offset; + + offset = ((void *) prepare_ftrace_return - + (void *) ftrace_graph_caller) / 2; + return probe_kernel_write(ftrace_graph_caller + 2, + &offset, sizeof(offset)); +} + +int ftrace_disable_ftrace_graph_caller(void) +{ + static unsigned short offset = 0x0002; + + return probe_kernel_write(ftrace_graph_caller + 2, + &offset, sizeof(offset)); +} + +#endif /* CONFIG_DYNAMIC_FTRACE */ #endif /* CONFIG_FUNCTION_GRAPH_TRACER */ diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c index 026a37a94fc..ea5099c9709 100644 --- a/arch/s390/kernel/irq.c +++ b/arch/s390/kernel/irq.c @@ -1,7 +1,5 @@ /* - * arch/s390/kernel/irq.c - * - * Copyright IBM Corp. 2004,2007 + * Copyright IBM Corp. 2004,2010 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com), * Thomas Spatzier (tspat@de.ibm.com) * @@ -17,12 +15,42 @@ #include <linux/proc_fs.h> #include <linux/profile.h> +struct irq_class { + char *name; + char *desc; +}; + +static const struct irq_class intrclass_names[] = { + {.name = "EXT" }, + {.name = "I/O" }, + {.name = "CLK", .desc = "[EXT] Clock Comparator" }, + {.name = "IPI", .desc = "[EXT] Signal Processor" }, + {.name = "TMR", .desc = "[EXT] CPU Timer" }, + {.name = "TAL", .desc = "[EXT] Timing Alert" }, + {.name = "PFL", .desc = "[EXT] Pseudo Page Fault" }, + {.name = "DSD", .desc = "[EXT] DASD Diag" }, + {.name = "VRT", .desc = "[EXT] Virtio" }, + {.name = "SCP", .desc = "[EXT] Service Call" }, + {.name = "IUC", .desc = "[EXT] IUCV" }, + {.name = "QAI", .desc = "[I/O] QDIO Adapter Interrupt" }, + {.name = "QDI", .desc = "[I/O] QDIO Interrupt" }, + {.name = "DAS", .desc = "[I/O] DASD" }, + {.name = "C15", .desc = "[I/O] 3215" }, + {.name = "C70", .desc = "[I/O] 3270" }, + {.name = "TAP", .desc = "[I/O] Tape" }, + {.name = "VMR", .desc = "[I/O] Unit Record Devices" }, + {.name = "LCS", .desc = "[I/O] LCS" }, + {.name = "CLW", .desc = "[I/O] CLAW" }, + {.name = "CTC", .desc = "[I/O] CTC" }, + {.name = "APB", .desc = "[I/O] AP Bus" }, + {.name = "NMI", .desc = "[NMI] Machine Check" }, +}; + /* * show_interrupts is needed by /proc/interrupts. */ int show_interrupts(struct seq_file *p, void *v) { - static const char *intrclass_names[] = { "EXT", "I/O", }; int i = *(loff_t *) v, j; get_online_cpus(); @@ -34,15 +62,16 @@ int show_interrupts(struct seq_file *p, void *v) } if (i < NR_IRQS) { - seq_printf(p, "%s: ", intrclass_names[i]); + seq_printf(p, "%s: ", intrclass_names[i].name); #ifndef CONFIG_SMP seq_printf(p, "%10u ", kstat_irqs(i)); #else for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); #endif + if (intrclass_names[i].desc) + seq_printf(p, " %s", intrclass_names[i].desc); seq_putc(p, '\n'); - } put_online_cpus(); return 0; diff --git a/arch/s390/kernel/kprobes.c b/arch/s390/kernel/kprobes.c index 2564793ec2b..1d05d669107 100644 --- a/arch/s390/kernel/kprobes.c +++ b/arch/s390/kernel/kprobes.c @@ -32,34 +32,14 @@ #include <linux/slab.h> #include <linux/hardirq.h> -DEFINE_PER_CPU(struct kprobe *, current_kprobe) = NULL; +DEFINE_PER_CPU(struct kprobe *, current_kprobe); DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk); -struct kretprobe_blackpoint kretprobe_blacklist[] = {{NULL, NULL}}; +struct kretprobe_blackpoint kretprobe_blacklist[] = { }; -int __kprobes arch_prepare_kprobe(struct kprobe *p) -{ - /* Make sure the probe isn't going on a difficult instruction */ - if (is_prohibited_opcode((kprobe_opcode_t *) p->addr)) - return -EINVAL; - - if ((unsigned long)p->addr & 0x01) - return -EINVAL; - - /* Use the get_insn_slot() facility for correctness */ - if (!(p->ainsn.insn = get_insn_slot())) - return -ENOMEM; - - memcpy(p->ainsn.insn, p->addr, MAX_INSN_SIZE * sizeof(kprobe_opcode_t)); - - get_instruction_type(&p->ainsn); - p->opcode = *p->addr; - return 0; -} - -int __kprobes is_prohibited_opcode(kprobe_opcode_t *instruction) +static int __kprobes is_prohibited_opcode(kprobe_opcode_t *insn) { - switch (*(__u8 *) instruction) { + switch (insn[0] >> 8) { case 0x0c: /* bassm */ case 0x0b: /* bsm */ case 0x83: /* diag */ @@ -68,7 +48,7 @@ int __kprobes is_prohibited_opcode(kprobe_opcode_t *instruction) case 0xad: /* stosm */ return -EINVAL; } - switch (*(__u16 *) instruction) { + switch (insn[0]) { case 0x0101: /* pr */ case 0xb25a: /* bsa */ case 0xb240: /* bakr */ @@ -81,93 +61,92 @@ int __kprobes is_prohibited_opcode(kprobe_opcode_t *instruction) return 0; } -void __kprobes get_instruction_type(struct arch_specific_insn *ainsn) +static int __kprobes get_fixup_type(kprobe_opcode_t *insn) { /* default fixup method */ - ainsn->fixup = FIXUP_PSW_NORMAL; - - /* save r1 operand */ - ainsn->reg = (*ainsn->insn & 0xf0) >> 4; + int fixup = FIXUP_PSW_NORMAL; - /* save the instruction length (pop 5-5) in bytes */ - switch (*(__u8 *) (ainsn->insn) >> 6) { - case 0: - ainsn->ilen = 2; - break; - case 1: - case 2: - ainsn->ilen = 4; - break; - case 3: - ainsn->ilen = 6; - break; - } - - switch (*(__u8 *) ainsn->insn) { + switch (insn[0] >> 8) { case 0x05: /* balr */ case 0x0d: /* basr */ - ainsn->fixup = FIXUP_RETURN_REGISTER; + fixup = FIXUP_RETURN_REGISTER; /* if r2 = 0, no branch will be taken */ - if ((*ainsn->insn & 0x0f) == 0) - ainsn->fixup |= FIXUP_BRANCH_NOT_TAKEN; + if ((insn[0] & 0x0f) == 0) + fixup |= FIXUP_BRANCH_NOT_TAKEN; break; case 0x06: /* bctr */ case 0x07: /* bcr */ - ainsn->fixup = FIXUP_BRANCH_NOT_TAKEN; + fixup = FIXUP_BRANCH_NOT_TAKEN; break; case 0x45: /* bal */ case 0x4d: /* bas */ - ainsn->fixup = FIXUP_RETURN_REGISTER; + fixup = FIXUP_RETURN_REGISTER; break; case 0x47: /* bc */ case 0x46: /* bct */ case 0x86: /* bxh */ case 0x87: /* bxle */ - ainsn->fixup = FIXUP_BRANCH_NOT_TAKEN; + fixup = FIXUP_BRANCH_NOT_TAKEN; break; case 0x82: /* lpsw */ - ainsn->fixup = FIXUP_NOT_REQUIRED; + fixup = FIXUP_NOT_REQUIRED; break; case 0xb2: /* lpswe */ - if (*(((__u8 *) ainsn->insn) + 1) == 0xb2) { - ainsn->fixup = FIXUP_NOT_REQUIRED; - } + if ((insn[0] & 0xff) == 0xb2) + fixup = FIXUP_NOT_REQUIRED; break; case 0xa7: /* bras */ - if ((*ainsn->insn & 0x0f) == 0x05) { - ainsn->fixup |= FIXUP_RETURN_REGISTER; - } + if ((insn[0] & 0x0f) == 0x05) + fixup |= FIXUP_RETURN_REGISTER; break; case 0xc0: - if ((*ainsn->insn & 0x0f) == 0x00 /* larl */ - || (*ainsn->insn & 0x0f) == 0x05) /* brasl */ - ainsn->fixup |= FIXUP_RETURN_REGISTER; + if ((insn[0] & 0x0f) == 0x00 || /* larl */ + (insn[0] & 0x0f) == 0x05) /* brasl */ + fixup |= FIXUP_RETURN_REGISTER; break; case 0xeb: - if (*(((__u8 *) ainsn->insn) + 5 ) == 0x44 || /* bxhg */ - *(((__u8 *) ainsn->insn) + 5) == 0x45) {/* bxleg */ - ainsn->fixup = FIXUP_BRANCH_NOT_TAKEN; - } + if ((insn[2] & 0xff) == 0x44 || /* bxhg */ + (insn[2] & 0xff) == 0x45) /* bxleg */ + fixup = FIXUP_BRANCH_NOT_TAKEN; break; case 0xe3: /* bctg */ - if (*(((__u8 *) ainsn->insn) + 5) == 0x46) { - ainsn->fixup = FIXUP_BRANCH_NOT_TAKEN; - } + if ((insn[2] & 0xff) == 0x46) + fixup = FIXUP_BRANCH_NOT_TAKEN; break; } + return fixup; +} + +int __kprobes arch_prepare_kprobe(struct kprobe *p) +{ + if ((unsigned long) p->addr & 0x01) + return -EINVAL; + + /* Make sure the probe isn't going on a difficult instruction */ + if (is_prohibited_opcode(p->addr)) + return -EINVAL; + + p->opcode = *p->addr; + memcpy(p->ainsn.insn, p->addr, ((p->opcode >> 14) + 3) & -2); + + return 0; } +struct ins_replace_args { + kprobe_opcode_t *ptr; + kprobe_opcode_t opcode; +}; + static int __kprobes swap_instruction(void *aref) { struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); unsigned long status = kcb->kprobe_status; struct ins_replace_args *args = aref; - int rc; kcb->kprobe_status = KPROBE_SWAP_INST; - rc = probe_kernel_write(args->ptr, &args->new, sizeof(args->new)); + probe_kernel_write(args->ptr, &args->opcode, sizeof(args->opcode)); kcb->kprobe_status = status; - return rc; + return 0; } void __kprobes arch_arm_kprobe(struct kprobe *p) @@ -175,8 +154,7 @@ void __kprobes arch_arm_kprobe(struct kprobe *p) struct ins_replace_args args; args.ptr = p->addr; - args.old = p->opcode; - args.new = BREAKPOINT_INSTRUCTION; + args.opcode = BREAKPOINT_INSTRUCTION; stop_machine(swap_instruction, &args, NULL); } @@ -185,64 +163,69 @@ void __kprobes arch_disarm_kprobe(struct kprobe *p) struct ins_replace_args args; args.ptr = p->addr; - args.old = BREAKPOINT_INSTRUCTION; - args.new = p->opcode; + args.opcode = p->opcode; stop_machine(swap_instruction, &args, NULL); } void __kprobes arch_remove_kprobe(struct kprobe *p) { - if (p->ainsn.insn) { - free_insn_slot(p->ainsn.insn, 0); - p->ainsn.insn = NULL; - } } -static void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs) +static void __kprobes enable_singlestep(struct kprobe_ctlblk *kcb, + struct pt_regs *regs, + unsigned long ip) { - per_cr_bits kprobe_per_regs[1]; + struct per_regs per_kprobe; - memset(kprobe_per_regs, 0, sizeof(per_cr_bits)); - regs->psw.addr = (unsigned long)p->ainsn.insn | PSW_ADDR_AMODE; + /* Set up the PER control registers %cr9-%cr11 */ + per_kprobe.control = PER_EVENT_IFETCH; + per_kprobe.start = ip; + per_kprobe.end = ip; - /* Set up the per control reg info, will pass to lctl */ - kprobe_per_regs[0].em_instruction_fetch = 1; - kprobe_per_regs[0].starting_addr = (unsigned long)p->ainsn.insn; - kprobe_per_regs[0].ending_addr = (unsigned long)p->ainsn.insn + 1; + /* Save control regs and psw mask */ + __ctl_store(kcb->kprobe_saved_ctl, 9, 11); + kcb->kprobe_saved_imask = regs->psw.mask & + (PSW_MASK_PER | PSW_MASK_IO | PSW_MASK_EXT); - /* Set the PER control regs, turns on single step for this address */ - __ctl_load(kprobe_per_regs, 9, 11); + /* Set PER control regs, turns on single step for the given address */ + __ctl_load(per_kprobe, 9, 11); regs->psw.mask |= PSW_MASK_PER; regs->psw.mask &= ~(PSW_MASK_IO | PSW_MASK_EXT); + regs->psw.addr = ip | PSW_ADDR_AMODE; } -static void __kprobes save_previous_kprobe(struct kprobe_ctlblk *kcb) +static void __kprobes disable_singlestep(struct kprobe_ctlblk *kcb, + struct pt_regs *regs, + unsigned long ip) { - kcb->prev_kprobe.kp = kprobe_running(); - kcb->prev_kprobe.status = kcb->kprobe_status; - kcb->prev_kprobe.kprobe_saved_imask = kcb->kprobe_saved_imask; - memcpy(kcb->prev_kprobe.kprobe_saved_ctl, kcb->kprobe_saved_ctl, - sizeof(kcb->kprobe_saved_ctl)); + /* Restore control regs and psw mask, set new psw address */ + __ctl_load(kcb->kprobe_saved_ctl, 9, 11); + regs->psw.mask &= ~PSW_MASK_PER; + regs->psw.mask |= kcb->kprobe_saved_imask; + regs->psw.addr = ip | PSW_ADDR_AMODE; } -static void __kprobes restore_previous_kprobe(struct kprobe_ctlblk *kcb) +/* + * Activate a kprobe by storing its pointer to current_kprobe. The + * previous kprobe is stored in kcb->prev_kprobe. A stack of up to + * two kprobes can be active, see KPROBE_REENTER. + */ +static void __kprobes push_kprobe(struct kprobe_ctlblk *kcb, struct kprobe *p) { - __get_cpu_var(current_kprobe) = kcb->prev_kprobe.kp; - kcb->kprobe_status = kcb->prev_kprobe.status; - kcb->kprobe_saved_imask = kcb->prev_kprobe.kprobe_saved_imask; - memcpy(kcb->kprobe_saved_ctl, kcb->prev_kprobe.kprobe_saved_ctl, - sizeof(kcb->kprobe_saved_ctl)); + kcb->prev_kprobe.kp = __get_cpu_var(current_kprobe); + kcb->prev_kprobe.status = kcb->kprobe_status; + __get_cpu_var(current_kprobe) = p; } -static void __kprobes set_current_kprobe(struct kprobe *p, struct pt_regs *regs, - struct kprobe_ctlblk *kcb) +/* + * Deactivate a kprobe by backing up to the previous state. If the + * current state is KPROBE_REENTER prev_kprobe.kp will be non-NULL, + * for any other state prev_kprobe.kp will be NULL. + */ +static void __kprobes pop_kprobe(struct kprobe_ctlblk *kcb) { - __get_cpu_var(current_kprobe) = p; - /* Save the interrupt and per flags */ - kcb->kprobe_saved_imask = regs->psw.mask & - (PSW_MASK_PER | PSW_MASK_IO | PSW_MASK_EXT); - /* Save the control regs that govern PER */ - __ctl_store(kcb->kprobe_saved_ctl, 9, 11); + __get_cpu_var(current_kprobe) = kcb->prev_kprobe.kp; + kcb->kprobe_status = kcb->prev_kprobe.status; } void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri, @@ -251,79 +234,104 @@ void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri, ri->ret_addr = (kprobe_opcode_t *) regs->gprs[14]; /* Replace the return addr with trampoline addr */ - regs->gprs[14] = (unsigned long)&kretprobe_trampoline; + regs->gprs[14] = (unsigned long) &kretprobe_trampoline; +} + +static void __kprobes kprobe_reenter_check(struct kprobe_ctlblk *kcb, + struct kprobe *p) +{ + switch (kcb->kprobe_status) { + case KPROBE_HIT_SSDONE: + case KPROBE_HIT_ACTIVE: + kprobes_inc_nmissed_count(p); + break; + case KPROBE_HIT_SS: + case KPROBE_REENTER: + default: + /* + * A kprobe on the code path to single step an instruction + * is a BUG. The code path resides in the .kprobes.text + * section and is executed with interrupts disabled. + */ + printk(KERN_EMERG "Invalid kprobe detected at %p.\n", p->addr); + dump_kprobe(p); + BUG(); + } } static int __kprobes kprobe_handler(struct pt_regs *regs) { - struct kprobe *p; - int ret = 0; - unsigned long *addr = (unsigned long *) - ((regs->psw.addr & PSW_ADDR_INSN) - 2); struct kprobe_ctlblk *kcb; + struct kprobe *p; /* - * We don't want to be preempted for the entire - * duration of kprobe processing + * We want to disable preemption for the entire duration of kprobe + * processing. That includes the calls to the pre/post handlers + * and single stepping the kprobe instruction. */ preempt_disable(); kcb = get_kprobe_ctlblk(); + p = get_kprobe((void *)((regs->psw.addr & PSW_ADDR_INSN) - 2)); - /* Check we're not actually recursing */ - if (kprobe_running()) { - p = get_kprobe(addr); - if (p) { - if (kcb->kprobe_status == KPROBE_HIT_SS && - *p->ainsn.insn == BREAKPOINT_INSTRUCTION) { - regs->psw.mask &= ~PSW_MASK_PER; - regs->psw.mask |= kcb->kprobe_saved_imask; - goto no_kprobe; - } - /* We have reentered the kprobe_handler(), since - * another probe was hit while within the handler. - * We here save the original kprobes variables and - * just single step on the instruction of the new probe - * without calling any user handlers. + if (p) { + if (kprobe_running()) { + /* + * We have hit a kprobe while another is still + * active. This can happen in the pre and post + * handler. Single step the instruction of the + * new probe but do not call any handler function + * of this secondary kprobe. + * push_kprobe and pop_kprobe saves and restores + * the currently active kprobe. */ - save_previous_kprobe(kcb); - set_current_kprobe(p, regs, kcb); - kprobes_inc_nmissed_count(p); - prepare_singlestep(p, regs); + kprobe_reenter_check(kcb, p); + push_kprobe(kcb, p); kcb->kprobe_status = KPROBE_REENTER; - return 1; } else { - p = __get_cpu_var(current_kprobe); - if (p->break_handler && p->break_handler(p, regs)) { - goto ss_probe; - } + /* + * If we have no pre-handler or it returned 0, we + * continue with single stepping. If we have a + * pre-handler and it returned non-zero, it prepped + * for calling the break_handler below on re-entry + * for jprobe processing, so get out doing nothing + * more here. + */ + push_kprobe(kcb, p); + kcb->kprobe_status = KPROBE_HIT_ACTIVE; + if (p->pre_handler && p->pre_handler(p, regs)) + return 1; + kcb->kprobe_status = KPROBE_HIT_SS; } - goto no_kprobe; - } - - p = get_kprobe(addr); - if (!p) - /* - * No kprobe at this address. The fault has not been - * caused by a kprobe breakpoint. The race of breakpoint - * vs. kprobe remove does not exist because on s390 we - * use stop_machine to arm/disarm the breakpoints. - */ - goto no_kprobe; - - kcb->kprobe_status = KPROBE_HIT_ACTIVE; - set_current_kprobe(p, regs, kcb); - if (p->pre_handler && p->pre_handler(p, regs)) - /* handler has already set things up, so skip ss setup */ + enable_singlestep(kcb, regs, (unsigned long) p->ainsn.insn); return 1; - -ss_probe: - prepare_singlestep(p, regs); - kcb->kprobe_status = KPROBE_HIT_SS; - return 1; - -no_kprobe: + } else if (kprobe_running()) { + p = __get_cpu_var(current_kprobe); + if (p->break_handler && p->break_handler(p, regs)) { + /* + * Continuation after the jprobe completed and + * caused the jprobe_return trap. The jprobe + * break_handler "returns" to the original + * function that still has the kprobe breakpoint + * installed. We continue with single stepping. + */ + kcb->kprobe_status = KPROBE_HIT_SS; + enable_singlestep(kcb, regs, + (unsigned long) p->ainsn.insn); + return 1; + } /* else: + * No kprobe at this address and the current kprobe + * has no break handler (no jprobe!). The kernel just + * exploded, let the standard trap handler pick up the + * pieces. + */ + } /* else: + * No kprobe at this address and no active kprobe. The trap has + * not been caused by a kprobe breakpoint. The race of breakpoint + * vs. kprobe remove does not exist because on s390 as we use + * stop_machine to arm/disarm the breakpoints. + */ preempt_enable_no_resched(); - return ret; + return 0; } /* @@ -344,12 +352,12 @@ static void __used kretprobe_trampoline_holder(void) static int __kprobes trampoline_probe_handler(struct kprobe *p, struct pt_regs *regs) { - struct kretprobe_instance *ri = NULL; + struct kretprobe_instance *ri; struct hlist_head *head, empty_rp; struct hlist_node *node, *tmp; - unsigned long flags, orig_ret_address = 0; - unsigned long trampoline_address = (unsigned long)&kretprobe_trampoline; - kprobe_opcode_t *correct_ret_addr = NULL; + unsigned long flags, orig_ret_address; + unsigned long trampoline_address; + kprobe_opcode_t *correct_ret_addr; INIT_HLIST_HEAD(&empty_rp); kretprobe_hash_lock(current, &head, &flags); @@ -367,12 +375,16 @@ static int __kprobes trampoline_probe_handler(struct kprobe *p, * real return address, and all the rest will point to * kretprobe_trampoline */ + ri = NULL; + orig_ret_address = 0; + correct_ret_addr = NULL; + trampoline_address = (unsigned long) &kretprobe_trampoline; hlist_for_each_entry_safe(ri, node, tmp, head, hlist) { if (ri->task != current) /* another task is sharing our hash bucket */ continue; - orig_ret_address = (unsigned long)ri->ret_addr; + orig_ret_address = (unsigned long) ri->ret_addr; if (orig_ret_address != trampoline_address) /* @@ -391,7 +403,7 @@ static int __kprobes trampoline_probe_handler(struct kprobe *p, /* another task is sharing our hash bucket */ continue; - orig_ret_address = (unsigned long)ri->ret_addr; + orig_ret_address = (unsigned long) ri->ret_addr; if (ri->rp && ri->rp->handler) { ri->ret_addr = correct_ret_addr; @@ -400,19 +412,18 @@ static int __kprobes trampoline_probe_handler(struct kprobe *p, recycle_rp_inst(ri, &empty_rp); - if (orig_ret_address != trampoline_address) { + if (orig_ret_address != trampoline_address) /* * This is the real return address. Any other * instances associated with this task are for * other calls deeper on the call stack */ break; - } } regs->psw.addr = orig_ret_address | PSW_ADDR_AMODE; - reset_current_kprobe(); + pop_kprobe(get_kprobe_ctlblk()); kretprobe_hash_unlock(current, &flags); preempt_enable_no_resched(); @@ -439,55 +450,42 @@ static int __kprobes trampoline_probe_handler(struct kprobe *p, static void __kprobes resume_execution(struct kprobe *p, struct pt_regs *regs) { struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); + unsigned long ip = regs->psw.addr & PSW_ADDR_INSN; + int fixup = get_fixup_type(p->ainsn.insn); - regs->psw.addr &= PSW_ADDR_INSN; - - if (p->ainsn.fixup & FIXUP_PSW_NORMAL) - regs->psw.addr = (unsigned long)p->addr + - ((unsigned long)regs->psw.addr - - (unsigned long)p->ainsn.insn); + if (fixup & FIXUP_PSW_NORMAL) + ip += (unsigned long) p->addr - (unsigned long) p->ainsn.insn; - if (p->ainsn.fixup & FIXUP_BRANCH_NOT_TAKEN) - if ((unsigned long)regs->psw.addr - - (unsigned long)p->ainsn.insn == p->ainsn.ilen) - regs->psw.addr = (unsigned long)p->addr + p->ainsn.ilen; + if (fixup & FIXUP_BRANCH_NOT_TAKEN) { + int ilen = ((p->ainsn.insn[0] >> 14) + 3) & -2; + if (ip - (unsigned long) p->ainsn.insn == ilen) + ip = (unsigned long) p->addr + ilen; + } - if (p->ainsn.fixup & FIXUP_RETURN_REGISTER) - regs->gprs[p->ainsn.reg] = ((unsigned long)p->addr + - (regs->gprs[p->ainsn.reg] - - (unsigned long)p->ainsn.insn)) - | PSW_ADDR_AMODE; + if (fixup & FIXUP_RETURN_REGISTER) { + int reg = (p->ainsn.insn[0] & 0xf0) >> 4; + regs->gprs[reg] += (unsigned long) p->addr - + (unsigned long) p->ainsn.insn; + } - regs->psw.addr |= PSW_ADDR_AMODE; - /* turn off PER mode */ - regs->psw.mask &= ~PSW_MASK_PER; - /* Restore the original per control regs */ - __ctl_load(kcb->kprobe_saved_ctl, 9, 11); - regs->psw.mask |= kcb->kprobe_saved_imask; + disable_singlestep(kcb, regs, ip); } static int __kprobes post_kprobe_handler(struct pt_regs *regs) { - struct kprobe *cur = kprobe_running(); struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); + struct kprobe *p = kprobe_running(); - if (!cur) + if (!p) return 0; - if ((kcb->kprobe_status != KPROBE_REENTER) && cur->post_handler) { + if (kcb->kprobe_status != KPROBE_REENTER && p->post_handler) { kcb->kprobe_status = KPROBE_HIT_SSDONE; - cur->post_handler(cur, regs, 0); + p->post_handler(p, regs, 0); } - resume_execution(cur, regs); - - /*Restore back the original saved kprobes variables and continue. */ - if (kcb->kprobe_status == KPROBE_REENTER) { - restore_previous_kprobe(kcb); - goto out; - } - reset_current_kprobe(); -out: + resume_execution(p, regs); + pop_kprobe(kcb); preempt_enable_no_resched(); /* @@ -495,17 +493,16 @@ out: * will have PER set, in which case, continue the remaining processing * of do_single_step, as if this is not a probe hit. */ - if (regs->psw.mask & PSW_MASK_PER) { + if (regs->psw.mask & PSW_MASK_PER) return 0; - } return 1; } static int __kprobes kprobe_trap_handler(struct pt_regs *regs, int trapnr) { - struct kprobe *cur = kprobe_running(); struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); + struct kprobe *p = kprobe_running(); const struct exception_table_entry *entry; switch(kcb->kprobe_status) { @@ -521,14 +518,8 @@ static int __kprobes kprobe_trap_handler(struct pt_regs *regs, int trapnr) * and allow the page fault handler to continue as a * normal page fault. */ - regs->psw.addr = (unsigned long)cur->addr | PSW_ADDR_AMODE; - regs->psw.mask &= ~PSW_MASK_PER; - regs->psw.mask |= kcb->kprobe_saved_imask; - if (kcb->kprobe_status == KPROBE_REENTER) - restore_previous_kprobe(kcb); - else { - reset_current_kprobe(); - } + disable_singlestep(kcb, regs, (unsigned long) p->addr); + pop_kprobe(kcb); preempt_enable_no_resched(); break; case KPROBE_HIT_ACTIVE: @@ -538,7 +529,7 @@ static int __kprobes kprobe_trap_handler(struct pt_regs *regs, int trapnr) * we can also use npre/npostfault count for accouting * these specific fault cases. */ - kprobes_inc_nmissed_count(cur); + kprobes_inc_nmissed_count(p); /* * We come here because instructions in the pre/post @@ -547,7 +538,7 @@ static int __kprobes kprobe_trap_handler(struct pt_regs *regs, int trapnr) * copy_from_user(), get_user() etc. Let the * user-specified handler try to fix it first. */ - if (cur->fault_handler && cur->fault_handler(cur, regs, trapnr)) + if (p->fault_handler && p->fault_handler(p, regs, trapnr)) return 1; /* @@ -589,7 +580,7 @@ int __kprobes kprobe_fault_handler(struct pt_regs *regs, int trapnr) int __kprobes kprobe_exceptions_notify(struct notifier_block *self, unsigned long val, void *data) { - struct die_args *args = (struct die_args *)data; + struct die_args *args = (struct die_args *) data; struct pt_regs *regs = args->regs; int ret = NOTIFY_DONE; @@ -598,16 +589,16 @@ int __kprobes kprobe_exceptions_notify(struct notifier_block *self, switch (val) { case DIE_BPT: - if (kprobe_handler(args->regs)) + if (kprobe_handler(regs)) ret = NOTIFY_STOP; break; case DIE_SSTEP: - if (post_kprobe_handler(args->regs)) + if (post_kprobe_handler(regs)) ret = NOTIFY_STOP; break; case DIE_TRAP: if (!preemptible() && kprobe_running() && - kprobe_trap_handler(args->regs, args->trapnr)) + kprobe_trap_handler(regs, args->trapnr)) ret = NOTIFY_STOP; break; default: @@ -623,23 +614,19 @@ int __kprobes kprobe_exceptions_notify(struct notifier_block *self, int __kprobes setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs) { struct jprobe *jp = container_of(p, struct jprobe, kp); - unsigned long addr; struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); + unsigned long stack; memcpy(&kcb->jprobe_saved_regs, regs, sizeof(struct pt_regs)); /* setup return addr to the jprobe handler routine */ - regs->psw.addr = (unsigned long)(jp->entry) | PSW_ADDR_AMODE; + regs->psw.addr = (unsigned long) jp->entry | PSW_ADDR_AMODE; regs->psw.mask &= ~(PSW_MASK_IO | PSW_MASK_EXT); - /* r14 is the function return address */ - kcb->jprobe_saved_r14 = (unsigned long)regs->gprs[14]; /* r15 is the stack pointer */ - kcb->jprobe_saved_r15 = (unsigned long)regs->gprs[15]; - addr = (unsigned long)kcb->jprobe_saved_r15; + stack = (unsigned long) regs->gprs[15]; - memcpy(kcb->jprobes_stack, (kprobe_opcode_t *) addr, - MIN_STACK_SIZE(addr)); + memcpy(kcb->jprobes_stack, (void *) stack, MIN_STACK_SIZE(stack)); return 1; } @@ -656,30 +643,29 @@ void __kprobes jprobe_return_end(void) int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs) { struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); - unsigned long stack_addr = (unsigned long)(kcb->jprobe_saved_r15); + unsigned long stack; + + stack = (unsigned long) kcb->jprobe_saved_regs.gprs[15]; /* Put the regs back */ memcpy(regs, &kcb->jprobe_saved_regs, sizeof(struct pt_regs)); /* put the stack back */ - memcpy((kprobe_opcode_t *) stack_addr, kcb->jprobes_stack, - MIN_STACK_SIZE(stack_addr)); + memcpy((void *) stack, kcb->jprobes_stack, MIN_STACK_SIZE(stack)); preempt_enable_no_resched(); return 1; } -static struct kprobe trampoline_p = { - .addr = (kprobe_opcode_t *) & kretprobe_trampoline, +static struct kprobe trampoline = { + .addr = (kprobe_opcode_t *) &kretprobe_trampoline, .pre_handler = trampoline_probe_handler }; int __init arch_init_kprobes(void) { - return register_kprobe(&trampoline_p); + return register_kprobe(&trampoline); } int __kprobes arch_trampoline_kprobe(struct kprobe *p) { - if (p->addr == (kprobe_opcode_t *) & kretprobe_trampoline) - return 1; - return 0; + return p->addr == (kprobe_opcode_t *) &kretprobe_trampoline; } diff --git a/arch/s390/kernel/mcount.S b/arch/s390/kernel/mcount.S index dfe015d7398..1e6a5579562 100644 --- a/arch/s390/kernel/mcount.S +++ b/arch/s390/kernel/mcount.S @@ -7,6 +7,8 @@ #include <asm/asm-offsets.h> + .section .kprobes.text, "ax" + .globl ftrace_stub ftrace_stub: br %r14 @@ -16,22 +18,12 @@ _mcount: #ifdef CONFIG_DYNAMIC_FTRACE br %r14 - .data - .globl ftrace_dyn_func -ftrace_dyn_func: - .long ftrace_stub - .previous - .globl ftrace_caller ftrace_caller: #endif stm %r2,%r5,16(%r15) bras %r1,2f -#ifdef CONFIG_DYNAMIC_FTRACE -0: .long ftrace_dyn_func -#else 0: .long ftrace_trace_function -#endif 1: .long function_trace_stop 2: l %r2,1b-0b(%r1) icm %r2,0xf,0(%r2) @@ -47,21 +39,15 @@ ftrace_caller: l %r14,0(%r14) basr %r14,%r14 #ifdef CONFIG_FUNCTION_GRAPH_TRACER -#ifdef CONFIG_DYNAMIC_FTRACE + l %r2,100(%r15) + l %r3,152(%r15) .globl ftrace_graph_caller ftrace_graph_caller: - # This unconditional branch gets runtime patched. Change only if - # you know what you are doing. See ftrace_enable_graph_caller(). - j 1f -#endif - bras %r1,0f - .long prepare_ftrace_return -0: l %r2,152(%r15) - l %r4,0(%r1) - l %r3,100(%r15) - basr %r14,%r4 - st %r2,100(%r15) -1: +# The bras instruction gets runtime patched to call prepare_ftrace_return. +# See ftrace_enable_ftrace_graph_caller. The patched instruction is: +# bras %r14,prepare_ftrace_return + bras %r14,0f +0: st %r2,100(%r15) #endif ahi %r15,96 l %r14,56(%r15) diff --git a/arch/s390/kernel/mcount64.S b/arch/s390/kernel/mcount64.S index c37211c6092..e73667286ac 100644 --- a/arch/s390/kernel/mcount64.S +++ b/arch/s390/kernel/mcount64.S @@ -7,6 +7,8 @@ #include <asm/asm-offsets.h> + .section .kprobes.text, "ax" + .globl ftrace_stub ftrace_stub: br %r14 @@ -16,12 +18,6 @@ _mcount: #ifdef CONFIG_DYNAMIC_FTRACE br %r14 - .data - .globl ftrace_dyn_func -ftrace_dyn_func: - .quad ftrace_stub - .previous - .globl ftrace_caller ftrace_caller: #endif @@ -35,26 +31,19 @@ ftrace_caller: stg %r1,__SF_BACKCHAIN(%r15) lgr %r2,%r14 lg %r3,168(%r15) -#ifdef CONFIG_DYNAMIC_FTRACE - larl %r14,ftrace_dyn_func -#else larl %r14,ftrace_trace_function -#endif lg %r14,0(%r14) basr %r14,%r14 #ifdef CONFIG_FUNCTION_GRAPH_TRACER -#ifdef CONFIG_DYNAMIC_FTRACE + lg %r2,168(%r15) + lg %r3,272(%r15) .globl ftrace_graph_caller ftrace_graph_caller: - # This unconditional branch gets runtime patched. Change only if - # you know what you are doing. See ftrace_enable_graph_caller(). - j 0f -#endif - lg %r2,272(%r15) - lg %r3,168(%r15) - brasl %r14,prepare_ftrace_return - stg %r2,168(%r15) -0: +# The bras instruction gets runtime patched to call prepare_ftrace_return. +# See ftrace_enable_ftrace_graph_caller. The patched instruction is: +# bras %r14,prepare_ftrace_return + bras %r14,0f +0: stg %r2,168(%r15) #endif aghi %r15,160 lmg %r2,%r5,32(%r15) diff --git a/arch/s390/kernel/nmi.c b/arch/s390/kernel/nmi.c index 1995c1712fc..fab88431a06 100644 --- a/arch/s390/kernel/nmi.c +++ b/arch/s390/kernel/nmi.c @@ -8,6 +8,7 @@ * Heiko Carstens <heiko.carstens@de.ibm.com>, */ +#include <linux/kernel_stat.h> #include <linux/init.h> #include <linux/errno.h> #include <linux/hardirq.h> @@ -255,7 +256,7 @@ void notrace s390_do_machine_check(struct pt_regs *regs) nmi_enter(); s390_idle_check(regs, S390_lowcore.mcck_clock, S390_lowcore.mcck_enter_timer); - + kstat_cpu(smp_processor_id()).irqs[NMI_NMI]++; mci = (struct mci *) &S390_lowcore.mcck_interruption_code; mcck = &__get_cpu_var(cpu_mcck); umode = user_mode(regs); diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c index ec2e03b22ea..6ba42222b54 100644 --- a/arch/s390/kernel/process.c +++ b/arch/s390/kernel/process.c @@ -32,6 +32,7 @@ #include <linux/kernel_stat.h> #include <linux/syscalls.h> #include <linux/compat.h> +#include <linux/kprobes.h> #include <asm/compat.h> #include <asm/uaccess.h> #include <asm/pgtable.h> @@ -41,6 +42,7 @@ #include <asm/irq.h> #include <asm/timer.h> #include <asm/nmi.h> +#include <asm/smp.h> #include "entry.h" asmlinkage void ret_from_fork(void) asm ("ret_from_fork"); @@ -75,13 +77,8 @@ unsigned long thread_saved_pc(struct task_struct *tsk) */ static void default_idle(void) { - /* CPU is going idle. */ -#ifdef CONFIG_HOTPLUG_CPU - if (cpu_is_offline(smp_processor_id())) { - preempt_enable_no_resched(); + if (cpu_is_offline(smp_processor_id())) cpu_die(); - } -#endif local_irq_disable(); if (need_resched()) { local_irq_enable(); @@ -116,15 +113,17 @@ void cpu_idle(void) } } -extern void kernel_thread_starter(void); +extern void __kprobes kernel_thread_starter(void); asm( - ".align 4\n" + ".section .kprobes.text, \"ax\"\n" + ".global kernel_thread_starter\n" "kernel_thread_starter:\n" " la 2,0(10)\n" " basr 14,9\n" " la 2,0\n" - " br 11\n"); + " br 11\n" + ".previous\n"); int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags) { @@ -214,8 +213,10 @@ int copy_thread(unsigned long clone_flags, unsigned long new_stackp, /* start new process with ar4 pointing to the correct address space */ p->thread.mm_segment = get_fs(); /* Don't copy debug registers */ - memset(&p->thread.per_info, 0, sizeof(p->thread.per_info)); + memset(&p->thread.per_user, 0, sizeof(p->thread.per_user)); + memset(&p->thread.per_event, 0, sizeof(p->thread.per_event)); clear_tsk_thread_flag(p, TIF_SINGLE_STEP); + clear_tsk_thread_flag(p, TIF_PER_TRAP); /* Initialize per thread user and system timer values */ ti = task_thread_info(p); ti->user_timer = 0; diff --git a/arch/s390/kernel/processor.c b/arch/s390/kernel/processor.c index 644548e615c..311e9d71288 100644 --- a/arch/s390/kernel/processor.c +++ b/arch/s390/kernel/processor.c @@ -13,7 +13,7 @@ #include <linux/smp.h> #include <linux/seq_file.h> #include <linux/delay.h> - +#include <linux/cpu.h> #include <asm/elf.h> #include <asm/lowcore.h> #include <asm/param.h> @@ -35,17 +35,6 @@ void __cpuinit cpu_init(void) } /* - * print_cpu_info - print basic information about a cpu - */ -void __cpuinit print_cpu_info(void) -{ - struct cpuid *id = &per_cpu(cpu_id, smp_processor_id()); - - pr_info("Processor %d started, address %d, identification %06X\n", - S390_lowcore.cpu_nr, stap(), id->ident); -} - -/* * show_cpuinfo - Get information on one CPU for use by procfs. */ static int show_cpuinfo(struct seq_file *m, void *v) @@ -57,9 +46,8 @@ static int show_cpuinfo(struct seq_file *m, void *v) unsigned long n = (unsigned long) v - 1; int i; - s390_adjust_jiffies(); - preempt_disable(); if (!n) { + s390_adjust_jiffies(); seq_printf(m, "vendor_id : IBM/S390\n" "# processors : %i\n" "bogomips per cpu: %lu.%02lu\n", @@ -71,7 +59,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "%s ", hwcap_str[i]); seq_puts(m, "\n"); } - + get_online_cpus(); if (cpu_online(n)) { struct cpuid *id = &per_cpu(cpu_id, n); seq_printf(m, "processor %li: " @@ -80,7 +68,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) "machine = %04X\n", n, id->version, id->ident, id->machine); } - preempt_enable(); + put_online_cpus(); return 0; } diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c index 019bb714db4..ef86ad24398 100644 --- a/arch/s390/kernel/ptrace.c +++ b/arch/s390/kernel/ptrace.c @@ -1,25 +1,9 @@ /* - * arch/s390/kernel/ptrace.c + * Ptrace user space interface. * - * S390 version - * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation - * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), + * Copyright IBM Corp. 1999,2010 + * Author(s): Denis Joseph Barrow * Martin Schwidefsky (schwidefsky@de.ibm.com) - * - * Based on PowerPC version - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Derived from "arch/m68k/kernel/ptrace.c" - * Copyright (C) 1994 by Hamish Macdonald - * Taken from linux/kernel/ptrace.c and modified for M680x0. - * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * - * - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file README.legal in the main directory of - * this archive for more details. */ #include <linux/kernel.h> @@ -61,76 +45,58 @@ enum s390_regset { REGSET_GENERAL_EXTENDED, }; -static void -FixPerRegisters(struct task_struct *task) +void update_per_regs(struct task_struct *task) { - struct pt_regs *regs; - per_struct *per_info; - per_cr_words cr_words; - - regs = task_pt_regs(task); - per_info = (per_struct *) &task->thread.per_info; - per_info->control_regs.bits.em_instruction_fetch = - per_info->single_step | per_info->instruction_fetch; - - if (per_info->single_step) { - per_info->control_regs.bits.starting_addr = 0; -#ifdef CONFIG_COMPAT - if (is_compat_task()) - per_info->control_regs.bits.ending_addr = 0x7fffffffUL; - else -#endif - per_info->control_regs.bits.ending_addr = PSW_ADDR_INSN; - } else { - per_info->control_regs.bits.starting_addr = - per_info->starting_addr; - per_info->control_regs.bits.ending_addr = - per_info->ending_addr; - } - /* - * if any of the control reg tracing bits are on - * we switch on per in the psw - */ - if (per_info->control_regs.words.cr[0] & PER_EM_MASK) - regs->psw.mask |= PSW_MASK_PER; - else + static const struct per_regs per_single_step = { + .control = PER_EVENT_IFETCH, + .start = 0, + .end = PSW_ADDR_INSN, + }; + struct pt_regs *regs = task_pt_regs(task); + struct thread_struct *thread = &task->thread; + const struct per_regs *new; + struct per_regs old; + + /* TIF_SINGLE_STEP overrides the user specified PER registers. */ + new = test_tsk_thread_flag(task, TIF_SINGLE_STEP) ? + &per_single_step : &thread->per_user; + + /* Take care of the PER enablement bit in the PSW. */ + if (!(new->control & PER_EVENT_MASK)) { regs->psw.mask &= ~PSW_MASK_PER; - - if (per_info->control_regs.bits.em_storage_alteration) - per_info->control_regs.bits.storage_alt_space_ctl = 1; - else - per_info->control_regs.bits.storage_alt_space_ctl = 0; - - if (task == current) { - __ctl_store(cr_words, 9, 11); - if (memcmp(&cr_words, &per_info->control_regs.words, - sizeof(cr_words)) != 0) - __ctl_load(per_info->control_regs.words, 9, 11); + return; } + regs->psw.mask |= PSW_MASK_PER; + __ctl_store(old, 9, 11); + if (memcmp(new, &old, sizeof(struct per_regs)) != 0) + __ctl_load(*new, 9, 11); } void user_enable_single_step(struct task_struct *task) { - task->thread.per_info.single_step = 1; - FixPerRegisters(task); + set_tsk_thread_flag(task, TIF_SINGLE_STEP); + if (task == current) + update_per_regs(task); } void user_disable_single_step(struct task_struct *task) { - task->thread.per_info.single_step = 0; - FixPerRegisters(task); + clear_tsk_thread_flag(task, TIF_SINGLE_STEP); + if (task == current) + update_per_regs(task); } /* * Called by kernel/ptrace.c when detaching.. * - * Make sure single step bits etc are not set. + * Clear all debugging related fields. */ -void -ptrace_disable(struct task_struct *child) +void ptrace_disable(struct task_struct *task) { - /* make sure the single step bit is not set. */ - user_disable_single_step(child); + memset(&task->thread.per_user, 0, sizeof(task->thread.per_user)); + memset(&task->thread.per_event, 0, sizeof(task->thread.per_event)); + clear_tsk_thread_flag(task, TIF_SINGLE_STEP); + clear_tsk_thread_flag(task, TIF_PER_TRAP); } #ifndef CONFIG_64BIT @@ -139,6 +105,47 @@ ptrace_disable(struct task_struct *child) # define __ADDR_MASK 7 #endif +static inline unsigned long __peek_user_per(struct task_struct *child, + addr_t addr) +{ + struct per_struct_kernel *dummy = NULL; + + if (addr == (addr_t) &dummy->cr9) + /* Control bits of the active per set. */ + return test_thread_flag(TIF_SINGLE_STEP) ? + PER_EVENT_IFETCH : child->thread.per_user.control; + else if (addr == (addr_t) &dummy->cr10) + /* Start address of the active per set. */ + return test_thread_flag(TIF_SINGLE_STEP) ? + 0 : child->thread.per_user.start; + else if (addr == (addr_t) &dummy->cr11) + /* End address of the active per set. */ + return test_thread_flag(TIF_SINGLE_STEP) ? + PSW_ADDR_INSN : child->thread.per_user.end; + else if (addr == (addr_t) &dummy->bits) + /* Single-step bit. */ + return test_thread_flag(TIF_SINGLE_STEP) ? + (1UL << (BITS_PER_LONG - 1)) : 0; + else if (addr == (addr_t) &dummy->starting_addr) + /* Start address of the user specified per set. */ + return child->thread.per_user.start; + else if (addr == (addr_t) &dummy->ending_addr) + /* End address of the user specified per set. */ + return child->thread.per_user.end; + else if (addr == (addr_t) &dummy->perc_atmid) + /* PER code, ATMID and AI of the last PER trap */ + return (unsigned long) + child->thread.per_event.cause << (BITS_PER_LONG - 16); + else if (addr == (addr_t) &dummy->address) + /* Address of the last PER trap */ + return child->thread.per_event.address; + else if (addr == (addr_t) &dummy->access_id) + /* Access id of the last PER trap */ + return (unsigned long) + child->thread.per_event.paid << (BITS_PER_LONG - 8); + return 0; +} + /* * Read the word at offset addr from the user area of a process. The * trouble here is that the information is littered over different @@ -204,10 +211,10 @@ static unsigned long __peek_user(struct task_struct *child, addr_t addr) } else if (addr < (addr_t) (&dummy->regs.per_info + 1)) { /* - * per_info is found in the thread structure + * Handle access to the per_info structure. */ - offset = addr - (addr_t) &dummy->regs.per_info; - tmp = *(addr_t *)((addr_t) &child->thread.per_info + offset); + addr -= (addr_t) &dummy->regs.per_info; + tmp = __peek_user_per(child, addr); } else tmp = 0; @@ -237,6 +244,35 @@ peek_user(struct task_struct *child, addr_t addr, addr_t data) return put_user(tmp, (addr_t __user *) data); } +static inline void __poke_user_per(struct task_struct *child, + addr_t addr, addr_t data) +{ + struct per_struct_kernel *dummy = NULL; + + /* + * There are only three fields in the per_info struct that the + * debugger user can write to. + * 1) cr9: the debugger wants to set a new PER event mask + * 2) starting_addr: the debugger wants to set a new starting + * address to use with the PER event mask. + * 3) ending_addr: the debugger wants to set a new ending + * address to use with the PER event mask. + * The user specified PER event mask and the start and end + * addresses are used only if single stepping is not in effect. + * Writes to any other field in per_info are ignored. + */ + if (addr == (addr_t) &dummy->cr9) + /* PER event mask of the user specified per set. */ + child->thread.per_user.control = + data & (PER_EVENT_MASK | PER_CONTROL_MASK); + else if (addr == (addr_t) &dummy->starting_addr) + /* Starting address of the user specified per set. */ + child->thread.per_user.start = data; + else if (addr == (addr_t) &dummy->ending_addr) + /* Ending address of the user specified per set. */ + child->thread.per_user.end = data; +} + /* * Write a word to the user area of a process at location addr. This * operation does have an additional problem compared to peek_user. @@ -311,19 +347,17 @@ static int __poke_user(struct task_struct *child, addr_t addr, addr_t data) } else if (addr < (addr_t) (&dummy->regs.per_info + 1)) { /* - * per_info is found in the thread structure + * Handle access to the per_info structure. */ - offset = addr - (addr_t) &dummy->regs.per_info; - *(addr_t *)((addr_t) &child->thread.per_info + offset) = data; + addr -= (addr_t) &dummy->regs.per_info; + __poke_user_per(child, addr, data); } - FixPerRegisters(child); return 0; } -static int -poke_user(struct task_struct *child, addr_t addr, addr_t data) +static int poke_user(struct task_struct *child, addr_t addr, addr_t data) { addr_t mask; @@ -410,12 +444,53 @@ long arch_ptrace(struct task_struct *child, long request, */ /* + * Same as peek_user_per but for a 31 bit program. + */ +static inline __u32 __peek_user_per_compat(struct task_struct *child, + addr_t addr) +{ + struct compat_per_struct_kernel *dummy32 = NULL; + + if (addr == (addr_t) &dummy32->cr9) + /* Control bits of the active per set. */ + return (__u32) test_thread_flag(TIF_SINGLE_STEP) ? + PER_EVENT_IFETCH : child->thread.per_user.control; + else if (addr == (addr_t) &dummy32->cr10) + /* Start address of the active per set. */ + return (__u32) test_thread_flag(TIF_SINGLE_STEP) ? + 0 : child->thread.per_user.start; + else if (addr == (addr_t) &dummy32->cr11) + /* End address of the active per set. */ + return test_thread_flag(TIF_SINGLE_STEP) ? + PSW32_ADDR_INSN : child->thread.per_user.end; + else if (addr == (addr_t) &dummy32->bits) + /* Single-step bit. */ + return (__u32) test_thread_flag(TIF_SINGLE_STEP) ? + 0x80000000 : 0; + else if (addr == (addr_t) &dummy32->starting_addr) + /* Start address of the user specified per set. */ + return (__u32) child->thread.per_user.start; + else if (addr == (addr_t) &dummy32->ending_addr) + /* End address of the user specified per set. */ + return (__u32) child->thread.per_user.end; + else if (addr == (addr_t) &dummy32->perc_atmid) + /* PER code, ATMID and AI of the last PER trap */ + return (__u32) child->thread.per_event.cause << 16; + else if (addr == (addr_t) &dummy32->address) + /* Address of the last PER trap */ + return (__u32) child->thread.per_event.address; + else if (addr == (addr_t) &dummy32->access_id) + /* Access id of the last PER trap */ + return (__u32) child->thread.per_event.paid << 24; + return 0; +} + +/* * Same as peek_user but for a 31 bit program. */ static u32 __peek_user_compat(struct task_struct *child, addr_t addr) { - struct user32 *dummy32 = NULL; - per_struct32 *dummy_per32 = NULL; + struct compat_user *dummy32 = NULL; addr_t offset; __u32 tmp; @@ -465,19 +540,10 @@ static u32 __peek_user_compat(struct task_struct *child, addr_t addr) } else if (addr < (addr_t) (&dummy32->regs.per_info + 1)) { /* - * per_info is found in the thread structure + * Handle access to the per_info structure. */ - offset = addr - (addr_t) &dummy32->regs.per_info; - /* This is magic. See per_struct and per_struct32. */ - if ((offset >= (addr_t) &dummy_per32->control_regs && - offset < (addr_t) (&dummy_per32->control_regs + 1)) || - (offset >= (addr_t) &dummy_per32->starting_addr && - offset <= (addr_t) &dummy_per32->ending_addr) || - offset == (addr_t) &dummy_per32->lowcore.words.address) - offset = offset*2 + 4; - else - offset = offset*2; - tmp = *(__u32 *)((addr_t) &child->thread.per_info + offset); + addr -= (addr_t) &dummy32->regs.per_info; + tmp = __peek_user_per_compat(child, addr); } else tmp = 0; @@ -498,13 +564,32 @@ static int peek_user_compat(struct task_struct *child, } /* + * Same as poke_user_per but for a 31 bit program. + */ +static inline void __poke_user_per_compat(struct task_struct *child, + addr_t addr, __u32 data) +{ + struct compat_per_struct_kernel *dummy32 = NULL; + + if (addr == (addr_t) &dummy32->cr9) + /* PER event mask of the user specified per set. */ + child->thread.per_user.control = + data & (PER_EVENT_MASK | PER_CONTROL_MASK); + else if (addr == (addr_t) &dummy32->starting_addr) + /* Starting address of the user specified per set. */ + child->thread.per_user.start = data; + else if (addr == (addr_t) &dummy32->ending_addr) + /* Ending address of the user specified per set. */ + child->thread.per_user.end = data; +} + +/* * Same as poke_user but for a 31 bit program. */ static int __poke_user_compat(struct task_struct *child, addr_t addr, addr_t data) { - struct user32 *dummy32 = NULL; - per_struct32 *dummy_per32 = NULL; + struct compat_user *dummy32 = NULL; __u32 tmp = (__u32) data; addr_t offset; @@ -561,37 +646,20 @@ static int __poke_user_compat(struct task_struct *child, } else if (addr < (addr_t) (&dummy32->regs.per_info + 1)) { /* - * per_info is found in the thread structure. - */ - offset = addr - (addr_t) &dummy32->regs.per_info; - /* - * This is magic. See per_struct and per_struct32. - * By incident the offsets in per_struct are exactly - * twice the offsets in per_struct32 for all fields. - * The 8 byte fields need special handling though, - * because the second half (bytes 4-7) is needed and - * not the first half. + * Handle access to the per_info structure. */ - if ((offset >= (addr_t) &dummy_per32->control_regs && - offset < (addr_t) (&dummy_per32->control_regs + 1)) || - (offset >= (addr_t) &dummy_per32->starting_addr && - offset <= (addr_t) &dummy_per32->ending_addr) || - offset == (addr_t) &dummy_per32->lowcore.words.address) - offset = offset*2 + 4; - else - offset = offset*2; - *(__u32 *)((addr_t) &child->thread.per_info + offset) = tmp; - + addr -= (addr_t) &dummy32->regs.per_info; + __poke_user_per_compat(child, addr, data); } - FixPerRegisters(child); return 0; } static int poke_user_compat(struct task_struct *child, addr_t addr, addr_t data) { - if (!is_compat_task() || (addr & 3) || addr > sizeof(struct user32) - 3) + if (!is_compat_task() || (addr & 3) || + addr > sizeof(struct compat_user) - 3) return -EIO; return __poke_user_compat(child, addr, data); @@ -602,7 +670,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, { unsigned long addr = caddr; unsigned long data = cdata; - ptrace_area_emu31 parea; + compat_ptrace_area parea; int copied, ret; switch (request) { diff --git a/arch/s390/kernel/s390_ext.c b/arch/s390/kernel/s390_ext.c index bd1db508e8a..185029919c4 100644 --- a/arch/s390/kernel/s390_ext.c +++ b/arch/s390/kernel/s390_ext.c @@ -1,33 +1,36 @@ /* - * arch/s390/kernel/s390_ext.c - * - * S390 version - * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation - * Author(s): Holger Smolinski (Holger.Smolinski@de.ibm.com), - * Martin Schwidefsky (schwidefsky@de.ibm.com) + * Copyright IBM Corp. 1999,2010 + * Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>, + * Martin Schwidefsky <schwidefsky@de.ibm.com>, */ +#include <linux/kernel_stat.h> +#include <linux/interrupt.h> #include <linux/module.h> #include <linux/kernel.h> -#include <linux/slab.h> #include <linux/ftrace.h> #include <linux/errno.h> -#include <linux/kernel_stat.h> -#include <linux/interrupt.h> -#include <asm/cputime.h> -#include <asm/lowcore.h> +#include <linux/slab.h> #include <asm/s390_ext.h> #include <asm/irq_regs.h> +#include <asm/cputime.h> +#include <asm/lowcore.h> #include <asm/irq.h> #include "entry.h" +struct ext_int_info { + struct ext_int_info *next; + ext_int_handler_t handler; + __u16 code; +}; + /* * ext_int_hash[index] is the start of the list for all external interrupts * that hash to this index. With the current set of external interrupts * (0x1202 external call, 0x1004 cpu timer, 0x2401 hwc console, 0x4000 * iucv and 0x2603 pfault) this is always the first element. */ -ext_int_info_t *ext_int_hash[256] = { NULL, }; +static struct ext_int_info *ext_int_hash[256]; static inline int ext_hash(__u16 code) { @@ -36,90 +39,53 @@ static inline int ext_hash(__u16 code) int register_external_interrupt(__u16 code, ext_int_handler_t handler) { - ext_int_info_t *p; - int index; - - p = kmalloc(sizeof(ext_int_info_t), GFP_ATOMIC); - if (p == NULL) - return -ENOMEM; - p->code = code; - p->handler = handler; - index = ext_hash(code); - p->next = ext_int_hash[index]; - ext_int_hash[index] = p; - return 0; -} - -int register_early_external_interrupt(__u16 code, ext_int_handler_t handler, - ext_int_info_t *p) -{ - int index; + struct ext_int_info *p; + int index; - if (p == NULL) - return -EINVAL; - p->code = code; - p->handler = handler; + p = kmalloc(sizeof(*p), GFP_ATOMIC); + if (!p) + return -ENOMEM; + p->code = code; + p->handler = handler; index = ext_hash(code); - p->next = ext_int_hash[index]; - ext_int_hash[index] = p; - return 0; + p->next = ext_int_hash[index]; + ext_int_hash[index] = p; + return 0; } +EXPORT_SYMBOL(register_external_interrupt); int unregister_external_interrupt(__u16 code, ext_int_handler_t handler) { - ext_int_info_t *p, *q; - int index; - - index = ext_hash(code); - q = NULL; - p = ext_int_hash[index]; - while (p != NULL) { - if (p->code == code && p->handler == handler) - break; - q = p; - p = p->next; - } - if (p == NULL) - return -ENOENT; - if (q != NULL) - q->next = p->next; - else - ext_int_hash[index] = p->next; - kfree(p); - return 0; -} - -int unregister_early_external_interrupt(__u16 code, ext_int_handler_t handler, - ext_int_info_t *p) -{ - ext_int_info_t *q; + struct ext_int_info *p, *q; int index; - if (p == NULL || p->code != code || p->handler != handler) - return -EINVAL; index = ext_hash(code); - q = ext_int_hash[index]; - if (p != q) { - while (q != NULL) { - if (q->next == p) - break; - q = q->next; - } - if (q == NULL) - return -ENOENT; + q = NULL; + p = ext_int_hash[index]; + while (p) { + if (p->code == code && p->handler == handler) + break; + q = p; + p = p->next; + } + if (!p) + return -ENOENT; + if (q) q->next = p->next; - } else + else ext_int_hash[index] = p->next; + kfree(p); return 0; } +EXPORT_SYMBOL(unregister_external_interrupt); void __irq_entry do_extint(struct pt_regs *regs, unsigned int ext_int_code, unsigned int param32, unsigned long param64) { struct pt_regs *old_regs; unsigned short code; - ext_int_info_t *p; - int index; + struct ext_int_info *p; + int index; code = (unsigned short) ext_int_code; old_regs = set_irq_regs(regs); @@ -132,7 +98,7 @@ void __irq_entry do_extint(struct pt_regs *regs, unsigned int ext_int_code, kstat_cpu(smp_processor_id()).irqs[EXTERNAL_INTERRUPT]++; if (code != 0x1004) __get_cpu_var(s390_idle).nohz_delay = 1; - index = ext_hash(code); + index = ext_hash(code); for (p = ext_int_hash[index]; p; p = p->next) { if (likely(p->code == code)) p->handler(ext_int_code, param32, param64); @@ -140,6 +106,3 @@ void __irq_entry do_extint(struct pt_regs *regs, unsigned int ext_int_code, irq_exit(); set_irq_regs(old_regs); } - -EXPORT_SYMBOL(register_external_interrupt); -EXPORT_SYMBOL(unregister_external_interrupt); diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c index ee7ac8b1178..abbb3c3c7aa 100644 --- a/arch/s390/kernel/signal.c +++ b/arch/s390/kernel/signal.c @@ -505,7 +505,7 @@ void do_signal(struct pt_regs *regs) * Let tracing know that we've done the handler setup. */ tracehook_signal_handler(signr, &info, &ka, regs, - current->thread.per_info.single_step); + test_thread_flag(TIF_SINGLE_STEP)); } return; } diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c index 94cf510b8fe..63a97db83f9 100644 --- a/arch/s390/kernel/smp.c +++ b/arch/s390/kernel/smp.c @@ -23,6 +23,7 @@ #define KMSG_COMPONENT "cpu" #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt +#include <linux/workqueue.h> #include <linux/module.h> #include <linux/init.h> #include <linux/mm.h> @@ -161,6 +162,7 @@ static void do_ext_call_interrupt(unsigned int ext_int_code, { unsigned long bits; + kstat_cpu(smp_processor_id()).irqs[EXTINT_IPI]++; /* * handle bit signal external calls * @@ -469,25 +471,25 @@ int __cpuinit start_secondary(void *cpuvoid) ipi_call_unlock(); /* Switch on interrupts */ local_irq_enable(); - /* Print info about this processor */ - print_cpu_info(); /* cpu_idle will call schedule for us */ cpu_idle(); return 0; } -static void __init smp_create_idle(unsigned int cpu) +struct create_idle { + struct work_struct work; + struct task_struct *idle; + struct completion done; + int cpu; +}; + +static void __cpuinit smp_fork_idle(struct work_struct *work) { - struct task_struct *p; + struct create_idle *c_idle; - /* - * don't care about the psw and regs settings since we'll never - * reschedule the forked task. - */ - p = fork_idle(cpu); - if (IS_ERR(p)) - panic("failed fork for CPU %u: %li", cpu, PTR_ERR(p)); - current_set[cpu] = p; + c_idle = container_of(work, struct create_idle, work); + c_idle->idle = fork_idle(c_idle->cpu); + complete(&c_idle->done); } static int __cpuinit smp_alloc_lowcore(int cpu) @@ -551,6 +553,7 @@ static void smp_free_lowcore(int cpu) int __cpuinit __cpu_up(unsigned int cpu) { struct _lowcore *cpu_lowcore; + struct create_idle c_idle; struct task_struct *idle; struct stack_frame *sf; u32 lowcore; @@ -558,6 +561,19 @@ int __cpuinit __cpu_up(unsigned int cpu) if (smp_cpu_state[cpu] != CPU_STATE_CONFIGURED) return -EIO; + idle = current_set[cpu]; + if (!idle) { + c_idle.done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done); + INIT_WORK_ONSTACK(&c_idle.work, smp_fork_idle); + c_idle.cpu = cpu; + schedule_work(&c_idle.work); + wait_for_completion(&c_idle.done); + if (IS_ERR(c_idle.idle)) + return PTR_ERR(c_idle.idle); + idle = c_idle.idle; + current_set[cpu] = c_idle.idle; + } + init_idle(idle, cpu); if (smp_alloc_lowcore(cpu)) return -ENOMEM; do { @@ -572,7 +588,6 @@ int __cpuinit __cpu_up(unsigned int cpu) while (sigp_p(lowcore, cpu, sigp_set_prefix) == sigp_busy) udelay(10); - idle = current_set[cpu]; cpu_lowcore = lowcore_ptr[cpu]; cpu_lowcore->kernel_stack = (unsigned long) task_stack_page(idle) + THREAD_SIZE; @@ -664,7 +679,6 @@ void __cpu_die(unsigned int cpu) udelay(10); smp_free_lowcore(cpu); atomic_dec(&init_mm.context.attach_count); - pr_info("Processor %d stopped\n", cpu); } void cpu_die(void) @@ -684,14 +698,12 @@ void __init smp_prepare_cpus(unsigned int max_cpus) #endif unsigned long async_stack, panic_stack; struct _lowcore *lowcore; - unsigned int cpu; smp_detect_cpus(); /* request the 0x1201 emergency signal external interrupt */ if (register_external_interrupt(0x1201, do_ext_call_interrupt) != 0) panic("Couldn't request external interrupt 0x1201"); - print_cpu_info(); /* Reallocate current lowcore, but keep its contents. */ lowcore = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); @@ -719,9 +731,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus) if (vdso_alloc_per_cpu(smp_processor_id(), &S390_lowcore)) BUG(); #endif - for_each_possible_cpu(cpu) - if (cpu != smp_processor_id()) - smp_create_idle(cpu); } void __init smp_prepare_boot_cpu(void) diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c index f754a6dc4f9..9e7b039458d 100644 --- a/arch/s390/kernel/time.c +++ b/arch/s390/kernel/time.c @@ -15,6 +15,7 @@ #define KMSG_COMPONENT "time" #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt +#include <linux/kernel_stat.h> #include <linux/errno.h> #include <linux/module.h> #include <linux/sched.h> @@ -37,6 +38,7 @@ #include <linux/clocksource.h> #include <linux/clockchips.h> #include <linux/gfp.h> +#include <linux/kprobes.h> #include <asm/uaccess.h> #include <asm/delay.h> #include <asm/s390_ext.h> @@ -60,7 +62,7 @@ static DEFINE_PER_CPU(struct clock_event_device, comparators); /* * Scheduler clock - returns current time in nanosec units. */ -unsigned long long notrace sched_clock(void) +unsigned long long notrace __kprobes sched_clock(void) { return (get_clock_monotonic() * 125) >> 9; } @@ -159,6 +161,7 @@ static void clock_comparator_interrupt(unsigned int ext_int_code, unsigned int param32, unsigned long param64) { + kstat_cpu(smp_processor_id()).irqs[EXTINT_CLK]++; if (S390_lowcore.clock_comparator == -1ULL) set_clock_comparator(S390_lowcore.clock_comparator); } @@ -169,6 +172,7 @@ static void stp_timing_alert(struct stp_irq_parm *); static void timing_alert_interrupt(unsigned int ext_int_code, unsigned int param32, unsigned long param64) { + kstat_cpu(smp_processor_id()).irqs[EXTINT_TLA]++; if (param32 & 0x00c40000) etr_timing_alert((struct etr_irq_parm *) ¶m32); if (param32 & 0x00038000) diff --git a/arch/s390/kernel/traps.c b/arch/s390/kernel/traps.c index 70640822621..5eb78dd584c 100644 --- a/arch/s390/kernel/traps.c +++ b/arch/s390/kernel/traps.c @@ -365,12 +365,10 @@ static inline void __user *get_psw_address(struct pt_regs *regs, ((regs->psw.addr - (pgm_int_code >> 16)) & PSW_ADDR_INSN); } -void __kprobes do_single_step(struct pt_regs *regs) +void __kprobes do_per_trap(struct pt_regs *regs) { - if (notify_die(DIE_SSTEP, "sstep", regs, 0, 0, - SIGTRAP) == NOTIFY_STOP){ + if (notify_die(DIE_SSTEP, "sstep", regs, 0, 0, SIGTRAP) == NOTIFY_STOP) return; - } if (tracehook_consider_fatal_signal(current, SIGTRAP)) force_sig(SIGTRAP, current); } @@ -451,8 +449,8 @@ static inline void do_fp_trap(struct pt_regs *regs, void __user *location, "floating point exception", regs, &si); } -static void illegal_op(struct pt_regs *regs, long pgm_int_code, - unsigned long trans_exc_code) +static void __kprobes illegal_op(struct pt_regs *regs, long pgm_int_code, + unsigned long trans_exc_code) { siginfo_t info; __u8 opcode[6]; @@ -688,7 +686,7 @@ static void space_switch_exception(struct pt_regs *regs, long pgm_int_code, do_trap(pgm_int_code, SIGILL, "space switch event", regs, &info); } -asmlinkage void kernel_stack_overflow(struct pt_regs * regs) +asmlinkage void __kprobes kernel_stack_overflow(struct pt_regs * regs) { bust_spinlocks(1); printk("Kernel stack overflow.\n"); @@ -733,5 +731,6 @@ void __init trap_init(void) pgm_check_table[0x15] = &operand_exception; pgm_check_table[0x1C] = &space_switch_exception; pgm_check_table[0x1D] = &hfp_sqrt_exception; - pfault_irq_init(); + /* Enable machine checks early. */ + local_mcck_enable(); } diff --git a/arch/s390/kernel/vtime.c b/arch/s390/kernel/vtime.c index 7eff9b7347c..1ccdf4d8aa8 100644 --- a/arch/s390/kernel/vtime.c +++ b/arch/s390/kernel/vtime.c @@ -20,6 +20,7 @@ #include <linux/rcupdate.h> #include <linux/posix-timers.h> #include <linux/cpu.h> +#include <linux/kprobes.h> #include <asm/s390_ext.h> #include <asm/timer.h> @@ -122,7 +123,7 @@ void account_system_vtime(struct task_struct *tsk) } EXPORT_SYMBOL_GPL(account_system_vtime); -void vtime_start_cpu(__u64 int_clock, __u64 enter_timer) +void __kprobes vtime_start_cpu(__u64 int_clock, __u64 enter_timer) { struct s390_idle_data *idle = &__get_cpu_var(s390_idle); struct vtimer_queue *vq = &__get_cpu_var(virt_cpu_timer); @@ -162,7 +163,7 @@ void vtime_start_cpu(__u64 int_clock, __u64 enter_timer) idle->sequence++; } -void vtime_stop_cpu(void) +void __kprobes vtime_stop_cpu(void) { struct s390_idle_data *idle = &__get_cpu_var(s390_idle); struct vtimer_queue *vq = &__get_cpu_var(virt_cpu_timer); @@ -323,6 +324,7 @@ static void do_cpu_timer_interrupt(unsigned int ext_int_code, struct list_head cb_list; /* the callback queue */ __u64 elapsed, next; + kstat_cpu(smp_processor_id()).irqs[EXTINT_TMR]++; INIT_LIST_HEAD(&cb_list); vq = &__get_cpu_var(virt_cpu_timer); diff --git a/arch/s390/kvm/Kconfig b/arch/s390/kvm/Kconfig index a7251580891..f66a1bdbb61 100644 --- a/arch/s390/kvm/Kconfig +++ b/arch/s390/kvm/Kconfig @@ -4,8 +4,8 @@ source "virt/kvm/Kconfig" menuconfig VIRTUALIZATION - bool "Virtualization" - default y + def_bool y + prompt "Virtualization" ---help--- Say Y here to get to see options for using your Linux host to run other operating systems inside virtual machines (guests). @@ -16,7 +16,8 @@ menuconfig VIRTUALIZATION if VIRTUALIZATION config KVM - tristate "Kernel-based Virtual Machine (KVM) support" + def_tristate y + prompt "Kernel-based Virtual Machine (KVM) support" depends on HAVE_KVM && EXPERIMENTAL select PREEMPT_NOTIFIERS select ANON_INODES diff --git a/arch/s390/lib/delay.c b/arch/s390/lib/delay.c index 7c37ec359ec..0f53110e1d0 100644 --- a/arch/s390/lib/delay.c +++ b/arch/s390/lib/delay.c @@ -47,7 +47,6 @@ static void __udelay_disabled(unsigned long long usecs) lockdep_on(); __ctl_load(cr0_saved, 0, 0); local_tick_enable(clock_saved); - set_clock_comparator(S390_lowcore.clock_comparator); } static void __udelay_enabled(unsigned long long usecs) @@ -70,7 +69,6 @@ static void __udelay_enabled(unsigned long long usecs) if (clock_saved) local_tick_enable(clock_saved); } while (get_clock() < end); - set_clock_comparator(S390_lowcore.clock_comparator); } /* diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c index fe5701e9efb..2c57806c085 100644 --- a/arch/s390/mm/fault.c +++ b/arch/s390/mm/fault.c @@ -10,6 +10,7 @@ * Copyright (C) 1995 Linus Torvalds */ +#include <linux/kernel_stat.h> #include <linux/perf_event.h> #include <linux/signal.h> #include <linux/sched.h> @@ -234,13 +235,13 @@ static noinline int signal_return(struct pt_regs *regs, long int_code, rc = __get_user(instruction, (u16 __user *) regs->psw.addr); if (!rc && instruction == 0x0a77) { - clear_tsk_thread_flag(current, TIF_SINGLE_STEP); + clear_tsk_thread_flag(current, TIF_PER_TRAP); if (is_compat_task()) sys32_sigreturn(); else sys_sigreturn(); } else if (!rc && instruction == 0x0aad) { - clear_tsk_thread_flag(current, TIF_SINGLE_STEP); + clear_tsk_thread_flag(current, TIF_PER_TRAP); if (is_compat_task()) sys32_rt_sigreturn(); else @@ -378,7 +379,7 @@ static inline int do_exception(struct pt_regs *regs, int access, * The instruction that caused the program check will * be repeated. Don't signal single step via SIGTRAP. */ - clear_tsk_thread_flag(tsk, TIF_SINGLE_STEP); + clear_tsk_thread_flag(tsk, TIF_PER_TRAP); fault = 0; out_up: up_read(&mm->mmap_sem); @@ -480,8 +481,7 @@ int __handle_fault(unsigned long uaddr, unsigned long pgm_int_code, int write) /* * 'pfault' pseudo page faults routines. */ -static ext_int_info_t ext_int_pfault; -static int pfault_disable = 0; +static int pfault_disable; static int __init nopfault(char *str) { @@ -543,6 +543,7 @@ static void pfault_interrupt(unsigned int ext_int_code, struct task_struct *tsk; __u16 subcode; + kstat_cpu(smp_processor_id()).irqs[EXTINT_PFL]++; /* * Get the external interruption subcode & pfault * initial/completion signal bit. VM stores this @@ -592,24 +593,28 @@ static void pfault_interrupt(unsigned int ext_int_code, } } -void __init pfault_irq_init(void) +static int __init pfault_irq_init(void) { - if (!MACHINE_IS_VM) - return; + int rc; + if (!MACHINE_IS_VM) + return 0; /* * Try to get pfault pseudo page faults going. */ - if (register_early_external_interrupt(0x2603, pfault_interrupt, - &ext_int_pfault) != 0) - panic("Couldn't request external interrupt 0x2603"); - + rc = register_external_interrupt(0x2603, pfault_interrupt); + if (rc) { + pfault_disable = 1; + return rc; + } if (pfault_init() == 0) - return; + return 0; /* Tough luck, no pfault. */ pfault_disable = 1; - unregister_early_external_interrupt(0x2603, pfault_interrupt, - &ext_int_pfault); + unregister_external_interrupt(0x2603, pfault_interrupt); + return 0; } +early_initcall(pfault_irq_init); + #endif diff --git a/arch/sh/boards/mach-sh03/rtc.c b/arch/sh/boards/mach-sh03/rtc.c index 1b200990500..f83ac7995d0 100644 --- a/arch/sh/boards/mach-sh03/rtc.c +++ b/arch/sh/boards/mach-sh03/rtc.c @@ -108,7 +108,7 @@ static int set_rtc_mmss(unsigned long nowtime) __raw_writeb(real_minutes % 10, RTC_MIN1); __raw_writeb(real_minutes / 10, RTC_MIN10); } else { - printk(KERN_WARNING + printk_once(KERN_NOTICE "set_rtc_mmss: can't update from %d to %d\n", cmos_minutes, real_minutes); retval = -1; diff --git a/arch/sh/drivers/push-switch.c b/arch/sh/drivers/push-switch.c index 7b42c247316..afc24556572 100644 --- a/arch/sh/drivers/push-switch.c +++ b/arch/sh/drivers/push-switch.c @@ -107,7 +107,7 @@ static int switch_drv_remove(struct platform_device *pdev) device_remove_file(&pdev->dev, &dev_attr_switch); platform_set_drvdata(pdev, NULL); - flush_scheduled_work(); + flush_work_sync(&psw->work); del_timer_sync(&psw->debounce); free_irq(irq, pdev); diff --git a/arch/sh/include/mach-common/mach/romimage.h b/arch/sh/include/mach-common/mach/romimage.h index 08fb42269ec..3670455faaa 100644 --- a/arch/sh/include/mach-common/mach/romimage.h +++ b/arch/sh/include/mach-common/mach/romimage.h @@ -4,7 +4,7 @@ #else /* __ASSEMBLY__ */ -extern inline void mmcif_update_progress(int nr) +static inline void mmcif_update_progress(int nr) { } diff --git a/arch/sh/include/mach-ecovec24/mach/romimage.h b/arch/sh/include/mach-ecovec24/mach/romimage.h index 1dcf5e6c8d8..d63ef51ec18 100644 --- a/arch/sh/include/mach-ecovec24/mach/romimage.h +++ b/arch/sh/include/mach-ecovec24/mach/romimage.h @@ -35,7 +35,7 @@ #define HIZCRA 0xa4050158 #define PGDR 0xa405012c -extern inline void mmcif_update_progress(int nr) +static inline void mmcif_update_progress(int nr) { /* disable Hi-Z for LED pins */ __raw_writew(__raw_readw(HIZCRA) & ~(1 << 1), HIZCRA); diff --git a/arch/sh/include/mach-kfr2r09/mach/romimage.h b/arch/sh/include/mach-kfr2r09/mach/romimage.h index 976256a323f..7a883167c84 100644 --- a/arch/sh/include/mach-kfr2r09/mach/romimage.h +++ b/arch/sh/include/mach-kfr2r09/mach/romimage.h @@ -23,7 +23,7 @@ #else /* __ASSEMBLY__ */ -extern inline void mmcif_update_progress(int nr) +static inline void mmcif_update_progress(int nr) { } diff --git a/arch/sparc/kernel/auxio_32.c b/arch/sparc/kernel/auxio_32.c index 35f48837871..8505e0ac78b 100644 --- a/arch/sparc/kernel/auxio_32.c +++ b/arch/sparc/kernel/auxio_32.c @@ -121,7 +121,7 @@ void __init auxio_power_probe(void) node = prom_searchsiblings(node, "obio"); node = prom_getchild(node); node = prom_searchsiblings(node, "power"); - if (node == 0 || node == -1) + if (node == 0 || (s32)node == -1) return; /* Map the power control register. */ diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c index e447938d39c..0dc714fa23d 100644 --- a/arch/sparc/kernel/cpu.c +++ b/arch/sparc/kernel/cpu.c @@ -375,5 +375,5 @@ static int __init cpu_type_probe(void) return 0; } -arch_initcall(cpu_type_probe); +early_initcall(cpu_type_probe); #endif diff --git a/arch/sparc/kernel/pcr.c b/arch/sparc/kernel/pcr.c index b87873c0e8e..ae96cf52a95 100644 --- a/arch/sparc/kernel/pcr.c +++ b/arch/sparc/kernel/pcr.c @@ -168,4 +168,4 @@ out_unregister: return err; } -arch_initcall(pcr_arch_init); +early_initcall(pcr_arch_init); diff --git a/arch/sparc/kernel/starfire.c b/arch/sparc/kernel/starfire.c index a4446c0fb7a..82281a566bb 100644 --- a/arch/sparc/kernel/starfire.c +++ b/arch/sparc/kernel/starfire.c @@ -24,7 +24,7 @@ int this_is_starfire = 0; void check_if_starfire(void) { phandle ssnode = prom_finddevice("/ssp-serial"); - if (ssnode != 0 && ssnode != -1) + if (ssnode != 0 && (s32)ssnode != -1) this_is_starfire = 1; } diff --git a/arch/sparc/prom/init_32.c b/arch/sparc/prom/init_32.c index d342dba4dd5..0a601b30063 100644 --- a/arch/sparc/prom/init_32.c +++ b/arch/sparc/prom/init_32.c @@ -60,7 +60,7 @@ void __init prom_init(struct linux_romvec *rp) prom_nodeops = romvec->pv_nodeops; prom_root_node = prom_getsibling(0); - if((prom_root_node == 0) || (prom_root_node == -1)) + if ((prom_root_node == 0) || ((s32)prom_root_node == -1)) prom_halt(); if((((unsigned long) prom_nodeops) == 0) || diff --git a/arch/sparc/prom/init_64.c b/arch/sparc/prom/init_64.c index 9c6ac4b81de..5016c5e2057 100644 --- a/arch/sparc/prom/init_64.c +++ b/arch/sparc/prom/init_64.c @@ -35,13 +35,13 @@ void __init prom_init(void *cif_handler, void *cif_stack) prom_cif_init(cif_handler, cif_stack); prom_chosen_node = prom_finddevice(prom_chosen_path); - if (!prom_chosen_node || prom_chosen_node == -1) + if (!prom_chosen_node || (s32)prom_chosen_node == -1) prom_halt(); prom_stdout = prom_getint(prom_chosen_node, "stdout"); node = prom_finddevice("/openprom"); - if (!node || node == -1) + if (!node || (s32)node == -1) prom_halt(); prom_getstring(node, "version", prom_version, sizeof(prom_version)); diff --git a/arch/sparc/prom/tree_32.c b/arch/sparc/prom/tree_32.c index bc8e4cb87a6..f30e8d038f0 100644 --- a/arch/sparc/prom/tree_32.c +++ b/arch/sparc/prom/tree_32.c @@ -40,11 +40,11 @@ phandle prom_getchild(phandle node) { phandle cnode; - if (node == -1) + if ((s32)node == -1) return 0; cnode = __prom_getchild(node); - if (cnode == 0 || cnode == -1) + if (cnode == 0 || (s32)cnode == -1) return 0; return cnode; @@ -72,11 +72,11 @@ phandle prom_getsibling(phandle node) { phandle sibnode; - if (node == -1) + if ((s32)node == -1) return 0; sibnode = __prom_getsibling(node); - if (sibnode == 0 || sibnode == -1) + if (sibnode == 0 || (s32)sibnode == -1) return 0; return sibnode; @@ -219,7 +219,7 @@ static char *__prom_nextprop(phandle node, char * oprop) */ char *prom_nextprop(phandle node, char *oprop, char *buffer) { - if (node == 0 || node == -1) + if (node == 0 || (s32)node == -1) return ""; return __prom_nextprop(node, oprop); @@ -253,7 +253,7 @@ phandle prom_finddevice(char *name) if (d != s + 3 && (!*d || *d == '/') && d <= s + 3 + 8) { node2 = node; - while (node2 && node2 != -1) { + while (node2 && (s32)node2 != -1) { if (prom_getproperty (node2, "reg", (char *)reg, sizeof (reg)) > 0) { if (which_io == reg[0].which_io && phys_addr == reg[0].phys_addr) { node = node2; @@ -261,7 +261,7 @@ phandle prom_finddevice(char *name) } } node2 = prom_getsibling(node2); - if (!node2 || node2 == -1) + if (!node2 || (s32)node2 == -1) break; node2 = prom_searchsiblings(prom_getsibling(node2), nbuf); } @@ -303,6 +303,7 @@ phandle prom_inst2pkg(int inst) node = (*romvec->pv_v2devops.v2_inst2pkg)(inst); restore_current(); spin_unlock_irqrestore(&prom_lock, flags); - if (node == -1) return 0; + if ((s32)node == -1) + return 0; return node; } diff --git a/arch/sparc/prom/tree_64.c b/arch/sparc/prom/tree_64.c index d9366004837..92204c3800b 100644 --- a/arch/sparc/prom/tree_64.c +++ b/arch/sparc/prom/tree_64.c @@ -43,10 +43,10 @@ inline phandle prom_getchild(phandle node) { phandle cnode; - if (node == -1) + if ((s32)node == -1) return 0; cnode = __prom_getchild(node); - if (cnode == -1) + if ((s32)cnode == -1) return 0; return cnode; } @@ -56,10 +56,10 @@ inline phandle prom_getparent(phandle node) { phandle cnode; - if (node == -1) + if ((s32)node == -1) return 0; cnode = prom_node_to_node("parent", node); - if (cnode == -1) + if ((s32)cnode == -1) return 0; return cnode; } @@ -76,10 +76,10 @@ inline phandle prom_getsibling(phandle node) { phandle sibnode; - if (node == -1) + if ((s32)node == -1) return 0; sibnode = __prom_getsibling(node); - if (sibnode == -1) + if ((s32)sibnode == -1) return 0; return sibnode; @@ -240,7 +240,7 @@ inline char *prom_firstprop(phandle node, char *buffer) unsigned long args[7]; *buffer = 0; - if (node == -1) + if ((s32)node == -1) return buffer; args[0] = (unsigned long) prom_nextprop_name; @@ -266,7 +266,7 @@ inline char *prom_nextprop(phandle node, const char *oprop, char *buffer) unsigned long args[7]; char buf[32]; - if (node == -1) { + if ((s32)node == -1) { *buffer = 0; return buffer; } @@ -369,7 +369,7 @@ inline phandle prom_inst2pkg(int inst) p1275_cmd_direct(args); node = (int) args[4]; - if (node == -1) + if ((s32)node == -1) return 0; return node; } diff --git a/arch/um/Kconfig.um b/arch/um/Kconfig.um index 50d6aa20c35..f8d1d0d47fe 100644 --- a/arch/um/Kconfig.um +++ b/arch/um/Kconfig.um @@ -131,7 +131,7 @@ config NR_CPUS config HIGHMEM bool "Highmem support (EXPERIMENTAL)" - depends on !64BIT && EXPERIMENTAL + depends on !64BIT && BROKEN default n help This was used to allow UML to run with big amounts of memory. diff --git a/arch/um/drivers/line.c b/arch/um/drivers/line.c index 1664cce7b0a..050e4ddbbb6 100644 --- a/arch/um/drivers/line.c +++ b/arch/um/drivers/line.c @@ -821,12 +821,12 @@ void register_winch_irq(int fd, int tty_fd, int pid, struct tty_struct *tty, static void unregister_winch(struct tty_struct *tty) { - struct list_head *ele; + struct list_head *ele, *next; struct winch *winch; spin_lock(&winch_handler_lock); - list_for_each(ele, &winch_handlers) { + list_for_each_safe(ele, next, &winch_handlers) { winch = list_entry(ele, struct winch, list); if (winch->tty == tty) { free_winch(winch, 1); diff --git a/arch/um/drivers/mmapper_kern.c b/arch/um/drivers/mmapper_kern.c index 8501e7d0015..7e0619c2c2c 100644 --- a/arch/um/drivers/mmapper_kern.c +++ b/arch/um/drivers/mmapper_kern.c @@ -37,13 +37,7 @@ static ssize_t mmapper_write(struct file *file, const char __user *buf, if (*ppos > mmapper_size) return -EINVAL; - if (count > mmapper_size - *ppos) - count = mmapper_size - *ppos; - - if (copy_from_user(&v_buf[*ppos], buf, count)) - return -EFAULT; - - return count; + return simple_write_to_buffer(v_buf, mmapper_size, ppos, buf, count); } static long mmapper_ioctl(struct file *file, unsigned int cmd, unsigned long arg) @@ -137,3 +131,4 @@ module_exit(mmapper_exit); MODULE_AUTHOR("Greg Lonnon <glonnon@ridgerun.com>"); MODULE_DESCRIPTION("DSPLinux simulator mmapper driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index b6fccb07123..6e15fa9455e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -51,6 +51,7 @@ config X86 select HAVE_KERNEL_GZIP select HAVE_KERNEL_BZIP2 select HAVE_KERNEL_LZMA + select HAVE_KERNEL_XZ select HAVE_KERNEL_LZO select HAVE_HW_BREAKPOINT select HAVE_MIXED_BREAKPOINTS_REGS @@ -65,6 +66,7 @@ config X86 select HAVE_SPARSE_IRQ select GENERIC_IRQ_PROBE select GENERIC_PENDING_IRQ if SMP + select USE_GENERIC_SMP_HELPERS if SMP config INSTRUCTION_DECODER def_bool (KPROBES || PERF_EVENTS) @@ -203,10 +205,6 @@ config HAVE_INTEL_TXT def_bool y depends on EXPERIMENTAL && DMAR && ACPI -config USE_GENERIC_SMP_HELPERS - def_bool y - depends on SMP - config X86_32_SMP def_bool y depends on X86_32 && SMP diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 2ac9069890c..15588a0ef46 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -310,6 +310,9 @@ config X86_INTERNODE_CACHE_SHIFT config X86_CMPXCHG def_bool X86_64 || (X86_32 && !M386) +config CMPXCHG_LOCAL + def_bool X86_64 || (X86_32 && !M386) + config X86_L1_CACHE_SHIFT int default "7" if MPENTIUM4 || MPSC diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile index 0c229551eea..09664efb9ce 100644 --- a/arch/x86/boot/compressed/Makefile +++ b/arch/x86/boot/compressed/Makefile @@ -4,7 +4,7 @@ # create a compressed vmlinux image from the original vmlinux # -targets := vmlinux.lds vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.lzo head_$(BITS).o misc.o string.o cmdline.o early_serial_console.o piggy.o +targets := vmlinux.lds vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.xz vmlinux.bin.lzo head_$(BITS).o misc.o string.o cmdline.o early_serial_console.o piggy.o KBUILD_CFLAGS := -m$(BITS) -D__KERNEL__ $(LINUX_INCLUDE) -O2 KBUILD_CFLAGS += -fno-strict-aliasing -fPIC @@ -49,12 +49,15 @@ $(obj)/vmlinux.bin.bz2: $(vmlinux.bin.all-y) FORCE $(call if_changed,bzip2) $(obj)/vmlinux.bin.lzma: $(vmlinux.bin.all-y) FORCE $(call if_changed,lzma) +$(obj)/vmlinux.bin.xz: $(vmlinux.bin.all-y) FORCE + $(call if_changed,xzkern) $(obj)/vmlinux.bin.lzo: $(vmlinux.bin.all-y) FORCE $(call if_changed,lzo) suffix-$(CONFIG_KERNEL_GZIP) := gz suffix-$(CONFIG_KERNEL_BZIP2) := bz2 suffix-$(CONFIG_KERNEL_LZMA) := lzma +suffix-$(CONFIG_KERNEL_XZ) := xz suffix-$(CONFIG_KERNEL_LZO) := lzo quiet_cmd_mkpiggy = MKPIGGY $@ diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/misc.c index 325c05294fc..3a19d04cebe 100644 --- a/arch/x86/boot/compressed/misc.c +++ b/arch/x86/boot/compressed/misc.c @@ -139,6 +139,10 @@ static int lines, cols; #include "../../../../lib/decompress_unlzma.c" #endif +#ifdef CONFIG_KERNEL_XZ +#include "../../../../lib/decompress_unxz.c" +#endif + #ifdef CONFIG_KERNEL_LZO #include "../../../../lib/decompress_unlzo.c" #endif diff --git a/arch/x86/boot/compressed/mkpiggy.c b/arch/x86/boot/compressed/mkpiggy.c index 5c228129d17..646aa78ba5f 100644 --- a/arch/x86/boot/compressed/mkpiggy.c +++ b/arch/x86/boot/compressed/mkpiggy.c @@ -74,7 +74,7 @@ int main(int argc, char *argv[]) offs = (olen > ilen) ? olen - ilen : 0; offs += olen >> 12; /* Add 8 bytes for each 32K block */ - offs += 32*1024 + 18; /* Add 32K + 18 bytes slack */ + offs += 64*1024 + 128; /* Add 64K + 128 bytes slack */ offs = (offs+4095) & ~4095; /* Round to a 4K boundary */ printf(".section \".rodata..compressed\",\"a\",@progbits\n"); diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index 55d106b5e31..211ca3f7fd1 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -185,17 +185,16 @@ struct bootnode; #ifdef CONFIG_ACPI_NUMA extern int acpi_numa; -extern int acpi_get_nodes(struct bootnode *physnodes); +extern void acpi_get_nodes(struct bootnode *physnodes, unsigned long start, + unsigned long end); extern int acpi_scan_nodes(unsigned long start, unsigned long end); #define NR_NODE_MEMBLKS (MAX_NUMNODES*2) + +#ifdef CONFIG_NUMA_EMU extern void acpi_fake_nodes(const struct bootnode *fake_nodes, int num_nodes); -#else -static inline void acpi_fake_nodes(const struct bootnode *fake_nodes, - int num_nodes) -{ -} #endif +#endif /* CONFIG_ACPI_NUMA */ #define acpi_unlazy_tlb(x) leave_mm(x) diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h index 6aee50d655d..64dc82ee19f 100644 --- a/arch/x86/include/asm/amd_nb.h +++ b/arch/x86/include/asm/amd_nb.h @@ -3,16 +3,27 @@ #include <linux/pci.h> +struct amd_nb_bus_dev_range { + u8 bus; + u8 dev_base; + u8 dev_limit; +}; + extern struct pci_device_id amd_nb_misc_ids[]; +extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[]; struct bootnode; extern int early_is_amd_nb(u32 value); extern int amd_cache_northbridges(void); extern void amd_flush_garts(void); -extern int amd_get_nodes(struct bootnode *nodes); extern int amd_numa_init(unsigned long start_pfn, unsigned long end_pfn); extern int amd_scan_nodes(void); +#ifdef CONFIG_NUMA_EMU +extern void amd_fake_nodes(const struct bootnode *nodes, int nr_nodes); +extern void amd_get_nodes(struct bootnode *nodes); +#endif + struct amd_northbridge { struct pci_dev *misc; }; diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index cf12007796d..5e3969c36d7 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -234,6 +234,7 @@ extern void init_bsp_APIC(void); extern void setup_local_APIC(void); extern void end_local_APIC_setup(void); extern void init_apic_mappings(void); +void register_lapic_address(unsigned long address); extern void setup_boot_APIC_clock(void); extern void setup_secondary_APIC_clock(void); extern int APIC_init_uniprocessor(void); @@ -244,7 +245,6 @@ extern int apic_force_enable(void); * On 32bit this is mach-xxx local */ #ifdef CONFIG_X86_64 -extern void early_init_lapic_mapping(void); extern int apic_is_clustered_box(void); #else static inline int apic_is_clustered_box(void) diff --git a/arch/x86/include/asm/boot.h b/arch/x86/include/asm/boot.h index 3b62ab56c7a..5e1a2eef3e7 100644 --- a/arch/x86/include/asm/boot.h +++ b/arch/x86/include/asm/boot.h @@ -32,11 +32,7 @@ #define BOOT_HEAP_SIZE 0x400000 #else /* !CONFIG_KERNEL_BZIP2 */ -#ifdef CONFIG_X86_64 -#define BOOT_HEAP_SIZE 0x7000 -#else -#define BOOT_HEAP_SIZE 0x4000 -#endif +#define BOOT_HEAP_SIZE 0x8000 #endif /* !CONFIG_KERNEL_BZIP2 */ diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h index b81002f2361..078ad0caefc 100644 --- a/arch/x86/include/asm/debugreg.h +++ b/arch/x86/include/asm/debugreg.h @@ -94,7 +94,7 @@ static inline void hw_breakpoint_disable(void) static inline int hw_breakpoint_active(void) { - return __get_cpu_var(cpu_dr7) & DR_GLOBAL_ENABLE_MASK; + return __this_cpu_read(cpu_dr7) & DR_GLOBAL_ENABLE_MASK; } extern void aout_dump_debugregs(struct user *dump); diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h index 0141b234406..4729b2b6311 100644 --- a/arch/x86/include/asm/fixmap.h +++ b/arch/x86/include/asm/fixmap.h @@ -116,11 +116,11 @@ enum fixed_addresses { #endif FIX_TEXT_POKE1, /* reserve 2 pages for text_poke() */ FIX_TEXT_POKE0, /* first page is last, because allocation is backward */ - __end_of_permanent_fixed_addresses, - #ifdef CONFIG_X86_MRST FIX_LNW_VRTC, #endif + __end_of_permanent_fixed_addresses, + /* * 256 temporary boot-time mappings, used by early_ioremap(), * before ioremap() is functional. diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h index 49dbfdfa50f..91d915a6525 100644 --- a/arch/x86/include/asm/gpio.h +++ b/arch/x86/include/asm/gpio.h @@ -38,12 +38,9 @@ static inline int gpio_cansleep(unsigned int gpio) return __gpio_cansleep(gpio); } -/* - * Not implemented, yet. - */ static inline int gpio_to_irq(unsigned int gpio) { - return -ENOSYS; + return __gpio_to_irq(gpio); } static inline int irq_to_gpio(unsigned int irq) diff --git a/arch/x86/include/asm/hypervisor.h b/arch/x86/include/asm/hypervisor.h index ff2546ce717..7a15153c675 100644 --- a/arch/x86/include/asm/hypervisor.h +++ b/arch/x86/include/asm/hypervisor.h @@ -20,6 +20,9 @@ #ifndef _ASM_X86_HYPERVISOR_H #define _ASM_X86_HYPERVISOR_H +#include <asm/kvm_para.h> +#include <asm/xen/hypervisor.h> + extern void init_hypervisor(struct cpuinfo_x86 *c); extern void init_hypervisor_platform(void); @@ -47,4 +50,13 @@ extern const struct hypervisor_x86 x86_hyper_vmware; extern const struct hypervisor_x86 x86_hyper_ms_hyperv; extern const struct hypervisor_x86 x86_hyper_xen_hvm; +static inline bool hypervisor_x2apic_available(void) +{ + if (kvm_para_available()) + return true; + if (xen_x2apic_para_available()) + return true; + return false; +} + #endif diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h index 0c5ca4e30d7..f327d386d6c 100644 --- a/arch/x86/include/asm/io_apic.h +++ b/arch/x86/include/asm/io_apic.h @@ -169,6 +169,7 @@ extern void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries); extern int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries); extern int get_nr_irqs_gsi(void); + extern void setup_ioapic_ids_from_mpc(void); extern void setup_ioapic_ids_from_mpc_nocheck(void); @@ -183,6 +184,8 @@ int mp_find_ioapic_pin(int ioapic, u32 gsi); void __init mp_register_ioapic(int id, u32 address, u32 gsi_base); extern void __init pre_init_apic_IRQ0(void); +extern void mp_save_irq(struct mpc_intsrc *m); + #else /* !CONFIG_X86_IO_APIC */ #define io_apic_assign_pci_irqs 0 diff --git a/arch/x86/include/asm/kdebug.h b/arch/x86/include/asm/kdebug.h index f23eb252846..ca242d35e87 100644 --- a/arch/x86/include/asm/kdebug.h +++ b/arch/x86/include/asm/kdebug.h @@ -18,7 +18,6 @@ enum die_val { DIE_TRAP, DIE_GPF, DIE_CALL, - DIE_NMI_IPI, DIE_PAGE_FAULT, DIE_NMIUNKNOWN, }; diff --git a/arch/x86/include/asm/mach_traps.h b/arch/x86/include/asm/mach_traps.h index f7920601e47..72a8b52e7df 100644 --- a/arch/x86/include/asm/mach_traps.h +++ b/arch/x86/include/asm/mach_traps.h @@ -7,9 +7,19 @@ #include <asm/mc146818rtc.h> +#define NMI_REASON_PORT 0x61 + +#define NMI_REASON_SERR 0x80 +#define NMI_REASON_IOCHK 0x40 +#define NMI_REASON_MASK (NMI_REASON_SERR | NMI_REASON_IOCHK) + +#define NMI_REASON_CLEAR_SERR 0x04 +#define NMI_REASON_CLEAR_IOCHK 0x08 +#define NMI_REASON_CLEAR_MASK 0x0f + static inline unsigned char get_nmi_reason(void) { - return inb(0x61); + return inb(NMI_REASON_PORT); } static inline void reassert_nmi(void) diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h index c4021b95351..c76f5b92b84 100644 --- a/arch/x86/include/asm/nmi.h +++ b/arch/x86/include/asm/nmi.h @@ -23,6 +23,26 @@ void arch_trigger_all_cpu_backtrace(void); #define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace #endif +/* + * Define some priorities for the nmi notifier call chain. + * + * Create a local nmi bit that has a higher priority than + * external nmis, because the local ones are more frequent. + * + * Also setup some default high/normal/low settings for + * subsystems to registers with. Using 4 bits to seperate + * the priorities. This can go alot higher if needed be. + */ + +#define NMI_LOCAL_SHIFT 16 /* randomly picked */ +#define NMI_LOCAL_BIT (1ULL << NMI_LOCAL_SHIFT) +#define NMI_HIGH_PRIOR (1ULL << 8) +#define NMI_NORMAL_PRIOR (1ULL << 4) +#define NMI_LOW_PRIOR (1ULL << 0) +#define NMI_LOCAL_HIGH_PRIOR (NMI_LOCAL_BIT | NMI_HIGH_PRIOR) +#define NMI_LOCAL_NORMAL_PRIOR (NMI_LOCAL_BIT | NMI_NORMAL_PRIOR) +#define NMI_LOCAL_LOW_PRIOR (NMI_LOCAL_BIT | NMI_LOW_PRIOR) + void stop_nmi(void); void restart_nmi(void); diff --git a/arch/x86/include/asm/numa_64.h b/arch/x86/include/asm/numa_64.h index 823e070e7c2..5ae87285a50 100644 --- a/arch/x86/include/asm/numa_64.h +++ b/arch/x86/include/asm/numa_64.h @@ -38,7 +38,7 @@ extern void __cpuinit numa_add_cpu(int cpu); extern void __cpuinit numa_remove_cpu(int cpu); #ifdef CONFIG_NUMA_EMU -#define FAKE_NODE_MIN_SIZE ((u64)64 << 20) +#define FAKE_NODE_MIN_SIZE ((u64)32 << 20) #define FAKE_NODE_MIN_HASH_MASK (~(FAKE_NODE_MIN_SIZE - 1UL)) #endif /* CONFIG_NUMA_EMU */ #else diff --git a/arch/x86/include/asm/olpc.h b/arch/x86/include/asm/olpc.h index 42a978c0c1b..f482010350f 100644 --- a/arch/x86/include/asm/olpc.h +++ b/arch/x86/include/asm/olpc.h @@ -107,10 +107,14 @@ extern int olpc_ec_mask_unset(uint8_t bits); /* GPIO assignments */ #define OLPC_GPIO_MIC_AC 1 -#define OLPC_GPIO_DCON_IRQ geode_gpio(7) +#define OLPC_GPIO_DCON_STAT0 5 +#define OLPC_GPIO_DCON_STAT1 6 +#define OLPC_GPIO_DCON_IRQ 7 #define OLPC_GPIO_THRM_ALRM geode_gpio(10) -#define OLPC_GPIO_SMB_CLK geode_gpio(14) -#define OLPC_GPIO_SMB_DATA geode_gpio(15) +#define OLPC_GPIO_DCON_LOAD 11 +#define OLPC_GPIO_DCON_BLANK 12 +#define OLPC_GPIO_SMB_CLK 14 +#define OLPC_GPIO_SMB_DATA 15 #define OLPC_GPIO_WORKAUX geode_gpio(24) #define OLPC_GPIO_LID geode_gpio(26) #define OLPC_GPIO_ECSCI geode_gpio(27) diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h index f899e01a8ac..8ee45167e81 100644 --- a/arch/x86/include/asm/percpu.h +++ b/arch/x86/include/asm/percpu.h @@ -230,6 +230,125 @@ do { \ }) /* + * Add return operation + */ +#define percpu_add_return_op(var, val) \ +({ \ + typeof(var) paro_ret__ = val; \ + switch (sizeof(var)) { \ + case 1: \ + asm("xaddb %0, "__percpu_arg(1) \ + : "+q" (paro_ret__), "+m" (var) \ + : : "memory"); \ + break; \ + case 2: \ + asm("xaddw %0, "__percpu_arg(1) \ + : "+r" (paro_ret__), "+m" (var) \ + : : "memory"); \ + break; \ + case 4: \ + asm("xaddl %0, "__percpu_arg(1) \ + : "+r" (paro_ret__), "+m" (var) \ + : : "memory"); \ + break; \ + case 8: \ + asm("xaddq %0, "__percpu_arg(1) \ + : "+re" (paro_ret__), "+m" (var) \ + : : "memory"); \ + break; \ + default: __bad_percpu_size(); \ + } \ + paro_ret__ += val; \ + paro_ret__; \ +}) + +/* + * xchg is implemented using cmpxchg without a lock prefix. xchg is + * expensive due to the implied lock prefix. The processor cannot prefetch + * cachelines if xchg is used. + */ +#define percpu_xchg_op(var, nval) \ +({ \ + typeof(var) pxo_ret__; \ + typeof(var) pxo_new__ = (nval); \ + switch (sizeof(var)) { \ + case 1: \ + asm("\n1:mov "__percpu_arg(1)",%%al" \ + "\n\tcmpxchgb %2, "__percpu_arg(1) \ + "\n\tjnz 1b" \ + : "=a" (pxo_ret__), "+m" (var) \ + : "q" (pxo_new__) \ + : "memory"); \ + break; \ + case 2: \ + asm("\n1:mov "__percpu_arg(1)",%%ax" \ + "\n\tcmpxchgw %2, "__percpu_arg(1) \ + "\n\tjnz 1b" \ + : "=a" (pxo_ret__), "+m" (var) \ + : "r" (pxo_new__) \ + : "memory"); \ + break; \ + case 4: \ + asm("\n1:mov "__percpu_arg(1)",%%eax" \ + "\n\tcmpxchgl %2, "__percpu_arg(1) \ + "\n\tjnz 1b" \ + : "=a" (pxo_ret__), "+m" (var) \ + : "r" (pxo_new__) \ + : "memory"); \ + break; \ + case 8: \ + asm("\n1:mov "__percpu_arg(1)",%%rax" \ + "\n\tcmpxchgq %2, "__percpu_arg(1) \ + "\n\tjnz 1b" \ + : "=a" (pxo_ret__), "+m" (var) \ + : "r" (pxo_new__) \ + : "memory"); \ + break; \ + default: __bad_percpu_size(); \ + } \ + pxo_ret__; \ +}) + +/* + * cmpxchg has no such implied lock semantics as a result it is much + * more efficient for cpu local operations. + */ +#define percpu_cmpxchg_op(var, oval, nval) \ +({ \ + typeof(var) pco_ret__; \ + typeof(var) pco_old__ = (oval); \ + typeof(var) pco_new__ = (nval); \ + switch (sizeof(var)) { \ + case 1: \ + asm("cmpxchgb %2, "__percpu_arg(1) \ + : "=a" (pco_ret__), "+m" (var) \ + : "q" (pco_new__), "0" (pco_old__) \ + : "memory"); \ + break; \ + case 2: \ + asm("cmpxchgw %2, "__percpu_arg(1) \ + : "=a" (pco_ret__), "+m" (var) \ + : "r" (pco_new__), "0" (pco_old__) \ + : "memory"); \ + break; \ + case 4: \ + asm("cmpxchgl %2, "__percpu_arg(1) \ + : "=a" (pco_ret__), "+m" (var) \ + : "r" (pco_new__), "0" (pco_old__) \ + : "memory"); \ + break; \ + case 8: \ + asm("cmpxchgq %2, "__percpu_arg(1) \ + : "=a" (pco_ret__), "+m" (var) \ + : "r" (pco_new__), "0" (pco_old__) \ + : "memory"); \ + break; \ + default: __bad_percpu_size(); \ + } \ + pco_ret__; \ +}) + +/* * percpu_read() makes gcc load the percpu variable every time it is * accessed while percpu_read_stable() allows the value to be cached. * percpu_read_stable() is more efficient and can be used if its value @@ -267,6 +386,12 @@ do { \ #define __this_cpu_xor_1(pcp, val) percpu_to_op("xor", (pcp), val) #define __this_cpu_xor_2(pcp, val) percpu_to_op("xor", (pcp), val) #define __this_cpu_xor_4(pcp, val) percpu_to_op("xor", (pcp), val) +/* + * Generic fallback operations for __this_cpu_xchg_[1-4] are okay and much + * faster than an xchg with forced lock semantics. + */ +#define __this_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval) +#define __this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) #define this_cpu_read_1(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) #define this_cpu_read_2(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) @@ -286,6 +411,11 @@ do { \ #define this_cpu_xor_1(pcp, val) percpu_to_op("xor", (pcp), val) #define this_cpu_xor_2(pcp, val) percpu_to_op("xor", (pcp), val) #define this_cpu_xor_4(pcp, val) percpu_to_op("xor", (pcp), val) +#define this_cpu_xchg_1(pcp, nval) percpu_xchg_op(pcp, nval) +#define this_cpu_xchg_2(pcp, nval) percpu_xchg_op(pcp, nval) +#define this_cpu_xchg_4(pcp, nval) percpu_xchg_op(pcp, nval) +#define this_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval) +#define this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) #define irqsafe_cpu_add_1(pcp, val) percpu_add_op((pcp), val) #define irqsafe_cpu_add_2(pcp, val) percpu_add_op((pcp), val) @@ -299,6 +429,31 @@ do { \ #define irqsafe_cpu_xor_1(pcp, val) percpu_to_op("xor", (pcp), val) #define irqsafe_cpu_xor_2(pcp, val) percpu_to_op("xor", (pcp), val) #define irqsafe_cpu_xor_4(pcp, val) percpu_to_op("xor", (pcp), val) +#define irqsafe_cpu_xchg_1(pcp, nval) percpu_xchg_op(pcp, nval) +#define irqsafe_cpu_xchg_2(pcp, nval) percpu_xchg_op(pcp, nval) +#define irqsafe_cpu_xchg_4(pcp, nval) percpu_xchg_op(pcp, nval) +#define irqsafe_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval) +#define irqsafe_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) + +#ifndef CONFIG_M386 +#define __this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val) +#define __this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val) +#define __this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val) +#define __this_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) +#define __this_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) +#define __this_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) + +#define this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val) +#define this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val) +#define this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val) +#define this_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) +#define this_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) +#define this_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) + +#define irqsafe_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) +#define irqsafe_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) +#define irqsafe_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) +#endif /* !CONFIG_M386 */ /* * Per cpu atomic 64 bit operations are only available under 64 bit. @@ -311,6 +466,7 @@ do { \ #define __this_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val) #define __this_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val) #define __this_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val) +#define __this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val) #define this_cpu_read_8(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) #define this_cpu_write_8(pcp, val) percpu_to_op("mov", (pcp), val) @@ -318,12 +474,12 @@ do { \ #define this_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val) #define this_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val) #define this_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val) +#define this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val) #define irqsafe_cpu_add_8(pcp, val) percpu_add_op((pcp), val) #define irqsafe_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val) #define irqsafe_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val) #define irqsafe_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val) - #endif /* This is not atomic against other CPUs -- CPU preemption needs to be off */ diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h index 295e2ff18a6..e2f6a99f14a 100644 --- a/arch/x86/include/asm/perf_event_p4.h +++ b/arch/x86/include/asm/perf_event_p4.h @@ -20,6 +20,9 @@ #define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR) #define ARCH_P4_MAX_CCCR (18) +#define ARCH_P4_CNTRVAL_BITS (40) +#define ARCH_P4_CNTRVAL_MASK ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1) + #define P4_ESCR_EVENT_MASK 0x7e000000U #define P4_ESCR_EVENT_SHIFT 25 #define P4_ESCR_EVENTMASK_MASK 0x01fffe00U diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index cae9c3cb95c..c6efecf85a6 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -141,10 +141,9 @@ extern __u32 cpu_caps_set[NCAPINTS]; #ifdef CONFIG_SMP DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); #define cpu_data(cpu) per_cpu(cpu_info, cpu) -#define current_cpu_data __get_cpu_var(cpu_info) #else +#define cpu_info boot_cpu_data #define cpu_data(cpu) boot_cpu_data -#define current_cpu_data boot_cpu_data #endif extern const struct seq_operations cpuinfo_op; diff --git a/arch/x86/include/asm/xen/hypervisor.h b/arch/x86/include/asm/xen/hypervisor.h index 396ff4cc8ed..66d0fff1ee8 100644 --- a/arch/x86/include/asm/xen/hypervisor.h +++ b/arch/x86/include/asm/xen/hypervisor.h @@ -37,4 +37,39 @@ extern struct shared_info *HYPERVISOR_shared_info; extern struct start_info *xen_start_info; +#include <asm/processor.h> + +static inline uint32_t xen_cpuid_base(void) +{ + uint32_t base, eax, ebx, ecx, edx; + char signature[13]; + + for (base = 0x40000000; base < 0x40010000; base += 0x100) { + cpuid(base, &eax, &ebx, &ecx, &edx); + *(uint32_t *)(signature + 0) = ebx; + *(uint32_t *)(signature + 4) = ecx; + *(uint32_t *)(signature + 8) = edx; + signature[12] = 0; + + if (!strcmp("XenVMMXenVMM", signature) && ((eax - base) >= 2)) + return base; + } + + return 0; +} + +#ifdef CONFIG_XEN +extern bool xen_hvm_need_lapic(void); + +static inline bool xen_x2apic_para_available(void) +{ + return xen_hvm_need_lapic(); +} +#else +static inline bool xen_x2apic_para_available(void) +{ + return (xen_cpuid_base() != 0); +} +#endif + #endif /* _ASM_X86_XEN_HYPERVISOR_H */ diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index 17c8090fabd..ec881c6bfee 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -852,18 +852,6 @@ static int __init acpi_parse_fadt(struct acpi_table_header *table) * returns 0 on success, < 0 on error */ -static void __init acpi_register_lapic_address(unsigned long address) -{ - mp_lapic_addr = address; - - set_fixmap_nocache(FIX_APIC_BASE, address); - if (boot_cpu_physical_apicid == -1U) { - boot_cpu_physical_apicid = read_apic_id(); - apic_version[boot_cpu_physical_apicid] = - GET_APIC_VERSION(apic_read(APIC_LVR)); - } -} - static int __init early_acpi_parse_madt_lapic_addr_ovr(void) { int count; @@ -885,7 +873,7 @@ static int __init early_acpi_parse_madt_lapic_addr_ovr(void) return count; } - acpi_register_lapic_address(acpi_lapic_addr); + register_lapic_address(acpi_lapic_addr); return count; } @@ -912,7 +900,7 @@ static int __init acpi_parse_madt_lapic_entries(void) return count; } - acpi_register_lapic_address(acpi_lapic_addr); + register_lapic_address(acpi_lapic_addr); count = acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_SAPIC, acpi_parse_sapic, MAX_LOCAL_APIC); @@ -954,32 +942,6 @@ static int __init acpi_parse_madt_lapic_entries(void) extern int es7000_plat; #endif -static void assign_to_mp_irq(struct mpc_intsrc *m, - struct mpc_intsrc *mp_irq) -{ - memcpy(mp_irq, m, sizeof(struct mpc_intsrc)); -} - -static int mp_irq_cmp(struct mpc_intsrc *mp_irq, - struct mpc_intsrc *m) -{ - return memcmp(mp_irq, m, sizeof(struct mpc_intsrc)); -} - -static void save_mp_irq(struct mpc_intsrc *m) -{ - int i; - - for (i = 0; i < mp_irq_entries; i++) { - if (!mp_irq_cmp(&mp_irqs[i], m)) - return; - } - - assign_to_mp_irq(m, &mp_irqs[mp_irq_entries]); - if (++mp_irq_entries == MAX_IRQ_SOURCES) - panic("Max # of irq sources exceeded!!\n"); -} - void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi) { int ioapic; @@ -1010,7 +972,7 @@ void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi) mp_irq.dstapic = mp_ioapics[ioapic].apicid; /* APIC ID */ mp_irq.dstirq = pin; /* INTIN# */ - save_mp_irq(&mp_irq); + mp_save_irq(&mp_irq); isa_irq_to_gsi[bus_irq] = gsi; } @@ -1085,7 +1047,7 @@ void __init mp_config_acpi_legacy_irqs(void) mp_irq.srcbusirq = i; /* Identity mapped */ mp_irq.dstirq = pin; - save_mp_irq(&mp_irq); + mp_save_irq(&mp_irq); } } @@ -1122,7 +1084,7 @@ static int mp_config_acpi_gsi(struct device *dev, u32 gsi, int trigger, mp_irq.dstapic = mp_ioapics[ioapic].apicid; mp_irq.dstirq = mp_find_ioapic_pin(ioapic, gsi); - save_mp_irq(&mp_irq); + mp_save_irq(&mp_irq); #endif return 0; } diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index affacb5e006..0a99f7198bc 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -20,6 +20,13 @@ struct pci_device_id amd_nb_misc_ids[] = { }; EXPORT_SYMBOL(amd_nb_misc_ids); +const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = { + { 0x00, 0x18, 0x20 }, + { 0xff, 0x00, 0x20 }, + { 0xfe, 0x00, 0x20 }, + { } +}; + struct amd_northbridge_info amd_northbridges; EXPORT_SYMBOL(amd_northbridges); diff --git a/arch/x86/kernel/aperture_64.c b/arch/x86/kernel/aperture_64.c index dcd7c83e165..5955a7800a9 100644 --- a/arch/x86/kernel/aperture_64.c +++ b/arch/x86/kernel/aperture_64.c @@ -39,18 +39,6 @@ int fallback_aper_force __initdata; int fix_aperture __initdata = 1; -struct bus_dev_range { - int bus; - int dev_base; - int dev_limit; -}; - -static struct bus_dev_range bus_dev_ranges[] __initdata = { - { 0x00, 0x18, 0x20}, - { 0xff, 0x00, 0x20}, - { 0xfe, 0x00, 0x20} -}; - static struct resource gart_resource = { .name = "GART", .flags = IORESOURCE_MEM, @@ -294,13 +282,13 @@ void __init early_gart_iommu_check(void) search_agp_bridge(&agp_aper_order, &valid_agp); fix = 0; - for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { + for (i = 0; amd_nb_bus_dev_ranges[i].dev_limit; i++) { int bus; int dev_base, dev_limit; - bus = bus_dev_ranges[i].bus; - dev_base = bus_dev_ranges[i].dev_base; - dev_limit = bus_dev_ranges[i].dev_limit; + bus = amd_nb_bus_dev_ranges[i].bus; + dev_base = amd_nb_bus_dev_ranges[i].dev_base; + dev_limit = amd_nb_bus_dev_ranges[i].dev_limit; for (slot = dev_base; slot < dev_limit; slot++) { if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) @@ -349,13 +337,13 @@ void __init early_gart_iommu_check(void) return; /* disable them all at first */ - for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { + for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) { int bus; int dev_base, dev_limit; - bus = bus_dev_ranges[i].bus; - dev_base = bus_dev_ranges[i].dev_base; - dev_limit = bus_dev_ranges[i].dev_limit; + bus = amd_nb_bus_dev_ranges[i].bus; + dev_base = amd_nb_bus_dev_ranges[i].dev_base; + dev_limit = amd_nb_bus_dev_ranges[i].dev_limit; for (slot = dev_base; slot < dev_limit; slot++) { if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) @@ -390,14 +378,14 @@ int __init gart_iommu_hole_init(void) fix = 0; node = 0; - for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { + for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) { int bus; int dev_base, dev_limit; u32 ctl; - bus = bus_dev_ranges[i].bus; - dev_base = bus_dev_ranges[i].dev_base; - dev_limit = bus_dev_ranges[i].dev_limit; + bus = amd_nb_bus_dev_ranges[i].bus; + dev_base = amd_nb_bus_dev_ranges[i].dev_base; + dev_limit = amd_nb_bus_dev_ranges[i].dev_limit; for (slot = dev_base; slot < dev_limit; slot++) { if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) @@ -505,7 +493,7 @@ out: } /* Fix up the north bridges */ - for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { + for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) { int bus, dev_base, dev_limit; /* @@ -514,9 +502,9 @@ out: */ u32 ctl = DISTLBWALKPRB | aper_order << 1; - bus = bus_dev_ranges[i].bus; - dev_base = bus_dev_ranges[i].dev_base; - dev_limit = bus_dev_ranges[i].dev_limit; + bus = amd_nb_bus_dev_ranges[i].bus; + dev_base = amd_nb_bus_dev_ranges[i].dev_base; + dev_limit = amd_nb_bus_dev_ranges[i].dev_limit; for (slot = dev_base; slot < dev_limit; slot++) { if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) continue; diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 879999a5230..06c196d7e59 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -49,8 +49,8 @@ #include <asm/mtrr.h> #include <asm/smp.h> #include <asm/mce.h> -#include <asm/kvm_para.h> #include <asm/tsc.h> +#include <asm/hypervisor.h> unsigned int num_processors; @@ -516,7 +516,7 @@ static void __cpuinit setup_APIC_timer(void) { struct clock_event_device *levt = &__get_cpu_var(lapic_events); - if (cpu_has(¤t_cpu_data, X86_FEATURE_ARAT)) { + if (cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_ARAT)) { lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; /* Make LAPIC timer preferrable over percpu HPET */ lapic_clockevent.rating = 150; @@ -684,7 +684,7 @@ static int __init calibrate_APIC_clock(void) lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, lapic_clockevent.shift); lapic_clockevent.max_delta_ns = - clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); + clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); lapic_clockevent.min_delta_ns = clockevent_delta2ns(0xF, &lapic_clockevent); @@ -1191,12 +1191,15 @@ static void __cpuinit lapic_setup_esr(void) oldvalue, value); } - /** * setup_local_APIC - setup the local APIC + * + * Used to setup local APIC while initializing BSP or bringin up APs. + * Always called with preemption disabled. */ void __cpuinit setup_local_APIC(void) { + int cpu = smp_processor_id(); unsigned int value, queued; int i, j, acked = 0; unsigned long long tsc = 0, ntsc; @@ -1221,8 +1224,6 @@ void __cpuinit setup_local_APIC(void) #endif perf_events_lapic_init(); - preempt_disable(); - /* * Double-check whether this APIC is really registered. * This is meaningless in clustered apic mode, so we skip it. @@ -1338,21 +1339,19 @@ void __cpuinit setup_local_APIC(void) * TODO: set up through-local-APIC from through-I/O-APIC? --macro */ value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; - if (!smp_processor_id() && (pic_mode || !value)) { + if (!cpu && (pic_mode || !value)) { value = APIC_DM_EXTINT; - apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", - smp_processor_id()); + apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); } else { value = APIC_DM_EXTINT | APIC_LVT_MASKED; - apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", - smp_processor_id()); + apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); } apic_write(APIC_LVT0, value); /* * only the BP should see the LINT1 NMI signal, obviously. */ - if (!smp_processor_id()) + if (!cpu) value = APIC_DM_NMI; else value = APIC_DM_NMI | APIC_LVT_MASKED; @@ -1360,11 +1359,9 @@ void __cpuinit setup_local_APIC(void) value |= APIC_LVT_LEVEL_TRIGGER; apic_write(APIC_LVT1, value); - preempt_enable(); - #ifdef CONFIG_X86_MCE_INTEL /* Recheck CMCI information after local APIC is up on CPU #0 */ - if (smp_processor_id() == 0) + if (!cpu) cmci_recheck(); #endif } @@ -1479,7 +1476,8 @@ void __init enable_IR_x2apic(void) /* IR is required if there is APIC ID > 255 even when running * under KVM */ - if (max_physical_apicid > 255 || !kvm_para_available()) + if (max_physical_apicid > 255 || + !hypervisor_x2apic_available()) goto nox2apic; /* * without IR all CPUs can be addressed by IOAPIC/MSI @@ -1633,28 +1631,6 @@ no_apic: } #endif -#ifdef CONFIG_X86_64 -void __init early_init_lapic_mapping(void) -{ - /* - * If no local APIC can be found then go out - * : it means there is no mpatable and MADT - */ - if (!smp_found_config) - return; - - set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); - apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", - APIC_BASE, mp_lapic_addr); - - /* - * Fetch the APIC ID of the BSP in case we have a - * default configuration (or the MP table is broken). - */ - boot_cpu_physical_apicid = read_apic_id(); -} -#endif - /** * init_apic_mappings - initialize APIC mappings */ @@ -1680,10 +1656,7 @@ void __init init_apic_mappings(void) * acpi_register_lapic_address() */ if (!acpi_lapic && !smp_found_config) - set_fixmap_nocache(FIX_APIC_BASE, apic_phys); - - apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", - APIC_BASE, apic_phys); + register_lapic_address(apic_phys); } /* @@ -1705,6 +1678,22 @@ void __init init_apic_mappings(void) } } +void __init register_lapic_address(unsigned long address) +{ + mp_lapic_addr = address; + + if (!x2apic_mode) { + set_fixmap_nocache(FIX_APIC_BASE, address); + apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", + APIC_BASE, mp_lapic_addr); + } + if (boot_cpu_physical_apicid == -1U) { + boot_cpu_physical_apicid = read_apic_id(); + apic_version[boot_cpu_physical_apicid] = + GET_APIC_VERSION(apic_read(APIC_LVR)); + } +} + /* * This initializes the IO-APIC and APIC hardware if this is * a UP kernel. diff --git a/arch/x86/kernel/apic/hw_nmi.c b/arch/x86/kernel/apic/hw_nmi.c index 72ec29e1ae0..79fd43ca6f9 100644 --- a/arch/x86/kernel/apic/hw_nmi.c +++ b/arch/x86/kernel/apic/hw_nmi.c @@ -68,7 +68,6 @@ arch_trigger_all_cpu_backtrace_handler(struct notifier_block *self, switch (cmd) { case DIE_NMI: - case DIE_NMI_IPI: break; default: @@ -96,7 +95,7 @@ arch_trigger_all_cpu_backtrace_handler(struct notifier_block *self, static __read_mostly struct notifier_block backtrace_notifier = { .notifier_call = arch_trigger_all_cpu_backtrace_handler, .next = NULL, - .priority = 1 + .priority = NMI_LOCAL_LOW_PRIOR, }; static int __init register_trigger_all_cpu_backtrace(void) diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index f6cd5b41077..697dc34b7b8 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -125,6 +125,26 @@ static int __init parse_noapic(char *str) } early_param("noapic", parse_noapic); +/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ +void mp_save_irq(struct mpc_intsrc *m) +{ + int i; + + apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," + " IRQ %02x, APIC ID %x, APIC INT %02x\n", + m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, + m->srcbusirq, m->dstapic, m->dstirq); + + for (i = 0; i < mp_irq_entries; i++) { + if (!memcmp(&mp_irqs[i], m, sizeof(*m))) + return; + } + + memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); + if (++mp_irq_entries == MAX_IRQ_SOURCES) + panic("Max # of irq sources exceeded!!\n"); +} + struct irq_pin_list { int apic, pin; struct irq_pin_list *next; @@ -135,6 +155,7 @@ static struct irq_pin_list *alloc_irq_pin_list(int node) return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node); } + /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ #ifdef CONFIG_SPARSE_IRQ static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; @@ -2006,9 +2027,12 @@ void __init setup_ioapic_ids_from_mpc_nocheck(void) = mp_ioapics[apic_id].apicid; /* - * Read the right value from the MPC table and - * write it into the ID register. + * Update the ID register according to the right value + * from the MPC table if they are different. */ + if (mp_ioapics[apic_id].apicid == reg_00.bits.ID) + continue; + apic_printk(APIC_VERBOSE, KERN_INFO "...changing IO-APIC physical APIC ID to %d ...", mp_ioapics[apic_id].apicid); @@ -2305,7 +2329,7 @@ asmlinkage void smp_irq_move_cleanup_interrupt(void) unsigned int irr; struct irq_desc *desc; struct irq_cfg *cfg; - irq = __get_cpu_var(vector_irq)[vector]; + irq = __this_cpu_read(vector_irq[vector]); if (irq == -1) continue; @@ -2339,7 +2363,7 @@ asmlinkage void smp_irq_move_cleanup_interrupt(void) apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); goto unlock; } - __get_cpu_var(vector_irq)[vector] = -1; + __this_cpu_write(vector_irq[vector], -1); unlock: raw_spin_unlock(&desc->lock); } diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c index 2a3f2a7db24..bd16b58b885 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -120,8 +120,8 @@ static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) else if (!strcmp(oem_table_id, "UVX")) uv_system_type = UV_X2APIC; else if (!strcmp(oem_table_id, "UVH")) { - __get_cpu_var(x2apic_extra_bits) = - pnodeid << uvh_apicid.s.pnode_shift; + __this_cpu_write(x2apic_extra_bits, + pnodeid << uvh_apicid.s.pnode_shift); uv_system_type = UV_NON_UNIQUE_APIC; uv_set_apicid_hibit(); return 1; @@ -286,7 +286,7 @@ static unsigned int x2apic_get_apic_id(unsigned long x) unsigned int id; WARN_ON(preemptible() && num_online_cpus() > 1); - id = x | __get_cpu_var(x2apic_extra_bits); + id = x | __this_cpu_read(x2apic_extra_bits); return id; } @@ -378,7 +378,7 @@ struct apic __refdata apic_x2apic_uv_x = { static __cpuinit void set_x2apic_extra_bits(int pnode) { - __get_cpu_var(x2apic_extra_bits) = (pnode << 6); + __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift); } /* @@ -641,7 +641,7 @@ void __cpuinit uv_cpu_init(void) */ int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data) { - if (reason != DIE_NMI_IPI) + if (reason != DIE_NMIUNKNOWN) return NOTIFY_OK; if (in_crash_kexec) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 9e093f8fe78..7c7bedb83c5 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -668,7 +668,7 @@ EXPORT_SYMBOL_GPL(amd_erratum_383); bool cpu_has_amd_erratum(const int *erratum) { - struct cpuinfo_x86 *cpu = ¤t_cpu_data; + struct cpuinfo_x86 *cpu = __this_cpu_ptr(&cpu_info); int osvw_id = *erratum++; u32 range; u32 ms; diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c index 491977baf6c..35c7e65e59b 100644 --- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c +++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c @@ -521,7 +521,7 @@ static void check_supported_cpu(void *_rc) *rc = -ENODEV; - if (current_cpu_data.x86_vendor != X86_VENDOR_AMD) + if (__this_cpu_read(cpu_info.x86_vendor) != X86_VENDOR_AMD) return; eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); @@ -1377,7 +1377,7 @@ static int __devexit powernowk8_cpu_exit(struct cpufreq_policy *pol) static void query_values_on_cpu(void *_err) { int *err = _err; - struct powernow_k8_data *data = __get_cpu_var(powernow_data); + struct powernow_k8_data *data = __this_cpu_read(powernow_data); *err = query_current_values_with_pending_wait(data); } diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index 9ecf81f9b90..7283e98deaa 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -265,7 +265,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax, line_size = l2.line_size; lines_per_tag = l2.lines_per_tag; /* cpu_data has errata corrections for K7 applied */ - size_in_kb = current_cpu_data.x86_cache_size; + size_in_kb = __this_cpu_read(cpu_info.x86_cache_size); break; case 3: if (!l3.val) @@ -287,7 +287,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax, eax->split.type = types[leaf]; eax->split.level = levels[leaf]; eax->split.num_threads_sharing = 0; - eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1; + eax->split.num_cores_on_die = __this_cpu_read(cpu_info.x86_max_cores) - 1; if (assoc == 0xffff) diff --git a/arch/x86/kernel/cpu/mcheck/mce-inject.c b/arch/x86/kernel/cpu/mcheck/mce-inject.c index e7dbde7bfed..a7797197956 100644 --- a/arch/x86/kernel/cpu/mcheck/mce-inject.c +++ b/arch/x86/kernel/cpu/mcheck/mce-inject.c @@ -25,6 +25,7 @@ #include <linux/gfp.h> #include <asm/mce.h> #include <asm/apic.h> +#include <asm/nmi.h> /* Update fake mce registers on current CPU. */ static void inject_mce(struct mce *m) @@ -83,7 +84,7 @@ static int mce_raise_notify(struct notifier_block *self, struct die_args *args = (struct die_args *)data; int cpu = smp_processor_id(); struct mce *m = &__get_cpu_var(injectm); - if (val != DIE_NMI_IPI || !cpumask_test_cpu(cpu, mce_inject_cpumask)) + if (val != DIE_NMI || !cpumask_test_cpu(cpu, mce_inject_cpumask)) return NOTIFY_DONE; cpumask_clear_cpu(cpu, mce_inject_cpumask); if (m->inject_flags & MCJ_EXCEPTION) @@ -95,7 +96,7 @@ static int mce_raise_notify(struct notifier_block *self, static struct notifier_block mce_raise_nb = { .notifier_call = mce_raise_notify, - .priority = 1000, + .priority = NMI_LOCAL_NORMAL_PRIOR, }; /* Inject mce on current CPU */ diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index 7a35b72d7c0..d916183b7f9 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -326,7 +326,7 @@ static void mce_panic(char *msg, struct mce *final, char *exp) static int msr_to_offset(u32 msr) { - unsigned bank = __get_cpu_var(injectm.bank); + unsigned bank = __this_cpu_read(injectm.bank); if (msr == rip_msr) return offsetof(struct mce, ip); @@ -346,7 +346,7 @@ static u64 mce_rdmsrl(u32 msr) { u64 v; - if (__get_cpu_var(injectm).finished) { + if (__this_cpu_read(injectm.finished)) { int offset = msr_to_offset(msr); if (offset < 0) @@ -369,7 +369,7 @@ static u64 mce_rdmsrl(u32 msr) static void mce_wrmsrl(u32 msr, u64 v) { - if (__get_cpu_var(injectm).finished) { + if (__this_cpu_read(injectm.finished)) { int offset = msr_to_offset(msr); if (offset >= 0) @@ -1159,7 +1159,7 @@ static void mce_start_timer(unsigned long data) WARN_ON(smp_processor_id() != data); - if (mce_available(¤t_cpu_data)) { + if (mce_available(__this_cpu_ptr(&cpu_info))) { machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_poll_banks)); } @@ -1767,7 +1767,7 @@ static int mce_shutdown(struct sys_device *dev) static int mce_resume(struct sys_device *dev) { __mcheck_cpu_init_generic(); - __mcheck_cpu_init_vendor(¤t_cpu_data); + __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info)); return 0; } @@ -1775,7 +1775,7 @@ static int mce_resume(struct sys_device *dev) static void mce_cpu_restart(void *data) { del_timer_sync(&__get_cpu_var(mce_timer)); - if (!mce_available(¤t_cpu_data)) + if (!mce_available(__this_cpu_ptr(&cpu_info))) return; __mcheck_cpu_init_generic(); __mcheck_cpu_init_timer(); @@ -1790,7 +1790,7 @@ static void mce_restart(void) /* Toggle features for corrected errors */ static void mce_disable_ce(void *all) { - if (!mce_available(¤t_cpu_data)) + if (!mce_available(__this_cpu_ptr(&cpu_info))) return; if (all) del_timer_sync(&__get_cpu_var(mce_timer)); @@ -1799,7 +1799,7 @@ static void mce_disable_ce(void *all) static void mce_enable_ce(void *all) { - if (!mce_available(¤t_cpu_data)) + if (!mce_available(__this_cpu_ptr(&cpu_info))) return; cmci_reenable(); cmci_recheck(); @@ -2022,7 +2022,7 @@ static void __cpuinit mce_disable_cpu(void *h) unsigned long action = *(unsigned long *)h; int i; - if (!mce_available(¤t_cpu_data)) + if (!mce_available(__this_cpu_ptr(&cpu_info))) return; if (!(action & CPU_TASKS_FROZEN)) @@ -2040,7 +2040,7 @@ static void __cpuinit mce_reenable_cpu(void *h) unsigned long action = *(unsigned long *)h; int i; - if (!mce_available(¤t_cpu_data)) + if (!mce_available(__this_cpu_ptr(&cpu_info))) return; if (!(action & CPU_TASKS_FROZEN)) diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c index 6fcd0936194..8694ef56459 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c @@ -130,7 +130,7 @@ void cmci_recheck(void) unsigned long flags; int banks; - if (!mce_available(¤t_cpu_data) || !cmci_supported(&banks)) + if (!mce_available(__this_cpu_ptr(&cpu_info)) || !cmci_supported(&banks)) return; local_irq_save(flags); machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned)); diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index 0a360d14659..9d977a2ea69 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -997,8 +997,7 @@ x86_perf_event_set_period(struct perf_event *event) static void x86_pmu_enable_event(struct perf_event *event) { - struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); - if (cpuc->enabled) + if (__this_cpu_read(cpu_hw_events.enabled)) __x86_pmu_enable_event(&event->hw, ARCH_PERFMON_EVENTSEL_ENABLE); } @@ -1268,11 +1267,10 @@ perf_event_nmi_handler(struct notifier_block *self, switch (cmd) { case DIE_NMI: - case DIE_NMI_IPI: break; case DIE_NMIUNKNOWN: this_nmi = percpu_read(irq_stat.__nmi_count); - if (this_nmi != __get_cpu_var(pmu_nmi).marked) + if (this_nmi != __this_cpu_read(pmu_nmi.marked)) /* let the kernel handle the unknown nmi */ return NOTIFY_DONE; /* @@ -1296,8 +1294,8 @@ perf_event_nmi_handler(struct notifier_block *self, this_nmi = percpu_read(irq_stat.__nmi_count); if ((handled > 1) || /* the next nmi could be a back-to-back nmi */ - ((__get_cpu_var(pmu_nmi).marked == this_nmi) && - (__get_cpu_var(pmu_nmi).handled > 1))) { + ((__this_cpu_read(pmu_nmi.marked) == this_nmi) && + (__this_cpu_read(pmu_nmi.handled) > 1))) { /* * We could have two subsequent back-to-back nmis: The * first handles more than one counter, the 2nd @@ -1308,8 +1306,8 @@ perf_event_nmi_handler(struct notifier_block *self, * handling more than one counter. We will mark the * next (3rd) and then drop it if unhandled. */ - __get_cpu_var(pmu_nmi).marked = this_nmi + 1; - __get_cpu_var(pmu_nmi).handled = handled; + __this_cpu_write(pmu_nmi.marked, this_nmi + 1); + __this_cpu_write(pmu_nmi.handled, handled); } return NOTIFY_STOP; @@ -1318,7 +1316,7 @@ perf_event_nmi_handler(struct notifier_block *self, static __read_mostly struct notifier_block perf_event_nmi_notifier = { .notifier_call = perf_event_nmi_handler, .next = NULL, - .priority = 1 + .priority = NMI_LOCAL_LOW_PRIOR, }; static struct event_constraint unconstrained; @@ -1484,11 +1482,9 @@ static inline void x86_pmu_read(struct perf_event *event) */ static void x86_pmu_start_txn(struct pmu *pmu) { - struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); - perf_pmu_disable(pmu); - cpuc->group_flag |= PERF_EVENT_TXN; - cpuc->n_txn = 0; + __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN); + __this_cpu_write(cpu_hw_events.n_txn, 0); } /* @@ -1498,14 +1494,12 @@ static void x86_pmu_start_txn(struct pmu *pmu) */ static void x86_pmu_cancel_txn(struct pmu *pmu) { - struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); - - cpuc->group_flag &= ~PERF_EVENT_TXN; + __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN); /* * Truncate the collected events. */ - cpuc->n_added -= cpuc->n_txn; - cpuc->n_events -= cpuc->n_txn; + __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); + __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); perf_pmu_enable(pmu); } diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 24e390e40f2..008835c1d79 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -649,7 +649,7 @@ static void intel_pmu_enable_event(struct perf_event *event) struct hw_perf_event *hwc = &event->hw; if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) { - if (!__get_cpu_var(cpu_hw_events).enabled) + if (!__this_cpu_read(cpu_hw_events.enabled)) return; intel_pmu_enable_bts(hwc->config); @@ -679,7 +679,7 @@ static int intel_pmu_save_and_restart(struct perf_event *event) static void intel_pmu_reset(void) { - struct debug_store *ds = __get_cpu_var(cpu_hw_events).ds; + struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); unsigned long flags; int idx; diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c index 81400b93e69..e56b9bfbabd 100644 --- a/arch/x86/kernel/cpu/perf_event_p4.c +++ b/arch/x86/kernel/cpu/perf_event_p4.c @@ -753,19 +753,21 @@ out: static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc) { - int overflow = 0; - u32 low, high; + u64 v; - rdmsr(hwc->config_base + hwc->idx, low, high); - - /* we need to check high bit for unflagged overflows */ - if ((low & P4_CCCR_OVF) || !(high & (1 << 31))) { - overflow = 1; - (void)checking_wrmsrl(hwc->config_base + hwc->idx, - ((u64)low) & ~P4_CCCR_OVF); + /* an official way for overflow indication */ + rdmsrl(hwc->config_base + hwc->idx, v); + if (v & P4_CCCR_OVF) { + wrmsrl(hwc->config_base + hwc->idx, v & ~P4_CCCR_OVF); + return 1; } - return overflow; + /* it might be unflagged overflow */ + rdmsrl(hwc->event_base + hwc->idx, v); + if (!(v & ARCH_P4_CNTRVAL_MASK)) + return 1; + + return 0; } static void p4_pmu_disable_pebs(void) @@ -1152,9 +1154,9 @@ static __initconst const struct x86_pmu p4_pmu = { */ .num_counters = ARCH_P4_MAX_CCCR, .apic = 1, - .cntval_bits = 40, - .cntval_mask = (1ULL << 40) - 1, - .max_period = (1ULL << 39) - 1, + .cntval_bits = ARCH_P4_CNTRVAL_BITS, + .cntval_mask = ARCH_P4_CNTRVAL_MASK, + .max_period = (1ULL << (ARCH_P4_CNTRVAL_BITS - 1)) - 1, .hw_config = p4_hw_config, .schedule_events = p4_pmu_schedule_events, /* diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c index 8474c998cbd..d6fb146c0d8 100644 --- a/arch/x86/kernel/dumpstack.c +++ b/arch/x86/kernel/dumpstack.c @@ -197,14 +197,8 @@ void show_stack(struct task_struct *task, unsigned long *sp) */ void dump_stack(void) { - unsigned long bp = 0; unsigned long stack; -#ifdef CONFIG_FRAME_POINTER - if (!bp) - get_bp(bp); -#endif - printk("Pid: %d, comm: %.20s %s %s %.*s\n", current->pid, current->comm, print_tainted(), init_utsname()->release, diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S index e3ba417e869..d3b895f375d 100644 --- a/arch/x86/kernel/entry_64.S +++ b/arch/x86/kernel/entry_64.S @@ -299,17 +299,21 @@ ENDPROC(native_usergs_sysret64) ENTRY(save_args) XCPT_FRAME cld - movq_cfi rdi, RDI+16-ARGOFFSET - movq_cfi rsi, RSI+16-ARGOFFSET - movq_cfi rdx, RDX+16-ARGOFFSET - movq_cfi rcx, RCX+16-ARGOFFSET - movq_cfi rax, RAX+16-ARGOFFSET - movq_cfi r8, R8+16-ARGOFFSET - movq_cfi r9, R9+16-ARGOFFSET - movq_cfi r10, R10+16-ARGOFFSET - movq_cfi r11, R11+16-ARGOFFSET - - leaq -ARGOFFSET+16(%rsp),%rdi /* arg1 for handler */ + /* + * start from rbp in pt_regs and jump over + * return address. + */ + movq_cfi rdi, RDI+8-RBP + movq_cfi rsi, RSI+8-RBP + movq_cfi rdx, RDX+8-RBP + movq_cfi rcx, RCX+8-RBP + movq_cfi rax, RAX+8-RBP + movq_cfi r8, R8+8-RBP + movq_cfi r9, R9+8-RBP + movq_cfi r10, R10+8-RBP + movq_cfi r11, R11+8-RBP + + leaq -RBP+8(%rsp),%rdi /* arg1 for handler */ movq_cfi rbp, 8 /* push %rbp */ leaq 8(%rsp), %rbp /* mov %rsp, %ebp */ testl $3, CS(%rdi) @@ -782,8 +786,9 @@ END(interrupt) /* 0(%rsp): ~(interrupt number) */ .macro interrupt func - subq $ORIG_RAX-ARGOFFSET+8, %rsp - CFI_ADJUST_CFA_OFFSET ORIG_RAX-ARGOFFSET+8 + /* reserve pt_regs for scratch regs and rbp */ + subq $ORIG_RAX-RBP, %rsp + CFI_ADJUST_CFA_OFFSET ORIG_RAX-RBP call save_args PARTIAL_FRAME 0 call \func @@ -808,9 +813,14 @@ ret_from_intr: TRACE_IRQS_OFF decl PER_CPU_VAR(irq_count) leaveq + CFI_RESTORE rbp CFI_DEF_CFA_REGISTER rsp CFI_ADJUST_CFA_OFFSET -8 + + /* we did not save rbx, restore only from ARGOFFSET */ + addq $8, %rsp + CFI_ADJUST_CFA_OFFSET -8 exit_intr: GET_THREAD_INFO(%rcx) testl $3,CS-ARGOFFSET(%rsp) diff --git a/arch/x86/kernel/ftrace.c b/arch/x86/kernel/ftrace.c index 298448656b6..382eb2936d4 100644 --- a/arch/x86/kernel/ftrace.c +++ b/arch/x86/kernel/ftrace.c @@ -170,9 +170,9 @@ static void ftrace_mod_code(void) void ftrace_nmi_enter(void) { - __get_cpu_var(save_modifying_code) = modifying_code; + __this_cpu_write(save_modifying_code, modifying_code); - if (!__get_cpu_var(save_modifying_code)) + if (!__this_cpu_read(save_modifying_code)) return; if (atomic_inc_return(&nmi_running) & MOD_CODE_WRITE_FLAG) { @@ -186,7 +186,7 @@ void ftrace_nmi_enter(void) void ftrace_nmi_exit(void) { - if (!__get_cpu_var(save_modifying_code)) + if (!__this_cpu_read(save_modifying_code)) return; /* Finish all executions before clearing nmi_running */ diff --git a/arch/x86/kernel/hw_breakpoint.c b/arch/x86/kernel/hw_breakpoint.c index 42c59425450..02f07634d26 100644 --- a/arch/x86/kernel/hw_breakpoint.c +++ b/arch/x86/kernel/hw_breakpoint.c @@ -122,7 +122,7 @@ int arch_install_hw_breakpoint(struct perf_event *bp) return -EBUSY; set_debugreg(info->address, i); - __get_cpu_var(cpu_debugreg[i]) = info->address; + __this_cpu_write(cpu_debugreg[i], info->address); dr7 = &__get_cpu_var(cpu_dr7); *dr7 |= encode_dr7(i, info->len, info->type); @@ -397,12 +397,12 @@ void flush_ptrace_hw_breakpoint(struct task_struct *tsk) void hw_breakpoint_restore(void) { - set_debugreg(__get_cpu_var(cpu_debugreg[0]), 0); - set_debugreg(__get_cpu_var(cpu_debugreg[1]), 1); - set_debugreg(__get_cpu_var(cpu_debugreg[2]), 2); - set_debugreg(__get_cpu_var(cpu_debugreg[3]), 3); + set_debugreg(__this_cpu_read(cpu_debugreg[0]), 0); + set_debugreg(__this_cpu_read(cpu_debugreg[1]), 1); + set_debugreg(__this_cpu_read(cpu_debugreg[2]), 2); + set_debugreg(__this_cpu_read(cpu_debugreg[3]), 3); set_debugreg(current->thread.debugreg6, 6); - set_debugreg(__get_cpu_var(cpu_dr7), 7); + set_debugreg(__this_cpu_read(cpu_dr7), 7); } EXPORT_SYMBOL_GPL(hw_breakpoint_restore); diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c index 83ec0175f98..3a43caa3beb 100644 --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c @@ -234,7 +234,7 @@ unsigned int __irq_entry do_IRQ(struct pt_regs *regs) exit_idle(); irq_enter(); - irq = __get_cpu_var(vector_irq)[vector]; + irq = __this_cpu_read(vector_irq[vector]); if (!handle_irq(irq, regs)) { ack_APIC_irq(); @@ -350,12 +350,12 @@ void fixup_irqs(void) for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { unsigned int irr; - if (__get_cpu_var(vector_irq)[vector] < 0) + if (__this_cpu_read(vector_irq[vector]) < 0) continue; irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); if (irr & (1 << (vector % 32))) { - irq = __get_cpu_var(vector_irq)[vector]; + irq = __this_cpu_read(vector_irq[vector]); data = irq_get_irq_data(irq); raw_spin_lock(&desc->lock); diff --git a/arch/x86/kernel/irq_32.c b/arch/x86/kernel/irq_32.c index 96656f20775..48ff6dcffa0 100644 --- a/arch/x86/kernel/irq_32.c +++ b/arch/x86/kernel/irq_32.c @@ -79,7 +79,7 @@ execute_on_irq_stack(int overflow, struct irq_desc *desc, int irq) u32 *isp, arg1, arg2; curctx = (union irq_ctx *) current_thread_info(); - irqctx = __get_cpu_var(hardirq_ctx); + irqctx = __this_cpu_read(hardirq_ctx); /* * this is where we switch to the IRQ stack. However, if we are @@ -166,7 +166,7 @@ asmlinkage void do_softirq(void) if (local_softirq_pending()) { curctx = current_thread_info(); - irqctx = __get_cpu_var(softirq_ctx); + irqctx = __this_cpu_read(softirq_ctx); irqctx->tinfo.task = curctx->task; irqctx->tinfo.previous_esp = current_stack_pointer; diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c index cd21b654dec..a4130005028 100644 --- a/arch/x86/kernel/kgdb.c +++ b/arch/x86/kernel/kgdb.c @@ -48,6 +48,7 @@ #include <asm/apicdef.h> #include <asm/system.h> #include <asm/apic.h> +#include <asm/nmi.h> struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = { @@ -525,10 +526,6 @@ static int __kgdb_notify(struct die_args *args, unsigned long cmd) } return NOTIFY_DONE; - case DIE_NMI_IPI: - /* Just ignore, we will handle the roundup on DIE_NMI. */ - return NOTIFY_DONE; - case DIE_NMIUNKNOWN: if (was_in_debug_nmi[raw_smp_processor_id()]) { was_in_debug_nmi[raw_smp_processor_id()] = 0; @@ -606,7 +603,7 @@ static struct notifier_block kgdb_notifier = { /* * Lowest-prio notifier priority, we want to be notified last: */ - .priority = -INT_MAX, + .priority = NMI_LOCAL_LOW_PRIOR, }; /** diff --git a/arch/x86/kernel/kprobes.c b/arch/x86/kernel/kprobes.c index 5940282bd2f..d91c477b3f6 100644 --- a/arch/x86/kernel/kprobes.c +++ b/arch/x86/kernel/kprobes.c @@ -403,7 +403,7 @@ static void __kprobes save_previous_kprobe(struct kprobe_ctlblk *kcb) static void __kprobes restore_previous_kprobe(struct kprobe_ctlblk *kcb) { - __get_cpu_var(current_kprobe) = kcb->prev_kprobe.kp; + __this_cpu_write(current_kprobe, kcb->prev_kprobe.kp); kcb->kprobe_status = kcb->prev_kprobe.status; kcb->kprobe_old_flags = kcb->prev_kprobe.old_flags; kcb->kprobe_saved_flags = kcb->prev_kprobe.saved_flags; @@ -412,7 +412,7 @@ static void __kprobes restore_previous_kprobe(struct kprobe_ctlblk *kcb) static void __kprobes set_current_kprobe(struct kprobe *p, struct pt_regs *regs, struct kprobe_ctlblk *kcb) { - __get_cpu_var(current_kprobe) = p; + __this_cpu_write(current_kprobe, p); kcb->kprobe_saved_flags = kcb->kprobe_old_flags = (regs->flags & (X86_EFLAGS_TF | X86_EFLAGS_IF)); if (is_IF_modifier(p->ainsn.insn)) @@ -586,7 +586,7 @@ static int __kprobes kprobe_handler(struct pt_regs *regs) preempt_enable_no_resched(); return 1; } else if (kprobe_running()) { - p = __get_cpu_var(current_kprobe); + p = __this_cpu_read(current_kprobe); if (p->break_handler && p->break_handler(p, regs)) { setup_singlestep(p, regs, kcb, 0); return 1; @@ -759,11 +759,11 @@ static __used __kprobes void *trampoline_handler(struct pt_regs *regs) orig_ret_address = (unsigned long)ri->ret_addr; if (ri->rp && ri->rp->handler) { - __get_cpu_var(current_kprobe) = &ri->rp->kp; + __this_cpu_write(current_kprobe, &ri->rp->kp); get_kprobe_ctlblk()->kprobe_status = KPROBE_HIT_ACTIVE; ri->ret_addr = correct_ret_addr; ri->rp->handler(ri, regs); - __get_cpu_var(current_kprobe) = NULL; + __this_cpu_write(current_kprobe, NULL); } recycle_rp_inst(ri, &empty_rp); @@ -1202,10 +1202,10 @@ static void __kprobes optimized_callback(struct optimized_kprobe *op, regs->ip = (unsigned long)op->kp.addr + INT3_SIZE; regs->orig_ax = ~0UL; - __get_cpu_var(current_kprobe) = &op->kp; + __this_cpu_write(current_kprobe, &op->kp); kcb->kprobe_status = KPROBE_HIT_ACTIVE; opt_pre_handler(&op->kp, regs); - __get_cpu_var(current_kprobe) = NULL; + __this_cpu_write(current_kprobe, NULL); } preempt_enable_no_resched(); } diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c index 9af64d9c4b6..01b0f6d0645 100644 --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -118,21 +118,8 @@ static void __init MP_bus_info(struct mpc_bus *m) static void __init MP_ioapic_info(struct mpc_ioapic *m) { - if (!(m->flags & MPC_APIC_USABLE)) - return; - - printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n", - m->apicid, m->apicver, m->apicaddr); - - mp_register_ioapic(m->apicid, m->apicaddr, gsi_top); -} - -static void print_MP_intsrc_info(struct mpc_intsrc *m) -{ - apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," - " IRQ %02x, APIC ID %x, APIC INT %02x\n", - m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, - m->srcbusirq, m->dstapic, m->dstirq); + if (m->flags & MPC_APIC_USABLE) + mp_register_ioapic(m->apicid, m->apicaddr, gsi_top); } static void __init print_mp_irq_info(struct mpc_intsrc *mp_irq) @@ -144,73 +131,11 @@ static void __init print_mp_irq_info(struct mpc_intsrc *mp_irq) mp_irq->srcbusirq, mp_irq->dstapic, mp_irq->dstirq); } -static void __init assign_to_mp_irq(struct mpc_intsrc *m, - struct mpc_intsrc *mp_irq) -{ - mp_irq->dstapic = m->dstapic; - mp_irq->type = m->type; - mp_irq->irqtype = m->irqtype; - mp_irq->irqflag = m->irqflag; - mp_irq->srcbus = m->srcbus; - mp_irq->srcbusirq = m->srcbusirq; - mp_irq->dstirq = m->dstirq; -} - -static void __init assign_to_mpc_intsrc(struct mpc_intsrc *mp_irq, - struct mpc_intsrc *m) -{ - m->dstapic = mp_irq->dstapic; - m->type = mp_irq->type; - m->irqtype = mp_irq->irqtype; - m->irqflag = mp_irq->irqflag; - m->srcbus = mp_irq->srcbus; - m->srcbusirq = mp_irq->srcbusirq; - m->dstirq = mp_irq->dstirq; -} - -static int __init mp_irq_mpc_intsrc_cmp(struct mpc_intsrc *mp_irq, - struct mpc_intsrc *m) -{ - if (mp_irq->dstapic != m->dstapic) - return 1; - if (mp_irq->type != m->type) - return 2; - if (mp_irq->irqtype != m->irqtype) - return 3; - if (mp_irq->irqflag != m->irqflag) - return 4; - if (mp_irq->srcbus != m->srcbus) - return 5; - if (mp_irq->srcbusirq != m->srcbusirq) - return 6; - if (mp_irq->dstirq != m->dstirq) - return 7; - - return 0; -} - -static void __init MP_intsrc_info(struct mpc_intsrc *m) -{ - int i; - - print_MP_intsrc_info(m); - - for (i = 0; i < mp_irq_entries; i++) { - if (!mp_irq_mpc_intsrc_cmp(&mp_irqs[i], m)) - return; - } - - assign_to_mp_irq(m, &mp_irqs[mp_irq_entries]); - if (++mp_irq_entries == MAX_IRQ_SOURCES) - panic("Max # of irq sources exceeded!!\n"); -} #else /* CONFIG_X86_IO_APIC */ static inline void __init MP_bus_info(struct mpc_bus *m) {} static inline void __init MP_ioapic_info(struct mpc_ioapic *m) {} -static inline void __init MP_intsrc_info(struct mpc_intsrc *m) {} #endif /* CONFIG_X86_IO_APIC */ - static void __init MP_lintsrc_info(struct mpc_lintsrc *m) { apic_printk(APIC_VERBOSE, "Lint: type %d, pol %d, trig %d, bus %02x," @@ -222,7 +147,6 @@ static void __init MP_lintsrc_info(struct mpc_lintsrc *m) /* * Read/parse the MPC */ - static int __init smp_check_mpc(struct mpc_table *mpc, char *oem, char *str) { @@ -275,18 +199,6 @@ static void __init smp_dump_mptable(struct mpc_table *mpc, unsigned char *mpt) void __init default_smp_read_mpc_oem(struct mpc_table *mpc) { } -static void __init smp_register_lapic_address(unsigned long address) -{ - mp_lapic_addr = address; - - set_fixmap_nocache(FIX_APIC_BASE, address); - if (boot_cpu_physical_apicid == -1U) { - boot_cpu_physical_apicid = read_apic_id(); - apic_version[boot_cpu_physical_apicid] = - GET_APIC_VERSION(apic_read(APIC_LVR)); - } -} - static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early) { char str[16]; @@ -301,17 +213,13 @@ static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early) #ifdef CONFIG_X86_32 generic_mps_oem_check(mpc, oem, str); #endif - /* save the local APIC address, it might be non-default */ + /* Initialize the lapic mapping */ if (!acpi_lapic) - mp_lapic_addr = mpc->lapic; + register_lapic_address(mpc->lapic); if (early) return 1; - /* Initialize the lapic mapping */ - if (!acpi_lapic) - smp_register_lapic_address(mpc->lapic); - if (mpc->oemptr) x86_init.mpparse.smp_read_mpc_oem(mpc); @@ -337,7 +245,7 @@ static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early) skip_entry(&mpt, &count, sizeof(struct mpc_ioapic)); break; case MP_INTSRC: - MP_intsrc_info((struct mpc_intsrc *)mpt); + mp_save_irq((struct mpc_intsrc *)mpt); skip_entry(&mpt, &count, sizeof(struct mpc_intsrc)); break; case MP_LINTSRC: @@ -429,13 +337,13 @@ static void __init construct_default_ioirq_mptable(int mpc_default_type) intsrc.srcbusirq = i; intsrc.dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ - MP_intsrc_info(&intsrc); + mp_save_irq(&intsrc); } intsrc.irqtype = mp_ExtINT; intsrc.srcbusirq = 0; intsrc.dstirq = 0; /* 8259A to INTIN0 */ - MP_intsrc_info(&intsrc); + mp_save_irq(&intsrc); } @@ -784,11 +692,11 @@ static void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare) int i; apic_printk(APIC_VERBOSE, "OLD "); - print_MP_intsrc_info(m); + print_mp_irq_info(m); i = get_MP_intsrc_index(m); if (i > 0) { - assign_to_mpc_intsrc(&mp_irqs[i], m); + memcpy(m, &mp_irqs[i], sizeof(*m)); apic_printk(APIC_VERBOSE, "NEW "); print_mp_irq_info(&mp_irqs[i]); return; @@ -875,14 +783,14 @@ static int __init replace_intsrc_all(struct mpc_table *mpc, if (nr_m_spare > 0) { apic_printk(APIC_VERBOSE, "*NEW* found\n"); nr_m_spare--; - assign_to_mpc_intsrc(&mp_irqs[i], m_spare[nr_m_spare]); + memcpy(m_spare[nr_m_spare], &mp_irqs[i], sizeof(mp_irqs[i])); m_spare[nr_m_spare] = NULL; } else { struct mpc_intsrc *m = (struct mpc_intsrc *)mpt; count += sizeof(struct mpc_intsrc); if (check_slot(mpc_new_phys, mpc_new_length, count) < 0) goto out; - assign_to_mpc_intsrc(&mp_irqs[i], m); + memcpy(m, &mp_irqs[i], sizeof(*m)); mpc->length = count; mpt += sizeof(struct mpc_intsrc); } diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index c852041bfc3..09c08a1c706 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -446,7 +446,7 @@ void mwait_idle_with_hints(unsigned long ax, unsigned long cx) trace_power_start(POWER_CSTATE, (ax>>4)+1, smp_processor_id()); trace_cpu_idle((ax>>4)+1, smp_processor_id()); if (!need_resched()) { - if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR)) + if (cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_CLFLUSH_MONITOR)) clflush((void *)¤t_thread_info()->flags); __monitor((void *)¤t_thread_info()->flags, 0, 0); @@ -462,7 +462,7 @@ static void mwait_idle(void) if (!need_resched()) { trace_power_start(POWER_CSTATE, 1, smp_processor_id()); trace_cpu_idle(1, smp_processor_id()); - if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR)) + if (cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_CLFLUSH_MONITOR)) clflush((void *)¤t_thread_info()->flags); __monitor((void *)¤t_thread_info()->flags, 0, 0); diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index c495aa8d481..fc7aae1e2bc 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c @@ -18,6 +18,7 @@ #include <asm/pci_x86.h> #include <asm/virtext.h> #include <asm/cpu.h> +#include <asm/nmi.h> #ifdef CONFIG_X86_32 # include <linux/ctype.h> @@ -747,7 +748,7 @@ static int crash_nmi_callback(struct notifier_block *self, { int cpu; - if (val != DIE_NMI_IPI) + if (val != DIE_NMI) return NOTIFY_OK; cpu = raw_smp_processor_id(); @@ -778,6 +779,8 @@ static void smp_send_nmi_allbutself(void) static struct notifier_block crash_nmi_nb = { .notifier_call = crash_nmi_callback, + /* we want to be the first one called */ + .priority = NMI_LOCAL_HIGH_PRIOR+1, }; /* Halt all other CPUs, calling the specified function on each of them diff --git a/arch/x86/kernel/rtc.c b/arch/x86/kernel/rtc.c index 1cfbbfc3ae2..6f39cab052d 100644 --- a/arch/x86/kernel/rtc.c +++ b/arch/x86/kernel/rtc.c @@ -76,7 +76,7 @@ int mach_set_rtc_mmss(unsigned long nowtime) CMOS_WRITE(real_seconds, RTC_SECONDS); CMOS_WRITE(real_minutes, RTC_MINUTES); } else { - printk(KERN_WARNING + printk_once(KERN_NOTICE "set_rtc_mmss: can't update from %d to %d\n", cmos_minutes, real_minutes); retval = -1; diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index ee886fe10ef..763df77343d 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -97,12 +97,12 @@ static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); */ static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); -void cpu_hotplug_driver_lock() +void cpu_hotplug_driver_lock(void) { mutex_lock(&x86_cpu_hotplug_driver_mutex); } -void cpu_hotplug_driver_unlock() +void cpu_hotplug_driver_unlock(void) { mutex_unlock(&x86_cpu_hotplug_driver_mutex); } @@ -427,7 +427,7 @@ void __cpuinit set_cpu_sibling_map(int cpu) cpumask_set_cpu(cpu, c->llc_shared_map); - if (current_cpu_data.x86_max_cores == 1) { + if (__this_cpu_read(cpu_info.x86_max_cores) == 1) { cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); c->booted_cores = 1; return; @@ -1089,7 +1089,7 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus) preempt_disable(); smp_cpu_index_default(); - current_cpu_data = boot_cpu_data; + memcpy(__this_cpu_ptr(&cpu_info), &boot_cpu_data, sizeof(cpu_info)); cpumask_copy(cpu_callin_mask, cpumask_of(0)); mb(); /* @@ -1383,7 +1383,7 @@ void play_dead_common(void) mb(); /* Ack it */ - __get_cpu_var(cpu_state) = CPU_DEAD; + __this_cpu_write(cpu_state, CPU_DEAD); /* * With physical CPU hotplug, we should halt the cpu @@ -1403,11 +1403,11 @@ static inline void mwait_play_dead(void) int i; void *mwait_ptr; - if (!cpu_has(¤t_cpu_data, X86_FEATURE_MWAIT)) + if (!cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_MWAIT)) return; - if (!cpu_has(¤t_cpu_data, X86_FEATURE_CLFLSH)) + if (!cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_CLFLSH)) return; - if (current_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) + if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) return; eax = CPUID_MWAIT_LEAF; @@ -1458,7 +1458,7 @@ static inline void mwait_play_dead(void) static inline void hlt_play_dead(void) { - if (current_cpu_data.x86 >= 4) + if (__this_cpu_read(cpu_info.x86) >= 4) wbinvd(); while (1) { diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index c76aaca5694..b9b67166f9d 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -84,6 +84,11 @@ EXPORT_SYMBOL_GPL(used_vectors); static int ignore_nmis; int unknown_nmi_panic; +/* + * Prevent NMI reason port (0x61) being accessed simultaneously, can + * only be used in NMI handler. + */ +static DEFINE_RAW_SPINLOCK(nmi_reason_lock); static inline void conditional_sti(struct pt_regs *regs) { @@ -310,15 +315,15 @@ static int __init setup_unknown_nmi_panic(char *str) __setup("unknown_nmi_panic", setup_unknown_nmi_panic); static notrace __kprobes void -mem_parity_error(unsigned char reason, struct pt_regs *regs) +pci_serr_error(unsigned char reason, struct pt_regs *regs) { - printk(KERN_EMERG - "Uhhuh. NMI received for unknown reason %02x on CPU %d.\n", - reason, smp_processor_id()); - - printk(KERN_EMERG - "You have some hardware problem, likely on the PCI bus.\n"); + pr_emerg("NMI: PCI system error (SERR) for reason %02x on CPU %d.\n", + reason, smp_processor_id()); + /* + * On some machines, PCI SERR line is used to report memory + * errors. EDAC makes use of it. + */ #if defined(CONFIG_EDAC) if (edac_handler_set()) { edac_atomic_assert_error(); @@ -329,11 +334,11 @@ mem_parity_error(unsigned char reason, struct pt_regs *regs) if (panic_on_unrecovered_nmi) panic("NMI: Not continuing"); - printk(KERN_EMERG "Dazed and confused, but trying to continue\n"); + pr_emerg("Dazed and confused, but trying to continue\n"); - /* Clear and disable the memory parity error line. */ - reason = (reason & 0xf) | 4; - outb(reason, 0x61); + /* Clear and disable the PCI SERR error line. */ + reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_SERR; + outb(reason, NMI_REASON_PORT); } static notrace __kprobes void @@ -341,15 +346,17 @@ io_check_error(unsigned char reason, struct pt_regs *regs) { unsigned long i; - printk(KERN_EMERG "NMI: IOCK error (debug interrupt?)\n"); + pr_emerg( + "NMI: IOCK error (debug interrupt?) for reason %02x on CPU %d.\n", + reason, smp_processor_id()); show_registers(regs); if (panic_on_io_nmi) panic("NMI IOCK error: Not continuing"); /* Re-enable the IOCK line, wait for a few seconds */ - reason = (reason & 0xf) | 8; - outb(reason, 0x61); + reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_IOCHK; + outb(reason, NMI_REASON_PORT); i = 20000; while (--i) { @@ -357,8 +364,8 @@ io_check_error(unsigned char reason, struct pt_regs *regs) udelay(100); } - reason &= ~8; - outb(reason, 0x61); + reason &= ~NMI_REASON_CLEAR_IOCHK; + outb(reason, NMI_REASON_PORT); } static notrace __kprobes void @@ -377,57 +384,50 @@ unknown_nmi_error(unsigned char reason, struct pt_regs *regs) return; } #endif - printk(KERN_EMERG - "Uhhuh. NMI received for unknown reason %02x on CPU %d.\n", - reason, smp_processor_id()); + pr_emerg("Uhhuh. NMI received for unknown reason %02x on CPU %d.\n", + reason, smp_processor_id()); - printk(KERN_EMERG "Do you have a strange power saving mode enabled?\n"); + pr_emerg("Do you have a strange power saving mode enabled?\n"); if (unknown_nmi_panic || panic_on_unrecovered_nmi) panic("NMI: Not continuing"); - printk(KERN_EMERG "Dazed and confused, but trying to continue\n"); + pr_emerg("Dazed and confused, but trying to continue\n"); } static notrace __kprobes void default_do_nmi(struct pt_regs *regs) { unsigned char reason = 0; - int cpu; - cpu = smp_processor_id(); - - /* Only the BSP gets external NMIs from the system. */ - if (!cpu) - reason = get_nmi_reason(); + /* + * CPU-specific NMI must be processed before non-CPU-specific + * NMI, otherwise we may lose it, because the CPU-specific + * NMI can not be detected/processed on other CPUs. + */ + if (notify_die(DIE_NMI, "nmi", regs, 0, 2, SIGINT) == NOTIFY_STOP) + return; - if (!(reason & 0xc0)) { - if (notify_die(DIE_NMI_IPI, "nmi_ipi", regs, reason, 2, SIGINT) - == NOTIFY_STOP) - return; + /* Non-CPU-specific NMI: NMI sources can be processed on any CPU */ + raw_spin_lock(&nmi_reason_lock); + reason = get_nmi_reason(); -#ifdef CONFIG_X86_LOCAL_APIC - if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT) - == NOTIFY_STOP) - return; + if (reason & NMI_REASON_MASK) { + if (reason & NMI_REASON_SERR) + pci_serr_error(reason, regs); + else if (reason & NMI_REASON_IOCHK) + io_check_error(reason, regs); +#ifdef CONFIG_X86_32 + /* + * Reassert NMI in case it became active + * meanwhile as it's edge-triggered: + */ + reassert_nmi(); #endif - unknown_nmi_error(reason, regs); - + raw_spin_unlock(&nmi_reason_lock); return; } - if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT) == NOTIFY_STOP) - return; + raw_spin_unlock(&nmi_reason_lock); - /* AK: following checks seem to be broken on modern chipsets. FIXME */ - if (reason & 0x80) - mem_parity_error(reason, regs); - if (reason & 0x40) - io_check_error(reason, regs); -#ifdef CONFIG_X86_32 - /* - * Reassert NMI in case it became active meanwhile - * as it's edge-triggered: - */ - reassert_nmi(); -#endif + unknown_nmi_error(reason, regs); } dotraplinkage notrace __kprobes void diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 356a0d455cf..823f79a17ad 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -659,7 +659,7 @@ void restore_sched_clock_state(void) local_irq_save(flags); - __get_cpu_var(cyc2ns_offset) = 0; + __this_cpu_write(cyc2ns_offset, 0); offset = cyc2ns_suspend - sched_clock(); for_each_possible_cpu(cpu) @@ -965,7 +965,7 @@ out: static int __init init_tsc_clocksource(void) { - if (!cpu_has_tsc || tsc_disabled > 0) + if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz) return 0; if (tsc_clocksource_reliable) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index b989e1f1e5d..46a368cb651 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -976,7 +976,7 @@ static inline u64 nsec_to_cycles(u64 nsec) if (kvm_tsc_changes_freq()) printk_once(KERN_WARNING "kvm: unreliable cycle conversion on adjustable rate TSC\n"); - ret = nsec * __get_cpu_var(cpu_tsc_khz); + ret = nsec * __this_cpu_read(cpu_tsc_khz); do_div(ret, USEC_PER_SEC); return ret; } @@ -1061,7 +1061,7 @@ static int kvm_guest_time_update(struct kvm_vcpu *v) local_irq_save(flags); kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp); kernel_ns = get_kernel_ns(); - this_tsc_khz = __get_cpu_var(cpu_tsc_khz); + this_tsc_khz = __this_cpu_read(cpu_tsc_khz); if (unlikely(this_tsc_khz == 0)) { local_irq_restore(flags); @@ -4427,7 +4427,7 @@ EXPORT_SYMBOL_GPL(kvm_fast_pio_out); static void tsc_bad(void *info) { - __get_cpu_var(cpu_tsc_khz) = 0; + __this_cpu_write(cpu_tsc_khz, 0); } static void tsc_khz_changed(void *data) @@ -4441,7 +4441,7 @@ static void tsc_khz_changed(void *data) khz = cpufreq_quick_get(raw_smp_processor_id()); if (!khz) khz = tsc_khz; - __get_cpu_var(cpu_tsc_khz) = khz; + __this_cpu_write(cpu_tsc_khz, khz); } static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, diff --git a/arch/x86/lib/delay.c b/arch/x86/lib/delay.c index ff485d36118..fc45ba887d0 100644 --- a/arch/x86/lib/delay.c +++ b/arch/x86/lib/delay.c @@ -121,7 +121,7 @@ inline void __const_udelay(unsigned long xloops) asm("mull %%edx" :"=d" (xloops), "=&a" (d0) :"1" (xloops), "0" - (cpu_data(raw_smp_processor_id()).loops_per_jiffy * (HZ/4))); + (this_cpu_read(cpu_info.loops_per_jiffy) * (HZ/4))); __delay(++xloops); } diff --git a/arch/x86/mm/amdtopology_64.c b/arch/x86/mm/amdtopology_64.c index 51fae9cfdec..f21962c435e 100644 --- a/arch/x86/mm/amdtopology_64.c +++ b/arch/x86/mm/amdtopology_64.c @@ -27,6 +27,7 @@ #include <asm/amd_nb.h> static struct bootnode __initdata nodes[8]; +static unsigned char __initdata nodeids[8]; static nodemask_t __initdata nodes_parsed = NODE_MASK_NONE; static __init int find_northbridge(void) @@ -66,20 +67,6 @@ static __init void early_get_boot_cpu_id(void) if (smp_found_config) early_get_smp_config(); #endif - early_init_lapic_mapping(); -} - -int __init amd_get_nodes(struct bootnode *physnodes) -{ - int i; - int ret = 0; - - for_each_node_mask(i, nodes_parsed) { - physnodes[ret].start = nodes[i].start; - physnodes[ret].end = nodes[i].end; - ret++; - } - return ret; } int __init amd_numa_init(unsigned long start_pfn, unsigned long end_pfn) @@ -114,7 +101,7 @@ int __init amd_numa_init(unsigned long start_pfn, unsigned long end_pfn) base = read_pci_config(0, nb, 1, 0x40 + i*8); limit = read_pci_config(0, nb, 1, 0x44 + i*8); - nodeid = limit & 7; + nodeids[i] = nodeid = limit & 7; if ((base & 3) == 0) { if (i < numnodes) pr_info("Skipping disabled node %d\n", i); @@ -194,6 +181,76 @@ int __init amd_numa_init(unsigned long start_pfn, unsigned long end_pfn) return 0; } +#ifdef CONFIG_NUMA_EMU +static s16 fake_apicid_to_node[MAX_LOCAL_APIC] __initdata = { + [0 ... MAX_LOCAL_APIC-1] = NUMA_NO_NODE +}; + +void __init amd_get_nodes(struct bootnode *physnodes) +{ + int i; + + for_each_node_mask(i, nodes_parsed) { + physnodes[i].start = nodes[i].start; + physnodes[i].end = nodes[i].end; + } +} + +static int __init find_node_by_addr(unsigned long addr) +{ + int ret = NUMA_NO_NODE; + int i; + + for (i = 0; i < 8; i++) + if (addr >= nodes[i].start && addr < nodes[i].end) { + ret = i; + break; + } + return ret; +} + +/* + * For NUMA emulation, fake proximity domain (_PXM) to node id mappings must be + * setup to represent the physical topology but reflect the emulated + * environment. For each emulated node, the real node which it appears on is + * found and a fake pxm to nid mapping is created which mirrors the actual + * locality. node_distance() then represents the correct distances between + * emulated nodes by using the fake acpi mappings to pxms. + */ +void __init amd_fake_nodes(const struct bootnode *nodes, int nr_nodes) +{ + unsigned int bits; + unsigned int cores; + unsigned int apicid_base = 0; + int i; + + bits = boot_cpu_data.x86_coreid_bits; + cores = 1 << bits; + early_get_boot_cpu_id(); + if (boot_cpu_physical_apicid > 0) + apicid_base = boot_cpu_physical_apicid; + + for (i = 0; i < nr_nodes; i++) { + int index; + int nid; + int j; + + nid = find_node_by_addr(nodes[i].start); + if (nid == NUMA_NO_NODE) + continue; + + index = nodeids[nid] << bits; + if (fake_apicid_to_node[index + apicid_base] == NUMA_NO_NODE) + for (j = apicid_base; j < cores + apicid_base; j++) + fake_apicid_to_node[index + j] = i; +#ifdef CONFIG_ACPI_NUMA + __acpi_map_pxm_to_node(nid, i); +#endif + } + memcpy(apicid_to_node, fake_apicid_to_node, sizeof(apicid_to_node)); +} +#endif /* CONFIG_NUMA_EMU */ + int __init amd_scan_nodes(void) { unsigned int bits; diff --git a/arch/x86/mm/numa_64.c b/arch/x86/mm/numa_64.c index 7762a517d69..1e72102e80c 100644 --- a/arch/x86/mm/numa_64.c +++ b/arch/x86/mm/numa_64.c @@ -260,30 +260,30 @@ void __init numa_init_array(void) #ifdef CONFIG_NUMA_EMU /* Numa emulation */ static struct bootnode nodes[MAX_NUMNODES] __initdata; -static struct bootnode physnodes[MAX_NUMNODES] __initdata; +static struct bootnode physnodes[MAX_NUMNODES] __cpuinitdata; static char *cmdline __initdata; static int __init setup_physnodes(unsigned long start, unsigned long end, int acpi, int amd) { - int nr_nodes = 0; int ret = 0; int i; + memset(physnodes, 0, sizeof(physnodes)); #ifdef CONFIG_ACPI_NUMA if (acpi) - nr_nodes = acpi_get_nodes(physnodes); + acpi_get_nodes(physnodes, start, end); #endif #ifdef CONFIG_AMD_NUMA if (amd) - nr_nodes = amd_get_nodes(physnodes); + amd_get_nodes(physnodes); #endif /* * Basic sanity checking on the physical node map: there may be errors * if the SRAT or AMD code incorrectly reported the topology or the mem= * kernel parameter is used. */ - for (i = 0; i < nr_nodes; i++) { + for (i = 0; i < MAX_NUMNODES; i++) { if (physnodes[i].start == physnodes[i].end) continue; if (physnodes[i].start > end) { @@ -298,17 +298,6 @@ static int __init setup_physnodes(unsigned long start, unsigned long end, physnodes[i].start = start; if (physnodes[i].end > end) physnodes[i].end = end; - } - - /* - * Remove all nodes that have no memory or were truncated because of the - * limited address range. - */ - for (i = 0; i < nr_nodes; i++) { - if (physnodes[i].start == physnodes[i].end) - continue; - physnodes[ret].start = physnodes[i].start; - physnodes[ret].end = physnodes[i].end; ret++; } @@ -324,6 +313,24 @@ static int __init setup_physnodes(unsigned long start, unsigned long end, return ret; } +static void __init fake_physnodes(int acpi, int amd, int nr_nodes) +{ + int i; + + BUG_ON(acpi && amd); +#ifdef CONFIG_ACPI_NUMA + if (acpi) + acpi_fake_nodes(nodes, nr_nodes); +#endif +#ifdef CONFIG_AMD_NUMA + if (amd) + amd_fake_nodes(nodes, nr_nodes); +#endif + if (!acpi && !amd) + for (i = 0; i < nr_cpu_ids; i++) + numa_set_node(i, 0); +} + /* * Setups up nid to range from addr to addr + size. If the end * boundary is greater than max_addr, then max_addr is used instead. @@ -352,8 +359,7 @@ static int __init setup_node_range(int nid, u64 *addr, u64 size, u64 max_addr) * Sets up nr_nodes fake nodes interleaved over physical nodes ranging from addr * to max_addr. The return value is the number of nodes allocated. */ -static int __init split_nodes_interleave(u64 addr, u64 max_addr, - int nr_phys_nodes, int nr_nodes) +static int __init split_nodes_interleave(u64 addr, u64 max_addr, int nr_nodes) { nodemask_t physnode_mask = NODE_MASK_NONE; u64 size; @@ -384,7 +390,7 @@ static int __init split_nodes_interleave(u64 addr, u64 max_addr, return -1; } - for (i = 0; i < nr_phys_nodes; i++) + for (i = 0; i < MAX_NUMNODES; i++) if (physnodes[i].start != physnodes[i].end) node_set(i, physnode_mask); @@ -553,11 +559,9 @@ static int __init numa_emulation(unsigned long start_pfn, { u64 addr = start_pfn << PAGE_SHIFT; u64 max_addr = last_pfn << PAGE_SHIFT; - int num_phys_nodes; int num_nodes; int i; - num_phys_nodes = setup_physnodes(addr, max_addr, acpi, amd); /* * If the numa=fake command-line contains a 'M' or 'G', it represents * the fixed node size. Otherwise, if it is just a single number N, @@ -572,7 +576,7 @@ static int __init numa_emulation(unsigned long start_pfn, unsigned long n; n = simple_strtoul(cmdline, NULL, 0); - num_nodes = split_nodes_interleave(addr, max_addr, num_phys_nodes, n); + num_nodes = split_nodes_interleave(addr, max_addr, n); } if (num_nodes < 0) @@ -595,7 +599,8 @@ static int __init numa_emulation(unsigned long start_pfn, nodes[i].end >> PAGE_SHIFT); setup_node_bootmem(i, nodes[i].start, nodes[i].end); } - acpi_fake_nodes(nodes, num_nodes); + setup_physnodes(addr, max_addr, acpi, amd); + fake_physnodes(acpi, amd, num_nodes); numa_init_array(); return 0; } @@ -610,8 +615,12 @@ void __init initmem_init(unsigned long start_pfn, unsigned long last_pfn, nodes_clear(node_online_map); #ifdef CONFIG_NUMA_EMU + setup_physnodes(start_pfn << PAGE_SHIFT, last_pfn << PAGE_SHIFT, + acpi, amd); if (cmdline && !numa_emulation(start_pfn, last_pfn, acpi, amd)) return; + setup_physnodes(start_pfn << PAGE_SHIFT, last_pfn << PAGE_SHIFT, + acpi, amd); nodes_clear(node_possible_map); nodes_clear(node_online_map); #endif @@ -767,6 +776,7 @@ void __cpuinit numa_clear_node(int cpu) #ifndef CONFIG_DEBUG_PER_CPU_MAPS +#ifndef CONFIG_NUMA_EMU void __cpuinit numa_add_cpu(int cpu) { cpumask_set_cpu(cpu, node_to_cpumask_map[early_cpu_to_node(cpu)]); @@ -776,34 +786,115 @@ void __cpuinit numa_remove_cpu(int cpu) { cpumask_clear_cpu(cpu, node_to_cpumask_map[early_cpu_to_node(cpu)]); } +#else +void __cpuinit numa_add_cpu(int cpu) +{ + unsigned long addr; + u16 apicid; + int physnid; + int nid = NUMA_NO_NODE; + + apicid = early_per_cpu(x86_cpu_to_apicid, cpu); + if (apicid != BAD_APICID) + nid = apicid_to_node[apicid]; + if (nid == NUMA_NO_NODE) + nid = early_cpu_to_node(cpu); + BUG_ON(nid == NUMA_NO_NODE || !node_online(nid)); + + /* + * Use the starting address of the emulated node to find which physical + * node it is allocated on. + */ + addr = node_start_pfn(nid) << PAGE_SHIFT; + for (physnid = 0; physnid < MAX_NUMNODES; physnid++) + if (addr >= physnodes[physnid].start && + addr < physnodes[physnid].end) + break; + + /* + * Map the cpu to each emulated node that is allocated on the physical + * node of the cpu's apic id. + */ + for_each_online_node(nid) { + addr = node_start_pfn(nid) << PAGE_SHIFT; + if (addr >= physnodes[physnid].start && + addr < physnodes[physnid].end) + cpumask_set_cpu(cpu, node_to_cpumask_map[nid]); + } +} + +void __cpuinit numa_remove_cpu(int cpu) +{ + int i; + + for_each_online_node(i) + cpumask_clear_cpu(cpu, node_to_cpumask_map[i]); +} +#endif /* !CONFIG_NUMA_EMU */ #else /* CONFIG_DEBUG_PER_CPU_MAPS */ +static struct cpumask __cpuinit *debug_cpumask_set_cpu(int cpu, int enable) +{ + int node = early_cpu_to_node(cpu); + struct cpumask *mask; + char buf[64]; + + mask = node_to_cpumask_map[node]; + if (!mask) { + pr_err("node_to_cpumask_map[%i] NULL\n", node); + dump_stack(); + return NULL; + } + + cpulist_scnprintf(buf, sizeof(buf), mask); + printk(KERN_DEBUG "%s cpu %d node %d: mask now %s\n", + enable ? "numa_add_cpu" : "numa_remove_cpu", + cpu, node, buf); + return mask; +} /* * --------- debug versions of the numa functions --------- */ +#ifndef CONFIG_NUMA_EMU static void __cpuinit numa_set_cpumask(int cpu, int enable) { - int node = early_cpu_to_node(cpu); struct cpumask *mask; - char buf[64]; - mask = node_to_cpumask_map[node]; - if (mask == NULL) { - printk(KERN_ERR "node_to_cpumask_map[%i] NULL\n", node); - dump_stack(); + mask = debug_cpumask_set_cpu(cpu, enable); + if (!mask) return; - } if (enable) cpumask_set_cpu(cpu, mask); else cpumask_clear_cpu(cpu, mask); +} +#else +static void __cpuinit numa_set_cpumask(int cpu, int enable) +{ + int node = early_cpu_to_node(cpu); + struct cpumask *mask; + int i; - cpulist_scnprintf(buf, sizeof(buf), mask); - printk(KERN_DEBUG "%s cpu %d node %d: mask now %s\n", - enable ? "numa_add_cpu" : "numa_remove_cpu", cpu, node, buf); + for_each_online_node(i) { + unsigned long addr; + + addr = node_start_pfn(i) << PAGE_SHIFT; + if (addr < physnodes[node].start || + addr >= physnodes[node].end) + continue; + mask = debug_cpumask_set_cpu(cpu, enable); + if (!mask) + return; + + if (enable) + cpumask_set_cpu(cpu, mask); + else + cpumask_clear_cpu(cpu, mask); + } } +#endif /* CONFIG_NUMA_EMU */ void __cpuinit numa_add_cpu(int cpu) { diff --git a/arch/x86/mm/srat_64.c b/arch/x86/mm/srat_64.c index 171a0aacb99..603d285d1da 100644 --- a/arch/x86/mm/srat_64.c +++ b/arch/x86/mm/srat_64.c @@ -349,18 +349,19 @@ static int __init nodes_cover_memory(const struct bootnode *nodes) void __init acpi_numa_arch_fixup(void) {} -int __init acpi_get_nodes(struct bootnode *physnodes) +#ifdef CONFIG_NUMA_EMU +void __init acpi_get_nodes(struct bootnode *physnodes, unsigned long start, + unsigned long end) { int i; - int ret = 0; for_each_node_mask(i, nodes_parsed) { - physnodes[ret].start = nodes[i].start; - physnodes[ret].end = nodes[i].end; - ret++; + cutoff_node(i, start, end); + physnodes[i].start = nodes[i].start; + physnodes[i].end = nodes[i].end; } - return ret; } +#endif /* CONFIG_NUMA_EMU */ /* Use the information discovered above to actually set up the nodes. */ int __init acpi_scan_nodes(unsigned long start, unsigned long end) @@ -505,8 +506,6 @@ void __init acpi_fake_nodes(const struct bootnode *fake_nodes, int num_nodes) { int i, j; - printk(KERN_INFO "Faking PXM affinity for fake nodes on real " - "topology.\n"); for (i = 0; i < num_nodes; i++) { int nid, pxm; @@ -526,6 +525,17 @@ void __init acpi_fake_nodes(const struct bootnode *fake_nodes, int num_nodes) fake_apicid_to_node[j] == NUMA_NO_NODE) fake_apicid_to_node[j] = i; } + + /* + * If there are apicid-to-node mappings for physical nodes that do not + * have a corresponding emulated node, it should default to a guaranteed + * value. + */ + for (i = 0; i < MAX_LOCAL_APIC; i++) + if (apicid_to_node[i] != NUMA_NO_NODE && + fake_apicid_to_node[i] == NUMA_NO_NODE) + fake_apicid_to_node[i] = 0; + for (i = 0; i < num_nodes; i++) __acpi_map_pxm_to_node(fake_node_to_pxm_map[i], i); memcpy(apicid_to_node, fake_apicid_to_node, sizeof(apicid_to_node)); diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c index 358c8b9c96a..e2b7b0c06cd 100644 --- a/arch/x86/oprofile/nmi_int.c +++ b/arch/x86/oprofile/nmi_int.c @@ -65,7 +65,6 @@ static int profile_exceptions_notify(struct notifier_block *self, switch (val) { case DIE_NMI: - case DIE_NMI_IPI: if (ctr_running) model->check_ctrs(args->regs, &__get_cpu_var(cpu_msrs)); else if (!nmi_enabled) @@ -143,7 +142,7 @@ static inline int has_mux(void) inline int op_x86_phys_to_virt(int phys) { - return __get_cpu_var(switch_index) + phys; + return __this_cpu_read(switch_index) + phys; } inline int op_x86_virt_to_phys(int virt) @@ -361,7 +360,7 @@ static void nmi_cpu_setup(void *dummy) static struct notifier_block profile_exceptions_nb = { .notifier_call = profile_exceptions_notify, .next = NULL, - .priority = 2 + .priority = NMI_LOCAL_LOW_PRIOR, }; static void nmi_cpu_restore_registers(struct op_msrs *msrs) diff --git a/arch/x86/oprofile/nmi_timer_int.c b/arch/x86/oprofile/nmi_timer_int.c index 0636dd93cef..720bf5a53c5 100644 --- a/arch/x86/oprofile/nmi_timer_int.c +++ b/arch/x86/oprofile/nmi_timer_int.c @@ -38,7 +38,7 @@ static int profile_timer_exceptions_notify(struct notifier_block *self, static struct notifier_block profile_timer_exceptions_nb = { .notifier_call = profile_timer_exceptions_notify, .next = NULL, - .priority = 0 + .priority = NMI_LOW_PRIOR, }; static int timer_start(void) diff --git a/arch/x86/oprofile/op_model_ppro.c b/arch/x86/oprofile/op_model_ppro.c index d769cda5408..94b745045e4 100644 --- a/arch/x86/oprofile/op_model_ppro.c +++ b/arch/x86/oprofile/op_model_ppro.c @@ -95,8 +95,8 @@ static void ppro_setup_ctrs(struct op_x86_model_spec const *model, * counter width: */ if (!(eax.split.version_id == 0 && - current_cpu_data.x86 == 6 && - current_cpu_data.x86_model == 15)) { + __this_cpu_read(cpu_info.x86) == 6 && + __this_cpu_read(cpu_info.x86_model) == 15)) { if (counter_width < eax.split.bit_width) counter_width = eax.split.bit_width; @@ -235,8 +235,8 @@ static void arch_perfmon_setup_counters(void) eax.full = cpuid_eax(0xa); /* Workaround for BIOS bugs in 6/15. Taken from perfmon2 */ - if (eax.split.version_id == 0 && current_cpu_data.x86 == 6 && - current_cpu_data.x86_model == 15) { + if (eax.split.version_id == 0 && __this_cpu_read(cpu_info.x86) == 6 && + __this_cpu_read(cpu_info.x86_model) == 15) { eax.split.version_id = 2; eax.split.num_counters = 2; eax.split.bit_width = 40; diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c index fc1e8fe07e5..e27dffbbb1a 100644 --- a/arch/x86/pci/amd_bus.c +++ b/arch/x86/pci/amd_bus.c @@ -4,6 +4,7 @@ #include <linux/cpu.h> #include <linux/range.h> +#include <asm/amd_nb.h> #include <asm/pci_x86.h> #include <asm/pci-direct.h> @@ -378,6 +379,34 @@ static struct notifier_block __cpuinitdata amd_cpu_notifier = { .notifier_call = amd_cpu_notify, }; +static void __init pci_enable_pci_io_ecs(void) +{ +#ifdef CONFIG_AMD_NB + unsigned int i, n; + + for (n = i = 0; !n && amd_nb_bus_dev_ranges[i].dev_limit; ++i) { + u8 bus = amd_nb_bus_dev_ranges[i].bus; + u8 slot = amd_nb_bus_dev_ranges[i].dev_base; + u8 limit = amd_nb_bus_dev_ranges[i].dev_limit; + + for (; slot < limit; ++slot) { + u32 val = read_pci_config(bus, slot, 3, 0); + + if (!early_is_amd_nb(val)) + continue; + + val = read_pci_config(bus, slot, 3, 0x8c); + if (!(val & (ENABLE_CF8_EXT_CFG >> 32))) { + val |= ENABLE_CF8_EXT_CFG >> 32; + write_pci_config(bus, slot, 3, 0x8c, val); + } + ++n; + } + } + pr_info("Extended Config Space enabled on %u nodes\n", n); +#endif +} + static int __init pci_io_ecs_init(void) { int cpu; @@ -386,6 +415,10 @@ static int __init pci_io_ecs_init(void) if (boot_cpu_data.x86 < 0x10) return 0; + /* Try the PCI method first. */ + if (early_pci_allowed()) + pci_enable_pci_io_ecs(); + register_cpu_notifier(&amd_cpu_notifier); for_each_online_cpu(cpu) amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE, diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c index fee0b4914e0..ea6529e93c6 100644 --- a/arch/x86/platform/mrst/mrst.c +++ b/arch/x86/platform/mrst/mrst.c @@ -71,32 +71,6 @@ struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX]; EXPORT_SYMBOL_GPL(sfi_mrtc_array); int sfi_mrtc_num; -static inline void assign_to_mp_irq(struct mpc_intsrc *m, - struct mpc_intsrc *mp_irq) -{ - memcpy(mp_irq, m, sizeof(struct mpc_intsrc)); -} - -static inline int mp_irq_cmp(struct mpc_intsrc *mp_irq, - struct mpc_intsrc *m) -{ - return memcmp(mp_irq, m, sizeof(struct mpc_intsrc)); -} - -static void save_mp_irq(struct mpc_intsrc *m) -{ - int i; - - for (i = 0; i < mp_irq_entries; i++) { - if (!mp_irq_cmp(&mp_irqs[i], m)) - return; - } - - assign_to_mp_irq(m, &mp_irqs[mp_irq_entries]); - if (++mp_irq_entries == MAX_IRQ_SOURCES) - panic("Max # of irq sources exceeded!!\n"); -} - /* parse all the mtimer info to a static mtimer array */ static int __init sfi_parse_mtmr(struct sfi_table_header *table) { @@ -130,7 +104,7 @@ static int __init sfi_parse_mtmr(struct sfi_table_header *table) mp_irq.srcbusirq = pentry->irq; /* IRQ */ mp_irq.dstapic = MP_APIC_ALL; mp_irq.dstirq = pentry->irq; - save_mp_irq(&mp_irq); + mp_save_irq(&mp_irq); } return 0; @@ -200,7 +174,7 @@ int __init sfi_parse_mrtc(struct sfi_table_header *table) mp_irq.srcbusirq = pentry->irq; /* IRQ */ mp_irq.dstapic = MP_APIC_ALL; mp_irq.dstirq = pentry->irq; - save_mp_irq(&mp_irq); + mp_save_irq(&mp_irq); } return 0; } diff --git a/arch/x86/platform/sfi/sfi.c b/arch/x86/platform/sfi/sfi.c index ca54875ac79..7785b72ecc3 100644 --- a/arch/x86/platform/sfi/sfi.c +++ b/arch/x86/platform/sfi/sfi.c @@ -34,17 +34,6 @@ #ifdef CONFIG_X86_LOCAL_APIC static unsigned long sfi_lapic_addr __initdata = APIC_DEFAULT_PHYS_BASE; -static void __init mp_sfi_register_lapic_address(unsigned long address) -{ - mp_lapic_addr = address; - - set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); - if (boot_cpu_physical_apicid == -1U) - boot_cpu_physical_apicid = read_apic_id(); - - pr_info("Boot CPU = %d\n", boot_cpu_physical_apicid); -} - /* All CPUs enumerated by SFI must be present and enabled */ static void __cpuinit mp_sfi_register_lapic(u8 id) { @@ -110,7 +99,7 @@ static int __init sfi_parse_ioapic(struct sfi_table_header *table) int __init sfi_platform_init(void) { #ifdef CONFIG_X86_LOCAL_APIC - mp_sfi_register_lapic_address(sfi_lapic_addr); + register_lapic_address(sfi_lapic_addr); sfi_table_parse(SFI_SIG_CPUS, NULL, NULL, sfi_parse_cpus); #endif #ifdef CONFIG_X86_IO_APIC diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index 44dcad43989..7e8d3bc80af 100644 --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c @@ -574,8 +574,8 @@ static void xen_write_idt_entry(gate_desc *dt, int entrynum, const gate_desc *g) preempt_disable(); - start = __get_cpu_var(idt_desc).address; - end = start + __get_cpu_var(idt_desc).size + 1; + start = __this_cpu_read(idt_desc.address); + end = start + __this_cpu_read(idt_desc.size) + 1; xen_mc_flush(); @@ -1174,6 +1174,15 @@ asmlinkage void __init xen_start_kernel(void) xen_smp_init(); +#ifdef CONFIG_ACPI_NUMA + /* + * The pages we from Xen are not related to machine pages, so + * any NUMA information the kernel tries to get from ACPI will + * be meaningless. Prevent it from trying. + */ + acpi_numa = -1; +#endif + pgd = (pgd_t *)xen_start_info->pt_base; if (!xen_initial_domain()) @@ -1256,25 +1265,6 @@ asmlinkage void __init xen_start_kernel(void) #endif } -static uint32_t xen_cpuid_base(void) -{ - uint32_t base, eax, ebx, ecx, edx; - char signature[13]; - - for (base = 0x40000000; base < 0x40010000; base += 0x100) { - cpuid(base, &eax, &ebx, &ecx, &edx); - *(uint32_t *)(signature + 0) = ebx; - *(uint32_t *)(signature + 4) = ecx; - *(uint32_t *)(signature + 8) = edx; - signature[12] = 0; - - if (!strcmp("XenVMMXenVMM", signature) && ((eax - base) >= 2)) - return base; - } - - return 0; -} - static int init_hvm_pv_info(int *major, int *minor) { uint32_t eax, ebx, ecx, edx, pages, msr, base; @@ -1384,6 +1374,18 @@ static bool __init xen_hvm_platform(void) return true; } +bool xen_hvm_need_lapic(void) +{ + if (xen_pv_domain()) + return false; + if (!xen_hvm_domain()) + return false; + if (xen_feature(XENFEAT_hvm_pirqs) && xen_have_vector_callback) + return false; + return true; +} +EXPORT_SYMBOL_GPL(xen_hvm_need_lapic); + const __refconst struct hypervisor_x86 x86_hyper_xen_hvm = { .name = "Xen HVM", .detect = xen_hvm_platform, diff --git a/arch/x86/xen/multicalls.h b/arch/x86/xen/multicalls.h index 9e565da5d1f..4ec8035e321 100644 --- a/arch/x86/xen/multicalls.h +++ b/arch/x86/xen/multicalls.h @@ -22,7 +22,7 @@ static inline void xen_mc_batch(void) unsigned long flags; /* need to disable interrupts until this entry is complete */ local_irq_save(flags); - __get_cpu_var(xen_mc_irq_flags) = flags; + __this_cpu_write(xen_mc_irq_flags, flags); } static inline struct multicall_space xen_mc_entry(size_t args) diff --git a/arch/x86/xen/spinlock.c b/arch/x86/xen/spinlock.c index 23e061b9327..cc9b1e182fc 100644 --- a/arch/x86/xen/spinlock.c +++ b/arch/x86/xen/spinlock.c @@ -159,8 +159,8 @@ static inline struct xen_spinlock *spinning_lock(struct xen_spinlock *xl) { struct xen_spinlock *prev; - prev = __get_cpu_var(lock_spinners); - __get_cpu_var(lock_spinners) = xl; + prev = __this_cpu_read(lock_spinners); + __this_cpu_write(lock_spinners, xl); wmb(); /* set lock of interest before count */ @@ -179,14 +179,14 @@ static inline void unspinning_lock(struct xen_spinlock *xl, struct xen_spinlock asm(LOCK_PREFIX " decw %0" : "+m" (xl->spinners) : : "memory"); wmb(); /* decrement count before restoring lock */ - __get_cpu_var(lock_spinners) = prev; + __this_cpu_write(lock_spinners, prev); } static noinline int xen_spin_lock_slow(struct arch_spinlock *lock, bool irq_enable) { struct xen_spinlock *xl = (struct xen_spinlock *)lock; struct xen_spinlock *prev; - int irq = __get_cpu_var(lock_kicker_irq); + int irq = __this_cpu_read(lock_kicker_irq); int ret; u64 start; diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c index 5da5e53fb94..067759e3d6a 100644 --- a/arch/x86/xen/time.c +++ b/arch/x86/xen/time.c @@ -135,24 +135,24 @@ static void do_stolen_accounting(void) /* Add the appropriate number of ticks of stolen time, including any left-overs from last time. */ - stolen = runnable + offline + __get_cpu_var(xen_residual_stolen); + stolen = runnable + offline + __this_cpu_read(xen_residual_stolen); if (stolen < 0) stolen = 0; ticks = iter_div_u64_rem(stolen, NS_PER_TICK, &stolen); - __get_cpu_var(xen_residual_stolen) = stolen; + __this_cpu_write(xen_residual_stolen, stolen); account_steal_ticks(ticks); /* Add the appropriate number of ticks of blocked time, including any left-overs from last time. */ - blocked += __get_cpu_var(xen_residual_blocked); + blocked += __this_cpu_read(xen_residual_blocked); if (blocked < 0) blocked = 0; ticks = iter_div_u64_rem(blocked, NS_PER_TICK, &blocked); - __get_cpu_var(xen_residual_blocked) = blocked; + __this_cpu_write(xen_residual_blocked, blocked); account_idle_ticks(ticks); } |