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-rw-r--r--arch/arm/mach-bcm/Kconfig1
-rw-r--r--arch/arm/plat-orion/gpio.c8
2 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 1bd39b45d08..aaeec78c3ec 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -143,6 +143,7 @@ config ARCH_BRCMSTB
select HAVE_ARM_ARCH_TIMER
select BRCMSTB_GISB_ARB
select BRCMSTB_L2_IRQ
+ select BCM7120_L2_IRQ
help
Say Y if you intend to run the kernel on a Broadcom ARM-based STB
chipset.
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index e048f6198d6..14f6e647c73 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -505,9 +505,9 @@ static void orion_gpio_unmask_irq(struct irq_data *d)
u32 mask = d->mask;
irq_gc_lock(gc);
- reg_val = irq_reg_readl(gc->reg_base + ct->regs.mask);
+ reg_val = irq_reg_readl(gc, ct->regs.mask);
reg_val |= mask;
- irq_reg_writel(reg_val, gc->reg_base + ct->regs.mask);
+ irq_reg_writel(gc, reg_val, ct->regs.mask);
irq_gc_unlock(gc);
}
@@ -519,9 +519,9 @@ static void orion_gpio_mask_irq(struct irq_data *d)
u32 reg_val;
irq_gc_lock(gc);
- reg_val = irq_reg_readl(gc->reg_base + ct->regs.mask);
+ reg_val = irq_reg_readl(gc, ct->regs.mask);
reg_val &= ~mask;
- irq_reg_writel(reg_val, gc->reg_base + ct->regs.mask);
+ irq_reg_writel(gc, reg_val, ct->regs.mask);
irq_gc_unlock(gc);
}