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-rw-r--r--drivers/bcma/driver_pci.c124
1 files changed, 70 insertions, 54 deletions
diff --git a/drivers/bcma/driver_pci.c b/drivers/bcma/driver_pci.c
index 4fde6254f04..fc462b4a099 100644
--- a/drivers/bcma/driver_pci.c
+++ b/drivers/bcma/driver_pci.c
@@ -4,6 +4,7 @@
*
* Copyright 2005, Broadcom Corporation
* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
+ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
*
* Licensed under the GNU/GPL. See COPYING for details.
*/
@@ -18,38 +19,39 @@
static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
{
- pcicore_write32(pc, 0x130, address);
- pcicore_read32(pc, 0x130);
- return pcicore_read32(pc, 0x134);
+ pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
+ pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
+ return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
}
#if 0
static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
{
- pcicore_write32(pc, 0x130, address);
- pcicore_read32(pc, 0x130);
- pcicore_write32(pc, 0x134, data);
+ pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
+ pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
+ pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
}
#endif
static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
{
- const u16 mdio_control = 0x128;
- const u16 mdio_data = 0x12C;
u32 v;
int i;
- v = (1 << 30); /* Start of Transaction */
- v |= (1 << 28); /* Write Transaction */
- v |= (1 << 17); /* Turnaround */
- v |= (0x1F << 18);
+ v = BCMA_CORE_PCI_MDIODATA_START;
+ v |= BCMA_CORE_PCI_MDIODATA_WRITE;
+ v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
+ BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
+ v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
+ BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
+ v |= BCMA_CORE_PCI_MDIODATA_TA;
v |= (phy << 4);
- pcicore_write32(pc, mdio_data, v);
+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
udelay(10);
for (i = 0; i < 200; i++) {
- v = pcicore_read32(pc, mdio_control);
- if (v & 0x100 /* Trans complete */)
+ v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
+ if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
break;
msleep(1);
}
@@ -57,79 +59,84 @@ static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
{
- const u16 mdio_control = 0x128;
- const u16 mdio_data = 0x12C;
int max_retries = 10;
u16 ret = 0;
u32 v;
int i;
- v = 0x80; /* Enable Preamble Sequence */
- v |= 0x2; /* MDIO Clock Divisor */
- pcicore_write32(pc, mdio_control, v);
+ /* enable mdio access to SERDES */
+ v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
+ v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
if (pc->core->id.rev >= 10) {
max_retries = 200;
bcma_pcie_mdio_set_phy(pc, device);
+ v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
+ BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
+ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
+ } else {
+ v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
+ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
}
- v = (1 << 30); /* Start of Transaction */
- v |= (1 << 29); /* Read Transaction */
- v |= (1 << 17); /* Turnaround */
- if (pc->core->id.rev < 10)
- v |= (u32)device << 22;
- v |= (u32)address << 18;
- pcicore_write32(pc, mdio_data, v);
+ v = BCMA_CORE_PCI_MDIODATA_START;
+ v |= BCMA_CORE_PCI_MDIODATA_READ;
+ v |= BCMA_CORE_PCI_MDIODATA_TA;
+
+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
/* Wait for the device to complete the transaction */
udelay(10);
for (i = 0; i < max_retries; i++) {
- v = pcicore_read32(pc, mdio_control);
- if (v & 0x100 /* Trans complete */) {
+ v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
+ if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
udelay(10);
- ret = pcicore_read32(pc, mdio_data);
+ ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
break;
}
msleep(1);
}
- pcicore_write32(pc, mdio_control, 0);
+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
return ret;
}
static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
u8 address, u16 data)
{
- const u16 mdio_control = 0x128;
- const u16 mdio_data = 0x12C;
int max_retries = 10;
u32 v;
int i;
- v = 0x80; /* Enable Preamble Sequence */
- v |= 0x2; /* MDIO Clock Divisor */
- pcicore_write32(pc, mdio_control, v);
+ /* enable mdio access to SERDES */
+ v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
+ v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
if (pc->core->id.rev >= 10) {
max_retries = 200;
bcma_pcie_mdio_set_phy(pc, device);
+ v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
+ BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
+ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
+ } else {
+ v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
+ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
}
- v = (1 << 30); /* Start of Transaction */
- v |= (1 << 28); /* Write Transaction */
- v |= (1 << 17); /* Turnaround */
- if (pc->core->id.rev < 10)
- v |= (u32)device << 22;
- v |= (u32)address << 18;
+ v = BCMA_CORE_PCI_MDIODATA_START;
+ v |= BCMA_CORE_PCI_MDIODATA_WRITE;
+ v |= BCMA_CORE_PCI_MDIODATA_TA;
v |= data;
- pcicore_write32(pc, mdio_data, v);
+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
/* Wait for the device to complete the transaction */
udelay(10);
for (i = 0; i < max_retries; i++) {
- v = pcicore_read32(pc, mdio_control);
- if (v & 0x100 /* Trans complete */)
+ v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
+ if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
break;
msleep(1);
}
- pcicore_write32(pc, mdio_control, 0);
+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
}
/**************************************************
@@ -138,20 +145,29 @@ static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
{
- return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
+ u32 tmp;
+
+ tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
+ if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
+ return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
+ BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
+ else
+ return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
}
static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
{
- const u8 serdes_pll_device = 0x1D;
- const u8 serdes_rx_device = 0x1F;
u16 tmp;
- bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
- bcma_pcicore_polarity_workaround(pc));
- tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
- if (tmp & 0x4000)
- bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
+ bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
+ BCMA_CORE_PCI_SERDES_RX_CTRL,
+ bcma_pcicore_polarity_workaround(pc));
+ tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
+ BCMA_CORE_PCI_SERDES_PLL_CTRL);
+ if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
+ bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
+ BCMA_CORE_PCI_SERDES_PLL_CTRL,
+ tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
}
/**************************************************
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2024-11-19 19:33:36 +0000