diff options
Diffstat (limited to 'drivers/edac')
-rw-r--r-- | drivers/edac/edac_core.h | 4 | ||||
-rw-r--r-- | drivers/edac/edac_device.c | 6 | ||||
-rw-r--r-- | drivers/edac/edac_mc.c | 2 | ||||
-rw-r--r-- | drivers/edac/i7core_edac.c | 25 | ||||
-rw-r--r-- | drivers/edac/mce_amd.h | 2 | ||||
-rw-r--r-- | drivers/edac/mpc85xx_edac.c | 3 | ||||
-rw-r--r-- | drivers/edac/sb_edac.c | 16 |
7 files changed, 25 insertions, 33 deletions
diff --git a/drivers/edac/edac_core.h b/drivers/edac/edac_core.h index 3843222e5b9..23bb99fa44f 100644 --- a/drivers/edac/edac_core.h +++ b/drivers/edac/edac_core.h @@ -102,13 +102,13 @@ do { \ * * CPU caches (L1 and L2) * DMA engines - * Core CPU swithces + * Core CPU switches * Fabric switch units * PCIe interface controllers * other EDAC/ECC type devices that can be monitored for * errors, etc. * - * It allows for a 2 level set of hiearchry. For example: + * It allows for a 2 level set of hierarchy. For example: * * cache could be composed of L1, L2 and L3 levels of cache. * Each CPU core would have its own L1 cache, while sharing diff --git a/drivers/edac/edac_device.c b/drivers/edac/edac_device.c index 9523e76191f..211021dfec7 100644 --- a/drivers/edac/edac_device.c +++ b/drivers/edac/edac_device.c @@ -57,7 +57,7 @@ static void edac_device_dump_device(struct edac_device_ctl_info *edac_dev) * * The control structure is allocated in complete chunk * from the OS. It is in turn sub allocated to the - * various objects that compose the struture + * various objects that compose the structure * * The structure has a 'nr_instance' array within itself. * Each instance represents a major component @@ -386,7 +386,7 @@ static void edac_device_workq_function(struct work_struct *work_req) /* Reschedule the workq for the next time period to start again * if the number of msec is for 1 sec, then adjust to the next - * whole one second to save timers fireing all over the period + * whole one second to save timers firing all over the period * between integral seconds */ if (edac_dev->poll_msec == 1000) @@ -555,7 +555,7 @@ EXPORT_SYMBOL_GPL(edac_device_add_device); * Remove sysfs entries for specified edac_device structure and * then remove edac_device structure from global list * - * @pdev: + * @dev: * Pointer to 'struct device' representing edac_device * structure to remove. * diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 8d59378f839..616d90bcb3a 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -189,7 +189,7 @@ void *edac_align_ptr(void **p, unsigned size, int n_elems) else return (char *)ptr; - r = size % align; + r = (unsigned long)p % align; if (r == 0) return (char *)ptr; diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c index a3c9a37b4cc..3672101023b 100644 --- a/drivers/edac/i7core_edac.c +++ b/drivers/edac/i7core_edac.c @@ -90,7 +90,7 @@ MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices"); #define MC_MAX_DOD 0x64 /* - * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet: + * OFFSETS for Device 3 Function 4, as indicated on Xeon 5500 datasheet: * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf */ @@ -101,7 +101,7 @@ MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices"); #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff) #define DIMM0_COR_ERR(r) ((r) & 0x7fff) -/* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */ +/* OFFSETS for Device 3 Function 2, as indicated on Xeon 5500 datasheet */ #define MC_SSRCONTROL 0x48 #define SSR_MODE_DISABLE 0x00 #define SSR_MODE_ENABLE 0x01 @@ -401,7 +401,7 @@ static DEFINE_PCI_DEVICE_TABLE(i7core_pci_tbl) = { }; /**************************************************************************** - Anciliary status routines + Ancillary status routines ****************************************************************************/ /* MC_CONTROL bits */ @@ -1330,7 +1330,7 @@ static int i7core_get_onedevice(struct pci_dev **prev, dev_descr->dev_id, *prev); /* - * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs + * On Xeon 55xx, the Intel QuickPath Arch Generic Non-core regs * is at addr 8086:2c40, instead of 8086:2c41. So, we need * to probe for the alternate address in case of failure */ @@ -1889,12 +1889,6 @@ static int i7core_mce_check_error(struct notifier_block *nb, unsigned long val, if (mce->bank != 8) return NOTIFY_DONE; -#ifdef CONFIG_SMP - /* Only handle if it is the right mc controller */ - if (mce->socketid != pvt->i7core_dev->socket) - return NOTIFY_DONE; -#endif - smp_rmb(); if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) { smp_wmb(); @@ -2089,7 +2083,7 @@ static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 new_bw) /* * get_sdram_scrub_rate This routine convert current scrub rate value - * into byte/sec bandwidth accourding to + * into byte/sec bandwidth according to * SCRUBINTERVAL formula found in datasheet. */ static int get_sdram_scrub_rate(struct mem_ctl_info *mci) @@ -2189,8 +2183,6 @@ static void i7core_unregister_mci(struct i7core_dev *i7core_dev) if (pvt->enable_scrub) disable_sdram_scrub_setting(mci); - mce_unregister_decode_chain(&i7_mce_dec); - /* Disable EDAC polling */ i7core_pci_ctl_release(pvt); @@ -2296,8 +2288,6 @@ static int i7core_register_mci(struct i7core_dev *i7core_dev) /* DCLK for scrub rate setting */ pvt->dclk_freq = get_dclk_freq(); - mce_register_decode_chain(&i7_mce_dec); - return 0; fail0: @@ -2441,8 +2431,10 @@ static int __init i7core_init(void) pci_rc = pci_register_driver(&i7core_driver); - if (pci_rc >= 0) + if (pci_rc >= 0) { + mce_register_decode_chain(&i7_mce_dec); return 0; + } i7core_printk(KERN_ERR, "Failed to register device with error %d.\n", pci_rc); @@ -2458,6 +2450,7 @@ static void __exit i7core_exit(void) { edac_dbg(2, "\n"); pci_unregister_driver(&i7core_driver); + mce_unregister_decode_chain(&i7_mce_dec); } module_init(i7core_init); diff --git a/drivers/edac/mce_amd.h b/drivers/edac/mce_amd.h index c6074c5cd1e..8c87a5e8705 100644 --- a/drivers/edac/mce_amd.h +++ b/drivers/edac/mce_amd.h @@ -5,8 +5,6 @@ #include <asm/mce.h> -#define BIT_64(n) (U64_C(1) << (n)) - #define EC(x) ((x) & 0xffff) #define XEC(x, mask) (((x) >> 16) & mask) diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c index 117cf00bd74..a1e791ec25d 100644 --- a/drivers/edac/mpc85xx_edac.c +++ b/drivers/edac/mpc85xx_edac.c @@ -992,7 +992,8 @@ static int __devinit mpc85xx_mc_err_probe(struct platform_device *op) layers[1].type = EDAC_MC_LAYER_CHANNEL; layers[1].size = 1; layers[1].is_virt_csrow = false; - mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), sizeof(*pdata)); + mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, + sizeof(*pdata)); if (!mci) { devres_release_group(&op->dev, mpc85xx_mc_err_probe); return -ENOMEM; diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c index 6f8861369e7..f3b1f9fafa4 100644 --- a/drivers/edac/sb_edac.c +++ b/drivers/edac/sb_edac.c @@ -58,7 +58,7 @@ static int probed; /* * FIXME: For now, let's order by device function, as it makes - * easier for driver's development proccess. This table should be + * easier for driver's development process. This table should be * moved to pci_id.h when submitted upstream */ #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */ @@ -373,7 +373,7 @@ static DEFINE_PCI_DEVICE_TABLE(sbridge_pci_tbl) = { /**************************************************************************** - Anciliary status routines + Ancillary status routines ****************************************************************************/ static inline int numrank(u32 mtr) @@ -555,7 +555,7 @@ static int get_dimm_config(struct mem_ctl_info *mci) pvt->is_close_pg = false; } - pci_read_config_dword(pvt->pci_ta, RANK_CFG_A, ®); + pci_read_config_dword(pvt->pci_ddrio, RANK_CFG_A, ®); if (IS_RDIMM_ENABLED(reg)) { /* FIXME: Can also be LRDIMM */ edac_dbg(0, "Memory is registered\n"); @@ -1368,7 +1368,7 @@ static void sbridge_mce_output_error(struct mem_ctl_info *mci, } /* - * According with Table 15-9 of the Intel Archictecture spec vol 3A, + * According with Table 15-9 of the Intel Architecture spec vol 3A, * memory errors should fit in this mask: * 000f 0000 1mmm cccc (binary) * where: @@ -1599,8 +1599,6 @@ static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev) edac_dbg(0, "MC: mci = %p, dev = %p\n", mci, &sbridge_dev->pdev[0]->dev); - mce_unregister_decode_chain(&sbridge_mce_dec); - /* Remove MC sysfs nodes */ edac_mc_del_mc(mci->pdev); @@ -1676,7 +1674,6 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev) goto fail0; } - mce_register_decode_chain(&sbridge_mce_dec); return 0; fail0: @@ -1806,8 +1803,10 @@ static int __init sbridge_init(void) pci_rc = pci_register_driver(&sbridge_driver); - if (pci_rc >= 0) + if (pci_rc >= 0) { + mce_register_decode_chain(&sbridge_mce_dec); return 0; + } sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n", pci_rc); @@ -1823,6 +1822,7 @@ static void __exit sbridge_exit(void) { edac_dbg(2, "\n"); pci_unregister_driver(&sbridge_driver); + mce_unregister_decode_chain(&sbridge_mce_dec); } module_init(sbridge_init); |