diff options
Diffstat (limited to 'drivers/edac')
| -rw-r--r-- | drivers/edac/amd64_edac.c | 8 | ||||
| -rw-r--r-- | drivers/edac/edac_mce_amd.c | 57 | ||||
| -rw-r--r-- | drivers/edac/edac_mce_amd.h | 4 |
3 files changed, 34 insertions, 35 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 2080b1e2e8a..c81ca2cf8dc 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -2283,10 +2283,11 @@ static void amd64_handle_ue(struct mem_ctl_info *mci, } static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci, - struct err_regs *info, int ecc_type) + struct err_regs *info) { u32 ec = ERROR_CODE(info->nbsl); u32 xec = EXT_ERROR_CODE(info->nbsl); + int ecc_type = info->nbsh & (0x3 << 13); pr_emerg(" Transaction type: %s(%s), %s, Cache Level: %s, %s\n", RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec), PP_MSG(ec)); @@ -2316,12 +2317,11 @@ static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci, edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR "Error Overflow"); } -void amd64_decode_bus_error(int node_id, struct err_regs *regs, - int ecc_type) +void amd64_decode_bus_error(int node_id, struct err_regs *regs) { struct mem_ctl_info *mci = mci_lookup[node_id]; - __amd64_decode_bus_error(mci, regs, ecc_type); + __amd64_decode_bus_error(mci, regs); /* * Check the UE bit of the NB status high register, if set generate some diff --git a/drivers/edac/edac_mce_amd.c b/drivers/edac/edac_mce_amd.c index 444c2cc4472..0ba92d65db4 100644 --- a/drivers/edac/edac_mce_amd.c +++ b/drivers/edac/edac_mce_amd.c @@ -2,7 +2,7 @@ #include "edac_mce_amd.h" static bool report_gart_errors; -static void (*nb_bus_decoder)(int node_id, struct err_regs *regs, int ecc_type); +static void (*nb_bus_decoder)(int node_id, struct err_regs *regs); void amd_report_gart_errors(bool v) { @@ -10,13 +10,13 @@ void amd_report_gart_errors(bool v) } EXPORT_SYMBOL_GPL(amd_report_gart_errors); -void amd_register_ecc_decoder(void (*f)(int, struct err_regs *, int)) +void amd_register_ecc_decoder(void (*f)(int, struct err_regs *)) { nb_bus_decoder = f; } EXPORT_SYMBOL_GPL(amd_register_ecc_decoder); -void amd_unregister_ecc_decoder(void (*f)(int, struct err_regs *, int)) +void amd_unregister_ecc_decoder(void (*f)(int, struct err_regs *)) { if (nb_bus_decoder) { WARN_ON(nb_bus_decoder != f); @@ -130,7 +130,6 @@ EXPORT_SYMBOL_GPL(ext_msgs); void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors) { - int ecc; u32 ec = ERROR_CODE(regs->nbsl); u32 xec = EXT_ERROR_CODE(regs->nbsl); @@ -151,21 +150,6 @@ void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors) pr_cont(", core: %d\n", ilog2((regs->nbsh & 0xf))); } - pr_emerg(" Error: %sorrected", - ((regs->nbsh & K8_NBSH_UC_ERR) ? "Unc" : "C")); - pr_cont(", Report Error: %s", - ((regs->nbsh & K8_NBSH_ERR_EN) ? "yes" : "no")); - pr_cont(", MiscV: %svalid, CPU context corrupt: %s", - ((regs->nbsh & K8_NBSH_MISCV) ? "" : "In"), - ((regs->nbsh & K8_NBSH_PCC) ? "yes" : "no")); - - /* do the two bits[14:13] together */ - ecc = regs->nbsh & (0x3 << 13); - if (ecc) - pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U")); - - pr_cont("\n"); - if (TLB_ERROR(ec)) { /* * GART errors are intended to help graphics driver developers @@ -191,7 +175,7 @@ void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors) } else if (BUS_ERROR(ec)) { pr_emerg(" Bus (Link/DRAM) error\n"); if (nb_bus_decoder) - nb_bus_decoder(node_id, regs, ecc); + nb_bus_decoder(node_id, regs); } else { /* shouldn't reach here! */ pr_warning("%s: unknown MCE error 0x%x\n", __func__, ec); @@ -204,16 +188,31 @@ EXPORT_SYMBOL_GPL(amd_decode_nb_mce); void decode_mce(struct mce *m) { struct err_regs regs; - int node; + int node, ecc; - if (m->bank != 4) - return; + pr_emerg("MC%d_STATUS:\n", m->bank); - regs.nbsl = (u32) m->status; - regs.nbsh = (u32)(m->status >> 32); - regs.nbeal = (u32) m->addr; - regs.nbeah = (u32)(m->addr >> 32); - node = topology_cpu_node_id(m->extcpu); + pr_emerg(" Error: %sorrected, Report: %s, MiscV: %svalid, " + "CPU context corrupt: %s", + ((m->status & MCI_STATUS_UC) ? "Unc" : "C"), + ((m->status & MCI_STATUS_EN) ? "yes" : "no"), + ((m->status & MCI_STATUS_MISCV) ? "" : "in"), + ((m->status & MCI_STATUS_PCC) ? "yes" : "no")); - amd_decode_nb_mce(node, ®s, 1); + /* do the two bits[14:13] together */ + ecc = m->status & (3ULL << 45); + if (ecc) + pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U")); + + pr_cont("\n"); + + if (m->bank == 4) { + regs.nbsl = (u32) m->status; + regs.nbsh = (u32)(m->status >> 32); + regs.nbeal = (u32) m->addr; + regs.nbeah = (u32)(m->addr >> 32); + node = per_cpu(cpu_llc_id, m->extcpu); + + amd_decode_nb_mce(node, ®s, 1); + } } diff --git a/drivers/edac/edac_mce_amd.h b/drivers/edac/edac_mce_amd.h index 9114dc62782..df23ee065f7 100644 --- a/drivers/edac/edac_mce_amd.h +++ b/drivers/edac/edac_mce_amd.h @@ -62,8 +62,8 @@ struct err_regs { void amd_report_gart_errors(bool); -void amd_register_ecc_decoder(void (*f)(int, struct err_regs *, int)); -void amd_unregister_ecc_decoder(void (*f)(int, struct err_regs *, int)); +void amd_register_ecc_decoder(void (*f)(int, struct err_regs *)); +void amd_unregister_ecc_decoder(void (*f)(int, struct err_regs *)); void amd_decode_nb_mce(int, struct err_regs *, int); #endif /* _EDAC_MCE_AMD_H */ |