1 files changed, 13 insertions, 30 deletions

diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 8f3a12f614e..04885d2fb15 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -285,53 +285,36 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
 			uint32_t flags, uint64_t phys)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_gpuobj **pgt;
-	unsigned psz, pfl, pages;
-
-	if (virt >= dev_priv->vm_gart_base &&
-	    (virt + size) < (dev_priv->vm_gart_base + dev_priv->vm_gart_size)) {
-		psz = 12;
-		pgt = &dev_priv->gart_info.sg_ctxdma;
-		pfl = 0x21;
-		virt -= dev_priv->vm_gart_base;
-	} else
-	if (virt >= dev_priv->vm_vram_base &&
-	    (virt + size) < (dev_priv->vm_vram_base + dev_priv->vm_vram_size)) {
-		psz = 16;
-		pgt = dev_priv->vm_vram_pt;
-		pfl = 0x01;
-		virt -= dev_priv->vm_vram_base;
-	} else {
-		NV_ERROR(dev, "Invalid address: 0x%16llx-0x%16llx\n",
-			 virt, virt + size - 1);
-		return -EINVAL;
-	}
+	unsigned pages;
 
-	pages = size >> psz;
+	virt -= dev_priv->vm_vram_base;
+	pages = size >> 16;
 
 	dev_priv->engine.instmem.prepare_access(dev, true);
 	if (flags & 0x80000000) {
 		while (pages--) {
-			struct nouveau_gpuobj *pt = pgt[virt >> 29];
-			unsigned pte = ((virt & 0x1fffffffULL) >> psz) << 1;
+			struct nouveau_gpuobj *pt =
+				dev_priv->vm_vram_pt[virt >> 29];
+			unsigned pte = ((virt & 0x1fffffffULL) >> 16) << 1;
 
 			nv_wo32(dev, pt, pte++, 0x00000000);
 			nv_wo32(dev, pt, pte++, 0x00000000);
 
-			virt += (1 << psz);
+			virt += (1 << 16);
 		}
 	} else {
 		while (pages--) {
-			struct nouveau_gpuobj *pt = pgt[virt >> 29];
-			unsigned pte = ((virt & 0x1fffffffULL) >> psz) << 1;
+			struct nouveau_gpuobj *pt =
+				dev_priv->vm_vram_pt[virt >> 29];
+			unsigned pte = ((virt & 0x1fffffffULL) >> 16) << 1;
 			unsigned offset_h = upper_32_bits(phys) & 0xff;
 			unsigned offset_l = lower_32_bits(phys);
 
-			nv_wo32(dev, pt, pte++, offset_l | pfl);
+			nv_wo32(dev, pt, pte++, offset_l | 1);
 			nv_wo32(dev, pt, pte++, offset_h | flags);
 
-			phys += (1 << psz);
-			virt += (1 << psz);
+			phys += (1 << 16);
+			virt += (1 << 16);
 		}
 	}
 	dev_priv->engine.instmem.finish_access(dev);