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path: root/drivers/net/wireless/zd1211rw/zd_chip.c
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Diffstat (limited to 'drivers/net/wireless/zd1211rw/zd_chip.c')
-rw-r--r--drivers/net/wireless/zd1211rw/zd_chip.c262
1 files changed, 131 insertions, 131 deletions
diff --git a/drivers/net/wireless/zd1211rw/zd_chip.c b/drivers/net/wireless/zd1211rw/zd_chip.c
index a73a305d3cb..ff306d763e3 100644
--- a/drivers/net/wireless/zd1211rw/zd_chip.c
+++ b/drivers/net/wireless/zd1211rw/zd_chip.c
@@ -557,7 +557,7 @@ int zd_chip_unlock_phy_regs(struct zd_chip *chip)
return r;
}
-/* CR157 can be optionally patched by the EEPROM for original ZD1211 */
+/* ZD_CR157 can be optionally patched by the EEPROM for original ZD1211 */
static int patch_cr157(struct zd_chip *chip)
{
int r;
@@ -571,7 +571,7 @@ static int patch_cr157(struct zd_chip *chip)
return r;
dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
- return zd_iowrite32_locked(chip, value >> 8, CR157);
+ return zd_iowrite32_locked(chip, value >> 8, ZD_CR157);
}
/*
@@ -593,8 +593,8 @@ static int patch_6m_band_edge(struct zd_chip *chip, u8 channel)
int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel)
{
struct zd_ioreq16 ioreqs[] = {
- { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
- { CR47, 0x1e },
+ { ZD_CR128, 0x14 }, { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 },
+ { ZD_CR47, 0x1e },
};
/* FIXME: Channel 11 is not the edge for all regulatory domains. */
@@ -608,69 +608,69 @@ int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel)
static int zd1211_hw_reset_phy(struct zd_chip *chip)
{
static const struct zd_ioreq16 ioreqs[] = {
- { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
- { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
- { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
- { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
- { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
- { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
- { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
- { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
- { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
- { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
- { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
- { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
- { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
- { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
- { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
- { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
- { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
- { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
- { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
- { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
- { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
- { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
- { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
- { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
- { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
- { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
- { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
- { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
- { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
- { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
- { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
- { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
- { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
+ { ZD_CR0, 0x0a }, { ZD_CR1, 0x06 }, { ZD_CR2, 0x26 },
+ { ZD_CR3, 0x38 }, { ZD_CR4, 0x80 }, { ZD_CR9, 0xa0 },
+ { ZD_CR10, 0x81 }, { ZD_CR11, 0x00 }, { ZD_CR12, 0x7f },
+ { ZD_CR13, 0x8c }, { ZD_CR14, 0x80 }, { ZD_CR15, 0x3d },
+ { ZD_CR16, 0x20 }, { ZD_CR17, 0x1e }, { ZD_CR18, 0x0a },
+ { ZD_CR19, 0x48 }, { ZD_CR20, 0x0c }, { ZD_CR21, 0x0c },
+ { ZD_CR22, 0x23 }, { ZD_CR23, 0x90 }, { ZD_CR24, 0x14 },
+ { ZD_CR25, 0x40 }, { ZD_CR26, 0x10 }, { ZD_CR27, 0x19 },
+ { ZD_CR28, 0x7f }, { ZD_CR29, 0x80 }, { ZD_CR30, 0x4b },
+ { ZD_CR31, 0x60 }, { ZD_CR32, 0x43 }, { ZD_CR33, 0x08 },
+ { ZD_CR34, 0x06 }, { ZD_CR35, 0x0a }, { ZD_CR36, 0x00 },
+ { ZD_CR37, 0x00 }, { ZD_CR38, 0x38 }, { ZD_CR39, 0x0c },
+ { ZD_CR40, 0x84 }, { ZD_CR41, 0x2a }, { ZD_CR42, 0x80 },
+ { ZD_CR43, 0x10 }, { ZD_CR44, 0x12 }, { ZD_CR46, 0xff },
+ { ZD_CR47, 0x1E }, { ZD_CR48, 0x26 }, { ZD_CR49, 0x5b },
+ { ZD_CR64, 0xd0 }, { ZD_CR65, 0x04 }, { ZD_CR66, 0x58 },
+ { ZD_CR67, 0xc9 }, { ZD_CR68, 0x88 }, { ZD_CR69, 0x41 },
+ { ZD_CR70, 0x23 }, { ZD_CR71, 0x10 }, { ZD_CR72, 0xff },
+ { ZD_CR73, 0x32 }, { ZD_CR74, 0x30 }, { ZD_CR75, 0x65 },
+ { ZD_CR76, 0x41 }, { ZD_CR77, 0x1b }, { ZD_CR78, 0x30 },
+ { ZD_CR79, 0x68 }, { ZD_CR80, 0x64 }, { ZD_CR81, 0x64 },
+ { ZD_CR82, 0x00 }, { ZD_CR83, 0x00 }, { ZD_CR84, 0x00 },
+ { ZD_CR85, 0x02 }, { ZD_CR86, 0x00 }, { ZD_CR87, 0x00 },
+ { ZD_CR88, 0xff }, { ZD_CR89, 0xfc }, { ZD_CR90, 0x00 },
+ { ZD_CR91, 0x00 }, { ZD_CR92, 0x00 }, { ZD_CR93, 0x08 },
+ { ZD_CR94, 0x00 }, { ZD_CR95, 0x00 }, { ZD_CR96, 0xff },
+ { ZD_CR97, 0xe7 }, { ZD_CR98, 0x00 }, { ZD_CR99, 0x00 },
+ { ZD_CR100, 0x00 }, { ZD_CR101, 0xae }, { ZD_CR102, 0x02 },
+ { ZD_CR103, 0x00 }, { ZD_CR104, 0x03 }, { ZD_CR105, 0x65 },
+ { ZD_CR106, 0x04 }, { ZD_CR107, 0x00 }, { ZD_CR108, 0x0a },
+ { ZD_CR109, 0xaa }, { ZD_CR110, 0xaa }, { ZD_CR111, 0x25 },
+ { ZD_CR112, 0x25 }, { ZD_CR113, 0x00 }, { ZD_CR119, 0x1e },
+ { ZD_CR125, 0x90 }, { ZD_CR126, 0x00 }, { ZD_CR127, 0x00 },
{ },
- { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
- { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
- { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
- { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
- { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
- { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
- { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
- { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
- { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
- { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
- { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
- { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
- { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
- { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
- { CR125, 0xaa }, { CR127, 0x03 }, { CR128, 0x14 },
- { CR129, 0x12 }, { CR130, 0x10 }, { CR131, 0x0C },
- { CR136, 0xdf }, { CR137, 0x40 }, { CR138, 0xa0 },
- { CR139, 0xb0 }, { CR140, 0x99 }, { CR141, 0x82 },
- { CR142, 0x54 }, { CR143, 0x1c }, { CR144, 0x6c },
- { CR147, 0x07 }, { CR148, 0x4c }, { CR149, 0x50 },
- { CR150, 0x0e }, { CR151, 0x18 }, { CR160, 0xfe },
- { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
- { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
- { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
- { CR170, 0xba }, { CR171, 0xba },
- /* Note: CR204 must lead the CR203 */
- { CR204, 0x7d },
+ { ZD_CR5, 0x00 }, { ZD_CR6, 0x00 }, { ZD_CR7, 0x00 },
+ { ZD_CR8, 0x00 }, { ZD_CR9, 0x20 }, { ZD_CR12, 0xf0 },
+ { ZD_CR20, 0x0e }, { ZD_CR21, 0x0e }, { ZD_CR27, 0x10 },
+ { ZD_CR44, 0x33 }, { ZD_CR47, 0x1E }, { ZD_CR83, 0x24 },
+ { ZD_CR84, 0x04 }, { ZD_CR85, 0x00 }, { ZD_CR86, 0x0C },
+ { ZD_CR87, 0x12 }, { ZD_CR88, 0x0C }, { ZD_CR89, 0x00 },
+ { ZD_CR90, 0x10 }, { ZD_CR91, 0x08 }, { ZD_CR93, 0x00 },
+ { ZD_CR94, 0x01 }, { ZD_CR95, 0x00 }, { ZD_CR96, 0x50 },
+ { ZD_CR97, 0x37 }, { ZD_CR98, 0x35 }, { ZD_CR101, 0x13 },
+ { ZD_CR102, 0x27 }, { ZD_CR103, 0x27 }, { ZD_CR104, 0x18 },
+ { ZD_CR105, 0x12 }, { ZD_CR109, 0x27 }, { ZD_CR110, 0x27 },
+ { ZD_CR111, 0x27 }, { ZD_CR112, 0x27 }, { ZD_CR113, 0x27 },
+ { ZD_CR114, 0x27 }, { ZD_CR115, 0x26 }, { ZD_CR116, 0x24 },
+ { ZD_CR117, 0xfc }, { ZD_CR118, 0xfa }, { ZD_CR120, 0x4f },
+ { ZD_CR125, 0xaa }, { ZD_CR127, 0x03 }, { ZD_CR128, 0x14 },
+ { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 }, { ZD_CR131, 0x0C },
+ { ZD_CR136, 0xdf }, { ZD_CR137, 0x40 }, { ZD_CR138, 0xa0 },
+ { ZD_CR139, 0xb0 }, { ZD_CR140, 0x99 }, { ZD_CR141, 0x82 },
+ { ZD_CR142, 0x54 }, { ZD_CR143, 0x1c }, { ZD_CR144, 0x6c },
+ { ZD_CR147, 0x07 }, { ZD_CR148, 0x4c }, { ZD_CR149, 0x50 },
+ { ZD_CR150, 0x0e }, { ZD_CR151, 0x18 }, { ZD_CR160, 0xfe },
+ { ZD_CR161, 0xee }, { ZD_CR162, 0xaa }, { ZD_CR163, 0xfa },
+ { ZD_CR164, 0xfa }, { ZD_CR165, 0xea }, { ZD_CR166, 0xbe },
+ { ZD_CR167, 0xbe }, { ZD_CR168, 0x6a }, { ZD_CR169, 0xba },
+ { ZD_CR170, 0xba }, { ZD_CR171, 0xba },
+ /* Note: ZD_CR204 must lead the ZD_CR203 */
+ { ZD_CR204, 0x7d },
{ },
- { CR203, 0x30 },
+ { ZD_CR203, 0x30 },
};
int r, t;
@@ -697,62 +697,62 @@ out:
static int zd1211b_hw_reset_phy(struct zd_chip *chip)
{
static const struct zd_ioreq16 ioreqs[] = {
- { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
- { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
- { CR10, 0x81 },
- /* power control { { CR11, 1 << 6 }, */
- { CR11, 0x00 },
- { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
- { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
- { CR18, 0x0a }, { CR19, 0x48 },
- { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
- { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
- { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
- { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
- { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
- { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
- { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
- { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
- { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
- { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
- { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
- { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
- { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
- { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
- { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
- { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
- { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
- { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
- { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
- { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
- { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
- { CR94, 0x01 },
- { CR95, 0x20 }, /* ZD1211B */
- { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
- { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
- { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
- { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
- { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
- { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
- { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
- { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
- { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
- { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
- { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
- { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
- { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
- { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
- { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
- { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
- { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
- { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
- { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
- { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
- { CR170, 0xba }, { CR171, 0xba },
- /* Note: CR204 must lead the CR203 */
- { CR204, 0x7d },
+ { ZD_CR0, 0x14 }, { ZD_CR1, 0x06 }, { ZD_CR2, 0x26 },
+ { ZD_CR3, 0x38 }, { ZD_CR4, 0x80 }, { ZD_CR9, 0xe0 },
+ { ZD_CR10, 0x81 },
+ /* power control { { ZD_CR11, 1 << 6 }, */
+ { ZD_CR11, 0x00 },
+ { ZD_CR12, 0xf0 }, { ZD_CR13, 0x8c }, { ZD_CR14, 0x80 },
+ { ZD_CR15, 0x3d }, { ZD_CR16, 0x20 }, { ZD_CR17, 0x1e },
+ { ZD_CR18, 0x0a }, { ZD_CR19, 0x48 },
+ { ZD_CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
+ { ZD_CR21, 0x0e }, { ZD_CR22, 0x23 }, { ZD_CR23, 0x90 },
+ { ZD_CR24, 0x14 }, { ZD_CR25, 0x40 }, { ZD_CR26, 0x10 },
+ { ZD_CR27, 0x10 }, { ZD_CR28, 0x7f }, { ZD_CR29, 0x80 },
+ { ZD_CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
+ { ZD_CR31, 0x60 }, { ZD_CR32, 0x43 }, { ZD_CR33, 0x08 },
+ { ZD_CR34, 0x06 }, { ZD_CR35, 0x0a }, { ZD_CR36, 0x00 },
+ { ZD_CR37, 0x00 }, { ZD_CR38, 0x38 }, { ZD_CR39, 0x0c },
+ { ZD_CR40, 0x84 }, { ZD_CR41, 0x2a }, { ZD_CR42, 0x80 },
+ { ZD_CR43, 0x10 }, { ZD_CR44, 0x33 }, { ZD_CR46, 0xff },
+ { ZD_CR47, 0x1E }, { ZD_CR48, 0x26 }, { ZD_CR49, 0x5b },
+ { ZD_CR64, 0xd0 }, { ZD_CR65, 0x04 }, { ZD_CR66, 0x58 },
+ { ZD_CR67, 0xc9 }, { ZD_CR68, 0x88 }, { ZD_CR69, 0x41 },
+ { ZD_CR70, 0x23 }, { ZD_CR71, 0x10 }, { ZD_CR72, 0xff },
+ { ZD_CR73, 0x32 }, { ZD_CR74, 0x30 }, { ZD_CR75, 0x65 },
+ { ZD_CR76, 0x41 }, { ZD_CR77, 0x1b }, { ZD_CR78, 0x30 },
+ { ZD_CR79, 0xf0 }, { ZD_CR80, 0x64 }, { ZD_CR81, 0x64 },
+ { ZD_CR82, 0x00 }, { ZD_CR83, 0x24 }, { ZD_CR84, 0x04 },
+ { ZD_CR85, 0x00 }, { ZD_CR86, 0x0c }, { ZD_CR87, 0x12 },
+ { ZD_CR88, 0x0c }, { ZD_CR89, 0x00 }, { ZD_CR90, 0x58 },
+ { ZD_CR91, 0x04 }, { ZD_CR92, 0x00 }, { ZD_CR93, 0x00 },
+ { ZD_CR94, 0x01 },
+ { ZD_CR95, 0x20 }, /* ZD1211B */
+ { ZD_CR96, 0x50 }, { ZD_CR97, 0x37 }, { ZD_CR98, 0x35 },
+ { ZD_CR99, 0x00 }, { ZD_CR100, 0x01 }, { ZD_CR101, 0x13 },
+ { ZD_CR102, 0x27 }, { ZD_CR103, 0x27 }, { ZD_CR104, 0x18 },
+ { ZD_CR105, 0x12 }, { ZD_CR106, 0x04 }, { ZD_CR107, 0x00 },
+ { ZD_CR108, 0x0a }, { ZD_CR109, 0x27 }, { ZD_CR110, 0x27 },
+ { ZD_CR111, 0x27 }, { ZD_CR112, 0x27 }, { ZD_CR113, 0x27 },
+ { ZD_CR114, 0x27 }, { ZD_CR115, 0x26 }, { ZD_CR116, 0x24 },
+ { ZD_CR117, 0xfc }, { ZD_CR118, 0xfa }, { ZD_CR119, 0x1e },
+ { ZD_CR125, 0x90 }, { ZD_CR126, 0x00 }, { ZD_CR127, 0x00 },
+ { ZD_CR128, 0x14 }, { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 },
+ { ZD_CR131, 0x0c }, { ZD_CR136, 0xdf }, { ZD_CR137, 0xa0 },
+ { ZD_CR138, 0xa8 }, { ZD_CR139, 0xb4 }, { ZD_CR140, 0x98 },
+ { ZD_CR141, 0x82 }, { ZD_CR142, 0x53 }, { ZD_CR143, 0x1c },
+ { ZD_CR144, 0x6c }, { ZD_CR147, 0x07 }, { ZD_CR148, 0x40 },
+ { ZD_CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
+ { ZD_CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
+ { ZD_CR151, 0x18 }, { ZD_CR159, 0x70 }, { ZD_CR160, 0xfe },
+ { ZD_CR161, 0xee }, { ZD_CR162, 0xaa }, { ZD_CR163, 0xfa },
+ { ZD_CR164, 0xfa }, { ZD_CR165, 0xea }, { ZD_CR166, 0xbe },
+ { ZD_CR167, 0xbe }, { ZD_CR168, 0x6a }, { ZD_CR169, 0xba },
+ { ZD_CR170, 0xba }, { ZD_CR171, 0xba },
+ /* Note: ZD_CR204 must lead the ZD_CR203 */
+ { ZD_CR204, 0x7d },
{},
- { CR203, 0x30 },
+ { ZD_CR203, 0x30 },
};
int r, t;
@@ -1200,24 +1200,24 @@ out:
static int update_pwr_int(struct zd_chip *chip, u8 channel)
{
u8 value = chip->pwr_int_values[channel - 1];
- return zd_iowrite16_locked(chip, value, CR31);
+ return zd_iowrite16_locked(chip, value, ZD_CR31);
}
static int update_pwr_cal(struct zd_chip *chip, u8 channel)
{
u8 value = chip->pwr_cal_values[channel-1];
- return zd_iowrite16_locked(chip, value, CR68);
+ return zd_iowrite16_locked(chip, value, ZD_CR68);
}
static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
{
struct zd_ioreq16 ioreqs[3];
- ioreqs[0].addr = CR67;
+ ioreqs[0].addr = ZD_CR67;
ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
- ioreqs[1].addr = CR66;
+ ioreqs[1].addr = ZD_CR66;
ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
- ioreqs[2].addr = CR65;
+ ioreqs[2].addr = ZD_CR65;
ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
@@ -1236,9 +1236,9 @@ static int update_channel_integration_and_calibration(struct zd_chip *chip,
return r;
if (zd_chip_is_zd1211b(chip)) {
static const struct zd_ioreq16 ioreqs[] = {
- { CR69, 0x28 },
+ { ZD_CR69, 0x28 },
{},
- { CR69, 0x2a },
+ { ZD_CR69, 0x2a },
};
r = update_ofdm_cal(chip, channel);
@@ -1269,7 +1269,7 @@ static int patch_cck_gain(struct zd_chip *chip)
if (r)
return r;
dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
- return zd_iowrite16_locked(chip, value & 0xff, CR47);
+ return zd_iowrite16_locked(chip, value & 0xff, ZD_CR47);
}
int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
@@ -1505,9 +1505,9 @@ int zd_rfwritev_locked(struct zd_chip *chip,
int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
{
const struct zd_ioreq16 ioreqs[] = {
- { CR244, (value >> 16) & 0xff },
- { CR243, (value >> 8) & 0xff },
- { CR242, value & 0xff },
+ { ZD_CR244, (value >> 16) & 0xff },
+ { ZD_CR243, (value >> 8) & 0xff },
+ { ZD_CR242, value & 0xff },
};
ZD_ASSERT(mutex_is_locked(&chip->mutex));
return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2024-12-05 00:39:15 +0000