diff options
Diffstat (limited to 'drivers/pinctrl')
51 files changed, 23732 insertions, 4233 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 8f669243814..5a8ad513931 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -58,6 +58,18 @@ config PINCTRL_AT91 help Say Y here to enable the at91 pinctrl driver +config PINCTRL_BAYTRAIL + bool "Intel Baytrail GPIO pin control" + depends on GPIOLIB && ACPI && X86 + select IRQ_DOMAIN + help + driver for memory mapped GPIO functionality on Intel Baytrail + platforms. Supports 3 banks with 102, 28 and 44 gpios. + Most pins are usually muxed to some other functionality by firmware, + so only a small amount is available for gpio use. + + Requires ACPI device enumeration code to set up a platform device. + config PINCTRL_BCM2835 bool select PINMUX @@ -108,6 +120,14 @@ config PINCTRL_IMX6SL help Say Y here to enable the imx6sl pinctrl driver +config PINCTRL_VF610 + bool "Freescale Vybrid VF610 pinctrl driver" + depends on OF + depends on SOC_VF610 + select PINCTRL_IMX + help + Say Y here to enable the Freescale Vybrid VF610 pinctrl driver + config PINCTRL_LANTIQ bool depends on LANTIQ @@ -150,6 +170,12 @@ config PINCTRL_DB8540 bool "DB8540 pin controller driver" depends on PINCTRL_NOMADIK && ARCH_U8500 +config PINCTRL_ROCKCHIP + bool + select PINMUX + select GENERIC_PINCONF + select GENERIC_IRQ_CHIP + config PINCTRL_SINGLE tristate "One-register-per-pin type device tree based pinctrl driver" depends on OF @@ -169,6 +195,12 @@ config PINCTRL_SUNXI select PINMUX select GENERIC_PINCONF +config PINCTRL_ST + bool + depends on OF + select PINMUX + select PINCONF + config PINCTRL_TEGRA bool select PINMUX @@ -186,6 +218,18 @@ config PINCTRL_TEGRA114 bool select PINCTRL_TEGRA +config PINCTRL_TZ1090 + bool "Toumaz Xenif TZ1090 pin control driver" + depends on SOC_TZ1090 + select PINMUX + select GENERIC_PINCONF + +config PINCTRL_TZ1090_PDC + bool "Toumaz Xenif TZ1090 PDC pin control driver" + depends on SOC_TZ1090 + select PINMUX + select PINCONF + config PINCTRL_U300 bool "U300 pin controller driver" depends on ARCH_U300 @@ -207,15 +251,21 @@ config PINCTRL_SAMSUNG select PINCONF config PINCTRL_EXYNOS - bool "Pinctrl driver data for Samsung EXYNOS SoCs" - depends on OF && GPIOLIB + bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440" + depends on OF && GPIOLIB && ARCH_EXYNOS select PINCTRL_SAMSUNG config PINCTRL_EXYNOS5440 bool "Samsung EXYNOS5440 SoC pinctrl driver" + depends on SOC_EXYNOS5440 select PINMUX select PINCONF +config PINCTRL_S3C24XX + bool "Samsung S3C24XX SoC pinctrl driver" + depends on ARCH_S3C24XX + select PINCTRL_SAMSUNG + config PINCTRL_S3C64XX bool "Samsung S3C64XX SoC pinctrl driver" depends on ARCH_S3C64XX diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 9bdaeb8785c..d64563bf6fb 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -16,12 +16,14 @@ obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o +obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o +obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o @@ -30,21 +32,27 @@ obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o +obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o -obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o +obj-$(CONFIG_PINCTRL_SIRF) += sirf/ obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sunxi.o obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o +obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o +obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o +obj-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o +obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o +obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_PLAT_ORION) += mvebu/ obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/ diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 5327f35d9b5..5b272bfd261 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -41,13 +41,13 @@ static bool pinctrl_dummy_state; /* Mutex taken to protect pinctrl_list */ -DEFINE_MUTEX(pinctrl_list_mutex); +static DEFINE_MUTEX(pinctrl_list_mutex); /* Mutex taken to protect pinctrl_maps */ DEFINE_MUTEX(pinctrl_maps_mutex); /* Mutex taken to protect pinctrldev_list */ -DEFINE_MUTEX(pinctrldev_list_mutex); +static DEFINE_MUTEX(pinctrldev_list_mutex); /* Global list of pin control devices (struct pinctrl_dev) */ static LIST_HEAD(pinctrldev_list); @@ -101,20 +101,23 @@ EXPORT_SYMBOL_GPL(pinctrl_dev_get_drvdata); struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *devname) { struct pinctrl_dev *pctldev = NULL; - bool found = false; if (!devname) return NULL; + mutex_lock(&pinctrldev_list_mutex); + list_for_each_entry(pctldev, &pinctrldev_list, node) { if (!strcmp(dev_name(pctldev->dev), devname)) { /* Matched on device name */ - found = true; - break; + mutex_unlock(&pinctrldev_list_mutex); + return pctldev; } } - return found ? pctldev : NULL; + mutex_unlock(&pinctrldev_list_mutex); + + return NULL; } struct pinctrl_dev *get_pinctrl_dev_from_of_node(struct device_node *np) @@ -280,6 +283,29 @@ static int pinctrl_register_pins(struct pinctrl_dev *pctldev, } /** + * gpio_to_pin() - GPIO range GPIO number to pin number translation + * @range: GPIO range used for the translation + * @gpio: gpio pin to translate to a pin number + * + * Finds the pin number for a given GPIO using the specified GPIO range + * as a base for translation. The distinction between linear GPIO ranges + * and pin list based GPIO ranges is managed correctly by this function. + * + * This function assumes the gpio is part of the specified GPIO range, use + * only after making sure this is the case (e.g. by calling it on the + * result of successful pinctrl_get_device_gpio_range calls)! + */ +static inline int gpio_to_pin(struct pinctrl_gpio_range *range, + unsigned int gpio) +{ + unsigned int offset = gpio - range->base; + if (range->pins) + return range->pins[offset]; + else + return range->pin_base + offset; +} + +/** * pinctrl_match_gpio_range() - check if a certain GPIO pin is in range * @pctldev: pin controller device to check * @gpio: gpio pin to check taken from the global GPIO pin space @@ -326,6 +352,8 @@ static bool pinctrl_ready_for_gpio_range(unsigned gpio) struct pinctrl_gpio_range *range = NULL; struct gpio_chip *chip = gpio_to_chip(gpio); + mutex_lock(&pinctrldev_list_mutex); + /* Loop over the pin controllers */ list_for_each_entry(pctldev, &pinctrldev_list, node) { /* Loop over the ranges */ @@ -334,9 +362,13 @@ static bool pinctrl_ready_for_gpio_range(unsigned gpio) if (range->base + range->npins - 1 < chip->base || range->base > chip->base + chip->ngpio - 1) continue; + mutex_unlock(&pinctrldev_list_mutex); return true; } } + + mutex_unlock(&pinctrldev_list_mutex); + return false; } #else @@ -408,8 +440,6 @@ struct pinctrl_dev *pinctrl_find_and_add_gpio_range(const char *devname, { struct pinctrl_dev *pctldev; - mutex_lock(&pinctrldev_list_mutex); - pctldev = get_pinctrl_dev_from_devname(devname); /* @@ -418,13 +448,10 @@ struct pinctrl_dev *pinctrl_find_and_add_gpio_range(const char *devname, * range need to defer probing. */ if (!pctldev) { - mutex_unlock(&pinctrldev_list_mutex); return ERR_PTR(-EPROBE_DEFER); } pinctrl_add_gpio_range(pctldev, range); - mutex_unlock(&pinctrldev_list_mutex); - return pctldev; } EXPORT_SYMBOL_GPL(pinctrl_find_and_add_gpio_range); @@ -438,21 +465,26 @@ struct pinctrl_gpio_range * pinctrl_find_gpio_range_from_pin(struct pinctrl_dev *pctldev, unsigned int pin) { - struct pinctrl_gpio_range *range = NULL; + struct pinctrl_gpio_range *range; mutex_lock(&pctldev->mutex); /* Loop over the ranges */ list_for_each_entry(range, &pctldev->gpio_ranges, node) { /* Check if we're in the valid range */ - if (pin >= range->pin_base && - pin < range->pin_base + range->npins) { - mutex_unlock(&pctldev->mutex); - return range; - } + if (range->pins) { + int a; + for (a = 0; a < range->npins; a++) { + if (range->pins[a] == pin) + goto out; + } + } else if (pin >= range->pin_base && + pin < range->pin_base + range->npins) + goto out; } + range = NULL; +out: mutex_unlock(&pctldev->mutex); - - return NULL; + return range; } EXPORT_SYMBOL_GPL(pinctrl_find_gpio_range_from_pin); @@ -517,22 +549,18 @@ int pinctrl_request_gpio(unsigned gpio) int ret; int pin; - mutex_lock(&pinctrldev_list_mutex); - ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range); if (ret) { if (pinctrl_ready_for_gpio_range(gpio)) ret = 0; - mutex_unlock(&pinctrldev_list_mutex); return ret; } /* Convert to the pin controllers number space */ - pin = gpio - range->base + range->pin_base; + pin = gpio_to_pin(range, gpio); ret = pinmux_request_gpio(pctldev, range, pin, gpio); - mutex_unlock(&pinctrldev_list_mutex); return ret; } EXPORT_SYMBOL_GPL(pinctrl_request_gpio); @@ -552,22 +580,18 @@ void pinctrl_free_gpio(unsigned gpio) int ret; int pin; - mutex_lock(&pinctrldev_list_mutex); - ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range); if (ret) { - mutex_unlock(&pinctrldev_list_mutex); return; } mutex_lock(&pctldev->mutex); /* Convert to the pin controllers number space */ - pin = gpio - range->base + range->pin_base; + pin = gpio_to_pin(range, gpio); pinmux_free_gpio(pctldev, pin, range); mutex_unlock(&pctldev->mutex); - mutex_unlock(&pinctrldev_list_mutex); } EXPORT_SYMBOL_GPL(pinctrl_free_gpio); @@ -578,22 +602,18 @@ static int pinctrl_gpio_direction(unsigned gpio, bool input) int ret; int pin; - mutex_lock(&pinctrldev_list_mutex); - ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range); if (ret) { - mutex_unlock(&pinctrldev_list_mutex); return ret; } mutex_lock(&pctldev->mutex); /* Convert to the pin controllers number space */ - pin = gpio - range->base + range->pin_base; + pin = gpio_to_pin(range, gpio); ret = pinmux_gpio_direction(pctldev, range, pin, input); mutex_unlock(&pctldev->mutex); - mutex_unlock(&pinctrldev_list_mutex); return ret; } @@ -1204,6 +1224,69 @@ int pinctrl_force_default(struct pinctrl_dev *pctldev) } EXPORT_SYMBOL_GPL(pinctrl_force_default); +#ifdef CONFIG_PM + +/** + * pinctrl_pm_select_default_state() - select default pinctrl state for PM + * @dev: device to select default state for + */ +int pinctrl_pm_select_default_state(struct device *dev) +{ + struct dev_pin_info *pins = dev->pins; + int ret; + + if (!pins) + return 0; + if (IS_ERR(pins->default_state)) + return 0; /* No default state */ + ret = pinctrl_select_state(pins->p, pins->default_state); + if (ret) + dev_err(dev, "failed to activate default pinctrl state\n"); + return ret; +} +EXPORT_SYMBOL_GPL(pinctrl_pm_select_default_state); + +/** + * pinctrl_pm_select_sleep_state() - select sleep pinctrl state for PM + * @dev: device to select sleep state for + */ +int pinctrl_pm_select_sleep_state(struct device *dev) +{ + struct dev_pin_info *pins = dev->pins; + int ret; + + if (!pins) + return 0; + if (IS_ERR(pins->sleep_state)) + return 0; /* No sleep state */ + ret = pinctrl_select_state(pins->p, pins->sleep_state); + if (ret) + dev_err(dev, "failed to activate pinctrl sleep state\n"); + return ret; +} +EXPORT_SYMBOL_GPL(pinctrl_pm_select_sleep_state); + +/** + * pinctrl_pm_select_idle_state() - select idle pinctrl state for PM + * @dev: device to select idle state for + */ +int pinctrl_pm_select_idle_state(struct device *dev) +{ + struct dev_pin_info *pins = dev->pins; + int ret; + + if (!pins) + return 0; + if (IS_ERR(pins->idle_state)) + return 0; /* No idle state */ + ret = pinctrl_select_state(pins->p, pins->idle_state); + if (ret) + dev_err(dev, "failed to activate pinctrl idle state\n"); + return ret; +} +EXPORT_SYMBOL_GPL(pinctrl_pm_select_idle_state); +#endif + #ifdef CONFIG_DEBUG_FS static int pinctrl_pins_show(struct seq_file *s, void *what) @@ -1296,11 +1379,21 @@ static int pinctrl_gpioranges_show(struct seq_file *s, void *what) /* Loop over the ranges */ list_for_each_entry(range, &pctldev->gpio_ranges, node) { - seq_printf(s, "%u: %s GPIOS [%u - %u] PINS [%u - %u]\n", - range->id, range->name, - range->base, (range->base + range->npins - 1), - range->pin_base, - (range->pin_base + range->npins - 1)); + if (range->pins) { + int a; + seq_printf(s, "%u: %s GPIOS [%u - %u] PINS {", + range->id, range->name, + range->base, (range->base + range->npins - 1)); + for (a = 0; a < range->npins - 1; a++) + seq_printf(s, "%u, ", range->pins[a]); + seq_printf(s, "%u}\n", range->pins[a]); + } + else + seq_printf(s, "%u: %s GPIOS [%u - %u] PINS [%u - %u]\n", + range->id, range->name, + range->base, (range->base + range->npins - 1), + range->pin_base, + (range->pin_base + range->npins - 1)); } mutex_unlock(&pctldev->mutex); diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c index 428ea96a94d..048ae80adab 100644 --- a/drivers/pinctrl/mvebu/pinctrl-dove.c +++ b/drivers/pinctrl/mvebu/pinctrl-dove.c @@ -26,6 +26,9 @@ #define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) #define DOVE_AU0_AC97_SEL BIT(16) +#define DOVE_PMU_SIGNAL_SELECT_0 (DOVE_SB_REGS_VIRT_BASE + 0xd802C) +#define DOVE_PMU_SIGNAL_SELECT_1 (DOVE_SB_REGS_VIRT_BASE + 0xd8030) +#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) #define DOVE_TWSI_ENABLE_OPTION1 BIT(7) #define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) @@ -58,12 +61,16 @@ static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl *ctrl, unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS; unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS; unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); - unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off); - - if (pmu & (1 << ctrl->pid)) - *config = CONFIG_PMU; - else - *config = (mpp >> shift) & MPP_MASK; + unsigned long func; + + if (pmu & (1 << ctrl->pid)) { + func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off); + *config = (func >> shift) & MPP_MASK; + *config |= CONFIG_PMU; + } else { + func = readl(DOVE_MPP_VIRT_BASE + off); + *config = (func >> shift) & MPP_MASK; + } return 0; } @@ -73,15 +80,20 @@ static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl *ctrl, unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS; unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS; unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); - unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off); + unsigned long func; - if (config == CONFIG_PMU) + if (config & CONFIG_PMU) { writel(pmu | (1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL); - else { + func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off); + func &= ~(MPP_MASK << shift); + func |= (config & MPP_MASK) << shift; + writel(func, DOVE_PMU_SIGNAL_SELECT_0 + off); + } else { writel(pmu & ~(1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL); - mpp &= ~(MPP_MASK << shift); - mpp |= config << shift; - writel(mpp, DOVE_MPP_VIRT_BASE + off); + func = readl(DOVE_MPP_VIRT_BASE + off); + func &= ~(MPP_MASK << shift); + func |= (config & MPP_MASK) << shift; + writel(func, DOVE_MPP_VIRT_BASE + off); } return 0; } @@ -378,20 +390,53 @@ static struct mvebu_mpp_mode dove_mpp_modes[] = { MPP_FUNCTION(0x02, "uart2", "rts"), MPP_FUNCTION(0x03, "sdio0", "cd"), MPP_FUNCTION(0x0f, "lcd0", "pwm"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(1, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x02, "uart2", "cts"), MPP_FUNCTION(0x03, "sdio0", "wp"), MPP_FUNCTION(0x0f, "lcd1", "pwm"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(2, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x01, "sata", "prsnt"), MPP_FUNCTION(0x02, "uart2", "txd"), MPP_FUNCTION(0x03, "sdio0", "buspwr"), MPP_FUNCTION(0x04, "uart1", "rts"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(3, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x01, "sata", "act"), @@ -399,43 +444,131 @@ static struct mvebu_mpp_mode dove_mpp_modes[] = { MPP_FUNCTION(0x03, "sdio0", "ledctrl"), MPP_FUNCTION(0x04, "uart1", "cts"), MPP_FUNCTION(0x0f, "lcd-spi", "cs1"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(4, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x02, "uart3", "rts"), MPP_FUNCTION(0x03, "sdio1", "cd"), MPP_FUNCTION(0x04, "spi1", "miso"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(5, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x02, "uart3", "cts"), MPP_FUNCTION(0x03, "sdio1", "wp"), MPP_FUNCTION(0x04, "spi1", "cs"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(6, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x02, "uart3", "txd"), MPP_FUNCTION(0x03, "sdio1", "buspwr"), MPP_FUNCTION(0x04, "spi1", "mosi"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(7, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x02, "uart3", "rxd"), MPP_FUNCTION(0x03, "sdio1", "ledctrl"), MPP_FUNCTION(0x04, "spi1", "sck"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(8, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x01, "watchdog", "rstout"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(9, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x05, "pex1", "clkreq"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(10, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x05, "ssp", "sclk"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(11, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x01, "sata", "prsnt"), @@ -443,33 +576,88 @@ static struct mvebu_mpp_mode dove_mpp_modes[] = { MPP_FUNCTION(0x03, "sdio0", "ledctrl"), MPP_FUNCTION(0x04, "sdio1", "ledctrl"), MPP_FUNCTION(0x05, "pex0", "clkreq"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(12, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x01, "sata", "act"), MPP_FUNCTION(0x02, "uart2", "rts"), MPP_FUNCTION(0x03, "audio0", "extclk"), MPP_FUNCTION(0x04, "sdio1", "cd"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(13, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x02, "uart2", "cts"), MPP_FUNCTION(0x03, "audio1", "extclk"), MPP_FUNCTION(0x04, "sdio1", "wp"), MPP_FUNCTION(0x05, "ssp", "extclk"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(14, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x02, "uart2", "txd"), MPP_FUNCTION(0x04, "sdio1", "buspwr"), MPP_FUNCTION(0x05, "ssp", "rxd"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(15, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x02, "uart2", "rxd"), MPP_FUNCTION(0x04, "sdio1", "ledctrl"), MPP_FUNCTION(0x05, "ssp", "sfrm"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(16, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x02, "uart3", "rts"), diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 2ad5a8d337b..8594f033ac2 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -21,6 +21,7 @@ #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> +#include <linux/of.h> #include "core.h" #include "pinconf.h" @@ -37,14 +38,18 @@ struct pin_config_item { static struct pin_config_item conf_items[] = { PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL), PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL), + PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL), PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL), PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL), + PCONFDUMP(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, + "input bias pull to pin specific state", NULL), PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL), PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL), PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL), + PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH, "output drive strength", "mA"), PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL), PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL), - PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "time units"), + PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec"), PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector"), PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL), PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, "pin low power", "mode"), @@ -135,3 +140,100 @@ void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, } EXPORT_SYMBOL_GPL(pinconf_generic_dump_config); #endif + +#ifdef CONFIG_OF +struct pinconf_generic_dt_params { + const char * const property; + enum pin_config_param param; + u32 default_value; +}; + +static struct pinconf_generic_dt_params dt_params[] = { + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 }, + { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, + { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 }, + { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 }, + { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, + { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 }, + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, + { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, + { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, + { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, + { "low-power-enable", PIN_CONFIG_LOW_POWER_MODE, 1 }, + { "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 }, + { "output-low", PIN_CONFIG_OUTPUT, 0, }, + { "output-high", PIN_CONFIG_OUTPUT, 1, }, +}; + +/** + * pinconf_generic_parse_dt_config() + * parse the config properties into generic pinconfig values. + * @np: node containing the pinconfig properties + * @configs: array with nconfigs entries containing the generic pinconf values + * @nconfigs: umber of configurations + */ +int pinconf_generic_parse_dt_config(struct device_node *np, + unsigned long **configs, + unsigned int *nconfigs) +{ + unsigned long *cfg; + unsigned int ncfg = 0; + int ret; + int i; + u32 val; + + if (!np) + return -EINVAL; + + /* allocate a temporary array big enough to hold one of each option */ + cfg = kzalloc(sizeof(*cfg) * ARRAY_SIZE(dt_params), GFP_KERNEL); + if (!cfg) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(dt_params); i++) { + struct pinconf_generic_dt_params *par = &dt_params[i]; + ret = of_property_read_u32(np, par->property, &val); + + /* property not found */ + if (ret == -EINVAL) + continue; + + /* use default value, when no value is specified */ + if (ret) + val = par->default_value; + + pr_debug("found %s with value %u\n", par->property, val); + cfg[ncfg] = pinconf_to_config_packed(par->param, val); + ncfg++; + } + + ret = 0; + + /* no configs found at all */ + if (ncfg == 0) { + *configs = NULL; + *nconfigs = 0; + goto out; + } + + /* + * Now limit the number of configs to the real number of + * found properties. + */ + *configs = kzalloc(ncfg * sizeof(unsigned long), GFP_KERNEL); + if (!*configs) { + ret = -ENOMEM; + goto out; + } + + memcpy(*configs, cfg, ncfg * sizeof(unsigned long)); + *nconfigs = ncfg; + +out: + kfree(cfg); + return ret; +} +#endif diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c index 694c3ace452..e875f21a590 100644 --- a/drivers/pinctrl/pinconf.c +++ b/drivers/pinctrl/pinconf.c @@ -75,98 +75,6 @@ int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin, return ops->pin_config_get(pctldev, pin, config); } -/** - * pin_config_get() - get the configuration of a single pin parameter - * @dev_name: name of the pin controller device for this pin - * @name: name of the pin to get the config for - * @config: the config pointed to by this argument will be filled in with the - * current pin state, it can be used directly by drivers as a numeral, or - * it can be dereferenced to any struct. - */ -int pin_config_get(const char *dev_name, const char *name, - unsigned long *config) -{ - struct pinctrl_dev *pctldev; - int pin; - - pctldev = get_pinctrl_dev_from_devname(dev_name); - if (!pctldev) { - pin = -EINVAL; - return pin; - } - - mutex_lock(&pctldev->mutex); - - pin = pin_get_from_name(pctldev, name); - if (pin < 0) - goto unlock; - - pin = pin_config_get_for_pin(pctldev, pin, config); - -unlock: - mutex_unlock(&pctldev->mutex); - return pin; -} -EXPORT_SYMBOL(pin_config_get); - -static int pin_config_set_for_pin(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long config) -{ - const struct pinconf_ops *ops = pctldev->desc->confops; - int ret; - - if (!ops || !ops->pin_config_set) { - dev_err(pctldev->dev, "cannot configure pin, missing " - "config function in driver\n"); - return -EINVAL; - } - - ret = ops->pin_config_set(pctldev, pin, config); - if (ret) { - dev_err(pctldev->dev, - "unable to set pin configuration on pin %d\n", pin); - return ret; - } - - return 0; -} - -/** - * pin_config_set() - set the configuration of a single pin parameter - * @dev_name: name of pin controller device for this pin - * @name: name of the pin to set the config for - * @config: the config in this argument will contain the desired pin state, it - * can be used directly by drivers as a numeral, or it can be dereferenced - * to any struct. - */ -int pin_config_set(const char *dev_name, const char *name, - unsigned long config) -{ - struct pinctrl_dev *pctldev; - int pin, ret; - - pctldev = get_pinctrl_dev_from_devname(dev_name); - if (!pctldev) { - ret = -EINVAL; - return ret; - } - - mutex_lock(&pctldev->mutex); - - pin = pin_get_from_name(pctldev, name); - if (pin < 0) { - ret = pin; - goto unlock; - } - - ret = pin_config_set_for_pin(pctldev, pin, config); - -unlock: - mutex_unlock(&pctldev->mutex); - return ret; -} -EXPORT_SYMBOL(pin_config_set); - int pin_config_group_get(const char *dev_name, const char *pin_group, unsigned long *config) { @@ -204,88 +112,6 @@ unlock: mutex_unlock(&pctldev->mutex); return ret; } -EXPORT_SYMBOL(pin_config_group_get); - -int pin_config_group_set(const char *dev_name, const char *pin_group, - unsigned long config) -{ - struct pinctrl_dev *pctldev; - const struct pinconf_ops *ops; - const struct pinctrl_ops *pctlops; - int selector; - const unsigned *pins; - unsigned num_pins; - int ret; - int i; - - pctldev = get_pinctrl_dev_from_devname(dev_name); - if (!pctldev) { - ret = -EINVAL; - return ret; - } - - mutex_lock(&pctldev->mutex); - - ops = pctldev->desc->confops; - pctlops = pctldev->desc->pctlops; - - if (!ops || (!ops->pin_config_group_set && !ops->pin_config_set)) { - dev_err(pctldev->dev, "cannot configure pin group, missing " - "config function in driver\n"); - ret = -EINVAL; - goto unlock; - } - - selector = pinctrl_get_group_selector(pctldev, pin_group); - if (selector < 0) { - ret = selector; - goto unlock; - } - - ret = pctlops->get_group_pins(pctldev, selector, &pins, &num_pins); - if (ret) { - dev_err(pctldev->dev, "cannot configure pin group, error " - "getting pins\n"); - goto unlock; - } - - /* - * If the pin controller supports handling entire groups we use that - * capability. - */ - if (ops->pin_config_group_set) { - ret = ops->pin_config_group_set(pctldev, selector, config); - /* - * If the pin controller prefer that a certain group be handled - * pin-by-pin as well, it returns -EAGAIN. - */ - if (ret != -EAGAIN) - goto unlock; - } - - /* - * If the controller cannot handle entire groups, we configure each pin - * individually. - */ - if (!ops->pin_config_set) { - ret = 0; - goto unlock; - } - - for (i = 0; i < num_pins; i++) { - ret = ops->pin_config_set(pctldev, pins[i], config); - if (ret < 0) - goto unlock; - } - - ret = 0; - -unlock: - mutex_unlock(&pctldev->mutex); - - return ret; -} -EXPORT_SYMBOL(pin_config_group_set); int pinconf_map_to_setting(struct pinctrl_map const *map, struct pinctrl_setting *setting) diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h index 92c7267244d..a4a5417e141 100644 --- a/drivers/pinctrl/pinconf.h +++ b/drivers/pinctrl/pinconf.h @@ -123,3 +123,9 @@ static inline void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, return; } #endif + +#if defined(CONFIG_GENERIC_PINCONF) && defined(CONFIG_OF) +int pinconf_generic_parse_dt_config(struct device_node *np, + unsigned long **configs, + unsigned int *nconfigs); +#endif diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c index 6d4532702f8..1d3f988c2c8 100644 --- a/drivers/pinctrl/pinctrl-abx500.c +++ b/drivers/pinctrl/pinctrl-abx500.c @@ -30,8 +30,11 @@ #include <linux/pinctrl/pinmux.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/machine.h> #include "pinctrl-abx500.h" +#include "core.h" +#include "pinconf.h" /* * The AB9540 and AB8540 GPIO support are extended versions @@ -93,13 +96,15 @@ #define AB8540_GPIOX_VBAT_START 51 #define AB8540_GPIOX_VBAT_END 54 +#define ABX500_GPIO_INPUT 0 +#define ABX500_GPIO_OUTPUT 1 + struct abx500_pinctrl { struct device *dev; struct pinctrl_dev *pctldev; struct abx500_pinctrl_soc_data *soc; struct gpio_chip chip; struct ab8500 *parent; - struct mutex lock; struct abx500_gpio_irq_cluster *irq_cluster; int irq_cluster_size; }; @@ -129,8 +134,8 @@ static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg, if (ret < 0) dev_err(pct->dev, - "%s read reg =%x, offset=%x failed\n", - __func__, reg, offset); + "%s read reg =%x, offset=%x failed (%d)\n", + __func__, reg, offset, ret); return ret; } @@ -146,7 +151,8 @@ static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg, ret = abx500_mask_and_set_register_interruptible(pct->dev, AB8500_MISC, reg, BIT(pos), val << pos); if (ret < 0) - dev_err(pct->dev, "%s write failed\n", __func__); + dev_err(pct->dev, "%s write reg, %x offset %x failed (%d)\n", + __func__, reg, offset, ret); return ret; } @@ -160,12 +166,24 @@ static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset) { struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); bool bit; + bool is_out; + u8 gpio_offset = offset - 1; int ret; - ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG, - offset, &bit); + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, + gpio_offset, &is_out); + if (ret < 0) + goto out; + + if (is_out) + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_OUT1_REG, + gpio_offset, &bit); + else + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG, + gpio_offset, &bit); +out: if (ret < 0) { - dev_err(pct->dev, "%s failed\n", __func__); + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); return ret; } @@ -179,13 +197,14 @@ static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val) ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); if (ret < 0) - dev_err(pct->dev, "%s write failed\n", __func__); + dev_err(pct->dev, "%s write failed (%d)\n", __func__, ret); } -static int abx500_config_pull_updown(struct abx500_pinctrl *pct, - int offset, enum abx500_gpio_pull_updown val) +static int abx500_get_pull_updown(struct abx500_pinctrl *pct, int offset, + enum abx500_gpio_pull_updown *pull_updown) { u8 pos; + u8 val; int ret; struct pullud *pullud; @@ -204,7 +223,41 @@ static int abx500_config_pull_updown(struct abx500_pinctrl *pct, goto out; } - pos = offset << 1; + ret = abx500_get_register_interruptible(pct->dev, + AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, &val); + + pos = (offset - pullud->first_pin) << 1; + *pull_updown = (val >> pos) & AB8540_GPIO_PULL_UPDOWN_MASK; + +out: + if (ret < 0) + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); + + return ret; +} + +static int abx500_set_pull_updown(struct abx500_pinctrl *pct, + int offset, enum abx500_gpio_pull_updown val) +{ + u8 pos; + int ret; + struct pullud *pullud; + + if (!pct->soc->pullud) { + dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature", + __func__); + ret = -EPERM; + goto out; + } + + pullud = pct->soc->pullud; + + if ((offset < pullud->first_pin) + || (offset > pullud->last_pin)) { + ret = -EINVAL; + goto out; + } + pos = (offset - pullud->first_pin) << 1; ret = abx500_mask_and_set_register_interruptible(pct->dev, AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, @@ -217,33 +270,51 @@ out: return ret; } +static bool abx500_pullud_supported(struct gpio_chip *chip, unsigned gpio) +{ + struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); + struct pullud *pullud = pct->soc->pullud; + + return (pullud && + gpio >= pullud->first_pin && + gpio <= pullud->last_pin); +} + static int abx500_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int val) { struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); - struct pullud *pullud = pct->soc->pullud; unsigned gpio; int ret; /* set direction as output */ - ret = abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1); + ret = abx500_gpio_set_bits(chip, + AB8500_GPIO_DIR1_REG, + offset, + ABX500_GPIO_OUTPUT); if (ret < 0) - return ret; + goto out; /* disable pull down */ - ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1); + ret = abx500_gpio_set_bits(chip, + AB8500_GPIO_PUD1_REG, + offset, + ABX500_GPIO_PULL_NONE); if (ret < 0) - return ret; + goto out; /* if supported, disable both pull down and pull up */ gpio = offset + 1; - if (pullud && gpio >= pullud->first_pin && gpio <= pullud->last_pin) { - ret = abx500_config_pull_updown(pct, + if (abx500_pullud_supported(chip, gpio)) { + ret = abx500_set_pull_updown(pct, gpio, ABX500_GPIO_PULL_NONE); - if (ret < 0) - return ret; + } +out: + if (ret < 0) { + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); + return ret; } /* set the output as 1 or 0 */ @@ -253,7 +324,10 @@ static int abx500_gpio_direction_output(struct gpio_chip *chip, static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { /* set the register as input */ - return abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0); + return abx500_gpio_set_bits(chip, + AB8500_GPIO_DIR1_REG, + offset, + ABX500_GPIO_INPUT); } static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset) @@ -338,10 +412,16 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, if (af.alt_bit1 != UNUSED) { ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, offset, 0); + if (ret < 0) + goto out; + ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit1, !!(af.alta_val && BIT(0))); + if (ret < 0) + goto out; + if (af.alt_bit2 != UNUSED) ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, @@ -355,8 +435,14 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, case ABX500_ALT_B: ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, offset, 0); + if (ret < 0) + goto out; + ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit1, !!(af.altb_val && BIT(0))); + if (ret < 0) + goto out; + if (af.alt_bit2 != UNUSED) ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, @@ -367,8 +453,14 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, case ABX500_ALT_C: ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, offset, 0); + if (ret < 0) + goto out; + ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2, !!(af.altc_val && BIT(0))); + if (ret < 0) + goto out; + ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2, !!(af.altc_val && BIT(1))); break; @@ -378,11 +470,14 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, return -EINVAL; } +out: + if (ret < 0) + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); return ret; } -static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, +static int abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, unsigned gpio) { u8 mode; @@ -393,6 +488,7 @@ static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, struct alternate_functions af = pct->soc->alternate_functions[gpio]; /* on ABx5xx, there is no GPIO0, so adjust the offset */ unsigned offset = gpio - 1; + int ret; /* * if gpiosel_bit is set to unused, @@ -402,8 +498,11 @@ static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, return ABX500_DEFAULT; /* read GpioSelx register */ - abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8), + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8), af.gpiosel_bit, &bit_mode); + if (ret < 0) + goto out; + mode = bit_mode; /* sanity check */ @@ -435,14 +534,19 @@ static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, * pin use the AlternatFunction register * read alt_bit1 value */ - abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit1, &alt_bit1); + if (ret < 0) + goto out; - if (af.alt_bit2 != UNUSED) + if (af.alt_bit2 != UNUSED) { /* read alt_bit2 value */ - abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2, + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, + af.alt_bit2, &alt_bit2); - else + if (ret < 0) + goto out; + } else alt_bit2 = 0; mode = (alt_bit2 << 1) + alt_bit1; @@ -452,6 +556,10 @@ static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, return ABX500_ALT_B; else return ABX500_ALT_C; + +out: + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); + return ret; } #ifdef CONFIG_DEBUG_FS @@ -463,11 +571,14 @@ static void abx500_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip, unsigned offset, unsigned gpio) { + struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); const char *label = gpiochip_is_requested(chip, offset - 1); u8 gpio_offset = offset - 1; int mode = -1; bool is_out; - bool pull; + bool pd; + enum abx500_gpio_pull_updown pud = 0; + int ret; const char *modes[] = { [ABX500_DEFAULT] = "default", @@ -476,21 +587,48 @@ static void abx500_gpio_dbg_show_one(struct seq_file *s, [ABX500_ALT_C] = "altC", }; - abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, gpio_offset, &is_out); - abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, gpio_offset, &pull); + const char *pull_up_down[] = { + [ABX500_GPIO_PULL_DOWN] = "pull down", + [ABX500_GPIO_PULL_NONE] = "pull none", + [ABX500_GPIO_PULL_NONE + 1] = "pull none", + [ABX500_GPIO_PULL_UP] = "pull up", + }; + + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, + gpio_offset, &is_out); + if (ret < 0) + goto out; + + seq_printf(s, " gpio-%-3d (%-20.20s) %-3s", + gpio, label ?: "(none)", + is_out ? "out" : "in "); + + if (!is_out) { + if (abx500_pullud_supported(chip, offset)) { + ret = abx500_get_pull_updown(pct, offset, &pud); + if (ret < 0) + goto out; + + seq_printf(s, " %-9s", pull_up_down[pud]); + } else { + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, + gpio_offset, &pd); + if (ret < 0) + goto out; + + seq_printf(s, " %-9s", pull_up_down[pd]); + } + } else + seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo"); if (pctldev) mode = abx500_get_mode(pctldev, chip, offset); - seq_printf(s, " gpio-%-3d (%-20.20s) %-3s %-9s %s", - gpio, label ?: "(none)", - is_out ? "out" : "in ", - is_out ? - (chip->get - ? (chip->get(chip, offset) ? "hi" : "lo") - : "? ") - : (pull ? "pull up" : "pull down"), - (mode < 0) ? "unknown" : modes[mode]); + seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]); + +out: + if (ret < 0) + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); } static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) @@ -594,6 +732,9 @@ static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting); } + if (ret < 0) + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); + return ret; } @@ -642,10 +783,8 @@ static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev, ret = abx500_set_mode(pct->pctldev, &pct->chip, offset, p->altfunc); - if (ret < 0) { + if (ret < 0) dev_err(pct->dev, "%s setting altfunc failed\n", __func__); - return ret; - } return ret; } @@ -704,11 +843,193 @@ static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev, chip->base + offset - 1); } +static void abx500_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ + int i; + + for (i = 0; i < num_maps; i++) + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) + kfree(map[i].data.configs.configs); + kfree(map); +} + +static int abx500_dt_reserve_map(struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps, + unsigned reserve) +{ + unsigned old_num = *reserved_maps; + unsigned new_num = *num_maps + reserve; + struct pinctrl_map *new_map; + + if (old_num >= new_num) + return 0; + + new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); + if (!new_map) + return -ENOMEM; + + memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); + + *map = new_map; + *reserved_maps = new_num; + + return 0; +} + +static int abx500_dt_add_map_mux(struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps, const char *group, + const char *function) +{ + if (*num_maps == *reserved_maps) + return -ENOSPC; + + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.group = group; + (*map)[*num_maps].data.mux.function = function; + (*num_maps)++; + + return 0; +} + +static int abx500_dt_add_map_configs(struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps, const char *group, + unsigned long *configs, unsigned num_configs) +{ + unsigned long *dup_configs; + + if (*num_maps == *reserved_maps) + return -ENOSPC; + + dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), + GFP_KERNEL); + if (!dup_configs) + return -ENOMEM; + + (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; + + (*map)[*num_maps].data.configs.group_or_pin = group; + (*map)[*num_maps].data.configs.configs = dup_configs; + (*map)[*num_maps].data.configs.num_configs = num_configs; + (*num_maps)++; + + return 0; +} + +static const char *abx500_find_pin_name(struct pinctrl_dev *pctldev, + const char *pin_name) +{ + int i, pin_number; + struct abx500_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + + if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) + for (i = 0; i < npct->soc->npins; i++) + if (npct->soc->pins[i].number == pin_number) + return npct->soc->pins[i].name; + return NULL; +} + +static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps) +{ + int ret; + const char *function = NULL; + unsigned long *configs; + unsigned int nconfigs = 0; + bool has_config = 0; + unsigned reserve = 0; + struct property *prop; + const char *group, *gpio_name; + struct device_node *np_config; + + ret = of_property_read_string(np, "ste,function", &function); + if (ret >= 0) + reserve = 1; + + ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs); + if (nconfigs) + has_config = 1; + + np_config = of_parse_phandle(np, "ste,config", 0); + if (np_config) { + ret = pinconf_generic_parse_dt_config(np_config, &configs, + &nconfigs); + if (ret) + goto exit; + has_config |= nconfigs; + } + + ret = of_property_count_strings(np, "ste,pins"); + if (ret < 0) + goto exit; + + if (has_config) + reserve++; + + reserve *= ret; + + ret = abx500_dt_reserve_map(map, reserved_maps, num_maps, reserve); + if (ret < 0) + goto exit; + + of_property_for_each_string(np, "ste,pins", prop, group) { + if (function) { + ret = abx500_dt_add_map_mux(map, reserved_maps, + num_maps, group, function); + if (ret < 0) + goto exit; + } + if (has_config) { + gpio_name = abx500_find_pin_name(pctldev, group); + + ret = abx500_dt_add_map_configs(map, reserved_maps, + num_maps, gpio_name, configs, 1); + if (ret < 0) + goto exit; + } + + } +exit: + return ret; +} + +static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, unsigned *num_maps) +{ + unsigned reserved_maps; + struct device_node *np; + int ret; + + reserved_maps = 0; + *map = NULL; + *num_maps = 0; + + for_each_child_of_node(np_config, np) { + ret = abx500_dt_subnode_to_map(pctldev, np, map, + &reserved_maps, num_maps); + if (ret < 0) { + abx500_dt_free_map(pctldev, *map, *num_maps); + return ret; + } + } + + return 0; +} + static const struct pinctrl_ops abx500_pinctrl_ops = { .get_groups_count = abx500_get_groups_cnt, .get_group_name = abx500_get_group_name, .get_group_pins = abx500_get_group_pins, .pin_dbg_show = abx500_pin_dbg_show, + .dt_node_to_map = abx500_dt_node_to_map, + .dt_free_map = abx500_dt_free_map, }; static int abx500_pin_config_get(struct pinctrl_dev *pctldev, @@ -723,10 +1044,9 @@ static int abx500_pin_config_set(struct pinctrl_dev *pctldev, unsigned long config) { struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); - struct pullud *pullud = pct->soc->pullud; struct gpio_chip *chip = &pct->chip; unsigned offset; - int ret; + int ret = -EINVAL; enum pin_config_param param = pinconf_to_config_param(config); enum pin_config_param argument = pinconf_to_config_argument(config); @@ -739,41 +1059,83 @@ static int abx500_pin_config_set(struct pinctrl_dev *pctldev, offset = pin - 1; switch (param) { - case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_DISABLE: + ret = abx500_gpio_direction_input(chip, offset); + if (ret < 0) + goto out; /* - * if argument = 1 set the pull down - * else clear the pull down + * Some chips only support pull down, while some actually + * support both pull up and pull down. Such chips have + * a "pullud" range specified for the pins that support + * both features. If the pin is not within that range, we + * fall back to the old bit set that only support pull down. */ + if (abx500_pullud_supported(chip, pin)) + ret = abx500_set_pull_updown(pct, + pin, + ABX500_GPIO_PULL_NONE); + else + /* Chip only supports pull down */ + ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, + offset, ABX500_GPIO_PULL_NONE); + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: ret = abx500_gpio_direction_input(chip, offset); + if (ret < 0) + goto out; /* + * if argument = 1 set the pull down + * else clear the pull down * Some chips only support pull down, while some actually * support both pull up and pull down. Such chips have * a "pullud" range specified for the pins that support * both features. If the pin is not within that range, we * fall back to the old bit set that only support pull down. */ - if (pullud && - pin >= pullud->first_pin && - pin <= pullud->last_pin) - ret = abx500_config_pull_updown(pct, + if (abx500_pullud_supported(chip, pin)) + ret = abx500_set_pull_updown(pct, pin, argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE); else /* Chip only supports pull down */ ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, - offset, argument ? 0 : 1); + offset, + argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE); + break; + + case PIN_CONFIG_BIAS_PULL_UP: + ret = abx500_gpio_direction_input(chip, offset); + if (ret < 0) + goto out; + /* + * if argument = 1 set the pull up + * else clear the pull up + */ + ret = abx500_gpio_direction_input(chip, offset); + /* + * Some chips only support pull down, while some actually + * support both pull up and pull down. Such chips have + * a "pullud" range specified for the pins that support + * both features. If the pin is not within that range, do + * nothing + */ + if (abx500_pullud_supported(chip, pin)) + ret = abx500_set_pull_updown(pct, + pin, + argument ? ABX500_GPIO_PULL_UP : ABX500_GPIO_PULL_NONE); break; case PIN_CONFIG_OUTPUT: ret = abx500_gpio_direction_output(chip, offset, argument); - break; default: dev_err(chip->dev, "illegal configuration requested\n"); - - return -EINVAL; } +out: + if (ret < 0) + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); return ret; } @@ -881,9 +1243,6 @@ static int abx500_gpio_probe(struct platform_device *pdev) id = (unsigned long)match->data; } - /* initialize the lock */ - mutex_init(&pct->lock); - /* Poke in other ASIC variants here */ switch (id) { case PINCTRL_AB8500: @@ -900,13 +1259,11 @@ static int abx500_gpio_probe(struct platform_device *pdev) break; default: dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id); - mutex_destroy(&pct->lock); return -EINVAL; } if (!pct->soc) { dev_err(&pdev->dev, "Invalid SOC data\n"); - mutex_destroy(&pct->lock); return -EINVAL; } @@ -917,7 +1274,6 @@ static int abx500_gpio_probe(struct platform_device *pdev) ret = gpiochip_add(&pct->chip); if (ret) { dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); - mutex_destroy(&pct->lock); return ret; } dev_info(&pdev->dev, "added gpiochip\n"); @@ -954,7 +1310,6 @@ out_rem_chip: if (err) dev_info(&pdev->dev, "failed to remove gpiochip\n"); - mutex_destroy(&pct->lock); return ret; } @@ -974,8 +1329,6 @@ static int abx500_gpio_remove(struct platform_device *pdev) return ret; } - mutex_destroy(&pct->lock); - return 0; } diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 5d7529ed539..b90a3a0ac53 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1543,12 +1543,6 @@ static int at91_gpio_probe(struct platform_device *pdev) goto err; } - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - ret = -ENOENT; - goto err; - } - irq = platform_get_irq(pdev, 0); if (irq < 0) { ret = irq; @@ -1561,6 +1555,7 @@ static int at91_gpio_probe(struct platform_device *pdev) goto err; } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(at91_chip->regbase)) { ret = PTR_ERR(at91_chip->regbase); diff --git a/drivers/pinctrl/pinctrl-baytrail.c b/drivers/pinctrl/pinctrl-baytrail.c new file mode 100644 index 00000000000..e9d735dcebf --- /dev/null +++ b/drivers/pinctrl/pinctrl-baytrail.c @@ -0,0 +1,543 @@ +/* + * Pinctrl GPIO driver for Intel Baytrail + * Copyright (c) 2012-2013, Intel Corporation. + * + * Author: Mathias Nyman <mathias.nyman@linux.intel.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/bitops.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/gpio.h> +#include <linux/irqdomain.h> +#include <linux/acpi.h> +#include <linux/acpi_gpio.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/io.h> +#include <linux/pm_runtime.h> +#include <linux/pinctrl/pinctrl.h> + +/* memory mapped register offsets */ +#define BYT_CONF0_REG 0x000 +#define BYT_CONF1_REG 0x004 +#define BYT_VAL_REG 0x008 +#define BYT_DFT_REG 0x00c +#define BYT_INT_STAT_REG 0x800 + +/* BYT_CONF0_REG register bits */ +#define BYT_TRIG_NEG BIT(26) +#define BYT_TRIG_POS BIT(25) +#define BYT_TRIG_LVL BIT(24) +#define BYT_PIN_MUX 0x07 + +/* BYT_VAL_REG register bits */ +#define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/ +#define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/ +#define BYT_LEVEL BIT(0) + +#define BYT_DIR_MASK (BIT(1) | BIT(2)) +#define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24)) + +#define BYT_NGPIO_SCORE 102 +#define BYT_NGPIO_NCORE 28 +#define BYT_NGPIO_SUS 44 + +/* + * Baytrail gpio controller consist of three separate sub-controllers called + * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID. + * + * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does + * _not_ correspond to the first gpio register at controller's gpio base. + * There is no logic or pattern in mapping gpio numbers to registers (pads) so + * each sub-controller needs to have its own mapping table + */ + +/* score_pins[gpio_nr] = pad_nr */ + +static unsigned const score_pins[BYT_NGPIO_SCORE] = { + 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, + 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, + 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, + 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, + 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, + 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, + 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, + 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, + 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, + 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, + 97, 100, +}; + +static unsigned const ncore_pins[BYT_NGPIO_NCORE] = { + 19, 18, 17, 20, 21, 22, 24, 25, 23, 16, + 14, 15, 12, 26, 27, 1, 4, 8, 11, 0, + 3, 6, 10, 13, 2, 5, 9, 7, +}; + +static unsigned const sus_pins[BYT_NGPIO_SUS] = { + 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, + 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, + 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, + 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, + 52, 53, 59, 40, +}; + +static struct pinctrl_gpio_range byt_ranges[] = { + { + .name = "1", /* match with acpi _UID in probe */ + .npins = BYT_NGPIO_SCORE, + .pins = score_pins, + }, + { + .name = "2", + .npins = BYT_NGPIO_NCORE, + .pins = ncore_pins, + }, + { + .name = "3", + .npins = BYT_NGPIO_SUS, + .pins = sus_pins, + }, + { + }, +}; + +struct byt_gpio { + struct gpio_chip chip; + struct irq_domain *domain; + struct platform_device *pdev; + spinlock_t lock; + void __iomem *reg_base; + struct pinctrl_gpio_range *range; +}; + +static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset, + int reg) +{ + struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip); + u32 reg_offset; + void __iomem *ptr; + + if (reg == BYT_INT_STAT_REG) + reg_offset = (offset / 32) * 4; + else + reg_offset = vg->range->pins[offset] * 16; + + ptr = (void __iomem *) (vg->reg_base + reg_offset + reg); + return ptr; +} + +static int byt_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip); + + pm_runtime_get(&vg->pdev->dev); + + return 0; +} + +static void byt_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip); + void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG); + u32 value; + + /* clear interrupt triggering */ + value = readl(reg); + value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); + writel(value, reg); + + pm_runtime_put(&vg->pdev->dev); +} + +static int byt_irq_type(struct irq_data *d, unsigned type) +{ + struct byt_gpio *vg = irq_data_get_irq_chip_data(d); + u32 offset = irqd_to_hwirq(d); + u32 value; + unsigned long flags; + void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG); + + if (offset >= vg->chip.ngpio) + return -EINVAL; + + spin_lock_irqsave(&vg->lock, flags); + value = readl(reg); + + /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits + * are used to indicate high and low level triggering + */ + value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); + + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + value |= BYT_TRIG_LVL; + case IRQ_TYPE_EDGE_RISING: + value |= BYT_TRIG_POS; + break; + case IRQ_TYPE_LEVEL_LOW: + value |= BYT_TRIG_LVL; + case IRQ_TYPE_EDGE_FALLING: + value |= BYT_TRIG_NEG; + break; + case IRQ_TYPE_EDGE_BOTH: + value |= (BYT_TRIG_NEG | BYT_TRIG_POS); + break; + } + writel(value, reg); + + spin_unlock_irqrestore(&vg->lock, flags); + + return 0; +} + +static int byt_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG); + return readl(reg) & BYT_LEVEL; +} + +static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip); + void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG); + unsigned long flags; + u32 old_val; + + spin_lock_irqsave(&vg->lock, flags); + + old_val = readl(reg); + + if (value) + writel(old_val | BYT_LEVEL, reg); + else + writel(old_val & ~BYT_LEVEL, reg); + + spin_unlock_irqrestore(&vg->lock, flags); +} + +static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip); + void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG); + unsigned long flags; + u32 value; + + spin_lock_irqsave(&vg->lock, flags); + + value = readl(reg) | BYT_DIR_MASK; + value = value & (~BYT_INPUT_EN); /* active low */ + writel(value, reg); + + spin_unlock_irqrestore(&vg->lock, flags); + + return 0; +} + +static int byt_gpio_direction_output(struct gpio_chip *chip, + unsigned gpio, int value) +{ + struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip); + void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG); + unsigned long flags; + u32 reg_val; + + spin_lock_irqsave(&vg->lock, flags); + + reg_val = readl(reg) | (BYT_DIR_MASK | !!value); + reg_val &= ~(BYT_OUTPUT_EN | !value); + writel(reg_val, reg); + + spin_unlock_irqrestore(&vg->lock, flags); + + return 0; +} + +static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip); + int i; + unsigned long flags; + u32 conf0, val, offs; + + spin_lock_irqsave(&vg->lock, flags); + + for (i = 0; i < vg->chip.ngpio; i++) { + offs = vg->range->pins[i] * 16; + conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG); + val = readl(vg->reg_base + offs + BYT_VAL_REG); + + seq_printf(s, + " gpio-%-3d %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s\n", + i, + val & BYT_INPUT_EN ? " " : "in", + val & BYT_OUTPUT_EN ? " " : "out", + val & BYT_LEVEL ? "hi" : "lo", + vg->range->pins[i], offs, + conf0 & 0x7, + conf0 & BYT_TRIG_NEG ? "fall " : "", + conf0 & BYT_TRIG_POS ? "rise " : "", + conf0 & BYT_TRIG_LVL ? "lvl " : ""); + } + spin_unlock_irqrestore(&vg->lock, flags); +} + +static int byt_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip); + return irq_create_mapping(vg->domain, offset); +} + +static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc) +{ + struct irq_data *data = irq_desc_get_irq_data(desc); + struct byt_gpio *vg = irq_data_get_irq_handler_data(data); + struct irq_chip *chip = irq_data_get_irq_chip(data); + u32 base, pin, mask; + void __iomem *reg; + u32 pending; + unsigned virq; + int looplimit = 0; + + /* check from GPIO controller which pin triggered the interrupt */ + for (base = 0; base < vg->chip.ngpio; base += 32) { + + reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG); + + while ((pending = readl(reg))) { + pin = __ffs(pending); + mask = BIT(pin); + /* Clear before handling so we can't lose an edge */ + writel(mask, reg); + + virq = irq_find_mapping(vg->domain, base + pin); + generic_handle_irq(virq); + + /* In case bios or user sets triggering incorretly a pin + * might remain in "interrupt triggered" state. + */ + if (looplimit++ > 32) { + dev_err(&vg->pdev->dev, + "Gpio %d interrupt flood, disabling\n", + base + pin); + + reg = byt_gpio_reg(&vg->chip, base + pin, + BYT_CONF0_REG); + mask = readl(reg); + mask &= ~(BYT_TRIG_NEG | BYT_TRIG_POS | + BYT_TRIG_LVL); + writel(mask, reg); + mask = readl(reg); /* flush */ + break; + } + } + } + chip->irq_eoi(data); +} + +static void byt_irq_unmask(struct irq_data *d) +{ +} + +static void byt_irq_mask(struct irq_data *d) +{ +} + +static struct irq_chip byt_irqchip = { + .name = "BYT-GPIO", + .irq_mask = byt_irq_mask, + .irq_unmask = byt_irq_unmask, + .irq_set_type = byt_irq_type, +}; + +static void byt_gpio_irq_init_hw(struct byt_gpio *vg) +{ + void __iomem *reg; + u32 base, value; + + /* clear interrupt status trigger registers */ + for (base = 0; base < vg->chip.ngpio; base += 32) { + reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG); + writel(0xffffffff, reg); + /* make sure trigger bits are cleared, if not then a pin + might be misconfigured in bios */ + value = readl(reg); + if (value) + dev_err(&vg->pdev->dev, + "GPIO interrupt error, pins misconfigured\n"); + } +} + +static int byt_gpio_irq_map(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hw) +{ + struct byt_gpio *vg = d->host_data; + + irq_set_chip_and_handler_name(virq, &byt_irqchip, handle_simple_irq, + "demux"); + irq_set_chip_data(virq, vg); + irq_set_irq_type(virq, IRQ_TYPE_NONE); + + return 0; +} + +static const struct irq_domain_ops byt_gpio_irq_ops = { + .map = byt_gpio_irq_map, +}; + +static int byt_gpio_probe(struct platform_device *pdev) +{ + struct byt_gpio *vg; + struct gpio_chip *gc; + struct resource *mem_rc, *irq_rc; + struct device *dev = &pdev->dev; + struct acpi_device *acpi_dev; + struct pinctrl_gpio_range *range; + acpi_handle handle = ACPI_HANDLE(dev); + unsigned hwirq; + int ret; + + if (acpi_bus_get_device(handle, &acpi_dev)) + return -ENODEV; + + vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL); + if (!vg) { + dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n"); + return -ENOMEM; + } + + for (range = byt_ranges; range->name; range++) { + if (!strcmp(acpi_dev->pnp.unique_id, range->name)) { + vg->chip.ngpio = range->npins; + vg->range = range; + break; + } + } + + if (!vg->chip.ngpio || !vg->range) + return -ENODEV; + + vg->pdev = pdev; + platform_set_drvdata(pdev, vg); + + mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0); + vg->reg_base = devm_ioremap_resource(dev, mem_rc); + if (IS_ERR(vg->reg_base)) + return PTR_ERR(vg->reg_base); + + spin_lock_init(&vg->lock); + + gc = &vg->chip; + gc->label = dev_name(&pdev->dev); + gc->owner = THIS_MODULE; + gc->request = byt_gpio_request; + gc->free = byt_gpio_free; + gc->direction_input = byt_gpio_direction_input; + gc->direction_output = byt_gpio_direction_output; + gc->get = byt_gpio_get; + gc->set = byt_gpio_set; + gc->dbg_show = byt_gpio_dbg_show; + gc->base = -1; + gc->can_sleep = 0; + gc->dev = dev; + + ret = gpiochip_add(gc); + if (ret) { + dev_err(&pdev->dev, "failed adding byt-gpio chip\n"); + return ret; + } + + /* set up interrupts */ + irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (irq_rc && irq_rc->start) { + hwirq = irq_rc->start; + gc->to_irq = byt_gpio_to_irq; + + vg->domain = irq_domain_add_linear(NULL, gc->ngpio, + &byt_gpio_irq_ops, vg); + if (!vg->domain) + return -ENXIO; + + byt_gpio_irq_init_hw(vg); + + irq_set_handler_data(hwirq, vg); + irq_set_chained_handler(hwirq, byt_gpio_irq_handler); + + /* Register interrupt handlers for gpio signaled acpi events */ + acpi_gpiochip_request_interrupts(gc); + } + + pm_runtime_enable(dev); + + return 0; +} + +static int byt_gpio_runtime_suspend(struct device *dev) +{ + return 0; +} + +static int byt_gpio_runtime_resume(struct device *dev) +{ + return 0; +} + +static const struct dev_pm_ops byt_gpio_pm_ops = { + .runtime_suspend = byt_gpio_runtime_suspend, + .runtime_resume = byt_gpio_runtime_resume, +}; + +static const struct acpi_device_id byt_gpio_acpi_match[] = { + { "INT33B2", 0 }, + { } +}; +MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match); + +static int byt_gpio_remove(struct platform_device *pdev) +{ + struct byt_gpio *vg = platform_get_drvdata(pdev); + int err; + pm_runtime_disable(&pdev->dev); + err = gpiochip_remove(&vg->chip); + if (err) + dev_warn(&pdev->dev, "failed to remove gpio_chip.\n"); + + return 0; +} + +static struct platform_driver byt_gpio_driver = { + .probe = byt_gpio_probe, + .remove = byt_gpio_remove, + .driver = { + .name = "byt_gpio", + .owner = THIS_MODULE, + .pm = &byt_gpio_pm_ops, + .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match), + }, +}; + +static int __init byt_gpio_init(void) +{ + return platform_driver_register(&byt_gpio_driver); +} + +subsys_initcall(byt_gpio_init); diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/pinctrl-bcm2835.c index c8f20a3d8f8..a1c88b30f71 100644 --- a/drivers/pinctrl/pinctrl-bcm2835.c +++ b/drivers/pinctrl/pinctrl-bcm2835.c @@ -113,7 +113,7 @@ static struct lock_class_key gpio_lock_class; /* pins are just named GPIO0..GPIO53 */ #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a) -struct pinctrl_pin_desc bcm2835_gpio_pins[] = { +static struct pinctrl_pin_desc bcm2835_gpio_pins[] = { BCM2835_GPIO_PIN(0), BCM2835_GPIO_PIN(1), BCM2835_GPIO_PIN(2), diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c index d6b41747d68..f22a2193d94 100644 --- a/drivers/pinctrl/pinctrl-coh901.c +++ b/drivers/pinctrl/pinctrl-coh901.c @@ -22,7 +22,6 @@ #include <linux/slab.h> #include <linux/pinctrl/consumer.h> #include <linux/pinctrl/pinconf-generic.h> -#include <linux/platform_data/pinctrl-coh901.h> #include "pinctrl-coh901.h" #define U300_GPIO_PORT_STRIDE (0x30) @@ -58,8 +57,9 @@ #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL) /* 8 bits per port, no version has more than 7 ports */ +#define U300_GPIO_NUM_PORTS 7 #define U300_GPIO_PINS_PER_PORT 8 -#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7) +#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS) struct u300_gpio { struct gpio_chip chip; @@ -111,9 +111,6 @@ struct u300_gpio_confdata { int outval; }; -/* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */ -#define BS335_GPIO_NUM_PORTS 7 - #define U300_FLOATING_INPUT { \ .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \ .output = false, \ @@ -136,7 +133,7 @@ struct u300_gpio_confdata { /* Initial configuration */ static const struct __initconst u300_gpio_confdata -bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { +bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { /* Port 0, pins 0-7 */ { U300_FLOATING_INPUT, @@ -630,13 +627,12 @@ static void __init u300_gpio_init_pin(struct u300_gpio *gpio, } } -static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio, - struct u300_gpio_platform *plat) +static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio) { int i, j; /* Write default config and values to all pins */ - for (i = 0; i < plat->ports; i++) { + for (i = 0; i < U300_GPIO_NUM_PORTS; i++) { for (j = 0; j < 8; j++) { const struct u300_gpio_confdata *conf; int offset = (i*8) + j; @@ -693,7 +689,6 @@ static struct coh901_pinpair coh901_pintable[] = { static int __init u300_gpio_probe(struct platform_device *pdev) { - struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev); struct u300_gpio *gpio; struct resource *memres; int err = 0; @@ -707,9 +702,9 @@ static int __init u300_gpio_probe(struct platform_device *pdev) return -ENOMEM; gpio->chip = u300_gpio_chip; - gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT; + gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT; gpio->chip.dev = &pdev->dev; - gpio->chip.base = plat->gpio_base; + gpio->chip.base = 0; gpio->dev = &pdev->dev; memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -750,11 +745,11 @@ static int __init u300_gpio_probe(struct platform_device *pdev) ((val & 0x0000FE00) >> 9) * 8); writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, gpio->base + U300_GPIO_CR); - u300_gpio_init_coh901571(gpio, plat); + u300_gpio_init_coh901571(gpio); /* Add each port with its IRQ separately */ INIT_LIST_HEAD(&gpio->port_list); - for (portno = 0 ; portno < plat->ports; portno++) { + for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) { struct u300_gpio_port *port = kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL); @@ -768,8 +763,7 @@ static int __init u300_gpio_probe(struct platform_device *pdev) port->number = portno; port->gpio = gpio; - port->irq = platform_get_irq_byname(pdev, - port->name); + port->irq = platform_get_irq(pdev, portno); dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq, port->name); @@ -806,6 +800,9 @@ static int __init u300_gpio_probe(struct platform_device *pdev) } dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno); +#ifdef CONFIG_OF_GPIO + gpio->chip.of_node = pdev->dev.of_node; +#endif err = gpiochip_add(&gpio->chip); if (err) { dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); @@ -856,13 +853,18 @@ static int __exit u300_gpio_remove(struct platform_device *pdev) } u300_gpio_free_ports(gpio); clk_disable_unprepare(gpio->clk); - platform_set_drvdata(pdev, NULL); return 0; } +static const struct of_device_id u300_gpio_match[] = { + { .compatible = "stericsson,gpio-coh901" }, + {}, +}; + static struct platform_driver u300_gpio_driver = { .driver = { .name = "u300-gpio", + .of_match_table = u300_gpio_match, }, .remove = __exit_p(u300_gpio_remove), }; diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c index 2d76f66a2e0..a74b3cbd745 100644 --- a/drivers/pinctrl/pinctrl-exynos.c +++ b/drivers/pinctrl/pinctrl-exynos.c @@ -50,37 +50,58 @@ static const struct of_device_id exynos_wkup_irq_ids[] = { { } }; -static void exynos_gpio_irq_unmask(struct irq_data *irqd) +static void exynos_gpio_irq_mask(struct irq_data *irqd) { struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); struct samsung_pinctrl_drv_data *d = bank->drvdata; unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; unsigned long mask; + unsigned long flags; + + spin_lock_irqsave(&bank->slock, flags); mask = readl(d->virt_base + reg_mask); - mask &= ~(1 << irqd->hwirq); + mask |= 1 << irqd->hwirq; writel(mask, d->virt_base + reg_mask); + + spin_unlock_irqrestore(&bank->slock, flags); } -static void exynos_gpio_irq_mask(struct irq_data *irqd) +static void exynos_gpio_irq_ack(struct irq_data *irqd) { struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; - unsigned long mask; + unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset; - mask = readl(d->virt_base + reg_mask); - mask |= 1 << irqd->hwirq; - writel(mask, d->virt_base + reg_mask); + writel(1 << irqd->hwirq, d->virt_base + reg_pend); } -static void exynos_gpio_irq_ack(struct irq_data *irqd) +static void exynos_gpio_irq_unmask(struct irq_data *irqd) { struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset; + unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; + unsigned long mask; + unsigned long flags; - writel(1 << irqd->hwirq, d->virt_base + reg_pend); + /* + * Ack level interrupts right before unmask + * + * If we don't do this we'll get a double-interrupt. Level triggered + * interrupts must not fire an interrupt if the level is not + * _currently_ active, even if it was active while the interrupt was + * masked. + */ + if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) + exynos_gpio_irq_ack(irqd); + + spin_lock_irqsave(&bank->slock, flags); + + mask = readl(d->virt_base + reg_mask); + mask &= ~(1 << irqd->hwirq); + writel(mask, d->virt_base + reg_mask); + + spin_unlock_irqrestore(&bank->slock, flags); } static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) @@ -258,37 +279,58 @@ err_domains: return ret; } -static void exynos_wkup_irq_unmask(struct irq_data *irqd) +static void exynos_wkup_irq_mask(struct irq_data *irqd) { struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); struct samsung_pinctrl_drv_data *d = b->drvdata; unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset; unsigned long mask; + unsigned long flags; + + spin_lock_irqsave(&b->slock, flags); mask = readl(d->virt_base + reg_mask); - mask &= ~(1 << irqd->hwirq); + mask |= 1 << irqd->hwirq; writel(mask, d->virt_base + reg_mask); + + spin_unlock_irqrestore(&b->slock, flags); } -static void exynos_wkup_irq_mask(struct irq_data *irqd) +static void exynos_wkup_irq_ack(struct irq_data *irqd) { struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); struct samsung_pinctrl_drv_data *d = b->drvdata; - unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset; - unsigned long mask; + unsigned long pend = d->ctrl->weint_pend + b->eint_offset; - mask = readl(d->virt_base + reg_mask); - mask |= 1 << irqd->hwirq; - writel(mask, d->virt_base + reg_mask); + writel(1 << irqd->hwirq, d->virt_base + pend); } -static void exynos_wkup_irq_ack(struct irq_data *irqd) +static void exynos_wkup_irq_unmask(struct irq_data *irqd) { struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); struct samsung_pinctrl_drv_data *d = b->drvdata; - unsigned long pend = d->ctrl->weint_pend + b->eint_offset; + unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset; + unsigned long mask; + unsigned long flags; - writel(1 << irqd->hwirq, d->virt_base + pend); + /* + * Ack level interrupts right before unmask + * + * If we don't do this we'll get a double-interrupt. Level triggered + * interrupts must not fire an interrupt if the level is not + * _currently_ active, even if it was active while the interrupt was + * masked. + */ + if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) + exynos_wkup_irq_ack(irqd); + + spin_lock_irqsave(&b->slock, flags); + + mask = readl(d->virt_base + reg_mask); + mask &= ~(1 << irqd->hwirq); + writel(mask, d->virt_base + reg_mask); + + spin_unlock_irqrestore(&b->slock, flags); } static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type) @@ -941,3 +983,121 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { .label = "exynos5250-gpio-ctrl3", }, }; + +/* pin banks of exynos5420 pin-controller 0 */ +static struct samsung_pin_bank exynos5420_pin_banks0[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5420 pin-controller 1 */ +static struct samsung_pin_bank exynos5420_pin_banks1[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04), + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14), + EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"), +}; + +/* pin banks of exynos5420 pin-controller 2 */ +static struct samsung_pin_bank exynos5420_pin_banks2[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), + EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), + EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), + EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), + EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c), +}; + +/* pin banks of exynos5420 pin-controller 3 */ +static struct samsung_pin_bank exynos5420_pin_banks3[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20), +}; + +/* pin banks of exynos5420 pin-controller 4 */ +static struct samsung_pin_bank exynos5420_pin_banks4[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), +}; + +/* + * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +struct samsung_pin_ctrl exynos5420_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5420_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .weint_con = EXYNOS_WKUP_ECON_OFFSET, + .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, + .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .label = "exynos5420-gpio-ctrl0", + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5420_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5420-gpio-ctrl1", + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5420_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5420-gpio-ctrl2", + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos5420_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5420-gpio-ctrl3", + }, { + /* pin-controller instance 4 data */ + .pin_banks = exynos5420_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5420-gpio-ctrl4", + }, +}; diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/pinctrl-exynos5440.c index 32a48f44f57..3b283fd898f 100644 --- a/drivers/pinctrl/pinctrl-exynos5440.c +++ b/drivers/pinctrl/pinctrl-exynos5440.c @@ -220,7 +220,7 @@ static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev, dev_err(dev, "failed to alloc memory for group name\n"); goto free_map; } - sprintf(gname, "%s%s", np->name, GROUP_SUFFIX); + snprintf(gname, strlen(np->name) + 4, "%s%s", np->name, GROUP_SUFFIX); /* * don't have config options? then skip over to creating function @@ -259,7 +259,8 @@ skip_cfgs: dev_err(dev, "failed to alloc memory for func name\n"); goto free_cfg; } - sprintf(fname, "%s%s", np->name, FUNCTION_SUFFIX); + snprintf(fname, strlen(np->name) + 4, "%s%s", np->name, + FUNCTION_SUFFIX); map[*nmaps].data.mux.group = gname; map[*nmaps].data.mux.function = fname; @@ -713,7 +714,8 @@ static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev, dev_err(dev, "failed to alloc memory for group name\n"); return -ENOMEM; } - sprintf(gname, "%s%s", cfg_np->name, GROUP_SUFFIX); + snprintf(gname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name, + GROUP_SUFFIX); grp->name = gname; grp->pins = pin_list; @@ -733,7 +735,8 @@ skip_to_pin_function: dev_err(dev, "failed to alloc memory for func name\n"); return -ENOMEM; } - sprintf(fname, "%s%s", cfg_np->name, FUNCTION_SUFFIX); + snprintf(fname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name, + FUNCTION_SUFFIX); func->name = fname; func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); @@ -806,7 +809,7 @@ static int exynos5440_pinctrl_register(struct platform_device *pdev, /* for each pin, set the name of the pin */ for (pin = 0; pin < ctrldesc->npins; pin++) { - sprintf(pin_names, "gpio%02d", pin); + snprintf(pin_names, 6, "gpio%02d", pin); pdesc = pindesc + pin; pdesc->name = pin_names; pin_names += PIN_NAME_LENGTH; diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c index 4fcfff9243b..57a4eb0add2 100644 --- a/drivers/pinctrl/pinctrl-imx.c +++ b/drivers/pinctrl/pinctrl-imx.c @@ -221,13 +221,21 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, pin_id = pins[i]; pin_reg = &info->pin_regs[pin_id]; - if (!pin_reg->mux_reg) { + if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) { dev_err(ipctl->dev, "Pin(%s) does not support mux function\n", info->pins[pin_id].name); return -EINVAL; } - writel(mux[i], ipctl->base + pin_reg->mux_reg); + if (info->flags & SHARE_MUX_CONF_REG) { + u32 reg; + reg = readl(ipctl->base + pin_reg->mux_reg); + reg &= ~(0x7 << 20); + reg |= (mux[i] << 20); + writel(reg, ipctl->base + pin_reg->mux_reg); + } else { + writel(mux[i], ipctl->base + pin_reg->mux_reg); + } dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", pin_reg->mux_reg, mux[i]); @@ -287,7 +295,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev, const struct imx_pinctrl_soc_info *info = ipctl->info; const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; - if (!pin_reg->conf_reg) { + if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) { dev_err(info->dev, "Pin(%s) does not support config function\n", info->pins[pin_id].name); return -EINVAL; @@ -295,6 +303,9 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev, *config = readl(ipctl->base + pin_reg->conf_reg); + if (info->flags & SHARE_MUX_CONF_REG) + *config &= 0xffff; + return 0; } @@ -305,7 +316,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev, const struct imx_pinctrl_soc_info *info = ipctl->info; const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; - if (!pin_reg->conf_reg) { + if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) { dev_err(info->dev, "Pin(%s) does not support config function\n", info->pins[pin_id].name); return -EINVAL; @@ -314,7 +325,15 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev, dev_dbg(ipctl->dev, "pinconf set pin %s\n", info->pins[pin_id].name); - writel(config, ipctl->base + pin_reg->conf_reg); + if (info->flags & SHARE_MUX_CONF_REG) { + u32 reg; + reg = readl(ipctl->base + pin_reg->conf_reg); + reg &= ~0xffff; + reg |= config; + writel(reg, ipctl->base + pin_reg->conf_reg); + } else { + writel(config, ipctl->base + pin_reg->conf_reg); + } dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", pin_reg->conf_reg, config); @@ -381,19 +400,24 @@ static struct pinctrl_desc imx_pinctrl_desc = { * 1 u32 CONFIG, so 24 types in total for each pin. */ #define FSL_PIN_SIZE 24 +#define SHARE_FSL_PIN_SIZE 20 static int imx_pinctrl_parse_groups(struct device_node *np, struct imx_pin_group *grp, struct imx_pinctrl_soc_info *info, u32 index) { - int size; + int size, pin_size; const __be32 *list; int i; u32 config; dev_dbg(info->dev, "group(%d): %s\n", index, np->name); + if (info->flags & SHARE_MUX_CONF_REG) + pin_size = SHARE_FSL_PIN_SIZE; + else + pin_size = FSL_PIN_SIZE; /* Initialise group */ grp->name = np->name; @@ -403,12 +427,12 @@ static int imx_pinctrl_parse_groups(struct device_node *np, */ list = of_get_property(np, "fsl,pins", &size); /* we do not check return since it's safe node passed down */ - if (!size || size % FSL_PIN_SIZE) { + if (!size || size % pin_size) { dev_err(info->dev, "Invalid fsl,pins property\n"); return -EINVAL; } - grp->npins = size / FSL_PIN_SIZE; + grp->npins = size / pin_size; grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), GFP_KERNEL); grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), @@ -421,10 +445,17 @@ static int imx_pinctrl_parse_groups(struct device_node *np, GFP_KERNEL); for (i = 0; i < grp->npins; i++) { u32 mux_reg = be32_to_cpu(*list++); - u32 conf_reg = be32_to_cpu(*list++); - unsigned int pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4; - struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; + u32 conf_reg; + unsigned int pin_id; + struct imx_pin_reg *pin_reg; + if (info->flags & SHARE_MUX_CONF_REG) + conf_reg = mux_reg; + else + conf_reg = be32_to_cpu(*list++); + + pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4; + pin_reg = &info->pin_regs[pin_id]; grp->pins[i] = pin_id; pin_reg->mux_reg = mux_reg; pin_reg->conf_reg = conf_reg; diff --git a/drivers/pinctrl/pinctrl-imx.h b/drivers/pinctrl/pinctrl-imx.h index 607ef549755..bcedd991c9f 100644 --- a/drivers/pinctrl/pinctrl-imx.h +++ b/drivers/pinctrl/pinctrl-imx.h @@ -74,8 +74,12 @@ struct imx_pinctrl_soc_info { unsigned int ngroups; struct imx_pmx_func *functions; unsigned int nfunctions; + unsigned int flags; }; +#define ZERO_OFFSET_VALID 0x1 +#define SHARE_MUX_CONF_REG 0x2 + #define NO_MUX 0x0 #define NO_PAD 0x0 diff --git a/drivers/pinctrl/pinctrl-mxs.c b/drivers/pinctrl/pinctrl-mxs.c index b45c4eb3579..f5d56436ba7 100644 --- a/drivers/pinctrl/pinctrl-mxs.c +++ b/drivers/pinctrl/pinctrl-mxs.c @@ -515,7 +515,6 @@ int mxs_pinctrl_probe(struct platform_device *pdev, return 0; err: - platform_set_drvdata(pdev, NULL); iounmap(d->base); return ret; } @@ -525,7 +524,6 @@ int mxs_pinctrl_remove(struct platform_device *pdev) { struct mxs_pinctrl_data *d = platform_get_drvdata(pdev); - platform_set_drvdata(pdev, NULL); pinctrl_unregister(d->pctl); iounmap(d->base); diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c index 34281754b62..4a1cfdce223 100644 --- a/drivers/pinctrl/pinctrl-nomadik.c +++ b/drivers/pinctrl/pinctrl-nomadik.c @@ -1309,7 +1309,7 @@ static int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq, return 0; } -const struct irq_domain_ops nmk_gpio_irq_simple_ops = { +static const struct irq_domain_ops nmk_gpio_irq_simple_ops = { .map = nmk_gpio_irq_map, .xlate = irq_domain_xlate_twocell, }; @@ -1681,7 +1681,7 @@ static bool nmk_pinctrl_dt_get_config(struct device_node *np, return has_config; } -int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, +static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **map, unsigned *reserved_maps, @@ -1740,7 +1740,7 @@ exit: return ret; } -int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, +static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np_config, struct pinctrl_map **map, unsigned *num_maps) { @@ -2104,15 +2104,15 @@ static struct pinctrl_desc nmk_pinctrl_desc = { static const struct of_device_id nmk_pinctrl_match[] = { { - .compatible = "stericsson,nmk-pinctrl-stn8815", + .compatible = "stericsson,stn8815-pinctrl", .data = (void *)PINCTRL_NMK_STN8815, }, { - .compatible = "stericsson,nmk-pinctrl", + .compatible = "stericsson,db8500-pinctrl", .data = (void *)PINCTRL_NMK_DB8500, }, { - .compatible = "stericsson,nmk-pinctrl-db8540", + .compatible = "stericsson,db8540-pinctrl", .data = (void *)PINCTRL_NMK_DB8540, }, {}, diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c new file mode 100644 index 00000000000..1eb5a2e43b0 --- /dev/null +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -0,0 +1,1394 @@ +/* + * Pinctrl driver for Rockchip SoCs + * + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * With some ideas taken from pinctrl-samsung: + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2012 Linaro Ltd + * http://www.linaro.org + * + * and pinctrl-at91: + * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/bitops.h> +#include <linux/gpio.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/irqchip/chained_irq.h> +#include <linux/clk-provider.h> +#include <dt-bindings/pinctrl/rockchip.h> + +#include "core.h" +#include "pinconf.h" + +/* GPIO control registers */ +#define GPIO_SWPORT_DR 0x00 +#define GPIO_SWPORT_DDR 0x04 +#define GPIO_INTEN 0x30 +#define GPIO_INTMASK 0x34 +#define GPIO_INTTYPE_LEVEL 0x38 +#define GPIO_INT_POLARITY 0x3c +#define GPIO_INT_STATUS 0x40 +#define GPIO_INT_RAWSTATUS 0x44 +#define GPIO_DEBOUNCE 0x48 +#define GPIO_PORTS_EOI 0x4c +#define GPIO_EXT_PORT 0x50 +#define GPIO_LS_SYNC 0x60 + +/** + * @reg_base: register base of the gpio bank + * @clk: clock of the gpio bank + * @irq: interrupt of the gpio bank + * @pin_base: first pin number + * @nr_pins: number of pins in this bank + * @name: name of the bank + * @bank_num: number of the bank, to account for holes + * @valid: are all necessary informations present + * @of_node: dt node of this bank + * @drvdata: common pinctrl basedata + * @domain: irqdomain of the gpio bank + * @gpio_chip: gpiolib chip + * @grange: gpio range + * @slock: spinlock for the gpio bank + */ +struct rockchip_pin_bank { + void __iomem *reg_base; + struct clk *clk; + int irq; + u32 pin_base; + u8 nr_pins; + char *name; + u8 bank_num; + bool valid; + struct device_node *of_node; + struct rockchip_pinctrl *drvdata; + struct irq_domain *domain; + struct gpio_chip gpio_chip; + struct pinctrl_gpio_range grange; + spinlock_t slock; + +}; + +#define PIN_BANK(id, pins, label) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + } + +/** + * @pull_auto: some SoCs don't allow pulls to be specified as up or down, but + * instead decide this automatically based on the pad-type. + */ +struct rockchip_pin_ctrl { + struct rockchip_pin_bank *pin_banks; + u32 nr_banks; + u32 nr_pins; + char *label; + int mux_offset; + int pull_offset; + bool pull_auto; + int pull_bank_stride; +}; + +struct rockchip_pin_config { + unsigned int func; + unsigned long *configs; + unsigned int nconfigs; +}; + +/** + * struct rockchip_pin_group: represent group of pins of a pinmux function. + * @name: name of the pin group, used to lookup the group. + * @pins: the pins included in this group. + * @npins: number of pins included in this group. + * @func: the mux function number to be programmed when selected. + * @configs: the config values to be set for each pin + * @nconfigs: number of configs for each pin + */ +struct rockchip_pin_group { + const char *name; + unsigned int npins; + unsigned int *pins; + struct rockchip_pin_config *data; +}; + +/** + * struct rockchip_pmx_func: represent a pin function. + * @name: name of the pin function, used to lookup the function. + * @groups: one or more names of pin groups that provide this function. + * @num_groups: number of groups included in @groups. + */ +struct rockchip_pmx_func { + const char *name; + const char **groups; + u8 ngroups; +}; + +struct rockchip_pinctrl { + void __iomem *reg_base; + struct device *dev; + struct rockchip_pin_ctrl *ctrl; + struct pinctrl_desc pctl; + struct pinctrl_dev *pctl_dev; + struct rockchip_pin_group *groups; + unsigned int ngroups; + struct rockchip_pmx_func *functions; + unsigned int nfunctions; +}; + +static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc) +{ + return container_of(gc, struct rockchip_pin_bank, gpio_chip); +} + +static const inline struct rockchip_pin_group *pinctrl_name_to_group( + const struct rockchip_pinctrl *info, + const char *name) +{ + const struct rockchip_pin_group *grp = NULL; + int i; + + for (i = 0; i < info->ngroups; i++) { + if (strcmp(info->groups[i].name, name)) + continue; + + grp = &info->groups[i]; + break; + } + + return grp; +} + +/* + * given a pin number that is local to a pin controller, find out the pin bank + * and the register base of the pin bank. + */ +static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, + unsigned pin) +{ + struct rockchip_pin_bank *b = info->ctrl->pin_banks; + + while ((pin >= b->pin_base) && + ((b->pin_base + b->nr_pins - 1) < pin)) + b++; + + return b; +} + +static struct rockchip_pin_bank *bank_num_to_bank( + struct rockchip_pinctrl *info, + unsigned num) +{ + struct rockchip_pin_bank *b = info->ctrl->pin_banks; + int i; + + for (i = 0; i < info->ctrl->nr_banks; i++) { + if (b->bank_num == num) + break; + + b++; + } + + if (b->bank_num != num) + return ERR_PTR(-EINVAL); + + return b; +} + +/* + * Pinctrl_ops handling + */ + +static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->ngroups; +} + +static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->groups[selector].name; +} + +static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, + unsigned selector, const unsigned **pins, + unsigned *npins) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + if (selector >= info->ngroups) + return -EINVAL; + + *pins = info->groups[selector].pins; + *npins = info->groups[selector].npins; + + return 0; +} + +static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, unsigned *num_maps) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + const struct rockchip_pin_group *grp; + struct pinctrl_map *new_map; + struct device_node *parent; + int map_num = 1; + int i; + + /* + * first find the group of this node and check if we need to create + * config maps for pins + */ + grp = pinctrl_name_to_group(info, np->name); + if (!grp) { + dev_err(info->dev, "unable to find group for node %s\n", + np->name); + return -EINVAL; + } + + map_num += grp->npins; + new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, + GFP_KERNEL); + if (!new_map) + return -ENOMEM; + + *map = new_map; + *num_maps = map_num; + + /* create mux map */ + parent = of_get_parent(np); + if (!parent) { + devm_kfree(pctldev->dev, new_map); + return -EINVAL; + } + new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; + new_map[0].data.mux.function = parent->name; + new_map[0].data.mux.group = np->name; + of_node_put(parent); + + /* create config map */ + new_map++; + for (i = 0; i < grp->npins; i++) { + new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; + new_map[i].data.configs.group_or_pin = + pin_get_name(pctldev, grp->pins[i]); + new_map[i].data.configs.configs = grp->data[i].configs; + new_map[i].data.configs.num_configs = grp->data[i].nconfigs; + } + + dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", + (*map)->data.mux.function, (*map)->data.mux.group, map_num); + + return 0; +} + +static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ +} + +static const struct pinctrl_ops rockchip_pctrl_ops = { + .get_groups_count = rockchip_get_groups_count, + .get_group_name = rockchip_get_group_name, + .get_group_pins = rockchip_get_group_pins, + .dt_node_to_map = rockchip_dt_node_to_map, + .dt_free_map = rockchip_dt_free_map, +}; + +/* + * Hardware access + */ + +/* + * Set a new mux function for a pin. + * + * The register is divided into the upper and lower 16 bit. When changing + * a value, the previous register value is not read and changed. Instead + * it seems the changed bits are marked in the upper 16 bit, while the + * changed value gets set in the same offset in the lower 16 bit. + * All pin settings seem to be 2 bit wide in both the upper and lower + * parts. + * @bank: pin bank to change + * @pin: pin to change + * @mux: new mux function to set + */ +static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl *info = bank->drvdata; + void __iomem *reg = info->reg_base + info->ctrl->mux_offset; + unsigned long flags; + u8 bit; + u32 data; + + dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", + bank->bank_num, pin, mux); + + /* get basic quadrupel of mux registers and the correct reg inside */ + reg += bank->bank_num * 0x10; + reg += (pin / 8) * 4; + bit = (pin % 8) * 2; + + spin_lock_irqsave(&bank->slock, flags); + + data = (3 << (bit + 16)); + data |= (mux & 3) << bit; + writel(data, reg); + + spin_unlock_irqrestore(&bank->slock, flags); +} + +static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) +{ + struct rockchip_pinctrl *info = bank->drvdata; + struct rockchip_pin_ctrl *ctrl = info->ctrl; + void __iomem *reg; + u8 bit; + + /* rk3066b does support any pulls */ + if (!ctrl->pull_offset) + return PIN_CONFIG_BIAS_DISABLE; + + reg = info->reg_base + ctrl->pull_offset; + + if (ctrl->pull_auto) { + reg += bank->bank_num * ctrl->pull_bank_stride; + reg += (pin_num / 16) * 4; + bit = pin_num % 16; + + return !(readl_relaxed(reg) & BIT(bit)) + ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT + : PIN_CONFIG_BIAS_DISABLE; + } else { + dev_err(info->dev, "pull support for rk31xx not implemented\n"); + return -EIO; + } +} + +static int rockchip_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct rockchip_pinctrl *info = bank->drvdata; + struct rockchip_pin_ctrl *ctrl = info->ctrl; + void __iomem *reg; + unsigned long flags; + u8 bit; + u32 data; + + dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", + bank->bank_num, pin_num, pull); + + /* rk3066b does support any pulls */ + if (!ctrl->pull_offset) + return pull ? -EINVAL : 0; + + reg = info->reg_base + ctrl->pull_offset; + + if (ctrl->pull_auto) { + if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT && + pull != PIN_CONFIG_BIAS_DISABLE) { + dev_err(info->dev, "only PIN_DEFAULT and DISABLE allowed\n"); + return -EINVAL; + } + + reg += bank->bank_num * ctrl->pull_bank_stride; + reg += (pin_num / 16) * 4; + bit = pin_num % 16; + + spin_lock_irqsave(&bank->slock, flags); + + data = BIT(bit + 16); + if (pull == PIN_CONFIG_BIAS_DISABLE) + data |= BIT(bit); + writel(data, reg); + + spin_unlock_irqrestore(&bank->slock, flags); + } else { + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) { + dev_err(info->dev, "pull direction (up/down) needs to be specified\n"); + return -EINVAL; + } + + dev_err(info->dev, "pull support for rk31xx not implemented\n"); + return -EIO; + } + + return 0; +} + +/* + * Pinmux_ops handling + */ + +static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->nfunctions; +} + +static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->functions[selector].name; +} + +static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, + unsigned selector, const char * const **groups, + unsigned * const num_groups) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + *groups = info->functions[selector].groups; + *num_groups = info->functions[selector].ngroups; + + return 0; +} + +static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + const unsigned int *pins = info->groups[group].pins; + const struct rockchip_pin_config *data = info->groups[group].data; + struct rockchip_pin_bank *bank; + int cnt; + + dev_dbg(info->dev, "enable function %s group %s\n", + info->functions[selector].name, info->groups[group].name); + + /* + * for each pin in the pin group selected, program the correspoding pin + * pin function number in the config register. + */ + for (cnt = 0; cnt < info->groups[group].npins; cnt++) { + bank = pin_to_bank(info, pins[cnt]); + rockchip_set_mux(bank, pins[cnt] - bank->pin_base, + data[cnt].func); + } + + return 0; +} + +static void rockchip_pmx_disable(struct pinctrl_dev *pctldev, + unsigned selector, unsigned group) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + const unsigned int *pins = info->groups[group].pins; + struct rockchip_pin_bank *bank; + int cnt; + + dev_dbg(info->dev, "disable function %s group %s\n", + info->functions[selector].name, info->groups[group].name); + + for (cnt = 0; cnt < info->groups[group].npins; cnt++) { + bank = pin_to_bank(info, pins[cnt]); + rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); + } +} + +/* + * The calls to gpio_direction_output() and gpio_direction_input() + * leads to this function call (via the pinctrl_gpio_direction_{input|output}() + * function called from the gpiolib interface). + */ +static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset, bool input) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct rockchip_pin_bank *bank; + struct gpio_chip *chip; + int pin; + u32 data; + + chip = range->gc; + bank = gc_to_pin_bank(chip); + pin = offset - chip->base; + + dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", + offset, range->name, pin, input ? "input" : "output"); + + rockchip_set_mux(bank, pin, RK_FUNC_GPIO); + + data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); + /* set bit to 1 for output, 0 for input */ + if (!input) + data |= BIT(pin); + else + data &= ~BIT(pin); + writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); + + return 0; +} + +static const struct pinmux_ops rockchip_pmx_ops = { + .get_functions_count = rockchip_pmx_get_funcs_count, + .get_function_name = rockchip_pmx_get_func_name, + .get_function_groups = rockchip_pmx_get_groups, + .enable = rockchip_pmx_enable, + .disable = rockchip_pmx_disable, + .gpio_set_direction = rockchip_pmx_gpio_set_direction, +}; + +/* + * Pinconf_ops handling + */ + +static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, + enum pin_config_param pull) +{ + /* rk3066b does support any pulls */ + if (!ctrl->pull_offset) + return pull ? false : true; + + if (ctrl->pull_auto) { + if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT && + pull != PIN_CONFIG_BIAS_DISABLE) + return false; + } else { + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return false; + } + + return true; +} + +/* set the pin config settings for a specified pin */ +static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long config) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct rockchip_pin_bank *bank = pin_to_bank(info, pin); + enum pin_config_param param = pinconf_to_config_param(config); + u16 arg = pinconf_to_config_argument(config); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + return rockchip_set_pull(bank, pin - bank->pin_base, param); + break; + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + if (!rockchip_pinconf_pull_valid(info->ctrl, param)) + return -ENOTSUPP; + + if (!arg) + return -EINVAL; + + return rockchip_set_pull(bank, pin - bank->pin_base, param); + break; + default: + return -ENOTSUPP; + break; + } + + return 0; +} + +/* get the pin config settings for a specified pin */ +static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct rockchip_pin_bank *bank = pin_to_bank(info, pin); + enum pin_config_param param = pinconf_to_config_param(*config); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (rockchip_get_pull(bank, pin - bank->pin_base) != param) + return -EINVAL; + + *config = 0; + break; + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + if (!rockchip_pinconf_pull_valid(info->ctrl, param)) + return -ENOTSUPP; + + if (rockchip_get_pull(bank, pin - bank->pin_base) != param) + return -EINVAL; + + *config = 1; + break; + default: + return -ENOTSUPP; + break; + } + + return 0; +} + +static const struct pinconf_ops rockchip_pinconf_ops = { + .pin_config_get = rockchip_pinconf_get, + .pin_config_set = rockchip_pinconf_set, +}; + +static const char *gpio_compat = "rockchip,gpio-bank"; + +static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, + struct device_node *np) +{ + struct device_node *child; + + for_each_child_of_node(np, child) { + if (of_device_is_compatible(child, gpio_compat)) + continue; + + info->nfunctions++; + info->ngroups += of_get_child_count(child); + } +} + +static int rockchip_pinctrl_parse_groups(struct device_node *np, + struct rockchip_pin_group *grp, + struct rockchip_pinctrl *info, + u32 index) +{ + struct rockchip_pin_bank *bank; + int size; + const __be32 *list; + int num; + int i, j; + int ret; + + dev_dbg(info->dev, "group(%d): %s\n", index, np->name); + + /* Initialise group */ + grp->name = np->name; + + /* + * the binding format is rockchip,pins = <bank pin mux CONFIG>, + * do sanity check and calculate pins number + */ + list = of_get_property(np, "rockchip,pins", &size); + /* we do not check return since it's safe node passed down */ + size /= sizeof(*list); + if (!size || size % 4) { + dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); + return -EINVAL; + } + + grp->npins = size / 4; + + grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), + GFP_KERNEL); + grp->data = devm_kzalloc(info->dev, grp->npins * + sizeof(struct rockchip_pin_config), + GFP_KERNEL); + if (!grp->pins || !grp->data) + return -ENOMEM; + + for (i = 0, j = 0; i < size; i += 4, j++) { + const __be32 *phandle; + struct device_node *np_config; + + num = be32_to_cpu(*list++); + bank = bank_num_to_bank(info, num); + if (IS_ERR(bank)) + return PTR_ERR(bank); + + grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); + grp->data[j].func = be32_to_cpu(*list++); + + phandle = list++; + if (!phandle) + return -EINVAL; + + np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); + ret = pinconf_generic_parse_dt_config(np_config, + &grp->data[j].configs, &grp->data[j].nconfigs); + if (ret) + return ret; + } + + return 0; +} + +static int rockchip_pinctrl_parse_functions(struct device_node *np, + struct rockchip_pinctrl *info, + u32 index) +{ + struct device_node *child; + struct rockchip_pmx_func *func; + struct rockchip_pin_group *grp; + int ret; + static u32 grp_index; + u32 i = 0; + + dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); + + func = &info->functions[index]; + + /* Initialise function */ + func->name = np->name; + func->ngroups = of_get_child_count(np); + if (func->ngroups <= 0) + return 0; + + func->groups = devm_kzalloc(info->dev, + func->ngroups * sizeof(char *), GFP_KERNEL); + if (!func->groups) + return -ENOMEM; + + for_each_child_of_node(np, child) { + func->groups[i] = child->name; + grp = &info->groups[grp_index++]; + ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); + if (ret) + return ret; + } + + return 0; +} + +static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, + struct rockchip_pinctrl *info) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct device_node *child; + int ret; + int i; + + rockchip_pinctrl_child_count(info, np); + + dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); + dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); + + info->functions = devm_kzalloc(dev, info->nfunctions * + sizeof(struct rockchip_pmx_func), + GFP_KERNEL); + if (!info->functions) { + dev_err(dev, "failed to allocate memory for function list\n"); + return -EINVAL; + } + + info->groups = devm_kzalloc(dev, info->ngroups * + sizeof(struct rockchip_pin_group), + GFP_KERNEL); + if (!info->groups) { + dev_err(dev, "failed allocate memory for ping group list\n"); + return -EINVAL; + } + + i = 0; + + for_each_child_of_node(np, child) { + if (of_device_is_compatible(child, gpio_compat)) + continue; + ret = rockchip_pinctrl_parse_functions(child, info, i++); + if (ret) { + dev_err(&pdev->dev, "failed to parse function\n"); + return ret; + } + } + + return 0; +} + +static int rockchip_pinctrl_register(struct platform_device *pdev, + struct rockchip_pinctrl *info) +{ + struct pinctrl_desc *ctrldesc = &info->pctl; + struct pinctrl_pin_desc *pindesc, *pdesc; + struct rockchip_pin_bank *pin_bank; + int pin, bank, ret; + int k; + + ctrldesc->name = "rockchip-pinctrl"; + ctrldesc->owner = THIS_MODULE; + ctrldesc->pctlops = &rockchip_pctrl_ops; + ctrldesc->pmxops = &rockchip_pmx_ops; + ctrldesc->confops = &rockchip_pinconf_ops; + + pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * + info->ctrl->nr_pins, GFP_KERNEL); + if (!pindesc) { + dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); + return -ENOMEM; + } + ctrldesc->pins = pindesc; + ctrldesc->npins = info->ctrl->nr_pins; + + pdesc = pindesc; + for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { + pin_bank = &info->ctrl->pin_banks[bank]; + for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { + pdesc->number = k; + pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", + pin_bank->name, pin); + pdesc++; + } + } + + info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info); + if (!info->pctl_dev) { + dev_err(&pdev->dev, "could not register pinctrl driver\n"); + return -EINVAL; + } + + for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { + pin_bank = &info->ctrl->pin_banks[bank]; + pin_bank->grange.name = pin_bank->name; + pin_bank->grange.id = bank; + pin_bank->grange.pin_base = pin_bank->pin_base; + pin_bank->grange.base = pin_bank->gpio_chip.base; + pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; + pin_bank->grange.gc = &pin_bank->gpio_chip; + pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); + } + + ret = rockchip_pinctrl_parse_dt(pdev, info); + if (ret) { + pinctrl_unregister(info->pctl_dev); + return ret; + } + + return 0; +} + +/* + * GPIO handling + */ + +static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) +{ + struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); + void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; + unsigned long flags; + u32 data; + + spin_lock_irqsave(&bank->slock, flags); + + data = readl(reg); + data &= ~BIT(offset); + if (value) + data |= BIT(offset); + writel(data, reg); + + spin_unlock_irqrestore(&bank->slock, flags); +} + +/* + * Returns the level of the pin for input direction and setting of the DR + * register for output gpios. + */ +static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) +{ + struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); + u32 data; + + data = readl(bank->reg_base + GPIO_EXT_PORT); + data >>= offset; + data &= 1; + return data; +} + +/* + * gpiolib gpio_direction_input callback function. The setting of the pin + * mux function as 'gpio input' will be handled by the pinctrl susbsystem + * interface. + */ +static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) +{ + return pinctrl_gpio_direction_input(gc->base + offset); +} + +/* + * gpiolib gpio_direction_output callback function. The setting of the pin + * mux function as 'gpio output' will be handled by the pinctrl susbsystem + * interface. + */ +static int rockchip_gpio_direction_output(struct gpio_chip *gc, + unsigned offset, int value) +{ + rockchip_gpio_set(gc, offset, value); + return pinctrl_gpio_direction_output(gc->base + offset); +} + +/* + * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin + * and a virtual IRQ, if not already present. + */ +static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) +{ + struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); + unsigned int virq; + + if (!bank->domain) + return -ENXIO; + + virq = irq_create_mapping(bank->domain, offset); + + return (virq) ? : -ENXIO; +} + +static const struct gpio_chip rockchip_gpiolib_chip = { + .set = rockchip_gpio_set, + .get = rockchip_gpio_get, + .direction_input = rockchip_gpio_direction_input, + .direction_output = rockchip_gpio_direction_output, + .to_irq = rockchip_gpio_to_irq, + .owner = THIS_MODULE, +}; + +/* + * Interrupt handling + */ + +static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) +{ + struct irq_chip *chip = irq_get_chip(irq); + struct rockchip_pin_bank *bank = irq_get_handler_data(irq); + u32 pend; + + dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); + + chained_irq_enter(chip, desc); + + pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); + + while (pend) { + unsigned int virq; + + irq = __ffs(pend); + pend &= ~BIT(irq); + virq = irq_linear_revmap(bank->domain, irq); + + if (!virq) { + dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); + continue; + } + + dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); + + generic_handle_irq(virq); + } + + chained_irq_exit(chip, desc); +} + +static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct rockchip_pin_bank *bank = gc->private; + u32 mask = BIT(d->hwirq); + u32 polarity; + u32 level; + u32 data; + + if (type & IRQ_TYPE_EDGE_BOTH) + __irq_set_handler_locked(d->irq, handle_edge_irq); + else + __irq_set_handler_locked(d->irq, handle_level_irq); + + irq_gc_lock(gc); + + level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); + polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + level |= mask; + polarity |= mask; + break; + case IRQ_TYPE_EDGE_FALLING: + level |= mask; + polarity &= ~mask; + break; + case IRQ_TYPE_LEVEL_HIGH: + level &= ~mask; + polarity |= mask; + break; + case IRQ_TYPE_LEVEL_LOW: + level &= ~mask; + polarity &= ~mask; + break; + default: + irq_gc_unlock(gc); + return -EINVAL; + } + + writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); + writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); + + irq_gc_unlock(gc); + + /* make sure the pin is configured as gpio input */ + rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); + data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); + data &= ~mask; + writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); + + return 0; +} + +static int rockchip_interrupts_register(struct platform_device *pdev, + struct rockchip_pinctrl *info) +{ + struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct rockchip_pin_bank *bank = ctrl->pin_banks; + unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; + struct irq_chip_generic *gc; + int ret; + int i; + + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { + if (!bank->valid) { + dev_warn(&pdev->dev, "bank %s is not valid\n", + bank->name); + continue; + } + + bank->domain = irq_domain_add_linear(bank->of_node, 32, + &irq_generic_chip_ops, NULL); + if (!bank->domain) { + dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", + bank->name); + continue; + } + + ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, + "rockchip_gpio_irq", handle_level_irq, + clr, 0, IRQ_GC_INIT_MASK_CACHE); + if (ret) { + dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", + bank->name); + irq_domain_remove(bank->domain); + continue; + } + + gc = irq_get_domain_generic_chip(bank->domain, 0); + gc->reg_base = bank->reg_base; + gc->private = bank; + gc->chip_types[0].regs.mask = GPIO_INTEN; + gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; + gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; + gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; + gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; + gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; + gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; + + irq_set_handler_data(bank->irq, bank); + irq_set_chained_handler(bank->irq, rockchip_irq_demux); + } + + return 0; +} + +static int rockchip_gpiolib_register(struct platform_device *pdev, + struct rockchip_pinctrl *info) +{ + struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct rockchip_pin_bank *bank = ctrl->pin_banks; + struct gpio_chip *gc; + int ret; + int i; + + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { + if (!bank->valid) { + dev_warn(&pdev->dev, "bank %s is not valid\n", + bank->name); + continue; + } + + bank->gpio_chip = rockchip_gpiolib_chip; + + gc = &bank->gpio_chip; + gc->base = bank->pin_base; + gc->ngpio = bank->nr_pins; + gc->dev = &pdev->dev; + gc->of_node = bank->of_node; + gc->label = bank->name; + + ret = gpiochip_add(gc); + if (ret) { + dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", + gc->label, ret); + goto fail; + } + } + + rockchip_interrupts_register(pdev, info); + + return 0; + +fail: + for (--i, --bank; i >= 0; --i, --bank) { + if (!bank->valid) + continue; + + if (gpiochip_remove(&bank->gpio_chip)) + dev_err(&pdev->dev, "gpio chip %s remove failed\n", + bank->gpio_chip.label); + } + return ret; +} + +static int rockchip_gpiolib_unregister(struct platform_device *pdev, + struct rockchip_pinctrl *info) +{ + struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct rockchip_pin_bank *bank = ctrl->pin_banks; + int ret = 0; + int i; + + for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) { + if (!bank->valid) + continue; + + ret = gpiochip_remove(&bank->gpio_chip); + } + + if (ret) + dev_err(&pdev->dev, "gpio chip remove failed\n"); + + return ret; +} + +static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, + struct device *dev) +{ + struct resource res; + + if (of_address_to_resource(bank->of_node, 0, &res)) { + dev_err(dev, "cannot find IO resource for bank\n"); + return -ENOENT; + } + + bank->reg_base = devm_ioremap_resource(dev, &res); + if (IS_ERR(bank->reg_base)) + return PTR_ERR(bank->reg_base); + + bank->irq = irq_of_parse_and_map(bank->of_node, 0); + + bank->clk = of_clk_get(bank->of_node, 0); + if (IS_ERR(bank->clk)) + return PTR_ERR(bank->clk); + + return clk_prepare_enable(bank->clk); +} + +static const struct of_device_id rockchip_pinctrl_dt_match[]; + +/* retrieve the soc specific data */ +static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( + struct rockchip_pinctrl *d, + struct platform_device *pdev) +{ + const struct of_device_id *match; + struct device_node *node = pdev->dev.of_node; + struct device_node *np; + struct rockchip_pin_ctrl *ctrl; + struct rockchip_pin_bank *bank; + int i; + + match = of_match_node(rockchip_pinctrl_dt_match, node); + ctrl = (struct rockchip_pin_ctrl *)match->data; + + for_each_child_of_node(node, np) { + if (!of_find_property(np, "gpio-controller", NULL)) + continue; + + bank = ctrl->pin_banks; + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { + if (!strcmp(bank->name, np->name)) { + bank->of_node = np; + + if (!rockchip_get_bank_data(bank, &pdev->dev)) + bank->valid = true; + + break; + } + } + } + + bank = ctrl->pin_banks; + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { + spin_lock_init(&bank->slock); + bank->drvdata = d; + bank->pin_base = ctrl->nr_pins; + ctrl->nr_pins += bank->nr_pins; + } + + return ctrl; +} + +static int rockchip_pinctrl_probe(struct platform_device *pdev) +{ + struct rockchip_pinctrl *info; + struct device *dev = &pdev->dev; + struct rockchip_pin_ctrl *ctrl; + struct resource *res; + int ret; + + if (!dev->of_node) { + dev_err(dev, "device tree node not found\n"); + return -ENODEV; + } + + info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL); + if (!info) + return -ENOMEM; + + ctrl = rockchip_pinctrl_get_soc_data(info, pdev); + if (!ctrl) { + dev_err(dev, "driver data not available\n"); + return -EINVAL; + } + info->ctrl = ctrl; + info->dev = dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "cannot find IO resource\n"); + return -ENOENT; + } + + info->reg_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(info->reg_base)) + return PTR_ERR(info->reg_base); + + ret = rockchip_gpiolib_register(pdev, info); + if (ret) + return ret; + + ret = rockchip_pinctrl_register(pdev, info); + if (ret) { + rockchip_gpiolib_unregister(pdev, info); + return ret; + } + + platform_set_drvdata(pdev, info); + + return 0; +} + +static struct rockchip_pin_bank rk2928_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; + +static struct rockchip_pin_ctrl rk2928_pin_ctrl = { + .pin_banks = rk2928_pin_banks, + .nr_banks = ARRAY_SIZE(rk2928_pin_banks), + .label = "RK2928-GPIO", + .mux_offset = 0xa8, + .pull_offset = 0x118, + .pull_auto = 1, + .pull_bank_stride = 8, +}; + +static struct rockchip_pin_bank rk3066a_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), + PIN_BANK(4, 32, "gpio4"), + PIN_BANK(6, 16, "gpio6"), +}; + +static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { + .pin_banks = rk3066a_pin_banks, + .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), + .label = "RK3066a-GPIO", + .mux_offset = 0xa8, + .pull_offset = 0x118, + .pull_auto = 1, + .pull_bank_stride = 8, +}; + +static struct rockchip_pin_bank rk3066b_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; + +static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { + .pin_banks = rk3066b_pin_banks, + .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), + .label = "RK3066b-GPIO", + .mux_offset = 0x60, + .pull_offset = -EINVAL, +}; + +static struct rockchip_pin_bank rk3188_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; + +static struct rockchip_pin_ctrl rk3188_pin_ctrl = { + .pin_banks = rk3188_pin_banks, + .nr_banks = ARRAY_SIZE(rk3188_pin_banks), + .label = "RK3188-GPIO", + .mux_offset = 0x68, + .pull_offset = 0x164, + .pull_bank_stride = 16, +}; + +static const struct of_device_id rockchip_pinctrl_dt_match[] = { + { .compatible = "rockchip,rk2928-pinctrl", + .data = (void *)&rk2928_pin_ctrl }, + { .compatible = "rockchip,rk3066a-pinctrl", + .data = (void *)&rk3066a_pin_ctrl }, + { .compatible = "rockchip,rk3066b-pinctrl", + .data = (void *)&rk3066b_pin_ctrl }, + { .compatible = "rockchip,rk3188-pinctrl", + .data = (void *)&rk3188_pin_ctrl }, + {}, +}; +MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); + +static struct platform_driver rockchip_pinctrl_driver = { + .probe = rockchip_pinctrl_probe, + .driver = { + .name = "rockchip-pinctrl", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(rockchip_pinctrl_dt_match), + }, +}; + +static int __init rockchip_pinctrl_drv_register(void) +{ + return platform_driver_register(&rockchip_pinctrl_driver); +} +postcore_initcall(rockchip_pinctrl_drv_register); + +MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>"); +MODULE_DESCRIPTION("Rockchip pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-s3c24xx.c b/drivers/pinctrl/pinctrl-s3c24xx.c new file mode 100644 index 00000000000..24446daaad7 --- /dev/null +++ b/drivers/pinctrl/pinctrl-s3c24xx.c @@ -0,0 +1,651 @@ +/* + * S3C24XX specific support for Samsung pinctrl/gpiolib driver. + * + * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This file contains the SamsungS3C24XX specific information required by the + * Samsung pinctrl/gpiolib driver. It also includes the implementation of + * external gpio and wakeup interrupt support. + */ + +#include <linux/module.h> +#include <linux/device.h> +#include <linux/interrupt.h> +#include <linux/irqdomain.h> +#include <linux/irq.h> +#include <linux/of_irq.h> +#include <linux/irqchip/chained_irq.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/err.h> + +#include "pinctrl-samsung.h" + +#define NUM_EINT 24 +#define NUM_EINT_IRQ 6 +#define EINT_MAX_PER_GROUP 8 + +#define EINTPEND_REG 0xa8 +#define EINTMASK_REG 0xa4 + +#define EINT_GROUP(i) ((int)((i) / EINT_MAX_PER_GROUP)) +#define EINT_REG(i) ((EINT_GROUP(i) * 4) + 0x88) +#define EINT_OFFS(i) ((i) % EINT_MAX_PER_GROUP * 4) + +#define EINT_LEVEL_LOW 0 +#define EINT_LEVEL_HIGH 1 +#define EINT_EDGE_FALLING 2 +#define EINT_EDGE_RISING 4 +#define EINT_EDGE_BOTH 6 +#define EINT_MASK 0xf + +static struct samsung_pin_bank_type bank_type_1bit = { + .fld_width = { 1, 1, }, + .reg_offset = { 0x00, 0x04, }, +}; + +static struct samsung_pin_bank_type bank_type_2bit = { + .fld_width = { 2, 1, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, }, +}; + +#define PIN_BANK_A(pins, reg, id) \ + { \ + .type = &bank_type_1bit, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define PIN_BANK_2BIT(pins, reg, id) \ + { \ + .type = &bank_type_2bit, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs, emask)\ + { \ + .type = &bank_type_2bit, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_func = 2, \ + .eint_mask = emask, \ + .eint_offset = eoffs, \ + .name = id \ + } + +/** + * struct s3c24xx_eint_data: EINT common data + * @drvdata: pin controller driver data + * @domains: IRQ domains of particular EINT interrupts + * @parents: mapped parent irqs in the main interrupt controller + */ +struct s3c24xx_eint_data { + struct samsung_pinctrl_drv_data *drvdata; + struct irq_domain *domains[NUM_EINT]; + int parents[NUM_EINT_IRQ]; +}; + +/** + * struct s3c24xx_eint_domain_data: per irq-domain data + * @bank: pin bank related to the domain + * @eint_data: common data + * eint0_3_parent_only: live eints 0-3 only in the main intc + */ +struct s3c24xx_eint_domain_data { + struct samsung_pin_bank *bank; + struct s3c24xx_eint_data *eint_data; + bool eint0_3_parent_only; +}; + +static int s3c24xx_eint_get_trigger(unsigned int type) +{ + switch (type) { + case IRQ_TYPE_EDGE_RISING: + return EINT_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + return EINT_EDGE_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + return EINT_EDGE_BOTH; + break; + case IRQ_TYPE_LEVEL_HIGH: + return EINT_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + return EINT_LEVEL_LOW; + break; + default: + return -EINVAL; + } +} + +static void s3c24xx_eint_set_handler(unsigned int irq, unsigned int type) +{ + /* Edge- and level-triggered interrupts need different handlers */ + if (type & IRQ_TYPE_EDGE_BOTH) + __irq_set_handler_locked(irq, handle_edge_irq); + else + __irq_set_handler_locked(irq, handle_level_irq); +} + +static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d, + struct samsung_pin_bank *bank, int pin) +{ + struct samsung_pin_bank_type *bank_type = bank->type; + unsigned long flags; + void __iomem *reg; + u8 shift; + u32 mask; + u32 val; + + /* Make sure that pin is configured as interrupt */ + reg = d->virt_base + bank->pctl_offset; + shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC]; + mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; + + spin_lock_irqsave(&bank->slock, flags); + + val = readl(reg); + val &= ~(mask << shift); + val |= bank->eint_func << shift; + writel(val, reg); + + spin_unlock_irqrestore(&bank->slock, flags); +} + +static int s3c24xx_eint_type(struct irq_data *data, unsigned int type) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + int index = bank->eint_offset + data->hwirq; + void __iomem *reg; + int trigger; + u8 shift; + u32 val; + + trigger = s3c24xx_eint_get_trigger(type); + if (trigger < 0) { + dev_err(d->dev, "unsupported external interrupt type\n"); + return -EINVAL; + } + + s3c24xx_eint_set_handler(data->irq, type); + + /* Set up interrupt trigger */ + reg = d->virt_base + EINT_REG(index); + shift = EINT_OFFS(index); + + val = readl(reg); + val &= ~(EINT_MASK << shift); + val |= trigger << shift; + writel(val, reg); + + s3c24xx_eint_set_function(d, bank, data->hwirq); + + return 0; +} + +/* Handling of EINTs 0-3 on all except S3C2412 and S3C2413 */ + +static void s3c2410_eint0_3_ack(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; + struct s3c24xx_eint_data *eint_data = ddata->eint_data; + int parent_irq = eint_data->parents[data->hwirq]; + struct irq_chip *parent_chip = irq_get_chip(parent_irq); + + parent_chip->irq_ack(irq_get_irq_data(parent_irq)); +} + +static void s3c2410_eint0_3_mask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; + struct s3c24xx_eint_data *eint_data = ddata->eint_data; + int parent_irq = eint_data->parents[data->hwirq]; + struct irq_chip *parent_chip = irq_get_chip(parent_irq); + + parent_chip->irq_mask(irq_get_irq_data(parent_irq)); +} + +static void s3c2410_eint0_3_unmask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; + struct s3c24xx_eint_data *eint_data = ddata->eint_data; + int parent_irq = eint_data->parents[data->hwirq]; + struct irq_chip *parent_chip = irq_get_chip(parent_irq); + + parent_chip->irq_unmask(irq_get_irq_data(parent_irq)); +} + +static struct irq_chip s3c2410_eint0_3_chip = { + .name = "s3c2410-eint0_3", + .irq_ack = s3c2410_eint0_3_ack, + .irq_mask = s3c2410_eint0_3_mask, + .irq_unmask = s3c2410_eint0_3_unmask, + .irq_set_type = s3c24xx_eint_type, +}; + +static void s3c2410_demux_eint0_3(unsigned int irq, struct irq_desc *desc) +{ + struct irq_data *data = irq_desc_get_irq_data(desc); + struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq); + unsigned int virq; + + /* the first 4 eints have a simple 1 to 1 mapping */ + virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq); + /* Something must be really wrong if an unmapped EINT is unmasked */ + BUG_ON(!virq); + + generic_handle_irq(virq); +} + +/* Handling of EINTs 0-3 on S3C2412 and S3C2413 */ + +static void s3c2412_eint0_3_ack(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + + unsigned long bitval = 1UL << data->hwirq; + writel(bitval, d->virt_base + EINTPEND_REG); +} + +static void s3c2412_eint0_3_mask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned long mask; + + mask = readl(d->virt_base + EINTMASK_REG); + mask |= (1UL << data->hwirq); + writel(mask, d->virt_base + EINTMASK_REG); +} + +static void s3c2412_eint0_3_unmask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned long mask; + + mask = readl(d->virt_base + EINTMASK_REG); + mask &= ~(1UL << data->hwirq); + writel(mask, d->virt_base + EINTMASK_REG); +} + +static struct irq_chip s3c2412_eint0_3_chip = { + .name = "s3c2412-eint0_3", + .irq_ack = s3c2412_eint0_3_ack, + .irq_mask = s3c2412_eint0_3_mask, + .irq_unmask = s3c2412_eint0_3_unmask, + .irq_set_type = s3c24xx_eint_type, +}; + +static void s3c2412_demux_eint0_3(unsigned int irq, struct irq_desc *desc) +{ + struct irq_chip *chip = irq_get_chip(irq); + struct irq_data *data = irq_desc_get_irq_data(desc); + struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq); + unsigned int virq; + + chained_irq_enter(chip, desc); + + /* the first 4 eints have a simple 1 to 1 mapping */ + virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq); + /* Something must be really wrong if an unmapped EINT is unmasked */ + BUG_ON(!virq); + + generic_handle_irq(virq); + + chained_irq_exit(chip, desc); +} + +/* Handling of all other eints */ + +static void s3c24xx_eint_ack(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned char index = bank->eint_offset + data->hwirq; + + writel(1UL << index, d->virt_base + EINTPEND_REG); +} + +static void s3c24xx_eint_mask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned char index = bank->eint_offset + data->hwirq; + unsigned long mask; + + mask = readl(d->virt_base + EINTMASK_REG); + mask |= (1UL << index); + writel(mask, d->virt_base + EINTMASK_REG); +} + +static void s3c24xx_eint_unmask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned char index = bank->eint_offset + data->hwirq; + unsigned long mask; + + mask = readl(d->virt_base + EINTMASK_REG); + mask &= ~(1UL << index); + writel(mask, d->virt_base + EINTMASK_REG); +} + +static struct irq_chip s3c24xx_eint_chip = { + .name = "s3c-eint", + .irq_ack = s3c24xx_eint_ack, + .irq_mask = s3c24xx_eint_mask, + .irq_unmask = s3c24xx_eint_unmask, + .irq_set_type = s3c24xx_eint_type, +}; + +static inline void s3c24xx_demux_eint(unsigned int irq, struct irq_desc *desc, + u32 offset, u32 range) +{ + struct irq_chip *chip = irq_get_chip(irq); + struct s3c24xx_eint_data *data = irq_get_handler_data(irq); + struct samsung_pinctrl_drv_data *d = data->drvdata; + unsigned int pend, mask; + + chained_irq_enter(chip, desc); + + pend = readl(d->virt_base + EINTPEND_REG); + mask = readl(d->virt_base + EINTMASK_REG); + + pend &= ~mask; + pend &= range; + + while (pend) { + unsigned int virq; + + irq = __ffs(pend); + pend &= ~(1 << irq); + virq = irq_linear_revmap(data->domains[irq], irq - offset); + /* Something is really wrong if an unmapped EINT is unmasked */ + BUG_ON(!virq); + + generic_handle_irq(virq); + } + + chained_irq_exit(chip, desc); +} + +static void s3c24xx_demux_eint4_7(unsigned int irq, struct irq_desc *desc) +{ + s3c24xx_demux_eint(irq, desc, 0, 0xf0); +} + +static void s3c24xx_demux_eint8_23(unsigned int irq, struct irq_desc *desc) +{ + s3c24xx_demux_eint(irq, desc, 8, 0xffff00); +} + +static irq_flow_handler_t s3c2410_eint_handlers[NUM_EINT_IRQ] = { + s3c2410_demux_eint0_3, + s3c2410_demux_eint0_3, + s3c2410_demux_eint0_3, + s3c2410_demux_eint0_3, + s3c24xx_demux_eint4_7, + s3c24xx_demux_eint8_23, +}; + +static irq_flow_handler_t s3c2412_eint_handlers[NUM_EINT_IRQ] = { + s3c2412_demux_eint0_3, + s3c2412_demux_eint0_3, + s3c2412_demux_eint0_3, + s3c2412_demux_eint0_3, + s3c24xx_demux_eint4_7, + s3c24xx_demux_eint8_23, +}; + +static int s3c24xx_gpf_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct s3c24xx_eint_domain_data *ddata = h->host_data; + struct samsung_pin_bank *bank = ddata->bank; + + if (!(bank->eint_mask & (1 << (bank->eint_offset + hw)))) + return -EINVAL; + + if (hw <= 3) { + if (ddata->eint0_3_parent_only) + irq_set_chip_and_handler(virq, &s3c2410_eint0_3_chip, + handle_edge_irq); + else + irq_set_chip_and_handler(virq, &s3c2412_eint0_3_chip, + handle_edge_irq); + } else { + irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, + handle_edge_irq); + } + irq_set_chip_data(virq, bank); + set_irq_flags(virq, IRQF_VALID); + return 0; +} + +static const struct irq_domain_ops s3c24xx_gpf_irq_ops = { + .map = s3c24xx_gpf_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +static int s3c24xx_gpg_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct s3c24xx_eint_domain_data *ddata = h->host_data; + struct samsung_pin_bank *bank = ddata->bank; + + if (!(bank->eint_mask & (1 << (bank->eint_offset + hw)))) + return -EINVAL; + + irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, handle_edge_irq); + irq_set_chip_data(virq, bank); + set_irq_flags(virq, IRQF_VALID); + return 0; +} + +static const struct irq_domain_ops s3c24xx_gpg_irq_ops = { + .map = s3c24xx_gpg_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +static const struct of_device_id s3c24xx_eint_irq_ids[] = { + { .compatible = "samsung,s3c2410-wakeup-eint", .data = (void *)1 }, + { .compatible = "samsung,s3c2412-wakeup-eint", .data = (void *)0 }, + { } +}; + +static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d) +{ + struct device *dev = d->dev; + const struct of_device_id *match; + struct device_node *eint_np = NULL; + struct device_node *np; + struct samsung_pin_bank *bank; + struct s3c24xx_eint_data *eint_data; + const struct irq_domain_ops *ops; + unsigned int i; + bool eint0_3_parent_only; + irq_flow_handler_t *handlers; + + for_each_child_of_node(dev->of_node, np) { + match = of_match_node(s3c24xx_eint_irq_ids, np); + if (match) { + eint_np = np; + eint0_3_parent_only = (bool)match->data; + break; + } + } + if (!eint_np) + return -ENODEV; + + eint_data = devm_kzalloc(dev, sizeof(*eint_data), GFP_KERNEL); + if (!eint_data) + return -ENOMEM; + + eint_data->drvdata = d; + + handlers = eint0_3_parent_only ? s3c2410_eint_handlers + : s3c2412_eint_handlers; + for (i = 0; i < NUM_EINT_IRQ; ++i) { + unsigned int irq; + + irq = irq_of_parse_and_map(eint_np, i); + if (!irq) { + dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i); + return -ENXIO; + } + + eint_data->parents[i] = irq; + irq_set_chained_handler(irq, handlers[i]); + irq_set_handler_data(irq, eint_data); + } + + bank = d->ctrl->pin_banks; + for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { + struct s3c24xx_eint_domain_data *ddata; + unsigned int mask; + unsigned int irq; + unsigned int pin; + + if (bank->eint_type != EINT_TYPE_WKUP) + continue; + + ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + ddata->bank = bank; + ddata->eint_data = eint_data; + ddata->eint0_3_parent_only = eint0_3_parent_only; + + ops = (bank->eint_offset == 0) ? &s3c24xx_gpf_irq_ops + : &s3c24xx_gpg_irq_ops; + + bank->irq_domain = irq_domain_add_linear(bank->of_node, + bank->nr_pins, ops, ddata); + if (!bank->irq_domain) { + dev_err(dev, "wkup irq domain add failed\n"); + return -ENXIO; + } + + irq = bank->eint_offset; + mask = bank->eint_mask; + for (pin = 0; mask; ++pin, mask >>= 1) { + if (irq > NUM_EINT) + break; + if (!(mask & 1)) + continue; + eint_data->domains[irq] = bank->irq_domain; + ++irq; + } + } + + return 0; +} + +static struct samsung_pin_bank s3c2412_pin_banks[] = { + PIN_BANK_A(23, 0x000, "gpa"), + PIN_BANK_2BIT(11, 0x010, "gpb"), + PIN_BANK_2BIT(16, 0x020, "gpc"), + PIN_BANK_2BIT(16, 0x030, "gpd"), + PIN_BANK_2BIT(16, 0x040, "gpe"), + PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), + PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00), + PIN_BANK_2BIT(11, 0x070, "gph"), + PIN_BANK_2BIT(13, 0x080, "gpj"), +}; + +struct samsung_pin_ctrl s3c2412_pin_ctrl[] = { + { + .pin_banks = s3c2412_pin_banks, + .nr_banks = ARRAY_SIZE(s3c2412_pin_banks), + .eint_wkup_init = s3c24xx_eint_init, + .label = "S3C2412-GPIO", + }, +}; + +static struct samsung_pin_bank s3c2416_pin_banks[] = { + PIN_BANK_A(27, 0x000, "gpa"), + PIN_BANK_2BIT(11, 0x010, "gpb"), + PIN_BANK_2BIT(16, 0x020, "gpc"), + PIN_BANK_2BIT(16, 0x030, "gpd"), + PIN_BANK_2BIT(16, 0x040, "gpe"), + PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), + PIN_BANK_2BIT_EINTW(8, 0x060, "gpg", 8, 0xff00), + PIN_BANK_2BIT(15, 0x070, "gph"), + PIN_BANK_2BIT(16, 0x0e0, "gpk"), + PIN_BANK_2BIT(14, 0x0f0, "gpl"), + PIN_BANK_2BIT(2, 0x100, "gpm"), +}; + +struct samsung_pin_ctrl s3c2416_pin_ctrl[] = { + { + .pin_banks = s3c2416_pin_banks, + .nr_banks = ARRAY_SIZE(s3c2416_pin_banks), + .eint_wkup_init = s3c24xx_eint_init, + .label = "S3C2416-GPIO", + }, +}; + +static struct samsung_pin_bank s3c2440_pin_banks[] = { + PIN_BANK_A(25, 0x000, "gpa"), + PIN_BANK_2BIT(11, 0x010, "gpb"), + PIN_BANK_2BIT(16, 0x020, "gpc"), + PIN_BANK_2BIT(16, 0x030, "gpd"), + PIN_BANK_2BIT(16, 0x040, "gpe"), + PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), + PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00), + PIN_BANK_2BIT(11, 0x070, "gph"), + PIN_BANK_2BIT(13, 0x0d0, "gpj"), +}; + +struct samsung_pin_ctrl s3c2440_pin_ctrl[] = { + { + .pin_banks = s3c2440_pin_banks, + .nr_banks = ARRAY_SIZE(s3c2440_pin_banks), + .eint_wkup_init = s3c24xx_eint_init, + .label = "S3C2440-GPIO", + }, +}; + +static struct samsung_pin_bank s3c2450_pin_banks[] = { + PIN_BANK_A(28, 0x000, "gpa"), + PIN_BANK_2BIT(11, 0x010, "gpb"), + PIN_BANK_2BIT(16, 0x020, "gpc"), + PIN_BANK_2BIT(16, 0x030, "gpd"), + PIN_BANK_2BIT(16, 0x040, "gpe"), + PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), + PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00), + PIN_BANK_2BIT(15, 0x070, "gph"), + PIN_BANK_2BIT(16, 0x0d0, "gpj"), + PIN_BANK_2BIT(16, 0x0e0, "gpk"), + PIN_BANK_2BIT(15, 0x0f0, "gpl"), + PIN_BANK_2BIT(2, 0x100, "gpm"), +}; + +struct samsung_pin_ctrl s3c2450_pin_ctrl[] = { + { + .pin_banks = s3c2450_pin_banks, + .nr_banks = ARRAY_SIZE(s3c2450_pin_banks), + .eint_wkup_init = s3c24xx_eint_init, + .label = "S3C2450-GPIO", + }, +}; diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c index 63ac22e8967..a7fa9e2d475 100644 --- a/drivers/pinctrl/pinctrl-samsung.c +++ b/drivers/pinctrl/pinctrl-samsung.c @@ -50,7 +50,7 @@ static struct pin_config { }; /* Global list of devices (struct samsung_pinctrl_drv_data) */ -LIST_HEAD(drvdata_list); +static LIST_HEAD(drvdata_list); static unsigned int pin_base; @@ -1113,11 +1113,23 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = (void *)exynos4x12_pin_ctrl }, { .compatible = "samsung,exynos5250-pinctrl", .data = (void *)exynos5250_pin_ctrl }, + { .compatible = "samsung,exynos5420-pinctrl", + .data = (void *)exynos5420_pin_ctrl }, #endif #ifdef CONFIG_PINCTRL_S3C64XX { .compatible = "samsung,s3c64xx-pinctrl", .data = s3c64xx_pin_ctrl }, #endif +#ifdef CONFIG_PINCTRL_S3C24XX + { .compatible = "samsung,s3c2412-pinctrl", + .data = s3c2412_pin_ctrl }, + { .compatible = "samsung,s3c2416-pinctrl", + .data = s3c2416_pin_ctrl }, + { .compatible = "samsung,s3c2440-pinctrl", + .data = s3c2440_pin_ctrl }, + { .compatible = "samsung,s3c2450-pinctrl", + .data = s3c2450_pin_ctrl }, +#endif {}, }; MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match); diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h index 26d3519240c..11bb75ba81a 100644 --- a/drivers/pinctrl/pinctrl-samsung.h +++ b/drivers/pinctrl/pinctrl-samsung.h @@ -254,6 +254,11 @@ struct samsung_pmx_func { extern struct samsung_pin_ctrl exynos4210_pin_ctrl[]; extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; extern struct samsung_pin_ctrl exynos5250_pin_ctrl[]; +extern struct samsung_pin_ctrl exynos5420_pin_ctrl[]; extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; +extern struct samsung_pin_ctrl s3c2412_pin_ctrl[]; +extern struct samsung_pin_ctrl s3c2416_pin_ctrl[]; +extern struct samsung_pin_ctrl s3c2440_pin_ctrl[]; +extern struct samsung_pin_ctrl s3c2450_pin_ctrl[]; #endif /* __PINCTRL_SAMSUNG_H */ diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index b9fa0461860..6866548fab3 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -30,7 +30,7 @@ #define DRIVER_NAME "pinctrl-single" #define PCS_MUX_PINS_NAME "pinctrl-single,pins" #define PCS_MUX_BITS_NAME "pinctrl-single,bits" -#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1) +#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 3) #define PCS_OFF_DISABLED ~0U /** @@ -163,6 +163,7 @@ struct pcs_name { * @foff: value to turn mux off * @fmax: max number of functions in fmask * @is_pinconf: whether supports pinconf + * @bits_per_pin:number of bits per pin * @names: array of register names for pins * @pins: physical pins on the SoC * @pgtree: pingroup index radix tree @@ -190,6 +191,7 @@ struct pcs_device { unsigned fmax; bool bits_per_mux; bool is_pinconf; + unsigned bits_per_pin; struct pcs_name *names; struct pcs_data pins; struct radix_tree_root pgtree; @@ -431,10 +433,11 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, vals = &func->vals[i]; val = pcs->read(vals->reg); - if (!vals->mask) - mask = pcs->fmask; + + if (pcs->bits_per_mux) + mask = vals->mask; else - mask = pcs->fmask & vals->mask; + mask = pcs->fmask; val &= ~mask; val |= (vals->val & mask); @@ -741,7 +744,8 @@ static const struct pinconf_ops pcs_pinconf_ops = { * @pcs: pcs driver instance * @offset: register offset from base */ -static int pcs_add_pin(struct pcs_device *pcs, unsigned offset) +static int pcs_add_pin(struct pcs_device *pcs, unsigned offset, + unsigned pin_pos) { struct pinctrl_pin_desc *pin; struct pcs_name *pn; @@ -756,8 +760,8 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset) pin = &pcs->pins.pa[i]; pn = &pcs->names[i]; - sprintf(pn->name, "%lx", - (unsigned long)pcs->res->start + offset); + sprintf(pn->name, "%lx.%d", + (unsigned long)pcs->res->start + offset, pin_pos); pin->name = pn->name; pin->number = i; pcs->pins.cur++; @@ -777,9 +781,17 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset) static int pcs_allocate_pin_table(struct pcs_device *pcs) { int mux_bytes, nr_pins, i; + int num_pins_in_register = 0; mux_bytes = pcs->width / BITS_PER_BYTE; - nr_pins = pcs->size / mux_bytes; + + if (pcs->bits_per_mux) { + pcs->bits_per_pin = fls(pcs->fmask); + nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; + num_pins_in_register = pcs->width / pcs->bits_per_pin; + } else { + nr_pins = pcs->size / mux_bytes; + } dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); pcs->pins.pa = devm_kzalloc(pcs->dev, @@ -800,9 +812,17 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs) for (i = 0; i < pcs->desc.npins; i++) { unsigned offset; int res; - - offset = i * mux_bytes; - res = pcs_add_pin(pcs, offset); + int byte_num; + int pin_pos = 0; + + if (pcs->bits_per_mux) { + byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE; + offset = (byte_num / mux_bytes) * mux_bytes; + pin_pos = i % num_pins_in_register; + } else { + offset = i * mux_bytes; + } + res = pcs_add_pin(pcs, offset, pin_pos); if (res < 0) { dev_err(pcs->dev, "error adding pins: %i\n", res); return res; @@ -919,7 +939,10 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset) return -EINVAL; } - index = offset / (pcs->width / BITS_PER_BYTE); + if (pcs->bits_per_mux) + index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin; + else + index = offset / (pcs->width / BITS_PER_BYTE); return index; } @@ -1097,29 +1120,18 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, { struct pcs_func_vals *vals; const __be32 *mux; - int size, params, rows, *pins, index = 0, found = 0, res = -ENOMEM; + int size, rows, *pins, index = 0, found = 0, res = -ENOMEM; struct pcs_function *function; - if (pcs->bits_per_mux) { - params = 3; - mux = of_get_property(np, PCS_MUX_BITS_NAME, &size); - } else { - params = 2; - mux = of_get_property(np, PCS_MUX_PINS_NAME, &size); - } - - if (!mux) { - dev_err(pcs->dev, "no valid property for %s\n", np->name); - return -EINVAL; - } - - if (size < (sizeof(*mux) * params)) { - dev_err(pcs->dev, "bad data for %s\n", np->name); + mux = of_get_property(np, PCS_MUX_PINS_NAME, &size); + if ((!mux) || (size < sizeof(*mux) * 2)) { + dev_err(pcs->dev, "bad data for mux %s\n", + np->name); return -EINVAL; } size /= sizeof(*mux); /* Number of elements in array */ - rows = size / params; + rows = size / 2; vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL); if (!vals) @@ -1137,10 +1149,6 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, val = be32_to_cpup(mux + index++); vals[found].reg = pcs->base + offset; vals[found].val = val; - if (params == 3) { - val = be32_to_cpup(mux + index++); - vals[found].mask = val; - } pin = pcs_get_pin_by_offset(pcs, offset); if (pin < 0) { @@ -1189,6 +1197,125 @@ free_vals: return res; } + +#define PARAMS_FOR_BITS_PER_MUX 3 + +static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, + struct device_node *np, + struct pinctrl_map **map, + unsigned *num_maps, + const char **pgnames) +{ + struct pcs_func_vals *vals; + const __be32 *mux; + int size, rows, *pins, index = 0, found = 0, res = -ENOMEM; + int npins_in_row; + struct pcs_function *function; + + mux = of_get_property(np, PCS_MUX_BITS_NAME, &size); + + if (!mux) { + dev_err(pcs->dev, "no valid property for %s\n", np->name); + return -EINVAL; + } + + if (size < (sizeof(*mux) * PARAMS_FOR_BITS_PER_MUX)) { + dev_err(pcs->dev, "bad data for %s\n", np->name); + return -EINVAL; + } + + /* Number of elements in array */ + size /= sizeof(*mux); + + rows = size / PARAMS_FOR_BITS_PER_MUX; + npins_in_row = pcs->width / pcs->bits_per_pin; + + vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row, + GFP_KERNEL); + if (!vals) + return -ENOMEM; + + pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row, + GFP_KERNEL); + if (!pins) + goto free_vals; + + while (index < size) { + unsigned offset, val; + unsigned mask, bit_pos, val_pos, mask_pos, submask; + unsigned pin_num_from_lsb; + int pin; + + offset = be32_to_cpup(mux + index++); + val = be32_to_cpup(mux + index++); + mask = be32_to_cpup(mux + index++); + + /* Parse pins in each row from LSB */ + while (mask) { + bit_pos = ffs(mask); + pin_num_from_lsb = bit_pos / pcs->bits_per_pin; + mask_pos = ((pcs->fmask) << (bit_pos - 1)); + val_pos = val & mask_pos; + submask = mask & mask_pos; + mask &= ~mask_pos; + + if (submask != mask_pos) { + dev_warn(pcs->dev, + "Invalid submask 0x%x for %s at 0x%x\n", + submask, np->name, offset); + continue; + } + + vals[found].mask = submask; + vals[found].reg = pcs->base + offset; + vals[found].val = val_pos; + + pin = pcs_get_pin_by_offset(pcs, offset); + if (pin < 0) { + dev_err(pcs->dev, + "could not add functions for %s %ux\n", + np->name, offset); + break; + } + pins[found++] = pin + pin_num_from_lsb; + } + } + + pgnames[0] = np->name; + function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1); + if (!function) + goto free_pins; + + res = pcs_add_pingroup(pcs, np, np->name, pins, found); + if (res < 0) + goto free_function; + + (*map)->type = PIN_MAP_TYPE_MUX_GROUP; + (*map)->data.mux.group = np->name; + (*map)->data.mux.function = np->name; + + if (pcs->is_pinconf) { + dev_err(pcs->dev, "pinconf not supported\n"); + goto free_pingroups; + } + + *num_maps = 1; + return 0; + +free_pingroups: + pcs_free_pingroups(pcs); + *num_maps = 1; +free_function: + pcs_remove_function(pcs, function); + +free_pins: + devm_kfree(pcs->dev, pins); + +free_vals: + devm_kfree(pcs->dev, vals); + + return res; +} /** * pcs_dt_node_to_map() - allocates and parses pinctrl maps * @pctldev: pinctrl instance @@ -1219,12 +1346,22 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, goto free_map; } - ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, num_maps, - pgnames); - if (ret < 0) { - dev_err(pcs->dev, "no pins entries for %s\n", - np_config->name); - goto free_pgnames; + if (pcs->bits_per_mux) { + ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map, + num_maps, pgnames); + if (ret < 0) { + dev_err(pcs->dev, "no pins entries for %s\n", + np_config->name); + goto free_pgnames; + } + } else { + ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, + num_maps, pgnames); + if (ret < 0) { + dev_err(pcs->dev, "no pins entries for %s\n", + np_config->name); + goto free_pgnames; + } } return 0; @@ -1346,6 +1483,29 @@ static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs) return ret; } +static int pinctrl_single_suspend(struct platform_device *pdev, + pm_message_t state) +{ + struct pcs_device *pcs; + + pcs = platform_get_drvdata(pdev); + if (!pcs) + return -EINVAL; + + return pinctrl_force_sleep(pcs->pctl); +} + +static int pinctrl_single_resume(struct platform_device *pdev) +{ + struct pcs_device *pcs; + + pcs = platform_get_drvdata(pdev); + if (!pcs) + return -EINVAL; + + return pinctrl_force_default(pcs->pctl); +} + static int pcs_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -1494,6 +1654,10 @@ static struct platform_driver pcs_driver = { .name = DRIVER_NAME, .of_match_table = pcs_of_match, }, +#ifdef CONFIG_PM + .suspend = pinctrl_single_suspend, + .resume = pinctrl_single_resume, +#endif }; module_platform_driver(pcs_driver); diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c new file mode 100644 index 00000000000..04d4506ae18 --- /dev/null +++ b/drivers/pinctrl/pinctrl-st.c @@ -0,0 +1,1403 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited. + * Authors: + * Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_gpio.h> +#include <linux/of_address.h> +#include <linux/regmap.h> +#include <linux/mfd/syscon.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/platform_device.h> +#include "core.h" + +/* PIO Block registers */ +/* PIO output */ +#define REG_PIO_POUT 0x00 +/* Set bits of POUT */ +#define REG_PIO_SET_POUT 0x04 +/* Clear bits of POUT */ +#define REG_PIO_CLR_POUT 0x08 +/* PIO input */ +#define REG_PIO_PIN 0x10 +/* PIO configuration */ +#define REG_PIO_PC(n) (0x20 + (n) * 0x10) +/* Set bits of PC[2:0] */ +#define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10) +/* Clear bits of PC[2:0] */ +#define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10) +/* PIO input comparison */ +#define REG_PIO_PCOMP 0x50 +/* Set bits of PCOMP */ +#define REG_PIO_SET_PCOMP 0x54 +/* Clear bits of PCOMP */ +#define REG_PIO_CLR_PCOMP 0x58 +/* PIO input comparison mask */ +#define REG_PIO_PMASK 0x60 +/* Set bits of PMASK */ +#define REG_PIO_SET_PMASK 0x64 +/* Clear bits of PMASK */ +#define REG_PIO_CLR_PMASK 0x68 + +#define ST_GPIO_DIRECTION_BIDIR 0x1 +#define ST_GPIO_DIRECTION_OUT 0x2 +#define ST_GPIO_DIRECTION_IN 0x4 + +/** + * Packed style retime configuration. + * There are two registers cfg0 and cfg1 in this style for each bank. + * Each field in this register is 8 bit corresponding to 8 pins in the bank. + */ +#define RT_P_CFGS_PER_BANK 2 +#define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7) +#define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23) +#define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31) +#define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7) +#define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15) +#define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23) +#define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31) + +/** + * Dedicated style retime Configuration register + * each register is dedicated per pin. + */ +#define RT_D_CFGS_PER_BANK 8 +#define RT_D_CFG_CLK_SHIFT 0 +#define RT_D_CFG_CLK_MASK (0x3 << 0) +#define RT_D_CFG_CLKNOTDATA_SHIFT 2 +#define RT_D_CFG_CLKNOTDATA_MASK BIT(2) +#define RT_D_CFG_DELAY_SHIFT 3 +#define RT_D_CFG_DELAY_MASK (0xf << 3) +#define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7 +#define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7) +#define RT_D_CFG_DOUBLE_EDGE_SHIFT 8 +#define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8) +#define RT_D_CFG_INVERTCLK_SHIFT 9 +#define RT_D_CFG_INVERTCLK_MASK BIT(9) +#define RT_D_CFG_RETIME_SHIFT 10 +#define RT_D_CFG_RETIME_MASK BIT(10) + +/* + * Pinconf is represented in an opaque unsigned long variable. + * Below is the bit allocation details for each possible configuration. + * All the bit fields can be encapsulated into four variables + * (direction, retime-type, retime-clk, retime-delay) + * + * +----------------+ + *[31:28]| reserved-3 | + * +----------------+------------- + *[27] | oe | | + * +----------------+ v + *[26] | pu | [Direction ] + * +----------------+ ^ + *[25] | od | | + * +----------------+------------- + *[24] | reserved-2 | + * +----------------+------------- + *[23] | retime | | + * +----------------+ | + *[22] | retime-invclk | | + * +----------------+ v + *[21] |retime-clknotdat| [Retime-type ] + * +----------------+ ^ + *[20] | retime-de | | + * +----------------+------------- + *[19:18]| retime-clk |------>[Retime-Clk ] + * +----------------+ + *[17:16]| reserved-1 | + * +----------------+ + *[15..0]| retime-delay |------>[Retime Delay] + * +----------------+ + */ + +#define ST_PINCONF_UNPACK(conf, param)\ + ((conf >> ST_PINCONF_ ##param ##_SHIFT) \ + & ST_PINCONF_ ##param ##_MASK) + +#define ST_PINCONF_PACK(conf, val, param) (conf |=\ + ((val & ST_PINCONF_ ##param ##_MASK) << \ + ST_PINCONF_ ##param ##_SHIFT)) + +/* Output enable */ +#define ST_PINCONF_OE_MASK 0x1 +#define ST_PINCONF_OE_SHIFT 27 +#define ST_PINCONF_OE BIT(27) +#define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE) +#define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE) + +/* Pull Up */ +#define ST_PINCONF_PU_MASK 0x1 +#define ST_PINCONF_PU_SHIFT 26 +#define ST_PINCONF_PU BIT(26) +#define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU) +#define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU) + +/* Open Drain */ +#define ST_PINCONF_OD_MASK 0x1 +#define ST_PINCONF_OD_SHIFT 25 +#define ST_PINCONF_OD BIT(25) +#define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD) +#define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD) + +#define ST_PINCONF_RT_MASK 0x1 +#define ST_PINCONF_RT_SHIFT 23 +#define ST_PINCONF_RT BIT(23) +#define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT) +#define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT) + +#define ST_PINCONF_RT_INVERTCLK_MASK 0x1 +#define ST_PINCONF_RT_INVERTCLK_SHIFT 22 +#define ST_PINCONF_RT_INVERTCLK BIT(22) +#define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \ + ST_PINCONF_UNPACK(conf, RT_INVERTCLK) +#define ST_PINCONF_PACK_RT_INVERTCLK(conf) \ + ST_PINCONF_PACK(conf, 1, RT_INVERTCLK) + +#define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1 +#define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21 +#define ST_PINCONF_RT_CLKNOTDATA BIT(21) +#define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \ + ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA) +#define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \ + ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA) + +#define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1 +#define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20 +#define ST_PINCONF_RT_DOUBLE_EDGE BIT(20) +#define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \ + ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE) +#define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \ + ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE) + +#define ST_PINCONF_RT_CLK_MASK 0x3 +#define ST_PINCONF_RT_CLK_SHIFT 18 +#define ST_PINCONF_RT_CLK BIT(18) +#define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK) +#define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK) + +/* RETIME_DELAY in Pico Secs */ +#define ST_PINCONF_RT_DELAY_MASK 0xffff +#define ST_PINCONF_RT_DELAY_SHIFT 0 +#define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY) +#define ST_PINCONF_PACK_RT_DELAY(conf, val) \ + ST_PINCONF_PACK(conf, val, RT_DELAY) + +#define ST_GPIO_PINS_PER_BANK (8) +#define OF_GPIO_ARGS_MIN (4) +#define OF_RT_ARGS_MIN (2) + +#define gpio_range_to_bank(chip) \ + container_of(chip, struct st_gpio_bank, range) + +#define gpio_chip_to_bank(chip) \ + container_of(chip, struct st_gpio_bank, gpio_chip) + + +enum st_retime_style { + st_retime_style_none, + st_retime_style_packed, + st_retime_style_dedicated, +}; + +struct st_retime_dedicated { + struct regmap_field *rt[ST_GPIO_PINS_PER_BANK]; +}; + +struct st_retime_packed { + struct regmap_field *clk1notclk0; + struct regmap_field *delay_0; + struct regmap_field *delay_1; + struct regmap_field *invertclk; + struct regmap_field *retime; + struct regmap_field *clknotdata; + struct regmap_field *double_edge; +}; + +struct st_pio_control { + u32 rt_pin_mask; + struct regmap_field *alt, *oe, *pu, *od; + /* retiming */ + union { + struct st_retime_packed rt_p; + struct st_retime_dedicated rt_d; + } rt; +}; + +struct st_pctl_data { + enum st_retime_style rt_style; + unsigned int *input_delays; + int ninput_delays; + unsigned int *output_delays; + int noutput_delays; + /* register offset information */ + int alt, oe, pu, od, rt; +}; + +struct st_pinconf { + int pin; + const char *name; + unsigned long config; + int altfunc; +}; + +struct st_pmx_func { + const char *name; + const char **groups; + unsigned ngroups; +}; + +struct st_pctl_group { + const char *name; + unsigned int *pins; + unsigned npins; + struct st_pinconf *pin_conf; +}; + +struct st_gpio_bank { + struct gpio_chip gpio_chip; + struct pinctrl_gpio_range range; + void __iomem *base; + struct st_pio_control pc; +}; + +struct st_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl; + struct st_gpio_bank *banks; + int nbanks; + struct st_pmx_func *functions; + int nfunctions; + struct st_pctl_group *groups; + int ngroups; + struct regmap *regmap; + const struct st_pctl_data *data; +}; + +/* SOC specific data */ +/* STiH415 data */ +unsigned int stih415_input_delays[] = {0, 500, 1000, 1500}; +unsigned int stih415_output_delays[] = {0, 1000, 2000, 3000}; + +#define STIH415_PCTRL_COMMON_DATA \ + .rt_style = st_retime_style_packed, \ + .input_delays = stih415_input_delays, \ + .ninput_delays = 4, \ + .output_delays = stih415_output_delays, \ + .noutput_delays = 4 + +static const struct st_pctl_data stih415_sbc_data = { + STIH415_PCTRL_COMMON_DATA, + .alt = 0, .oe = 5, .pu = 7, .od = 9, .rt = 16, +}; + +static const struct st_pctl_data stih415_front_data = { + STIH415_PCTRL_COMMON_DATA, + .alt = 0, .oe = 8, .pu = 10, .od = 12, .rt = 16, +}; + +static const struct st_pctl_data stih415_rear_data = { + STIH415_PCTRL_COMMON_DATA, + .alt = 0, .oe = 6, .pu = 8, .od = 10, .rt = 38, +}; + +static const struct st_pctl_data stih415_left_data = { + STIH415_PCTRL_COMMON_DATA, + .alt = 0, .oe = 3, .pu = 4, .od = 5, .rt = 6, +}; + +static const struct st_pctl_data stih415_right_data = { + STIH415_PCTRL_COMMON_DATA, + .alt = 0, .oe = 5, .pu = 7, .od = 9, .rt = 11, +}; + +/* STiH416 data */ +unsigned int stih416_delays[] = {0, 300, 500, 750, 1000, 1250, 1500, + 1750, 2000, 2250, 2500, 2750, 3000, 3250 }; + +static const struct st_pctl_data stih416_data = { + .rt_style = st_retime_style_dedicated, + .input_delays = stih416_delays, + .ninput_delays = 14, + .output_delays = stih416_delays, + .noutput_delays = 14, + .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100, +}; + +/* Low level functions.. */ +static inline int st_gpio_bank(int gpio) +{ + return gpio/ST_GPIO_PINS_PER_BANK; +} + +static inline int st_gpio_pin(int gpio) +{ + return gpio%ST_GPIO_PINS_PER_BANK; +} + +static void st_pinconf_set_config(struct st_pio_control *pc, + int pin, unsigned long config) +{ + struct regmap_field *output_enable = pc->oe; + struct regmap_field *pull_up = pc->pu; + struct regmap_field *open_drain = pc->od; + unsigned int oe_value, pu_value, od_value; + unsigned long mask = BIT(pin); + + regmap_field_read(output_enable, &oe_value); + regmap_field_read(pull_up, &pu_value); + regmap_field_read(open_drain, &od_value); + + /* Clear old values */ + oe_value &= ~mask; + pu_value &= ~mask; + od_value &= ~mask; + + if (config & ST_PINCONF_OE) + oe_value |= mask; + if (config & ST_PINCONF_PU) + pu_value |= mask; + if (config & ST_PINCONF_OD) + od_value |= mask; + + regmap_field_write(output_enable, oe_value); + regmap_field_write(pull_up, pu_value); + regmap_field_write(open_drain, od_value); +} + +static void st_pctl_set_function(struct st_pio_control *pc, + int pin_id, int function) +{ + struct regmap_field *alt = pc->alt; + unsigned int val; + int pin = st_gpio_pin(pin_id); + int offset = pin * 4; + + regmap_field_read(alt, &val); + val &= ~(0xf << offset); + val |= function << offset; + regmap_field_write(alt, val); +} + +static unsigned long st_pinconf_delay_to_bit(unsigned int delay, + const struct st_pctl_data *data, unsigned long config) +{ + unsigned int *delay_times; + int num_delay_times, i, closest_index = -1; + unsigned int closest_divergence = UINT_MAX; + + if (ST_PINCONF_UNPACK_OE(config)) { + delay_times = data->output_delays; + num_delay_times = data->noutput_delays; + } else { + delay_times = data->input_delays; + num_delay_times = data->ninput_delays; + } + + for (i = 0; i < num_delay_times; i++) { + unsigned int divergence = abs(delay - delay_times[i]); + + if (divergence == 0) + return i; + + if (divergence < closest_divergence) { + closest_divergence = divergence; + closest_index = i; + } + } + + pr_warn("Attempt to set delay %d, closest available %d\n", + delay, delay_times[closest_index]); + + return closest_index; +} + +static unsigned long st_pinconf_bit_to_delay(unsigned int index, + const struct st_pctl_data *data, unsigned long output) +{ + unsigned int *delay_times; + int num_delay_times; + + if (output) { + delay_times = data->output_delays; + num_delay_times = data->noutput_delays; + } else { + delay_times = data->input_delays; + num_delay_times = data->ninput_delays; + } + + if (index < num_delay_times) { + return delay_times[index]; + } else { + pr_warn("Delay not found in/out delay list\n"); + return 0; + } +} + +static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field, + int enable, int pin) +{ + unsigned int val = 0; + + regmap_field_read(field, &val); + if (enable) + val |= BIT(pin); + else + val &= ~BIT(pin); + regmap_field_write(field, val); +} + +static void st_pinconf_set_retime_packed(struct st_pinctrl *info, + struct st_pio_control *pc, unsigned long config, int pin) +{ + const struct st_pctl_data *data = info->data; + struct st_retime_packed *rt_p = &pc->rt.rt_p; + unsigned int delay; + + st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0, + ST_PINCONF_UNPACK_RT_CLK(config), pin); + + st_regmap_field_bit_set_clear_pin(rt_p->clknotdata, + ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin); + + st_regmap_field_bit_set_clear_pin(rt_p->double_edge, + ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin); + + st_regmap_field_bit_set_clear_pin(rt_p->invertclk, + ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin); + + st_regmap_field_bit_set_clear_pin(rt_p->retime, + ST_PINCONF_UNPACK_RT(config), pin); + + delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config), + data, config); + /* 2 bit delay, lsb */ + st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin); + /* 2 bit delay, msb */ + st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin); + +} + +static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info, + struct st_pio_control *pc, unsigned long config, int pin) +{ + int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1; + int clk = ST_PINCONF_UNPACK_RT_CLK(config); + int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config); + int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config); + int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config); + int retime = ST_PINCONF_UNPACK_RT(config); + + unsigned long delay = st_pinconf_delay_to_bit( + ST_PINCONF_UNPACK_RT_DELAY(config), + info->data, config); + struct st_retime_dedicated *rt_d = &pc->rt.rt_d; + + unsigned long retime_config = + ((clk) << RT_D_CFG_CLK_SHIFT) | + ((delay) << RT_D_CFG_DELAY_SHIFT) | + ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) | + ((retime) << RT_D_CFG_RETIME_SHIFT) | + ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) | + ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) | + ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT); + + regmap_field_write(rt_d->rt[pin], retime_config); +} + +static void st_pinconf_get_direction(struct st_pio_control *pc, + int pin, unsigned long *config) +{ + unsigned int oe_value, pu_value, od_value; + + regmap_field_read(pc->oe, &oe_value); + regmap_field_read(pc->pu, &pu_value); + regmap_field_read(pc->od, &od_value); + + if (oe_value & BIT(pin)) + ST_PINCONF_PACK_OE(*config); + if (pu_value & BIT(pin)) + ST_PINCONF_PACK_PU(*config); + if (od_value & BIT(pin)) + ST_PINCONF_PACK_OD(*config); + +} + +static int st_pinconf_get_retime_packed(struct st_pinctrl *info, + struct st_pio_control *pc, int pin, unsigned long *config) +{ + const struct st_pctl_data *data = info->data; + struct st_retime_packed *rt_p = &pc->rt.rt_p; + unsigned int delay_bits, delay, delay0, delay1, val; + int output = ST_PINCONF_UNPACK_OE(*config); + + if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) + ST_PINCONF_PACK_RT(*config); + + if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) + ST_PINCONF_PACK_RT_CLK(*config, 1); + + if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) + ST_PINCONF_PACK_RT_CLKNOTDATA(*config); + + if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) + ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); + + if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) + ST_PINCONF_PACK_RT_INVERTCLK(*config); + + regmap_field_read(rt_p->delay_0, &delay0); + regmap_field_read(rt_p->delay_1, &delay1); + delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) | + (((delay0 & BIT(pin)) ? 1 : 0)); + delay = st_pinconf_bit_to_delay(delay_bits, data, output); + ST_PINCONF_PACK_RT_DELAY(*config, delay); + + return 0; +} + +static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info, + struct st_pio_control *pc, int pin, unsigned long *config) +{ + unsigned int value; + unsigned long delay_bits, delay, rt_clk; + int output = ST_PINCONF_UNPACK_OE(*config); + struct st_retime_dedicated *rt_d = &pc->rt.rt_d; + + regmap_field_read(rt_d->rt[pin], &value); + + rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT; + ST_PINCONF_PACK_RT_CLK(*config, rt_clk); + + delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT; + delay = st_pinconf_bit_to_delay(delay_bits, info->data, output); + ST_PINCONF_PACK_RT_DELAY(*config, delay); + + if (value & RT_D_CFG_CLKNOTDATA_MASK) + ST_PINCONF_PACK_RT_CLKNOTDATA(*config); + + if (value & RT_D_CFG_DOUBLE_EDGE_MASK) + ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); + + if (value & RT_D_CFG_INVERTCLK_MASK) + ST_PINCONF_PACK_RT_INVERTCLK(*config); + + if (value & RT_D_CFG_RETIME_MASK) + ST_PINCONF_PACK_RT(*config); + + return 0; +} + +/* GPIO related functions */ + +static inline void __st_gpio_set(struct st_gpio_bank *bank, + unsigned offset, int value) +{ + if (value) + writel(BIT(offset), bank->base + REG_PIO_SET_POUT); + else + writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); +} + +static void st_gpio_direction(struct st_gpio_bank *bank, + unsigned int gpio, unsigned int direction) +{ + int offset = st_gpio_pin(gpio); + int i = 0; + /** + * There are three configuration registers (PIOn_PC0, PIOn_PC1 + * and PIOn_PC2) for each port. These are used to configure the + * PIO port pins. Each pin can be configured as an input, output, + * bidirectional, or alternative function pin. Three bits, one bit + * from each of the three registers, configure the corresponding bit of + * the port. Valid bit settings is: + * + * PC2 PC1 PC0 Direction. + * 0 0 0 [Input Weak pull-up] + * 0 0 or 1 1 [Bidirection] + * 0 1 0 [Output] + * 1 0 0 [Input] + * + * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits + * individually. + */ + for (i = 0; i <= 2; i++) { + if (direction & BIT(i)) + writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); + else + writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); + } +} + +static int st_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_request_gpio(chip->base + offset); +} + +static void st_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_free_gpio(chip->base + offset); +} + +static int st_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct st_gpio_bank *bank = gpio_chip_to_bank(chip); + + return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); +} + +static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct st_gpio_bank *bank = gpio_chip_to_bank(chip); + __st_gpio_set(bank, offset, value); +} + +static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_gpio_direction_input(chip->base + offset); + + return 0; +} + +static int st_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct st_gpio_bank *bank = gpio_chip_to_bank(chip); + + __st_gpio_set(bank, offset, value); + pinctrl_gpio_direction_output(chip->base + offset); + + return 0; +} + +static int st_gpio_xlate(struct gpio_chip *gc, + const struct of_phandle_args *gpiospec, u32 *flags) +{ + if (WARN_ON(gc->of_gpio_n_cells < 1)) + return -EINVAL; + + if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) + return -EINVAL; + + if (gpiospec->args[0] > gc->ngpio) + return -EINVAL; + + return gpiospec->args[0]; +} + +/* Pinctrl Groups */ +static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->ngroups; +} + +static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->groups[selector].name; +} + +static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned selector, const unsigned **pins, unsigned *npins) +{ + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + if (selector >= info->ngroups) + return -EINVAL; + + *pins = info->groups[selector].pins; + *npins = info->groups[selector].npins; + + return 0; +} + +static const inline struct st_pctl_group *st_pctl_find_group_by_name( + const struct st_pinctrl *info, const char *name) +{ + int i; + + for (i = 0; i < info->ngroups; i++) { + if (!strcmp(info->groups[i].name, name)) + return &info->groups[i]; + } + + return NULL; +} + +static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, struct pinctrl_map **map, unsigned *num_maps) +{ + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + const struct st_pctl_group *grp; + struct pinctrl_map *new_map; + struct device_node *parent; + int map_num, i; + + grp = st_pctl_find_group_by_name(info, np->name); + if (!grp) { + dev_err(info->dev, "unable to find group for node %s\n", + np->name); + return -EINVAL; + } + + map_num = grp->npins + 1; + new_map = devm_kzalloc(pctldev->dev, + sizeof(*new_map) * map_num, GFP_KERNEL); + if (!new_map) + return -ENOMEM; + + parent = of_get_parent(np); + if (!parent) { + devm_kfree(pctldev->dev, new_map); + return -EINVAL; + } + + *map = new_map; + *num_maps = map_num; + new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; + new_map[0].data.mux.function = parent->name; + new_map[0].data.mux.group = np->name; + of_node_put(parent); + + /* create config map per pin */ + new_map++; + for (i = 0; i < grp->npins; i++) { + new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; + new_map[i].data.configs.group_or_pin = + pin_get_name(pctldev, grp->pins[i]); + new_map[i].data.configs.configs = &grp->pin_conf[i].config; + new_map[i].data.configs.num_configs = 1; + } + dev_info(pctldev->dev, "maps: function %s group %s num %d\n", + (*map)->data.mux.function, grp->name, map_num); + + return 0; +} + +static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ +} + +static struct pinctrl_ops st_pctlops = { + .get_groups_count = st_pctl_get_groups_count, + .get_group_pins = st_pctl_get_group_pins, + .get_group_name = st_pctl_get_group_name, + .dt_node_to_map = st_pctl_dt_node_to_map, + .dt_free_map = st_pctl_dt_free_map, +}; + +/* Pinmux */ +static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->nfunctions; +} + +const char *st_pmx_get_fname(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->functions[selector].name; +} + +static int st_pmx_get_groups(struct pinctrl_dev *pctldev, + unsigned selector, const char * const **grps, unsigned * const ngrps) +{ + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + *grps = info->functions[selector].groups; + *ngrps = info->functions[selector].ngroups; + + return 0; +} + +static struct st_pio_control *st_get_pio_control( + struct pinctrl_dev *pctldev, int pin) +{ + struct pinctrl_gpio_range *range = + pinctrl_find_gpio_range_from_pin(pctldev, pin); + struct st_gpio_bank *bank = gpio_range_to_bank(range); + + return &bank->pc; +} + +static int st_pmx_enable(struct pinctrl_dev *pctldev, unsigned fselector, + unsigned group) +{ + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct st_pinconf *conf = info->groups[group].pin_conf; + struct st_pio_control *pc; + int i; + + for (i = 0; i < info->groups[group].npins; i++) { + pc = st_get_pio_control(pctldev, conf[i].pin); + st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc); + } + + return 0; +} + +static void st_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) +{ +} + +static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned gpio, + bool input) +{ + struct st_gpio_bank *bank = gpio_range_to_bank(range); + /* + * When a PIO bank is used in its primary function mode (altfunc = 0) + * Output Enable (OE), Open Drain(OD), and Pull Up (PU) + * for the primary PIO functions are driven by the related PIO block + */ + st_pctl_set_function(&bank->pc, gpio, 0); + st_gpio_direction(bank, gpio, input ? + ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT); + + return 0; +} + +static struct pinmux_ops st_pmxops = { + .get_functions_count = st_pmx_get_funcs_count, + .get_function_name = st_pmx_get_fname, + .get_function_groups = st_pmx_get_groups, + .enable = st_pmx_enable, + .disable = st_pmx_disable, + .gpio_set_direction = st_pmx_set_gpio_direction, +}; + +/* Pinconf */ +static void st_pinconf_get_retime(struct st_pinctrl *info, + struct st_pio_control *pc, int pin, unsigned long *config) +{ + if (info->data->rt_style == st_retime_style_packed) + st_pinconf_get_retime_packed(info, pc, pin, config); + else if (info->data->rt_style == st_retime_style_dedicated) + if ((BIT(pin) & pc->rt_pin_mask)) + st_pinconf_get_retime_dedicated(info, pc, + pin, config); +} + +static void st_pinconf_set_retime(struct st_pinctrl *info, + struct st_pio_control *pc, int pin, unsigned long config) +{ + if (info->data->rt_style == st_retime_style_packed) + st_pinconf_set_retime_packed(info, pc, config, pin); + else if (info->data->rt_style == st_retime_style_dedicated) + if ((BIT(pin) & pc->rt_pin_mask)) + st_pinconf_set_retime_dedicated(info, pc, + config, pin); +} + +static int st_pinconf_set(struct pinctrl_dev *pctldev, + unsigned pin_id, unsigned long config) +{ + int pin = st_gpio_pin(pin_id); + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); + + st_pinconf_set_config(pc, pin, config); + st_pinconf_set_retime(info, pc, pin, config); + + return 0; +} + +static int st_pinconf_get(struct pinctrl_dev *pctldev, + unsigned pin_id, unsigned long *config) +{ + int pin = st_gpio_pin(pin_id); + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); + + *config = 0; + st_pinconf_get_direction(pc, pin, config); + st_pinconf_get_retime(info, pc, pin, config); + + return 0; +} + +static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned pin_id) +{ + unsigned long config; + st_pinconf_get(pctldev, pin_id, &config); + + seq_printf(s, "[OE:%ld,PU:%ld,OD:%ld]\n" + "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld," + "de:%ld,rt-clk:%ld,rt-delay:%ld]", + ST_PINCONF_UNPACK_OE(config), + ST_PINCONF_UNPACK_PU(config), + ST_PINCONF_UNPACK_OD(config), + ST_PINCONF_UNPACK_RT(config), + ST_PINCONF_UNPACK_RT_INVERTCLK(config), + ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), + ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), + ST_PINCONF_UNPACK_RT_CLK(config), + ST_PINCONF_UNPACK_RT_DELAY(config)); +} + +static struct pinconf_ops st_confops = { + .pin_config_get = st_pinconf_get, + .pin_config_set = st_pinconf_set, + .pin_config_dbg_show = st_pinconf_dbg_show, +}; + +static void st_pctl_dt_child_count(struct st_pinctrl *info, + struct device_node *np) +{ + struct device_node *child; + for_each_child_of_node(np, child) { + if (of_property_read_bool(child, "gpio-controller")) { + info->nbanks++; + } else { + info->nfunctions++; + info->ngroups += of_get_child_count(child); + } + } +} + +static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info, + int bank, struct st_pio_control *pc) +{ + struct device *dev = info->dev; + struct regmap *rm = info->regmap; + const struct st_pctl_data *data = info->data; + /* 2 registers per bank */ + int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; + struct st_retime_packed *rt_p = &pc->rt.rt_p; + /* cfg0 */ + struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg); + struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg); + struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg); + /* cfg1 */ + struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4); + struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4); + struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4); + struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4); + + rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0); + rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0); + rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1); + rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk); + rt_p->retime = devm_regmap_field_alloc(dev, rm, retime); + rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata); + rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge); + + if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) || + IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) || + IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) || + IS_ERR(rt_p->double_edge)) + return -EINVAL; + + return 0; +} + +static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info, + int bank, struct st_pio_control *pc) +{ + struct device *dev = info->dev; + struct regmap *rm = info->regmap; + const struct st_pctl_data *data = info->data; + /* 8 registers per bank */ + int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; + struct st_retime_dedicated *rt_d = &pc->rt.rt_d; + unsigned int j; + u32 pin_mask = pc->rt_pin_mask; + + for (j = 0; j < RT_D_CFGS_PER_BANK; j++) { + if (BIT(j) & pin_mask) { + struct reg_field reg = REG_FIELD(reg_offset, 0, 31); + rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg); + if (IS_ERR(rt_d->rt[j])) + return -EINVAL; + reg_offset += 4; + } + } + return 0; +} + +static int st_pctl_dt_setup_retime(struct st_pinctrl *info, + int bank, struct st_pio_control *pc) +{ + const struct st_pctl_data *data = info->data; + if (data->rt_style == st_retime_style_packed) + return st_pctl_dt_setup_retime_packed(info, bank, pc); + else if (data->rt_style == st_retime_style_dedicated) + return st_pctl_dt_setup_retime_dedicated(info, bank, pc); + + return -EINVAL; +} + +static int st_parse_syscfgs(struct st_pinctrl *info, + int bank, struct device_node *np) +{ + const struct st_pctl_data *data = info->data; + /** + * For a given shared register like OE/PU/OD, there are 8 bits per bank + * 0:7 belongs to bank0, 8:15 belongs to bank1 ... + * So each register is shared across 4 banks. + */ + int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK; + int msb = lsb + ST_GPIO_PINS_PER_BANK - 1; + struct reg_field alt_reg = REG_FIELD((data->alt + bank) * 4, 0, 31); + struct reg_field oe_reg = REG_FIELD((data->oe + bank/4) * 4, lsb, msb); + struct reg_field pu_reg = REG_FIELD((data->pu + bank/4) * 4, lsb, msb); + struct reg_field od_reg = REG_FIELD((data->od + bank/4) * 4, lsb, msb); + struct st_pio_control *pc = &info->banks[bank].pc; + struct device *dev = info->dev; + struct regmap *regmap = info->regmap; + + pc->alt = devm_regmap_field_alloc(dev, regmap, alt_reg); + pc->oe = devm_regmap_field_alloc(dev, regmap, oe_reg); + pc->pu = devm_regmap_field_alloc(dev, regmap, pu_reg); + pc->od = devm_regmap_field_alloc(dev, regmap, od_reg); + + if (IS_ERR(pc->alt) || IS_ERR(pc->oe) || + IS_ERR(pc->pu) || IS_ERR(pc->od)) + return -EINVAL; + + /* retime avaiable for all pins by default */ + pc->rt_pin_mask = 0xff; + of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); + st_pctl_dt_setup_retime(info, bank, pc); + + return 0; +} + +/* + * Each pin is represented in of the below forms. + * <bank offset mux direction rt_type rt_delay rt_clk> + */ +static int st_pctl_dt_parse_groups(struct device_node *np, + struct st_pctl_group *grp, struct st_pinctrl *info, int idx) +{ + /* bank pad direction val altfunction */ + const __be32 *list; + struct property *pp; + struct st_pinconf *conf; + phandle phandle; + struct device_node *pins; + u32 pin; + int i = 0, npins = 0, nr_props; + + pins = of_get_child_by_name(np, "st,pins"); + if (!pins) + return -ENODATA; + + for_each_property_of_node(pins, pp) { + /* Skip those we do not want to proceed */ + if (!strcmp(pp->name, "name")) + continue; + + if (pp && (pp->length/sizeof(__be32)) >= OF_GPIO_ARGS_MIN) { + npins++; + } else { + pr_warn("Invalid st,pins in %s node\n", np->name); + return -EINVAL; + } + } + + grp->npins = npins; + grp->name = np->name; + grp->pins = devm_kzalloc(info->dev, npins * sizeof(u32), GFP_KERNEL); + grp->pin_conf = devm_kzalloc(info->dev, + npins * sizeof(*conf), GFP_KERNEL); + + if (!grp->pins || !grp->pin_conf) + return -ENOMEM; + + /* <bank offset mux direction rt_type rt_delay rt_clk> */ + for_each_property_of_node(pins, pp) { + if (!strcmp(pp->name, "name")) + continue; + nr_props = pp->length/sizeof(u32); + list = pp->value; + conf = &grp->pin_conf[i]; + + /* bank & offset */ + phandle = be32_to_cpup(list++); + pin = be32_to_cpup(list++); + conf->pin = of_get_named_gpio(pins, pp->name, 0); + conf->name = pp->name; + grp->pins[i] = conf->pin; + /* mux */ + conf->altfunc = be32_to_cpup(list++); + conf->config = 0; + /* direction */ + conf->config |= be32_to_cpup(list++); + /* rt_type rt_delay rt_clk */ + if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) { + /* rt_type */ + conf->config |= be32_to_cpup(list++); + /* rt_delay */ + conf->config |= be32_to_cpup(list++); + /* rt_clk */ + if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) + conf->config |= be32_to_cpup(list++); + } + i++; + } + of_node_put(pins); + + return 0; +} + +static int st_pctl_parse_functions(struct device_node *np, + struct st_pinctrl *info, u32 index, int *grp_index) +{ + struct device_node *child; + struct st_pmx_func *func; + struct st_pctl_group *grp; + int ret, i; + + func = &info->functions[index]; + func->name = np->name; + func->ngroups = of_get_child_count(np); + if (func->ngroups <= 0) { + dev_err(info->dev, "No groups defined\n"); + return -EINVAL; + } + func->groups = devm_kzalloc(info->dev, + func->ngroups * sizeof(char *), GFP_KERNEL); + if (!func->groups) + return -ENOMEM; + + i = 0; + for_each_child_of_node(np, child) { + func->groups[i] = child->name; + grp = &info->groups[*grp_index]; + *grp_index += 1; + ret = st_pctl_dt_parse_groups(child, grp, info, i++); + if (ret) + return ret; + } + dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n", + index, func->name, func->ngroups); + + return 0; +} + +static struct gpio_chip st_gpio_template = { + .request = st_gpio_request, + .free = st_gpio_free, + .get = st_gpio_get, + .set = st_gpio_set, + .direction_input = st_gpio_direction_input, + .direction_output = st_gpio_direction_output, + .ngpio = ST_GPIO_PINS_PER_BANK, + .of_gpio_n_cells = 1, + .of_xlate = st_gpio_xlate, +}; + +static int st_gpiolib_register_bank(struct st_pinctrl *info, + int bank_nr, struct device_node *np) +{ + struct st_gpio_bank *bank = &info->banks[bank_nr]; + struct pinctrl_gpio_range *range = &bank->range; + struct device *dev = info->dev; + int bank_num = of_alias_get_id(np, "gpio"); + struct resource res; + int err; + + if (of_address_to_resource(np, 0, &res)) + return -ENODEV; + + bank->base = devm_request_and_ioremap(dev, &res); + if (!bank->base) { + dev_err(dev, "Can't get IO memory mapping!\n"); + return -ENODEV; + } + + bank->gpio_chip = st_gpio_template; + bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; + bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; + bank->gpio_chip.of_node = np; + + of_property_read_string(np, "st,bank-name", &range->name); + bank->gpio_chip.label = range->name; + + range->id = bank_num; + range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; + range->npins = bank->gpio_chip.ngpio; + range->gc = &bank->gpio_chip; + err = gpiochip_add(&bank->gpio_chip); + if (err) { + dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num); + return err; + } + dev_info(dev, "%s bank added.\n", range->name); + + return 0; +} + +static struct of_device_id st_pctl_of_match[] = { + { .compatible = "st,stih415-sbc-pinctrl", .data = &stih415_sbc_data }, + { .compatible = "st,stih415-rear-pinctrl", .data = &stih415_rear_data }, + { .compatible = "st,stih415-left-pinctrl", .data = &stih415_left_data }, + { .compatible = "st,stih415-right-pinctrl", + .data = &stih415_right_data }, + { .compatible = "st,stih415-front-pinctrl", + .data = &stih415_front_data }, + { .compatible = "st,stih416-sbc-pinctrl", .data = &stih416_data}, + { .compatible = "st,stih416-front-pinctrl", .data = &stih416_data}, + { .compatible = "st,stih416-rear-pinctrl", .data = &stih416_data}, + { .compatible = "st,stih416-fvdp-fe-pinctrl", .data = &stih416_data}, + { .compatible = "st,stih416-fvdp-lite-pinctrl", .data = &stih416_data}, + { /* sentinel */ } +}; + +static int st_pctl_probe_dt(struct platform_device *pdev, + struct pinctrl_desc *pctl_desc, struct st_pinctrl *info) +{ + int ret = 0; + int i = 0, j = 0, k = 0, bank; + struct pinctrl_pin_desc *pdesc; + struct device_node *np = pdev->dev.of_node; + struct device_node *child; + int grp_index = 0; + + st_pctl_dt_child_count(info, np); + if (!info->nbanks) { + dev_err(&pdev->dev, "you need atleast one gpio bank\n"); + return -EINVAL; + } + + dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks); + dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions); + dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups); + + info->functions = devm_kzalloc(&pdev->dev, + info->nfunctions * sizeof(*info->functions), GFP_KERNEL); + + info->groups = devm_kzalloc(&pdev->dev, + info->ngroups * sizeof(*info->groups) , GFP_KERNEL); + + info->banks = devm_kzalloc(&pdev->dev, + info->nbanks * sizeof(*info->banks), GFP_KERNEL); + + if (!info->functions || !info->groups || !info->banks) + return -ENOMEM; + + info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); + if (IS_ERR(info->regmap)) { + dev_err(info->dev, "No syscfg phandle specified\n"); + return PTR_ERR(info->regmap); + } + info->data = of_match_node(st_pctl_of_match, np)->data; + + pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; + pdesc = devm_kzalloc(&pdev->dev, + sizeof(*pdesc) * pctl_desc->npins, GFP_KERNEL); + if (!pdesc) + return -ENOMEM; + + pctl_desc->pins = pdesc; + + bank = 0; + for_each_child_of_node(np, child) { + if (of_property_read_bool(child, "gpio-controller")) { + const char *bank_name = NULL; + ret = st_gpiolib_register_bank(info, bank, child); + if (ret) + return ret; + + k = info->banks[bank].range.pin_base; + bank_name = info->banks[bank].range.name; + for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) { + pdesc->number = k; + pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]", + bank_name, j); + pdesc++; + } + st_parse_syscfgs(info, bank, child); + bank++; + } else { + ret = st_pctl_parse_functions(child, info, + i++, &grp_index); + if (ret) { + dev_err(&pdev->dev, "No functions found.\n"); + return ret; + } + } + } + + return 0; +} + +static int st_pctl_probe(struct platform_device *pdev) +{ + struct st_pinctrl *info; + struct pinctrl_desc *pctl_desc; + int ret, i; + + if (!pdev->dev.of_node) { + dev_err(&pdev->dev, "device node not found.\n"); + return -EINVAL; + } + + pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); + if (!pctl_desc) + return -ENOMEM; + + info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + info->dev = &pdev->dev; + platform_set_drvdata(pdev, info); + ret = st_pctl_probe_dt(pdev, pctl_desc, info); + if (ret) + return ret; + + pctl_desc->owner = THIS_MODULE, + pctl_desc->pctlops = &st_pctlops, + pctl_desc->pmxops = &st_pmxops, + pctl_desc->confops = &st_confops, + pctl_desc->name = dev_name(&pdev->dev); + + info->pctl = pinctrl_register(pctl_desc, &pdev->dev, info); + if (!info->pctl) { + dev_err(&pdev->dev, "Failed pinctrl registration\n"); + return -EINVAL; + } + + for (i = 0; i < info->nbanks; i++) + pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); + + return 0; +} + +static struct platform_driver st_pctl_driver = { + .driver = { + .name = "st-pinctrl", + .owner = THIS_MODULE, + .of_match_table = st_pctl_of_match, + }, + .probe = st_pctl_probe, +}; + +static int __init st_pctl_init(void) +{ + return platform_driver_register(&st_pctl_driver); +} +arch_initcall(st_pctl_init); diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h new file mode 100644 index 00000000000..2eeae0c066c --- /dev/null +++ b/drivers/pinctrl/pinctrl-sunxi-pins.h @@ -0,0 +1,2023 @@ +/* + * Allwinner A1X SoCs pinctrl driver. + * + * Copyright (C) 2012 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PINCTRL_SUNXI_PINS_H +#define __PINCTRL_SUNXI_PINS_H + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun4i_a10_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */ + SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */ + SUNXI_FUNCTION(0x4, "uart2")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */ + SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart2")), /* CTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */ + SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x4, "uart2")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */ + SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x4, "uart2")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */ + SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */ + SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */ + SUNXI_FUNCTION(0x3, "spi3")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */ + SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */ + SUNXI_FUNCTION(0x3, "spi3")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */ + SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */ + SUNXI_FUNCTION(0x4, "uart1")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* EMDC */ + SUNXI_FUNCTION(0x4, "uart1")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */ + SUNXI_FUNCTION(0x3, "uart6"), /* TX */ + SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */ + SUNXI_FUNCTION(0x3, "uart6"), /* RX */ + SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */ + SUNXI_FUNCTION(0x3, "uart7"), /* TX */ + SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ECRS */ + SUNXI_FUNCTION(0x3, "uart7"), /* RX */ + SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ECOL */ + SUNXI_FUNCTION(0x3, "can"), /* TX */ + SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */ + SUNXI_FUNCTION(0x3, "can"), /* RX */ + SUNXI_FUNCTION(0x4, "uart1")), /* RING */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ + SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ + SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */ + SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */ + SUNXI_FUNCTION(0x3, "ac97")), /* DO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* DI */ + SUNXI_FUNCTION(0x3, "ac97")), /* DI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ + SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ + SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ + SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ + SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* TX */ + SUNXI_FUNCTION(0x3, "ir1")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* RX */ + SUNXI_FUNCTION(0x3, "ir1")), /* RX */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NWP */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ + SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */ + SUNXI_FUNCTION(0x3, "spi2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */ + SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */ + SUNXI_FUNCTION(0x3, "spi2")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ + SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ + SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ + SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ + SUNXI_FUNCTION(0x3, "sim")), /* DET */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ + SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ + SUNXI_FUNCTION(0x3, "sim")), /* RST */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "sim")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "sim")), /* SDA */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ + SUNXI_FUNCTION(0x3, "csi0")), /* PCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ + SUNXI_FUNCTION(0x3, "csi0")), /* CK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ + SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ + SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ + SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D7 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x4, "jtag")), /* MSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x4, "uart0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* CLK */ + SUNXI_FUNCTION(0x3, "csi1"), /* PCK */ + SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* ERR */ + SUNXI_FUNCTION(0x3, "csi1"), /* CK */ + SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */ + SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */ + SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */ + SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */ + SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D0 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D0 */ + SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */ + SUNXI_FUNCTION(0x5, "csi0")), /* D8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D1 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D1 */ + SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */ + SUNXI_FUNCTION(0x5, "csi0")), /* D9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D2 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D2 */ + SUNXI_FUNCTION(0x4, "uart3"), /* TX */ + SUNXI_FUNCTION(0x5, "csi0")), /* D10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D3 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D3 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RX */ + SUNXI_FUNCTION(0x5, "csi0")), /* D11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D4 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D4 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ + SUNXI_FUNCTION(0x5, "csi0")), /* D12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D5 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D5 */ + SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ + SUNXI_FUNCTION(0x5, "csi0")), /* D13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D6 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D6 */ + SUNXI_FUNCTION(0x4, "uart4"), /* TX */ + SUNXI_FUNCTION(0x5, "csi0")), /* D14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D7 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D7 */ + SUNXI_FUNCTION(0x4, "uart4"), /* RX */ + SUNXI_FUNCTION(0x5, "csi0")), /* D15 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */ + SUNXI_FUNCTION(0x4, "uart3"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ + SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */ + SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */ + SUNXI_FUNCTION(0x4, "uart4"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */ + SUNXI_FUNCTION(0x4, "uart4"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */ + SUNXI_FUNCTION(0x4, "uart5"), /* TX */ + SUNXI_FUNCTION(0x5, "ms"), /* BS */ + SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */ + SUNXI_FUNCTION(0x4, "uart5"), /* RX */ + SUNXI_FUNCTION(0x5, "ms"), /* CLK */ + SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */ + SUNXI_FUNCTION(0x5, "ms"), /* D0 */ + SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */ + SUNXI_FUNCTION(0x5, "ms"), /* D1 */ + SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */ + SUNXI_FUNCTION(0x5, "ms"), /* D2 */ + SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */ + SUNXI_FUNCTION(0x5, "ms"), /* D3 */ + SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */ + SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */ + SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */ + SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */ + SUNXI_FUNCTION(0x5, "sim"), /* RST */ + SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */ + SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */ + SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */ + SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */ + SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */ + SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */ + SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */ + SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */ + SUNXI_FUNCTION(0x5, "sim"), /* SCK */ + SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */ + SUNXI_FUNCTION(0x5, "sim"), /* SDA */ + SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */ + SUNXI_FUNCTION(0x4, "can"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */ + SUNXI_FUNCTION(0x4, "can"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D21 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */ + SUNXI_FUNCTION(0x7, "csi1")), /* D22 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */ + SUNXI_FUNCTION(0x7, "csi1")), /* D23 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */ + SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */ + SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* DE */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */ + SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */ + SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */ + SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */ + SUNXI_FUNCTION(0x3, "uart5"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart5"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart6"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ + SUNXI_FUNCTION(0x3, "uart6"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */ + SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */ + SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */ + SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ + SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */ + SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */ + SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ + SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ + SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart2"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x3, "uart2"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */ + SUNXI_FUNCTION(0x3, "uart7"), /* TX */ + SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */ + SUNXI_FUNCTION(0x3, "uart7"), /* RX */ + SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */ +}; + +static const struct sunxi_desc_pin sun5i_a10s_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */ + SUNXI_FUNCTION(0x3, "ts0"), /* CLK */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */ + SUNXI_FUNCTION(0x3, "ts0"), /* ERR */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */ + SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */ + SUNXI_FUNCTION(0x3, "ts0"), /* DLVD */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D0 */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D1 */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D2 */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D3 */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */ + SUNXI_FUNCTION(0x3, "ts0"), /* D4 */ + SUNXI_FUNCTION(0x4, "uart1"), /* DTR */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */ + SUNXI_FUNCTION(0x3, "ts0"), /* D5 */ + SUNXI_FUNCTION(0x4, "uart1"), /* DSR */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */ + SUNXI_FUNCTION(0x3, "ts0"), /* D6 */ + SUNXI_FUNCTION(0x4, "uart1"), /* DCD */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* EMDC */ + SUNXI_FUNCTION(0x3, "ts0"), /* D7 */ + SUNXI_FUNCTION(0x4, "uart1"), /* RING */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */ + SUNXI_FUNCTION(0x3, "uart1"), /* TX */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */ + SUNXI_FUNCTION(0x3, "uart1"), /* RX */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */ + SUNXI_FUNCTION(0x3, "uart1"), /* CTS */ + SUNXI_FUNCTION(0x4, "uart3"), /* TX */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ECRS */ + SUNXI_FUNCTION(0x3, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x4, "uart3"), /* RX */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ECOL */ + SUNXI_FUNCTION(0x3, "uart2")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */ + SUNXI_FUNCTION(0x3, "uart2"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */ + SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ + SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ + SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */ + SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* DO */ + SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* DI */ + SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */ + SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */ + SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */ + SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */ + SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ + SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */ + SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */ + SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NRE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NWP */ + SUNXI_FUNCTION(0x4, "uart3")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE2 */ + SUNXI_FUNCTION(0x4, "uart3")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE3 */ + SUNXI_FUNCTION(0x3, "uart2"), /* TX */ + SUNXI_FUNCTION(0x4, "uart3")), /* CTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ + SUNXI_FUNCTION(0x3, "uart2"), /* RX */ + SUNXI_FUNCTION(0x4, "uart3")), /* RTS */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x3, "uart2")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart2")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x3, "uart2")), /* CTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x3, "uart2")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x3, "emac")), /* ECRS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x3, "emac")), /* ECOL */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "emac")), /* EMDC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ + SUNXI_FUNCTION(0x3, "csi0"), /* PCK */ + SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */ + SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ + SUNXI_FUNCTION(0x3, "csi0"), /* CK */ + SUNXI_FUNCTION(0x4, "spi2"), /* CLK */ + SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ + SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */ + SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ + SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */ + SUNXI_FUNCTION(0x4, "spi2")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D0 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D2 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D3 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D4 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D5 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D6 */ + SUNXI_FUNCTION(0x4, "uart1")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D7 */ + SUNXI_FUNCTION(0x4, "uart1")), /* RX */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x4, "uart0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "gps"), /* CLK */ + SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "gps"), /* SIGN */ + SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "gps"), /* MAG */ + SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION(0x4, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* DO */ + SUNXI_FUNCTION(0x4, "uart1"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ + SUNXI_FUNCTION(0x4, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x5, "uart2"), /* RTS */ + SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ + SUNXI_FUNCTION(0x5, "uart2"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ + SUNXI_FUNCTION(0x5, "uart2"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ + SUNXI_FUNCTION(0x3, "uart3"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart3"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ + SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG13, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ + SUNXI_FUNCTION(0x3, "uart3"), /* PWM1 */ + SUNXI_FUNCTION(0x5, "uart2"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */ +}; + +static const struct sunxi_desc_pin sun5i_a13_pins[] = { + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm"), + SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */ + SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */ + SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NRE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */ + SUNXI_FUNCTION(0x4, "uart3")), /* RTS */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* DE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */ + SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */ + SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */ + SUNXI_FUNCTION(0x4, "spi2"), /* CLK */ + SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */ + SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */ + SUNXI_FUNCTION(0x4, "spi2")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D0 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D2 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D3 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D4 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D5 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D6 */ + SUNXI_FUNCTION(0x4, "uart1")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D7 */ + SUNXI_FUNCTION(0x4, "uart1")), /* RX */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION(0x4, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ + SUNXI_FUNCTION(0x3, "uart3"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart3"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ + SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ +}; + +static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { + .pins = sun4i_a10_pins, + .npins = ARRAY_SIZE(sun4i_a10_pins), +}; + +static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = { + .pins = sun5i_a10s_pins, + .npins = ARRAY_SIZE(sun5i_a10s_pins), +}; + +static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = { + .pins = sun5i_a13_pins, + .npins = ARRAY_SIZE(sun5i_a13_pins), +}; + +#endif /* __PINCTRL_SUNXI_PINS_H */ diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c index b7d8c890514..c47fd1e5450 100644 --- a/drivers/pinctrl/pinctrl-sunxi.c +++ b/drivers/pinctrl/pinctrl-sunxi.c @@ -13,10 +13,12 @@ #include <linux/io.h> #include <linux/clk.h> #include <linux/gpio.h> +#include <linux/irqdomain.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_device.h> +#include <linux/of_irq.h> #include <linux/pinctrl/consumer.h> #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinctrl.h> @@ -27,1319 +29,7 @@ #include "core.h" #include "pinctrl-sunxi.h" - -static const struct sunxi_desc_pin sun4i_a10_pins[] = { - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */ - SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */ - SUNXI_FUNCTION(0x4, "uart2")), /* RTS */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */ - SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ - SUNXI_FUNCTION(0x4, "uart2")), /* CTS */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */ - SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ - SUNXI_FUNCTION(0x4, "uart2")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */ - SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ - SUNXI_FUNCTION(0x4, "uart2")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */ - SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */ - SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */ - SUNXI_FUNCTION(0x3, "spi3")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */ - SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */ - SUNXI_FUNCTION(0x3, "spi3")), /* MISO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */ - SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */ - SUNXI_FUNCTION(0x4, "uart1")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* EMDC */ - SUNXI_FUNCTION(0x4, "uart1")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */ - SUNXI_FUNCTION(0x3, "uart6"), /* TX */ - SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */ - SUNXI_FUNCTION(0x3, "uart6"), /* RX */ - SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */ - SUNXI_FUNCTION(0x3, "uart7"), /* TX */ - SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ECRS */ - SUNXI_FUNCTION(0x3, "uart7"), /* RX */ - SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ECOL */ - SUNXI_FUNCTION(0x3, "can"), /* TX */ - SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */ - SUNXI_FUNCTION(0x3, "can"), /* RX */ - SUNXI_FUNCTION(0x4, "uart1")), /* RING */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ - SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ - SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */ - SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */ - SUNXI_FUNCTION(0x3, "ac97")), /* DO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* DI */ - SUNXI_FUNCTION(0x3, "ac97")), /* DI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ - SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ - SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ - SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ - SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "uart0"), /* TX */ - SUNXI_FUNCTION(0x3, "ir1")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "uart0"), /* RX */ - SUNXI_FUNCTION(0x3, "ir1")), /* RX */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ - SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ - SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ - SUNXI_FUNCTION(0x3, "spi0")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NWP */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ - SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */ - SUNXI_FUNCTION(0x3, "spi2")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */ - SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */ - SUNXI_FUNCTION(0x3, "spi2")), /* MISO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ - SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ - SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ - SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ - SUNXI_FUNCTION(0x3, "sim")), /* DET */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ - SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ - SUNXI_FUNCTION(0x3, "sim")), /* RST */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ - SUNXI_FUNCTION(0x3, "sim")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ - SUNXI_FUNCTION(0x3, "sim")), /* SDA */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ - SUNXI_FUNCTION(0x3, "csi0")), /* PCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ - SUNXI_FUNCTION(0x3, "csi0")), /* CK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ - SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ - SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ - SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ - SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D7 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ - SUNXI_FUNCTION(0x4, "jtag")), /* MSI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ - SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ - SUNXI_FUNCTION(0x4, "uart0")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ - SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ - SUNXI_FUNCTION(0x4, "uart0")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ - SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* CLK */ - SUNXI_FUNCTION(0x3, "csi1"), /* PCK */ - SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* ERR */ - SUNXI_FUNCTION(0x3, "csi1"), /* CK */ - SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */ - SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */ - SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */ - SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */ - SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D0 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D0 */ - SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */ - SUNXI_FUNCTION(0x5, "csi0")), /* D8 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D1 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D1 */ - SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */ - SUNXI_FUNCTION(0x5, "csi0")), /* D9 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D2 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D2 */ - SUNXI_FUNCTION(0x4, "uart3"), /* TX */ - SUNXI_FUNCTION(0x5, "csi0")), /* D10 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D3 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D3 */ - SUNXI_FUNCTION(0x4, "uart3"), /* RX */ - SUNXI_FUNCTION(0x5, "csi0")), /* D11 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D4 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D4 */ - SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ - SUNXI_FUNCTION(0x5, "csi0")), /* D12 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D5 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D5 */ - SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ - SUNXI_FUNCTION(0x5, "csi0")), /* D13 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D6 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D6 */ - SUNXI_FUNCTION(0x4, "uart4"), /* TX */ - SUNXI_FUNCTION(0x5, "csi0")), /* D14 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D7 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D7 */ - SUNXI_FUNCTION(0x4, "uart4"), /* RX */ - SUNXI_FUNCTION(0x5, "csi0")), /* D15 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */ - SUNXI_FUNCTION(0x4, "uart3"), /* TX */ - SUNXI_FUNCTION(0x7, "csi1")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */ - SUNXI_FUNCTION(0x4, "uart3"), /* RX */ - SUNXI_FUNCTION(0x7, "csi1")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */ - SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ - SUNXI_FUNCTION(0x7, "csi1")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */ - SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ - SUNXI_FUNCTION(0x7, "csi1")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */ - SUNXI_FUNCTION(0x4, "uart4"), /* TX */ - SUNXI_FUNCTION(0x7, "csi1")), /* D4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */ - SUNXI_FUNCTION(0x4, "uart4"), /* RX */ - SUNXI_FUNCTION(0x7, "csi1")), /* D5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */ - SUNXI_FUNCTION(0x4, "uart5"), /* TX */ - SUNXI_FUNCTION(0x5, "ms"), /* BS */ - SUNXI_FUNCTION(0x7, "csi1")), /* D6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */ - SUNXI_FUNCTION(0x4, "uart5"), /* RX */ - SUNXI_FUNCTION(0x5, "ms"), /* CLK */ - SUNXI_FUNCTION(0x7, "csi1")), /* D7 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */ - SUNXI_FUNCTION(0x5, "ms"), /* D0 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D8 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */ - SUNXI_FUNCTION(0x5, "ms"), /* D1 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D9 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */ - SUNXI_FUNCTION(0x5, "ms"), /* D2 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D10 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */ - SUNXI_FUNCTION(0x5, "ms"), /* D3 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D11 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */ - SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D12 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */ - SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */ - SUNXI_FUNCTION(0x5, "sim"), /* RST */ - SUNXI_FUNCTION(0x7, "csi1")), /* D13 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */ - SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */ - SUNXI_FUNCTION(0x7, "csi1")), /* D14 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */ - SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */ - SUNXI_FUNCTION(0x7, "csi1")), /* D15 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D16 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */ - SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */ - SUNXI_FUNCTION(0x7, "csi1")), /* D17 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */ - SUNXI_FUNCTION(0x5, "sim"), /* SCK */ - SUNXI_FUNCTION(0x7, "csi1")), /* D18 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */ - SUNXI_FUNCTION(0x5, "sim"), /* SDA */ - SUNXI_FUNCTION(0x7, "csi1")), /* D19 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */ - SUNXI_FUNCTION(0x4, "can"), /* TX */ - SUNXI_FUNCTION(0x7, "csi1")), /* D20 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */ - SUNXI_FUNCTION(0x4, "can"), /* RX */ - SUNXI_FUNCTION(0x7, "csi1")), /* D21 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */ - SUNXI_FUNCTION(0x7, "csi1")), /* D22 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */ - SUNXI_FUNCTION(0x7, "csi1")), /* D23 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */ - SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */ - SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* DE */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */ - SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */ - SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */ - SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */ - SUNXI_FUNCTION(0x3, "uart5")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ - SUNXI_FUNCTION(0x3, "uart5")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ - SUNXI_FUNCTION(0x3, "uart6")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ - SUNXI_FUNCTION(0x3, "uart6")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */ - SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */ - SUNXI_FUNCTION(0x4, "timer4")), /* TCLKIN0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ - SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */ - SUNXI_FUNCTION(0x4, "timer5")), /* TCLKIN1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ - SUNXI_FUNCTION(0x3, "uart2")), /* RTS */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ - SUNXI_FUNCTION(0x3, "uart2")), /* CTS */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ - SUNXI_FUNCTION(0x3, "uart2")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ - SUNXI_FUNCTION(0x3, "uart2")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */ - SUNXI_FUNCTION(0x3, "uart7"), /* TX */ - SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */ - SUNXI_FUNCTION(0x3, "uart7"), /* RX */ - SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */ -}; - -static const struct sunxi_desc_pin sun5i_a13_pins[] = { - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "pwm")), - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0")), /* RX */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ - SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ - SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ - SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */ - SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NRE */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */ - SUNXI_FUNCTION(0x4, "uart3")), /* RTS */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* DE */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */ - SUNXI_FUNCTION(0x4, "spi2")), /* CS0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */ - SUNXI_FUNCTION(0x4, "spi2")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */ - SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */ - SUNXI_FUNCTION(0x4, "spi2")), /* MISO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D0 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D2 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D3 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D4 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D5 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D6 */ - SUNXI_FUNCTION(0x4, "uart1")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D7 */ - SUNXI_FUNCTION(0x4, "uart1")), /* RX */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ - SUNXI_FUNCTION(0x4, "uart1")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ - SUNXI_FUNCTION(0x4, "uart1")), /* RX */ -/* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ - SUNXI_FUNCTION(0x3, "uart3")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ - SUNXI_FUNCTION(0x3, "uart3")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ - SUNXI_FUNCTION(0x3, "uart3")), /* CTS */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ - SUNXI_FUNCTION(0x3, "uart3")), /* RTS */ -}; - -static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { - .pins = sun4i_a10_pins, - .npins = ARRAY_SIZE(sun4i_a10_pins), -}; - -static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = { - .pins = sun5i_a13_pins, - .npins = ARRAY_SIZE(sun5i_a13_pins), -}; +#include "pinctrl-sunxi-pins.h" static struct sunxi_pinctrl_group * sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) @@ -1399,6 +89,31 @@ sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, return NULL; } +static struct sunxi_desc_function * +sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl, + const u16 pin_num, + const char *func_name) +{ + int i; + + for (i = 0; i < pctl->desc->npins; i++) { + const struct sunxi_desc_pin *pin = pctl->desc->pins + i; + + if (pin->pin.number == pin_num) { + struct sunxi_desc_function *func = pin->functions; + + while (func->name) { + if (!strcmp(func->name, func_name)) + return func; + + func++; + } + } + } + + return NULL; +} + static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) { struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); @@ -1680,37 +395,20 @@ sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, { struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct sunxi_desc_function *desc; - char pin_name[SUNXI_PIN_NAME_MAX_LEN]; const char *func; - u8 bank, pin; - int ret; - - bank = (offset) / PINS_PER_BANK; - pin = (offset) % PINS_PER_BANK; - - ret = sprintf(pin_name, "P%c%d", 'A' + bank, pin); - if (!ret) - goto error; if (input) func = "gpio_in"; else func = "gpio_out"; - desc = sunxi_pinctrl_desc_find_function_by_name(pctl, - pin_name, - func); - if (!desc) { - ret = -EINVAL; - goto error; - } + desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func); + if (!desc) + return -EINVAL; sunxi_pmx_set(pctldev, offset, desc->muxval); - ret = 0; - -error: - return ret; + return 0; } static const struct pinmux_ops sunxi_pmx_ops = { @@ -1788,6 +486,26 @@ static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, return pin; } +static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); + struct sunxi_desc_function *desc; + + if (offset > chip->ngpio) + return -ENXIO; + + desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq"); + if (!desc) + return -EINVAL; + + pctl->irq_array[desc->irqnum] = offset; + + dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", + chip->label, offset + chip->base, desc->irqnum); + + return irq_find_mapping(pctl->domain, desc->irqnum); +} + static struct gpio_chip sunxi_pinctrl_gpio_chip = { .owner = THIS_MODULE, .request = sunxi_pinctrl_gpio_request, @@ -1797,12 +515,121 @@ static struct gpio_chip sunxi_pinctrl_gpio_chip = { .get = sunxi_pinctrl_gpio_get, .set = sunxi_pinctrl_gpio_set, .of_xlate = sunxi_pinctrl_gpio_of_xlate, + .to_irq = sunxi_pinctrl_gpio_to_irq, .of_gpio_n_cells = 3, .can_sleep = 0, }; +static int sunxi_pinctrl_irq_set_type(struct irq_data *d, + unsigned int type) +{ + struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); + u32 reg = sunxi_irq_cfg_reg(d->hwirq); + u8 index = sunxi_irq_cfg_offset(d->hwirq); + u8 mode; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + mode = IRQ_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + mode = IRQ_EDGE_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + mode = IRQ_EDGE_BOTH; + break; + case IRQ_TYPE_LEVEL_HIGH: + mode = IRQ_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + mode = IRQ_LEVEL_LOW; + break; + default: + return -EINVAL; + } + + writel((mode & IRQ_CFG_IRQ_MASK) << index, pctl->membase + reg); + + return 0; +} + +static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d) +{ + struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); + u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq); + u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq); + u32 status_reg = sunxi_irq_status_reg(d->hwirq); + u8 status_idx = sunxi_irq_status_offset(d->hwirq); + u32 val; + + /* Mask the IRQ */ + val = readl(pctl->membase + ctrl_reg); + writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg); + + /* Clear the IRQ */ + writel(1 << status_idx, pctl->membase + status_reg); +} + +static void sunxi_pinctrl_irq_mask(struct irq_data *d) +{ + struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); + u32 reg = sunxi_irq_ctrl_reg(d->hwirq); + u8 idx = sunxi_irq_ctrl_offset(d->hwirq); + u32 val; + + /* Mask the IRQ */ + val = readl(pctl->membase + reg); + writel(val & ~(1 << idx), pctl->membase + reg); +} + +static void sunxi_pinctrl_irq_unmask(struct irq_data *d) +{ + struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); + struct sunxi_desc_function *func; + u32 reg = sunxi_irq_ctrl_reg(d->hwirq); + u8 idx = sunxi_irq_ctrl_offset(d->hwirq); + u32 val; + + func = sunxi_pinctrl_desc_find_function_by_pin(pctl, + pctl->irq_array[d->hwirq], + "irq"); + + /* Change muxing to INT mode */ + sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); + + /* Unmask the IRQ */ + val = readl(pctl->membase + reg); + writel(val | (1 << idx), pctl->membase + reg); +} + +static struct irq_chip sunxi_pinctrl_irq_chip = { + .irq_mask = sunxi_pinctrl_irq_mask, + .irq_mask_ack = sunxi_pinctrl_irq_mask_ack, + .irq_unmask = sunxi_pinctrl_irq_unmask, + .irq_set_type = sunxi_pinctrl_irq_set_type, +}; + +static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc) +{ + struct sunxi_pinctrl *pctl = irq_get_handler_data(irq); + const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG); + + /* Clear all interrupts */ + writel(reg, pctl->membase + IRQ_STATUS_REG); + + if (reg) { + int irqoffset; + + for_each_set_bit(irqoffset, ®, SUNXI_IRQ_NUMBER) { + int pin_irq = irq_find_mapping(pctl->domain, irqoffset); + generic_handle_irq(pin_irq); + } + } +} + static struct of_device_id sunxi_pinctrl_match[] = { { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data }, + { .compatible = "allwinner,sun5i-a10s-pinctrl", .data = (void *)&sun5i_a10s_pinctrl_data }, { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data }, {} }; @@ -1997,6 +824,31 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev) clk_prepare_enable(clk); + pctl->irq = irq_of_parse_and_map(node, 0); + if (!pctl->irq) { + ret = -EINVAL; + goto gpiochip_error; + } + + pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER, + &irq_domain_simple_ops, NULL); + if (!pctl->domain) { + dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); + ret = -ENOMEM; + goto gpiochip_error; + } + + for (i = 0; i < SUNXI_IRQ_NUMBER; i++) { + int irqno = irq_create_mapping(pctl->domain, i); + + irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip, + handle_simple_irq); + irq_set_chip_data(irqno, pctl); + }; + + irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler); + irq_set_handler_data(pctl->irq, pctl); + dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); return 0; diff --git a/drivers/pinctrl/pinctrl-sunxi.h b/drivers/pinctrl/pinctrl-sunxi.h index e921621059c..d68047d8f69 100644 --- a/drivers/pinctrl/pinctrl-sunxi.h +++ b/drivers/pinctrl/pinctrl-sunxi.h @@ -344,9 +344,31 @@ #define PULL_PINS_BITS 2 #define PULL_PINS_MASK 0x03 +#define SUNXI_IRQ_NUMBER 32 + +#define IRQ_CFG_REG 0x200 +#define IRQ_CFG_IRQ_PER_REG 8 +#define IRQ_CFG_IRQ_BITS 4 +#define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1) +#define IRQ_CTRL_REG 0x210 +#define IRQ_CTRL_IRQ_PER_REG 32 +#define IRQ_CTRL_IRQ_BITS 1 +#define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1) +#define IRQ_STATUS_REG 0x214 +#define IRQ_STATUS_IRQ_PER_REG 32 +#define IRQ_STATUS_IRQ_BITS 1 +#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1) + +#define IRQ_EDGE_RISING 0x00 +#define IRQ_EDGE_FALLING 0x01 +#define IRQ_LEVEL_HIGH 0x02 +#define IRQ_LEVEL_LOW 0x03 +#define IRQ_EDGE_BOTH 0x04 + struct sunxi_desc_function { const char *name; u8 muxval; + u8 irqnum; }; struct sunxi_desc_pin { @@ -378,10 +400,13 @@ struct sunxi_pinctrl { struct gpio_chip *chip; struct sunxi_pinctrl_desc *desc; struct device *dev; + struct irq_domain *domain; struct sunxi_pinctrl_function *functions; unsigned nfunctions; struct sunxi_pinctrl_group *groups; unsigned ngroups; + int irq; + int irq_array[SUNXI_IRQ_NUMBER]; struct pinctrl_dev *pctl_dev; }; @@ -398,6 +423,13 @@ struct sunxi_pinctrl { .muxval = _val, \ } +#define SUNXI_FUNCTION_IRQ(_val, _irq) \ + { \ + .name = "irq", \ + .muxval = _val, \ + .irqnum = _irq, \ + } + /* * The sunXi PIO registers are organized as is: * 0x00 - 0x0c Muxing values. @@ -475,4 +507,40 @@ static inline u32 sunxi_pull_offset(u16 pin) return pin_num * PULL_PINS_BITS; } +static inline u32 sunxi_irq_cfg_reg(u16 irq) +{ + u8 reg = irq / IRQ_CFG_IRQ_PER_REG; + return reg + IRQ_CFG_REG; +} + +static inline u32 sunxi_irq_cfg_offset(u16 irq) +{ + u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG; + return irq_num * IRQ_CFG_IRQ_BITS; +} + +static inline u32 sunxi_irq_ctrl_reg(u16 irq) +{ + u8 reg = irq / IRQ_CTRL_IRQ_PER_REG; + return reg + IRQ_CTRL_REG; +} + +static inline u32 sunxi_irq_ctrl_offset(u16 irq) +{ + u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG; + return irq_num * IRQ_CTRL_IRQ_BITS; +} + +static inline u32 sunxi_irq_status_reg(u16 irq) +{ + u8 reg = irq / IRQ_STATUS_IRQ_PER_REG; + return reg + IRQ_STATUS_REG; +} + +static inline u32 sunxi_irq_status_offset(u16 irq) +{ + u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG; + return irq_num * IRQ_STATUS_IRQ_BITS; +} + #endif /* __PINCTRL_SUNXI_H */ diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c new file mode 100644 index 00000000000..d4f12cc556b --- /dev/null +++ b/drivers/pinctrl/pinctrl-tz1090-pdc.c @@ -0,0 +1,1024 @@ +/* + * Pinctrl driver for the Toumaz Xenif TZ1090 PowerDown Controller pins + * + * Copyright (c) 2013, Imagination Technologies Ltd. + * + * Derived from Tegra code: + * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. + * + * Derived from code: + * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2010 NVIDIA Corporation + * Copyright (C) 2009-2011 ST-Ericsson AB + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/slab.h> + +/* + * The registers may be shared with other threads/cores, so we need to use the + * metag global lock2 for atomicity. + */ +#include <asm/global_lock.h> + +#include "core.h" +#include "pinconf.h" + +/* Register offsets from bank base address */ +#define REG_GPIO_CONTROL0 0x00 +#define REG_GPIO_CONTROL2 0x08 + +/* Register field information */ +#define REG_GPIO_CONTROL2_PU_PD_S 16 +#define REG_GPIO_CONTROL2_PDC_POS_S 4 +#define REG_GPIO_CONTROL2_PDC_DR_S 2 +#define REG_GPIO_CONTROL2_PDC_SR_S 1 +#define REG_GPIO_CONTROL2_PDC_SCHMITT_S 0 + +/* PU_PD field values */ +#define REG_PU_PD_TRISTATE 0 +#define REG_PU_PD_UP 1 +#define REG_PU_PD_DOWN 2 +#define REG_PU_PD_REPEATER 3 + +/* DR field values */ +#define REG_DR_2mA 0 +#define REG_DR_4mA 1 +#define REG_DR_8mA 2 +#define REG_DR_12mA 3 + +/** + * struct tz1090_pdc_function - TZ1090 PDC pinctrl mux function + * @name: The name of the function, exported to pinctrl core. + * @groups: An array of pin groups that may select this function. + * @ngroups: The number of entries in @groups. + */ +struct tz1090_pdc_function { + const char *name; + const char * const *groups; + unsigned int ngroups; +}; + +/** + * struct tz1090_pdc_pingroup - TZ1090 PDC pin group + * @name: Name of pin group. + * @pins: Array of pin numbers in this pin group. + * @npins: Number of pins in this pin group. + * @func: Function enabled by the mux. + * @reg: Mux register offset. + * @bit: Mux register bit. + * @drv: Drive control supported, otherwise it's a mux. + * This means Schmitt, Slew, and Drive strength. + * + * A representation of a group of pins (possibly just one pin) in the TZ1090 + * PDC pin controller. Each group allows some parameter or parameters to be + * configured. The most common is mux function selection. + */ +struct tz1090_pdc_pingroup { + const char *name; + const unsigned int *pins; + unsigned int npins; + int func; + u16 reg; + u8 bit; + bool drv; +}; + +/* + * All PDC pins can be GPIOs. Define these first to match how the GPIO driver + * names/numbers its pins. + */ + +enum tz1090_pdc_pin { + TZ1090_PDC_PIN_GPIO0, + TZ1090_PDC_PIN_GPIO1, + TZ1090_PDC_PIN_SYS_WAKE0, + TZ1090_PDC_PIN_SYS_WAKE1, + TZ1090_PDC_PIN_SYS_WAKE2, + TZ1090_PDC_PIN_IR_DATA, + TZ1090_PDC_PIN_EXT_POWER, +}; + +/* Pin names */ + +static const struct pinctrl_pin_desc tz1090_pdc_pins[] = { + /* PDC GPIOs */ + PINCTRL_PIN(TZ1090_PDC_PIN_GPIO0, "gpio0"), + PINCTRL_PIN(TZ1090_PDC_PIN_GPIO1, "gpio1"), + PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE0, "sys_wake0"), + PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE1, "sys_wake1"), + PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE2, "sys_wake2"), + PINCTRL_PIN(TZ1090_PDC_PIN_IR_DATA, "ir_data"), + PINCTRL_PIN(TZ1090_PDC_PIN_EXT_POWER, "ext_power"), +}; + +/* Pin group pins */ + +static const unsigned int gpio0_pins[] = { + TZ1090_PDC_PIN_GPIO0, +}; + +static const unsigned int gpio1_pins[] = { + TZ1090_PDC_PIN_GPIO1, +}; + +static const unsigned int pdc_pins[] = { + TZ1090_PDC_PIN_GPIO0, + TZ1090_PDC_PIN_GPIO1, + TZ1090_PDC_PIN_SYS_WAKE0, + TZ1090_PDC_PIN_SYS_WAKE1, + TZ1090_PDC_PIN_SYS_WAKE2, + TZ1090_PDC_PIN_IR_DATA, + TZ1090_PDC_PIN_EXT_POWER, +}; + +/* Mux functions */ + +enum tz1090_pdc_mux { + /* PDC_GPIO0 mux */ + TZ1090_PDC_MUX_IR_MOD_STABLE_OUT, + /* PDC_GPIO1 mux */ + TZ1090_PDC_MUX_IR_MOD_POWER_OUT, +}; + +/* Pin groups a function can be muxed to */ + +static const char * const gpio0_groups[] = { + "gpio0", +}; + +static const char * const gpio1_groups[] = { + "gpio1", +}; + +#define FUNCTION(mux, fname, group) \ + [(TZ1090_PDC_MUX_ ## mux)] = { \ + .name = #fname, \ + .groups = group##_groups, \ + .ngroups = ARRAY_SIZE(group##_groups), \ + } + +/* Must correlate with enum tz1090_pdc_mux */ +static const struct tz1090_pdc_function tz1090_pdc_functions[] = { + /* MUX fn pingroups */ + FUNCTION(IR_MOD_STABLE_OUT, ir_mod_stable_out, gpio0), + FUNCTION(IR_MOD_POWER_OUT, ir_mod_power_out, gpio1), +}; + +/** + * MUX_PG() - Initialise a pin group with mux control + * @pg_name: Pin group name (stringified, _pins appended to get pins array) + * @f0: Function 0 (TZ1090_PDC_MUX_ is prepended) + * @mux_r: Mux register (REG_PINCTRL_ is prepended) + * @mux_b: Bit number in register of mux field + */ +#define MUX_PG(pg_name, f0, mux_r, mux_b) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .func = TZ1090_PDC_MUX_ ## f0, \ + .reg = (REG_ ## mux_r), \ + .bit = (mux_b), \ + } + +/** + * DRV_PG() - Initialise a pin group with drive control + * @pg_name: Pin group name (stringified, _pins appended to get pins array) + */ +#define DRV_PG(pg_name) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .drv = true, \ + } + +static const struct tz1090_pdc_pingroup tz1090_pdc_groups[] = { + /* Muxing pin groups */ + /* pg_name, f0, mux register, mux bit */ + MUX_PG(gpio0, IR_MOD_STABLE_OUT, GPIO_CONTROL0, 7), + MUX_PG(gpio1, IR_MOD_POWER_OUT, GPIO_CONTROL0, 6), + + /* Drive pin groups */ + /* pg_name */ + DRV_PG(pdc), +}; + +/** + * struct tz1090_pdc_pmx - Private pinctrl data + * @dev: Platform device + * @pctl: Pin control device + * @regs: Register region + * @lock: Lock protecting coherency of mux_en and gpio_en + * @mux_en: Muxes that have been enabled + * @gpio_en: Muxable GPIOs that have been enabled + */ +struct tz1090_pdc_pmx { + struct device *dev; + struct pinctrl_dev *pctl; + void __iomem *regs; + spinlock_t lock; + u32 mux_en; + u32 gpio_en; +}; + +static inline u32 pmx_read(struct tz1090_pdc_pmx *pmx, u32 reg) +{ + return ioread32(pmx->regs + reg); +} + +static inline void pmx_write(struct tz1090_pdc_pmx *pmx, u32 val, u32 reg) +{ + iowrite32(val, pmx->regs + reg); +} + +/* + * Pin control operations + */ + +static int tz1090_pdc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(tz1090_pdc_groups); +} + +static const char *tz1090_pdc_pinctrl_get_group_name(struct pinctrl_dev *pctl, + unsigned int group) +{ + return tz1090_pdc_groups[group].name; +} + +static int tz1090_pdc_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group, + const unsigned int **pins, + unsigned int *num_pins) +{ + *pins = tz1090_pdc_groups[group].pins; + *num_pins = tz1090_pdc_groups[group].npins; + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void tz1090_pdc_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned int offset) +{ + seq_printf(s, " %s", dev_name(pctldev->dev)); +} +#endif + +static int reserve_map(struct device *dev, struct pinctrl_map **map, + unsigned int *reserved_maps, unsigned int *num_maps, + unsigned int reserve) +{ + unsigned int old_num = *reserved_maps; + unsigned int new_num = *num_maps + reserve; + struct pinctrl_map *new_map; + + if (old_num >= new_num) + return 0; + + new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); + if (!new_map) { + dev_err(dev, "krealloc(map) failed\n"); + return -ENOMEM; + } + + memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); + + *map = new_map; + *reserved_maps = new_num; + + return 0; +} + +static int add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps, + unsigned int *num_maps, const char *group, + const char *function) +{ + if (WARN_ON(*num_maps == *reserved_maps)) + return -ENOSPC; + + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.group = group; + (*map)[*num_maps].data.mux.function = function; + (*num_maps)++; + + return 0; +} + +/** + * get_group_selector() - returns the group selector for a group + * @pin_group: the pin group to look up + * + * This is the same as pinctrl_get_group_selector except it doesn't produce an + * error message if the group isn't found or debug messages. + */ +static int get_group_selector(const char *pin_group) +{ + unsigned int group; + + for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group) + if (!strcmp(tz1090_pdc_groups[group].name, pin_group)) + return group; + + return -EINVAL; +} + +static int add_map_configs(struct device *dev, + struct pinctrl_map **map, + unsigned int *reserved_maps, unsigned int *num_maps, + const char *group, unsigned long *configs, + unsigned int num_configs) +{ + unsigned long *dup_configs; + enum pinctrl_map_type type; + + if (WARN_ON(*num_maps == *reserved_maps)) + return -ENOSPC; + + dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), + GFP_KERNEL); + if (!dup_configs) { + dev_err(dev, "kmemdup(configs) failed\n"); + return -ENOMEM; + } + + /* + * We support both pins and pin groups, but we need to figure out which + * one we have. + */ + if (get_group_selector(group) >= 0) + type = PIN_MAP_TYPE_CONFIGS_GROUP; + else + type = PIN_MAP_TYPE_CONFIGS_PIN; + (*map)[*num_maps].type = type; + (*map)[*num_maps].data.configs.group_or_pin = group; + (*map)[*num_maps].data.configs.configs = dup_configs; + (*map)[*num_maps].data.configs.num_configs = num_configs; + (*num_maps)++; + + return 0; +} + +static void tz1090_pdc_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, + unsigned int num_maps) +{ + int i; + + for (i = 0; i < num_maps; i++) + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) + kfree(map[i].data.configs.configs); + + kfree(map); +} + +static int tz1090_pdc_pinctrl_dt_subnode_to_map(struct device *dev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *reserved_maps, + unsigned int *num_maps) +{ + int ret; + const char *function; + unsigned long *configs = NULL; + unsigned int num_configs = 0; + unsigned int reserve; + struct property *prop; + const char *group; + + ret = of_property_read_string(np, "tz1090,function", &function); + if (ret < 0) { + /* EINVAL=missing, which is fine since it's optional */ + if (ret != -EINVAL) + dev_err(dev, + "could not parse property function\n"); + function = NULL; + } + + ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs); + if (ret) + return ret; + + reserve = 0; + if (function != NULL) + reserve++; + if (num_configs) + reserve++; + ret = of_property_count_strings(np, "tz1090,pins"); + if (ret < 0) { + dev_err(dev, "could not parse property pins\n"); + goto exit; + } + reserve *= ret; + + ret = reserve_map(dev, map, reserved_maps, num_maps, reserve); + if (ret < 0) + goto exit; + + of_property_for_each_string(np, "tz1090,pins", prop, group) { + if (function) { + ret = add_map_mux(map, reserved_maps, num_maps, + group, function); + if (ret < 0) + goto exit; + } + + if (num_configs) { + ret = add_map_configs(dev, map, reserved_maps, + num_maps, group, configs, + num_configs); + if (ret < 0) + goto exit; + } + } + + ret = 0; + +exit: + kfree(configs); + return ret; +} + +static int tz1090_pdc_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + unsigned int reserved_maps; + struct device_node *np; + int ret; + + reserved_maps = 0; + *map = NULL; + *num_maps = 0; + + for_each_child_of_node(np_config, np) { + ret = tz1090_pdc_pinctrl_dt_subnode_to_map(pctldev->dev, np, + map, &reserved_maps, + num_maps); + if (ret < 0) { + tz1090_pdc_pinctrl_dt_free_map(pctldev, *map, + *num_maps); + return ret; + } + } + + return 0; +} + +static struct pinctrl_ops tz1090_pdc_pinctrl_ops = { + .get_groups_count = tz1090_pdc_pinctrl_get_groups_count, + .get_group_name = tz1090_pdc_pinctrl_get_group_name, + .get_group_pins = tz1090_pdc_pinctrl_get_group_pins, +#ifdef CONFIG_DEBUG_FS + .pin_dbg_show = tz1090_pdc_pinctrl_pin_dbg_show, +#endif + .dt_node_to_map = tz1090_pdc_pinctrl_dt_node_to_map, + .dt_free_map = tz1090_pdc_pinctrl_dt_free_map, +}; + +/* + * Pin mux operations + */ + +static int tz1090_pdc_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(tz1090_pdc_functions); +} + +static const char *tz1090_pdc_pinctrl_get_func_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + return tz1090_pdc_functions[function].name; +} + +static int tz1090_pdc_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char * const **groups, + unsigned int * const num_groups) +{ + *groups = tz1090_pdc_functions[function].groups; + *num_groups = tz1090_pdc_functions[function].ngroups; + + return 0; +} + +/** + * tz1090_pdc_pinctrl_mux() - update mux bit + * @pmx: Pinmux data + * @grp: Pin mux group + */ +static void tz1090_pdc_pinctrl_mux(struct tz1090_pdc_pmx *pmx, + const struct tz1090_pdc_pingroup *grp) +{ + u32 reg, select; + unsigned int pin_shift = grp->pins[0]; + unsigned long flags; + + /* select = mux && !gpio */ + select = ((pmx->mux_en & ~pmx->gpio_en) >> pin_shift) & 1; + + /* set up the mux */ + __global_lock2(flags); + reg = pmx_read(pmx, grp->reg); + reg &= ~BIT(grp->bit); + reg |= select << grp->bit; + pmx_write(pmx, reg, grp->reg); + __global_unlock2(flags); +} + +static int tz1090_pdc_pinctrl_enable(struct pinctrl_dev *pctldev, + unsigned int function, unsigned int group) +{ + struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group]; + + dev_dbg(pctldev->dev, "%s(func=%u (%s), group=%u (%s))\n", + __func__, + function, tz1090_pdc_functions[function].name, + group, tz1090_pdc_groups[group].name); + + /* is it even a mux? */ + if (grp->drv) + return -EINVAL; + + /* does this group even control the function? */ + if (function != grp->func) + return -EINVAL; + + /* record the pin being muxed and update mux bit */ + spin_lock(&pmx->lock); + pmx->mux_en |= BIT(grp->pins[0]); + tz1090_pdc_pinctrl_mux(pmx, grp); + spin_unlock(&pmx->lock); + return 0; +} + +static void tz1090_pdc_pinctrl_disable(struct pinctrl_dev *pctldev, + unsigned int function, + unsigned int group) +{ + struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group]; + + dev_dbg(pctldev->dev, "%s(func=%u (%s), group=%u (%s))\n", + __func__, + function, tz1090_pdc_functions[function].name, + group, tz1090_pdc_groups[group].name); + + /* is it even a mux? */ + if (grp->drv) + return; + + /* does this group even control the function? */ + if (function != grp->func) + return; + + /* record the pin being unmuxed and update mux bit */ + spin_lock(&pmx->lock); + pmx->mux_en &= ~BIT(grp->pins[0]); + tz1090_pdc_pinctrl_mux(pmx, grp); + spin_unlock(&pmx->lock); +} + +static const struct tz1090_pdc_pingroup *find_mux_group( + struct tz1090_pdc_pmx *pmx, + unsigned int pin) +{ + const struct tz1090_pdc_pingroup *grp; + unsigned int group; + + grp = tz1090_pdc_groups; + for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group, ++grp) { + /* only match muxes */ + if (grp->drv) + continue; + + /* with a matching pin */ + if (grp->pins[0] == pin) + return grp; + } + + return NULL; +} + +static int tz1090_pdc_pinctrl_gpio_request_enable( + struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin); + + if (grp) { + /* record the pin in GPIO use and update mux bit */ + spin_lock(&pmx->lock); + pmx->gpio_en |= BIT(pin); + tz1090_pdc_pinctrl_mux(pmx, grp); + spin_unlock(&pmx->lock); + } + return 0; +} + +static void tz1090_pdc_pinctrl_gpio_disable_free( + struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin); + + if (grp) { + /* record the pin not in GPIO use and update mux bit */ + spin_lock(&pmx->lock); + pmx->gpio_en &= ~BIT(pin); + tz1090_pdc_pinctrl_mux(pmx, grp); + spin_unlock(&pmx->lock); + } +} + +static struct pinmux_ops tz1090_pdc_pinmux_ops = { + .get_functions_count = tz1090_pdc_pinctrl_get_funcs_count, + .get_function_name = tz1090_pdc_pinctrl_get_func_name, + .get_function_groups = tz1090_pdc_pinctrl_get_func_groups, + .enable = tz1090_pdc_pinctrl_enable, + .disable = tz1090_pdc_pinctrl_disable, + .gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable, + .gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free, +}; + +/* + * Pin config operations + */ + +static int tz1090_pdc_pinconf_reg(struct pinctrl_dev *pctldev, + unsigned int pin, + enum pin_config_param param, + bool report_err, + u32 *reg, u32 *width, u32 *mask, u32 *shift, + u32 *val) +{ + /* Find information about parameter's register */ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + *val = REG_PU_PD_TRISTATE; + break; + case PIN_CONFIG_BIAS_PULL_UP: + *val = REG_PU_PD_UP; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + *val = REG_PU_PD_DOWN; + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + *val = REG_PU_PD_REPEATER; + break; + default: + return -ENOTSUPP; + }; + + /* Only input bias parameters supported */ + *reg = REG_GPIO_CONTROL2; + *shift = REG_GPIO_CONTROL2_PU_PD_S + pin*2; + *width = 2; + + /* Calculate field information */ + *mask = (BIT(*width) - 1) << *shift; + + return 0; +} + +static int tz1090_pdc_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + int ret; + u32 reg, width, mask, shift, val, tmp, arg; + + /* Get register information */ + ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true, + ®, &width, &mask, &shift, &val); + if (ret < 0) + return ret; + + /* Extract field from register */ + tmp = pmx_read(pmx, reg); + arg = ((tmp & mask) >> shift) == val; + + /* Config not active */ + if (!arg) + return -EINVAL; + + /* And pack config */ + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int tz1090_pdc_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long config) +{ + struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(config); + unsigned int arg = pinconf_to_config_argument(config); + int ret; + u32 reg, width, mask, shift, val, tmp; + unsigned long flags; + + dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n", + __func__, tz1090_pdc_pins[pin].name, config); + + /* Get register information */ + ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true, + ®, &width, &mask, &shift, &val); + if (ret < 0) + return ret; + + /* Unpack argument and range check it */ + if (arg > 1) { + dev_dbg(pctldev->dev, "%s: arg %u out of range\n", + __func__, arg); + return -EINVAL; + } + + /* Write register field */ + __global_lock2(flags); + tmp = pmx_read(pmx, reg); + tmp &= ~mask; + if (arg) + tmp |= val << shift; + pmx_write(pmx, tmp, reg); + __global_unlock2(flags); + + return 0; +} + +static const int tz1090_pdc_boolean_map[] = { + [0] = -EINVAL, + [1] = 1, +}; + +static const int tz1090_pdc_dr_map[] = { + [REG_DR_2mA] = 2, + [REG_DR_4mA] = 4, + [REG_DR_8mA] = 8, + [REG_DR_12mA] = 12, +}; + +static int tz1090_pdc_pinconf_group_reg(struct pinctrl_dev *pctldev, + const struct tz1090_pdc_pingroup *g, + enum pin_config_param param, + bool report_err, u32 *reg, u32 *width, + u32 *mask, u32 *shift, const int **map) +{ + /* Drive configuration applies in groups, but not to all groups. */ + if (!g->drv) { + if (report_err) + dev_dbg(pctldev->dev, + "%s: group %s has no drive control\n", + __func__, g->name); + return -ENOTSUPP; + } + + /* Find information about drive parameter's register */ + *reg = REG_GPIO_CONTROL2; + switch (param) { + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + *shift = REG_GPIO_CONTROL2_PDC_SCHMITT_S; + *width = 1; + *map = tz1090_pdc_boolean_map; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + *shift = REG_GPIO_CONTROL2_PDC_DR_S; + *width = 2; + *map = tz1090_pdc_dr_map; + break; + case PIN_CONFIG_LOW_POWER_MODE: + *shift = REG_GPIO_CONTROL2_PDC_POS_S; + *width = 1; + *map = tz1090_pdc_boolean_map; + break; + default: + return -ENOTSUPP; + }; + + /* Calculate field information */ + *mask = (BIT(*width) - 1) << *shift; + + return 0; +} + +static int tz1090_pdc_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *config) +{ + struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group]; + enum pin_config_param param = pinconf_to_config_param(*config); + int ret, arg; + u32 reg, width, mask, shift, val; + const int *map; + + /* Get register information */ + ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true, + ®, &width, &mask, &shift, &map); + if (ret < 0) + return ret; + + /* Extract field from register */ + val = pmx_read(pmx, reg); + arg = map[(val & mask) >> shift]; + if (arg < 0) + return arg; + + /* And pack config */ + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int tz1090_pdc_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long config) +{ + struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group]; + enum pin_config_param param = pinconf_to_config_param(config); + const unsigned int *pit; + unsigned int i; + int ret, arg; + u32 reg, width, mask, shift, val; + unsigned long flags; + const int *map; + + dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n", + __func__, g->name, config); + + /* Get register information */ + ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true, + ®, &width, &mask, &shift, &map); + if (ret < 0) { + /* + * Maybe we're trying to set a per-pin configuration of a group, + * so do the pins one by one. This is mainly as a convenience. + */ + for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) { + ret = tz1090_pdc_pinconf_set(pctldev, *pit, config); + if (ret) + return ret; + } + return 0; + } + + /* Unpack argument and map it to register value */ + arg = pinconf_to_config_argument(config); + for (i = 0; i < BIT(width); ++i) { + if (map[i] == arg || (map[i] == -EINVAL && !arg)) { + /* Write register field */ + __global_lock2(flags); + val = pmx_read(pmx, reg); + val &= ~mask; + val |= i << shift; + pmx_write(pmx, val, reg); + __global_unlock2(flags); + return 0; + } + } + + dev_dbg(pctldev->dev, "%s: arg %u not supported\n", + __func__, arg); + return 0; +} + +static struct pinconf_ops tz1090_pdc_pinconf_ops = { + .is_generic = true, + .pin_config_get = tz1090_pdc_pinconf_get, + .pin_config_set = tz1090_pdc_pinconf_set, + .pin_config_group_get = tz1090_pdc_pinconf_group_get, + .pin_config_group_set = tz1090_pdc_pinconf_group_set, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + +/* + * Pin control driver setup + */ + +static struct pinctrl_desc tz1090_pdc_pinctrl_desc = { + .pctlops = &tz1090_pdc_pinctrl_ops, + .pmxops = &tz1090_pdc_pinmux_ops, + .confops = &tz1090_pdc_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int tz1090_pdc_pinctrl_probe(struct platform_device *pdev) +{ + struct tz1090_pdc_pmx *pmx; + struct resource *res; + + pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); + if (!pmx) { + dev_err(&pdev->dev, "Can't alloc tz1090_pdc_pmx\n"); + return -ENOMEM; + } + pmx->dev = &pdev->dev; + spin_lock_init(&pmx->lock); + + tz1090_pdc_pinctrl_desc.name = dev_name(&pdev->dev); + tz1090_pdc_pinctrl_desc.pins = tz1090_pdc_pins; + tz1090_pdc_pinctrl_desc.npins = ARRAY_SIZE(tz1090_pdc_pins); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Missing MEM resource\n"); + return -ENODEV; + } + + if (!devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), + dev_name(&pdev->dev))) { + dev_err(&pdev->dev, + "Couldn't request MEM resource\n"); + return -ENODEV; + } + + pmx->regs = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (!pmx->regs) { + dev_err(&pdev->dev, "Couldn't ioremap regs\n"); + return -ENODEV; + } + + pmx->pctl = pinctrl_register(&tz1090_pdc_pinctrl_desc, &pdev->dev, pmx); + if (!pmx->pctl) { + dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); + return -ENODEV; + } + + platform_set_drvdata(pdev, pmx); + + dev_info(&pdev->dev, "TZ1090 PDC pinctrl driver initialised\n"); + + return 0; +} + +static int tz1090_pdc_pinctrl_remove(struct platform_device *pdev) +{ + struct tz1090_pdc_pmx *pmx = platform_get_drvdata(pdev); + + pinctrl_unregister(pmx->pctl); + + return 0; +} + +static struct of_device_id tz1090_pdc_pinctrl_of_match[] = { + { .compatible = "img,tz1090-pdc-pinctrl", }, + { }, +}; + +static struct platform_driver tz1090_pdc_pinctrl_driver = { + .driver = { + .name = "tz1090-pdc-pinctrl", + .owner = THIS_MODULE, + .of_match_table = tz1090_pdc_pinctrl_of_match, + }, + .probe = tz1090_pdc_pinctrl_probe, + .remove = tz1090_pdc_pinctrl_remove, +}; + +static int __init tz1090_pdc_pinctrl_init(void) +{ + return platform_driver_register(&tz1090_pdc_pinctrl_driver); +} +arch_initcall(tz1090_pdc_pinctrl_init); + +static void __exit tz1090_pdc_pinctrl_exit(void) +{ + platform_driver_unregister(&tz1090_pdc_pinctrl_driver); +} +module_exit(tz1090_pdc_pinctrl_exit); + +MODULE_AUTHOR("Imagination Technologies Ltd."); +MODULE_DESCRIPTION("Toumaz Xenif TZ1090 PDC pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, tz1090_pdc_pinctrl_of_match); diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c new file mode 100644 index 00000000000..4edae08a0a6 --- /dev/null +++ b/drivers/pinctrl/pinctrl-tz1090.c @@ -0,0 +1,2072 @@ +/* + * Pinctrl driver for the Toumaz Xenif TZ1090 SoC + * + * Copyright (c) 2013, Imagination Technologies Ltd. + * + * Derived from Tegra code: + * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. + * + * Derived from code: + * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2010 NVIDIA Corporation + * Copyright (C) 2009-2011 ST-Ericsson AB + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/slab.h> +#include <linux/spinlock.h> + +/* + * The registers may be shared with other threads/cores, so we need to use the + * metag global lock2 for atomicity. + */ +#include <asm/global_lock.h> + +#include "core.h" +#include "pinconf.h" + +/* Register offsets from bank base address */ +#define REG_PINCTRL_SELECT 0x10 +#define REG_PINCTRL_SCHMITT 0x90 +#define REG_PINCTRL_PU_PD 0xa0 +#define REG_PINCTRL_SR 0xc0 +#define REG_PINCTRL_DR 0xd0 +#define REG_PINCTRL_IF_CTL 0xe0 + +/* REG_PINCTRL_PU_PD field values */ +#define REG_PU_PD_TRISTATE 0 +#define REG_PU_PD_UP 1 +#define REG_PU_PD_DOWN 2 +#define REG_PU_PD_REPEATER 3 + +/* REG_PINCTRL_DR field values */ +#define REG_DR_2mA 0 +#define REG_DR_4mA 1 +#define REG_DR_8mA 2 +#define REG_DR_12mA 3 + +/** + * struct tz1090_function - TZ1090 pinctrl mux function + * @name: The name of the function, exported to pinctrl core. + * @groups: An array of pin groups that may select this function. + * @ngroups: The number of entries in @groups. + */ +struct tz1090_function { + const char *name; + const char * const *groups; + unsigned int ngroups; +}; + +/** + * struct tz1090_muxdesc - TZ1090 individual mux description + * @funcs: Function for each mux value. + * @reg: Mux register offset. 0 if unsupported. + * @bit: Mux register bit. 0 if unsupported. + * @width: Mux field width. 0 if unsupported. + * + * A representation of a group of signals (possibly just one signal) in the + * TZ1090 which can be muxed to a set of functions or sub muxes. + */ +struct tz1090_muxdesc { + int funcs[5]; + u16 reg; + u8 bit; + u8 width; +}; + +/** + * struct tz1090_pingroup - TZ1090 pin group + * @name: Name of pin group. + * @pins: Array of pin numbers in this pin group. + * @npins: Number of pins in this pin group. + * @mux: Top level mux. + * @drv: Drive control supported, 0 if unsupported. + * This means Schmitt, Slew, and Drive strength. + * @slw_bit: Slew register bit. 0 if unsupported. + * The same bit is used for Schmitt, and Drive (*2). + * @func: Currently muxed function. + * @func_count: Number of pins using current mux function. + * + * A representation of a group of pins (possibly just one pin) in the TZ1090 + * pin controller. Each group allows some parameter or parameters to be + * configured. The most common is mux function selection. + */ +struct tz1090_pingroup { + const char *name; + const unsigned int *pins; + unsigned int npins; + struct tz1090_muxdesc mux; + + bool drv; + u8 slw_bit; + + int func; + unsigned int func_count; +}; + +/* + * Most pins affected by the pinmux can also be GPIOs. Define these first. + * These must match how the GPIO driver names/numbers its pins. + */ + +enum tz1090_pin { + /* GPIO pins */ + TZ1090_PIN_SDIO_CLK, + TZ1090_PIN_SDIO_CMD, + TZ1090_PIN_SDIO_D0, + TZ1090_PIN_SDIO_D1, + TZ1090_PIN_SDIO_D2, + TZ1090_PIN_SDIO_D3, + TZ1090_PIN_SDH_CD, + TZ1090_PIN_SDH_WP, + TZ1090_PIN_SPI0_MCLK, + TZ1090_PIN_SPI0_CS0, + TZ1090_PIN_SPI0_CS1, + TZ1090_PIN_SPI0_CS2, + TZ1090_PIN_SPI0_DOUT, + TZ1090_PIN_SPI0_DIN, + TZ1090_PIN_SPI1_MCLK, + TZ1090_PIN_SPI1_CS0, + TZ1090_PIN_SPI1_CS1, + TZ1090_PIN_SPI1_CS2, + TZ1090_PIN_SPI1_DOUT, + TZ1090_PIN_SPI1_DIN, + TZ1090_PIN_UART0_RXD, + TZ1090_PIN_UART0_TXD, + TZ1090_PIN_UART0_CTS, + TZ1090_PIN_UART0_RTS, + TZ1090_PIN_UART1_RXD, + TZ1090_PIN_UART1_TXD, + TZ1090_PIN_SCB0_SDAT, + TZ1090_PIN_SCB0_SCLK, + TZ1090_PIN_SCB1_SDAT, + TZ1090_PIN_SCB1_SCLK, + TZ1090_PIN_SCB2_SDAT, + TZ1090_PIN_SCB2_SCLK, + TZ1090_PIN_I2S_MCLK, + TZ1090_PIN_I2S_BCLK_OUT, + TZ1090_PIN_I2S_LRCLK_OUT, + TZ1090_PIN_I2S_DOUT0, + TZ1090_PIN_I2S_DOUT1, + TZ1090_PIN_I2S_DOUT2, + TZ1090_PIN_I2S_DIN, + TZ1090_PIN_PDM_A, + TZ1090_PIN_PDM_B, + TZ1090_PIN_PDM_C, + TZ1090_PIN_PDM_D, + TZ1090_PIN_TFT_RED0, + TZ1090_PIN_TFT_RED1, + TZ1090_PIN_TFT_RED2, + TZ1090_PIN_TFT_RED3, + TZ1090_PIN_TFT_RED4, + TZ1090_PIN_TFT_RED5, + TZ1090_PIN_TFT_RED6, + TZ1090_PIN_TFT_RED7, + TZ1090_PIN_TFT_GREEN0, + TZ1090_PIN_TFT_GREEN1, + TZ1090_PIN_TFT_GREEN2, + TZ1090_PIN_TFT_GREEN3, + TZ1090_PIN_TFT_GREEN4, + TZ1090_PIN_TFT_GREEN5, + TZ1090_PIN_TFT_GREEN6, + TZ1090_PIN_TFT_GREEN7, + TZ1090_PIN_TFT_BLUE0, + TZ1090_PIN_TFT_BLUE1, + TZ1090_PIN_TFT_BLUE2, + TZ1090_PIN_TFT_BLUE3, + TZ1090_PIN_TFT_BLUE4, + TZ1090_PIN_TFT_BLUE5, + TZ1090_PIN_TFT_BLUE6, + TZ1090_PIN_TFT_BLUE7, + TZ1090_PIN_TFT_VDDEN_GD, + TZ1090_PIN_TFT_PANELCLK, + TZ1090_PIN_TFT_BLANK_LS, + TZ1090_PIN_TFT_VSYNC_NS, + TZ1090_PIN_TFT_HSYNC_NR, + TZ1090_PIN_TFT_VD12ACB, + TZ1090_PIN_TFT_PWRSAVE, + TZ1090_PIN_TX_ON, + TZ1090_PIN_RX_ON, + TZ1090_PIN_PLL_ON, + TZ1090_PIN_PA_ON, + TZ1090_PIN_RX_HP, + TZ1090_PIN_GAIN0, + TZ1090_PIN_GAIN1, + TZ1090_PIN_GAIN2, + TZ1090_PIN_GAIN3, + TZ1090_PIN_GAIN4, + TZ1090_PIN_GAIN5, + TZ1090_PIN_GAIN6, + TZ1090_PIN_GAIN7, + TZ1090_PIN_ANT_SEL0, + TZ1090_PIN_ANT_SEL1, + TZ1090_PIN_SDH_CLK_IN, + + /* Non-GPIO pins */ + TZ1090_PIN_TCK, + TZ1090_PIN_TRST, + TZ1090_PIN_TDI, + TZ1090_PIN_TDO, + TZ1090_PIN_TMS, + TZ1090_PIN_CLK_OUT0, + TZ1090_PIN_CLK_OUT1, + + NUM_GPIOS = TZ1090_PIN_TCK, +}; + +/* Pin names */ + +static const struct pinctrl_pin_desc tz1090_pins[] = { + /* GPIO pins */ + PINCTRL_PIN(TZ1090_PIN_SDIO_CLK, "sdio_clk"), + PINCTRL_PIN(TZ1090_PIN_SDIO_CMD, "sdio_cmd"), + PINCTRL_PIN(TZ1090_PIN_SDIO_D0, "sdio_d0"), + PINCTRL_PIN(TZ1090_PIN_SDIO_D1, "sdio_d1"), + PINCTRL_PIN(TZ1090_PIN_SDIO_D2, "sdio_d2"), + PINCTRL_PIN(TZ1090_PIN_SDIO_D3, "sdio_d3"), + PINCTRL_PIN(TZ1090_PIN_SDH_CD, "sdh_cd"), + PINCTRL_PIN(TZ1090_PIN_SDH_WP, "sdh_wp"), + PINCTRL_PIN(TZ1090_PIN_SPI0_MCLK, "spi0_mclk"), + PINCTRL_PIN(TZ1090_PIN_SPI0_CS0, "spi0_cs0"), + PINCTRL_PIN(TZ1090_PIN_SPI0_CS1, "spi0_cs1"), + PINCTRL_PIN(TZ1090_PIN_SPI0_CS2, "spi0_cs2"), + PINCTRL_PIN(TZ1090_PIN_SPI0_DOUT, "spi0_dout"), + PINCTRL_PIN(TZ1090_PIN_SPI0_DIN, "spi0_din"), + PINCTRL_PIN(TZ1090_PIN_SPI1_MCLK, "spi1_mclk"), + PINCTRL_PIN(TZ1090_PIN_SPI1_CS0, "spi1_cs0"), + PINCTRL_PIN(TZ1090_PIN_SPI1_CS1, "spi1_cs1"), + PINCTRL_PIN(TZ1090_PIN_SPI1_CS2, "spi1_cs2"), + PINCTRL_PIN(TZ1090_PIN_SPI1_DOUT, "spi1_dout"), + PINCTRL_PIN(TZ1090_PIN_SPI1_DIN, "spi1_din"), + PINCTRL_PIN(TZ1090_PIN_UART0_RXD, "uart0_rxd"), + PINCTRL_PIN(TZ1090_PIN_UART0_TXD, "uart0_txd"), + PINCTRL_PIN(TZ1090_PIN_UART0_CTS, "uart0_cts"), + PINCTRL_PIN(TZ1090_PIN_UART0_RTS, "uart0_rts"), + PINCTRL_PIN(TZ1090_PIN_UART1_RXD, "uart1_rxd"), + PINCTRL_PIN(TZ1090_PIN_UART1_TXD, "uart1_txd"), + PINCTRL_PIN(TZ1090_PIN_SCB0_SDAT, "scb0_sdat"), + PINCTRL_PIN(TZ1090_PIN_SCB0_SCLK, "scb0_sclk"), + PINCTRL_PIN(TZ1090_PIN_SCB1_SDAT, "scb1_sdat"), + PINCTRL_PIN(TZ1090_PIN_SCB1_SCLK, "scb1_sclk"), + PINCTRL_PIN(TZ1090_PIN_SCB2_SDAT, "scb2_sdat"), + PINCTRL_PIN(TZ1090_PIN_SCB2_SCLK, "scb2_sclk"), + PINCTRL_PIN(TZ1090_PIN_I2S_MCLK, "i2s_mclk"), + PINCTRL_PIN(TZ1090_PIN_I2S_BCLK_OUT, "i2s_bclk_out"), + PINCTRL_PIN(TZ1090_PIN_I2S_LRCLK_OUT, "i2s_lrclk_out"), + PINCTRL_PIN(TZ1090_PIN_I2S_DOUT0, "i2s_dout0"), + PINCTRL_PIN(TZ1090_PIN_I2S_DOUT1, "i2s_dout1"), + PINCTRL_PIN(TZ1090_PIN_I2S_DOUT2, "i2s_dout2"), + PINCTRL_PIN(TZ1090_PIN_I2S_DIN, "i2s_din"), + PINCTRL_PIN(TZ1090_PIN_PDM_A, "pdm_a"), + PINCTRL_PIN(TZ1090_PIN_PDM_B, "pdm_b"), + PINCTRL_PIN(TZ1090_PIN_PDM_C, "pdm_c"), + PINCTRL_PIN(TZ1090_PIN_PDM_D, "pdm_d"), + PINCTRL_PIN(TZ1090_PIN_TFT_RED0, "tft_red0"), + PINCTRL_PIN(TZ1090_PIN_TFT_RED1, "tft_red1"), + PINCTRL_PIN(TZ1090_PIN_TFT_RED2, "tft_red2"), + PINCTRL_PIN(TZ1090_PIN_TFT_RED3, "tft_red3"), + PINCTRL_PIN(TZ1090_PIN_TFT_RED4, "tft_red4"), + PINCTRL_PIN(TZ1090_PIN_TFT_RED5, "tft_red5"), + PINCTRL_PIN(TZ1090_PIN_TFT_RED6, "tft_red6"), + PINCTRL_PIN(TZ1090_PIN_TFT_RED7, "tft_red7"), + PINCTRL_PIN(TZ1090_PIN_TFT_GREEN0, "tft_green0"), + PINCTRL_PIN(TZ1090_PIN_TFT_GREEN1, "tft_green1"), + PINCTRL_PIN(TZ1090_PIN_TFT_GREEN2, "tft_green2"), + PINCTRL_PIN(TZ1090_PIN_TFT_GREEN3, "tft_green3"), + PINCTRL_PIN(TZ1090_PIN_TFT_GREEN4, "tft_green4"), + PINCTRL_PIN(TZ1090_PIN_TFT_GREEN5, "tft_green5"), + PINCTRL_PIN(TZ1090_PIN_TFT_GREEN6, "tft_green6"), + PINCTRL_PIN(TZ1090_PIN_TFT_GREEN7, "tft_green7"), + PINCTRL_PIN(TZ1090_PIN_TFT_BLUE0, "tft_blue0"), + PINCTRL_PIN(TZ1090_PIN_TFT_BLUE1, "tft_blue1"), + PINCTRL_PIN(TZ1090_PIN_TFT_BLUE2, "tft_blue2"), + PINCTRL_PIN(TZ1090_PIN_TFT_BLUE3, "tft_blue3"), + PINCTRL_PIN(TZ1090_PIN_TFT_BLUE4, "tft_blue4"), + PINCTRL_PIN(TZ1090_PIN_TFT_BLUE5, "tft_blue5"), + PINCTRL_PIN(TZ1090_PIN_TFT_BLUE6, "tft_blue6"), + PINCTRL_PIN(TZ1090_PIN_TFT_BLUE7, "tft_blue7"), + PINCTRL_PIN(TZ1090_PIN_TFT_VDDEN_GD, "tft_vdden_gd"), + PINCTRL_PIN(TZ1090_PIN_TFT_PANELCLK, "tft_panelclk"), + PINCTRL_PIN(TZ1090_PIN_TFT_BLANK_LS, "tft_blank_ls"), + PINCTRL_PIN(TZ1090_PIN_TFT_VSYNC_NS, "tft_vsync_ns"), + PINCTRL_PIN(TZ1090_PIN_TFT_HSYNC_NR, "tft_hsync_nr"), + PINCTRL_PIN(TZ1090_PIN_TFT_VD12ACB, "tft_vd12acb"), + PINCTRL_PIN(TZ1090_PIN_TFT_PWRSAVE, "tft_pwrsave"), + PINCTRL_PIN(TZ1090_PIN_TX_ON, "tx_on"), + PINCTRL_PIN(TZ1090_PIN_RX_ON, "rx_on"), + PINCTRL_PIN(TZ1090_PIN_PLL_ON, "pll_on"), + PINCTRL_PIN(TZ1090_PIN_PA_ON, "pa_on"), + PINCTRL_PIN(TZ1090_PIN_RX_HP, "rx_hp"), + PINCTRL_PIN(TZ1090_PIN_GAIN0, "gain0"), + PINCTRL_PIN(TZ1090_PIN_GAIN1, "gain1"), + PINCTRL_PIN(TZ1090_PIN_GAIN2, "gain2"), + PINCTRL_PIN(TZ1090_PIN_GAIN3, "gain3"), + PINCTRL_PIN(TZ1090_PIN_GAIN4, "gain4"), + PINCTRL_PIN(TZ1090_PIN_GAIN5, "gain5"), + PINCTRL_PIN(TZ1090_PIN_GAIN6, "gain6"), + PINCTRL_PIN(TZ1090_PIN_GAIN7, "gain7"), + PINCTRL_PIN(TZ1090_PIN_ANT_SEL0, "ant_sel0"), + PINCTRL_PIN(TZ1090_PIN_ANT_SEL1, "ant_sel1"), + PINCTRL_PIN(TZ1090_PIN_SDH_CLK_IN, "sdh_clk_in"), + + /* Non-GPIO pins */ + PINCTRL_PIN(TZ1090_PIN_TCK, "tck"), + PINCTRL_PIN(TZ1090_PIN_TRST, "trst"), + PINCTRL_PIN(TZ1090_PIN_TDI, "tdi"), + PINCTRL_PIN(TZ1090_PIN_TDO, "tdo"), + PINCTRL_PIN(TZ1090_PIN_TMS, "tms"), + PINCTRL_PIN(TZ1090_PIN_CLK_OUT0, "clk_out0"), + PINCTRL_PIN(TZ1090_PIN_CLK_OUT1, "clk_out1"), +}; + +/* Pins in each pin group */ + +static const unsigned int spi1_cs2_pins[] = { + TZ1090_PIN_SPI1_CS2, +}; + +static const unsigned int pdm_d_pins[] = { + TZ1090_PIN_PDM_D, +}; + +static const unsigned int tft_pins[] = { + TZ1090_PIN_TFT_RED0, + TZ1090_PIN_TFT_RED1, + TZ1090_PIN_TFT_RED2, + TZ1090_PIN_TFT_RED3, + TZ1090_PIN_TFT_RED4, + TZ1090_PIN_TFT_RED5, + TZ1090_PIN_TFT_RED6, + TZ1090_PIN_TFT_RED7, + TZ1090_PIN_TFT_GREEN0, + TZ1090_PIN_TFT_GREEN1, + TZ1090_PIN_TFT_GREEN2, + TZ1090_PIN_TFT_GREEN3, + TZ1090_PIN_TFT_GREEN4, + TZ1090_PIN_TFT_GREEN5, + TZ1090_PIN_TFT_GREEN6, + TZ1090_PIN_TFT_GREEN7, + TZ1090_PIN_TFT_BLUE0, + TZ1090_PIN_TFT_BLUE1, + TZ1090_PIN_TFT_BLUE2, + TZ1090_PIN_TFT_BLUE3, + TZ1090_PIN_TFT_BLUE4, + TZ1090_PIN_TFT_BLUE5, + TZ1090_PIN_TFT_BLUE6, + TZ1090_PIN_TFT_BLUE7, + TZ1090_PIN_TFT_VDDEN_GD, + TZ1090_PIN_TFT_PANELCLK, + TZ1090_PIN_TFT_BLANK_LS, + TZ1090_PIN_TFT_VSYNC_NS, + TZ1090_PIN_TFT_HSYNC_NR, + TZ1090_PIN_TFT_VD12ACB, + TZ1090_PIN_TFT_PWRSAVE, +}; + +static const unsigned int afe_pins[] = { + TZ1090_PIN_TX_ON, + TZ1090_PIN_RX_ON, + TZ1090_PIN_PLL_ON, + TZ1090_PIN_PA_ON, + TZ1090_PIN_RX_HP, + TZ1090_PIN_ANT_SEL0, + TZ1090_PIN_ANT_SEL1, + TZ1090_PIN_GAIN0, + TZ1090_PIN_GAIN1, + TZ1090_PIN_GAIN2, + TZ1090_PIN_GAIN3, + TZ1090_PIN_GAIN4, + TZ1090_PIN_GAIN5, + TZ1090_PIN_GAIN6, + TZ1090_PIN_GAIN7, +}; + +static const unsigned int sdio_pins[] = { + TZ1090_PIN_SDIO_CLK, + TZ1090_PIN_SDIO_CMD, + TZ1090_PIN_SDIO_D0, + TZ1090_PIN_SDIO_D1, + TZ1090_PIN_SDIO_D2, + TZ1090_PIN_SDIO_D3, +}; + +static const unsigned int sdh_pins[] = { + TZ1090_PIN_SDH_CD, + TZ1090_PIN_SDH_WP, + TZ1090_PIN_SDH_CLK_IN, +}; + +static const unsigned int spi0_pins[] = { + TZ1090_PIN_SPI0_MCLK, + TZ1090_PIN_SPI0_CS0, + TZ1090_PIN_SPI0_CS1, + TZ1090_PIN_SPI0_CS2, + TZ1090_PIN_SPI0_DOUT, + TZ1090_PIN_SPI0_DIN, +}; + +static const unsigned int spi1_pins[] = { + TZ1090_PIN_SPI1_MCLK, + TZ1090_PIN_SPI1_CS0, + TZ1090_PIN_SPI1_CS1, + TZ1090_PIN_SPI1_CS2, + TZ1090_PIN_SPI1_DOUT, + TZ1090_PIN_SPI1_DIN, +}; + +static const unsigned int uart0_pins[] = { + TZ1090_PIN_UART0_RTS, + TZ1090_PIN_UART0_CTS, + TZ1090_PIN_UART0_TXD, + TZ1090_PIN_UART0_RXD, +}; + +static const unsigned int uart1_pins[] = { + TZ1090_PIN_UART1_TXD, + TZ1090_PIN_UART1_RXD, +}; + +static const unsigned int uart_pins[] = { + TZ1090_PIN_UART1_TXD, + TZ1090_PIN_UART1_RXD, + TZ1090_PIN_UART0_RTS, + TZ1090_PIN_UART0_CTS, + TZ1090_PIN_UART0_TXD, + TZ1090_PIN_UART0_RXD, +}; + +static const unsigned int scb0_pins[] = { + TZ1090_PIN_SCB0_SDAT, + TZ1090_PIN_SCB0_SCLK, +}; + +static const unsigned int scb1_pins[] = { + TZ1090_PIN_SCB1_SDAT, + TZ1090_PIN_SCB1_SCLK, +}; + +static const unsigned int scb2_pins[] = { + TZ1090_PIN_SCB2_SDAT, + TZ1090_PIN_SCB2_SCLK, +}; + +static const unsigned int i2s_pins[] = { + TZ1090_PIN_I2S_MCLK, + TZ1090_PIN_I2S_BCLK_OUT, + TZ1090_PIN_I2S_LRCLK_OUT, + TZ1090_PIN_I2S_DOUT0, + TZ1090_PIN_I2S_DOUT1, + TZ1090_PIN_I2S_DOUT2, + TZ1090_PIN_I2S_DIN, +}; + +static const unsigned int jtag_pins[] = { + TZ1090_PIN_TCK, + TZ1090_PIN_TRST, + TZ1090_PIN_TDI, + TZ1090_PIN_TDO, + TZ1090_PIN_TMS, +}; + +/* Pins in each drive pin group */ + +static const unsigned int drive_sdio_pins[] = { + TZ1090_PIN_SDIO_CLK, + TZ1090_PIN_SDIO_CMD, + TZ1090_PIN_SDIO_D0, + TZ1090_PIN_SDIO_D1, + TZ1090_PIN_SDIO_D2, + TZ1090_PIN_SDIO_D3, + TZ1090_PIN_SDH_WP, + TZ1090_PIN_SDH_CD, + TZ1090_PIN_SDH_CLK_IN, +}; + +static const unsigned int drive_i2s_pins[] = { + TZ1090_PIN_CLK_OUT1, + TZ1090_PIN_I2S_DIN, + TZ1090_PIN_I2S_DOUT0, + TZ1090_PIN_I2S_DOUT1, + TZ1090_PIN_I2S_DOUT2, + TZ1090_PIN_I2S_LRCLK_OUT, + TZ1090_PIN_I2S_BCLK_OUT, + TZ1090_PIN_I2S_MCLK, +}; + +static const unsigned int drive_scb0_pins[] = { + TZ1090_PIN_SCB0_SCLK, + TZ1090_PIN_SCB0_SDAT, + TZ1090_PIN_PDM_D, + TZ1090_PIN_PDM_C, +}; + +static const unsigned int drive_pdm_pins[] = { + TZ1090_PIN_CLK_OUT0, + TZ1090_PIN_PDM_B, + TZ1090_PIN_PDM_A, +}; + +/* Pin groups each function can be muxed to */ + +/* + * The magic "perip" function allows otherwise non-muxing pins to be enabled in + * peripheral mode. + */ +static const char * const perip_groups[] = { + /* non-muxing convenient gpio pingroups */ + "uart", + "uart0", + "uart1", + "spi0", + "spi1", + "scb0", + "scb1", + "scb2", + "i2s", + /* individual pins not part of a pin mux group */ + "spi0_mclk", + "spi0_cs0", + "spi0_cs1", + "spi0_cs2", + "spi0_dout", + "spi0_din", + "spi1_mclk", + "spi1_cs0", + "spi1_cs1", + "spi1_dout", + "spi1_din", + "uart0_rxd", + "uart0_txd", + "uart0_cts", + "uart0_rts", + "uart1_rxd", + "uart1_txd", + "scb0_sdat", + "scb0_sclk", + "scb1_sdat", + "scb1_sclk", + "scb2_sdat", + "scb2_sclk", + "i2s_mclk", + "i2s_bclk_out", + "i2s_lrclk_out", + "i2s_dout0", + "i2s_dout1", + "i2s_dout2", + "i2s_din", + "pdm_a", + "pdm_b", + "pdm_c", +}; + +static const char * const sdh_sdio_groups[] = { + "sdh", + "sdio", + /* sdh pins */ + "sdh_cd", + "sdh_wp", + "sdh_clk_in", + /* sdio pins */ + "sdio_clk", + "sdio_cmd", + "sdio_d0", + "sdio_d1", + "sdio_d2", + "sdio_d3", +}; + +static const char * const spi1_cs2_groups[] = { + "spi1_cs2", +}; + +static const char * const pdm_dac_groups[] = { + "pdm_d", +}; + +static const char * const usb_vbus_groups[] = { + "spi1_cs2", + "pdm_d", +}; + +static const char * const afe_groups[] = { + "afe", + /* afe pins */ + "tx_on", + "rx_on", + "pll_on", + "pa_on", + "rx_hp", + "ant_sel0", + "ant_sel1", + "gain0", + "gain1", + "gain2", + "gain3", + "gain4", + "gain5", + "gain6", + "gain7", +}; + +static const char * const tft_groups[] = { + "tft", + /* tft pins */ + "tft_red0", + "tft_red1", + "tft_red2", + "tft_red3", + "tft_red4", + "tft_red5", + "tft_red6", + "tft_red7", + "tft_green0", + "tft_green1", + "tft_green2", + "tft_green3", + "tft_green4", + "tft_green5", + "tft_green6", + "tft_green7", + "tft_blue0", + "tft_blue1", + "tft_blue2", + "tft_blue3", + "tft_blue4", + "tft_blue5", + "tft_blue6", + "tft_blue7", + "tft_vdden_gd", + "tft_panelclk", + "tft_blank_ls", + "tft_vsync_ns", + "tft_hsync_nr", + "tft_vd12acb", + "tft_pwrsave", +}; + +/* Mux functions that can be used by a mux */ + +enum tz1090_mux { + /* internal placeholder */ + TZ1090_MUX_NA = -1, + /* magic per-non-muxing-GPIO-pin peripheral mode mux */ + TZ1090_MUX_PERIP, + /* SDH/SDIO mux */ + TZ1090_MUX_SDH, + TZ1090_MUX_SDIO, + /* USB_VBUS muxes */ + TZ1090_MUX_SPI1_CS2, + TZ1090_MUX_PDM_DAC, + TZ1090_MUX_USB_VBUS, + /* AFE mux */ + TZ1090_MUX_AFE, + TZ1090_MUX_TS_OUT_0, + /* EXT_DAC mux */ + TZ1090_MUX_DAC, + TZ1090_MUX_NOT_IQADC_STB, + TZ1090_MUX_IQDAC_STB, + /* TFT mux */ + TZ1090_MUX_TFT, + TZ1090_MUX_EXT_DAC, + TZ1090_MUX_TS_OUT_1, + TZ1090_MUX_LCD_TRACE, + TZ1090_MUX_PHY_RINGOSC, +}; + +#define FUNCTION(mux, fname, group) \ + [(TZ1090_MUX_ ## mux)] = { \ + .name = #fname, \ + .groups = group##_groups, \ + .ngroups = ARRAY_SIZE(group##_groups), \ + } +/* For intermediate functions with submuxes */ +#define NULL_FUNCTION(mux, fname) \ + [(TZ1090_MUX_ ## mux)] = { \ + .name = #fname, \ + } + +/* Must correlate with enum tz1090_mux */ +static const struct tz1090_function tz1090_functions[] = { + /* FUNCTION function name pingroups */ + FUNCTION(PERIP, perip, perip), + FUNCTION(SDH, sdh, sdh_sdio), + FUNCTION(SDIO, sdio, sdh_sdio), + FUNCTION(SPI1_CS2, spi1_cs2, spi1_cs2), + FUNCTION(PDM_DAC, pdm_dac, pdm_dac), + FUNCTION(USB_VBUS, usb_vbus, usb_vbus), + FUNCTION(AFE, afe, afe), + FUNCTION(TS_OUT_0, ts_out_0, afe), + FUNCTION(DAC, ext_dac, tft), + FUNCTION(NOT_IQADC_STB, not_iqadc_stb, tft), + FUNCTION(IQDAC_STB, iqdac_stb, tft), + FUNCTION(TFT, tft, tft), + NULL_FUNCTION(EXT_DAC, _ext_dac), + FUNCTION(TS_OUT_1, ts_out_1, tft), + FUNCTION(LCD_TRACE, lcd_trace, tft), + FUNCTION(PHY_RINGOSC, phy_ringosc, tft), +}; + +/* Sub muxes */ + +/** + * MUX() - Initialise a mux description. + * @f0: Function 0 (TZ1090_MUX_ is prepended, NA for none) + * @f1: Function 1 (TZ1090_MUX_ is prepended, NA for none) + * @f2: Function 2 (TZ1090_MUX_ is prepended, NA for none) + * @f3: Function 3 (TZ1090_MUX_ is prepended, NA for none) + * @f4: Function 4 (TZ1090_MUX_ is prepended, NA for none) + * @mux_r: Mux register (REG_PINCTRL_ is prepended) + * @mux_b: Bit number in register that the mux field begins + * @mux_w: Width of mux field in register + */ +#define MUX(f0, f1, f2, f3, f4, mux_r, mux_b, mux_w) \ + { \ + .funcs = { \ + TZ1090_MUX_ ## f0, \ + TZ1090_MUX_ ## f1, \ + TZ1090_MUX_ ## f2, \ + TZ1090_MUX_ ## f3, \ + TZ1090_MUX_ ## f4, \ + }, \ + .reg = (REG_PINCTRL_ ## mux_r), \ + .bit = (mux_b), \ + .width = (mux_w), \ + } + +/** + * DEFINE_SUBMUX() - Defines a submux description separate from a pin group. + * @mux: Mux name (_submux is appended) + * @f0: Function 0 (TZ1090_MUX_ is prepended, NA for none) + * @f1: Function 1 (TZ1090_MUX_ is prepended, NA for none) + * @f2: Function 2 (TZ1090_MUX_ is prepended, NA for none) + * @f3: Function 3 (TZ1090_MUX_ is prepended, NA for none) + * @f4: Function 4 (TZ1090_MUX_ is prepended, NA for none) + * @mux_r: Mux register (REG_PINCTRL_ is prepended) + * @mux_b: Bit number in register that the mux field begins + * @mux_w: Width of mux field in register + * + * A sub mux is a nested mux that can be bound to a magic function number used + * by another mux description. For example value 4 of the top level mux might + * correspond to a function which has a submux pointed to in tz1090_submux[]. + * The outer mux can then take on any function in the top level mux or the + * submux, and if a submux function is chosen both muxes are updated to route + * the signal from the submux. + * + * The submux can be defined with DEFINE_SUBMUX and pointed to from + * tz1090_submux[] using SUBMUX. + */ +#define DEFINE_SUBMUX(mux, f0, f1, f2, f3, f4, mux_r, mux_b, mux_w) \ + static struct tz1090_muxdesc mux ## _submux = \ + MUX(f0, f1, f2, f3, f4, mux_r, mux_b, mux_w) + +/** + * SUBMUX() - Link a submux to a function number. + * @f: Function name (TZ1090_MUX_ is prepended) + * @submux: Submux name (_submux is appended) + * + * For use in tz1090_submux[] initialisation to link an intermediate function + * number to a particular submux description. It indicates that when the + * function is chosen the signal is connected to the submux. + */ +#define SUBMUX(f, submux) [(TZ1090_MUX_ ## f)] = &(submux ## _submux) + +/** + * MUX_PG() - Initialise a pin group with mux control + * @pg_name: Pin group name (stringified, _pins appended to get pins array) + * @f0: Function 0 (TZ1090_MUX_ is prepended, NA for none) + * @f1: Function 1 (TZ1090_MUX_ is prepended, NA for none) + * @f2: Function 2 (TZ1090_MUX_ is prepended, NA for none) + * @f3: Function 3 (TZ1090_MUX_ is prepended, NA for none) + * @f4: Function 4 (TZ1090_MUX_ is prepended, NA for none) + * @mux_r: Mux register (REG_PINCTRL_ is prepended) + * @mux_b: Bit number in register that the mux field begins + * @mux_w: Width of mux field in register + */ +#define MUX_PG(pg_name, f0, f1, f2, f3, f4, \ + mux_r, mux_b, mux_w) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .mux = MUX(f0, f1, f2, f3, f4, \ + mux_r, mux_b, mux_w), \ + } + +/** + * SIMPLE_PG() - Initialise a simple convenience pin group + * @pg_name: Pin group name (stringified, _pins appended to get pins array) + * + * A simple pin group is simply used for binding pins together so they can be + * referred to by a single name instead of having to list every pin + * individually. + */ +#define SIMPLE_PG(pg_name) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + } + +/** + * DRV_PG() - Initialise a pin group with drive control + * @pg_name: Pin group name (stringified, _pins appended to get pins array) + * @slw_b: Slew register bit. + * The same bit is used for Schmitt, and Drive (*2). + */ +#define DRV_PG(pg_name, slw_b) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .drv = true, \ + .slw_bit = (slw_b), \ + } + +/* + * Define main muxing pin groups + */ + +/* submuxes */ + +/* name f0, f1, f2, f3, f4, mux r/b/w */ +DEFINE_SUBMUX(ext_dac, DAC, NOT_IQADC_STB, IQDAC_STB, NA, NA, IF_CTL, 6, 2); + +/* bind submuxes to internal functions */ +static struct tz1090_muxdesc *tz1090_submux[] = { + SUBMUX(EXT_DAC, ext_dac), +}; + +/* + * These are the pin mux groups. Pin muxing can be enabled and disabled for each + * pin individually so these groups are internal. The mapping of pins to pin mux + * group is below (tz1090_mux_pins). + */ +static struct tz1090_pingroup tz1090_mux_groups[] = { + /* Muxing pin groups */ + /* pg_name, f0, f1, f2, f3, f4, mux r/b/w */ + MUX_PG(sdh, SDH, SDIO, NA, NA, NA, IF_CTL, 20, 2), + MUX_PG(sdio, SDIO, SDH, NA, NA, NA, IF_CTL, 16, 2), + MUX_PG(spi1_cs2, SPI1_CS2, USB_VBUS, NA, NA, NA, IF_CTL, 10, 2), + MUX_PG(pdm_d, PDM_DAC, USB_VBUS, NA, NA, NA, IF_CTL, 8, 2), + MUX_PG(afe, AFE, TS_OUT_0, NA, NA, NA, IF_CTL, 4, 2), + MUX_PG(tft, TFT, EXT_DAC, TS_OUT_1, LCD_TRACE, PHY_RINGOSC, IF_CTL, 0, 3), +}; + +/* + * This is the mapping from GPIO pins to pin mux groups in tz1090_mux_groups[]. + * Pins which aren't muxable to multiple peripherals are set to + * TZ1090_MUX_GROUP_MAX to enable the "perip" function to enable/disable + * peripheral control of the pin. + * + * This array is initialised in tz1090_init_mux_pins(). + */ +static u8 tz1090_mux_pins[NUM_GPIOS]; + +/* TZ1090_MUX_GROUP_MAX is used in tz1090_mux_pins[] for non-muxing pins */ +#define TZ1090_MUX_GROUP_MAX ARRAY_SIZE(tz1090_mux_groups) + +/** + * tz1090_init_mux_pins() - Initialise GPIO pin to mux group mapping. + * + * Initialises the tz1090_mux_pins[] array to be the inverse of the pin lists in + * each pin mux group in tz1090_mux_groups[]. + * + * It is assumed that no pin mux groups overlap (share pins). + */ +static void __init tz1090_init_mux_pins(void) +{ + unsigned int g, p; + const struct tz1090_pingroup *grp; + const unsigned int *pin; + + for (p = 0; p < NUM_GPIOS; ++p) + tz1090_mux_pins[p] = TZ1090_MUX_GROUP_MAX; + + grp = tz1090_mux_groups; + for (g = 0, grp = tz1090_mux_groups; + g < ARRAY_SIZE(tz1090_mux_groups); ++g, ++grp) + for (pin = grp->pins, p = 0; p < grp->npins; ++p, ++pin) + tz1090_mux_pins[*pin] = g; +} + +/* + * These are the externally visible pin groups. Some of them allow group control + * of drive configuration. Some are just simple convenience pingroups. All the + * internal pin mux groups in tz1090_mux_groups[] are mirrored here with the + * same pins. + * Pseudo pin groups follow in the group numbers after this array for each GPIO + * pin. Any group used for muxing must have all pins belonging to the same pin + * mux group. + */ +static struct tz1090_pingroup tz1090_groups[] = { + /* Pin groups with drive control (with no out of place pins) */ + /* pg_name, slw/schmitt/drv b */ + DRV_PG(jtag, 11 /* 11, 22 */), + DRV_PG(tft, 10 /* 10, 20 */), + DRV_PG(scb2, 9 /* 9, 18 */), + DRV_PG(spi0, 7 /* 7, 14 */), + DRV_PG(uart, 5 /* 5, 10 */), + DRV_PG(scb1, 4 /* 4, 8 */), + DRV_PG(spi1, 3 /* 3, 6 */), + DRV_PG(afe, 0 /* 0, 0 */), + + /* + * Drive specific pin groups (with odd combinations of pins which makes + * the pin group naming somewhat arbitrary) + */ + /* pg_name, slw/schmitt/drv b */ + DRV_PG(drive_sdio, 8 /* 8, 16 */), /* sdio_* + sdh_* */ + DRV_PG(drive_i2s, 6 /* 6, 12 */), /* i2s_* + clk_out1 */ + DRV_PG(drive_scb0, 2 /* 2, 4 */), /* scb0_* + pdm_{c,d} */ + DRV_PG(drive_pdm, 1 /* 1, 2 */), /* pdm_{a,b} + clk_out0 */ + + /* Convenience pin groups */ + /* pg_name */ + SIMPLE_PG(uart0), + SIMPLE_PG(uart1), + SIMPLE_PG(scb0), + SIMPLE_PG(i2s), + SIMPLE_PG(sdh), + SIMPLE_PG(sdio), + + /* pseudo-pingroups for each GPIO pin follow */ +}; + +/** + * struct tz1090_pmx - Private pinctrl data + * @dev: Platform device + * @pctl: Pin control device + * @regs: Register region + * @lock: Lock protecting coherency of pin_en, gpio_en, and SELECT regs + * @pin_en: Pins that have been enabled (32 pins packed into each element) + * @gpio_en: GPIOs that have been enabled (32 pins packed into each element) + */ +struct tz1090_pmx { + struct device *dev; + struct pinctrl_dev *pctl; + void __iomem *regs; + spinlock_t lock; + u32 pin_en[3]; + u32 gpio_en[3]; +}; + +static inline u32 pmx_read(struct tz1090_pmx *pmx, u32 reg) +{ + return ioread32(pmx->regs + reg); +} + +static inline void pmx_write(struct tz1090_pmx *pmx, u32 val, u32 reg) +{ + iowrite32(val, pmx->regs + reg); +} + +/* + * Pin control operations + */ + +/* each GPIO pin has it's own pseudo pingroup containing only itself */ + +static int tz1090_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(tz1090_groups) + NUM_GPIOS; +} + +static const char *tz1090_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group) +{ + if (group < ARRAY_SIZE(tz1090_groups)) { + /* normal pingroup */ + return tz1090_groups[group].name; + } else { + /* individual gpio pin pseudo-pingroup */ + unsigned int pin = group - ARRAY_SIZE(tz1090_groups); + return tz1090_pins[pin].name; + } +} + +static int tz1090_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group, + const unsigned int **pins, + unsigned int *num_pins) +{ + if (group < ARRAY_SIZE(tz1090_groups)) { + /* normal pingroup */ + *pins = tz1090_groups[group].pins; + *num_pins = tz1090_groups[group].npins; + } else { + /* individual gpio pin pseudo-pingroup */ + unsigned int pin = group - ARRAY_SIZE(tz1090_groups); + *pins = &tz1090_pins[pin].number; + *num_pins = 1; + } + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void tz1090_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned int offset) +{ + seq_printf(s, " %s", dev_name(pctldev->dev)); +} +#endif + +static int reserve_map(struct device *dev, struct pinctrl_map **map, + unsigned int *reserved_maps, unsigned int *num_maps, + unsigned int reserve) +{ + unsigned int old_num = *reserved_maps; + unsigned int new_num = *num_maps + reserve; + struct pinctrl_map *new_map; + + if (old_num >= new_num) + return 0; + + new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); + if (!new_map) { + dev_err(dev, "krealloc(map) failed\n"); + return -ENOMEM; + } + + memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); + + *map = new_map; + *reserved_maps = new_num; + + return 0; +} + +static int add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps, + unsigned int *num_maps, const char *group, + const char *function) +{ + if (WARN_ON(*num_maps == *reserved_maps)) + return -ENOSPC; + + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.group = group; + (*map)[*num_maps].data.mux.function = function; + (*num_maps)++; + + return 0; +} + +static int add_map_configs(struct device *dev, + struct pinctrl_map **map, + unsigned int *reserved_maps, unsigned int *num_maps, + const char *group, unsigned long *configs, + unsigned int num_configs) +{ + unsigned long *dup_configs; + + if (WARN_ON(*num_maps == *reserved_maps)) + return -ENOSPC; + + dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), + GFP_KERNEL); + if (!dup_configs) { + dev_err(dev, "kmemdup(configs) failed\n"); + return -ENOMEM; + } + + (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP; + (*map)[*num_maps].data.configs.group_or_pin = group; + (*map)[*num_maps].data.configs.configs = dup_configs; + (*map)[*num_maps].data.configs.num_configs = num_configs; + (*num_maps)++; + + return 0; +} + +static void tz1090_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, + unsigned int num_maps) +{ + int i; + + for (i = 0; i < num_maps; i++) + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) + kfree(map[i].data.configs.configs); + + kfree(map); +} + +static int tz1090_pinctrl_dt_subnode_to_map(struct device *dev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *reserved_maps, + unsigned int *num_maps) +{ + int ret; + const char *function; + unsigned long *configs = NULL; + unsigned int num_configs = 0; + unsigned int reserve; + struct property *prop; + const char *group; + + ret = of_property_read_string(np, "tz1090,function", &function); + if (ret < 0) { + /* EINVAL=missing, which is fine since it's optional */ + if (ret != -EINVAL) + dev_err(dev, "could not parse property function\n"); + function = NULL; + } + + ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs); + if (ret) + return ret; + + reserve = 0; + if (function != NULL) + reserve++; + if (num_configs) + reserve++; + ret = of_property_count_strings(np, "tz1090,pins"); + if (ret < 0) { + dev_err(dev, "could not parse property pins\n"); + goto exit; + } + reserve *= ret; + + ret = reserve_map(dev, map, reserved_maps, num_maps, reserve); + if (ret < 0) + goto exit; + + of_property_for_each_string(np, "tz1090,pins", prop, group) { + if (function) { + ret = add_map_mux(map, reserved_maps, num_maps, + group, function); + if (ret < 0) + goto exit; + } + + if (num_configs) { + ret = add_map_configs(dev, map, reserved_maps, + num_maps, group, configs, + num_configs); + if (ret < 0) + goto exit; + } + } + + ret = 0; + +exit: + kfree(configs); + return ret; +} + +static int tz1090_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + unsigned int reserved_maps; + struct device_node *np; + int ret; + + reserved_maps = 0; + *map = NULL; + *num_maps = 0; + + for_each_child_of_node(np_config, np) { + ret = tz1090_pinctrl_dt_subnode_to_map(pctldev->dev, np, map, + &reserved_maps, + num_maps); + if (ret < 0) { + tz1090_pinctrl_dt_free_map(pctldev, *map, *num_maps); + return ret; + } + } + + return 0; +} + +static struct pinctrl_ops tz1090_pinctrl_ops = { + .get_groups_count = tz1090_pinctrl_get_groups_count, + .get_group_name = tz1090_pinctrl_get_group_name, + .get_group_pins = tz1090_pinctrl_get_group_pins, +#ifdef CONFIG_DEBUG_FS + .pin_dbg_show = tz1090_pinctrl_pin_dbg_show, +#endif + .dt_node_to_map = tz1090_pinctrl_dt_node_to_map, + .dt_free_map = tz1090_pinctrl_dt_free_map, +}; + +/* + * Pin mux operations + */ + +static int tz1090_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(tz1090_functions); +} + +static const char *tz1090_pinctrl_get_func_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + return tz1090_functions[function].name; +} + +static int tz1090_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char * const **groups, + unsigned int * const num_groups) +{ + /* pingroup functions */ + *groups = tz1090_functions[function].groups; + *num_groups = tz1090_functions[function].ngroups; + return 0; +} + +/** + * tz1090_pinctrl_select() - update bit in SELECT register + * @pmx: Pinmux data + * @pin: Pin number (must be within GPIO range) + */ +static void tz1090_pinctrl_select(struct tz1090_pmx *pmx, + unsigned int pin) +{ + u32 reg, reg_shift, select, val; + unsigned int pmx_index, pmx_shift; + unsigned long flags; + + /* uses base 32 instead of base 30 */ + pmx_index = pin >> 5; + pmx_shift = pin & 0x1f; + + /* select = !perip || gpio */ + select = ((~pmx->pin_en[pmx_index] | + pmx->gpio_en[pmx_index]) >> pmx_shift) & 1; + + /* find register and bit offset (base 30) */ + reg = REG_PINCTRL_SELECT + 4*(pin / 30); + reg_shift = pin % 30; + + /* modify gpio select bit */ + __global_lock2(flags); + val = pmx_read(pmx, reg); + val &= ~BIT(reg_shift); + val |= select << reg_shift; + pmx_write(pmx, val, reg); + __global_unlock2(flags); +} + +/** + * tz1090_pinctrl_gpio_select() - enable/disable GPIO usage for a pin + * @pmx: Pinmux data + * @pin: Pin number + * @gpio_select: true to enable pin as GPIO, + * false to leave control to whatever function is enabled + * + * Records that GPIO usage is enabled/disabled so that enabling a function + * doesn't override the SELECT register bit. + */ +static void tz1090_pinctrl_gpio_select(struct tz1090_pmx *pmx, + unsigned int pin, + bool gpio_select) +{ + unsigned int index, shift; + u32 gpio_en; + + if (pin >= NUM_GPIOS) + return; + + /* uses base 32 instead of base 30 */ + index = pin >> 5; + shift = pin & 0x1f; + + spin_lock(&pmx->lock); + + /* keep a record whether gpio is selected */ + gpio_en = pmx->gpio_en[index]; + gpio_en &= ~BIT(shift); + if (gpio_select) + gpio_en |= BIT(shift); + pmx->gpio_en[index] = gpio_en; + + /* update the select bit */ + tz1090_pinctrl_select(pmx, pin); + + spin_unlock(&pmx->lock); +} + +/** + * tz1090_pinctrl_perip_select() - enable/disable peripheral interface for a pin + * @pmx: Pinmux data + * @pin: Pin number + * @perip_select: true to enable peripheral interface when not GPIO, + * false to leave pin in GPIO mode + * + * Records that peripheral usage is enabled/disabled so that SELECT register can + * be set appropriately when GPIO is disabled. + */ +static void tz1090_pinctrl_perip_select(struct tz1090_pmx *pmx, + unsigned int pin, + bool perip_select) +{ + unsigned int index, shift; + u32 pin_en; + + if (pin >= NUM_GPIOS) + return; + + /* uses base 32 instead of base 30 */ + index = pin >> 5; + shift = pin & 0x1f; + + spin_lock(&pmx->lock); + + /* keep a record whether peripheral is selected */ + pin_en = pmx->pin_en[index]; + pin_en &= ~BIT(shift); + if (perip_select) + pin_en |= BIT(shift); + pmx->pin_en[index] = pin_en; + + /* update the select bit */ + tz1090_pinctrl_select(pmx, pin); + + spin_unlock(&pmx->lock); +} + +/** + * tz1090_pinctrl_enable_mux() - Switch a pin mux group to a function. + * @pmx: Pinmux data + * @desc: Pinmux description + * @function: Function to switch to + * + * Enable a particular function on a pin mux group. Since pin mux descriptions + * are nested this function is recursive. + */ +static int tz1090_pinctrl_enable_mux(struct tz1090_pmx *pmx, + const struct tz1090_muxdesc *desc, + unsigned int function) +{ + const int *fit; + unsigned long flags; + int mux; + unsigned int func, ret; + u32 reg, mask; + + /* find the mux value for this function, searching recursively */ + for (mux = 0, fit = desc->funcs; + mux < ARRAY_SIZE(desc->funcs); ++mux, ++fit) { + func = *fit; + if (func == function) + goto found_mux; + + /* maybe it's a sub-mux */ + if (func < ARRAY_SIZE(tz1090_submux) && tz1090_submux[func]) { + ret = tz1090_pinctrl_enable_mux(pmx, + tz1090_submux[func], + function); + if (!ret) + goto found_mux; + } + } + + return -EINVAL; +found_mux: + + /* Set up the mux */ + if (desc->width) { + mask = (BIT(desc->width) - 1) << desc->bit; + __global_lock2(flags); + reg = pmx_read(pmx, desc->reg); + reg &= ~mask; + reg |= (mux << desc->bit) & mask; + pmx_write(pmx, reg, desc->reg); + __global_unlock2(flags); + } + + return 0; +} + +/** + * tz1090_pinctrl_enable() - Enable a function on a pin group. + * @pctldev: Pin control data + * @function: Function index to enable + * @group: Group index to enable + * + * Enable a particular function on a group of pins. The per GPIO pin pseudo pin + * groups can be used (in which case the pin will be enabled in peripheral mode + * and if it belongs to a pin mux group the mux will be switched if it isn't + * already in use. Some convenience pin groups can also be used in which case + * the effect is the same as enabling the function on each individual pin in the + * group. + */ +static int tz1090_pinctrl_enable(struct pinctrl_dev *pctldev, + unsigned int function, unsigned int group) +{ + struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + struct tz1090_pingroup *grp; + int ret; + unsigned int pin_num, mux_group, i, npins; + const unsigned int *pins; + + /* group of pins? */ + if (group < ARRAY_SIZE(tz1090_groups)) { + grp = &tz1090_groups[group]; + npins = grp->npins; + pins = grp->pins; + /* + * All pins in the group must belong to the same mux group, + * which allows us to just use the mux group of the first pin. + * By explicitly listing permitted pingroups for each function + * the pinmux core should ensure this is always the case. + */ + } else { + pin_num = group - ARRAY_SIZE(tz1090_groups); + npins = 1; + pins = &pin_num; + } + mux_group = tz1090_mux_pins[*pins]; + + /* no mux group, but can still be individually muxed to peripheral */ + if (mux_group >= TZ1090_MUX_GROUP_MAX) { + if (function == TZ1090_MUX_PERIP) + goto mux_pins; + return -EINVAL; + } + + /* mux group already set to a different function? */ + grp = &tz1090_mux_groups[mux_group]; + if (grp->func_count && grp->func != function) { + dev_err(pctldev->dev, + "%s: can't mux pin(s) to '%s', group already muxed to '%s'\n", + __func__, tz1090_functions[function].name, + tz1090_functions[grp->func].name); + return -EBUSY; + } + + dev_dbg(pctldev->dev, "%s: muxing %u pin(s) in '%s' to '%s'\n", + __func__, npins, grp->name, tz1090_functions[function].name); + + /* if first pin in mux group to be enabled, enable the group mux */ + if (!grp->func_count) { + grp->func = function; + ret = tz1090_pinctrl_enable_mux(pmx, &grp->mux, function); + if (ret) + return ret; + } + /* add pins to ref count and mux individually to peripheral */ + grp->func_count += npins; +mux_pins: + for (i = 0; i < npins; ++i) + tz1090_pinctrl_perip_select(pmx, pins[i], true); + + return 0; +} + +/** + * tz1090_pinctrl_disable() - Disable a function on a pin group. + * @pctldev: Pin control data + * @function: Function index to disable + * @group: Group index to disable + * + * Disable a particular function on a group of pins. The per GPIO pin pseudo pin + * groups can be used (in which case the pin will be taken out of peripheral + * mode. Some convenience pin groups can also be used in which case the effect + * is the same as enabling the function on each individual pin in the group. + */ +static void tz1090_pinctrl_disable(struct pinctrl_dev *pctldev, + unsigned int function, unsigned int group) +{ + struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + struct tz1090_pingroup *grp; + unsigned int pin_num, mux_group, i, npins; + const unsigned int *pins; + + /* group of pins? */ + if (group < ARRAY_SIZE(tz1090_groups)) { + grp = &tz1090_groups[group]; + npins = grp->npins; + pins = grp->pins; + /* + * All pins in the group must belong to the same mux group, + * which allows us to just use the mux group of the first pin. + * By explicitly listing permitted pingroups for each function + * the pinmux core should ensure this is always the case. + */ + } else { + pin_num = group - ARRAY_SIZE(tz1090_groups); + npins = 1; + pins = &pin_num; + } + mux_group = tz1090_mux_pins[*pins]; + + /* no mux group, but can still be individually muxed to peripheral */ + if (mux_group >= TZ1090_MUX_GROUP_MAX) { + if (function == TZ1090_MUX_PERIP) + goto unmux_pins; + return; + } + + /* mux group already set to a different function? */ + grp = &tz1090_mux_groups[mux_group]; + dev_dbg(pctldev->dev, "%s: unmuxing %u pin(s) in '%s' from '%s'\n", + __func__, npins, grp->name, tz1090_functions[function].name); + + /* subtract pins from ref count and unmux individually */ + WARN_ON(grp->func_count < npins); + grp->func_count -= npins; +unmux_pins: + for (i = 0; i < npins; ++i) + tz1090_pinctrl_perip_select(pmx, pins[i], false); +} + +/** + * tz1090_pinctrl_gpio_request_enable() - Put pin in GPIO mode. + * @pctldev: Pin control data + * @range: GPIO range + * @pin: Pin number + * + * Puts a particular pin into GPIO mode, disabling peripheral control until it's + * disabled again. + */ +static int tz1090_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + tz1090_pinctrl_gpio_select(pmx, pin, true); + return 0; +} + +/** + * tz1090_pinctrl_gpio_disable_free() - Take pin out of GPIO mode. + * @pctldev: Pin control data + * @range: GPIO range + * @pin: Pin number + * + * Take a particular pin out of GPIO mode. If the pin is enabled for a + * peripheral it will return to peripheral mode. + */ +static void tz1090_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + tz1090_pinctrl_gpio_select(pmx, pin, false); +} + +static struct pinmux_ops tz1090_pinmux_ops = { + .get_functions_count = tz1090_pinctrl_get_funcs_count, + .get_function_name = tz1090_pinctrl_get_func_name, + .get_function_groups = tz1090_pinctrl_get_func_groups, + .enable = tz1090_pinctrl_enable, + .disable = tz1090_pinctrl_disable, + .gpio_request_enable = tz1090_pinctrl_gpio_request_enable, + .gpio_disable_free = tz1090_pinctrl_gpio_disable_free, +}; + +/* + * Pin config operations + */ + +struct tz1090_pinconf_pullup { + unsigned char index; + unsigned char shift; +}; + +/* The mapping of pin to pull up/down register index and shift */ +static struct tz1090_pinconf_pullup tz1090_pinconf_pullup[] = { + {5, 22}, /* 0 - TZ1090_PIN_SDIO_CLK */ + {0, 14}, /* 1 - TZ1090_PIN_SDIO_CMD */ + {0, 6}, /* 2 - TZ1090_PIN_SDIO_D0 */ + {0, 8}, /* 3 - TZ1090_PIN_SDIO_D1 */ + {0, 10}, /* 4 - TZ1090_PIN_SDIO_D2 */ + {0, 12}, /* 5 - TZ1090_PIN_SDIO_D3 */ + {0, 2}, /* 6 - TZ1090_PIN_SDH_CD */ + {0, 4}, /* 7 - TZ1090_PIN_SDH_WP */ + {0, 16}, /* 8 - TZ1090_PIN_SPI0_MCLK */ + {0, 18}, /* 9 - TZ1090_PIN_SPI0_CS0 */ + {0, 20}, /* 10 - TZ1090_PIN_SPI0_CS1 */ + {0, 22}, /* 11 - TZ1090_PIN_SPI0_CS2 */ + {0, 24}, /* 12 - TZ1090_PIN_SPI0_DOUT */ + {0, 26}, /* 13 - TZ1090_PIN_SPI0_DIN */ + {0, 28}, /* 14 - TZ1090_PIN_SPI1_MCLK */ + {0, 30}, /* 15 - TZ1090_PIN_SPI1_CS0 */ + {1, 0}, /* 16 - TZ1090_PIN_SPI1_CS1 */ + {1, 2}, /* 17 - TZ1090_PIN_SPI1_CS2 */ + {1, 4}, /* 18 - TZ1090_PIN_SPI1_DOUT */ + {1, 6}, /* 19 - TZ1090_PIN_SPI1_DIN */ + {1, 8}, /* 20 - TZ1090_PIN_UART0_RXD */ + {1, 10}, /* 21 - TZ1090_PIN_UART0_TXD */ + {1, 12}, /* 22 - TZ1090_PIN_UART0_CTS */ + {1, 14}, /* 23 - TZ1090_PIN_UART0_RTS */ + {1, 16}, /* 24 - TZ1090_PIN_UART1_RXD */ + {1, 18}, /* 25 - TZ1090_PIN_UART1_TXD */ + {1, 20}, /* 26 - TZ1090_PIN_SCB0_SDAT */ + {1, 22}, /* 27 - TZ1090_PIN_SCB0_SCLK */ + {1, 24}, /* 28 - TZ1090_PIN_SCB1_SDAT */ + {1, 26}, /* 29 - TZ1090_PIN_SCB1_SCLK */ + + {1, 28}, /* 30 - TZ1090_PIN_SCB2_SDAT */ + {1, 30}, /* 31 - TZ1090_PIN_SCB2_SCLK */ + {2, 0}, /* 32 - TZ1090_PIN_I2S_MCLK */ + {2, 2}, /* 33 - TZ1090_PIN_I2S_BCLK_OUT */ + {2, 4}, /* 34 - TZ1090_PIN_I2S_LRCLK_OUT */ + {2, 6}, /* 35 - TZ1090_PIN_I2S_DOUT0 */ + {2, 8}, /* 36 - TZ1090_PIN_I2S_DOUT1 */ + {2, 10}, /* 37 - TZ1090_PIN_I2S_DOUT2 */ + {2, 12}, /* 38 - TZ1090_PIN_I2S_DIN */ + {4, 12}, /* 39 - TZ1090_PIN_PDM_A */ + {4, 14}, /* 40 - TZ1090_PIN_PDM_B */ + {4, 18}, /* 41 - TZ1090_PIN_PDM_C */ + {4, 20}, /* 42 - TZ1090_PIN_PDM_D */ + {2, 14}, /* 43 - TZ1090_PIN_TFT_RED0 */ + {2, 16}, /* 44 - TZ1090_PIN_TFT_RED1 */ + {2, 18}, /* 45 - TZ1090_PIN_TFT_RED2 */ + {2, 20}, /* 46 - TZ1090_PIN_TFT_RED3 */ + {2, 22}, /* 47 - TZ1090_PIN_TFT_RED4 */ + {2, 24}, /* 48 - TZ1090_PIN_TFT_RED5 */ + {2, 26}, /* 49 - TZ1090_PIN_TFT_RED6 */ + {2, 28}, /* 50 - TZ1090_PIN_TFT_RED7 */ + {2, 30}, /* 51 - TZ1090_PIN_TFT_GREEN0 */ + {3, 0}, /* 52 - TZ1090_PIN_TFT_GREEN1 */ + {3, 2}, /* 53 - TZ1090_PIN_TFT_GREEN2 */ + {3, 4}, /* 54 - TZ1090_PIN_TFT_GREEN3 */ + {3, 6}, /* 55 - TZ1090_PIN_TFT_GREEN4 */ + {3, 8}, /* 56 - TZ1090_PIN_TFT_GREEN5 */ + {3, 10}, /* 57 - TZ1090_PIN_TFT_GREEN6 */ + {3, 12}, /* 58 - TZ1090_PIN_TFT_GREEN7 */ + {3, 14}, /* 59 - TZ1090_PIN_TFT_BLUE0 */ + + {3, 16}, /* 60 - TZ1090_PIN_TFT_BLUE1 */ + {3, 18}, /* 61 - TZ1090_PIN_TFT_BLUE2 */ + {3, 20}, /* 62 - TZ1090_PIN_TFT_BLUE3 */ + {3, 22}, /* 63 - TZ1090_PIN_TFT_BLUE4 */ + {3, 24}, /* 64 - TZ1090_PIN_TFT_BLUE5 */ + {3, 26}, /* 65 - TZ1090_PIN_TFT_BLUE6 */ + {3, 28}, /* 66 - TZ1090_PIN_TFT_BLUE7 */ + {3, 30}, /* 67 - TZ1090_PIN_TFT_VDDEN_GD */ + {4, 0}, /* 68 - TZ1090_PIN_TFT_PANELCLK */ + {4, 2}, /* 69 - TZ1090_PIN_TFT_BLANK_LS */ + {4, 4}, /* 70 - TZ1090_PIN_TFT_VSYNC_NS */ + {4, 6}, /* 71 - TZ1090_PIN_TFT_HSYNC_NR */ + {4, 8}, /* 72 - TZ1090_PIN_TFT_VD12ACB */ + {4, 10}, /* 73 - TZ1090_PIN_TFT_PWRSAVE */ + {4, 24}, /* 74 - TZ1090_PIN_TX_ON */ + {4, 26}, /* 75 - TZ1090_PIN_RX_ON */ + {4, 28}, /* 76 - TZ1090_PIN_PLL_ON */ + {4, 30}, /* 77 - TZ1090_PIN_PA_ON */ + {5, 0}, /* 78 - TZ1090_PIN_RX_HP */ + {5, 6}, /* 79 - TZ1090_PIN_GAIN0 */ + {5, 8}, /* 80 - TZ1090_PIN_GAIN1 */ + {5, 10}, /* 81 - TZ1090_PIN_GAIN2 */ + {5, 12}, /* 82 - TZ1090_PIN_GAIN3 */ + {5, 14}, /* 83 - TZ1090_PIN_GAIN4 */ + {5, 16}, /* 84 - TZ1090_PIN_GAIN5 */ + {5, 18}, /* 85 - TZ1090_PIN_GAIN6 */ + {5, 20}, /* 86 - TZ1090_PIN_GAIN7 */ + {5, 2}, /* 87 - TZ1090_PIN_ANT_SEL0 */ + {5, 4}, /* 88 - TZ1090_PIN_ANT_SEL1 */ + {0, 0}, /* 89 - TZ1090_PIN_SDH_CLK_IN */ + + {5, 24}, /* 90 - TZ1090_PIN_TCK */ + {5, 26}, /* 91 - TZ1090_PIN_TRST */ + {5, 28}, /* 92 - TZ1090_PIN_TDI */ + {5, 30}, /* 93 - TZ1090_PIN_TDO */ + {6, 0}, /* 94 - TZ1090_PIN_TMS */ + {4, 16}, /* 95 - TZ1090_PIN_CLK_OUT0 */ + {4, 22}, /* 96 - TZ1090_PIN_CLK_OUT1 */ +}; + +static int tz1090_pinconf_reg(struct pinctrl_dev *pctldev, + unsigned int pin, + enum pin_config_param param, + bool report_err, + u32 *reg, u32 *width, u32 *mask, u32 *shift, + u32 *val) +{ + struct tz1090_pinconf_pullup *pu; + + /* All supported pins have controllable input bias */ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + *val = REG_PU_PD_TRISTATE; + break; + case PIN_CONFIG_BIAS_PULL_UP: + *val = REG_PU_PD_UP; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + *val = REG_PU_PD_DOWN; + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + *val = REG_PU_PD_REPEATER; + break; + default: + return -ENOTSUPP; + }; + + /* Only input bias parameters supported */ + pu = &tz1090_pinconf_pullup[pin]; + *reg = REG_PINCTRL_PU_PD + 4*pu->index; + *shift = pu->shift; + *width = 2; + + /* Calculate field information */ + *mask = (BIT(*width) - 1) << *shift; + + return 0; +} + +static int tz1090_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + int ret; + u32 reg, width, mask, shift, val, tmp, arg; + + /* Get register information */ + ret = tz1090_pinconf_reg(pctldev, pin, param, true, + ®, &width, &mask, &shift, &val); + if (ret < 0) + return ret; + + /* Extract field from register */ + tmp = pmx_read(pmx, reg); + arg = ((tmp & mask) >> shift) == val; + + /* Config not active */ + if (!arg) + return -EINVAL; + + /* And pack config */ + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int tz1090_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long config) +{ + struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(config); + unsigned int arg = pinconf_to_config_argument(config); + int ret; + u32 reg, width, mask, shift, val, tmp; + unsigned long flags; + + dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n", + __func__, tz1090_pins[pin].name, config); + + /* Get register information */ + ret = tz1090_pinconf_reg(pctldev, pin, param, true, + ®, &width, &mask, &shift, &val); + if (ret < 0) + return ret; + + /* Unpack argument and range check it */ + if (arg > 1) { + dev_dbg(pctldev->dev, "%s: arg %u out of range\n", + __func__, arg); + return -EINVAL; + } + + /* Write register field */ + __global_lock2(flags); + tmp = pmx_read(pmx, reg); + tmp &= ~mask; + if (arg) + tmp |= val << shift; + pmx_write(pmx, tmp, reg); + __global_unlock2(flags); + + return 0; +} + +static const int tz1090_boolean_map[] = { + [0] = -EINVAL, + [1] = 1, +}; + +static const int tz1090_dr_map[] = { + [REG_DR_2mA] = 2, + [REG_DR_4mA] = 4, + [REG_DR_8mA] = 8, + [REG_DR_12mA] = 12, +}; + +static int tz1090_pinconf_group_reg(struct pinctrl_dev *pctldev, + const struct tz1090_pingroup *g, + enum pin_config_param param, + bool report_err, + u32 *reg, u32 *width, u32 *mask, u32 *shift, + const int **map) +{ + /* Drive configuration applies in groups, but not to all groups. */ + if (!g->drv) { + if (report_err) + dev_dbg(pctldev->dev, + "%s: group %s has no drive control\n", + __func__, g->name); + return -ENOTSUPP; + } + + /* Find information about drive parameter's register */ + switch (param) { + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + *reg = REG_PINCTRL_SCHMITT; + *width = 1; + *map = tz1090_boolean_map; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + *reg = REG_PINCTRL_DR; + *width = 2; + *map = tz1090_dr_map; + break; + default: + return -ENOTSUPP; + }; + + /* Calculate field information */ + *shift = g->slw_bit * *width; + *mask = (BIT(*width) - 1) << *shift; + + return 0; +} + +static int tz1090_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *config) +{ + struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tz1090_pingroup *g; + enum pin_config_param param = pinconf_to_config_param(*config); + int ret, arg; + unsigned int pin; + u32 reg, width, mask, shift, val; + const int *map; + + if (group >= ARRAY_SIZE(tz1090_groups)) { + pin = group - ARRAY_SIZE(tz1090_groups); + return tz1090_pinconf_get(pctldev, pin, config); + } + + g = &tz1090_groups[group]; + if (g->npins == 1) { + pin = g->pins[0]; + ret = tz1090_pinconf_get(pctldev, pin, config); + if (ret != -ENOTSUPP) + return ret; + } + + /* Get register information */ + ret = tz1090_pinconf_group_reg(pctldev, g, param, true, + ®, &width, &mask, &shift, &map); + if (ret < 0) + return ret; + + /* Extract field from register */ + val = pmx_read(pmx, reg); + arg = map[(val & mask) >> shift]; + if (arg < 0) + return arg; + + /* And pack config */ + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int tz1090_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int group, unsigned long config) +{ + struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tz1090_pingroup *g; + enum pin_config_param param = pinconf_to_config_param(config); + unsigned int arg, pin, i; + const unsigned int *pit; + int ret; + u32 reg, width, mask, shift, val; + unsigned long flags; + const int *map; + + if (group >= ARRAY_SIZE(tz1090_groups)) { + pin = group - ARRAY_SIZE(tz1090_groups); + return tz1090_pinconf_set(pctldev, pin, config); + } + + g = &tz1090_groups[group]; + if (g->npins == 1) { + pin = g->pins[0]; + ret = tz1090_pinconf_set(pctldev, pin, config); + if (ret != -ENOTSUPP) + return ret; + } + + dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n", + __func__, g->name, config); + + /* Get register information */ + ret = tz1090_pinconf_group_reg(pctldev, g, param, true, + ®, &width, &mask, &shift, &map); + if (ret < 0) { + /* + * Maybe we're trying to set a per-pin configuration of a group, + * so do the pins one by one. This is mainly as a convenience. + */ + for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) { + ret = tz1090_pinconf_set(pctldev, *pit, config); + if (ret) + return ret; + } + return 0; + } + + /* Unpack argument and map it to register value */ + arg = pinconf_to_config_argument(config); + for (i = 0; i < BIT(width); ++i) { + if (map[i] == arg || (map[i] == -EINVAL && !arg)) { + /* Write register field */ + __global_lock2(flags); + val = pmx_read(pmx, reg); + val &= ~mask; + val |= i << shift; + pmx_write(pmx, val, reg); + __global_unlock2(flags); + return 0; + } + } + + dev_dbg(pctldev->dev, "%s: arg %u not supported\n", + __func__, arg); + return -EINVAL; +} + +static struct pinconf_ops tz1090_pinconf_ops = { + .is_generic = true, + .pin_config_get = tz1090_pinconf_get, + .pin_config_set = tz1090_pinconf_set, + .pin_config_group_get = tz1090_pinconf_group_get, + .pin_config_group_set = tz1090_pinconf_group_set, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + +/* + * Pin control driver setup + */ + +static struct pinctrl_desc tz1090_pinctrl_desc = { + .pctlops = &tz1090_pinctrl_ops, + .pmxops = &tz1090_pinmux_ops, + .confops = &tz1090_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int tz1090_pinctrl_probe(struct platform_device *pdev) +{ + struct tz1090_pmx *pmx; + struct resource *res; + + pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); + if (!pmx) { + dev_err(&pdev->dev, "Can't alloc tz1090_pmx\n"); + return -ENOMEM; + } + pmx->dev = &pdev->dev; + spin_lock_init(&pmx->lock); + + tz1090_pinctrl_desc.name = dev_name(&pdev->dev); + tz1090_pinctrl_desc.pins = tz1090_pins; + tz1090_pinctrl_desc.npins = ARRAY_SIZE(tz1090_pins); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Missing MEM resource\n"); + return -ENODEV; + } + + if (!devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), + dev_name(&pdev->dev))) { + dev_err(&pdev->dev, + "Couldn't request MEM resource\n"); + return -ENODEV; + } + + pmx->regs = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (!pmx->regs) { + dev_err(&pdev->dev, "Couldn't ioremap regs\n"); + return -ENODEV; + } + + pmx->pctl = pinctrl_register(&tz1090_pinctrl_desc, &pdev->dev, pmx); + if (!pmx->pctl) { + dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); + return -ENODEV; + } + + platform_set_drvdata(pdev, pmx); + + dev_info(&pdev->dev, "TZ1090 pinctrl driver initialised\n"); + + return 0; +} + +static int tz1090_pinctrl_remove(struct platform_device *pdev) +{ + struct tz1090_pmx *pmx = platform_get_drvdata(pdev); + + pinctrl_unregister(pmx->pctl); + + return 0; +} + +static struct of_device_id tz1090_pinctrl_of_match[] = { + { .compatible = "img,tz1090-pinctrl", }, + { }, +}; + +static struct platform_driver tz1090_pinctrl_driver = { + .driver = { + .name = "tz1090-pinctrl", + .owner = THIS_MODULE, + .of_match_table = tz1090_pinctrl_of_match, + }, + .probe = tz1090_pinctrl_probe, + .remove = tz1090_pinctrl_remove, +}; + +static int __init tz1090_pinctrl_init(void) +{ + tz1090_init_mux_pins(); + return platform_driver_register(&tz1090_pinctrl_driver); +} +arch_initcall(tz1090_pinctrl_init); + +static void __exit tz1090_pinctrl_exit(void) +{ + platform_driver_unregister(&tz1090_pinctrl_driver); +} +module_exit(tz1090_pinctrl_exit); + +MODULE_AUTHOR("Imagination Technologies Ltd."); +MODULE_DESCRIPTION("Toumaz Xenif TZ1090 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, tz1090_pinctrl_of_match); diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c index 6a3a7503e6a..46a152d1735 100644 --- a/drivers/pinctrl/pinctrl-u300.c +++ b/drivers/pinctrl/pinctrl-u300.c @@ -1100,15 +1100,21 @@ static int u300_pmx_remove(struct platform_device *pdev) struct u300_pmx *upmx = platform_get_drvdata(pdev); pinctrl_unregister(upmx->pctl); - platform_set_drvdata(pdev, NULL); return 0; } +static const struct of_device_id u300_pinctrl_match[] = { + { .compatible = "stericsson,pinctrl-u300" }, + {}, +}; + + static struct platform_driver u300_pmx_driver = { .driver = { .name = DRIVER_NAME, .owner = THIS_MODULE, + .of_match_table = u300_pinctrl_match, }, .probe = u300_pmx_probe, .remove = u300_pmx_remove, diff --git a/drivers/pinctrl/pinctrl-vf610.c b/drivers/pinctrl/pinctrl-vf610.c new file mode 100644 index 00000000000..68a970b1dbc --- /dev/null +++ b/drivers/pinctrl/pinctrl-vf610.c @@ -0,0 +1,338 @@ +/* + * VF610 pinctrl driver based on imx pinmux and pinconf core + * + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-imx.h" + +enum vf610_pads { + VF610_PAD_PTA6 = 0, + VF610_PAD_PTA8 = 1, + VF610_PAD_PTA9 = 2, + VF610_PAD_PTA10 = 3, + VF610_PAD_PTA11 = 4, + VF610_PAD_PTA12 = 5, + VF610_PAD_PTA16 = 6, + VF610_PAD_PTA17 = 7, + VF610_PAD_PTA18 = 8, + VF610_PAD_PTA19 = 9, + VF610_PAD_PTA20 = 10, + VF610_PAD_PTA21 = 11, + VF610_PAD_PTA22 = 12, + VF610_PAD_PTA23 = 13, + VF610_PAD_PTA24 = 14, + VF610_PAD_PTA25 = 15, + VF610_PAD_PTA26 = 16, + VF610_PAD_PTA27 = 17, + VF610_PAD_PTA28 = 18, + VF610_PAD_PTA29 = 19, + VF610_PAD_PTA30 = 20, + VF610_PAD_PTA31 = 21, + VF610_PAD_PTB0 = 22, + VF610_PAD_PTB1 = 23, + VF610_PAD_PTB2 = 24, + VF610_PAD_PTB3 = 25, + VF610_PAD_PTB4 = 26, + VF610_PAD_PTB5 = 27, + VF610_PAD_PTB6 = 28, + VF610_PAD_PTB7 = 29, + VF610_PAD_PTB8 = 30, + VF610_PAD_PTB9 = 31, + VF610_PAD_PTB10 = 32, + VF610_PAD_PTB11 = 33, + VF610_PAD_PTB12 = 34, + VF610_PAD_PTB13 = 35, + VF610_PAD_PTB14 = 36, + VF610_PAD_PTB15 = 37, + VF610_PAD_PTB16 = 38, + VF610_PAD_PTB17 = 39, + VF610_PAD_PTB18 = 40, + VF610_PAD_PTB19 = 41, + VF610_PAD_PTB20 = 42, + VF610_PAD_PTB21 = 43, + VF610_PAD_PTB22 = 44, + VF610_PAD_PTC0 = 45, + VF610_PAD_PTC1 = 46, + VF610_PAD_PTC2 = 47, + VF610_PAD_PTC3 = 48, + VF610_PAD_PTC4 = 49, + VF610_PAD_PTC5 = 50, + VF610_PAD_PTC6 = 51, + VF610_PAD_PTC7 = 52, + VF610_PAD_PTC8 = 53, + VF610_PAD_PTC9 = 54, + VF610_PAD_PTC10 = 55, + VF610_PAD_PTC11 = 56, + VF610_PAD_PTC12 = 57, + VF610_PAD_PTC13 = 58, + VF610_PAD_PTC14 = 59, + VF610_PAD_PTC15 = 60, + VF610_PAD_PTC16 = 61, + VF610_PAD_PTC17 = 62, + VF610_PAD_PTD31 = 63, + VF610_PAD_PTD30 = 64, + VF610_PAD_PTD29 = 65, + VF610_PAD_PTD28 = 66, + VF610_PAD_PTD27 = 67, + VF610_PAD_PTD26 = 68, + VF610_PAD_PTD25 = 69, + VF610_PAD_PTD24 = 70, + VF610_PAD_PTD23 = 71, + VF610_PAD_PTD22 = 72, + VF610_PAD_PTD21 = 73, + VF610_PAD_PTD20 = 74, + VF610_PAD_PTD19 = 75, + VF610_PAD_PTD18 = 76, + VF610_PAD_PTD17 = 77, + VF610_PAD_PTD16 = 78, + VF610_PAD_PTD0 = 79, + VF610_PAD_PTD1 = 80, + VF610_PAD_PTD2 = 81, + VF610_PAD_PTD3 = 82, + VF610_PAD_PTD4 = 83, + VF610_PAD_PTD5 = 84, + VF610_PAD_PTD6 = 85, + VF610_PAD_PTD7 = 86, + VF610_PAD_PTD8 = 87, + VF610_PAD_PTD9 = 88, + VF610_PAD_PTD10 = 89, + VF610_PAD_PTD11 = 90, + VF610_PAD_PTD12 = 91, + VF610_PAD_PTD13 = 92, + VF610_PAD_PTB23 = 93, + VF610_PAD_PTB24 = 94, + VF610_PAD_PTB25 = 95, + VF610_PAD_PTB26 = 96, + VF610_PAD_PTB27 = 97, + VF610_PAD_PTB28 = 98, + VF610_PAD_PTC26 = 99, + VF610_PAD_PTC27 = 100, + VF610_PAD_PTC28 = 101, + VF610_PAD_PTC29 = 102, + VF610_PAD_PTC30 = 103, + VF610_PAD_PTC31 = 104, + VF610_PAD_PTE0 = 105, + VF610_PAD_PTE1 = 106, + VF610_PAD_PTE2 = 107, + VF610_PAD_PTE3 = 108, + VF610_PAD_PTE4 = 109, + VF610_PAD_PTE5 = 110, + VF610_PAD_PTE6 = 111, + VF610_PAD_PTE7 = 112, + VF610_PAD_PTE8 = 113, + VF610_PAD_PTE9 = 114, + VF610_PAD_PTE10 = 115, + VF610_PAD_PTE11 = 116, + VF610_PAD_PTE12 = 117, + VF610_PAD_PTE13 = 118, + VF610_PAD_PTE14 = 119, + VF610_PAD_PTE15 = 120, + VF610_PAD_PTE16 = 121, + VF610_PAD_PTE17 = 122, + VF610_PAD_PTE18 = 123, + VF610_PAD_PTE19 = 124, + VF610_PAD_PTE20 = 125, + VF610_PAD_PTE21 = 126, + VF610_PAD_PTE22 = 127, + VF610_PAD_PTE23 = 128, + VF610_PAD_PTE24 = 129, + VF610_PAD_PTE25 = 130, + VF610_PAD_PTE26 = 131, + VF610_PAD_PTE27 = 132, + VF610_PAD_PTE28 = 133, + VF610_PAD_PTA7 = 134, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = { + IMX_PINCTRL_PIN(VF610_PAD_PTA6), + IMX_PINCTRL_PIN(VF610_PAD_PTA8), + IMX_PINCTRL_PIN(VF610_PAD_PTA9), + IMX_PINCTRL_PIN(VF610_PAD_PTA10), + IMX_PINCTRL_PIN(VF610_PAD_PTA11), + IMX_PINCTRL_PIN(VF610_PAD_PTA12), + IMX_PINCTRL_PIN(VF610_PAD_PTA16), + IMX_PINCTRL_PIN(VF610_PAD_PTA17), + IMX_PINCTRL_PIN(VF610_PAD_PTA18), + IMX_PINCTRL_PIN(VF610_PAD_PTA19), + IMX_PINCTRL_PIN(VF610_PAD_PTA20), + IMX_PINCTRL_PIN(VF610_PAD_PTA21), + IMX_PINCTRL_PIN(VF610_PAD_PTA22), + IMX_PINCTRL_PIN(VF610_PAD_PTA23), + IMX_PINCTRL_PIN(VF610_PAD_PTA24), + IMX_PINCTRL_PIN(VF610_PAD_PTA25), + IMX_PINCTRL_PIN(VF610_PAD_PTA26), + IMX_PINCTRL_PIN(VF610_PAD_PTA27), + IMX_PINCTRL_PIN(VF610_PAD_PTA28), + IMX_PINCTRL_PIN(VF610_PAD_PTA29), + IMX_PINCTRL_PIN(VF610_PAD_PTA30), + IMX_PINCTRL_PIN(VF610_PAD_PTA31), + IMX_PINCTRL_PIN(VF610_PAD_PTB0), + IMX_PINCTRL_PIN(VF610_PAD_PTB1), + IMX_PINCTRL_PIN(VF610_PAD_PTB2), + IMX_PINCTRL_PIN(VF610_PAD_PTB3), + IMX_PINCTRL_PIN(VF610_PAD_PTB4), + IMX_PINCTRL_PIN(VF610_PAD_PTB5), + IMX_PINCTRL_PIN(VF610_PAD_PTB6), + IMX_PINCTRL_PIN(VF610_PAD_PTB7), + IMX_PINCTRL_PIN(VF610_PAD_PTB8), + IMX_PINCTRL_PIN(VF610_PAD_PTB9), + IMX_PINCTRL_PIN(VF610_PAD_PTB10), + IMX_PINCTRL_PIN(VF610_PAD_PTB11), + IMX_PINCTRL_PIN(VF610_PAD_PTB12), + IMX_PINCTRL_PIN(VF610_PAD_PTB13), + IMX_PINCTRL_PIN(VF610_PAD_PTB14), + IMX_PINCTRL_PIN(VF610_PAD_PTB15), + IMX_PINCTRL_PIN(VF610_PAD_PTB16), + IMX_PINCTRL_PIN(VF610_PAD_PTB17), + IMX_PINCTRL_PIN(VF610_PAD_PTB18), + IMX_PINCTRL_PIN(VF610_PAD_PTB19), + IMX_PINCTRL_PIN(VF610_PAD_PTB20), + IMX_PINCTRL_PIN(VF610_PAD_PTB21), + IMX_PINCTRL_PIN(VF610_PAD_PTB22), + IMX_PINCTRL_PIN(VF610_PAD_PTC0), + IMX_PINCTRL_PIN(VF610_PAD_PTC1), + IMX_PINCTRL_PIN(VF610_PAD_PTC2), + IMX_PINCTRL_PIN(VF610_PAD_PTC3), + IMX_PINCTRL_PIN(VF610_PAD_PTC4), + IMX_PINCTRL_PIN(VF610_PAD_PTC5), + IMX_PINCTRL_PIN(VF610_PAD_PTC6), + IMX_PINCTRL_PIN(VF610_PAD_PTC7), + IMX_PINCTRL_PIN(VF610_PAD_PTC8), + IMX_PINCTRL_PIN(VF610_PAD_PTC9), + IMX_PINCTRL_PIN(VF610_PAD_PTC10), + IMX_PINCTRL_PIN(VF610_PAD_PTC11), + IMX_PINCTRL_PIN(VF610_PAD_PTC12), + IMX_PINCTRL_PIN(VF610_PAD_PTC13), + IMX_PINCTRL_PIN(VF610_PAD_PTC14), + IMX_PINCTRL_PIN(VF610_PAD_PTC15), + IMX_PINCTRL_PIN(VF610_PAD_PTC16), + IMX_PINCTRL_PIN(VF610_PAD_PTC17), + IMX_PINCTRL_PIN(VF610_PAD_PTD31), + IMX_PINCTRL_PIN(VF610_PAD_PTD30), + IMX_PINCTRL_PIN(VF610_PAD_PTD29), + IMX_PINCTRL_PIN(VF610_PAD_PTD28), + IMX_PINCTRL_PIN(VF610_PAD_PTD27), + IMX_PINCTRL_PIN(VF610_PAD_PTD26), + IMX_PINCTRL_PIN(VF610_PAD_PTD25), + IMX_PINCTRL_PIN(VF610_PAD_PTD24), + IMX_PINCTRL_PIN(VF610_PAD_PTD23), + IMX_PINCTRL_PIN(VF610_PAD_PTD22), + IMX_PINCTRL_PIN(VF610_PAD_PTD21), + IMX_PINCTRL_PIN(VF610_PAD_PTD20), + IMX_PINCTRL_PIN(VF610_PAD_PTD19), + IMX_PINCTRL_PIN(VF610_PAD_PTD18), + IMX_PINCTRL_PIN(VF610_PAD_PTD17), + IMX_PINCTRL_PIN(VF610_PAD_PTD16), + IMX_PINCTRL_PIN(VF610_PAD_PTD0), + IMX_PINCTRL_PIN(VF610_PAD_PTD1), + IMX_PINCTRL_PIN(VF610_PAD_PTD2), + IMX_PINCTRL_PIN(VF610_PAD_PTD3), + IMX_PINCTRL_PIN(VF610_PAD_PTD4), + IMX_PINCTRL_PIN(VF610_PAD_PTD5), + IMX_PINCTRL_PIN(VF610_PAD_PTD6), + IMX_PINCTRL_PIN(VF610_PAD_PTD7), + IMX_PINCTRL_PIN(VF610_PAD_PTD8), + IMX_PINCTRL_PIN(VF610_PAD_PTD9), + IMX_PINCTRL_PIN(VF610_PAD_PTD10), + IMX_PINCTRL_PIN(VF610_PAD_PTD11), + IMX_PINCTRL_PIN(VF610_PAD_PTD12), + IMX_PINCTRL_PIN(VF610_PAD_PTD13), + IMX_PINCTRL_PIN(VF610_PAD_PTB23), + IMX_PINCTRL_PIN(VF610_PAD_PTB24), + IMX_PINCTRL_PIN(VF610_PAD_PTB25), + IMX_PINCTRL_PIN(VF610_PAD_PTB26), + IMX_PINCTRL_PIN(VF610_PAD_PTB27), + IMX_PINCTRL_PIN(VF610_PAD_PTB28), + IMX_PINCTRL_PIN(VF610_PAD_PTC26), + IMX_PINCTRL_PIN(VF610_PAD_PTC27), + IMX_PINCTRL_PIN(VF610_PAD_PTC28), + IMX_PINCTRL_PIN(VF610_PAD_PTC29), + IMX_PINCTRL_PIN(VF610_PAD_PTC30), + IMX_PINCTRL_PIN(VF610_PAD_PTC31), + IMX_PINCTRL_PIN(VF610_PAD_PTE0), + IMX_PINCTRL_PIN(VF610_PAD_PTE1), + IMX_PINCTRL_PIN(VF610_PAD_PTE2), + IMX_PINCTRL_PIN(VF610_PAD_PTE3), + IMX_PINCTRL_PIN(VF610_PAD_PTE4), + IMX_PINCTRL_PIN(VF610_PAD_PTE5), + IMX_PINCTRL_PIN(VF610_PAD_PTE6), + IMX_PINCTRL_PIN(VF610_PAD_PTE7), + IMX_PINCTRL_PIN(VF610_PAD_PTE8), + IMX_PINCTRL_PIN(VF610_PAD_PTE9), + IMX_PINCTRL_PIN(VF610_PAD_PTE10), + IMX_PINCTRL_PIN(VF610_PAD_PTE11), + IMX_PINCTRL_PIN(VF610_PAD_PTE12), + IMX_PINCTRL_PIN(VF610_PAD_PTE13), + IMX_PINCTRL_PIN(VF610_PAD_PTE14), + IMX_PINCTRL_PIN(VF610_PAD_PTE15), + IMX_PINCTRL_PIN(VF610_PAD_PTE16), + IMX_PINCTRL_PIN(VF610_PAD_PTE17), + IMX_PINCTRL_PIN(VF610_PAD_PTE18), + IMX_PINCTRL_PIN(VF610_PAD_PTE19), + IMX_PINCTRL_PIN(VF610_PAD_PTE20), + IMX_PINCTRL_PIN(VF610_PAD_PTE21), + IMX_PINCTRL_PIN(VF610_PAD_PTE22), + IMX_PINCTRL_PIN(VF610_PAD_PTE23), + IMX_PINCTRL_PIN(VF610_PAD_PTE24), + IMX_PINCTRL_PIN(VF610_PAD_PTE25), + IMX_PINCTRL_PIN(VF610_PAD_PTE26), + IMX_PINCTRL_PIN(VF610_PAD_PTE27), + IMX_PINCTRL_PIN(VF610_PAD_PTE28), + IMX_PINCTRL_PIN(VF610_PAD_PTA7), +}; + +static struct imx_pinctrl_soc_info vf610_pinctrl_info = { + .pins = vf610_pinctrl_pads, + .npins = ARRAY_SIZE(vf610_pinctrl_pads), + .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG, +}; + +static struct of_device_id vf610_pinctrl_of_match[] = { + { .compatible = "fsl,vf610-iomuxc", }, + { /* sentinel */ } +}; + +static int vf610_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &vf610_pinctrl_info); +} + +static struct platform_driver vf610_pinctrl_driver = { + .driver = { + .name = "vf610-pinctrl", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(vf610_pinctrl_of_match), + }, + .probe = vf610_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init vf610_pinctrl_init(void) +{ + return platform_driver_register(&vf610_pinctrl_driver); +} +arch_initcall(vf610_pinctrl_init); + +static void __exit vf610_pinctrl_exit(void) +{ + platform_driver_unregister(&vf610_pinctrl_driver); +} +module_exit(vf610_pinctrl_exit); + +MODULE_DESCRIPTION("Freescale VF610 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index f8a2ae413c7..636a882b406 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -5,8 +5,6 @@ if ARCH_SHMOBILE || SUPERH config PINCTRL_SH_PFC - # XXX move off the gpio dependency - depends on GPIOLIB select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB select PINMUX select PINCONF @@ -32,11 +30,21 @@ config PINCTRL_PFC_R8A7740 depends on ARCH_R8A7740 select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A7778 + def_bool y + depends on ARCH_R8A7778 + select PINCTRL_SH_PFC + config PINCTRL_PFC_R8A7779 def_bool y depends on ARCH_R8A7779 select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A7790 + def_bool y + depends on ARCH_R8A7790 + select PINCTRL_SH_PFC + config PINCTRL_PFC_SH7203 def_bool y depends on CPU_SUBTYPE_SH7203 @@ -64,6 +72,7 @@ config PINCTRL_PFC_SH73A0 def_bool y depends on ARCH_SH73A0 select PINCTRL_SH_PFC + select REGULATOR config PINCTRL_PFC_SH7720 def_bool y diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 211cd8e98a8..5e0c222c12d 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -5,7 +5,9 @@ endif obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o +obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o +obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index b551336924a..f3fc66b2437 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -18,6 +18,8 @@ #include <linux/ioport.h> #include <linux/kernel.h> #include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> #include <linux/pinctrl/machine.h> #include <linux/platform_device.h> #include <linux/slab.h> @@ -348,14 +350,72 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) return 0; } +#ifdef CONFIG_OF +static const struct of_device_id sh_pfc_of_table[] = { +#ifdef CONFIG_PINCTRL_PFC_R8A73A4 + { + .compatible = "renesas,pfc-r8a73a4", + .data = &r8a73a4_pinmux_info, + }, +#endif +#ifdef CONFIG_PINCTRL_PFC_R8A7740 + { + .compatible = "renesas,pfc-r8a7740", + .data = &r8a7740_pinmux_info, + }, +#endif +#ifdef CONFIG_PINCTRL_PFC_R8A7778 + { + .compatible = "renesas,pfc-r8a7778", + .data = &r8a7778_pinmux_info, + }, +#endif +#ifdef CONFIG_PINCTRL_PFC_R8A7779 + { + .compatible = "renesas,pfc-r8a7779", + .data = &r8a7779_pinmux_info, + }, +#endif +#ifdef CONFIG_PINCTRL_PFC_R8A7790 + { + .compatible = "renesas,pfc-r8a7790", + .data = &r8a7790_pinmux_info, + }, +#endif +#ifdef CONFIG_PINCTRL_PFC_SH7372 + { + .compatible = "renesas,pfc-sh7372", + .data = &sh7372_pinmux_info, + }, +#endif +#ifdef CONFIG_PINCTRL_PFC_SH73A0 + { + .compatible = "renesas,pfc-sh73a0", + .data = &sh73a0_pinmux_info, + }, +#endif + { }, +}; +MODULE_DEVICE_TABLE(of, sh_pfc_of_table); +#endif + static int sh_pfc_probe(struct platform_device *pdev) { + const struct platform_device_id *platid = platform_get_device_id(pdev); +#ifdef CONFIG_OF + struct device_node *np = pdev->dev.of_node; +#endif const struct sh_pfc_soc_info *info; struct sh_pfc *pfc; int ret; - info = pdev->id_entry->driver_data - ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data; +#ifdef CONFIG_OF + if (np) + info = of_match_device(sh_pfc_of_table, &pdev->dev)->data; + else +#endif + info = platid ? (const void *)platid->driver_data : NULL; + if (info == NULL) return -ENODEV; @@ -372,6 +432,12 @@ static int sh_pfc_probe(struct platform_device *pdev) spin_lock_init(&pfc->lock); + if (info->ops && info->ops->init) { + ret = info->ops->init(pfc); + if (ret < 0) + return ret; + } + pinctrl_provide_dummies(); /* @@ -379,7 +445,7 @@ static int sh_pfc_probe(struct platform_device *pdev) */ ret = sh_pfc_register_pinctrl(pfc); if (unlikely(ret != 0)) - return ret; + goto error; #ifdef CONFIG_GPIO_SH_PFC /* @@ -401,6 +467,11 @@ static int sh_pfc_probe(struct platform_device *pdev) dev_info(pfc->dev, "%s support registered\n", info->name); return 0; + +error: + if (info->ops && info->ops->exit) + info->ops->exit(pfc); + return ret; } static int sh_pfc_remove(struct platform_device *pdev) @@ -412,6 +483,9 @@ static int sh_pfc_remove(struct platform_device *pdev) #endif sh_pfc_unregister_pinctrl(pfc); + if (pfc->info->ops && pfc->info->ops->exit) + pfc->info->ops->exit(pfc); + platform_set_drvdata(pdev, NULL); return 0; @@ -424,9 +498,15 @@ static const struct platform_device_id sh_pfc_id_table[] = { #ifdef CONFIG_PINCTRL_PFC_R8A7740 { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A7778 + { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A7779 { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A7790 + { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info }, +#endif #ifdef CONFIG_PINCTRL_PFC_SH7203 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, #endif @@ -481,6 +561,7 @@ static struct platform_driver sh_pfc_driver = { .driver = { .name = DRV_NAME, .owner = THIS_MODULE, + .of_match_table = of_match_ptr(sh_pfc_of_table), }, }; diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index 89cb4289d76..f02ba1dde3a 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -11,6 +11,7 @@ #define __SH_PFC_CORE_H__ #include <linux/compiler.h> +#include <linux/spinlock.h> #include <linux/types.h> #include "sh_pfc.h" @@ -27,6 +28,7 @@ struct sh_pfc_pinctrl; struct sh_pfc { struct device *dev; const struct sh_pfc_soc_info *info; + void *soc_data; spinlock_t lock; unsigned int num_windows; @@ -56,7 +58,9 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; extern const struct sh_pfc_soc_info r8a7740_pinmux_info; +extern const struct sh_pfc_soc_info r8a7778_pinmux_info; extern const struct sh_pfc_soc_info r8a7779_pinmux_info; +extern const struct sh_pfc_soc_info r8a7790_pinmux_info; extern const struct sh_pfc_soc_info sh7203_pinmux_info; extern const struct sh_pfc_soc_info sh7264_pinmux_info; extern const struct sh_pfc_soc_info sh7269_pinmux_info; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index bbff5596e92..82bf6aba007 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -1488,6 +1488,66 @@ IRQC_PINS_MUX(326, 54); IRQC_PINS_MUX(327, 55); IRQC_PINS_MUX(328, 56); IRQC_PINS_MUX(329, 57); +/* - MMCIF0 ----------------------------------------------------------------- */ +static const unsigned int mmc0_data1_pins[] = { + /* D[0] */ + 164, +}; +static const unsigned int mmc0_data1_mux[] = { + MMCD0_0_MARK, +}; +static const unsigned int mmc0_data4_pins[] = { + /* D[0:3] */ + 164, 165, 166, 167, +}; +static const unsigned int mmc0_data4_mux[] = { + MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, +}; +static const unsigned int mmc0_data8_pins[] = { + /* D[0:7] */ + 164, 165, 166, 167, 168, 169, 170, 171, +}; +static const unsigned int mmc0_data8_mux[] = { + MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, + MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK, +}; +static const unsigned int mmc0_ctrl_pins[] = { + /* CMD, CLK */ + 172, 173, +}; +static const unsigned int mmc0_ctrl_mux[] = { + MMCCMD0_MARK, MMCCLK0_MARK, +}; +/* - MMCIF1 ----------------------------------------------------------------- */ +static const unsigned int mmc1_data1_pins[] = { + /* D[0] */ + 199, +}; +static const unsigned int mmc1_data1_mux[] = { + MMCD1_0_MARK, +}; +static const unsigned int mmc1_data4_pins[] = { + /* D[0:3] */ + 199, 198, 197, 196, +}; +static const unsigned int mmc1_data4_mux[] = { + MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, +}; +static const unsigned int mmc1_data8_pins[] = { + /* D[0:7] */ + 199, 198, 197, 196, 195, 194, 193, 192, +}; +static const unsigned int mmc1_data8_mux[] = { + MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, + MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK, +}; +static const unsigned int mmc1_ctrl_pins[] = { + /* CMD, CLK */ + 200, 203, +}; +static const unsigned int mmc1_ctrl_mux[] = { + MMCCMD1_MARK, MMCCLK1_MARK, +}; /* - SCIFA0 ----------------------------------------------------------------- */ static const unsigned int scifa0_data_pins[] = { /* SCIFA0_RXD, SCIFA0_TXD */ @@ -1683,6 +1743,86 @@ static const unsigned int scifb3_ctrl_b_pins[] = { static const unsigned int scifb3_ctrl_b_mux[] = { SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK, }; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + 302, +}; +static const unsigned int sdhi0_data1_mux[] = { + SDHID0_0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + 302, 303, 304, 305, +}; +static const unsigned int sdhi0_data4_mux[] = { + SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CLK, CMD */ + 308, 306, +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SDHICLK0_MARK, SDHICMD0_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + 301, +}; +static const unsigned int sdhi0_cd_mux[] = { + SDHICD0_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + 307, +}; +static const unsigned int sdhi0_wp_mux[] = { + SDHIWP0_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + 289, +}; +static const unsigned int sdhi1_data1_mux[] = { + SDHID1_0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + 289, 290, 291, 292, +}; +static const unsigned int sdhi1_data4_mux[] = { + SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CLK, CMD */ + 293, 294, +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SDHICLK1_MARK, SDHICMD1_MARK, +}; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + 295, +}; +static const unsigned int sdhi2_data1_mux[] = { + SDHID2_0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + 295, 296, 297, 298, +}; +static const unsigned int sdhi2_data4_mux[] = { + SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CLK, CMD */ + 299, 300, +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SDHICLK2_MARK, SDHICMD2_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(irqc_irq0), @@ -1743,6 +1883,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(irqc_irq55), SH_PFC_PIN_GROUP(irqc_irq56), SH_PFC_PIN_GROUP(irqc_irq57), + SH_PFC_PIN_GROUP(mmc0_data1), + SH_PFC_PIN_GROUP(mmc0_data4), + SH_PFC_PIN_GROUP(mmc0_data8), + SH_PFC_PIN_GROUP(mmc0_ctrl), + SH_PFC_PIN_GROUP(mmc1_data1), + SH_PFC_PIN_GROUP(mmc1_data4), + SH_PFC_PIN_GROUP(mmc1_data8), + SH_PFC_PIN_GROUP(mmc1_ctrl), SH_PFC_PIN_GROUP(scifa0_data), SH_PFC_PIN_GROUP(scifa0_clk), SH_PFC_PIN_GROUP(scifa0_ctrl), @@ -1770,6 +1918,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scifb3_data_b), SH_PFC_PIN_GROUP(scifb3_clk_b), SH_PFC_PIN_GROUP(scifb3_ctrl_b), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), }; static const char * const irqc_groups[] = { @@ -1833,6 +1992,20 @@ static const char * const irqc_groups[] = { "irqc_irq57", }; +static const char * const mmc0_groups[] = { + "mmc0_data1", + "mmc0_data4", + "mmc0_data8", + "mmc0_ctrl", +}; + +static const char * const mmc1_groups[] = { + "mmc1_data1", + "mmc1_data4", + "mmc1_data8", + "mmc1_ctrl", +}; + static const char * const scifa0_groups[] = { "scifa0_data", "scifa0_clk", @@ -1878,14 +2051,39 @@ static const char * const scifb3_groups[] = { "scifb3_ctrl_b", }; +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_ctrl", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(irqc), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(mmc1), SH_PFC_FUNCTION(scifa0), SH_PFC_FUNCTION(scifa1), SH_PFC_FUNCTION(scifb0), SH_PFC_FUNCTION(scifb1), SH_PFC_FUNCTION(scifb2), SH_PFC_FUNCTION(scifb3), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), }; #undef PORTCR diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index bbd87d29bfd..f6ea47c433b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -18,10 +18,14 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <linux/io.h> #include <linux/kernel.h> +#include <linux/pinctrl/pinconf-generic.h> + #include <mach/r8a7740.h> #include <mach/irqs.h> +#include "core.h" #include "sh_pfc.h" #define CPU_ALL_PORT(fn, pfx, sfx) \ @@ -30,6 +34,29 @@ PORT_10(fn, pfx##20, sfx), \ PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx) +#undef _GPIO_PORT +#define _GPIO_PORT(gpio, sfx) \ + [gpio] = { \ + .name = __stringify(PORT##gpio), \ + .enum_id = PORT##gpio##_DATA, \ + } + +#define IRQC_PIN_MUX(irq, pin) \ +static const unsigned int intc_irq##irq##_pins[] = { \ + pin, \ +}; \ +static const unsigned int intc_irq##irq##_mux[] = { \ + IRQ##irq##_MARK, \ +} + +#define IRQC_PINS_MUX(irq, idx, pin) \ +static const unsigned int intc_irq##irq##_##idx##_pins[] = { \ + pin, \ +}; \ +static const unsigned int intc_irq##irq##_##idx##_mux[] = { \ + IRQ##irq##_PORT##pin##_MARK, \ +} + enum { PINMUX_RESERVED = 0, @@ -43,16 +70,6 @@ enum { PORT_ALL(IN), PINMUX_INPUT_END, - /* PORT0_IN_PU -> PORT211_IN_PU */ - PINMUX_INPUT_PULLUP_BEGIN, - PORT_ALL(IN_PU), - PINMUX_INPUT_PULLUP_END, - - /* PORT0_IN_PD -> PORT211_IN_PD */ - PINMUX_INPUT_PULLDOWN_BEGIN, - PORT_ALL(IN_PD), - PINMUX_INPUT_PULLDOWN_END, - /* PORT0_OUT -> PORT211_OUT */ PINMUX_OUTPUT_BEGIN, PORT_ALL(OUT), @@ -261,8 +278,6 @@ enum { SCIFB_CTS_PORT173_MARK, /* LCD0 */ - LCDC0_SELECT_MARK, - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, @@ -285,8 +300,6 @@ enum { LCD0_LCLK_PORT102_MARK, /* LCD1 */ - LCDC1_SELECT_MARK, - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, @@ -577,137 +590,11 @@ enum { PINMUX_MARK_END, }; +#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) + static const pinmux_enum_t pinmux_data[] = { - /* specify valid pin states for each pin in GPIO mode */ - - /* I/O and Pull U/D */ - PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1), - PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3), - PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5), - PORT_DATA_IO_PD(6), PORT_DATA_IO(7), - PORT_DATA_IO(8), PORT_DATA_IO(9), - - PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11), - PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13), - PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15), - PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17), - PORT_DATA_IO(18), PORT_DATA_IO_PU(19), - - PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21), - PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23), - PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25), - PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27), - PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29), - - PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31), - PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33), - PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35), - PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37), - PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39), - - PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41), - PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43), - PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45), - PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47), - PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49), - - PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51), - PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53), - PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55), - PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57), - PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59), - - PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61), - PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63), - PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65), - PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67), - PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69), - - PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71), - PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73), - PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75), - PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77), - PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79), - - PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81), - PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83), - PORT_DATA_IO(84), PORT_DATA_IO_PD(85), - PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87), - PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89), - - PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91), - PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93), - PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95), - PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), - PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99), - - PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101), - PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103), - PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105), - PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107), - PORT_DATA_IO(108), PORT_DATA_IO(109), - - PORT_DATA_IO(110), PORT_DATA_IO(111), - PORT_DATA_IO(112), PORT_DATA_IO(113), - PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115), - PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117), - PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119), - - PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121), - PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123), - PORT_DATA_IO_PD(124), PORT_DATA_IO(125), - PORT_DATA_IO(126), PORT_DATA_IO(127), - PORT_DATA_IO(128), PORT_DATA_IO(129), - - PORT_DATA_IO(130), PORT_DATA_IO(131), - PORT_DATA_IO(132), PORT_DATA_IO(133), - PORT_DATA_IO(134), PORT_DATA_IO(135), - PORT_DATA_IO(136), PORT_DATA_IO(137), - PORT_DATA_IO(138), PORT_DATA_IO(139), - - PORT_DATA_IO(140), PORT_DATA_IO(141), - PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143), - PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145), - PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147), - PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149), - - PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151), - PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153), - PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155), - PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157), - PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159), - - PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161), - PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), - PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165), - PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167), - PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169), - - PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171), - PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173), - PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175), - PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177), - PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179), - - PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181), - PORT_DATA_IO_PU(182), PORT_DATA_IO(183), - PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185), - PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187), - PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189), - - PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191), - PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193), - PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195), - PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197), - PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199), - - PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201), - PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203), - PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205), - PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207), - PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209), - - PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211), + PINMUX_DATA_GP_ALL(), /* Port0 */ PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1), @@ -986,7 +873,7 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1), /* Port58 */ - PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1), + PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1, MSEL3CR_6_0), PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3), PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1), PINMUX_DATA(DV_D0_MARK, PORT58_FN6), @@ -1633,10 +1520,6 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1), PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1), - /* LCDC select */ - PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0), - PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1), - /* SDENC */ PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0), PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1), @@ -1654,9 +1537,565 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0), }; +#define R8A7740_PIN(pin, cfgs) \ + { \ + .name = __stringify(PORT##pin), \ + .enum_id = PORT##pin##_DATA, \ + .configs = cfgs, \ + } + +#define __I (SH_PFC_PIN_CFG_INPUT) +#define __O (SH_PFC_PIN_CFG_OUTPUT) +#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) +#define __PD (SH_PFC_PIN_CFG_PULL_DOWN) +#define __PU (SH_PFC_PIN_CFG_PULL_UP) +#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) + +#define R8A7740_PIN_I_PD(pin) R8A7740_PIN(pin, __I | __PD) +#define R8A7740_PIN_I_PU(pin) R8A7740_PIN(pin, __I | __PU) +#define R8A7740_PIN_I_PU_PD(pin) R8A7740_PIN(pin, __I | __PUD) +#define R8A7740_PIN_IO(pin) R8A7740_PIN(pin, __IO) +#define R8A7740_PIN_IO_PD(pin) R8A7740_PIN(pin, __IO | __PD) +#define R8A7740_PIN_IO_PU(pin) R8A7740_PIN(pin, __IO | __PU) +#define R8A7740_PIN_IO_PU_PD(pin) R8A7740_PIN(pin, __IO | __PUD) +#define R8A7740_PIN_O(pin) R8A7740_PIN(pin, __O) +#define R8A7740_PIN_O_PU_PD(pin) R8A7740_PIN(pin, __O | __PUD) + static struct sh_pfc_pin pinmux_pins[] = { - GPIO_PORT_ALL(), + /* Table 56-1 (I/O and Pull U/D) */ + R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1), + R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3), + R8A7740_PIN_IO_PD(4), R8A7740_PIN_IO_PD(5), + R8A7740_PIN_IO_PD(6), R8A7740_PIN_IO(7), + R8A7740_PIN_IO(8), R8A7740_PIN_IO(9), + R8A7740_PIN_IO_PD(10), R8A7740_PIN_IO_PD(11), + R8A7740_PIN_IO_PD(12), R8A7740_PIN_IO_PU_PD(13), + R8A7740_PIN_IO_PD(14), R8A7740_PIN_IO_PD(15), + R8A7740_PIN_IO_PD(16), R8A7740_PIN_IO_PD(17), + R8A7740_PIN_IO(18), R8A7740_PIN_IO_PU(19), + R8A7740_PIN_IO_PU_PD(20), R8A7740_PIN_IO_PD(21), + R8A7740_PIN_IO_PU_PD(22), R8A7740_PIN_IO(23), + R8A7740_PIN_IO_PU(24), R8A7740_PIN_IO_PU(25), + R8A7740_PIN_IO_PU(26), R8A7740_PIN_IO_PU(27), + R8A7740_PIN_IO_PU(28), R8A7740_PIN_IO_PU(29), + R8A7740_PIN_IO_PU(30), R8A7740_PIN_IO_PD(31), + R8A7740_PIN_IO_PD(32), R8A7740_PIN_IO_PD(33), + R8A7740_PIN_IO_PD(34), R8A7740_PIN_IO_PU(35), + R8A7740_PIN_IO_PU(36), R8A7740_PIN_IO_PD(37), + R8A7740_PIN_IO_PU(38), R8A7740_PIN_IO_PD(39), + R8A7740_PIN_IO_PU_PD(40), R8A7740_PIN_IO_PD(41), + R8A7740_PIN_IO_PD(42), R8A7740_PIN_IO_PU_PD(43), + R8A7740_PIN_IO_PU_PD(44), R8A7740_PIN_IO_PU_PD(45), + R8A7740_PIN_IO_PU_PD(46), R8A7740_PIN_IO_PU_PD(47), + R8A7740_PIN_IO_PU_PD(48), R8A7740_PIN_IO_PU_PD(49), + R8A7740_PIN_IO_PU_PD(50), R8A7740_PIN_IO_PD(51), + R8A7740_PIN_IO_PD(52), R8A7740_PIN_IO_PD(53), + R8A7740_PIN_IO_PD(54), R8A7740_PIN_IO_PU_PD(55), + R8A7740_PIN_IO_PU_PD(56), R8A7740_PIN_IO_PU_PD(57), + R8A7740_PIN_IO_PU_PD(58), R8A7740_PIN_IO_PU_PD(59), + R8A7740_PIN_IO_PU_PD(60), R8A7740_PIN_IO_PD(61), + R8A7740_PIN_IO_PD(62), R8A7740_PIN_IO_PD(63), + R8A7740_PIN_IO_PD(64), R8A7740_PIN_IO_PD(65), + R8A7740_PIN_IO_PU_PD(66), R8A7740_PIN_IO_PU_PD(67), + R8A7740_PIN_IO_PU_PD(68), R8A7740_PIN_IO_PU_PD(69), + R8A7740_PIN_IO_PU_PD(70), R8A7740_PIN_IO_PU_PD(71), + R8A7740_PIN_IO_PU_PD(72), R8A7740_PIN_IO_PU_PD(73), + R8A7740_PIN_IO_PU_PD(74), R8A7740_PIN_IO_PU_PD(75), + R8A7740_PIN_IO_PU_PD(76), R8A7740_PIN_IO_PU_PD(77), + R8A7740_PIN_IO_PU_PD(78), R8A7740_PIN_IO_PU_PD(79), + R8A7740_PIN_IO_PU_PD(80), R8A7740_PIN_IO_PU_PD(81), + R8A7740_PIN_IO(82), R8A7740_PIN_IO_PU_PD(83), + R8A7740_PIN_IO(84), R8A7740_PIN_IO_PD(85), + R8A7740_PIN_IO_PD(86), R8A7740_PIN_IO_PD(87), + R8A7740_PIN_IO_PD(88), R8A7740_PIN_IO_PD(89), + R8A7740_PIN_IO_PD(90), R8A7740_PIN_IO_PU_PD(91), + R8A7740_PIN_IO_PU_PD(92), R8A7740_PIN_IO_PU_PD(93), + R8A7740_PIN_IO_PU_PD(94), R8A7740_PIN_IO_PU_PD(95), + R8A7740_PIN_IO_PU_PD(96), R8A7740_PIN_IO_PU_PD(97), + R8A7740_PIN_IO_PU_PD(98), R8A7740_PIN_IO_PU_PD(99), + R8A7740_PIN_IO_PU_PD(100), R8A7740_PIN_IO(101), + R8A7740_PIN_IO_PU(102), R8A7740_PIN_IO_PU_PD(103), + R8A7740_PIN_IO_PU(104), R8A7740_PIN_IO_PU(105), + R8A7740_PIN_IO_PU_PD(106), R8A7740_PIN_IO(107), + R8A7740_PIN_IO(108), R8A7740_PIN_IO(109), + R8A7740_PIN_IO(110), R8A7740_PIN_IO(111), + R8A7740_PIN_IO(112), R8A7740_PIN_IO(113), + R8A7740_PIN_IO_PU_PD(114), R8A7740_PIN_IO(115), + R8A7740_PIN_IO_PD(116), R8A7740_PIN_IO_PD(117), + R8A7740_PIN_IO_PD(118), R8A7740_PIN_IO_PD(119), + R8A7740_PIN_IO_PD(120), R8A7740_PIN_IO_PD(121), + R8A7740_PIN_IO_PD(122), R8A7740_PIN_IO_PD(123), + R8A7740_PIN_IO_PD(124), R8A7740_PIN_IO(125), + R8A7740_PIN_IO(126), R8A7740_PIN_IO(127), + R8A7740_PIN_IO(128), R8A7740_PIN_IO(129), + R8A7740_PIN_IO(130), R8A7740_PIN_IO(131), + R8A7740_PIN_IO(132), R8A7740_PIN_IO(133), + R8A7740_PIN_IO(134), R8A7740_PIN_IO(135), + R8A7740_PIN_IO(136), R8A7740_PIN_IO(137), + R8A7740_PIN_IO(138), R8A7740_PIN_IO(139), + R8A7740_PIN_IO(140), R8A7740_PIN_IO(141), + R8A7740_PIN_IO_PU(142), R8A7740_PIN_IO_PU(143), + R8A7740_PIN_IO_PU(144), R8A7740_PIN_IO_PU(145), + R8A7740_PIN_IO_PU(146), R8A7740_PIN_IO_PU(147), + R8A7740_PIN_IO_PU(148), R8A7740_PIN_IO_PU(149), + R8A7740_PIN_IO_PU(150), R8A7740_PIN_IO_PU(151), + R8A7740_PIN_IO_PU(152), R8A7740_PIN_IO_PU(153), + R8A7740_PIN_IO_PU(154), R8A7740_PIN_IO_PU(155), + R8A7740_PIN_IO_PU(156), R8A7740_PIN_IO_PU(157), + R8A7740_PIN_IO_PD(158), R8A7740_PIN_IO_PD(159), + R8A7740_PIN_IO_PU_PD(160), R8A7740_PIN_IO_PD(161), + R8A7740_PIN_IO_PD(162), R8A7740_PIN_IO_PD(163), + R8A7740_PIN_IO_PD(164), R8A7740_PIN_IO_PD(165), + R8A7740_PIN_IO_PU(166), R8A7740_PIN_IO_PU(167), + R8A7740_PIN_IO_PU(168), R8A7740_PIN_IO_PU(169), + R8A7740_PIN_IO_PU(170), R8A7740_PIN_IO_PU(171), + R8A7740_PIN_IO_PD(172), R8A7740_PIN_IO_PD(173), + R8A7740_PIN_IO_PD(174), R8A7740_PIN_IO_PD(175), + R8A7740_PIN_IO_PU(176), R8A7740_PIN_IO_PU_PD(177), + R8A7740_PIN_IO_PU(178), R8A7740_PIN_IO_PD(179), + R8A7740_PIN_IO_PD(180), R8A7740_PIN_IO_PU(181), + R8A7740_PIN_IO_PU(182), R8A7740_PIN_IO(183), + R8A7740_PIN_IO_PD(184), R8A7740_PIN_IO_PD(185), + R8A7740_PIN_IO_PD(186), R8A7740_PIN_IO_PD(187), + R8A7740_PIN_IO_PD(188), R8A7740_PIN_IO_PD(189), + R8A7740_PIN_IO_PD(190), R8A7740_PIN_IO_PD(191), + R8A7740_PIN_IO_PD(192), R8A7740_PIN_IO_PU_PD(193), + R8A7740_PIN_IO_PU_PD(194), R8A7740_PIN_IO_PD(195), + R8A7740_PIN_IO_PU_PD(196), R8A7740_PIN_IO_PD(197), + R8A7740_PIN_IO_PU_PD(198), R8A7740_PIN_IO_PU_PD(199), + R8A7740_PIN_IO_PU_PD(200), R8A7740_PIN_IO_PU(201), + R8A7740_PIN_IO_PU_PD(202), R8A7740_PIN_IO(203), + R8A7740_PIN_IO_PU_PD(204), R8A7740_PIN_IO_PU_PD(205), + R8A7740_PIN_IO_PU_PD(206), R8A7740_PIN_IO_PU_PD(207), + R8A7740_PIN_IO_PU_PD(208), R8A7740_PIN_IO_PD(209), + R8A7740_PIN_IO_PD(210), R8A7740_PIN_IO_PD(211), +}; + +/* - BSC -------------------------------------------------------------------- */ +static const unsigned int bsc_data8_pins[] = { + /* D[0:7] */ + 157, 156, 155, 154, 153, 152, 151, 150, +}; +static const unsigned int bsc_data8_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, +}; +static const unsigned int bsc_data16_pins[] = { + /* D[0:15] */ + 157, 156, 155, 154, 153, 152, 151, 150, + 149, 148, 147, 146, 145, 144, 143, 142, +}; +static const unsigned int bsc_data16_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, + D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, + D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, +}; +static const unsigned int bsc_data32_pins[] = { + /* D[0:31] */ + 157, 156, 155, 154, 153, 152, 151, 150, + 149, 148, 147, 146, 145, 144, 143, 142, + 171, 170, 169, 168, 167, 166, 173, 172, + 165, 164, 163, 162, 161, 160, 159, 158, +}; +static const unsigned int bsc_data32_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, + D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, + D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, + D16_MARK, D17_MARK, D18_MARK, D19_MARK, + D20_MARK, D21_MARK, D22_MARK, D23_MARK, + D24_MARK, D25_MARK, D26_MARK, D27_MARK, + D28_MARK, D29_MARK, D30_MARK, D31_MARK, +}; +static const unsigned int bsc_cs0_pins[] = { + /* CS */ + 109, +}; +static const unsigned int bsc_cs0_mux[] = { + CS0_MARK, +}; +static const unsigned int bsc_cs2_pins[] = { + /* CS */ + 110, +}; +static const unsigned int bsc_cs2_mux[] = { + CS2_MARK, +}; +static const unsigned int bsc_cs4_pins[] = { + /* CS */ + 111, +}; +static const unsigned int bsc_cs4_mux[] = { + CS4_MARK, +}; +static const unsigned int bsc_cs5a_0_pins[] = { + /* CS */ + 105, +}; +static const unsigned int bsc_cs5a_0_mux[] = { + CS5A_PORT105_MARK, +}; +static const unsigned int bsc_cs5a_1_pins[] = { + /* CS */ + 19, +}; +static const unsigned int bsc_cs5a_1_mux[] = { + CS5A_PORT19_MARK, +}; +static const unsigned int bsc_cs5b_pins[] = { + /* CS */ + 103, +}; +static const unsigned int bsc_cs5b_mux[] = { + CS5B_MARK, +}; +static const unsigned int bsc_cs6a_pins[] = { + /* CS */ + 104, +}; +static const unsigned int bsc_cs6a_mux[] = { + CS6A_MARK, +}; +static const unsigned int bsc_rd_we8_pins[] = { + /* RD, WE[0] */ + 115, 113, +}; +static const unsigned int bsc_rd_we8_mux[] = { + RD_FSC_MARK, WE0_FWE_MARK, +}; +static const unsigned int bsc_rd_we16_pins[] = { + /* RD, WE[0:1] */ + 115, 113, 112, +}; +static const unsigned int bsc_rd_we16_mux[] = { + RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, +}; +static const unsigned int bsc_rd_we32_pins[] = { + /* RD, WE[0:3] */ + 115, 113, 112, 108, 107, +}; +static const unsigned int bsc_rd_we32_mux[] = { + RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK, +}; +static const unsigned int bsc_bs_pins[] = { + /* BS */ + 175, +}; +static const unsigned int bsc_bs_mux[] = { + BS_MARK, +}; +static const unsigned int bsc_rdwr_pins[] = { + /* RDWR */ + 114, +}; +static const unsigned int bsc_rdwr_mux[] = { + RDWR_MARK, +}; +/* - CEU0 ------------------------------------------------------------------- */ +static const unsigned int ceu0_data_0_7_pins[] = { + /* D[0:7] */ + 34, 33, 32, 31, 30, 29, 28, 27, +}; +static const unsigned int ceu0_data_0_7_mux[] = { + VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK, + VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK, +}; +static const unsigned int ceu0_data_8_15_0_pins[] = { + /* D[8:15] */ + 182, 181, 180, 179, 178, 26, 25, 24, +}; +static const unsigned int ceu0_data_8_15_0_mux[] = { + VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK, + VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK, + VIO0_D15_PORT24_MARK, +}; +static const unsigned int ceu0_data_8_15_1_pins[] = { + /* D[8:15] */ + 182, 181, 180, 179, 178, 22, 95, 96, +}; +static const unsigned int ceu0_data_8_15_1_mux[] = { + VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK, + VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK, + VIO0_D15_PORT96_MARK, +}; +static const unsigned int ceu0_clk_0_pins[] = { + /* CKO */ + 36, +}; +static const unsigned int ceu0_clk_0_mux[] = { + VIO_CKO_MARK, +}; +static const unsigned int ceu0_clk_1_pins[] = { + /* CKO */ + 14, +}; +static const unsigned int ceu0_clk_1_mux[] = { + VIO_CKO1_MARK, +}; +static const unsigned int ceu0_clk_2_pins[] = { + /* CKO */ + 15, +}; +static const unsigned int ceu0_clk_2_mux[] = { + VIO_CKO2_MARK, +}; +static const unsigned int ceu0_sync_pins[] = { + /* CLK, VD, HD */ + 35, 39, 37, +}; +static const unsigned int ceu0_sync_mux[] = { + VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK, +}; +static const unsigned int ceu0_field_pins[] = { + /* FIELD */ + 38, +}; +static const unsigned int ceu0_field_mux[] = { + VIO0_FIELD_MARK, +}; +/* - CEU1 ------------------------------------------------------------------- */ +static const unsigned int ceu1_data_pins[] = { + /* D[0:7] */ + 182, 181, 180, 179, 178, 26, 25, 24, +}; +static const unsigned int ceu1_data_mux[] = { + VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK, + VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK, +}; +static const unsigned int ceu1_clk_pins[] = { + /* CKO */ + 23, +}; +static const unsigned int ceu1_clk_mux[] = { + VIO_CKO_1_MARK, +}; +static const unsigned int ceu1_sync_pins[] = { + /* CLK, VD, HD */ + 197, 198, 160, +}; +static const unsigned int ceu1_sync_mux[] = { + VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK, +}; +static const unsigned int ceu1_field_pins[] = { + /* FIELD */ + 21, +}; +static const unsigned int ceu1_field_mux[] = { + VIO1_FIELD_MARK, +}; +/* - FSIA ------------------------------------------------------------------- */ +static const unsigned int fsia_mclk_in_pins[] = { + /* CK */ + 11, +}; +static const unsigned int fsia_mclk_in_mux[] = { + FSIACK_MARK, +}; +static const unsigned int fsia_mclk_out_pins[] = { + /* OMC */ + 10, +}; +static const unsigned int fsia_mclk_out_mux[] = { + FSIAOMC_MARK, +}; +static const unsigned int fsia_sclk_in_pins[] = { + /* ILR, IBT */ + 12, 13, +}; +static const unsigned int fsia_sclk_in_mux[] = { + FSIAILR_MARK, FSIAIBT_MARK, +}; +static const unsigned int fsia_sclk_out_pins[] = { + /* OLR, OBT */ + 7, 8, +}; +static const unsigned int fsia_sclk_out_mux[] = { + FSIAOLR_MARK, FSIAOBT_MARK, +}; +static const unsigned int fsia_data_in_0_pins[] = { + /* ISLD */ + 0, }; +static const unsigned int fsia_data_in_0_mux[] = { + FSIAISLD_PORT0_MARK, +}; +static const unsigned int fsia_data_in_1_pins[] = { + /* ISLD */ + 5, +}; +static const unsigned int fsia_data_in_1_mux[] = { + FSIAISLD_PORT5_MARK, +}; +static const unsigned int fsia_data_out_0_pins[] = { + /* OSLD */ + 9, +}; +static const unsigned int fsia_data_out_0_mux[] = { + FSIAOSLD_MARK, +}; +static const unsigned int fsia_data_out_1_pins[] = { + /* OSLD */ + 0, +}; +static const unsigned int fsia_data_out_1_mux[] = { + FSIAOSLD1_MARK, +}; +static const unsigned int fsia_data_out_2_pins[] = { + /* OSLD */ + 1, +}; +static const unsigned int fsia_data_out_2_mux[] = { + FSIAOSLD2_MARK, +}; +static const unsigned int fsia_spdif_0_pins[] = { + /* SPDIF */ + 9, +}; +static const unsigned int fsia_spdif_0_mux[] = { + FSIASPDIF_PORT9_MARK, +}; +static const unsigned int fsia_spdif_1_pins[] = { + /* SPDIF */ + 18, +}; +static const unsigned int fsia_spdif_1_mux[] = { + FSIASPDIF_PORT18_MARK, +}; +/* - FSIB ------------------------------------------------------------------- */ +static const unsigned int fsib_mclk_in_pins[] = { + /* CK */ + 11, +}; +static const unsigned int fsib_mclk_in_mux[] = { + FSIBCK_MARK, +}; +/* - GETHER ----------------------------------------------------------------- */ +static const unsigned int gether_rmii_pins[] = { + /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */ + 195, 196, 194, 193, 200, 201, 199, 159, 202, 208, +}; +static const unsigned int gether_rmii_mux[] = { + RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK, + RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK, + RMII_MDC_MARK, RMII_MDIO_MARK, +}; +static const unsigned int gether_mii_pins[] = { + /* RXD[0:3], RX_CLK, RX_DV, RX_ER + * TXD[0:3], TX_CLK, TX_EN, TX_ER + * CRS, COL, MDC, MDIO, + */ + 185, 186, 187, 188, 174, 161, 204, + 171, 170, 169, 168, 184, 183, 203, + 205, 163, 206, 207, +}; +static const unsigned int gether_mii_mux[] = { + ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK, + ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK, + ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK, + ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK, + ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK, +}; +static const unsigned int gether_gmii_pins[] = { + /* RXD[0:7], RX_CLK, RX_DV, RX_ER + * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER + * CRS, COL, MDC, MDIO, REF125CK_MARK, + */ + 185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204, + 171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203, + 205, 163, 206, 207, +}; +static const unsigned int gether_gmii_mux[] = { + ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK, + ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK, + ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK, + ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK, + ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK, + ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK, + ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK, + RMII_REF125CK_MARK, +}; +static const unsigned int gether_int_pins[] = { + /* PHY_INT */ + 164, +}; +static const unsigned int gether_int_mux[] = { + ET_PHY_INT_MARK, +}; +static const unsigned int gether_link_pins[] = { + /* LINK */ + 177, +}; +static const unsigned int gether_link_mux[] = { + ET_LINK_MARK, +}; +static const unsigned int gether_wol_pins[] = { + /* WOL */ + 175, +}; +static const unsigned int gether_wol_mux[] = { + ET_WOL_MARK, +}; +/* - HDMI ------------------------------------------------------------------- */ +static const unsigned int hdmi_pins[] = { + /* HPD, CEC */ + 210, 211, +}; +static const unsigned int hdmi_mux[] = { + HDMI_HPD_MARK, HDMI_CEC_MARK, +}; +/* - INTC ------------------------------------------------------------------- */ +IRQC_PINS_MUX(0, 0, 2); +IRQC_PINS_MUX(0, 1, 13); +IRQC_PIN_MUX(1, 20); +IRQC_PINS_MUX(2, 0, 11); +IRQC_PINS_MUX(2, 1, 12); +IRQC_PINS_MUX(3, 0, 10); +IRQC_PINS_MUX(3, 1, 14); +IRQC_PINS_MUX(4, 0, 15); +IRQC_PINS_MUX(4, 1, 172); +IRQC_PINS_MUX(5, 0, 0); +IRQC_PINS_MUX(5, 1, 1); +IRQC_PINS_MUX(6, 0, 121); +IRQC_PINS_MUX(6, 1, 173); +IRQC_PINS_MUX(7, 0, 120); +IRQC_PINS_MUX(7, 1, 209); +IRQC_PIN_MUX(8, 119); +IRQC_PINS_MUX(9, 0, 118); +IRQC_PINS_MUX(9, 1, 210); +IRQC_PIN_MUX(10, 19); +IRQC_PIN_MUX(11, 104); +IRQC_PINS_MUX(12, 0, 42); +IRQC_PINS_MUX(12, 1, 97); +IRQC_PINS_MUX(13, 0, 64); +IRQC_PINS_MUX(13, 1, 98); +IRQC_PINS_MUX(14, 0, 63); +IRQC_PINS_MUX(14, 1, 99); +IRQC_PINS_MUX(15, 0, 62); +IRQC_PINS_MUX(15, 1, 100); +IRQC_PINS_MUX(16, 0, 68); +IRQC_PINS_MUX(16, 1, 211); +IRQC_PIN_MUX(17, 69); +IRQC_PIN_MUX(18, 70); +IRQC_PIN_MUX(19, 71); +IRQC_PIN_MUX(20, 67); +IRQC_PIN_MUX(21, 202); +IRQC_PIN_MUX(22, 95); +IRQC_PIN_MUX(23, 96); +IRQC_PIN_MUX(24, 180); +IRQC_PIN_MUX(25, 38); +IRQC_PINS_MUX(26, 0, 58); +IRQC_PINS_MUX(26, 1, 81); +IRQC_PINS_MUX(27, 0, 57); +IRQC_PINS_MUX(27, 1, 168); +IRQC_PINS_MUX(28, 0, 56); +IRQC_PINS_MUX(28, 1, 169); +IRQC_PINS_MUX(29, 0, 50); +IRQC_PINS_MUX(29, 1, 170); +IRQC_PINS_MUX(30, 0, 49); +IRQC_PINS_MUX(30, 1, 171); +IRQC_PINS_MUX(31, 0, 41); +IRQC_PINS_MUX(31, 1, 167); /* - LCD0 ------------------------------------------------------------------- */ static const unsigned int lcd0_data8_pins[] = { @@ -1930,6 +2369,260 @@ static const unsigned int mmc0_ctrl_1_pins[] = { static const unsigned int mmc0_ctrl_1_mux[] = { MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK, }; +/* - SCIFA0 ----------------------------------------------------------------- */ +static const unsigned int scifa0_data_pins[] = { + /* RXD, TXD */ + 197, 198, +}; +static const unsigned int scifa0_data_mux[] = { + SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, +}; +static const unsigned int scifa0_clk_pins[] = { + /* SCK */ + 188, +}; +static const unsigned int scifa0_clk_mux[] = { + SCIFA0_SCK_MARK, +}; +static const unsigned int scifa0_ctrl_pins[] = { + /* RTS, CTS */ + 194, 193, +}; +static const unsigned int scifa0_ctrl_mux[] = { + SCIFA0_RTS_MARK, SCIFA0_CTS_MARK, +}; +/* - SCIFA1 ----------------------------------------------------------------- */ +static const unsigned int scifa1_data_pins[] = { + /* RXD, TXD */ + 195, 196, +}; +static const unsigned int scifa1_data_mux[] = { + SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, +}; +static const unsigned int scifa1_clk_pins[] = { + /* SCK */ + 185, +}; +static const unsigned int scifa1_clk_mux[] = { + SCIFA1_SCK_MARK, +}; +static const unsigned int scifa1_ctrl_pins[] = { + /* RTS, CTS */ + 23, 21, +}; +static const unsigned int scifa1_ctrl_mux[] = { + SCIFA1_RTS_MARK, SCIFA1_CTS_MARK, +}; +/* - SCIFA2 ----------------------------------------------------------------- */ +static const unsigned int scifa2_data_pins[] = { + /* RXD, TXD */ + 200, 201, +}; +static const unsigned int scifa2_data_mux[] = { + SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, +}; +static const unsigned int scifa2_clk_0_pins[] = { + /* SCK */ + 22, +}; +static const unsigned int scifa2_clk_0_mux[] = { + SCIFA2_SCK_PORT22_MARK, +}; +static const unsigned int scifa2_clk_1_pins[] = { + /* SCK */ + 199, +}; +static const unsigned int scifa2_clk_1_mux[] = { + SCIFA2_SCK_PORT199_MARK, +}; +static const unsigned int scifa2_ctrl_pins[] = { + /* RTS, CTS */ + 96, 95, +}; +static const unsigned int scifa2_ctrl_mux[] = { + SCIFA2_RTS_MARK, SCIFA2_CTS_MARK, +}; +/* - SCIFA3 ----------------------------------------------------------------- */ +static const unsigned int scifa3_data_0_pins[] = { + /* RXD, TXD */ + 174, 175, +}; +static const unsigned int scifa3_data_0_mux[] = { + SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK, +}; +static const unsigned int scifa3_clk_0_pins[] = { + /* SCK */ + 116, +}; +static const unsigned int scifa3_clk_0_mux[] = { + SCIFA3_SCK_PORT116_MARK, +}; +static const unsigned int scifa3_ctrl_0_pins[] = { + /* RTS, CTS */ + 105, 117, +}; +static const unsigned int scifa3_ctrl_0_mux[] = { + SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK, +}; +static const unsigned int scifa3_data_1_pins[] = { + /* RXD, TXD */ + 159, 160, +}; +static const unsigned int scifa3_data_1_mux[] = { + SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK, +}; +static const unsigned int scifa3_clk_1_pins[] = { + /* SCK */ + 158, +}; +static const unsigned int scifa3_clk_1_mux[] = { + SCIFA3_SCK_PORT158_MARK, +}; +static const unsigned int scifa3_ctrl_1_pins[] = { + /* RTS, CTS */ + 161, 162, +}; +static const unsigned int scifa3_ctrl_1_mux[] = { + SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK, +}; +/* - SCIFA4 ----------------------------------------------------------------- */ +static const unsigned int scifa4_data_0_pins[] = { + /* RXD, TXD */ + 12, 13, +}; +static const unsigned int scifa4_data_0_mux[] = { + SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK, +}; +static const unsigned int scifa4_data_1_pins[] = { + /* RXD, TXD */ + 204, 203, +}; +static const unsigned int scifa4_data_1_mux[] = { + SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK, +}; +static const unsigned int scifa4_data_2_pins[] = { + /* RXD, TXD */ + 94, 93, +}; +static const unsigned int scifa4_data_2_mux[] = { + SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK, +}; +static const unsigned int scifa4_clk_0_pins[] = { + /* SCK */ + 21, +}; +static const unsigned int scifa4_clk_0_mux[] = { + SCIFA4_SCK_PORT21_MARK, +}; +static const unsigned int scifa4_clk_1_pins[] = { + /* SCK */ + 205, +}; +static const unsigned int scifa4_clk_1_mux[] = { + SCIFA4_SCK_PORT205_MARK, +}; +/* - SCIFA5 ----------------------------------------------------------------- */ +static const unsigned int scifa5_data_0_pins[] = { + /* RXD, TXD */ + 10, 20, +}; +static const unsigned int scifa5_data_0_mux[] = { + SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK, +}; +static const unsigned int scifa5_data_1_pins[] = { + /* RXD, TXD */ + 207, 208, +}; +static const unsigned int scifa5_data_1_mux[] = { + SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK, +}; +static const unsigned int scifa5_data_2_pins[] = { + /* RXD, TXD */ + 92, 91, +}; +static const unsigned int scifa5_data_2_mux[] = { + SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK, +}; +static const unsigned int scifa5_clk_0_pins[] = { + /* SCK */ + 23, +}; +static const unsigned int scifa5_clk_0_mux[] = { + SCIFA5_SCK_PORT23_MARK, +}; +static const unsigned int scifa5_clk_1_pins[] = { + /* SCK */ + 206, +}; +static const unsigned int scifa5_clk_1_mux[] = { + SCIFA5_SCK_PORT206_MARK, +}; +/* - SCIFA6 ----------------------------------------------------------------- */ +static const unsigned int scifa6_data_pins[] = { + /* RXD, TXD */ + 25, 26, +}; +static const unsigned int scifa6_data_mux[] = { + SCIFA6_RXD_MARK, SCIFA6_TXD_MARK, +}; +static const unsigned int scifa6_clk_pins[] = { + /* SCK */ + 24, +}; +static const unsigned int scifa6_clk_mux[] = { + SCIFA6_SCK_MARK, +}; +/* - SCIFA7 ----------------------------------------------------------------- */ +static const unsigned int scifa7_data_pins[] = { + /* RXD, TXD */ + 0, 1, +}; +static const unsigned int scifa7_data_mux[] = { + SCIFA7_RXD_MARK, SCIFA7_TXD_MARK, +}; +/* - SCIFB ------------------------------------------------------------------ */ +static const unsigned int scifb_data_0_pins[] = { + /* RXD, TXD */ + 191, 192, +}; +static const unsigned int scifb_data_0_mux[] = { + SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK, +}; +static const unsigned int scifb_clk_0_pins[] = { + /* SCK */ + 190, +}; +static const unsigned int scifb_clk_0_mux[] = { + SCIFB_SCK_PORT190_MARK, +}; +static const unsigned int scifb_ctrl_0_pins[] = { + /* RTS, CTS */ + 186, 187, +}; +static const unsigned int scifb_ctrl_0_mux[] = { + SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK, +}; +static const unsigned int scifb_data_1_pins[] = { + /* RXD, TXD */ + 3, 4, +}; +static const unsigned int scifb_data_1_mux[] = { + SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK, +}; +static const unsigned int scifb_clk_1_pins[] = { + /* SCK */ + 2, +}; +static const unsigned int scifb_clk_1_mux[] = { + SCIFB_SCK_PORT2_MARK, +}; +static const unsigned int scifb_ctrl_1_pins[] = { + /* RTS, CTS */ + 172, 173, +}; +static const unsigned int scifb_ctrl_1_mux[] = { + SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK, +}; /* - SDHI0 ------------------------------------------------------------------ */ static const unsigned int sdhi0_data1_pins[] = { /* D0 */ @@ -2052,8 +2745,141 @@ static const unsigned int sdhi2_wp_1_pins[] = { static const unsigned int sdhi2_wp_1_mux[] = { SDHI2_WP_PORT25_MARK, }; +/* - TPU0 ------------------------------------------------------------------- */ +static const unsigned int tpu0_to0_pins[] = { + /* TO */ + 23, +}; +static const unsigned int tpu0_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu0_to1_pins[] = { + /* TO */ + 21, +}; +static const unsigned int tpu0_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu0_to2_0_pins[] = { + /* TO */ + 66, +}; +static const unsigned int tpu0_to2_0_mux[] = { + TPU0TO2_PORT66_MARK, +}; +static const unsigned int tpu0_to2_1_pins[] = { + /* TO */ + 202, +}; +static const unsigned int tpu0_to2_1_mux[] = { + TPU0TO2_PORT202_MARK, +}; +static const unsigned int tpu0_to3_pins[] = { + /* TO */ + 180, +}; +static const unsigned int tpu0_to3_mux[] = { + TPU0TO3_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(bsc_data8), + SH_PFC_PIN_GROUP(bsc_data16), + SH_PFC_PIN_GROUP(bsc_data32), + SH_PFC_PIN_GROUP(bsc_cs0), + SH_PFC_PIN_GROUP(bsc_cs2), + SH_PFC_PIN_GROUP(bsc_cs4), + SH_PFC_PIN_GROUP(bsc_cs5a_0), + SH_PFC_PIN_GROUP(bsc_cs5a_1), + SH_PFC_PIN_GROUP(bsc_cs5b), + SH_PFC_PIN_GROUP(bsc_cs6a), + SH_PFC_PIN_GROUP(bsc_rd_we8), + SH_PFC_PIN_GROUP(bsc_rd_we16), + SH_PFC_PIN_GROUP(bsc_rd_we32), + SH_PFC_PIN_GROUP(bsc_bs), + SH_PFC_PIN_GROUP(bsc_rdwr), + SH_PFC_PIN_GROUP(ceu0_data_0_7), + SH_PFC_PIN_GROUP(ceu0_data_8_15_0), + SH_PFC_PIN_GROUP(ceu0_data_8_15_1), + SH_PFC_PIN_GROUP(ceu0_clk_0), + SH_PFC_PIN_GROUP(ceu0_clk_1), + SH_PFC_PIN_GROUP(ceu0_clk_2), + SH_PFC_PIN_GROUP(ceu0_sync), + SH_PFC_PIN_GROUP(ceu0_field), + SH_PFC_PIN_GROUP(ceu1_data), + SH_PFC_PIN_GROUP(ceu1_clk), + SH_PFC_PIN_GROUP(ceu1_sync), + SH_PFC_PIN_GROUP(ceu1_field), + SH_PFC_PIN_GROUP(fsia_mclk_in), + SH_PFC_PIN_GROUP(fsia_mclk_out), + SH_PFC_PIN_GROUP(fsia_sclk_in), + SH_PFC_PIN_GROUP(fsia_sclk_out), + SH_PFC_PIN_GROUP(fsia_data_in_0), + SH_PFC_PIN_GROUP(fsia_data_in_1), + SH_PFC_PIN_GROUP(fsia_data_out_0), + SH_PFC_PIN_GROUP(fsia_data_out_1), + SH_PFC_PIN_GROUP(fsia_data_out_2), + SH_PFC_PIN_GROUP(fsia_spdif_0), + SH_PFC_PIN_GROUP(fsia_spdif_1), + SH_PFC_PIN_GROUP(fsib_mclk_in), + SH_PFC_PIN_GROUP(gether_rmii), + SH_PFC_PIN_GROUP(gether_mii), + SH_PFC_PIN_GROUP(gether_gmii), + SH_PFC_PIN_GROUP(gether_int), + SH_PFC_PIN_GROUP(gether_link), + SH_PFC_PIN_GROUP(gether_wol), + SH_PFC_PIN_GROUP(hdmi), + SH_PFC_PIN_GROUP(intc_irq0_0), + SH_PFC_PIN_GROUP(intc_irq0_1), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2_0), + SH_PFC_PIN_GROUP(intc_irq2_1), + SH_PFC_PIN_GROUP(intc_irq3_0), + SH_PFC_PIN_GROUP(intc_irq3_1), + SH_PFC_PIN_GROUP(intc_irq4_0), + SH_PFC_PIN_GROUP(intc_irq4_1), + SH_PFC_PIN_GROUP(intc_irq5_0), + SH_PFC_PIN_GROUP(intc_irq5_1), + SH_PFC_PIN_GROUP(intc_irq6_0), + SH_PFC_PIN_GROUP(intc_irq6_1), + SH_PFC_PIN_GROUP(intc_irq7_0), + SH_PFC_PIN_GROUP(intc_irq7_1), + SH_PFC_PIN_GROUP(intc_irq8), + SH_PFC_PIN_GROUP(intc_irq9_0), + SH_PFC_PIN_GROUP(intc_irq9_1), + SH_PFC_PIN_GROUP(intc_irq10), + SH_PFC_PIN_GROUP(intc_irq11), + SH_PFC_PIN_GROUP(intc_irq12_0), + SH_PFC_PIN_GROUP(intc_irq12_1), + SH_PFC_PIN_GROUP(intc_irq13_0), + SH_PFC_PIN_GROUP(intc_irq13_1), + SH_PFC_PIN_GROUP(intc_irq14_0), + SH_PFC_PIN_GROUP(intc_irq14_1), + SH_PFC_PIN_GROUP(intc_irq15_0), + SH_PFC_PIN_GROUP(intc_irq15_1), + SH_PFC_PIN_GROUP(intc_irq16_0), + SH_PFC_PIN_GROUP(intc_irq16_1), + SH_PFC_PIN_GROUP(intc_irq17), + SH_PFC_PIN_GROUP(intc_irq18), + SH_PFC_PIN_GROUP(intc_irq19), + SH_PFC_PIN_GROUP(intc_irq20), + SH_PFC_PIN_GROUP(intc_irq21), + SH_PFC_PIN_GROUP(intc_irq22), + SH_PFC_PIN_GROUP(intc_irq23), + SH_PFC_PIN_GROUP(intc_irq24), + SH_PFC_PIN_GROUP(intc_irq25), + SH_PFC_PIN_GROUP(intc_irq26_0), + SH_PFC_PIN_GROUP(intc_irq26_1), + SH_PFC_PIN_GROUP(intc_irq27_0), + SH_PFC_PIN_GROUP(intc_irq27_1), + SH_PFC_PIN_GROUP(intc_irq28_0), + SH_PFC_PIN_GROUP(intc_irq28_1), + SH_PFC_PIN_GROUP(intc_irq29_0), + SH_PFC_PIN_GROUP(intc_irq29_1), + SH_PFC_PIN_GROUP(intc_irq30_0), + SH_PFC_PIN_GROUP(intc_irq30_1), + SH_PFC_PIN_GROUP(intc_irq31_0), + SH_PFC_PIN_GROUP(intc_irq31_1), SH_PFC_PIN_GROUP(lcd0_data8), SH_PFC_PIN_GROUP(lcd0_data9), SH_PFC_PIN_GROUP(lcd0_data12), @@ -2084,6 +2910,41 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc0_data4_1), SH_PFC_PIN_GROUP(mmc0_data8_1), SH_PFC_PIN_GROUP(mmc0_ctrl_1), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_clk), + SH_PFC_PIN_GROUP(scifa0_ctrl), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_ctrl), + SH_PFC_PIN_GROUP(scifa2_data), + SH_PFC_PIN_GROUP(scifa2_clk_0), + SH_PFC_PIN_GROUP(scifa2_clk_1), + SH_PFC_PIN_GROUP(scifa2_ctrl), + SH_PFC_PIN_GROUP(scifa3_data_0), + SH_PFC_PIN_GROUP(scifa3_clk_0), + SH_PFC_PIN_GROUP(scifa3_ctrl_0), + SH_PFC_PIN_GROUP(scifa3_data_1), + SH_PFC_PIN_GROUP(scifa3_clk_1), + SH_PFC_PIN_GROUP(scifa3_ctrl_1), + SH_PFC_PIN_GROUP(scifa4_data_0), + SH_PFC_PIN_GROUP(scifa4_data_1), + SH_PFC_PIN_GROUP(scifa4_data_2), + SH_PFC_PIN_GROUP(scifa4_clk_0), + SH_PFC_PIN_GROUP(scifa4_clk_1), + SH_PFC_PIN_GROUP(scifa5_data_0), + SH_PFC_PIN_GROUP(scifa5_data_1), + SH_PFC_PIN_GROUP(scifa5_data_2), + SH_PFC_PIN_GROUP(scifa5_clk_0), + SH_PFC_PIN_GROUP(scifa5_clk_1), + SH_PFC_PIN_GROUP(scifa6_data), + SH_PFC_PIN_GROUP(scifa6_clk), + SH_PFC_PIN_GROUP(scifa7_data), + SH_PFC_PIN_GROUP(scifb_data_0), + SH_PFC_PIN_GROUP(scifb_clk_0), + SH_PFC_PIN_GROUP(scifb_ctrl_0), + SH_PFC_PIN_GROUP(scifb_data_1), + SH_PFC_PIN_GROUP(scifb_clk_1), + SH_PFC_PIN_GROUP(scifb_ctrl_1), SH_PFC_PIN_GROUP(sdhi0_data1), SH_PFC_PIN_GROUP(sdhi0_data4), SH_PFC_PIN_GROUP(sdhi0_ctrl), @@ -2101,6 +2962,132 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi2_wp_0), SH_PFC_PIN_GROUP(sdhi2_cd_1), SH_PFC_PIN_GROUP(sdhi2_wp_1), + SH_PFC_PIN_GROUP(tpu0_to0), + SH_PFC_PIN_GROUP(tpu0_to1), + SH_PFC_PIN_GROUP(tpu0_to2_0), + SH_PFC_PIN_GROUP(tpu0_to2_1), + SH_PFC_PIN_GROUP(tpu0_to3), +}; + +static const char * const bsc_groups[] = { + "bsc_data8", + "bsc_data16", + "bsc_data32", + "bsc_cs0", + "bsc_cs2", + "bsc_cs4", + "bsc_cs5a_0", + "bsc_cs5a_1", + "bsc_cs5b", + "bsc_cs6a", + "bsc_rd_we8", + "bsc_rd_we16", + "bsc_rd_we32", + "bsc_bs", + "bsc_rdwr", +}; + +static const char * const ceu0_groups[] = { + "ceu0_data_0_7", + "ceu0_data_8_15_0", + "ceu0_data_8_15_1", + "ceu0_clk_0", + "ceu0_clk_1", + "ceu0_clk_2", + "ceu0_sync", + "ceu0_field", +}; + +static const char * const ceu1_groups[] = { + "ceu1_data", + "ceu1_clk", + "ceu1_sync", + "ceu1_field", +}; + +static const char * const fsia_groups[] = { + "fsia_mclk_in", + "fsia_mclk_out", + "fsia_sclk_in", + "fsia_sclk_out", + "fsia_data_in_0", + "fsia_data_in_1", + "fsia_data_out_0", + "fsia_data_out_1", + "fsia_data_out_2", + "fsia_spdif_0", + "fsia_spdif_1", +}; + +static const char * const fsib_groups[] = { + "fsib_mclk_in", +}; + +static const char * const gether_groups[] = { + "gether_rmii", + "gether_mii", + "gether_gmii", + "gether_int", + "gether_link", + "gether_wol", +}; + +static const char * const hdmi_groups[] = { + "hdmi", +}; + +static const char * const intc_groups[] = { + "intc_irq0_0", + "intc_irq0_1", + "intc_irq1", + "intc_irq2_0", + "intc_irq2_1", + "intc_irq3_0", + "intc_irq3_1", + "intc_irq4_0", + "intc_irq4_1", + "intc_irq5_0", + "intc_irq5_1", + "intc_irq6_0", + "intc_irq6_1", + "intc_irq7_0", + "intc_irq7_1", + "intc_irq8", + "intc_irq9_0", + "intc_irq9_1", + "intc_irq10", + "intc_irq11", + "intc_irq12_0", + "intc_irq12_1", + "intc_irq13_0", + "intc_irq13_1", + "intc_irq14_0", + "intc_irq14_1", + "intc_irq15_0", + "intc_irq15_1", + "intc_irq16_0", + "intc_irq16_1", + "intc_irq17", + "intc_irq18", + "intc_irq19", + "intc_irq20", + "intc_irq21", + "intc_irq22", + "intc_irq23", + "intc_irq24", + "intc_irq25", + "intc_irq26_0", + "intc_irq26_1", + "intc_irq27_0", + "intc_irq27_1", + "intc_irq28_0", + "intc_irq28_1", + "intc_irq29_0", + "intc_irq29_1", + "intc_irq30_0", + "intc_irq30_1", + "intc_irq31_0", + "intc_irq31_1", }; static const char * const lcd0_groups[] = { @@ -2142,6 +3129,68 @@ static const char * const mmc0_groups[] = { "mmc0_ctrl_1", }; +static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_clk", + "scifa0_ctrl", +}; + +static const char * const scifa1_groups[] = { + "scifa1_data", + "scifa1_clk", + "scifa1_ctrl", +}; + +static const char * const scifa2_groups[] = { + "scifa2_data", + "scifa2_clk_0", + "scifa2_clk_1", + "scifa2_ctrl", +}; + +static const char * const scifa3_groups[] = { + "scifa3_data_0", + "scifa3_clk_0", + "scifa3_ctrl_0", + "scifa3_data_1", + "scifa3_clk_1", + "scifa3_ctrl_1", +}; + +static const char * const scifa4_groups[] = { + "scifa4_data_0", + "scifa4_data_1", + "scifa4_data_2", + "scifa4_clk_0", + "scifa4_clk_1", +}; + +static const char * const scifa5_groups[] = { + "scifa5_data_0", + "scifa5_data_1", + "scifa5_data_2", + "scifa5_clk_0", + "scifa5_clk_1", +}; + +static const char * const scifa6_groups[] = { + "scifa6_data", + "scifa6_clk", +}; + +static const char * const scifa7_groups[] = { + "scifa7_data", +}; + +static const char * const scifb_groups[] = { + "scifb_data_0", + "scifb_clk_0", + "scifb_ctrl_0", + "scifb_data_1", + "scifb_clk_1", + "scifb_ctrl_1", +}; + static const char * const sdhi0_groups[] = { "sdhi0_data1", "sdhi0_data4", @@ -2168,412 +3217,51 @@ static const char * const sdhi2_groups[] = { "sdhi2_wp_1", }; +static const char * const tpu0_groups[] = { + "tpu0_to0", + "tpu0_to1", + "tpu0_to2_0", + "tpu0_to2_1", + "tpu0_to3", +}; + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(bsc), + SH_PFC_FUNCTION(ceu0), + SH_PFC_FUNCTION(ceu1), + SH_PFC_FUNCTION(fsia), + SH_PFC_FUNCTION(fsib), + SH_PFC_FUNCTION(gether), + SH_PFC_FUNCTION(hdmi), + SH_PFC_FUNCTION(intc), SH_PFC_FUNCTION(lcd0), SH_PFC_FUNCTION(lcd1), SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifa3), + SH_PFC_FUNCTION(scifa4), + SH_PFC_FUNCTION(scifa5), + SH_PFC_FUNCTION(scifa6), + SH_PFC_FUNCTION(scifa7), + SH_PFC_FUNCTION(scifb), SH_PFC_FUNCTION(sdhi0), SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(tpu0), }; -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) - -static const struct pinmux_func pinmux_func_gpios[] = { - /* IRQ */ - GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13), - GPIO_FN(IRQ1), - GPIO_FN(IRQ2_PORT11), GPIO_FN(IRQ2_PORT12), - GPIO_FN(IRQ3_PORT10), GPIO_FN(IRQ3_PORT14), - GPIO_FN(IRQ4_PORT15), GPIO_FN(IRQ4_PORT172), - GPIO_FN(IRQ5_PORT0), GPIO_FN(IRQ5_PORT1), - GPIO_FN(IRQ6_PORT121), GPIO_FN(IRQ6_PORT173), - GPIO_FN(IRQ7_PORT120), GPIO_FN(IRQ7_PORT209), - GPIO_FN(IRQ8), - GPIO_FN(IRQ9_PORT118), GPIO_FN(IRQ9_PORT210), - GPIO_FN(IRQ10), - GPIO_FN(IRQ11), - GPIO_FN(IRQ12_PORT42), GPIO_FN(IRQ12_PORT97), - GPIO_FN(IRQ13_PORT64), GPIO_FN(IRQ13_PORT98), - GPIO_FN(IRQ14_PORT63), GPIO_FN(IRQ14_PORT99), - GPIO_FN(IRQ15_PORT62), GPIO_FN(IRQ15_PORT100), - GPIO_FN(IRQ16_PORT68), GPIO_FN(IRQ16_PORT211), - GPIO_FN(IRQ17), - GPIO_FN(IRQ18), - GPIO_FN(IRQ19), - GPIO_FN(IRQ20), - GPIO_FN(IRQ21), - GPIO_FN(IRQ22), - GPIO_FN(IRQ23), - GPIO_FN(IRQ24), - GPIO_FN(IRQ25), - GPIO_FN(IRQ26_PORT58), GPIO_FN(IRQ26_PORT81), - GPIO_FN(IRQ27_PORT57), GPIO_FN(IRQ27_PORT168), - GPIO_FN(IRQ28_PORT56), GPIO_FN(IRQ28_PORT169), - GPIO_FN(IRQ29_PORT50), GPIO_FN(IRQ29_PORT170), - GPIO_FN(IRQ30_PORT49), GPIO_FN(IRQ30_PORT171), - GPIO_FN(IRQ31_PORT41), GPIO_FN(IRQ31_PORT167), - - /* Function */ - - /* DBGT */ - GPIO_FN(DBGMDT2), GPIO_FN(DBGMDT1), GPIO_FN(DBGMDT0), - GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20), - GPIO_FN(DBGMD21), - - /* FSI-A */ - GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */ - GPIO_FN(FSIAISLD_PORT5), - GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */ - GPIO_FN(FSIASPDIF_PORT18), - GPIO_FN(FSIAOSLD1), GPIO_FN(FSIAOSLD2), GPIO_FN(FSIAOLR), - GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC), - GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT), - - /* FSI-B */ - GPIO_FN(FSIBCK), - - /* FMSI */ - GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */ - GPIO_FN(FMSISLD_PORT6), - GPIO_FN(FMSIILR), GPIO_FN(FMSIIBT), GPIO_FN(FMSIOLR), - GPIO_FN(FMSIOBT), GPIO_FN(FMSICK), GPIO_FN(FMSOILR), - GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT), - GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK), - - /* SCIFA0 */ - GPIO_FN(SCIFA0_SCK), GPIO_FN(SCIFA0_CTS), GPIO_FN(SCIFA0_RTS), - GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_TXD), - - /* SCIFA1 */ - GPIO_FN(SCIFA1_CTS), GPIO_FN(SCIFA1_SCK), - GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RTS), - - /* SCIFA2 */ - GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */ - GPIO_FN(SCIFA2_SCK_PORT199), - GPIO_FN(SCIFA2_RXD), GPIO_FN(SCIFA2_TXD), - GPIO_FN(SCIFA2_CTS), GPIO_FN(SCIFA2_RTS), - - /* SCIFA3 */ - GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */ - GPIO_FN(SCIFA3_SCK_PORT116), - GPIO_FN(SCIFA3_CTS_PORT117), - GPIO_FN(SCIFA3_RXD_PORT174), - GPIO_FN(SCIFA3_TXD_PORT175), - - GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */ - GPIO_FN(SCIFA3_SCK_PORT158), - GPIO_FN(SCIFA3_CTS_PORT162), - GPIO_FN(SCIFA3_RXD_PORT159), - GPIO_FN(SCIFA3_TXD_PORT160), - - /* SCIFA4 */ - GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */ - GPIO_FN(SCIFA4_TXD_PORT13), - - GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */ - GPIO_FN(SCIFA4_TXD_PORT203), - - GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */ - GPIO_FN(SCIFA4_TXD_PORT93), - - GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */ - GPIO_FN(SCIFA4_SCK_PORT205), - - /* SCIFA5 */ - GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */ - GPIO_FN(SCIFA5_RXD_PORT10), - - GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */ - GPIO_FN(SCIFA5_TXD_PORT208), - - GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */ - GPIO_FN(SCIFA5_RXD_PORT92), - - GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */ - GPIO_FN(SCIFA5_SCK_PORT206), - - /* SCIFA6 */ - GPIO_FN(SCIFA6_SCK), GPIO_FN(SCIFA6_RXD), GPIO_FN(SCIFA6_TXD), - - /* SCIFA7 */ - GPIO_FN(SCIFA7_TXD), GPIO_FN(SCIFA7_RXD), - - /* SCIFAB */ - GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */ - GPIO_FN(SCIFB_RXD_PORT191), - GPIO_FN(SCIFB_TXD_PORT192), - GPIO_FN(SCIFB_RTS_PORT186), - GPIO_FN(SCIFB_CTS_PORT187), - - GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */ - GPIO_FN(SCIFB_RXD_PORT3), - GPIO_FN(SCIFB_TXD_PORT4), - GPIO_FN(SCIFB_RTS_PORT172), - GPIO_FN(SCIFB_CTS_PORT173), - - /* RSPI */ - GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A), - GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A), - GPIO_FN(RSPI_MISO_A), - - /* VIO CKO */ - GPIO_FN(VIO_CKO1), - GPIO_FN(VIO_CKO2), - GPIO_FN(VIO_CKO_1), - GPIO_FN(VIO_CKO), - - /* VIO0 */ - GPIO_FN(VIO0_D0), GPIO_FN(VIO0_D1), GPIO_FN(VIO0_D2), - GPIO_FN(VIO0_D3), GPIO_FN(VIO0_D4), GPIO_FN(VIO0_D5), - GPIO_FN(VIO0_D6), GPIO_FN(VIO0_D7), GPIO_FN(VIO0_D8), - GPIO_FN(VIO0_D9), GPIO_FN(VIO0_D10), GPIO_FN(VIO0_D11), - GPIO_FN(VIO0_D12), GPIO_FN(VIO0_VD), GPIO_FN(VIO0_HD), - GPIO_FN(VIO0_CLK), GPIO_FN(VIO0_FIELD), - - GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */ - GPIO_FN(VIO0_D14_PORT25), - GPIO_FN(VIO0_D15_PORT24), - - GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */ - GPIO_FN(VIO0_D14_PORT95), - GPIO_FN(VIO0_D15_PORT96), - - /* VIO1 */ - GPIO_FN(VIO1_D0), GPIO_FN(VIO1_D1), GPIO_FN(VIO1_D2), - GPIO_FN(VIO1_D3), GPIO_FN(VIO1_D4), GPIO_FN(VIO1_D5), - GPIO_FN(VIO1_D6), GPIO_FN(VIO1_D7), GPIO_FN(VIO1_VD), - GPIO_FN(VIO1_HD), GPIO_FN(VIO1_CLK), GPIO_FN(VIO1_FIELD), - - /* TPU0 */ - GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3), - GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */ - GPIO_FN(TPU0TO2_PORT202), - - /* SSP1 0 */ - GPIO_FN(STP0_IPD0), GPIO_FN(STP0_IPD1), GPIO_FN(STP0_IPD2), - GPIO_FN(STP0_IPD3), GPIO_FN(STP0_IPD4), GPIO_FN(STP0_IPD5), - GPIO_FN(STP0_IPD6), GPIO_FN(STP0_IPD7), GPIO_FN(STP0_IPEN), - GPIO_FN(STP0_IPCLK), GPIO_FN(STP0_IPSYNC), - - /* SSP1 1 */ - GPIO_FN(STP1_IPD1), GPIO_FN(STP1_IPD2), GPIO_FN(STP1_IPD3), - GPIO_FN(STP1_IPD4), GPIO_FN(STP1_IPD5), GPIO_FN(STP1_IPD6), - GPIO_FN(STP1_IPD7), GPIO_FN(STP1_IPCLK), GPIO_FN(STP1_IPSYNC), - - GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */ - GPIO_FN(STP1_IPEN_PORT187), - - GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */ - GPIO_FN(STP1_IPEN_PORT193), - - /* SIM */ - GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK), - GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */ - GPIO_FN(SIM_D_PORT199), - - /* MSIOF2 */ - GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK), - GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1), - GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_MCK0), GPIO_FN(MSIOF2_RSYNC), - GPIO_FN(MSIOF2_RSCK), - - /* KEYSC */ - GPIO_FN(KEYIN4), GPIO_FN(KEYIN5), - GPIO_FN(KEYIN6), GPIO_FN(KEYIN7), - GPIO_FN(KEYOUT0), GPIO_FN(KEYOUT1), GPIO_FN(KEYOUT2), - GPIO_FN(KEYOUT3), GPIO_FN(KEYOUT4), GPIO_FN(KEYOUT5), - GPIO_FN(KEYOUT6), GPIO_FN(KEYOUT7), - - GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */ - GPIO_FN(KEYIN1_PORT44), - GPIO_FN(KEYIN2_PORT45), - GPIO_FN(KEYIN3_PORT46), - - GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */ - GPIO_FN(KEYIN1_PORT57), - GPIO_FN(KEYIN2_PORT56), - GPIO_FN(KEYIN3_PORT55), - - /* VOU */ - GPIO_FN(DV_D0), GPIO_FN(DV_D1), GPIO_FN(DV_D2), - GPIO_FN(DV_D3), GPIO_FN(DV_D4), GPIO_FN(DV_D5), - GPIO_FN(DV_D6), GPIO_FN(DV_D7), GPIO_FN(DV_D8), - GPIO_FN(DV_D9), GPIO_FN(DV_D10), GPIO_FN(DV_D11), - GPIO_FN(DV_D12), GPIO_FN(DV_D13), GPIO_FN(DV_D14), - GPIO_FN(DV_D15), GPIO_FN(DV_CLK), - GPIO_FN(DV_VSYNC), GPIO_FN(DV_HSYNC), - - /* MEMC */ - GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2), - GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5), - GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8), - GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11), - GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14), - GPIO_FN(MEMC_AD15), GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_INT), - GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_NOE), GPIO_FN(MEMC_CS1), - GPIO_FN(MEMC_A1), GPIO_FN(MEMC_ADV), GPIO_FN(MEMC_DREQ0), - GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK), - GPIO_FN(MEMC_A0), - - /* MSIOF0 */ - GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD), - GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1), - GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_TSCK), - GPIO_FN(MSIOF0_TSYNC), - - /* MSIOF1 */ - GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC), - GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1), - - GPIO_FN(MSIOF1_SS2_PORT116), GPIO_FN(MSIOF1_SS1_PORT117), - GPIO_FN(MSIOF1_RXD_PORT118), GPIO_FN(MSIOF1_TXD_PORT119), - GPIO_FN(MSIOF1_TSYNC_PORT120), - GPIO_FN(MSIOF1_TSCK_PORT121), /* MSEL4CR_10_0 */ - - GPIO_FN(MSIOF1_SS1_PORT67), GPIO_FN(MSIOF1_TSCK_PORT72), - GPIO_FN(MSIOF1_TSYNC_PORT73), GPIO_FN(MSIOF1_TXD_PORT74), - GPIO_FN(MSIOF1_RXD_PORT75), - GPIO_FN(MSIOF1_SS2_PORT202), /* MSEL4CR_10_1 */ - - /* GPIO */ - GPIO_FN(GPO0), GPIO_FN(GPI0), - GPIO_FN(GPO1), GPIO_FN(GPI1), - - /* USB0 */ - GPIO_FN(USB0_OCI), GPIO_FN(USB0_PPON), GPIO_FN(VBUS), - - /* USB1 */ - GPIO_FN(USB1_OCI), GPIO_FN(USB1_PPON), - - /* BBIF1 */ - GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_TSYNC), - GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC), - GPIO_FN(BBIF1_FLOW), GPIO_FN(BBIF1_RX_FLOW_N), - - /* BBIF2 */ - GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */ - GPIO_FN(BBIF2_RXD2_PORT60), - GPIO_FN(BBIF2_TSYNC2_PORT6), - GPIO_FN(BBIF2_TSCK2_PORT59), - - GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */ - GPIO_FN(BBIF2_TXD2_PORT183), - GPIO_FN(BBIF2_TSCK2_PORT89), - GPIO_FN(BBIF2_TSYNC2_PORT184), - - /* BSC / FLCTL / PCMCIA */ - GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4), - GPIO_FN(CS5B), GPIO_FN(CS6A), - GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */ - GPIO_FN(CS5A_PORT19), - GPIO_FN(IOIS16), /* ? */ - - GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3), - GPIO_FN(A4_FOE), GPIO_FN(A5_FCDE), /* share with FLCTL */ - GPIO_FN(A6), GPIO_FN(A7), GPIO_FN(A8), GPIO_FN(A9), - GPIO_FN(A10), GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13), - GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), GPIO_FN(A17), - GPIO_FN(A18), GPIO_FN(A19), GPIO_FN(A20), GPIO_FN(A21), - GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25), - GPIO_FN(A26), - - GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), /* share with FLCTL */ - GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), /* share with FLCTL */ - GPIO_FN(D4_NAF4), GPIO_FN(D5_NAF5), /* share with FLCTL */ - GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), /* share with FLCTL */ - GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), /* share with FLCTL */ - GPIO_FN(D10_NAF10), GPIO_FN(D11_NAF11), /* share with FLCTL */ - GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), /* share with FLCTL */ - GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), /* share with FLCTL */ - GPIO_FN(D16), GPIO_FN(D17), GPIO_FN(D18), GPIO_FN(D19), - GPIO_FN(D20), GPIO_FN(D21), GPIO_FN(D22), GPIO_FN(D23), - GPIO_FN(D24), GPIO_FN(D25), GPIO_FN(D26), GPIO_FN(D27), - GPIO_FN(D28), GPIO_FN(D29), GPIO_FN(D30), GPIO_FN(D31), - - GPIO_FN(WE0_FWE), /* share with FLCTL */ - GPIO_FN(WE1), - GPIO_FN(WE2_ICIORD), /* share with PCMCIA */ - GPIO_FN(WE3_ICIOWR), /* share with PCMCIA */ - GPIO_FN(CKO), GPIO_FN(BS), GPIO_FN(RDWR), - GPIO_FN(RD_FSC), /* share with FLCTL */ - GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */ - GPIO_FN(WAIT_PORT90), - - GPIO_FN(FCE0), GPIO_FN(FCE1), GPIO_FN(FRB), /* FLCTL */ - - /* IRDA */ - GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_OUT), - - /* ATAPI */ - GPIO_FN(IDE_D0), GPIO_FN(IDE_D1), GPIO_FN(IDE_D2), - GPIO_FN(IDE_D3), GPIO_FN(IDE_D4), GPIO_FN(IDE_D5), - GPIO_FN(IDE_D6), GPIO_FN(IDE_D7), GPIO_FN(IDE_D8), - GPIO_FN(IDE_D9), GPIO_FN(IDE_D10), GPIO_FN(IDE_D11), - GPIO_FN(IDE_D12), GPIO_FN(IDE_D13), GPIO_FN(IDE_D14), - GPIO_FN(IDE_D15), GPIO_FN(IDE_A0), GPIO_FN(IDE_A1), - GPIO_FN(IDE_A2), GPIO_FN(IDE_CS0), GPIO_FN(IDE_CS1), - GPIO_FN(IDE_IOWR), GPIO_FN(IDE_IORD), GPIO_FN(IDE_IORDY), - GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION), - GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ), - - /* RMII */ - GPIO_FN(RMII_CRS_DV), GPIO_FN(RMII_RX_ER), GPIO_FN(RMII_RXD0), - GPIO_FN(RMII_RXD1), GPIO_FN(RMII_TX_EN), GPIO_FN(RMII_TXD0), - GPIO_FN(RMII_MDC), GPIO_FN(RMII_TXD1), GPIO_FN(RMII_MDIO), - GPIO_FN(RMII_REF50CK), GPIO_FN(RMII_REF125CK), /* for GMII */ - - /* GEther */ - GPIO_FN(ET_TX_CLK), GPIO_FN(ET_TX_EN), GPIO_FN(ET_ETXD0), - GPIO_FN(ET_ETXD1), GPIO_FN(ET_ETXD2), GPIO_FN(ET_ETXD3), - GPIO_FN(ET_ETXD4), GPIO_FN(ET_ETXD5), /* for GEther */ - GPIO_FN(ET_ETXD6), GPIO_FN(ET_ETXD7), /* for GEther */ - GPIO_FN(ET_COL), GPIO_FN(ET_TX_ER), GPIO_FN(ET_RX_CLK), - GPIO_FN(ET_RX_DV), GPIO_FN(ET_ERXD0), GPIO_FN(ET_ERXD1), - GPIO_FN(ET_ERXD2), GPIO_FN(ET_ERXD3), - GPIO_FN(ET_ERXD4), GPIO_FN(ET_ERXD5), /* for GEther */ - GPIO_FN(ET_ERXD6), GPIO_FN(ET_ERXD7), /* for GEther */ - GPIO_FN(ET_RX_ER), GPIO_FN(ET_CRS), GPIO_FN(ET_MDC), - GPIO_FN(ET_MDIO), GPIO_FN(ET_LINK), GPIO_FN(ET_PHY_INT), - GPIO_FN(ET_WOL), GPIO_FN(ET_GTX_CLK), - - /* DMA0 */ - GPIO_FN(DREQ0), GPIO_FN(DACK0), - - /* DMA1 */ - GPIO_FN(DREQ1), GPIO_FN(DACK1), - - /* SYSC */ - GPIO_FN(RESETOUTS), - - /* IRREM */ - GPIO_FN(IROUT), - - /* LCDC */ - GPIO_FN(LCDC0_SELECT), - GPIO_FN(LCDC1_SELECT), - - /* SDENC */ - GPIO_FN(SDENC_CPG), - GPIO_FN(SDENC_DV_CLKI), - - /* HDMI */ - GPIO_FN(HDMI_HPD), - GPIO_FN(HDMI_CEC), - - /* SYSC */ - GPIO_FN(RESETP_PULLUP), - GPIO_FN(RESETP_PLAIN), - - /* DEBUG */ - GPIO_FN(EDEBGREQ_PULLDOWN), - GPIO_FN(EDEBGREQ_PULLUP), - - GPIO_FN(TRACEAUD_FROM_VIO), - GPIO_FN(TRACEAUD_FROM_LCDC0), - GPIO_FN(TRACEAUD_FROM_MEMC), -}; +#undef PORTCR +#define PORTCR(nr, reg) \ + { \ + PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ + _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \ + PORT##nr##_FN0, PORT##nr##_FN1, \ + PORT##nr##_FN2, PORT##nr##_FN3, \ + PORT##nr##_FN4, PORT##nr##_FN5, \ + PORT##nr##_FN6, PORT##nr##_FN7 } \ + } static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xe6050000), /* PORT0CR */ @@ -2994,48 +3682,114 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { }; static const struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(irq_pin(0), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */ - PINMUX_IRQ(irq_pin(1), GPIO_PORT20), /* IRQ1A */ - PINMUX_IRQ(irq_pin(2), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */ - PINMUX_IRQ(irq_pin(3), GPIO_PORT10, GPIO_PORT14), /* IRQ3A */ - PINMUX_IRQ(irq_pin(4), GPIO_PORT15, GPIO_PORT172),/* IRQ4A */ - PINMUX_IRQ(irq_pin(5), GPIO_PORT0, GPIO_PORT1), /* IRQ5A */ - PINMUX_IRQ(irq_pin(6), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */ - PINMUX_IRQ(irq_pin(7), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */ - PINMUX_IRQ(irq_pin(8), GPIO_PORT119), /* IRQ8A */ - PINMUX_IRQ(irq_pin(9), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */ - PINMUX_IRQ(irq_pin(10), GPIO_PORT19), /* IRQ10A */ - PINMUX_IRQ(irq_pin(11), GPIO_PORT104), /* IRQ11A */ - PINMUX_IRQ(irq_pin(12), GPIO_PORT42, GPIO_PORT97), /* IRQ12A */ - PINMUX_IRQ(irq_pin(13), GPIO_PORT64, GPIO_PORT98), /* IRQ13A */ - PINMUX_IRQ(irq_pin(14), GPIO_PORT63, GPIO_PORT99), /* IRQ14A */ - PINMUX_IRQ(irq_pin(15), GPIO_PORT62, GPIO_PORT100),/* IRQ15A */ - PINMUX_IRQ(irq_pin(16), GPIO_PORT68, GPIO_PORT211),/* IRQ16A */ - PINMUX_IRQ(irq_pin(17), GPIO_PORT69), /* IRQ17A */ - PINMUX_IRQ(irq_pin(18), GPIO_PORT70), /* IRQ18A */ - PINMUX_IRQ(irq_pin(19), GPIO_PORT71), /* IRQ19A */ - PINMUX_IRQ(irq_pin(20), GPIO_PORT67), /* IRQ20A */ - PINMUX_IRQ(irq_pin(21), GPIO_PORT202), /* IRQ21A */ - PINMUX_IRQ(irq_pin(22), GPIO_PORT95), /* IRQ22A */ - PINMUX_IRQ(irq_pin(23), GPIO_PORT96), /* IRQ23A */ - PINMUX_IRQ(irq_pin(24), GPIO_PORT180), /* IRQ24A */ - PINMUX_IRQ(irq_pin(25), GPIO_PORT38), /* IRQ25A */ - PINMUX_IRQ(irq_pin(26), GPIO_PORT58, GPIO_PORT81), /* IRQ26A */ - PINMUX_IRQ(irq_pin(27), GPIO_PORT57, GPIO_PORT168),/* IRQ27A */ - PINMUX_IRQ(irq_pin(28), GPIO_PORT56, GPIO_PORT169),/* IRQ28A */ - PINMUX_IRQ(irq_pin(29), GPIO_PORT50, GPIO_PORT170),/* IRQ29A */ - PINMUX_IRQ(irq_pin(30), GPIO_PORT49, GPIO_PORT171),/* IRQ30A */ - PINMUX_IRQ(irq_pin(31), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */ + PINMUX_IRQ(irq_pin(0), 2, 13), /* IRQ0A */ + PINMUX_IRQ(irq_pin(1), 20), /* IRQ1A */ + PINMUX_IRQ(irq_pin(2), 11, 12), /* IRQ2A */ + PINMUX_IRQ(irq_pin(3), 10, 14), /* IRQ3A */ + PINMUX_IRQ(irq_pin(4), 15, 172), /* IRQ4A */ + PINMUX_IRQ(irq_pin(5), 0, 1), /* IRQ5A */ + PINMUX_IRQ(irq_pin(6), 121, 173), /* IRQ6A */ + PINMUX_IRQ(irq_pin(7), 120, 209), /* IRQ7A */ + PINMUX_IRQ(irq_pin(8), 119), /* IRQ8A */ + PINMUX_IRQ(irq_pin(9), 118, 210), /* IRQ9A */ + PINMUX_IRQ(irq_pin(10), 19), /* IRQ10A */ + PINMUX_IRQ(irq_pin(11), 104), /* IRQ11A */ + PINMUX_IRQ(irq_pin(12), 42, 97), /* IRQ12A */ + PINMUX_IRQ(irq_pin(13), 64, 98), /* IRQ13A */ + PINMUX_IRQ(irq_pin(14), 63, 99), /* IRQ14A */ + PINMUX_IRQ(irq_pin(15), 62, 100), /* IRQ15A */ + PINMUX_IRQ(irq_pin(16), 68, 211), /* IRQ16A */ + PINMUX_IRQ(irq_pin(17), 69), /* IRQ17A */ + PINMUX_IRQ(irq_pin(18), 70), /* IRQ18A */ + PINMUX_IRQ(irq_pin(19), 71), /* IRQ19A */ + PINMUX_IRQ(irq_pin(20), 67), /* IRQ20A */ + PINMUX_IRQ(irq_pin(21), 202), /* IRQ21A */ + PINMUX_IRQ(irq_pin(22), 95), /* IRQ22A */ + PINMUX_IRQ(irq_pin(23), 96), /* IRQ23A */ + PINMUX_IRQ(irq_pin(24), 180), /* IRQ24A */ + PINMUX_IRQ(irq_pin(25), 38), /* IRQ25A */ + PINMUX_IRQ(irq_pin(26), 58, 81), /* IRQ26A */ + PINMUX_IRQ(irq_pin(27), 57, 168), /* IRQ27A */ + PINMUX_IRQ(irq_pin(28), 56, 169), /* IRQ28A */ + PINMUX_IRQ(irq_pin(29), 50, 170), /* IRQ29A */ + PINMUX_IRQ(irq_pin(30), 49, 171), /* IRQ30A */ + PINMUX_IRQ(irq_pin(31), 41, 167), /* IRQ31A */ +}; + +#define PORTnCR_PULMD_OFF (0 << 6) +#define PORTnCR_PULMD_DOWN (2 << 6) +#define PORTnCR_PULMD_UP (3 << 6) +#define PORTnCR_PULMD_MASK (3 << 6) + +struct r8a7740_portcr_group { + unsigned int end_pin; + unsigned int offset; +}; + +static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = { + { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 }, +}; + +static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) { + const struct r8a7740_portcr_group *group = + &r8a7740_portcr_offsets[i]; + + if (i <= group->end_pin) + return pfc->window->virt + group->offset + pin; + } + + return NULL; +} + +static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) +{ + void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin); + u32 value = ioread8(addr) & PORTnCR_PULMD_MASK; + + switch (value) { + case PORTnCR_PULMD_UP: + return PIN_CONFIG_BIAS_PULL_UP; + case PORTnCR_PULMD_DOWN: + return PIN_CONFIG_BIAS_PULL_DOWN; + case PORTnCR_PULMD_OFF: + default: + return PIN_CONFIG_BIAS_DISABLE; + } +} + +static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin); + u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK; + + switch (bias) { + case PIN_CONFIG_BIAS_PULL_UP: + value |= PORTnCR_PULMD_UP; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + value |= PORTnCR_PULMD_DOWN; + break; + } + + iowrite8(value, addr); +} + +static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = { + .get_bias = r8a7740_pinmux_get_bias, + .set_bias = r8a7740_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a7740_pinmux_info = { .name = "r8a7740_pfc", + .ops = &r8a7740_pinmux_ops, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, - PINMUX_INPUT_PULLUP_END }, - .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, - PINMUX_INPUT_PULLDOWN_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, @@ -3048,9 +3802,6 @@ const struct sh_pfc_soc_info r8a7740_pinmux_info = { .functions = pinmux_functions, .nr_functions = ARRAY_SIZE(pinmux_functions), - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c new file mode 100644 index 00000000000..f9039102bb4 --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c @@ -0,0 +1,2783 @@ +/* + * r8a7778 processor support - PFC hardware block + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * Copyright (C) 2013 Cogent Embedded, Inc. + * + * based on + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/platform_data/gpio-rcar.h> +#include <linux/kernel.h> +#include "sh_pfc.h" + +#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx) + +#define PORT_GP_32(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ + PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ + PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ + PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ + PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ + PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ + PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ + PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ + PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ + PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \ + PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx) + +#define PORT_GP_27(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ + PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ + PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ + PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ + PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ + PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ + PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ + PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ + PORT_GP_1(bank, 26, fn, sfx) + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_32(0, fn, sfx), \ + PORT_GP_32(1, fn, sfx), \ + PORT_GP_32(2, fn, sfx), \ + PORT_GP_32(3, fn, sfx), \ + PORT_GP_27(4, fn, sfx) + +#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx + +#define _GP_GPIO(bank, pin, _name, sfx) \ + [RCAR_GP_PIN(bank, pin)] = { \ + .name = __stringify(_name), \ + .enum_id = _name##_DATA, \ + } + +#define _GP_DATA(bank, pin, name, sfx) \ + PINMUX_DATA(name##_DATA, name##_FN) + +#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) + +#define PINMUX_IPSR_NOGP(ispr, fn) PINMUX_DATA(fn##_MARK, FN_##fn) +#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr) +#define PINMUX_IPSR_MSEL(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms) +#define PINMUX_IPSR_NOGM(ispr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */ + PINMUX_DATA_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */ + + /* GPSR0 */ + FN_IP0_1_0, FN_PENC0, FN_PENC1, FN_IP0_4_2, + FN_IP0_7_5, FN_IP0_11_8, FN_IP0_14_12, FN_A1, + FN_A2, FN_A3, FN_IP0_15, FN_IP0_16, + FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, + FN_IP0_21, FN_IP0_22, FN_IP0_23, FN_IP0_24, + FN_IP0_25, FN_IP0_26, FN_IP0_27, FN_IP0_28, + FN_IP0_29, FN_IP0_30, FN_IP1_0, FN_IP1_1, + FN_IP1_4_2, FN_IP1_7_5, FN_IP1_10_8, FN_IP1_14_11, + + /* GPSR1 */ + FN_IP1_23_21, FN_WE0, FN_IP1_24, FN_IP1_27_25, + FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, + FN_IP2_11_9, FN_IP2_13_12, FN_IP2_16_14, FN_IP2_17, + FN_IP2_30, FN_IP2_31, FN_IP3_1_0, FN_IP3_4_2, + FN_IP3_7_5, FN_IP3_9_8, FN_IP3_12_10, FN_IP3_15_13, + FN_IP3_18_16, FN_IP3_20_19, FN_IP3_23_21, FN_IP3_26_24, + FN_IP3_27, FN_IP3_28, FN_IP3_29, FN_IP3_30, + FN_IP3_31, FN_IP4_0, FN_IP4_3_1, FN_IP4_6_4, + + /* GPSR2 */ + FN_IP4_7, FN_IP4_8, FN_IP4_10_9, FN_IP4_12_11, + FN_IP4_14_13, FN_IP4_16_15, FN_IP4_20_17, FN_IP4_24_21, + FN_IP4_26_25, FN_IP4_28_27, FN_IP4_30_29, FN_IP5_1_0, + FN_IP5_3_2, FN_IP5_5_4, FN_IP5_6, FN_IP5_7, + FN_IP5_9_8, FN_IP5_11_10, FN_IP5_12, FN_IP5_14_13, + FN_IP5_17_15, FN_IP5_20_18, FN_AUDIO_CLKA, FN_AUDIO_CLKB, + FN_IP5_22_21, FN_IP5_25_23, FN_IP5_28_26, FN_IP5_30_29, + FN_IP6_1_0, FN_IP6_4_2, FN_IP6_6_5, FN_IP6_7, + + /* GPSR3 */ + FN_IP6_8, FN_IP6_9, FN_SSI_SCK34, FN_IP6_10, + FN_IP6_12_11, FN_IP6_13, FN_IP6_15_14, FN_IP6_16, + FN_IP6_18_17, FN_IP6_20_19, FN_IP6_21, FN_IP6_23_22, + FN_IP6_25_24, FN_IP6_27_26, FN_IP6_29_28, FN_IP6_31_30, + FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_8_6, + FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18, + FN_IP7_21, FN_IP7_24_22, FN_IP7_28_25, FN_IP7_31_29, + FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_10_9, + + /* GPSR4 */ + FN_IP8_13_11, FN_IP8_15_14, FN_IP8_18_16, FN_IP8_21_19, + FN_IP8_23_22, FN_IP8_26_24, FN_IP8_29_27, FN_IP9_2_0, + FN_IP9_5_3, FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, + FN_IP9_17_15, FN_IP9_20_18, FN_IP9_23_21, FN_IP9_26_24, + FN_IP9_29_27, FN_IP10_2_0, FN_IP10_5_3, FN_IP10_8_6, + FN_IP10_12_9, FN_IP10_15_13, FN_IP10_18_16, FN_IP10_21_19, + FN_IP10_24_22, FN_AVS1, FN_AVS2, + + /* IPSR0 */ + FN_PRESETOUT, FN_PWM1, FN_AUDATA0, FN_ARM_TRACEDATA_0, + FN_GPSCLK_C, FN_USB_OVC0, FN_TX2_E, FN_SDA2_B, + FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C, + FN_USB_OVC1, FN_RX2_E, FN_SCL2_B, FN_SD1_DAT2_A, + FN_MMC_D2, FN_BS, FN_ATADIR0_A, FN_SDSELF_A, + FN_PWM4_B, FN_SD1_DAT3_A, FN_MMC_D3, FN_A0, + FN_ATAG0_A, FN_REMOCON_B, FN_A4, FN_A5, + FN_A6, FN_A7, FN_A8, FN_A9, + FN_A10, FN_A11, FN_A12, FN_A13, + FN_A14, FN_A15, FN_A16, FN_A17, + FN_A18, FN_A19, + + /* IPSR1 */ + FN_A20, FN_HSPI_CS1_B, FN_A21, FN_HSPI_CLK1_B, + FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A, + FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A, + FN_TS_SDEN0_A, FN_SD1_CD_A, FN_MMC_D6, FN_A24, + FN_DREQ1_A, FN_HRX0_B, FN_TS_SPSYNC0_A, + FN_SD1_WP_A, FN_MMC_D7, FN_A25, FN_DACK1_A, + FN_HCTS0_B, FN_RX3_C, FN_TS_SDAT0_A, FN_CLKOUT, + FN_HSPI_TX1_B, FN_PWM0_B, FN_CS0, FN_HSPI_RX1_B, + FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A, + FN_SCK2_B, FN_MMC_D5, FN_ATADIR0_B, FN_RD_WR, + FN_WE1, FN_ATAWR0_B, FN_SSI_WS1_B, FN_EX_CS0, + FN_SCL2_A, FN_TX3_C, FN_TS_SCK0_A, FN_EX_CS1, + FN_MMC_D4, + + /* IPSR2 */ + FN_SD1_CLK_A, FN_MMC_CLK, FN_ATACS00, FN_EX_CS2, + FN_SD1_CMD_A, FN_MMC_CMD, FN_ATACS10, FN_EX_CS3, + FN_SD1_DAT0_A, FN_MMC_D0, FN_ATARD0, FN_EX_CS4, + FN_EX_WAIT1_A, FN_SD1_DAT1_A, FN_MMC_D1, FN_ATAWR0_A, + FN_EX_CS5, FN_EX_WAIT2_A, FN_DREQ0_A, FN_RX3_A, + FN_DACK0, FN_TX3_A, FN_DRACK0, FN_EX_WAIT0, + FN_PWM0_C, FN_D0, FN_D1, FN_D2, + FN_D3, FN_D4, FN_D5, FN_D6, + FN_D7, FN_D8, FN_D9, FN_D10, + FN_D11, FN_RD_WR_B, FN_IRQ0, FN_MLB_CLK, + FN_IRQ1_A, + + /* IPSR3 */ + FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A, + FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A, + FN_SDSELF_B, FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B, + FN_CAN_CLK_B, FN_SDA3_B, FN_SD1_CLK_B, FN_HTX0_A, + FN_TX0_A, FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A, + FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B, + FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, FN_SD1_DAT3_B, + FN_HRTS0_A, FN_RTS0, FN_SSI_SCK4, FN_DU0_DR0, + FN_LCDOUT0, FN_AUDATA2, FN_ARM_TRACEDATA_2, + FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B, FN_SSI_WS4, + FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3, FN_ARM_TRACEDATA_3, + FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B, + FN_DU0_DR2, FN_LCDOUT2, FN_DU0_DR3, FN_LCDOUT3, + FN_DU0_DR4, FN_LCDOUT4, FN_DU0_DR5, FN_LCDOUT5, + FN_DU0_DR6, FN_LCDOUT6, + + /* IPSR4 */ + FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8, + FN_AUDATA4, FN_ARM_TRACEDATA_4, FN_TX1_D, + FN_CAN0_TX_A, FN_ADICHS0, FN_DU0_DG1, FN_LCDOUT9, + FN_AUDATA5, FN_ARM_TRACEDATA_5, FN_RX1_D, + FN_CAN0_RX_A, FN_ADIDATA, FN_DU0_DG2, FN_LCDOUT10, + FN_DU0_DG3, FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, + FN_RX0_B, FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B, + FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, FN_DU0_DG7, + FN_LCDOUT15, FN_TX4_A, FN_SSI_SCK2_B, FN_VI0_R0_B, + FN_DU0_DB0, FN_LCDOUT16, FN_AUDATA6, FN_ARM_TRACEDATA_6, + FN_GPSCLK_A, FN_PWM0_A, FN_ADICLK, FN_TS_SDAT0_B, + FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17, + FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A, + FN_ADICS_SAMP, FN_TS_SCK0_B, FN_VI0_R2_B, FN_DU0_DB2, + FN_LCDOUT18, FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19, + FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20, + + /* IPSR5 */ + FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, FN_VI1_DATA10_B, + FN_DU0_DB6, FN_LCDOUT22, FN_VI1_DATA11_B, + FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, + FN_QSTVA_QVS, FN_DU0_DOTCLKO_UT0, FN_QCLK, + FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE, FN_AUDIO_CLKOUT_A, + FN_REMOCON_C, FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC, + FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, + FN_QCPV_QDE, FN_FMCLK_D, FN_SSI_SCK1_A, FN_DU0_DISP, + FN_QPOLA, FN_AUDCK, FN_ARM_TRACECLK, + FN_BPFCLK_D, FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB, + FN_AUDSYNC, FN_ARM_TRACECTL, FN_FMIN_D, + FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B, + FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B, + FN_CAN_CLK_D, FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B, + FN_TX2_A, FN_CAN0_TX_B, FN_SSI_SDATA7, FN_HSPI_TX0_B, + FN_RX2_A, FN_CAN0_RX_B, + + /* IPSR6 */ + FN_SSI_SCK6, FN_HSPI_RX2_A, FN_FMCLK_B, FN_CAN1_TX_B, + FN_SSI_WS6, FN_HSPI_CLK2_A, FN_BPFCLK_B, FN_CAN1_RX_B, + FN_SSI_SDATA6, FN_HSPI_TX2_A, FN_FMIN_B, FN_SSI_SCK5, + FN_RX4_C, FN_SSI_WS5, FN_TX4_C, FN_SSI_SDATA5, + FN_RX0_D, FN_SSI_WS34, FN_ARM_TRACEDATA_8, + FN_SSI_SDATA4, FN_SSI_WS2_A, FN_ARM_TRACEDATA_9, + FN_SSI_SDATA3, FN_ARM_TRACEDATA_10, + FN_SSI_SCK012, FN_ARM_TRACEDATA_11, + FN_TX0_D, FN_SSI_WS012, FN_ARM_TRACEDATA_12, + FN_SSI_SDATA2, FN_HSPI_CS2_A, FN_ARM_TRACEDATA_13, + FN_SDA1_A, FN_SSI_SDATA1, FN_ARM_TRACEDATA_14, + FN_SCL1_A, FN_SCK2_A, FN_SSI_SDATA0, + FN_ARM_TRACEDATA_15, + FN_SD0_CLK, FN_SUB_TDO, FN_SD0_CMD, FN_SUB_TRST, + FN_SD0_DAT0, FN_SUB_TMS, FN_SD0_DAT1, FN_SUB_TCK, + FN_SD0_DAT2, FN_SUB_TDI, + + /* IPSR7 */ + FN_SD0_DAT3, FN_IRQ1_B, FN_SD0_CD, FN_TX5_A, + FN_SD0_WP, FN_RX5_A, FN_VI1_CLKENB, FN_HSPI_CLK0_A, + FN_HTX1_A, FN_RTS1_C, FN_VI1_FIELD, FN_HSPI_CS0_A, + FN_HRX1_A, FN_SCK1_C, FN_VI1_HSYNC, FN_HSPI_RX0_A, + FN_HRTS1_A, FN_FMCLK_A, FN_RX1_C, FN_VI1_VSYNC, + FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A, FN_TX1_C, + FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, FN_IRQ2_C, + FN_CTS1_C, FN_SPEEDIN, FN_VI0_CLK, FN_CAN_CLK_A, + FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6, + FN_HSPI_RX1_A, FN_RX4_B, FN_VI0_FIELD, FN_SD2_DAT3_B, + FN_VI0_R3_C, FN_VI1_DATA1, FN_DU1_DG7, FN_HSPI_CLK1_A, + FN_TX4_B, FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, + FN_DU1_DR2, FN_HSPI_CS1_A, FN_RX3_B, + + /* IPSR8 */ + FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3, + FN_HSPI_TX1_A, FN_TX3_B, FN_VI0_DATA0_VI0_B0, + FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D, FN_VI0_DATA1_VI0_B1, + FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D, FN_VI0_DATA2_VI0_B2, + FN_DU1_DG4, FN_RX0_C, FN_VI0_DATA3_VI0_B3, + FN_DU1_DG5, FN_TX1_A, FN_TX0_C, FN_VI0_DATA4_VI0_B4, + FN_DU1_DB2, FN_RX1_A, FN_VI0_DATA5_VI0_B5, + FN_DU1_DB3, FN_SCK1_A, FN_PWM4, FN_HSCK1_B, + FN_VI0_DATA6_VI0_G0, FN_DU1_DB4, FN_CTS1_A, + FN_PWM5, FN_VI0_DATA7_VI0_G1, FN_DU1_DB5, + FN_RTS1_A, FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4, + FN_DU1_DR4, FN_HTX1_B, FN_VI0_G3, FN_SD2_CMD_B, + FN_VI1_DATA5, FN_DU1_DR5, FN_HRX1_B, + + /* IPSR9 */ + FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6, + FN_HRTS1_B, FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7, + FN_DU1_DR7, FN_HCTS1_B, FN_VI0_R0_A, FN_VI1_CLK, + FN_ETH_REF_CLK, FN_DU1_DOTCLKIN, FN_VI0_R1_A, + FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0, FN_PWM2, + FN_TCLK1, FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7, + FN_ETH_TXD1, FN_PWM3, FN_VI0_R3_A, FN_ETH_CRS_DV, + FN_IECLK, FN_SCK2_C, FN_VI0_R4_A, FN_ETH_TX_EN, + FN_IETX, FN_TX2_C, FN_VI0_R5_A, FN_ETH_RX_ER, + FN_FMCLK_C, FN_IERX, FN_RX2_C, FN_VI1_DATA10_A, + FN_DU1_DOTCLKOUT, FN_ETH_RXD0, FN_BPFCLK_C, + FN_TX2_D, FN_SDA2_C, FN_VI1_DATA11_A, + FN_DU1_EXHSYNC_DU1_HSYNC, FN_ETH_RXD1, FN_FMIN_C, + FN_RX2_D, FN_SCL2_C, + + /* IPSR10 */ + FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC, FN_ATARD1, + FN_ETH_MDC, FN_SDA1_B, FN_SD2_CMD_A, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_ATAWR1, + FN_ETH_MDIO, FN_SCL1_B, FN_SD2_DAT0_A, FN_DU1_DISP, + FN_ATACS01, FN_DREQ1_B, FN_ETH_LINK, FN_CAN1_RX_A, + FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B, + FN_ETH_MAGIC, FN_CAN1_TX_A, FN_PWM6, FN_SD2_DAT2_A, + FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1, FN_HSPI_CLK2_B, + FN_GPSCLK_B, FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B, + FN_ATAG1, FN_HSPI_CS2_B, FN_GPSIN_B, FN_SD2_CD_A, + FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B, FN_HSPI_RX2_B, + FN_REMOCON_A, FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B, + FN_DACK0_B, FN_HSPI_TX2_B, FN_CAN_CLK_C, + + /* SEL */ + FN_SEL_SCIF5_A, FN_SEL_SCIF5_B, + FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, FN_SEL_SCIF4_C, + FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, FN_SEL_SCIF3_C, FN_SEL_SCIF3_D, + FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, FN_SEL_SCIF2_E, + FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, FN_SEL_SCIF1_C, FN_SEL_SCIF1_D, + FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, FN_SEL_SCIF0_C, FN_SEL_SCIF0_D, + FN_SEL_SSI2_A, FN_SEL_SSI2_B, + FN_SEL_SSI1_A, FN_SEL_SSI1_B, + FN_SEL_VI1_A, FN_SEL_VI1_B, + FN_SEL_VI0_A, FN_SEL_VI0_B, FN_SEL_VI0_C, FN_SEL_VI0_D, + FN_SEL_SD2_A, FN_SEL_SD2_B, + FN_SEL_SD1_A, FN_SEL_SD1_B, + FN_SEL_IRQ3_A, FN_SEL_IRQ3_B, + FN_SEL_IRQ2_A, FN_SEL_IRQ2_B, FN_SEL_IRQ2_C, + FN_SEL_IRQ1_A, FN_SEL_IRQ1_B, + FN_SEL_DREQ2_A, FN_SEL_DREQ2_B, + FN_SEL_DREQ1_A, FN_SEL_DREQ1_B, + FN_SEL_DREQ0_A, FN_SEL_DREQ0_B, + FN_SEL_WAIT2_A, FN_SEL_WAIT2_B, + FN_SEL_WAIT1_A, FN_SEL_WAIT1_B, + FN_SEL_CAN1_A, FN_SEL_CAN1_B, + FN_SEL_CAN0_A, FN_SEL_CAN0_B, + FN_SEL_CANCLK_A, FN_SEL_CANCLK_B, + FN_SEL_CANCLK_C, FN_SEL_CANCLK_D, + FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B, + FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B, + FN_SEL_REMOCON_A, FN_SEL_REMOCON_B, FN_SEL_REMOCON_C, + FN_SEL_FM_A, FN_SEL_FM_B, FN_SEL_FM_C, FN_SEL_FM_D, + FN_SEL_GPS_A, FN_SEL_GPS_B, FN_SEL_GPS_C, + FN_SEL_TSIF0_A, FN_SEL_TSIF0_B, + FN_SEL_HSPI2_A, FN_SEL_HSPI2_B, + FN_SEL_HSPI1_A, FN_SEL_HSPI1_B, + FN_SEL_HSPI0_A, FN_SEL_HSPI0_B, + FN_SEL_I2C3_A, FN_SEL_I2C3_B, FN_SEL_I2C3_C, + FN_SEL_I2C2_A, FN_SEL_I2C2_B, FN_SEL_I2C2_C, + FN_SEL_I2C1_A, FN_SEL_I2C1_B, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + /* GPSR0 */ + PENC0_MARK, PENC1_MARK, A1_MARK, A2_MARK, A3_MARK, + + /* GPSR1 */ + WE0_MARK, + + /* GPSR2 */ + AUDIO_CLKA_MARK, + AUDIO_CLKB_MARK, + + /* GPSR3 */ + SSI_SCK34_MARK, + + /* GPSR4 */ + AVS1_MARK, + AVS2_MARK, + + VI0_R0_C_MARK, /* see sel_vi0 */ + VI0_R1_C_MARK, /* see sel_vi0 */ + VI0_R2_C_MARK, /* see sel_vi0 */ + /* VI0_R3_C_MARK, */ + VI0_R4_C_MARK, /* see sel_vi0 */ + VI0_R5_C_MARK, /* see sel_vi0 */ + + VI0_R0_D_MARK, /* see sel_vi0 */ + VI0_R1_D_MARK, /* see sel_vi0 */ + VI0_R2_D_MARK, /* see sel_vi0 */ + VI0_R3_D_MARK, /* see sel_vi0 */ + VI0_R4_D_MARK, /* see sel_vi0 */ + VI0_R5_D_MARK, /* see sel_vi0 */ + + /* IPSR0 */ + PRESETOUT_MARK, PWM1_MARK, AUDATA0_MARK, + ARM_TRACEDATA_0_MARK, GPSCLK_C_MARK, USB_OVC0_MARK, + TX2_E_MARK, SDA2_B_MARK, AUDATA1_MARK, ARM_TRACEDATA_1_MARK, + GPSIN_C_MARK, USB_OVC1_MARK, RX2_E_MARK, SCL2_B_MARK, + SD1_DAT2_A_MARK, MMC_D2_MARK, BS_MARK, + ATADIR0_A_MARK, SDSELF_A_MARK, PWM4_B_MARK, SD1_DAT3_A_MARK, + MMC_D3_MARK, A0_MARK, ATAG0_A_MARK, REMOCON_B_MARK, + A4_MARK, A5_MARK, A6_MARK, A7_MARK, + A8_MARK, A9_MARK, A10_MARK, A11_MARK, + A12_MARK, A13_MARK, A14_MARK, A15_MARK, + A16_MARK, A17_MARK, A18_MARK, A19_MARK, + + /* IPSR1 */ + A20_MARK, HSPI_CS1_B_MARK, A21_MARK, + HSPI_CLK1_B_MARK, A22_MARK, HRTS0_B_MARK, + RX2_B_MARK, DREQ2_A_MARK, A23_MARK, HTX0_B_MARK, + TX2_B_MARK, DACK2_A_MARK, TS_SDEN0_A_MARK, + SD1_CD_A_MARK, MMC_D6_MARK, A24_MARK, DREQ1_A_MARK, + HRX0_B_MARK, TS_SPSYNC0_A_MARK, SD1_WP_A_MARK, + MMC_D7_MARK, A25_MARK, DACK1_A_MARK, HCTS0_B_MARK, + RX3_C_MARK, TS_SDAT0_A_MARK, CLKOUT_MARK, + HSPI_TX1_B_MARK, PWM0_B_MARK, CS0_MARK, + HSPI_RX1_B_MARK, SSI_SCK1_B_MARK, + ATAG0_B_MARK, CS1_A26_MARK, SDA2_A_MARK, SCK2_B_MARK, + MMC_D5_MARK, ATADIR0_B_MARK, RD_WR_MARK, WE1_MARK, + ATAWR0_B_MARK, SSI_WS1_B_MARK, EX_CS0_MARK, SCL2_A_MARK, + TX3_C_MARK, TS_SCK0_A_MARK, EX_CS1_MARK, MMC_D4_MARK, + + /* IPSR2 */ + SD1_CLK_A_MARK, MMC_CLK_MARK, ATACS00_MARK, EX_CS2_MARK, + SD1_CMD_A_MARK, MMC_CMD_MARK, ATACS10_MARK, EX_CS3_MARK, + SD1_DAT0_A_MARK, MMC_D0_MARK, ATARD0_MARK, + EX_CS4_MARK, EX_WAIT1_A_MARK, SD1_DAT1_A_MARK, + MMC_D1_MARK, ATAWR0_A_MARK, EX_CS5_MARK, EX_WAIT2_A_MARK, + DREQ0_A_MARK, RX3_A_MARK, DACK0_MARK, TX3_A_MARK, + DRACK0_MARK, EX_WAIT0_MARK, PWM0_C_MARK, D0_MARK, + D1_MARK, D2_MARK, D3_MARK, D4_MARK, + D5_MARK, D6_MARK, D7_MARK, D8_MARK, + D9_MARK, D10_MARK, D11_MARK, RD_WR_B_MARK, + IRQ0_MARK, MLB_CLK_MARK, IRQ1_A_MARK, + + /* IPSR3 */ + MLB_SIG_MARK, RX5_B_MARK, SDA3_A_MARK, IRQ2_A_MARK, + MLB_DAT_MARK, TX5_B_MARK, SCL3_A_MARK, IRQ3_A_MARK, + SDSELF_B_MARK, SD1_CMD_B_MARK, SCIF_CLK_MARK, AUDIO_CLKOUT_B_MARK, + CAN_CLK_B_MARK, SDA3_B_MARK, SD1_CLK_B_MARK, HTX0_A_MARK, + TX0_A_MARK, SD1_DAT0_B_MARK, HRX0_A_MARK, + RX0_A_MARK, SD1_DAT1_B_MARK, HSCK0_MARK, + SCK0_MARK, SCL3_B_MARK, SD1_DAT2_B_MARK, + HCTS0_A_MARK, CTS0_MARK, SD1_DAT3_B_MARK, + HRTS0_A_MARK, RTS0_MARK, SSI_SCK4_MARK, + DU0_DR0_MARK, LCDOUT0_MARK, AUDATA2_MARK, ARM_TRACEDATA_2_MARK, + SDA3_C_MARK, ADICHS1_MARK, TS_SDEN0_B_MARK, + SSI_WS4_MARK, DU0_DR1_MARK, LCDOUT1_MARK, AUDATA3_MARK, + ARM_TRACEDATA_3_MARK, SCL3_C_MARK, ADICHS2_MARK, + TS_SPSYNC0_B_MARK, DU0_DR2_MARK, LCDOUT2_MARK, + DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK, + DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK, + + /* IPSR4 */ + DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK, + AUDATA4_MARK, ARM_TRACEDATA_4_MARK, + TX1_D_MARK, CAN0_TX_A_MARK, ADICHS0_MARK, DU0_DG1_MARK, + LCDOUT9_MARK, AUDATA5_MARK, ARM_TRACEDATA_5_MARK, + RX1_D_MARK, CAN0_RX_A_MARK, ADIDATA_MARK, DU0_DG2_MARK, + LCDOUT10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, DU0_DG4_MARK, + LCDOUT12_MARK, RX0_B_MARK, DU0_DG5_MARK, LCDOUT13_MARK, + TX0_B_MARK, DU0_DG6_MARK, LCDOUT14_MARK, RX4_A_MARK, + DU0_DG7_MARK, LCDOUT15_MARK, TX4_A_MARK, SSI_SCK2_B_MARK, + VI0_R0_B_MARK, DU0_DB0_MARK, LCDOUT16_MARK, AUDATA6_MARK, + ARM_TRACEDATA_6_MARK, GPSCLK_A_MARK, PWM0_A_MARK, + ADICLK_MARK, TS_SDAT0_B_MARK, AUDIO_CLKC_MARK, + VI0_R1_B_MARK, DU0_DB1_MARK, LCDOUT17_MARK, AUDATA7_MARK, + ARM_TRACEDATA_7_MARK, GPSIN_A_MARK, ADICS_SAMP_MARK, + TS_SCK0_B_MARK, VI0_R2_B_MARK, DU0_DB2_MARK, LCDOUT18_MARK, + VI0_R3_B_MARK, DU0_DB3_MARK, LCDOUT19_MARK, VI0_R4_B_MARK, + DU0_DB4_MARK, LCDOUT20_MARK, + + /* IPSR5 */ + VI0_R5_B_MARK, DU0_DB5_MARK, LCDOUT21_MARK, VI1_DATA10_B_MARK, + DU0_DB6_MARK, LCDOUT22_MARK, VI1_DATA11_B_MARK, + DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, + QSTVA_QVS_MARK, DU0_DOTCLKO_UT0_MARK, + QCLK_MARK, DU0_DOTCLKO_UT1_MARK, QSTVB_QVE_MARK, + AUDIO_CLKOUT_A_MARK, REMOCON_C_MARK, SSI_WS2_B_MARK, + DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK, + DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, + QCPV_QDE_MARK, FMCLK_D_MARK, SSI_SCK1_A_MARK, + DU0_DISP_MARK, QPOLA_MARK, AUDCK_MARK, ARM_TRACECLK_MARK, + BPFCLK_D_MARK, SSI_WS1_A_MARK, DU0_CDE_MARK, QPOLB_MARK, + AUDSYNC_MARK, ARM_TRACECTL_MARK, FMIN_D_MARK, + SD1_CD_B_MARK, SSI_SCK78_MARK, HSPI_RX0_B_MARK, + TX1_B_MARK, SD1_WP_B_MARK, SSI_WS78_MARK, HSPI_CLK0_B_MARK, + RX1_B_MARK, CAN_CLK_D_MARK, SSI_SDATA8_MARK, + SSI_SCK2_A_MARK, HSPI_CS0_B_MARK, + TX2_A_MARK, CAN0_TX_B_MARK, SSI_SDATA7_MARK, + HSPI_TX0_B_MARK, RX2_A_MARK, CAN0_RX_B_MARK, + + /* IPSR6 */ + SSI_SCK6_MARK, HSPI_RX2_A_MARK, FMCLK_B_MARK, + CAN1_TX_B_MARK, SSI_WS6_MARK, HSPI_CLK2_A_MARK, + BPFCLK_B_MARK, CAN1_RX_B_MARK, SSI_SDATA6_MARK, + HSPI_TX2_A_MARK, FMIN_B_MARK, SSI_SCK5_MARK, + RX4_C_MARK, SSI_WS5_MARK, TX4_C_MARK, SSI_SDATA5_MARK, + RX0_D_MARK, SSI_WS34_MARK, ARM_TRACEDATA_8_MARK, + SSI_SDATA4_MARK, SSI_WS2_A_MARK, ARM_TRACEDATA_9_MARK, + SSI_SDATA3_MARK, ARM_TRACEDATA_10_MARK, + SSI_SCK012_MARK, ARM_TRACEDATA_11_MARK, + TX0_D_MARK, SSI_WS012_MARK, ARM_TRACEDATA_12_MARK, + SSI_SDATA2_MARK, HSPI_CS2_A_MARK, + ARM_TRACEDATA_13_MARK, SDA1_A_MARK, SSI_SDATA1_MARK, + ARM_TRACEDATA_14_MARK, SCL1_A_MARK, SCK2_A_MARK, + SSI_SDATA0_MARK, ARM_TRACEDATA_15_MARK, + SD0_CLK_MARK, SUB_TDO_MARK, SD0_CMD_MARK, SUB_TRST_MARK, + SD0_DAT0_MARK, SUB_TMS_MARK, SD0_DAT1_MARK, SUB_TCK_MARK, + SD0_DAT2_MARK, SUB_TDI_MARK, + + /* IPSR7 */ + SD0_DAT3_MARK, IRQ1_B_MARK, SD0_CD_MARK, TX5_A_MARK, + SD0_WP_MARK, RX5_A_MARK, VI1_CLKENB_MARK, + HSPI_CLK0_A_MARK, HTX1_A_MARK, RTS1_C_MARK, VI1_FIELD_MARK, + HSPI_CS0_A_MARK, HRX1_A_MARK, SCK1_C_MARK, VI1_HSYNC_MARK, + HSPI_RX0_A_MARK, HRTS1_A_MARK, FMCLK_A_MARK, RX1_C_MARK, + VI1_VSYNC_MARK, HSPI_TX0_MARK, HCTS1_A_MARK, BPFCLK_A_MARK, + TX1_C_MARK, TCLK0_MARK, HSCK1_A_MARK, FMIN_A_MARK, + IRQ2_C_MARK, CTS1_C_MARK, SPEEDIN_MARK, VI0_CLK_MARK, + CAN_CLK_A_MARK, VI0_CLKENB_MARK, SD2_DAT2_B_MARK, + VI1_DATA0_MARK, DU1_DG6_MARK, HSPI_RX1_A_MARK, + RX4_B_MARK, VI0_FIELD_MARK, SD2_DAT3_B_MARK, + VI0_R3_C_MARK, VI1_DATA1_MARK, DU1_DG7_MARK, HSPI_CLK1_A_MARK, + TX4_B_MARK, VI0_HSYNC_MARK, SD2_CD_B_MARK, VI1_DATA2_MARK, + DU1_DR2_MARK, HSPI_CS1_A_MARK, RX3_B_MARK, + + /* IPSR8 */ + VI0_VSYNC_MARK, SD2_WP_B_MARK, VI1_DATA3_MARK, DU1_DR3_MARK, + HSPI_TX1_A_MARK, TX3_B_MARK, VI0_DATA0_VI0_B0_MARK, + DU1_DG2_MARK, IRQ2_B_MARK, RX3_D_MARK, VI0_DATA1_VI0_B1_MARK, + DU1_DG3_MARK, IRQ3_B_MARK, TX3_D_MARK, VI0_DATA2_VI0_B2_MARK, + DU1_DG4_MARK, RX0_C_MARK, VI0_DATA3_VI0_B3_MARK, + DU1_DG5_MARK, TX1_A_MARK, TX0_C_MARK, VI0_DATA4_VI0_B4_MARK, + DU1_DB2_MARK, RX1_A_MARK, VI0_DATA5_VI0_B5_MARK, + DU1_DB3_MARK, SCK1_A_MARK, PWM4_MARK, HSCK1_B_MARK, + VI0_DATA6_VI0_G0_MARK, DU1_DB4_MARK, CTS1_A_MARK, + PWM5_MARK, VI0_DATA7_VI0_G1_MARK, DU1_DB5_MARK, + RTS1_A_MARK, VI0_G2_MARK, SD2_CLK_B_MARK, VI1_DATA4_MARK, + DU1_DR4_MARK, HTX1_B_MARK, VI0_G3_MARK, SD2_CMD_B_MARK, + VI1_DATA5_MARK, DU1_DR5_MARK, HRX1_B_MARK, + + /* IPSR9 */ + VI0_G4_MARK, SD2_DAT0_B_MARK, VI1_DATA6_MARK, + DU1_DR6_MARK, HRTS1_B_MARK, VI0_G5_MARK, SD2_DAT1_B_MARK, + VI1_DATA7_MARK, DU1_DR7_MARK, HCTS1_B_MARK, VI0_R0_A_MARK, + VI1_CLK_MARK, ETH_REF_CLK_MARK, DU1_DOTCLKIN_MARK, + VI0_R1_A_MARK, VI1_DATA8_MARK, DU1_DB6_MARK, ETH_TXD0_MARK, + PWM2_MARK, TCLK1_MARK, VI0_R2_A_MARK, VI1_DATA9_MARK, + DU1_DB7_MARK, ETH_TXD1_MARK, PWM3_MARK, VI0_R3_A_MARK, + ETH_CRS_DV_MARK, IECLK_MARK, SCK2_C_MARK, + VI0_R4_A_MARK, ETH_TX_EN_MARK, IETX_MARK, + TX2_C_MARK, VI0_R5_A_MARK, ETH_RX_ER_MARK, FMCLK_C_MARK, + IERX_MARK, RX2_C_MARK, VI1_DATA10_A_MARK, + DU1_DOTCLKOUT_MARK, ETH_RXD0_MARK, + BPFCLK_C_MARK, TX2_D_MARK, SDA2_C_MARK, VI1_DATA11_A_MARK, + DU1_EXHSYNC_DU1_HSYNC_MARK, ETH_RXD1_MARK, FMIN_C_MARK, + RX2_D_MARK, SCL2_C_MARK, + + /* IPSR10 */ + SD2_CLK_A_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, ATARD1_MARK, + ETH_MDC_MARK, SDA1_B_MARK, SD2_CMD_A_MARK, + DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, ATAWR1_MARK, + ETH_MDIO_MARK, SCL1_B_MARK, SD2_DAT0_A_MARK, + DU1_DISP_MARK, ATACS01_MARK, DREQ1_B_MARK, ETH_LINK_MARK, + CAN1_RX_A_MARK, SD2_DAT1_A_MARK, DU1_CDE_MARK, + ATACS11_MARK, DACK1_B_MARK, ETH_MAGIC_MARK, CAN1_TX_A_MARK, + PWM6_MARK, SD2_DAT2_A_MARK, VI1_DATA12_MARK, + DREQ2_B_MARK, ATADIR1_MARK, HSPI_CLK2_B_MARK, + GPSCLK_B_MARK, SD2_DAT3_A_MARK, VI1_DATA13_MARK, + DACK2_B_MARK, ATAG1_MARK, HSPI_CS2_B_MARK, + GPSIN_B_MARK, SD2_CD_A_MARK, VI1_DATA14_MARK, + EX_WAIT1_B_MARK, DREQ0_B_MARK, HSPI_RX2_B_MARK, + REMOCON_A_MARK, SD2_WP_A_MARK, VI1_DATA15_MARK, + EX_WAIT2_B_MARK, DACK0_B_MARK, + HSPI_TX2_B_MARK, CAN_CLK_C_MARK, + + PINMUX_MARK_END, +}; + +static const pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(PENC0_MARK, FN_PENC0), + PINMUX_DATA(PENC1_MARK, FN_PENC1), + PINMUX_DATA(A1_MARK, FN_A1), + PINMUX_DATA(A2_MARK, FN_A2), + PINMUX_DATA(A3_MARK, FN_A3), + PINMUX_DATA(WE0_MARK, FN_WE0), + PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA), + PINMUX_DATA(AUDIO_CLKB_MARK, FN_AUDIO_CLKB), + PINMUX_DATA(SSI_SCK34_MARK, FN_SSI_SCK34), + PINMUX_DATA(AVS1_MARK, FN_AVS1), + PINMUX_DATA(AVS2_MARK, FN_AVS2), + + /* IPSR0 */ + PINMUX_IPSR_DATA(IP0_1_0, PRESETOUT), + PINMUX_IPSR_DATA(IP0_1_0, PWM1), + + PINMUX_IPSR_DATA(IP0_4_2, AUDATA0), + PINMUX_IPSR_DATA(IP0_4_2, ARM_TRACEDATA_0), + PINMUX_IPSR_MSEL(IP0_4_2, GPSCLK_C, SEL_GPS_C), + PINMUX_IPSR_DATA(IP0_4_2, USB_OVC0), + PINMUX_IPSR_DATA(IP0_4_2, TX2_E), + PINMUX_IPSR_MSEL(IP0_4_2, SDA2_B, SEL_I2C2_B), + + PINMUX_IPSR_DATA(IP0_7_5, AUDATA1), + PINMUX_IPSR_DATA(IP0_7_5, ARM_TRACEDATA_1), + PINMUX_IPSR_MSEL(IP0_7_5, GPSIN_C, SEL_GPS_C), + PINMUX_IPSR_DATA(IP0_7_5, USB_OVC1), + PINMUX_IPSR_MSEL(IP0_7_5, RX2_E, SEL_SCIF2_E), + PINMUX_IPSR_MSEL(IP0_7_5, SCL2_B, SEL_I2C2_B), + + PINMUX_IPSR_MSEL(IP0_11_8, SD1_DAT2_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP0_11_8, MMC_D2), + PINMUX_IPSR_DATA(IP0_11_8, BS), + PINMUX_IPSR_DATA(IP0_11_8, ATADIR0_A), + PINMUX_IPSR_DATA(IP0_11_8, SDSELF_A), + PINMUX_IPSR_DATA(IP0_11_8, PWM4_B), + + PINMUX_IPSR_MSEL(IP0_14_12, SD1_DAT3_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP0_14_12, MMC_D3), + PINMUX_IPSR_DATA(IP0_14_12, A0), + PINMUX_IPSR_DATA(IP0_14_12, ATAG0_A), + PINMUX_IPSR_MSEL(IP0_14_12, REMOCON_B, SEL_REMOCON_B), + + PINMUX_IPSR_DATA(IP0_15, A4), + PINMUX_IPSR_DATA(IP0_16, A5), + PINMUX_IPSR_DATA(IP0_17, A6), + PINMUX_IPSR_DATA(IP0_18, A7), + PINMUX_IPSR_DATA(IP0_19, A8), + PINMUX_IPSR_DATA(IP0_20, A9), + PINMUX_IPSR_DATA(IP0_21, A10), + PINMUX_IPSR_DATA(IP0_22, A11), + PINMUX_IPSR_DATA(IP0_23, A12), + PINMUX_IPSR_DATA(IP0_24, A13), + PINMUX_IPSR_DATA(IP0_25, A14), + PINMUX_IPSR_DATA(IP0_26, A15), + PINMUX_IPSR_DATA(IP0_27, A16), + PINMUX_IPSR_DATA(IP0_28, A17), + PINMUX_IPSR_DATA(IP0_29, A18), + PINMUX_IPSR_DATA(IP0_30, A19), + + /* IPSR1 */ + PINMUX_IPSR_DATA(IP1_0, A20), + PINMUX_IPSR_MSEL(IP1_0, HSPI_CS1_B, SEL_HSPI1_B), + + PINMUX_IPSR_DATA(IP1_1, A21), + PINMUX_IPSR_MSEL(IP1_1, HSPI_CLK1_B, SEL_HSPI1_B), + + PINMUX_IPSR_DATA(IP1_4_2, A22), + PINMUX_IPSR_MSEL(IP1_4_2, HRTS0_B, SEL_HSCIF0_B), + PINMUX_IPSR_MSEL(IP1_4_2, RX2_B, SEL_SCIF2_B), + PINMUX_IPSR_MSEL(IP1_4_2, DREQ2_A, SEL_DREQ2_A), + + PINMUX_IPSR_DATA(IP1_7_5, A23), + PINMUX_IPSR_DATA(IP1_7_5, HTX0_B), + PINMUX_IPSR_DATA(IP1_7_5, TX2_B), + PINMUX_IPSR_DATA(IP1_7_5, DACK2_A), + PINMUX_IPSR_MSEL(IP1_7_5, TS_SDEN0_A, SEL_TSIF0_A), + + PINMUX_IPSR_MSEL(IP1_10_8, SD1_CD_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP1_10_8, MMC_D6), + PINMUX_IPSR_DATA(IP1_10_8, A24), + PINMUX_IPSR_MSEL(IP1_10_8, DREQ1_A, SEL_DREQ1_A), + PINMUX_IPSR_MSEL(IP1_10_8, HRX0_B, SEL_HSCIF0_B), + PINMUX_IPSR_MSEL(IP1_10_8, TS_SPSYNC0_A, SEL_TSIF0_A), + + PINMUX_IPSR_MSEL(IP1_14_11, SD1_WP_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP1_14_11, MMC_D7), + PINMUX_IPSR_DATA(IP1_14_11, A25), + PINMUX_IPSR_DATA(IP1_14_11, DACK1_A), + PINMUX_IPSR_MSEL(IP1_14_11, HCTS0_B, SEL_HSCIF0_B), + PINMUX_IPSR_MSEL(IP1_14_11, RX3_C, SEL_SCIF3_C), + PINMUX_IPSR_MSEL(IP1_14_11, TS_SDAT0_A, SEL_TSIF0_A), + + PINMUX_IPSR_NOGP(IP1_16_15, CLKOUT), + PINMUX_IPSR_NOGP(IP1_16_15, HSPI_TX1_B), + PINMUX_IPSR_NOGP(IP1_16_15, PWM0_B), + + PINMUX_IPSR_NOGP(IP1_17, CS0), + PINMUX_IPSR_NOGM(IP1_17, HSPI_RX1_B, SEL_HSPI1_B), + + PINMUX_IPSR_NOGM(IP1_20_18, SSI_SCK1_B, SEL_SSI1_B), + PINMUX_IPSR_NOGP(IP1_20_18, ATAG0_B), + PINMUX_IPSR_NOGP(IP1_20_18, CS1_A26), + PINMUX_IPSR_NOGM(IP1_20_18, SDA2_A, SEL_I2C2_A), + PINMUX_IPSR_NOGM(IP1_20_18, SCK2_B, SEL_SCIF2_B), + + PINMUX_IPSR_DATA(IP1_23_21, MMC_D5), + PINMUX_IPSR_DATA(IP1_23_21, ATADIR0_B), + PINMUX_IPSR_DATA(IP1_23_21, RD_WR), + + PINMUX_IPSR_DATA(IP1_24, WE1), + PINMUX_IPSR_DATA(IP1_24, ATAWR0_B), + + PINMUX_IPSR_MSEL(IP1_27_25, SSI_WS1_B, SEL_SSI1_B), + PINMUX_IPSR_DATA(IP1_27_25, EX_CS0), + PINMUX_IPSR_MSEL(IP1_27_25, SCL2_A, SEL_I2C2_A), + PINMUX_IPSR_DATA(IP1_27_25, TX3_C), + PINMUX_IPSR_MSEL(IP1_27_25, TS_SCK0_A, SEL_TSIF0_A), + + PINMUX_IPSR_DATA(IP1_29_28, EX_CS1), + PINMUX_IPSR_DATA(IP1_29_28, MMC_D4), + + /* IPSR2 */ + PINMUX_IPSR_DATA(IP2_2_0, SD1_CLK_A), + PINMUX_IPSR_DATA(IP2_2_0, MMC_CLK), + PINMUX_IPSR_DATA(IP2_2_0, ATACS00), + PINMUX_IPSR_DATA(IP2_2_0, EX_CS2), + + PINMUX_IPSR_MSEL(IP2_5_3, SD1_CMD_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP2_5_3, MMC_CMD), + PINMUX_IPSR_DATA(IP2_5_3, ATACS10), + PINMUX_IPSR_DATA(IP2_5_3, EX_CS3), + + PINMUX_IPSR_MSEL(IP2_8_6, SD1_DAT0_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP2_8_6, MMC_D0), + PINMUX_IPSR_DATA(IP2_8_6, ATARD0), + PINMUX_IPSR_DATA(IP2_8_6, EX_CS4), + PINMUX_IPSR_MSEL(IP2_8_6, EX_WAIT1_A, SEL_WAIT1_A), + + PINMUX_IPSR_MSEL(IP2_11_9, SD1_DAT1_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP2_11_9, MMC_D1), + PINMUX_IPSR_DATA(IP2_11_9, ATAWR0_A), + PINMUX_IPSR_DATA(IP2_11_9, EX_CS5), + PINMUX_IPSR_MSEL(IP2_11_9, EX_WAIT2_A, SEL_WAIT2_A), + + PINMUX_IPSR_MSEL(IP2_13_12, DREQ0_A, SEL_DREQ0_A), + PINMUX_IPSR_MSEL(IP2_13_12, RX3_A, SEL_SCIF3_A), + + PINMUX_IPSR_DATA(IP2_16_14, DACK0), + PINMUX_IPSR_DATA(IP2_16_14, TX3_A), + PINMUX_IPSR_DATA(IP2_16_14, DRACK0), + + PINMUX_IPSR_DATA(IP2_17, EX_WAIT0), + PINMUX_IPSR_DATA(IP2_17, PWM0_C), + + PINMUX_IPSR_NOGP(IP2_18, D0), + PINMUX_IPSR_NOGP(IP2_19, D1), + PINMUX_IPSR_NOGP(IP2_20, D2), + PINMUX_IPSR_NOGP(IP2_21, D3), + PINMUX_IPSR_NOGP(IP2_22, D4), + PINMUX_IPSR_NOGP(IP2_23, D5), + PINMUX_IPSR_NOGP(IP2_24, D6), + PINMUX_IPSR_NOGP(IP2_25, D7), + PINMUX_IPSR_NOGP(IP2_26, D8), + PINMUX_IPSR_NOGP(IP2_27, D9), + PINMUX_IPSR_NOGP(IP2_28, D10), + PINMUX_IPSR_NOGP(IP2_29, D11), + + PINMUX_IPSR_DATA(IP2_30, RD_WR_B), + PINMUX_IPSR_DATA(IP2_30, IRQ0), + + PINMUX_IPSR_DATA(IP2_31, MLB_CLK), + PINMUX_IPSR_MSEL(IP2_31, IRQ1_A, SEL_IRQ1_A), + + /* IPSR3 */ + PINMUX_IPSR_DATA(IP3_1_0, MLB_SIG), + PINMUX_IPSR_MSEL(IP3_1_0, RX5_B, SEL_SCIF5_B), + PINMUX_IPSR_MSEL(IP3_1_0, SDA3_A, SEL_I2C3_A), + PINMUX_IPSR_MSEL(IP3_1_0, IRQ2_A, SEL_IRQ2_A), + + PINMUX_IPSR_DATA(IP3_4_2, MLB_DAT), + PINMUX_IPSR_DATA(IP3_4_2, TX5_B), + PINMUX_IPSR_MSEL(IP3_4_2, SCL3_A, SEL_I2C3_A), + PINMUX_IPSR_MSEL(IP3_4_2, IRQ3_A, SEL_IRQ3_A), + PINMUX_IPSR_DATA(IP3_4_2, SDSELF_B), + + PINMUX_IPSR_MSEL(IP3_7_5, SD1_CMD_B, SEL_SD1_B), + PINMUX_IPSR_DATA(IP3_7_5, SCIF_CLK), + PINMUX_IPSR_DATA(IP3_7_5, AUDIO_CLKOUT_B), + PINMUX_IPSR_MSEL(IP3_7_5, CAN_CLK_B, SEL_CANCLK_B), + PINMUX_IPSR_MSEL(IP3_7_5, SDA3_B, SEL_I2C3_B), + + PINMUX_IPSR_DATA(IP3_9_8, SD1_CLK_B), + PINMUX_IPSR_DATA(IP3_9_8, HTX0_A), + PINMUX_IPSR_DATA(IP3_9_8, TX0_A), + + PINMUX_IPSR_MSEL(IP3_12_10, SD1_DAT0_B, SEL_SD1_B), + PINMUX_IPSR_MSEL(IP3_12_10, HRX0_A, SEL_HSCIF0_A), + PINMUX_IPSR_MSEL(IP3_12_10, RX0_A, SEL_SCIF0_A), + + PINMUX_IPSR_MSEL(IP3_15_13, SD1_DAT1_B, SEL_SD1_B), + PINMUX_IPSR_MSEL(IP3_15_13, HSCK0, SEL_HSCIF0_A), + PINMUX_IPSR_DATA(IP3_15_13, SCK0), + PINMUX_IPSR_MSEL(IP3_15_13, SCL3_B, SEL_I2C3_B), + + PINMUX_IPSR_MSEL(IP3_18_16, SD1_DAT2_B, SEL_SD1_B), + PINMUX_IPSR_MSEL(IP3_18_16, HCTS0_A, SEL_HSCIF0_A), + PINMUX_IPSR_DATA(IP3_18_16, CTS0), + + PINMUX_IPSR_MSEL(IP3_20_19, SD1_DAT3_B, SEL_SD1_B), + PINMUX_IPSR_MSEL(IP3_20_19, HRTS0_A, SEL_HSCIF0_A), + PINMUX_IPSR_DATA(IP3_20_19, RTS0), + + PINMUX_IPSR_DATA(IP3_23_21, SSI_SCK4), + PINMUX_IPSR_DATA(IP3_23_21, DU0_DR0), + PINMUX_IPSR_DATA(IP3_23_21, LCDOUT0), + PINMUX_IPSR_DATA(IP3_23_21, AUDATA2), + PINMUX_IPSR_DATA(IP3_23_21, ARM_TRACEDATA_2), + PINMUX_IPSR_MSEL(IP3_23_21, SDA3_C, SEL_I2C3_C), + PINMUX_IPSR_DATA(IP3_23_21, ADICHS1), + PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN0_B, SEL_TSIF0_B), + + PINMUX_IPSR_DATA(IP3_26_24, SSI_WS4), + PINMUX_IPSR_DATA(IP3_26_24, DU0_DR1), + PINMUX_IPSR_DATA(IP3_26_24, LCDOUT1), + PINMUX_IPSR_DATA(IP3_26_24, AUDATA3), + PINMUX_IPSR_DATA(IP3_26_24, ARM_TRACEDATA_3), + PINMUX_IPSR_MSEL(IP3_26_24, SCL3_C, SEL_I2C3_C), + PINMUX_IPSR_DATA(IP3_26_24, ADICHS2), + PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC0_B, SEL_TSIF0_B), + + PINMUX_IPSR_DATA(IP3_27, DU0_DR2), + PINMUX_IPSR_DATA(IP3_27, LCDOUT2), + + PINMUX_IPSR_DATA(IP3_28, DU0_DR3), + PINMUX_IPSR_DATA(IP3_28, LCDOUT3), + + PINMUX_IPSR_DATA(IP3_29, DU0_DR4), + PINMUX_IPSR_DATA(IP3_29, LCDOUT4), + + PINMUX_IPSR_DATA(IP3_30, DU0_DR5), + PINMUX_IPSR_DATA(IP3_30, LCDOUT5), + + PINMUX_IPSR_DATA(IP3_31, DU0_DR6), + PINMUX_IPSR_DATA(IP3_31, LCDOUT6), + + /* IPSR4 */ + PINMUX_IPSR_DATA(IP4_0, DU0_DR7), + PINMUX_IPSR_DATA(IP4_0, LCDOUT7), + + PINMUX_IPSR_DATA(IP4_3_1, DU0_DG0), + PINMUX_IPSR_DATA(IP4_3_1, LCDOUT8), + PINMUX_IPSR_DATA(IP4_3_1, AUDATA4), + PINMUX_IPSR_DATA(IP4_3_1, ARM_TRACEDATA_4), + PINMUX_IPSR_DATA(IP4_3_1, TX1_D), + PINMUX_IPSR_DATA(IP4_3_1, CAN0_TX_A), + PINMUX_IPSR_DATA(IP4_3_1, ADICHS0), + + PINMUX_IPSR_DATA(IP4_6_4, DU0_DG1), + PINMUX_IPSR_DATA(IP4_6_4, LCDOUT9), + PINMUX_IPSR_DATA(IP4_6_4, AUDATA5), + PINMUX_IPSR_DATA(IP4_6_4, ARM_TRACEDATA_5), + PINMUX_IPSR_MSEL(IP4_6_4, RX1_D, SEL_SCIF1_D), + PINMUX_IPSR_MSEL(IP4_6_4, CAN0_RX_A, SEL_CAN0_A), + PINMUX_IPSR_DATA(IP4_6_4, ADIDATA), + + PINMUX_IPSR_DATA(IP4_7, DU0_DG2), + PINMUX_IPSR_DATA(IP4_7, LCDOUT10), + + PINMUX_IPSR_DATA(IP4_8, DU0_DG3), + PINMUX_IPSR_DATA(IP4_8, LCDOUT11), + + PINMUX_IPSR_DATA(IP4_10_9, DU0_DG4), + PINMUX_IPSR_DATA(IP4_10_9, LCDOUT12), + PINMUX_IPSR_MSEL(IP4_10_9, RX0_B, SEL_SCIF0_B), + + PINMUX_IPSR_DATA(IP4_12_11, DU0_DG5), + PINMUX_IPSR_DATA(IP4_12_11, LCDOUT13), + PINMUX_IPSR_DATA(IP4_12_11, TX0_B), + + PINMUX_IPSR_DATA(IP4_14_13, DU0_DG6), + PINMUX_IPSR_DATA(IP4_14_13, LCDOUT14), + PINMUX_IPSR_MSEL(IP4_14_13, RX4_A, SEL_SCIF4_A), + + PINMUX_IPSR_DATA(IP4_16_15, DU0_DG7), + PINMUX_IPSR_DATA(IP4_16_15, LCDOUT15), + PINMUX_IPSR_DATA(IP4_16_15, TX4_A), + + PINMUX_IPSR_MSEL(IP4_20_17, SSI_SCK2_B, SEL_SSI2_B), + PINMUX_DATA(VI0_R0_B_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_B), /* see sel_vi0 */ + PINMUX_DATA(VI0_R0_D_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_D), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP4_20_17, DU0_DB0), + PINMUX_IPSR_DATA(IP4_20_17, LCDOUT16), + PINMUX_IPSR_DATA(IP4_20_17, AUDATA6), + PINMUX_IPSR_DATA(IP4_20_17, ARM_TRACEDATA_6), + PINMUX_IPSR_MSEL(IP4_20_17, GPSCLK_A, SEL_GPS_A), + PINMUX_IPSR_DATA(IP4_20_17, PWM0_A), + PINMUX_IPSR_DATA(IP4_20_17, ADICLK), + PINMUX_IPSR_MSEL(IP4_20_17, TS_SDAT0_B, SEL_TSIF0_B), + + PINMUX_IPSR_DATA(IP4_24_21, AUDIO_CLKC), + PINMUX_DATA(VI0_R1_B_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_B), /* see sel_vi0 */ + PINMUX_DATA(VI0_R1_D_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_D), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP4_24_21, DU0_DB1), + PINMUX_IPSR_DATA(IP4_24_21, LCDOUT17), + PINMUX_IPSR_DATA(IP4_24_21, AUDATA7), + PINMUX_IPSR_DATA(IP4_24_21, ARM_TRACEDATA_7), + PINMUX_IPSR_MSEL(IP4_24_21, GPSIN_A, SEL_GPS_A), + PINMUX_IPSR_DATA(IP4_24_21, ADICS_SAMP), + PINMUX_IPSR_MSEL(IP4_24_21, TS_SCK0_B, SEL_TSIF0_B), + + PINMUX_DATA(VI0_R2_B_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_B), /* see sel_vi0 */ + PINMUX_DATA(VI0_R2_D_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_D), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP4_26_25, DU0_DB2), + PINMUX_IPSR_DATA(IP4_26_25, LCDOUT18), + + PINMUX_IPSR_MSEL(IP4_28_27, VI0_R3_B, SEL_VI0_B), + PINMUX_IPSR_DATA(IP4_28_27, DU0_DB3), + PINMUX_IPSR_DATA(IP4_28_27, LCDOUT19), + + PINMUX_DATA(VI0_R4_B_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_B), /* see sel_vi0 */ + PINMUX_DATA(VI0_R4_D_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_D), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP4_30_29, DU0_DB4), + PINMUX_IPSR_DATA(IP4_30_29, LCDOUT20), + + /* IPSR5 */ + PINMUX_DATA(VI0_R5_B_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_B), /* see sel_vi0 */ + PINMUX_DATA(VI0_R5_D_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_D), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP5_1_0, DU0_DB5), + PINMUX_IPSR_DATA(IP5_1_0, LCDOUT21), + + PINMUX_IPSR_MSEL(IP5_3_2, VI1_DATA10_B, SEL_VI1_B), + PINMUX_IPSR_DATA(IP5_3_2, DU0_DB6), + PINMUX_IPSR_DATA(IP5_3_2, LCDOUT22), + + PINMUX_IPSR_MSEL(IP5_5_4, VI1_DATA11_B, SEL_VI1_B), + PINMUX_IPSR_DATA(IP5_5_4, DU0_DB7), + PINMUX_IPSR_DATA(IP5_5_4, LCDOUT23), + + PINMUX_IPSR_DATA(IP5_6, DU0_DOTCLKIN), + PINMUX_IPSR_DATA(IP5_6, QSTVA_QVS), + + PINMUX_IPSR_DATA(IP5_7, DU0_DOTCLKO_UT0), + PINMUX_IPSR_DATA(IP5_7, QCLK), + + PINMUX_IPSR_DATA(IP5_9_8, DU0_DOTCLKO_UT1), + PINMUX_IPSR_DATA(IP5_9_8, QSTVB_QVE), + PINMUX_IPSR_DATA(IP5_9_8, AUDIO_CLKOUT_A), + PINMUX_IPSR_MSEL(IP5_9_8, REMOCON_C, SEL_REMOCON_C), + + PINMUX_IPSR_MSEL(IP5_11_10, SSI_WS2_B, SEL_SSI2_B), + PINMUX_IPSR_DATA(IP5_11_10, DU0_EXHSYNC_DU0_HSYNC), + PINMUX_IPSR_DATA(IP5_11_10, QSTH_QHS), + + PINMUX_IPSR_DATA(IP5_12, DU0_EXVSYNC_DU0_VSYNC), + PINMUX_IPSR_DATA(IP5_12, QSTB_QHE), + + PINMUX_IPSR_DATA(IP5_14_13, DU0_EXODDF_DU0_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP5_14_13, QCPV_QDE), + PINMUX_IPSR_MSEL(IP5_14_13, FMCLK_D, SEL_FM_D), + + PINMUX_IPSR_MSEL(IP5_17_15, SSI_SCK1_A, SEL_SSI1_A), + PINMUX_IPSR_DATA(IP5_17_15, DU0_DISP), + PINMUX_IPSR_DATA(IP5_17_15, QPOLA), + PINMUX_IPSR_DATA(IP5_17_15, AUDCK), + PINMUX_IPSR_DATA(IP5_17_15, ARM_TRACECLK), + PINMUX_IPSR_DATA(IP5_17_15, BPFCLK_D), + + PINMUX_IPSR_MSEL(IP5_20_18, SSI_WS1_A, SEL_SSI1_A), + PINMUX_IPSR_DATA(IP5_20_18, DU0_CDE), + PINMUX_IPSR_DATA(IP5_20_18, QPOLB), + PINMUX_IPSR_DATA(IP5_20_18, AUDSYNC), + PINMUX_IPSR_DATA(IP5_20_18, ARM_TRACECTL), + PINMUX_IPSR_MSEL(IP5_20_18, FMIN_D, SEL_FM_D), + + PINMUX_IPSR_MSEL(IP5_22_21, SD1_CD_B, SEL_SD1_B), + PINMUX_IPSR_DATA(IP5_22_21, SSI_SCK78), + PINMUX_IPSR_MSEL(IP5_22_21, HSPI_RX0_B, SEL_HSPI0_B), + PINMUX_IPSR_DATA(IP5_22_21, TX1_B), + + PINMUX_IPSR_MSEL(IP5_25_23, SD1_WP_B, SEL_SD1_B), + PINMUX_IPSR_DATA(IP5_25_23, SSI_WS78), + PINMUX_IPSR_MSEL(IP5_25_23, HSPI_CLK0_B, SEL_HSPI0_B), + PINMUX_IPSR_MSEL(IP5_25_23, RX1_B, SEL_SCIF1_B), + PINMUX_IPSR_MSEL(IP5_25_23, CAN_CLK_D, SEL_CANCLK_D), + + PINMUX_IPSR_DATA(IP5_28_26, SSI_SDATA8), + PINMUX_IPSR_MSEL(IP5_28_26, SSI_SCK2_A, SEL_SSI2_A), + PINMUX_IPSR_MSEL(IP5_28_26, HSPI_CS0_B, SEL_HSPI0_B), + PINMUX_IPSR_DATA(IP5_28_26, TX2_A), + PINMUX_IPSR_DATA(IP5_28_26, CAN0_TX_B), + + PINMUX_IPSR_DATA(IP5_30_29, SSI_SDATA7), + PINMUX_IPSR_DATA(IP5_30_29, HSPI_TX0_B), + PINMUX_IPSR_MSEL(IP5_30_29, RX2_A, SEL_SCIF2_A), + PINMUX_IPSR_MSEL(IP5_30_29, CAN0_RX_B, SEL_CAN0_B), + + /* IPSR6 */ + PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK6), + PINMUX_IPSR_MSEL(IP6_1_0, HSPI_RX2_A, SEL_HSPI2_A), + PINMUX_IPSR_MSEL(IP6_1_0, FMCLK_B, SEL_FM_B), + PINMUX_IPSR_DATA(IP6_1_0, CAN1_TX_B), + + PINMUX_IPSR_DATA(IP6_4_2, SSI_WS6), + PINMUX_IPSR_MSEL(IP6_4_2, HSPI_CLK2_A, SEL_HSPI2_A), + PINMUX_IPSR_DATA(IP6_4_2, BPFCLK_B), + PINMUX_IPSR_MSEL(IP6_4_2, CAN1_RX_B, SEL_CAN1_B), + + PINMUX_IPSR_DATA(IP6_6_5, SSI_SDATA6), + PINMUX_IPSR_DATA(IP6_6_5, HSPI_TX2_A), + PINMUX_IPSR_MSEL(IP6_6_5, FMIN_B, SEL_FM_B), + + PINMUX_IPSR_DATA(IP6_7, SSI_SCK5), + PINMUX_IPSR_MSEL(IP6_7, RX4_C, SEL_SCIF4_C), + + PINMUX_IPSR_DATA(IP6_8, SSI_WS5), + PINMUX_IPSR_DATA(IP6_8, TX4_C), + + PINMUX_IPSR_DATA(IP6_9, SSI_SDATA5), + PINMUX_IPSR_MSEL(IP6_9, RX0_D, SEL_SCIF0_D), + + PINMUX_IPSR_DATA(IP6_10, SSI_WS34), + PINMUX_IPSR_DATA(IP6_10, ARM_TRACEDATA_8), + + PINMUX_IPSR_DATA(IP6_12_11, SSI_SDATA4), + PINMUX_IPSR_MSEL(IP6_12_11, SSI_WS2_A, SEL_SSI2_A), + PINMUX_IPSR_DATA(IP6_12_11, ARM_TRACEDATA_9), + + PINMUX_IPSR_DATA(IP6_13, SSI_SDATA3), + PINMUX_IPSR_DATA(IP6_13, ARM_TRACEDATA_10), + + PINMUX_IPSR_DATA(IP6_15_14, SSI_SCK012), + PINMUX_IPSR_DATA(IP6_15_14, ARM_TRACEDATA_11), + PINMUX_IPSR_DATA(IP6_15_14, TX0_D), + + PINMUX_IPSR_DATA(IP6_16, SSI_WS012), + PINMUX_IPSR_DATA(IP6_16, ARM_TRACEDATA_12), + + PINMUX_IPSR_DATA(IP6_18_17, SSI_SDATA2), + PINMUX_IPSR_MSEL(IP6_18_17, HSPI_CS2_A, SEL_HSPI2_A), + PINMUX_IPSR_DATA(IP6_18_17, ARM_TRACEDATA_13), + PINMUX_IPSR_MSEL(IP6_18_17, SDA1_A, SEL_I2C1_A), + + PINMUX_IPSR_DATA(IP6_20_19, SSI_SDATA1), + PINMUX_IPSR_DATA(IP6_20_19, ARM_TRACEDATA_14), + PINMUX_IPSR_MSEL(IP6_20_19, SCL1_A, SEL_I2C1_A), + PINMUX_IPSR_MSEL(IP6_20_19, SCK2_A, SEL_SCIF2_A), + + PINMUX_IPSR_DATA(IP6_21, SSI_SDATA0), + PINMUX_IPSR_DATA(IP6_21, ARM_TRACEDATA_15), + + PINMUX_IPSR_DATA(IP6_23_22, SD0_CLK), + PINMUX_IPSR_DATA(IP6_23_22, SUB_TDO), + + PINMUX_IPSR_DATA(IP6_25_24, SD0_CMD), + PINMUX_IPSR_DATA(IP6_25_24, SUB_TRST), + + PINMUX_IPSR_DATA(IP6_27_26, SD0_DAT0), + PINMUX_IPSR_DATA(IP6_27_26, SUB_TMS), + + PINMUX_IPSR_DATA(IP6_29_28, SD0_DAT1), + PINMUX_IPSR_DATA(IP6_29_28, SUB_TCK), + + PINMUX_IPSR_DATA(IP6_31_30, SD0_DAT2), + PINMUX_IPSR_DATA(IP6_31_30, SUB_TDI), + + /* IPSR7 */ + PINMUX_IPSR_DATA(IP7_1_0, SD0_DAT3), + PINMUX_IPSR_MSEL(IP7_1_0, IRQ1_B, SEL_IRQ1_B), + + PINMUX_IPSR_DATA(IP7_3_2, SD0_CD), + PINMUX_IPSR_DATA(IP7_3_2, TX5_A), + + PINMUX_IPSR_DATA(IP7_5_4, SD0_WP), + PINMUX_IPSR_MSEL(IP7_5_4, RX5_A, SEL_SCIF5_A), + + PINMUX_IPSR_DATA(IP7_8_6, VI1_CLKENB), + PINMUX_IPSR_MSEL(IP7_8_6, HSPI_CLK0_A, SEL_HSPI0_A), + PINMUX_IPSR_DATA(IP7_8_6, HTX1_A), + PINMUX_IPSR_MSEL(IP7_8_6, RTS1_C, SEL_SCIF1_C), + + PINMUX_IPSR_DATA(IP7_11_9, VI1_FIELD), + PINMUX_IPSR_MSEL(IP7_11_9, HSPI_CS0_A, SEL_HSPI0_A), + PINMUX_IPSR_MSEL(IP7_11_9, HRX1_A, SEL_HSCIF1_A), + PINMUX_IPSR_MSEL(IP7_11_9, SCK1_C, SEL_SCIF1_C), + + PINMUX_IPSR_DATA(IP7_14_12, VI1_HSYNC), + PINMUX_IPSR_MSEL(IP7_14_12, HSPI_RX0_A, SEL_HSPI0_A), + PINMUX_IPSR_MSEL(IP7_14_12, HRTS1_A, SEL_HSCIF1_A), + PINMUX_IPSR_MSEL(IP7_14_12, FMCLK_A, SEL_FM_A), + PINMUX_IPSR_MSEL(IP7_14_12, RX1_C, SEL_SCIF1_C), + + PINMUX_IPSR_DATA(IP7_17_15, VI1_VSYNC), + PINMUX_IPSR_DATA(IP7_17_15, HSPI_TX0), + PINMUX_IPSR_MSEL(IP7_17_15, HCTS1_A, SEL_HSCIF1_A), + PINMUX_IPSR_DATA(IP7_17_15, BPFCLK_A), + PINMUX_IPSR_DATA(IP7_17_15, TX1_C), + + PINMUX_IPSR_DATA(IP7_20_18, TCLK0), + PINMUX_IPSR_MSEL(IP7_20_18, HSCK1_A, SEL_HSCIF1_A), + PINMUX_IPSR_MSEL(IP7_20_18, FMIN_A, SEL_FM_A), + PINMUX_IPSR_MSEL(IP7_20_18, IRQ2_C, SEL_IRQ2_C), + PINMUX_IPSR_MSEL(IP7_20_18, CTS1_C, SEL_SCIF1_C), + PINMUX_IPSR_DATA(IP7_20_18, SPEEDIN), + + PINMUX_IPSR_DATA(IP7_21, VI0_CLK), + PINMUX_IPSR_MSEL(IP7_21, CAN_CLK_A, SEL_CANCLK_A), + + PINMUX_IPSR_DATA(IP7_24_22, VI0_CLKENB), + PINMUX_IPSR_MSEL(IP7_24_22, SD2_DAT2_B, SEL_SD2_B), + PINMUX_IPSR_DATA(IP7_24_22, VI1_DATA0), + PINMUX_IPSR_DATA(IP7_24_22, DU1_DG6), + PINMUX_IPSR_MSEL(IP7_24_22, HSPI_RX1_A, SEL_HSPI1_A), + PINMUX_IPSR_MSEL(IP7_24_22, RX4_B, SEL_SCIF4_B), + + PINMUX_IPSR_DATA(IP7_28_25, VI0_FIELD), + PINMUX_IPSR_MSEL(IP7_28_25, SD2_DAT3_B, SEL_SD2_B), + PINMUX_DATA(VI0_R3_C_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_C), /* see sel_vi0 */ + PINMUX_DATA(VI0_R3_D_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_D), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP7_28_25, VI1_DATA1), + PINMUX_IPSR_DATA(IP7_28_25, DU1_DG7), + PINMUX_IPSR_MSEL(IP7_28_25, HSPI_CLK1_A, SEL_HSPI1_A), + PINMUX_IPSR_DATA(IP7_28_25, TX4_B), + + PINMUX_IPSR_DATA(IP7_31_29, VI0_HSYNC), + PINMUX_IPSR_MSEL(IP7_31_29, SD2_CD_B, SEL_SD2_B), + PINMUX_IPSR_DATA(IP7_31_29, VI1_DATA2), + PINMUX_IPSR_DATA(IP7_31_29, DU1_DR2), + PINMUX_IPSR_MSEL(IP7_31_29, HSPI_CS1_A, SEL_HSPI1_A), + PINMUX_IPSR_MSEL(IP7_31_29, RX3_B, SEL_SCIF3_B), + + /* IPSR8 */ + PINMUX_IPSR_DATA(IP8_2_0, VI0_VSYNC), + PINMUX_IPSR_MSEL(IP8_2_0, SD2_WP_B, SEL_SD2_B), + PINMUX_IPSR_DATA(IP8_2_0, VI1_DATA3), + PINMUX_IPSR_DATA(IP8_2_0, DU1_DR3), + PINMUX_IPSR_DATA(IP8_2_0, HSPI_TX1_A), + PINMUX_IPSR_DATA(IP8_2_0, TX3_B), + + PINMUX_IPSR_DATA(IP8_5_3, VI0_DATA0_VI0_B0), + PINMUX_IPSR_DATA(IP8_5_3, DU1_DG2), + PINMUX_IPSR_MSEL(IP8_5_3, IRQ2_B, SEL_IRQ2_B), + PINMUX_IPSR_MSEL(IP8_5_3, RX3_D, SEL_SCIF3_D), + + PINMUX_IPSR_DATA(IP8_8_6, VI0_DATA1_VI0_B1), + PINMUX_IPSR_DATA(IP8_8_6, DU1_DG3), + PINMUX_IPSR_MSEL(IP8_8_6, IRQ3_B, SEL_IRQ3_B), + PINMUX_IPSR_DATA(IP8_8_6, TX3_D), + + PINMUX_IPSR_DATA(IP8_10_9, VI0_DATA2_VI0_B2), + PINMUX_IPSR_DATA(IP8_10_9, DU1_DG4), + PINMUX_IPSR_MSEL(IP8_10_9, RX0_C, SEL_SCIF0_C), + + PINMUX_IPSR_DATA(IP8_13_11, VI0_DATA3_VI0_B3), + PINMUX_IPSR_DATA(IP8_13_11, DU1_DG5), + PINMUX_IPSR_DATA(IP8_13_11, TX1_A), + PINMUX_IPSR_DATA(IP8_13_11, TX0_C), + + PINMUX_IPSR_DATA(IP8_15_14, VI0_DATA4_VI0_B4), + PINMUX_IPSR_DATA(IP8_15_14, DU1_DB2), + PINMUX_IPSR_MSEL(IP8_15_14, RX1_A, SEL_SCIF1_A), + + PINMUX_IPSR_DATA(IP8_18_16, VI0_DATA5_VI0_B5), + PINMUX_IPSR_DATA(IP8_18_16, DU1_DB3), + PINMUX_IPSR_MSEL(IP8_18_16, SCK1_A, SEL_SCIF1_A), + PINMUX_IPSR_DATA(IP8_18_16, PWM4), + PINMUX_IPSR_MSEL(IP8_18_16, HSCK1_B, SEL_HSCIF1_B), + + PINMUX_IPSR_DATA(IP8_21_19, VI0_DATA6_VI0_G0), + PINMUX_IPSR_DATA(IP8_21_19, DU1_DB4), + PINMUX_IPSR_MSEL(IP8_21_19, CTS1_A, SEL_SCIF1_A), + PINMUX_IPSR_DATA(IP8_21_19, PWM5), + + PINMUX_IPSR_DATA(IP8_23_22, VI0_DATA7_VI0_G1), + PINMUX_IPSR_DATA(IP8_23_22, DU1_DB5), + PINMUX_IPSR_MSEL(IP8_23_22, RTS1_A, SEL_SCIF1_A), + + PINMUX_IPSR_DATA(IP8_26_24, VI0_G2), + PINMUX_IPSR_DATA(IP8_26_24, SD2_CLK_B), + PINMUX_IPSR_DATA(IP8_26_24, VI1_DATA4), + PINMUX_IPSR_DATA(IP8_26_24, DU1_DR4), + PINMUX_IPSR_DATA(IP8_26_24, HTX1_B), + + PINMUX_IPSR_DATA(IP8_29_27, VI0_G3), + PINMUX_IPSR_MSEL(IP8_29_27, SD2_CMD_B, SEL_SD2_B), + PINMUX_IPSR_DATA(IP8_29_27, VI1_DATA5), + PINMUX_IPSR_DATA(IP8_29_27, DU1_DR5), + PINMUX_IPSR_MSEL(IP8_29_27, HRX1_B, SEL_HSCIF1_B), + + /* IPSR9 */ + PINMUX_IPSR_DATA(IP9_2_0, VI0_G4), + PINMUX_IPSR_MSEL(IP9_2_0, SD2_DAT0_B, SEL_SD2_B), + PINMUX_IPSR_DATA(IP9_2_0, VI1_DATA6), + PINMUX_IPSR_DATA(IP9_2_0, DU1_DR6), + PINMUX_IPSR_MSEL(IP9_2_0, HRTS1_B, SEL_HSCIF1_B), + + PINMUX_IPSR_DATA(IP9_5_3, VI0_G5), + PINMUX_IPSR_MSEL(IP9_5_3, SD2_DAT1_B, SEL_SD2_B), + PINMUX_IPSR_DATA(IP9_5_3, VI1_DATA7), + PINMUX_IPSR_DATA(IP9_5_3, DU1_DR7), + PINMUX_IPSR_MSEL(IP9_5_3, HCTS1_B, SEL_HSCIF1_B), + + PINMUX_DATA(VI0_R0_A_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_A), /* see sel_vi0 */ + PINMUX_DATA(VI0_R0_C_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_C), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP9_8_6, VI1_CLK), + PINMUX_IPSR_DATA(IP9_8_6, ETH_REF_CLK), + PINMUX_IPSR_DATA(IP9_8_6, DU1_DOTCLKIN), + + PINMUX_DATA(VI0_R1_A_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_A), /* see sel_vi0 */ + PINMUX_DATA(VI0_R1_C_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_C), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP9_11_9, VI1_DATA8), + PINMUX_IPSR_DATA(IP9_11_9, DU1_DB6), + PINMUX_IPSR_DATA(IP9_11_9, ETH_TXD0), + PINMUX_IPSR_DATA(IP9_11_9, PWM2), + PINMUX_IPSR_DATA(IP9_11_9, TCLK1), + + PINMUX_DATA(VI0_R2_A_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_A), /* see sel_vi0 */ + PINMUX_DATA(VI0_R2_C_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_C), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP9_14_12, VI1_DATA9), + PINMUX_IPSR_DATA(IP9_14_12, DU1_DB7), + PINMUX_IPSR_DATA(IP9_14_12, ETH_TXD1), + PINMUX_IPSR_DATA(IP9_14_12, PWM3), + + PINMUX_IPSR_MSEL(IP9_17_15, VI0_R3_A, SEL_VI0_A), + PINMUX_IPSR_DATA(IP9_17_15, ETH_CRS_DV), + PINMUX_IPSR_DATA(IP9_17_15, IECLK), + PINMUX_IPSR_MSEL(IP9_17_15, SCK2_C, SEL_SCIF2_C), + + PINMUX_DATA(VI0_R4_A_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_A), /* see sel_vi0 */ + PINMUX_DATA(VI0_R3_C_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_C), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP9_20_18, ETH_TX_EN), + PINMUX_IPSR_DATA(IP9_20_18, IETX), + PINMUX_IPSR_DATA(IP9_20_18, TX2_C), + + PINMUX_DATA(VI0_R5_A_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_A), /* see sel_vi0 */ + PINMUX_DATA(VI0_R5_C_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_C), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP9_23_21, ETH_RX_ER), + PINMUX_IPSR_MSEL(IP9_23_21, FMCLK_C, SEL_FM_C), + PINMUX_IPSR_DATA(IP9_23_21, IERX), + PINMUX_IPSR_MSEL(IP9_23_21, RX2_C, SEL_SCIF2_C), + + PINMUX_IPSR_MSEL(IP9_26_24, VI1_DATA10_A, SEL_VI1_A), + PINMUX_IPSR_DATA(IP9_26_24, DU1_DOTCLKOUT), + PINMUX_IPSR_DATA(IP9_26_24, ETH_RXD0), + PINMUX_IPSR_DATA(IP9_26_24, BPFCLK_C), + PINMUX_IPSR_DATA(IP9_26_24, TX2_D), + PINMUX_IPSR_MSEL(IP9_26_24, SDA2_C, SEL_I2C2_C), + + PINMUX_IPSR_MSEL(IP9_29_27, VI1_DATA11_A, SEL_VI1_A), + PINMUX_IPSR_DATA(IP9_29_27, DU1_EXHSYNC_DU1_HSYNC), + PINMUX_IPSR_DATA(IP9_29_27, ETH_RXD1), + PINMUX_IPSR_MSEL(IP9_29_27, FMIN_C, SEL_FM_C), + PINMUX_IPSR_MSEL(IP9_29_27, RX2_D, SEL_SCIF2_D), + PINMUX_IPSR_MSEL(IP9_29_27, SCL2_C, SEL_I2C2_C), + + /* IPSR10 */ + PINMUX_IPSR_DATA(IP10_2_0, SD2_CLK_A), + PINMUX_IPSR_DATA(IP10_2_0, DU1_EXVSYNC_DU1_VSYNC), + PINMUX_IPSR_DATA(IP10_2_0, ATARD1), + PINMUX_IPSR_DATA(IP10_2_0, ETH_MDC), + PINMUX_IPSR_MSEL(IP10_2_0, SDA1_B, SEL_I2C1_B), + + PINMUX_IPSR_MSEL(IP10_5_3, SD2_CMD_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_5_3, DU1_EXODDF_DU1_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP10_5_3, ATAWR1), + PINMUX_IPSR_DATA(IP10_5_3, ETH_MDIO), + PINMUX_IPSR_MSEL(IP10_5_3, SCL1_B, SEL_I2C1_B), + + PINMUX_IPSR_MSEL(IP10_8_6, SD2_DAT0_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_8_6, DU1_DISP), + PINMUX_IPSR_DATA(IP10_8_6, ATACS01), + PINMUX_IPSR_MSEL(IP10_8_6, DREQ1_B, SEL_DREQ1_B), + PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK), + PINMUX_IPSR_MSEL(IP10_8_6, CAN1_RX_A, SEL_CAN1_A), + + PINMUX_IPSR_MSEL(IP10_12_9, SD2_DAT1_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_12_9, DU1_CDE), + PINMUX_IPSR_DATA(IP10_12_9, ATACS11), + PINMUX_IPSR_DATA(IP10_12_9, DACK1_B), + PINMUX_IPSR_DATA(IP10_12_9, ETH_MAGIC), + PINMUX_IPSR_DATA(IP10_12_9, CAN1_TX_A), + PINMUX_IPSR_DATA(IP10_12_9, PWM6), + + PINMUX_IPSR_MSEL(IP10_15_13, SD2_DAT2_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_15_13, VI1_DATA12), + PINMUX_IPSR_MSEL(IP10_15_13, DREQ2_B, SEL_DREQ2_B), + PINMUX_IPSR_DATA(IP10_15_13, ATADIR1), + PINMUX_IPSR_MSEL(IP10_15_13, HSPI_CLK2_B, SEL_HSPI2_B), + PINMUX_IPSR_MSEL(IP10_15_13, GPSCLK_B, SEL_GPS_B), + + PINMUX_IPSR_MSEL(IP10_18_16, SD2_DAT3_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_18_16, VI1_DATA13), + PINMUX_IPSR_DATA(IP10_18_16, DACK2_B), + PINMUX_IPSR_DATA(IP10_18_16, ATAG1), + PINMUX_IPSR_MSEL(IP10_18_16, HSPI_CS2_B, SEL_HSPI2_B), + PINMUX_IPSR_MSEL(IP10_18_16, GPSIN_B, SEL_GPS_B), + + PINMUX_IPSR_MSEL(IP10_21_19, SD2_CD_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_21_19, VI1_DATA14), + PINMUX_IPSR_MSEL(IP10_21_19, EX_WAIT1_B, SEL_WAIT1_B), + PINMUX_IPSR_MSEL(IP10_21_19, DREQ0_B, SEL_DREQ0_B), + PINMUX_IPSR_MSEL(IP10_21_19, HSPI_RX2_B, SEL_HSPI2_B), + PINMUX_IPSR_MSEL(IP10_21_19, REMOCON_A, SEL_REMOCON_A), + + PINMUX_IPSR_MSEL(IP10_24_22, SD2_WP_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_24_22, VI1_DATA15), + PINMUX_IPSR_MSEL(IP10_24_22, EX_WAIT2_B, SEL_WAIT2_B), + PINMUX_IPSR_DATA(IP10_24_22, DACK0_B), + PINMUX_IPSR_DATA(IP10_24_22, HSPI_TX2_B), + PINMUX_IPSR_MSEL(IP10_24_22, CAN_CLK_C, SEL_CANCLK_C), +}; + +static struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), +}; + +/* Pin numbers for pins without a corresponding GPIO port number are computed + * from the row and column numbers with a 1000 offset to avoid collisions with + * GPIO port numbers. + */ +#define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1) + +/* - macro */ +#define SH_PFC_PINS(name, args...) \ + static const unsigned int name ##_pins[] = { args } +#define SH_PFC_MUX1(name, arg1) \ + static const unsigned int name ##_mux[] = { arg1##_MARK } +#define SH_PFC_MUX2(name, arg1, arg2) \ + static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, } +#define SH_PFC_MUX3(name, arg1, arg2, arg3) \ + static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \ + arg3##_MARK } +#define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4) \ + static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \ + arg3##_MARK, arg4##_MARK } +#define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \ + static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \ + arg3##_MARK, arg4##_MARK, \ + arg5##_MARK, arg6##_MARK, \ + arg7##_MARK, arg8##_MARK, } + +/* - Ether ------------------------------------------------------------------ */ +SH_PFC_PINS(ether_rmii, RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 9), + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), + RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 14), + RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17)); +static const unsigned int ether_rmii_mux[] = { + ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, + ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK, + ETH_MDIO_MARK, ETH_MDC_MARK, +}; +SH_PFC_PINS(ether_link, RCAR_GP_PIN(4, 19)); +SH_PFC_MUX1(ether_link, ETH_LINK); +SH_PFC_PINS(ether_magic, RCAR_GP_PIN(4, 20)); +SH_PFC_MUX1(ether_magic, ETH_MAGIC); + +/* - SCIF macro ------------------------------------------------------------- */ +#define SCIF_PFC_PIN(name, args...) SH_PFC_PINS(name, args) +#define SCIF_PFC_DAT(name, tx, rx) SH_PFC_MUX2(name, tx, rx) +#define SCIF_PFC_CTR(name, cts, rts) SH_PFC_MUX2(name, cts, rts) +#define SCIF_PFC_CLK(name, sck) SH_PFC_MUX1(name, sck) + +/* - HSCIF0 ----------------------------------------------------------------- */ +SCIF_PFC_PIN(hscif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18)); +SCIF_PFC_DAT(hscif0_data_a, HTX0_A, HRX0_A); +SCIF_PFC_PIN(hscif0_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30)); +SCIF_PFC_DAT(hscif0_data_b, HTX0_B, HRX0_B); +SCIF_PFC_PIN(hscif0_ctrl_a, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); +SCIF_PFC_CTR(hscif0_ctrl_a, HCTS0_A, HRTS0_A); +SCIF_PFC_PIN(hscif0_ctrl_b, RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 28)); +SCIF_PFC_CTR(hscif0_ctrl_b, HCTS0_B, HRTS0_B); +SCIF_PFC_PIN(hscif0_clk, RCAR_GP_PIN(1, 19)); +SCIF_PFC_CLK(hscif0_clk, HSCK0); + +/* - HSCIF1 ----------------------------------------------------------------- */ +SCIF_PFC_PIN(hscif1_data_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20)); +SCIF_PFC_DAT(hscif1_data_a, HTX1_A, HRX1_A); +SCIF_PFC_PIN(hscif1_data_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6)); +SCIF_PFC_DAT(hscif1_data_b, HTX1_B, HRX1_B); +SCIF_PFC_PIN(hscif1_ctrl_a, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21)); +SCIF_PFC_CTR(hscif1_ctrl_a, HCTS1_A, HRTS1_A); +SCIF_PFC_PIN(hscif1_ctrl_b, RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7)); +SCIF_PFC_CTR(hscif1_ctrl_b, HCTS1_B, HRTS1_B); +SCIF_PFC_PIN(hscif1_clk_a, RCAR_GP_PIN(3, 23)); +SCIF_PFC_CLK(hscif1_clk_a, HSCK1_A); +SCIF_PFC_PIN(hscif1_clk_b, RCAR_GP_PIN(4, 2)); +SCIF_PFC_CLK(hscif1_clk_b, HSCK1_B); + +/* - HSPI macro --------------------------------------------------------------*/ +#define HSPI_PFC_PIN(name, args...) SH_PFC_PINS(name, args) +#define HSPI_PFC_DAT(name, clk, cs, rx, tx) SH_PFC_MUX4(name, clk, cs, rx, tx) + +/* - HSPI0 -------------------------------------------------------------------*/ +HSPI_PFC_PIN(hspi0_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), + RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22)); +HSPI_PFC_DAT(hspi0_a, HSPI_CLK0_A, HSPI_CS0_A, + HSPI_RX0_A, HSPI_TX0); + +HSPI_PFC_PIN(hspi0_b, RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), + RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 27)); +HSPI_PFC_DAT(hspi0_b, HSPI_CLK0_B, HSPI_CS0_B, + HSPI_RX0_B, HSPI_TX0_B); + +/* - HSPI1 -------------------------------------------------------------------*/ +HSPI_PFC_PIN(hspi1_a, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 28)); +HSPI_PFC_DAT(hspi1_a, HSPI_CLK1_A, HSPI_CS1_A, + HSPI_RX1_A, HSPI_TX1_A); + +HSPI_PFC_PIN(hspi1_b, RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 26), + PIN_NUMBER(20, 1), PIN_NUMBER(25, 2)); +HSPI_PFC_DAT(hspi1_b, HSPI_CLK1_B, HSPI_CS1_B, + HSPI_RX1_B, HSPI_TX1_B); + +/* - HSPI2 -------------------------------------------------------------------*/ +HSPI_PFC_PIN(hspi2_a, RCAR_GP_PIN(2, 29), RCAR_GP_PIN(3, 8), + RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 30)); +HSPI_PFC_DAT(hspi2_a, HSPI_CLK2_A, HSPI_CS2_A, + HSPI_RX2_A, HSPI_TX2_A); + +HSPI_PFC_PIN(hspi2_b, RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22), + RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24)); +HSPI_PFC_DAT(hspi2_b, HSPI_CLK2_B, HSPI_CS2_B, + HSPI_RX2_B, HSPI_TX2_B); + +/* - I2C macro ------------------------------------------------------------- */ +#define I2C_PFC_PIN(name, args...) SH_PFC_PINS(name, args) +#define I2C_PFC_MUX(name, sda, scl) SH_PFC_MUX2(name, sda, scl) + +/* - I2C1 ------------------------------------------------------------------ */ +I2C_PFC_PIN(i2c1_a, RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9)); +I2C_PFC_MUX(i2c1_a, SDA1_A, SCL1_A); +I2C_PFC_PIN(i2c1_b, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); +I2C_PFC_MUX(i2c1_b, SDA1_B, SCL1_B); + +/* - I2C2 ------------------------------------------------------------------ */ +I2C_PFC_PIN(i2c2_a, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3)); +I2C_PFC_MUX(i2c2_a, SDA2_A, SCL2_A); +I2C_PFC_PIN(i2c2_b, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4)); +I2C_PFC_MUX(i2c2_b, SDA2_B, SCL2_B); +I2C_PFC_PIN(i2c2_c, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16)); +I2C_PFC_MUX(i2c2_c, SDA2_C, SCL2_C); + +/* - I2C3 ------------------------------------------------------------------ */ +I2C_PFC_PIN(i2c3_a, RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15)); +I2C_PFC_MUX(i2c3_a, SDA3_A, SCL3_A); +I2C_PFC_PIN(i2c3_b, RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 19)); +I2C_PFC_MUX(i2c3_b, SDA3_B, SCL3_B); +I2C_PFC_PIN(i2c3_c, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23)); +I2C_PFC_MUX(i2c3_c, SDA3_C, SCL3_C); + +/* - MMC macro -------------------------------------------------------------- */ +#define MMC_PFC_PINS(name, args...) SH_PFC_PINS(name, args) +#define MMC_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd) +#define MMC_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0) +#define MMC_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3) +#define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \ + SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7) + +/* - MMC -------------------------------------------------------------------- */ +MMC_PFC_PINS(mmc_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); +MMC_PFC_CTRL(mmc_ctrl, MMC_CLK, MMC_CMD); +MMC_PFC_PINS(mmc_data1, RCAR_GP_PIN(1, 7)); +MMC_PFC_DAT1(mmc_data1, MMC_D0); +MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6)); +MMC_PFC_DAT4(mmc_data4, MMC_D0, MMC_D1, + MMC_D2, MMC_D3); +MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0), + RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31)); +MMC_PFC_DAT8(mmc_data8, MMC_D0, MMC_D1, + MMC_D2, MMC_D3, + MMC_D4, MMC_D5, + MMC_D6, MMC_D7); + +/* - SCIF CLOCK ------------------------------------------------------------- */ +SCIF_PFC_PIN(scif_clk, RCAR_GP_PIN(1, 16)); +SCIF_PFC_CLK(scif_clk, SCIF_CLK); + +/* - SCIF0 ------------------------------------------------------------------ */ +SCIF_PFC_PIN(scif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18)); +SCIF_PFC_DAT(scif0_data_a, TX0_A, RX0_A); +SCIF_PFC_PIN(scif0_data_b, RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2)); +SCIF_PFC_DAT(scif0_data_b, TX0_B, RX0_B); +SCIF_PFC_PIN(scif0_data_c, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(3, 31)); +SCIF_PFC_DAT(scif0_data_c, TX0_C, RX0_C); +SCIF_PFC_PIN(scif0_data_d, RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 1)); +SCIF_PFC_DAT(scif0_data_d, TX0_D, RX0_D); +SCIF_PFC_PIN(scif0_ctrl, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); +SCIF_PFC_CTR(scif0_ctrl, CTS0, RTS0); +SCIF_PFC_PIN(scif0_clk, RCAR_GP_PIN(1, 19)); +SCIF_PFC_CLK(scif0_clk, SCK0); + +/* - SCIF1 ------------------------------------------------------------------ */ +SCIF_PFC_PIN(scif1_data_a, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1)); +SCIF_PFC_DAT(scif1_data_a, TX1_A, RX1_A); +SCIF_PFC_PIN(scif1_data_b, RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25)); +SCIF_PFC_DAT(scif1_data_b, TX1_B, RX1_B); +SCIF_PFC_PIN(scif1_data_c, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21)); +SCIF_PFC_DAT(scif1_data_c, TX1_C, RX1_C); +SCIF_PFC_PIN(scif1_data_d, RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31)); +SCIF_PFC_DAT(scif1_data_d, TX1_D, RX1_D); +SCIF_PFC_PIN(scif1_ctrl_a, RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4)); +SCIF_PFC_CTR(scif1_ctrl_a, CTS1_A, RTS1_A); +SCIF_PFC_PIN(scif1_ctrl_c, RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 19)); +SCIF_PFC_CTR(scif1_ctrl_c, CTS1_C, RTS1_C); +SCIF_PFC_PIN(scif1_clk_a, RCAR_GP_PIN(4, 2)); +SCIF_PFC_CLK(scif1_clk_a, SCK1_A); +SCIF_PFC_PIN(scif1_clk_c, RCAR_GP_PIN(3, 20)); +SCIF_PFC_CLK(scif1_clk_c, SCK1_C); + +/* - SCIF2 ------------------------------------------------------------------ */ +SCIF_PFC_PIN(scif2_data_a, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27)); +SCIF_PFC_DAT(scif2_data_a, TX2_A, RX2_A); +SCIF_PFC_PIN(scif2_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 28)); +SCIF_PFC_DAT(scif2_data_b, TX2_B, RX2_B); +SCIF_PFC_PIN(scif2_data_c, RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14)); +SCIF_PFC_DAT(scif2_data_c, TX2_C, RX2_C); +SCIF_PFC_PIN(scif2_data_d, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16)); +SCIF_PFC_DAT(scif2_data_d, TX2_D, RX2_D); +SCIF_PFC_PIN(scif2_data_e, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4)); +SCIF_PFC_DAT(scif2_data_e, TX2_E, RX2_E); +SCIF_PFC_PIN(scif2_clk_a, RCAR_GP_PIN(3, 9)); +SCIF_PFC_CLK(scif2_clk_a, SCK2_A); +SCIF_PFC_PIN(scif2_clk_b, PIN_NUMBER(3, 20)); +SCIF_PFC_CLK(scif2_clk_b, SCK2_B); +SCIF_PFC_PIN(scif2_clk_c, RCAR_GP_PIN(4, 12)); +SCIF_PFC_CLK(scif2_clk_c, SCK2_C); + +/* - SCIF3 ------------------------------------------------------------------ */ +SCIF_PFC_PIN(scif3_data_a, RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9)); +SCIF_PFC_DAT(scif3_data_a, TX3_A, RX3_A); +SCIF_PFC_PIN(scif3_data_b, RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27)); +SCIF_PFC_DAT(scif3_data_b, TX3_B, RX3_B); +SCIF_PFC_PIN(scif3_data_c, RCAR_GP_PIN(1, 3), RCAR_GP_PIN(0, 31)); +SCIF_PFC_DAT(scif3_data_c, TX3_C, RX3_C); +SCIF_PFC_PIN(scif3_data_d, RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 29)); +SCIF_PFC_DAT(scif3_data_d, TX3_D, RX3_D); + +/* - SCIF4 ------------------------------------------------------------------ */ +SCIF_PFC_PIN(scif4_data_a, RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4)); +SCIF_PFC_DAT(scif4_data_a, TX4_A, RX4_A); +SCIF_PFC_PIN(scif4_data_b, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 25)); +SCIF_PFC_DAT(scif4_data_b, TX4_B, RX4_B); +SCIF_PFC_PIN(scif4_data_c, RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 31)); +SCIF_PFC_DAT(scif4_data_c, TX4_C, RX4_C); + +/* - SCIF5 ------------------------------------------------------------------ */ +SCIF_PFC_PIN(scif5_data_a, RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18)); +SCIF_PFC_DAT(scif5_data_a, TX5_A, RX5_A); +SCIF_PFC_PIN(scif5_data_b, RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14)); +SCIF_PFC_DAT(scif5_data_b, TX5_B, RX5_B); + +/* - SDHI macro ------------------------------------------------------------- */ +#define SDHI_PFC_PINS(name, args...) SH_PFC_PINS(name, args) +#define SDHI_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0) +#define SDHI_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3) +#define SDHI_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd) +#define SDHI_PFC_CDPN(name, cd) SH_PFC_MUX1(name, cd) +#define SDHI_PFC_WPPN(name, wp) SH_PFC_MUX1(name, wp) + +/* - SDHI0 ------------------------------------------------------------------ */ +SDHI_PFC_PINS(sdhi0_cd, RCAR_GP_PIN(3, 17)); +SDHI_PFC_CDPN(sdhi0_cd, SD0_CD); +SDHI_PFC_PINS(sdhi0_ctrl, RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12)); +SDHI_PFC_CTRL(sdhi0_ctrl, SD0_CLK, SD0_CMD); +SDHI_PFC_PINS(sdhi0_data1, RCAR_GP_PIN(3, 13)); +SDHI_PFC_DAT1(sdhi0_data1, SD0_DAT0); +SDHI_PFC_PINS(sdhi0_data4, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16)); +SDHI_PFC_DAT4(sdhi0_data4, SD0_DAT0, SD0_DAT1, + SD0_DAT2, SD0_DAT3); +SDHI_PFC_PINS(sdhi0_wp, RCAR_GP_PIN(3, 18)); +SDHI_PFC_WPPN(sdhi0_wp, SD0_WP); + +/* - SDHI1 ------------------------------------------------------------------ */ +SDHI_PFC_PINS(sdhi1_cd_a, RCAR_GP_PIN(0, 30)); +SDHI_PFC_CDPN(sdhi1_cd_a, SD1_CD_A); +SDHI_PFC_PINS(sdhi1_cd_b, RCAR_GP_PIN(2, 24)); +SDHI_PFC_CDPN(sdhi1_cd_b, SD1_CD_B); +SDHI_PFC_PINS(sdhi1_ctrl_a, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); +SDHI_PFC_CTRL(sdhi1_ctrl_a, SD1_CLK_A, SD1_CMD_A); +SDHI_PFC_PINS(sdhi1_ctrl_b, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16)); +SDHI_PFC_CTRL(sdhi1_ctrl_b, SD1_CLK_B, SD1_CMD_B); +SDHI_PFC_PINS(sdhi1_data1_a, RCAR_GP_PIN(1, 7)); +SDHI_PFC_DAT1(sdhi1_data1_a, SD1_DAT0_A); +SDHI_PFC_PINS(sdhi1_data1_b, RCAR_GP_PIN(1, 18)); +SDHI_PFC_DAT1(sdhi1_data1_b, SD1_DAT0_B); +SDHI_PFC_PINS(sdhi1_data4_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6)); +SDHI_PFC_DAT4(sdhi1_data4_a, SD1_DAT0_A, SD1_DAT1_A, + SD1_DAT2_A, SD1_DAT3_A); +SDHI_PFC_PINS(sdhi1_data4_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); +SDHI_PFC_DAT4(sdhi1_data4_b, SD1_DAT0_B, SD1_DAT1_B, + SD1_DAT2_B, SD1_DAT3_B); +SDHI_PFC_PINS(sdhi1_wp_a, RCAR_GP_PIN(0, 31)); +SDHI_PFC_WPPN(sdhi1_wp_a, SD1_WP_A); +SDHI_PFC_PINS(sdhi1_wp_b, RCAR_GP_PIN(2, 25)); +SDHI_PFC_WPPN(sdhi1_wp_b, SD1_WP_B); + +/* - SDH2 ------------------------------------------------------------------- */ +SDHI_PFC_PINS(sdhi2_cd_a, RCAR_GP_PIN(4, 23)); +SDHI_PFC_CDPN(sdhi2_cd_a, SD2_CD_A); +SDHI_PFC_PINS(sdhi2_cd_b, RCAR_GP_PIN(3, 27)); +SDHI_PFC_CDPN(sdhi2_cd_b, SD2_CD_B); +SDHI_PFC_PINS(sdhi2_ctrl_a, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); +SDHI_PFC_CTRL(sdhi2_ctrl_a, SD2_CLK_A, SD2_CMD_A); +SDHI_PFC_PINS(sdhi2_ctrl_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6)); +SDHI_PFC_CTRL(sdhi2_ctrl_b, SD2_CLK_B, SD2_CMD_B); +SDHI_PFC_PINS(sdhi2_data1_a, RCAR_GP_PIN(4, 19)); +SDHI_PFC_DAT1(sdhi2_data1_a, SD2_DAT0_A); +SDHI_PFC_PINS(sdhi2_data1_b, RCAR_GP_PIN(4, 7)); +SDHI_PFC_DAT1(sdhi2_data1_b, SD2_DAT0_B); +SDHI_PFC_PINS(sdhi2_data4_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), + RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22)); +SDHI_PFC_DAT4(sdhi2_data4_a, SD2_DAT0_A, SD2_DAT1_A, + SD2_DAT2_A, SD2_DAT3_A); +SDHI_PFC_PINS(sdhi2_data4_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26)); +SDHI_PFC_DAT4(sdhi2_data4_b, SD2_DAT0_B, SD2_DAT1_B, + SD2_DAT2_B, SD2_DAT3_B); +SDHI_PFC_PINS(sdhi2_wp_a, RCAR_GP_PIN(4, 24)); +SDHI_PFC_WPPN(sdhi2_wp_a, SD2_WP_A); +SDHI_PFC_PINS(sdhi2_wp_b, RCAR_GP_PIN(3, 28)); +SDHI_PFC_WPPN(sdhi2_wp_b, SD2_WP_B); + +/* - USB0 ------------------------------------------------------------------- */ +SH_PFC_PINS(usb0, RCAR_GP_PIN(0, 1)); +SH_PFC_MUX1(usb0, PENC0); +SH_PFC_PINS(usb0_ovc, RCAR_GP_PIN(0, 3)); +SH_PFC_MUX1(usb0_ovc, USB_OVC0); + +/* - USB1 ------------------------------------------------------------------- */ +SH_PFC_PINS(usb1, RCAR_GP_PIN(0, 2)); +SH_PFC_MUX1(usb1, PENC1); +SH_PFC_PINS(usb1_ovc, RCAR_GP_PIN(0, 4)); +SH_PFC_MUX1(usb1_ovc, USB_OVC1); + +/* - VIN macros ------------------------------------------------------------- */ +#define VIN_PFC_PINS(name, args...) SH_PFC_PINS(name, args) +#define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \ + SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7) +#define VIN_PFC_CLK(name, clk) SH_PFC_MUX1(name, clk) +#define VIN_PFC_SYNC(name, hsync, vsync) SH_PFC_MUX2(name, hsync, vsync) + +/* - VIN0 ------------------------------------------------------------------- */ +VIN_PFC_PINS(vin0_data8, RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 30), + RCAR_GP_PIN(3, 31), RCAR_GP_PIN(4, 0), + RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), + RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4)); +VIN_PFC_DAT8(vin0_data8, VI0_DATA0_VI0_B0, VI0_DATA1_VI0_B1, + VI0_DATA2_VI0_B2, VI0_DATA3_VI0_B3, + VI0_DATA4_VI0_B4, VI0_DATA5_VI0_B5, + VI0_DATA6_VI0_G0, VI0_DATA7_VI0_G1); +VIN_PFC_PINS(vin0_clk, RCAR_GP_PIN(3, 24)); +VIN_PFC_CLK(vin0_clk, VI0_CLK); +VIN_PFC_PINS(vin0_sync, RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28)); +VIN_PFC_SYNC(vin0_sync, VI0_HSYNC, VI0_VSYNC); +/* - VIN1 ------------------------------------------------------------------- */ +VIN_PFC_PINS(vin1_data8, RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), + RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), + RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6), + RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8)); +VIN_PFC_DAT8(vin1_data8, VI1_DATA0, VI1_DATA1, + VI1_DATA2, VI1_DATA3, + VI1_DATA4, VI1_DATA5, + VI1_DATA6, VI1_DATA7); +VIN_PFC_PINS(vin1_clk, RCAR_GP_PIN(4, 9)); +VIN_PFC_CLK(vin1_clk, VI1_CLK); +VIN_PFC_PINS(vin1_sync, RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22)); +VIN_PFC_SYNC(vin1_sync, VI1_HSYNC, VI1_VSYNC); + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(ether_rmii), + SH_PFC_PIN_GROUP(ether_link), + SH_PFC_PIN_GROUP(ether_magic), + SH_PFC_PIN_GROUP(hscif0_data_a), + SH_PFC_PIN_GROUP(hscif0_data_b), + SH_PFC_PIN_GROUP(hscif0_ctrl_a), + SH_PFC_PIN_GROUP(hscif0_ctrl_b), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif1_data_a), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_a), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(hscif1_clk_a), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hspi0_a), + SH_PFC_PIN_GROUP(hspi0_b), + SH_PFC_PIN_GROUP(hspi1_a), + SH_PFC_PIN_GROUP(hspi1_b), + SH_PFC_PIN_GROUP(hspi2_a), + SH_PFC_PIN_GROUP(hspi2_b), + SH_PFC_PIN_GROUP(i2c1_a), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c2_a), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c2_c), + SH_PFC_PIN_GROUP(i2c3_a), + SH_PFC_PIN_GROUP(i2c3_b), + SH_PFC_PIN_GROUP(i2c3_c), + SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(mmc_data1), + SH_PFC_PIN_GROUP(mmc_data4), + SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(scif0_data_a), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif0_data_c), + SH_PFC_PIN_GROUP(scif0_data_d), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif1_data_a), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_data_c), + SH_PFC_PIN_GROUP(scif1_data_d), + SH_PFC_PIN_GROUP(scif1_ctrl_a), + SH_PFC_PIN_GROUP(scif1_ctrl_c), + SH_PFC_PIN_GROUP(scif1_clk_a), + SH_PFC_PIN_GROUP(scif1_clk_c), + SH_PFC_PIN_GROUP(scif2_data_a), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scif2_data_c), + SH_PFC_PIN_GROUP(scif2_data_d), + SH_PFC_PIN_GROUP(scif2_data_e), + SH_PFC_PIN_GROUP(scif2_clk_a), + SH_PFC_PIN_GROUP(scif2_clk_b), + SH_PFC_PIN_GROUP(scif2_clk_c), + SH_PFC_PIN_GROUP(scif3_data_a), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif3_data_c), + SH_PFC_PIN_GROUP(scif3_data_d), + SH_PFC_PIN_GROUP(scif4_data_a), + SH_PFC_PIN_GROUP(scif4_data_b), + SH_PFC_PIN_GROUP(scif4_data_c), + SH_PFC_PIN_GROUP(scif5_data_a), + SH_PFC_PIN_GROUP(scif5_data_b), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_cd_a), + SH_PFC_PIN_GROUP(sdhi1_cd_b), + SH_PFC_PIN_GROUP(sdhi1_ctrl_a), + SH_PFC_PIN_GROUP(sdhi1_ctrl_b), + SH_PFC_PIN_GROUP(sdhi1_data1_a), + SH_PFC_PIN_GROUP(sdhi1_data1_b), + SH_PFC_PIN_GROUP(sdhi1_data4_a), + SH_PFC_PIN_GROUP(sdhi1_data4_b), + SH_PFC_PIN_GROUP(sdhi1_wp_a), + SH_PFC_PIN_GROUP(sdhi1_wp_b), + SH_PFC_PIN_GROUP(sdhi2_cd_a), + SH_PFC_PIN_GROUP(sdhi2_cd_b), + SH_PFC_PIN_GROUP(sdhi2_ctrl_a), + SH_PFC_PIN_GROUP(sdhi2_ctrl_b), + SH_PFC_PIN_GROUP(sdhi2_data1_a), + SH_PFC_PIN_GROUP(sdhi2_data1_b), + SH_PFC_PIN_GROUP(sdhi2_data4_a), + SH_PFC_PIN_GROUP(sdhi2_data4_b), + SH_PFC_PIN_GROUP(sdhi2_wp_a), + SH_PFC_PIN_GROUP(sdhi2_wp_b), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb0_ovc), + SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb1_ovc), + SH_PFC_PIN_GROUP(vin0_data8), + SH_PFC_PIN_GROUP(vin0_clk), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin1_data8), + SH_PFC_PIN_GROUP(vin1_clk), + SH_PFC_PIN_GROUP(vin1_sync), +}; + +static const char * const ether_groups[] = { + "ether_rmii", + "ether_link", + "ether_magic", +}; + +static const char * const hscif0_groups[] = { + "hscif0_data_a", + "hscif0_data_b", + "hscif0_ctrl_a", + "hscif0_ctrl_b", + "hscif0_clk", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data_a", + "hscif1_data_b", + "hscif1_ctrl_a", + "hscif1_ctrl_b", + "hscif1_clk_a", + "hscif1_clk_b", +}; + +static const char * const hspi0_groups[] = { + "hspi0_a", + "hspi0_b", +}; + +static const char * const hspi1_groups[] = { + "hspi1_a", + "hspi1_b", +}; + +static const char * const hspi2_groups[] = { + "hspi2_a", + "hspi2_b", +}; + +static const char * const i2c1_groups[] = { + "i2c1_a", + "i2c1_b", +}; + +static const char * const i2c2_groups[] = { + "i2c2_a", + "i2c2_b", + "i2c2_c", +}; + +static const char * const i2c3_groups[] = { + "i2c3_a", + "i2c3_b", + "i2c3_c", +}; + +static const char * const mmc_groups[] = { + "mmc_ctrl", + "mmc_data1", + "mmc_data4", + "mmc_data8", +}; + +static const char * const scif_clk_groups[] = { + "scif_clk", +}; + +static const char * const scif0_groups[] = { + "scif0_data_a", + "scif0_data_b", + "scif0_data_c", + "scif0_data_d", + "scif0_ctrl", + "scif0_clk", +}; + +static const char * const scif1_groups[] = { + "scif1_data_a", + "scif1_data_b", + "scif1_data_c", + "scif1_data_d", + "scif1_ctrl_a", + "scif1_ctrl_c", + "scif1_clk_a", + "scif1_clk_c", +}; + +static const char * const scif2_groups[] = { + "scif2_data_a", + "scif2_data_b", + "scif2_data_c", + "scif2_data_d", + "scif2_data_e", + "scif2_clk_a", + "scif2_clk_b", + "scif2_clk_c", +}; + +static const char * const scif3_groups[] = { + "scif3_data_a", + "scif3_data_b", + "scif3_data_c", + "scif3_data_d", +}; + +static const char * const scif4_groups[] = { + "scif4_data_a", + "scif4_data_b", + "scif4_data_c", +}; + +static const char * const scif5_groups[] = { + "scif5_data_a", + "scif5_data_b", +}; + + +static const char * const sdhi0_groups[] = { + "sdhi0_cd", + "sdhi0_ctrl", + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_cd_a", + "sdhi1_cd_b", + "sdhi1_ctrl_a", + "sdhi1_ctrl_b", + "sdhi1_data1_a", + "sdhi1_data1_b", + "sdhi1_data4_a", + "sdhi1_data4_b", + "sdhi1_wp_a", + "sdhi1_wp_b", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_cd_a", + "sdhi2_cd_b", + "sdhi2_ctrl_a", + "sdhi2_ctrl_b", + "sdhi2_data1_a", + "sdhi2_data1_b", + "sdhi2_data4_a", + "sdhi2_data4_b", + "sdhi2_wp_a", + "sdhi2_wp_b", +}; + +static const char * const usb0_groups[] = { + "usb0", + "usb0_ovc", +}; + +static const char * const usb1_groups[] = { + "usb1", + "usb1_ovc", +}; + +static const char * const vin0_groups[] = { + "vin0_data8", + "vin0_clk", + "vin0_sync", +}; + +static const char * const vin1_groups[] = { + "vin1_data8", + "vin1_clk", + "vin1_sync", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(ether), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hspi0), + SH_PFC_FUNCTION(hspi1), + SH_PFC_FUNCTION(hspi2), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(mmc), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { + GP_0_31_FN, FN_IP1_14_11, + GP_0_30_FN, FN_IP1_10_8, + GP_0_29_FN, FN_IP1_7_5, + GP_0_28_FN, FN_IP1_4_2, + GP_0_27_FN, FN_IP1_1, + GP_0_26_FN, FN_IP1_0, + GP_0_25_FN, FN_IP0_30, + GP_0_24_FN, FN_IP0_29, + GP_0_23_FN, FN_IP0_28, + GP_0_22_FN, FN_IP0_27, + GP_0_21_FN, FN_IP0_26, + GP_0_20_FN, FN_IP0_25, + GP_0_19_FN, FN_IP0_24, + GP_0_18_FN, FN_IP0_23, + GP_0_17_FN, FN_IP0_22, + GP_0_16_FN, FN_IP0_21, + GP_0_15_FN, FN_IP0_20, + GP_0_14_FN, FN_IP0_19, + GP_0_13_FN, FN_IP0_18, + GP_0_12_FN, FN_IP0_17, + GP_0_11_FN, FN_IP0_16, + GP_0_10_FN, FN_IP0_15, + GP_0_9_FN, FN_A3, + GP_0_8_FN, FN_A2, + GP_0_7_FN, FN_A1, + GP_0_6_FN, FN_IP0_14_12, + GP_0_5_FN, FN_IP0_11_8, + GP_0_4_FN, FN_IP0_7_5, + GP_0_3_FN, FN_IP0_4_2, + GP_0_2_FN, FN_PENC1, + GP_0_1_FN, FN_PENC0, + GP_0_0_FN, FN_IP0_1_0 } + }, + { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) { + GP_1_31_FN, FN_IP4_6_4, + GP_1_30_FN, FN_IP4_3_1, + GP_1_29_FN, FN_IP4_0, + GP_1_28_FN, FN_IP3_31, + GP_1_27_FN, FN_IP3_30, + GP_1_26_FN, FN_IP3_29, + GP_1_25_FN, FN_IP3_28, + GP_1_24_FN, FN_IP3_27, + GP_1_23_FN, FN_IP3_26_24, + GP_1_22_FN, FN_IP3_23_21, + GP_1_21_FN, FN_IP3_20_19, + GP_1_20_FN, FN_IP3_18_16, + GP_1_19_FN, FN_IP3_15_13, + GP_1_18_FN, FN_IP3_12_10, + GP_1_17_FN, FN_IP3_9_8, + GP_1_16_FN, FN_IP3_7_5, + GP_1_15_FN, FN_IP3_4_2, + GP_1_14_FN, FN_IP3_1_0, + GP_1_13_FN, FN_IP2_31, + GP_1_12_FN, FN_IP2_30, + GP_1_11_FN, FN_IP2_17, + GP_1_10_FN, FN_IP2_16_14, + GP_1_9_FN, FN_IP2_13_12, + GP_1_8_FN, FN_IP2_11_9, + GP_1_7_FN, FN_IP2_8_6, + GP_1_6_FN, FN_IP2_5_3, + GP_1_5_FN, FN_IP2_2_0, + GP_1_4_FN, FN_IP1_29_28, + GP_1_3_FN, FN_IP1_27_25, + GP_1_2_FN, FN_IP1_24, + GP_1_1_FN, FN_WE0, + GP_1_0_FN, FN_IP1_23_21 } + }, + { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) { + GP_2_31_FN, FN_IP6_7, + GP_2_30_FN, FN_IP6_6_5, + GP_2_29_FN, FN_IP6_4_2, + GP_2_28_FN, FN_IP6_1_0, + GP_2_27_FN, FN_IP5_30_29, + GP_2_26_FN, FN_IP5_28_26, + GP_2_25_FN, FN_IP5_25_23, + GP_2_24_FN, FN_IP5_22_21, + GP_2_23_FN, FN_AUDIO_CLKB, + GP_2_22_FN, FN_AUDIO_CLKA, + GP_2_21_FN, FN_IP5_20_18, + GP_2_20_FN, FN_IP5_17_15, + GP_2_19_FN, FN_IP5_14_13, + GP_2_18_FN, FN_IP5_12, + GP_2_17_FN, FN_IP5_11_10, + GP_2_16_FN, FN_IP5_9_8, + GP_2_15_FN, FN_IP5_7, + GP_2_14_FN, FN_IP5_6, + GP_2_13_FN, FN_IP5_5_4, + GP_2_12_FN, FN_IP5_3_2, + GP_2_11_FN, FN_IP5_1_0, + GP_2_10_FN, FN_IP4_30_29, + GP_2_9_FN, FN_IP4_28_27, + GP_2_8_FN, FN_IP4_26_25, + GP_2_7_FN, FN_IP4_24_21, + GP_2_6_FN, FN_IP4_20_17, + GP_2_5_FN, FN_IP4_16_15, + GP_2_4_FN, FN_IP4_14_13, + GP_2_3_FN, FN_IP4_12_11, + GP_2_2_FN, FN_IP4_10_9, + GP_2_1_FN, FN_IP4_8, + GP_2_0_FN, FN_IP4_7 } + }, + { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) { + GP_3_31_FN, FN_IP8_10_9, + GP_3_30_FN, FN_IP8_8_6, + GP_3_29_FN, FN_IP8_5_3, + GP_3_28_FN, FN_IP8_2_0, + GP_3_27_FN, FN_IP7_31_29, + GP_3_26_FN, FN_IP7_28_25, + GP_3_25_FN, FN_IP7_24_22, + GP_3_24_FN, FN_IP7_21, + GP_3_23_FN, FN_IP7_20_18, + GP_3_22_FN, FN_IP7_17_15, + GP_3_21_FN, FN_IP7_14_12, + GP_3_20_FN, FN_IP7_11_9, + GP_3_19_FN, FN_IP7_8_6, + GP_3_18_FN, FN_IP7_5_4, + GP_3_17_FN, FN_IP7_3_2, + GP_3_16_FN, FN_IP7_1_0, + GP_3_15_FN, FN_IP6_31_30, + GP_3_14_FN, FN_IP6_29_28, + GP_3_13_FN, FN_IP6_27_26, + GP_3_12_FN, FN_IP6_25_24, + GP_3_11_FN, FN_IP6_23_22, + GP_3_10_FN, FN_IP6_21, + GP_3_9_FN, FN_IP6_20_19, + GP_3_8_FN, FN_IP6_18_17, + GP_3_7_FN, FN_IP6_16, + GP_3_6_FN, FN_IP6_15_14, + GP_3_5_FN, FN_IP6_13, + GP_3_4_FN, FN_IP6_12_11, + GP_3_3_FN, FN_IP6_10, + GP_3_2_FN, FN_SSI_SCK34, + GP_3_1_FN, FN_IP6_9, + GP_3_0_FN, FN_IP6_8 } + }, + { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_4_26_FN, FN_AVS2, + GP_4_25_FN, FN_AVS1, + GP_4_24_FN, FN_IP10_24_22, + GP_4_23_FN, FN_IP10_21_19, + GP_4_22_FN, FN_IP10_18_16, + GP_4_21_FN, FN_IP10_15_13, + GP_4_20_FN, FN_IP10_12_9, + GP_4_19_FN, FN_IP10_8_6, + GP_4_18_FN, FN_IP10_5_3, + GP_4_17_FN, FN_IP10_2_0, + GP_4_16_FN, FN_IP9_29_27, + GP_4_15_FN, FN_IP9_26_24, + GP_4_14_FN, FN_IP9_23_21, + GP_4_13_FN, FN_IP9_20_18, + GP_4_12_FN, FN_IP9_17_15, + GP_4_11_FN, FN_IP9_14_12, + GP_4_10_FN, FN_IP9_11_9, + GP_4_9_FN, FN_IP9_8_6, + GP_4_8_FN, FN_IP9_5_3, + GP_4_7_FN, FN_IP9_2_0, + GP_4_6_FN, FN_IP8_29_27, + GP_4_5_FN, FN_IP8_26_24, + GP_4_4_FN, FN_IP8_23_22, + GP_4_3_FN, FN_IP8_21_19, + GP_4_2_FN, FN_IP8_18_16, + GP_4_1_FN, FN_IP8_15_14, + GP_4_0_FN, FN_IP8_13_11 } + }, + + { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 3, 4, 3, 3, 2) { + /* IP0_31 [1] */ + 0, 0, + /* IP0_30 [1] */ + FN_A19, 0, + /* IP0_29 [1] */ + FN_A18, 0, + /* IP0_28 [1] */ + FN_A17, 0, + /* IP0_27 [1] */ + FN_A16, 0, + /* IP0_26 [1] */ + FN_A15, 0, + /* IP0_25 [1] */ + FN_A14, 0, + /* IP0_24 [1] */ + FN_A13, 0, + /* IP0_23 [1] */ + FN_A12, 0, + /* IP0_22 [1] */ + FN_A11, 0, + /* IP0_21 [1] */ + FN_A10, 0, + /* IP0_20 [1] */ + FN_A9, 0, + /* IP0_19 [1] */ + FN_A8, 0, + /* IP0_18 [1] */ + FN_A7, 0, + /* IP0_17 [1] */ + FN_A6, 0, + /* IP0_16 [1] */ + FN_A5, 0, + /* IP0_15 [1] */ + FN_A4, 0, + /* IP0_14_12 [3] */ + FN_SD1_DAT3_A, FN_MMC_D3, 0, FN_A0, + FN_ATAG0_A, 0, FN_REMOCON_B, 0, + /* IP0_11_8 [4] */ + FN_SD1_DAT2_A, FN_MMC_D2, 0, FN_BS, + FN_ATADIR0_A, 0, FN_SDSELF_B, 0, + FN_PWM4_B, 0, 0, 0, + 0, 0, 0, 0, + /* IP0_7_5 [3] */ + FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C, FN_USB_OVC1, + FN_RX2_E, FN_SCL2_B, 0, 0, + /* IP0_4_2 [3] */ + FN_AUDATA0, FN_ARM_TRACEDATA_0, FN_GPSCLK_C, FN_USB_OVC0, + FN_TX2_E, FN_SDA2_B, 0, 0, + /* IP0_1_0 [2] */ + FN_PRESETOUT, 0, FN_PWM1, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32, + 1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3, 3, 1, 1) { + /* IP1_31 [1] */ + 0, 0, + /* IP1_30 [1] */ + 0, 0, + /* IP1_29_28 [2] */ + FN_EX_CS1, FN_MMC_D4, 0, 0, + /* IP1_27_25 [3] */ + FN_SSI_WS1_B, FN_EX_CS0, FN_SCL2_A, FN_TX3_C, + FN_TS_SCK0_A, 0, 0, 0, + /* IP1_24 [1] */ + FN_WE1, FN_ATAWR0_B, + /* IP1_23_21 [3] */ + FN_MMC_D5, FN_ATADIR0_B, 0, FN_RD_WR, + 0, 0, 0, 0, + /* IP1_20_18 [3] */ + FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A, + FN_SCK2_B, 0, 0, 0, + /* IP1_17 [1] */ + FN_CS0, FN_HSPI_RX1_B, + /* IP1_16_15 [2] */ + FN_CLKOUT, FN_HSPI_TX1_B, FN_PWM0_B, 0, + /* IP1_14_11 [4] */ + FN_SD1_WP_A, FN_MMC_D7, 0, FN_A25, + FN_DACK1_A, 0, FN_HCTS0_B, FN_RX3_C, + FN_TS_SDAT0_A, 0, 0, 0, + 0, 0, 0, 0, + /* IP1_10_8 [3] */ + FN_SD1_CLK_B, FN_MMC_D6, 0, FN_A24, + FN_DREQ1_A, 0, FN_HRX0_B, FN_TS_SPSYNC0_A, + /* IP1_7_5 [3] */ + FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A, + FN_TS_SDEN0_A, 0, 0, 0, + /* IP1_4_2 [3] */ + FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A, + 0, 0, 0, 0, + /* IP1_1 [1] */ + FN_A21, FN_HSPI_CLK1_B, + /* IP1_0 [1] */ + FN_A20, FN_HSPI_CS1_B, + } + }, + { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 3, 2, 3, 3, 3, 3) { + /* IP2_31 [1] */ + FN_MLB_CLK, FN_IRQ1_A, + /* IP2_30 [1] */ + FN_RD_WR_B, FN_IRQ0, + /* IP2_29 [1] */ + FN_D11, 0, + /* IP2_28 [1] */ + FN_D10, 0, + /* IP2_27 [1] */ + FN_D9, 0, + /* IP2_26 [1] */ + FN_D8, 0, + /* IP2_25 [1] */ + FN_D7, 0, + /* IP2_24 [1] */ + FN_D6, 0, + /* IP2_23 [1] */ + FN_D5, 0, + /* IP2_22 [1] */ + FN_D4, 0, + /* IP2_21 [1] */ + FN_D3, 0, + /* IP2_20 [1] */ + FN_D2, 0, + /* IP2_19 [1] */ + FN_D1, 0, + /* IP2_18 [1] */ + FN_D0, 0, + /* IP2_17 [1] */ + FN_EX_WAIT0, FN_PWM0_C, + /* IP2_16_14 [3] */ + FN_DACK0, 0, 0, FN_TX3_A, + FN_DRACK0, 0, 0, 0, + /* IP2_13_12 [2] */ + FN_DREQ0_A, 0, 0, FN_RX3_A, + /* IP2_11_9 [3] */ + FN_SD1_DAT1_A, FN_MMC_D1, 0, FN_ATAWR0_A, + FN_EX_CS5, FN_EX_WAIT2_A, 0, 0, + /* IP2_8_6 [3] */ + FN_SD1_DAT0_A, FN_MMC_D0, 0, FN_ATARD0, + FN_EX_CS4, FN_EX_WAIT1_A, 0, 0, + /* IP2_5_3 [3] */ + FN_SD1_CMD_A, FN_MMC_CMD, 0, FN_ATACS10, + FN_EX_CS3, 0, 0, 0, + /* IP2_2_0 [3] */ + FN_SD1_CLK_A, FN_MMC_CLK, 0, FN_ATACS00, + FN_EX_CS2, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32, + 1, 1, 1, 1, 1, 3, 3, 2, + 3, 3, 3, 2, 3, 3, 2) { + /* IP3_31 [1] */ + FN_DU0_DR6, FN_LCDOUT6, + /* IP3_30 [1] */ + FN_DU0_DR5, FN_LCDOUT5, + /* IP3_29 [1] */ + FN_DU0_DR4, FN_LCDOUT4, + /* IP3_28 [1] */ + FN_DU0_DR3, FN_LCDOUT3, + /* IP3_27 [1] */ + FN_DU0_DR2, FN_LCDOUT2, + /* IP3_26_24 [3] */ + FN_SSI_WS4, FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3, + FN_ARM_TRACEDATA_3, FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B, + /* IP3_23_21 [3] */ + FN_SSI_SCK4, FN_DU0_DR0, FN_LCDOUT0, FN_AUDATA2, + FN_ARM_TRACEDATA_2, FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B, + /* IP3_20_19 [2] */ + FN_SD1_DAT3_B, FN_HRTS0_A, FN_RTS0, 0, + /* IP3_18_16 [3] */ + FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, 0, + 0, 0, 0, 0, + /* IP3_15_13 [3] */ + FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B, + 0, 0, 0, 0, + /* IP3_12_10 [3] */ + FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A, 0, + 0, 0, 0, 0, + /* IP3_9_8 [2] */ + FN_SD1_CLK_B, FN_HTX0_A, FN_TX0_A, 0, + /* IP3_7_5 [3] */ + FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B, FN_CAN_CLK_B, + FN_SDA3_B, 0, 0, 0, + /* IP3_4_2 [3] */ + FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A, + FN_SDSELF_B, 0, 0, 0, + /* IP3_1_0 [2] */ + FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A, + } + }, + { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32, + 1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1, 3, 3, 1) { + /* IP4_31 [1] */ + 0, 0, + /* IP4_30_29 [2] */ + FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20, 0, + /* IP4_28_27 [2] */ + FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19, 0, + /* IP4_26_25 [2] */ + FN_VI0_R2_B, FN_DU0_DB2, FN_LCDOUT18, 0, + /* IP4_24_21 [4] */ + FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17, + FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A, 0, + FN_ADICS_SAMP, FN_TS_SCK0_B, 0, 0, + 0, 0, 0, 0, + /* IP4_20_17 [4] */ + FN_SSI_SCK2_B, FN_VI0_R0_B, FN_DU0_DB0, FN_LCDOUT16, + FN_AUDATA6, FN_ARM_TRACEDATA_6, FN_GPSCLK_A, FN_PWM0_A, + FN_ADICLK, FN_TS_SDAT0_B, 0, 0, + 0, 0, 0, 0, + /* IP4_16_15 [2] */ + FN_DU0_DG7, FN_LCDOUT15, FN_TX4_A, 0, + /* IP4_14_13 [2] */ + FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, 0, + /* IP4_12_11 [2] */ + FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B, 0, + /* IP4_10_9 [2] */ + FN_DU0_DG4, FN_LCDOUT12, FN_RX0_B, 0, + /* IP4_8 [1] */ + FN_DU0_DG3, FN_LCDOUT11, + /* IP4_7 [1] */ + FN_DU0_DG2, FN_LCDOUT10, + /* IP4_6_4 [3] */ + FN_DU0_DG1, FN_LCDOUT9, FN_AUDATA5, FN_ARM_TRACEDATA_5, + FN_RX1_D, FN_CAN0_RX_A, FN_ADIDATA, 0, + /* IP4_3_1 [3] */ + FN_DU0_DG0, FN_LCDOUT8, FN_AUDATA4, FN_ARM_TRACEDATA_4, + FN_TX1_D, FN_CAN0_TX_A, FN_ADICHS0, 0, + /* IP4_0 [1] */ + FN_DU0_DR7, FN_LCDOUT7, + } + }, + { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32, + 1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1, 1, 2, 2, 2) { + + /* IP5_31 [1] */ + 0, 0, + /* IP5_30_29 [2] */ + FN_SSI_SDATA7, FN_HSPI_TX0_B, FN_RX2_A, FN_CAN0_RX_B, + /* IP5_28_26 [3] */ + FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B, FN_TX2_A, + FN_CAN0_TX_B, 0, 0, 0, + /* IP5_25_23 [3] */ + FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B, + FN_CAN_CLK_D, 0, 0, 0, + /* IP5_22_21 [2] */ + FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B, + /* IP5_20_18 [3] */ + FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB, FN_AUDSYNC, + FN_ARM_TRACECTL, FN_FMIN_D, 0, 0, + /* IP5_17_15 [3] */ + FN_SSI_SCK1_A, FN_DU0_DISP, FN_QPOLA, FN_AUDCK, + FN_ARM_TRACECLK, FN_BPFCLK_D, 0, 0, + /* IP5_14_13 [2] */ + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, + FN_FMCLK_D, 0, + /* IP5_12 [1] */ + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, + /* IP5_11_10 [2] */ + FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC, + FN_QSTH_QHS, 0, + /* IP5_9_8 [2] */ + FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE, + FN_AUDIO_CLKOUT_A, FN_REMOCON_C, + /* IP5_7 [1] */ + FN_DU0_DOTCLKO_UT0, FN_QCLK, + /* IP5_6 [1] */ + FN_DU0_DOTCLKIN, FN_QSTVA_QVS, + /* IP5_5_4 [2] */ + FN_VI1_DATA11_B, FN_DU0_DB7, FN_LCDOUT23, 0, + /* IP5_3_2 [2] */ + FN_VI1_DATA10_B, FN_DU0_DB6, FN_LCDOUT22, 0, + /* IP5_1_0 [2] */ + FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32, + 2, 2, 2, 2, 2, 1, 2, 2, 1, 2, + 1, 2, 1, 1, 1, 1, 2, 3, 2) { + /* IP6_31_30 [2] */ + FN_SD0_DAT2, 0, FN_SUB_TDI, 0, + /* IP6_29_28 [2] */ + FN_SD0_DAT1, 0, FN_SUB_TCK, 0, + /* IP6_27_26 [2] */ + FN_SD0_DAT0, 0, FN_SUB_TMS, 0, + /* IP6_25_24 [2] */ + FN_SD0_CMD, 0, FN_SUB_TRST, 0, + /* IP6_23_22 [2] */ + FN_SD0_CLK, 0, FN_SUB_TDO, 0, + /* IP6_21 [1] */ + FN_SSI_SDATA0, FN_ARM_TRACEDATA_15, + /* IP6_20_19 [2] */ + FN_SSI_SDATA1, FN_ARM_TRACEDATA_14, + FN_SCL1_A, FN_SCK2_A, + /* IP6_18_17 [2] */ + FN_SSI_SDATA2, FN_HSPI_CS2_A, + FN_ARM_TRACEDATA_13, FN_SDA1_A, + /* IP6_16 [1] */ + FN_SSI_WS012, FN_ARM_TRACEDATA_12, + /* IP6_15_14 [2] */ + FN_SSI_SCK012, FN_ARM_TRACEDATA_11, + FN_TX0_D, 0, + /* IP6_13 [1] */ + FN_SSI_SDATA3, FN_ARM_TRACEDATA_10, + /* IP6_12_11 [2] */ + FN_SSI_SDATA4, FN_SSI_WS2_A, + FN_ARM_TRACEDATA_9, 0, + /* IP6_10 [1] */ + FN_SSI_WS34, FN_ARM_TRACEDATA_8, + /* IP6_9 [1] */ + FN_SSI_SDATA5, FN_RX0_D, + /* IP6_8 [1] */ + FN_SSI_WS5, FN_TX4_C, + /* IP6_7 [1] */ + FN_SSI_SCK5, FN_RX4_C, + /* IP6_6_5 [2] */ + FN_SSI_SDATA6, FN_HSPI_TX2_A, + FN_FMIN_B, 0, + /* IP6_4_2 [3] */ + FN_SSI_WS6, FN_HSPI_CLK2_A, + FN_BPFCLK_B, FN_CAN1_RX_B, + 0, 0, 0, 0, + /* IP6_1_0 [2] */ + FN_SSI_SCK6, FN_HSPI_RX2_A, + FN_FMCLK_B, FN_CAN1_TX_B, + } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32, + 3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2) { + + /* IP7_31_29 [3] */ + FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, FN_DU1_DR2, + 0, FN_HSPI_CS1_A, FN_RX3_B, 0, + /* IP7_28_25 [4] */ + FN_VI0_FIELD, FN_SD2_DAT3_B, FN_VI0_R3_C, FN_VI1_DATA1, + FN_DU1_DG7, 0, FN_HSPI_CLK1_A, FN_TX4_B, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IP7_24_22 [3] */ + FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6, + 0, FN_HSPI_RX1_A, FN_RX4_B, 0, + /* IP7_21 [1] */ + FN_VI0_CLK, FN_CAN_CLK_A, + /* IP7_20_18 [3] */ + FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, 0, + FN_IRQ2_C, FN_CTS1_C, FN_SPEEDIN, 0, + /* IP7_17_15 [3] */ + FN_VI1_VSYNC, FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A, + 0, FN_TX1_C, 0, 0, + /* IP7_14_12 [3] */ + FN_VI1_HSYNC, FN_HSPI_RX0_A, FN_HRTS1_A, FN_FMCLK_A, + 0, FN_RX1_C, 0, 0, + /* IP7_11_9 [3] */ + FN_VI1_FIELD, FN_HSPI_CS0_A, FN_HRX1_A, 0, + FN_SCK1_C, 0, 0, 0, + /* IP7_8_6 [3] */ + FN_VI1_CLKENB, FN_HSPI_CLK0_A, FN_HTX1_A, 0, + FN_RTS1_C, 0, 0, 0, + /* IP7_5_4 [2] */ + FN_SD0_WP, 0, FN_RX5_A, 0, + /* IP7_3_2 [2] */ + FN_SD0_CD, 0, FN_TX5_A, 0, + /* IP7_1_0 [2] */ + FN_SD0_DAT3, 0, FN_IRQ1_B, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32, + 1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3) { + /* IP8_31 [1] */ + 0, 0, + /* IP8_30 [1] */ + 0, 0, + /* IP8_29_27 [3] */ + FN_VI0_G3, FN_SD2_CMD_B, FN_VI1_DATA5, FN_DU1_DR5, + 0, FN_HRX1_B, 0, 0, + /* IP8_26_24 [3] */ + FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4, FN_DU1_DR4, + 0, FN_HTX1_B, 0, 0, + /* IP8_23_22 [2] */ + FN_VI0_DATA7_VI0_G1, FN_DU1_DB5, + FN_RTS1_A, 0, + /* IP8_21_19 [3] */ + FN_VI0_DATA6_VI0_G0, FN_DU1_DB4, + FN_CTS1_A, FN_PWM5, + 0, 0, 0, 0, + /* IP8_18_16 [3] */ + FN_VI0_DATA5_VI0_B5, FN_DU1_DB3, FN_SCK1_A, FN_PWM4, + 0, FN_HSCK1_B, 0, 0, + /* IP8_15_14 [2] */ + FN_VI0_DATA4_VI0_B4, FN_DU1_DB2, FN_RX1_A, 0, + /* IP8_13_11 [3] */ + FN_VI0_DATA3_VI0_B3, FN_DU1_DG5, FN_TX1_A, FN_TX0_C, + 0, 0, 0, 0, + /* IP8_10_9 [2] */ + FN_VI0_DATA2_VI0_B2, FN_DU1_DG4, FN_RX0_C, 0, + /* IP8_8_6 [3] */ + FN_VI0_DATA1_VI0_B1, FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D, + 0, 0, 0, 0, + /* IP8_5_3 [3] */ + FN_VI0_DATA0_VI0_B0, FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D, + 0, 0, 0, 0, + /* IP8_2_0 [3] */ + FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3, + 0, FN_HSPI_TX1_A, FN_TX3_B, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32, + 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + /* IP9_31 [1] */ + 0, 0, + /* IP9_30 [1] */ + 0, 0, + /* IP9_29_27 [3] */ + FN_VI1_DATA11_A, FN_DU1_EXHSYNC_DU1_HSYNC, + FN_ETH_RXD1, FN_FMIN_C, + 0, FN_RX2_D, + FN_SCL2_C, 0, + /* IP9_26_24 [3] */ + FN_VI1_DATA10_A, FN_DU1_DOTCLKOUT, + FN_ETH_RXD0, FN_BPFCLK_C, + 0, FN_TX2_D, + FN_SDA2_C, 0, + /* IP9_23_21 [3] */ + FN_VI0_R5_A, 0, FN_ETH_RX_ER, FN_FMCLK_C, + FN_IERX, FN_RX2_C, 0, 0, + /* IP9_20_18 [3] */ + FN_VI0_R4_A, FN_ETH_TX_EN, 0, 0, + FN_IETX, FN_TX2_C, 0, 0, + /* IP9_17_15 [3] */ + FN_VI0_R3_A, FN_ETH_CRS_DV, 0, FN_IECLK, + FN_SCK2_C, 0, 0, 0, + /* IP9_14_12 [3] */ + FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7, FN_ETH_TXD1, + 0, FN_PWM3, 0, 0, + /* IP9_11_9 [3] */ + FN_VI0_R1_A, FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0, + 0, FN_PWM2, FN_TCLK1, 0, + /* IP9_8_6 [3] */ + FN_VI0_R0_A, FN_VI1_CLK, FN_ETH_REF_CLK, FN_DU1_DOTCLKIN, + 0, 0, 0, 0, + /* IP9_5_3 [3] */ + FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7, FN_DU1_DR7, + 0, FN_HCTS1_B, 0, 0, + /* IP9_2_0 [3] */ + FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6, + 0, FN_HRTS1_B, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32, + 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4, 3, 3, 3) { + + /* IP10_31 [1] */ + 0, 0, + /* IP10_30 [1] */ + 0, 0, + /* IP10_29 [1] */ + 0, 0, + /* IP10_28 [1] */ + 0, 0, + /* IP10_27 [1] */ + 0, 0, + /* IP10_26 [1] */ + 0, 0, + /* IP10_25 [1] */ + 0, 0, + /* IP10_24_22 [3] */ + FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B, FN_DACK0_B, + FN_HSPI_TX2_B, FN_CAN_CLK_C, 0, 0, + /* IP10_21_19 [3] */ + FN_SD2_CD_A, FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B, + FN_HSPI_RX2_B, FN_REMOCON_A, 0, 0, + /* IP10_18_16 [3] */ + FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B, FN_ATAG1, + FN_HSPI_CS2_B, FN_GPSIN_B, 0, 0, + /* IP10_15_13 [3] */ + FN_SD2_DAT2_A, FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1, + FN_HSPI_CLK2_B, FN_GPSCLK_B, 0, 0, + /* IP10_12_9 [4] */ + FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B, + FN_ETH_MAGIC, FN_CAN1_TX_A, 0, FN_PWM6, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IP10_8_6 [3] */ + FN_SD2_DAT0_A, FN_DU1_DISP, FN_ATACS01, FN_DREQ1_B, + FN_ETH_LINK, FN_CAN1_RX_A, 0, 0, + /* IP10_5_3 [3] */ + FN_SD2_CMD_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, + FN_ATAWR1, FN_ETH_MDIO, + FN_SCL1_B, 0, + 0, 0, + /* IP10_2_0 [3] */ + FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC, + FN_ATARD1, FN_ETH_MDC, + FN_SDA1_B, 0, + 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32, + 1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2, + 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { + + /* SEL 31 [1] */ + 0, 0, + /* SEL_30 (SCIF5) [1] */ + FN_SEL_SCIF5_A, FN_SEL_SCIF5_B, + /* SEL_29_28 (SCIF4) [2] */ + FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, + FN_SEL_SCIF4_C, 0, + /* SEL_27_26 (SCIF3) [2] */ + FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, + FN_SEL_SCIF3_C, FN_SEL_SCIF3_D, + /* SEL_25_23 (SCIF2) [3] */ + FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, + FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, + FN_SEL_SCIF2_E, 0, + 0, 0, + /* SEL_22_21 (SCIF1) [2] */ + FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, + FN_SEL_SCIF1_C, FN_SEL_SCIF1_D, + /* SEL_20_19 (SCIF0) [2] */ + FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, + FN_SEL_SCIF0_C, FN_SEL_SCIF0_D, + /* SEL_18 [1] */ + 0, 0, + /* SEL_17 (SSI2) [1] */ + FN_SEL_SSI2_A, FN_SEL_SSI2_B, + /* SEL_16 (SSI1) [1] */ + FN_SEL_SSI1_A, FN_SEL_SSI1_B, + /* SEL_15 (VI1) [1] */ + FN_SEL_VI1_A, FN_SEL_VI1_B, + /* SEL_14_13 (VI0) [2] */ + FN_SEL_VI0_A, FN_SEL_VI0_B, + FN_SEL_VI0_C, FN_SEL_VI0_D, + /* SEL_12 [1] */ + 0, 0, + /* SEL_11 (SD2) [1] */ + FN_SEL_SD2_A, FN_SEL_SD2_B, + /* SEL_10 (SD1) [1] */ + FN_SEL_SD1_A, FN_SEL_SD1_B, + /* SEL_9 (IRQ3) [1] */ + FN_SEL_IRQ3_A, FN_SEL_IRQ3_B, + /* SEL_8_7 (IRQ2) [2] */ + FN_SEL_IRQ2_A, FN_SEL_IRQ2_B, + FN_SEL_IRQ2_C, 0, + /* SEL_6 (IRQ1) [1] */ + FN_SEL_IRQ1_A, FN_SEL_IRQ1_B, + /* SEL_5 [1] */ + 0, 0, + /* SEL_4 (DREQ2) [1] */ + FN_SEL_DREQ2_A, FN_SEL_DREQ2_B, + /* SEL_3 (DREQ1) [1] */ + FN_SEL_DREQ1_A, FN_SEL_DREQ1_B, + /* SEL_2 (DREQ0) [1] */ + FN_SEL_DREQ0_A, FN_SEL_DREQ0_B, + /* SEL_1 (WAIT2) [1] */ + FN_SEL_WAIT2_A, FN_SEL_WAIT2_B, + /* SEL_0 (WAIT1) [1] */ + FN_SEL_WAIT1_A, FN_SEL_WAIT1_B, + } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32, + 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1) { + + /* SEL_31 [1] */ + 0, 0, + /* SEL_30 [1] */ + 0, 0, + /* SEL_29 [1] */ + 0, 0, + /* SEL_28 [1] */ + 0, 0, + /* SEL_27 (CAN1) [1] */ + FN_SEL_CAN1_A, FN_SEL_CAN1_B, + /* SEL_26 (CAN0) [1] */ + FN_SEL_CAN0_A, FN_SEL_CAN0_B, + /* SEL_25_24 (CANCLK) [2] */ + FN_SEL_CANCLK_A, FN_SEL_CANCLK_B, + FN_SEL_CANCLK_C, FN_SEL_CANCLK_D, + /* SEL_23 (HSCIF1) [1] */ + FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B, + /* SEL_22 (HSCIF0) [1] */ + FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B, + /* SEL_21 [1] */ + 0, 0, + /* SEL_20 [1] */ + 0, 0, + /* SEL_19 [1] */ + 0, 0, + /* SEL_18 [1] */ + 0, 0, + /* SEL_17 [1] */ + 0, 0, + /* SEL_16 [1] */ + 0, 0, + /* SEL_15 [1] */ + 0, 0, + /* SEL_14_13 (REMOCON) [2] */ + FN_SEL_REMOCON_A, FN_SEL_REMOCON_B, + FN_SEL_REMOCON_C, 0, + /* SEL_12_11 (FM) [2] */ + FN_SEL_FM_A, FN_SEL_FM_B, + FN_SEL_FM_C, FN_SEL_FM_D, + /* SEL_10_9 (GPS) [2] */ + FN_SEL_GPS_A, FN_SEL_GPS_B, + FN_SEL_GPS_C, 0, + /* SEL_8 (TSIF0) [1] */ + FN_SEL_TSIF0_A, FN_SEL_TSIF0_B, + /* SEL_7 (HSPI2) [1] */ + FN_SEL_HSPI2_A, FN_SEL_HSPI2_B, + /* SEL_6 (HSPI1) [1] */ + FN_SEL_HSPI1_A, FN_SEL_HSPI1_B, + /* SEL_5 (HSPI0) [1] */ + FN_SEL_HSPI0_A, FN_SEL_HSPI0_B, + /* SEL_4_3 (I2C3) [2] */ + FN_SEL_I2C3_A, FN_SEL_I2C3_B, + FN_SEL_I2C3_C, 0, + /* SEL_2_1 (I2C2) [2] */ + FN_SEL_I2C2_A, FN_SEL_I2C2_B, + FN_SEL_I2C2_C, 0, + /* SEL_0 (I2C1) [1] */ + FN_SEL_I2C1_A, FN_SEL_I2C1_B, + } + }, + { }, +}; + +const struct sh_pfc_soc_info r8a7778_pinmux_info = { + .name = "r8a7778_pfc", + + .unlock_reg = 0xfffc0000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 8cd90e7e945..8e22ca6c104 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -1,8 +1,9 @@ /* * r8a7779 processor support - PFC hardware block * - * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011, 2013 Renesas Solutions Corp. * Copyright (C) 2011 Magnus Damm + * Copyright (C) 2013 Cogent Embedded, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,6 +20,7 @@ */ #include <linux/kernel.h> +#include <linux/platform_data/gpio-rcar.h> #include "sh_pfc.h" @@ -79,7 +81,7 @@ #define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx #define _GP_GPIO(bank, pin, _name, sfx) \ - [(bank * 32) + pin] = { \ + [RCAR_GP_PIN(bank, pin)] = { \ .name = __stringify(_name), \ .enum_id = _name##_DATA, \ } @@ -1472,9 +1474,12 @@ static struct sh_pfc_pin pinmux_pins[] = { /* - DU0 -------------------------------------------------------------------- */ static const unsigned int du0_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ - 188, 187, 186, 185, 184, 183, - 194, 193, 192, 191, 190, 189, - 200, 199, 198, 197, 196, 195, + RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26), + RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), + RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 0), + RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), + RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 3), }; static const unsigned int du0_rgb666_mux[] = { DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, @@ -1486,9 +1491,14 @@ static const unsigned int du0_rgb666_mux[] = { }; static const unsigned int du0_rgb888_pins[] = { /* R[7:0], G[7:0], B[7:0] */ - 188, 187, 186, 185, 184, 183, 24, 23, - 194, 193, 192, 191, 190, 189, 26, 25, - 200, 199, 198, 197, 196, 195, 28, 27, + RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26), + RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), RCAR_GP_PIN(6, 2), + RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(5, 31), + RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), RCAR_GP_PIN(0, 26), + RCAR_GP_PIN(0, 25), RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 7), + RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 4), + RCAR_GP_PIN(6, 3), RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 27), }; static const unsigned int du0_rgb888_mux[] = { DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, @@ -1500,28 +1510,28 @@ static const unsigned int du0_rgb888_mux[] = { }; static const unsigned int du0_clk_in_pins[] = { /* CLKIN */ - 29, + RCAR_GP_PIN(0, 29), }; static const unsigned int du0_clk_in_mux[] = { DU0_DOTCLKIN_MARK, }; static const unsigned int du0_clk_out_0_pins[] = { /* CLKOUT */ - 180, + RCAR_GP_PIN(5, 20), }; static const unsigned int du0_clk_out_0_mux[] = { DU0_DOTCLKOUT0_MARK, }; static const unsigned int du0_clk_out_1_pins[] = { /* CLKOUT */ - 30, + RCAR_GP_PIN(0, 30), }; static const unsigned int du0_clk_out_1_mux[] = { DU0_DOTCLKOUT1_MARK, }; static const unsigned int du0_sync_0_pins[] = { /* VSYNC, HSYNC, DISP */ - 182, 181, 31, + RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(0, 31), }; static const unsigned int du0_sync_0_mux[] = { DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, @@ -1529,7 +1539,7 @@ static const unsigned int du0_sync_0_mux[] = { }; static const unsigned int du0_sync_1_pins[] = { /* VSYNC, HSYNC, DISP */ - 182, 181, 32, + RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(1, 0), }; static const unsigned int du0_sync_1_mux[] = { DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, @@ -1537,14 +1547,14 @@ static const unsigned int du0_sync_1_mux[] = { }; static const unsigned int du0_oddf_pins[] = { /* ODDF */ - 31, + RCAR_GP_PIN(0, 31), }; static const unsigned int du0_oddf_mux[] = { DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK }; static const unsigned int du0_cde_pins[] = { /* CDE */ - 33, + RCAR_GP_PIN(1, 1), }; static const unsigned int du0_cde_mux[] = { DU0_CDE_MARK @@ -1552,9 +1562,12 @@ static const unsigned int du0_cde_mux[] = { /* - DU1 -------------------------------------------------------------------- */ static const unsigned int du1_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ - 41, 40, 39, 38, 37, 36, - 49, 48, 47, 46, 45, 44, - 57, 56, 55, 54, 53, 52, + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 20), }; static const unsigned int du1_rgb666_mux[] = { DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, @@ -1566,9 +1579,14 @@ static const unsigned int du1_rgb666_mux[] = { }; static const unsigned int du1_rgb888_pins[] = { /* R[7:0], G[7:0], B[7:0] */ - 41, 40, 39, 38, 37, 36, 35, 34, - 49, 48, 47, 46, 45, 44, 43, 32, - 57, 56, 55, 54, 53, 52, 51, 50, + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 17), + RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), }; static const unsigned int du1_rgb888_mux[] = { DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, @@ -1580,21 +1598,21 @@ static const unsigned int du1_rgb888_mux[] = { }; static const unsigned int du1_clk_in_pins[] = { /* CLKIN */ - 58, + RCAR_GP_PIN(1, 26), }; static const unsigned int du1_clk_in_mux[] = { DU1_DOTCLKIN_MARK, }; static const unsigned int du1_clk_out_pins[] = { /* CLKOUT */ - 59, + RCAR_GP_PIN(1, 27), }; static const unsigned int du1_clk_out_mux[] = { DU1_DOTCLKOUT_MARK, }; static const unsigned int du1_sync_0_pins[] = { /* VSYNC, HSYNC, DISP */ - 61, 60, 62, + RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 30), }; static const unsigned int du1_sync_0_mux[] = { DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, @@ -1602,7 +1620,7 @@ static const unsigned int du1_sync_0_mux[] = { }; static const unsigned int du1_sync_1_pins[] = { /* VSYNC, HSYNC, DISP */ - 61, 60, 63, + RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 31), }; static const unsigned int du1_sync_1_mux[] = { DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, @@ -1610,22 +1628,55 @@ static const unsigned int du1_sync_1_mux[] = { }; static const unsigned int du1_oddf_pins[] = { /* ODDF */ - 62, + RCAR_GP_PIN(1, 30), }; static const unsigned int du1_oddf_mux[] = { DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK }; static const unsigned int du1_cde_pins[] = { /* CDE */ - 64, + RCAR_GP_PIN(2, 0), }; static const unsigned int du1_cde_mux[] = { DU1_CDE_MARK }; +/* - Ether ------------------------------------------------------------------ */ +static const unsigned int ether_rmii_pins[] = { + /* + * ETH_TXD0, ETH_TXD1, ETH_TX_EN, ETH_REFCLK, + * ETH_RXD0, ETH_RXD1, ETH_CRS_DV, ETH_RX_ER, + * ETH_MDIO, ETH_MDC + */ + RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 26), + RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 17), + RCAR_GP_PIN(2, 19), + RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 28), +}; +static const unsigned int ether_rmii_mux[] = { + ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, + ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK, + ETH_MDIO_MARK, ETH_MDC_MARK, +}; +static const unsigned int ether_link_pins[] = { + /* ETH_LINK */ + RCAR_GP_PIN(2, 24), +}; +static const unsigned int ether_link_mux[] = { + ETH_LINK_MARK, +}; +static const unsigned int ether_magic_pins[] = { + /* ETH_MAGIC */ + RCAR_GP_PIN(2, 25), +}; +static const unsigned int ether_magic_mux[] = { + ETH_MAGIC_MARK, +}; /* - HSPI0 ------------------------------------------------------------------ */ static const unsigned int hspi0_pins[] = { /* CLK, CS, RX, TX */ - 150, 151, 153, 152, + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 25), + RCAR_GP_PIN(4, 24), }; static const unsigned int hspi0_mux[] = { HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK, @@ -1633,28 +1684,32 @@ static const unsigned int hspi0_mux[] = { /* - HSPI1 ------------------------------------------------------------------ */ static const unsigned int hspi1_pins[] = { /* CLK, CS, RX, TX */ - 63, 58, 64, 62, + RCAR_GP_PIN(1, 31), RCAR_GP_PIN(1, 26), RCAR_GP_PIN(2, 0), + RCAR_GP_PIN(1, 30), }; static const unsigned int hspi1_mux[] = { HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK, }; static const unsigned int hspi1_b_pins[] = { /* CLK, CS, RX, TX */ - 90, 91, 93, 92, + RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 29), + RCAR_GP_PIN(2, 28), }; static const unsigned int hspi1_b_mux[] = { HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK, }; static const unsigned int hspi1_c_pins[] = { /* CLK, CS, RX, TX */ - 141, 142, 144, 143, + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 16), + RCAR_GP_PIN(4, 15), }; static const unsigned int hspi1_c_mux[] = { HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK, }; static const unsigned int hspi1_d_pins[] = { /* CLK, CS, RX, TX */ - 101, 102, 104, 103, + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 8), + RCAR_GP_PIN(3, 7), }; static const unsigned int hspi1_d_mux[] = { HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK, @@ -1662,14 +1717,16 @@ static const unsigned int hspi1_d_mux[] = { /* - HSPI2 ------------------------------------------------------------------ */ static const unsigned int hspi2_pins[] = { /* CLK, CS, RX, TX */ - 9, 10, 11, 14, + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 14), }; static const unsigned int hspi2_mux[] = { HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK, }; static const unsigned int hspi2_b_pins[] = { /* CLK, CS, RX, TX */ - 7, 13, 8, 6, + RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 8), + RCAR_GP_PIN(0, 6), }; static const unsigned int hspi2_b_mux[] = { HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK, @@ -1677,56 +1734,56 @@ static const unsigned int hspi2_b_mux[] = { /* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = { /* IRQ */ - 78, + RCAR_GP_PIN(2, 14), }; static const unsigned int intc_irq0_mux[] = { IRQ0_MARK, }; static const unsigned int intc_irq0_b_pins[] = { /* IRQ */ - 141, + RCAR_GP_PIN(4, 13), }; static const unsigned int intc_irq0_b_mux[] = { IRQ0_B_MARK, }; static const unsigned int intc_irq1_pins[] = { /* IRQ */ - 79, + RCAR_GP_PIN(2, 15), }; static const unsigned int intc_irq1_mux[] = { IRQ1_MARK, }; static const unsigned int intc_irq1_b_pins[] = { /* IRQ */ - 142, + RCAR_GP_PIN(4, 14), }; static const unsigned int intc_irq1_b_mux[] = { IRQ1_B_MARK, }; static const unsigned int intc_irq2_pins[] = { /* IRQ */ - 88, + RCAR_GP_PIN(2, 24), }; static const unsigned int intc_irq2_mux[] = { IRQ2_MARK, }; static const unsigned int intc_irq2_b_pins[] = { /* IRQ */ - 143, + RCAR_GP_PIN(4, 15), }; static const unsigned int intc_irq2_b_mux[] = { IRQ2_B_MARK, }; static const unsigned int intc_irq3_pins[] = { /* IRQ */ - 89, + RCAR_GP_PIN(2, 25), }; static const unsigned int intc_irq3_mux[] = { IRQ3_MARK, }; static const unsigned int intc_irq3_b_pins[] = { /* IRQ */ - 144, + RCAR_GP_PIN(4, 16), }; static const unsigned int intc_irq3_b_mux[] = { IRQ3_B_MARK, @@ -1734,56 +1791,56 @@ static const unsigned int intc_irq3_b_mux[] = { /* - LSBC ------------------------------------------------------------------- */ static const unsigned int lbsc_cs0_pins[] = { /* CS */ - 13, + RCAR_GP_PIN(0, 13), }; static const unsigned int lbsc_cs0_mux[] = { CS0_MARK, }; static const unsigned int lbsc_cs1_pins[] = { /* CS */ - 14, + RCAR_GP_PIN(0, 14), }; static const unsigned int lbsc_cs1_mux[] = { CS1_A26_MARK, }; static const unsigned int lbsc_ex_cs0_pins[] = { /* CS */ - 15, + RCAR_GP_PIN(0, 15), }; static const unsigned int lbsc_ex_cs0_mux[] = { EX_CS0_MARK, }; static const unsigned int lbsc_ex_cs1_pins[] = { /* CS */ - 16, + RCAR_GP_PIN(0, 16), }; static const unsigned int lbsc_ex_cs1_mux[] = { EX_CS1_MARK, }; static const unsigned int lbsc_ex_cs2_pins[] = { /* CS */ - 17, + RCAR_GP_PIN(0, 17), }; static const unsigned int lbsc_ex_cs2_mux[] = { EX_CS2_MARK, }; static const unsigned int lbsc_ex_cs3_pins[] = { /* CS */ - 18, + RCAR_GP_PIN(0, 18), }; static const unsigned int lbsc_ex_cs3_mux[] = { EX_CS3_MARK, }; static const unsigned int lbsc_ex_cs4_pins[] = { /* CS */ - 19, + RCAR_GP_PIN(0, 19), }; static const unsigned int lbsc_ex_cs4_mux[] = { EX_CS4_MARK, }; static const unsigned int lbsc_ex_cs5_pins[] = { /* CS */ - 20, + RCAR_GP_PIN(0, 20), }; static const unsigned int lbsc_ex_cs5_mux[] = { EX_CS5_MARK, @@ -1791,21 +1848,24 @@ static const unsigned int lbsc_ex_cs5_mux[] = { /* - MMCIF ------------------------------------------------------------------ */ static const unsigned int mmc0_data1_pins[] = { /* D[0] */ - 19, + RCAR_GP_PIN(0, 19), }; static const unsigned int mmc0_data1_mux[] = { MMC0_D0_MARK, }; static const unsigned int mmc0_data4_pins[] = { /* D[0:3] */ - 19, 20, 21, 2, + RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), + RCAR_GP_PIN(0, 2), }; static const unsigned int mmc0_data4_mux[] = { MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, }; static const unsigned int mmc0_data8_pins[] = { /* D[0:7] */ - 19, 20, 21, 2, 10, 11, 15, 16, + RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16), }; static const unsigned int mmc0_data8_mux[] = { MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, @@ -1813,28 +1873,31 @@ static const unsigned int mmc0_data8_mux[] = { }; static const unsigned int mmc0_ctrl_pins[] = { /* CMD, CLK */ - 18, 17, + RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17), }; static const unsigned int mmc0_ctrl_mux[] = { MMC0_CMD_MARK, MMC0_CLK_MARK, }; static const unsigned int mmc1_data1_pins[] = { /* D[0] */ - 72, + RCAR_GP_PIN(2, 8), }; static const unsigned int mmc1_data1_mux[] = { MMC1_D0_MARK, }; static const unsigned int mmc1_data4_pins[] = { /* D[0:3] */ - 72, 73, 74, 75, + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), + RCAR_GP_PIN(2, 11), }; static const unsigned int mmc1_data4_mux[] = { MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, }; static const unsigned int mmc1_data8_pins[] = { /* D[0:7] */ - 72, 73, 74, 75, 76, 77, 80, 81, + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), }; static const unsigned int mmc1_data8_mux[] = { MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, @@ -1842,7 +1905,7 @@ static const unsigned int mmc1_data8_mux[] = { }; static const unsigned int mmc1_ctrl_pins[] = { /* CMD, CLK */ - 68, 65, + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 1), }; static const unsigned int mmc1_ctrl_mux[] = { MMC1_CMD_MARK, MMC1_CLK_MARK, @@ -1850,84 +1913,84 @@ static const unsigned int mmc1_ctrl_mux[] = { /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RXD, TXD */ - 153, 152, + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), }; static const unsigned int scif0_data_mux[] = { RX0_MARK, TX0_MARK, }; static const unsigned int scif0_clk_pins[] = { /* SCK */ - 156, + RCAR_GP_PIN(4, 28), }; static const unsigned int scif0_clk_mux[] = { SCK0_MARK, }; static const unsigned int scif0_ctrl_pins[] = { /* RTS, CTS */ - 151, 150, + RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), }; static const unsigned int scif0_ctrl_mux[] = { RTS0_TANS_MARK, CTS0_MARK, }; static const unsigned int scif0_data_b_pins[] = { /* RXD, TXD */ - 20, 19, + RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), }; static const unsigned int scif0_data_b_mux[] = { RX0_B_MARK, TX0_B_MARK, }; static const unsigned int scif0_clk_b_pins[] = { /* SCK */ - 33, + RCAR_GP_PIN(1, 1), }; static const unsigned int scif0_clk_b_mux[] = { SCK0_B_MARK, }; static const unsigned int scif0_ctrl_b_pins[] = { /* RTS, CTS */ - 18, 11, + RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11), }; static const unsigned int scif0_ctrl_b_mux[] = { RTS0_B_TANS_B_MARK, CTS0_B_MARK, }; static const unsigned int scif0_data_c_pins[] = { /* RXD, TXD */ - 146, 147, + RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19), }; static const unsigned int scif0_data_c_mux[] = { RX0_C_MARK, TX0_C_MARK, }; static const unsigned int scif0_clk_c_pins[] = { /* SCK */ - 145, + RCAR_GP_PIN(4, 17), }; static const unsigned int scif0_clk_c_mux[] = { SCK0_C_MARK, }; static const unsigned int scif0_ctrl_c_pins[] = { /* RTS, CTS */ - 149, 148, + RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), }; static const unsigned int scif0_ctrl_c_mux[] = { RTS0_C_TANS_C_MARK, CTS0_C_MARK, }; static const unsigned int scif0_data_d_pins[] = { /* RXD, TXD */ - 43, 42, + RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), }; static const unsigned int scif0_data_d_mux[] = { RX0_D_MARK, TX0_D_MARK, }; static const unsigned int scif0_clk_d_pins[] = { /* SCK */ - 50, + RCAR_GP_PIN(1, 18), }; static const unsigned int scif0_clk_d_mux[] = { SCK0_D_MARK, }; static const unsigned int scif0_ctrl_d_pins[] = { /* RTS, CTS */ - 51, 35, + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 3), }; static const unsigned int scif0_ctrl_d_mux[] = { RTS0_D_TANS_D_MARK, CTS0_D_MARK, @@ -1935,63 +1998,63 @@ static const unsigned int scif0_ctrl_d_mux[] = { /* - SCIF1 ------------------------------------------------------------------ */ static const unsigned int scif1_data_pins[] = { /* RXD, TXD */ - 149, 148, + RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), }; static const unsigned int scif1_data_mux[] = { RX1_MARK, TX1_MARK, }; static const unsigned int scif1_clk_pins[] = { /* SCK */ - 145, + RCAR_GP_PIN(4, 17), }; static const unsigned int scif1_clk_mux[] = { SCK1_MARK, }; static const unsigned int scif1_ctrl_pins[] = { /* RTS, CTS */ - 147, 146, + RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18), }; static const unsigned int scif1_ctrl_mux[] = { RTS1_TANS_MARK, CTS1_MARK, }; static const unsigned int scif1_data_b_pins[] = { /* RXD, TXD */ - 117, 114, + RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 18), }; static const unsigned int scif1_data_b_mux[] = { RX1_B_MARK, TX1_B_MARK, }; static const unsigned int scif1_clk_b_pins[] = { /* SCK */ - 113, + RCAR_GP_PIN(3, 17), }; static const unsigned int scif1_clk_b_mux[] = { SCK1_B_MARK, }; static const unsigned int scif1_ctrl_b_pins[] = { /* RTS, CTS */ - 115, 116, + RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), }; static const unsigned int scif1_ctrl_b_mux[] = { RTS1_B_TANS_B_MARK, CTS1_B_MARK, }; static const unsigned int scif1_data_c_pins[] = { /* RXD, TXD */ - 67, 66, + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), }; static const unsigned int scif1_data_c_mux[] = { RX1_C_MARK, TX1_C_MARK, }; static const unsigned int scif1_clk_c_pins[] = { /* SCK */ - 86, + RCAR_GP_PIN(2, 22), }; static const unsigned int scif1_clk_c_mux[] = { SCK1_C_MARK, }; static const unsigned int scif1_ctrl_c_pins[] = { /* RTS, CTS */ - 69, 68, + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), }; static const unsigned int scif1_ctrl_c_mux[] = { RTS1_C_TANS_C_MARK, CTS1_C_MARK, @@ -1999,63 +2062,63 @@ static const unsigned int scif1_ctrl_c_mux[] = { /* - SCIF2 ------------------------------------------------------------------ */ static const unsigned int scif2_data_pins[] = { /* RXD, TXD */ - 106, 105, + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 9), }; static const unsigned int scif2_data_mux[] = { RX2_MARK, TX2_MARK, }; static const unsigned int scif2_clk_pins[] = { /* SCK */ - 107, + RCAR_GP_PIN(3, 11), }; static const unsigned int scif2_clk_mux[] = { SCK2_MARK, }; static const unsigned int scif2_data_b_pins[] = { /* RXD, TXD */ - 120, 119, + RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 23), }; static const unsigned int scif2_data_b_mux[] = { RX2_B_MARK, TX2_B_MARK, }; static const unsigned int scif2_clk_b_pins[] = { /* SCK */ - 118, + RCAR_GP_PIN(3, 22), }; static const unsigned int scif2_clk_b_mux[] = { SCK2_B_MARK, }; static const unsigned int scif2_data_c_pins[] = { /* RXD, TXD */ - 33, 31, + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(0, 31), }; static const unsigned int scif2_data_c_mux[] = { RX2_C_MARK, TX2_C_MARK, }; static const unsigned int scif2_clk_c_pins[] = { /* SCK */ - 32, + RCAR_GP_PIN(1, 0), }; static const unsigned int scif2_clk_c_mux[] = { SCK2_C_MARK, }; static const unsigned int scif2_data_d_pins[] = { /* RXD, TXD */ - 64, 62, + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30), }; static const unsigned int scif2_data_d_mux[] = { RX2_D_MARK, TX2_D_MARK, }; static const unsigned int scif2_clk_d_pins[] = { /* SCK */ - 63, + RCAR_GP_PIN(1, 31), }; static const unsigned int scif2_clk_d_mux[] = { SCK2_D_MARK, }; static const unsigned int scif2_data_e_pins[] = { /* RXD, TXD */ - 20, 19, + RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), }; static const unsigned int scif2_data_e_mux[] = { RX2_E_MARK, TX2_E_MARK, @@ -2063,14 +2126,14 @@ static const unsigned int scif2_data_e_mux[] = { /* - SCIF3 ------------------------------------------------------------------ */ static const unsigned int scif3_data_pins[] = { /* RXD, TXD */ - 137, 136, + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), }; static const unsigned int scif3_data_mux[] = { RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK, }; static const unsigned int scif3_clk_pins[] = { /* SCK */ - 135, + RCAR_GP_PIN(4, 7), }; static const unsigned int scif3_clk_mux[] = { SCK3_MARK, @@ -2078,35 +2141,35 @@ static const unsigned int scif3_clk_mux[] = { static const unsigned int scif3_data_b_pins[] = { /* RXD, TXD */ - 64, 62, + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30), }; static const unsigned int scif3_data_b_mux[] = { RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK, }; static const unsigned int scif3_data_c_pins[] = { /* RXD, TXD */ - 15, 12, + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 12), }; static const unsigned int scif3_data_c_mux[] = { RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK, }; static const unsigned int scif3_data_d_pins[] = { /* RXD, TXD */ - 30, 29, + RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 29), }; static const unsigned int scif3_data_d_mux[] = { RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK, }; static const unsigned int scif3_data_e_pins[] = { /* RXD, TXD */ - 35, 34, + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), }; static const unsigned int scif3_data_e_mux[] = { RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK, }; static const unsigned int scif3_clk_e_pins[] = { /* SCK */ - 42, + RCAR_GP_PIN(1, 10), }; static const unsigned int scif3_clk_e_mux[] = { SCK3_E_MARK, @@ -2114,42 +2177,42 @@ static const unsigned int scif3_clk_e_mux[] = { /* - SCIF4 ------------------------------------------------------------------ */ static const unsigned int scif4_data_pins[] = { /* RXD, TXD */ - 123, 122, + RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 26), }; static const unsigned int scif4_data_mux[] = { RX4_MARK, TX4_MARK, }; static const unsigned int scif4_clk_pins[] = { /* SCK */ - 121, + RCAR_GP_PIN(3, 25), }; static const unsigned int scif4_clk_mux[] = { SCK4_MARK, }; static const unsigned int scif4_data_b_pins[] = { /* RXD, TXD */ - 111, 110, + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), }; static const unsigned int scif4_data_b_mux[] = { RX4_B_MARK, TX4_B_MARK, }; static const unsigned int scif4_clk_b_pins[] = { /* SCK */ - 112, + RCAR_GP_PIN(3, 16), }; static const unsigned int scif4_clk_b_mux[] = { SCK4_B_MARK, }; static const unsigned int scif4_data_c_pins[] = { /* RXD, TXD */ - 22, 21, + RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21), }; static const unsigned int scif4_data_c_mux[] = { RX4_C_MARK, TX4_C_MARK, }; static const unsigned int scif4_data_d_pins[] = { /* RXD, TXD */ - 69, 68, + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), }; static const unsigned int scif4_data_d_mux[] = { RX4_D_MARK, TX4_D_MARK, @@ -2157,56 +2220,56 @@ static const unsigned int scif4_data_d_mux[] = { /* - SCIF5 ------------------------------------------------------------------ */ static const unsigned int scif5_data_pins[] = { /* RXD, TXD */ - 51, 50, + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), }; static const unsigned int scif5_data_mux[] = { RX5_MARK, TX5_MARK, }; static const unsigned int scif5_clk_pins[] = { /* SCK */ - 43, + RCAR_GP_PIN(1, 11), }; static const unsigned int scif5_clk_mux[] = { SCK5_MARK, }; static const unsigned int scif5_data_b_pins[] = { /* RXD, TXD */ - 18, 11, + RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11), }; static const unsigned int scif5_data_b_mux[] = { RX5_B_MARK, TX5_B_MARK, }; static const unsigned int scif5_clk_b_pins[] = { /* SCK */ - 19, + RCAR_GP_PIN(0, 19), }; static const unsigned int scif5_clk_b_mux[] = { SCK5_B_MARK, }; static const unsigned int scif5_data_c_pins[] = { /* RXD, TXD */ - 24, 23, + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), }; static const unsigned int scif5_data_c_mux[] = { RX5_C_MARK, TX5_C_MARK, }; static const unsigned int scif5_clk_c_pins[] = { /* SCK */ - 28, + RCAR_GP_PIN(0, 28), }; static const unsigned int scif5_clk_c_mux[] = { SCK5_C_MARK, }; static const unsigned int scif5_data_d_pins[] = { /* RXD, TXD */ - 8, 6, + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), }; static const unsigned int scif5_data_d_mux[] = { RX5_D_MARK, TX5_D_MARK, }; static const unsigned int scif5_clk_d_pins[] = { /* SCK */ - 7, + RCAR_GP_PIN(0, 7), }; static const unsigned int scif5_clk_d_mux[] = { SCK5_D_MARK, @@ -2214,35 +2277,36 @@ static const unsigned int scif5_clk_d_mux[] = { /* - SDHI0 ------------------------------------------------------------------ */ static const unsigned int sdhi0_data1_pins[] = { /* D0 */ - 117, + RCAR_GP_PIN(3, 21), }; static const unsigned int sdhi0_data1_mux[] = { SD0_DAT0_MARK, }; static const unsigned int sdhi0_data4_pins[] = { /* D[0:3] */ - 117, 118, 119, 120, + RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), + RCAR_GP_PIN(3, 24), }; static const unsigned int sdhi0_data4_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { /* CMD, CLK */ - 114, 113, + RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 17), }; static const unsigned int sdhi0_ctrl_mux[] = { SD0_CMD_MARK, SD0_CLK_MARK, }; static const unsigned int sdhi0_cd_pins[] = { /* CD */ - 115, + RCAR_GP_PIN(3, 19), }; static const unsigned int sdhi0_cd_mux[] = { SD0_CD_MARK, }; static const unsigned int sdhi0_wp_pins[] = { /* WP */ - 116, + RCAR_GP_PIN(3, 20), }; static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, @@ -2250,35 +2314,36 @@ static const unsigned int sdhi0_wp_mux[] = { /* - SDHI1 ------------------------------------------------------------------ */ static const unsigned int sdhi1_data1_pins[] = { /* D0 */ - 19, + RCAR_GP_PIN(0, 19), }; static const unsigned int sdhi1_data1_mux[] = { SD1_DAT0_MARK, }; static const unsigned int sdhi1_data4_pins[] = { /* D[0:3] */ - 19, 20, 21, 2, + RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), + RCAR_GP_PIN(0, 2), }; static const unsigned int sdhi1_data4_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; static const unsigned int sdhi1_ctrl_pins[] = { /* CMD, CLK */ - 18, 17, + RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17), }; static const unsigned int sdhi1_ctrl_mux[] = { SD1_CMD_MARK, SD1_CLK_MARK, }; static const unsigned int sdhi1_cd_pins[] = { /* CD */ - 10, + RCAR_GP_PIN(0, 10), }; static const unsigned int sdhi1_cd_mux[] = { SD1_CD_MARK, }; static const unsigned int sdhi1_wp_pins[] = { /* WP */ - 11, + RCAR_GP_PIN(0, 11), }; static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, @@ -2286,35 +2351,36 @@ static const unsigned int sdhi1_wp_mux[] = { /* - SDHI2 ------------------------------------------------------------------ */ static const unsigned int sdhi2_data1_pins[] = { /* D0 */ - 97, + RCAR_GP_PIN(3, 1), }; static const unsigned int sdhi2_data1_mux[] = { SD2_DAT0_MARK, }; static const unsigned int sdhi2_data4_pins[] = { /* D[0:3] */ - 97, 98, 99, 100, + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), }; static const unsigned int sdhi2_data4_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { /* CMD, CLK */ - 102, 101, + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5), }; static const unsigned int sdhi2_ctrl_mux[] = { SD2_CMD_MARK, SD2_CLK_MARK, }; static const unsigned int sdhi2_cd_pins[] = { /* CD */ - 103, + RCAR_GP_PIN(3, 7), }; static const unsigned int sdhi2_cd_mux[] = { SD2_CD_MARK, }; static const unsigned int sdhi2_wp_pins[] = { /* WP */ - 104, + RCAR_GP_PIN(3, 8), }; static const unsigned int sdhi2_wp_mux[] = { SD2_WP_MARK, @@ -2322,35 +2388,36 @@ static const unsigned int sdhi2_wp_mux[] = { /* - SDHI3 ------------------------------------------------------------------ */ static const unsigned int sdhi3_data1_pins[] = { /* D0 */ - 50, + RCAR_GP_PIN(1, 18), }; static const unsigned int sdhi3_data1_mux[] = { SD3_DAT0_MARK, }; static const unsigned int sdhi3_data4_pins[] = { /* D[0:3] */ - 50, 51, 52, 53, + RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 21), }; static const unsigned int sdhi3_data4_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, }; static const unsigned int sdhi3_ctrl_pins[] = { /* CMD, CLK */ - 35, 34, + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), }; static const unsigned int sdhi3_ctrl_mux[] = { SD3_CMD_MARK, SD3_CLK_MARK, }; static const unsigned int sdhi3_cd_pins[] = { /* CD */ - 62, + RCAR_GP_PIN(1, 30), }; static const unsigned int sdhi3_cd_mux[] = { SD3_CD_MARK, }; static const unsigned int sdhi3_wp_pins[] = { /* WP */ - 64, + RCAR_GP_PIN(2, 0), }; static const unsigned int sdhi3_wp_mux[] = { SD3_WP_MARK, @@ -2358,14 +2425,14 @@ static const unsigned int sdhi3_wp_mux[] = { /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { /* PENC */ - 154, + RCAR_GP_PIN(4, 26), }; static const unsigned int usb0_mux[] = { USB_PENC0_MARK, }; static const unsigned int usb0_ovc_pins[] = { /* USB_OVC */ - 150 + RCAR_GP_PIN(4, 22), }; static const unsigned int usb0_ovc_mux[] = { USB_OVC0_MARK, @@ -2373,14 +2440,14 @@ static const unsigned int usb0_ovc_mux[] = { /* - USB1 ------------------------------------------------------------------- */ static const unsigned int usb1_pins[] = { /* PENC */ - 155, + RCAR_GP_PIN(4, 27), }; static const unsigned int usb1_mux[] = { USB_PENC1_MARK, }; static const unsigned int usb1_ovc_pins[] = { /* USB_OVC */ - 152, + RCAR_GP_PIN(4, 24), }; static const unsigned int usb1_ovc_mux[] = { USB_OVC1_MARK, @@ -2388,18 +2455,122 @@ static const unsigned int usb1_ovc_mux[] = { /* - USB2 ------------------------------------------------------------------- */ static const unsigned int usb2_pins[] = { /* PENC */ - 156, + RCAR_GP_PIN(4, 28), }; static const unsigned int usb2_mux[] = { USB_PENC2_MARK, }; static const unsigned int usb2_ovc_pins[] = { /* USB_OVC */ - 125, + RCAR_GP_PIN(3, 29), }; static const unsigned int usb2_ovc_mux[] = { USB_OVC2_MARK, }; +/* - VIN0 ------------------------------------------------------------------- */ +static const unsigned int vin0_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), + RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), +}; +static const unsigned int vin0_data8_mux[] = { + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK, + VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, +}; +static const unsigned int vin0_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(2, 1), +}; +static const unsigned int vin0_clk_mux[] = { + VI0_CLK_MARK, +}; +static const unsigned int vin0_sync_pins[] = { + /* HSYNC, VSYNC */ + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), +}; +static const unsigned int vin0_sync_mux[] = { + VI0_HSYNC_MARK, VI0_VSYNC_MARK, +}; +/* - VIN1 ------------------------------------------------------------------- */ +static const unsigned int vin1_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), +}; +static const unsigned int vin1_data8_mux[] = { + VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK, + VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, + VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, +}; +static const unsigned int vin1_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(2, 30), +}; +static const unsigned int vin1_clk_mux[] = { + VI1_CLK_MARK, +}; +static const unsigned int vin1_sync_pins[] = { + /* HSYNC, VSYNC */ + RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0), +}; +static const unsigned int vin1_sync_mux[] = { + VI1_HSYNC_MARK, VI1_VSYNC_MARK, +}; +/* - VIN2 ------------------------------------------------------------------- */ +static const unsigned int vin2_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), + RCAR_GP_PIN(1, 31), RCAR_GP_PIN(2, 0), +}; +static const unsigned int vin2_data8_mux[] = { + VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK, + VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, + VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, +}; +static const unsigned int vin2_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(1, 30), +}; +static const unsigned int vin2_clk_mux[] = { + VI2_CLK_MARK, +}; +static const unsigned int vin2_sync_pins[] = { + /* HSYNC, VSYNC */ + RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29), +}; +static const unsigned int vin2_sync_mux[] = { + VI2_HSYNC_MARK, VI2_VSYNC_MARK, +}; +/* - VIN3 ------------------------------------------------------------------- */ +static const unsigned int vin3_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), +}; +static const unsigned int vin3_data8_mux[] = { + VI3_DATA0_MARK, VI3_DATA1_MARK, VI3_DATA2_MARK, + VI3_DATA3_MARK, VI3_DATA4_MARK, VI3_DATA5_MARK, + VI3_DATA6_MARK, VI3_DATA7_MARK, +}; +static const unsigned int vin3_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(2, 31), +}; +static const unsigned int vin3_clk_mux[] = { + VI3_CLK_MARK, +}; +static const unsigned int vin3_sync_pins[] = { + /* HSYNC, VSYNC */ + RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29), +}; +static const unsigned int vin3_sync_mux[] = { + VI3_HSYNC_MARK, VI3_VSYNC_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du0_rgb666), @@ -2419,6 +2590,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du1_sync_1), SH_PFC_PIN_GROUP(du1_oddf), SH_PFC_PIN_GROUP(du1_cde), + SH_PFC_PIN_GROUP(ether_rmii), + SH_PFC_PIN_GROUP(ether_link), + SH_PFC_PIN_GROUP(ether_magic), SH_PFC_PIN_GROUP(hspi0), SH_PFC_PIN_GROUP(hspi1), SH_PFC_PIN_GROUP(hspi1_b), @@ -2527,6 +2701,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(usb1_ovc), SH_PFC_PIN_GROUP(usb2), SH_PFC_PIN_GROUP(usb2_ovc), + SH_PFC_PIN_GROUP(vin0_data8), + SH_PFC_PIN_GROUP(vin0_clk), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin1_data8), + SH_PFC_PIN_GROUP(vin1_clk), + SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin2_data8), + SH_PFC_PIN_GROUP(vin2_clk), + SH_PFC_PIN_GROUP(vin2_sync), + SH_PFC_PIN_GROUP(vin3_data8), + SH_PFC_PIN_GROUP(vin3_clk), + SH_PFC_PIN_GROUP(vin3_sync), }; static const char * const du0_groups[] = { @@ -2552,6 +2738,12 @@ static const char * const du1_groups[] = { "du1_cde", }; +static const char * const ether_groups[] = { + "ether_rmii", + "ether_link", + "ether_magic", +}; + static const char * const hspi0_groups[] = { "hspi0", }; @@ -2720,9 +2912,34 @@ static const char * const usb2_groups[] = { "usb2_ovc", }; +static const char * const vin0_groups[] = { + "vin0_data8", + "vin0_clk", + "vin0_sync", +}; + +static const char * const vin1_groups[] = { + "vin1_data8", + "vin1_clk", + "vin1_sync", +}; + +static const char * const vin2_groups[] = { + "vin2_data8", + "vin2_clk", + "vin2_sync", +}; + +static const char * const vin3_groups[] = { + "vin3_data8", + "vin3_clk", + "vin3_sync", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), + SH_PFC_FUNCTION(ether), SH_PFC_FUNCTION(hspi0), SH_PFC_FUNCTION(hspi1), SH_PFC_FUNCTION(hspi2), @@ -2743,6 +2960,10 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb2), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), + SH_PFC_FUNCTION(vin2), + SH_PFC_FUNCTION(vin3), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -3547,7 +3768,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_SCIF [2] */ FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3, /* SEL_CANCLK [2] */ - FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 0, /* SEL_CAN0 [1] */ FN_SEL_CAN0_0, FN_SEL_CAN0_1, /* SEL_HSCIF1 [1] */ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c new file mode 100644 index 00000000000..14f3ec267e1 --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -0,0 +1,4014 @@ +/* + * R8A7790 processor support + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013 Magnus Damm + * Copyright (C) 2012 Renesas Solutions Corp. + * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/kernel.h> +#include <linux/platform_data/gpio-rcar.h> + +#include "core.h" +#include "sh_pfc.h" + +#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx) + +#define PORT_GP_32(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ + PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ + PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ + PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ + PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ + PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ + PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ + PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ + PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ + PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \ + PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx) + +#define PORT_GP_32_REV(bank, fn, sfx) \ + PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ + PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ + PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ + PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ + PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ + PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ + PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ + PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ + PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ + PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ + PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ + PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ + PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ + PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ + PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ + PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_32(0, fn, sfx), \ + PORT_GP_32(1, fn, sfx), \ + PORT_GP_32(2, fn, sfx), \ + PORT_GP_32(3, fn, sfx), \ + PORT_GP_32(4, fn, sfx), \ + PORT_GP_32(5, fn, sfx) + +#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx + +#define _GP_GPIO(bank, pin, _name, sfx) \ + [(bank * 32) + pin] = { \ + .name = __stringify(_name), \ + .enum_id = _name##_DATA, \ + } + +#define _GP_DATA(bank, pin, name, sfx) \ + PINMUX_DATA(name##_DATA, name##_FN) + +#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) + +#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) +#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ + FN_##ipsr, FN_##fn) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12, + FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27, + FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12, + FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26, + FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9, + FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22, + FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8, + FN_IP3_14_12, FN_IP3_17_15, + + /* GPSR1 */ + FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26, + FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9, + FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21, + FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6, + FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18, + FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0, + FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11, + + /* GPSR2 */ + FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4, + FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14, + FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22, + FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7, + FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23, + FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6, + FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13, + + /* GPSR3 */ + FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4, + FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18, + FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26, + FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11, + FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26, + FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9, + FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18, + + /* GPSR4 */ + FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30, + FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8, + FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20, + FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0, + FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13, + FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26, + FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9, + FN_IP14_15_12, FN_IP14_18_16, + + /* GPSR5 */ + FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28, + FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12, + FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20, + FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0, + FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7, + FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0, + FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22, + + /* IPSR0 */ + FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, + FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, + FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, + FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B, + FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4, + FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, + FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5, + FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, + FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6, + FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, + FN_SCL2_CIS_C, FN_D7, FN_AD_DI_B, FN_SDA2_C, + FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C, + FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0, + FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, + + /* IPSR1 */ + FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1, + FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10, + FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2, + FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11, + FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3, + FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, + FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, + FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, + FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, + FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14, + FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, + FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, + FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, + FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, + FN_A0, FN_PWM3, FN_A1, FN_PWM4, + + /* IPSR2 */ + FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3, + FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B, + FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, + FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7, + FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, + FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, + FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_VI2_DATA0_VI2_B0_B, + FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, + FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_VI2_DATA1_VI2_B1_B, + FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, + FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, + + /* IPSR3 */ + FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, + FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, + FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, + FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, + FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, + FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, + FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B, + FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B, + FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N, + FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18, + FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B, + FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK, + FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, + + /* IPSR4 */ + FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, + FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, + FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7, + FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3, + FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, + FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6, + FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N, + FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, + FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, + FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B, + FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B, + FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK, + FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B, + FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, + FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, + + /* IPSR5 */ + FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, + FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, + FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B, + FN_INTC_EN0_N, FN_SCL1_CIS, FN_EX_CS5_N, FN_CAN0_RX, + FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2, + FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N, + FN_SDA1_CIS, FN_BS_N, FN_IETX, FN_HTX1_B, + FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N, + FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3, + FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, + FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK, + FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, + FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, + FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, + FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, + FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, + FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N, + FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, + FN_SSI_WS78_B, + + /* IPSR6 */ + FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, + FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, + FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, + FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1, + FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C, + FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, + FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, + FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, + FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, + FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, + FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER, + FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, + FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0, + FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, + FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, + FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, + FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, + FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, + FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, + FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, + FN_STP_IVCXO27_1_B, FN_HRX0_F, + + /* IPSR7 */ + FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, + FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, + FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, + FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, + FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC, + FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0, + FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C, + FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, + FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0, + FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, + FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, + FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C, + FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, + FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN, + FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, + FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, + FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, + FN_MII_RXD2, + + /* IPSR8 */ + FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, + FN_MII_RXD3, FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, + FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, + FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, + FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, + FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, + FN_MII_RX_ER, FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, + FN_MII_RX_CLK, FN_VI1_CLK, FN_AVB_RX_DV, + FN_MII_RX_DV, FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, + FN_AVB_CRS, FN_MII_CRS, FN_VI1_DATA1_VI1_B1, + FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC, + FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, + FN_MII_MDIO, FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, + FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, + FN_AVB_MAGIC, FN_MII_MAGIC, FN_VI1_DATA5_VI1_B5, + FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, + FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD, + FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, + + /* IPSR9 */ + FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, + FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, + FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, + FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, + FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, + FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B, + FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP, + FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, + FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B, + FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, + FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD, + FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B, + FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, + FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK, + FN_MII_LINK, FN_SCIFB0_TXD_B, FN_SD1_DAT2, + FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B, + FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, + FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6, + FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, + FN_SCL2_D, FN_SCL2_CIS_D, FN_SIM0_CLK_B, + FN_VI3_CLK_B, + + /* IPSR10 */ + FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, + FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D, + FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, + FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, + FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, + FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, + FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, + FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, + FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, + FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, + FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA, + FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, + FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, + FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK, + FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, + FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3, + FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, + FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, + FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4, + FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, + FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, + FN_GLO_I0_B, FN_VI3_DATA6_B, + + /* IPSR11 */ + FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, + FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, + FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, + FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD, + FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, + FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2, + FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3, + FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, + FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP, + FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, + FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F, + FN_RDS_DATA_E, FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, + FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, + FN_SDA2_CIS_B, FN_MLB_DAT, FN_SPV_EVEN, + FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, + FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B, + FN_MOUT0, + + /* IPSR12 */ + FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, + FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, + FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, + FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, + FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, + FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34, + FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, + FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0, + FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, + FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, + FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, + FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, + FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, + FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, + FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK, + FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, + FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD, + FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, + FN_CAN_DEBUGOUT4, + + /* IPSR13 */ + FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, + FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6, + FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C, + FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, + FN_BPFCLK_F, FN_RDS_CLK_E, FN_SSI_WS6, + FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, + FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6, + FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5, + FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1, + FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6, + FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1, + FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7, + FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7, + FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, + FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, + FN_BPFCLK_E, FN_RDS_CLK_D, FN_SSI_SDATA7_B, + FN_FMIN_G, FN_RDS_DATA_F, FN_SSI_SDATA8, + FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, + FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9, + FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, + FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA, + FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, + + /* IPSR14 */ + FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, + FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, + FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, + FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_SDA1_C, + FN_SDA1_CIS_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0, + FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1, + FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N, + FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3, + FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C, + FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS, + FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, + FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, + FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, + FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, + FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK, + FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK, + FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS, + FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, + FN_HRTS0_N_C, + + /* IPSR15 */ + FN_SCIFA2_SCK, FN_FMCLK, FN_MSIOF3_SCK, FN_DU2_DG7, + FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN, + FN_DU2_DB0, FN_LCDOUT16, FN_SCL2, FN_SCL2_CIS, + FN_SCIFA2_TXD, FN_BPFCLK, FN_DU2_DB1, FN_LCDOUT17, + FN_SDA2, FN_SDA2_CIS, FN_HSCK0, FN_TS_SDEN0, + FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0, + FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3, + FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, + FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, + FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, + FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0, + FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23, + FN_SCIFA2_RXD_B, FN_MSIOF0_SS1, FN_ADICHS0, + FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1, + FN_DU2_DG6, FN_LCDOUT14, + + /* IPSR16 */ + FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, + FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, + FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, + FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C, + FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC, + FN_TCLK1_B, + + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + FN_SEL_SCIF1_4, + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, + FN_SEL_SCIFB1_4, + FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6, + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3, + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + FN_SEL_SOF1_0, FN_SEL_SOF1_1, + FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, + FN_SEL_SSI6_0, FN_SEL_SSI6_1, + FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, + FN_SEL_VI3_0, FN_SEL_VI3_1, + FN_SEL_VI2_0, FN_SEL_VI2_1, + FN_SEL_VI1_0, FN_SEL_VI1_1, + FN_SEL_VI0_0, FN_SEL_VI0_1, + FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, + FN_SEL_LBS_0, FN_SEL_LBS_1, + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + FN_SEL_SOF3_0, FN_SEL_SOF3_1, + FN_SEL_SOF0_0, FN_SEL_SOF0_1, + + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, + FN_SEL_CAN1_0, FN_SEL_CAN1_1, + FN_SEL_ADI_0, FN_SEL_ADI_1, + FN_SEL_SSP_0, FN_SEL_SSP_1, + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, + FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3, + FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, + FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, + FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, + FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, + FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, + + FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, + FN_SEL_IIC0_0, FN_SEL_IIC0_1, + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + FN_SEL_IIC2_4, + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, + FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, + FN_SEL_I2C2_4, + FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + VI1_DATA7_VI1_B7_MARK, + + USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, + USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK, + DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK, + + D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK, + D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK, + VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK, + VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK, + VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK, + SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK, + VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK, + SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK, + VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK, + SCL2_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, + SCL2_CIS_C_MARK, D7_MARK, AD_DI_B_MARK, SDA2_C_MARK, + VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, SDA2_CIS_C_MARK, + D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK, + VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, + + D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, MII_TXD1_MARK, + VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK, + SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, MII_TXD2_MARK, + VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK, + SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, MII_TXD3_MARK, + VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK, + D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK, + VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK, + D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK, + VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK, + SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK, + VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK, + D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK, + VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK, + A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK, + + A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK, + PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK, + TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK, + A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK, + SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK, + A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK, + VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, VI2_DATA0_VI2_B0_B_MARK, + A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK, + VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, VI2_DATA1_VI2_B1_B_MARK, + A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK, + VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK, + + A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK, + VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK, + A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK, + VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK, + A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK, + MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK, + VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK, + ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK, + ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK, + A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK, + AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK, + ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK, + VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK, + + A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK, + A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK, + VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK, + VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK, + VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK, + VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK, + VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK, + VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK, + CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK, + VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK, + VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK, + MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK, + HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK, + VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK, + VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK, + + EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK, + VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK, + EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK, + VI2_HSYNC_N_MARK, SCL1_MARK, VI2_HSYNC_N_B_MARK, + INTC_EN0_N_MARK, SCL1_CIS_MARK, EX_CS5_N_MARK, CAN0_RX_MARK, + MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK, + VI1_G2_B_MARK, VI2_R4_MARK, SDA1_MARK, INTC_EN1_N_MARK, + SDA1_CIS_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK, + CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, + CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, + VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, + INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, + VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK, + WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK, + VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK, + IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK, + VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK, + MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK, + VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK, + SSI_WS78_B_MARK, + + DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, + VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, + DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, + SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK, + INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, + DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, + MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, + SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, + ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK, + TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK, + SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK, + STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, + SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK, + STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, + SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, + RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK, + TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK, + RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK, + STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK, + ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK, + STP_IVCXO27_1_B_MARK, HRX0_F_MARK, + + ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK, + SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, + RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK, + ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK, + HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK, + SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK, + STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK, + ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK, + TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK, + SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK, + GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, + STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK, + PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, + PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK, + AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, + ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK, + VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, + MII_RXD2_MARK, + + VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK, + MII_RXD3_MARK, VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK, + AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK, + AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK, + AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK, + AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK, + MII_RX_ER_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK, + MII_RX_CLK_MARK, VI1_CLK_MARK, AVB_RX_DV_MARK, + MII_RX_DV_MARK, VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK, + AVB_CRS_MARK, MII_CRS_MARK, VI1_DATA1_VI1_B1_MARK, + SCIFA1_RXD_D_MARK, AVB_MDC_MARK, MII_MDC_MARK, + VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK, + MII_MDIO_MARK, VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK, + AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK, + AVB_MAGIC_MARK, MII_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK, + AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK, + SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK, + SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK, + + SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK, + SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK, + SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK, + SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK, + SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK, + GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, SCL1_B_MARK, + SCL1_CIS_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK, + MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK, + GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, SDA1_B_MARK, + SDA1_CIS_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, + AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK, + AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK, + SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK, + SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK, + MII_LINK_MARK, SCIFB0_TXD_B_MARK, SD1_DAT2_MARK, + AVB_COL_MARK, MII_COL_MARK, SCIFB0_CTS_N_B_MARK, + SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK, + SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK, + TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK, + SCL2_D_MARK, SCL2_CIS_D_MARK, SIM0_CLK_B_MARK, + VI3_CLK_B_MARK, + + SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK, + GLO_RFON_MARK, VI1_CLK_B_MARK, SDA2_D_MARK, SDA2_CIS_D_MARK, + SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK, + VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK, + VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK, + VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK, + TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK, + SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK, + VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK, + TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK, + SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, RDS_DATA_MARK, + VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK, + TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK, + SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, RDS_CLK_MARK, + VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK, + GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK, + MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK, + HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK, + VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK, + TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK, + VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK, + GLO_I0_B_MARK, VI3_DATA6_B_MARK, + + SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK, + GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK, + TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK, + SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK, + MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK, + SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK, + MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK, + SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK, + VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK, + MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK, + RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK, + RDS_DATA_E_MARK, MLB_CLK_MARK, SCL2_B_MARK, SCL2_CIS_B_MARK, + MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, SDA2_B_MARK, + SDA2_CIS_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK, + SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK, + RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK, + MOUT0_MARK, + + SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK, + SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK, + SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK, + SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK, + SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK, + MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK, + STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK, + CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK, + SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK, + SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK, + MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK, + SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK, + MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK, + SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK, + CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK, + IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK, + CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK, + IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK, + CAN_DEBUGOUT4_MARK, + + SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK, + LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK, + SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, RDS_CLK_C_MARK, + DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK, + BPFCLK_F_MARK, RDS_CLK_E_MARK, SSI_WS6_MARK, + SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK, + LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK, + FMIN_D_MARK, RDS_DATA_C_MARK, DU2_DR5_MARK, LCDOUT5_MARK, + CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK, + SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK, + CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK, + SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK, + LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK, + STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK, + TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK, + BPFCLK_E_MARK, RDS_CLK_D_MARK, SSI_SDATA7_B_MARK, + FMIN_G_MARK, RDS_DATA_F_MARK, SSI_SDATA8_MARK, + STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK, + CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK, + STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK, + SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK, + SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK, + + AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK, + DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK, + REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK, + MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, SDA1_C_MARK, + SDA1_CIS_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK, + DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK, + TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK, + HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK, + LCDOUT11_MARK, PWM0_B_MARK, SCL1_C_MARK, SCL1_CIS_C_MARK, + SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK, + MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK, + SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK, + DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, + SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK, + LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK, + CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK, + SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_TANS_MARK, + MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK, + HRTS0_N_C_MARK, + + SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, + LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK, + DU2_DB0_MARK, LCDOUT16_MARK, SCL2_MARK, SCL2_CIS_MARK, + SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK, + SDA2_MARK, SDA2_CIS_MARK, HSCK0_MARK, TS_SDEN0_MARK, + DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK, + DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK, + LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK, + LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK, + LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK, + DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK, + SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK, + SCIFA2_RXD_B_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK, + DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK, + DU2_DG6_MARK, LCDOUT14_MARK, + + MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK, + DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK, + MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK, + ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, HRX0_C_MARK, + USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK, + TCLK1_B_MARK, + PINMUX_MARK_END, +}; + +static const pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7), + PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), + PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS), + PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN), + PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC), + PINMUX_DATA(AVS1_MARK, FN_AVS1), + PINMUX_DATA(AVS2_MARK, FN_AVS2), + PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0), + PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2), + + PINMUX_IPSR_DATA(IP0_2_0, D0), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1), + PINMUX_IPSR_DATA(IP0_5_3, D1), + PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1), + PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1), + PINMUX_IPSR_DATA(IP0_8_6, D2), + PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1), + PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1), + PINMUX_IPSR_DATA(IP0_11_9, D3), + PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1), + PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1), + PINMUX_IPSR_DATA(IP0_15_12, D4), + PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5), + PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2), + PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1), + PINMUX_IPSR_DATA(IP0_19_16, D5), + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5), + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2), + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1), + PINMUX_IPSR_DATA(IP0_22_20, D6), + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_C, SEL_IIC2_2), + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_CIS_C, SEL_I2C2_2), + PINMUX_IPSR_DATA(IP0_26_23, D7), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_C, SEL_IIC2_2), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_CIS_C, SEL_I2C2_2), + PINMUX_IPSR_DATA(IP0_30_27, D8), + PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0), + PINMUX_IPSR_DATA(IP0_30_27, MII_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0), + + PINMUX_IPSR_DATA(IP1_3_0, D9), + PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1), + PINMUX_IPSR_DATA(IP1_3_0, MII_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_7_4, D10), + PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2), + PINMUX_IPSR_DATA(IP1_7_4, MII_TXD2), + PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_11_8, D11), + PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3), + PINMUX_IPSR_DATA(IP1_11_8, MII_TXD3), + PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_14_12, D12), + PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4), + PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_17_15, D13), + PINMUX_IPSR_MODSEL_DATA(IP1_17_15, AVB_TXD5, SEL_SCIFA1_2), + PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_21_18, D14), + PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2), + PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6), + PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_25_22, D15), + PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2), + PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7), + PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_27_26, A0), + PINMUX_IPSR_DATA(IP1_27_26, PWM3), + PINMUX_IPSR_DATA(IP1_29_28, A1), + PINMUX_IPSR_DATA(IP1_29_28, PWM4), + + PINMUX_IPSR_DATA(IP2_2_0, A2), + PINMUX_IPSR_DATA(IP2_2_0, PWM5), + PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1), + PINMUX_IPSR_DATA(IP2_5_3, A3), + PINMUX_IPSR_DATA(IP2_5_3, PWM6), + PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1), + PINMUX_IPSR_DATA(IP2_8_6, A4), + PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1), + PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0), + PINMUX_IPSR_DATA(IP2_11_9, A5), + PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1), + PINMUX_IPSR_DATA(IP2_14_12, A6), + PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1), + PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2), + PINMUX_IPSR_DATA(IP2_17_15, A7), + PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1), + PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B), + PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3), + PINMUX_IPSR_DATA(IP2_21_18, A8), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP2_25_22, A9), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP2_28_26, A10), + PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1), + PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC), + PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1), + + PINMUX_IPSR_DATA(IP3_3_0, A11), + PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1), + PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK), + PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP3_3_0, VI2_G0), + PINMUX_IPSR_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B), + PINMUX_IPSR_DATA(IP3_7_4, A12), + PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1), + PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD), + PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP3_7_4, VI2_G1), + PINMUX_IPSR_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B), + PINMUX_IPSR_DATA(IP3_11_8, A13), + PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1), + PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2), + PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD), + PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP3_11_8, VI2_G2), + PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_0), + PINMUX_IPSR_DATA(IP3_14_12, A14), + PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1), + PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N), + PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1), + PINMUX_IPSR_DATA(IP3_17_15, A15), + PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1), + PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N), + PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2), + PINMUX_IPSR_DATA(IP3_19_18, A16), + PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N), + PINMUX_IPSR_DATA(IP3_22_20, A17), + PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N), + PINMUX_IPSR_DATA(IP3_25_23, A18), + PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N), + PINMUX_IPSR_DATA(IP3_28_26, A19), + PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N), + PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1), + PINMUX_IPSR_DATA(IP3_31_29, A20), + PINMUX_IPSR_DATA(IP3_31_29, SPCLK), + PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP3_31_29, VI2_G4), + + PINMUX_IPSR_DATA(IP4_2_0, A21), + PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0), + PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_2_0, VI2_G5), + PINMUX_IPSR_DATA(IP4_5_3, A22), + PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1), + PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_5_3, VI2_G6), + PINMUX_IPSR_DATA(IP4_8_6, A23), + PINMUX_IPSR_DATA(IP4_8_6, IO2), + PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_8_6, VI2_G7), + PINMUX_IPSR_DATA(IP4_11_9, A24), + PINMUX_IPSR_DATA(IP4_11_9, IO3), + PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0), + PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP4_14_12, A25), + PINMUX_IPSR_DATA(IP4_14_12, SSL), + PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0), + PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP4_17_15, CS0_N), + PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_17_15, VI2_G3), + PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26), + PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN), + PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0), + PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N), + PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_23_21, VI2_R0), + PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N), + PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK), + PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_26_24, VI2_R1), + PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N), + PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN), + PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB), + PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_29_27, VI2_R2), + + PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N), + PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG), + PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD), + PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP5_2_0, VI2_R3), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, EX_CS4_N, SEL_I2C1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1), + PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1, SEL_IIC1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1_CIS, SEL_I2C1_0), + PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1), + PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP5_9_6, VI2_R4), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1, SEL_IIC1_0), + PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1_CIS, SEL_I2C1_0), + PINMUX_IPSR_DATA(IP5_12_10, BS_N), + PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0), + PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0), + PINMUX_IPSR_DATA(IP5_12_10, DRACK0), + PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP5_14_13, RD_N), + PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0), + PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1), + PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N), + PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP5_17_15, VI2_R5), + PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1), + PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N), + PINMUX_IPSR_DATA(IP5_20_18, WE0_N), + PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0), + PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0), + PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0), + PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1), + PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP5_23_21, WE1_N), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP5_23_21, VI2_R6), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP5_26_24, EX_WAIT0), + PINMUX_IPSR_DATA(IP5_26_24, IRQ3), + PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N), + PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1), + PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N), + PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP5_29_27, VI2_R7), + PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2), + PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1), + + PINMUX_IPSR_DATA(IP6_2_0, DACK0), + PINMUX_IPSR_DATA(IP6_2_0, IRQ0), + PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2), + PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP6_8_6, DACK1), + PINMUX_IPSR_DATA(IP6_8_6, IRQ1), + PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N), + PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), + PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N), + PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP6_13_11, DACK2), + PINMUX_IPSR_DATA(IP6_13_11, IRQ2), + PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N), + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV), + PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4), + PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER), + PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4), + PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0), + PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1), + PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK), + PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK), + PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5), + + PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO), + PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1), + PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN), + PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC), + PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2), + PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0), + PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC), + PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_18_16, PWM0), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_21_19, PWM1), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N), + PINMUX_IPSR_DATA(IP7_24_22, PWM2), + PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0), + PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2), + PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N), + PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN), + PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC), + PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C), + PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0), + PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N), + PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1), + PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), + PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N), + PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2), + PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2), + + PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N), + PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3), + PINMUX_IPSR_DATA(IP8_1_0, MII_RXD3), + PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N), + PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4), + PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N), + PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5), + PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N), + PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6), + PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1), + PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7), + PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER), + PINMUX_IPSR_DATA(IP8_11_10, MII_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK), + PINMUX_IPSR_DATA(IP8_13_12, MII_RX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0), + PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV), + PINMUX_IPSR_DATA(IP8_15_14, MII_RX_DV), + PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS), + PINMUX_IPSR_DATA(IP8_17_16, MII_CRS), + PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC), + PINMUX_IPSR_DATA(IP8_19_18, MII_MDC), + PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO), + PINMUX_IPSR_DATA(IP8_21_20, MII_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC), + PINMUX_IPSR_DATA(IP8_25_24, MII_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3), + PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), + PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK), + PINMUX_IPSR_DATA(IP8_28, SD0_CLK), + PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD), + PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1), + + PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0), + PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1), + PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2), + PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3), + PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP9_11_8, SD0_CD), + PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1), + PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_B, SEL_IIC1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_CIS_B, SEL_I2C1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP9_15_12, SD0_WP), + PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1), + PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_B, SEL_IIC1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_CIS_B, SEL_I2C1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK), + PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN), + PINMUX_IPSR_DATA(IP9_17_16, MII_TX_EN), + PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD), + PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER), + PINMUX_IPSR_DATA(IP9_19_18, MII_TX_ER), + PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0), + PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK), + PINMUX_IPSR_DATA(IP9_21_20, MII_TX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1), + PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK), + PINMUX_IPSR_DATA(IP9_23_22, MII_LINK), + PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2), + PINMUX_IPSR_DATA(IP9_25_24, AVB_COL), + PINMUX_IPSR_DATA(IP9_25_24, MII_COL), + PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3), + PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0), + PINMUX_IPSR_DATA(IP9_27_26, MII_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_31_28, SD1_CD), + PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0), + PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_CIS_D, SEL_I2C2_3), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1), + + PINMUX_IPSR_DATA(IP10_3_0, SD1_WP), + PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0), + PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_CIS_D, SEL_I2C2_3), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1), + PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK), + PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD), + PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0), + PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1), + PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, RDS_DATA, SEL_RDS_0), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2), + PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, RDS_CLK, SEL_RDS_0), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3), + PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_29_26, SD2_CD), + PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1), + PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1), + + PINMUX_IPSR_DATA(IP11_3_0, SD2_WP), + PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1), + PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP11_4, SD3_CLK), + PINMUX_IPSR_DATA(IP11_4, MMC1_CLK), + PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD), + PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD), + PINMUX_IPSR_DATA(IP11_6_5, MTS_N), + PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0), + PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0), + PINMUX_IPSR_DATA(IP11_8_7, STM_N), + PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1), + PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1), + PINMUX_IPSR_DATA(IP11_10_9, MDATA), + PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2), + PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2), + PINMUX_IPSR_DATA(IP11_12_11, SDATA), + PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3), + PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3), + PINMUX_IPSR_DATA(IP11_14_13, SCKZ), + PINMUX_IPSR_DATA(IP11_17_15, SD3_CD), + PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4), + PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0), + PINMUX_IPSR_DATA(IP11_17_15, VSP), + PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1), + PINMUX_IPSR_DATA(IP11_21_18, SD3_WP), + PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_B, SEL_RDS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_D, SEL_RDS_3), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4), + PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK), + PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_B, SEL_IIC2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_CIS_B, SEL_I2C2_1), + PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_B, SEL_IIC2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_CIS_B, SEL_I2C2_1), + PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT), + PINMUX_IPSR_DATA(IP11_29_27, SPV_EVEN), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RDS_CLK_B, SEL_RDS_1), + PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129), + PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1), + PINMUX_IPSR_DATA(IP11_31_30, MOUT0), + + PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129), + PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1), + PINMUX_IPSR_DATA(IP12_1_0, MOUT1), + PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0), + PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_DATA(IP12_3_2, MOUT2), + PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1), + PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1), + PINMUX_IPSR_DATA(IP12_5_4, MOUT5), + PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2), + PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1), + PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_TX_B, SEL_CAN1_1), + PINMUX_IPSR_DATA(IP12_7_6, MOUT6), + PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34), + PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0), + PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0), + PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER), + PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34), + PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0), + PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC), + PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0), + PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3), + PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0), + PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK), + PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4), + PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2), + PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0), + PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4), + PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2), + PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1), + PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4), + PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0), + PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2), + PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC), + PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS), + PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3), + PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC), + PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE), + PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4), + + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2), + PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2), + PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5), + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0), + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3), + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_C, SEL_RDS_2), + PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3), + PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3), + PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6), + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5), + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_E, SEL_RDS_4), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3), + PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4), + PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4), + PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7), + PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3), + PINMUX_IPSR_MODSEL_DATA(IP13_12_10, RDS_DATA_C, SEL_RDS_2), + PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5), + PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5), + PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8), + PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0), + PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6), + PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6), + PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0), + PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N), + PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7), + PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7), + PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0), + PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N), + PINMUX_IPSR_DATA(IP13_22_19, TCLK2), + PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS), + PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_CLK_D, SEL_RDS_3), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_DATA_F, SEL_RDS_5), + PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0), + PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0), + PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2), + PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12), + PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1), + PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9), + PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0), + PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1), + PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2), + PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13), + PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA), + PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0), + PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14), + + PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB), + PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0), + PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3), + PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE), + PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2), + PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15), + PINMUX_IPSR_DATA(IP14_2_0, REMOCON), + PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0), + PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0), + PINMUX_IPSR_DATA(IP14_5_3, SCK0), + PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2), + PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2), + PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10), + PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_C, SEL_IIC1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_CIS_C, SEL_I2C1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0), + PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0), + PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0), + PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0), + PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0), + PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0), + PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1), + PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, CTS0_N, SEL_SCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0), + PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, LCDOUT11, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, PWM0_B, SEL_SCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_C, SEL_IIC1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_CIS_C, SEL_I2C1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), + PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), + PINMUX_IPSR_DATA(IP14_18_16, RTS0_N_TANS), + PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1), + PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0), + PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8), + PINMUX_IPSR_DATA(IP14_18_16, PWM1_B), + PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE), + PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1), + PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9), + PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0), + PINMUX_IPSR_DATA(IP14_27_25, CTS1_N), + PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0), + PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT), + PINMUX_IPSR_DATA(IP14_27_25, QCLK), + PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0), + PINMUX_IPSR_DATA(IP14_30_28, RTS1_N_TANS), + PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0), + PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT), + PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE), + PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2), + + PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0), + PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0), + PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7), + PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15), + PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0), + PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0), + PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2, SEL_IIC2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2_CIS, SEL_I2C2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0), + PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1), + PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2, SEL_IIC2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2_CIS, SEL_I2C2_0), + PINMUX_IPSR_DATA(IP15_11_9, HSCK0), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4), + PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_IIC2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SDA2_CIS, SEL_I2C2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2), + PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18), + PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3), + PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19), + PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9), + PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4), + PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20), + PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9), + PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5), + PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21), + PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP15_22_20, ADICLK), + PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6), + PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22), + PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC), + PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2), + PINMUX_IPSR_DATA(IP15_25_23, ADIDATA), + PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7), + PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23), + PINMUX_IPSR_MODSEL_DATA(IP15_25_23, SCIFA2_RXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0), + PINMUX_IPSR_DATA(IP15_27_26, ADICHS0), + PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5), + PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13), + PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0), + PINMUX_IPSR_DATA(IP15_29_28, ADICHS1), + PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6), + PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14), + + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0), + PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT), + PINMUX_IPSR_DATA(IP16_2_0, ADICHS2), + PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP), + PINMUX_IPSR_DATA(IP16_2_0, QPOLA), + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2), + PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP), + PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE), + PINMUX_IPSR_DATA(IP16_5_3, QPOLB), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HRX0_C, SEL_HSCIF0_2), + PINMUX_IPSR_DATA(IP16_6, USB1_PWEN), + PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D), + PINMUX_IPSR_DATA(IP16_7, USB1_OVC), + PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1), +}; + +static struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), +}; + +/* - ETH -------------------------------------------------------------------- */ +static const unsigned int eth_link_pins[] = { + /* LINK */ + RCAR_GP_PIN(2, 22), +}; +static const unsigned int eth_link_mux[] = { + ETH_LINK_MARK, +}; +static const unsigned int eth_magic_pins[] = { + /* MAGIC */ + RCAR_GP_PIN(2, 27), +}; +static const unsigned int eth_magic_mux[] = { + ETH_MAGIC_MARK, +}; +static const unsigned int eth_mdio_pins[] = { + /* MDC, MDIO */ + RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24), +}; +static const unsigned int eth_mdio_mux[] = { + ETH_MDC_MARK, ETH_MDIO_MARK, +}; +static const unsigned int eth_rmii_pins[] = { + /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ + RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19), + RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25), + RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23), +}; +static const unsigned int eth_rmii_mux[] = { + ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, + ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, +}; +/* - INTC ------------------------------------------------------------------- */ +static const unsigned int intc_irq0_pins[] = { + /* IRQ */ + RCAR_GP_PIN(1, 25), +}; +static const unsigned int intc_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_irq1_pins[] = { + /* IRQ */ + RCAR_GP_PIN(1, 27), +}; +static const unsigned int intc_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_irq2_pins[] = { + /* IRQ */ + RCAR_GP_PIN(1, 29), +}; +static const unsigned int intc_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_irq3_pins[] = { + /* IRQ */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int intc_irq3_mux[] = { + IRQ3_MARK, +}; +/* - SCIF0 ----------------------------------------------------------------- */ +static const unsigned int scif0_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), +}; +static const unsigned int scif0_data_mux[] = { + RX0_MARK, TX0_MARK, +}; +static const unsigned int scif0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 27), +}; +static const unsigned int scif0_clk_mux[] = { + SCK0_MARK, +}; +static const unsigned int scif0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), +}; +static const unsigned int scif0_ctrl_mux[] = { + RTS0_N_TANS_MARK, CTS0_N_MARK, +}; +static const unsigned int scif0_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), +}; +static const unsigned int scif0_data_b_mux[] = { + RX0_B_MARK, TX0_B_MARK, +}; +/* - SCIF1 ----------------------------------------------------------------- */ +static const unsigned int scif1_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), +}; +static const unsigned int scif1_data_mux[] = { + RX1_MARK, TX1_MARK, +}; +static const unsigned int scif1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 20), +}; +static const unsigned int scif1_clk_mux[] = { + SCK1_MARK, +}; +static const unsigned int scif1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), +}; +static const unsigned int scif1_ctrl_mux[] = { + RTS1_N_TANS_MARK, CTS1_N_MARK, +}; +static const unsigned int scif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), +}; +static const unsigned int scif1_data_b_mux[] = { + RX1_B_MARK, TX1_B_MARK, +}; +static const unsigned int scif1_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), +}; +static const unsigned int scif1_data_c_mux[] = { + RX1_C_MARK, TX1_C_MARK, +}; +static const unsigned int scif1_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), +}; +static const unsigned int scif1_data_d_mux[] = { + RX1_D_MARK, TX1_D_MARK, +}; +static const unsigned int scif1_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 17), +}; +static const unsigned int scif1_clk_d_mux[] = { + SCK1_D_MARK, +}; +static const unsigned int scif1_data_e_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), +}; +static const unsigned int scif1_data_e_mux[] = { + RX1_E_MARK, TX1_E_MARK, +}; +static const unsigned int scif1_clk_e_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 20), +}; +static const unsigned int scif1_clk_e_mux[] = { + SCK1_E_MARK, +}; +/* - HSCIF0 ----------------------------------------------------------------- */ +static const unsigned int hscif0_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), +}; +static const unsigned int hscif0_data_mux[] = { + HRX0_MARK, HTX0_MARK, +}; +static const unsigned int hscif0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 7), +}; +static const unsigned int hscif0_clk_mux[] = { + HSCK0_MARK, +}; +static const unsigned int hscif0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), +}; +static const unsigned int hscif0_ctrl_mux[] = { + HRTS0_N_MARK, HCTS0_N_MARK, +}; +static const unsigned int hscif0_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12), +}; +static const unsigned int hscif0_data_b_mux[] = { + HRX0_B_MARK, HTX0_B_MARK, +}; +static const unsigned int hscif0_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), +}; +static const unsigned int hscif0_ctrl_b_mux[] = { + HRTS0_N_B_MARK, HCTS0_N_B_MARK, +}; +static const unsigned int hscif0_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), +}; +static const unsigned int hscif0_data_c_mux[] = { + HRX0_C_MARK, HTX0_C_MARK, +}; +static const unsigned int hscif0_ctrl_c_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7), +}; +static const unsigned int hscif0_ctrl_c_mux[] = { + HRTS0_N_C_MARK, HCTS0_N_C_MARK, +}; +static const unsigned int hscif0_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), +}; +static const unsigned int hscif0_data_d_mux[] = { + HRX0_D_MARK, HTX0_D_MARK, +}; +static const unsigned int hscif0_ctrl_d_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), +}; +static const unsigned int hscif0_ctrl_d_mux[] = { + HRTS0_N_D_MARK, HCTS0_N_D_MARK, +}; +static const unsigned int hscif0_data_e_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), +}; +static const unsigned int hscif0_data_e_mux[] = { + HRX0_E_MARK, HTX0_E_MARK, +}; +static const unsigned int hscif0_ctrl_e_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23), +}; +static const unsigned int hscif0_ctrl_e_mux[] = { + HRTS0_N_E_MARK, HCTS0_N_E_MARK, +}; +static const unsigned int hscif0_data_f_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25), +}; +static const unsigned int hscif0_data_f_mux[] = { + HRX0_F_MARK, HTX0_F_MARK, +}; +static const unsigned int hscif0_ctrl_f_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24), +}; +static const unsigned int hscif0_ctrl_f_mux[] = { + HRTS0_N_F_MARK, HCTS0_N_F_MARK, +}; +/* - HSCIF1 ----------------------------------------------------------------- */ +static const unsigned int hscif1_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), +}; +static const unsigned int hscif1_data_mux[] = { + HRX1_MARK, HTX1_MARK, +}; +static const unsigned int hscif1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 27), +}; +static const unsigned int hscif1_clk_mux[] = { + HSCK1_MARK, +}; +static const unsigned int hscif1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), +}; +static const unsigned int hscif1_ctrl_mux[] = { + HRTS1_N_MARK, HCTS1_N_MARK, +}; +static const unsigned int hscif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18), +}; +static const unsigned int hscif1_data_b_mux[] = { + HRX1_B_MARK, HTX1_B_MARK, +}; +static const unsigned int hscif1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 28), +}; +static const unsigned int hscif1_clk_b_mux[] = { + HSCK1_B_MARK, +}; +static const unsigned int hscif1_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), +}; +static const unsigned int hscif1_ctrl_b_mux[] = { + HRTS1_N_B_MARK, HCTS1_N_B_MARK, +}; +/* - SCIFA0 ----------------------------------------------------------------- */ +static const unsigned int scifa0_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), +}; +static const unsigned int scifa0_data_mux[] = { + SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, +}; +static const unsigned int scifa0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 27), +}; +static const unsigned int scifa0_clk_mux[] = { + SCIFA0_SCK_MARK, +}; +static const unsigned int scifa0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), +}; +static const unsigned int scifa0_ctrl_mux[] = { + SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK, +}; +static const unsigned int scifa0_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21), +}; +static const unsigned int scifa0_data_b_mux[] = { + SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK +}; +static const unsigned int scifa0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 19), +}; +static const unsigned int scifa0_clk_b_mux[] = { + SCIFA0_SCK_B_MARK, +}; +static const unsigned int scifa0_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), +}; +static const unsigned int scifa0_ctrl_b_mux[] = { + SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK, +}; +/* - SCIFA1 ----------------------------------------------------------------- */ +static const unsigned int scifa1_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), +}; +static const unsigned int scifa1_data_mux[] = { + SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, +}; +static const unsigned int scifa1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 20), +}; +static const unsigned int scifa1_clk_mux[] = { + SCIFA1_SCK_MARK, +}; +static const unsigned int scifa1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), +}; +static const unsigned int scifa1_ctrl_mux[] = { + SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK, +}; +static const unsigned int scifa1_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21), +}; +static const unsigned int scifa1_data_b_mux[] = { + SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, +}; +static const unsigned int scifa1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 23), +}; +static const unsigned int scifa1_clk_b_mux[] = { + SCIFA1_SCK_B_MARK, +}; +static const unsigned int scifa1_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25), +}; +static const unsigned int scifa1_ctrl_b_mux[] = { + SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK, +}; +static const unsigned int scifa1_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), +}; +static const unsigned int scifa1_data_c_mux[] = { + SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, +}; +static const unsigned int scifa1_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 8), +}; +static const unsigned int scifa1_clk_c_mux[] = { + SCIFA1_SCK_C_MARK, +}; +static const unsigned int scifa1_ctrl_c_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), +}; +static const unsigned int scifa1_ctrl_c_mux[] = { + SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK, +}; +static const unsigned int scifa1_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), +}; +static const unsigned int scifa1_data_d_mux[] = { + SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK, +}; +static const unsigned int scifa1_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 10), +}; +static const unsigned int scifa1_clk_d_mux[] = { + SCIFA1_SCK_D_MARK, +}; +static const unsigned int scifa1_ctrl_d_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), +}; +static const unsigned int scifa1_ctrl_d_mux[] = { + SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK, +}; +/* - SCIFA2 ----------------------------------------------------------------- */ +static const unsigned int scifa2_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +}; +static const unsigned int scifa2_data_mux[] = { + SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, +}; +static const unsigned int scifa2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 4), +}; +static const unsigned int scifa2_clk_mux[] = { + SCIFA2_SCK_MARK, +}; +static const unsigned int scifa2_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), +}; +static const unsigned int scifa2_ctrl_mux[] = { + SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK, +}; +static const unsigned int scifa2_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), +}; +static const unsigned int scifa2_data_b_mux[] = { + SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, +}; +static const unsigned int scifa2_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), +}; +static const unsigned int scifa2_data_c_mux[] = { + SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK, +}; +static const unsigned int scifa2_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 29), +}; +static const unsigned int scifa2_clk_c_mux[] = { + SCIFA2_SCK_C_MARK, +}; +/* - SCIFB0 ----------------------------------------------------------------- */ +static const unsigned int scifb0_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), +}; +static const unsigned int scifb0_data_mux[] = { + SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, +}; +static const unsigned int scifb0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 8), +}; +static const unsigned int scifb0_clk_mux[] = { + SCIFB0_SCK_MARK, +}; +static const unsigned int scifb0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), +}; +static const unsigned int scifb0_ctrl_mux[] = { + SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, +}; +static const unsigned int scifb0_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), +}; +static const unsigned int scifb0_data_b_mux[] = { + SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK, +}; +static const unsigned int scifb0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 9), +}; +static const unsigned int scifb0_clk_b_mux[] = { + SCIFB0_SCK_B_MARK, +}; +static const unsigned int scifb0_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), +}; +static const unsigned int scifb0_ctrl_b_mux[] = { + SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK, +}; +static const unsigned int scifb0_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), +}; +static const unsigned int scifb0_data_c_mux[] = { + SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK, +}; +/* - SCIFB1 ----------------------------------------------------------------- */ +static const unsigned int scifb1_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), +}; +static const unsigned int scifb1_data_mux[] = { + SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, +}; +static const unsigned int scifb1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 14), +}; +static const unsigned int scifb1_clk_mux[] = { + SCIFB1_SCK_MARK, +}; +static const unsigned int scifb1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), +}; +static const unsigned int scifb1_ctrl_mux[] = { + SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK, +}; +static const unsigned int scifb1_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), +}; +static const unsigned int scifb1_data_b_mux[] = { + SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK, +}; +static const unsigned int scifb1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 1), +}; +static const unsigned int scifb1_clk_b_mux[] = { + SCIFB1_SCK_B_MARK, +}; +static const unsigned int scifb1_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4), +}; +static const unsigned int scifb1_ctrl_b_mux[] = { + SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK, +}; +static const unsigned int scifb1_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), +}; +static const unsigned int scifb1_data_c_mux[] = { + SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK, +}; +static const unsigned int scifb1_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), +}; +static const unsigned int scifb1_data_d_mux[] = { + SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK, +}; +static const unsigned int scifb1_data_e_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), +}; +static const unsigned int scifb1_data_e_mux[] = { + SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK, +}; +static const unsigned int scifb1_clk_e_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 17), +}; +static const unsigned int scifb1_clk_e_mux[] = { + SCIFB1_SCK_E_MARK, +}; +static const unsigned int scifb1_data_f_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), +}; +static const unsigned int scifb1_data_f_mux[] = { + SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK, +}; +static const unsigned int scifb1_data_g_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), +}; +static const unsigned int scifb1_data_g_mux[] = { + SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK, +}; +static const unsigned int scifb1_clk_g_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 20), +}; +static const unsigned int scifb1_clk_g_mux[] = { + SCIFB1_SCK_G_MARK, +}; +/* - SCIFB2 ----------------------------------------------------------------- */ +static const unsigned int scifb2_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), +}; +static const unsigned int scifb2_data_mux[] = { + SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, +}; +static const unsigned int scifb2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 21), +}; +static const unsigned int scifb2_clk_mux[] = { + SCIFB2_SCK_MARK, +}; +static const unsigned int scifb2_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), +}; +static const unsigned int scifb2_ctrl_mux[] = { + SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, +}; +static const unsigned int scifb2_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30), +}; +static const unsigned int scifb2_data_b_mux[] = { + SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK, +}; +static const unsigned int scifb2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 31), +}; +static const unsigned int scifb2_clk_b_mux[] = { + SCIFB2_SCK_B_MARK, +}; +static const unsigned int scifb2_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27), +}; +static const unsigned int scifb2_ctrl_b_mux[] = { + SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK, +}; +static const unsigned int scifb2_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), +}; +static const unsigned int scifb2_data_c_mux[] = { + SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, +}; +/* - TPU0 ------------------------------------------------------------------- */ +static const unsigned int tpu0_to0_pins[] = { + /* TO */ + RCAR_GP_PIN(0, 20), +}; +static const unsigned int tpu0_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu0_to1_pins[] = { + /* TO */ + RCAR_GP_PIN(0, 21), +}; +static const unsigned int tpu0_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu0_to2_pins[] = { + /* TO */ + RCAR_GP_PIN(0, 22), +}; +static const unsigned int tpu0_to2_mux[] = { + TPU0TO2_MARK, +}; +static const unsigned int tpu0_to3_pins[] = { + /* TO */ + RCAR_GP_PIN(0, 23), +}; +static const unsigned int tpu0_to3_mux[] = { + TPU0TO3_MARK, +}; +/* - MMCIF0 ----------------------------------------------------------------- */ +static const unsigned int mmc0_data1_pins[] = { + /* D[0] */ + RCAR_GP_PIN(3, 18), +}; +static const unsigned int mmc0_data1_mux[] = { + MMC0_D0_MARK, +}; +static const unsigned int mmc0_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), + RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), +}; +static const unsigned int mmc0_data4_mux[] = { + MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, +}; +static const unsigned int mmc0_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), + RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), + RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), +}; +static const unsigned int mmc0_data8_mux[] = { + MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, + MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, +}; +static const unsigned int mmc0_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), +}; +static const unsigned int mmc0_ctrl_mux[] = { + MMC0_CLK_MARK, MMC0_CMD_MARK, +}; +/* - MMCIF1 ----------------------------------------------------------------- */ +static const unsigned int mmc1_data1_pins[] = { + /* D[0] */ + RCAR_GP_PIN(3, 26), +}; +static const unsigned int mmc1_data1_mux[] = { + MMC1_D0_MARK, +}; +static const unsigned int mmc1_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), + RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), +}; +static const unsigned int mmc1_data4_mux[] = { + MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, +}; +static const unsigned int mmc1_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), + RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), + RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), +}; +static const unsigned int mmc1_data8_mux[] = { + MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, + MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, +}; +static const unsigned int mmc1_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), +}; +static const unsigned int mmc1_ctrl_mux[] = { + MMC1_CLK_MARK, MMC1_CMD_MARK, +}; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 2), +}; +static const unsigned int sdhi0_data1_mux[] = { + SD0_DAT0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), +}; +static const unsigned int sdhi0_data4_mux[] = { + SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SD0_CLK_MARK, SD0_CMD_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 6), +}; +static const unsigned int sdhi0_cd_mux[] = { + SD0_CD_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 7), +}; +static const unsigned int sdhi0_wp_mux[] = { + SD0_WP_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 10), +}; +static const unsigned int sdhi1_data1_mux[] = { + SD1_DAT0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), +}; +static const unsigned int sdhi1_data4_mux[] = { + SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SD1_CLK_MARK, SD1_CMD_MARK, +}; +static const unsigned int sdhi1_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 14), +}; +static const unsigned int sdhi1_cd_mux[] = { + SD1_CD_MARK, +}; +static const unsigned int sdhi1_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 15), +}; +static const unsigned int sdhi1_wp_mux[] = { + SD1_WP_MARK, +}; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 18), +}; +static const unsigned int sdhi2_data1_mux[] = { + SD2_DAT0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), +}; +static const unsigned int sdhi2_data4_mux[] = { + SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SD2_CLK_MARK, SD2_CMD_MARK, +}; +static const unsigned int sdhi2_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 22), +}; +static const unsigned int sdhi2_cd_mux[] = { + SD2_CD_MARK, +}; +static const unsigned int sdhi2_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 23), +}; +static const unsigned int sdhi2_wp_mux[] = { + SD2_WP_MARK, +}; +/* - SDHI3 ------------------------------------------------------------------ */ +static const unsigned int sdhi3_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 26), +}; +static const unsigned int sdhi3_data1_mux[] = { + SD3_DAT0_MARK, +}; +static const unsigned int sdhi3_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), +}; +static const unsigned int sdhi3_data4_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, +}; +static const unsigned int sdhi3_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), +}; +static const unsigned int sdhi3_ctrl_mux[] = { + SD3_CLK_MARK, SD3_CMD_MARK, +}; +static const unsigned int sdhi3_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 30), +}; +static const unsigned int sdhi3_cd_mux[] = { + SD3_CD_MARK, +}; +static const unsigned int sdhi3_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 31), +}; +static const unsigned int sdhi3_wp_mux[] = { + SD3_WP_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(eth_link), + SH_PFC_PIN_GROUP(eth_magic), + SH_PFC_PIN_GROUP(eth_mdio), + SH_PFC_PIN_GROUP(eth_rmii), + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif0_data_b), + SH_PFC_PIN_GROUP(hscif0_ctrl_b), + SH_PFC_PIN_GROUP(hscif0_data_c), + SH_PFC_PIN_GROUP(hscif0_ctrl_c), + SH_PFC_PIN_GROUP(hscif0_data_d), + SH_PFC_PIN_GROUP(hscif0_ctrl_d), + SH_PFC_PIN_GROUP(hscif0_data_e), + SH_PFC_PIN_GROUP(hscif0_ctrl_e), + SH_PFC_PIN_GROUP(hscif0_data_f), + SH_PFC_PIN_GROUP(hscif0_ctrl_f), + SH_PFC_PIN_GROUP(hscif1_data), + SH_PFC_PIN_GROUP(hscif1_clk), + SH_PFC_PIN_GROUP(hscif1_ctrl), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(intc_irq0), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2), + SH_PFC_PIN_GROUP(intc_irq3), + SH_PFC_PIN_GROUP(mmc0_data1), + SH_PFC_PIN_GROUP(mmc0_data4), + SH_PFC_PIN_GROUP(mmc0_data8), + SH_PFC_PIN_GROUP(mmc0_ctrl), + SH_PFC_PIN_GROUP(mmc1_data1), + SH_PFC_PIN_GROUP(mmc1_data4), + SH_PFC_PIN_GROUP(mmc1_data8), + SH_PFC_PIN_GROUP(mmc1_ctrl), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif1_data), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_data_c), + SH_PFC_PIN_GROUP(scif1_data_d), + SH_PFC_PIN_GROUP(scif1_clk_d), + SH_PFC_PIN_GROUP(scif1_data_e), + SH_PFC_PIN_GROUP(scif1_clk_e), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_clk), + SH_PFC_PIN_GROUP(scifa0_ctrl), + SH_PFC_PIN_GROUP(scifa0_data_b), + SH_PFC_PIN_GROUP(scifa0_clk_b), + SH_PFC_PIN_GROUP(scifa0_ctrl_b), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_ctrl), + SH_PFC_PIN_GROUP(scifa1_data_b), + SH_PFC_PIN_GROUP(scifa1_clk_b), + SH_PFC_PIN_GROUP(scifa1_ctrl_b), + SH_PFC_PIN_GROUP(scifa1_data_c), + SH_PFC_PIN_GROUP(scifa1_clk_c), + SH_PFC_PIN_GROUP(scifa1_ctrl_c), + SH_PFC_PIN_GROUP(scifa1_data_d), + SH_PFC_PIN_GROUP(scifa1_clk_d), + SH_PFC_PIN_GROUP(scifa1_ctrl_d), + SH_PFC_PIN_GROUP(scifa2_data), + SH_PFC_PIN_GROUP(scifa2_clk), + SH_PFC_PIN_GROUP(scifa2_ctrl), + SH_PFC_PIN_GROUP(scifa2_data_b), + SH_PFC_PIN_GROUP(scifa2_data_c), + SH_PFC_PIN_GROUP(scifa2_clk_c), + SH_PFC_PIN_GROUP(scifb0_data), + SH_PFC_PIN_GROUP(scifb0_clk), + SH_PFC_PIN_GROUP(scifb0_ctrl), + SH_PFC_PIN_GROUP(scifb0_data_b), + SH_PFC_PIN_GROUP(scifb0_clk_b), + SH_PFC_PIN_GROUP(scifb0_ctrl_b), + SH_PFC_PIN_GROUP(scifb0_data_c), + SH_PFC_PIN_GROUP(scifb1_data), + SH_PFC_PIN_GROUP(scifb1_clk), + SH_PFC_PIN_GROUP(scifb1_ctrl), + SH_PFC_PIN_GROUP(scifb1_data_b), + SH_PFC_PIN_GROUP(scifb1_clk_b), + SH_PFC_PIN_GROUP(scifb1_ctrl_b), + SH_PFC_PIN_GROUP(scifb1_data_c), + SH_PFC_PIN_GROUP(scifb1_data_d), + SH_PFC_PIN_GROUP(scifb1_data_e), + SH_PFC_PIN_GROUP(scifb1_clk_e), + SH_PFC_PIN_GROUP(scifb1_data_f), + SH_PFC_PIN_GROUP(scifb1_data_g), + SH_PFC_PIN_GROUP(scifb1_clk_g), + SH_PFC_PIN_GROUP(scifb2_data), + SH_PFC_PIN_GROUP(scifb2_clk), + SH_PFC_PIN_GROUP(scifb2_ctrl), + SH_PFC_PIN_GROUP(scifb2_data_b), + SH_PFC_PIN_GROUP(scifb2_clk_b), + SH_PFC_PIN_GROUP(scifb2_ctrl_b), + SH_PFC_PIN_GROUP(scifb2_data_c), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd), + SH_PFC_PIN_GROUP(sdhi2_wp), + SH_PFC_PIN_GROUP(sdhi3_data1), + SH_PFC_PIN_GROUP(sdhi3_data4), + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), + SH_PFC_PIN_GROUP(tpu0_to0), + SH_PFC_PIN_GROUP(tpu0_to1), + SH_PFC_PIN_GROUP(tpu0_to2), + SH_PFC_PIN_GROUP(tpu0_to3), +}; + +static const char * const eth_groups[] = { + "eth_link", + "eth_magic", + "eth_mdio", + "eth_rmii", +}; + +static const char * const intc_groups[] = { + "intc_irq0", + "intc_irq1", + "intc_irq2", + "intc_irq3", +}; + +static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk", + "scif0_ctrl", + "scif0_data_b", +}; + +static const char * const scif1_groups[] = { + "scif1_data", + "scif1_clk", + "scif1_ctrl", + "scif1_data_b", + "scif1_data_c", + "scif1_data_d", + "scif1_clk_d", + "scif1_data_e", + "scif1_clk_e", +}; + +static const char * const hscif0_groups[] = { + "hscif0_data", + "hscif0_clk", + "hscif0_ctrl", + "hscif0_data_b", + "hscif0_ctrl_b", + "hscif0_data_c", + "hscif0_ctrl_c", + "hscif0_data_d", + "hscif0_ctrl_d", + "hscif0_data_e", + "hscif0_ctrl_e", + "hscif0_data_f", + "hscif0_ctrl_f", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data", + "hscif1_clk", + "hscif1_ctrl", + "hscif1_data_b", + "hscif1_clk_b", + "hscif1_ctrl_b", +}; + +static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_clk", + "scifa0_ctrl", + "scifa0_data_b", + "scifa0_clk_b", + "scifa0_ctrl_b", +}; + +static const char * const scifa1_groups[] = { + "scifa1_data", + "scifa1_clk", + "scifa1_ctrl", + "scifa1_data_b", + "scifa1_clk_b", + "scifa1_ctrl_b", + "scifa1_data_c", + "scifa1_clk_c", + "scifa1_ctrl_c", + "scifa1_data_d", + "scifa1_clk_d", + "scifa1_ctrl_d", +}; + +static const char * const scifa2_groups[] = { + "scifa2_data", + "scifa2_clk", + "scifa2_ctrl", + "scifa2_data_b", + "scifa2_data_c", + "scifa2_clk_c", +}; + +static const char * const scifb0_groups[] = { + "scifb0_data", + "scifb0_clk", + "scifb0_ctrl", + "scifb0_data_b", + "scifb0_clk_b", + "scifb0_ctrl_b", + "scifb0_data_c", +}; + +static const char * const scifb1_groups[] = { + "scifb1_data", + "scifb1_clk", + "scifb1_ctrl", + "scifb1_data_b", + "scifb1_clk_b", + "scifb1_ctrl_b", + "scifb1_data_c", + "scifb1_data_d", + "scifb1_data_e", + "scifb1_clk_e", + "scifb1_data_f", + "scifb1_data_g", + "scifb1_clk_g", +}; + +static const char * const scifb2_groups[] = { + "scifb2_data", + "scifb2_clk", + "scifb2_ctrl", + "scifb2_data_b", + "scifb2_clk_b", + "scifb2_ctrl_b", + "scifb2_data_c", +}; + +static const char * const tpu0_groups[] = { + "tpu0_to0", + "tpu0_to1", + "tpu0_to2", + "tpu0_to3", +}; + +static const char * const mmc0_groups[] = { + "mmc0_data1", + "mmc0_data4", + "mmc0_data8", + "mmc0_ctrl", +}; + +static const char * const mmc1_groups[] = { + "mmc1_data1", + "mmc1_data4", + "mmc1_data8", + "mmc1_ctrl", +}; + +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", + "sdhi1_cd", + "sdhi1_wp", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_ctrl", + "sdhi2_cd", + "sdhi2_wp", +}; + +static const char * const sdhi3_groups[] = { + "sdhi3_data1", + "sdhi3_data4", + "sdhi3_ctrl", + "sdhi3_cd", + "sdhi3_wp", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(mmc1), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifb0), + SH_PFC_FUNCTION(scifb1), + SH_PFC_FUNCTION(scifb2), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), + SH_PFC_FUNCTION(tpu0), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + GP_0_31_FN, FN_IP3_17_15, + GP_0_30_FN, FN_IP3_14_12, + GP_0_29_FN, FN_IP3_11_8, + GP_0_28_FN, FN_IP3_7_4, + GP_0_27_FN, FN_IP3_3_0, + GP_0_26_FN, FN_IP2_28_26, + GP_0_25_FN, FN_IP2_25_22, + GP_0_24_FN, FN_IP2_21_18, + GP_0_23_FN, FN_IP2_17_15, + GP_0_22_FN, FN_IP2_14_12, + GP_0_21_FN, FN_IP2_11_9, + GP_0_20_FN, FN_IP2_8_6, + GP_0_19_FN, FN_IP2_5_3, + GP_0_18_FN, FN_IP2_2_0, + GP_0_17_FN, FN_IP1_29_28, + GP_0_16_FN, FN_IP1_27_26, + GP_0_15_FN, FN_IP1_25_22, + GP_0_14_FN, FN_IP1_21_18, + GP_0_13_FN, FN_IP1_17_15, + GP_0_12_FN, FN_IP1_14_12, + GP_0_11_FN, FN_IP1_11_8, + GP_0_10_FN, FN_IP1_7_4, + GP_0_9_FN, FN_IP1_3_0, + GP_0_8_FN, FN_IP0_30_27, + GP_0_7_FN, FN_IP0_26_23, + GP_0_6_FN, FN_IP0_22_20, + GP_0_5_FN, FN_IP0_19_16, + GP_0_4_FN, FN_IP0_15_12, + GP_0_3_FN, FN_IP0_11_9, + GP_0_2_FN, FN_IP0_8_6, + GP_0_1_FN, FN_IP0_5_3, + GP_0_0_FN, FN_IP0_2_0 } + }, + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + 0, 0, + 0, 0, + GP_1_29_FN, FN_IP6_13_11, + GP_1_28_FN, FN_IP6_10_9, + GP_1_27_FN, FN_IP6_8_6, + GP_1_26_FN, FN_IP6_5_3, + GP_1_25_FN, FN_IP6_2_0, + GP_1_24_FN, FN_IP5_29_27, + GP_1_23_FN, FN_IP5_26_24, + GP_1_22_FN, FN_IP5_23_21, + GP_1_21_FN, FN_IP5_20_18, + GP_1_20_FN, FN_IP5_17_15, + GP_1_19_FN, FN_IP5_14_13, + GP_1_18_FN, FN_IP5_12_10, + GP_1_17_FN, FN_IP5_9_6, + GP_1_16_FN, FN_IP5_5_3, + GP_1_15_FN, FN_IP5_2_0, + GP_1_14_FN, FN_IP4_29_27, + GP_1_13_FN, FN_IP4_26_24, + GP_1_12_FN, FN_IP4_23_21, + GP_1_11_FN, FN_IP4_20_18, + GP_1_10_FN, FN_IP4_17_15, + GP_1_9_FN, FN_IP4_14_12, + GP_1_8_FN, FN_IP4_11_9, + GP_1_7_FN, FN_IP4_8_6, + GP_1_6_FN, FN_IP4_5_3, + GP_1_5_FN, FN_IP4_2_0, + GP_1_4_FN, FN_IP3_31_29, + GP_1_3_FN, FN_IP3_28_26, + GP_1_2_FN, FN_IP3_25_23, + GP_1_1_FN, FN_IP3_22_20, + GP_1_0_FN, FN_IP3_19_18, } + }, + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + 0, 0, + 0, 0, + GP_2_29_FN, FN_IP7_15_13, + GP_2_28_FN, FN_IP7_12_10, + GP_2_27_FN, FN_IP7_9_8, + GP_2_26_FN, FN_IP7_7_6, + GP_2_25_FN, FN_IP7_5_3, + GP_2_24_FN, FN_IP7_2_0, + GP_2_23_FN, FN_IP6_31_29, + GP_2_22_FN, FN_IP6_28_26, + GP_2_21_FN, FN_IP6_25_23, + GP_2_20_FN, FN_IP6_22_20, + GP_2_19_FN, FN_IP6_19_17, + GP_2_18_FN, FN_IP6_16_14, + GP_2_17_FN, FN_VI1_DATA7_VI1_B7, + GP_2_16_FN, FN_IP8_27, + GP_2_15_FN, FN_IP8_26, + GP_2_14_FN, FN_IP8_25_24, + GP_2_13_FN, FN_IP8_23_22, + GP_2_12_FN, FN_IP8_21_20, + GP_2_11_FN, FN_IP8_19_18, + GP_2_10_FN, FN_IP8_17_16, + GP_2_9_FN, FN_IP8_15_14, + GP_2_8_FN, FN_IP8_13_12, + GP_2_7_FN, FN_IP8_11_10, + GP_2_6_FN, FN_IP8_9_8, + GP_2_5_FN, FN_IP8_7_6, + GP_2_4_FN, FN_IP8_5_4, + GP_2_3_FN, FN_IP8_3_2, + GP_2_2_FN, FN_IP8_1_0, + GP_2_1_FN, FN_IP7_30_29, + GP_2_0_FN, FN_IP7_28_27 } + }, + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + GP_3_31_FN, FN_IP11_21_18, + GP_3_30_FN, FN_IP11_17_15, + GP_3_29_FN, FN_IP11_14_13, + GP_3_28_FN, FN_IP11_12_11, + GP_3_27_FN, FN_IP11_10_9, + GP_3_26_FN, FN_IP11_8_7, + GP_3_25_FN, FN_IP11_6_5, + GP_3_24_FN, FN_IP11_4, + GP_3_23_FN, FN_IP11_3_0, + GP_3_22_FN, FN_IP10_29_26, + GP_3_21_FN, FN_IP10_25_23, + GP_3_20_FN, FN_IP10_22_19, + GP_3_19_FN, FN_IP10_18_15, + GP_3_18_FN, FN_IP10_14_11, + GP_3_17_FN, FN_IP10_10_7, + GP_3_16_FN, FN_IP10_6_4, + GP_3_15_FN, FN_IP10_3_0, + GP_3_14_FN, FN_IP9_31_28, + GP_3_13_FN, FN_IP9_27_26, + GP_3_12_FN, FN_IP9_25_24, + GP_3_11_FN, FN_IP9_23_22, + GP_3_10_FN, FN_IP9_21_20, + GP_3_9_FN, FN_IP9_19_18, + GP_3_8_FN, FN_IP9_17_16, + GP_3_7_FN, FN_IP9_15_12, + GP_3_6_FN, FN_IP9_11_8, + GP_3_5_FN, FN_IP9_7_6, + GP_3_4_FN, FN_IP9_5_4, + GP_3_3_FN, FN_IP9_3_2, + GP_3_2_FN, FN_IP9_1_0, + GP_3_1_FN, FN_IP8_30_29, + GP_3_0_FN, FN_IP8_28 } + }, + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + GP_4_31_FN, FN_IP14_18_16, + GP_4_30_FN, FN_IP14_15_12, + GP_4_29_FN, FN_IP14_11_9, + GP_4_28_FN, FN_IP14_8_6, + GP_4_27_FN, FN_IP14_5_3, + GP_4_26_FN, FN_IP14_2_0, + GP_4_25_FN, FN_IP13_30_29, + GP_4_24_FN, FN_IP13_28_26, + GP_4_23_FN, FN_IP13_25_23, + GP_4_22_FN, FN_IP13_22_19, + GP_4_21_FN, FN_IP13_18_16, + GP_4_20_FN, FN_IP13_15_13, + GP_4_19_FN, FN_IP13_12_10, + GP_4_18_FN, FN_IP13_9_7, + GP_4_17_FN, FN_IP13_6_3, + GP_4_16_FN, FN_IP13_2_0, + GP_4_15_FN, FN_IP12_30_28, + GP_4_14_FN, FN_IP12_27_25, + GP_4_13_FN, FN_IP12_24_23, + GP_4_12_FN, FN_IP12_22_20, + GP_4_11_FN, FN_IP12_19_17, + GP_4_10_FN, FN_IP12_16_14, + GP_4_9_FN, FN_IP12_13_11, + GP_4_8_FN, FN_IP12_10_8, + GP_4_7_FN, FN_IP12_7_6, + GP_4_6_FN, FN_IP12_5_4, + GP_4_5_FN, FN_IP12_3_2, + GP_4_4_FN, FN_IP12_1_0, + GP_4_3_FN, FN_IP11_31_30, + GP_4_2_FN, FN_IP11_29_27, + GP_4_1_FN, FN_IP11_26_24, + GP_4_0_FN, FN_IP11_23_22 } + }, + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + GP_5_31_FN, FN_IP7_24_22, + GP_5_30_FN, FN_IP7_21_19, + GP_5_29_FN, FN_IP7_18_16, + GP_5_28_FN, FN_DU_DOTCLKIN2, + GP_5_27_FN, FN_IP7_26_25, + GP_5_26_FN, FN_DU_DOTCLKIN0, + GP_5_25_FN, FN_AVS2, + GP_5_24_FN, FN_AVS1, + GP_5_23_FN, FN_USB2_OVC, + GP_5_22_FN, FN_USB2_PWEN, + GP_5_21_FN, FN_IP16_7, + GP_5_20_FN, FN_IP16_6, + GP_5_19_FN, FN_USB0_OVC_VBUS, + GP_5_18_FN, FN_USB0_PWEN, + GP_5_17_FN, FN_IP16_5_3, + GP_5_16_FN, FN_IP16_2_0, + GP_5_15_FN, FN_IP15_29_28, + GP_5_14_FN, FN_IP15_27_26, + GP_5_13_FN, FN_IP15_25_23, + GP_5_12_FN, FN_IP15_22_20, + GP_5_11_FN, FN_IP15_19_18, + GP_5_10_FN, FN_IP15_17_16, + GP_5_9_FN, FN_IP15_15_14, + GP_5_8_FN, FN_IP15_13_12, + GP_5_7_FN, FN_IP15_11_9, + GP_5_6_FN, FN_IP15_8_6, + GP_5_5_FN, FN_IP15_5_3, + GP_5_4_FN, FN_IP15_2_0, + GP_5_3_FN, FN_IP14_30_28, + GP_5_2_FN, FN_IP14_27_25, + GP_5_1_FN, FN_IP14_24_22, + GP_5_0_FN, FN_IP14_21_19 } + }, + { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, + 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) { + /* IP0_31 [1] */ + 0, 0, + /* IP0_30_27 [4] */ + FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0, + FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_26_23 [4] */ + FN_D7, FN_AD_DI_B, FN_SDA2_C, + FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_22_20 [3] */ + FN_D6, FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, + FN_SCL2_CIS_C, 0, 0, + /* IP0_19_16 [4] */ + FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, + FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_15_12 [4] */ + FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, + FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_11_9 [3] */ + FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, + 0, 0, 0, + /* IP0_8_6 [3] */ + FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B, + 0, 0, 0, + /* IP0_5_3 [3] */ + FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B, + 0, 0, 0, + /* IP0_2_0 [3] */ + FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, + 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, + 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) { + /* IP1_31_30 [2] */ + 0, 0, 0, 0, + /* IP1_29_28 [2] */ + FN_A1, FN_PWM4, 0, 0, + /* IP1_27_26 [2] */ + FN_A0, FN_PWM3, 0, 0, + /* IP1_25_22 [4] */ + FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, + FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_21_18 [4] */ + FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, + FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_17_15 [3] */ + FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, + FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, + 0, 0, 0, + /* IP1_14_12 [3] */ + FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, + FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, + 0, 0, + /* IP1_11_8 [4] */ + FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3, + FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_7_4 [4] */ + FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2, + FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_3_0 [4] */ + FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1, + FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, + 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) { + /* IP2_31_29 [3] */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_28_26 [3] */ + FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, + FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0, + /* IP2_25_22 [4] */ + FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, + FN_VI0_R5_B, FN_SCIFB2_TXD_C, 0, FN_VI2_DATA1_VI2_B1_B, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_21_18 [4] */ + FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, + FN_VI0_R4_B, FN_SCIFB2_RXD_C, 0, FN_VI2_DATA0_VI2_B0_B, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_17_15 [3] */ + FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, + 0, 0, 0, 0, + /* IP2_14_12 [3] */ + FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0, + /* IP2_11_9 [3] */ + FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0, + /* IP2_8_6 [3] */ + FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0, + /* IP2_5_3 [3] */ + FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0, + /* IP2_2_0 [3] */ + FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, + 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) { + /* IP3_31_29 [3] */ + FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, + 0, 0, 0, + /* IP3_28_26 [3] */ + FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B, + 0, 0, 0, 0, + /* IP3_25_23 [3] */ + FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0, + /* IP3_22_20 [3] */ + FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0, + /* IP3_19_18 [2] */ + FN_A16, FN_ATAWR1_N, 0, 0, + /* IP3_17_15 [3] */ + FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2, + 0, 0, 0, 0, + /* IP3_14_12 [3] */ + FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1, + 0, 0, 0, 0, + /* IP3_11_8 [4] */ + FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, + FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, + FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP3_7_4 [4] */ + FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, + FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP3_3_0 [4] */ + FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, + FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0, + 0, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, + 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + /* IP4_31_30 [2] */ + 0, 0, 0, 0, + /* IP4_29_27 [3] */ + FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, + FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0, + /* IP4_26_24 [3] */ + FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD, + FN_VI1_FIELD_B, FN_VI2_R1, 0, 0, + /* IP4_23_21 [3] */ + FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, + FN_HTX0_B, FN_MSIOF0_SS1_B, 0, + /* IP4_20_18 [3] */ + FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, + FN_VI2_CLK, FN_VI2_CLK_B, 0, 0, + /* IP4_17_15 [3] */ + FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, + 0, 0, 0, + /* IP4_14_12 [3] */ + FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD, + FN_VI2_FIELD_B, 0, 0, + /* IP4_11_9 [3] */ + FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, + FN_VI2_CLKENB_B, 0, 0, + /* IP4_8_6 [3] */ + FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0, + /* IP4_5_3 [3] */ + FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0, + /* IP4_2_0 [3] */ + FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, + 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) { + /* IP5_31_30 [2] */ + 0, 0, 0, 0, + /* IP5_29_27 [3] */ + FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, + FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0, + /* IP5_26_24 [3] */ + FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, + FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, + FN_MSIOF0_SCK_B, 0, + /* IP5_23_21 [3] */ + FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, + FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, + FN_IERX_C, 0, + /* IP5_20_18 [3] */ + FN_WE0_N, FN_IECLK, FN_CAN_CLK, + FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0, + /* IP5_17_15 [3] */ + FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, + FN_INTC_IRQ4_N, 0, 0, + /* IP5_14_13 [2] */ + FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0, + /* IP5_12_10 [3] */ + FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C, + 0, 0, + /* IP5_9_6 [4] */ + FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, + FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N, + FN_SDA1_CIS, 0, 0, 0, 0, 0, 0, + /* IP5_5_3 [3] */ + FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, + FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B, + FN_INTC_EN0_N, FN_SCL1_CIS, + /* IP5_2_0 [3] */ + FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, + FN_VI2_R3, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, + 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { + /* IP6_31_29 [3] */ + FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, + FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, + /* IP6_28_26 [3] */ + FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, + FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0, + /* IP6_25_23 [3] */ + FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, + FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E, + /* IP6_22_20 [3] */ + FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, + FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, + /* IP6_19_17 [3] */ + FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B, + FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0, + /* IP6_16_14 [3] */ + FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, + FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, + FN_SCL2_CIS_E, 0, + /* IP6_13_11 [3] */ + FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, + FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, + /* IP6_10_9 [2] */ + FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B, + /* IP6_8_6 [3] */ + FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B, + FN_SSI_SDATA8_C, 0, 0, 0, + /* IP6_5_3 [3] */ + FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, + FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, + /* IP6_2_0 [3] */ + FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, + FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, + 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) { + /* IP7_31 [1] */ + 0, 0, + /* IP7_30_29 [2] */ + FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, + FN_MII_RXD2, + /* IP7_28_27 [2] */ + FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, + /* IP7_26_25 [2] */ + FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, + /* IP7_24_22 [3] */ + FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C, + 0, 0, 0, + /* IP7_21_19 [3] */ + FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, + FN_GLO_RFON_C, FN_PCMOE_N, 0, 0, + /* IP7_18_16 [3] */ + FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, + FN_GLO_SS_C, 0, 0, 0, + /* IP7_15_13 [3] */ + FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, + FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0, + /* IP7_12_10 [3] */ + FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, + FN_GLO_SCLK_C, 0, 0, 0, + /* IP7_9_8 [2] */ + FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0, + /* IP7_7_6 [2] */ + FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F, + /* IP7_5_3 [3] */ + FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, + 0, 0, 0, + /* IP7_2_0 [3] */ + FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, + FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, + 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2) { + /* IP8_31 [1] */ + 0, 0, + /* IP8_30_29 [2] */ + FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0, + /* IP8_28 [1] */ + FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, + /* IP8_27 [1] */ + FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, + /* IP8_26 [1] */ + FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT, + /* IP8_25_24 [2] */ + FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, + FN_AVB_MAGIC, FN_MII_MAGIC, + /* IP8_23_22 [2] */ + FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0, + /* IP8_21_20 [2] */ + FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, + FN_MII_MDIO, + /* IP8_19_18 [2] */ + FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC, + /* IP8_17_16 [2] */ + FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, FN_MII_CRS, + /* IP8_15_14 [2] */ + FN_VI1_CLK, FN_AVB_RX_DV, FN_MII_RX_DV, 0, + /* IP8_13_12 [2] */ + FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, FN_MII_RX_CLK, 0, + /* IP8_11_10 [2] */ + FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, FN_MII_RX_ER, 0, + /* IP8_9_8 [2] */ + FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0, + /* IP8_7_6 [2] */ + FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0, + /* IP8_5_4 [2] */ + FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0, + /* IP8_3_2 [2] */ + FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, + /* IP8_1_0 [2] */ + FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, FN_MII_RXD3, } + }, + { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, + 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { + /* IP9_31_28 [4] */ + FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, + FN_GLO_SS, FN_VI0_CLK_B, FN_SCL2_D, FN_SCL2_CIS_D, + FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0, + /* IP9_27_26 [2] */ + FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B, + /* IP9_25_24 [2] */ + FN_SD1_DAT2, FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B, + /* IP9_23_22 [2] */ + FN_SD1_DAT1, FN_AVB_LINK, FN_MII_LINK, FN_SCIFB0_TXD_B, + /* IP9_21_20 [2] */ + FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, FN_SCIFB0_RXD_B, + /* IP9_19_18 [2] */ + FN_SD1_CMD, FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B, + /* IP9_17_16 [2] */ + FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0, + /* IP9_15_12 [4] */ + FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, + FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B, + FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0, + /* IP9_11_8 [4] */ + FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, + FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B, + FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0, + /* IP9_7_6 [2] */ + FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0, + /* IP9_5_4 [2] */ + FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0, + /* IP9_3_2 [2] */ + FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0, + /* IP9_1_0 [2] */ + FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, + 2, 4, 3, 4, 4, 4, 4, 3, 4) { + /* IP10_31_30 [2] */ + 0, 0, 0, 0, + /* IP10_29_26 [4] */ + FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, + FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, + FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0, + /* IP10_25_23 [3] */ + FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, + FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B, + /* IP10_22_19 [4] */ + FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK, + FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, + FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0, + /* IP10_18_15 [4] */ + FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA, + FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, + FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, + 0, 0, 0, 0, 0, 0, + /* IP10_14_11 [4] */ + FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, + FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, + FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, + 0, 0, 0, 0, 0, 0, 0, + /* IP10_10_7 [4] */ + FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, + FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, + FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, + 0, 0, 0, 0, 0, 0, 0, + /* IP10_6_4 [3] */ + FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, + FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, + FN_VI3_DATA0_B, 0, + /* IP10_3_0 [4] */ + FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, + FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D, + FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, + 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) { + /* IP11_31_30 [2] */ + FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, + /* IP11_29_27 [3] */ + FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, + FN_RDS_CLK_B, 0, 0, + /* IP11_26_24 [3] */ + FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, FN_SDA2_CIS_B, + 0, 0, 0, + /* IP11_23_22 [2] */ + FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, 0, + /* IP11_21_18 [4] */ + FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, + FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F, + FN_RDS_DATA_E, 0, 0, 0, 0, 0, 0, + /* IP11_17_15 [3] */ + FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, + FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0, + /* IP11_14_13 [2] */ + FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0, + /* IP11_12_11 [2] */ + FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0, + /* IP11_10_9 [2] */ + FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0, + /* IP11_8_7 [2] */ + FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0, + /* IP11_6_5 [2] */ + FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0, + /* IP11_4 [1] */ + FN_SD3_CLK, FN_MMC1_CLK, + /* IP11_3_0 [4] */ + FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, + FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, + FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, + 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) { + /* IP12_31 [1] */ + 0, 0, + /* IP12_30_28 [3] */ + FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B, + FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, + FN_CAN_DEBUGOUT4, 0, 0, + /* IP12_27_25 [3] */ + FN_SSI_SCK5, FN_SCIFB1_SCK, + FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, + FN_CAN_DEBUGOUT3, 0, 0, + /* IP12_24_23 [2] */ + FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, + FN_CAN_DEBUGOUT2, + /* IP12_22_20 [3] */ + FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, + FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0, + /* IP12_19_17 [3] */ + FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, + FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0, + /* IP12_16_14 [3] */ + FN_SSI_SDATA3, FN_STP_ISCLK_0, + FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0, + /* IP12_13_11 [3] */ + FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, + FN_CAN_STEP0, 0, 0, 0, + /* IP12_10_8 [3] */ + FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, + FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0, + /* IP12_7_6 [2] */ + FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, + /* IP12_5_4 [2] */ + FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0, + /* IP12_3_2 [2] */ + FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0, + /* IP12_1_0 [2] */ + FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, + 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) { + /* IP13_31 [1] */ + 0, 0, + /* IP13_30_29 [2] */ + FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0, + /* IP13_28_26 [3] */ + FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, + FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0, + /* IP13_25_23 [3] */ + FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, + FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0, + /* IP13_22_19 [4] */ + FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, + FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E, + FN_RDS_CLK_D, FN_SSI_SDATA7_B, FN_FMIN_G, FN_RDS_DATA_F, + 0, 0, 0, 0, + /* IP13_18_16 [3] */ + FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, + FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0, + /* IP13_15_13 [3] */ + FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK, + FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0, + /* IP13_12_10 [3] */ + FN_SSI_SDATA6, FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5, + FN_CAN_DEBUGOUT8, 0, 0, + /* IP13_9_7 [3] */ + FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, + FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0, + /* IP13_6_3 [4] */ + FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C, + FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, + FN_BPFCLK_F, FN_RDS_CLK_E, 0, 0, 0, 0, 0, 0, 0, + /* IP13_2_0 [3] */ + FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, + FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, + 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) { + /* IP14_30 [1] */ + 0, 0, + /* IP14_30_28 [3] */ + FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS, + FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, + FN_HRTS0_N_C, 0, + /* IP14_27_25 [3] */ + FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD, + FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0, + /* IP14_24_22 [3] */ + FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, + FN_LCDOUT9, 0, 0, 0, + /* IP14_21_19 [3] */ + FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, + FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0, + /* IP14_18_16 [3] */ + FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS, + FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0, + /* IP14_15_12 [4] */ + FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, + FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C, + 0, 0, 0, 0, 0, 0, 0, + /* IP14_11_9 [3] */ + FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1, + 0, 0, 0, + /* IP14_8_6 [3] */ + FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0, + 0, 0, 0, + /* IP14_5_3 [3] */ + FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2, + FN_LCDOUT10, FN_SDA1_C, FN_SDA1_CIS_C, + /* IP14_2_0 [3] */ + FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, + FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, + FN_REMOCON, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, + 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) { + /* IP15_31_30 [2] */ + 0, 0, 0, 0, + /* IP15_29_28 [2] */ + FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14, + /* IP15_27_26 [2] */ + FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13, + /* IP15_25_23 [3] */ + FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA, + FN_DU2_DB7, FN_LCDOUT23, FN_SCIFA2_RXD_B, 0, + /* IP15_22_20 [3] */ + FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, + FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0, + /* IP15_19_18 [2] */ + FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21, + /* IP15_17_16 [2] */ + FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20, + /* IP15_15_14 [2] */ + FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0, + /* IP15_13_12 [2] */ + FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0, + /* IP15_11_9 [3] */ + FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, + 0, 0, 0, + /* IP15_8_6 [3] */ + FN_SCIFA2_TXD, FN_BPFCLK, 0, FN_DU2_DB1, FN_LCDOUT17, + FN_SDA2, FN_SDA2_CIS, 0, + /* IP15_5_3 [3] */ + FN_SCIFA2_RXD, FN_FMIN, 0, FN_DU2_DB0, FN_LCDOUT16, + FN_SCL2, FN_SCL2_CIS, 0, + /* IP15_2_0 [3] */ + FN_SCIFA2_SCK, FN_FMCLK, 0, FN_MSIOF3_SCK, FN_DU2_DG7, + FN_LCDOUT15, FN_SCIF_CLK_B, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, + 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) { + /* IP16_31_28 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_27_24 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_23_20 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_19_16 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_15_12 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_11_8 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_7 [1] */ + FN_USB1_OVC, FN_TCLK1_B, + /* IP16_6 [1] */ + FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, + /* IP16_5_3 [3] */ + FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, + FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C, 0, + /* IP16_2_0 [3] */ + FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, + FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, + 3, 2, 2, 3, 2, 1, 1, 1, 2, 1, + 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) { + /* SEL_SCIF1 [3] */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + FN_SEL_SCIF1_4, 0, 0, 0, + /* SEL_SCIFB [2] */ + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0, + /* SEL_SCIFB2 [2] */ + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0, + /* SEL_SCIFB1 [3] */ + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, + FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5, + FN_SEL_SCIFB1_6, 0, + /* SEL_SCIFA1 [2] */ + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, + FN_SEL_SCIFA1_3, + /* SEL_SCIF0 [1] */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, + /* SEL_SCIFA [1] */ + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + /* SEL_SOF1 [1] */ + FN_SEL_SOF1_0, FN_SEL_SOF1_1, + /* SEL_SSI7 [2] */ + FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0, + /* SEL_SSI6 [1] */ + FN_SEL_SSI6_0, FN_SEL_SSI6_1, + /* SEL_SSI5 [2] */ + FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0, + /* SEL_VI3 [1] */ + FN_SEL_VI3_0, FN_SEL_VI3_1, + /* SEL_VI2 [1] */ + FN_SEL_VI2_0, FN_SEL_VI2_1, + /* SEL_VI1 [1] */ + FN_SEL_VI1_0, FN_SEL_VI1_1, + /* SEL_VI0 [1] */ + FN_SEL_VI0_0, FN_SEL_VI0_1, + /* SEL_TSIF1 [2] */ + FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0, + /* RESERVED [1] */ + 0, 0, + /* SEL_LBS [1] */ + FN_SEL_LBS_0, FN_SEL_LBS_1, + /* SEL_TSIF0 [2] */ + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + /* SEL_SOF3 [1] */ + FN_SEL_SOF3_0, FN_SEL_SOF3_1, + /* SEL_SOF0 [1] */ + FN_SEL_SOF0_0, FN_SEL_SOF0_1, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, + 3, 1, 1, 1, 2, 1, 2, 1, 2, + 1, 1, 1, 3, 3, 2, 3, 2, 2) { + /* RESERVED [3] */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* SEL_TMU1 [1] */ + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + /* SEL_HSCIF1 [1] */ + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + /* SEL_SCIFCLK [1] */ + FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, + /* SEL_CAN0 [2] */ + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + /* SEL_CANCLK [1] */ + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, + /* SEL_SCIFA2 [2] */ + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0, + /* SEL_CAN1 [1] */ + FN_SEL_CAN1_0, FN_SEL_CAN1_1, + /* RESERVED [2] */ + 0, 0, 0, 0, + /* RESERVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */ + 0, 0, + /* SEL_ADI [1] */ + FN_SEL_ADI_0, FN_SEL_ADI_1, + /* SEL_SSP [1] */ + FN_SEL_SSP_0, FN_SEL_SSP_1, + /* SEL_FM [3] */ + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, + FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0, + /* SEL_HSCIF0 [3] */ + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, + FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0, + /* SEL_GPS [2] */ + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0, + /* SEL_RDS [3] */ + FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, + FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, 0, 0, + /* SEL_SIM [2] */ + FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, + /* SEL_SSI8 [2] */ + FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, + 1, 1, 2, 4, 4, 2, 2, + 4, 2, 3, 2, 3, 2) { + /* SEL_IICDVFS [1] */ + FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, + /* SEL_IIC0 [1] */ + FN_SEL_IIC0_0, FN_SEL_IIC0_1, + /* RESERVED [2] */ + 0, 0, 0, 0, + /* RESERVED [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED [2] */ + 0, 0, 0, 0, + /* SEL_IEB [2] */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, + /* RESERVED [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED [2] */ + 0, 0, 0, 0, + /* SEL_IIC2 [3] */ + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + FN_SEL_IIC2_4, 0, 0, 0, + /* SEL_IIC1 [2] */ + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0, + /* SEL_I2C2 [3] */ + FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, + FN_SEL_I2C2_4, 0, 0, 0, + /* SEL_I2C1 [2] */ + FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, } + }, + { }, +}; + +const struct sh_pfc_soc_info r8a7790_pinmux_info = { + .name = "r8a77900_pfc", + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c index df0ae21a5ac..6dfb1877257 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c @@ -20,10 +20,14 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <linux/io.h> #include <linux/kernel.h> +#include <linux/pinctrl/pinconf-generic.h> + #include <mach/irqs.h> #include <mach/sh7372.h> +#include "core.h" #include "sh_pfc.h" #define CPU_ALL_PORT(fn, pfx, sfx) \ @@ -34,6 +38,35 @@ PORT_10(fn, pfx##16, sfx), PORT_10(fn, pfx##17, sfx), \ PORT_10(fn, pfx##18, sfx), PORT_1(fn, pfx##190, sfx) +#undef _GPIO_PORT +#define _GPIO_PORT(gpio, sfx) \ + [gpio] = { \ + .name = __stringify(PORT##gpio), \ + .enum_id = PORT##gpio##_DATA, \ + } + +#define IRQC_PIN_MUX(irq, pin) \ +static const unsigned int intc_irq##irq##_pins[] = { \ + pin, \ +}; \ +static const unsigned int intc_irq##irq##_mux[] = { \ + IRQ##irq##_MARK, \ +} + +#define IRQC_PINS_MUX(irq, pin0, pin1) \ +static const unsigned int intc_irq##irq##_0_pins[] = { \ + pin0, \ +}; \ +static const unsigned int intc_irq##irq##_0_mux[] = { \ + IRQ##irq##_##pin0##_MARK, \ +}; \ +static const unsigned int intc_irq##irq##_1_pins[] = { \ + pin1, \ +}; \ +static const unsigned int intc_irq##irq##_1_mux[] = { \ + IRQ##irq##_##pin1##_MARK, \ +} + enum { PINMUX_RESERVED = 0, @@ -47,16 +80,6 @@ enum { PORT_ALL(IN), PINMUX_INPUT_END, - /* PORT0_IN_PU -> PORT190_IN_PU */ - PINMUX_INPUT_PULLUP_BEGIN, - PORT_ALL(IN_PU), - PINMUX_INPUT_PULLUP_END, - - /* PORT0_IN_PD -> PORT190_IN_PD */ - PINMUX_INPUT_PULLDOWN_BEGIN, - PORT_ALL(IN_PD), - PINMUX_INPUT_PULLDOWN_END, - /* PORT0_OUT -> PORT190_OUT */ PINMUX_OUTPUT_BEGIN, PORT_ALL(OUT), @@ -368,124 +391,11 @@ enum { PINMUX_MARK_END, }; -static const pinmux_enum_t pinmux_data[] = { +#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) - /* specify valid pin states for each pin in GPIO mode */ - PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1), - PORT_DATA_O(2), PORT_DATA_I_PD(3), - PORT_DATA_I_PD(4), PORT_DATA_I_PD(5), - PORT_DATA_IO_PU_PD(6), PORT_DATA_I_PD(7), - PORT_DATA_IO_PD(8), PORT_DATA_O(9), - - PORT_DATA_O(10), PORT_DATA_O(11), - PORT_DATA_IO_PU_PD(12), PORT_DATA_IO_PD(13), - PORT_DATA_IO_PD(14), PORT_DATA_O(15), - PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17), - PORT_DATA_I_PD(18), PORT_DATA_IO(19), - - PORT_DATA_IO(20), PORT_DATA_IO(21), - PORT_DATA_IO(22), PORT_DATA_IO(23), - PORT_DATA_IO(24), PORT_DATA_IO(25), - PORT_DATA_IO(26), PORT_DATA_IO(27), - PORT_DATA_IO(28), PORT_DATA_IO(29), - - PORT_DATA_IO(30), PORT_DATA_IO(31), - PORT_DATA_IO(32), PORT_DATA_IO(33), - PORT_DATA_IO(34), PORT_DATA_IO(35), - PORT_DATA_IO(36), PORT_DATA_IO(37), - PORT_DATA_IO(38), PORT_DATA_IO(39), - - PORT_DATA_IO(40), PORT_DATA_IO(41), - PORT_DATA_IO(42), PORT_DATA_IO(43), - PORT_DATA_IO(44), PORT_DATA_IO(45), - PORT_DATA_IO_PU(46), PORT_DATA_IO_PU(47), - PORT_DATA_IO_PU(48), PORT_DATA_IO_PU(49), - - PORT_DATA_IO_PU(50), PORT_DATA_IO_PU(51), - PORT_DATA_IO_PU(52), PORT_DATA_IO_PU(53), - PORT_DATA_IO_PU(54), PORT_DATA_IO_PU(55), - PORT_DATA_IO_PU(56), PORT_DATA_IO_PU(57), - PORT_DATA_IO_PU(58), PORT_DATA_IO_PU(59), - - PORT_DATA_IO_PU(60), PORT_DATA_IO_PU(61), - PORT_DATA_IO(62), PORT_DATA_O(63), - PORT_DATA_O(64), PORT_DATA_IO_PU(65), - PORT_DATA_O(66), PORT_DATA_IO_PU(67), /*66?*/ - PORT_DATA_O(68), PORT_DATA_IO(69), - - PORT_DATA_IO(70), PORT_DATA_IO(71), - PORT_DATA_O(72), PORT_DATA_I_PU(73), - PORT_DATA_I_PU_PD(74), PORT_DATA_IO_PU_PD(75), - PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77), - PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79), - - PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81), - PORT_DATA_IO_PU_PD(82), PORT_DATA_IO_PU_PD(83), - PORT_DATA_IO_PU_PD(84), PORT_DATA_IO_PU_PD(85), - PORT_DATA_IO_PU_PD(86), PORT_DATA_IO_PU_PD(87), - PORT_DATA_IO_PU_PD(88), PORT_DATA_IO_PU_PD(89), - - PORT_DATA_IO_PU_PD(90), PORT_DATA_IO_PU_PD(91), - PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93), - PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95), - PORT_DATA_IO_PU(96), PORT_DATA_IO_PU_PD(97), - PORT_DATA_IO_PU_PD(98), PORT_DATA_O(99), /*99?*/ - - PORT_DATA_IO_PD(100), PORT_DATA_IO_PD(101), - PORT_DATA_IO_PD(102), PORT_DATA_IO_PD(103), - PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105), - PORT_DATA_IO_PU(106), PORT_DATA_IO_PU(107), - PORT_DATA_IO_PU(108), PORT_DATA_IO_PU(109), - - PORT_DATA_IO_PU(110), PORT_DATA_IO_PU(111), - PORT_DATA_IO_PD(112), PORT_DATA_IO_PD(113), - PORT_DATA_IO_PU(114), PORT_DATA_IO_PU(115), - PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117), - PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119), - - PORT_DATA_IO_PU(120), PORT_DATA_IO_PD(121), - PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123), - PORT_DATA_IO_PD(124), PORT_DATA_IO_PD(125), - PORT_DATA_IO_PD(126), PORT_DATA_IO_PD(127), - PORT_DATA_IO_PD(128), PORT_DATA_IO_PU_PD(129), - - PORT_DATA_IO_PU_PD(130), PORT_DATA_IO_PU_PD(131), - PORT_DATA_IO_PU_PD(132), PORT_DATA_IO_PU_PD(133), - PORT_DATA_IO_PU_PD(134), PORT_DATA_IO_PU_PD(135), - PORT_DATA_IO_PD(136), PORT_DATA_IO_PD(137), - PORT_DATA_IO_PD(138), PORT_DATA_IO_PD(139), - - PORT_DATA_IO_PD(140), PORT_DATA_IO_PD(141), - PORT_DATA_IO_PD(142), PORT_DATA_IO_PU_PD(143), - PORT_DATA_IO_PD(144), PORT_DATA_IO_PD(145), - PORT_DATA_IO_PD(146), PORT_DATA_IO_PD(147), - PORT_DATA_IO_PD(148), PORT_DATA_IO_PD(149), - - PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151), - PORT_DATA_IO_PU_PD(152), PORT_DATA_I_PD(153), - PORT_DATA_IO_PU_PD(154), PORT_DATA_I_PD(155), - PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157), - PORT_DATA_I_PD(158), PORT_DATA_IO_PD(159), - - PORT_DATA_O(160), PORT_DATA_IO_PD(161), - PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), - PORT_DATA_I_PD(164), PORT_DATA_IO_PD(165), - PORT_DATA_I_PD(166), PORT_DATA_I_PD(167), - PORT_DATA_I_PD(168), PORT_DATA_I_PD(169), - - PORT_DATA_I_PD(170), PORT_DATA_O(171), - PORT_DATA_IO_PU_PD(172), PORT_DATA_IO_PU_PD(173), - PORT_DATA_IO_PU_PD(174), PORT_DATA_IO_PU_PD(175), - PORT_DATA_IO_PU_PD(176), PORT_DATA_IO_PU_PD(177), - PORT_DATA_IO_PU_PD(178), PORT_DATA_O(179), - - PORT_DATA_IO_PU_PD(180), PORT_DATA_IO_PU_PD(181), - PORT_DATA_IO_PU_PD(182), PORT_DATA_IO_PU_PD(183), - PORT_DATA_IO_PU_PD(184), PORT_DATA_O(185), - PORT_DATA_IO_PU_PD(186), PORT_DATA_IO_PU_PD(187), - PORT_DATA_IO_PU_PD(188), PORT_DATA_IO_PU_PD(189), - - PORT_DATA_IO_PU_PD(190), +static const pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* IRQ */ PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0), @@ -929,10 +839,582 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1), }; +#define SH7372_PIN(pin, cfgs) \ + { \ + .name = __stringify(PORT##pin), \ + .enum_id = PORT##pin##_DATA, \ + .configs = cfgs, \ + } + +#define __I (SH_PFC_PIN_CFG_INPUT) +#define __O (SH_PFC_PIN_CFG_OUTPUT) +#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) +#define __PD (SH_PFC_PIN_CFG_PULL_DOWN) +#define __PU (SH_PFC_PIN_CFG_PULL_UP) +#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) + +#define SH7372_PIN_I_PD(pin) SH7372_PIN(pin, __I | __PD) +#define SH7372_PIN_I_PU(pin) SH7372_PIN(pin, __I | __PU) +#define SH7372_PIN_I_PU_PD(pin) SH7372_PIN(pin, __I | __PUD) +#define SH7372_PIN_IO(pin) SH7372_PIN(pin, __IO) +#define SH7372_PIN_IO_PD(pin) SH7372_PIN(pin, __IO | __PD) +#define SH7372_PIN_IO_PU(pin) SH7372_PIN(pin, __IO | __PU) +#define SH7372_PIN_IO_PU_PD(pin) SH7372_PIN(pin, __IO | __PUD) +#define SH7372_PIN_O(pin) SH7372_PIN(pin, __O) +#define SH7372_PIN_O_PU_PD(pin) SH7372_PIN(pin, __O | __PUD) + static struct sh_pfc_pin pinmux_pins[] = { - GPIO_PORT_ALL(), + /* Table 57-1 (I/O and Pull U/D) */ + SH7372_PIN_IO_PD(0), SH7372_PIN_IO_PD(1), + SH7372_PIN_O(2), SH7372_PIN_I_PD(3), + SH7372_PIN_I_PD(4), SH7372_PIN_I_PD(5), + SH7372_PIN_IO_PU_PD(6), SH7372_PIN_I_PD(7), + SH7372_PIN_IO_PD(8), SH7372_PIN_O(9), + SH7372_PIN_O(10), SH7372_PIN_O(11), + SH7372_PIN_IO_PU_PD(12), SH7372_PIN_IO_PD(13), + SH7372_PIN_IO_PD(14), SH7372_PIN_O(15), + SH7372_PIN_IO_PD(16), SH7372_PIN_IO_PD(17), + SH7372_PIN_I_PD(18), SH7372_PIN_IO(19), + SH7372_PIN_IO(20), SH7372_PIN_IO(21), + SH7372_PIN_IO(22), SH7372_PIN_IO(23), + SH7372_PIN_IO(24), SH7372_PIN_IO(25), + SH7372_PIN_IO(26), SH7372_PIN_IO(27), + SH7372_PIN_IO(28), SH7372_PIN_IO(29), + SH7372_PIN_IO(30), SH7372_PIN_IO(31), + SH7372_PIN_IO(32), SH7372_PIN_IO(33), + SH7372_PIN_IO(34), SH7372_PIN_IO(35), + SH7372_PIN_IO(36), SH7372_PIN_IO(37), + SH7372_PIN_IO(38), SH7372_PIN_IO(39), + SH7372_PIN_IO(40), SH7372_PIN_IO(41), + SH7372_PIN_IO(42), SH7372_PIN_IO(43), + SH7372_PIN_IO(44), SH7372_PIN_IO(45), + SH7372_PIN_IO_PU(46), SH7372_PIN_IO_PU(47), + SH7372_PIN_IO_PU(48), SH7372_PIN_IO_PU(49), + SH7372_PIN_IO_PU(50), SH7372_PIN_IO_PU(51), + SH7372_PIN_IO_PU(52), SH7372_PIN_IO_PU(53), + SH7372_PIN_IO_PU(54), SH7372_PIN_IO_PU(55), + SH7372_PIN_IO_PU(56), SH7372_PIN_IO_PU(57), + SH7372_PIN_IO_PU(58), SH7372_PIN_IO_PU(59), + SH7372_PIN_IO_PU(60), SH7372_PIN_IO_PU(61), + SH7372_PIN_IO(62), SH7372_PIN_O(63), + SH7372_PIN_O(64), SH7372_PIN_IO_PU(65), + SH7372_PIN_O_PU_PD(66), SH7372_PIN_IO_PU(67), + SH7372_PIN_O(68), SH7372_PIN_IO(69), + SH7372_PIN_IO(70), SH7372_PIN_IO(71), + SH7372_PIN_O(72), SH7372_PIN_I_PU(73), + SH7372_PIN_I_PU_PD(74), SH7372_PIN_IO_PU_PD(75), + SH7372_PIN_IO_PU_PD(76), SH7372_PIN_IO_PU_PD(77), + SH7372_PIN_IO_PU_PD(78), SH7372_PIN_IO_PU_PD(79), + SH7372_PIN_IO_PU_PD(80), SH7372_PIN_IO_PU_PD(81), + SH7372_PIN_IO_PU_PD(82), SH7372_PIN_IO_PU_PD(83), + SH7372_PIN_IO_PU_PD(84), SH7372_PIN_IO_PU_PD(85), + SH7372_PIN_IO_PU_PD(86), SH7372_PIN_IO_PU_PD(87), + SH7372_PIN_IO_PU_PD(88), SH7372_PIN_IO_PU_PD(89), + SH7372_PIN_IO_PU_PD(90), SH7372_PIN_IO_PU_PD(91), + SH7372_PIN_IO_PU_PD(92), SH7372_PIN_IO_PU_PD(93), + SH7372_PIN_IO_PU_PD(94), SH7372_PIN_IO_PU_PD(95), + SH7372_PIN_IO_PU(96), SH7372_PIN_IO_PU_PD(97), + SH7372_PIN_IO_PU_PD(98), SH7372_PIN_O_PU_PD(99), + SH7372_PIN_IO_PD(100), SH7372_PIN_IO_PD(101), + SH7372_PIN_IO_PD(102), SH7372_PIN_IO_PD(103), + SH7372_PIN_IO_PD(104), SH7372_PIN_IO_PD(105), + SH7372_PIN_IO_PU(106), SH7372_PIN_IO_PU(107), + SH7372_PIN_IO_PU(108), SH7372_PIN_IO_PU(109), + SH7372_PIN_IO_PU(110), SH7372_PIN_IO_PU(111), + SH7372_PIN_IO_PD(112), SH7372_PIN_IO_PD(113), + SH7372_PIN_IO_PU(114), SH7372_PIN_IO_PU(115), + SH7372_PIN_IO_PU(116), SH7372_PIN_IO_PU(117), + SH7372_PIN_IO_PU(118), SH7372_PIN_IO_PU(119), + SH7372_PIN_IO_PU(120), SH7372_PIN_IO_PD(121), + SH7372_PIN_IO_PD(122), SH7372_PIN_IO_PD(123), + SH7372_PIN_IO_PD(124), SH7372_PIN_IO_PD(125), + SH7372_PIN_IO_PD(126), SH7372_PIN_IO_PD(127), + SH7372_PIN_IO_PD(128), SH7372_PIN_IO_PU_PD(129), + SH7372_PIN_IO_PU_PD(130), SH7372_PIN_IO_PU_PD(131), + SH7372_PIN_IO_PU_PD(132), SH7372_PIN_IO_PU_PD(133), + SH7372_PIN_IO_PU_PD(134), SH7372_PIN_IO_PU_PD(135), + SH7372_PIN_IO_PD(136), SH7372_PIN_IO_PD(137), + SH7372_PIN_IO_PD(138), SH7372_PIN_IO_PD(139), + SH7372_PIN_IO_PD(140), SH7372_PIN_IO_PD(141), + SH7372_PIN_IO_PD(142), SH7372_PIN_IO_PU_PD(143), + SH7372_PIN_IO_PD(144), SH7372_PIN_IO_PD(145), + SH7372_PIN_IO_PD(146), SH7372_PIN_IO_PD(147), + SH7372_PIN_IO_PD(148), SH7372_PIN_IO_PD(149), + SH7372_PIN_IO_PD(150), SH7372_PIN_IO_PD(151), + SH7372_PIN_IO_PU_PD(152), SH7372_PIN_I_PD(153), + SH7372_PIN_IO_PU_PD(154), SH7372_PIN_I_PD(155), + SH7372_PIN_IO_PD(156), SH7372_PIN_IO_PD(157), + SH7372_PIN_I_PD(158), SH7372_PIN_IO_PD(159), + SH7372_PIN_O(160), SH7372_PIN_IO_PD(161), + SH7372_PIN_IO_PD(162), SH7372_PIN_IO_PD(163), + SH7372_PIN_I_PD(164), SH7372_PIN_IO_PD(165), + SH7372_PIN_I_PD(166), SH7372_PIN_I_PD(167), + SH7372_PIN_I_PD(168), SH7372_PIN_I_PD(169), + SH7372_PIN_I_PD(170), SH7372_PIN_O(171), + SH7372_PIN_IO_PU_PD(172), SH7372_PIN_IO_PU_PD(173), + SH7372_PIN_IO_PU_PD(174), SH7372_PIN_IO_PU_PD(175), + SH7372_PIN_IO_PU_PD(176), SH7372_PIN_IO_PU_PD(177), + SH7372_PIN_IO_PU_PD(178), SH7372_PIN_O(179), + SH7372_PIN_IO_PU_PD(180), SH7372_PIN_IO_PU_PD(181), + SH7372_PIN_IO_PU_PD(182), SH7372_PIN_IO_PU_PD(183), + SH7372_PIN_IO_PU_PD(184), SH7372_PIN_O(185), + SH7372_PIN_IO_PU_PD(186), SH7372_PIN_IO_PU_PD(187), + SH7372_PIN_IO_PU_PD(188), SH7372_PIN_IO_PU_PD(189), + SH7372_PIN_IO_PU_PD(190), }; +/* - BSC -------------------------------------------------------------------- */ +static const unsigned int bsc_data8_pins[] = { + /* D[0:7] */ + 46, 47, 48, 49, 50, 51, 52, 53, +}; +static const unsigned int bsc_data8_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, +}; +static const unsigned int bsc_data16_pins[] = { + /* D[0:15] */ + 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, +}; +static const unsigned int bsc_data16_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, + D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, + D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, +}; +static const unsigned int bsc_cs0_pins[] = { + /* CS */ + 62, +}; +static const unsigned int bsc_cs0_mux[] = { + CS0_MARK, +}; +static const unsigned int bsc_cs2_pins[] = { + /* CS */ + 63, +}; +static const unsigned int bsc_cs2_mux[] = { + CS2_MARK, +}; +static const unsigned int bsc_cs4_pins[] = { + /* CS */ + 64, +}; +static const unsigned int bsc_cs4_mux[] = { + CS4_MARK, +}; +static const unsigned int bsc_cs5a_pins[] = { + /* CS */ + 65, +}; +static const unsigned int bsc_cs5a_mux[] = { + CS5A_MARK, +}; +static const unsigned int bsc_cs5b_pins[] = { + /* CS */ + 66, +}; +static const unsigned int bsc_cs5b_mux[] = { + CS5B_MARK, +}; +static const unsigned int bsc_cs6a_pins[] = { + /* CS */ + 67, +}; +static const unsigned int bsc_cs6a_mux[] = { + CS6A_MARK, +}; +static const unsigned int bsc_rd_we8_pins[] = { + /* RD, WE[0] */ + 69, 70, +}; +static const unsigned int bsc_rd_we8_mux[] = { + RD_FSC_MARK, WE0_FWE_MARK, +}; +static const unsigned int bsc_rd_we16_pins[] = { + /* RD, WE[0:1] */ + 69, 70, 71, +}; +static const unsigned int bsc_rd_we16_mux[] = { + RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, +}; +static const unsigned int bsc_bs_pins[] = { + /* BS */ + 19, +}; +static const unsigned int bsc_bs_mux[] = { + BS_MARK, +}; +static const unsigned int bsc_rdwr_pins[] = { + /* RDWR */ + 75, +}; +static const unsigned int bsc_rdwr_mux[] = { + RDWR_MARK, +}; +static const unsigned int bsc_wait_pins[] = { + /* WAIT */ + 74, +}; +static const unsigned int bsc_wait_mux[] = { + WAIT_MARK, +}; +/* - CEU -------------------------------------------------------------------- */ +static const unsigned int ceu_data_0_7_pins[] = { + /* D[0:7] */ + 102, 103, 104, 105, 106, 107, 108, 109, +}; +static const unsigned int ceu_data_0_7_mux[] = { + VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK, + VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK, +}; +static const unsigned int ceu_data_8_15_pins[] = { + /* D[8:15] */ + 110, 111, 112, 113, 114, 115, 116, 117, +}; +static const unsigned int ceu_data_8_15_mux[] = { + VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK, + VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK, +}; +static const unsigned int ceu_clk_0_pins[] = { + /* CKO */ + 120, +}; +static const unsigned int ceu_clk_0_mux[] = { + VIO_CKO_MARK, +}; +static const unsigned int ceu_clk_1_pins[] = { + /* CKO */ + 16, +}; +static const unsigned int ceu_clk_1_mux[] = { + VIO_CKO1_MARK, +}; +static const unsigned int ceu_clk_2_pins[] = { + /* CKO */ + 17, +}; +static const unsigned int ceu_clk_2_mux[] = { + VIO_CKO2_MARK, +}; +static const unsigned int ceu_sync_pins[] = { + /* CLK, VD, HD */ + 118, 100, 101, +}; +static const unsigned int ceu_sync_mux[] = { + VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK, +}; +static const unsigned int ceu_field_pins[] = { + /* FIELD */ + 119, +}; +static const unsigned int ceu_field_mux[] = { + VIO_FIELD_MARK, +}; +/* - FLCTL ------------------------------------------------------------------ */ +static const unsigned int flctl_data_pins[] = { + /* NAF[0:15] */ + 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, +}; +static const unsigned int flctl_data_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, + D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, + D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, +}; +static const unsigned int flctl_ce0_pins[] = { + /* CE */ + 68, +}; +static const unsigned int flctl_ce0_mux[] = { + FCE0_MARK, +}; +static const unsigned int flctl_ce1_pins[] = { + /* CE */ + 66, +}; +static const unsigned int flctl_ce1_mux[] = { + FCE1_MARK, +}; +static const unsigned int flctl_ctrl_pins[] = { + /* FCDE, FOE, FSC, FWE, FRB */ + 24, 23, 69, 70, 73, +}; +static const unsigned int flctl_ctrl_mux[] = { + A5_FCDE_MARK, A4_FOE_MARK, RD_FSC_MARK, WE0_FWE_MARK, FRB_MARK, +}; +/* - FSIA ------------------------------------------------------------------- */ +static const unsigned int fsia_mclk_in_pins[] = { + /* CK */ + 4, +}; +static const unsigned int fsia_mclk_in_mux[] = { + FSIACK_MARK, +}; +static const unsigned int fsia_mclk_out_pins[] = { + /* OMC */ + 8, +}; +static const unsigned int fsia_mclk_out_mux[] = { + FSIAOMC_MARK, +}; +static const unsigned int fsia_sclk_in_pins[] = { + /* ILR, IBT */ + 5, 6, +}; +static const unsigned int fsia_sclk_in_mux[] = { + FSIAILR_MARK, FSIAIBT_MARK, +}; +static const unsigned int fsia_sclk_out_pins[] = { + /* OLR, OBT */ + 9, 10, +}; +static const unsigned int fsia_sclk_out_mux[] = { + FSIAOLR_MARK, FSIAOBT_MARK, +}; +static const unsigned int fsia_data_in_pins[] = { + /* ISLD */ + 7, +}; +static const unsigned int fsia_data_in_mux[] = { + FSIAISLD_MARK, +}; +static const unsigned int fsia_data_out_pins[] = { + /* OSLD */ + 11, +}; +static const unsigned int fsia_data_out_mux[] = { + FSIAOSLD_MARK, +}; +static const unsigned int fsia_spdif_0_pins[] = { + /* SPDIF */ + 11, +}; +static const unsigned int fsia_spdif_0_mux[] = { + FSIASPDIF_11_MARK, +}; +static const unsigned int fsia_spdif_1_pins[] = { + /* SPDIF */ + 15, +}; +static const unsigned int fsia_spdif_1_mux[] = { + FSIASPDIF_15_MARK, +}; +/* - FSIB ------------------------------------------------------------------- */ +static const unsigned int fsib_mclk_in_pins[] = { + /* CK */ + 4, +}; +static const unsigned int fsib_mclk_in_mux[] = { + FSIBCK_MARK, +}; +/* - HDMI ------------------------------------------------------------------- */ +static const unsigned int hdmi_pins[] = { + /* HPD, CEC */ + 169, 170, +}; +static const unsigned int hdmi_mux[] = { + HDMI_HPD_MARK, HDMI_CEC_MARK, +}; +/* - INTC ------------------------------------------------------------------- */ +IRQC_PINS_MUX(0, 6, 162); +IRQC_PIN_MUX(1, 12); +IRQC_PINS_MUX(2, 4, 5); +IRQC_PINS_MUX(3, 8, 16); +IRQC_PINS_MUX(4, 17, 163); +IRQC_PIN_MUX(5, 18); +IRQC_PINS_MUX(6, 39, 164); +IRQC_PINS_MUX(7, 40, 167); +IRQC_PINS_MUX(8, 41, 168); +IRQC_PINS_MUX(9, 42, 169); +IRQC_PIN_MUX(10, 65); +IRQC_PIN_MUX(11, 67); +IRQC_PINS_MUX(12, 80, 137); +IRQC_PINS_MUX(13, 81, 145); +IRQC_PINS_MUX(14, 82, 146); +IRQC_PINS_MUX(15, 83, 147); +IRQC_PINS_MUX(16, 84, 170); +IRQC_PIN_MUX(17, 85); +IRQC_PIN_MUX(18, 86); +IRQC_PIN_MUX(19, 87); +IRQC_PIN_MUX(20, 92); +IRQC_PIN_MUX(21, 93); +IRQC_PIN_MUX(22, 94); +IRQC_PIN_MUX(23, 95); +IRQC_PIN_MUX(24, 112); +IRQC_PIN_MUX(25, 119); +IRQC_PINS_MUX(26, 121, 172); +IRQC_PINS_MUX(27, 122, 180); +IRQC_PINS_MUX(28, 123, 181); +IRQC_PINS_MUX(29, 129, 182); +IRQC_PINS_MUX(30, 130, 183); +IRQC_PINS_MUX(31, 138, 184); +/* - KEYSC ------------------------------------------------------------------ */ +static const unsigned int keysc_in04_0_pins[] = { + /* KEYIN[0:4] */ + 136, 135, 134, 133, 132, +}; +static const unsigned int keysc_in04_0_mux[] = { + KEYIN0_136_MARK, KEYIN1_135_MARK, KEYIN2_134_MARK, KEYIN3_133_MARK, + KEYIN4_MARK, +}; +static const unsigned int keysc_in04_1_pins[] = { + /* KEYIN[0:4] */ + 121, 122, 123, 124, 132, +}; +static const unsigned int keysc_in04_1_mux[] = { + KEYIN0_121_MARK, KEYIN1_122_MARK, KEYIN2_123_MARK, KEYIN3_124_MARK, + KEYIN4_MARK, +}; +static const unsigned int keysc_in5_pins[] = { + /* KEYIN5 */ + 131, +}; +static const unsigned int keysc_in5_mux[] = { + KEYIN5_MARK, +}; +static const unsigned int keysc_in6_pins[] = { + /* KEYIN6 */ + 130, +}; +static const unsigned int keysc_in6_mux[] = { + KEYIN6_MARK, +}; +static const unsigned int keysc_in7_pins[] = { + /* KEYIN7 */ + 129, +}; +static const unsigned int keysc_in7_mux[] = { + KEYIN7_MARK, +}; +static const unsigned int keysc_out4_pins[] = { + /* KEYOUT[0:3] */ + 128, 127, 126, 125, +}; +static const unsigned int keysc_out4_mux[] = { + KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, +}; +static const unsigned int keysc_out5_pins[] = { + /* KEYOUT[0:4] */ + 128, 127, 126, 125, 124, +}; +static const unsigned int keysc_out5_mux[] = { + KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, + KEYOUT4_MARK, +}; +static const unsigned int keysc_out6_pins[] = { + /* KEYOUT[0:5] */ + 128, 127, 126, 125, 124, 123, +}; +static const unsigned int keysc_out6_mux[] = { + KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, + KEYOUT4_MARK, KEYOUT5_MARK, +}; +static const unsigned int keysc_out8_pins[] = { + /* KEYOUT[0:7] */ + 128, 127, 126, 125, 124, 123, 122, 121, +}; +static const unsigned int keysc_out8_mux[] = { + KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, + KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK, +}; +/* - LCD -------------------------------------------------------------------- */ +static const unsigned int lcd_data8_pins[] = { + /* D[0:7] */ + 121, 122, 123, 124, 125, 126, 127, 128, +}; +static const unsigned int lcd_data8_mux[] = { + /* LCDC */ + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, +}; +static const unsigned int lcd_data9_pins[] = { + /* D[0:8] */ + 121, 122, 123, 124, 125, 126, 127, 128, + 129, + 137, 138, 139, 140, 141, 142, 143, 144, +}; +static const unsigned int lcd_data9_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, +}; +static const unsigned int lcd_data12_pins[] = { + /* D[0:11] */ + 121, 122, 123, 124, 125, 126, 127, 128, + 129, 130, 131, 132, +}; +static const unsigned int lcd_data12_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, +}; +static const unsigned int lcd_data16_pins[] = { + /* D[0:15] */ + 121, 122, 123, 124, 125, 126, 127, 128, + 129, 130, 131, 132, 133, 134, 135, 136, +}; +static const unsigned int lcd_data16_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, + LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, +}; +static const unsigned int lcd_data18_pins[] = { + /* D[0:17] */ + 121, 122, 123, 124, 125, 126, 127, 128, + 129, 130, 131, 132, 133, 134, 135, 136, + 137, 138, +}; +static const unsigned int lcd_data18_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, + LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, + LCDD16_MARK, LCDD17_MARK, +}; +static const unsigned int lcd_data24_pins[] = { + /* D[0:23] */ + 121, 122, 123, 124, 125, 126, 127, 128, + 129, 130, 131, 132, 133, 134, 135, 136, + 137, 138, 139, 140, 141, 142, 143, 144, +}; +static const unsigned int lcd_data24_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, + LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, + LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK, + LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK, +}; +static const unsigned int lcd_display_pins[] = { + /* DON */ + 151, +}; +static const unsigned int lcd_display_mux[] = { + LCDDON_MARK, +}; +static const unsigned int lcd_lclk_pins[] = { + /* LCLK */ + 150, +}; +static const unsigned int lcd_lclk_mux[] = { + LCDLCLK_MARK, +}; +static const unsigned int lcd_sync_pins[] = { + /* VSYN, HSYN, DCK, DISP */ + 146, 145, 147, 149, +}; +static const unsigned int lcd_sync_mux[] = { + LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK, +}; +static const unsigned int lcd_sys_pins[] = { + /* CS, WR, RD, RS */ + 145, 147, 148, 149, +}; +static const unsigned int lcd_sys_mux[] = { + LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, LCDRS_MARK, +}; /* - MMCIF ------------------------------------------------------------------ */ static const unsigned int mmc0_data1_0_pins[] = { /* D[0] */ @@ -993,6 +1475,139 @@ static const unsigned int mmc0_ctrl_1_pins[] = { static const unsigned int mmc0_ctrl_1_mux[] = { MMCCMD1_MARK, MMCCLK1_MARK, }; +/* - SCIFA0 ----------------------------------------------------------------- */ +static const unsigned int scifa0_data_pins[] = { + /* RXD, TXD */ + 153, 152, +}; +static const unsigned int scifa0_data_mux[] = { + SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, +}; +static const unsigned int scifa0_clk_pins[] = { + /* SCK */ + 156, +}; +static const unsigned int scifa0_clk_mux[] = { + SCIFA0_SCK_MARK, +}; +static const unsigned int scifa0_ctrl_pins[] = { + /* RTS, CTS */ + 157, 158, +}; +static const unsigned int scifa0_ctrl_mux[] = { + SCIFA0_RTS_MARK, SCIFA0_CTS_MARK, +}; +/* - SCIFA1 ----------------------------------------------------------------- */ +static const unsigned int scifa1_data_pins[] = { + /* RXD, TXD */ + 155, 154, +}; +static const unsigned int scifa1_data_mux[] = { + SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, +}; +static const unsigned int scifa1_clk_pins[] = { + /* SCK */ + 159, +}; +static const unsigned int scifa1_clk_mux[] = { + SCIFA1_SCK_MARK, +}; +static const unsigned int scifa1_ctrl_pins[] = { + /* RTS, CTS */ + 160, 161, +}; +static const unsigned int scifa1_ctrl_mux[] = { + SCIFA1_RTS_MARK, SCIFA1_CTS_MARK, +}; +/* - SCIFA2 ----------------------------------------------------------------- */ +static const unsigned int scifa2_data_pins[] = { + /* RXD, TXD */ + 97, 96, +}; +static const unsigned int scifa2_data_mux[] = { + SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK, +}; +static const unsigned int scifa2_clk_pins[] = { + /* SCK */ + 98, +}; +static const unsigned int scifa2_clk_mux[] = { + SCIFA2_SCK1_MARK, +}; +static const unsigned int scifa2_ctrl_pins[] = { + /* RTS, CTS */ + 95, 94, +}; +static const unsigned int scifa2_ctrl_mux[] = { + SCIFA2_RTS1_MARK, SCIFA2_CTS1_MARK, +}; +/* - SCIFA3 ----------------------------------------------------------------- */ +static const unsigned int scifa3_data_pins[] = { + /* RXD, TXD */ + 144, 143, +}; +static const unsigned int scifa3_data_mux[] = { + SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, +}; +static const unsigned int scifa3_clk_pins[] = { + /* SCK */ + 142, +}; +static const unsigned int scifa3_clk_mux[] = { + SCIFA3_SCK_MARK, +}; +static const unsigned int scifa3_ctrl_0_pins[] = { + /* RTS, CTS */ + 44, 43, +}; +static const unsigned int scifa3_ctrl_0_mux[] = { + SCIFA3_RTS_44_MARK, SCIFA3_CTS_43_MARK, +}; +static const unsigned int scifa3_ctrl_1_pins[] = { + /* RTS, CTS */ + 141, 140, +}; +static const unsigned int scifa3_ctrl_1_mux[] = { + SCIFA3_RTS_141_MARK, SCIFA3_CTS_140_MARK, +}; +/* - SCIFA4 ----------------------------------------------------------------- */ +static const unsigned int scifa4_data_pins[] = { + /* RXD, TXD */ + 5, 6, +}; +static const unsigned int scifa4_data_mux[] = { + SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, +}; +/* - SCIFA5 ----------------------------------------------------------------- */ +static const unsigned int scifa5_data_pins[] = { + /* RXD, TXD */ + 8, 12, +}; +static const unsigned int scifa5_data_mux[] = { + SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, +}; +/* - SCIFB ------------------------------------------------------------------ */ +static const unsigned int scifb_data_pins[] = { + /* RXD, TXD */ + 166, 165, +}; +static const unsigned int scifb_data_mux[] = { + SCIFB_RXD_MARK, SCIFB_TXD_MARK, +}; +static const unsigned int scifb_clk_pins[] = { + /* SCK */ + 162, +}; +static const unsigned int scifb_clk_mux[] = { + SCIFB_SCK_MARK, +}; +static const unsigned int scifb_ctrl_pins[] = { + /* RTS, CTS */ + 163, 164, +}; +static const unsigned int scifb_ctrl_mux[] = { + SCIFB_RTS_MARK, SCIFB_CTS_MARK, +}; /* - SDHI0 ------------------------------------------------------------------ */ static const unsigned int sdhi0_data1_pins[] = { /* D0 */ @@ -1073,8 +1688,169 @@ static const unsigned int sdhi2_ctrl_pins[] = { static const unsigned int sdhi2_ctrl_mux[] = { SDHICMD2_MARK, SDHICLK2_MARK, }; +/* - USB0 ------------------------------------------------------------------- */ +static const unsigned int usb0_vbus_pins[] = { + /* VBUS */ + 167, +}; +static const unsigned int usb0_vbus_mux[] = { + VBUS0_0_MARK, +}; +static const unsigned int usb0_otg_id_pins[] = { + /* IDIN */ + 113, +}; +static const unsigned int usb0_otg_id_mux[] = { + IDIN_0_MARK, +}; +static const unsigned int usb0_otg_ctrl_pins[] = { + /* PWEN, EXTLP, OVCN, OVCN2 */ + 116, 114, 117, 115, +}; +static const unsigned int usb0_otg_ctrl_mux[] = { + PWEN_0_MARK, EXTLP_0_MARK, OVCN_0_MARK, OVCN2_0_MARK, +}; +/* - USB1 ------------------------------------------------------------------- */ +static const unsigned int usb1_vbus_pins[] = { + /* VBUS */ + 168, +}; +static const unsigned int usb1_vbus_mux[] = { + VBUS0_1_MARK, +}; +static const unsigned int usb1_otg_id_0_pins[] = { + /* IDIN */ + 113, +}; +static const unsigned int usb1_otg_id_0_mux[] = { + IDIN_1_113_MARK, +}; +static const unsigned int usb1_otg_id_1_pins[] = { + /* IDIN */ + 18, +}; +static const unsigned int usb1_otg_id_1_mux[] = { + IDIN_1_18_MARK, +}; +static const unsigned int usb1_otg_ctrl_0_pins[] = { + /* PWEN, EXTLP, OVCN, OVCN2 */ + 115, 116, 114, 117, 113, +}; +static const unsigned int usb1_otg_ctrl_0_mux[] = { + PWEN_1_115_MARK, EXTLP_1_MARK, OVCN_1_114_MARK, OVCN2_1_MARK, +}; +static const unsigned int usb1_otg_ctrl_1_pins[] = { + /* PWEN, EXTLP, OVCN, OVCN2 */ + 138, 116, 162, 117, 18, +}; +static const unsigned int usb1_otg_ctrl_1_mux[] = { + PWEN_1_138_MARK, EXTLP_1_MARK, OVCN_1_162_MARK, OVCN2_1_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(bsc_data8), + SH_PFC_PIN_GROUP(bsc_data16), + SH_PFC_PIN_GROUP(bsc_cs0), + SH_PFC_PIN_GROUP(bsc_cs2), + SH_PFC_PIN_GROUP(bsc_cs4), + SH_PFC_PIN_GROUP(bsc_cs5a), + SH_PFC_PIN_GROUP(bsc_cs5b), + SH_PFC_PIN_GROUP(bsc_cs6a), + SH_PFC_PIN_GROUP(bsc_rd_we8), + SH_PFC_PIN_GROUP(bsc_rd_we16), + SH_PFC_PIN_GROUP(bsc_bs), + SH_PFC_PIN_GROUP(bsc_rdwr), + SH_PFC_PIN_GROUP(ceu_data_0_7), + SH_PFC_PIN_GROUP(ceu_data_8_15), + SH_PFC_PIN_GROUP(ceu_clk_0), + SH_PFC_PIN_GROUP(ceu_clk_1), + SH_PFC_PIN_GROUP(ceu_clk_2), + SH_PFC_PIN_GROUP(ceu_sync), + SH_PFC_PIN_GROUP(ceu_field), + SH_PFC_PIN_GROUP(flctl_data), + SH_PFC_PIN_GROUP(flctl_ce0), + SH_PFC_PIN_GROUP(flctl_ce1), + SH_PFC_PIN_GROUP(flctl_ctrl), + SH_PFC_PIN_GROUP(fsia_mclk_in), + SH_PFC_PIN_GROUP(fsia_mclk_out), + SH_PFC_PIN_GROUP(fsia_sclk_in), + SH_PFC_PIN_GROUP(fsia_sclk_out), + SH_PFC_PIN_GROUP(fsia_data_in), + SH_PFC_PIN_GROUP(fsia_data_out), + SH_PFC_PIN_GROUP(fsia_spdif_0), + SH_PFC_PIN_GROUP(fsia_spdif_1), + SH_PFC_PIN_GROUP(fsib_mclk_in), + SH_PFC_PIN_GROUP(hdmi), + SH_PFC_PIN_GROUP(intc_irq0_0), + SH_PFC_PIN_GROUP(intc_irq0_1), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2_0), + SH_PFC_PIN_GROUP(intc_irq2_1), + SH_PFC_PIN_GROUP(intc_irq3_0), + SH_PFC_PIN_GROUP(intc_irq3_1), + SH_PFC_PIN_GROUP(intc_irq4_0), + SH_PFC_PIN_GROUP(intc_irq4_1), + SH_PFC_PIN_GROUP(intc_irq5), + SH_PFC_PIN_GROUP(intc_irq6_0), + SH_PFC_PIN_GROUP(intc_irq6_1), + SH_PFC_PIN_GROUP(intc_irq7_0), + SH_PFC_PIN_GROUP(intc_irq7_1), + SH_PFC_PIN_GROUP(intc_irq8_0), + SH_PFC_PIN_GROUP(intc_irq8_1), + SH_PFC_PIN_GROUP(intc_irq9_0), + SH_PFC_PIN_GROUP(intc_irq9_1), + SH_PFC_PIN_GROUP(intc_irq10), + SH_PFC_PIN_GROUP(intc_irq11), + SH_PFC_PIN_GROUP(intc_irq12_0), + SH_PFC_PIN_GROUP(intc_irq12_1), + SH_PFC_PIN_GROUP(intc_irq13_0), + SH_PFC_PIN_GROUP(intc_irq13_1), + SH_PFC_PIN_GROUP(intc_irq14_0), + SH_PFC_PIN_GROUP(intc_irq14_1), + SH_PFC_PIN_GROUP(intc_irq15_0), + SH_PFC_PIN_GROUP(intc_irq15_1), + SH_PFC_PIN_GROUP(intc_irq16_0), + SH_PFC_PIN_GROUP(intc_irq16_1), + SH_PFC_PIN_GROUP(intc_irq17), + SH_PFC_PIN_GROUP(intc_irq18), + SH_PFC_PIN_GROUP(intc_irq19), + SH_PFC_PIN_GROUP(intc_irq20), + SH_PFC_PIN_GROUP(intc_irq21), + SH_PFC_PIN_GROUP(intc_irq22), + SH_PFC_PIN_GROUP(intc_irq23), + SH_PFC_PIN_GROUP(intc_irq24), + SH_PFC_PIN_GROUP(intc_irq25), + SH_PFC_PIN_GROUP(intc_irq26_0), + SH_PFC_PIN_GROUP(intc_irq26_1), + SH_PFC_PIN_GROUP(intc_irq27_0), + SH_PFC_PIN_GROUP(intc_irq27_1), + SH_PFC_PIN_GROUP(intc_irq28_0), + SH_PFC_PIN_GROUP(intc_irq28_1), + SH_PFC_PIN_GROUP(intc_irq29_0), + SH_PFC_PIN_GROUP(intc_irq29_1), + SH_PFC_PIN_GROUP(intc_irq30_0), + SH_PFC_PIN_GROUP(intc_irq30_1), + SH_PFC_PIN_GROUP(intc_irq31_0), + SH_PFC_PIN_GROUP(intc_irq31_1), + SH_PFC_PIN_GROUP(keysc_in04_0), + SH_PFC_PIN_GROUP(keysc_in04_1), + SH_PFC_PIN_GROUP(keysc_in5), + SH_PFC_PIN_GROUP(keysc_in6), + SH_PFC_PIN_GROUP(keysc_in7), + SH_PFC_PIN_GROUP(keysc_out4), + SH_PFC_PIN_GROUP(keysc_out5), + SH_PFC_PIN_GROUP(keysc_out6), + SH_PFC_PIN_GROUP(keysc_out8), + SH_PFC_PIN_GROUP(lcd_data8), + SH_PFC_PIN_GROUP(lcd_data9), + SH_PFC_PIN_GROUP(lcd_data12), + SH_PFC_PIN_GROUP(lcd_data16), + SH_PFC_PIN_GROUP(lcd_data18), + SH_PFC_PIN_GROUP(lcd_data24), + SH_PFC_PIN_GROUP(lcd_display), + SH_PFC_PIN_GROUP(lcd_lclk), + SH_PFC_PIN_GROUP(lcd_sync), + SH_PFC_PIN_GROUP(lcd_sys), SH_PFC_PIN_GROUP(mmc0_data1_0), SH_PFC_PIN_GROUP(mmc0_data4_0), SH_PFC_PIN_GROUP(mmc0_data8_0), @@ -1083,6 +1859,24 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc0_data4_1), SH_PFC_PIN_GROUP(mmc0_data8_1), SH_PFC_PIN_GROUP(mmc0_ctrl_1), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_clk), + SH_PFC_PIN_GROUP(scifa0_ctrl), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_ctrl), + SH_PFC_PIN_GROUP(scifa2_data), + SH_PFC_PIN_GROUP(scifa2_clk), + SH_PFC_PIN_GROUP(scifa2_ctrl), + SH_PFC_PIN_GROUP(scifa3_data), + SH_PFC_PIN_GROUP(scifa3_clk), + SH_PFC_PIN_GROUP(scifa3_ctrl_0), + SH_PFC_PIN_GROUP(scifa3_ctrl_1), + SH_PFC_PIN_GROUP(scifa4_data), + SH_PFC_PIN_GROUP(scifa5_data), + SH_PFC_PIN_GROUP(scifb_data), + SH_PFC_PIN_GROUP(scifb_clk), + SH_PFC_PIN_GROUP(scifb_ctrl), SH_PFC_PIN_GROUP(sdhi0_data1), SH_PFC_PIN_GROUP(sdhi0_data4), SH_PFC_PIN_GROUP(sdhi0_ctrl), @@ -1094,6 +1888,144 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi2_data1), SH_PFC_PIN_GROUP(sdhi2_data4), SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(usb0_vbus), + SH_PFC_PIN_GROUP(usb0_otg_id), + SH_PFC_PIN_GROUP(usb0_otg_ctrl), + SH_PFC_PIN_GROUP(usb1_vbus), + SH_PFC_PIN_GROUP(usb1_otg_id_0), + SH_PFC_PIN_GROUP(usb1_otg_id_1), + SH_PFC_PIN_GROUP(usb1_otg_ctrl_0), + SH_PFC_PIN_GROUP(usb1_otg_ctrl_1), +}; + +static const char * const bsc_groups[] = { + "bsc_data8", + "bsc_data16", + "bsc_cs0", + "bsc_cs2", + "bsc_cs4", + "bsc_cs5a", + "bsc_cs5b", + "bsc_cs6a", + "bsc_rd_we8", + "bsc_rd_we16", + "bsc_bs", + "bsc_rdwr", +}; + +static const char * const ceu_groups[] = { + "ceu_data_0_7", + "ceu_data_8_15", + "ceu_clk_0", + "ceu_clk_1", + "ceu_clk_2", + "ceu_sync", + "ceu_field", +}; + +static const char * const flctl_groups[] = { + "flctl_data", + "flctl_ce0", + "flctl_ce1", + "flctl_ctrl", +}; + +static const char * const fsia_groups[] = { + "fsia_mclk_in", + "fsia_mclk_out", + "fsia_sclk_in", + "fsia_sclk_out", + "fsia_data_in", + "fsia_data_out", + "fsia_spdif_0", + "fsia_spdif_1", +}; + +static const char * const fsib_groups[] = { + "fsib_mclk_in", +}; + +static const char * const hdmi_groups[] = { + "hdmi", +}; + +static const char * const intc_groups[] = { + "intc_irq0_0", + "intc_irq0_1", + "intc_irq1", + "intc_irq2_0", + "intc_irq2_1", + "intc_irq3_0", + "intc_irq3_1", + "intc_irq4_0", + "intc_irq4_1", + "intc_irq5", + "intc_irq6_0", + "intc_irq6_1", + "intc_irq7_0", + "intc_irq7_1", + "intc_irq8_0", + "intc_irq8_1", + "intc_irq9_0", + "intc_irq9_1", + "intc_irq10", + "intc_irq11", + "intc_irq12_0", + "intc_irq12_1", + "intc_irq13_0", + "intc_irq13_1", + "intc_irq14_0", + "intc_irq14_1", + "intc_irq15_0", + "intc_irq15_1", + "intc_irq16_0", + "intc_irq16_1", + "intc_irq17", + "intc_irq18", + "intc_irq19", + "intc_irq20", + "intc_irq21", + "intc_irq22", + "intc_irq23", + "intc_irq24", + "intc_irq25", + "intc_irq26_0", + "intc_irq26_1", + "intc_irq27_0", + "intc_irq27_1", + "intc_irq28_0", + "intc_irq28_1", + "intc_irq29_0", + "intc_irq29_1", + "intc_irq30_0", + "intc_irq30_1", + "intc_irq31_0", + "intc_irq31_1", +}; + +static const char * const keysc_groups[] = { + "keysc_in04_0", + "keysc_in04_1", + "keysc_in5", + "keysc_in6", + "keysc_in7", + "keysc_out4", + "keysc_out5", + "keysc_out6", + "keysc_out8", +}; + +static const char * const lcd_groups[] = { + "lcd_data8", + "lcd_data9", + "lcd_data12", + "lcd_data16", + "lcd_data18", + "lcd_data24", + "lcd_display", + "lcd_lclk", + "lcd_sync", + "lcd_sys", }; static const char * const mmc0_groups[] = { @@ -1107,6 +2039,45 @@ static const char * const mmc0_groups[] = { "mmc0_ctrl_1", }; +static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_clk", + "scifa0_ctrl", +}; + +static const char * const scifa1_groups[] = { + "scifa1_data", + "scifa1_clk", + "scifa1_ctrl", +}; + +static const char * const scifa2_groups[] = { + "scifa2_data", + "scifa2_clk", + "scifa2_ctrl", +}; + +static const char * const scifa3_groups[] = { + "scifa3_data", + "scifa3_clk", + "scifa3_ctrl_0", + "scifa3_ctrl_1", +}; + +static const char * const scifa4_groups[] = { + "scifa4_data", +}; + +static const char * const scifa5_groups[] = { + "scifa5_data", +}; + +static const char * const scifb_groups[] = { + "scifb_data", + "scifb_clk", + "scifb_ctrl", +}; + static const char * const sdhi0_groups[] = { "sdhi0_data1", "sdhi0_data4", @@ -1127,256 +2098,55 @@ static const char * const sdhi2_groups[] = { "sdhi2_ctrl", }; +static const char * const usb0_groups[] = { + "usb0_vbus", + "usb0_otg_id", + "usb0_otg_ctrl", +}; + +static const char * const usb1_groups[] = { + "usb1_vbus", + "usb1_otg_id_0", + "usb1_otg_id_1", + "usb1_otg_ctrl_0", + "usb1_otg_ctrl_1", +}; + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(bsc), + SH_PFC_FUNCTION(ceu), + SH_PFC_FUNCTION(flctl), + SH_PFC_FUNCTION(fsia), + SH_PFC_FUNCTION(fsib), + SH_PFC_FUNCTION(hdmi), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(keysc), + SH_PFC_FUNCTION(lcd), SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifa3), + SH_PFC_FUNCTION(scifa4), + SH_PFC_FUNCTION(scifa5), + SH_PFC_FUNCTION(scifb), SH_PFC_FUNCTION(sdhi0), SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), }; -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) - -static const struct pinmux_func pinmux_func_gpios[] = { - /* IRQ */ - GPIO_FN(IRQ0_6), GPIO_FN(IRQ0_162), GPIO_FN(IRQ1), - GPIO_FN(IRQ2_4), GPIO_FN(IRQ2_5), GPIO_FN(IRQ3_8), - GPIO_FN(IRQ3_16), GPIO_FN(IRQ4_17), GPIO_FN(IRQ4_163), - GPIO_FN(IRQ5), GPIO_FN(IRQ6_39), GPIO_FN(IRQ6_164), - GPIO_FN(IRQ7_40), GPIO_FN(IRQ7_167), GPIO_FN(IRQ8_41), - GPIO_FN(IRQ8_168), GPIO_FN(IRQ9_42), GPIO_FN(IRQ9_169), - GPIO_FN(IRQ10), GPIO_FN(IRQ11), GPIO_FN(IRQ12_80), - GPIO_FN(IRQ12_137), GPIO_FN(IRQ13_81), GPIO_FN(IRQ13_145), - GPIO_FN(IRQ14_82), GPIO_FN(IRQ14_146), GPIO_FN(IRQ15_83), - GPIO_FN(IRQ15_147), GPIO_FN(IRQ16_84), GPIO_FN(IRQ16_170), - GPIO_FN(IRQ17), GPIO_FN(IRQ18), GPIO_FN(IRQ19), - GPIO_FN(IRQ20), GPIO_FN(IRQ21), GPIO_FN(IRQ22), - GPIO_FN(IRQ23), GPIO_FN(IRQ24), GPIO_FN(IRQ25), - GPIO_FN(IRQ26_121), GPIO_FN(IRQ26_172), GPIO_FN(IRQ27_122), - GPIO_FN(IRQ27_180), GPIO_FN(IRQ28_123), GPIO_FN(IRQ28_181), - GPIO_FN(IRQ29_129), GPIO_FN(IRQ29_182), GPIO_FN(IRQ30_130), - GPIO_FN(IRQ30_183), GPIO_FN(IRQ31_138), GPIO_FN(IRQ31_184), - - /* MSIOF0 */ - GPIO_FN(MSIOF0_TSYNC), GPIO_FN(MSIOF0_TSCK), GPIO_FN(MSIOF0_RXD), - GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_MCK0), - GPIO_FN(MSIOF0_MCK1), GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), - GPIO_FN(MSIOF0_TXD), - - /* MSIOF1 */ - GPIO_FN(MSIOF1_TSCK_39), GPIO_FN(MSIOF1_TSCK_88), - GPIO_FN(MSIOF1_TSYNC_40), GPIO_FN(MSIOF1_TSYNC_89), - GPIO_FN(MSIOF1_TXD_41), GPIO_FN(MSIOF1_TXD_90), - GPIO_FN(MSIOF1_RXD_42), GPIO_FN(MSIOF1_RXD_91), - GPIO_FN(MSIOF1_SS1_43), GPIO_FN(MSIOF1_SS1_92), - GPIO_FN(MSIOF1_SS2_44), GPIO_FN(MSIOF1_SS2_93), - GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC), - GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1), - - /* MSIOF2 */ - GPIO_FN(MSIOF2_RSCK), GPIO_FN(MSIOF2_RSYNC), GPIO_FN(MSIOF2_MCK0), - GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_SS1), GPIO_FN(MSIOF2_SS2), - GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_TSCK), GPIO_FN(MSIOF2_RXD), - GPIO_FN(MSIOF2_TXD), - - /* BBIF1 */ - GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TSYNC), GPIO_FN(BBIF1_TSCK), - GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC), - GPIO_FN(BBIF1_FLOW), GPIO_FN(BB_RX_FLOW_N), - - /* BBIF2 */ - GPIO_FN(BBIF2_TSCK1), GPIO_FN(BBIF2_TSYNC1), - GPIO_FN(BBIF2_TXD1), GPIO_FN(BBIF2_RXD), - - /* FSI */ - GPIO_FN(FSIACK), GPIO_FN(FSIBCK), GPIO_FN(FSIAILR), - GPIO_FN(FSIAIBT), GPIO_FN(FSIAISLD), GPIO_FN(FSIAOMC), - GPIO_FN(FSIAOLR), GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), - GPIO_FN(FSIASPDIF_11), GPIO_FN(FSIASPDIF_15), - - /* FMSI */ - GPIO_FN(FMSOCK), GPIO_FN(FMSOOLR), GPIO_FN(FMSIOLR), - GPIO_FN(FMSOOBT), GPIO_FN(FMSIOBT), GPIO_FN(FMSOSLD), - GPIO_FN(FMSOILR), GPIO_FN(FMSIILR), GPIO_FN(FMSOIBT), - GPIO_FN(FMSIIBT), GPIO_FN(FMSISLD), GPIO_FN(FMSICK), - - /* SCIFA0 */ - GPIO_FN(SCIFA0_TXD), GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_SCK), - GPIO_FN(SCIFA0_RTS), GPIO_FN(SCIFA0_CTS), - - /* SCIFA1 */ - GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_SCK), - GPIO_FN(SCIFA1_RTS), GPIO_FN(SCIFA1_CTS), - - /* SCIFA2 */ - GPIO_FN(SCIFA2_CTS1), GPIO_FN(SCIFA2_RTS1), GPIO_FN(SCIFA2_TXD1), - GPIO_FN(SCIFA2_RXD1), GPIO_FN(SCIFA2_SCK1), - - /* SCIFA3 */ - GPIO_FN(SCIFA3_CTS_43), GPIO_FN(SCIFA3_CTS_140), - GPIO_FN(SCIFA3_RTS_44), GPIO_FN(SCIFA3_RTS_141), - GPIO_FN(SCIFA3_SCK), GPIO_FN(SCIFA3_TXD), - GPIO_FN(SCIFA3_RXD), - - /* SCIFA4 */ - GPIO_FN(SCIFA4_RXD), GPIO_FN(SCIFA4_TXD), - - /* SCIFA5 */ - GPIO_FN(SCIFA5_RXD), GPIO_FN(SCIFA5_TXD), - - /* SCIFB */ - GPIO_FN(SCIFB_SCK), GPIO_FN(SCIFB_RTS), GPIO_FN(SCIFB_CTS), - GPIO_FN(SCIFB_TXD), GPIO_FN(SCIFB_RXD), - - /* CEU */ - GPIO_FN(VIO_HD), GPIO_FN(VIO_CKO1), GPIO_FN(VIO_CKO2), - GPIO_FN(VIO_VD), GPIO_FN(VIO_CLK), GPIO_FN(VIO_FIELD), - GPIO_FN(VIO_CKO), GPIO_FN(VIO_D0), GPIO_FN(VIO_D1), - GPIO_FN(VIO_D2), GPIO_FN(VIO_D3), GPIO_FN(VIO_D4), - GPIO_FN(VIO_D5), GPIO_FN(VIO_D6), GPIO_FN(VIO_D7), - GPIO_FN(VIO_D8), GPIO_FN(VIO_D9), GPIO_FN(VIO_D10), - GPIO_FN(VIO_D11), GPIO_FN(VIO_D12), GPIO_FN(VIO_D13), - GPIO_FN(VIO_D14), GPIO_FN(VIO_D15), - - /* USB0 */ - GPIO_FN(IDIN_0), GPIO_FN(EXTLP_0), GPIO_FN(OVCN2_0), - GPIO_FN(PWEN_0), GPIO_FN(OVCN_0), GPIO_FN(VBUS0_0), - - /* USB1 */ - GPIO_FN(IDIN_1_18), GPIO_FN(IDIN_1_113), - GPIO_FN(OVCN_1_114), GPIO_FN(OVCN_1_162), - GPIO_FN(PWEN_1_115), GPIO_FN(PWEN_1_138), - GPIO_FN(EXTLP_1), GPIO_FN(OVCN2_1), - GPIO_FN(VBUS0_1), - - /* GPIO */ - GPIO_FN(GPI0), GPIO_FN(GPI1), GPIO_FN(GPO0), GPIO_FN(GPO1), - - /* BSC */ - GPIO_FN(BS), GPIO_FN(WE1), GPIO_FN(CKO), - GPIO_FN(WAIT), GPIO_FN(RDWR), - - GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), - GPIO_FN(A3), GPIO_FN(A6), GPIO_FN(A7), - GPIO_FN(A8), GPIO_FN(A9), GPIO_FN(A10), - GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13), - GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), - GPIO_FN(A17), GPIO_FN(A18), GPIO_FN(A19), - GPIO_FN(A20), GPIO_FN(A21), GPIO_FN(A22), - GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25), - GPIO_FN(A26), - - GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4), - GPIO_FN(CS5A), GPIO_FN(CS5B), GPIO_FN(CS6A), - - /* BSC/FLCTL */ - GPIO_FN(RD_FSC), GPIO_FN(WE0_FWE), GPIO_FN(A4_FOE), - GPIO_FN(A5_FCDE), GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), - GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), GPIO_FN(D4_NAF4), - GPIO_FN(D5_NAF5), GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), - GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), GPIO_FN(D10_NAF10), - GPIO_FN(D11_NAF11), GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), - GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), - - /* SPU2 */ - GPIO_FN(VINT_I), - - /* FLCTL */ - GPIO_FN(FCE1), GPIO_FN(FCE0), GPIO_FN(FRB), - - /* HSI */ - GPIO_FN(GP_RX_FLAG), GPIO_FN(GP_RX_DATA), GPIO_FN(GP_TX_READY), - GPIO_FN(GP_RX_WAKE), GPIO_FN(MP_TX_FLAG), GPIO_FN(MP_TX_DATA), - GPIO_FN(MP_RX_READY), GPIO_FN(MP_TX_WAKE), - - /* MFI */ - GPIO_FN(MFIv6), - GPIO_FN(MFIv4), - - GPIO_FN(MEMC_BUSCLK_MEMC_A0), GPIO_FN(MEMC_ADV_MEMC_DREQ0), - GPIO_FN(MEMC_WAIT_MEMC_DREQ1), GPIO_FN(MEMC_CS1_MEMC_A1), - GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_NOE), - GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_INT), - - GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2), - GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5), - GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8), - GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11), - GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14), - GPIO_FN(MEMC_AD15), - - /* SIM */ - GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK), GPIO_FN(SIM_D), - - /* TPU */ - GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO2_93), - GPIO_FN(TPU0TO2_99), GPIO_FN(TPU0TO3), - - /* I2C2 */ - GPIO_FN(I2C_SCL2), GPIO_FN(I2C_SDA2), - - /* I2C3(1) */ - GPIO_FN(I2C_SCL3), GPIO_FN(I2C_SDA3), - - /* I2C3(2) */ - GPIO_FN(I2C_SCL3S), GPIO_FN(I2C_SDA3S), - - /* I2C4(2) */ - GPIO_FN(I2C_SCL4), GPIO_FN(I2C_SDA4), - - /* I2C4(2) */ - GPIO_FN(I2C_SCL4S), GPIO_FN(I2C_SDA4S), - - /* KEYSC */ - GPIO_FN(KEYOUT0), GPIO_FN(KEYIN0_121), GPIO_FN(KEYIN0_136), - GPIO_FN(KEYOUT1), GPIO_FN(KEYIN1_122), GPIO_FN(KEYIN1_135), - GPIO_FN(KEYOUT2), GPIO_FN(KEYIN2_123), GPIO_FN(KEYIN2_134), - GPIO_FN(KEYOUT3), GPIO_FN(KEYIN3_124), GPIO_FN(KEYIN3_133), - GPIO_FN(KEYOUT4), GPIO_FN(KEYIN4), GPIO_FN(KEYOUT5), - GPIO_FN(KEYIN5), GPIO_FN(KEYOUT6), GPIO_FN(KEYIN6), - GPIO_FN(KEYOUT7), GPIO_FN(KEYIN7), - - /* LCDC */ - GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDVSYN), - GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(LCDRD), - GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(LCDLCLK), - GPIO_FN(LCDDON), - - GPIO_FN(LCDD0), GPIO_FN(LCDD1), GPIO_FN(LCDD2), - GPIO_FN(LCDD3), GPIO_FN(LCDD4), GPIO_FN(LCDD5), - GPIO_FN(LCDD6), GPIO_FN(LCDD7), GPIO_FN(LCDD8), - GPIO_FN(LCDD9), GPIO_FN(LCDD10), GPIO_FN(LCDD11), - GPIO_FN(LCDD12), GPIO_FN(LCDD13), GPIO_FN(LCDD14), - GPIO_FN(LCDD15), GPIO_FN(LCDD16), GPIO_FN(LCDD17), - GPIO_FN(LCDD18), GPIO_FN(LCDD19), GPIO_FN(LCDD20), - GPIO_FN(LCDD21), GPIO_FN(LCDD22), GPIO_FN(LCDD23), - - GPIO_FN(LCDC0_SELECT), - GPIO_FN(LCDC1_SELECT), - - /* IRDA */ - GPIO_FN(IRDA_OUT), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL), - GPIO_FN(IROUT_139), GPIO_FN(IROUT_140), - - /* TSIF1 */ - GPIO_FN(TS0_1SELECT), - GPIO_FN(TS0_2SELECT), - GPIO_FN(TS1_1SELECT), - GPIO_FN(TS1_2SELECT), - - GPIO_FN(TS_SPSYNC1), GPIO_FN(TS_SDAT1), - GPIO_FN(TS_SDEN1), GPIO_FN(TS_SCK1), - - /* TSIF2 */ - GPIO_FN(TS_SPSYNC2), GPIO_FN(TS_SDAT2), - GPIO_FN(TS_SDEN2), GPIO_FN(TS_SCK2), - - /* HDMI */ - GPIO_FN(HDMI_HPD), GPIO_FN(HDMI_CEC), - - /* SDENC */ - GPIO_FN(SDENC_CPG), - GPIO_FN(SDENC_DV_CLKI), -}; +#undef PORTCR +#define PORTCR(nr, reg) \ + { \ + PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ + _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \ + PORT##nr##_FN0, PORT##nr##_FN1, \ + PORT##nr##_FN2, PORT##nr##_FN3, \ + PORT##nr##_FN4, PORT##nr##_FN5, \ + PORT##nr##_FN6, PORT##nr##_FN7 } \ + } static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xE6051000), /* PORT0CR */ @@ -1776,45 +2546,114 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { #define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5)) #define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5)) static const struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162), - PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12), - PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5), - PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT8, GPIO_PORT16), - PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT17, GPIO_PORT163), - PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT18), - PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT39, GPIO_PORT164), - PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT40, GPIO_PORT167), - PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT41, GPIO_PORT168), - PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT42, GPIO_PORT169), - PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT65), - PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT67), - PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT80, GPIO_PORT137), - PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT81, GPIO_PORT145), - PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT82, GPIO_PORT146), - PINMUX_IRQ(EXT_IRQ16L(15), GPIO_PORT83, GPIO_PORT147), - PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT84, GPIO_PORT170), - PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT85), - PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT86), - PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT87), - PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT92), - PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT93), - PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT94), - PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT95), - PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT112), - PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT119), - PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT121, GPIO_PORT172), - PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT122, GPIO_PORT180), - PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT123, GPIO_PORT181), - PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT129, GPIO_PORT182), - PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT130, GPIO_PORT183), - PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184), + PINMUX_IRQ(EXT_IRQ16L(0), 6, 162), + PINMUX_IRQ(EXT_IRQ16L(1), 12), + PINMUX_IRQ(EXT_IRQ16L(2), 4, 5), + PINMUX_IRQ(EXT_IRQ16L(3), 8, 16), + PINMUX_IRQ(EXT_IRQ16L(4), 17, 163), + PINMUX_IRQ(EXT_IRQ16L(5), 18), + PINMUX_IRQ(EXT_IRQ16L(6), 39, 164), + PINMUX_IRQ(EXT_IRQ16L(7), 40, 167), + PINMUX_IRQ(EXT_IRQ16L(8), 41, 168), + PINMUX_IRQ(EXT_IRQ16L(9), 42, 169), + PINMUX_IRQ(EXT_IRQ16L(10), 65), + PINMUX_IRQ(EXT_IRQ16L(11), 67), + PINMUX_IRQ(EXT_IRQ16L(12), 80, 137), + PINMUX_IRQ(EXT_IRQ16L(13), 81, 145), + PINMUX_IRQ(EXT_IRQ16L(14), 82, 146), + PINMUX_IRQ(EXT_IRQ16L(15), 83, 147), + PINMUX_IRQ(EXT_IRQ16H(16), 84, 170), + PINMUX_IRQ(EXT_IRQ16H(17), 85), + PINMUX_IRQ(EXT_IRQ16H(18), 86), + PINMUX_IRQ(EXT_IRQ16H(19), 87), + PINMUX_IRQ(EXT_IRQ16H(20), 92), + PINMUX_IRQ(EXT_IRQ16H(21), 93), + PINMUX_IRQ(EXT_IRQ16H(22), 94), + PINMUX_IRQ(EXT_IRQ16H(23), 95), + PINMUX_IRQ(EXT_IRQ16H(24), 112), + PINMUX_IRQ(EXT_IRQ16H(25), 119), + PINMUX_IRQ(EXT_IRQ16H(26), 121, 172), + PINMUX_IRQ(EXT_IRQ16H(27), 122, 180), + PINMUX_IRQ(EXT_IRQ16H(28), 123, 181), + PINMUX_IRQ(EXT_IRQ16H(29), 129, 182), + PINMUX_IRQ(EXT_IRQ16H(30), 130, 183), + PINMUX_IRQ(EXT_IRQ16H(31), 138, 184), +}; + +#define PORTnCR_PULMD_OFF (0 << 6) +#define PORTnCR_PULMD_DOWN (2 << 6) +#define PORTnCR_PULMD_UP (3 << 6) +#define PORTnCR_PULMD_MASK (3 << 6) + +struct sh7372_portcr_group { + unsigned int end_pin; + unsigned int offset; +}; + +static const struct sh7372_portcr_group sh7372_portcr_offsets[] = { + { 45, 0x1000 }, { 75, 0x2000 }, { 99, 0x0000 }, { 120, 0x3000 }, + { 151, 0x0000 }, { 155, 0x3000 }, { 166, 0x0000 }, { 190, 0x2000 }, +}; + +static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(sh7372_portcr_offsets); ++i) { + const struct sh7372_portcr_group *group = + &sh7372_portcr_offsets[i]; + + if (i <= group->end_pin) + return pfc->window->virt + group->offset + pin; + } + + return NULL; +} + +static unsigned int sh7372_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) +{ + void __iomem *addr = sh7372_pinmux_portcr(pfc, pin); + u32 value = ioread8(addr) & PORTnCR_PULMD_MASK; + + switch (value) { + case PORTnCR_PULMD_UP: + return PIN_CONFIG_BIAS_PULL_UP; + case PORTnCR_PULMD_DOWN: + return PIN_CONFIG_BIAS_PULL_DOWN; + case PORTnCR_PULMD_OFF: + default: + return PIN_CONFIG_BIAS_DISABLE; + } +} + +static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + void __iomem *addr = sh7372_pinmux_portcr(pfc, pin); + u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK; + + switch (bias) { + case PIN_CONFIG_BIAS_PULL_UP: + value |= PORTnCR_PULMD_UP; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + value |= PORTnCR_PULMD_DOWN; + break; + } + + iowrite8(value, addr); +} + +static const struct sh_pfc_soc_operations sh7372_pinmux_ops = { + .get_bias = sh7372_pinmux_get_bias, + .set_bias = sh7372_pinmux_set_bias, }; const struct sh_pfc_soc_info sh7372_pinmux_info = { .name = "sh7372_pfc", + .ops = &sh7372_pinmux_ops, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, - .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -1825,9 +2664,6 @@ const struct sh_pfc_soc_info sh7372_pinmux_info = { .functions = pinmux_functions, .nr_functions = ARRAY_SIZE(pinmux_functions), - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 587f7772abf..7956df58d75 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -20,9 +20,12 @@ */ #include <linux/io.h> #include <linux/kernel.h> +#include <linux/module.h> #include <linux/pinctrl/pinconf-generic.h> +#include <linux/regulator/driver.h> +#include <linux/regulator/machine.h> +#include <linux/slab.h> -#include <mach/sh73a0.h> #include <mach/irqs.h> #include "core.h" @@ -2538,6 +2541,157 @@ static const unsigned int sdhi2_ctrl_pins[] = { static const unsigned int sdhi2_ctrl_mux[] = { SDHICMD2_MARK, SDHICLK2_MARK, }; +/* - TPU0 ------------------------------------------------------------------- */ +static const unsigned int tpu0_to0_pins[] = { + /* TO */ + 55, +}; +static const unsigned int tpu0_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu0_to1_pins[] = { + /* TO */ + 59, +}; +static const unsigned int tpu0_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu0_to2_pins[] = { + /* TO */ + 140, +}; +static const unsigned int tpu0_to2_mux[] = { + TPU0TO2_MARK, +}; +static const unsigned int tpu0_to3_pins[] = { + /* TO */ + 141, +}; +static const unsigned int tpu0_to3_mux[] = { + TPU0TO3_MARK, +}; +/* - TPU1 ------------------------------------------------------------------- */ +static const unsigned int tpu1_to0_pins[] = { + /* TO */ + 246, +}; +static const unsigned int tpu1_to0_mux[] = { + TPU1TO0_MARK, +}; +static const unsigned int tpu1_to1_0_pins[] = { + /* TO */ + 28, +}; +static const unsigned int tpu1_to1_0_mux[] = { + PORT28_TPU1TO1_MARK, +}; +static const unsigned int tpu1_to1_1_pins[] = { + /* TO */ + 29, +}; +static const unsigned int tpu1_to1_1_mux[] = { + PORT29_TPU1TO1_MARK, +}; +static const unsigned int tpu1_to2_pins[] = { + /* TO */ + 153, +}; +static const unsigned int tpu1_to2_mux[] = { + TPU1TO2_MARK, +}; +static const unsigned int tpu1_to3_pins[] = { + /* TO */ + 145, +}; +static const unsigned int tpu1_to3_mux[] = { + TPU1TO3_MARK, +}; +/* - TPU2 ------------------------------------------------------------------- */ +static const unsigned int tpu2_to0_pins[] = { + /* TO */ + 248, +}; +static const unsigned int tpu2_to0_mux[] = { + TPU2TO0_MARK, +}; +static const unsigned int tpu2_to1_pins[] = { + /* TO */ + 197, +}; +static const unsigned int tpu2_to1_mux[] = { + TPU2TO1_MARK, +}; +static const unsigned int tpu2_to2_pins[] = { + /* TO */ + 50, +}; +static const unsigned int tpu2_to2_mux[] = { + TPU2TO2_MARK, +}; +static const unsigned int tpu2_to3_pins[] = { + /* TO */ + 51, +}; +static const unsigned int tpu2_to3_mux[] = { + TPU2TO3_MARK, +}; +/* - TPU3 ------------------------------------------------------------------- */ +static const unsigned int tpu3_to0_pins[] = { + /* TO */ + 163, +}; +static const unsigned int tpu3_to0_mux[] = { + TPU3TO0_MARK, +}; +static const unsigned int tpu3_to1_pins[] = { + /* TO */ + 247, +}; +static const unsigned int tpu3_to1_mux[] = { + TPU3TO1_MARK, +}; +static const unsigned int tpu3_to2_pins[] = { + /* TO */ + 54, +}; +static const unsigned int tpu3_to2_mux[] = { + TPU3TO2_MARK, +}; +static const unsigned int tpu3_to3_pins[] = { + /* TO */ + 53, +}; +static const unsigned int tpu3_to3_mux[] = { + TPU3TO3_MARK, +}; +/* - TPU4 ------------------------------------------------------------------- */ +static const unsigned int tpu4_to0_pins[] = { + /* TO */ + 241, +}; +static const unsigned int tpu4_to0_mux[] = { + TPU4TO0_MARK, +}; +static const unsigned int tpu4_to1_pins[] = { + /* TO */ + 199, +}; +static const unsigned int tpu4_to1_mux[] = { + TPU4TO1_MARK, +}; +static const unsigned int tpu4_to2_pins[] = { + /* TO */ + 58, +}; +static const unsigned int tpu4_to2_mux[] = { + TPU4TO2_MARK, +}; +static const unsigned int tpu4_to3_pins[] = { + /* TO */ +}; +static const unsigned int tpu4_to3_mux[] = { + TPU4TO3_MARK, +}; /* - USB -------------------------------------------------------------------- */ static const unsigned int usb_vbus_pins[] = { /* VBUS */ @@ -2689,6 +2843,27 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi2_data1), SH_PFC_PIN_GROUP(sdhi2_data4), SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(tpu0_to0), + SH_PFC_PIN_GROUP(tpu0_to1), + SH_PFC_PIN_GROUP(tpu0_to2), + SH_PFC_PIN_GROUP(tpu0_to3), + SH_PFC_PIN_GROUP(tpu1_to0), + SH_PFC_PIN_GROUP(tpu1_to1_0), + SH_PFC_PIN_GROUP(tpu1_to1_1), + SH_PFC_PIN_GROUP(tpu1_to2), + SH_PFC_PIN_GROUP(tpu1_to3), + SH_PFC_PIN_GROUP(tpu2_to0), + SH_PFC_PIN_GROUP(tpu2_to1), + SH_PFC_PIN_GROUP(tpu2_to2), + SH_PFC_PIN_GROUP(tpu2_to3), + SH_PFC_PIN_GROUP(tpu3_to0), + SH_PFC_PIN_GROUP(tpu3_to1), + SH_PFC_PIN_GROUP(tpu3_to2), + SH_PFC_PIN_GROUP(tpu3_to3), + SH_PFC_PIN_GROUP(tpu4_to0), + SH_PFC_PIN_GROUP(tpu4_to1), + SH_PFC_PIN_GROUP(tpu4_to2), + SH_PFC_PIN_GROUP(tpu4_to3), SH_PFC_PIN_GROUP(usb_vbus), }; @@ -2908,6 +3083,42 @@ static const char * const usb_groups[] = { "usb_vbus", }; +static const char * const tpu0_groups[] = { + "tpu0_to0", + "tpu0_to1", + "tpu0_to2", + "tpu0_to3", +}; + +static const char * const tpu1_groups[] = { + "tpu1_to0", + "tpu1_to1_0", + "tpu1_to1_1", + "tpu1_to2", + "tpu1_to3", +}; + +static const char * const tpu2_groups[] = { + "tpu2_to0", + "tpu2_to1", + "tpu2_to2", + "tpu2_to3", +}; + +static const char * const tpu3_groups[] = { + "tpu3_to0", + "tpu3_to1", + "tpu3_to2", + "tpu3_to3", +}; + +static const char * const tpu4_groups[] = { + "tpu4_to0", + "tpu4_to1", + "tpu4_to2", + "tpu4_to3", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(bsc), SH_PFC_FUNCTION(fsia), @@ -2933,400 +3144,14 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi0), SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(tpu0), + SH_PFC_FUNCTION(tpu1), + SH_PFC_FUNCTION(tpu2), + SH_PFC_FUNCTION(tpu3), + SH_PFC_FUNCTION(tpu4), SH_PFC_FUNCTION(usb), }; -#define PINMUX_FN_BASE GPIO_FN_GPI0 - -static const struct pinmux_func pinmux_func_gpios[] = { - /* Table 25-1 (Functions 0-7) */ - GPIO_FN(GPI0), - GPIO_FN(GPI1), - GPIO_FN(GPI2), - GPIO_FN(GPI3), - GPIO_FN(GPI4), - GPIO_FN(GPI5), - GPIO_FN(GPI6), - GPIO_FN(GPI7), - GPIO_FN(GPO7), \ - GPIO_FN(MFG0_OUT2), - GPIO_FN(GPO6), \ - GPIO_FN(MFG1_OUT2), - GPIO_FN(GPO5), \ - GPIO_FN(PORT16_VIO_CKOR), - GPIO_FN(PORT19_VIO_CKO2), - GPIO_FN(GPO0), - GPIO_FN(GPO1), - GPIO_FN(GPO2), \ - GPIO_FN(STATUS0), - GPIO_FN(GPO3), \ - GPIO_FN(STATUS1), - GPIO_FN(GPO4), \ - GPIO_FN(STATUS2), - GPIO_FN(VINT), - GPIO_FN(TCKON), - GPIO_FN(XDVFS1), \ - GPIO_FN(MFG0_OUT1), \ - GPIO_FN(PORT27_IROUT), - GPIO_FN(XDVFS2), \ - GPIO_FN(PORT28_TPU1TO1), - GPIO_FN(SIM_RST), \ - GPIO_FN(PORT29_TPU1TO1), - GPIO_FN(SIM_CLK), \ - GPIO_FN(PORT30_VIO_CKOR), - GPIO_FN(SIM_D), \ - GPIO_FN(PORT31_IROUT), - GPIO_FN(XWUP), - GPIO_FN(VACK), - GPIO_FN(XTAL1L), - GPIO_FN(PORT49_IROUT), \ - GPIO_FN(BBIF2_TSYNC2), \ - GPIO_FN(TPU2TO2), \ - - GPIO_FN(BBIF2_TSCK2), \ - GPIO_FN(TPU2TO3), \ - GPIO_FN(BBIF2_TXD2), - GPIO_FN(TPU3TO3), \ - GPIO_FN(TPU3TO2), \ - GPIO_FN(TPU0TO0), - GPIO_FN(A0), \ - GPIO_FN(BS_), - GPIO_FN(A12), \ - GPIO_FN(TPU4TO2), - GPIO_FN(A13), \ - GPIO_FN(TPU0TO1), - GPIO_FN(A14), \ - GPIO_FN(A15), \ - GPIO_FN(A16), \ - GPIO_FN(MSIOF0_SS1), - GPIO_FN(A17), \ - GPIO_FN(MSIOF0_TSYNC), - GPIO_FN(A18), \ - GPIO_FN(MSIOF0_TSCK), - GPIO_FN(A19), \ - GPIO_FN(MSIOF0_TXD), - GPIO_FN(A20), \ - GPIO_FN(MSIOF0_RSCK), - GPIO_FN(A21), \ - GPIO_FN(MSIOF0_RSYNC), - GPIO_FN(A22), \ - GPIO_FN(MSIOF0_MCK0), - GPIO_FN(A23), \ - GPIO_FN(MSIOF0_MCK1), - GPIO_FN(A24), \ - GPIO_FN(MSIOF0_RXD), - GPIO_FN(A25), \ - GPIO_FN(MSIOF0_SS2), - GPIO_FN(A26), \ - GPIO_FN(FCE1_), - GPIO_FN(DACK0), - GPIO_FN(FCE0_), \ - GPIO_FN(WAIT_), \ - GPIO_FN(DREQ0), - GPIO_FN(FRB), - GPIO_FN(CKO), - GPIO_FN(NBRSTOUT_), - GPIO_FN(NBRST_), - GPIO_FN(BBIF2_TXD), - GPIO_FN(BBIF2_RXD), - GPIO_FN(BBIF2_SYNC), - GPIO_FN(BBIF2_SCK), - GPIO_FN(MFG3_IN2), - GPIO_FN(MFG3_IN1), - GPIO_FN(BBIF1_SS2), \ - GPIO_FN(MFG3_OUT1), - GPIO_FN(HSI_RX_DATA), \ - GPIO_FN(BBIF1_RXD), - GPIO_FN(HSI_TX_WAKE), \ - GPIO_FN(BBIF1_TSCK), - GPIO_FN(HSI_TX_DATA), \ - GPIO_FN(BBIF1_TSYNC), - GPIO_FN(HSI_TX_READY), \ - GPIO_FN(BBIF1_TXD), - GPIO_FN(HSI_RX_READY), \ - GPIO_FN(BBIF1_RSCK), \ - GPIO_FN(HSI_RX_WAKE), \ - GPIO_FN(BBIF1_RSYNC), \ - GPIO_FN(HSI_RX_FLAG), \ - GPIO_FN(BBIF1_SS1), \ - GPIO_FN(BBIF1_FLOW), - GPIO_FN(HSI_TX_FLAG), - GPIO_FN(VIO_VD), \ - GPIO_FN(VIO2_VD), \ - - GPIO_FN(VIO_HD), \ - GPIO_FN(VIO2_HD), \ - GPIO_FN(VIO_D0), \ - GPIO_FN(PORT130_MSIOF2_RXD), \ - GPIO_FN(VIO_D1), \ - GPIO_FN(PORT131_MSIOF2_SS1), \ - GPIO_FN(VIO_D2), \ - GPIO_FN(PORT132_MSIOF2_SS2), \ - GPIO_FN(VIO_D3), \ - GPIO_FN(MSIOF2_TSYNC), \ - GPIO_FN(VIO_D4), \ - GPIO_FN(MSIOF2_TXD), \ - GPIO_FN(VIO_D5), \ - GPIO_FN(MSIOF2_TSCK), \ - GPIO_FN(VIO_D6), \ - GPIO_FN(VIO_D7), \ - GPIO_FN(VIO_D8), \ - GPIO_FN(VIO2_D0), \ - GPIO_FN(VIO_D9), \ - GPIO_FN(VIO2_D1), \ - GPIO_FN(VIO_D10), \ - GPIO_FN(TPU0TO2), \ - GPIO_FN(VIO2_D2), \ - GPIO_FN(VIO_D11), \ - GPIO_FN(TPU0TO3), \ - GPIO_FN(VIO2_D3), \ - GPIO_FN(VIO_D12), \ - GPIO_FN(VIO2_D4), \ - GPIO_FN(VIO_D13), \ - GPIO_FN(VIO2_D5), \ - GPIO_FN(VIO_D14), \ - GPIO_FN(VIO2_D6), \ - GPIO_FN(VIO_D15), \ - GPIO_FN(TPU1TO3), \ - GPIO_FN(VIO2_D7), \ - GPIO_FN(VIO_CLK), \ - GPIO_FN(VIO2_CLK), \ - GPIO_FN(VIO_FIELD), \ - GPIO_FN(VIO2_FIELD), \ - GPIO_FN(VIO_CKO), - GPIO_FN(A27), \ - GPIO_FN(MFG0_IN1), \ - GPIO_FN(MFG0_IN2), - GPIO_FN(TS_SPSYNC3), \ - GPIO_FN(MSIOF2_RSCK), - GPIO_FN(TS_SDAT3), \ - GPIO_FN(MSIOF2_RSYNC), - GPIO_FN(TPU1TO2), \ - GPIO_FN(TS_SDEN3), \ - GPIO_FN(PORT153_MSIOF2_SS1), - GPIO_FN(MSIOF2_MCK0), - GPIO_FN(MSIOF2_MCK1), - GPIO_FN(PORT156_MSIOF2_SS2), - GPIO_FN(PORT157_MSIOF2_RXD), - GPIO_FN(DINT_), \ - GPIO_FN(TS_SCK3), - GPIO_FN(NMI), - GPIO_FN(TPU3TO0), - GPIO_FN(BBIF2_TSYNC1), - GPIO_FN(BBIF2_TSCK1), - GPIO_FN(BBIF2_TXD1), - GPIO_FN(MFG2_OUT2), \ - GPIO_FN(TPU2TO1), - GPIO_FN(TPU4TO1), \ - GPIO_FN(MFG4_OUT2), - GPIO_FN(D16), - GPIO_FN(D17), - GPIO_FN(D18), - GPIO_FN(D19), - GPIO_FN(D20), - GPIO_FN(D21), - GPIO_FN(D22), - GPIO_FN(PORT207_MSIOF0L_SS1), \ - GPIO_FN(D23), - GPIO_FN(PORT208_MSIOF0L_SS2), \ - GPIO_FN(D24), - GPIO_FN(D25), - GPIO_FN(DREQ2), \ - GPIO_FN(PORT210_MSIOF0L_SS1), \ - GPIO_FN(D26), - GPIO_FN(PORT211_MSIOF0L_SS2), \ - GPIO_FN(D27), - GPIO_FN(TS_SPSYNC1), \ - GPIO_FN(MSIOF0L_MCK0), \ - GPIO_FN(D28), - GPIO_FN(TS_SDAT1), \ - GPIO_FN(MSIOF0L_MCK1), \ - GPIO_FN(D29), - GPIO_FN(TS_SDEN1), \ - GPIO_FN(MSIOF0L_RSCK), \ - GPIO_FN(D30), - GPIO_FN(TS_SCK1), \ - GPIO_FN(MSIOF0L_RSYNC), \ - GPIO_FN(D31), - GPIO_FN(DACK2), \ - GPIO_FN(MSIOF0L_TSYNC), \ - GPIO_FN(VIO2_FIELD3), \ - GPIO_FN(DACK3), \ - GPIO_FN(PORT218_VIO_CKOR), - GPIO_FN(DREQ3), \ - GPIO_FN(MSIOF0L_TSCK), \ - GPIO_FN(VIO2_CLK3), \ - GPIO_FN(DREQ1), \ - GPIO_FN(PWEN), \ - GPIO_FN(MSIOF0L_RXD), \ - GPIO_FN(VIO2_HD3), \ - GPIO_FN(DACK1), \ - GPIO_FN(OVCN), \ - GPIO_FN(MSIOF0L_TXD), \ - GPIO_FN(VIO2_VD3), \ - - GPIO_FN(OVCN2), - GPIO_FN(EXTLP), \ - GPIO_FN(PORT226_VIO_CKO2), - GPIO_FN(IDIN), - GPIO_FN(MFG1_IN1), - GPIO_FN(MSIOF1_TXD), \ - GPIO_FN(MSIOF1_TSYNC), \ - GPIO_FN(MSIOF1_TSCK), \ - GPIO_FN(MSIOF1_RXD), \ - GPIO_FN(MSIOF1_RSCK), \ - GPIO_FN(VIO2_CLK2), \ - GPIO_FN(MSIOF1_RSYNC), \ - GPIO_FN(MFG1_IN2), \ - GPIO_FN(VIO2_VD2), \ - GPIO_FN(MSIOF1_MCK0), \ - GPIO_FN(MSIOF1_MCK1), \ - GPIO_FN(MSIOF1_SS1), \ - GPIO_FN(VIO2_FIELD2), \ - GPIO_FN(MSIOF1_SS2), \ - GPIO_FN(VIO2_HD2), \ - GPIO_FN(PORT241_IROUT), \ - GPIO_FN(MFG4_OUT1), \ - GPIO_FN(TPU4TO0), - GPIO_FN(MFG4_IN2), - GPIO_FN(PORT243_VIO_CKO2), - GPIO_FN(MFG2_IN1), \ - GPIO_FN(MSIOF2R_RXD), - GPIO_FN(MFG2_IN2), \ - GPIO_FN(MSIOF2R_TXD), - GPIO_FN(MFG1_OUT1), \ - GPIO_FN(TPU1TO0), - GPIO_FN(MFG3_OUT2), \ - GPIO_FN(TPU3TO1), - GPIO_FN(MFG2_OUT1), \ - GPIO_FN(TPU2TO0), \ - GPIO_FN(MSIOF2R_TSCK), - GPIO_FN(PORT249_IROUT), \ - GPIO_FN(MFG4_IN1), \ - GPIO_FN(MSIOF2R_TSYNC), - GPIO_FN(SDHICLK0), - GPIO_FN(SDHICD0), - GPIO_FN(SDHID0_0), - GPIO_FN(SDHID0_1), - GPIO_FN(SDHID0_2), - GPIO_FN(SDHID0_3), - GPIO_FN(SDHICMD0), - GPIO_FN(SDHIWP0), - GPIO_FN(SDHICLK1), - GPIO_FN(SDHID1_0), \ - GPIO_FN(TS_SPSYNC2), - GPIO_FN(SDHID1_1), \ - GPIO_FN(TS_SDAT2), - GPIO_FN(SDHID1_2), \ - GPIO_FN(TS_SDEN2), - GPIO_FN(SDHID1_3), \ - GPIO_FN(TS_SCK2), - GPIO_FN(SDHICMD1), - GPIO_FN(SDHICLK2), - GPIO_FN(SDHID2_0), \ - GPIO_FN(TS_SPSYNC4), - GPIO_FN(SDHID2_1), \ - GPIO_FN(TS_SDAT4), - GPIO_FN(SDHID2_2), \ - GPIO_FN(TS_SDEN4), - GPIO_FN(SDHID2_3), \ - GPIO_FN(TS_SCK4), - GPIO_FN(SDHICMD2), - GPIO_FN(MMCCLK0), - GPIO_FN(MMCD0_0), - GPIO_FN(MMCD0_1), - GPIO_FN(MMCD0_2), - GPIO_FN(MMCD0_3), - GPIO_FN(MMCD0_4), \ - GPIO_FN(TS_SPSYNC5), - GPIO_FN(MMCD0_5), \ - GPIO_FN(TS_SDAT5), - GPIO_FN(MMCD0_6), \ - GPIO_FN(TS_SDEN5), - GPIO_FN(MMCD0_7), \ - GPIO_FN(TS_SCK5), - GPIO_FN(MMCCMD0), - GPIO_FN(RESETOUTS_), \ - GPIO_FN(EXTAL2OUT), - GPIO_FN(MCP_WAIT__MCP_FRB), - GPIO_FN(MCP_CKO), \ - GPIO_FN(MMCCLK1), - GPIO_FN(MCP_D15_MCP_NAF15), - GPIO_FN(MCP_D14_MCP_NAF14), - GPIO_FN(MCP_D13_MCP_NAF13), - GPIO_FN(MCP_D12_MCP_NAF12), - GPIO_FN(MCP_D11_MCP_NAF11), - GPIO_FN(MCP_D10_MCP_NAF10), - GPIO_FN(MCP_D9_MCP_NAF9), - GPIO_FN(MCP_D8_MCP_NAF8), \ - GPIO_FN(MMCCMD1), - GPIO_FN(MCP_D7_MCP_NAF7), \ - GPIO_FN(MMCD1_7), - - GPIO_FN(MCP_D6_MCP_NAF6), \ - GPIO_FN(MMCD1_6), - GPIO_FN(MCP_D5_MCP_NAF5), \ - GPIO_FN(MMCD1_5), - GPIO_FN(MCP_D4_MCP_NAF4), \ - GPIO_FN(MMCD1_4), - GPIO_FN(MCP_D3_MCP_NAF3), \ - GPIO_FN(MMCD1_3), - GPIO_FN(MCP_D2_MCP_NAF2), \ - GPIO_FN(MMCD1_2), - GPIO_FN(MCP_D1_MCP_NAF1), \ - GPIO_FN(MMCD1_1), - GPIO_FN(MCP_D0_MCP_NAF0), \ - GPIO_FN(MMCD1_0), - GPIO_FN(MCP_NBRSTOUT_), - GPIO_FN(MCP_WE0__MCP_FWE), \ - GPIO_FN(MCP_RDWR_MCP_FWE), - - /* MSEL2 special cases */ - GPIO_FN(TSIF2_TS_XX1), - GPIO_FN(TSIF2_TS_XX2), - GPIO_FN(TSIF2_TS_XX3), - GPIO_FN(TSIF2_TS_XX4), - GPIO_FN(TSIF2_TS_XX5), - GPIO_FN(TSIF1_TS_XX1), - GPIO_FN(TSIF1_TS_XX2), - GPIO_FN(TSIF1_TS_XX3), - GPIO_FN(TSIF1_TS_XX4), - GPIO_FN(TSIF1_TS_XX5), - GPIO_FN(TSIF0_TS_XX1), - GPIO_FN(TSIF0_TS_XX2), - GPIO_FN(TSIF0_TS_XX3), - GPIO_FN(TSIF0_TS_XX4), - GPIO_FN(TSIF0_TS_XX5), - GPIO_FN(MST1_TS_XX1), - GPIO_FN(MST1_TS_XX2), - GPIO_FN(MST1_TS_XX3), - GPIO_FN(MST1_TS_XX4), - GPIO_FN(MST1_TS_XX5), - GPIO_FN(MST0_TS_XX1), - GPIO_FN(MST0_TS_XX2), - GPIO_FN(MST0_TS_XX3), - GPIO_FN(MST0_TS_XX4), - GPIO_FN(MST0_TS_XX5), - - /* MSEL3 special cases */ - GPIO_FN(SDHI0_VCCQ_MC0_ON), - GPIO_FN(SDHI0_VCCQ_MC0_OFF), - GPIO_FN(DEBUG_MON_VIO), - GPIO_FN(DEBUG_MON_LCDD), - GPIO_FN(LCDC_LCDC0), - GPIO_FN(LCDC_LCDC1), - - /* MSEL4 special cases */ - GPIO_FN(IRQ9_MEM_INT), - GPIO_FN(IRQ9_MCP_INT), - GPIO_FN(A11), - GPIO_FN(TPU4TO3), - GPIO_FN(RESETA_N_PU_ON), - GPIO_FN(RESETA_N_PU_OFF), - GPIO_FN(EDBGREQ_PD), - GPIO_FN(EDBGREQ_PU), -}; - #undef PORTCR #define PORTCR(nr, reg) \ { \ @@ -3888,6 +3713,92 @@ static const struct pinmux_irq pinmux_irqs[] = { PINMUX_IRQ(EXT_IRQ16L(9), 308), }; +/* ----------------------------------------------------------------------------- + * VCCQ MC0 regulator + */ + +static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable) +{ + struct sh_pfc *pfc = reg->reg_data; + void __iomem *addr = pfc->window[1].virt + 4; + unsigned long flags; + u32 value; + + spin_lock_irqsave(&pfc->lock, flags); + + value = ioread32(addr); + + if (enable) + value |= BIT(28); + else + value &= ~BIT(28); + + iowrite32(value, addr); + + spin_unlock_irqrestore(&pfc->lock, flags); +} + +static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg) +{ + sh73a0_vccq_mc0_endisable(reg, true); + return 0; +} + +static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg) +{ + sh73a0_vccq_mc0_endisable(reg, false); + return 0; +} + +static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg) +{ + struct sh_pfc *pfc = reg->reg_data; + void __iomem *addr = pfc->window[1].virt + 4; + unsigned long flags; + u32 value; + + spin_lock_irqsave(&pfc->lock, flags); + value = ioread32(addr); + spin_unlock_irqrestore(&pfc->lock, flags); + + return !!(value & BIT(28)); +} + +static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg) +{ + return 3300000; +} + +static struct regulator_ops sh73a0_vccq_mc0_ops = { + .enable = sh73a0_vccq_mc0_enable, + .disable = sh73a0_vccq_mc0_disable, + .is_enabled = sh73a0_vccq_mc0_is_enabled, + .get_voltage = sh73a0_vccq_mc0_get_voltage, +}; + +static const struct regulator_desc sh73a0_vccq_mc0_desc = { + .owner = THIS_MODULE, + .name = "vccq_mc0", + .type = REGULATOR_VOLTAGE, + .ops = &sh73a0_vccq_mc0_ops, +}; + +static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = { + REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), +}; + +static const struct regulator_init_data sh73a0_vccq_mc0_init_data = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers), + .consumer_supplies = sh73a0_vccq_mc0_consumers, +}; + +/* ----------------------------------------------------------------------------- + * Pin bias + */ + #define PORTnCR_PULMD_OFF (0 << 6) #define PORTnCR_PULMD_DOWN (2 << 6) #define PORTnCR_PULMD_UP (3 << 6) @@ -3934,7 +3845,51 @@ static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, iowrite8(value, addr); } +/* ----------------------------------------------------------------------------- + * SoC information + */ + +struct sh73a0_pinmux_data { + struct regulator_dev *vccq_mc0; +}; + +static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc) +{ + struct sh73a0_pinmux_data *data; + struct regulator_config cfg = { }; + int ret; + + data = devm_kzalloc(pfc->dev, sizeof(*data), GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + + cfg.dev = pfc->dev; + cfg.init_data = &sh73a0_vccq_mc0_init_data; + cfg.driver_data = pfc; + + data->vccq_mc0 = regulator_register(&sh73a0_vccq_mc0_desc, &cfg); + if (IS_ERR(data->vccq_mc0)) { + ret = PTR_ERR(data->vccq_mc0); + dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n", + ret); + return ret; + } + + pfc->soc_data = data; + + return 0; +} + +static void sh73a0_pinmux_soc_exit(struct sh_pfc *pfc) +{ + struct sh73a0_pinmux_data *data = pfc->soc_data; + + regulator_unregister(data->vccq_mc0); +} + static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = { + .init = sh73a0_pinmux_soc_init, + .exit = sh73a0_pinmux_soc_exit, .get_bias = sh73a0_pinmux_get_bias, .set_bias = sh73a0_pinmux_set_bias, }; @@ -3956,9 +3911,6 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = { .functions = pinmux_functions, .nr_functions = ARRAY_SIZE(pinmux_functions), - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 3492ec9a33b..bc8b028bb5d 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -14,7 +14,9 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/module.h> +#include <linux/of.h> #include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinctrl.h> @@ -72,11 +74,214 @@ static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, seq_printf(s, "%s", DRV_NAME); } +#ifdef CONFIG_OF +static int sh_pfc_map_add_config(struct pinctrl_map *map, + const char *group_or_pin, + enum pinctrl_map_type type, + unsigned long *configs, + unsigned int num_configs) +{ + unsigned long *cfgs; + + cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), + GFP_KERNEL); + if (cfgs == NULL) + return -ENOMEM; + + map->type = type; + map->data.configs.group_or_pin = group_or_pin; + map->data.configs.configs = cfgs; + map->data.configs.num_configs = num_configs; + + return 0; +} + +static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps, unsigned int *index) +{ + struct pinctrl_map *maps = *map; + unsigned int nmaps = *num_maps; + unsigned int idx = *index; + unsigned int num_configs; + const char *function = NULL; + unsigned long *configs; + struct property *prop; + unsigned int num_groups; + unsigned int num_pins; + const char *group; + const char *pin; + int ret; + + /* Parse the function and configuration properties. At least a function + * or one configuration must be specified. + */ + ret = of_property_read_string(np, "renesas,function", &function); + if (ret < 0 && ret != -EINVAL) { + dev_err(dev, "Invalid function in DT\n"); + return ret; + } + + ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs); + if (ret < 0) + return ret; + + if (!function && num_configs == 0) { + dev_err(dev, + "DT node must contain at least a function or config\n"); + goto done; + } + + /* Count the number of pins and groups and reallocate mappings. */ + ret = of_property_count_strings(np, "renesas,pins"); + if (ret == -EINVAL) { + num_pins = 0; + } else if (ret < 0) { + dev_err(dev, "Invalid pins list in DT\n"); + goto done; + } else { + num_pins = ret; + } + + ret = of_property_count_strings(np, "renesas,groups"); + if (ret == -EINVAL) { + num_groups = 0; + } else if (ret < 0) { + dev_err(dev, "Invalid pin groups list in DT\n"); + goto done; + } else { + num_groups = ret; + } + + if (!num_pins && !num_groups) { + dev_err(dev, "No pin or group provided in DT node\n"); + ret = -ENODEV; + goto done; + } + + if (function) + nmaps += num_groups; + if (configs) + nmaps += num_pins + num_groups; + + maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL); + if (maps == NULL) { + ret = -ENOMEM; + goto done; + } + + *map = maps; + *num_maps = nmaps; + + /* Iterate over pins and groups and create the mappings. */ + of_property_for_each_string(np, "renesas,groups", prop, group) { + if (function) { + maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; + maps[idx].data.mux.group = group; + maps[idx].data.mux.function = function; + idx++; + } + + if (configs) { + ret = sh_pfc_map_add_config(&maps[idx], group, + PIN_MAP_TYPE_CONFIGS_GROUP, + configs, num_configs); + if (ret < 0) + goto done; + + idx++; + } + } + + if (!configs) { + ret = 0; + goto done; + } + + of_property_for_each_string(np, "renesas,pins", prop, pin) { + ret = sh_pfc_map_add_config(&maps[idx], pin, + PIN_MAP_TYPE_CONFIGS_PIN, + configs, num_configs); + if (ret < 0) + goto done; + + idx++; + } + +done: + *index = idx; + kfree(configs); + return ret; +} + +static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ + unsigned int i; + + if (map == NULL) + return; + + for (i = 0; i < num_maps; ++i) { + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || + map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) + kfree(map[i].data.configs.configs); + } + + kfree(map); +} + +static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, unsigned *num_maps) +{ + struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + struct device *dev = pmx->pfc->dev; + struct device_node *child; + unsigned int index; + int ret; + + *map = NULL; + *num_maps = 0; + index = 0; + + for_each_child_of_node(np, child) { + ret = sh_pfc_dt_subnode_to_map(dev, child, map, num_maps, + &index); + if (ret < 0) + goto done; + } + + /* If no mapping has been found in child nodes try the config node. */ + if (*num_maps == 0) { + ret = sh_pfc_dt_subnode_to_map(dev, np, map, num_maps, &index); + if (ret < 0) + goto done; + } + + if (*num_maps) + return 0; + + dev_err(dev, "no mapping found in node %s\n", np->full_name); + ret = -EINVAL; + +done: + if (ret < 0) + sh_pfc_dt_free_map(pctldev, *map, *num_maps); + + return ret; +} +#endif /* CONFIG_OF */ + static const struct pinctrl_ops sh_pfc_pinctrl_ops = { .get_groups_count = sh_pfc_get_groups_count, .get_group_name = sh_pfc_get_group_name, .get_group_pins = sh_pfc_get_group_pins, .pin_dbg_show = sh_pfc_pin_dbg_show, +#ifdef CONFIG_OF + .dt_node_to_map = sh_pfc_dt_node_to_map, + .dt_free_map = sh_pfc_dt_free_map, +#endif }; static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev) diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 3b785fc428d..830ae1ffd0b 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -11,8 +11,8 @@ #ifndef __SH_PFC_H #define __SH_PFC_H +#include <linux/bug.h> #include <linux/stringify.h> -#include <asm-generic/gpio.h> typedef unsigned short pinmux_enum_t; @@ -129,6 +129,8 @@ struct pinmux_range { struct sh_pfc; struct sh_pfc_soc_operations { + int (*init)(struct sh_pfc *pfc); + void (*exit)(struct sh_pfc *pfc); unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, unsigned int bias); diff --git a/drivers/pinctrl/sirf/Makefile b/drivers/pinctrl/sirf/Makefile new file mode 100644 index 00000000000..3ffc475ce40 --- /dev/null +++ b/drivers/pinctrl/sirf/Makefile @@ -0,0 +1,5 @@ +# CSR SiRFsoc pinmux support + +obj-y += pinctrl-sirf.o +obj-y += pinctrl-prima2.o +obj-y += pinctrl-atlas6.o diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c new file mode 100644 index 00000000000..1fa39a44417 --- /dev/null +++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c @@ -0,0 +1,947 @@ +/* + * pinctrl pads, groups, functions for CSR SiRFatlasVI + * + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +#include <linux/pinctrl/pinctrl.h> +#include <linux/bitops.h> + +#include "pinctrl-sirf.h" + +/* + * pad list for the pinmux subsystem + * refer to atlasVI_io_table_v0.93.xls + */ +static const struct pinctrl_pin_desc sirfsoc_pads[] = { + PINCTRL_PIN(0, "gpio0-0"), + PINCTRL_PIN(1, "gpio0-1"), + PINCTRL_PIN(2, "gpio0-2"), + PINCTRL_PIN(3, "gpio0-3"), + PINCTRL_PIN(4, "pwm0"), + PINCTRL_PIN(5, "pwm1"), + PINCTRL_PIN(6, "pwm2"), + PINCTRL_PIN(7, "pwm3"), + PINCTRL_PIN(8, "warm_rst_b"), + PINCTRL_PIN(9, "odo_0"), + PINCTRL_PIN(10, "odo_1"), + PINCTRL_PIN(11, "dr_dir"), + PINCTRL_PIN(12, "rts_0"), + PINCTRL_PIN(13, "scl_1"), + PINCTRL_PIN(14, "ntrst"), + PINCTRL_PIN(15, "sda_1"), + PINCTRL_PIN(16, "x_ldd[16]"), + PINCTRL_PIN(17, "x_ldd[17]"), + PINCTRL_PIN(18, "x_ldd[18]"), + PINCTRL_PIN(19, "x_ldd[19]"), + PINCTRL_PIN(20, "x_ldd[20]"), + PINCTRL_PIN(21, "x_ldd[21]"), + PINCTRL_PIN(22, "x_ldd[22]"), + PINCTRL_PIN(23, "x_ldd[23]"), + PINCTRL_PIN(24, "gps_sgn"), + PINCTRL_PIN(25, "gps_mag"), + PINCTRL_PIN(26, "gps_clk"), + PINCTRL_PIN(27, "sd_cd_b_2"), + PINCTRL_PIN(28, "sd_vcc_on_2"), + PINCTRL_PIN(29, "sd_wp_b_2"), + PINCTRL_PIN(30, "sd_clk_3"), + PINCTRL_PIN(31, "sd_cmd_3"), + + PINCTRL_PIN(32, "x_sd_dat_3[0]"), + PINCTRL_PIN(33, "x_sd_dat_3[1]"), + PINCTRL_PIN(34, "x_sd_dat_3[2]"), + PINCTRL_PIN(35, "x_sd_dat_3[3]"), + PINCTRL_PIN(36, "usb_clk"), + PINCTRL_PIN(37, "usb_dir"), + PINCTRL_PIN(38, "usb_nxt"), + PINCTRL_PIN(39, "usb_stp"), + PINCTRL_PIN(40, "usb_dat[7]"), + PINCTRL_PIN(41, "usb_dat[6]"), + PINCTRL_PIN(42, "x_cko_1"), + PINCTRL_PIN(43, "spi_clk_1"), + PINCTRL_PIN(44, "spi_dout_1"), + PINCTRL_PIN(45, "spi_din_1"), + PINCTRL_PIN(46, "spi_en_1"), + PINCTRL_PIN(47, "x_txd_1"), + PINCTRL_PIN(48, "x_txd_2"), + PINCTRL_PIN(49, "x_rxd_1"), + PINCTRL_PIN(50, "x_rxd_2"), + PINCTRL_PIN(51, "x_usclk_0"), + PINCTRL_PIN(52, "x_utxd_0"), + PINCTRL_PIN(53, "x_urxd_0"), + PINCTRL_PIN(54, "x_utfs_0"), + PINCTRL_PIN(55, "x_urfs_0"), + PINCTRL_PIN(56, "usb_dat5"), + PINCTRL_PIN(57, "usb_dat4"), + PINCTRL_PIN(58, "usb_dat3"), + PINCTRL_PIN(59, "usb_dat2"), + PINCTRL_PIN(60, "usb_dat1"), + PINCTRL_PIN(61, "usb_dat0"), + PINCTRL_PIN(62, "x_ldd[14]"), + PINCTRL_PIN(63, "x_ldd[15]"), + + PINCTRL_PIN(64, "x_gps_gpio"), + PINCTRL_PIN(65, "x_ldd[13]"), + PINCTRL_PIN(66, "x_df_we_b"), + PINCTRL_PIN(67, "x_df_re_b"), + PINCTRL_PIN(68, "x_txd_0"), + PINCTRL_PIN(69, "x_rxd_0"), + PINCTRL_PIN(70, "x_l_lck"), + PINCTRL_PIN(71, "x_l_fck"), + PINCTRL_PIN(72, "x_l_de"), + PINCTRL_PIN(73, "x_ldd[0]"), + PINCTRL_PIN(74, "x_ldd[1]"), + PINCTRL_PIN(75, "x_ldd[2]"), + PINCTRL_PIN(76, "x_ldd[3]"), + PINCTRL_PIN(77, "x_ldd[4]"), + PINCTRL_PIN(78, "x_cko_0"), + PINCTRL_PIN(79, "x_ldd[5]"), + PINCTRL_PIN(80, "x_ldd[6]"), + PINCTRL_PIN(81, "x_ldd[7]"), + PINCTRL_PIN(82, "x_ldd[8]"), + PINCTRL_PIN(83, "x_ldd[9]"), + PINCTRL_PIN(84, "x_ldd[10]"), + PINCTRL_PIN(85, "x_ldd[11]"), + PINCTRL_PIN(86, "x_ldd[12]"), + PINCTRL_PIN(87, "x_vip_vsync"), + PINCTRL_PIN(88, "x_vip_hsync"), + PINCTRL_PIN(89, "x_vip_pxclk"), + PINCTRL_PIN(90, "x_sda_0"), + PINCTRL_PIN(91, "x_scl_0"), + PINCTRL_PIN(92, "x_df_ry_by"), + PINCTRL_PIN(93, "x_df_cs_b[1]"), + PINCTRL_PIN(94, "x_df_cs_b[0]"), + PINCTRL_PIN(95, "x_l_pclk"), + + PINCTRL_PIN(96, "x_df_dqs"), + PINCTRL_PIN(97, "x_df_wp_b"), + PINCTRL_PIN(98, "ac97_sync"), + PINCTRL_PIN(99, "ac97_bit_clk "), + PINCTRL_PIN(100, "ac97_dout"), + PINCTRL_PIN(101, "ac97_din"), + PINCTRL_PIN(102, "x_rtc_io"), +}; + +static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { + { + .group = 1, + .mask = BIT(30) | BIT(31), + }, { + .group = 2, + .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | + BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | + BIT(20) | BIT(21) | BIT(22) | BIT(31), + }, +}; + +static const struct sirfsoc_padmux lcd_16bits_padmux = { + .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask), + .muxmask = lcd_16bits_sirfsoc_muxmask, + .funcmask = BIT(4), + .funcval = 0, +}; + +static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, + 84, 85, 86, 95 }; + +static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = { + { + .group = 2, + .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | + BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | + BIT(20) | BIT(21) | BIT(22) | BIT(31), + }, { + .group = 1, + .mask = BIT(30) | BIT(31), + }, { + .group = 0, + .mask = BIT(16) | BIT(17), + }, +}; + +static const struct sirfsoc_padmux lcd_18bits_padmux = { + .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask), + .muxmask = lcd_18bits_muxmask, + .funcmask = BIT(4) | BIT(15), + .funcval = 0, +}; + +static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, + 84, 85, 86, 95 }; + +static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = { + { + .group = 2, + .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | + BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | + BIT(20) | BIT(21) | BIT(22) | BIT(31), + }, { + .group = 1, + .mask = BIT(30) | BIT(31), + }, { + .group = 0, + .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), + }, +}; + +static const struct sirfsoc_padmux lcd_24bits_padmux = { + .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask), + .muxmask = lcd_24bits_muxmask, + .funcmask = BIT(4) | BIT(15), + .funcval = 0, +}; + +static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, + 80, 81, 82, 83, 84, 85, 86, 95}; + +static const struct sirfsoc_muxmask lcdrom_muxmask[] = { + { + .group = 2, + .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | + BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | + BIT(20) | BIT(21) | BIT(22) | BIT(31), + }, { + .group = 1, + .mask = BIT(30) | BIT(31), + }, { + .group = 0, + .mask = BIT(8), + }, +}; + +static const struct sirfsoc_padmux lcdrom_padmux = { + .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask), + .muxmask = lcdrom_muxmask, + .funcmask = BIT(4), + .funcval = BIT(4), +}; + +static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, + 84, 85, 86, 95}; + +static const struct sirfsoc_muxmask uart0_muxmask[] = { + { + .group = 0, + .mask = BIT(12), + }, { + .group = 1, + .mask = BIT(23), + }, { + .group = 2, + .mask = BIT(4) | BIT(5), + }, +}; + +static const struct sirfsoc_padmux uart0_padmux = { + .muxmask_counts = ARRAY_SIZE(uart0_muxmask), + .muxmask = uart0_muxmask, + .funcmask = BIT(9), + .funcval = BIT(9), +}; + +static const unsigned uart0_pins[] = { 12, 55, 68, 69 }; + +static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = { + { + .group = 2, + .mask = BIT(4) | BIT(5), + }, +}; + +static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = { + .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask), + .muxmask = uart0_nostreamctrl_muxmask, +}; + +static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 }; + +static const struct sirfsoc_muxmask uart1_muxmask[] = { + { + .group = 1, + .mask = BIT(15) | BIT(17), + }, +}; + +static const struct sirfsoc_padmux uart1_padmux = { + .muxmask_counts = ARRAY_SIZE(uart1_muxmask), + .muxmask = uart1_muxmask, +}; + +static const unsigned uart1_pins[] = { 47, 49 }; + +static const struct sirfsoc_muxmask uart2_muxmask[] = { + { + .group = 0, + .mask = BIT(10) | BIT(14), + }, { + .group = 1, + .mask = BIT(16) | BIT(18), + }, +}; + +static const struct sirfsoc_padmux uart2_padmux = { + .muxmask_counts = ARRAY_SIZE(uart2_muxmask), + .muxmask = uart2_muxmask, + .funcmask = BIT(10), + .funcval = BIT(10), +}; + +static const unsigned uart2_pins[] = { 10, 14, 48, 50 }; + +static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = { + { + .group = 1, + .mask = BIT(16) | BIT(18), + }, +}; + +static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = { + .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask), + .muxmask = uart2_nostreamctrl_muxmask, +}; + +static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 }; + +static const struct sirfsoc_muxmask sdmmc3_muxmask[] = { + { + .group = 0, + .mask = BIT(30) | BIT(31), + }, { + .group = 1, + .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3), + }, +}; + +static const struct sirfsoc_padmux sdmmc3_padmux = { + .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask), + .muxmask = sdmmc3_muxmask, + .funcmask = BIT(7), + .funcval = 0, +}; + +static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 }; + +static const struct sirfsoc_muxmask spi0_muxmask[] = { + { + .group = 0, + .mask = BIT(30), + }, { + .group = 1, + .mask = BIT(0) | BIT(2) | BIT(3), + }, +}; + +static const struct sirfsoc_padmux spi0_padmux = { + .muxmask_counts = ARRAY_SIZE(spi0_muxmask), + .muxmask = spi0_muxmask, + .funcmask = BIT(7), + .funcval = BIT(7), +}; + +static const unsigned spi0_pins[] = { 30, 32, 34, 35 }; + +static const struct sirfsoc_muxmask cko1_muxmask[] = { + { + .group = 1, + .mask = BIT(10), + }, +}; + +static const struct sirfsoc_padmux cko1_padmux = { + .muxmask_counts = ARRAY_SIZE(cko1_muxmask), + .muxmask = cko1_muxmask, + .funcmask = BIT(3), + .funcval = 0, +}; + +static const unsigned cko1_pins[] = { 42 }; + +static const struct sirfsoc_muxmask i2s_muxmask[] = { + { + .group = 1, + .mask = BIT(10), + }, { + .group = 3, + .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), + }, +}; + +static const struct sirfsoc_padmux i2s_padmux = { + .muxmask_counts = ARRAY_SIZE(i2s_muxmask), + .muxmask = i2s_muxmask, + .funcmask = BIT(3), + .funcval = BIT(3), +}; + +static const unsigned i2s_pins[] = { 42, 98, 99, 100, 101 }; + +static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = { + { + .group = 1, + .mask = BIT(10), + }, { + .group = 3, + .mask = BIT(2) | BIT(3) | BIT(4), + }, +}; + +static const struct sirfsoc_padmux i2s_no_din_padmux = { + .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask), + .muxmask = i2s_no_din_muxmask, + .funcmask = BIT(3), + .funcval = BIT(3), +}; + +static const unsigned i2s_no_din_pins[] = { 42, 98, 99, 100 }; + +static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = { + { + .group = 1, + .mask = BIT(10) | BIT(20) | BIT(23), + }, { + .group = 3, + .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), + }, +}; + +static const struct sirfsoc_padmux i2s_6chn_padmux = { + .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask), + .muxmask = i2s_6chn_muxmask, + .funcmask = BIT(1) | BIT(3) | BIT(9), + .funcval = BIT(1) | BIT(3) | BIT(9), +}; + +static const unsigned i2s_6chn_pins[] = { 42, 52, 55, 98, 99, 100, 101 }; + +static const struct sirfsoc_muxmask ac97_muxmask[] = { + { + .group = 3, + .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), + }, +}; + +static const struct sirfsoc_padmux ac97_padmux = { + .muxmask_counts = ARRAY_SIZE(ac97_muxmask), + .muxmask = ac97_muxmask, +}; + +static const unsigned ac97_pins[] = { 98, 99, 100, 101 }; + +static const struct sirfsoc_muxmask spi1_muxmask[] = { + { + .group = 1, + .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), + }, +}; + +static const struct sirfsoc_padmux spi1_padmux = { + .muxmask_counts = ARRAY_SIZE(spi1_muxmask), + .muxmask = spi1_muxmask, + .funcmask = BIT(16), + .funcval = 0, +}; + +static const unsigned spi1_pins[] = { 43, 44, 45, 46 }; + +static const struct sirfsoc_muxmask sdmmc1_muxmask[] = { + { + .group = 2, + .mask = BIT(2) | BIT(3), + }, +}; + +static const struct sirfsoc_padmux sdmmc1_padmux = { + .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask), + .muxmask = sdmmc1_muxmask, + .funcmask = BIT(5), + .funcval = BIT(5), +}; + +static const unsigned sdmmc1_pins[] = { 66, 67 }; + +static const struct sirfsoc_muxmask gps_muxmask[] = { + { + .group = 0, + .mask = BIT(24) | BIT(25) | BIT(26), + }, +}; + +static const struct sirfsoc_padmux gps_padmux = { + .muxmask_counts = ARRAY_SIZE(gps_muxmask), + .muxmask = gps_muxmask, + .funcmask = BIT(13), + .funcval = 0, +}; + +static const unsigned gps_pins[] = { 24, 25, 26 }; + +static const struct sirfsoc_muxmask sdmmc5_muxmask[] = { + { + .group = 0, + .mask = BIT(24) | BIT(25) | BIT(26), + }, +}; + +static const struct sirfsoc_padmux sdmmc5_padmux = { + .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask), + .muxmask = sdmmc5_muxmask, + .funcmask = BIT(13), + .funcval = BIT(13), +}; + +static const unsigned sdmmc5_pins[] = { 24, 25, 26 }; + +static const struct sirfsoc_muxmask usp0_muxmask[] = { + { + .group = 1, + .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22), + }, +}; + +static const struct sirfsoc_padmux usp0_padmux = { + .muxmask_counts = ARRAY_SIZE(usp0_muxmask), + .muxmask = usp0_muxmask, + .funcmask = BIT(1) | BIT(2) | BIT(9), + .funcval = 0, +}; + +static const unsigned usp0_pins[] = { 51, 52, 53, 54 }; + +static const struct sirfsoc_muxmask usp1_muxmask[] = { + { + .group = 0, + .mask = BIT(15), + }, { + .group = 1, + .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), + }, +}; + +static const struct sirfsoc_padmux usp1_padmux = { + .muxmask_counts = ARRAY_SIZE(usp1_muxmask), + .muxmask = usp1_muxmask, + .funcmask = BIT(16), + .funcval = BIT(16), +}; + +static const unsigned usp1_pins[] = { 15, 43, 44, 45, 46 }; + +static const struct sirfsoc_muxmask nand_muxmask[] = { + { + .group = 2, + .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30), + }, { + .group = 3, + .mask = BIT(0) | BIT(1), + }, +}; + +static const struct sirfsoc_padmux nand_padmux = { + .muxmask_counts = ARRAY_SIZE(nand_muxmask), + .muxmask = nand_muxmask, + .funcmask = BIT(5) | BIT(19), + .funcval = 0, +}; + +static const unsigned nand_pins[] = { 66, 67, 92, 93, 94, 96, 97 }; + +static const struct sirfsoc_muxmask sdmmc0_muxmask[] = { + { + .group = 3, + .mask = BIT(1), + }, +}; + +static const struct sirfsoc_padmux sdmmc0_padmux = { + .muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask), + .muxmask = sdmmc0_muxmask, + .funcmask = BIT(5) | BIT(19), + .funcval = BIT(19), +}; + +static const unsigned sdmmc0_pins[] = { 97 }; + +static const struct sirfsoc_muxmask sdmmc2_muxmask[] = { + { + .group = 0, + .mask = BIT(27) | BIT(28) | BIT(29), + }, +}; + +static const struct sirfsoc_padmux sdmmc2_padmux = { + .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask), + .muxmask = sdmmc2_muxmask, + .funcmask = BIT(11), + .funcval = 0, +}; + +static const unsigned sdmmc2_pins[] = { 27, 28, 29 }; + +static const struct sirfsoc_muxmask sdmmc2_nowp_muxmask[] = { + { + .group = 0, + .mask = BIT(27) | BIT(28), + }, +}; + +static const struct sirfsoc_padmux sdmmc2_nowp_padmux = { + .muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask), + .muxmask = sdmmc2_nowp_muxmask, + .funcmask = BIT(11), + .funcval = 0, +}; + +static const unsigned sdmmc2_nowp_pins[] = { 27, 28 }; + +static const struct sirfsoc_muxmask cko0_muxmask[] = { + { + .group = 2, + .mask = BIT(14), + }, +}; + +static const struct sirfsoc_padmux cko0_padmux = { + .muxmask_counts = ARRAY_SIZE(cko0_muxmask), + .muxmask = cko0_muxmask, +}; + +static const unsigned cko0_pins[] = { 78 }; + +static const struct sirfsoc_muxmask vip_muxmask[] = { + { + .group = 1, + .mask = BIT(4) | BIT(5) | BIT(6) | BIT(8) | BIT(9) + | BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28) | + BIT(29), + }, +}; + +static const struct sirfsoc_padmux vip_padmux = { + .muxmask_counts = ARRAY_SIZE(vip_muxmask), + .muxmask = vip_muxmask, + .funcmask = BIT(18), + .funcval = BIT(18), +}; + +static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59, 60, 61 }; + +static const struct sirfsoc_muxmask vip_noupli_muxmask[] = { + { + .group = 0, + .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) + | BIT(21) | BIT(22) | BIT(23), + }, { + .group = 2, + .mask = BIT(23) | BIT(24) | BIT(25), + }, +}; + +static const struct sirfsoc_padmux vip_noupli_padmux = { + .muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask), + .muxmask = vip_noupli_muxmask, + .funcmask = BIT(15), + .funcval = BIT(15), +}; + +static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 87, 88, 89 }; + +static const struct sirfsoc_muxmask i2c0_muxmask[] = { + { + .group = 2, + .mask = BIT(26) | BIT(27), + }, +}; + +static const struct sirfsoc_padmux i2c0_padmux = { + .muxmask_counts = ARRAY_SIZE(i2c0_muxmask), + .muxmask = i2c0_muxmask, +}; + +static const unsigned i2c0_pins[] = { 90, 91 }; + +static const struct sirfsoc_muxmask i2c1_muxmask[] = { + { + .group = 0, + .mask = BIT(13) | BIT(15), + }, +}; + +static const struct sirfsoc_padmux i2c1_padmux = { + .muxmask_counts = ARRAY_SIZE(i2c1_muxmask), + .muxmask = i2c1_muxmask, + .funcmask = BIT(16), + .funcval = 0, +}; + +static const unsigned i2c1_pins[] = { 13, 15 }; + +static const struct sirfsoc_muxmask pwm0_muxmask[] = { + { + .group = 0, + .mask = BIT(4), + }, +}; + +static const struct sirfsoc_padmux pwm0_padmux = { + .muxmask_counts = ARRAY_SIZE(pwm0_muxmask), + .muxmask = pwm0_muxmask, + .funcmask = BIT(12), + .funcval = 0, +}; + +static const unsigned pwm0_pins[] = { 4 }; + +static const struct sirfsoc_muxmask pwm1_muxmask[] = { + { + .group = 0, + .mask = BIT(5), + }, +}; + +static const struct sirfsoc_padmux pwm1_padmux = { + .muxmask_counts = ARRAY_SIZE(pwm1_muxmask), + .muxmask = pwm1_muxmask, +}; + +static const unsigned pwm1_pins[] = { 5 }; + +static const struct sirfsoc_muxmask pwm2_muxmask[] = { + { + .group = 0, + .mask = BIT(6), + }, +}; + +static const struct sirfsoc_padmux pwm2_padmux = { + .muxmask_counts = ARRAY_SIZE(pwm2_muxmask), + .muxmask = pwm2_muxmask, +}; + +static const unsigned pwm2_pins[] = { 6 }; + +static const struct sirfsoc_muxmask pwm3_muxmask[] = { + { + .group = 0, + .mask = BIT(7), + }, +}; + +static const struct sirfsoc_padmux pwm3_padmux = { + .muxmask_counts = ARRAY_SIZE(pwm3_muxmask), + .muxmask = pwm3_muxmask, +}; + +static const unsigned pwm3_pins[] = { 7 }; + +static const struct sirfsoc_muxmask pwm4_muxmask[] = { + { + .group = 2, + .mask = BIT(14), + }, +}; + +static const struct sirfsoc_padmux pwm4_padmux = { + .muxmask_counts = ARRAY_SIZE(pwm4_muxmask), + .muxmask = pwm4_muxmask, +}; + +static const unsigned pwm4_pins[] = { 78 }; + +static const struct sirfsoc_muxmask warm_rst_muxmask[] = { + { + .group = 0, + .mask = BIT(8), + }, +}; + +static const struct sirfsoc_padmux warm_rst_padmux = { + .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask), + .muxmask = warm_rst_muxmask, + .funcmask = BIT(4), + .funcval = 0, +}; + +static const unsigned warm_rst_pins[] = { 8 }; + +static const struct sirfsoc_muxmask usb0_upli_drvbus_muxmask[] = { + { + .group = 1, + .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) + | BIT(9) | BIT(24) | BIT(25) | BIT(26) | + BIT(27) | BIT(28) | BIT(29), + }, +}; +static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = { + .muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask), + .muxmask = usb0_upli_drvbus_muxmask, + .funcmask = BIT(18), + .funcval = 0, +}; + +static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40, 41, 56, 57, 58, 59, 60, 61 }; + +static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = { + { + .group = 0, + .mask = BIT(28), + }, +}; + +static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = { + .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask), + .muxmask = usb1_utmi_drvbus_muxmask, + .funcmask = BIT(11), + .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */ +}; + +static const unsigned usb1_utmi_drvbus_pins[] = { 28 }; + +static const struct sirfsoc_muxmask pulse_count_muxmask[] = { + { + .group = 0, + .mask = BIT(9) | BIT(10) | BIT(11), + }, +}; + +static const struct sirfsoc_padmux pulse_count_padmux = { + .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask), + .muxmask = pulse_count_muxmask, +}; + +static const unsigned pulse_count_pins[] = { 9, 10, 11 }; + +static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { + SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins), + SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins), + SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins), + SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins), + SIRFSOC_PIN_GROUP("uart0grp", uart0_pins), + SIRFSOC_PIN_GROUP("uart1grp", uart1_pins), + SIRFSOC_PIN_GROUP("uart2grp", uart2_pins), + SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins), + SIRFSOC_PIN_GROUP("usp0grp", usp0_pins), + SIRFSOC_PIN_GROUP("usp1grp", usp1_pins), + SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins), + SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins), + SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins), + SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins), + SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins), + SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins), + SIRFSOC_PIN_GROUP("pwm4grp", pwm4_pins), + SIRFSOC_PIN_GROUP("vipgrp", vip_pins), + SIRFSOC_PIN_GROUP("vip_noupligrp", vip_noupli_pins), + SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins), + SIRFSOC_PIN_GROUP("cko0grp", cko0_pins), + SIRFSOC_PIN_GROUP("cko1grp", cko1_pins), + SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins), + SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins), + SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins), + SIRFSOC_PIN_GROUP("sdmmc2_nowpgrp", sdmmc2_nowp_pins), + SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins), + SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins), + SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins), + SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins), + SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), + SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), + SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins), + SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins), + SIRFSOC_PIN_GROUP("ac97grp", ac97_pins), + SIRFSOC_PIN_GROUP("nandgrp", nand_pins), + SIRFSOC_PIN_GROUP("spi0grp", spi0_pins), + SIRFSOC_PIN_GROUP("spi1grp", spi1_pins), + SIRFSOC_PIN_GROUP("gpsgrp", gps_pins), +}; + +static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" }; +static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" }; +static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" }; +static const char * const lcdromgrp[] = { "lcdromgrp" }; +static const char * const uart0grp[] = { "uart0grp" }; +static const char * const uart1grp[] = { "uart1grp" }; +static const char * const uart2grp[] = { "uart2grp" }; +static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" }; +static const char * const usp0grp[] = { "usp0grp" }; +static const char * const usp1grp[] = { "usp1grp" }; +static const char * const i2c0grp[] = { "i2c0grp" }; +static const char * const i2c1grp[] = { "i2c1grp" }; +static const char * const pwm0grp[] = { "pwm0grp" }; +static const char * const pwm1grp[] = { "pwm1grp" }; +static const char * const pwm2grp[] = { "pwm2grp" }; +static const char * const pwm3grp[] = { "pwm3grp" }; +static const char * const pwm4grp[] = { "pwm4grp" }; +static const char * const vipgrp[] = { "vipgrp" }; +static const char * const vip_noupligrp[] = { "vip_noupligrp" }; +static const char * const warm_rstgrp[] = { "warm_rstgrp" }; +static const char * const cko0grp[] = { "cko0grp" }; +static const char * const cko1grp[] = { "cko1grp" }; +static const char * const sdmmc0grp[] = { "sdmmc0grp" }; +static const char * const sdmmc1grp[] = { "sdmmc1grp" }; +static const char * const sdmmc2grp[] = { "sdmmc2grp" }; +static const char * const sdmmc3grp[] = { "sdmmc3grp" }; +static const char * const sdmmc5grp[] = { "sdmmc5grp" }; +static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" }; +static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" }; +static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; +static const char * const pulse_countgrp[] = { "pulse_countgrp" }; +static const char * const i2sgrp[] = { "i2sgrp" }; +static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" }; +static const char * const i2s_6chngrp[] = { "i2s_6chngrp" }; +static const char * const ac97grp[] = { "ac97grp" }; +static const char * const nandgrp[] = { "nandgrp" }; +static const char * const spi0grp[] = { "spi0grp" }; +static const char * const spi1grp[] = { "spi1grp" }; +static const char * const gpsgrp[] = { "gpsgrp" }; + +static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { + SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux), + SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux), + SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux), + SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux), + SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux), + SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux), + SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux), + SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), + SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux), + SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux), + SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux), + SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux), + SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux), + SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux), + SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux), + SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux), + SIRFSOC_PMX_FUNCTION("pwm4", pwm4grp, pwm4_padmux), + SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux), + SIRFSOC_PMX_FUNCTION("vip_noupli", vip_noupligrp, vip_noupli_padmux), + SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux), + SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux), + SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux), + SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux), + SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux), + SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux), + SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux), + SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux), + SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", sdmmc2_nowpgrp, sdmmc2_nowp_padmux), + SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux), + SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), + SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), + SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), + SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux), + SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux), + SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux), + SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux), + SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux), + SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux), + SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux), +}; + +struct sirfsoc_pinctrl_data atlas6_pinctrl_data = { + (struct pinctrl_pin_desc *)sirfsoc_pads, + ARRAY_SIZE(sirfsoc_pads), + (struct sirfsoc_pin_group *)sirfsoc_pin_groups, + ARRAY_SIZE(sirfsoc_pin_groups), + (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions, + ARRAY_SIZE(sirfsoc_pmx_functions), +}; + diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-prima2.c index bc9d1be27fb..1f0ad1ef5a3 100644 --- a/drivers/pinctrl/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-prima2.c @@ -1,70 +1,15 @@ /* - * pinmux driver for CSR SiRFprimaII + * pinctrl pads, groups, functions for CSR SiRFprimaII * * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. * * Licensed under GPLv2 or later. */ -#include <linux/init.h> -#include <linux/module.h> -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/err.h> -#include <linux/irqdomain.h> -#include <linux/irqchip/chained_irq.h> #include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/consumer.h> -#include <linux/pinctrl/machine.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> -#include <linux/of_platform.h> #include <linux/bitops.h> -#include <linux/gpio.h> -#include <linux/of_gpio.h> - -#define DRIVER_NAME "pinmux-sirf" - -#define SIRFSOC_NUM_PADS 622 -#define SIRFSOC_RSC_PIN_MUX 0x4 - -#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84) -#define SIRFSOC_GPIO_PAD_EN_CLR(g) ((g)*0x100 + 0x90) -#define SIRFSOC_GPIO_CTRL(g, i) ((g)*0x100 + (i)*4) -#define SIRFSOC_GPIO_DSP_EN0 (0x80) -#define SIRFSOC_GPIO_INT_STATUS(g) ((g)*0x100 + 0x8C) - -#define SIRFSOC_GPIO_CTL_INTR_LOW_MASK 0x1 -#define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK 0x2 -#define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK 0x4 -#define SIRFSOC_GPIO_CTL_INTR_EN_MASK 0x8 -#define SIRFSOC_GPIO_CTL_INTR_STS_MASK 0x10 -#define SIRFSOC_GPIO_CTL_OUT_EN_MASK 0x20 -#define SIRFSOC_GPIO_CTL_DATAOUT_MASK 0x40 -#define SIRFSOC_GPIO_CTL_DATAIN_MASK 0x80 -#define SIRFSOC_GPIO_CTL_PULL_MASK 0x100 -#define SIRFSOC_GPIO_CTL_PULL_HIGH 0x200 -#define SIRFSOC_GPIO_CTL_DSP_INT 0x400 - -#define SIRFSOC_GPIO_NO_OF_BANKS 5 -#define SIRFSOC_GPIO_BANK_SIZE 32 -#define SIRFSOC_GPIO_NUM(bank, index) (((bank)*(32)) + (index)) - -struct sirfsoc_gpio_bank { - struct of_mm_gpio_chip chip; - struct irq_domain *domain; - int id; - int parent_irq; - spinlock_t lock; - bool is_marco; /* for marco, some registers are different with prima2 */ -}; - -static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS]; -static DEFINE_SPINLOCK(sgpio_lock); + +#include "pinctrl-sirf.h" /* * pad list for the pinmux subsystem @@ -183,46 +128,6 @@ static const struct pinctrl_pin_desc sirfsoc_pads[] = { PINCTRL_PIN(114, "x_ldd[15]"), }; -/** - * @dev: a pointer back to containing device - * @virtbase: the offset to the controller in virtual memory - */ -struct sirfsoc_pmx { - struct device *dev; - struct pinctrl_dev *pmx; - void __iomem *gpio_virtbase; - void __iomem *rsc_virtbase; - bool is_marco; -}; - -/* SIRFSOC_GPIO_PAD_EN set */ -struct sirfsoc_muxmask { - unsigned long group; - unsigned long mask; -}; - -struct sirfsoc_padmux { - unsigned long muxmask_counts; - const struct sirfsoc_muxmask *muxmask; - /* RSC_PIN_MUX set */ - unsigned long funcmask; - unsigned long funcval; -}; - - /** - * struct sirfsoc_pin_group - describes a SiRFprimaII pin group - * @name: the name of this specific pin group - * @pins: an array of discrete physical pins used in this group, taken - * from the driver-local pin enumeration space - * @num_pins: the number of pins in this group array, i.e. the number of - * elements in .pins so we can iterate over that array - */ -struct sirfsoc_pin_group { - const char *name; - const unsigned int *pins; - const unsigned num_pins; -}; - static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { { .group = 3, @@ -351,7 +256,7 @@ static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = { .muxmask = uart0_nostreamctrl_muxmask, }; -static const unsigned uart0_nostreamctrl_pins[] = { 68, 39 }; +static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 }; static const struct sirfsoc_muxmask uart1_muxmask[] = { { @@ -853,13 +758,6 @@ static const struct sirfsoc_padmux pulse_count_padmux = { static const unsigned pulse_count_pins[] = { 9, 10, 11 }; -#define SIRFSOC_PIN_GROUP(n, p) \ - { \ - .name = n, \ - .pins = p, \ - .num_pins = ARRAY_SIZE(p), \ - } - static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins), SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins), @@ -881,8 +779,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { SIRFSOC_PIN_GROUP("vipgrp", vip_pins), SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins), SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins), - SIRFSOC_PIN_GROUP("cko0_rstgrp", cko0_pins), - SIRFSOC_PIN_GROUP("cko1_rstgrp", cko1_pins), + SIRFSOC_PIN_GROUP("cko0grp", cko0_pins), + SIRFSOC_PIN_GROUP("cko1grp", cko1_pins), SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins), SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins), SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins), @@ -900,101 +798,6 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { SIRFSOC_PIN_GROUP("gpsgrp", gps_pins), }; -static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev) -{ - return ARRAY_SIZE(sirfsoc_pin_groups); -} - -static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - return sirfsoc_pin_groups[selector].name; -} - -static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - const unsigned **pins, - unsigned *num_pins) -{ - *pins = sirfsoc_pin_groups[selector].pins; - *num_pins = sirfsoc_pin_groups[selector].num_pins; - return 0; -} - -static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned offset) -{ - seq_printf(s, " " DRIVER_NAME); -} - -static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, unsigned *num_maps) -{ - struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev); - struct device_node *np; - struct property *prop; - const char *function, *group; - int ret, index = 0, count = 0; - - /* calculate number of maps required */ - for_each_child_of_node(np_config, np) { - ret = of_property_read_string(np, "sirf,function", &function); - if (ret < 0) - return ret; - - ret = of_property_count_strings(np, "sirf,pins"); - if (ret < 0) - return ret; - - count += ret; - } - - if (!count) { - dev_err(spmx->dev, "No child nodes passed via DT\n"); - return -ENODEV; - } - - *map = kzalloc(sizeof(**map) * count, GFP_KERNEL); - if (!*map) - return -ENOMEM; - - for_each_child_of_node(np_config, np) { - of_property_read_string(np, "sirf,function", &function); - of_property_for_each_string(np, "sirf,pins", prop, group) { - (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP; - (*map)[index].data.mux.group = group; - (*map)[index].data.mux.function = function; - index++; - } - } - - *num_maps = count; - - return 0; -} - -static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - kfree(map); -} - -static const struct pinctrl_ops sirfsoc_pctrl_ops = { - .get_groups_count = sirfsoc_get_groups_count, - .get_group_name = sirfsoc_get_group_name, - .get_group_pins = sirfsoc_get_group_pins, - .pin_dbg_show = sirfsoc_pin_dbg_show, - .dt_node_to_map = sirfsoc_dt_node_to_map, - .dt_free_map = sirfsoc_dt_free_map, -}; - -struct sirfsoc_pmx_func { - const char *name; - const char * const *groups; - const unsigned num_groups; - const struct sirfsoc_padmux *padmux; -}; - static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" }; static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" }; static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" }; @@ -1033,14 +836,6 @@ static const char * const spi0grp[] = { "spi0grp" }; static const char * const spi1grp[] = { "spi1grp" }; static const char * const gpsgrp[] = { "gpsgrp" }; -#define SIRFSOC_PMX_FUNCTION(n, g, m) \ - { \ - .name = n, \ - .groups = g, \ - .num_groups = ARRAY_SIZE(g), \ - .padmux = &m, \ - } - static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux), SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux), @@ -1081,730 +876,12 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux), }; -static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector, - bool enable) -{ - int i; - const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux; - const struct sirfsoc_muxmask *mask = mux->muxmask; - - for (i = 0; i < mux->muxmask_counts; i++) { - u32 muxval; - if (!spmx->is_marco) { - muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); - if (enable) - muxval = muxval & ~mask[i].mask; - else - muxval = muxval | mask[i].mask; - writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); - } else { - if (enable) - writel(mask[i].mask, spmx->gpio_virtbase + - SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group)); - else - writel(mask[i].mask, spmx->gpio_virtbase + - SIRFSOC_GPIO_PAD_EN(mask[i].group)); - } - } - - if (mux->funcmask && enable) { - u32 func_en_val; - func_en_val = - readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX); - func_en_val = - (func_en_val & ~mux->funcmask) | (mux-> - funcval); - writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX); - } -} - -static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector, - unsigned group) -{ - struct sirfsoc_pmx *spmx; - - spmx = pinctrl_dev_get_drvdata(pmxdev); - sirfsoc_pinmux_endisable(spmx, selector, true); - - return 0; -} - -static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector, - unsigned group) -{ - struct sirfsoc_pmx *spmx; - - spmx = pinctrl_dev_get_drvdata(pmxdev); - sirfsoc_pinmux_endisable(spmx, selector, false); -} - -static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev) -{ - return ARRAY_SIZE(sirfsoc_pmx_functions); -} - -static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - return sirfsoc_pmx_functions[selector].name; -} - -static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector, - const char * const **groups, - unsigned * const num_groups) -{ - *groups = sirfsoc_pmx_functions[selector].groups; - *num_groups = sirfsoc_pmx_functions[selector].num_groups; - return 0; -} - -static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, - struct pinctrl_gpio_range *range, unsigned offset) -{ - struct sirfsoc_pmx *spmx; - - int group = range->id; - - u32 muxval; - - spmx = pinctrl_dev_get_drvdata(pmxdev); - - if (!spmx->is_marco) { - muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); - muxval = muxval | (1 << (offset - range->pin_base)); - writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); - } else { - writel(1 << (offset - range->pin_base), spmx->gpio_virtbase + - SIRFSOC_GPIO_PAD_EN(group)); - } - - return 0; -} - -static const struct pinmux_ops sirfsoc_pinmux_ops = { - .enable = sirfsoc_pinmux_enable, - .disable = sirfsoc_pinmux_disable, - .get_functions_count = sirfsoc_pinmux_get_funcs_count, - .get_function_name = sirfsoc_pinmux_get_func_name, - .get_function_groups = sirfsoc_pinmux_get_groups, - .gpio_request_enable = sirfsoc_pinmux_request_gpio, -}; - -static struct pinctrl_desc sirfsoc_pinmux_desc = { - .name = DRIVER_NAME, - .pins = sirfsoc_pads, - .npins = ARRAY_SIZE(sirfsoc_pads), - .pctlops = &sirfsoc_pctrl_ops, - .pmxops = &sirfsoc_pinmux_ops, - .owner = THIS_MODULE, -}; - -/* - * Todo: bind irq_chip to every pinctrl_gpio_range - */ -static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = { - { - .name = "sirfsoc-gpio*", - .id = 0, - .base = 0, - .pin_base = 0, - .npins = 32, - }, { - .name = "sirfsoc-gpio*", - .id = 1, - .base = 32, - .pin_base = 32, - .npins = 32, - }, { - .name = "sirfsoc-gpio*", - .id = 2, - .base = 64, - .pin_base = 64, - .npins = 32, - }, { - .name = "sirfsoc-gpio*", - .id = 3, - .base = 96, - .pin_base = 96, - .npins = 19, - }, -}; - -static void __iomem *sirfsoc_rsc_of_iomap(void) -{ - const struct of_device_id rsc_ids[] = { - { .compatible = "sirf,prima2-rsc" }, - { .compatible = "sirf,marco-rsc" }, - {} - }; - struct device_node *np; - - np = of_find_matching_node(NULL, rsc_ids); - if (!np) - panic("unable to find compatible rsc node in dtb\n"); - - return of_iomap(np, 0); -} - -static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc, - const struct of_phandle_args *gpiospec, - u32 *flags) -{ - if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE) - return -EINVAL; - - if (gc != &sgpio_bank[gpiospec->args[0] / SIRFSOC_GPIO_BANK_SIZE].chip.gc) - return -EINVAL; - - if (flags) - *flags = gpiospec->args[1]; - - return gpiospec->args[0] % SIRFSOC_GPIO_BANK_SIZE; -} - -static int sirfsoc_pinmux_probe(struct platform_device *pdev) -{ - int ret; - struct sirfsoc_pmx *spmx; - struct device_node *np = pdev->dev.of_node; - int i; - - /* Create state holders etc for this driver */ - spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL); - if (!spmx) - return -ENOMEM; - - spmx->dev = &pdev->dev; - - platform_set_drvdata(pdev, spmx); - - spmx->gpio_virtbase = of_iomap(np, 0); - if (!spmx->gpio_virtbase) { - ret = -ENOMEM; - dev_err(&pdev->dev, "can't map gpio registers\n"); - goto out_no_gpio_remap; - } - - spmx->rsc_virtbase = sirfsoc_rsc_of_iomap(); - if (!spmx->rsc_virtbase) { - ret = -ENOMEM; - dev_err(&pdev->dev, "can't map rsc registers\n"); - goto out_no_rsc_remap; - } - - if (of_device_is_compatible(np, "sirf,marco-pinctrl")) - spmx->is_marco = 1; - - /* Now register the pin controller and all pins it handles */ - spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx); - if (!spmx->pmx) { - dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n"); - ret = -EINVAL; - goto out_no_pmx; - } - - for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) { - sirfsoc_gpio_ranges[i].gc = &sgpio_bank[i].chip.gc; - pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]); - } - - dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n"); - - return 0; - -out_no_pmx: - iounmap(spmx->rsc_virtbase); -out_no_rsc_remap: - iounmap(spmx->gpio_virtbase); -out_no_gpio_remap: - platform_set_drvdata(pdev, NULL); - return ret; -} - -static const struct of_device_id pinmux_ids[] = { - { .compatible = "sirf,prima2-pinctrl" }, - { .compatible = "sirf,marco-pinctrl" }, - {} -}; - -static struct platform_driver sirfsoc_pinmux_driver = { - .driver = { - .name = DRIVER_NAME, - .owner = THIS_MODULE, - .of_match_table = pinmux_ids, - }, - .probe = sirfsoc_pinmux_probe, +struct sirfsoc_pinctrl_data prima2_pinctrl_data = { + (struct pinctrl_pin_desc *)sirfsoc_pads, + ARRAY_SIZE(sirfsoc_pads), + (struct sirfsoc_pin_group *)sirfsoc_pin_groups, + ARRAY_SIZE(sirfsoc_pin_groups), + (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions, + ARRAY_SIZE(sirfsoc_pmx_functions), }; -static int __init sirfsoc_pinmux_init(void) -{ - return platform_driver_register(&sirfsoc_pinmux_driver); -} -arch_initcall(sirfsoc_pinmux_init); - -static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip), - struct sirfsoc_gpio_bank, chip); - - return irq_create_mapping(bank->domain, offset); -} - -static inline int sirfsoc_gpio_to_offset(unsigned int gpio) -{ - return gpio % SIRFSOC_GPIO_BANK_SIZE; -} - -static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio) -{ - return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE]; -} - -static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip) -{ - return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip); -} - -static void sirfsoc_gpio_irq_ack(struct irq_data *d) -{ - struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); - int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; - u32 val, offset; - unsigned long flags; - - offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - - spin_lock_irqsave(&sgpio_lock, flags); - - val = readl(bank->chip.regs + offset); - - writel(val, bank->chip.regs + offset); - - spin_unlock_irqrestore(&sgpio_lock, flags); -} - -static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx) -{ - u32 val, offset; - unsigned long flags; - - offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - - spin_lock_irqsave(&sgpio_lock, flags); - - val = readl(bank->chip.regs + offset); - val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; - val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; - writel(val, bank->chip.regs + offset); - - spin_unlock_irqrestore(&sgpio_lock, flags); -} - -static void sirfsoc_gpio_irq_mask(struct irq_data *d) -{ - struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); - - __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); -} - -static void sirfsoc_gpio_irq_unmask(struct irq_data *d) -{ - struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); - int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; - u32 val, offset; - unsigned long flags; - - offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - - spin_lock_irqsave(&sgpio_lock, flags); - - val = readl(bank->chip.regs + offset); - val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; - val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK; - writel(val, bank->chip.regs + offset); - - spin_unlock_irqrestore(&sgpio_lock, flags); -} - -static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) -{ - struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); - int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; - u32 val, offset; - unsigned long flags; - - offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - - spin_lock_irqsave(&sgpio_lock, flags); - - val = readl(bank->chip.regs + offset); - val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; - - switch (type) { - case IRQ_TYPE_NONE: - break; - case IRQ_TYPE_EDGE_RISING: - val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; - val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK; - break; - case IRQ_TYPE_EDGE_FALLING: - val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; - val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; - break; - case IRQ_TYPE_EDGE_BOTH: - val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK | - SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; - break; - case IRQ_TYPE_LEVEL_LOW: - val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); - val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK; - break; - case IRQ_TYPE_LEVEL_HIGH: - val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; - val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); - break; - } - - writel(val, bank->chip.regs + offset); - - spin_unlock_irqrestore(&sgpio_lock, flags); - - return 0; -} - -static struct irq_chip sirfsoc_irq_chip = { - .name = "sirf-gpio-irq", - .irq_ack = sirfsoc_gpio_irq_ack, - .irq_mask = sirfsoc_gpio_irq_mask, - .irq_unmask = sirfsoc_gpio_irq_unmask, - .irq_set_type = sirfsoc_gpio_irq_type, -}; - -static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) -{ - struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq); - u32 status, ctrl; - int idx = 0; - struct irq_chip *chip = irq_get_chip(irq); - - chained_irq_enter(chip, desc); - - status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); - if (!status) { - printk(KERN_WARNING - "%s: gpio id %d status %#x no interrupt is flaged\n", - __func__, bank->id, status); - handle_bad_irq(irq, desc); - return; - } - - while (status) { - ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx)); - - /* - * Here we must check whether the corresponding GPIO's interrupt - * has been enabled, otherwise just skip it - */ - if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) { - pr_debug("%s: gpio id %d idx %d happens\n", - __func__, bank->id, idx); - generic_handle_irq(irq_find_mapping(bank->domain, idx)); - } - - idx++; - status = status >> 1; - } - - chained_irq_exit(chip, desc); -} - -static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset) -{ - u32 val; - - val = readl(bank->chip.regs + ctrl_offset); - val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK; - writel(val, bank->chip.regs + ctrl_offset); -} - -static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); - unsigned long flags; - - if (pinctrl_request_gpio(chip->base + offset)) - return -ENODEV; - - spin_lock_irqsave(&bank->lock, flags); - - /* - * default status: - * set direction as input and mask irq - */ - sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset)); - __sirfsoc_gpio_irq_mask(bank, offset); - - spin_unlock_irqrestore(&bank->lock, flags); - - return 0; -} - -static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset) -{ - struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); - unsigned long flags; - - spin_lock_irqsave(&bank->lock, flags); - - __sirfsoc_gpio_irq_mask(bank, offset); - sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset)); - - spin_unlock_irqrestore(&bank->lock, flags); - - pinctrl_free_gpio(chip->base + offset); -} - -static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) -{ - struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); - int idx = sirfsoc_gpio_to_offset(gpio); - unsigned long flags; - unsigned offset; - - offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - - spin_lock_irqsave(&bank->lock, flags); - - sirfsoc_gpio_set_input(bank, offset); - - spin_unlock_irqrestore(&bank->lock, flags); - - return 0; -} - -static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset, - int value) -{ - u32 out_ctrl; - unsigned long flags; - - spin_lock_irqsave(&bank->lock, flags); - - out_ctrl = readl(bank->chip.regs + offset); - if (value) - out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; - else - out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; - - out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; - out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK; - writel(out_ctrl, bank->chip.regs + offset); - - spin_unlock_irqrestore(&bank->lock, flags); -} - -static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) -{ - struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); - int idx = sirfsoc_gpio_to_offset(gpio); - u32 offset; - unsigned long flags; - - offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - - spin_lock_irqsave(&sgpio_lock, flags); - - sirfsoc_gpio_set_output(bank, offset, value); - - spin_unlock_irqrestore(&sgpio_lock, flags); - - return 0; -} - -static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset) -{ - struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); - u32 val; - unsigned long flags; - - spin_lock_irqsave(&bank->lock, flags); - - val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); - - spin_unlock_irqrestore(&bank->lock, flags); - - return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK); -} - -static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset, - int value) -{ - struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); - u32 ctrl; - unsigned long flags; - - spin_lock_irqsave(&bank->lock, flags); - - ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); - if (value) - ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; - else - ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; - writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); - - spin_unlock_irqrestore(&bank->lock, flags); -} - -static int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hwirq) -{ - struct sirfsoc_gpio_bank *bank = d->host_data; - - if (!bank) - return -EINVAL; - - irq_set_chip(irq, &sirfsoc_irq_chip); - irq_set_handler(irq, handle_level_irq); - irq_set_chip_data(irq, bank); - set_irq_flags(irq, IRQF_VALID); - - return 0; -} - -const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = { - .map = sirfsoc_gpio_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - -static void sirfsoc_gpio_set_pullup(const u32 *pullups) -{ - int i, n; - const unsigned long *p = (const unsigned long *)pullups; - - for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { - for_each_set_bit(n, p + i, BITS_PER_LONG) { - u32 offset = SIRFSOC_GPIO_CTRL(i, n); - u32 val = readl(sgpio_bank[i].chip.regs + offset); - val |= SIRFSOC_GPIO_CTL_PULL_MASK; - val |= SIRFSOC_GPIO_CTL_PULL_HIGH; - writel(val, sgpio_bank[i].chip.regs + offset); - } - } -} - -static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns) -{ - int i, n; - const unsigned long *p = (const unsigned long *)pulldowns; - - for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { - for_each_set_bit(n, p + i, BITS_PER_LONG) { - u32 offset = SIRFSOC_GPIO_CTRL(i, n); - u32 val = readl(sgpio_bank[i].chip.regs + offset); - val |= SIRFSOC_GPIO_CTL_PULL_MASK; - val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH; - writel(val, sgpio_bank[i].chip.regs + offset); - } - } -} - -static int sirfsoc_gpio_probe(struct device_node *np) -{ - int i, err = 0; - struct sirfsoc_gpio_bank *bank; - void *regs; - struct platform_device *pdev; - bool is_marco = false; - - u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS]; - - pdev = of_find_device_by_node(np); - if (!pdev) - return -ENODEV; - - regs = of_iomap(np, 0); - if (!regs) - return -ENOMEM; - - if (of_device_is_compatible(np, "sirf,marco-pinctrl")) - is_marco = 1; - - for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { - bank = &sgpio_bank[i]; - spin_lock_init(&bank->lock); - bank->chip.gc.request = sirfsoc_gpio_request; - bank->chip.gc.free = sirfsoc_gpio_free; - bank->chip.gc.direction_input = sirfsoc_gpio_direction_input; - bank->chip.gc.get = sirfsoc_gpio_get_value; - bank->chip.gc.direction_output = sirfsoc_gpio_direction_output; - bank->chip.gc.set = sirfsoc_gpio_set_value; - bank->chip.gc.to_irq = sirfsoc_gpio_to_irq; - bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE; - bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE; - bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL); - bank->chip.gc.of_node = np; - bank->chip.gc.of_xlate = sirfsoc_gpio_of_xlate; - bank->chip.gc.of_gpio_n_cells = 2; - bank->chip.regs = regs; - bank->id = i; - bank->is_marco = is_marco; - bank->parent_irq = platform_get_irq(pdev, i); - if (bank->parent_irq < 0) { - err = bank->parent_irq; - goto out; - } - - err = gpiochip_add(&bank->chip.gc); - if (err) { - pr_err("%s: error in probe function with status %d\n", - np->full_name, err); - goto out; - } - - bank->domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE, - &sirfsoc_gpio_irq_simple_ops, bank); - - if (!bank->domain) { - pr_err("%s: Failed to create irqdomain\n", np->full_name); - err = -ENOSYS; - goto out; - } - - irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq); - irq_set_handler_data(bank->parent_irq, bank); - } - - if (!of_property_read_u32_array(np, "sirf,pullups", pullups, - SIRFSOC_GPIO_NO_OF_BANKS)) - sirfsoc_gpio_set_pullup(pullups); - - if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns, - SIRFSOC_GPIO_NO_OF_BANKS)) - sirfsoc_gpio_set_pulldown(pulldowns); - - return 0; - -out: - iounmap(regs); - return err; -} - -static int __init sirfsoc_gpio_init(void) -{ - - struct device_node *np; - - np = of_find_matching_node(NULL, pinmux_ids); - - if (!np) - return -ENODEV; - - return sirfsoc_gpio_probe(np); -} -subsys_initcall(sirfsoc_gpio_init); - -MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, " - "Yuping Luo <yuping.luo@csr.com>, " - "Barry Song <baohua.song@csr.com>"); -MODULE_DESCRIPTION("SIRFSOC pin control driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c new file mode 100644 index 00000000000..0677e198db6 --- /dev/null +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -0,0 +1,929 @@ +/* + * pinmux driver for CSR SiRFprimaII + * + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/irq.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/err.h> +#include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/machine.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/bitops.h> +#include <linux/gpio.h> +#include <linux/of_gpio.h> +#include <asm/mach/irq.h> + +#include "pinctrl-sirf.h" + +#define DRIVER_NAME "pinmux-sirf" + +struct sirfsoc_gpio_bank { + struct of_mm_gpio_chip chip; + struct irq_domain *domain; + int id; + int parent_irq; + spinlock_t lock; + bool is_marco; /* for marco, some registers are different with prima2 */ +}; + +static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS]; +static DEFINE_SPINLOCK(sgpio_lock); + +static struct sirfsoc_pin_group *sirfsoc_pin_groups; +static int sirfsoc_pingrp_cnt; + +static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev) +{ + return sirfsoc_pingrp_cnt; +} + +static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return sirfsoc_pin_groups[selector].name; +} + +static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, + const unsigned **pins, + unsigned *num_pins) +{ + *pins = sirfsoc_pin_groups[selector].pins; + *num_pins = sirfsoc_pin_groups[selector].num_pins; + return 0; +} + +static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned offset) +{ + seq_printf(s, " " DRIVER_NAME); +} + +static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, unsigned *num_maps) +{ + struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev); + struct device_node *np; + struct property *prop; + const char *function, *group; + int ret, index = 0, count = 0; + + /* calculate number of maps required */ + for_each_child_of_node(np_config, np) { + ret = of_property_read_string(np, "sirf,function", &function); + if (ret < 0) + return ret; + + ret = of_property_count_strings(np, "sirf,pins"); + if (ret < 0) + return ret; + + count += ret; + } + + if (!count) { + dev_err(spmx->dev, "No child nodes passed via DT\n"); + return -ENODEV; + } + + *map = kzalloc(sizeof(**map) * count, GFP_KERNEL); + if (!*map) + return -ENOMEM; + + for_each_child_of_node(np_config, np) { + of_property_read_string(np, "sirf,function", &function); + of_property_for_each_string(np, "sirf,pins", prop, group) { + (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[index].data.mux.group = group; + (*map)[index].data.mux.function = function; + index++; + } + } + + *num_maps = count; + + return 0; +} + +static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ + kfree(map); +} + +static struct pinctrl_ops sirfsoc_pctrl_ops = { + .get_groups_count = sirfsoc_get_groups_count, + .get_group_name = sirfsoc_get_group_name, + .get_group_pins = sirfsoc_get_group_pins, + .pin_dbg_show = sirfsoc_pin_dbg_show, + .dt_node_to_map = sirfsoc_dt_node_to_map, + .dt_free_map = sirfsoc_dt_free_map, +}; + +static struct sirfsoc_pmx_func *sirfsoc_pmx_functions; +static int sirfsoc_pmxfunc_cnt; + +static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector, + bool enable) +{ + int i; + const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux; + const struct sirfsoc_muxmask *mask = mux->muxmask; + + for (i = 0; i < mux->muxmask_counts; i++) { + u32 muxval; + if (!spmx->is_marco) { + muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); + if (enable) + muxval = muxval & ~mask[i].mask; + else + muxval = muxval | mask[i].mask; + writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); + } else { + if (enable) + writel(mask[i].mask, spmx->gpio_virtbase + + SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group)); + else + writel(mask[i].mask, spmx->gpio_virtbase + + SIRFSOC_GPIO_PAD_EN(mask[i].group)); + } + } + + if (mux->funcmask && enable) { + u32 func_en_val; + func_en_val = + readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX); + func_en_val = + (func_en_val & ~mux->funcmask) | (mux-> + funcval); + writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX); + } +} + +static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector, + unsigned group) +{ + struct sirfsoc_pmx *spmx; + + spmx = pinctrl_dev_get_drvdata(pmxdev); + sirfsoc_pinmux_endisable(spmx, selector, true); + + return 0; +} + +static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector, + unsigned group) +{ + struct sirfsoc_pmx *spmx; + + spmx = pinctrl_dev_get_drvdata(pmxdev); + sirfsoc_pinmux_endisable(spmx, selector, false); +} + +static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev) +{ + return sirfsoc_pmxfunc_cnt; +} + +static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return sirfsoc_pmx_functions[selector].name; +} + +static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector, + const char * const **groups, + unsigned * const num_groups) +{ + *groups = sirfsoc_pmx_functions[selector].groups; + *num_groups = sirfsoc_pmx_functions[selector].num_groups; + return 0; +} + +static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, + struct pinctrl_gpio_range *range, unsigned offset) +{ + struct sirfsoc_pmx *spmx; + + int group = range->id; + + u32 muxval; + + spmx = pinctrl_dev_get_drvdata(pmxdev); + + if (!spmx->is_marco) { + muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); + muxval = muxval | (1 << (offset - range->pin_base)); + writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); + } else { + writel(1 << (offset - range->pin_base), spmx->gpio_virtbase + + SIRFSOC_GPIO_PAD_EN(group)); + } + + return 0; +} + +static struct pinmux_ops sirfsoc_pinmux_ops = { + .enable = sirfsoc_pinmux_enable, + .disable = sirfsoc_pinmux_disable, + .get_functions_count = sirfsoc_pinmux_get_funcs_count, + .get_function_name = sirfsoc_pinmux_get_func_name, + .get_function_groups = sirfsoc_pinmux_get_groups, + .gpio_request_enable = sirfsoc_pinmux_request_gpio, +}; + +static struct pinctrl_desc sirfsoc_pinmux_desc = { + .name = DRIVER_NAME, + .pctlops = &sirfsoc_pctrl_ops, + .pmxops = &sirfsoc_pinmux_ops, + .owner = THIS_MODULE, +}; + +/* + * Todo: bind irq_chip to every pinctrl_gpio_range + */ +static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = { + { + .name = "sirfsoc-gpio*", + .id = 0, + .base = 0, + .pin_base = 0, + .npins = 32, + }, { + .name = "sirfsoc-gpio*", + .id = 1, + .base = 32, + .pin_base = 32, + .npins = 32, + }, { + .name = "sirfsoc-gpio*", + .id = 2, + .base = 64, + .pin_base = 64, + .npins = 32, + }, { + .name = "sirfsoc-gpio*", + .id = 3, + .base = 96, + .pin_base = 96, + .npins = 19, + }, +}; + +static void __iomem *sirfsoc_rsc_of_iomap(void) +{ + const struct of_device_id rsc_ids[] = { + { .compatible = "sirf,prima2-rsc" }, + { .compatible = "sirf,marco-rsc" }, + {} + }; + struct device_node *np; + + np = of_find_matching_node(NULL, rsc_ids); + if (!np) + panic("unable to find compatible rsc node in dtb\n"); + + return of_iomap(np, 0); +} + +static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc, + const struct of_phandle_args *gpiospec, + u32 *flags) +{ + if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE) + return -EINVAL; + + if (gc != &sgpio_bank[gpiospec->args[0] / SIRFSOC_GPIO_BANK_SIZE].chip.gc) + return -EINVAL; + + if (flags) + *flags = gpiospec->args[1]; + + return gpiospec->args[0] % SIRFSOC_GPIO_BANK_SIZE; +} + +static const struct of_device_id pinmux_ids[] = { + { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, }, + { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, }, + { .compatible = "sirf,marco-pinctrl", .data = &prima2_pinctrl_data, }, + {} +}; + +static int sirfsoc_pinmux_probe(struct platform_device *pdev) +{ + int ret; + struct sirfsoc_pmx *spmx; + struct device_node *np = pdev->dev.of_node; + const struct sirfsoc_pinctrl_data *pdata; + int i; + + /* Create state holders etc for this driver */ + spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL); + if (!spmx) + return -ENOMEM; + + spmx->dev = &pdev->dev; + + platform_set_drvdata(pdev, spmx); + + spmx->gpio_virtbase = of_iomap(np, 0); + if (!spmx->gpio_virtbase) { + dev_err(&pdev->dev, "can't map gpio registers\n"); + return -ENOMEM; + } + + spmx->rsc_virtbase = sirfsoc_rsc_of_iomap(); + if (!spmx->rsc_virtbase) { + ret = -ENOMEM; + dev_err(&pdev->dev, "can't map rsc registers\n"); + goto out_no_rsc_remap; + } + + if (of_device_is_compatible(np, "sirf,marco-pinctrl")) + spmx->is_marco = 1; + + pdata = of_match_node(pinmux_ids, np)->data; + sirfsoc_pin_groups = pdata->grps; + sirfsoc_pingrp_cnt = pdata->grps_cnt; + sirfsoc_pmx_functions = pdata->funcs; + sirfsoc_pmxfunc_cnt = pdata->funcs_cnt; + sirfsoc_pinmux_desc.pins = pdata->pads; + sirfsoc_pinmux_desc.npins = pdata->pads_cnt; + + + /* Now register the pin controller and all pins it handles */ + spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx); + if (!spmx->pmx) { + dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n"); + ret = -EINVAL; + goto out_no_pmx; + } + + for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) { + sirfsoc_gpio_ranges[i].gc = &sgpio_bank[i].chip.gc; + pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]); + } + + dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n"); + + return 0; + +out_no_pmx: + iounmap(spmx->rsc_virtbase); +out_no_rsc_remap: + iounmap(spmx->gpio_virtbase); + return ret; +} + +#ifdef CONFIG_PM_SLEEP +static int sirfsoc_pinmux_suspend_noirq(struct device *dev) +{ + int i, j; + struct sirfsoc_pmx *spmx = dev_get_drvdata(dev); + + for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { + for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) { + spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase + + SIRFSOC_GPIO_CTRL(i, j)); + } + spmx->ints_regs[i] = readl(spmx->gpio_virtbase + + SIRFSOC_GPIO_INT_STATUS(i)); + spmx->paden_regs[i] = readl(spmx->gpio_virtbase + + SIRFSOC_GPIO_PAD_EN(i)); + } + spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0); + + for (i = 0; i < 3; i++) + spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i); + + return 0; +} + +static int sirfsoc_pinmux_resume_noirq(struct device *dev) +{ + int i, j; + struct sirfsoc_pmx *spmx = dev_get_drvdata(dev); + + for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { + for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) { + writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase + + SIRFSOC_GPIO_CTRL(i, j)); + } + writel(spmx->ints_regs[i], spmx->gpio_virtbase + + SIRFSOC_GPIO_INT_STATUS(i)); + writel(spmx->paden_regs[i], spmx->gpio_virtbase + + SIRFSOC_GPIO_PAD_EN(i)); + } + writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0); + + for (i = 0; i < 3; i++) + writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i); + + return 0; +} + +static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = { + .suspend_noirq = sirfsoc_pinmux_suspend_noirq, + .resume_noirq = sirfsoc_pinmux_resume_noirq, +}; +#endif + +static struct platform_driver sirfsoc_pinmux_driver = { + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = pinmux_ids, +#ifdef CONFIG_PM_SLEEP + .pm = &sirfsoc_pinmux_pm_ops, +#endif + }, + .probe = sirfsoc_pinmux_probe, +}; + +static int __init sirfsoc_pinmux_init(void) +{ + return platform_driver_register(&sirfsoc_pinmux_driver); +} +arch_initcall(sirfsoc_pinmux_init); + +static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip), + struct sirfsoc_gpio_bank, chip); + + return irq_create_mapping(bank->domain, offset); +} + +static inline int sirfsoc_gpio_to_offset(unsigned int gpio) +{ + return gpio % SIRFSOC_GPIO_BANK_SIZE; +} + +static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio) +{ + return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE]; +} + +static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip) +{ + return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip); +} + +static void sirfsoc_gpio_irq_ack(struct irq_data *d) +{ + struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); + int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; + u32 val, offset; + unsigned long flags; + + offset = SIRFSOC_GPIO_CTRL(bank->id, idx); + + spin_lock_irqsave(&sgpio_lock, flags); + + val = readl(bank->chip.regs + offset); + + writel(val, bank->chip.regs + offset); + + spin_unlock_irqrestore(&sgpio_lock, flags); +} + +static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx) +{ + u32 val, offset; + unsigned long flags; + + offset = SIRFSOC_GPIO_CTRL(bank->id, idx); + + spin_lock_irqsave(&sgpio_lock, flags); + + val = readl(bank->chip.regs + offset); + val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; + val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; + writel(val, bank->chip.regs + offset); + + spin_unlock_irqrestore(&sgpio_lock, flags); +} + +static void sirfsoc_gpio_irq_mask(struct irq_data *d) +{ + struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); + + __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); +} + +static void sirfsoc_gpio_irq_unmask(struct irq_data *d) +{ + struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); + int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; + u32 val, offset; + unsigned long flags; + + offset = SIRFSOC_GPIO_CTRL(bank->id, idx); + + spin_lock_irqsave(&sgpio_lock, flags); + + val = readl(bank->chip.regs + offset); + val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; + val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK; + writel(val, bank->chip.regs + offset); + + spin_unlock_irqrestore(&sgpio_lock, flags); +} + +static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) +{ + struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); + int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; + u32 val, offset; + unsigned long flags; + + offset = SIRFSOC_GPIO_CTRL(bank->id, idx); + + spin_lock_irqsave(&sgpio_lock, flags); + + val = readl(bank->chip.regs + offset); + val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; + + switch (type) { + case IRQ_TYPE_NONE: + break; + case IRQ_TYPE_EDGE_RISING: + val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; + val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK; + break; + case IRQ_TYPE_EDGE_FALLING: + val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; + val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; + break; + case IRQ_TYPE_EDGE_BOTH: + val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK | + SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; + break; + case IRQ_TYPE_LEVEL_LOW: + val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); + val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK; + break; + case IRQ_TYPE_LEVEL_HIGH: + val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; + val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); + break; + } + + writel(val, bank->chip.regs + offset); + + spin_unlock_irqrestore(&sgpio_lock, flags); + + return 0; +} + +static struct irq_chip sirfsoc_irq_chip = { + .name = "sirf-gpio-irq", + .irq_ack = sirfsoc_gpio_irq_ack, + .irq_mask = sirfsoc_gpio_irq_mask, + .irq_unmask = sirfsoc_gpio_irq_unmask, + .irq_set_type = sirfsoc_gpio_irq_type, +}; + +static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) +{ + struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq); + u32 status, ctrl; + int idx = 0; + struct irq_chip *chip = irq_get_chip(irq); + + chained_irq_enter(chip, desc); + + status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); + if (!status) { + printk(KERN_WARNING + "%s: gpio id %d status %#x no interrupt is flaged\n", + __func__, bank->id, status); + handle_bad_irq(irq, desc); + return; + } + + while (status) { + ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx)); + + /* + * Here we must check whether the corresponding GPIO's interrupt + * has been enabled, otherwise just skip it + */ + if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) { + pr_debug("%s: gpio id %d idx %d happens\n", + __func__, bank->id, idx); + generic_handle_irq(irq_find_mapping(bank->domain, idx)); + } + + idx++; + status = status >> 1; + } + + chained_irq_exit(chip, desc); +} + +static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset) +{ + u32 val; + + val = readl(bank->chip.regs + ctrl_offset); + val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK; + writel(val, bank->chip.regs + ctrl_offset); +} + +static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); + unsigned long flags; + + if (pinctrl_request_gpio(chip->base + offset)) + return -ENODEV; + + spin_lock_irqsave(&bank->lock, flags); + + /* + * default status: + * set direction as input and mask irq + */ + sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset)); + __sirfsoc_gpio_irq_mask(bank, offset); + + spin_unlock_irqrestore(&bank->lock, flags); + + return 0; +} + +static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); + unsigned long flags; + + spin_lock_irqsave(&bank->lock, flags); + + __sirfsoc_gpio_irq_mask(bank, offset); + sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset)); + + spin_unlock_irqrestore(&bank->lock, flags); + + pinctrl_free_gpio(chip->base + offset); +} + +static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) +{ + struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); + int idx = sirfsoc_gpio_to_offset(gpio); + unsigned long flags; + unsigned offset; + + offset = SIRFSOC_GPIO_CTRL(bank->id, idx); + + spin_lock_irqsave(&bank->lock, flags); + + sirfsoc_gpio_set_input(bank, offset); + + spin_unlock_irqrestore(&bank->lock, flags); + + return 0; +} + +static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset, + int value) +{ + u32 out_ctrl; + unsigned long flags; + + spin_lock_irqsave(&bank->lock, flags); + + out_ctrl = readl(bank->chip.regs + offset); + if (value) + out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; + else + out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; + + out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; + out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK; + writel(out_ctrl, bank->chip.regs + offset); + + spin_unlock_irqrestore(&bank->lock, flags); +} + +static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) +{ + struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); + int idx = sirfsoc_gpio_to_offset(gpio); + u32 offset; + unsigned long flags; + + offset = SIRFSOC_GPIO_CTRL(bank->id, idx); + + spin_lock_irqsave(&sgpio_lock, flags); + + sirfsoc_gpio_set_output(bank, offset, value); + + spin_unlock_irqrestore(&sgpio_lock, flags); + + return 0; +} + +static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset) +{ + struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); + u32 val; + unsigned long flags; + + spin_lock_irqsave(&bank->lock, flags); + + val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); + + spin_unlock_irqrestore(&bank->lock, flags); + + return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK); +} + +static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset, + int value) +{ + struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); + u32 ctrl; + unsigned long flags; + + spin_lock_irqsave(&bank->lock, flags); + + ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); + if (value) + ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; + else + ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; + writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); + + spin_unlock_irqrestore(&bank->lock, flags); +} + +static int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct sirfsoc_gpio_bank *bank = d->host_data; + + if (!bank) + return -EINVAL; + + irq_set_chip(irq, &sirfsoc_irq_chip); + irq_set_handler(irq, handle_level_irq); + irq_set_chip_data(irq, bank); + set_irq_flags(irq, IRQF_VALID); + + return 0; +} + +static const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = { + .map = sirfsoc_gpio_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +static void sirfsoc_gpio_set_pullup(const u32 *pullups) +{ + int i, n; + const unsigned long *p = (const unsigned long *)pullups; + + for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { + for_each_set_bit(n, p + i, BITS_PER_LONG) { + u32 offset = SIRFSOC_GPIO_CTRL(i, n); + u32 val = readl(sgpio_bank[i].chip.regs + offset); + val |= SIRFSOC_GPIO_CTL_PULL_MASK; + val |= SIRFSOC_GPIO_CTL_PULL_HIGH; + writel(val, sgpio_bank[i].chip.regs + offset); + } + } +} + +static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns) +{ + int i, n; + const unsigned long *p = (const unsigned long *)pulldowns; + + for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { + for_each_set_bit(n, p + i, BITS_PER_LONG) { + u32 offset = SIRFSOC_GPIO_CTRL(i, n); + u32 val = readl(sgpio_bank[i].chip.regs + offset); + val |= SIRFSOC_GPIO_CTL_PULL_MASK; + val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH; + writel(val, sgpio_bank[i].chip.regs + offset); + } + } +} + +static int sirfsoc_gpio_probe(struct device_node *np) +{ + int i, err = 0; + struct sirfsoc_gpio_bank *bank; + void *regs; + struct platform_device *pdev; + bool is_marco = false; + + u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS]; + + pdev = of_find_device_by_node(np); + if (!pdev) + return -ENODEV; + + regs = of_iomap(np, 0); + if (!regs) + return -ENOMEM; + + if (of_device_is_compatible(np, "sirf,marco-pinctrl")) + is_marco = 1; + + for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { + bank = &sgpio_bank[i]; + spin_lock_init(&bank->lock); + bank->chip.gc.request = sirfsoc_gpio_request; + bank->chip.gc.free = sirfsoc_gpio_free; + bank->chip.gc.direction_input = sirfsoc_gpio_direction_input; + bank->chip.gc.get = sirfsoc_gpio_get_value; + bank->chip.gc.direction_output = sirfsoc_gpio_direction_output; + bank->chip.gc.set = sirfsoc_gpio_set_value; + bank->chip.gc.to_irq = sirfsoc_gpio_to_irq; + bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE; + bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE; + bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL); + bank->chip.gc.of_node = np; + bank->chip.gc.of_xlate = sirfsoc_gpio_of_xlate; + bank->chip.gc.of_gpio_n_cells = 2; + bank->chip.regs = regs; + bank->id = i; + bank->is_marco = is_marco; + bank->parent_irq = platform_get_irq(pdev, i); + if (bank->parent_irq < 0) { + err = bank->parent_irq; + goto out; + } + + err = gpiochip_add(&bank->chip.gc); + if (err) { + pr_err("%s: error in probe function with status %d\n", + np->full_name, err); + goto out; + } + + bank->domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE, + &sirfsoc_gpio_irq_simple_ops, bank); + + if (!bank->domain) { + pr_err("%s: Failed to create irqdomain\n", np->full_name); + err = -ENOSYS; + goto out; + } + + irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq); + irq_set_handler_data(bank->parent_irq, bank); + } + + if (!of_property_read_u32_array(np, "sirf,pullups", pullups, + SIRFSOC_GPIO_NO_OF_BANKS)) + sirfsoc_gpio_set_pullup(pullups); + + if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns, + SIRFSOC_GPIO_NO_OF_BANKS)) + sirfsoc_gpio_set_pulldown(pulldowns); + + return 0; + +out: + iounmap(regs); + return err; +} + +static int __init sirfsoc_gpio_init(void) +{ + + struct device_node *np; + + np = of_find_matching_node(NULL, pinmux_ids); + + if (!np) + return -ENODEV; + + return sirfsoc_gpio_probe(np); +} +subsys_initcall(sirfsoc_gpio_init); + +MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, " + "Yuping Luo <yuping.luo@csr.com>, " + "Barry Song <baohua.song@csr.com>"); +MODULE_DESCRIPTION("SIRFSOC pin control driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.h b/drivers/pinctrl/sirf/pinctrl-sirf.h new file mode 100644 index 00000000000..17cc108510b --- /dev/null +++ b/drivers/pinctrl/sirf/pinctrl-sirf.h @@ -0,0 +1,116 @@ +/* + * pinmux driver shared headfile for CSR SiRFsoc + * + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +#ifndef __PINMUX_SIRF_H__ +#define __PINMUX_SIRF_H__ + +#define SIRFSOC_NUM_PADS 622 +#define SIRFSOC_RSC_PIN_MUX 0x4 + +#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84) +#define SIRFSOC_GPIO_PAD_EN_CLR(g) ((g)*0x100 + 0x90) +#define SIRFSOC_GPIO_CTRL(g, i) ((g)*0x100 + (i)*4) +#define SIRFSOC_GPIO_DSP_EN0 (0x80) +#define SIRFSOC_GPIO_INT_STATUS(g) ((g)*0x100 + 0x8C) + +#define SIRFSOC_GPIO_CTL_INTR_LOW_MASK 0x1 +#define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK 0x2 +#define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK 0x4 +#define SIRFSOC_GPIO_CTL_INTR_EN_MASK 0x8 +#define SIRFSOC_GPIO_CTL_INTR_STS_MASK 0x10 +#define SIRFSOC_GPIO_CTL_OUT_EN_MASK 0x20 +#define SIRFSOC_GPIO_CTL_DATAOUT_MASK 0x40 +#define SIRFSOC_GPIO_CTL_DATAIN_MASK 0x80 +#define SIRFSOC_GPIO_CTL_PULL_MASK 0x100 +#define SIRFSOC_GPIO_CTL_PULL_HIGH 0x200 +#define SIRFSOC_GPIO_CTL_DSP_INT 0x400 + +#define SIRFSOC_GPIO_NO_OF_BANKS 5 +#define SIRFSOC_GPIO_BANK_SIZE 32 +#define SIRFSOC_GPIO_NUM(bank, index) (((bank)*(32)) + (index)) + +/** + * @dev: a pointer back to containing device + * @virtbase: the offset to the controller in virtual memory + */ +struct sirfsoc_pmx { + struct device *dev; + struct pinctrl_dev *pmx; + void __iomem *gpio_virtbase; + void __iomem *rsc_virtbase; + u32 gpio_regs[SIRFSOC_GPIO_NO_OF_BANKS][SIRFSOC_GPIO_BANK_SIZE]; + u32 ints_regs[SIRFSOC_GPIO_NO_OF_BANKS]; + u32 paden_regs[SIRFSOC_GPIO_NO_OF_BANKS]; + u32 dspen_regs; + u32 rsc_regs[3]; + bool is_marco; +}; + +/* SIRFSOC_GPIO_PAD_EN set */ +struct sirfsoc_muxmask { + unsigned long group; + unsigned long mask; +}; + +struct sirfsoc_padmux { + unsigned long muxmask_counts; + const struct sirfsoc_muxmask *muxmask; + /* RSC_PIN_MUX set */ + unsigned long funcmask; + unsigned long funcval; +}; + + /** + * struct sirfsoc_pin_group - describes a SiRFprimaII pin group + * @name: the name of this specific pin group + * @pins: an array of discrete physical pins used in this group, taken + * from the driver-local pin enumeration space + * @num_pins: the number of pins in this group array, i.e. the number of + * elements in .pins so we can iterate over that array + */ +struct sirfsoc_pin_group { + const char *name; + const unsigned int *pins; + const unsigned num_pins; +}; + +#define SIRFSOC_PIN_GROUP(n, p) \ + { \ + .name = n, \ + .pins = p, \ + .num_pins = ARRAY_SIZE(p), \ + } + +struct sirfsoc_pmx_func { + const char *name; + const char * const *groups; + const unsigned num_groups; + const struct sirfsoc_padmux *padmux; +}; + +#define SIRFSOC_PMX_FUNCTION(n, g, m) \ + { \ + .name = n, \ + .groups = g, \ + .num_groups = ARRAY_SIZE(g), \ + .padmux = &m, \ + } + +struct sirfsoc_pinctrl_data { + struct pinctrl_pin_desc *pads; + int pads_cnt; + struct sirfsoc_pin_group *grps; + int grps_cnt; + struct sirfsoc_pmx_func *funcs; + int funcs_cnt; +}; + +extern struct sirfsoc_pinctrl_data prima2_pinctrl_data; +extern struct sirfsoc_pinctrl_data atlas6_pinctrl_data; + +#endif diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c index 3e5a887216b..0a7f0bdbaa7 100644 --- a/drivers/pinctrl/spear/pinctrl-plgpio.c +++ b/drivers/pinctrl/spear/pinctrl-plgpio.c @@ -441,7 +441,7 @@ static int spear310_p2o(int pin) return offset; } -int spear310_o2p(int offset) +static int spear310_o2p(int offset) { if (offset <= 3) return 101 - offset; @@ -528,18 +528,13 @@ static int plgpio_probe(struct platform_device *pdev) struct resource *res; int ret, irq, i; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "invalid IORESOURCE_MEM\n"); - return -EBUSY; - } - plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL); if (!plgpio) { dev_err(&pdev->dev, "memory allocation fail\n"); return -ENOMEM; } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); plgpio->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(plgpio->base)) return PTR_ERR(plgpio->base); diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c index 70d986e04af..0cc4335bc0f 100644 --- a/drivers/pinctrl/vt8500/pinctrl-wmt.c +++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c @@ -569,11 +569,9 @@ int wmt_pinctrl_probe(struct platform_device *pdev, struct resource *res; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - data->base = devm_request_and_ioremap(&pdev->dev, res); - if (!data->base) { - dev_err(&pdev->dev, "failed to map memory resource\n"); - return -EBUSY; - } + data->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->base)) + return PTR_ERR(data->base); wmt_desc.pins = data->pins; wmt_desc.npins = data->npins; |