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-rw-r--r--drivers/serial/8250.c137
-rw-r--r--drivers/serial/8250_pci.c36
-rw-r--r--drivers/serial/Kconfig27
-rw-r--r--drivers/serial/Makefile5
-rw-r--r--drivers/serial/amba-pl011.c592
-rw-r--r--drivers/serial/apbuart.c61
-rw-r--r--drivers/serial/cpm_uart/cpm_uart.h6
-rw-r--r--drivers/serial/cpm_uart/cpm_uart_core.c19
-rw-r--r--drivers/serial/crisv10.c1
-rw-r--r--drivers/serial/ifx6x60.c1406
-rw-r--r--drivers/serial/ifx6x60.h129
-rw-r--r--drivers/serial/kgdboc.c3
-rw-r--r--drivers/serial/mfd.c24
-rw-r--r--drivers/serial/mpc52xx_uart.c6
-rw-r--r--drivers/serial/msm_serial.c2
-rw-r--r--drivers/serial/of_serial.c1
-rw-r--r--drivers/serial/omap-serial.c78
-rw-r--r--drivers/serial/pch_uart.c1451
-rw-r--r--drivers/serial/serial_core.c11
-rw-r--r--drivers/serial/sh-sci.h7
-rw-r--r--drivers/serial/vt8500_serial.c648
21 files changed, 4487 insertions, 163 deletions
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index 4d8e14b7aa9..b25e6e49053 100644
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -454,21 +454,40 @@ static void tsi_serial_out(struct uart_port *p, int offset, int value)
writeb(value, p->membase + offset);
}
+/* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */
+static inline void dwapb_save_out_value(struct uart_port *p, int offset,
+ int value)
+{
+ struct uart_8250_port *up =
+ container_of(p, struct uart_8250_port, port);
+
+ if (offset == UART_LCR)
+ up->lcr = value;
+}
+
+/* Read the IER to ensure any interrupt is cleared before returning from ISR. */
+static inline void dwapb_check_clear_ier(struct uart_port *p, int offset)
+{
+ if (offset == UART_TX || offset == UART_IER)
+ p->serial_in(p, UART_IER);
+}
+
static void dwapb_serial_out(struct uart_port *p, int offset, int value)
{
int save_offset = offset;
offset = map_8250_out_reg(p, offset) << p->regshift;
- /* Save the LCR value so it can be re-written when a
- * Busy Detect interrupt occurs. */
- if (save_offset == UART_LCR) {
- struct uart_8250_port *up = (struct uart_8250_port *)p;
- up->lcr = value;
- }
+ dwapb_save_out_value(p, save_offset, value);
writeb(value, p->membase + offset);
- /* Read the IER to ensure any interrupt is cleared before
- * returning from ISR. */
- if (save_offset == UART_TX || save_offset == UART_IER)
- value = p->serial_in(p, UART_IER);
+ dwapb_check_clear_ier(p, save_offset);
+}
+
+static void dwapb32_serial_out(struct uart_port *p, int offset, int value)
+{
+ int save_offset = offset;
+ offset = map_8250_out_reg(p, offset) << p->regshift;
+ dwapb_save_out_value(p, save_offset, value);
+ writel(value, p->membase + offset);
+ dwapb_check_clear_ier(p, save_offset);
}
static unsigned int io_serial_in(struct uart_port *p, int offset)
@@ -485,7 +504,8 @@ static void io_serial_out(struct uart_port *p, int offset, int value)
static void set_io_from_upio(struct uart_port *p)
{
- struct uart_8250_port *up = (struct uart_8250_port *)p;
+ struct uart_8250_port *up =
+ container_of(p, struct uart_8250_port, port);
switch (p->iotype) {
case UPIO_HUB6:
p->serial_in = hub6_serial_in;
@@ -518,6 +538,11 @@ static void set_io_from_upio(struct uart_port *p)
p->serial_out = dwapb_serial_out;
break;
+ case UPIO_DWAPB32:
+ p->serial_in = mem32_serial_in;
+ p->serial_out = dwapb32_serial_out;
+ break;
+
default:
p->serial_in = io_serial_in;
p->serial_out = io_serial_out;
@@ -536,6 +561,7 @@ serial_out_sync(struct uart_8250_port *up, int offset, int value)
case UPIO_MEM32:
case UPIO_AU:
case UPIO_DWAPB:
+ case UPIO_DWAPB32:
p->serial_out(p, offset, value);
p->serial_in(p, UART_LCR); /* safe, no side-effects */
break;
@@ -653,13 +679,13 @@ static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
{
if (p->capabilities & UART_CAP_SLEEP) {
if (p->capabilities & UART_CAP_EFR) {
- serial_outp(p, UART_LCR, 0xBF);
+ serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
serial_outp(p, UART_EFR, UART_EFR_ECB);
serial_outp(p, UART_LCR, 0);
}
serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
if (p->capabilities & UART_CAP_EFR) {
- serial_outp(p, UART_LCR, 0xBF);
+ serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
serial_outp(p, UART_EFR, 0);
serial_outp(p, UART_LCR, 0);
}
@@ -752,7 +778,7 @@ static int size_fifo(struct uart_8250_port *up)
serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
serial_outp(up, UART_MCR, UART_MCR_LOOP);
- serial_outp(up, UART_LCR, UART_LCR_DLAB);
+ serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
old_dl = serial_dl_read(up);
serial_dl_write(up, 0x0001);
serial_outp(up, UART_LCR, 0x03);
@@ -764,7 +790,7 @@ static int size_fifo(struct uart_8250_port *up)
serial_inp(up, UART_RX);
serial_outp(up, UART_FCR, old_fcr);
serial_outp(up, UART_MCR, old_mcr);
- serial_outp(up, UART_LCR, UART_LCR_DLAB);
+ serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial_dl_write(up, old_dl);
serial_outp(up, UART_LCR, old_lcr);
@@ -782,7 +808,7 @@ static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
unsigned int id;
old_lcr = serial_inp(p, UART_LCR);
- serial_outp(p, UART_LCR, UART_LCR_DLAB);
+ serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
old_dll = serial_inp(p, UART_DLL);
old_dlm = serial_inp(p, UART_DLM);
@@ -836,7 +862,7 @@ static void autoconfig_has_efr(struct uart_8250_port *up)
* recommended for new designs).
*/
up->acr = 0;
- serial_out(up, UART_LCR, 0xBF);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_EFR, UART_EFR_ECB);
serial_out(up, UART_LCR, 0x00);
id1 = serial_icr_read(up, UART_ID1);
@@ -945,7 +971,7 @@ static void autoconfig_16550a(struct uart_8250_port *up)
* Check for presence of the EFR when DLAB is set.
* Only ST16C650V1 UARTs pass this test.
*/
- serial_outp(up, UART_LCR, UART_LCR_DLAB);
+ serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
if (serial_in(up, UART_EFR) == 0) {
serial_outp(up, UART_EFR, 0xA8);
if (serial_in(up, UART_EFR) != 0) {
@@ -963,7 +989,7 @@ static void autoconfig_16550a(struct uart_8250_port *up)
* Maybe it requires 0xbf to be written to the LCR.
* (other ST16C650V2 UARTs, TI16C752A, etc)
*/
- serial_outp(up, UART_LCR, 0xBF);
+ serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
DEBUG_AUTOCONF("EFRv2 ");
autoconfig_has_efr(up);
@@ -1024,7 +1050,7 @@ static void autoconfig_16550a(struct uart_8250_port *up)
serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
status1 = serial_in(up, UART_IIR) >> 5;
serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
- serial_outp(up, UART_LCR, UART_LCR_DLAB);
+ serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
status2 = serial_in(up, UART_IIR) >> 5;
serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
@@ -1183,7 +1209,7 @@ static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
* We also initialise the EFR (if any) to zero for later. The
* EFR occupies the same register location as the FCR and IIR.
*/
- serial_outp(up, UART_LCR, 0xBF);
+ serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_outp(up, UART_EFR, 0);
serial_outp(up, UART_LCR, 0);
@@ -1319,7 +1345,8 @@ static inline void __stop_tx(struct uart_8250_port *p)
static void serial8250_stop_tx(struct uart_port *port)
{
- struct uart_8250_port *up = (struct uart_8250_port *)port;
+ struct uart_8250_port *up =
+ container_of(port, struct uart_8250_port, port);
__stop_tx(up);
@@ -1336,7 +1363,8 @@ static void transmit_chars(struct uart_8250_port *up);
static void serial8250_start_tx(struct uart_port *port)
{
- struct uart_8250_port *up = (struct uart_8250_port *)port;
+ struct uart_8250_port *up =
+ container_of(port, struct uart_8250_port, port);
if (!(up->ier & UART_IER_THRI)) {
up->ier |= UART_IER_THRI;
@@ -1364,7 +1392,8 @@ static void serial8250_start_tx(struct uart_port *port)
static void serial8250_stop_rx(struct uart_port *port)
{
- struct uart_8250_port *up = (struct uart_8250_port *)port;
+ struct uart_8250_port *up =
+ container_of(port, struct uart_8250_port, port);
up->ier &= ~UART_IER_RLSI;
up->port.read_status_mask &= ~UART_LSR_DR;
@@ -1373,7 +1402,8 @@ static void serial8250_stop_rx(struct uart_port *port)
static void serial8250_enable_ms(struct uart_port *port)
{
- struct uart_8250_port *up = (struct uart_8250_port *)port;
+ struct uart_8250_port *up =
+ container_of(port, struct uart_8250_port, port);
/* no MSR capabilities */
if (up->bugs & UART_BUG_NOMSR)
@@ -1581,7 +1611,8 @@ static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
handled = 1;
end = NULL;
- } else if (up->port.iotype == UPIO_DWAPB &&
+ } else if ((up->port.iotype == UPIO_DWAPB ||
+ up->port.iotype == UPIO_DWAPB32) &&
(iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
/* The DesignWare APB UART has an Busy Detect (0x07)
* interrupt meaning an LCR write attempt occured while the
@@ -1781,7 +1812,8 @@ static void serial8250_backup_timeout(unsigned long data)
static unsigned int serial8250_tx_empty(struct uart_port *port)
{
- struct uart_8250_port *up = (struct uart_8250_port *)port;
+ struct uart_8250_port *up =
+ container_of(port, struct uart_8250_port, port);
unsigned long flags;
unsigned int lsr;
@@ -1795,7 +1827,8 @@ static unsigned int serial8250_tx_empty(struct uart_port *port)
static unsigned int serial8250_get_mctrl(struct uart_port *port)
{
- struct uart_8250_port *up = (struct uart_8250_port *)port;
+ struct uart_8250_port *up =
+ container_of(port, struct uart_8250_port, port);
unsigned int status;
unsigned int ret;
@@ -1815,7 +1848,8 @@ static unsigned int serial8250_get_mctrl(struct uart_port *port)
static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
- struct uart_8250_port *up = (struct uart_8250_port *)port;
+ struct uart_8250_port *up =
+ container_of(port, struct uart_8250_port, port);
unsigned char mcr = 0;
if (mctrl & TIOCM_RTS)
@@ -1836,7 +1870,8 @@ static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
static void serial8250_break_ctl(struct uart_port *port, int break_state)
{
- struct uart_8250_port *up = (struct uart_8250_port *)port;
+ struct uart_8250_port *up =
+ container_of(port, struct uart_8250_port, port);
unsigned long flags;
spin_lock_irqsave(&up->port.lock, flags);
@@ -1890,7 +1925,8 @@ static void wait_for_xmitr(struct uart_8250_port *up, int bits)
static int serial8250_get_poll_char(struct uart_port *port)
{
- struct uart_8250_port *up = (struct uart_8250_port *)port;
+ struct uart_8250_port *up =
+ container_of(port, struct uart_8250_port, port);
unsigned char lsr = serial_inp(up, UART_LSR);
if (!(lsr & UART_LSR_DR))
@@ -1904,7 +1940,8 @@ static void serial8250_put_poll_char(struct uart_port *port,
unsigned char c)
{
unsigned int ier;
- struct uart_8250_port *up = (struct uart_8250_port *)port;
+ struct uart_8250_port *up =
+ container_of(port, struct uart_8250_port, port);
/*
* First save the IER then disable the interrupts
@@ -1938,11 +1975,14 @@ static void serial8250_put_poll_char(struct uart_port *port,
static int serial8250_startup(struct uart_port *port)
{
- struct uart_8250_port *up = (struct uart_8250_port *)port;
+ struct uart_8250_port *up =
+ container_of(port, struct uart_8250_port, port);
unsigned long flags;
unsigned char lsr, iir;
int retval;
+ up->port.fifosize = uart_config[up->port.type].fifo_size;
+ up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
up->capabilities = uart_config[up->port.type].flags;
up->mcr = 0;
@@ -1952,7 +1992,7 @@ static int serial8250_startup(struct uart_port *port)
if (up->port.type == PORT_16C950) {
/* Wake up and initialize UART */
up->acr = 0;
- serial_outp(up, UART_LCR, 0xBF);
+ serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_outp(up, UART_EFR, UART_EFR_ECB);
serial_outp(up, UART_IER, 0);
serial_outp(up, UART_LCR, 0);
@@ -2002,7 +2042,7 @@ static int serial8250_startup(struct uart_port *port)
if (up->port.type == PORT_16850) {
unsigned char fctr;
- serial_outp(up, UART_LCR, 0xbf);
+ serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
@@ -2166,7 +2206,8 @@ dont_test_tx_en:
static void serial8250_shutdown(struct uart_port *port)
{
- struct uart_8250_port *up = (struct uart_8250_port *)port;
+ struct uart_8250_port *up =
+ container_of(port, struct uart_8250_port, port);
unsigned long flags;
/*
@@ -2235,7 +2276,8 @@ void
serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
struct ktermios *old)
{
- struct uart_8250_port *up = (struct uart_8250_port *)port;
+ struct uart_8250_port *up =
+ container_of(port, struct uart_8250_port, port);
unsigned char cval, fcr = 0;
unsigned long flags;
unsigned int baud, quot;
@@ -2363,7 +2405,7 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
if (termios->c_cflag & CRTSCTS)
efr |= UART_EFR_CTS;
- serial_outp(up, UART_LCR, 0xBF);
+ serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_outp(up, UART_EFR, efr);
}
@@ -2435,7 +2477,8 @@ serial8250_set_ldisc(struct uart_port *port, int new)
void serial8250_do_pm(struct uart_port *port, unsigned int state,
unsigned int oldstate)
{
- struct uart_8250_port *p = (struct uart_8250_port *)port;
+ struct uart_8250_port *p =
+ container_of(port, struct uart_8250_port, port);
serial8250_set_sleep(p, state != 0);
}
@@ -2476,6 +2519,7 @@ static int serial8250_request_std_resource(struct uart_8250_port *up)
case UPIO_MEM32:
case UPIO_MEM:
case UPIO_DWAPB:
+ case UPIO_DWAPB32:
if (!up->port.mapbase)
break;
@@ -2513,6 +2557,7 @@ static void serial8250_release_std_resource(struct uart_8250_port *up)
case UPIO_MEM32:
case UPIO_MEM:
case UPIO_DWAPB:
+ case UPIO_DWAPB32:
if (!up->port.mapbase)
break;
@@ -2566,7 +2611,8 @@ static void serial8250_release_rsa_resource(struct uart_8250_port *up)
static void serial8250_release_port(struct uart_port *port)
{
- struct uart_8250_port *up = (struct uart_8250_port *)port;
+ struct uart_8250_port *up =
+ container_of(port, struct uart_8250_port, port);
serial8250_release_std_resource(up);
if (up->port.type == PORT_RSA)
@@ -2575,7 +2621,8 @@ static void serial8250_release_port(struct uart_port *port)
static int serial8250_request_port(struct uart_port *port)
{
- struct uart_8250_port *up = (struct uart_8250_port *)port;
+ struct uart_8250_port *up =
+ container_of(port, struct uart_8250_port, port);
int ret = 0;
ret = serial8250_request_std_resource(up);
@@ -2590,7 +2637,8 @@ static int serial8250_request_port(struct uart_port *port)
static void serial8250_config_port(struct uart_port *port, int flags)
{
- struct uart_8250_port *up = (struct uart_8250_port *)port;
+ struct uart_8250_port *up =
+ container_of(port, struct uart_8250_port, port);
int probeflags = PROBE_ANY;
int ret;
@@ -2771,7 +2819,8 @@ serial8250_register_ports(struct uart_driver *drv, struct device *dev)
static void serial8250_console_putchar(struct uart_port *port, int ch)
{
- struct uart_8250_port *up = (struct uart_8250_port *)port;
+ struct uart_8250_port *up =
+ container_of(port, struct uart_8250_port, port);
wait_for_xmitr(up, UART_LSR_THRE);
serial_out(up, UART_TX, ch);
@@ -2872,7 +2921,7 @@ static struct console serial8250_console = {
.device = uart_console_device,
.setup = serial8250_console_setup,
.early_setup = serial8250_console_early_setup,
- .flags = CON_PRINTBUFFER,
+ .flags = CON_PRINTBUFFER | CON_ANYTIME,
.index = -1,
.data = &serial8250_reg,
};
diff --git a/drivers/serial/8250_pci.c b/drivers/serial/8250_pci.c
index 842e3b2a02b..8b8930f700b 100644
--- a/drivers/serial/8250_pci.c
+++ b/drivers/serial/8250_pci.c
@@ -957,6 +957,22 @@ pci_default_setup(struct serial_private *priv,
return setup_port(priv, port, bar, offset, board->reg_shift);
}
+static int
+ce4100_serial_setup(struct serial_private *priv,
+ const struct pciserial_board *board,
+ struct uart_port *port, int idx)
+{
+ int ret;
+
+ ret = setup_port(priv, port, 0, 0, board->reg_shift);
+ port->iotype = UPIO_MEM32;
+ port->type = PORT_XSCALE;
+ port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
+ port->regshift = 2;
+
+ return ret;
+}
+
static int skip_tx_en_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_port *port, int idx)
@@ -981,6 +997,7 @@ static int skip_tx_en_setup(struct serial_private *priv,
#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
#define PCI_VENDOR_ID_ADVANTECH 0x13fe
+#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
#define PCI_DEVICE_ID_TITAN_200I 0x8028
#define PCI_DEVICE_ID_TITAN_400I 0x8048
@@ -1072,6 +1089,13 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
.subdevice = PCI_ANY_ID,
.setup = skip_tx_en_setup,
},
+ {
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
+ .subvendor = PCI_ANY_ID,
+ .subdevice = PCI_ANY_ID,
+ .setup = ce4100_serial_setup,
+ },
/*
* ITE
*/
@@ -1592,6 +1616,7 @@ enum pci_board_num_t {
pbn_ADDIDATA_PCIe_2_3906250,
pbn_ADDIDATA_PCIe_4_3906250,
pbn_ADDIDATA_PCIe_8_3906250,
+ pbn_ce4100_1_115200,
};
/*
@@ -2281,6 +2306,12 @@ static struct pciserial_board pci_boards[] __devinitdata = {
.uart_offset = 0x200,
.first_offset = 0x1000,
},
+ [pbn_ce4100_1_115200] = {
+ .flags = FL_BASE0,
+ .num_ports = 1,
+ .base_baud = 921600,
+ .reg_shift = 2,
+ },
};
static const struct pci_device_id softmodem_blacklist[] = {
@@ -3765,6 +3796,11 @@ static struct pci_device_id serial_pci_tbl[] = {
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
0xA000, 0x3004,
0, 0, pbn_b0_bt_4_115200 },
+ /* Intel CE4100 */
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_ce4100_1_115200 },
+
/*
* These entries match devices with class COMMUNICATION_SERIAL,
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index aff9dcd051c..188aff6d263 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -1381,6 +1381,16 @@ config SERIAL_MSM_CONSOLE
depends on SERIAL_MSM=y
select SERIAL_CORE_CONSOLE
+config SERIAL_VT8500
+ bool "VIA VT8500 on-chip serial port support"
+ depends on ARM && ARCH_VT8500
+ select SERIAL_CORE
+
+config SERIAL_VT8500_CONSOLE
+ bool "VIA VT8500 serial console support"
+ depends on SERIAL_VT8500=y
+ select SERIAL_CORE_CONSOLE
+
config SERIAL_NETX
tristate "NetX serial port support"
depends on ARM && ARCH_NETX
@@ -1402,7 +1412,7 @@ config SERIAL_NETX_CONSOLE
config SERIAL_OF_PLATFORM
tristate "Serial port on Open Firmware platform bus"
- depends on PPC_OF || MICROBLAZE
+ depends on OF
depends on SERIAL_8250 || SERIAL_OF_PLATFORM_NWPSERIAL
help
If you have a PowerPC based system that has serial ports
@@ -1632,4 +1642,19 @@ config SERIAL_ALTERA_UART_CONSOLE
help
Enable a Altera UART port to be the system console.
+config SERIAL_IFX6X60
+ tristate "SPI protocol driver for Infineon 6x60 modem (EXPERIMENTAL)"
+ depends on GPIOLIB && SPI && EXPERIMENTAL
+ help
+ Support for the IFX6x60 modem devices on Intel MID platforms.
+
+config SERIAL_PCH_UART
+ tristate "Intel EG20T PCH UART"
+ depends on PCI && DMADEVICES
+ select SERIAL_CORE
+ select PCH_DMA
+ help
+ This driver is for PCH(Platform controller Hub) UART of Intel EG20T
+ which is an IOH(Input/Output Hub) for x86 embedded processor.
+ Enabling PCH_DMA, this PCH UART works as DMA mode.
endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index c5705765454..8ea92e9c73b 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -80,12 +80,15 @@ obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o
obj-$(CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL) += nwpserial.o
obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
+obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o
obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o
obj-$(CONFIG_SERIAL_QE) += ucc_uart.o
obj-$(CONFIG_SERIAL_TIMBERDALE) += timbuart.o
obj-$(CONFIG_SERIAL_GRLIB_GAISLER_APBUART) += apbuart.o
obj-$(CONFIG_SERIAL_ALTERA_JTAGUART) += altera_jtaguart.o
obj-$(CONFIG_SERIAL_ALTERA_UART) += altera_uart.o
+obj-$(CONFIG_SERIAL_VT8500) += vt8500_serial.o
obj-$(CONFIG_SERIAL_MRST_MAX3110) += mrst_max3110.o
obj-$(CONFIG_SERIAL_MFD_HSU) += mfd.o
-obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o
+obj-$(CONFIG_SERIAL_IFX6X60) += ifx6x60.o
+obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o
diff --git a/drivers/serial/amba-pl011.c b/drivers/serial/amba-pl011.c
index 6ca7a44f29c..e76d7d00012 100644
--- a/drivers/serial/amba-pl011.c
+++ b/drivers/serial/amba-pl011.c
@@ -7,6 +7,7 @@
*
* Copyright 1999 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd.
+ * Copyright (C) 2010 ST-Ericsson SA
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -48,6 +49,9 @@
#include <linux/amba/serial.h>
#include <linux/clk.h>
#include <linux/slab.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/scatterlist.h>
#include <asm/io.h>
#include <asm/sizes.h>
@@ -63,21 +67,6 @@
#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
#define UART_DUMMY_DR_RX (1 << 16)
-/*
- * We wrap our port structure around the generic uart_port.
- */
-struct uart_amba_port {
- struct uart_port port;
- struct clk *clk;
- unsigned int im; /* interrupt mask */
- unsigned int old_status;
- unsigned int ifls; /* vendor-specific */
- unsigned int lcrh_tx; /* vendor-specific */
- unsigned int lcrh_rx; /* vendor-specific */
- bool oversampling; /* vendor-specific */
- bool autorts;
-};
-
/* There is by now at least one vendor with differing details, so handle it */
struct vendor_data {
unsigned int ifls;
@@ -85,6 +74,7 @@ struct vendor_data {
unsigned int lcrh_tx;
unsigned int lcrh_rx;
bool oversampling;
+ bool dma_threshold;
};
static struct vendor_data vendor_arm = {
@@ -93,6 +83,7 @@ static struct vendor_data vendor_arm = {
.lcrh_tx = UART011_LCRH,
.lcrh_rx = UART011_LCRH,
.oversampling = false,
+ .dma_threshold = false,
};
static struct vendor_data vendor_st = {
@@ -101,22 +92,535 @@ static struct vendor_data vendor_st = {
.lcrh_tx = ST_UART011_LCRH_TX,
.lcrh_rx = ST_UART011_LCRH_RX,
.oversampling = true,
+ .dma_threshold = true,
+};
+
+/* Deals with DMA transactions */
+struct pl011_dmatx_data {
+ struct dma_chan *chan;
+ struct scatterlist sg;
+ char *buf;
+ bool queued;
};
+/*
+ * We wrap our port structure around the generic uart_port.
+ */
+struct uart_amba_port {
+ struct uart_port port;
+ struct clk *clk;
+ const struct vendor_data *vendor;
+ unsigned int dmacr; /* dma control reg */
+ unsigned int im; /* interrupt mask */
+ unsigned int old_status;
+ unsigned int fifosize; /* vendor-specific */
+ unsigned int lcrh_tx; /* vendor-specific */
+ unsigned int lcrh_rx; /* vendor-specific */
+ bool autorts;
+ char type[12];
+#ifdef CONFIG_DMA_ENGINE
+ /* DMA stuff */
+ bool using_dma;
+ struct pl011_dmatx_data dmatx;
+#endif
+};
+
+/*
+ * All the DMA operation mode stuff goes inside this ifdef.
+ * This assumes that you have a generic DMA device interface,
+ * no custom DMA interfaces are supported.
+ */
+#ifdef CONFIG_DMA_ENGINE
+
+#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
+
+static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
+{
+ /* DMA is the sole user of the platform data right now */
+ struct amba_pl011_data *plat = uap->port.dev->platform_data;
+ struct dma_slave_config tx_conf = {
+ .dst_addr = uap->port.mapbase + UART01x_DR,
+ .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
+ .direction = DMA_TO_DEVICE,
+ .dst_maxburst = uap->fifosize >> 1,
+ };
+ struct dma_chan *chan;
+ dma_cap_mask_t mask;
+
+ /* We need platform data */
+ if (!plat || !plat->dma_filter) {
+ dev_info(uap->port.dev, "no DMA platform data\n");
+ return;
+ }
+
+ /* Try to acquire a generic DMA engine slave channel */
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+
+ chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param);
+ if (!chan) {
+ dev_err(uap->port.dev, "no TX DMA channel!\n");
+ return;
+ }
+
+ dmaengine_slave_config(chan, &tx_conf);
+ uap->dmatx.chan = chan;
+
+ dev_info(uap->port.dev, "DMA channel TX %s\n",
+ dma_chan_name(uap->dmatx.chan));
+}
+
+#ifndef MODULE
+/*
+ * Stack up the UARTs and let the above initcall be done at device
+ * initcall time, because the serial driver is called as an arch
+ * initcall, and at this time the DMA subsystem is not yet registered.
+ * At this point the driver will switch over to using DMA where desired.
+ */
+struct dma_uap {
+ struct list_head node;
+ struct uart_amba_port *uap;
+};
+
+static LIST_HEAD(pl011_dma_uarts);
+
+static int __init pl011_dma_initcall(void)
+{
+ struct list_head *node, *tmp;
+
+ list_for_each_safe(node, tmp, &pl011_dma_uarts) {
+ struct dma_uap *dmau = list_entry(node, struct dma_uap, node);
+ pl011_dma_probe_initcall(dmau->uap);
+ list_del(node);
+ kfree(dmau);
+ }
+ return 0;
+}
+
+device_initcall(pl011_dma_initcall);
+
+static void pl011_dma_probe(struct uart_amba_port *uap)
+{
+ struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL);
+ if (dmau) {
+ dmau->uap = uap;
+ list_add_tail(&dmau->node, &pl011_dma_uarts);
+ }
+}
+#else
+static void pl011_dma_probe(struct uart_amba_port *uap)
+{
+ pl011_dma_probe_initcall(uap);
+}
+#endif
+
+static void pl011_dma_remove(struct uart_amba_port *uap)
+{
+ /* TODO: remove the initcall if it has not yet executed */
+ if (uap->dmatx.chan)
+ dma_release_channel(uap->dmatx.chan);
+}
+
+
+/* Forward declare this for the refill routine */
+static int pl011_dma_tx_refill(struct uart_amba_port *uap);
+
+/*
+ * The current DMA TX buffer has been sent.
+ * Try to queue up another DMA buffer.
+ */
+static void pl011_dma_tx_callback(void *data)
+{
+ struct uart_amba_port *uap = data;
+ struct pl011_dmatx_data *dmatx = &uap->dmatx;
+ unsigned long flags;
+ u16 dmacr;
+
+ spin_lock_irqsave(&uap->port.lock, flags);
+ if (uap->dmatx.queued)
+ dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
+ DMA_TO_DEVICE);
+
+ dmacr = uap->dmacr;
+ uap->dmacr = dmacr & ~UART011_TXDMAE;
+ writew(uap->dmacr, uap->port.membase + UART011_DMACR);
+
+ /*
+ * If TX DMA was disabled, it means that we've stopped the DMA for
+ * some reason (eg, XOFF received, or we want to send an X-char.)
+ *
+ * Note: we need to be careful here of a potential race between DMA
+ * and the rest of the driver - if the driver disables TX DMA while
+ * a TX buffer completing, we must update the tx queued status to
+ * get further refills (hence we check dmacr).
+ */
+ if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
+ uart_circ_empty(&uap->port.state->xmit)) {
+ uap->dmatx.queued = false;
+ spin_unlock_irqrestore(&uap->port.lock, flags);
+ return;
+ }
+
+ if (pl011_dma_tx_refill(uap) <= 0) {
+ /*
+ * We didn't queue a DMA buffer for some reason, but we
+ * have data pending to be sent. Re-enable the TX IRQ.
+ */
+ uap->im |= UART011_TXIM;
+ writew(uap->im, uap->port.membase + UART011_IMSC);
+ }
+ spin_unlock_irqrestore(&uap->port.lock, flags);
+}
+
+/*
+ * Try to refill the TX DMA buffer.
+ * Locking: called with port lock held and IRQs disabled.
+ * Returns:
+ * 1 if we queued up a TX DMA buffer.
+ * 0 if we didn't want to handle this by DMA
+ * <0 on error
+ */
+static int pl011_dma_tx_refill(struct uart_amba_port *uap)
+{
+ struct pl011_dmatx_data *dmatx = &uap->dmatx;
+ struct dma_chan *chan = dmatx->chan;
+ struct dma_device *dma_dev = chan->device;
+ struct dma_async_tx_descriptor *desc;
+ struct circ_buf *xmit = &uap->port.state->xmit;
+ unsigned int count;
+
+ /*
+ * Try to avoid the overhead involved in using DMA if the
+ * transaction fits in the first half of the FIFO, by using
+ * the standard interrupt handling. This ensures that we
+ * issue a uart_write_wakeup() at the appropriate time.
+ */
+ count = uart_circ_chars_pending(xmit);
+ if (count < (uap->fifosize >> 1)) {
+ uap->dmatx.queued = false;
+ return 0;
+ }
+
+ /*
+ * Bodge: don't send the last character by DMA, as this
+ * will prevent XON from notifying us to restart DMA.
+ */
+ count -= 1;
+
+ /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
+ if (count > PL011_DMA_BUFFER_SIZE)
+ count = PL011_DMA_BUFFER_SIZE;
+
+ if (xmit->tail < xmit->head)
+ memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
+ else {
+ size_t first = UART_XMIT_SIZE - xmit->tail;
+ size_t second = xmit->head;
+
+ memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
+ if (second)
+ memcpy(&dmatx->buf[first], &xmit->buf[0], second);
+ }
+
+ dmatx->sg.length = count;
+
+ if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
+ uap->dmatx.queued = false;
+ dev_dbg(uap->port.dev, "unable to map TX DMA\n");
+ return -EBUSY;
+ }
+
+ desc = dma_dev->device_prep_slave_sg(chan, &dmatx->sg, 1, DMA_TO_DEVICE,
+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+ if (!desc) {
+ dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
+ uap->dmatx.queued = false;
+ /*
+ * If DMA cannot be used right now, we complete this
+ * transaction via IRQ and let the TTY layer retry.
+ */
+ dev_dbg(uap->port.dev, "TX DMA busy\n");
+ return -EBUSY;
+ }
+
+ /* Some data to go along to the callback */
+ desc->callback = pl011_dma_tx_callback;
+ desc->callback_param = uap;
+
+ /* All errors should happen at prepare time */
+ dmaengine_submit(desc);
+
+ /* Fire the DMA transaction */
+ dma_dev->device_issue_pending(chan);
+
+ uap->dmacr |= UART011_TXDMAE;
+ writew(uap->dmacr, uap->port.membase + UART011_DMACR);
+ uap->dmatx.queued = true;
+
+ /*
+ * Now we know that DMA will fire, so advance the ring buffer
+ * with the stuff we just dispatched.
+ */
+ xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
+ uap->port.icount.tx += count;
+
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ uart_write_wakeup(&uap->port);
+
+ return 1;
+}
+
+/*
+ * We received a transmit interrupt without a pending X-char but with
+ * pending characters.
+ * Locking: called with port lock held and IRQs disabled.
+ * Returns:
+ * false if we want to use PIO to transmit
+ * true if we queued a DMA buffer
+ */
+static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
+{
+ if (!uap->using_dma)
+ return false;
+
+ /*
+ * If we already have a TX buffer queued, but received a
+ * TX interrupt, it will be because we've just sent an X-char.
+ * Ensure the TX DMA is enabled and the TX IRQ is disabled.
+ */
+ if (uap->dmatx.queued) {
+ uap->dmacr |= UART011_TXDMAE;
+ writew(uap->dmacr, uap->port.membase + UART011_DMACR);
+ uap->im &= ~UART011_TXIM;
+ writew(uap->im, uap->port.membase + UART011_IMSC);
+ return true;
+ }
+
+ /*
+ * We don't have a TX buffer queued, so try to queue one.
+ * If we succesfully queued a buffer, mask the TX IRQ.
+ */
+ if (pl011_dma_tx_refill(uap) > 0) {
+ uap->im &= ~UART011_TXIM;
+ writew(uap->im, uap->port.membase + UART011_IMSC);
+ return true;
+ }
+ return false;
+}
+
+/*
+ * Stop the DMA transmit (eg, due to received XOFF).
+ * Locking: called with port lock held and IRQs disabled.
+ */
+static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
+{
+ if (uap->dmatx.queued) {
+ uap->dmacr &= ~UART011_TXDMAE;
+ writew(uap->dmacr, uap->port.membase + UART011_DMACR);
+ }
+}
+
+/*
+ * Try to start a DMA transmit, or in the case of an XON/OFF
+ * character queued for send, try to get that character out ASAP.
+ * Locking: called with port lock held and IRQs disabled.
+ * Returns:
+ * false if we want the TX IRQ to be enabled
+ * true if we have a buffer queued
+ */
+static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
+{
+ u16 dmacr;
+
+ if (!uap->using_dma)
+ return false;
+
+ if (!uap->port.x_char) {
+ /* no X-char, try to push chars out in DMA mode */
+ bool ret = true;
+
+ if (!uap->dmatx.queued) {
+ if (pl011_dma_tx_refill(uap) > 0) {
+ uap->im &= ~UART011_TXIM;
+ ret = true;
+ } else {
+ uap->im |= UART011_TXIM;
+ ret = false;
+ }
+ writew(uap->im, uap->port.membase + UART011_IMSC);
+ } else if (!(uap->dmacr & UART011_TXDMAE)) {
+ uap->dmacr |= UART011_TXDMAE;
+ writew(uap->dmacr,
+ uap->port.membase + UART011_DMACR);
+ }
+ return ret;
+ }
+
+ /*
+ * We have an X-char to send. Disable DMA to prevent it loading
+ * the TX fifo, and then see if we can stuff it into the FIFO.
+ */
+ dmacr = uap->dmacr;
+ uap->dmacr &= ~UART011_TXDMAE;
+ writew(uap->dmacr, uap->port.membase + UART011_DMACR);
+
+ if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
+ /*
+ * No space in the FIFO, so enable the transmit interrupt
+ * so we know when there is space. Note that once we've
+ * loaded the character, we should just re-enable DMA.
+ */
+ return false;
+ }
+
+ writew(uap->port.x_char, uap->port.membase + UART01x_DR);
+ uap->port.icount.tx++;
+ uap->port.x_char = 0;
+
+ /* Success - restore the DMA state */
+ uap->dmacr = dmacr;
+ writew(dmacr, uap->port.membase + UART011_DMACR);
+
+ return true;
+}
+
+/*
+ * Flush the transmit buffer.
+ * Locking: called with port lock held and IRQs disabled.
+ */
+static void pl011_dma_flush_buffer(struct uart_port *port)
+{
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+
+ if (!uap->using_dma)
+ return;
+
+ /* Avoid deadlock with the DMA engine callback */
+ spin_unlock(&uap->port.lock);
+ dmaengine_terminate_all(uap->dmatx.chan);
+ spin_lock(&uap->port.lock);
+ if (uap->dmatx.queued) {
+ dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
+ DMA_TO_DEVICE);
+ uap->dmatx.queued = false;
+ uap->dmacr &= ~UART011_TXDMAE;
+ writew(uap->dmacr, uap->port.membase + UART011_DMACR);
+ }
+}
+
+
+static void pl011_dma_startup(struct uart_amba_port *uap)
+{
+ if (!uap->dmatx.chan)
+ return;
+
+ uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
+ if (!uap->dmatx.buf) {
+ dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
+ uap->port.fifosize = uap->fifosize;
+ return;
+ }
+
+ sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
+
+ /* The DMA buffer is now the FIFO the TTY subsystem can use */
+ uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
+ uap->using_dma = true;
+
+ /* Turn on DMA error (RX/TX will be enabled on demand) */
+ uap->dmacr |= UART011_DMAONERR;
+ writew(uap->dmacr, uap->port.membase + UART011_DMACR);
+
+ /*
+ * ST Micro variants has some specific dma burst threshold
+ * compensation. Set this to 16 bytes, so burst will only
+ * be issued above/below 16 bytes.
+ */
+ if (uap->vendor->dma_threshold)
+ writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
+ uap->port.membase + ST_UART011_DMAWM);
+}
+
+static void pl011_dma_shutdown(struct uart_amba_port *uap)
+{
+ if (!uap->using_dma)
+ return;
+
+ /* Disable RX and TX DMA */
+ while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
+ barrier();
+
+ spin_lock_irq(&uap->port.lock);
+ uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
+ writew(uap->dmacr, uap->port.membase + UART011_DMACR);
+ spin_unlock_irq(&uap->port.lock);
+
+ /* In theory, this should already be done by pl011_dma_flush_buffer */
+ dmaengine_terminate_all(uap->dmatx.chan);
+ if (uap->dmatx.queued) {
+ dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
+ DMA_TO_DEVICE);
+ uap->dmatx.queued = false;
+ }
+
+ kfree(uap->dmatx.buf);
+
+ uap->using_dma = false;
+}
+
+#else
+/* Blank functions if the DMA engine is not available */
+static inline void pl011_dma_probe(struct uart_amba_port *uap)
+{
+}
+
+static inline void pl011_dma_remove(struct uart_amba_port *uap)
+{
+}
+
+static inline void pl011_dma_startup(struct uart_amba_port *uap)
+{
+}
+
+static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
+{
+}
+
+static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
+{
+ return false;
+}
+
+static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
+{
+}
+
+static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
+{
+ return false;
+}
+
+#define pl011_dma_flush_buffer NULL
+#endif
+
+
static void pl011_stop_tx(struct uart_port *port)
{
struct uart_amba_port *uap = (struct uart_amba_port *)port;
uap->im &= ~UART011_TXIM;
writew(uap->im, uap->port.membase + UART011_IMSC);
+ pl011_dma_tx_stop(uap);
}
static void pl011_start_tx(struct uart_port *port)
{
struct uart_amba_port *uap = (struct uart_amba_port *)port;
- uap->im |= UART011_TXIM;
- writew(uap->im, uap->port.membase + UART011_IMSC);
+ if (!pl011_dma_tx_start(uap)) {
+ uap->im |= UART011_TXIM;
+ writew(uap->im, uap->port.membase + UART011_IMSC);
+ }
}
static void pl011_stop_rx(struct uart_port *port)
@@ -203,7 +707,11 @@ static void pl011_tx_chars(struct uart_amba_port *uap)
return;
}
- count = uap->port.fifosize >> 1;
+ /* If we are using DMA mode, try to send some characters. */
+ if (pl011_dma_tx_irq(uap))
+ return;
+
+ count = uap->fifosize >> 1;
do {
writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
@@ -246,10 +754,11 @@ static void pl011_modem_status(struct uart_amba_port *uap)
static irqreturn_t pl011_int(int irq, void *dev_id)
{
struct uart_amba_port *uap = dev_id;
+ unsigned long flags;
unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
int handled = 0;
- spin_lock(&uap->port.lock);
+ spin_lock_irqsave(&uap->port.lock, flags);
status = readw(uap->port.membase + UART011_MIS);
if (status) {
@@ -274,7 +783,7 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
handled = 1;
}
- spin_unlock(&uap->port.lock);
+ spin_unlock_irqrestore(&uap->port.lock, flags);
return IRQ_RETVAL(handled);
}
@@ -396,7 +905,7 @@ static int pl011_startup(struct uart_port *port)
if (retval)
goto clk_dis;
- writew(uap->ifls, uap->port.membase + UART011_IFLS);
+ writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
/*
* Provoke TX FIFO interrupt into asserting.
@@ -423,11 +932,18 @@ static int pl011_startup(struct uart_port *port)
cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
writew(cr, uap->port.membase + UART011_CR);
+ /* Clear pending error interrupts */
+ writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
+ uap->port.membase + UART011_ICR);
+
/*
* initialise the old status of the modem signals
*/
uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
+ /* Startup DMA */
+ pl011_dma_startup(uap);
+
/*
* Finally, enable interrupts
*/
@@ -467,6 +983,8 @@ static void pl011_shutdown(struct uart_port *port)
writew(0xffff, uap->port.membase + UART011_ICR);
spin_unlock_irq(&uap->port.lock);
+ pl011_dma_shutdown(uap);
+
/*
* Free the interrupt
*/
@@ -498,13 +1016,18 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
struct uart_amba_port *uap = (struct uart_amba_port *)port;
unsigned int lcr_h, old_cr;
unsigned long flags;
- unsigned int baud, quot;
+ unsigned int baud, quot, clkdiv;
+
+ if (uap->vendor->oversampling)
+ clkdiv = 8;
+ else
+ clkdiv = 16;
/*
* Ask the core to calculate the divisor for us.
*/
baud = uart_get_baud_rate(port, termios, old, 0,
- port->uartclk/(uap->oversampling ? 8 : 16));
+ port->uartclk / clkdiv);
if (baud > port->uartclk/16)
quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
@@ -532,7 +1055,7 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
if (!(termios->c_cflag & PARODD))
lcr_h |= UART01x_LCRH_EPS;
}
- if (port->fifosize > 1)
+ if (uap->fifosize > 1)
lcr_h |= UART01x_LCRH_FEN;
spin_lock_irqsave(&port->lock, flags);
@@ -588,8 +1111,8 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
uap->autorts = false;
}
- if (uap->oversampling) {
- if (baud > port->uartclk/16)
+ if (uap->vendor->oversampling) {
+ if (baud > port->uartclk / 16)
old_cr |= ST_UART011_CR_OVSFACT;
else
old_cr &= ~ST_UART011_CR_OVSFACT;
@@ -622,7 +1145,8 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
static const char *pl011_type(struct uart_port *port)
{
- return port->type == PORT_AMBA ? "AMBA/PL011" : NULL;
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+ return uap->port.type == PORT_AMBA ? uap->type : NULL;
}
/*
@@ -679,6 +1203,7 @@ static struct uart_ops amba_pl011_pops = {
.break_ctl = pl011_break_ctl,
.startup = pl011_startup,
.shutdown = pl011_shutdown,
+ .flush_buffer = pl011_dma_flush_buffer,
.set_termios = pl011_set_termios,
.type = pl011_type,
.release_port = pl010_release_port,
@@ -761,7 +1286,7 @@ pl011_console_get_options(struct uart_amba_port *uap, int *baud,
*baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
- if (uap->oversampling) {
+ if (uap->vendor->oversampling) {
if (readw(uap->port.membase + UART011_CR)
& ST_UART011_CR_OVSFACT)
*baud *= 2;
@@ -858,19 +1383,22 @@ static int pl011_probe(struct amba_device *dev, struct amba_id *id)
goto unmap;
}
- uap->ifls = vendor->ifls;
+ uap->vendor = vendor;
uap->lcrh_rx = vendor->lcrh_rx;
uap->lcrh_tx = vendor->lcrh_tx;
- uap->oversampling = vendor->oversampling;
+ uap->fifosize = vendor->fifosize;
uap->port.dev = &dev->dev;
uap->port.mapbase = dev->res.start;
uap->port.membase = base;
uap->port.iotype = UPIO_MEM;
uap->port.irq = dev->irq[0];
- uap->port.fifosize = vendor->fifosize;
+ uap->port.fifosize = uap->fifosize;
uap->port.ops = &amba_pl011_pops;
uap->port.flags = UPF_BOOT_AUTOCONF;
uap->port.line = i;
+ pl011_dma_probe(uap);
+
+ snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
amba_ports[i] = uap;
@@ -879,6 +1407,7 @@ static int pl011_probe(struct amba_device *dev, struct amba_id *id)
if (ret) {
amba_set_drvdata(dev, NULL);
amba_ports[i] = NULL;
+ pl011_dma_remove(uap);
clk_put(uap->clk);
unmap:
iounmap(base);
@@ -902,6 +1431,7 @@ static int pl011_remove(struct amba_device *dev)
if (amba_ports[i] == uap)
amba_ports[i] = NULL;
+ pl011_dma_remove(uap);
iounmap(uap->port.membase);
clk_put(uap->clk);
kfree(uap);
diff --git a/drivers/serial/apbuart.c b/drivers/serial/apbuart.c
index cc01c650a14..095a5d56261 100644
--- a/drivers/serial/apbuart.c
+++ b/drivers/serial/apbuart.c
@@ -26,6 +26,7 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
+#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/serial_core.h>
@@ -520,11 +521,12 @@ static struct console grlib_apbuart_console = {
};
-static void grlib_apbuart_configure(void);
+static int grlib_apbuart_configure(void);
static int __init apbuart_console_init(void)
{
- grlib_apbuart_configure();
+ if (grlib_apbuart_configure())
+ return -ENODEV;
register_console(&grlib_apbuart_console);
return 0;
}
@@ -573,13 +575,15 @@ static int __devinit apbuart_probe(struct platform_device *op,
printk(KERN_INFO "grlib-apbuart at 0x%llx, irq %d\n",
(unsigned long long) port->mapbase, port->irq);
return 0;
-
}
static struct of_device_id __initdata apbuart_match[] = {
{
.name = "GAISLER_APBUART",
},
+ {
+ .name = "01_00c",
+ },
{},
};
@@ -593,54 +597,49 @@ static struct of_platform_driver grlib_apbuart_of_driver = {
};
-static void grlib_apbuart_configure(void)
+static int grlib_apbuart_configure(void)
{
- static int enum_done;
struct device_node *np, *rp;
- struct uart_port *port = NULL;
const u32 *prop;
- int freq_khz;
- int v = 0, d = 0;
- unsigned int addr;
- int irq, line;
- struct amba_prom_registers *regs;
-
- if (enum_done)
- return;
+ int freq_khz, line = 0;
/* Get bus frequency */
rp = of_find_node_by_path("/");
+ if (!rp)
+ return -ENODEV;
rp = of_get_next_child(rp, NULL);
+ if (!rp)
+ return -ENODEV;
prop = of_get_property(rp, "clock-frequency", NULL);
+ if (!prop)
+ return -ENODEV;
freq_khz = *prop;
- line = 0;
for_each_matching_node(np, apbuart_match) {
+ const int *irqs, *ampopts;
+ const struct amba_prom_registers *regs;
+ struct uart_port *port;
+ unsigned long addr;
- int *vendor = (int *) of_get_property(np, "vendor", NULL);
- int *device = (int *) of_get_property(np, "device", NULL);
- int *irqs = (int *) of_get_property(np, "interrupts", NULL);
- regs = (struct amba_prom_registers *)
- of_get_property(np, "reg", NULL);
+ ampopts = of_get_property(np, "ampopts", NULL);
+ if (ampopts && (*ampopts == 0))
+ continue; /* Ignore if used by another OS instance */
- if (vendor)
- v = *vendor;
- if (device)
- d = *device;
+ irqs = of_get_property(np, "interrupts", NULL);
+ regs = of_get_property(np, "reg", NULL);
if (!irqs || !regs)
- return;
+ continue;
grlib_apbuart_nodes[line] = np;
addr = regs->phys_addr;
- irq = *irqs;
port = &grlib_apbuart_ports[line];
port->mapbase = addr;
port->membase = ioremap(addr, sizeof(struct grlib_apbuart_regs_map));
- port->irq = irq;
+ port->irq = *irqs;
port->iotype = UPIO_MEM;
port->ops = &grlib_apbuart_ops;
port->flags = UPF_BOOT_AUTOCONF;
@@ -652,12 +651,10 @@ static void grlib_apbuart_configure(void)
/* We support maximum UART_NR uarts ... */
if (line == UART_NR)
break;
-
}
- enum_done = 1;
-
grlib_apbuart_driver.nr = grlib_apbuart_port_nr = line;
+ return line ? 0 : -ENODEV;
}
static int __init grlib_apbuart_init(void)
@@ -665,7 +662,9 @@ static int __init grlib_apbuart_init(void)
int ret;
/* Find all APBUARTS in device the tree and initialize their ports */
- grlib_apbuart_configure();
+ ret = grlib_apbuart_configure();
+ if (ret)
+ return ret;
printk(KERN_INFO "Serial: GRLIB APBUART driver\n");
diff --git a/drivers/serial/cpm_uart/cpm_uart.h b/drivers/serial/cpm_uart/cpm_uart.h
index 7274b527a3c..b754dcf0fda 100644
--- a/drivers/serial/cpm_uart/cpm_uart.h
+++ b/drivers/serial/cpm_uart/cpm_uart.h
@@ -76,18 +76,12 @@ struct uart_cpm_port {
unsigned char *tx_buf;
unsigned char *rx_buf;
u32 flags;
- void (*set_lineif)(struct uart_cpm_port *);
struct clk *clk;
u8 brg;
uint dp_addr;
void *mem_addr;
dma_addr_t dma_addr;
u32 mem_size;
- /* helpers */
- int baud;
- int bits;
- /* Keep track of 'odd' SMC2 wirings */
- int is_portb;
/* wait on close if needed */
int wait_closing;
/* value to combine with opcode to form cpm command */
diff --git a/drivers/serial/cpm_uart/cpm_uart_core.c b/drivers/serial/cpm_uart/cpm_uart_core.c
index f2b8adcc6c9..8692ff98fc0 100644
--- a/drivers/serial/cpm_uart/cpm_uart_core.c
+++ b/drivers/serial/cpm_uart/cpm_uart_core.c
@@ -72,6 +72,8 @@ static void cpm_uart_initbd(struct uart_cpm_port *pinfo);
/**************************************************************/
+#define HW_BUF_SPD_THRESHOLD 9600
+
/*
* Check, if transmit buffers are processed
*/
@@ -503,6 +505,11 @@ static void cpm_uart_set_termios(struct uart_port *port,
pr_debug("CPM uart[%d]:set_termios\n", port->line);
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
+ if (baud <= HW_BUF_SPD_THRESHOLD ||
+ (pinfo->port.state && pinfo->port.state->port.tty->low_latency))
+ pinfo->rx_fifosize = 1;
+ else
+ pinfo->rx_fifosize = RX_BUF_SIZE;
/* Character length programmed into the mode register is the
* sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
@@ -594,6 +601,17 @@ static void cpm_uart_set_termios(struct uart_port *port,
*/
bits++;
if (IS_SMC(pinfo)) {
+ /*
+ * MRBLR can be changed while an SMC/SCC is operating only
+ * if it is done in a single bus cycle with one 16-bit move
+ * (not two 8-bit bus cycles back-to-back). This occurs when
+ * the cp shifts control to the next RxBD, so the change does
+ * not take effect immediately. To guarantee the exact RxBD
+ * on which the change occurs, change MRBLR only while the
+ * SMC/SCC receiver is disabled.
+ */
+ out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize);
+
/* Set the mode register. We want to keep a copy of the
* enables, because we want to put them back if they were
* present.
@@ -604,6 +622,7 @@ static void cpm_uart_set_termios(struct uart_port *port,
out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval |
SMCMR_SM_UART | prev_mode);
} else {
+ out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
out_be16(&sccp->scc_psmr, (sbits << 12) | scval);
}
diff --git a/drivers/serial/crisv10.c b/drivers/serial/crisv10.c
index fa62578fcd2..bcc31f2140a 100644
--- a/drivers/serial/crisv10.c
+++ b/drivers/serial/crisv10.c
@@ -18,7 +18,6 @@ static char *serial_version = "$Revision: 1.25 $";
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/major.h>
-#include <linux/smp_lock.h>
#include <linux/string.h>
#include <linux/fcntl.h>
#include <linux/mm.h>
diff --git a/drivers/serial/ifx6x60.c b/drivers/serial/ifx6x60.c
new file mode 100644
index 00000000000..ab93763862d
--- /dev/null
+++ b/drivers/serial/ifx6x60.c
@@ -0,0 +1,1406 @@
+/****************************************************************************
+ *
+ * Driver for the IFX 6x60 spi modem.
+ *
+ * Copyright (C) 2008 Option International
+ * Copyright (C) 2008 Filip Aben <f.aben@option.com>
+ * Denis Joseph Barrow <d.barow@option.com>
+ * Jan Dumon <j.dumon@option.com>
+ *
+ * Copyright (C) 2009, 2010 Intel Corp
+ * Russ Gorby <richardx.r.gorby@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
+ * USA
+ *
+ * Driver modified by Intel from Option gtm501l_spi.c
+ *
+ * Notes
+ * o The driver currently assumes a single device only. If you need to
+ * change this then look for saved_ifx_dev and add a device lookup
+ * o The driver is intended to be big-endian safe but has never been
+ * tested that way (no suitable hardware). There are a couple of FIXME
+ * notes by areas that may need addressing
+ * o Some of the GPIO naming/setup assumptions may need revisiting if
+ * you need to use this driver for another platform.
+ *
+ *****************************************************************************/
+#include <linux/module.h>
+#include <linux/termios.h>
+#include <linux/tty.h>
+#include <linux/device.h>
+#include <linux/spi/spi.h>
+#include <linux/tty.h>
+#include <linux/kfifo.h>
+#include <linux/tty_flip.h>
+#include <linux/timer.h>
+#include <linux/serial.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/rfkill.h>
+#include <linux/fs.h>
+#include <linux/ip.h>
+#include <linux/dmapool.h>
+#include <linux/gpio.h>
+#include <linux/sched.h>
+#include <linux/time.h>
+#include <linux/wait.h>
+#include <linux/tty.h>
+#include <linux/pm.h>
+#include <linux/pm_runtime.h>
+#include <linux/spi/ifx_modem.h>
+#include <linux/delay.h>
+
+#include "ifx6x60.h"
+
+#define IFX_SPI_MORE_MASK 0x10
+#define IFX_SPI_MORE_BIT 12 /* bit position in u16 */
+#define IFX_SPI_CTS_BIT 13 /* bit position in u16 */
+#define IFX_SPI_TTY_ID 0
+#define IFX_SPI_TIMEOUT_SEC 2
+#define IFX_SPI_HEADER_0 (-1)
+#define IFX_SPI_HEADER_F (-2)
+
+/* forward reference */
+static void ifx_spi_handle_srdy(struct ifx_spi_device *ifx_dev);
+
+/* local variables */
+static int spi_b16 = 1; /* 8 or 16 bit word length */
+static struct tty_driver *tty_drv;
+static struct ifx_spi_device *saved_ifx_dev;
+static struct lock_class_key ifx_spi_key;
+
+/* GPIO/GPE settings */
+
+/**
+ * mrdy_set_high - set MRDY GPIO
+ * @ifx: device we are controlling
+ *
+ */
+static inline void mrdy_set_high(struct ifx_spi_device *ifx)
+{
+ gpio_set_value(ifx->gpio.mrdy, 1);
+}
+
+/**
+ * mrdy_set_low - clear MRDY GPIO
+ * @ifx: device we are controlling
+ *
+ */
+static inline void mrdy_set_low(struct ifx_spi_device *ifx)
+{
+ gpio_set_value(ifx->gpio.mrdy, 0);
+}
+
+/**
+ * ifx_spi_power_state_set
+ * @ifx_dev: our SPI device
+ * @val: bits to set
+ *
+ * Set bit in power status and signal power system if status becomes non-0
+ */
+static void
+ifx_spi_power_state_set(struct ifx_spi_device *ifx_dev, unsigned char val)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&ifx_dev->power_lock, flags);
+
+ /*
+ * if power status is already non-0, just update, else
+ * tell power system
+ */
+ if (!ifx_dev->power_status)
+ pm_runtime_get(&ifx_dev->spi_dev->dev);
+ ifx_dev->power_status |= val;
+
+ spin_unlock_irqrestore(&ifx_dev->power_lock, flags);
+}
+
+/**
+ * ifx_spi_power_state_clear - clear power bit
+ * @ifx_dev: our SPI device
+ * @val: bits to clear
+ *
+ * clear bit in power status and signal power system if status becomes 0
+ */
+static void
+ifx_spi_power_state_clear(struct ifx_spi_device *ifx_dev, unsigned char val)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&ifx_dev->power_lock, flags);
+
+ if (ifx_dev->power_status) {
+ ifx_dev->power_status &= ~val;
+ if (!ifx_dev->power_status)
+ pm_runtime_put(&ifx_dev->spi_dev->dev);
+ }
+
+ spin_unlock_irqrestore(&ifx_dev->power_lock, flags);
+}
+
+/**
+ * swap_buf
+ * @buf: our buffer
+ * @len : number of bytes (not words) in the buffer
+ * @end: end of buffer
+ *
+ * Swap the contents of a buffer into big endian format
+ */
+static inline void swap_buf(u16 *buf, int len, void *end)
+{
+ int n;
+
+ len = ((len + 1) >> 1);
+ if ((void *)&buf[len] > end) {
+ pr_err("swap_buf: swap exceeds boundary (%p > %p)!",
+ &buf[len], end);
+ return;
+ }
+ for (n = 0; n < len; n++) {
+ *buf = cpu_to_be16(*buf);
+ buf++;
+ }
+}
+
+/**
+ * mrdy_assert - assert MRDY line
+ * @ifx_dev: our SPI device
+ *
+ * Assert mrdy and set timer to wait for SRDY interrupt, if SRDY is low
+ * now.
+ *
+ * FIXME: Can SRDY even go high as we are running this code ?
+ */
+static void mrdy_assert(struct ifx_spi_device *ifx_dev)
+{
+ int val = gpio_get_value(ifx_dev->gpio.srdy);
+ if (!val) {
+ if (!test_and_set_bit(IFX_SPI_STATE_TIMER_PENDING,
+ &ifx_dev->flags)) {
+ ifx_dev->spi_timer.expires =
+ jiffies + IFX_SPI_TIMEOUT_SEC*HZ;
+ add_timer(&ifx_dev->spi_timer);
+
+ }
+ }
+ ifx_spi_power_state_set(ifx_dev, IFX_SPI_POWER_DATA_PENDING);
+ mrdy_set_high(ifx_dev);
+}
+
+/**
+ * ifx_spi_hangup - hang up an IFX device
+ * @ifx_dev: our SPI device
+ *
+ * Hang up the tty attached to the IFX device if one is currently
+ * open. If not take no action
+ */
+static void ifx_spi_ttyhangup(struct ifx_spi_device *ifx_dev)
+{
+ struct tty_port *pport = &ifx_dev->tty_port;
+ struct tty_struct *tty = tty_port_tty_get(pport);
+ if (tty) {
+ tty_hangup(tty);
+ tty_kref_put(tty);
+ }
+}
+
+/**
+ * ifx_spi_timeout - SPI timeout
+ * @arg: our SPI device
+ *
+ * The SPI has timed out: hang up the tty. Users will then see a hangup
+ * and error events.
+ */
+static void ifx_spi_timeout(unsigned long arg)
+{
+ struct ifx_spi_device *ifx_dev = (struct ifx_spi_device *)arg;
+
+ dev_warn(&ifx_dev->spi_dev->dev, "*** SPI Timeout ***");
+ ifx_spi_ttyhangup(ifx_dev);
+ mrdy_set_low(ifx_dev);
+ clear_bit(IFX_SPI_STATE_TIMER_PENDING, &ifx_dev->flags);
+}
+
+/* char/tty operations */
+
+/**
+ * ifx_spi_tiocmget - get modem lines
+ * @tty: our tty device
+ * @filp: file handle issuing the request
+ *
+ * Map the signal state into Linux modem flags and report the value
+ * in Linux terms
+ */
+static int ifx_spi_tiocmget(struct tty_struct *tty, struct file *filp)
+{
+ unsigned int value;
+ struct ifx_spi_device *ifx_dev = tty->driver_data;
+
+ value =
+ (test_bit(IFX_SPI_RTS, &ifx_dev->signal_state) ? TIOCM_RTS : 0) |
+ (test_bit(IFX_SPI_DTR, &ifx_dev->signal_state) ? TIOCM_DTR : 0) |
+ (test_bit(IFX_SPI_CTS, &ifx_dev->signal_state) ? TIOCM_CTS : 0) |
+ (test_bit(IFX_SPI_DSR, &ifx_dev->signal_state) ? TIOCM_DSR : 0) |
+ (test_bit(IFX_SPI_DCD, &ifx_dev->signal_state) ? TIOCM_CAR : 0) |
+ (test_bit(IFX_SPI_RI, &ifx_dev->signal_state) ? TIOCM_RNG : 0);
+ return value;
+}
+
+/**
+ * ifx_spi_tiocmset - set modem bits
+ * @tty: the tty structure
+ * @filp: file handle issuing the request
+ * @set: bits to set
+ * @clear: bits to clear
+ *
+ * The IFX6x60 only supports DTR and RTS. Set them accordingly
+ * and flag that an update to the modem is needed.
+ *
+ * FIXME: do we need to kick the tranfers when we do this ?
+ */
+static int ifx_spi_tiocmset(struct tty_struct *tty, struct file *filp,
+ unsigned int set, unsigned int clear)
+{
+ struct ifx_spi_device *ifx_dev = tty->driver_data;
+
+ if (set & TIOCM_RTS)
+ set_bit(IFX_SPI_RTS, &ifx_dev->signal_state);
+ if (set & TIOCM_DTR)
+ set_bit(IFX_SPI_DTR, &ifx_dev->signal_state);
+ if (clear & TIOCM_RTS)
+ clear_bit(IFX_SPI_RTS, &ifx_dev->signal_state);
+ if (clear & TIOCM_DTR)
+ clear_bit(IFX_SPI_DTR, &ifx_dev->signal_state);
+
+ set_bit(IFX_SPI_UPDATE, &ifx_dev->signal_state);
+ return 0;
+}
+
+/**
+ * ifx_spi_open - called on tty open
+ * @tty: our tty device
+ * @filp: file handle being associated with the tty
+ *
+ * Open the tty interface. We let the tty_port layer do all the work
+ * for us.
+ *
+ * FIXME: Remove single device assumption and saved_ifx_dev
+ */
+static int ifx_spi_open(struct tty_struct *tty, struct file *filp)
+{
+ return tty_port_open(&saved_ifx_dev->tty_port, tty, filp);
+}
+
+/**
+ * ifx_spi_close - called when our tty closes
+ * @tty: the tty being closed
+ * @filp: the file handle being closed
+ *
+ * Perform the close of the tty. We use the tty_port layer to do all
+ * our hard work.
+ */
+static void ifx_spi_close(struct tty_struct *tty, struct file *filp)
+{
+ struct ifx_spi_device *ifx_dev = tty->driver_data;
+ tty_port_close(&ifx_dev->tty_port, tty, filp);
+ /* FIXME: should we do an ifx_spi_reset here ? */
+}
+
+/**
+ * ifx_decode_spi_header - decode received header
+ * @buffer: the received data
+ * @length: decoded length
+ * @more: decoded more flag
+ * @received_cts: status of cts we received
+ *
+ * Note how received_cts is handled -- if header is all F it is left
+ * the same as it was, if header is all 0 it is set to 0 otherwise it is
+ * taken from the incoming header.
+ *
+ * FIXME: endianness
+ */
+static int ifx_spi_decode_spi_header(unsigned char *buffer, int *length,
+ unsigned char *more, unsigned char *received_cts)
+{
+ u16 h1;
+ u16 h2;
+ u16 *in_buffer = (u16 *)buffer;
+
+ h1 = *in_buffer;
+ h2 = *(in_buffer+1);
+
+ if (h1 == 0 && h2 == 0) {
+ *received_cts = 0;
+ return IFX_SPI_HEADER_0;
+ } else if (h1 == 0xffff && h2 == 0xffff) {
+ /* spi_slave_cts remains as it was */
+ return IFX_SPI_HEADER_F;
+ }
+
+ *length = h1 & 0xfff; /* upper bits of byte are flags */
+ *more = (buffer[1] >> IFX_SPI_MORE_BIT) & 1;
+ *received_cts = (buffer[3] >> IFX_SPI_CTS_BIT) & 1;
+ return 0;
+}
+
+/**
+ * ifx_setup_spi_header - set header fields
+ * @txbuffer: pointer to start of SPI buffer
+ * @tx_count: bytes
+ * @more: indicate if more to follow
+ *
+ * Format up an SPI header for a transfer
+ *
+ * FIXME: endianness?
+ */
+static void ifx_spi_setup_spi_header(unsigned char *txbuffer, int tx_count,
+ unsigned char more)
+{
+ *(u16 *)(txbuffer) = tx_count;
+ *(u16 *)(txbuffer+2) = IFX_SPI_PAYLOAD_SIZE;
+ txbuffer[1] |= (more << IFX_SPI_MORE_BIT) & IFX_SPI_MORE_MASK;
+}
+
+/**
+ * ifx_spi_wakeup_serial - SPI space made
+ * @port_data: our SPI device
+ *
+ * We have emptied the FIFO enough that we want to get more data
+ * queued into it. Poke the line discipline via tty_wakeup so that
+ * it will feed us more bits
+ */
+static void ifx_spi_wakeup_serial(struct ifx_spi_device *ifx_dev)
+{
+ struct tty_struct *tty;
+
+ tty = tty_port_tty_get(&ifx_dev->tty_port);
+ if (!tty)
+ return;
+ tty_wakeup(tty);
+ tty_kref_put(tty);
+}
+
+/**
+ * ifx_spi_prepare_tx_buffer - prepare transmit frame
+ * @ifx_dev: our SPI device
+ *
+ * The transmit buffr needs a header and various other bits of
+ * information followed by as much data as we can pull from the FIFO
+ * and transfer. This function formats up a suitable buffer in the
+ * ifx_dev->tx_buffer
+ *
+ * FIXME: performance - should we wake the tty when the queue is half
+ * empty ?
+ */
+static int ifx_spi_prepare_tx_buffer(struct ifx_spi_device *ifx_dev)
+{
+ int temp_count;
+ int queue_length;
+ int tx_count;
+ unsigned char *tx_buffer;
+
+ tx_buffer = ifx_dev->tx_buffer;
+ memset(tx_buffer, 0, IFX_SPI_TRANSFER_SIZE);
+
+ /* make room for required SPI header */
+ tx_buffer += IFX_SPI_HEADER_OVERHEAD;
+ tx_count = IFX_SPI_HEADER_OVERHEAD;
+
+ /* clear to signal no more data if this turns out to be the
+ * last buffer sent in a sequence */
+ ifx_dev->spi_more = 0;
+
+ /* if modem cts is set, just send empty buffer */
+ if (!ifx_dev->spi_slave_cts) {
+ /* see if there's tx data */
+ queue_length = kfifo_len(&ifx_dev->tx_fifo);
+ if (queue_length != 0) {
+ /* data to mux -- see if there's room for it */
+ temp_count = min(queue_length, IFX_SPI_PAYLOAD_SIZE);
+ temp_count = kfifo_out_locked(&ifx_dev->tx_fifo,
+ tx_buffer, temp_count,
+ &ifx_dev->fifo_lock);
+
+ /* update buffer pointer and data count in message */
+ tx_buffer += temp_count;
+ tx_count += temp_count;
+ if (temp_count == queue_length)
+ /* poke port to get more data */
+ ifx_spi_wakeup_serial(ifx_dev);
+ else /* more data in port, use next SPI message */
+ ifx_dev->spi_more = 1;
+ }
+ }
+ /* have data and info for header -- set up SPI header in buffer */
+ /* spi header needs payload size, not entire buffer size */
+ ifx_spi_setup_spi_header(ifx_dev->tx_buffer,
+ tx_count-IFX_SPI_HEADER_OVERHEAD,
+ ifx_dev->spi_more);
+ /* swap actual data in the buffer */
+ swap_buf((u16 *)(ifx_dev->tx_buffer), tx_count,
+ &ifx_dev->tx_buffer[IFX_SPI_TRANSFER_SIZE]);
+ return tx_count;
+}
+
+/**
+ * ifx_spi_write - line discipline write
+ * @tty: our tty device
+ * @buf: pointer to buffer to write (kernel space)
+ * @count: size of buffer
+ *
+ * Write the characters we have been given into the FIFO. If the device
+ * is not active then activate it, when the SRDY line is asserted back
+ * this will commence I/O
+ */
+static int ifx_spi_write(struct tty_struct *tty, const unsigned char *buf,
+ int count)
+{
+ struct ifx_spi_device *ifx_dev = tty->driver_data;
+ unsigned char *tmp_buf = (unsigned char *)buf;
+ int tx_count = kfifo_in_locked(&ifx_dev->tx_fifo, tmp_buf, count,
+ &ifx_dev->fifo_lock);
+ mrdy_assert(ifx_dev);
+ return tx_count;
+}
+
+/**
+ * ifx_spi_chars_in_buffer - line discipline helper
+ * @tty: our tty device
+ *
+ * Report how much data we can accept before we drop bytes. As we use
+ * a simple FIFO this is nice and easy.
+ */
+static int ifx_spi_write_room(struct tty_struct *tty)
+{
+ struct ifx_spi_device *ifx_dev = tty->driver_data;
+ return IFX_SPI_FIFO_SIZE - kfifo_len(&ifx_dev->tx_fifo);
+}
+
+/**
+ * ifx_spi_chars_in_buffer - line discipline helper
+ * @tty: our tty device
+ *
+ * Report how many characters we have buffered. In our case this is the
+ * number of bytes sitting in our transmit FIFO.
+ */
+static int ifx_spi_chars_in_buffer(struct tty_struct *tty)
+{
+ struct ifx_spi_device *ifx_dev = tty->driver_data;
+ return kfifo_len(&ifx_dev->tx_fifo);
+}
+
+/**
+ * ifx_port_hangup
+ * @port: our tty port
+ *
+ * tty port hang up. Called when tty_hangup processing is invoked either
+ * by loss of carrier, or by software (eg vhangup). Serialized against
+ * activate/shutdown by the tty layer.
+ */
+static void ifx_spi_hangup(struct tty_struct *tty)
+{
+ struct ifx_spi_device *ifx_dev = tty->driver_data;
+ tty_port_hangup(&ifx_dev->tty_port);
+}
+
+/**
+ * ifx_port_activate
+ * @port: our tty port
+ *
+ * tty port activate method - called for first open. Serialized
+ * with hangup and shutdown by the tty layer.
+ */
+static int ifx_port_activate(struct tty_port *port, struct tty_struct *tty)
+{
+ struct ifx_spi_device *ifx_dev =
+ container_of(port, struct ifx_spi_device, tty_port);
+
+ /* clear any old data; can't do this in 'close' */
+ kfifo_reset(&ifx_dev->tx_fifo);
+
+ /* put port data into this tty */
+ tty->driver_data = ifx_dev;
+
+ /* allows flip string push from int context */
+ tty->low_latency = 1;
+
+ return 0;
+}
+
+/**
+ * ifx_port_shutdown
+ * @port: our tty port
+ *
+ * tty port shutdown method - called for last port close. Serialized
+ * with hangup and activate by the tty layer.
+ */
+static void ifx_port_shutdown(struct tty_port *port)
+{
+ struct ifx_spi_device *ifx_dev =
+ container_of(port, struct ifx_spi_device, tty_port);
+
+ mrdy_set_low(ifx_dev);
+ clear_bit(IFX_SPI_STATE_TIMER_PENDING, &ifx_dev->flags);
+ tasklet_kill(&ifx_dev->io_work_tasklet);
+}
+
+static const struct tty_port_operations ifx_tty_port_ops = {
+ .activate = ifx_port_activate,
+ .shutdown = ifx_port_shutdown,
+};
+
+static const struct tty_operations ifx_spi_serial_ops = {
+ .open = ifx_spi_open,
+ .close = ifx_spi_close,
+ .write = ifx_spi_write,
+ .hangup = ifx_spi_hangup,
+ .write_room = ifx_spi_write_room,
+ .chars_in_buffer = ifx_spi_chars_in_buffer,
+ .tiocmget = ifx_spi_tiocmget,
+ .tiocmset = ifx_spi_tiocmset,
+};
+
+/**
+ * ifx_spi_insert_fip_string - queue received data
+ * @ifx_ser: our SPI device
+ * @chars: buffer we have received
+ * @size: number of chars reeived
+ *
+ * Queue bytes to the tty assuming the tty side is currently open. If
+ * not the discard the data.
+ */
+static void ifx_spi_insert_flip_string(struct ifx_spi_device *ifx_dev,
+ unsigned char *chars, size_t size)
+{
+ struct tty_struct *tty = tty_port_tty_get(&ifx_dev->tty_port);
+ if (!tty)
+ return;
+ tty_insert_flip_string(tty, chars, size);
+ tty_flip_buffer_push(tty);
+ tty_kref_put(tty);
+}
+
+/**
+ * ifx_spi_complete - SPI transfer completed
+ * @ctx: our SPI device
+ *
+ * An SPI transfer has completed. Process any received data and kick off
+ * any further transmits we can commence.
+ */
+static void ifx_spi_complete(void *ctx)
+{
+ struct ifx_spi_device *ifx_dev = ctx;
+ struct tty_struct *tty;
+ struct tty_ldisc *ldisc = NULL;
+ int length;
+ int actual_length;
+ unsigned char more;
+ unsigned char cts;
+ int local_write_pending = 0;
+ int queue_length;
+ int srdy;
+ int decode_result;
+
+ mrdy_set_low(ifx_dev);
+
+ if (!ifx_dev->spi_msg.status) {
+ /* check header validity, get comm flags */
+ swap_buf((u16 *)ifx_dev->rx_buffer, IFX_SPI_HEADER_OVERHEAD,
+ &ifx_dev->rx_buffer[IFX_SPI_HEADER_OVERHEAD]);
+ decode_result = ifx_spi_decode_spi_header(ifx_dev->rx_buffer,
+ &length, &more, &cts);
+ if (decode_result == IFX_SPI_HEADER_0) {
+ dev_dbg(&ifx_dev->spi_dev->dev,
+ "ignore input: invalid header 0");
+ ifx_dev->spi_slave_cts = 0;
+ goto complete_exit;
+ } else if (decode_result == IFX_SPI_HEADER_F) {
+ dev_dbg(&ifx_dev->spi_dev->dev,
+ "ignore input: invalid header F");
+ goto complete_exit;
+ }
+
+ ifx_dev->spi_slave_cts = cts;
+
+ actual_length = min((unsigned int)length,
+ ifx_dev->spi_msg.actual_length);
+ swap_buf((u16 *)(ifx_dev->rx_buffer + IFX_SPI_HEADER_OVERHEAD),
+ actual_length,
+ &ifx_dev->rx_buffer[IFX_SPI_TRANSFER_SIZE]);
+ ifx_spi_insert_flip_string(
+ ifx_dev,
+ ifx_dev->rx_buffer + IFX_SPI_HEADER_OVERHEAD,
+ (size_t)actual_length);
+ } else {
+ dev_dbg(&ifx_dev->spi_dev->dev, "SPI transfer error %d",
+ ifx_dev->spi_msg.status);
+ }
+
+complete_exit:
+ if (ifx_dev->write_pending) {
+ ifx_dev->write_pending = 0;
+ local_write_pending = 1;
+ }
+
+ clear_bit(IFX_SPI_STATE_IO_IN_PROGRESS, &(ifx_dev->flags));
+
+ queue_length = kfifo_len(&ifx_dev->tx_fifo);
+ srdy = gpio_get_value(ifx_dev->gpio.srdy);
+ if (!srdy)
+ ifx_spi_power_state_clear(ifx_dev, IFX_SPI_POWER_SRDY);
+
+ /* schedule output if there is more to do */
+ if (test_and_clear_bit(IFX_SPI_STATE_IO_READY, &ifx_dev->flags))
+ tasklet_schedule(&ifx_dev->io_work_tasklet);
+ else {
+ if (more || ifx_dev->spi_more || queue_length > 0 ||
+ local_write_pending) {
+ if (ifx_dev->spi_slave_cts) {
+ if (more)
+ mrdy_assert(ifx_dev);
+ } else
+ mrdy_assert(ifx_dev);
+ } else {
+ /*
+ * poke line discipline driver if any for more data
+ * may or may not get more data to write
+ * for now, say not busy
+ */
+ ifx_spi_power_state_clear(ifx_dev,
+ IFX_SPI_POWER_DATA_PENDING);
+ tty = tty_port_tty_get(&ifx_dev->tty_port);
+ if (tty) {
+ ldisc = tty_ldisc_ref(tty);
+ if (ldisc) {
+ ldisc->ops->write_wakeup(tty);
+ tty_ldisc_deref(ldisc);
+ }
+ tty_kref_put(tty);
+ }
+ }
+ }
+}
+
+/**
+ * ifx_spio_io - I/O tasklet
+ * @data: our SPI device
+ *
+ * Queue data for transmission if possible and then kick off the
+ * transfer.
+ */
+static void ifx_spi_io(unsigned long data)
+{
+ int retval;
+ struct ifx_spi_device *ifx_dev = (struct ifx_spi_device *) data;
+
+ if (!test_and_set_bit(IFX_SPI_STATE_IO_IN_PROGRESS, &ifx_dev->flags)) {
+ if (ifx_dev->gpio.unack_srdy_int_nb > 0)
+ ifx_dev->gpio.unack_srdy_int_nb--;
+
+ ifx_spi_prepare_tx_buffer(ifx_dev);
+
+ spi_message_init(&ifx_dev->spi_msg);
+ INIT_LIST_HEAD(&ifx_dev->spi_msg.queue);
+
+ ifx_dev->spi_msg.context = ifx_dev;
+ ifx_dev->spi_msg.complete = ifx_spi_complete;
+
+ /* set up our spi transfer */
+ /* note len is BYTES, not transfers */
+ ifx_dev->spi_xfer.len = IFX_SPI_TRANSFER_SIZE;
+ ifx_dev->spi_xfer.cs_change = 0;
+ ifx_dev->spi_xfer.speed_hz = 12500000;
+ /* ifx_dev->spi_xfer.speed_hz = 390625; */
+ ifx_dev->spi_xfer.bits_per_word = spi_b16 ? 16 : 8;
+
+ ifx_dev->spi_xfer.tx_buf = ifx_dev->tx_buffer;
+ ifx_dev->spi_xfer.rx_buf = ifx_dev->rx_buffer;
+
+ /*
+ * setup dma pointers
+ */
+ if (ifx_dev->is_6160) {
+ ifx_dev->spi_msg.is_dma_mapped = 1;
+ ifx_dev->tx_dma = ifx_dev->tx_bus;
+ ifx_dev->rx_dma = ifx_dev->rx_bus;
+ ifx_dev->spi_xfer.tx_dma = ifx_dev->tx_dma;
+ ifx_dev->spi_xfer.rx_dma = ifx_dev->rx_dma;
+ } else {
+ ifx_dev->spi_msg.is_dma_mapped = 0;
+ ifx_dev->tx_dma = (dma_addr_t)0;
+ ifx_dev->rx_dma = (dma_addr_t)0;
+ ifx_dev->spi_xfer.tx_dma = (dma_addr_t)0;
+ ifx_dev->spi_xfer.rx_dma = (dma_addr_t)0;
+ }
+
+ spi_message_add_tail(&ifx_dev->spi_xfer, &ifx_dev->spi_msg);
+
+ /* Assert MRDY. This may have already been done by the write
+ * routine.
+ */
+ mrdy_assert(ifx_dev);
+
+ retval = spi_async(ifx_dev->spi_dev, &ifx_dev->spi_msg);
+ if (retval) {
+ clear_bit(IFX_SPI_STATE_IO_IN_PROGRESS,
+ &ifx_dev->flags);
+ tasklet_schedule(&ifx_dev->io_work_tasklet);
+ return;
+ }
+ } else
+ ifx_dev->write_pending = 1;
+}
+
+/**
+ * ifx_spi_free_port - free up the tty side
+ * @ifx_dev: IFX device going away
+ *
+ * Unregister and free up a port when the device goes away
+ */
+static void ifx_spi_free_port(struct ifx_spi_device *ifx_dev)
+{
+ if (ifx_dev->tty_dev)
+ tty_unregister_device(tty_drv, ifx_dev->minor);
+ kfifo_free(&ifx_dev->tx_fifo);
+}
+
+/**
+ * ifx_spi_create_port - create a new port
+ * @ifx_dev: our spi device
+ *
+ * Allocate and initialise the tty port that goes with this interface
+ * and add it to the tty layer so that it can be opened.
+ */
+static int ifx_spi_create_port(struct ifx_spi_device *ifx_dev)
+{
+ int ret = 0;
+ struct tty_port *pport = &ifx_dev->tty_port;
+
+ spin_lock_init(&ifx_dev->fifo_lock);
+ lockdep_set_class_and_subclass(&ifx_dev->fifo_lock,
+ &ifx_spi_key, 0);
+
+ if (kfifo_alloc(&ifx_dev->tx_fifo, IFX_SPI_FIFO_SIZE, GFP_KERNEL)) {
+ ret = -ENOMEM;
+ goto error_ret;
+ }
+
+ pport->ops = &ifx_tty_port_ops;
+ tty_port_init(pport);
+ ifx_dev->minor = IFX_SPI_TTY_ID;
+ ifx_dev->tty_dev = tty_register_device(tty_drv, ifx_dev->minor,
+ &ifx_dev->spi_dev->dev);
+ if (IS_ERR(ifx_dev->tty_dev)) {
+ dev_dbg(&ifx_dev->spi_dev->dev,
+ "%s: registering tty device failed", __func__);
+ ret = PTR_ERR(ifx_dev->tty_dev);
+ goto error_ret;
+ }
+ return 0;
+
+error_ret:
+ ifx_spi_free_port(ifx_dev);
+ return ret;
+}
+
+/**
+ * ifx_spi_handle_srdy - handle SRDY
+ * @ifx_dev: device asserting SRDY
+ *
+ * Check our device state and see what we need to kick off when SRDY
+ * is asserted. This usually means killing the timer and firing off the
+ * I/O processing.
+ */
+static void ifx_spi_handle_srdy(struct ifx_spi_device *ifx_dev)
+{
+ if (test_bit(IFX_SPI_STATE_TIMER_PENDING, &ifx_dev->flags)) {
+ del_timer_sync(&ifx_dev->spi_timer);
+ clear_bit(IFX_SPI_STATE_TIMER_PENDING, &ifx_dev->flags);
+ }
+
+ ifx_spi_power_state_set(ifx_dev, IFX_SPI_POWER_SRDY);
+
+ if (!test_bit(IFX_SPI_STATE_IO_IN_PROGRESS, &ifx_dev->flags))
+ tasklet_schedule(&ifx_dev->io_work_tasklet);
+ else
+ set_bit(IFX_SPI_STATE_IO_READY, &ifx_dev->flags);
+}
+
+/**
+ * ifx_spi_srdy_interrupt - SRDY asserted
+ * @irq: our IRQ number
+ * @dev: our ifx device
+ *
+ * The modem asserted SRDY. Handle the srdy event
+ */
+static irqreturn_t ifx_spi_srdy_interrupt(int irq, void *dev)
+{
+ struct ifx_spi_device *ifx_dev = dev;
+ ifx_dev->gpio.unack_srdy_int_nb++;
+ ifx_spi_handle_srdy(ifx_dev);
+ return IRQ_HANDLED;
+}
+
+/**
+ * ifx_spi_reset_interrupt - Modem has changed reset state
+ * @irq: interrupt number
+ * @dev: our device pointer
+ *
+ * The modem has either entered or left reset state. Check the GPIO
+ * line to see which.
+ *
+ * FIXME: review locking on MR_INPROGRESS versus
+ * parallel unsolicited reset/solicited reset
+ */
+static irqreturn_t ifx_spi_reset_interrupt(int irq, void *dev)
+{
+ struct ifx_spi_device *ifx_dev = dev;
+ int val = gpio_get_value(ifx_dev->gpio.reset_out);
+ int solreset = test_bit(MR_START, &ifx_dev->mdm_reset_state);
+
+ if (val == 0) {
+ /* entered reset */
+ set_bit(MR_INPROGRESS, &ifx_dev->mdm_reset_state);
+ if (!solreset) {
+ /* unsolicited reset */
+ ifx_spi_ttyhangup(ifx_dev);
+ }
+ } else {
+ /* exited reset */
+ clear_bit(MR_INPROGRESS, &ifx_dev->mdm_reset_state);
+ if (solreset) {
+ set_bit(MR_COMPLETE, &ifx_dev->mdm_reset_state);
+ wake_up(&ifx_dev->mdm_reset_wait);
+ }
+ }
+ return IRQ_HANDLED;
+}
+
+/**
+ * ifx_spi_free_device - free device
+ * @ifx_dev: device to free
+ *
+ * Free the IFX device
+ */
+static void ifx_spi_free_device(struct ifx_spi_device *ifx_dev)
+{
+ ifx_spi_free_port(ifx_dev);
+ dma_free_coherent(&ifx_dev->spi_dev->dev,
+ IFX_SPI_TRANSFER_SIZE,
+ ifx_dev->tx_buffer,
+ ifx_dev->tx_bus);
+ dma_free_coherent(&ifx_dev->spi_dev->dev,
+ IFX_SPI_TRANSFER_SIZE,
+ ifx_dev->rx_buffer,
+ ifx_dev->rx_bus);
+}
+
+/**
+ * ifx_spi_reset - reset modem
+ * @ifx_dev: modem to reset
+ *
+ * Perform a reset on the modem
+ */
+static int ifx_spi_reset(struct ifx_spi_device *ifx_dev)
+{
+ int ret;
+ /*
+ * set up modem power, reset
+ *
+ * delays are required on some platforms for the modem
+ * to reset properly
+ */
+ set_bit(MR_START, &ifx_dev->mdm_reset_state);
+ gpio_set_value(ifx_dev->gpio.po, 0);
+ gpio_set_value(ifx_dev->gpio.reset, 0);
+ msleep(25);
+ gpio_set_value(ifx_dev->gpio.reset, 1);
+ msleep(1);
+ gpio_set_value(ifx_dev->gpio.po, 1);
+ msleep(1);
+ gpio_set_value(ifx_dev->gpio.po, 0);
+ ret = wait_event_timeout(ifx_dev->mdm_reset_wait,
+ test_bit(MR_COMPLETE,
+ &ifx_dev->mdm_reset_state),
+ IFX_RESET_TIMEOUT);
+ if (!ret)
+ dev_warn(&ifx_dev->spi_dev->dev, "Modem reset timeout: (state:%lx)",
+ ifx_dev->mdm_reset_state);
+
+ ifx_dev->mdm_reset_state = 0;
+ return ret;
+}
+
+/**
+ * ifx_spi_spi_probe - probe callback
+ * @spi: our possible matching SPI device
+ *
+ * Probe for a 6x60 modem on SPI bus. Perform any needed device and
+ * GPIO setup.
+ *
+ * FIXME:
+ * - Support for multiple devices
+ * - Split out MID specific GPIO handling eventually
+ */
+
+static int ifx_spi_spi_probe(struct spi_device *spi)
+{
+ int ret;
+ int srdy;
+ struct ifx_modem_platform_data *pl_data = NULL;
+ struct ifx_spi_device *ifx_dev;
+
+ if (saved_ifx_dev) {
+ dev_dbg(&spi->dev, "ignoring subsequent detection");
+ return -ENODEV;
+ }
+
+ /* initialize structure to hold our device variables */
+ ifx_dev = kzalloc(sizeof(struct ifx_spi_device), GFP_KERNEL);
+ if (!ifx_dev) {
+ dev_err(&spi->dev, "spi device allocation failed");
+ return -ENOMEM;
+ }
+ saved_ifx_dev = ifx_dev;
+ ifx_dev->spi_dev = spi;
+ clear_bit(IFX_SPI_STATE_IO_IN_PROGRESS, &ifx_dev->flags);
+ spin_lock_init(&ifx_dev->write_lock);
+ spin_lock_init(&ifx_dev->power_lock);
+ ifx_dev->power_status = 0;
+ init_timer(&ifx_dev->spi_timer);
+ ifx_dev->spi_timer.function = ifx_spi_timeout;
+ ifx_dev->spi_timer.data = (unsigned long)ifx_dev;
+ ifx_dev->is_6160 = pl_data->is_6160;
+
+ /* ensure SPI protocol flags are initialized to enable transfer */
+ ifx_dev->spi_more = 0;
+ ifx_dev->spi_slave_cts = 0;
+
+ /*initialize transfer and dma buffers */
+ ifx_dev->tx_buffer = dma_alloc_coherent(&ifx_dev->spi_dev->dev,
+ IFX_SPI_TRANSFER_SIZE,
+ &ifx_dev->tx_bus,
+ GFP_KERNEL);
+ if (!ifx_dev->tx_buffer) {
+ dev_err(&spi->dev, "DMA-TX buffer allocation failed");
+ ret = -ENOMEM;
+ goto error_ret;
+ }
+ ifx_dev->rx_buffer = dma_alloc_coherent(&ifx_dev->spi_dev->dev,
+ IFX_SPI_TRANSFER_SIZE,
+ &ifx_dev->rx_bus,
+ GFP_KERNEL);
+ if (!ifx_dev->rx_buffer) {
+ dev_err(&spi->dev, "DMA-RX buffer allocation failed");
+ ret = -ENOMEM;
+ goto error_ret;
+ }
+
+ /* initialize waitq for modem reset */
+ init_waitqueue_head(&ifx_dev->mdm_reset_wait);
+
+ spi_set_drvdata(spi, ifx_dev);
+ tasklet_init(&ifx_dev->io_work_tasklet, ifx_spi_io,
+ (unsigned long)ifx_dev);
+
+ set_bit(IFX_SPI_STATE_PRESENT, &ifx_dev->flags);
+
+ /* create our tty port */
+ ret = ifx_spi_create_port(ifx_dev);
+ if (ret != 0) {
+ dev_err(&spi->dev, "create default tty port failed");
+ goto error_ret;
+ }
+
+ pl_data = (struct ifx_modem_platform_data *)spi->dev.platform_data;
+ if (pl_data) {
+ ifx_dev->gpio.reset = pl_data->rst_pmu;
+ ifx_dev->gpio.po = pl_data->pwr_on;
+ ifx_dev->gpio.mrdy = pl_data->mrdy;
+ ifx_dev->gpio.srdy = pl_data->srdy;
+ ifx_dev->gpio.reset_out = pl_data->rst_out;
+ } else {
+ dev_err(&spi->dev, "missing platform data!");
+ ret = -ENODEV;
+ goto error_ret;
+ }
+
+ dev_info(&spi->dev, "gpios %d, %d, %d, %d, %d",
+ ifx_dev->gpio.reset, ifx_dev->gpio.po, ifx_dev->gpio.mrdy,
+ ifx_dev->gpio.srdy, ifx_dev->gpio.reset_out);
+
+ /* Configure gpios */
+ ret = gpio_request(ifx_dev->gpio.reset, "ifxModem");
+ if (ret < 0) {
+ dev_err(&spi->dev, "Unable to allocate GPIO%d (RESET)",
+ ifx_dev->gpio.reset);
+ goto error_ret;
+ }
+ ret += gpio_direction_output(ifx_dev->gpio.reset, 0);
+ ret += gpio_export(ifx_dev->gpio.reset, 1);
+ if (ret) {
+ dev_err(&spi->dev, "Unable to configure GPIO%d (RESET)",
+ ifx_dev->gpio.reset);
+ ret = -EBUSY;
+ goto error_ret2;
+ }
+
+ ret = gpio_request(ifx_dev->gpio.po, "ifxModem");
+ ret += gpio_direction_output(ifx_dev->gpio.po, 0);
+ ret += gpio_export(ifx_dev->gpio.po, 1);
+ if (ret) {
+ dev_err(&spi->dev, "Unable to configure GPIO%d (ON)",
+ ifx_dev->gpio.po);
+ ret = -EBUSY;
+ goto error_ret3;
+ }
+
+ ret = gpio_request(ifx_dev->gpio.mrdy, "ifxModem");
+ if (ret < 0) {
+ dev_err(&spi->dev, "Unable to allocate GPIO%d (MRDY)",
+ ifx_dev->gpio.mrdy);
+ goto error_ret3;
+ }
+ ret += gpio_export(ifx_dev->gpio.mrdy, 1);
+ ret += gpio_direction_output(ifx_dev->gpio.mrdy, 0);
+ if (ret) {
+ dev_err(&spi->dev, "Unable to configure GPIO%d (MRDY)",
+ ifx_dev->gpio.mrdy);
+ ret = -EBUSY;
+ goto error_ret4;
+ }
+
+ ret = gpio_request(ifx_dev->gpio.srdy, "ifxModem");
+ if (ret < 0) {
+ dev_err(&spi->dev, "Unable to allocate GPIO%d (SRDY)",
+ ifx_dev->gpio.srdy);
+ ret = -EBUSY;
+ goto error_ret4;
+ }
+ ret += gpio_export(ifx_dev->gpio.srdy, 1);
+ ret += gpio_direction_input(ifx_dev->gpio.srdy);
+ if (ret) {
+ dev_err(&spi->dev, "Unable to configure GPIO%d (SRDY)",
+ ifx_dev->gpio.srdy);
+ ret = -EBUSY;
+ goto error_ret5;
+ }
+
+ ret = gpio_request(ifx_dev->gpio.reset_out, "ifxModem");
+ if (ret < 0) {
+ dev_err(&spi->dev, "Unable to allocate GPIO%d (RESET_OUT)",
+ ifx_dev->gpio.reset_out);
+ goto error_ret5;
+ }
+ ret += gpio_export(ifx_dev->gpio.reset_out, 1);
+ ret += gpio_direction_input(ifx_dev->gpio.reset_out);
+ if (ret) {
+ dev_err(&spi->dev, "Unable to configure GPIO%d (RESET_OUT)",
+ ifx_dev->gpio.reset_out);
+ ret = -EBUSY;
+ goto error_ret6;
+ }
+
+ ret = request_irq(gpio_to_irq(ifx_dev->gpio.reset_out),
+ ifx_spi_reset_interrupt,
+ IRQF_TRIGGER_RISING|IRQF_TRIGGER_FALLING, DRVNAME,
+ (void *)ifx_dev);
+ if (ret) {
+ dev_err(&spi->dev, "Unable to get irq %x\n",
+ gpio_to_irq(ifx_dev->gpio.reset_out));
+ goto error_ret6;
+ }
+
+ ret = ifx_spi_reset(ifx_dev);
+
+ ret = request_irq(gpio_to_irq(ifx_dev->gpio.srdy),
+ ifx_spi_srdy_interrupt,
+ IRQF_TRIGGER_RISING, DRVNAME,
+ (void *)ifx_dev);
+ if (ret) {
+ dev_err(&spi->dev, "Unable to get irq %x",
+ gpio_to_irq(ifx_dev->gpio.srdy));
+ goto error_ret7;
+ }
+
+ /* set pm runtime power state and register with power system */
+ pm_runtime_set_active(&spi->dev);
+ pm_runtime_enable(&spi->dev);
+
+ /* handle case that modem is already signaling SRDY */
+ /* no outgoing tty open at this point, this just satisfies the
+ * modem's read and should reset communication properly
+ */
+ srdy = gpio_get_value(ifx_dev->gpio.srdy);
+
+ if (srdy) {
+ mrdy_assert(ifx_dev);
+ ifx_spi_handle_srdy(ifx_dev);
+ } else
+ mrdy_set_low(ifx_dev);
+ return 0;
+
+error_ret7:
+ free_irq(gpio_to_irq(ifx_dev->gpio.reset_out), (void *)ifx_dev);
+error_ret6:
+ gpio_free(ifx_dev->gpio.srdy);
+error_ret5:
+ gpio_free(ifx_dev->gpio.mrdy);
+error_ret4:
+ gpio_free(ifx_dev->gpio.reset);
+error_ret3:
+ gpio_free(ifx_dev->gpio.po);
+error_ret2:
+ gpio_free(ifx_dev->gpio.reset_out);
+error_ret:
+ ifx_spi_free_device(ifx_dev);
+ saved_ifx_dev = NULL;
+ return ret;
+}
+
+/**
+ * ifx_spi_spi_remove - SPI device was removed
+ * @spi: SPI device
+ *
+ * FIXME: We should be shutting the device down here not in
+ * the module unload path.
+ */
+
+static int ifx_spi_spi_remove(struct spi_device *spi)
+{
+ struct ifx_spi_device *ifx_dev = spi_get_drvdata(spi);
+ /* stop activity */
+ tasklet_kill(&ifx_dev->io_work_tasklet);
+ /* free irq */
+ free_irq(gpio_to_irq(ifx_dev->gpio.reset_out), (void *)ifx_dev);
+ free_irq(gpio_to_irq(ifx_dev->gpio.srdy), (void *)ifx_dev);
+
+ gpio_free(ifx_dev->gpio.srdy);
+ gpio_free(ifx_dev->gpio.mrdy);
+ gpio_free(ifx_dev->gpio.reset);
+ gpio_free(ifx_dev->gpio.po);
+ gpio_free(ifx_dev->gpio.reset_out);
+
+ /* free allocations */
+ ifx_spi_free_device(ifx_dev);
+
+ saved_ifx_dev = NULL;
+ return 0;
+}
+
+/**
+ * ifx_spi_spi_shutdown - called on SPI shutdown
+ * @spi: SPI device
+ *
+ * No action needs to be taken here
+ */
+
+static void ifx_spi_spi_shutdown(struct spi_device *spi)
+{
+}
+
+/*
+ * various suspends and resumes have nothing to do
+ * no hardware to save state for
+ */
+
+/**
+ * ifx_spi_spi_suspend - suspend SPI on system suspend
+ * @dev: device being suspended
+ *
+ * Suspend the SPI side. No action needed on Intel MID platforms, may
+ * need extending for other systems.
+ */
+static int ifx_spi_spi_suspend(struct spi_device *spi, pm_message_t msg)
+{
+ return 0;
+}
+
+/**
+ * ifx_spi_spi_resume - resume SPI side on system resume
+ * @dev: device being suspended
+ *
+ * Suspend the SPI side. No action needed on Intel MID platforms, may
+ * need extending for other systems.
+ */
+static int ifx_spi_spi_resume(struct spi_device *spi)
+{
+ return 0;
+}
+
+/**
+ * ifx_spi_pm_suspend - suspend modem on system suspend
+ * @dev: device being suspended
+ *
+ * Suspend the modem. No action needed on Intel MID platforms, may
+ * need extending for other systems.
+ */
+static int ifx_spi_pm_suspend(struct device *dev)
+{
+ return 0;
+}
+
+/**
+ * ifx_spi_pm_resume - resume modem on system resume
+ * @dev: device being suspended
+ *
+ * Allow the modem to resume. No action needed.
+ *
+ * FIXME: do we need to reset anything here ?
+ */
+static int ifx_spi_pm_resume(struct device *dev)
+{
+ return 0;
+}
+
+/**
+ * ifx_spi_pm_runtime_resume - suspend modem
+ * @dev: device being suspended
+ *
+ * Allow the modem to resume. No action needed.
+ */
+static int ifx_spi_pm_runtime_resume(struct device *dev)
+{
+ return 0;
+}
+
+/**
+ * ifx_spi_pm_runtime_suspend - suspend modem
+ * @dev: device being suspended
+ *
+ * Allow the modem to suspend and thus suspend to continue up the
+ * device tree.
+ */
+static int ifx_spi_pm_runtime_suspend(struct device *dev)
+{
+ return 0;
+}
+
+/**
+ * ifx_spi_pm_runtime_idle - check if modem idle
+ * @dev: our device
+ *
+ * Check conditions and queue runtime suspend if idle.
+ */
+static int ifx_spi_pm_runtime_idle(struct device *dev)
+{
+ struct spi_device *spi = to_spi_device(dev);
+ struct ifx_spi_device *ifx_dev = spi_get_drvdata(spi);
+
+ if (!ifx_dev->power_status)
+ pm_runtime_suspend(dev);
+
+ return 0;
+}
+
+static const struct dev_pm_ops ifx_spi_pm = {
+ .resume = ifx_spi_pm_resume,
+ .suspend = ifx_spi_pm_suspend,
+ .runtime_resume = ifx_spi_pm_runtime_resume,
+ .runtime_suspend = ifx_spi_pm_runtime_suspend,
+ .runtime_idle = ifx_spi_pm_runtime_idle
+};
+
+static const struct spi_device_id ifx_id_table[] = {
+ {"ifx6160", 0},
+ {"ifx6260", 0},
+ { }
+};
+MODULE_DEVICE_TABLE(spi, ifx_id_table);
+
+/* spi operations */
+static const struct spi_driver ifx_spi_driver_6160 = {
+ .driver = {
+ .name = "ifx6160",
+ .bus = &spi_bus_type,
+ .pm = &ifx_spi_pm,
+ .owner = THIS_MODULE},
+ .probe = ifx_spi_spi_probe,
+ .shutdown = ifx_spi_spi_shutdown,
+ .remove = __devexit_p(ifx_spi_spi_remove),
+ .suspend = ifx_spi_spi_suspend,
+ .resume = ifx_spi_spi_resume,
+ .id_table = ifx_id_table
+};
+
+/**
+ * ifx_spi_exit - module exit
+ *
+ * Unload the module.
+ */
+
+static void __exit ifx_spi_exit(void)
+{
+ /* unregister */
+ tty_unregister_driver(tty_drv);
+ spi_unregister_driver((void *)&ifx_spi_driver_6160);
+}
+
+/**
+ * ifx_spi_init - module entry point
+ *
+ * Initialise the SPI and tty interfaces for the IFX SPI driver
+ * We need to initialize upper-edge spi driver after the tty
+ * driver because otherwise the spi probe will race
+ */
+
+static int __init ifx_spi_init(void)
+{
+ int result;
+
+ tty_drv = alloc_tty_driver(1);
+ if (!tty_drv) {
+ pr_err("%s: alloc_tty_driver failed", DRVNAME);
+ return -ENOMEM;
+ }
+
+ tty_drv->magic = TTY_DRIVER_MAGIC;
+ tty_drv->owner = THIS_MODULE;
+ tty_drv->driver_name = DRVNAME;
+ tty_drv->name = TTYNAME;
+ tty_drv->minor_start = IFX_SPI_TTY_ID;
+ tty_drv->num = 1;
+ tty_drv->type = TTY_DRIVER_TYPE_SERIAL;
+ tty_drv->subtype = SERIAL_TYPE_NORMAL;
+ tty_drv->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
+ tty_drv->init_termios = tty_std_termios;
+
+ tty_set_operations(tty_drv, &ifx_spi_serial_ops);
+
+ result = tty_register_driver(tty_drv);
+ if (result) {
+ pr_err("%s: tty_register_driver failed(%d)",
+ DRVNAME, result);
+ put_tty_driver(tty_drv);
+ return result;
+ }
+
+ result = spi_register_driver((void *)&ifx_spi_driver_6160);
+ if (result) {
+ pr_err("%s: spi_register_driver failed(%d)",
+ DRVNAME, result);
+ tty_unregister_driver(tty_drv);
+ }
+ return result;
+}
+
+module_init(ifx_spi_init);
+module_exit(ifx_spi_exit);
+
+MODULE_AUTHOR("Intel");
+MODULE_DESCRIPTION("IFX6x60 spi driver");
+MODULE_LICENSE("GPL");
+MODULE_INFO(Version, "0.1-IFX6x60");
diff --git a/drivers/serial/ifx6x60.h b/drivers/serial/ifx6x60.h
new file mode 100644
index 00000000000..deb7b8d977d
--- /dev/null
+++ b/drivers/serial/ifx6x60.h
@@ -0,0 +1,129 @@
+/****************************************************************************
+ *
+ * Driver for the IFX spi modem.
+ *
+ * Copyright (C) 2009, 2010 Intel Corp
+ * Jim Stanley <jim.stanley@intel.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
+ * USA
+ *
+ *
+ *
+ *****************************************************************************/
+#ifndef _IFX6X60_H
+#define _IFX6X60_H
+
+#define DRVNAME "ifx6x60"
+#define TTYNAME "ttyIFX"
+
+/* #define IFX_THROTTLE_CODE */
+
+#define IFX_SPI_MAX_MINORS 1
+#define IFX_SPI_TRANSFER_SIZE 2048
+#define IFX_SPI_FIFO_SIZE 4096
+
+#define IFX_SPI_HEADER_OVERHEAD 4
+#define IFX_RESET_TIMEOUT msecs_to_jiffies(50)
+
+/* device flags bitfield definitions */
+#define IFX_SPI_STATE_PRESENT 0
+#define IFX_SPI_STATE_IO_IN_PROGRESS 1
+#define IFX_SPI_STATE_IO_READY 2
+#define IFX_SPI_STATE_TIMER_PENDING 3
+
+/* flow control bitfields */
+#define IFX_SPI_DCD 0
+#define IFX_SPI_CTS 1
+#define IFX_SPI_DSR 2
+#define IFX_SPI_RI 3
+#define IFX_SPI_DTR 4
+#define IFX_SPI_RTS 5
+#define IFX_SPI_TX_FC 6
+#define IFX_SPI_RX_FC 7
+#define IFX_SPI_UPDATE 8
+
+#define IFX_SPI_PAYLOAD_SIZE (IFX_SPI_TRANSFER_SIZE - \
+ IFX_SPI_HEADER_OVERHEAD)
+
+#define IFX_SPI_IRQ_TYPE DETECT_EDGE_RISING
+#define IFX_SPI_GPIO_TARGET 0
+#define IFX_SPI_GPIO0 0x105
+
+#define IFX_SPI_STATUS_TIMEOUT (2000*HZ)
+
+/* values for bits in power status byte */
+#define IFX_SPI_POWER_DATA_PENDING 1
+#define IFX_SPI_POWER_SRDY 2
+
+struct ifx_spi_device {
+ /* Our SPI device */
+ struct spi_device *spi_dev;
+
+ /* Port specific data */
+ struct kfifo tx_fifo;
+ spinlock_t fifo_lock;
+ unsigned long signal_state;
+
+ /* TTY Layer logic */
+ struct tty_port tty_port;
+ struct device *tty_dev;
+ int minor;
+
+ /* Low level I/O work */
+ struct tasklet_struct io_work_tasklet;
+ unsigned long flags;
+ dma_addr_t rx_dma;
+ dma_addr_t tx_dma;
+
+ int is_6160; /* Modem type */
+
+ spinlock_t write_lock;
+ int write_pending;
+ spinlock_t power_lock;
+ unsigned char power_status;
+
+ unsigned char *rx_buffer;
+ unsigned char *tx_buffer;
+ dma_addr_t rx_bus;
+ dma_addr_t tx_bus;
+ unsigned char spi_more;
+ unsigned char spi_slave_cts;
+
+ struct timer_list spi_timer;
+
+ struct spi_message spi_msg;
+ struct spi_transfer spi_xfer;
+
+ struct {
+ /* gpio lines */
+ unsigned short srdy; /* slave-ready gpio */
+ unsigned short mrdy; /* master-ready gpio */
+ unsigned short reset; /* modem-reset gpio */
+ unsigned short po; /* modem-on gpio */
+ unsigned short reset_out; /* modem-in-reset gpio */
+ /* state/stats */
+ int unack_srdy_int_nb;
+ } gpio;
+
+ /* modem reset */
+ unsigned long mdm_reset_state;
+#define MR_START 0
+#define MR_INPROGRESS 1
+#define MR_COMPLETE 2
+ wait_queue_head_t mdm_reset_wait;
+};
+
+#endif /* _IFX6X60_H */
diff --git a/drivers/serial/kgdboc.c b/drivers/serial/kgdboc.c
index 3374618300a..25a8bc565f4 100644
--- a/drivers/serial/kgdboc.c
+++ b/drivers/serial/kgdboc.c
@@ -90,7 +90,8 @@ static DECLARE_WORK(kgdboc_restore_input_work, kgdboc_restore_input_helper);
static void kgdboc_restore_input(void)
{
- schedule_work(&kgdboc_restore_input_work);
+ if (likely(system_state == SYSTEM_RUNNING))
+ schedule_work(&kgdboc_restore_input_work);
}
static int kgdboc_register_kbd(char **cptr)
diff --git a/drivers/serial/mfd.c b/drivers/serial/mfd.c
index 5fc699e929d..d40010a22ec 100644
--- a/drivers/serial/mfd.c
+++ b/drivers/serial/mfd.c
@@ -900,8 +900,7 @@ serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
unsigned char cval, fcr = 0;
unsigned long flags;
unsigned int baud, quot;
- u32 mul = 0x3600;
- u32 ps = 0x10;
+ u32 ps, mul;
switch (termios->c_cflag & CSIZE) {
case CS5:
@@ -943,31 +942,24 @@ serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
quot = 1;
+ ps = 0x10;
+ mul = 0x3600;
switch (baud) {
case 3500000:
mul = 0x3345;
ps = 0xC;
break;
- case 3000000:
- mul = 0x2EE0;
- break;
- case 2500000:
- mul = 0x2710;
- break;
- case 2000000:
- mul = 0x1F40;
- break;
case 1843200:
mul = 0x2400;
break;
+ case 3000000:
+ case 2500000:
+ case 2000000:
case 1500000:
- mul = 0x1770;
- break;
case 1000000:
- mul = 0xFA0;
- break;
case 500000:
- mul = 0x7D0;
+ /* mul/ps/quot = 0x9C4/0x10/0x1 will make a 500000 bps */
+ mul = baud / 500000 * 0x9C4;
break;
default:
/* Use uart_get_divisor to get quot for other baud rates */
diff --git a/drivers/serial/mpc52xx_uart.c b/drivers/serial/mpc52xx_uart.c
index c4399e23565..126ec7f568e 100644
--- a/drivers/serial/mpc52xx_uart.c
+++ b/drivers/serial/mpc52xx_uart.c
@@ -838,7 +838,11 @@ mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
static const char *
mpc52xx_uart_type(struct uart_port *port)
{
- return port->type == PORT_MPC52xx ? "MPC52xx PSC" : NULL;
+ /*
+ * We keep using PORT_MPC52xx for historic reasons although it applies
+ * for MPC512x, too, but print "MPC5xxx" to not irritate users
+ */
+ return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL;
}
static void
diff --git a/drivers/serial/msm_serial.c b/drivers/serial/msm_serial.c
index f8c816e7725..8e43a7b69e6 100644
--- a/drivers/serial/msm_serial.c
+++ b/drivers/serial/msm_serial.c
@@ -686,7 +686,7 @@ static int __init msm_serial_probe(struct platform_device *pdev)
msm_port = UART_TO_MSM(port);
msm_port->clk = clk_get(&pdev->dev, "uart_clk");
- if (unlikely(IS_ERR(msm_port->clk)))
+ if (IS_ERR(msm_port->clk))
return PTR_ERR(msm_port->clk);
port->uartclk = clk_get_rate(msm_port->clk);
printk(KERN_INFO "uartclk = %d\n", port->uartclk);
diff --git a/drivers/serial/of_serial.c b/drivers/serial/of_serial.c
index 17849dcb9ad..5c7abe4c94d 100644
--- a/drivers/serial/of_serial.c
+++ b/drivers/serial/of_serial.c
@@ -15,6 +15,7 @@
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#include <linux/of_address.h>
+#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/nwpserial.h>
diff --git a/drivers/serial/omap-serial.c b/drivers/serial/omap-serial.c
index 14365f72b66..7f2f0105878 100644
--- a/drivers/serial/omap-serial.c
+++ b/drivers/serial/omap-serial.c
@@ -570,7 +570,7 @@ serial_omap_configure_xonxoff
unsigned char efr = 0;
up->lcr = serial_in(up, UART_LCR);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
up->efr = serial_in(up, UART_EFR);
serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
@@ -598,7 +598,7 @@ serial_omap_configure_xonxoff
efr |= OMAP_UART_SW_RX;
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
- serial_out(up, UART_LCR, UART_LCR_DLAB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
up->mcr = serial_in(up, UART_MCR);
@@ -612,14 +612,14 @@ serial_omap_configure_xonxoff
up->mcr |= UART_MCR_XONANY;
serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
/* Enable special char function UARTi.EFR_REG[5] and
* load the new software flow control mode IXON or IXOFF
* and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
*/
serial_out(up, UART_EFR, efr | UART_EFR_SCD);
- serial_out(up, UART_LCR, UART_LCR_DLAB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
serial_out(up, UART_LCR, up->lcr);
@@ -724,22 +724,22 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
* baud clock is not running
* DLL_REG and DLH_REG set to 0.
*/
- serial_out(up, UART_LCR, UART_LCR_DLAB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial_out(up, UART_DLL, 0);
serial_out(up, UART_DLM, 0);
serial_out(up, UART_LCR, 0);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
up->efr = serial_in(up, UART_EFR);
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
- serial_out(up, UART_LCR, UART_LCR_DLAB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
up->mcr = serial_in(up, UART_MCR);
serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
/* FIFO ENABLE, DMA MODE */
serial_out(up, UART_FCR, up->fcr);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
if (up->use_dma) {
serial_out(up, UART_TI752_TLR, 0);
@@ -748,52 +748,52 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
}
serial_out(up, UART_EFR, up->efr);
- serial_out(up, UART_LCR, UART_LCR_DLAB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial_out(up, UART_MCR, up->mcr);
/* Protocol, Baud Rate, and Interrupt Settings */
- serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_DISABLE);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
up->efr = serial_in(up, UART_EFR);
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
serial_out(up, UART_LCR, 0);
serial_out(up, UART_IER, 0);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
serial_out(up, UART_LCR, 0);
serial_out(up, UART_IER, up->ier);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_EFR, up->efr);
serial_out(up, UART_LCR, cval);
if (baud > 230400 && baud != 3000000)
- serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_MODE13X);
+ serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_13X_MODE);
else
- serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_MODE16X);
+ serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
/* Hardware Flow Control Configuration */
if (termios->c_cflag & CRTSCTS) {
efr |= (UART_EFR_CTS | UART_EFR_RTS);
- serial_out(up, UART_LCR, UART_LCR_DLAB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
up->mcr = serial_in(up, UART_MCR);
serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
up->efr = serial_in(up, UART_EFR);
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
- serial_out(up, UART_LCR, UART_LCR_DLAB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
serial_out(up, UART_LCR, cval);
}
@@ -815,13 +815,13 @@ serial_omap_pm(struct uart_port *port, unsigned int state,
unsigned char efr;
dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->pdev->id);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
efr = serial_in(up, UART_EFR);
serial_out(up, UART_EFR, efr | UART_EFR_ECB);
serial_out(up, UART_LCR, 0);
serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
- serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_EFR, efr);
serial_out(up, UART_LCR, 0);
/* Enable module level wake up */
@@ -866,12 +866,6 @@ serial_omap_type(struct uart_port *port)
return up->name;
}
-#ifdef CONFIG_SERIAL_OMAP_CONSOLE
-
-static struct uart_omap_port *serial_omap_console_ports[4];
-
-static struct uart_driver serial_omap_reg;
-
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
static inline void wait_for_xmitr(struct uart_omap_port *up)
@@ -905,6 +899,34 @@ static inline void wait_for_xmitr(struct uart_omap_port *up)
}
}
+#ifdef CONFIG_CONSOLE_POLL
+
+static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
+{
+ struct uart_omap_port *up = (struct uart_omap_port *)port;
+ wait_for_xmitr(up);
+ serial_out(up, UART_TX, ch);
+}
+
+static int serial_omap_poll_get_char(struct uart_port *port)
+{
+ struct uart_omap_port *up = (struct uart_omap_port *)port;
+ unsigned int status = serial_in(up, UART_LSR);
+
+ if (!(status & UART_LSR_DR))
+ return NO_POLL_CHAR;
+
+ return serial_in(up, UART_RX);
+}
+
+#endif /* CONFIG_CONSOLE_POLL */
+
+#ifdef CONFIG_SERIAL_OMAP_CONSOLE
+
+static struct uart_omap_port *serial_omap_console_ports[4];
+
+static struct uart_driver serial_omap_reg;
+
static void serial_omap_console_putchar(struct uart_port *port, int ch)
{
struct uart_omap_port *up = (struct uart_omap_port *)port;
@@ -1022,6 +1044,10 @@ static struct uart_ops serial_omap_pops = {
.request_port = serial_omap_request_port,
.config_port = serial_omap_config_port,
.verify_port = serial_omap_verify_port,
+#ifdef CONFIG_CONSOLE_POLL
+ .poll_put_char = serial_omap_poll_put_char,
+ .poll_get_char = serial_omap_poll_get_char,
+#endif
};
static struct uart_driver serial_omap_reg = {
diff --git a/drivers/serial/pch_uart.c b/drivers/serial/pch_uart.c
new file mode 100644
index 00000000000..70a61458ec4
--- /dev/null
+++ b/drivers/serial/pch_uart.c
@@ -0,0 +1,1451 @@
+/*
+ *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
+ *
+ *This program is free software; you can redistribute it and/or modify
+ *it under the terms of the GNU General Public License as published by
+ *the Free Software Foundation; version 2 of the License.
+ *
+ *This program is distributed in the hope that it will be useful,
+ *but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *GNU General Public License for more details.
+ *
+ *You should have received a copy of the GNU General Public License
+ *along with this program; if not, write to the Free Software
+ *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+#include <linux/serial_reg.h>
+#include <linux/pci.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/serial_core.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+
+#include <linux/dmaengine.h>
+#include <linux/pch_dma.h>
+
+enum {
+ PCH_UART_HANDLED_RX_INT_SHIFT,
+ PCH_UART_HANDLED_TX_INT_SHIFT,
+ PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
+ PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
+ PCH_UART_HANDLED_MS_INT_SHIFT,
+};
+
+enum {
+ PCH_UART_8LINE,
+ PCH_UART_2LINE,
+};
+
+#define PCH_UART_DRIVER_DEVICE "ttyPCH"
+
+#define PCH_UART_NR_GE_256FIFO 1
+#define PCH_UART_NR_GE_64FIFO 3
+#define PCH_UART_NR_GE (PCH_UART_NR_GE_256FIFO+PCH_UART_NR_GE_64FIFO)
+#define PCH_UART_NR PCH_UART_NR_GE
+
+#define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
+#define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
+#define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
+ PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
+#define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
+ PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
+#define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
+
+#define PCH_UART_RBR 0x00
+#define PCH_UART_THR 0x00
+
+#define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
+ PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
+#define PCH_UART_IER_ERBFI 0x00000001
+#define PCH_UART_IER_ETBEI 0x00000002
+#define PCH_UART_IER_ELSI 0x00000004
+#define PCH_UART_IER_EDSSI 0x00000008
+
+#define PCH_UART_IIR_IP 0x00000001
+#define PCH_UART_IIR_IID 0x00000006
+#define PCH_UART_IIR_MSI 0x00000000
+#define PCH_UART_IIR_TRI 0x00000002
+#define PCH_UART_IIR_RRI 0x00000004
+#define PCH_UART_IIR_REI 0x00000006
+#define PCH_UART_IIR_TOI 0x00000008
+#define PCH_UART_IIR_FIFO256 0x00000020
+#define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
+#define PCH_UART_IIR_FE 0x000000C0
+
+#define PCH_UART_FCR_FIFOE 0x00000001
+#define PCH_UART_FCR_RFR 0x00000002
+#define PCH_UART_FCR_TFR 0x00000004
+#define PCH_UART_FCR_DMS 0x00000008
+#define PCH_UART_FCR_FIFO256 0x00000020
+#define PCH_UART_FCR_RFTL 0x000000C0
+
+#define PCH_UART_FCR_RFTL1 0x00000000
+#define PCH_UART_FCR_RFTL64 0x00000040
+#define PCH_UART_FCR_RFTL128 0x00000080
+#define PCH_UART_FCR_RFTL224 0x000000C0
+#define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
+#define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
+#define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
+#define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
+#define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
+#define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
+#define PCH_UART_FCR_RFTL_SHIFT 6
+
+#define PCH_UART_LCR_WLS 0x00000003
+#define PCH_UART_LCR_STB 0x00000004
+#define PCH_UART_LCR_PEN 0x00000008
+#define PCH_UART_LCR_EPS 0x00000010
+#define PCH_UART_LCR_SP 0x00000020
+#define PCH_UART_LCR_SB 0x00000040
+#define PCH_UART_LCR_DLAB 0x00000080
+#define PCH_UART_LCR_NP 0x00000000
+#define PCH_UART_LCR_OP PCH_UART_LCR_PEN
+#define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
+#define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
+#define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
+ PCH_UART_LCR_SP)
+
+#define PCH_UART_LCR_5BIT 0x00000000
+#define PCH_UART_LCR_6BIT 0x00000001
+#define PCH_UART_LCR_7BIT 0x00000002
+#define PCH_UART_LCR_8BIT 0x00000003
+
+#define PCH_UART_MCR_DTR 0x00000001
+#define PCH_UART_MCR_RTS 0x00000002
+#define PCH_UART_MCR_OUT 0x0000000C
+#define PCH_UART_MCR_LOOP 0x00000010
+#define PCH_UART_MCR_AFE 0x00000020
+
+#define PCH_UART_LSR_DR 0x00000001
+#define PCH_UART_LSR_ERR (1<<7)
+
+#define PCH_UART_MSR_DCTS 0x00000001
+#define PCH_UART_MSR_DDSR 0x00000002
+#define PCH_UART_MSR_TERI 0x00000004
+#define PCH_UART_MSR_DDCD 0x00000008
+#define PCH_UART_MSR_CTS 0x00000010
+#define PCH_UART_MSR_DSR 0x00000020
+#define PCH_UART_MSR_RI 0x00000040
+#define PCH_UART_MSR_DCD 0x00000080
+#define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
+ PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
+
+#define PCH_UART_DLL 0x00
+#define PCH_UART_DLM 0x01
+
+#define DIV_ROUND(a, b) (((a) + ((b)/2)) / (b))
+
+#define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
+#define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
+#define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
+#define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
+#define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
+
+#define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
+#define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
+#define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
+#define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
+#define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
+#define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
+#define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
+#define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
+#define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
+#define PCH_UART_HAL_STB1 0
+#define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
+
+#define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
+#define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
+#define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
+ PCH_UART_HAL_CLR_RX_FIFO)
+
+#define PCH_UART_HAL_DMA_MODE0 0
+#define PCH_UART_HAL_FIFO_DIS 0
+#define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
+#define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
+ PCH_UART_FCR_FIFO256)
+#define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
+#define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
+#define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
+#define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
+#define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
+#define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
+#define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
+#define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
+#define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
+#define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
+#define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
+#define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
+#define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
+#define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
+
+#define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
+#define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
+#define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
+#define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
+#define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
+
+#define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
+#define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
+#define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
+#define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
+#define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
+
+struct pch_uart_buffer {
+ unsigned char *buf;
+ int size;
+};
+
+struct eg20t_port {
+ struct uart_port port;
+ int port_type;
+ void __iomem *membase;
+ resource_size_t mapbase;
+ unsigned int iobase;
+ struct pci_dev *pdev;
+ int fifo_size;
+ int base_baud;
+ int start_tx;
+ int start_rx;
+ int tx_empty;
+ int int_dis_flag;
+ int trigger;
+ int trigger_level;
+ struct pch_uart_buffer rxbuf;
+ unsigned int dmsr;
+ unsigned int fcr;
+ unsigned int use_dma;
+ unsigned int use_dma_flag;
+ struct dma_async_tx_descriptor *desc_tx;
+ struct dma_async_tx_descriptor *desc_rx;
+ struct pch_dma_slave param_tx;
+ struct pch_dma_slave param_rx;
+ struct dma_chan *chan_tx;
+ struct dma_chan *chan_rx;
+ struct scatterlist sg_tx;
+ struct scatterlist sg_rx;
+ int tx_dma_use;
+ void *rx_buf_virt;
+ dma_addr_t rx_buf_dma;
+};
+
+static unsigned int default_baud = 9600;
+static const int trigger_level_256[4] = { 1, 64, 128, 224 };
+static const int trigger_level_64[4] = { 1, 16, 32, 56 };
+static const int trigger_level_16[4] = { 1, 4, 8, 14 };
+static const int trigger_level_1[4] = { 1, 1, 1, 1 };
+
+static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
+ int base_baud)
+{
+ struct eg20t_port *priv = pci_get_drvdata(pdev);
+
+ priv->trigger_level = 1;
+ priv->fcr = 0;
+}
+
+static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
+{
+ unsigned int msr = ioread8(base + UART_MSR);
+ priv->dmsr |= msr & PCH_UART_MSR_DELTA;
+
+ return msr;
+}
+
+static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
+ unsigned int flag)
+{
+ u8 ier = ioread8(priv->membase + UART_IER);
+ ier |= flag & PCH_UART_IER_MASK;
+ iowrite8(ier, priv->membase + UART_IER);
+}
+
+static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
+ unsigned int flag)
+{
+ u8 ier = ioread8(priv->membase + UART_IER);
+ ier &= ~(flag & PCH_UART_IER_MASK);
+ iowrite8(ier, priv->membase + UART_IER);
+}
+
+static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
+ unsigned int parity, unsigned int bits,
+ unsigned int stb)
+{
+ unsigned int dll, dlm, lcr;
+ int div;
+
+ div = DIV_ROUND(priv->base_baud / 16, baud);
+ if (div < 0 || USHRT_MAX <= div) {
+ pr_err("Invalid Baud(div=0x%x)\n", div);
+ return -EINVAL;
+ }
+
+ dll = (unsigned int)div & 0x00FFU;
+ dlm = ((unsigned int)div >> 8) & 0x00FFU;
+
+ if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
+ pr_err("Invalid parity(0x%x)\n", parity);
+ return -EINVAL;
+ }
+
+ if (bits & ~PCH_UART_LCR_WLS) {
+ pr_err("Invalid bits(0x%x)\n", bits);
+ return -EINVAL;
+ }
+
+ if (stb & ~PCH_UART_LCR_STB) {
+ pr_err("Invalid STB(0x%x)\n", stb);
+ return -EINVAL;
+ }
+
+ lcr = parity;
+ lcr |= bits;
+ lcr |= stb;
+
+ pr_debug("%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
+ __func__, baud, div, lcr, jiffies);
+ iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
+ iowrite8(dll, priv->membase + PCH_UART_DLL);
+ iowrite8(dlm, priv->membase + PCH_UART_DLM);
+ iowrite8(lcr, priv->membase + UART_LCR);
+
+ return 0;
+}
+
+static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
+ unsigned int flag)
+{
+ if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
+ pr_err("%s:Invalid flag(0x%x)\n", __func__, flag);
+ return -EINVAL;
+ }
+
+ iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
+ iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
+ priv->membase + UART_FCR);
+ iowrite8(priv->fcr, priv->membase + UART_FCR);
+
+ return 0;
+}
+
+static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
+ unsigned int dmamode,
+ unsigned int fifo_size, unsigned int trigger)
+{
+ u8 fcr;
+
+ if (dmamode & ~PCH_UART_FCR_DMS) {
+ pr_err("%s:Invalid DMA Mode(0x%x)\n", __func__, dmamode);
+ return -EINVAL;
+ }
+
+ if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
+ pr_err("%s:Invalid FIFO SIZE(0x%x)\n", __func__, fifo_size);
+ return -EINVAL;
+ }
+
+ if (trigger & ~PCH_UART_FCR_RFTL) {
+ pr_err("%s:Invalid TRIGGER(0x%x)\n", __func__, trigger);
+ return -EINVAL;
+ }
+
+ switch (priv->fifo_size) {
+ case 256:
+ priv->trigger_level =
+ trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
+ break;
+ case 64:
+ priv->trigger_level =
+ trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
+ break;
+ case 16:
+ priv->trigger_level =
+ trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
+ break;
+ default:
+ priv->trigger_level =
+ trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
+ break;
+ }
+ fcr =
+ dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
+ iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
+ iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
+ priv->membase + UART_FCR);
+ iowrite8(fcr, priv->membase + UART_FCR);
+ priv->fcr = fcr;
+
+ return 0;
+}
+
+static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
+{
+ priv->dmsr = 0;
+ return get_msr(priv, priv->membase);
+}
+
+static int pch_uart_hal_write(struct eg20t_port *priv,
+ const unsigned char *buf, int tx_size)
+{
+ int i;
+ unsigned int thr;
+
+ for (i = 0; i < tx_size;) {
+ thr = buf[i++];
+ iowrite8(thr, priv->membase + PCH_UART_THR);
+ }
+ return i;
+}
+
+static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
+ int rx_size)
+{
+ int i;
+ u8 rbr, lsr;
+
+ lsr = ioread8(priv->membase + UART_LSR);
+ for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
+ i < rx_size && lsr & UART_LSR_DR;
+ lsr = ioread8(priv->membase + UART_LSR)) {
+ rbr = ioread8(priv->membase + PCH_UART_RBR);
+ buf[i++] = rbr;
+ }
+ return i;
+}
+
+static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
+{
+ unsigned int iir;
+ int ret;
+
+ iir = ioread8(priv->membase + UART_IIR);
+ ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
+ return ret;
+}
+
+static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
+{
+ return ioread8(priv->membase + UART_LSR);
+}
+
+static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
+{
+ unsigned int lcr;
+
+ lcr = ioread8(priv->membase + UART_LCR);
+ if (on)
+ lcr |= PCH_UART_LCR_SB;
+ else
+ lcr &= ~PCH_UART_LCR_SB;
+
+ iowrite8(lcr, priv->membase + UART_LCR);
+}
+
+static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
+ int size)
+{
+ struct uart_port *port;
+ struct tty_struct *tty;
+
+ port = &priv->port;
+ tty = tty_port_tty_get(&port->state->port);
+ if (!tty) {
+ pr_debug("%s:tty is busy now", __func__);
+ return -EBUSY;
+ }
+
+ tty_insert_flip_string(tty, buf, size);
+ tty_flip_buffer_push(tty);
+ tty_kref_put(tty);
+
+ return 0;
+}
+
+static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
+{
+ int ret;
+ struct uart_port *port = &priv->port;
+
+ if (port->x_char) {
+ pr_debug("%s:X character send %02x (%lu)\n", __func__,
+ port->x_char, jiffies);
+ buf[0] = port->x_char;
+ port->x_char = 0;
+ ret = 1;
+ } else {
+ ret = 0;
+ }
+
+ return ret;
+}
+
+static int dma_push_rx(struct eg20t_port *priv, int size)
+{
+ struct tty_struct *tty;
+ int room;
+ struct uart_port *port = &priv->port;
+
+ port = &priv->port;
+ tty = tty_port_tty_get(&port->state->port);
+ if (!tty) {
+ pr_debug("%s:tty is busy now", __func__);
+ return 0;
+ }
+
+ room = tty_buffer_request_room(tty, size);
+
+ if (room < size)
+ dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
+ size - room);
+ if (!room)
+ return room;
+
+ tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
+
+ port->icount.rx += room;
+ tty_kref_put(tty);
+
+ return room;
+}
+
+static void pch_free_dma(struct uart_port *port)
+{
+ struct eg20t_port *priv;
+ priv = container_of(port, struct eg20t_port, port);
+
+ if (priv->chan_tx) {
+ dma_release_channel(priv->chan_tx);
+ priv->chan_tx = NULL;
+ }
+ if (priv->chan_rx) {
+ dma_release_channel(priv->chan_rx);
+ priv->chan_rx = NULL;
+ }
+ if (sg_dma_address(&priv->sg_rx))
+ dma_free_coherent(port->dev, port->fifosize,
+ sg_virt(&priv->sg_rx),
+ sg_dma_address(&priv->sg_rx));
+
+ return;
+}
+
+static bool filter(struct dma_chan *chan, void *slave)
+{
+ struct pch_dma_slave *param = slave;
+
+ if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
+ chan->device->dev)) {
+ chan->private = param;
+ return true;
+ } else {
+ return false;
+ }
+}
+
+static void pch_request_dma(struct uart_port *port)
+{
+ dma_cap_mask_t mask;
+ struct dma_chan *chan;
+ struct pci_dev *dma_dev;
+ struct pch_dma_slave *param;
+ struct eg20t_port *priv =
+ container_of(port, struct eg20t_port, port);
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+
+ dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(0xa, 0)); /* Get DMA's dev
+ information */
+ /* Set Tx DMA */
+ param = &priv->param_tx;
+ param->dma_dev = &dma_dev->dev;
+ param->chan_id = priv->port.line;
+ param->tx_reg = port->mapbase + UART_TX;
+ chan = dma_request_channel(mask, filter, param);
+ if (!chan) {
+ pr_err("%s:dma_request_channel FAILS(Tx)\n", __func__);
+ return;
+ }
+ priv->chan_tx = chan;
+
+ /* Set Rx DMA */
+ param = &priv->param_rx;
+ param->dma_dev = &dma_dev->dev;
+ param->chan_id = priv->port.line + 1; /* Rx = Tx + 1 */
+ param->rx_reg = port->mapbase + UART_RX;
+ chan = dma_request_channel(mask, filter, param);
+ if (!chan) {
+ pr_err("%s:dma_request_channel FAILS(Rx)\n", __func__);
+ dma_release_channel(priv->chan_tx);
+ return;
+ }
+
+ /* Get Consistent memory for DMA */
+ priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
+ &priv->rx_buf_dma, GFP_KERNEL);
+ priv->chan_rx = chan;
+}
+
+static void pch_dma_rx_complete(void *arg)
+{
+ struct eg20t_port *priv = arg;
+ struct uart_port *port = &priv->port;
+ struct tty_struct *tty = tty_port_tty_get(&port->state->port);
+
+ if (!tty) {
+ pr_debug("%s:tty is busy now", __func__);
+ return;
+ }
+
+ if (dma_push_rx(priv, priv->trigger_level))
+ tty_flip_buffer_push(tty);
+
+ tty_kref_put(tty);
+}
+
+static void pch_dma_tx_complete(void *arg)
+{
+ struct eg20t_port *priv = arg;
+ struct uart_port *port = &priv->port;
+ struct circ_buf *xmit = &port->state->xmit;
+
+ xmit->tail += sg_dma_len(&priv->sg_tx);
+ xmit->tail &= UART_XMIT_SIZE - 1;
+ port->icount.tx += sg_dma_len(&priv->sg_tx);
+
+ async_tx_ack(priv->desc_tx);
+ priv->tx_dma_use = 0;
+}
+
+static int pop_tx(struct eg20t_port *priv, unsigned char *buf, int size)
+{
+ int count = 0;
+ struct uart_port *port = &priv->port;
+ struct circ_buf *xmit = &port->state->xmit;
+
+ if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
+ goto pop_tx_end;
+
+ do {
+ int cnt_to_end =
+ CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
+ int sz = min(size - count, cnt_to_end);
+ memcpy(&buf[count], &xmit->buf[xmit->tail], sz);
+ xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
+ count += sz;
+ } while (!uart_circ_empty(xmit) && count < size);
+
+pop_tx_end:
+ pr_debug("%d characters. Remained %d characters. (%lu)\n",
+ count, size - count, jiffies);
+
+ return count;
+}
+
+static int handle_rx_to(struct eg20t_port *priv)
+{
+ struct pch_uart_buffer *buf;
+ int rx_size;
+ int ret;
+ if (!priv->start_rx) {
+ pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
+ return 0;
+ }
+ buf = &priv->rxbuf;
+ do {
+ rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
+ ret = push_rx(priv, buf->buf, rx_size);
+ if (ret)
+ return 0;
+ } while (rx_size == buf->size);
+
+ return PCH_UART_HANDLED_RX_INT;
+}
+
+static int handle_rx(struct eg20t_port *priv)
+{
+ return handle_rx_to(priv);
+}
+
+static int dma_handle_rx(struct eg20t_port *priv)
+{
+ struct uart_port *port = &priv->port;
+ struct dma_async_tx_descriptor *desc;
+ struct scatterlist *sg;
+
+ priv = container_of(port, struct eg20t_port, port);
+ sg = &priv->sg_rx;
+
+ sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
+
+ sg_dma_len(sg) = priv->fifo_size;
+
+ sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
+ sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
+ ~PAGE_MASK);
+
+ sg_dma_address(sg) = priv->rx_buf_dma;
+
+ desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
+ sg, 1, DMA_FROM_DEVICE,
+ DMA_PREP_INTERRUPT);
+ if (!desc)
+ return 0;
+
+ priv->desc_rx = desc;
+ desc->callback = pch_dma_rx_complete;
+ desc->callback_param = priv;
+ desc->tx_submit(desc);
+ dma_async_issue_pending(priv->chan_rx);
+
+ return PCH_UART_HANDLED_RX_INT;
+}
+
+static unsigned int handle_tx(struct eg20t_port *priv)
+{
+ struct uart_port *port = &priv->port;
+ struct circ_buf *xmit = &port->state->xmit;
+ int ret;
+ int fifo_size;
+ int tx_size;
+ int size;
+ int tx_empty;
+
+ if (!priv->start_tx) {
+ pr_info("%s:Tx isn't started. (%lu)\n", __func__, jiffies);
+ pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
+ priv->tx_empty = 1;
+ return 0;
+ }
+
+ fifo_size = max(priv->fifo_size, 1);
+ tx_empty = 1;
+ if (pop_tx_x(priv, xmit->buf)) {
+ pch_uart_hal_write(priv, xmit->buf, 1);
+ port->icount.tx++;
+ tx_empty = 0;
+ fifo_size--;
+ }
+ size = min(xmit->head - xmit->tail, fifo_size);
+ tx_size = pop_tx(priv, xmit->buf, size);
+ if (tx_size > 0) {
+ ret = pch_uart_hal_write(priv, xmit->buf, tx_size);
+ port->icount.tx += ret;
+ tx_empty = 0;
+ }
+
+ priv->tx_empty = tx_empty;
+
+ if (tx_empty)
+ pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
+
+ return PCH_UART_HANDLED_TX_INT;
+}
+
+static unsigned int dma_handle_tx(struct eg20t_port *priv)
+{
+ struct uart_port *port = &priv->port;
+ struct circ_buf *xmit = &port->state->xmit;
+ struct scatterlist *sg = &priv->sg_tx;
+ int nent;
+ int fifo_size;
+ int tx_empty;
+ struct dma_async_tx_descriptor *desc;
+
+ if (!priv->start_tx) {
+ pr_info("%s:Tx isn't started. (%lu)\n", __func__, jiffies);
+ pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
+ priv->tx_empty = 1;
+ return 0;
+ }
+
+ fifo_size = max(priv->fifo_size, 1);
+ tx_empty = 1;
+ if (pop_tx_x(priv, xmit->buf)) {
+ pch_uart_hal_write(priv, xmit->buf, 1);
+ port->icount.tx++;
+ tx_empty = 0;
+ fifo_size--;
+ }
+
+ pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
+
+ priv->tx_dma_use = 1;
+
+ sg_init_table(&priv->sg_tx, 1); /* Initialize SG table */
+
+ sg_set_page(&priv->sg_tx, virt_to_page(xmit->buf),
+ UART_XMIT_SIZE, (int)xmit->buf & ~PAGE_MASK);
+
+ nent = dma_map_sg(port->dev, &priv->sg_tx, 1, DMA_TO_DEVICE);
+ if (!nent) {
+ pr_err("%s:dma_map_sg Failed\n", __func__);
+ return 0;
+ }
+
+ sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
+ sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
+ sg->offset;
+ sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail,
+ UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
+ xmit->tail, UART_XMIT_SIZE));
+
+ desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
+ sg, nent, DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+ if (!desc) {
+ pr_err("%s:device_prep_slave_sg Failed\n", __func__);
+ return 0;
+ }
+
+ dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
+
+ priv->desc_tx = desc;
+ desc->callback = pch_dma_tx_complete;
+ desc->callback_param = priv;
+
+ desc->tx_submit(desc);
+
+ dma_async_issue_pending(priv->chan_tx);
+
+ return PCH_UART_HANDLED_TX_INT;
+}
+
+static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
+{
+ u8 fcr = ioread8(priv->membase + UART_FCR);
+
+ /* Reset FIFO */
+ fcr |= UART_FCR_CLEAR_RCVR;
+ iowrite8(fcr, priv->membase + UART_FCR);
+
+ if (lsr & PCH_UART_LSR_ERR)
+ dev_err(&priv->pdev->dev, "Error data in FIFO\n");
+
+ if (lsr & UART_LSR_FE)
+ dev_err(&priv->pdev->dev, "Framing Error\n");
+
+ if (lsr & UART_LSR_PE)
+ dev_err(&priv->pdev->dev, "Parity Error\n");
+
+ if (lsr & UART_LSR_OE)
+ dev_err(&priv->pdev->dev, "Overrun Error\n");
+}
+
+static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
+{
+ struct eg20t_port *priv = dev_id;
+ unsigned int handled;
+ u8 lsr;
+ int ret = 0;
+ unsigned int iid;
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->port.lock, flags);
+ handled = 0;
+ while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
+ switch (iid) {
+ case PCH_UART_IID_RLS: /* Receiver Line Status */
+ lsr = pch_uart_hal_get_line_status(priv);
+ if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
+ UART_LSR_PE | UART_LSR_OE)) {
+ pch_uart_err_ir(priv, lsr);
+ ret = PCH_UART_HANDLED_RX_ERR_INT;
+ }
+ break;
+ case PCH_UART_IID_RDR: /* Received Data Ready */
+ if (priv->use_dma)
+ ret = dma_handle_rx(priv);
+ else
+ ret = handle_rx(priv);
+ break;
+ case PCH_UART_IID_RDR_TO: /* Received Data Ready
+ (FIFO Timeout) */
+ ret = handle_rx_to(priv);
+ break;
+ case PCH_UART_IID_THRE: /* Transmitter Holding Register
+ Empty */
+ if (priv->use_dma)
+ ret = dma_handle_tx(priv);
+ else
+ ret = handle_tx(priv);
+ break;
+ case PCH_UART_IID_MS: /* Modem Status */
+ ret = PCH_UART_HANDLED_MS_INT;
+ break;
+ default: /* Never junp to this label */
+ pr_err("%s:iid=%d (%lu)\n", __func__, iid, jiffies);
+ ret = -1;
+ break;
+ }
+ handled |= (unsigned int)ret;
+ }
+ if (handled == 0 && iid <= 1) {
+ if (priv->int_dis_flag)
+ priv->int_dis_flag = 0;
+ }
+
+ spin_unlock_irqrestore(&priv->port.lock, flags);
+ return IRQ_RETVAL(handled);
+}
+
+/* This function tests whether the transmitter fifo and shifter for the port
+ described by 'port' is empty. */
+static unsigned int pch_uart_tx_empty(struct uart_port *port)
+{
+ struct eg20t_port *priv;
+ int ret;
+ priv = container_of(port, struct eg20t_port, port);
+ if (priv->tx_empty)
+ ret = TIOCSER_TEMT;
+ else
+ ret = 0;
+
+ return ret;
+}
+
+/* Returns the current state of modem control inputs. */
+static unsigned int pch_uart_get_mctrl(struct uart_port *port)
+{
+ struct eg20t_port *priv;
+ u8 modem;
+ unsigned int ret = 0;
+
+ priv = container_of(port, struct eg20t_port, port);
+ modem = pch_uart_hal_get_modem(priv);
+
+ if (modem & UART_MSR_DCD)
+ ret |= TIOCM_CAR;
+
+ if (modem & UART_MSR_RI)
+ ret |= TIOCM_RNG;
+
+ if (modem & UART_MSR_DSR)
+ ret |= TIOCM_DSR;
+
+ if (modem & UART_MSR_CTS)
+ ret |= TIOCM_CTS;
+
+ return ret;
+}
+
+static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+ u32 mcr = 0;
+ unsigned int dat;
+ struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
+
+ if (mctrl & TIOCM_DTR)
+ mcr |= UART_MCR_DTR;
+ if (mctrl & TIOCM_RTS)
+ mcr |= UART_MCR_RTS;
+ if (mctrl & TIOCM_LOOP)
+ mcr |= UART_MCR_LOOP;
+
+ if (mctrl) {
+ dat = pch_uart_get_mctrl(port);
+ dat |= mcr;
+ iowrite8(dat, priv->membase + UART_MCR);
+ }
+}
+
+static void pch_uart_stop_tx(struct uart_port *port)
+{
+ struct eg20t_port *priv;
+ priv = container_of(port, struct eg20t_port, port);
+ priv->start_tx = 0;
+ priv->tx_dma_use = 0;
+}
+
+static void pch_uart_start_tx(struct uart_port *port)
+{
+ struct eg20t_port *priv;
+
+ priv = container_of(port, struct eg20t_port, port);
+
+ if (priv->use_dma)
+ if (priv->tx_dma_use)
+ return;
+
+ priv->start_tx = 1;
+ pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
+}
+
+static void pch_uart_stop_rx(struct uart_port *port)
+{
+ struct eg20t_port *priv;
+ priv = container_of(port, struct eg20t_port, port);
+ priv->start_rx = 0;
+ pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
+ priv->int_dis_flag = 1;
+}
+
+/* Enable the modem status interrupts. */
+static void pch_uart_enable_ms(struct uart_port *port)
+{
+ struct eg20t_port *priv;
+ priv = container_of(port, struct eg20t_port, port);
+ pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
+}
+
+/* Control the transmission of a break signal. */
+static void pch_uart_break_ctl(struct uart_port *port, int ctl)
+{
+ struct eg20t_port *priv;
+ unsigned long flags;
+
+ priv = container_of(port, struct eg20t_port, port);
+ spin_lock_irqsave(&port->lock, flags);
+ pch_uart_hal_set_break(priv, ctl);
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+/* Grab any interrupt resources and initialise any low level driver state. */
+static int pch_uart_startup(struct uart_port *port)
+{
+ struct eg20t_port *priv;
+ int ret;
+ int fifo_size;
+ int trigger_level;
+
+ priv = container_of(port, struct eg20t_port, port);
+ priv->tx_empty = 1;
+ port->uartclk = priv->base_baud;
+ pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
+ ret = pch_uart_hal_set_line(priv, default_baud,
+ PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
+ PCH_UART_HAL_STB1);
+ if (ret)
+ return ret;
+
+ switch (priv->fifo_size) {
+ case 256:
+ fifo_size = PCH_UART_HAL_FIFO256;
+ break;
+ case 64:
+ fifo_size = PCH_UART_HAL_FIFO64;
+ break;
+ case 16:
+ fifo_size = PCH_UART_HAL_FIFO16;
+ case 1:
+ default:
+ fifo_size = PCH_UART_HAL_FIFO_DIS;
+ break;
+ }
+
+ switch (priv->trigger) {
+ case PCH_UART_HAL_TRIGGER1:
+ trigger_level = 1;
+ break;
+ case PCH_UART_HAL_TRIGGER_L:
+ trigger_level = priv->fifo_size / 4;
+ break;
+ case PCH_UART_HAL_TRIGGER_M:
+ trigger_level = priv->fifo_size / 2;
+ break;
+ case PCH_UART_HAL_TRIGGER_H:
+ default:
+ trigger_level = priv->fifo_size - (priv->fifo_size / 8);
+ break;
+ }
+
+ priv->trigger_level = trigger_level;
+ ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
+ fifo_size, priv->trigger);
+ if (ret < 0)
+ return ret;
+
+ ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
+ KBUILD_MODNAME, priv);
+ if (ret < 0)
+ return ret;
+
+ if (priv->use_dma)
+ pch_request_dma(port);
+
+ priv->start_rx = 1;
+ pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
+ uart_update_timeout(port, CS8, default_baud);
+
+ return 0;
+}
+
+static void pch_uart_shutdown(struct uart_port *port)
+{
+ struct eg20t_port *priv;
+ int ret;
+
+ priv = container_of(port, struct eg20t_port, port);
+ pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
+ pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
+ ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
+ PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
+ if (ret)
+ pr_err("pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
+
+ if (priv->use_dma_flag)
+ pch_free_dma(port);
+
+ free_irq(priv->port.irq, priv);
+}
+
+/* Change the port parameters, including word length, parity, stop
+ *bits. Update read_status_mask and ignore_status_mask to indicate
+ *the types of events we are interested in receiving. */
+static void pch_uart_set_termios(struct uart_port *port,
+ struct ktermios *termios, struct ktermios *old)
+{
+ int baud;
+ int rtn;
+ unsigned int parity, bits, stb;
+ struct eg20t_port *priv;
+ unsigned long flags;
+
+ priv = container_of(port, struct eg20t_port, port);
+ switch (termios->c_cflag & CSIZE) {
+ case CS5:
+ bits = PCH_UART_HAL_5BIT;
+ break;
+ case CS6:
+ bits = PCH_UART_HAL_6BIT;
+ break;
+ case CS7:
+ bits = PCH_UART_HAL_7BIT;
+ break;
+ default: /* CS8 */
+ bits = PCH_UART_HAL_8BIT;
+ break;
+ }
+ if (termios->c_cflag & CSTOPB)
+ stb = PCH_UART_HAL_STB2;
+ else
+ stb = PCH_UART_HAL_STB1;
+
+ if (termios->c_cflag & PARENB) {
+ if (!(termios->c_cflag & PARODD))
+ parity = PCH_UART_HAL_PARITY_ODD;
+ else
+ parity = PCH_UART_HAL_PARITY_EVEN;
+
+ } else {
+ parity = PCH_UART_HAL_PARITY_NONE;
+ }
+ termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
+
+ baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ uart_update_timeout(port, termios->c_cflag, baud);
+ rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
+ if (rtn)
+ goto out;
+
+ /* Don't rewrite B0 */
+ if (tty_termios_baud_rate(termios))
+ tty_termios_encode_baud_rate(termios, baud, baud);
+
+out:
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static const char *pch_uart_type(struct uart_port *port)
+{
+ return KBUILD_MODNAME;
+}
+
+static void pch_uart_release_port(struct uart_port *port)
+{
+ struct eg20t_port *priv;
+
+ priv = container_of(port, struct eg20t_port, port);
+ pci_iounmap(priv->pdev, priv->membase);
+ pci_release_regions(priv->pdev);
+}
+
+static int pch_uart_request_port(struct uart_port *port)
+{
+ struct eg20t_port *priv;
+ int ret;
+ void __iomem *membase;
+
+ priv = container_of(port, struct eg20t_port, port);
+ ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
+ if (ret < 0)
+ return -EBUSY;
+
+ membase = pci_iomap(priv->pdev, 1, 0);
+ if (!membase) {
+ pci_release_regions(priv->pdev);
+ return -EBUSY;
+ }
+ priv->membase = port->membase = membase;
+
+ return 0;
+}
+
+static void pch_uart_config_port(struct uart_port *port, int type)
+{
+ struct eg20t_port *priv;
+
+ priv = container_of(port, struct eg20t_port, port);
+ if (type & UART_CONFIG_TYPE) {
+ port->type = priv->port_type;
+ pch_uart_request_port(port);
+ }
+}
+
+static int pch_uart_verify_port(struct uart_port *port,
+ struct serial_struct *serinfo)
+{
+ struct eg20t_port *priv;
+
+ priv = container_of(port, struct eg20t_port, port);
+ if (serinfo->flags & UPF_LOW_LATENCY) {
+ pr_info("PCH UART : Use PIO Mode (without DMA)\n");
+ priv->use_dma = 0;
+ serinfo->flags &= ~UPF_LOW_LATENCY;
+ } else {
+#ifndef CONFIG_PCH_DMA
+ pr_err("%s : PCH DMA is not Loaded.\n", __func__);
+ return -EOPNOTSUPP;
+#endif
+ priv->use_dma = 1;
+ priv->use_dma_flag = 1;
+ pr_info("PCH UART : Use DMA Mode\n");
+ }
+
+ return 0;
+}
+
+static struct uart_ops pch_uart_ops = {
+ .tx_empty = pch_uart_tx_empty,
+ .set_mctrl = pch_uart_set_mctrl,
+ .get_mctrl = pch_uart_get_mctrl,
+ .stop_tx = pch_uart_stop_tx,
+ .start_tx = pch_uart_start_tx,
+ .stop_rx = pch_uart_stop_rx,
+ .enable_ms = pch_uart_enable_ms,
+ .break_ctl = pch_uart_break_ctl,
+ .startup = pch_uart_startup,
+ .shutdown = pch_uart_shutdown,
+ .set_termios = pch_uart_set_termios,
+/* .pm = pch_uart_pm, Not supported yet */
+/* .set_wake = pch_uart_set_wake, Not supported yet */
+ .type = pch_uart_type,
+ .release_port = pch_uart_release_port,
+ .request_port = pch_uart_request_port,
+ .config_port = pch_uart_config_port,
+ .verify_port = pch_uart_verify_port
+};
+
+static struct uart_driver pch_uart_driver = {
+ .owner = THIS_MODULE,
+ .driver_name = KBUILD_MODNAME,
+ .dev_name = PCH_UART_DRIVER_DEVICE,
+ .major = 0,
+ .minor = 0,
+ .nr = PCH_UART_NR,
+};
+
+static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
+ int port_type)
+{
+ struct eg20t_port *priv;
+ int ret;
+ unsigned int iobase;
+ unsigned int mapbase;
+ unsigned char *rxbuf;
+ int fifosize, base_baud;
+ static int num;
+
+ priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
+ if (priv == NULL)
+ goto init_port_alloc_err;
+
+ rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
+ if (!rxbuf)
+ goto init_port_free_txbuf;
+
+ switch (port_type) {
+ case PORT_UNKNOWN:
+ fifosize = 256; /* UART0 */
+ base_baud = 1843200; /* 1.8432MHz */
+ break;
+ case PORT_8250:
+ fifosize = 64; /* UART1~3 */
+ base_baud = 1843200; /* 1.8432MHz */
+ break;
+ default:
+ dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
+ goto init_port_hal_free;
+ }
+
+ iobase = pci_resource_start(pdev, 0);
+ mapbase = pci_resource_start(pdev, 1);
+ priv->mapbase = mapbase;
+ priv->iobase = iobase;
+ priv->pdev = pdev;
+ priv->tx_empty = 1;
+ priv->rxbuf.buf = rxbuf;
+ priv->rxbuf.size = PAGE_SIZE;
+
+ priv->fifo_size = fifosize;
+ priv->base_baud = base_baud;
+ priv->port_type = PORT_MAX_8250 + port_type + 1;
+ priv->port.dev = &pdev->dev;
+ priv->port.iobase = iobase;
+ priv->port.membase = NULL;
+ priv->port.mapbase = mapbase;
+ priv->port.irq = pdev->irq;
+ priv->port.iotype = UPIO_PORT;
+ priv->port.ops = &pch_uart_ops;
+ priv->port.flags = UPF_BOOT_AUTOCONF;
+ priv->port.fifosize = fifosize;
+ priv->port.line = num++;
+ priv->trigger = PCH_UART_HAL_TRIGGER_M;
+
+ pci_set_drvdata(pdev, priv);
+ pch_uart_hal_request(pdev, fifosize, base_baud);
+ ret = uart_add_one_port(&pch_uart_driver, &priv->port);
+ if (ret < 0)
+ goto init_port_hal_free;
+
+ return priv;
+
+init_port_hal_free:
+ free_page((unsigned long)rxbuf);
+init_port_free_txbuf:
+ kfree(priv);
+init_port_alloc_err:
+
+ return NULL;
+}
+
+static void pch_uart_exit_port(struct eg20t_port *priv)
+{
+ uart_remove_one_port(&pch_uart_driver, &priv->port);
+ pci_set_drvdata(priv->pdev, NULL);
+ free_page((unsigned long)priv->rxbuf.buf);
+}
+
+static void pch_uart_pci_remove(struct pci_dev *pdev)
+{
+ struct eg20t_port *priv;
+
+ priv = (struct eg20t_port *)pci_get_drvdata(pdev);
+ pch_uart_exit_port(priv);
+ pci_disable_device(pdev);
+ kfree(priv);
+ return;
+}
+#ifdef CONFIG_PM
+static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ struct eg20t_port *priv = pci_get_drvdata(pdev);
+
+ uart_suspend_port(&pch_uart_driver, &priv->port);
+
+ pci_save_state(pdev);
+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
+ return 0;
+}
+
+static int pch_uart_pci_resume(struct pci_dev *pdev)
+{
+ struct eg20t_port *priv = pci_get_drvdata(pdev);
+ int ret;
+
+ pci_set_power_state(pdev, PCI_D0);
+ pci_restore_state(pdev);
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
+ return ret;
+ }
+
+ uart_resume_port(&pch_uart_driver, &priv->port);
+
+ return 0;
+}
+#else
+#define pch_uart_pci_suspend NULL
+#define pch_uart_pci_resume NULL
+#endif
+
+static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
+ .driver_data = PCH_UART_8LINE},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
+ .driver_data = PCH_UART_2LINE},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
+ .driver_data = PCH_UART_2LINE},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
+ .driver_data = PCH_UART_2LINE},
+ {0,},
+};
+
+static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ int ret;
+ struct eg20t_port *priv;
+
+ ret = pci_enable_device(pdev);
+ if (ret < 0)
+ goto probe_error;
+
+ priv = pch_uart_init_port(pdev, id->driver_data);
+ if (!priv) {
+ ret = -EBUSY;
+ goto probe_disable_device;
+ }
+ pci_set_drvdata(pdev, priv);
+
+ return ret;
+
+probe_disable_device:
+ pci_disable_device(pdev);
+probe_error:
+ return ret;
+}
+
+static struct pci_driver pch_uart_pci_driver = {
+ .name = "pch_uart",
+ .id_table = pch_uart_pci_id,
+ .probe = pch_uart_pci_probe,
+ .remove = __devexit_p(pch_uart_pci_remove),
+ .suspend = pch_uart_pci_suspend,
+ .resume = pch_uart_pci_resume,
+};
+
+static int __init pch_uart_module_init(void)
+{
+ int ret;
+
+ /* register as UART driver */
+ ret = uart_register_driver(&pch_uart_driver);
+ if (ret < 0)
+ return ret;
+
+ /* register as PCI driver */
+ ret = pci_register_driver(&pch_uart_pci_driver);
+ if (ret < 0)
+ uart_unregister_driver(&pch_uart_driver);
+
+ return ret;
+}
+module_init(pch_uart_module_init);
+
+static void __exit pch_uart_module_exit(void)
+{
+ pci_unregister_driver(&pch_uart_pci_driver);
+ uart_unregister_driver(&pch_uart_driver);
+}
+module_exit(pch_uart_module_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
+module_param(default_baud, uint, S_IRUGO);
diff --git a/drivers/serial/serial_core.c b/drivers/serial/serial_core.c
index c4ea14670d4..460a72d91bb 100644
--- a/drivers/serial/serial_core.c
+++ b/drivers/serial/serial_core.c
@@ -29,7 +29,6 @@
#include <linux/console.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
-#include <linux/smp_lock.h>
#include <linux/device.h>
#include <linux/serial.h> /* for serial_state and serial_icounter_struct */
#include <linux/serial_core.h>
@@ -1986,7 +1985,8 @@ int uart_suspend_port(struct uart_driver *drv, struct uart_port *uport)
tty_dev = device_find_child(uport->dev, &match, serial_match_port);
if (device_may_wakeup(tty_dev)) {
- enable_irq_wake(uport->irq);
+ if (!enable_irq_wake(uport->irq))
+ uport->irq_wake = 1;
put_device(tty_dev);
mutex_unlock(&port->mutex);
return 0;
@@ -2052,7 +2052,10 @@ int uart_resume_port(struct uart_driver *drv, struct uart_port *uport)
tty_dev = device_find_child(uport->dev, &match, serial_match_port);
if (!uport->suspended && device_may_wakeup(tty_dev)) {
- disable_irq_wake(uport->irq);
+ if (uport->irq_wake) {
+ disable_irq_wake(uport->irq);
+ uport->irq_wake = 0;
+ }
mutex_unlock(&port->mutex);
return 0;
}
@@ -2135,6 +2138,7 @@ uart_report_port(struct uart_driver *drv, struct uart_port *port)
case UPIO_AU:
case UPIO_TSI:
case UPIO_DWAPB:
+ case UPIO_DWAPB32:
snprintf(address, sizeof(address),
"MMIO 0x%llx", (unsigned long long)port->mapbase);
break;
@@ -2555,6 +2559,7 @@ int uart_match_port(struct uart_port *port1, struct uart_port *port2)
case UPIO_AU:
case UPIO_TSI:
case UPIO_DWAPB:
+ case UPIO_DWAPB32:
return (port1->mapbase == port2->mapbase);
}
return 0;
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index d2352ac437c..4bc614e4221 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -31,6 +31,7 @@
# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+ defined(CONFIG_ARCH_SH73A0) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377) || \
defined(CONFIG_ARCH_SH7372)
@@ -244,6 +245,7 @@
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+ defined(CONFIG_ARCH_SH73A0) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377) || \
defined(CONFIG_ARCH_SH7372)
@@ -280,6 +282,7 @@
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+ defined(CONFIG_ARCH_SH73A0) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377) || \
defined(CONFIG_ARCH_SH7372)
@@ -378,6 +381,7 @@
}
#if defined(CONFIG_CPU_SH3) || \
+ defined(CONFIG_ARCH_SH73A0) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377) || \
defined(CONFIG_ARCH_SH7372)
@@ -391,6 +395,7 @@
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+ defined(CONFIG_ARCH_SH73A0) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377)
#define SCIF_FNS(name, scif_offset, scif_size) \
@@ -433,6 +438,7 @@
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+ defined(CONFIG_ARCH_SH73A0) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377)
@@ -632,6 +638,7 @@ static inline int sci_rxd_in(struct uart_port *port)
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+ defined(CONFIG_ARCH_SH73A0) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377) || \
defined(CONFIG_ARCH_SH7372)
diff --git a/drivers/serial/vt8500_serial.c b/drivers/serial/vt8500_serial.c
new file mode 100644
index 00000000000..322bf56c0d8
--- /dev/null
+++ b/drivers/serial/vt8500_serial.c
@@ -0,0 +1,648 @@
+/*
+ * drivers/serial/vt8500_serial.c
+ *
+ * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
+ *
+ * Based on msm_serial.c, which is:
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Robert Love <rlove@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#if defined(CONFIG_SERIAL_VT8500_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+# define SUPPORT_SYSRQ
+#endif
+
+#include <linux/hrtimer.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+
+/*
+ * UART Register offsets
+ */
+
+#define VT8500_URTDR 0x0000 /* Transmit data */
+#define VT8500_URRDR 0x0004 /* Receive data */
+#define VT8500_URDIV 0x0008 /* Clock/Baud rate divisor */
+#define VT8500_URLCR 0x000C /* Line control */
+#define VT8500_URICR 0x0010 /* IrDA control */
+#define VT8500_URIER 0x0014 /* Interrupt enable */
+#define VT8500_URISR 0x0018 /* Interrupt status */
+#define VT8500_URUSR 0x001c /* UART status */
+#define VT8500_URFCR 0x0020 /* FIFO control */
+#define VT8500_URFIDX 0x0024 /* FIFO index */
+#define VT8500_URBKR 0x0028 /* Break signal count */
+#define VT8500_URTOD 0x002c /* Time out divisor */
+#define VT8500_TXFIFO 0x1000 /* Transmit FIFO (16x8) */
+#define VT8500_RXFIFO 0x1020 /* Receive FIFO (16x10) */
+
+/*
+ * Interrupt enable and status bits
+ */
+
+#define TXDE (1 << 0) /* Tx Data empty */
+#define RXDF (1 << 1) /* Rx Data full */
+#define TXFAE (1 << 2) /* Tx FIFO almost empty */
+#define TXFE (1 << 3) /* Tx FIFO empty */
+#define RXFAF (1 << 4) /* Rx FIFO almost full */
+#define RXFF (1 << 5) /* Rx FIFO full */
+#define TXUDR (1 << 6) /* Tx underrun */
+#define RXOVER (1 << 7) /* Rx overrun */
+#define PER (1 << 8) /* Parity error */
+#define FER (1 << 9) /* Frame error */
+#define TCTS (1 << 10) /* Toggle of CTS */
+#define RXTOUT (1 << 11) /* Rx timeout */
+#define BKDONE (1 << 12) /* Break signal done */
+#define ERR (1 << 13) /* AHB error response */
+
+#define RX_FIFO_INTS (RXFAF | RXFF | RXOVER | PER | FER | RXTOUT)
+#define TX_FIFO_INTS (TXFAE | TXFE | TXUDR)
+
+struct vt8500_port {
+ struct uart_port uart;
+ char name[16];
+ struct clk *clk;
+ unsigned int ier;
+};
+
+static inline void vt8500_write(struct uart_port *port, unsigned int val,
+ unsigned int off)
+{
+ writel(val, port->membase + off);
+}
+
+static inline unsigned int vt8500_read(struct uart_port *port, unsigned int off)
+{
+ return readl(port->membase + off);
+}
+
+static void vt8500_stop_tx(struct uart_port *port)
+{
+ struct vt8500_port *vt8500_port = container_of(port,
+ struct vt8500_port,
+ uart);
+
+ vt8500_port->ier &= ~TX_FIFO_INTS;
+ vt8500_write(port, vt8500_port->ier, VT8500_URIER);
+}
+
+static void vt8500_stop_rx(struct uart_port *port)
+{
+ struct vt8500_port *vt8500_port = container_of(port,
+ struct vt8500_port,
+ uart);
+
+ vt8500_port->ier &= ~RX_FIFO_INTS;
+ vt8500_write(port, vt8500_port->ier, VT8500_URIER);
+}
+
+static void vt8500_enable_ms(struct uart_port *port)
+{
+ struct vt8500_port *vt8500_port = container_of(port,
+ struct vt8500_port,
+ uart);
+
+ vt8500_port->ier |= TCTS;
+ vt8500_write(port, vt8500_port->ier, VT8500_URIER);
+}
+
+static void handle_rx(struct uart_port *port)
+{
+ struct tty_struct *tty = tty_port_tty_get(&port->state->port);
+ if (!tty) {
+ /* Discard data: no tty available */
+ int count = (vt8500_read(port, VT8500_URFIDX) & 0x1f00) >> 8;
+ u16 ch;
+ while (count--)
+ ch = readw(port->membase + VT8500_RXFIFO);
+ return;
+ }
+
+ /*
+ * Handle overrun
+ */
+ if ((vt8500_read(port, VT8500_URISR) & RXOVER)) {
+ port->icount.overrun++;
+ tty_insert_flip_char(tty, 0, TTY_OVERRUN);
+ }
+
+ /* and now the main RX loop */
+ while (vt8500_read(port, VT8500_URFIDX) & 0x1f00) {
+ unsigned int c;
+ char flag = TTY_NORMAL;
+
+ c = readw(port->membase + VT8500_RXFIFO) & 0x3ff;
+
+ /* Mask conditions we're ignorning. */
+ c &= ~port->read_status_mask;
+
+ if (c & FER) {
+ port->icount.frame++;
+ flag = TTY_FRAME;
+ } else if (c & PER) {
+ port->icount.parity++;
+ flag = TTY_PARITY;
+ }
+ port->icount.rx++;
+
+ if (!uart_handle_sysrq_char(port, c))
+ tty_insert_flip_char(tty, c, flag);
+ }
+
+ tty_flip_buffer_push(tty);
+ tty_kref_put(tty);
+}
+
+static void handle_tx(struct uart_port *port)
+{
+ struct circ_buf *xmit = &port->state->xmit;
+
+ if (port->x_char) {
+ writeb(port->x_char, port->membase + VT8500_TXFIFO);
+ port->icount.tx++;
+ port->x_char = 0;
+ }
+ if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
+ vt8500_stop_tx(port);
+ return;
+ }
+
+ while ((vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16) {
+ if (uart_circ_empty(xmit))
+ break;
+
+ writeb(xmit->buf[xmit->tail], port->membase + VT8500_TXFIFO);
+
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ port->icount.tx++;
+ }
+
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ uart_write_wakeup(port);
+
+ if (uart_circ_empty(xmit))
+ vt8500_stop_tx(port);
+}
+
+static void vt8500_start_tx(struct uart_port *port)
+{
+ struct vt8500_port *vt8500_port = container_of(port,
+ struct vt8500_port,
+ uart);
+
+ vt8500_port->ier &= ~TX_FIFO_INTS;
+ vt8500_write(port, vt8500_port->ier, VT8500_URIER);
+ handle_tx(port);
+ vt8500_port->ier |= TX_FIFO_INTS;
+ vt8500_write(port, vt8500_port->ier, VT8500_URIER);
+}
+
+static void handle_delta_cts(struct uart_port *port)
+{
+ port->icount.cts++;
+ wake_up_interruptible(&port->state->port.delta_msr_wait);
+}
+
+static irqreturn_t vt8500_irq(int irq, void *dev_id)
+{
+ struct uart_port *port = dev_id;
+ unsigned long isr;
+
+ spin_lock(&port->lock);
+ isr = vt8500_read(port, VT8500_URISR);
+
+ /* Acknowledge active status bits */
+ vt8500_write(port, isr, VT8500_URISR);
+
+ if (isr & RX_FIFO_INTS)
+ handle_rx(port);
+ if (isr & TX_FIFO_INTS)
+ handle_tx(port);
+ if (isr & TCTS)
+ handle_delta_cts(port);
+
+ spin_unlock(&port->lock);
+
+ return IRQ_HANDLED;
+}
+
+static unsigned int vt8500_tx_empty(struct uart_port *port)
+{
+ return (vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16 ?
+ TIOCSER_TEMT : 0;
+}
+
+static unsigned int vt8500_get_mctrl(struct uart_port *port)
+{
+ unsigned int usr;
+
+ usr = vt8500_read(port, VT8500_URUSR);
+ if (usr & (1 << 4))
+ return TIOCM_CTS;
+ else
+ return 0;
+}
+
+static void vt8500_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+}
+
+static void vt8500_break_ctl(struct uart_port *port, int break_ctl)
+{
+ if (break_ctl)
+ vt8500_write(port, vt8500_read(port, VT8500_URLCR) | (1 << 9),
+ VT8500_URLCR);
+}
+
+static int vt8500_set_baud_rate(struct uart_port *port, unsigned int baud)
+{
+ unsigned long div;
+ unsigned int loops = 1000;
+
+ div = vt8500_read(port, VT8500_URDIV) & ~(0x3ff);
+
+ if (unlikely((baud < 900) || (baud > 921600)))
+ div |= 7;
+ else
+ div |= (921600 / baud) - 1;
+
+ while ((vt8500_read(port, VT8500_URUSR) & (1 << 5)) && --loops)
+ cpu_relax();
+ vt8500_write(port, div, VT8500_URDIV);
+
+ return baud;
+}
+
+static int vt8500_startup(struct uart_port *port)
+{
+ struct vt8500_port *vt8500_port =
+ container_of(port, struct vt8500_port, uart);
+ int ret;
+
+ snprintf(vt8500_port->name, sizeof(vt8500_port->name),
+ "vt8500_serial%d", port->line);
+
+ ret = request_irq(port->irq, vt8500_irq, IRQF_TRIGGER_HIGH,
+ vt8500_port->name, port);
+ if (unlikely(ret))
+ return ret;
+
+ vt8500_write(port, 0x03, VT8500_URLCR); /* enable TX & RX */
+
+ return 0;
+}
+
+static void vt8500_shutdown(struct uart_port *port)
+{
+ struct vt8500_port *vt8500_port =
+ container_of(port, struct vt8500_port, uart);
+
+ vt8500_port->ier = 0;
+
+ /* disable interrupts and FIFOs */
+ vt8500_write(&vt8500_port->uart, 0, VT8500_URIER);
+ vt8500_write(&vt8500_port->uart, 0x880, VT8500_URFCR);
+ free_irq(port->irq, port);
+}
+
+static void vt8500_set_termios(struct uart_port *port,
+ struct ktermios *termios,
+ struct ktermios *old)
+{
+ struct vt8500_port *vt8500_port =
+ container_of(port, struct vt8500_port, uart);
+ unsigned long flags;
+ unsigned int baud, lcr;
+ unsigned int loops = 1000;
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ /* calculate and set baud rate */
+ baud = uart_get_baud_rate(port, termios, old, 900, 921600);
+ baud = vt8500_set_baud_rate(port, baud);
+ if (tty_termios_baud_rate(termios))
+ tty_termios_encode_baud_rate(termios, baud, baud);
+
+ /* calculate parity */
+ lcr = vt8500_read(&vt8500_port->uart, VT8500_URLCR);
+ lcr &= ~((1 << 5) | (1 << 4));
+ if (termios->c_cflag & PARENB) {
+ lcr |= (1 << 4);
+ termios->c_cflag &= ~CMSPAR;
+ if (termios->c_cflag & PARODD)
+ lcr |= (1 << 5);
+ }
+
+ /* calculate bits per char */
+ lcr &= ~(1 << 2);
+ switch (termios->c_cflag & CSIZE) {
+ case CS7:
+ break;
+ case CS8:
+ default:
+ lcr |= (1 << 2);
+ termios->c_cflag &= ~CSIZE;
+ termios->c_cflag |= CS8;
+ break;
+ }
+
+ /* calculate stop bits */
+ lcr &= ~(1 << 3);
+ if (termios->c_cflag & CSTOPB)
+ lcr |= (1 << 3);
+
+ /* set parity, bits per char, and stop bit */
+ vt8500_write(&vt8500_port->uart, lcr, VT8500_URLCR);
+
+ /* Configure status bits to ignore based on termio flags. */
+ port->read_status_mask = 0;
+ if (termios->c_iflag & IGNPAR)
+ port->read_status_mask = FER | PER;
+
+ uart_update_timeout(port, termios->c_cflag, baud);
+
+ /* Reset FIFOs */
+ vt8500_write(&vt8500_port->uart, 0x88c, VT8500_URFCR);
+ while ((vt8500_read(&vt8500_port->uart, VT8500_URFCR) & 0xc)
+ && --loops)
+ cpu_relax();
+
+ /* Every possible FIFO-related interrupt */
+ vt8500_port->ier = RX_FIFO_INTS | TX_FIFO_INTS;
+
+ /*
+ * CTS flow control
+ */
+ if (UART_ENABLE_MS(&vt8500_port->uart, termios->c_cflag))
+ vt8500_port->ier |= TCTS;
+
+ vt8500_write(&vt8500_port->uart, 0x881, VT8500_URFCR);
+ vt8500_write(&vt8500_port->uart, vt8500_port->ier, VT8500_URIER);
+
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static const char *vt8500_type(struct uart_port *port)
+{
+ struct vt8500_port *vt8500_port =
+ container_of(port, struct vt8500_port, uart);
+ return vt8500_port->name;
+}
+
+static void vt8500_release_port(struct uart_port *port)
+{
+}
+
+static int vt8500_request_port(struct uart_port *port)
+{
+ return 0;
+}
+
+static void vt8500_config_port(struct uart_port *port, int flags)
+{
+ port->type = PORT_VT8500;
+}
+
+static int vt8500_verify_port(struct uart_port *port,
+ struct serial_struct *ser)
+{
+ if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_VT8500))
+ return -EINVAL;
+ if (unlikely(port->irq != ser->irq))
+ return -EINVAL;
+ return 0;
+}
+
+static struct vt8500_port *vt8500_uart_ports[4];
+static struct uart_driver vt8500_uart_driver;
+
+#ifdef CONFIG_SERIAL_VT8500_CONSOLE
+
+static inline void wait_for_xmitr(struct uart_port *port)
+{
+ unsigned int status, tmout = 10000;
+
+ /* Wait up to 10ms for the character(s) to be sent. */
+ do {
+ status = vt8500_read(port, VT8500_URFIDX);
+
+ if (--tmout == 0)
+ break;
+ udelay(1);
+ } while (status & 0x10);
+}
+
+static void vt8500_console_putchar(struct uart_port *port, int c)
+{
+ wait_for_xmitr(port);
+ writeb(c, port->membase + VT8500_TXFIFO);
+}
+
+static void vt8500_console_write(struct console *co, const char *s,
+ unsigned int count)
+{
+ struct vt8500_port *vt8500_port = vt8500_uart_ports[co->index];
+ unsigned long ier;
+
+ BUG_ON(co->index < 0 || co->index >= vt8500_uart_driver.nr);
+
+ ier = vt8500_read(&vt8500_port->uart, VT8500_URIER);
+ vt8500_write(&vt8500_port->uart, VT8500_URIER, 0);
+
+ uart_console_write(&vt8500_port->uart, s, count,
+ vt8500_console_putchar);
+
+ /*
+ * Finally, wait for transmitter to become empty
+ * and switch back to FIFO
+ */
+ wait_for_xmitr(&vt8500_port->uart);
+ vt8500_write(&vt8500_port->uart, VT8500_URIER, ier);
+}
+
+static int __init vt8500_console_setup(struct console *co, char *options)
+{
+ struct vt8500_port *vt8500_port;
+ int baud = 9600;
+ int bits = 8;
+ int parity = 'n';
+ int flow = 'n';
+
+ if (unlikely(co->index >= vt8500_uart_driver.nr || co->index < 0))
+ return -ENXIO;
+
+ vt8500_port = vt8500_uart_ports[co->index];
+
+ if (!vt8500_port)
+ return -ENODEV;
+
+ if (options)
+ uart_parse_options(options, &baud, &parity, &bits, &flow);
+
+ return uart_set_options(&vt8500_port->uart,
+ co, baud, parity, bits, flow);
+}
+
+static struct console vt8500_console = {
+ .name = "ttyWMT",
+ .write = vt8500_console_write,
+ .device = uart_console_device,
+ .setup = vt8500_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+ .data = &vt8500_uart_driver,
+};
+
+#define VT8500_CONSOLE (&vt8500_console)
+
+#else
+#define VT8500_CONSOLE NULL
+#endif
+
+static struct uart_ops vt8500_uart_pops = {
+ .tx_empty = vt8500_tx_empty,
+ .set_mctrl = vt8500_set_mctrl,
+ .get_mctrl = vt8500_get_mctrl,
+ .stop_tx = vt8500_stop_tx,
+ .start_tx = vt8500_start_tx,
+ .stop_rx = vt8500_stop_rx,
+ .enable_ms = vt8500_enable_ms,
+ .break_ctl = vt8500_break_ctl,
+ .startup = vt8500_startup,
+ .shutdown = vt8500_shutdown,
+ .set_termios = vt8500_set_termios,
+ .type = vt8500_type,
+ .release_port = vt8500_release_port,
+ .request_port = vt8500_request_port,
+ .config_port = vt8500_config_port,
+ .verify_port = vt8500_verify_port,
+};
+
+static struct uart_driver vt8500_uart_driver = {
+ .owner = THIS_MODULE,
+ .driver_name = "vt8500_serial",
+ .dev_name = "ttyWMT",
+ .nr = 6,
+ .cons = VT8500_CONSOLE,
+};
+
+static int __init vt8500_serial_probe(struct platform_device *pdev)
+{
+ struct vt8500_port *vt8500_port;
+ struct resource *mmres, *irqres;
+ int ret;
+
+ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (!mmres || !irqres)
+ return -ENODEV;
+
+ vt8500_port = kzalloc(sizeof(struct vt8500_port), GFP_KERNEL);
+ if (!vt8500_port)
+ return -ENOMEM;
+
+ vt8500_port->uart.type = PORT_VT8500;
+ vt8500_port->uart.iotype = UPIO_MEM;
+ vt8500_port->uart.mapbase = mmres->start;
+ vt8500_port->uart.irq = irqres->start;
+ vt8500_port->uart.fifosize = 16;
+ vt8500_port->uart.ops = &vt8500_uart_pops;
+ vt8500_port->uart.line = pdev->id;
+ vt8500_port->uart.dev = &pdev->dev;
+ vt8500_port->uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
+ vt8500_port->uart.uartclk = 24000000;
+
+ snprintf(vt8500_port->name, sizeof(vt8500_port->name),
+ "VT8500 UART%d", pdev->id);
+
+ vt8500_port->uart.membase = ioremap(mmres->start,
+ mmres->end - mmres->start + 1);
+ if (!vt8500_port->uart.membase) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ vt8500_uart_ports[pdev->id] = vt8500_port;
+
+ uart_add_one_port(&vt8500_uart_driver, &vt8500_port->uart);
+
+ platform_set_drvdata(pdev, vt8500_port);
+
+ return 0;
+
+err:
+ kfree(vt8500_port);
+ return ret;
+}
+
+static int __devexit vt8500_serial_remove(struct platform_device *pdev)
+{
+ struct vt8500_port *vt8500_port = platform_get_drvdata(pdev);
+
+ platform_set_drvdata(pdev, NULL);
+ uart_remove_one_port(&vt8500_uart_driver, &vt8500_port->uart);
+ kfree(vt8500_port);
+
+ return 0;
+}
+
+static struct platform_driver vt8500_platform_driver = {
+ .probe = vt8500_serial_probe,
+ .remove = vt8500_serial_remove,
+ .driver = {
+ .name = "vt8500_serial",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init vt8500_serial_init(void)
+{
+ int ret;
+
+ ret = uart_register_driver(&vt8500_uart_driver);
+ if (unlikely(ret))
+ return ret;
+
+ ret = platform_driver_register(&vt8500_platform_driver);
+
+ if (unlikely(ret))
+ uart_unregister_driver(&vt8500_uart_driver);
+
+ return ret;
+}
+
+static void __exit vt8500_serial_exit(void)
+{
+#ifdef CONFIG_SERIAL_VT8500_CONSOLE
+ unregister_console(&vt8500_console);
+#endif
+ platform_driver_unregister(&vt8500_platform_driver);
+ uart_unregister_driver(&vt8500_uart_driver);
+}
+
+module_init(vt8500_serial_init);
+module_exit(vt8500_serial_exit);
+
+MODULE_AUTHOR("Alexey Charkov <alchark@gmail.com>");
+MODULE_DESCRIPTION("Driver for vt8500 serial device");
+MODULE_LICENSE("GPL");
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2024-12-22 14:39:13 +0000