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-rw-r--r--drivers/serial/Kconfig45
-rw-r--r--drivers/serial/Makefile1
-rw-r--r--drivers/serial/amba-pl010.c2
-rw-r--r--drivers/serial/at91_serial.c463
-rw-r--r--drivers/serial/ioc4_serial.c9
-rw-r--r--drivers/serial/netx-serial.c749
-rw-r--r--drivers/serial/pxa.c1
-rw-r--r--drivers/serial/s3c2410.c145
-rw-r--r--drivers/serial/serial_lh7a40x.c13
-rw-r--r--drivers/serial/sunhv.c35
-rw-r--r--drivers/serial/sunsab.c12
-rw-r--r--drivers/serial/sunsu.c8
-rw-r--r--drivers/serial/sunzilog.c6
13 files changed, 1257 insertions, 232 deletions
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 7d22dc0478d..5b48ac22c9c 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -300,21 +300,22 @@ config SERIAL_AMBA_PL011_CONSOLE
kernel at boot time.)
config SERIAL_AT91
- bool "AT91RM9200 serial port support"
- depends on ARM && ARCH_AT91RM9200
+ bool "AT91RM9200 / AT91SAM9261 serial port support"
+ depends on ARM && (ARCH_AT91RM9200 || ARCH_AT91SAM9261)
select SERIAL_CORE
help
- This enables the driver for the on-chip UARTs of the AT91RM9200
- processor.
+ This enables the driver for the on-chip UARTs of the Atmel
+ AT91RM9200 and AT91SAM926 processor.
config SERIAL_AT91_CONSOLE
- bool "Support for console on AT91RM9200 serial port"
+ bool "Support for console on AT91RM9200 / AT91SAM9261 serial port"
depends on SERIAL_AT91=y
select SERIAL_CORE_CONSOLE
help
- Say Y here if you wish to use a UART on the AT91RM9200 as the system
- console (the system console is the device which receives all kernel
- messages and warnings and which allows logins in single user mode).
+ Say Y here if you wish to use a UART on the Atmel AT91RM9200 or
+ AT91SAM9261 as the system console (the system console is the device
+ which receives all kernel messages and warnings and which allows
+ logins in single user mode).
config SERIAL_AT91_TTYAT
bool "Install as device ttyAT0-4 instead of ttyS0-4"
@@ -353,21 +354,24 @@ config SERIAL_CLPS711X_CONSOLE
kernel at boot time.)
config SERIAL_S3C2410
- tristate "Samsung S3C2410 Serial port support"
+ tristate "Samsung S3C2410/S3C2440/S3C2442/S3C2412 Serial port support"
depends on ARM && ARCH_S3C2410
select SERIAL_CORE
help
- Support for the on-chip UARTs on the Samsung S3C2410X CPU,
+ Support for the on-chip UARTs on the Samsung S3C24XX series CPUs,
providing /dev/ttySAC0, 1 and 2 (note, some machines may not
provide all of these ports, depending on how the serial port
pins are configured.
+ Currently this driver supports the UARTS on the S3C2410, S3C2440,
+ S3C2442, S3C2412 and S3C2413 CPUs.
+
config SERIAL_S3C2410_CONSOLE
bool "Support for console on S3C2410 serial port"
depends on SERIAL_S3C2410=y
select SERIAL_CORE_CONSOLE
help
- Allow selection of the S3C2410 on-board serial ports for use as
+ Allow selection of the S3C24XX on-board serial ports for use as
an virtual console.
Even if you say Y here, the currently visible virtual console
@@ -936,4 +940,23 @@ config SERIAL_SGI_IOC3
If you have an SGI Altix with an IOC3 serial card,
say Y or M. Otherwise, say N.
+config SERIAL_NETX
+ bool "NetX serial port support"
+ depends on ARM && ARCH_NETX
+ select SERIAL_CORE
+ help
+ If you have a machine based on a Hilscher NetX SoC you
+ can enable its onboard serial port by enabling this option.
+
+ To compile this driver as a module, choose M here: the
+ module will be called netx-serial.
+
+config SERIAL_NETX_CONSOLE
+ bool "Console on NetX serial port"
+ depends on SERIAL_NETX
+ select SERIAL_CORE_CONSOLE
+ help
+ If you have enabled the serial port on the Motorola IMX
+ CPU you can make it the console by answering Y to this option.
+
endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 0a71bf68a03..927faee0362 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_SERIAL_VR41XX) += vr41xx_siu.o
obj-$(CONFIG_SERIAL_SGI_IOC4) += ioc4_serial.o
obj-$(CONFIG_SERIAL_SGI_IOC3) += ioc3_serial.o
obj-$(CONFIG_SERIAL_AT91) += at91_serial.o
+obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
diff --git a/drivers/serial/amba-pl010.c b/drivers/serial/amba-pl010.c
index 1631414000a..e920d196d0b 100644
--- a/drivers/serial/amba-pl010.c
+++ b/drivers/serial/amba-pl010.c
@@ -52,7 +52,7 @@
#include <asm/io.h>
-#define UART_NR 2
+#define UART_NR 8
#define SERIAL_AMBA_MAJOR 204
#define SERIAL_AMBA_MINOR 16
diff --git a/drivers/serial/at91_serial.c b/drivers/serial/at91_serial.c
index 6547fe0cef9..db5b25fafed 100644
--- a/drivers/serial/at91_serial.c
+++ b/drivers/serial/at91_serial.c
@@ -2,7 +2,6 @@
* linux/drivers/char/at91_serial.c
*
* Driver for Atmel AT91RM9200 Serial ports
- *
* Copyright (C) 2003 Rick Bronson
*
* Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
@@ -30,17 +29,19 @@
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/serial.h>
+#include <linux/clk.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/tty_flip.h>
+#include <linux/platform_device.h>
#include <asm/io.h>
#include <asm/arch/at91rm9200_usart.h>
-#include <asm/mach/serial_at91rm9200.h>
+#include <asm/arch/at91rm9200_pdc.h>
+#include <asm/mach/serial_at91.h>
#include <asm/arch/board.h>
-#include <asm/arch/pio.h>
-
+#include <asm/arch/system.h>
#if defined(CONFIG_SERIAL_AT91_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
#define SUPPORT_SYSRQ
@@ -67,7 +68,6 @@
#endif
-#define AT91_VA_BASE_DBGU ((unsigned long) AT91_VA_BASE_SYS + AT91_DBGU)
#define AT91_ISR_PASS_LIMIT 256
#define UART_PUT_CR(port,v) writel(v, (port)->membase + AT91_US_CR)
@@ -87,16 +87,33 @@
/* PDC registers */
#define UART_PUT_PTCR(port,v) writel(v, (port)->membase + AT91_PDC_PTCR)
+#define UART_GET_PTSR(port) readl((port)->membase + AT91_PDC_PTSR)
+
#define UART_PUT_RPR(port,v) writel(v, (port)->membase + AT91_PDC_RPR)
+#define UART_GET_RPR(port) readl((port)->membase + AT91_PDC_RPR)
#define UART_PUT_RCR(port,v) writel(v, (port)->membase + AT91_PDC_RCR)
-#define UART_GET_RCR(port) readl((port)->membase + AT91_PDC_RCR)
#define UART_PUT_RNPR(port,v) writel(v, (port)->membase + AT91_PDC_RNPR)
#define UART_PUT_RNCR(port,v) writel(v, (port)->membase + AT91_PDC_RNCR)
+#define UART_PUT_TPR(port,v) writel(v, (port)->membase + AT91_PDC_TPR)
+#define UART_PUT_TCR(port,v) writel(v, (port)->membase + AT91_PDC_TCR)
+//#define UART_PUT_TNPR(port,v) writel(v, (port)->membase + AT91_PDC_TNPR)
+//#define UART_PUT_TNCR(port,v) writel(v, (port)->membase + AT91_PDC_TNCR)
static int (*at91_open)(struct uart_port *);
static void (*at91_close)(struct uart_port *);
+/*
+ * We wrap our port structure around the generic uart_port.
+ */
+struct at91_uart_port {
+ struct uart_port uart; /* uart */
+ struct clk *clk; /* uart clock */
+ unsigned short suspended; /* is port suspended? */
+};
+
+static struct at91_uart_port at91_ports[AT91_NR_UART];
+
#ifdef SUPPORT_SYSRQ
static struct console at91_console;
#endif
@@ -115,16 +132,19 @@ static u_int at91_tx_empty(struct uart_port *port)
static void at91_set_mctrl(struct uart_port *port, u_int mctrl)
{
unsigned int control = 0;
+ unsigned int mode;
- /*
- * Errata #39: RTS0 is not internally connected to PA21. We need to drive
- * the pin manually.
- */
- if (port->mapbase == AT91_VA_BASE_US0) {
- if (mctrl & TIOCM_RTS)
- at91_sys_write(AT91_PIOA + PIO_CODR, AT91_PA21_RTS0);
- else
- at91_sys_write(AT91_PIOA + PIO_SODR, AT91_PA21_RTS0);
+ if (arch_identify() == ARCH_ID_AT91RM9200) {
+ /*
+ * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21.
+ * We need to drive the pin manually.
+ */
+ if (port->mapbase == AT91_BASE_US0) {
+ if (mctrl & TIOCM_RTS)
+ at91_sys_write(AT91_PIOA + PIO_CODR, AT91_PA21_RTS0);
+ else
+ at91_sys_write(AT91_PIOA + PIO_SODR, AT91_PA21_RTS0);
+ }
}
if (mctrl & TIOCM_RTS)
@@ -137,7 +157,15 @@ static void at91_set_mctrl(struct uart_port *port, u_int mctrl)
else
control |= AT91_US_DTRDIS;
- UART_PUT_CR(port,control);
+ UART_PUT_CR(port, control);
+
+ /* Local loopback mode? */
+ mode = UART_GET_MR(port) & ~AT91_US_CHMODE;
+ if (mctrl & TIOCM_LOOP)
+ mode |= AT91_US_CHMODE_LOC_LOOP;
+ else
+ mode |= AT91_US_CHMODE_NORMAL;
+ UART_PUT_MR(port, mode);
}
/*
@@ -169,8 +197,9 @@ static u_int at91_get_mctrl(struct uart_port *port)
*/
static void at91_stop_tx(struct uart_port *port)
{
+ struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
+
UART_PUT_IDR(port, AT91_US_TXRDY);
- port->read_status_mask &= ~AT91_US_TXRDY;
}
/*
@@ -178,7 +207,8 @@ static void at91_stop_tx(struct uart_port *port)
*/
static void at91_start_tx(struct uart_port *port)
{
- port->read_status_mask |= AT91_US_TXRDY;
+ struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
+
UART_PUT_IER(port, AT91_US_TXRDY);
}
@@ -187,6 +217,8 @@ static void at91_start_tx(struct uart_port *port)
*/
static void at91_stop_rx(struct uart_port *port)
{
+ struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
+
UART_PUT_IDR(port, AT91_US_RXRDY);
}
@@ -195,7 +227,6 @@ static void at91_stop_rx(struct uart_port *port)
*/
static void at91_enable_ms(struct uart_port *port)
{
- port->read_status_mask |= (AT91_US_RIIC | AT91_US_DSRIC | AT91_US_DCDIC | AT91_US_CTSIC);
UART_PUT_IER(port, AT91_US_RIIC | AT91_US_DSRIC | AT91_US_DCDIC | AT91_US_CTSIC);
}
@@ -218,8 +249,8 @@ static void at91_rx_chars(struct uart_port *port, struct pt_regs *regs)
struct tty_struct *tty = port->info->tty;
unsigned int status, ch, flg;
- status = UART_GET_CSR(port) & port->read_status_mask;
- while (status & (AT91_US_RXRDY)) {
+ status = UART_GET_CSR(port);
+ while (status & AT91_US_RXRDY) {
ch = UART_GET_CHAR(port);
port->icount.rx++;
@@ -230,40 +261,38 @@ static void at91_rx_chars(struct uart_port *port, struct pt_regs *regs)
* note that the error handling code is
* out of the main execution path
*/
- if (unlikely(status & (AT91_US_PARE | AT91_US_FRAME | AT91_US_OVRE))) {
+ if (unlikely(status & (AT91_US_PARE | AT91_US_FRAME | AT91_US_OVRE | AT91_US_RXBRK))) {
UART_PUT_CR(port, AT91_US_RSTSTA); /* clear error */
- if (status & (AT91_US_PARE))
+ if (status & AT91_US_RXBRK) {
+ status &= ~(AT91_US_PARE | AT91_US_FRAME); /* ignore side-effect */
+ port->icount.brk++;
+ if (uart_handle_break(port))
+ goto ignore_char;
+ }
+ if (status & AT91_US_PARE)
port->icount.parity++;
- if (status & (AT91_US_FRAME))
+ if (status & AT91_US_FRAME)
port->icount.frame++;
- if (status & (AT91_US_OVRE))
+ if (status & AT91_US_OVRE)
port->icount.overrun++;
- if (status & AT91_US_PARE)
+ status &= port->read_status_mask;
+
+ if (status & AT91_US_RXBRK)
+ flg = TTY_BREAK;
+ else if (status & AT91_US_PARE)
flg = TTY_PARITY;
else if (status & AT91_US_FRAME)
flg = TTY_FRAME;
- if (status & AT91_US_OVRE) {
- /*
- * overrun does *not* affect the character
- * we read from the FIFO
- */
- tty_insert_flip_char(tty, ch, flg);
- ch = 0;
- flg = TTY_OVERRUN;
- }
-#ifdef SUPPORT_SYSRQ
- port->sysrq = 0;
-#endif
}
if (uart_handle_sysrq_char(port, ch, regs))
goto ignore_char;
- tty_insert_flip_char(tty, ch, flg);
+ uart_insert_char(port, status, AT91_US_OVRE, ch, flg);
ignore_char:
- status = UART_GET_CSR(port) & port->read_status_mask;
+ status = UART_GET_CSR(port);
}
tty_flip_buffer_push(tty);
@@ -308,40 +337,35 @@ static void at91_tx_chars(struct uart_port *port)
static irqreturn_t at91_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
struct uart_port *port = dev_id;
+ struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
unsigned int status, pending, pass_counter = 0;
status = UART_GET_CSR(port);
- pending = status & port->read_status_mask;
- if (pending) {
- do {
- if (pending & AT91_US_RXRDY)
- at91_rx_chars(port, regs);
-
- /* Clear the relevent break bits */
- if (pending & AT91_US_RXBRK) {
- UART_PUT_CR(port, AT91_US_RSTSTA);
- port->icount.brk++;
- uart_handle_break(port);
- }
+ pending = status & UART_GET_IMR(port);
+ while (pending) {
+ /* Interrupt receive */
+ if (pending & AT91_US_RXRDY)
+ at91_rx_chars(port, regs);
+
+ // TODO: All reads to CSR will clear these interrupts!
+ if (pending & AT91_US_RIIC) port->icount.rng++;
+ if (pending & AT91_US_DSRIC) port->icount.dsr++;
+ if (pending & AT91_US_DCDIC)
+ uart_handle_dcd_change(port, !(status & AT91_US_DCD));
+ if (pending & AT91_US_CTSIC)
+ uart_handle_cts_change(port, !(status & AT91_US_CTS));
+ if (pending & (AT91_US_RIIC | AT91_US_DSRIC | AT91_US_DCDIC | AT91_US_CTSIC))
+ wake_up_interruptible(&port->info->delta_msr_wait);
+
+ /* Interrupt transmit */
+ if (pending & AT91_US_TXRDY)
+ at91_tx_chars(port);
+
+ if (pass_counter++ > AT91_ISR_PASS_LIMIT)
+ break;
- // TODO: All reads to CSR will clear these interrupts!
- if (pending & AT91_US_RIIC) port->icount.rng++;
- if (pending & AT91_US_DSRIC) port->icount.dsr++;
- if (pending & AT91_US_DCDIC)
- uart_handle_dcd_change(port, !(status & AT91_US_DCD));
- if (pending & AT91_US_CTSIC)
- uart_handle_cts_change(port, !(status & AT91_US_CTS));
- if (pending & (AT91_US_RIIC | AT91_US_DSRIC | AT91_US_DCDIC | AT91_US_CTSIC))
- wake_up_interruptible(&port->info->delta_msr_wait);
-
- if (pending & AT91_US_TXRDY)
- at91_tx_chars(port);
- if (pass_counter++ > AT91_ISR_PASS_LIMIT)
- break;
-
- status = UART_GET_CSR(port);
- pending = status & port->read_status_mask;
- } while (pending);
+ status = UART_GET_CSR(port);
+ pending = status & UART_GET_IMR(port);
}
return IRQ_HANDLED;
}
@@ -351,6 +375,7 @@ static irqreturn_t at91_interrupt(int irq, void *dev_id, struct pt_regs *regs)
*/
static int at91_startup(struct uart_port *port)
{
+ struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
int retval;
/*
@@ -381,14 +406,14 @@ static int at91_startup(struct uart_port *port)
}
}
- port->read_status_mask = AT91_US_RXRDY | AT91_US_TXRDY | AT91_US_OVRE
- | AT91_US_FRAME | AT91_US_PARE | AT91_US_RXBRK;
/*
* Finally, enable the serial port
*/
UART_PUT_CR(port, AT91_US_RSTSTA | AT91_US_RSTRX);
UART_PUT_CR(port, AT91_US_TXEN | AT91_US_RXEN); /* enable xmit & rcvr */
- UART_PUT_IER(port, AT91_US_RXRDY); /* do receive only */
+
+ UART_PUT_IER(port, AT91_US_RXRDY); /* enable receive only */
+
return 0;
}
@@ -397,6 +422,8 @@ static int at91_startup(struct uart_port *port)
*/
static void at91_shutdown(struct uart_port *port)
{
+ struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
+
/*
* Disable all interrupts, port and break condition.
*/
@@ -421,21 +448,22 @@ static void at91_shutdown(struct uart_port *port)
*/
static void at91_serial_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
{
+ struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
+
switch (state) {
case 0:
/*
* Enable the peripheral clock for this serial port.
* This is called on uart_open() or a resume event.
*/
- at91_sys_write(AT91_PMC_PCER, 1 << port->irq);
+ clk_enable(at91_port->clk);
break;
case 3:
/*
* Disable the peripheral clock for this serial port.
* This is called on uart_close() or a suspend event.
*/
- if (port->irq != AT91_ID_SYS) /* is this a shared clock? */
- at91_sys_write(AT91_PMC_PCDR, 1 << port->irq);
+ clk_disable(at91_port->clk);
break;
default:
printk(KERN_ERR "at91_serial: unknown pm %d\n", state);
@@ -494,9 +522,9 @@ static void at91_set_termios(struct uart_port *port, struct termios * termios, s
spin_lock_irqsave(&port->lock, flags);
- port->read_status_mask |= AT91_US_OVRE;
+ port->read_status_mask = AT91_US_OVRE;
if (termios->c_iflag & INPCK)
- port->read_status_mask |= AT91_US_FRAME | AT91_US_PARE;
+ port->read_status_mask |= (AT91_US_FRAME | AT91_US_PARE);
if (termios->c_iflag & (BRKINT | PARMRK))
port->read_status_mask |= AT91_US_RXBRK;
@@ -552,7 +580,7 @@ static void at91_set_termios(struct uart_port *port, struct termios * termios, s
*/
static const char *at91_type(struct uart_port *port)
{
- return (port->type == PORT_AT91RM9200) ? "AT91_SERIAL" : NULL;
+ return (port->type == PORT_AT91) ? "AT91_SERIAL" : NULL;
}
/*
@@ -560,8 +588,15 @@ static const char *at91_type(struct uart_port *port)
*/
static void at91_release_port(struct uart_port *port)
{
- release_mem_region(port->mapbase,
- (port->mapbase == AT91_VA_BASE_DBGU) ? 512 : SZ_16K);
+ struct platform_device *pdev = to_platform_device(port->dev);
+ int size = pdev->resource[0].end - pdev->resource[0].start + 1;
+
+ release_mem_region(port->mapbase, size);
+
+ if (port->flags & UPF_IOREMAP) {
+ iounmap(port->membase);
+ port->membase = NULL;
+ }
}
/*
@@ -569,10 +604,21 @@ static void at91_release_port(struct uart_port *port)
*/
static int at91_request_port(struct uart_port *port)
{
- return request_mem_region(port->mapbase,
- (port->mapbase == AT91_VA_BASE_DBGU) ? 512 : SZ_16K,
- "at91_serial") != NULL ? 0 : -EBUSY;
+ struct platform_device *pdev = to_platform_device(port->dev);
+ int size = pdev->resource[0].end - pdev->resource[0].start + 1;
+
+ if (!request_mem_region(port->mapbase, size, "at91_serial"))
+ return -EBUSY;
+
+ if (port->flags & UPF_IOREMAP) {
+ port->membase = ioremap(port->mapbase, size);
+ if (port->membase == NULL) {
+ release_mem_region(port->mapbase, size);
+ return -ENOMEM;
+ }
+ }
+ return 0;
}
/*
@@ -581,7 +627,7 @@ static int at91_request_port(struct uart_port *port)
static void at91_config_port(struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE) {
- port->type = PORT_AT91RM9200;
+ port->type = PORT_AT91;
at91_request_port(port);
}
}
@@ -592,7 +638,7 @@ static void at91_config_port(struct uart_port *port, int flags)
static int at91_verify_port(struct uart_port *port, struct serial_struct *ser)
{
int ret = 0;
- if (ser->type != PORT_UNKNOWN && ser->type != PORT_AT91RM9200)
+ if (ser->type != PORT_UNKNOWN && ser->type != PORT_AT91)
ret = -EINVAL;
if (port->irq != ser->irq)
ret = -EINVAL;
@@ -624,33 +670,47 @@ static struct uart_ops at91_pops = {
.type = at91_type,
.release_port = at91_release_port,
.request_port = at91_request_port,
- .config_port = at91_config_port,
- .verify_port = at91_verify_port,
+ .config_port = at91_config_port,
+ .verify_port = at91_verify_port,
.pm = at91_serial_pm,
};
-static struct uart_port at91_ports[AT91_NR_UART];
-
-void __init at91_init_ports(void)
+/*
+ * Configure the port from the platform device resource info.
+ */
+static void __devinit at91_init_port(struct at91_uart_port *at91_port, struct platform_device *pdev)
{
- static int first = 1;
- int i;
-
- if (!first)
- return;
- first = 0;
+ struct uart_port *port = &at91_port->uart;
+ struct at91_uart_data *data = pdev->dev.platform_data;
+
+ port->iotype = UPIO_MEM;
+ port->flags = UPF_BOOT_AUTOCONF;
+ port->ops = &at91_pops;
+ port->fifosize = 1;
+ port->line = pdev->id;
+ port->dev = &pdev->dev;
+
+ port->mapbase = pdev->resource[0].start;
+ port->irq = pdev->resource[1].start;
+
+ if (port->mapbase == AT91_VA_BASE_SYS + AT91_DBGU) /* Part of system perpherals - already mapped */
+ port->membase = (void __iomem *) port->mapbase;
+ else {
+ port->flags |= UPF_IOREMAP;
+ port->membase = NULL;
+ }
- for (i = 0; i < AT91_NR_UART; i++) {
- at91_ports[i].iotype = UPIO_MEM;
- at91_ports[i].flags = UPF_BOOT_AUTOCONF;
- at91_ports[i].uartclk = at91_master_clock;
- at91_ports[i].ops = &at91_pops;
- at91_ports[i].fifosize = 1;
- at91_ports[i].line = i;
- }
+ if (!at91_port->clk) { /* for console, the clock could already be configured */
+ at91_port->clk = clk_get(&pdev->dev, "usart");
+ clk_enable(at91_port->clk);
+ port->uartclk = clk_get_rate(at91_port->clk);
+ }
}
-void __init at91_register_uart_fns(struct at91rm9200_port_fns *fns)
+/*
+ * Register board-specific modem-control line handlers.
+ */
+void __init at91_register_uart_fns(struct at91_port_fns *fns)
{
if (fns->enable_ms)
at91_pops.enable_ms = fns->enable_ms;
@@ -664,51 +724,6 @@ void __init at91_register_uart_fns(struct at91rm9200_port_fns *fns)
at91_pops.set_wake = fns->set_wake;
}
-/*
- * Setup ports.
- */
-void __init at91_register_uart(int idx, int port)
-{
- if ((idx < 0) || (idx >= AT91_NR_UART)) {
- printk(KERN_ERR "%s: bad index number %d\n", __FUNCTION__, idx);
- return;
- }
-
- switch (port) {
- case 0:
- at91_ports[idx].membase = (void __iomem *) AT91_VA_BASE_US0;
- at91_ports[idx].mapbase = AT91_VA_BASE_US0;
- at91_ports[idx].irq = AT91_ID_US0;
- AT91_CfgPIO_USART0();
- break;
- case 1:
- at91_ports[idx].membase = (void __iomem *) AT91_VA_BASE_US1;
- at91_ports[idx].mapbase = AT91_VA_BASE_US1;
- at91_ports[idx].irq = AT91_ID_US1;
- AT91_CfgPIO_USART1();
- break;
- case 2:
- at91_ports[idx].membase = (void __iomem *) AT91_VA_BASE_US2;
- at91_ports[idx].mapbase = AT91_VA_BASE_US2;
- at91_ports[idx].irq = AT91_ID_US2;
- AT91_CfgPIO_USART2();
- break;
- case 3:
- at91_ports[idx].membase = (void __iomem *) AT91_VA_BASE_US3;
- at91_ports[idx].mapbase = AT91_VA_BASE_US3;
- at91_ports[idx].irq = AT91_ID_US3;
- AT91_CfgPIO_USART3();
- break;
- case 4:
- at91_ports[idx].membase = (void __iomem *) AT91_VA_BASE_DBGU;
- at91_ports[idx].mapbase = AT91_VA_BASE_DBGU;
- at91_ports[idx].irq = AT91_ID_SYS;
- AT91_CfgPIO_DBGU();
- break;
- default:
- printk(KERN_ERR "%s : bad port number %d\n", __FUNCTION__, port);
- }
-}
#ifdef CONFIG_SERIAL_AT91_CONSOLE
static void at91_console_putchar(struct uart_port *port, int ch)
@@ -723,7 +738,7 @@ static void at91_console_putchar(struct uart_port *port, int ch)
*/
static void at91_console_write(struct console *co, const char *s, u_int count)
{
- struct uart_port *port = at91_ports + co->index;
+ struct uart_port *port = &at91_ports[co->index].uart;
unsigned int status, imr;
/*
@@ -778,23 +793,15 @@ static void __init at91_console_get_options(struct uart_port *port, int *baud, i
static int __init at91_console_setup(struct console *co, char *options)
{
- struct uart_port *port;
+ struct uart_port *port = &at91_ports[co->index].uart;
int baud = 115200;
int bits = 8;
int parity = 'n';
int flow = 'n';
- /*
- * Check whether an invalid uart number has been specified, and
- * if so, search for the first available port that does have
- * console support.
- */
- port = uart_get_console(at91_ports, AT91_NR_UART, co);
+ if (port->membase == 0) /* Port not initialized yet - delay setup */
+ return -ENODEV;
- /*
- * Enable the serial console, in-case bootloader did not do it.
- */
- at91_sys_write(AT91_PMC_PCER, 1 << port->irq); /* enable clock */
UART_PUT_IDR(port, -1); /* disable interrupts */
UART_PUT_CR(port, AT91_US_RSTSTA | AT91_US_RSTRX);
UART_PUT_CR(port, AT91_US_TXEN | AT91_US_RXEN);
@@ -821,23 +828,40 @@ static struct console at91_console = {
#define AT91_CONSOLE_DEVICE &at91_console
-static int __init at91_console_init(void)
+/*
+ * Early console initialization (before VM subsystem initialized).
+ */
+static int __init at91_console_init(void)
{
- at91_init_ports();
+ if (at91_default_console_device) {
+ add_preferred_console(AT91_DEVICENAME, at91_default_console_device->id, NULL);
+ at91_init_port(&(at91_ports[at91_default_console_device->id]), at91_default_console_device);
+ register_console(&at91_console);
+ }
- at91_console.index = at91_console_port;
- register_console(&at91_console);
return 0;
}
console_initcall(at91_console_init);
+/*
+ * Late console initialization.
+ */
+static int __init at91_late_console_init(void)
+{
+ if (at91_default_console_device && !(at91_console.flags & CON_ENABLED))
+ register_console(&at91_console);
+
+ return 0;
+}
+core_initcall(at91_late_console_init);
+
#else
#define AT91_CONSOLE_DEVICE NULL
#endif
static struct uart_driver at91_uart = {
.owner = THIS_MODULE,
- .driver_name = AT91_DEVICENAME,
+ .driver_name = "at91_serial",
.dev_name = AT91_DEVICENAME,
.devfs_name = AT91_DEVICENAME,
.major = SERIAL_AT91_MAJOR,
@@ -846,33 +870,106 @@ static struct uart_driver at91_uart = {
.cons = AT91_CONSOLE_DEVICE,
};
-static int __init at91_serial_init(void)
+#ifdef CONFIG_PM
+static int at91_serial_suspend(struct platform_device *pdev, pm_message_t state)
{
- int ret, i;
+ struct uart_port *port = platform_get_drvdata(pdev);
+ struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
+
+ if (device_may_wakeup(&pdev->dev) && !at91_suspend_entering_slow_clock())
+ enable_irq_wake(port->irq);
+ else {
+ disable_irq_wake(port->irq);
+ uart_suspend_port(&at91_uart, port);
+ at91_port->suspended = 1;
+ }
- at91_init_ports();
+ return 0;
+}
- ret = uart_register_driver(&at91_uart);
- if (ret)
- return ret;
+static int at91_serial_resume(struct platform_device *pdev)
+{
+ struct uart_port *port = platform_get_drvdata(pdev);
+ struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
- for (i = 0; i < AT91_NR_UART; i++) {
- if (at91_serial_map[i] >= 0)
- uart_add_one_port(&at91_uart, &at91_ports[i]);
+ if (at91_port->suspended) {
+ uart_resume_port(&at91_uart, port);
+ at91_port->suspended = 0;
}
return 0;
}
+#else
+#define at91_serial_suspend NULL
+#define at91_serial_resume NULL
+#endif
-static void __exit at91_serial_exit(void)
+static int __devinit at91_serial_probe(struct platform_device *pdev)
{
- int i;
+ struct at91_uart_port *port;
+ int ret;
- for (i = 0; i < AT91_NR_UART; i++) {
- if (at91_serial_map[i] >= 0)
- uart_remove_one_port(&at91_uart, &at91_ports[i]);
- }
+ port = &at91_ports[pdev->id];
+ at91_init_port(port, pdev);
+ ret = uart_add_one_port(&at91_uart, &port->uart);
+ if (!ret) {
+ device_init_wakeup(&pdev->dev, 1);
+ platform_set_drvdata(pdev, port);
+ }
+
+ return ret;
+}
+
+static int __devexit at91_serial_remove(struct platform_device *pdev)
+{
+ struct uart_port *port = platform_get_drvdata(pdev);
+ struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
+ int ret = 0;
+
+ clk_disable(at91_port->clk);
+ clk_put(at91_port->clk);
+
+ device_init_wakeup(&pdev->dev, 0);
+ platform_set_drvdata(pdev, NULL);
+
+ if (port) {
+ ret = uart_remove_one_port(&at91_uart, port);
+ kfree(port);
+ }
+
+ return ret;
+}
+
+static struct platform_driver at91_serial_driver = {
+ .probe = at91_serial_probe,
+ .remove = __devexit_p(at91_serial_remove),
+ .suspend = at91_serial_suspend,
+ .resume = at91_serial_resume,
+ .driver = {
+ .name = "at91_usart",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init at91_serial_init(void)
+{
+ int ret;
+
+ ret = uart_register_driver(&at91_uart);
+ if (ret)
+ return ret;
+
+ ret = platform_driver_register(&at91_serial_driver);
+ if (ret)
+ uart_unregister_driver(&at91_uart);
+
+ return ret;
+}
+
+static void __exit at91_serial_exit(void)
+{
+ platform_driver_unregister(&at91_serial_driver);
uart_unregister_driver(&at91_uart);
}
diff --git a/drivers/serial/ioc4_serial.c b/drivers/serial/ioc4_serial.c
index c620209d7b9..717e47bbd78 100644
--- a/drivers/serial/ioc4_serial.c
+++ b/drivers/serial/ioc4_serial.c
@@ -2646,7 +2646,10 @@ static int ioc4_serial_remove_one(struct ioc4_driver_data *idd)
struct ioc4_port *port;
struct ioc4_soft *soft;
+ /* If serial driver did not attach, don't try to detach */
control = idd->idd_serial_data;
+ if (!control)
+ return 0;
for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
for (port_type = UART_PORT_MIN;
@@ -2778,6 +2781,12 @@ ioc4_serial_attach_one(struct ioc4_driver_data *idd)
DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __FUNCTION__, idd->idd_pdev,
idd->idd_pci_id));
+ /* PCI-RT does not bring out serial connections.
+ * Do not attach to this particular IOC4.
+ */
+ if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
+ return 0;
+
/* request serial registers */
tmp_addr1 = idd->idd_bar0 + IOC4_SERIAL_OFFSET;
diff --git a/drivers/serial/netx-serial.c b/drivers/serial/netx-serial.c
new file mode 100644
index 00000000000..c1adc9e4b23
--- /dev/null
+++ b/drivers/serial/netx-serial.c
@@ -0,0 +1,749 @@
+/*
+ * drivers/serial/netx-serial.c
+ *
+ * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/config.h>
+
+#if defined(CONFIG_SERIAL_NETX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/sysrq.h>
+#include <linux/platform_device.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/hardware.h>
+#include <asm/arch/netx-regs.h>
+
+/* We've been assigned a range on the "Low-density serial ports" major */
+#define SERIAL_NX_MAJOR 204
+#define MINOR_START 170
+
+#ifdef CONFIG_SERIAL_NETX_CONSOLE
+
+enum uart_regs {
+ UART_DR = 0x00,
+ UART_SR = 0x04,
+ UART_LINE_CR = 0x08,
+ UART_BAUDDIV_MSB = 0x0c,
+ UART_BAUDDIV_LSB = 0x10,
+ UART_CR = 0x14,
+ UART_FR = 0x18,
+ UART_IIR = 0x1c,
+ UART_ILPR = 0x20,
+ UART_RTS_CR = 0x24,
+ UART_RTS_LEAD = 0x28,
+ UART_RTS_TRAIL = 0x2c,
+ UART_DRV_ENABLE = 0x30,
+ UART_BRM_CR = 0x34,
+ UART_RXFIFO_IRQLEVEL = 0x38,
+ UART_TXFIFO_IRQLEVEL = 0x3c,
+};
+
+#define SR_FE (1<<0)
+#define SR_PE (1<<1)
+#define SR_BE (1<<2)
+#define SR_OE (1<<3)
+
+#define LINE_CR_BRK (1<<0)
+#define LINE_CR_PEN (1<<1)
+#define LINE_CR_EPS (1<<2)
+#define LINE_CR_STP2 (1<<3)
+#define LINE_CR_FEN (1<<4)
+#define LINE_CR_5BIT (0<<5)
+#define LINE_CR_6BIT (1<<5)
+#define LINE_CR_7BIT (2<<5)
+#define LINE_CR_8BIT (3<<5)
+#define LINE_CR_BITS_MASK (3<<5)
+
+#define CR_UART_EN (1<<0)
+#define CR_SIREN (1<<1)
+#define CR_SIRLP (1<<2)
+#define CR_MSIE (1<<3)
+#define CR_RIE (1<<4)
+#define CR_TIE (1<<5)
+#define CR_RTIE (1<<6)
+#define CR_LBE (1<<7)
+
+#define FR_CTS (1<<0)
+#define FR_DSR (1<<1)
+#define FR_DCD (1<<2)
+#define FR_BUSY (1<<3)
+#define FR_RXFE (1<<4)
+#define FR_TXFF (1<<5)
+#define FR_RXFF (1<<6)
+#define FR_TXFE (1<<7)
+
+#define IIR_MIS (1<<0)
+#define IIR_RIS (1<<1)
+#define IIR_TIS (1<<2)
+#define IIR_RTIS (1<<3)
+#define IIR_MASK 0xf
+
+#define RTS_CR_AUTO (1<<0)
+#define RTS_CR_RTS (1<<1)
+#define RTS_CR_COUNT (1<<2)
+#define RTS_CR_MOD2 (1<<3)
+#define RTS_CR_RTS_POL (1<<4)
+#define RTS_CR_CTS_CTR (1<<5)
+#define RTS_CR_CTS_POL (1<<6)
+#define RTS_CR_STICK (1<<7)
+
+#define UART_PORT_SIZE 0x40
+#define DRIVER_NAME "netx-uart"
+
+struct netx_port {
+ struct uart_port port;
+};
+
+static void netx_stop_tx(struct uart_port *port)
+{
+ unsigned int val;
+ val = readl(port->membase + UART_CR);
+ writel(val & ~CR_TIE, port->membase + UART_CR);
+}
+
+static void netx_stop_rx(struct uart_port *port)
+{
+ unsigned int val;
+ val = readl(port->membase + UART_CR);
+ writel(val & ~CR_RIE, port->membase + UART_CR);
+}
+
+static void netx_enable_ms(struct uart_port *port)
+{
+ unsigned int val;
+ val = readl(port->membase + UART_CR);
+ writel(val | CR_MSIE, port->membase + UART_CR);
+}
+
+static inline void netx_transmit_buffer(struct uart_port *port)
+{
+ struct circ_buf *xmit = &port->info->xmit;
+
+ if (port->x_char) {
+ writel(port->x_char, port->membase + UART_DR);
+ port->icount.tx++;
+ port->x_char = 0;
+ return;
+ }
+
+ if (uart_tx_stopped(port) || uart_circ_empty(xmit)) {
+ netx_stop_tx(port);
+ return;
+ }
+
+ do {
+ /* send xmit->buf[xmit->tail]
+ * out the port here */
+ writel(xmit->buf[xmit->tail], port->membase + UART_DR);
+ xmit->tail = (xmit->tail + 1) &
+ (UART_XMIT_SIZE - 1);
+ port->icount.tx++;
+ if (uart_circ_empty(xmit))
+ break;
+ } while (!(readl(port->membase + UART_FR) & FR_TXFF));
+
+ if (uart_circ_empty(xmit))
+ netx_stop_tx(port);
+}
+
+static void netx_start_tx(struct uart_port *port)
+{
+ writel(
+ readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR);
+
+ if (!(readl(port->membase + UART_FR) & FR_TXFF))
+ netx_transmit_buffer(port);
+}
+
+static unsigned int netx_tx_empty(struct uart_port *port)
+{
+ return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT;
+}
+
+static void netx_txint(struct uart_port *port)
+{
+ struct circ_buf *xmit = &port->info->xmit;
+
+ if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
+ netx_stop_tx(port);
+ return;
+ }
+
+ netx_transmit_buffer(port);
+
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ uart_write_wakeup(port);
+}
+
+static void netx_rxint(struct uart_port *port, struct pt_regs *regs)
+{
+ unsigned char rx, flg, status;
+ struct tty_struct *tty = port->info->tty;
+
+ while (!(readl(port->membase + UART_FR) & FR_RXFE)) {
+ rx = readl(port->membase + UART_DR);
+ flg = TTY_NORMAL;
+ port->icount.rx++;
+ status = readl(port->membase + UART_SR);
+ if (status & SR_BE) {
+ writel(0, port->membase + UART_SR);
+ if (uart_handle_break(port))
+ continue;
+ }
+
+ if (unlikely(status & (SR_FE | SR_PE | SR_OE))) {
+
+ if (status & SR_PE)
+ port->icount.parity++;
+ else if (status & SR_FE)
+ port->icount.frame++;
+ if (status & SR_OE)
+ port->icount.overrun++;
+
+ status &= port->read_status_mask;
+
+ if (status & SR_BE)
+ flg = TTY_BREAK;
+ else if (status & SR_PE)
+ flg = TTY_PARITY;
+ else if (status & SR_FE)
+ flg = TTY_FRAME;
+ }
+
+ if (uart_handle_sysrq_char(port, rx, regs))
+ continue;
+
+ uart_insert_char(port, status, SR_OE, rx, flg);
+ }
+
+ tty_flip_buffer_push(tty);
+ return;
+}
+
+static irqreturn_t netx_int(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct uart_port *port = (struct uart_port *)dev_id;
+ unsigned long flags;
+ unsigned char status;
+
+ spin_lock_irqsave(&port->lock,flags);
+
+ status = readl(port->membase + UART_IIR) & IIR_MASK;
+ while (status) {
+ if (status & IIR_RIS)
+ netx_rxint(port, regs);
+ if (status & IIR_TIS)
+ netx_txint(port);
+ if (status & IIR_MIS) {
+ if (readl(port->membase + UART_FR) & FR_CTS)
+ uart_handle_cts_change(port, 1);
+ else
+ uart_handle_cts_change(port, 0);
+ }
+ writel(0, port->membase + UART_IIR);
+ status = readl(port->membase + UART_IIR) & IIR_MASK;
+ }
+
+ spin_unlock_irqrestore(&port->lock,flags);
+ return IRQ_HANDLED;
+}
+
+static unsigned int netx_get_mctrl(struct uart_port *port)
+{
+ unsigned int ret = TIOCM_DSR | TIOCM_CAR;
+
+ if (readl(port->membase + UART_FR) & FR_CTS)
+ ret |= TIOCM_CTS;
+
+ return ret;
+}
+
+static void netx_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+ unsigned int val;
+
+ if (mctrl & TIOCM_RTS) {
+ val = readl(port->membase + UART_RTS_CR);
+ writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR);
+ }
+}
+
+static void netx_break_ctl(struct uart_port *port, int break_state)
+{
+ unsigned int line_cr;
+ spin_lock_irq(&port->lock);
+
+ line_cr = readl(port->membase + UART_LINE_CR);
+ if (break_state != 0)
+ line_cr |= LINE_CR_BRK;
+ else
+ line_cr &= ~LINE_CR_BRK;
+ writel(line_cr, port->membase + UART_LINE_CR);
+
+ spin_unlock_irq(&port->lock);
+}
+
+static int netx_startup(struct uart_port *port)
+{
+ int ret;
+
+ ret = request_irq(port->irq, netx_int, 0,
+ DRIVER_NAME, port);
+ if (ret) {
+ dev_err(port->dev, "unable to grab irq%d\n",port->irq);
+ goto exit;
+ }
+
+ writel(readl(port->membase + UART_LINE_CR) | LINE_CR_FEN,
+ port->membase + UART_LINE_CR);
+
+ writel(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE | CR_UART_EN,
+ port->membase + UART_CR);
+
+exit:
+ return ret;
+}
+
+static void netx_shutdown(struct uart_port *port)
+{
+ writel(0, port->membase + UART_CR) ;
+
+ free_irq(port->irq, port);
+}
+
+static void
+netx_set_termios(struct uart_port *port, struct termios *termios,
+ struct termios *old)
+{
+ unsigned int baud, quot;
+ unsigned char old_cr;
+ unsigned char line_cr = LINE_CR_FEN;
+ unsigned char rts_cr = 0;
+
+ switch (termios->c_cflag & CSIZE) {
+ case CS5:
+ line_cr |= LINE_CR_5BIT;
+ break;
+ case CS6:
+ line_cr |= LINE_CR_6BIT;
+ break;
+ case CS7:
+ line_cr |= LINE_CR_7BIT;
+ break;
+ case CS8:
+ line_cr |= LINE_CR_8BIT;
+ break;
+ }
+
+ if (termios->c_cflag & CSTOPB)
+ line_cr |= LINE_CR_STP2;
+
+ if (termios->c_cflag & PARENB) {
+ line_cr |= LINE_CR_PEN;
+ if (!(termios->c_cflag & PARODD))
+ line_cr |= LINE_CR_EPS;
+ }
+
+ if (termios->c_cflag & CRTSCTS)
+ rts_cr = RTS_CR_AUTO | RTS_CR_CTS_CTR | RTS_CR_RTS_POL;
+
+ baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
+ quot = baud * 4096;
+ quot /= 1000;
+ quot *= 256;
+ quot /= 100000;
+
+ spin_lock_irq(&port->lock);
+
+ uart_update_timeout(port, termios->c_cflag, baud);
+
+ old_cr = readl(port->membase + UART_CR);
+
+ /* disable interrupts */
+ writel(old_cr & ~(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE),
+ port->membase + UART_CR);
+
+ /* drain transmitter */
+ while (readl(port->membase + UART_FR) & FR_BUSY);
+
+ /* disable UART */
+ writel(old_cr & ~CR_UART_EN, port->membase + UART_CR);
+
+ /* modem status interrupts */
+ old_cr &= ~CR_MSIE;
+ if (UART_ENABLE_MS(port, termios->c_cflag))
+ old_cr |= CR_MSIE;
+
+ writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB);
+ writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB);
+ writel(line_cr, port->membase + UART_LINE_CR);
+
+ writel(rts_cr, port->membase + UART_RTS_CR);
+
+ /*
+ * Characters to ignore
+ */
+ port->ignore_status_mask = 0;
+ if (termios->c_iflag & IGNPAR)
+ port->ignore_status_mask |= SR_PE;
+ if (termios->c_iflag & IGNBRK) {
+ port->ignore_status_mask |= SR_BE;
+ /*
+ * If we're ignoring parity and break indicators,
+ * ignore overruns too (for real raw support).
+ */
+ if (termios->c_iflag & IGNPAR)
+ port->ignore_status_mask |= SR_PE;
+ }
+
+ port->read_status_mask = 0;
+ if (termios->c_iflag & (BRKINT | PARMRK))
+ port->read_status_mask |= SR_BE;
+ if (termios->c_iflag & INPCK)
+ port->read_status_mask |= SR_PE | SR_FE;
+
+ writel(old_cr, port->membase + UART_CR);
+
+ spin_unlock_irq(&port->lock);
+}
+
+static const char *netx_type(struct uart_port *port)
+{
+ return port->type == PORT_NETX ? "NETX" : NULL;
+}
+
+static void netx_release_port(struct uart_port *port)
+{
+ release_mem_region(port->mapbase, UART_PORT_SIZE);
+}
+
+static int netx_request_port(struct uart_port *port)
+{
+ return request_mem_region(port->mapbase, UART_PORT_SIZE,
+ DRIVER_NAME) != NULL ? 0 : -EBUSY;
+}
+
+static void netx_config_port(struct uart_port *port, int flags)
+{
+ if (flags & UART_CONFIG_TYPE && netx_request_port(port) == 0)
+ port->type = PORT_NETX;
+}
+
+static int
+netx_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
+ int ret = 0;
+
+ if (ser->type != PORT_UNKNOWN && ser->type != PORT_NETX)
+ ret = -EINVAL;
+
+ return ret;
+}
+
+static struct uart_ops netx_pops = {
+ .tx_empty = netx_tx_empty,
+ .set_mctrl = netx_set_mctrl,
+ .get_mctrl = netx_get_mctrl,
+ .stop_tx = netx_stop_tx,
+ .start_tx = netx_start_tx,
+ .stop_rx = netx_stop_rx,
+ .enable_ms = netx_enable_ms,
+ .break_ctl = netx_break_ctl,
+ .startup = netx_startup,
+ .shutdown = netx_shutdown,
+ .set_termios = netx_set_termios,
+ .type = netx_type,
+ .release_port = netx_release_port,
+ .request_port = netx_request_port,
+ .config_port = netx_config_port,
+ .verify_port = netx_verify_port,
+};
+
+static struct netx_port netx_ports[] = {
+ {
+ .port = {
+ .type = PORT_NETX,
+ .iotype = UPIO_MEM,
+ .membase = (char __iomem *)io_p2v(NETX_PA_UART0),
+ .mapbase = NETX_PA_UART0,
+ .irq = NETX_IRQ_UART0,
+ .uartclk = 100000000,
+ .fifosize = 16,
+ .flags = UPF_BOOT_AUTOCONF,
+ .ops = &netx_pops,
+ .line = 0,
+ },
+ }, {
+ .port = {
+ .type = PORT_NETX,
+ .iotype = UPIO_MEM,
+ .membase = (char __iomem *)io_p2v(NETX_PA_UART1),
+ .mapbase = NETX_PA_UART1,
+ .irq = NETX_IRQ_UART1,
+ .uartclk = 100000000,
+ .fifosize = 16,
+ .flags = UPF_BOOT_AUTOCONF,
+ .ops = &netx_pops,
+ .line = 1,
+ },
+ }, {
+ .port = {
+ .type = PORT_NETX,
+ .iotype = UPIO_MEM,
+ .membase = (char __iomem *)io_p2v(NETX_PA_UART2),
+ .mapbase = NETX_PA_UART2,
+ .irq = NETX_IRQ_UART2,
+ .uartclk = 100000000,
+ .fifosize = 16,
+ .flags = UPF_BOOT_AUTOCONF,
+ .ops = &netx_pops,
+ .line = 2,
+ },
+ }
+};
+
+static void netx_console_putchar(struct uart_port *port, int ch)
+{
+ while (readl(port->membase + UART_FR) & FR_BUSY);
+ writel(ch, port->membase + UART_DR);
+}
+
+static void
+netx_console_write(struct console *co, const char *s, unsigned int count)
+{
+ struct uart_port *port = &netx_ports[co->index].port;
+ unsigned char cr_save;
+
+ cr_save = readl(port->membase + UART_CR);
+ writel(cr_save | CR_UART_EN, port->membase + UART_CR);
+
+ uart_console_write(port, s, count, netx_console_putchar);
+
+ while (readl(port->membase + UART_FR) & FR_BUSY);
+ writel(cr_save, port->membase + UART_CR);
+}
+
+static void __init
+netx_console_get_options(struct uart_port *port, int *baud,
+ int *parity, int *bits, int *flow)
+{
+ unsigned char line_cr;
+
+ *baud = (readl(port->membase + UART_BAUDDIV_MSB) << 8) |
+ readl(port->membase + UART_BAUDDIV_LSB);
+ *baud *= 1000;
+ *baud /= 4096;
+ *baud *= 1000;
+ *baud /= 256;
+ *baud *= 100;
+
+ line_cr = readl(port->membase + UART_LINE_CR);
+ *parity = 'n';
+ if (line_cr & LINE_CR_PEN) {
+ if (line_cr & LINE_CR_EPS)
+ *parity = 'e';
+ else
+ *parity = 'o';
+ }
+
+ switch (line_cr & LINE_CR_BITS_MASK) {
+ case LINE_CR_8BIT:
+ *bits = 8;
+ break;
+ case LINE_CR_7BIT:
+ *bits = 7;
+ break;
+ case LINE_CR_6BIT:
+ *bits = 6;
+ break;
+ case LINE_CR_5BIT:
+ *bits = 5;
+ break;
+ }
+
+ if (readl(port->membase + UART_RTS_CR) & RTS_CR_AUTO)
+ *flow = 'r';
+}
+
+static int __init
+netx_console_setup(struct console *co, char *options)
+{
+ struct netx_port *sport;
+ int baud = 9600;
+ int bits = 8;
+ int parity = 'n';
+ int flow = 'n';
+
+ /*
+ * Check whether an invalid uart number has been specified, and
+ * if so, search for the first available port that does have
+ * console support.
+ */
+ if (co->index == -1 || co->index >= ARRAY_SIZE(netx_ports))
+ co->index = 0;
+ sport = &netx_ports[co->index];
+
+ if (options) {
+ uart_parse_options(options, &baud, &parity, &bits, &flow);
+ } else {
+ /* if the UART is enabled, assume it has been correctly setup
+ * by the bootloader and get the options
+ */
+ if (readl(sport->port.membase + UART_CR) & CR_UART_EN) {
+ netx_console_get_options(&sport->port, &baud,
+ &parity, &bits, &flow);
+ }
+
+ }
+
+ return uart_set_options(&sport->port, co, baud, parity, bits, flow);
+}
+
+static struct uart_driver netx_reg;
+static struct console netx_console = {
+ .name = "ttyNX",
+ .write = netx_console_write,
+ .device = uart_console_device,
+ .setup = netx_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+ .data = &netx_reg,
+};
+
+static int __init netx_console_init(void)
+{
+ register_console(&netx_console);
+ return 0;
+}
+console_initcall(netx_console_init);
+
+#define NETX_CONSOLE &netx_console
+#else
+#define NETX_CONSOLE NULL
+#endif
+
+static struct uart_driver netx_reg = {
+ .owner = THIS_MODULE,
+ .driver_name = DRIVER_NAME,
+ .dev_name = "ttyNX",
+ .major = SERIAL_NX_MAJOR,
+ .minor = MINOR_START,
+ .nr = ARRAY_SIZE(netx_ports),
+ .cons = NETX_CONSOLE,
+};
+
+static int serial_netx_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct netx_port *sport = platform_get_drvdata(pdev);
+
+ if (sport)
+ uart_suspend_port(&netx_reg, &sport->port);
+
+ return 0;
+}
+
+static int serial_netx_resume(struct platform_device *pdev)
+{
+ struct netx_port *sport = platform_get_drvdata(pdev);
+
+ if (sport)
+ uart_resume_port(&netx_reg, &sport->port);
+
+ return 0;
+}
+
+static int serial_netx_probe(struct platform_device *pdev)
+{
+ struct uart_port *port = &netx_ports[pdev->id].port;
+
+ dev_info(&pdev->dev, "initialising\n");
+
+ port->dev = &pdev->dev;
+
+ writel(1, port->membase + UART_RXFIFO_IRQLEVEL);
+ uart_add_one_port(&netx_reg, &netx_ports[pdev->id].port);
+ platform_set_drvdata(pdev, &netx_ports[pdev->id]);
+
+ return 0;
+}
+
+static int serial_netx_remove(struct platform_device *pdev)
+{
+ struct netx_port *sport = platform_get_drvdata(pdev);
+
+ platform_set_drvdata(pdev, NULL);
+
+ if (sport)
+ uart_remove_one_port(&netx_reg, &sport->port);
+
+ return 0;
+}
+
+static struct platform_driver serial_netx_driver = {
+ .probe = serial_netx_probe,
+ .remove = serial_netx_remove,
+
+ .suspend = serial_netx_suspend,
+ .resume = serial_netx_resume,
+
+ .driver = {
+ .name = DRIVER_NAME,
+ },
+};
+
+static int __init netx_serial_init(void)
+{
+ int ret;
+
+ printk(KERN_INFO "Serial: NetX driver\n");
+
+ ret = uart_register_driver(&netx_reg);
+ if (ret)
+ return ret;
+
+ ret = platform_driver_register(&serial_netx_driver);
+ if (ret != 0)
+ uart_unregister_driver(&netx_reg);
+
+ return 0;
+}
+
+static void __exit netx_serial_exit(void)
+{
+ platform_driver_unregister(&serial_netx_driver);
+ uart_unregister_driver(&netx_reg);
+}
+
+module_init(netx_serial_init);
+module_exit(netx_serial_exit);
+
+MODULE_AUTHOR("Sascha Hauer");
+MODULE_DESCRIPTION("NetX serial port driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/serial/pxa.c b/drivers/serial/pxa.c
index 77d4568ccc3..ae364956854 100644
--- a/drivers/serial/pxa.c
+++ b/drivers/serial/pxa.c
@@ -269,7 +269,6 @@ static unsigned int serial_pxa_get_mctrl(struct uart_port *port)
unsigned char status;
unsigned int ret;
-return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
status = serial_in(up, UART_MSR);
ret = 0;
diff --git a/drivers/serial/s3c2410.c b/drivers/serial/s3c2410.c
index f5aac92fb79..837b6da520b 100644
--- a/drivers/serial/s3c2410.c
+++ b/drivers/serial/s3c2410.c
@@ -872,6 +872,8 @@ static const char *s3c24xx_serial_type(struct uart_port *port)
return "S3C2410";
case PORT_S3C2440:
return "S3C2440";
+ case PORT_S3C2412:
+ return "S3C2412";
default:
return NULL;
}
@@ -1365,7 +1367,7 @@ static inline void s3c2410_serial_exit(void)
#endif /* CONFIG_CPU_S3C2410 */
-#ifdef CONFIG_CPU_S3C2440
+#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
static int s3c2440_serial_setsource(struct uart_port *port,
struct s3c24xx_uart_clksrc *clk)
@@ -1528,6 +1530,141 @@ static inline void s3c2440_serial_exit(void)
#define s3c2440_uart_inf_at NULL
#endif /* CONFIG_CPU_S3C2440 */
+#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
+
+static int s3c2412_serial_setsource(struct uart_port *port,
+ struct s3c24xx_uart_clksrc *clk)
+{
+ unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+ ucon &= ~S3C2412_UCON_CLKMASK;
+
+ if (strcmp(clk->name, "uclk") == 0)
+ ucon |= S3C2440_UCON_UCLK;
+ else if (strcmp(clk->name, "pclk") == 0)
+ ucon |= S3C2440_UCON_PCLK;
+ else if (strcmp(clk->name, "usysclk") == 0)
+ ucon |= S3C2412_UCON_USYSCLK;
+ else {
+ printk(KERN_ERR "unknown clock source %s\n", clk->name);
+ return -EINVAL;
+ }
+
+ wr_regl(port, S3C2410_UCON, ucon);
+ return 0;
+}
+
+
+static int s3c2412_serial_getsource(struct uart_port *port,
+ struct s3c24xx_uart_clksrc *clk)
+{
+ unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+ switch (ucon & S3C2412_UCON_CLKMASK) {
+ case S3C2412_UCON_UCLK:
+ clk->divisor = 1;
+ clk->name = "uclk";
+ break;
+
+ case S3C2412_UCON_PCLK:
+ case S3C2412_UCON_PCLK2:
+ clk->divisor = 1;
+ clk->name = "pclk";
+ break;
+
+ case S3C2412_UCON_USYSCLK:
+ clk->divisor = 1;
+ clk->name = "usysclk";
+ break;
+ }
+
+ return 0;
+}
+
+static int s3c2412_serial_resetport(struct uart_port *port,
+ struct s3c2410_uartcfg *cfg)
+{
+ unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+ dbg("%s: port=%p (%08lx), cfg=%p\n",
+ __FUNCTION__, port, port->mapbase, cfg);
+
+ /* ensure we don't change the clock settings... */
+
+ ucon &= S3C2412_UCON_CLKMASK;
+
+ wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
+ wr_regl(port, S3C2410_ULCON, cfg->ulcon);
+
+ /* reset both fifos */
+
+ wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
+ wr_regl(port, S3C2410_UFCON, cfg->ufcon);
+
+ return 0;
+}
+
+static struct s3c24xx_uart_info s3c2412_uart_inf = {
+ .name = "Samsung S3C2412 UART",
+ .type = PORT_S3C2412,
+ .fifosize = 64,
+ .rx_fifomask = S3C2440_UFSTAT_RXMASK,
+ .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
+ .rx_fifofull = S3C2440_UFSTAT_RXFULL,
+ .tx_fifofull = S3C2440_UFSTAT_TXFULL,
+ .tx_fifomask = S3C2440_UFSTAT_TXMASK,
+ .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
+ .get_clksrc = s3c2412_serial_getsource,
+ .set_clksrc = s3c2412_serial_setsource,
+ .reset_port = s3c2412_serial_resetport,
+};
+
+/* device management */
+
+static int s3c2412_serial_probe(struct platform_device *dev)
+{
+ dbg("s3c2440_serial_probe: dev=%p\n", dev);
+ return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
+}
+
+static struct platform_driver s3c2412_serial_drv = {
+ .probe = s3c2412_serial_probe,
+ .remove = s3c24xx_serial_remove,
+ .suspend = s3c24xx_serial_suspend,
+ .resume = s3c24xx_serial_resume,
+ .driver = {
+ .name = "s3c2412-uart",
+ .owner = THIS_MODULE,
+ },
+};
+
+
+static inline int s3c2412_serial_init(void)
+{
+ return s3c24xx_serial_init(&s3c2412_serial_drv, &s3c2412_uart_inf);
+}
+
+static inline void s3c2412_serial_exit(void)
+{
+ platform_driver_unregister(&s3c2412_serial_drv);
+}
+
+#define s3c2412_uart_inf_at &s3c2412_uart_inf
+#else
+
+static inline int s3c2412_serial_init(void)
+{
+ return 0;
+}
+
+static inline void s3c2412_serial_exit(void)
+{
+}
+
+#define s3c2412_uart_inf_at NULL
+#endif /* CONFIG_CPU_S3C2440 */
+
+
/* module initialisation code */
static int __init s3c24xx_serial_modinit(void)
@@ -1542,6 +1679,7 @@ static int __init s3c24xx_serial_modinit(void)
s3c2400_serial_init();
s3c2410_serial_init();
+ s3c2412_serial_init();
s3c2440_serial_init();
return 0;
@@ -1551,6 +1689,7 @@ static void __exit s3c24xx_serial_modexit(void)
{
s3c2400_serial_exit();
s3c2410_serial_exit();
+ s3c2412_serial_exit();
s3c2440_serial_exit();
uart_unregister_driver(&s3c24xx_uart_drv);
@@ -1773,6 +1912,8 @@ static int s3c24xx_serial_initconsole(void)
info = s3c2410_uart_inf_at;
} else if (strcmp(dev->name, "s3c2440-uart") == 0) {
info = s3c2440_uart_inf_at;
+ } else if (strcmp(dev->name, "s3c2412-uart") == 0) {
+ info = s3c2412_uart_inf_at;
} else {
printk(KERN_ERR "s3c24xx: no driver for %s\n", dev->name);
return 0;
@@ -1796,4 +1937,4 @@ console_initcall(s3c24xx_serial_initconsole);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
-MODULE_DESCRIPTION("Samsung S3C2410/S3C2440 Serial port driver");
+MODULE_DESCRIPTION("Samsung S3C2410/S3C2440/S3C2412 Serial port driver");
diff --git a/drivers/serial/serial_lh7a40x.c b/drivers/serial/serial_lh7a40x.c
index aa521b8e0d4..776d4ff0608 100644
--- a/drivers/serial/serial_lh7a40x.c
+++ b/drivers/serial/serial_lh7a40x.c
@@ -145,14 +145,15 @@ lh7a40xuart_rx_chars (struct uart_port* port)
{
struct tty_struct* tty = port->info->tty;
int cbRxMax = 256; /* (Gross) limit on receive */
- unsigned int data, flag;/* Received data and status */
+ unsigned int data; /* Received data and status */
+ unsigned int flag;
while (!(UR (port, UART_R_STATUS) & nRxRdy) && --cbRxMax) {
data = UR (port, UART_R_DATA);
flag = TTY_NORMAL;
++port->icount.rx;
- if (unlikely(data & RxError)) { /* Quick check, short-circuit */
+ if (unlikely(data & RxError)) {
if (data & RxBreak) {
data &= ~(RxFramingError | RxParityError);
++port->icount.brk;
@@ -303,7 +304,7 @@ static void lh7a40xuart_set_mctrl (struct uart_port* port, unsigned int mctrl)
/* Note, kernel appears to be setting DTR and RTS on console. */
/* *** FIXME: this deserves more work. There's some work in
- tracing all of the IO pins. */
+ tracing all of the IO pins. */
#if 0
if( port->mapbase == UART1_PHYS) {
gpioRegs_t *gpio = (gpioRegs_t *)IO_ADDRESS(GPIO_PHYS);
@@ -662,9 +663,13 @@ static int __init lh7a40xuart_init(void)
if (ret == 0) {
int i;
- for (i = 0; i < DEV_NR; i++)
+ for (i = 0; i < DEV_NR; i++) {
+ /* UART3, when used, requires GPIO pin reallocation */
+ if (lh7a40x_ports[i].port.mapbase == UART3_PHYS)
+ GPIO_PINMUX |= 1<<3;
uart_add_one_port (&lh7a40x_reg,
&lh7a40x_ports[i].port);
+ }
}
return ret;
}
diff --git a/drivers/serial/sunhv.c b/drivers/serial/sunhv.c
index f137804b313..ba22e256c6f 100644
--- a/drivers/serial/sunhv.c
+++ b/drivers/serial/sunhv.c
@@ -427,31 +427,32 @@ static int __init hv_console_compatible(char *buf, int len)
static unsigned int __init get_interrupt(void)
{
- const char *cons_str = "console";
- const char *compat_str = "compatible";
- int node = prom_getchild(sun4v_vdev_root);
- char buf[64];
- int err, len;
-
- node = prom_searchsiblings(node, cons_str);
- if (!node)
- return 0;
+ struct device_node *dev_node;
- len = prom_getproplen(node, compat_str);
- if (len == 0 || len == -1)
- return 0;
+ dev_node = sun4v_vdev_root->child;
+ while (dev_node != NULL) {
+ struct property *prop;
- err = prom_getproperty(node, compat_str, buf, 64);
- if (err == -1)
- return 0;
+ if (strcmp(dev_node->name, "console"))
+ goto next_sibling;
+
+ prop = of_find_property(dev_node, "compatible", NULL);
+ if (!prop)
+ goto next_sibling;
- if (!hv_console_compatible(buf, len))
+ if (hv_console_compatible(prop->value, prop->length))
+ break;
+
+ next_sibling:
+ dev_node = dev_node->sibling;
+ }
+ if (!dev_node)
return 0;
/* Ok, the this is the OBP node for the sun4v hypervisor
* console device. Decode the interrupt.
*/
- return sun4v_vdev_device_interrupt(node);
+ return sun4v_vdev_device_interrupt(dev_node);
}
static int __init sunhv_init(void)
diff --git a/drivers/serial/sunsab.c b/drivers/serial/sunsab.c
index bfbe9dc90cc..e4c0fd2d6a9 100644
--- a/drivers/serial/sunsab.c
+++ b/drivers/serial/sunsab.c
@@ -984,19 +984,19 @@ static void __init for_each_sab_edev(void (*callback)(struct linux_ebus_device *
for_each_ebus(ebus) {
for_each_ebusdev(edev, ebus) {
- if (!strcmp(edev->prom_name, "se")) {
+ if (!strcmp(edev->prom_node->name, "se")) {
callback(edev, arg);
continue;
- } else if (!strcmp(edev->prom_name, "serial")) {
- char compat[32];
+ } else if (!strcmp(edev->prom_node->name, "serial")) {
+ char *compat;
int clen;
/* On RIO this can be an SE, check it. We could
* just check ebus->is_rio, but this is more portable.
*/
- clen = prom_getproperty(edev->prom_node, "compatible",
- compat, sizeof(compat));
- if (clen > 0) {
+ compat = of_get_property(edev->prom_node,
+ "compatible", &clen);
+ if (compat && clen > 0) {
if (strncmp(compat, "sab82532", 8) == 0) {
callback(edev, arg);
continue;
diff --git a/drivers/serial/sunsu.c b/drivers/serial/sunsu.c
index 2b4f96541b8..0268b307c01 100644
--- a/drivers/serial/sunsu.c
+++ b/drivers/serial/sunsu.c
@@ -1053,7 +1053,7 @@ static void sunsu_autoconfig(struct uart_sunsu_port *up)
*/
for_each_ebus(ebus) {
for_each_ebusdev(dev, ebus) {
- if (dev->prom_node == up->port_node) {
+ if (dev->prom_node->node == up->port_node) {
/*
* The EBus is broken on sparc; it delivers
* virtual addresses in resources. Oh well...
@@ -1073,7 +1073,7 @@ static void sunsu_autoconfig(struct uart_sunsu_port *up)
#ifdef CONFIG_SPARC64
for_each_isa(isa_br) {
for_each_isadev(isa_dev, isa_br) {
- if (isa_dev->prom_node == up->port_node) {
+ if (isa_dev->prom_node->node == up->port_node) {
/* Same on sparc64. Cool architecure... */
up->port.membase = (char *) isa_dev->resource.start;
up->port.mapbase = isa_dev->resource.start;
@@ -1295,9 +1295,9 @@ static int __init sunsu_kbd_ms_init(struct uart_sunsu_port *up, int channel)
if (up->port.type == PORT_UNKNOWN)
return -1;
- printk(KERN_INFO "su%d at 0x%p (irq = %s) is a %s\n",
+ printk(KERN_INFO "su%d at 0x%p (irq = %d) is a %s\n",
channel,
- up->port.membase, __irq_itoa(up->port.irq),
+ up->port.membase, up->port.irq,
sunsu_type(&up->port));
#ifdef CONFIG_SERIO
diff --git a/drivers/serial/sunzilog.c b/drivers/serial/sunzilog.c
index cd49ebbf4a4..76c9bac9271 100644
--- a/drivers/serial/sunzilog.c
+++ b/drivers/serial/sunzilog.c
@@ -1106,7 +1106,7 @@ static struct zilog_layout __iomem * __init get_zs_sun4u(int chip, int zsnode)
+ FHC_UREGS_ICLR;
imap = central_bus->child->fhc_regs.uregs
+ FHC_UREGS_IMAP;
- zilog_irq = build_irq(12, 0, iclr, imap);
+ zilog_irq = build_irq(0, iclr, imap);
} else {
err = prom_getproperty(zsnode, "interrupts",
(char *) &sun4u_ino,
@@ -1540,8 +1540,8 @@ static void __init sunzilog_init_kbdms(struct uart_sunzilog_port *up, int channe
up->cflag = B4800 | CS8 | CLOCAL | CREAD;
baud = 4800;
}
- printk(KERN_INFO "zs%d at 0x%p (irq = %s) is a SunZilog\n",
- channel, up->port.membase, __irq_itoa(zilog_irq));
+ printk(KERN_INFO "zs%d at 0x%p (irq = %d) is a SunZilog\n",
+ channel, up->port.membase, zilog_irq);
up->curregs[R15] = BRKIE;
brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2024-12-19 18:30:02 +0000