diff options
Diffstat (limited to 'drivers/staging/rtl8192e/r819xE_phy.c')
-rw-r--r-- | drivers/staging/rtl8192e/r819xE_phy.c | 1610 |
1 files changed, 252 insertions, 1358 deletions
diff --git a/drivers/staging/rtl8192e/r819xE_phy.c b/drivers/staging/rtl8192e/r819xE_phy.c index 50cd0e52b92..dfa4e112ef4 100644 --- a/drivers/staging/rtl8192e/r819xE_phy.c +++ b/drivers/staging/rtl8192e/r819xE_phy.c @@ -24,839 +24,7 @@ static const u32 RF_CHANNEL_TABLE_ZEBRA[] = { 0x0e5c, //2472 13 0x0f72, //2484 }; -#ifdef RTL8190P -u32 Rtl8190PciMACPHY_Array[] = { -0x03c,0xffff0000,0x00000f0f, -0x340,0xffffffff,0x161a1a1a, -0x344,0xffffffff,0x12121416, -0x348,0x0000ffff,0x00001818, -0x12c,0xffffffff,0x04000802, -0x318,0x00000fff,0x00000800, -}; -u32 Rtl8190PciMACPHY_Array_PG[] = { -0x03c,0xffff0000,0x00000f0f, -0x340,0xffffffff,0x0a0c0d0f, -0x344,0xffffffff,0x06070809, -0x344,0xffffffff,0x06070809, -0x348,0x0000ffff,0x00000000, -0x12c,0xffffffff,0x04000802, -0x318,0x00000fff,0x00000800, -}; - -u32 Rtl8190PciAGCTAB_Array[AGCTAB_ArrayLength] = { -0xc78,0x7d000001, -0xc78,0x7d010001, -0xc78,0x7d020001, -0xc78,0x7d030001, -0xc78,0x7c040001, -0xc78,0x7b050001, -0xc78,0x7a060001, -0xc78,0x79070001, -0xc78,0x78080001, -0xc78,0x77090001, -0xc78,0x760a0001, -0xc78,0x750b0001, -0xc78,0x740c0001, -0xc78,0x730d0001, -0xc78,0x720e0001, -0xc78,0x710f0001, -0xc78,0x70100001, -0xc78,0x6f110001, -0xc78,0x6e120001, -0xc78,0x6d130001, -0xc78,0x6c140001, -0xc78,0x6b150001, -0xc78,0x6a160001, -0xc78,0x69170001, -0xc78,0x68180001, -0xc78,0x67190001, -0xc78,0x661a0001, -0xc78,0x651b0001, -0xc78,0x641c0001, -0xc78,0x491d0001, -0xc78,0x481e0001, -0xc78,0x471f0001, -0xc78,0x46200001, -0xc78,0x45210001, -0xc78,0x44220001, -0xc78,0x43230001, -0xc78,0x28240001, -0xc78,0x27250001, -0xc78,0x26260001, -0xc78,0x25270001, -0xc78,0x24280001, -0xc78,0x23290001, -0xc78,0x222a0001, -0xc78,0x212b0001, -0xc78,0x202c0001, -0xc78,0x0a2d0001, -0xc78,0x082e0001, -0xc78,0x062f0001, -0xc78,0x05300001, -0xc78,0x04310001, -0xc78,0x03320001, -0xc78,0x02330001, -0xc78,0x01340001, -0xc78,0x00350001, -0xc78,0x00360001, -0xc78,0x00370001, -0xc78,0x00380001, -0xc78,0x00390001, -0xc78,0x003a0001, -0xc78,0x003b0001, -0xc78,0x003c0001, -0xc78,0x003d0001, -0xc78,0x003e0001, -0xc78,0x003f0001, -0xc78,0x7d400001, -0xc78,0x7d410001, -0xc78,0x7d420001, -0xc78,0x7d430001, -0xc78,0x7c440001, -0xc78,0x7b450001, -0xc78,0x7a460001, -0xc78,0x79470001, -0xc78,0x78480001, -0xc78,0x77490001, -0xc78,0x764a0001, -0xc78,0x754b0001, -0xc78,0x744c0001, -0xc78,0x734d0001, -0xc78,0x724e0001, -0xc78,0x714f0001, -0xc78,0x70500001, -0xc78,0x6f510001, -0xc78,0x6e520001, -0xc78,0x6d530001, -0xc78,0x6c540001, -0xc78,0x6b550001, -0xc78,0x6a560001, -0xc78,0x69570001, -0xc78,0x68580001, -0xc78,0x67590001, -0xc78,0x665a0001, -0xc78,0x655b0001, -0xc78,0x645c0001, -0xc78,0x495d0001, -0xc78,0x485e0001, -0xc78,0x475f0001, -0xc78,0x46600001, -0xc78,0x45610001, -0xc78,0x44620001, -0xc78,0x43630001, -0xc78,0x28640001, -0xc78,0x27650001, -0xc78,0x26660001, -0xc78,0x25670001, -0xc78,0x24680001, -0xc78,0x23690001, -0xc78,0x226a0001, -0xc78,0x216b0001, -0xc78,0x206c0001, -0xc78,0x0a6d0001, -0xc78,0x086e0001, -0xc78,0x066f0001, -0xc78,0x05700001, -0xc78,0x04710001, -0xc78,0x03720001, -0xc78,0x02730001, -0xc78,0x01740001, -0xc78,0x00750001, -0xc78,0x00760001, -0xc78,0x00770001, -0xc78,0x00780001, -0xc78,0x00790001, -0xc78,0x007a0001, -0xc78,0x007b0001, -0xc78,0x007c0001, -0xc78,0x007d0001, -0xc78,0x007e0001, -0xc78,0x007f0001, -0xc78,0x3600001e, -0xc78,0x3601001e, -0xc78,0x3602001e, -0xc78,0x3603001e, -0xc78,0x3604001e, -0xc78,0x3605001e, -0xc78,0x3a06001e, -0xc78,0x3c07001e, -0xc78,0x3e08001e, -0xc78,0x4209001e, -0xc78,0x430a001e, -0xc78,0x450b001e, -0xc78,0x470c001e, -0xc78,0x480d001e, -0xc78,0x490e001e, -0xc78,0x4b0f001e, -0xc78,0x4c10001e, -0xc78,0x4d11001e, -0xc78,0x4d12001e, -0xc78,0x4e13001e, -0xc78,0x4f14001e, -0xc78,0x5015001e, -0xc78,0x5116001e, -0xc78,0x5117001e, -0xc78,0x5218001e, -0xc78,0x5219001e, -0xc78,0x531a001e, -0xc78,0x541b001e, -0xc78,0x541c001e, -0xc78,0x551d001e, -0xc78,0x561e001e, -0xc78,0x561f001e, -0xc78,0x5720001e, -0xc78,0x5821001e, -0xc78,0x5822001e, -0xc78,0x5923001e, -0xc78,0x5924001e, -0xc78,0x5a25001e, -0xc78,0x5b26001e, -0xc78,0x5b27001e, -0xc78,0x5c28001e, -0xc78,0x5c29001e, -0xc78,0x5d2a001e, -0xc78,0x5d2b001e, -0xc78,0x5e2c001e, -0xc78,0x5e2d001e, -0xc78,0x5f2e001e, -0xc78,0x602f001e, -0xc78,0x6030001e, -0xc78,0x6131001e, -0xc78,0x6132001e, -0xc78,0x6233001e, -0xc78,0x6234001e, -0xc78,0x6335001e, -0xc78,0x6336001e, -0xc78,0x6437001e, -0xc78,0x6538001e, -0xc78,0x6639001e, -0xc78,0x663a001e, -0xc78,0x673b001e, -0xc78,0x683c001e, -0xc78,0x693d001e, -0xc78,0x6a3e001e, -0xc78,0x6b3f001e, -}; - -u32 Rtl8190PciPHY_REGArray[PHY_REGArrayLength] = { -0x800,0x00050060, -0x804,0x00000005, -0x808,0x0000fc00, -0x80c,0x0000001c, -0x810,0x801010aa, -0x814,0x000908c0, -0x818,0x00000000, -0x81c,0x00000000, -0x820,0x00000004, -0x824,0x00690000, -0x828,0x00000004, -0x82c,0x00e90000, -0x830,0x00000004, -0x834,0x00690000, -0x838,0x00000004, -0x83c,0x00e90000, -0x840,0x00000000, -0x844,0x00000000, -0x848,0x00000000, -0x84c,0x00000000, -0x850,0x00000000, -0x854,0x00000000, -0x858,0x65a965a9, -0x85c,0x65a965a9, -0x860,0x001f0010, -0x864,0x007f0010, -0x868,0x001f0010, -0x86c,0x007f0010, -0x870,0x0f100f70, -0x874,0x0f100f70, -0x878,0x00000000, -0x87c,0x00000000, -0x880,0x5c385eb8, -0x884,0x6357060d, -0x888,0x0460c341, -0x88c,0x0000ff00, -0x890,0x00000000, -0x894,0xfffffffe, -0x898,0x4c42382f, -0x89c,0x00656056, -0x8b0,0x00000000, -0x8e0,0x00000000, -0x8e4,0x00000000, -0x900,0x00000000, -0x904,0x00000023, -0x908,0x00000000, -0x90c,0x35541545, -0xa00,0x00d0c7d8, -0xa04,0xab1f0008, -0xa08,0x80cd8300, -0xa0c,0x2e62740f, -0xa10,0x95009b78, -0xa14,0x11145008, -0xa18,0x00881117, -0xa1c,0x89140fa0, -0xa20,0x1a1b0000, -0xa24,0x090e1317, -0xa28,0x00000204, -0xa2c,0x00000000, -0xc00,0x00000040, -0xc04,0x0000500f, -0xc08,0x000000e4, -0xc0c,0x6c6c6c6c, -0xc10,0x08000000, -0xc14,0x40000100, -0xc18,0x08000000, -0xc1c,0x40000100, -0xc20,0x08000000, -0xc24,0x40000100, -0xc28,0x08000000, -0xc2c,0x40000100, -0xc30,0x6de9ac44, -0xc34,0x164052cd, -0xc38,0x00070a14, -0xc3c,0x0a969764, -0xc40,0x1f7c403f, -0xc44,0x000100b7, -0xc48,0xec020000, -0xc4c,0x00000300, -0xc50,0x69543420, -0xc54,0x433c0094, -0xc58,0x69543420, -0xc5c,0x433c0094, -0xc60,0x69543420, -0xc64,0x433c0094, -0xc68,0x69543420, -0xc6c,0x433c0094, -0xc70,0x2c7f000d, -0xc74,0x0186175b, -0xc78,0x0000001f, -0xc7c,0x00b91612, -0xc80,0x40000100, -0xc84,0x00000000, -0xc88,0x40000100, -0xc8c,0x08000000, -0xc90,0x40000100, -0xc94,0x00000000, -0xc98,0x40000100, -0xc9c,0x00000000, -0xca0,0x00492492, -0xca4,0x00000000, -0xca8,0x00000000, -0xcac,0x00000000, -0xcb0,0x00000000, -0xcb4,0x00000000, -0xcb8,0x00000000, -0xcbc,0x00492492, -0xcc0,0x00000000, -0xcc4,0x00000000, -0xcc8,0x00000000, -0xccc,0x00000000, -0xcd0,0x00000000, -0xcd4,0x00000000, -0xcd8,0x64b22427, -0xcdc,0x00766932, -0xce0,0x00222222, -0xd00,0x00000740, -0xd04,0x0000040f, -0xd08,0x0000803f, -0xd0c,0x00000001, -0xd10,0xa0633333, -0xd14,0x33333c63, -0xd18,0x6a8f5b6b, -0xd1c,0x00000000, -0xd20,0x00000000, -0xd24,0x00000000, -0xd28,0x00000000, -0xd2c,0xcc979975, -0xd30,0x00000000, -0xd34,0x00000000, -0xd38,0x00000000, -0xd3c,0x00027293, -0xd40,0x00000000, -0xd44,0x00000000, -0xd48,0x00000000, -0xd4c,0x00000000, -0xd50,0x6437140a, -0xd54,0x024dbd02, -0xd58,0x00000000, -0xd5c,0x14032064, -}; -u32 Rtl8190PciPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = { -0x800,0x00050060, -0x804,0x00000004, -0x808,0x0000fc00, -0x80c,0x0000001c, -0x810,0x801010aa, -0x814,0x000908c0, -0x818,0x00000000, -0x81c,0x00000000, -0x820,0x00000004, -0x824,0x00690000, -0x828,0x00000004, -0x82c,0x00e90000, -0x830,0x00000004, -0x834,0x00690000, -0x838,0x00000004, -0x83c,0x00e90000, -0x840,0x00000000, -0x844,0x00000000, -0x848,0x00000000, -0x84c,0x00000000, -0x850,0x00000000, -0x854,0x00000000, -0x858,0x65a965a9, -0x85c,0x65a965a9, -0x860,0x001f0000, -0x864,0x007f0000, -0x868,0x001f0010, -0x86c,0x007f0010, -0x870,0x0f100f70, -0x874,0x0f100f70, -0x878,0x00000000, -0x87c,0x00000000, -0x880,0x5c385898, -0x884,0x6357060d, -0x888,0x0460c341, -0x88c,0x0000fc00, -0x890,0x00000000, -0x894,0xfffffffe, -0x898,0x4c42382f, -0x89c,0x00656056, -0x8b0,0x00000000, -0x8e0,0x00000000, -0x8e4,0x00000000, -0x900,0x00000000, -0x904,0x00000023, -0x908,0x00000000, -0x90c,0x34441444, -0xa00,0x00d0c7d8, -0xa04,0x2b1f0008, -0xa08,0x80cd8300, -0xa0c,0x2e62740f, -0xa10,0x95009b78, -0xa14,0x11145008, -0xa18,0x00881117, -0xa1c,0x89140fa0, -0xa20,0x1a1b0000, -0xa24,0x090e1317, -0xa28,0x00000204, -0xa2c,0x00000000, -0xc00,0x00000040, -0xc04,0x0000500c, -0xc08,0x000000e4, -0xc0c,0x6c6c6c6c, -0xc10,0x08000000, -0xc14,0x40000100, -0xc18,0x08000000, -0xc1c,0x40000100, -0xc20,0x08000000, -0xc24,0x40000100, -0xc28,0x08000000, -0xc2c,0x40000100, -0xc30,0x6de9ac44, -0xc34,0x164052cd, -0xc38,0x00070a14, -0xc3c,0x0a969764, -0xc40,0x1f7c403f, -0xc44,0x000100b7, -0xc48,0xec020000, -0xc4c,0x00000300, -0xc50,0x69543420, -0xc54,0x433c0094, -0xc58,0x69543420, -0xc5c,0x433c0094, -0xc60,0x69543420, -0xc64,0x433c0094, -0xc68,0x69543420, -0xc6c,0x433c0094, -0xc70,0x2c7f000d, -0xc74,0x0186175b, -0xc78,0x0000001f, -0xc7c,0x00b91612, -0xc80,0x40000100, -0xc84,0x00000000, -0xc88,0x40000100, -0xc8c,0x08000000, -0xc90,0x40000100, -0xc94,0x00000000, -0xc98,0x40000100, -0xc9c,0x00000000, -0xca0,0x00492492, -0xca4,0x00000000, -0xca8,0x00000000, -0xcac,0x00000000, -0xcb0,0x00000000, -0xcb4,0x00000000, -0xcb8,0x00000000, -0xcbc,0x00492492, -0xcc0,0x00000000, -0xcc4,0x00000000, -0xcc8,0x00000000, -0xccc,0x00000000, -0xcd0,0x00000000, -0xcd4,0x00000000, -0xcd8,0x64b22427, -0xcdc,0x00766932, -0xce0,0x00222222, -0xd00,0x00000740, -0xd04,0x0000040c, -0xd08,0x0000803f, -0xd0c,0x00000001, -0xd10,0xa0633333, -0xd14,0x33333c63, -0xd18,0x6a8f5b6b, -0xd1c,0x00000000, -0xd20,0x00000000, -0xd24,0x00000000, -0xd28,0x00000000, -0xd2c,0xcc979975, -0xd30,0x00000000, -0xd34,0x00000000, -0xd38,0x00000000, -0xd3c,0x00027293, -0xd40,0x00000000, -0xd44,0x00000000, -0xd48,0x00000000, -0xd4c,0x00000000, -0xd50,0x6437140a, -0xd54,0x024dbd02, -0xd58,0x00000000, -0xd5c,0x14032064, -}; -u32 Rtl8190PciRadioA_Array[RadioA_ArrayLength] = { -0x019,0x00000003, -0x000,0x000000bf, -0x001,0x00000ee0, -0x002,0x0000004c, -0x003,0x000007f1, -0x004,0x00000975, -0x005,0x00000c58, -0x006,0x00000ae6, -0x007,0x000000ca, -0x008,0x00000e1c, -0x009,0x000007f0, -0x00a,0x000009d0, -0x00b,0x000001ba, -0x00c,0x00000240, -0x00e,0x00000020, -0x00f,0x00000990, -0x012,0x00000806, -0x014,0x000005ab, -0x015,0x00000f80, -0x016,0x00000020, -0x017,0x00000597, -0x018,0x0000050a, -0x01a,0x00000f80, -0x01b,0x00000f5e, -0x01c,0x00000008, -0x01d,0x00000607, -0x01e,0x000006cc, -0x01f,0x00000000, -0x020,0x000001a5, -0x01f,0x00000001, -0x020,0x00000165, -0x01f,0x00000002, -0x020,0x000000c6, -0x01f,0x00000003, -0x020,0x00000086, -0x01f,0x00000004, -0x020,0x00000046, -0x01f,0x00000005, -0x020,0x000001e6, -0x01f,0x00000006, -0x020,0x000001a6, -0x01f,0x00000007, -0x020,0x00000166, -0x01f,0x00000008, -0x020,0x000000c7, -0x01f,0x00000009, -0x020,0x00000087, -0x01f,0x0000000a, -0x020,0x000000f7, -0x01f,0x0000000b, -0x020,0x000000d7, -0x01f,0x0000000c, -0x020,0x000000b7, -0x01f,0x0000000d, -0x020,0x00000097, -0x01f,0x0000000e, -0x020,0x00000077, -0x01f,0x0000000f, -0x020,0x00000057, -0x01f,0x00000010, -0x020,0x00000037, -0x01f,0x00000011, -0x020,0x000000fb, -0x01f,0x00000012, -0x020,0x000000db, -0x01f,0x00000013, -0x020,0x000000bb, -0x01f,0x00000014, -0x020,0x000000ff, -0x01f,0x00000015, -0x020,0x000000e3, -0x01f,0x00000016, -0x020,0x000000c3, -0x01f,0x00000017, -0x020,0x000000a3, -0x01f,0x00000018, -0x020,0x00000083, -0x01f,0x00000019, -0x020,0x00000063, -0x01f,0x0000001a, -0x020,0x00000043, -0x01f,0x0000001b, -0x020,0x00000023, -0x01f,0x0000001c, -0x020,0x00000003, -0x01f,0x0000001d, -0x020,0x000001e3, -0x01f,0x0000001e, -0x020,0x000001c3, -0x01f,0x0000001f, -0x020,0x000001a3, -0x01f,0x00000020, -0x020,0x00000183, -0x01f,0x00000021, -0x020,0x00000163, -0x01f,0x00000022, -0x020,0x00000143, -0x01f,0x00000023, -0x020,0x00000123, -0x01f,0x00000024, -0x020,0x00000103, -0x023,0x00000203, -0x024,0x00000200, -0x00b,0x000001ba, -0x02c,0x000003d7, -0x02d,0x00000ff0, -0x000,0x00000037, -0x004,0x00000160, -0x007,0x00000080, -0x002,0x0000088d, -0x0fe,0x00000000, -0x0fe,0x00000000, -0x016,0x00000200, -0x016,0x00000380, -0x016,0x00000020, -0x016,0x000001a0, -0x000,0x000000bf, -0x00d,0x0000001f, -0x00d,0x00000c9f, -0x002,0x0000004d, -0x000,0x00000cbf, -0x004,0x00000975, -0x007,0x00000700, -}; -u32 Rtl8190PciRadioB_Array[RadioB_ArrayLength] = { -0x019,0x00000003, -0x000,0x000000bf, -0x001,0x000006e0, -0x002,0x0000004c, -0x003,0x000007f1, -0x004,0x00000975, -0x005,0x00000c58, -0x006,0x00000ae6, -0x007,0x000000ca, -0x008,0x00000e1c, -0x000,0x000000b7, -0x00a,0x00000850, -0x000,0x000000bf, -0x00b,0x000001ba, -0x00c,0x00000240, -0x00e,0x00000020, -0x015,0x00000f80, -0x016,0x00000020, -0x017,0x00000597, -0x018,0x0000050a, -0x01a,0x00000e00, -0x01b,0x00000f5e, -0x01d,0x00000607, -0x01e,0x000006cc, -0x00b,0x000001ba, -0x023,0x00000203, -0x024,0x00000200, -0x000,0x00000037, -0x004,0x00000160, -0x016,0x00000200, -0x016,0x00000380, -0x016,0x00000020, -0x016,0x000001a0, -0x00d,0x00000ccc, -0x000,0x000000bf, -0x002,0x0000004d, -0x000,0x00000cbf, -0x004,0x00000975, -0x007,0x00000700, -}; -u32 Rtl8190PciRadioC_Array[RadioC_ArrayLength] = { -0x019,0x00000003, -0x000,0x000000bf, -0x001,0x00000ee0, -0x002,0x0000004c, -0x003,0x000007f1, -0x004,0x00000975, -0x005,0x00000c58, -0x006,0x00000ae6, -0x007,0x000000ca, -0x008,0x00000e1c, -0x009,0x000007f0, -0x00a,0x000009d0, -0x00b,0x000001ba, -0x00c,0x00000240, -0x00e,0x00000020, -0x00f,0x00000990, -0x012,0x00000806, -0x014,0x000005ab, -0x015,0x00000f80, -0x016,0x00000020, -0x017,0x00000597, -0x018,0x0000050a, -0x01a,0x00000f80, -0x01b,0x00000f5e, -0x01c,0x00000008, -0x01d,0x00000607, -0x01e,0x000006cc, -0x01f,0x00000000, -0x020,0x000001a5, -0x01f,0x00000001, -0x020,0x00000165, -0x01f,0x00000002, -0x020,0x000000c6, -0x01f,0x00000003, -0x020,0x00000086, -0x01f,0x00000004, -0x020,0x00000046, -0x01f,0x00000005, -0x020,0x000001e6, -0x01f,0x00000006, -0x020,0x000001a6, -0x01f,0x00000007, -0x020,0x00000166, -0x01f,0x00000008, -0x020,0x000000c7, -0x01f,0x00000009, -0x020,0x00000087, -0x01f,0x0000000a, -0x020,0x000000f7, -0x01f,0x0000000b, -0x020,0x000000d7, -0x01f,0x0000000c, -0x020,0x000000b7, -0x01f,0x0000000d, -0x020,0x00000097, -0x01f,0x0000000e, -0x020,0x00000077, -0x01f,0x0000000f, -0x020,0x00000057, -0x01f,0x00000010, -0x020,0x00000037, -0x01f,0x00000011, -0x020,0x000000fb, -0x01f,0x00000012, -0x020,0x000000db, -0x01f,0x00000013, -0x020,0x000000bb, -0x01f,0x00000014, -0x020,0x000000ff, -0x01f,0x00000015, -0x020,0x000000e3, -0x01f,0x00000016, -0x020,0x000000c3, -0x01f,0x00000017, -0x020,0x000000a3, -0x01f,0x00000018, -0x020,0x00000083, -0x01f,0x00000019, -0x020,0x00000063, -0x01f,0x0000001a, -0x020,0x00000043, -0x01f,0x0000001b, -0x020,0x00000023, -0x01f,0x0000001c, -0x020,0x00000003, -0x01f,0x0000001d, -0x020,0x000001e3, -0x01f,0x0000001e, -0x020,0x000001c3, -0x01f,0x0000001f, -0x020,0x000001a3, -0x01f,0x00000020, -0x020,0x00000183, -0x01f,0x00000021, -0x020,0x00000163, -0x01f,0x00000022, -0x020,0x00000143, -0x01f,0x00000023, -0x020,0x00000123, -0x01f,0x00000024, -0x020,0x00000103, -0x023,0x00000203, -0x024,0x00000200, -0x00b,0x000001ba, -0x02c,0x000003d7, -0x02d,0x00000ff0, -0x000,0x00000037, -0x004,0x00000160, -0x007,0x00000080, -0x002,0x0000088d, -0x0fe,0x00000000, -0x0fe,0x00000000, -0x016,0x00000200, -0x016,0x00000380, -0x016,0x00000020, -0x016,0x000001a0, -0x000,0x000000bf, -0x00d,0x0000001f, -0x00d,0x00000c9f, -0x002,0x0000004d, -0x000,0x00000cbf, -0x004,0x00000975, -0x007,0x00000700, -}; -u32 Rtl8190PciRadioD_Array[RadioD_ArrayLength] = { -0x019,0x00000003, -0x000,0x000000bf, -0x001,0x000006e0, -0x002,0x0000004c, -0x003,0x000007f1, -0x004,0x00000975, -0x005,0x00000c58, -0x006,0x00000ae6, -0x007,0x000000ca, -0x008,0x00000e1c, -0x000,0x000000b7, -0x00a,0x00000850, -0x000,0x000000bf, -0x00b,0x000001ba, -0x00c,0x00000240, -0x00e,0x00000020, -0x015,0x00000f80, -0x016,0x00000020, -0x017,0x00000597, -0x018,0x0000050a, -0x01a,0x00000e00, -0x01b,0x00000f5e, -0x01d,0x00000607, -0x01e,0x000006cc, -0x00b,0x000001ba, -0x023,0x00000203, -0x024,0x00000200, -0x000,0x00000037, -0x004,0x00000160, -0x016,0x00000200, -0x016,0x00000380, -0x016,0x00000020, -0x016,0x000001a0, -0x00d,0x00000ccc, -0x000,0x000000bf, -0x002,0x0000004d, -0x000,0x00000cbf, -0x004,0x00000975, -0x007,0x00000700, -}; -#endif -#ifdef RTL8192E static u32 Rtl8192PciEMACPHY_Array[] = { 0x03c,0xffff0000,0x00000f0f, 0x340,0xffffffff,0x161a1a1a, @@ -1393,12 +561,12 @@ static u32 Rtl8192PciERadioC_Array[RadioC_ArrayLength] = { 0x0, }; static u32 Rtl8192PciERadioD_Array[RadioD_ArrayLength] = { 0x0, }; -#endif /*************************Define local function prototype**********************/ -static u32 phy_FwRFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset); -static void phy_FwRFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32 Data); +static u32 phy_FwRFSerialRead(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath, u32 Offset); +static void phy_FwRFSerialWrite(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data); + /*************************Define local function prototype**********************/ /****************************************************************************** *function: This function read BB parameters from Header file we gen, @@ -1423,24 +591,10 @@ static u32 rtl8192_CalculateBitShift(u32 dwBitMask) * output: none * return: 0(illegal, false), 1(legal,true) * ***************************************************************************/ -u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath) +u8 rtl8192_phy_CheckIsLegalRFPath(struct r8192_priv *priv, u32 eRFPath) { u8 ret = 1; - struct r8192_priv *priv = ieee80211_priv(dev); -#ifdef RTL8190P - if(priv->rf_type == RF_2T4R) - { - ret= 1; - } - else if (priv->rf_type == RF_1T2R) - { - if(eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) - ret = 0; - else if(eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) - ret = 1; - } -#else - #ifdef RTL8192E + if (priv->rf_type == RF_2T4R) ret = 0; else if (priv->rf_type == RF_1T2R) @@ -1450,8 +604,7 @@ u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath) else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) ret = 0; } - #endif -#endif + return ret; } /****************************************************************************** @@ -1464,19 +617,18 @@ u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath) * return: none * notice: * ****************************************************************************/ -void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData) +void rtl8192_setBBreg(struct r8192_priv *priv, u32 dwRegAddr, u32 dwBitMask, u32 dwData) { - u32 OriginalValue, BitShift, NewValue; if(dwBitMask!= bMaskDWord) {//if not "double word" write - OriginalValue = read_nic_dword(dev, dwRegAddr); + OriginalValue = read_nic_dword(priv, dwRegAddr); BitShift = rtl8192_CalculateBitShift(dwBitMask); NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift)); - write_nic_dword(dev, dwRegAddr, NewValue); + write_nic_dword(priv, dwRegAddr, NewValue); }else - write_nic_dword(dev, dwRegAddr, dwData); + write_nic_dword(priv, dwRegAddr, dwData); } /****************************************************************************** *function: This function reads specific bits from BB register @@ -1487,11 +639,11 @@ void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 * return: u32 Data //the readback register value * notice: * ****************************************************************************/ -u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask) +u32 rtl8192_QueryBBReg(struct r8192_priv *priv, u32 dwRegAddr, u32 dwBitMask) { u32 OriginalValue, BitShift; - OriginalValue = read_nic_dword(dev, dwRegAddr); + OriginalValue = read_nic_dword(priv, dwRegAddr); BitShift = rtl8192_CalculateBitShift(dwBitMask); return (OriginalValue & dwBitMask) >> BitShift; } @@ -1504,9 +656,9 @@ u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask) * return: u32 readback value * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information. * ****************************************************************************/ -static u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset) +static u32 rtl8192_phy_RFSerialRead(struct r8192_priv *priv, + RF90_RADIO_PATH_E eRFPath, u32 Offset) { - struct r8192_priv *priv = ieee80211_priv(dev); u32 ret = 0; u32 NewOffset = 0; BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath]; @@ -1515,89 +667,55 @@ static u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eR Offset &= 0x3f; //switch page for 8256 RF IC - if (priv->rf_chip == RF_8256) + //analog to digital off, for protection + rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] + if (Offset >= 31) { -#ifdef RTL8190P - //analog to digital off, for protection - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] -#else - #ifdef RTL8192E - //analog to digital off, for protection - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] - #endif -#endif - if (Offset >= 31) - { - priv->RfReg0Value[eRFPath] |= 0x140; - //Switch to Reg_Mode2 for Reg 31-45 - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); - //modify offset - NewOffset = Offset -30; - } - else if (Offset >= 16) - { - priv->RfReg0Value[eRFPath] |= 0x100; - priv->RfReg0Value[eRFPath] &= (~0x40); - //Switch to Reg_Mode 1 for Reg16-30 - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); + priv->RfReg0Value[eRFPath] |= 0x140; + //Switch to Reg_Mode2 for Reg 31-45 + rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); + //modify offset + NewOffset = Offset -30; + } + else if (Offset >= 16) + { + priv->RfReg0Value[eRFPath] |= 0x100; + priv->RfReg0Value[eRFPath] &= (~0x40); + //Switch to Reg_Mode 1 for Reg16-30 + rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); - NewOffset = Offset - 15; - } - else - NewOffset = Offset; + NewOffset = Offset - 15; } else - { - RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n"); NewOffset = Offset; - } + //put desired read addr to LSSI control Register - rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset); + rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset); //Issue a posedge trigger // - rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); - rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); + rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); + rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); // TODO: we should not delay such a long time. Ask help from SD3 msleep(1); - ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); + ret = rtl8192_QueryBBReg(priv, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); // Switch back to Reg_Mode0; - if(priv->rf_chip == RF_8256) - { - priv->RfReg0Value[eRFPath] &= 0xebf; + priv->RfReg0Value[eRFPath] &= 0xebf; - rtl8192_setBBreg( - dev, - pPhyReg->rf3wireOffset, - bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16)); - -#ifdef RTL8190P - if(priv->rf_type == RF_2T4R) - { - //analog to digital on - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8] - } - else if(priv->rf_type == RF_1T2R) - { - //analog to digital on - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10] - } -#else - #ifdef RTL8192E - //analog to digital on - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] - #endif -#endif - } + rtl8192_setBBreg( + priv, + pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16)); + //analog to digital on + rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] return ret; - } /****************************************************************************** @@ -1620,94 +738,61 @@ static u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eR * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) *------------------------------------------------------------------ * ****************************************************************************/ -static void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data) +static void rtl8192_phy_RFSerialWrite(struct r8192_priv *priv, + RF90_RADIO_PATH_E eRFPath, u32 Offset, + u32 Data) { - struct r8192_priv *priv = ieee80211_priv(dev); u32 DataAndAddr = 0, NewOffset = 0; BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; Offset &= 0x3f; - if (priv->rf_chip == RF_8256) - { -#ifdef RTL8190P - //analog to digital off, for protection - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] -#else - #ifdef RTL8192E - //analog to digital off, for protection - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] - #endif -#endif + //analog to digital off, for protection + rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] - if (Offset >= 31) - { - priv->RfReg0Value[eRFPath] |= 0x140; - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16)); - NewOffset = Offset - 30; - } - else if (Offset >= 16) - { - priv->RfReg0Value[eRFPath] |= 0x100; - priv->RfReg0Value[eRFPath] &= (~0x40); - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16)); - NewOffset = Offset - 15; - } - else - NewOffset = Offset; + if (Offset >= 31) + { + priv->RfReg0Value[eRFPath] |= 0x140; + rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16)); + NewOffset = Offset - 30; } - else + else if (Offset >= 16) { - RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n"); - NewOffset = Offset; + priv->RfReg0Value[eRFPath] |= 0x100; + priv->RfReg0Value[eRFPath] &= (~0x40); + rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16)); + NewOffset = Offset - 15; } + else + NewOffset = Offset; // Put write addr in [5:0] and write data in [31:16] DataAndAddr = (Data<<16) | (NewOffset&0x3f); // Write Operation - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); + rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); if(Offset==0x0) priv->RfReg0Value[eRFPath] = Data; // Switch back to Reg_Mode0; - if(priv->rf_chip == RF_8256) + if(Offset != 0) { - if(Offset != 0) - { - priv->RfReg0Value[eRFPath] &= 0xebf; - rtl8192_setBBreg( - dev, - pPhyReg->rf3wireOffset, - bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16)); - } -#ifdef RTL8190P - if(priv->rf_type == RF_2T4R) - { - //analog to digital on - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8] - } - else if(priv->rf_type == RF_1T2R) - { - //analog to digital on - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10] - } -#else - #ifdef RTL8192E - //analog to digital on - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] - #endif -#endif + priv->RfReg0Value[eRFPath] &= 0xebf; + rtl8192_setBBreg( + priv, + pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16)); } + //analog to digital on + rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] } /****************************************************************************** *function: This function set specific bits to RF register - * input: net_device dev - * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D + * input: RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D * u32 RegAddr //target addr to be modified * u32 BitMask //taget bit pos in the addr to be modified * u32 Data //value to be write @@ -1715,19 +800,16 @@ static void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E * return: none * notice: * ****************************************************************************/ -void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data) +void rtl8192_phy_SetRFReg(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath, + u32 RegAddr, u32 BitMask, u32 Data) { - struct r8192_priv *priv = ieee80211_priv(dev); u32 Original_Value, BitShift, New_Value; // u8 time = 0; - if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) + if (!rtl8192_phy_CheckIsLegalRFPath(priv, eRFPath)) return; -#ifdef RTL8192E - if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter) + if (priv->eRFPowerState != eRfOn && !priv->being_init_adapter) return; -#endif - //spin_lock_irqsave(&priv->rf_lock, flags); //down(&priv->rf_sem); RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n"); @@ -1735,13 +817,13 @@ void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 { if (BitMask != bMask12Bits) // RF data is 12 bits only { - Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); + Original_Value = phy_FwRFSerialRead(priv, eRFPath, RegAddr); BitShift = rtl8192_CalculateBitShift(BitMask); New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); - phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value); + phy_FwRFSerialWrite(priv, eRFPath, RegAddr, New_Value); }else - phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data); + phy_FwRFSerialWrite(priv, eRFPath, RegAddr, Data); udelay(200); } @@ -1749,15 +831,14 @@ void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 { if (BitMask != bMask12Bits) // RF data is 12 bits only { - Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); + Original_Value = rtl8192_phy_RFSerialRead(priv, eRFPath, RegAddr); BitShift = rtl8192_CalculateBitShift(BitMask); New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); - rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value); + rtl8192_phy_RFSerialWrite(priv, eRFPath, RegAddr, New_Value); }else - rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data); + rtl8192_phy_RFSerialWrite(priv, eRFPath, RegAddr, Data); } - //spin_unlock_irqrestore(&priv->rf_lock, flags); //up(&priv->rf_sem); } @@ -1770,25 +851,24 @@ void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 * return: u32 Data //the readback register value * notice: * ****************************************************************************/ -u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask) +u32 rtl8192_phy_QueryRFReg(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath, + u32 RegAddr, u32 BitMask) { u32 Original_Value, Readback_Value, BitShift; - struct r8192_priv *priv = ieee80211_priv(dev); - if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) + + if (!rtl8192_phy_CheckIsLegalRFPath(priv, eRFPath)) return 0; -#ifdef RTL8192E - if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter) + if (priv->eRFPowerState != eRfOn && !priv->being_init_adapter) return 0; -#endif down(&priv->rf_sem); if (priv->Rf_Mode == RF_OP_By_FW) { - Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); + Original_Value = phy_FwRFSerialRead(priv, eRFPath, RegAddr); udelay(200); } else { - Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); + Original_Value = rtl8192_phy_RFSerialRead(priv, eRFPath, RegAddr); } BitShift = rtl8192_CalculateBitShift(BitMask); @@ -1805,10 +885,8 @@ u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u3 * return: none * notice: * ***************************************************************************/ -static u32 phy_FwRFSerialRead( - struct net_device* dev, - RF90_RADIO_PATH_E eRFPath, - u32 Offset ) +static u32 phy_FwRFSerialRead(struct r8192_priv *priv, + RF90_RADIO_PATH_E eRFPath, u32 Offset) { u32 Data = 0; u8 time = 0; @@ -1827,7 +905,7 @@ static u32 phy_FwRFSerialRead( // 5. Trigger Fw to operate the command. bit 31 Data |= 0x80000000; // 6. We can not execute read operation if bit 31 is 1. - while (read_nic_dword(dev, QPNR)&0x80000000) + while (read_nic_dword(priv, QPNR)&0x80000000) { // If FW can not finish RF-R/W for more than ?? times. We must reset FW. if (time++ < 100) @@ -1839,9 +917,9 @@ static u32 phy_FwRFSerialRead( break; } // 7. Execute read operation. - write_nic_dword(dev, QPNR, Data); + write_nic_dword(priv, QPNR, Data); // 8. Check if firmawre send back RF content. - while (read_nic_dword(dev, QPNR)&0x80000000) + while (read_nic_dword(priv, QPNR)&0x80000000) { // If FW can not finish RF-R/W for more than ?? times. We must reset FW. if (time++ < 100) @@ -1852,7 +930,7 @@ static u32 phy_FwRFSerialRead( else return 0; } - return read_nic_dword(dev, RF_DATA); + return read_nic_dword(priv, RF_DATA); } /****************************************************************************** @@ -1862,12 +940,8 @@ static u32 phy_FwRFSerialRead( * return: none * notice: * ***************************************************************************/ -static void -phy_FwRFSerialWrite( - struct net_device* dev, - RF90_RADIO_PATH_E eRFPath, - u32 Offset, - u32 Data ) +static void phy_FwRFSerialWrite(struct r8192_priv *priv, + RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data) { u8 time = 0; @@ -1888,7 +962,7 @@ phy_FwRFSerialWrite( Data |= 0x80000000; // 6. Write operation. We can not write if bit 31 is 1. - while (read_nic_dword(dev, QPNR)&0x80000000) + while (read_nic_dword(priv, QPNR)&0x80000000) { // If FW can not finish RF-R/W for more than ?? times. We must reset FW. if (time++ < 100) @@ -1901,7 +975,7 @@ phy_FwRFSerialWrite( } // 7. No matter check bit. We always force the write. Because FW will // not accept the command. - write_nic_dword(dev, QPNR, Data); + write_nic_dword(priv, QPNR, Data); /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware to finish RF write operation. */ /* 2008/01/17 MH We support delay in firmware side now. */ @@ -1919,11 +993,10 @@ phy_FwRFSerialWrite( * notice: BB parameters may change all the time, so please make * sure it has been synced with the newest. * ***************************************************************************/ -void rtl8192_phy_configmac(struct net_device* dev) +void rtl8192_phy_configmac(struct r8192_priv *priv) { u32 dwArrayLen = 0, i = 0; u32* pdwArray = NULL; - struct r8192_priv *priv = ieee80211_priv(dev); #ifdef TO_DO_LIST if(Adapter->bInHctTest) { @@ -1955,7 +1028,7 @@ if(Adapter->bInHctTest) //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n", // ptrArray[i], ptrArray[i+1], ptrArray[i+2]); } - rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]); + rtl8192_setBBreg(priv, pdwArray[i], pdwArray[i+1], pdwArray[i+2]); } } @@ -1968,14 +1041,13 @@ if(Adapter->bInHctTest) * sure it has been synced with the newest. * ***************************************************************************/ -void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType) +void rtl8192_phyConfigBB(struct r8192_priv *priv, u8 ConfigType) { int i; //u8 ArrayLength; u32* Rtl819XPHY_REGArray_Table = NULL; u32* Rtl819XAGCTAB_Array_Table = NULL; u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0; - struct r8192_priv *priv = ieee80211_priv(dev); #ifdef TO_DO_LIST u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL; if(Adapter->bInHctTest) @@ -2015,16 +1087,16 @@ void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType) { for (i=0; i<PHY_REGArrayLen; i+=2) { - rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]); - RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]); + rtl8192_setBBreg(priv, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]); + RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",i, Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]); } } else if (ConfigType == BaseBand_Config_AGC_TAB) { for (i=0; i<AGCTAB_ArrayLen; i+=2) { - rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]); - RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]); + rtl8192_setBBreg(priv, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]); + RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x\n",i, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]); } } } @@ -2036,9 +1108,8 @@ void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType) * return: none * notice: Initialization value here is constant and it should never be changed * ***************************************************************************/ -static void rtl8192_InitBBRFRegDef(struct net_device* dev) +static void rtl8192_InitBBRFRegDef(struct r8192_priv *priv) { - struct r8192_priv *priv = ieee80211_priv(dev); // RF Interface Sowrtware Control priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) @@ -2151,9 +1222,10 @@ static void rtl8192_InitBBRFRegDef(struct net_device* dev) * return: return whether BB and RF is ok(0:OK; 1:Fail) * notice: This function may be removed in the ASIC * ***************************************************************************/ -RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath) +RT_STATUS rtl8192_phy_checkBBAndRF(struct r8192_priv *priv, + HW90_BLOCK_E CheckBlock, + RF90_RADIO_PATH_E eRFPath) { - //struct r8192_priv *priv = ieee80211_priv(dev); // BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; RT_STATUS ret = RT_STATUS_SUCCESS; u32 i, CheckTimes = 4, dwRegRead = 0; @@ -2174,21 +1246,21 @@ RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlo switch(CheckBlock) { case HW90_BLOCK_MAC: - RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!"); + RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!\n"); break; case HW90_BLOCK_PHY0: case HW90_BLOCK_PHY1: - write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]); - dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]); + write_nic_dword(priv, WriteAddr[CheckBlock], WriteData[i]); + dwRegRead = read_nic_dword(priv, WriteAddr[CheckBlock]); break; case HW90_BLOCK_RF: WriteData[i] &= 0xfff; - rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]); + rtl8192_phy_SetRFReg(priv, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]); // TODO: we should not delay for such a long time. Ask SD3 mdelay(10); - dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord); + dwRegRead = rtl8192_phy_QueryRFReg(priv, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord); mdelay(10); break; @@ -2203,7 +1275,7 @@ RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlo // if(dwRegRead != WriteData[i]) { - RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]); + RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, WriteData: %x\n", dwRegRead, WriteData[i]); ret = RT_STATUS_FAILURE; break; } @@ -2221,10 +1293,10 @@ RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlo * notice: Initialization value may change all the time, so please make * sure it has been synced with the newest. * ***************************************************************************/ -static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev) +static RT_STATUS rtl8192_BB_Config_ParaFile(struct r8192_priv *priv) { - struct r8192_priv *priv = ieee80211_priv(dev); RT_STATUS rtStatus = RT_STATUS_SUCCESS; + u8 bRegValue = 0, eCheckItem = 0; u32 dwRegValue = 0; /************************************** @@ -2232,18 +1304,18 @@ static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev) **************************************/ /*--set BB Global Reset--*/ - bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET); - write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT)); + bRegValue = read_nic_byte(priv, BB_GLOBAL_RESET); + write_nic_byte(priv, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT)); /*---set BB reset Active---*/ - dwRegValue = read_nic_dword(dev, CPU_GEN); - write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); + dwRegValue = read_nic_dword(priv, CPU_GEN); + write_nic_dword(priv, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/ // TODO: this function should be removed on ASIC , Emily 2007.2.2 for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++) { - rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path + rtStatus = rtl8192_phy_checkBBAndRF(priv, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path if(rtStatus != RT_STATUS_SUCCESS) { RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1); @@ -2251,18 +1323,18 @@ static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev) } } /*---- Set CCK and OFDM Block "OFF"----*/ - rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); + rtl8192_setBBreg(priv, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); /*----BB Register Initilazation----*/ //==m==>Set PHY REG From Header<==m== - rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG); + rtl8192_phyConfigBB(priv, BaseBand_Config_PHY_REG); /*----Set BB reset de-Active----*/ - dwRegValue = read_nic_dword(dev, CPU_GEN); - write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); + dwRegValue = read_nic_dword(priv, CPU_GEN); + write_nic_dword(priv, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); /*----BB AGC table Initialization----*/ //==m==>Set PHY REG From Header<==m== - rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB); + rtl8192_phyConfigBB(priv, BaseBand_Config_AGC_TAB); if (priv->card_8192_version > VERSION_8190_BD) { @@ -2275,23 +1347,13 @@ static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev) } else dwRegValue = 0x0; //Antenna gain offset doesn't make sense in RF 1T2R. - rtl8192_setBBreg(dev, rFPGA0_TxGainStage, + rtl8192_setBBreg(priv, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue); //XSTALLCap -#ifdef RTL8190P - dwRegValue = priv->CrystalCap & 0x3; // bit0~1 of crystal cap - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap01, dwRegValue); - dwRegValue = ((priv->CrystalCap & 0xc)>>2); // bit2~3 of crystal cap - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, bXtalCap23, dwRegValue); -#else - #ifdef RTL8192E dwRegValue = priv->CrystalCap; - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue); - #endif -#endif - + rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue); } // Check if the CCK HighPower is turned ON. @@ -2307,12 +1369,12 @@ static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev) * notice: Initialization value may change all the time, so please make * sure it has been synced with the newest. * ***************************************************************************/ -RT_STATUS rtl8192_BBConfig(struct net_device* dev) +RT_STATUS rtl8192_BBConfig(struct r8192_priv *priv) { - rtl8192_InitBBRFRegDef(dev); + rtl8192_InitBBRFRegDef(priv); //config BB&RF. As hardCode based initialization has not been well //implemented, so use file first.FIXME:should implement it for hardcode? - return rtl8192_BB_Config_ParaFile(dev); + return rtl8192_BB_Config_ParaFile(priv); } /****************************************************************************** @@ -2321,49 +1383,37 @@ RT_STATUS rtl8192_BBConfig(struct net_device* dev) * output: none * return: none * ***************************************************************************/ -void rtl8192_phy_getTxPower(struct net_device* dev) +void rtl8192_phy_getTxPower(struct r8192_priv *priv) { - struct r8192_priv *priv = ieee80211_priv(dev); -#ifdef RTL8190P - priv->MCSTxPowerLevelOriginalOffset[0] = - read_nic_dword(dev, MCS_TXAGC); - priv->MCSTxPowerLevelOriginalOffset[1] = - read_nic_dword(dev, (MCS_TXAGC+4)); - priv->CCKTxPowerLevelOriginalOffset = - read_nic_dword(dev, CCK_TXAGC); -#else - #ifdef RTL8192E priv->MCSTxPowerLevelOriginalOffset[0] = - read_nic_dword(dev, rTxAGC_Rate18_06); + read_nic_dword(priv, rTxAGC_Rate18_06); priv->MCSTxPowerLevelOriginalOffset[1] = - read_nic_dword(dev, rTxAGC_Rate54_24); + read_nic_dword(priv, rTxAGC_Rate54_24); priv->MCSTxPowerLevelOriginalOffset[2] = - read_nic_dword(dev, rTxAGC_Mcs03_Mcs00); + read_nic_dword(priv, rTxAGC_Mcs03_Mcs00); priv->MCSTxPowerLevelOriginalOffset[3] = - read_nic_dword(dev, rTxAGC_Mcs07_Mcs04); + read_nic_dword(priv, rTxAGC_Mcs07_Mcs04); priv->MCSTxPowerLevelOriginalOffset[4] = - read_nic_dword(dev, rTxAGC_Mcs11_Mcs08); + read_nic_dword(priv, rTxAGC_Mcs11_Mcs08); priv->MCSTxPowerLevelOriginalOffset[5] = - read_nic_dword(dev, rTxAGC_Mcs15_Mcs12); - #endif -#endif + read_nic_dword(priv, rTxAGC_Mcs15_Mcs12); // read rx initial gain - priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1); - priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1); - priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1); - priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1); - RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n", + priv->DefaultInitialGain[0] = read_nic_byte(priv, rOFDM0_XAAGCCore1); + priv->DefaultInitialGain[1] = read_nic_byte(priv, rOFDM0_XBAGCCore1); + priv->DefaultInitialGain[2] = read_nic_byte(priv, rOFDM0_XCAGCCore1); + priv->DefaultInitialGain[3] = read_nic_byte(priv, rOFDM0_XDAGCCore1); + RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n", priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); // read framesync - priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3); - priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2); - RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n", + priv->framesync = read_nic_byte(priv, rOFDM0_RxDetector3); + priv->framesyncC34 = read_nic_dword(priv, rOFDM0_RxDetector2); + RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n", rOFDM0_RxDetector3, priv->framesync); // read SIFS (save the value read fome MACPHY_REG.txt) - priv->SifsTime = read_nic_word(dev, SIFS); + priv->SifsTime = read_nic_word(priv, SIFS); } /****************************************************************************** @@ -2372,9 +1422,8 @@ void rtl8192_phy_getTxPower(struct net_device* dev) * output: none * return: none * ***************************************************************************/ -void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel) +void rtl8192_phy_setTxPower(struct r8192_priv *priv, u8 channel) { - struct r8192_priv *priv = ieee80211_priv(dev); u8 powerlevel = 0,powerlevelOFDM24G = 0; char ant_pwr_diff; u32 u4RegValue; @@ -2402,8 +1451,6 @@ void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel) ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1] -priv->TxPowerLevelOFDM24G_A[channel-1]; ant_pwr_diff &= 0xf; - //DbgPrint(" ant_pwr_diff = 0x%x", (u8)(ant_pwr_diff)); - priv->RF_C_TxPwDiff = ant_pwr_diff; priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);// RF-C @@ -2414,7 +1461,7 @@ void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel) priv->AntennaTxPwDiff[1]<<4 | priv->AntennaTxPwDiff[0]); - rtl8192_setBBreg(dev, rFPGA0_TxGainStage, + rtl8192_setBBreg(priv, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); } } @@ -2469,22 +1516,8 @@ void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel) pHalData->CurrentCckTxPwrIdx = powerlevel; pHalData->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G; #endif - switch(priv->rf_chip) - { - case RF_8225: - // PHY_SetRF8225CckTxPower(Adapter, powerlevel); - // PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G); - break; - case RF_8256: - PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement - PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); - break; - case RF_8258: - break; - default: - RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n", __FUNCTION__); - break; - } + PHY_SetRF8256CCKTxPower(priv, powerlevel); //need further implement + PHY_SetRF8256OFDMTxPower(priv, powerlevelOFDM24G); } /****************************************************************************** @@ -2493,30 +1526,9 @@ void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel) * output: none * return: only 8256 is supported * ***************************************************************************/ -RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev) +RT_STATUS rtl8192_phy_RFConfig(struct r8192_priv *priv) { - struct r8192_priv *priv = ieee80211_priv(dev); - RT_STATUS rtStatus = RT_STATUS_SUCCESS; - switch(priv->rf_chip) - { - case RF_8225: -// rtStatus = PHY_RF8225_Config(Adapter); - break; - case RF_8256: - rtStatus = PHY_RF8256_Config(dev); - break; - - case RF_8258: - break; - case RF_PSEUDO_11N: - //rtStatus = PHY_RF8225_Config(Adapter); - break; - - default: - RT_TRACE(COMP_ERR, "error chip id\n"); - break; - } - return rtStatus; + return PHY_RF8256_Config(priv); } /****************************************************************************** @@ -2525,7 +1537,7 @@ RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev) * output: none * return: As Windows has not implemented this, wait for complement * ***************************************************************************/ -void rtl8192_phy_updateInitGain(struct net_device* dev) +void rtl8192_phy_updateInitGain(struct r8192_priv *priv) { } @@ -2536,7 +1548,8 @@ void rtl8192_phy_updateInitGain(struct net_device* dev) * return: return code show if RF configuration is successful(0:pass, 1:fail) * Note: Delay may be required for RF configuration * ***************************************************************************/ -u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath) +u8 rtl8192_phy_ConfigRFWithHeaderFile(struct r8192_priv *priv, + RF90_RADIO_PATH_E eRFPath) { int i; @@ -2551,7 +1564,7 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E msleep(100); continue; } - rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array[i], bMask12Bits, Rtl819XRadioA_Array[i+1]); + rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioA_Array[i], bMask12Bits, Rtl819XRadioA_Array[i+1]); //msleep(1); } @@ -2563,7 +1576,7 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E msleep(100); continue; } - rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array[i], bMask12Bits, Rtl819XRadioB_Array[i+1]); + rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioB_Array[i], bMask12Bits, Rtl819XRadioB_Array[i+1]); //msleep(1); } @@ -2575,7 +1588,7 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E msleep(100); continue; } - rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioC_Array[i], bMask12Bits, Rtl819XRadioC_Array[i+1]); + rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioC_Array[i], bMask12Bits, Rtl819XRadioC_Array[i+1]); //msleep(1); } @@ -2587,7 +1600,7 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E msleep(100); continue; } - rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioD_Array[i], bMask12Bits, Rtl819XRadioD_Array[i+1]); + rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioD_Array[i], bMask12Bits, Rtl819XRadioD_Array[i+1]); //msleep(1); } @@ -2607,33 +1620,15 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E * return: none * Note: * ***************************************************************************/ -static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) +static void rtl8192_SetTxPowerLevel(struct r8192_priv *priv, u8 channel) { - struct r8192_priv *priv = ieee80211_priv(dev); u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; - switch(priv->rf_chip) - { - case RF_8225: -#ifdef TO_DO_LIST - PHY_SetRF8225CckTxPower(Adapter, powerlevel); - PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G); -#endif - break; - - case RF_8256: - PHY_SetRF8256CCKTxPower(dev, powerlevel); - PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); - break; - - case RF_8258: - break; - default: - RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n"); - break; - } + PHY_SetRF8256CCKTxPower(priv, powerlevel); + PHY_SetRF8256OFDMTxPower(priv, powerlevelOFDM24G); } + /**************************************************************************************** *function: This function set command table variable(struct SwChnlCmd). * input: SwChnlCmd* CmdTable //table to be set. @@ -2690,9 +1685,9 @@ static u8 rtl8192_phy_SetSwChnlCmdArray( * return: true if finished, false otherwise * Note: Wait for simpler function to replace it //wb * ***************************************************************************/ -static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay) +static u8 rtl8192_phy_SwChnlStepByStep(struct r8192_priv *priv, u8 channel, + u8* stage, u8* step, u32* delay) { - struct r8192_priv *priv = ieee80211_priv(dev); // PCHANNEL_ACCESS_SETTING pChnlAccessSetting; SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT]; u32 PreCommonCmdCnt; @@ -2737,42 +1732,17 @@ static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* s // <3> Fill up RF dependent command. RfDependCmdCnt = 0; - switch( priv->rf_chip ) - { - case RF_8225: - if (!(channel >= 1 && channel <= 14)) - { - RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel); - return false; - } - rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, - CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10); - rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, - CmdID_End, 0, 0, 0); - break; - - case RF_8256: - // TEST!! This is not the table for 8256!! - if (!(channel >= 1 && channel <= 14)) - { - RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel); - return false; - } - rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, - CmdID_RF_WriteReg, rZebra1_Channel, channel, 10); - rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, - CmdID_End, 0, 0, 0); - break; - - case RF_8258: - break; - default: - RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); + // TEST!! This is not the table for 8256!! + if (!(channel >= 1 && channel <= 14)) + { + RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel); return false; - break; } - + rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, + CmdID_RF_WriteReg, rZebra1_Channel, channel, 10); + rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, + CmdID_End, 0, 0, 0); do{ switch(*stage) @@ -2806,20 +1776,20 @@ static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* s { case CmdID_SetTxPowerLevel: if(priv->card_8192_version > (u8)VERSION_8190_BD) //xiong: consider it later! - rtl8192_SetTxPowerLevel(dev,channel); + rtl8192_SetTxPowerLevel(priv, channel); break; case CmdID_WritePortUlong: - write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2); + write_nic_dword(priv, CurrentCmd->Para1, CurrentCmd->Para2); break; case CmdID_WritePortUshort: - write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2); + write_nic_word(priv, CurrentCmd->Para1, (u16)CurrentCmd->Para2); break; case CmdID_WritePortUchar: - write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2); + write_nic_byte(priv, CurrentCmd->Para1, (u8)CurrentCmd->Para2); break; case CmdID_RF_WriteReg: for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) - rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7); + rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7); break; default: break; @@ -2842,12 +1812,11 @@ static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* s * return: noin * Note: We should not call this function directly * ***************************************************************************/ -static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) +static void rtl8192_phy_FinishSwChnlNow(struct r8192_priv *priv, u8 channel) { - struct r8192_priv *priv = ieee80211_priv(dev); u32 delay = 0; - while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay)) + while (!rtl8192_phy_SwChnlStepByStep(priv, channel, &priv->SwChnlStage, &priv->SwChnlStep, &delay)) { if(delay>0) msleep(delay);//or mdelay? need further consideration @@ -2862,16 +1831,13 @@ static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) * output: none * return: noin * ***************************************************************************/ -void rtl8192_SwChnl_WorkItem(struct net_device *dev) +void rtl8192_SwChnl_WorkItem(struct r8192_priv *priv) { - - struct r8192_priv *priv = ieee80211_priv(dev); - RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n"); RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __FUNCTION__, priv->chan, priv); - rtl8192_phy_FinishSwChnlNow(dev , priv->chan); + rtl8192_phy_FinishSwChnlNow(priv, priv->chan); RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n"); } @@ -2884,9 +1850,10 @@ void rtl8192_SwChnl_WorkItem(struct net_device *dev) * return: return code show if workitem is scheduled(1:pass, 0:fail) * Note: Delay may be required for RF configuration * ***************************************************************************/ -u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel) +u8 rtl8192_phy_SwChnl(struct ieee80211_device *ieee80211, u8 channel) { - struct r8192_priv *priv = ieee80211_priv(dev); + struct r8192_priv *priv = ieee80211_priv(ieee80211->dev); + RT_TRACE(COMP_PHY, "=====>%s()\n", __FUNCTION__); if(!priv->up) return false; @@ -2902,20 +1869,20 @@ u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel) case WIRELESS_MODE_A: case WIRELESS_MODE_N_5G: if (channel<=14){ - RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14"); + RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n"); return false; } break; case WIRELESS_MODE_B: if (channel>14){ - RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14"); + RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n"); return false; } break; case WIRELESS_MODE_G: case WIRELESS_MODE_N_24G: if (channel>14){ - RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14"); + RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n"); return false; } break; @@ -2930,20 +1897,15 @@ u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel) priv->SwChnlStage=0; priv->SwChnlStep=0; -// schedule_work(&(priv->SwChnlWorkItem)); -// rtl8192_SwChnl_WorkItem(dev); - if(priv->up) { -// queue_work(priv->priv_wq,&(priv->SwChnlWorkItem)); - rtl8192_SwChnl_WorkItem(dev); - } + if (priv->up) + rtl8192_SwChnl_WorkItem(priv); + priv->SwChnlInProgress = false; return true; } -static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev ) +static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct r8192_priv *priv) { - struct r8192_priv *priv = ieee80211_priv(dev); - switch(priv->CurrentChannelBW) { /* 20 MHz channel*/ @@ -2962,15 +1924,15 @@ static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev ) if(priv->ieee80211->current_network.channel== 14 && !priv->bcck_in_ch14) { priv->bcck_in_ch14 = TRUE; - dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); + dm_cck_txpower_adjust(priv, priv->bcck_in_ch14); } else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) { priv->bcck_in_ch14 = FALSE; - dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); + dm_cck_txpower_adjust(priv, priv->bcck_in_ch14); } else - dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); + dm_cck_txpower_adjust(priv, priv->bcck_in_ch14); break; /* 40 MHz channel*/ @@ -2988,24 +1950,21 @@ static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev ) if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) { priv->bcck_in_ch14 = TRUE; - dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); + dm_cck_txpower_adjust(priv, priv->bcck_in_ch14); } else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) { priv->bcck_in_ch14 = FALSE; - dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); + dm_cck_txpower_adjust(priv, priv->bcck_in_ch14); } else - dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); + dm_cck_txpower_adjust(priv, priv->bcck_in_ch14); break; } } -#ifndef RTL8190P -static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev) +static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct r8192_priv *priv) { - struct r8192_priv *priv = ieee80211_priv(dev); - if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) priv->bcck_in_ch14 = TRUE; else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) @@ -3028,25 +1987,17 @@ static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev) RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n", priv->CCK_index); break; } - dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + dm_cck_txpower_adjust(priv, priv->bcck_in_ch14); } -#endif -static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev) +static void CCK_Tx_Power_Track_BW_Switch(struct r8192_priv *priv) { -#ifdef RTL8192E - struct r8192_priv *priv = ieee80211_priv(dev); -#endif -#ifdef RTL8190P - CCK_Tx_Power_Track_BW_Switch_TSSI(dev); -#else //if(pHalData->bDcut == TRUE) if(priv->IC_Cut >= IC_VersionCut_D) - CCK_Tx_Power_Track_BW_Switch_TSSI(dev); + CCK_Tx_Power_Track_BW_Switch_TSSI(priv); else - CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev); -#endif + CCK_Tx_Power_Track_BW_Switch_ThermalMeter(priv); } @@ -3061,41 +2012,34 @@ static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev) * Note: I doubt whether SetBWModeInProgress flag is necessary as we can * test whether current work in the queue or not.//do I? * ***************************************************************************/ -void rtl8192_SetBWModeWorkItem(struct net_device *dev) +void rtl8192_SetBWModeWorkItem(struct r8192_priv *priv) { - - struct r8192_priv *priv = ieee80211_priv(dev); u8 regBwOpMode; RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n", priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz") - if(priv->rf_chip== RF_PSEUDO_11N) - { - priv->SetBWModeInProgress= false; - return; - } if(!priv->up) { priv->SetBWModeInProgress= false; return; } //<1>Set MAC register - regBwOpMode = read_nic_byte(dev, BW_OPMODE); + regBwOpMode = read_nic_byte(priv, BW_OPMODE); switch(priv->CurrentChannelBW) { case HT_CHANNEL_WIDTH_20: regBwOpMode |= BW_OPMODE_20MHZ; // 2007/02/07 Mark by Emily becasue we have not verify whether this register works - write_nic_byte(dev, BW_OPMODE, regBwOpMode); + write_nic_byte(priv, BW_OPMODE, regBwOpMode); break; case HT_CHANNEL_WIDTH_20_40: regBwOpMode &= ~BW_OPMODE_20MHZ; // 2007/02/07 Mark by Emily becasue we have not verify whether this register works - write_nic_byte(dev, BW_OPMODE, regBwOpMode); + write_nic_byte(priv, BW_OPMODE, regBwOpMode); break; default: @@ -3108,8 +2052,8 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev) { case HT_CHANNEL_WIDTH_20: // Add by Vivi 20071119 - rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); - rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); + rtl8192_setBBreg(priv, rFPGA0_RFMOD, bRFMOD, 0x0); + rtl8192_setBBreg(priv, rFPGA1_RFMOD, bRFMOD, 0x0); // rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207 @@ -3118,27 +2062,19 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev) // write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); if(!priv->btxpower_tracking) { - write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); - write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); - write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); + write_nic_dword(priv, rCCK0_TxFilter1, 0x1a1b0000); + write_nic_dword(priv, rCCK0_TxFilter2, 0x090e1317); + write_nic_dword(priv, rCCK0_DebugPort, 0x00000204); } else - CCK_Tx_Power_Track_BW_Switch(dev); - -#ifdef RTL8190P - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1); - rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x44); // 0xc30 is for 8190 only, Emily -#else - #ifdef RTL8192E - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); - #endif -#endif + CCK_Tx_Power_Track_BW_Switch(priv); + rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x00100000, 1); break; case HT_CHANNEL_WIDTH_20_40: // Add by Vivi 20071119 - rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); - rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); + rtl8192_setBBreg(priv, rFPGA0_RFMOD, bRFMOD, 0x1); + rtl8192_setBBreg(priv, rFPGA1_RFMOD, bRFMOD, 0x1); //rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); //rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); @@ -3149,37 +2085,19 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev) //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); if(!priv->btxpower_tracking) { - write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000); - write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e); - write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); + write_nic_dword(priv, rCCK0_TxFilter1, 0x35360000); + write_nic_dword(priv, rCCK0_TxFilter2, 0x121c252e); + write_nic_dword(priv, rCCK0_DebugPort, 0x00000409); } else - CCK_Tx_Power_Track_BW_Switch(dev); + CCK_Tx_Power_Track_BW_Switch(priv); // Set Control channel to upper or lower. These settings are required only for 40MHz - rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); - rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); + rtl8192_setBBreg(priv, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); + rtl8192_setBBreg(priv, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); -#ifdef RTL8190P - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0); - rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x42); // 0xc30 is for 8190 only, Emily - - // Set whether CCK should be sent in upper or lower channel. Suggest by YN. 20071207 - // It is set in Tx descriptor for 8192x series - if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) - { - rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x01); - }else if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) - { - rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x02); - } - -#else - #ifdef RTL8192E - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); - #endif -#endif + rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x00100000, 0); break; default: RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW); @@ -3188,37 +2106,13 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev) } //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 -#if 1 //<3>Set RF related register - switch( priv->rf_chip ) - { - case RF_8225: -#ifdef TO_DO_LIST - PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW); -#endif - break; - - case RF_8256: - PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); - break; + PHY_SetRF8256Bandwidth(priv, priv->CurrentChannelBW); - case RF_8258: - // PHY_SetRF8258Bandwidth(); - break; - - case RF_PSEUDO_11N: - // Do Nothing - break; - - default: - RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); - break; - } -#endif atomic_dec(&(priv->ieee80211->atm_swbw)); priv->SetBWModeInProgress= false; - RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()"); + RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()\n"); } /****************************************************************************** @@ -3231,9 +2125,9 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev) * Note: I doubt whether SetBWModeInProgress flag is necessary as we can * test whether current work in the queue or not.//do I? * ***************************************************************************/ -void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset) +void rtl8192_SetBWMode(struct ieee80211_device *ieee, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset) { - struct r8192_priv *priv = ieee80211_priv(dev); + struct r8192_priv *priv = ieee80211_priv(ieee->dev); if(priv->SetBWModeInProgress) @@ -3253,16 +2147,16 @@ void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EX //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem)); // schedule_work(&(priv->SetBWModeWorkItem)); - rtl8192_SetBWModeWorkItem(dev); + rtl8192_SetBWModeWorkItem(priv); } -void InitialGain819xPci(struct net_device *dev, u8 Operation) +void InitialGain819xPci(struct ieee80211_device *ieee, u8 Operation) { #define SCAN_RX_INITIAL_GAIN 0x17 #define POWER_DETECTION_TH 0x08 - struct r8192_priv *priv = ieee80211_priv(dev); + struct r8192_priv *priv = ieee80211_priv(ieee->dev); u32 BitMask; u8 initial_gain; @@ -3275,13 +2169,13 @@ void InitialGain819xPci(struct net_device *dev, u8 Operation) initial_gain = SCAN_RX_INITIAL_GAIN;//pHalData->DefaultInitialGain[0];// BitMask = bMaskByte0; if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) - rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF - priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); - priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask); - priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask); - priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask); + rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x8); // FW DIG OFF + priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XAAGCCore1, BitMask); + priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XBAGCCore1, BitMask); + priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XCAGCCore1, BitMask); + priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XDAGCCore1, BitMask); BitMask = bMaskByte2; - priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask); + priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(priv, rCCK0_CCA, BitMask); RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1); RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1); @@ -3290,25 +2184,25 @@ void InitialGain819xPci(struct net_device *dev, u8 Operation) RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca); RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain); - write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); - write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); - write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); - write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); + write_nic_byte(priv, rOFDM0_XAAGCCore1, initial_gain); + write_nic_byte(priv, rOFDM0_XBAGCCore1, initial_gain); + write_nic_byte(priv, rOFDM0_XCAGCCore1, initial_gain); + write_nic_byte(priv, rOFDM0_XDAGCCore1, initial_gain); RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH); - write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); + write_nic_byte(priv, 0xa0a, POWER_DETECTION_TH); break; case IG_Restore: RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); BitMask = 0x7f; //Bit0~ Bit6 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) - rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF + rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x8); // FW DIG OFF - rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1); - rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1); - rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1); - rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1); + rtl8192_setBBreg(priv, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1); + rtl8192_setBBreg(priv, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1); + rtl8192_setBBreg(priv, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1); + rtl8192_setBBreg(priv, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1); BitMask = bMaskByte2; - rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca); + rtl8192_setBBreg(priv, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca); RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1); RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1); @@ -3316,14 +2210,14 @@ void InitialGain819xPci(struct net_device *dev, u8 Operation) RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1); RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca); - rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel); + rtl8192_phy_setTxPower(priv, priv->ieee80211->current_network.channel); if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) - rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON + rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x1); // FW DIG ON break; default: - RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n"); + RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n"); break; } } |