diff options
Diffstat (limited to 'drivers/video/matrox/matroxfb_DAC1064.c')
| -rw-r--r-- | drivers/video/matrox/matroxfb_DAC1064.c | 378 |
1 files changed, 189 insertions, 189 deletions
diff --git a/drivers/video/matrox/matroxfb_DAC1064.c b/drivers/video/matrox/matroxfb_DAC1064.c index a74e5da17aa..7662a286289 100644 --- a/drivers/video/matrox/matroxfb_DAC1064.c +++ b/drivers/video/matrox/matroxfb_DAC1064.c @@ -85,19 +85,19 @@ static void DAC1064_setpclk(WPMINFO unsigned long fout) { DBG(__func__) - DAC1064_calcclock(PMINFO fout, ACCESS_FBINFO(max_pixel_clock), &m, &n, &p); - ACCESS_FBINFO(hw).DACclk[0] = m; - ACCESS_FBINFO(hw).DACclk[1] = n; - ACCESS_FBINFO(hw).DACclk[2] = p; + DAC1064_calcclock(PMINFO fout, minfo->max_pixel_clock, &m, &n, &p); + minfo->hw.DACclk[0] = m; + minfo->hw.DACclk[1] = n; + minfo->hw.DACclk[2] = p; } static void DAC1064_setmclk(WPMINFO int oscinfo, unsigned long fmem) { u_int32_t mx; - struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); + struct matrox_hw_state *hw = &minfo->hw; DBG(__func__) - if (ACCESS_FBINFO(devflags.noinit)) { + if (minfo->devflags.noinit) { /* read MCLK and give up... */ hw->DACclk[3] = inDAC1064(PMINFO DAC1064_XSYSPLLM); hw->DACclk[4] = inDAC1064(PMINFO DAC1064_XSYSPLLN); @@ -105,7 +105,7 @@ static void DAC1064_setmclk(WPMINFO int oscinfo, unsigned long fmem) { return; } mx = hw->MXoptionReg | 0x00000004; - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, mx); + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); mx &= ~0x000000BB; if (oscinfo & DAC1064_OPT_GDIV1) mx |= 0x00000008; @@ -120,9 +120,9 @@ static void DAC1064_setmclk(WPMINFO int oscinfo, unsigned long fmem) { /* powerup system PLL, select PCI clock */ mx |= 0x00000020; - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, mx); + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); mx &= ~0x00000004; - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, mx); + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); /* !!! you must not access device if MCLK is not running !!! Doing so cause immediate PCI lockup :-( Maybe they should @@ -131,7 +131,7 @@ static void DAC1064_setmclk(WPMINFO int oscinfo, unsigned long fmem) { perfect... */ /* (bit 2 of PCI_OPTION_REG must be 0... and bits 0,1 must not select PLL... because of PLL can be stopped at this time) */ - DAC1064_calcclock(PMINFO fmem, ACCESS_FBINFO(max_pixel_clock), &m, &n, &p); + DAC1064_calcclock(PMINFO fmem, minfo->max_pixel_clock, &m, &n, &p); outDAC1064(PMINFO DAC1064_XSYSPLLM, hw->DACclk[3] = m); outDAC1064(PMINFO DAC1064_XSYSPLLN, hw->DACclk[4] = n); outDAC1064(PMINFO DAC1064_XSYSPLLP, hw->DACclk[5] = p); @@ -147,9 +147,9 @@ static void DAC1064_setmclk(WPMINFO int oscinfo, unsigned long fmem) { /* select specified system clock source */ mx |= oscinfo & DAC1064_OPT_SCLK_MASK; } - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, mx); + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); mx &= ~0x00000004; - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, mx); + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); hw->MXoptionReg = mx; } @@ -157,19 +157,19 @@ static void DAC1064_setmclk(WPMINFO int oscinfo, unsigned long fmem) { static void g450_set_plls(WPMINFO2) { u_int32_t c2_ctl; unsigned int pxc; - struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); + struct matrox_hw_state *hw = &minfo->hw; int pixelmnp; int videomnp; c2_ctl = hw->crtc2.ctl & ~0x4007; /* Clear PLL + enable for CRTC2 */ c2_ctl |= 0x0001; /* Enable CRTC2 */ hw->DACreg[POS1064_XPWRCTRL] &= ~0x02; /* Stop VIDEO PLL */ - pixelmnp = ACCESS_FBINFO(crtc1).mnp; - videomnp = ACCESS_FBINFO(crtc2).mnp; + pixelmnp = minfo->crtc1.mnp; + videomnp = minfo->crtc2.mnp; if (videomnp < 0) { c2_ctl &= ~0x0001; /* Disable CRTC2 */ hw->DACreg[POS1064_XPWRCTRL] &= ~0x10; /* Powerdown CRTC2 */ - } else if (ACCESS_FBINFO(crtc2).pixclock == ACCESS_FBINFO(features).pll.ref_freq) { + } else if (minfo->crtc2.pixclock == minfo->features.pll.ref_freq) { c2_ctl |= 0x4002; /* Use reference directly */ } else if (videomnp == pixelmnp) { c2_ctl |= 0x0004; /* Use pixel PLL */ @@ -200,11 +200,11 @@ static void g450_set_plls(WPMINFO2) { mga_outl(0x3C10, c2_ctl); } - pxc = ACCESS_FBINFO(crtc1).pixclock; - if (pxc == 0 || ACCESS_FBINFO(outputs[2]).src == MATROXFB_SRC_CRTC2) { - pxc = ACCESS_FBINFO(crtc2).pixclock; + pxc = minfo->crtc1.pixclock; + if (pxc == 0 || minfo->outputs[2].src == MATROXFB_SRC_CRTC2) { + pxc = minfo->crtc2.pixclock; } - if (ACCESS_FBINFO(chip) == MGA_G550) { + if (minfo->chip == MGA_G550) { if (pxc < 45000) { hw->DACreg[POS1064_XPANMODE] = 0x00; /* 0-50 */ } else if (pxc < 55000) { @@ -246,17 +246,17 @@ static void g450_set_plls(WPMINFO2) { #endif void DAC1064_global_init(WPMINFO2) { - struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); + struct matrox_hw_state *hw = &minfo->hw; hw->DACreg[POS1064_XMISCCTRL] &= M1064_XMISCCTRL_DAC_WIDTHMASK; hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_LUT_EN; hw->DACreg[POS1064_XPIXCLKCTRL] = M1064_XPIXCLKCTRL_PLL_UP | M1064_XPIXCLKCTRL_EN | M1064_XPIXCLKCTRL_SRC_PLL; #ifdef CONFIG_FB_MATROX_G - if (ACCESS_FBINFO(devflags.g450dac)) { + if (minfo->devflags.g450dac) { hw->DACreg[POS1064_XPWRCTRL] = 0x1F; /* powerup everything */ hw->DACreg[POS1064_XOUTPUTCONN] = 0x00; /* disable outputs */ hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_DAC_EN; - switch (ACCESS_FBINFO(outputs[0]).src) { + switch (minfo->outputs[0].src) { case MATROXFB_SRC_CRTC1: case MATROXFB_SRC_CRTC2: hw->DACreg[POS1064_XOUTPUTCONN] |= 0x01; /* enable output; CRTC1/2 selection is in CRTC2 ctl */ @@ -265,12 +265,12 @@ void DAC1064_global_init(WPMINFO2) { hw->DACreg[POS1064_XMISCCTRL] &= ~M1064_XMISCCTRL_DAC_EN; break; } - switch (ACCESS_FBINFO(outputs[1]).src) { + switch (minfo->outputs[1].src) { case MATROXFB_SRC_CRTC1: hw->DACreg[POS1064_XOUTPUTCONN] |= 0x04; break; case MATROXFB_SRC_CRTC2: - if (ACCESS_FBINFO(outputs[1]).mode == MATROXFB_OUTPUT_MODE_MONITOR) { + if (minfo->outputs[1].mode == MATROXFB_OUTPUT_MODE_MONITOR) { hw->DACreg[POS1064_XOUTPUTCONN] |= 0x08; } else { hw->DACreg[POS1064_XOUTPUTCONN] |= 0x0C; @@ -280,7 +280,7 @@ void DAC1064_global_init(WPMINFO2) { hw->DACreg[POS1064_XPWRCTRL] &= ~0x01; /* Poweroff DAC2 */ break; } - switch (ACCESS_FBINFO(outputs[2]).src) { + switch (minfo->outputs[2].src) { case MATROXFB_SRC_CRTC1: hw->DACreg[POS1064_XOUTPUTCONN] |= 0x20; break; @@ -303,30 +303,30 @@ void DAC1064_global_init(WPMINFO2) { } else #endif { - if (ACCESS_FBINFO(outputs[1]).src == MATROXFB_SRC_CRTC1) { + if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1) { hw->DACreg[POS1064_XPIXCLKCTRL] = M1064_XPIXCLKCTRL_PLL_UP | M1064_XPIXCLKCTRL_EN | M1064_XPIXCLKCTRL_SRC_EXT; hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_MAFC | G400_XMISCCTRL_VDO_MAFC12; - } else if (ACCESS_FBINFO(outputs[1]).src == MATROXFB_SRC_CRTC2) { + } else if (minfo->outputs[1].src == MATROXFB_SRC_CRTC2) { hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_MAFC | G400_XMISCCTRL_VDO_C2_MAFC12; - } else if (ACCESS_FBINFO(outputs[2]).src == MATROXFB_SRC_CRTC1) + } else if (minfo->outputs[2].src == MATROXFB_SRC_CRTC1) hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_PANELLINK | G400_XMISCCTRL_VDO_MAFC12; else hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_DIS; - if (ACCESS_FBINFO(outputs[0]).src != MATROXFB_SRC_NONE) + if (minfo->outputs[0].src != MATROXFB_SRC_NONE) hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_DAC_EN; } } void DAC1064_global_restore(WPMINFO2) { - struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); + struct matrox_hw_state *hw = &minfo->hw; outDAC1064(PMINFO M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]); outDAC1064(PMINFO M1064_XMISCCTRL, hw->DACreg[POS1064_XMISCCTRL]); - if (ACCESS_FBINFO(devflags.accelerator) == FB_ACCEL_MATROX_MGAG400) { + if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400) { outDAC1064(PMINFO 0x20, 0x04); - outDAC1064(PMINFO 0x1F, ACCESS_FBINFO(devflags.dfp_type)); - if (ACCESS_FBINFO(devflags.g450dac)) { + outDAC1064(PMINFO 0x1F, minfo->devflags.dfp_type); + if (minfo->devflags.g450dac) { outDAC1064(PMINFO M1064_XSYNCCTRL, 0xCC); outDAC1064(PMINFO M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]); outDAC1064(PMINFO M1064_XPANMODE, hw->DACreg[POS1064_XPANMODE]); @@ -336,18 +336,18 @@ void DAC1064_global_restore(WPMINFO2) { } static int DAC1064_init_1(WPMINFO struct my_timming* m) { - struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); + struct matrox_hw_state *hw = &minfo->hw; DBG(__func__) memcpy(hw->DACreg, MGA1064_DAC, sizeof(MGA1064_DAC_regs)); - switch (ACCESS_FBINFO(fbcon).var.bits_per_pixel) { + switch (minfo->fbcon.var.bits_per_pixel) { /* case 4: not supported by MGA1064 DAC */ case 8: hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_8BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED; break; case 16: - if (ACCESS_FBINFO(fbcon).var.green.length == 5) + if (minfo->fbcon.var.green.length == 5) hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_15BPP_1BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED; else hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_16BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED; @@ -361,7 +361,7 @@ static int DAC1064_init_1(WPMINFO struct my_timming* m) { default: return 1; /* unsupported depth */ } - hw->DACreg[POS1064_XVREFCTRL] = ACCESS_FBINFO(features.DAC1064.xvrefctrl); + hw->DACreg[POS1064_XVREFCTRL] = minfo->features.DAC1064.xvrefctrl; hw->DACreg[POS1064_XGENCTRL] &= ~M1064_XGENCTRL_SYNC_ON_GREEN_MASK; hw->DACreg[POS1064_XGENCTRL] |= (m->sync & FB_SYNC_ON_GREEN)?M1064_XGENCTRL_SYNC_ON_GREEN:M1064_XGENCTRL_NO_SYNC_ON_GREEN; hw->DACreg[POS1064_XCURADDL] = 0; @@ -372,11 +372,11 @@ static int DAC1064_init_1(WPMINFO struct my_timming* m) { } static int DAC1064_init_2(WPMINFO struct my_timming* m) { - struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); + struct matrox_hw_state *hw = &minfo->hw; DBG(__func__) - if (ACCESS_FBINFO(fbcon).var.bits_per_pixel > 16) { /* 256 entries */ + if (minfo->fbcon.var.bits_per_pixel > 16) { /* 256 entries */ int i; for (i = 0; i < 256; i++) { @@ -384,8 +384,8 @@ static int DAC1064_init_2(WPMINFO struct my_timming* m) { hw->DACpal[i * 3 + 1] = i; hw->DACpal[i * 3 + 2] = i; } - } else if (ACCESS_FBINFO(fbcon).var.bits_per_pixel > 8) { - if (ACCESS_FBINFO(fbcon).var.green.length == 5) { /* 0..31, 128..159 */ + } else if (minfo->fbcon.var.bits_per_pixel > 8) { + if (minfo->fbcon.var.green.length == 5) { /* 0..31, 128..159 */ int i; for (i = 0; i < 32; i++) { @@ -414,7 +414,7 @@ static int DAC1064_init_2(WPMINFO struct my_timming* m) { } static void DAC1064_restore_1(WPMINFO2) { - struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); + struct matrox_hw_state *hw = &minfo->hw; CRITFLAGS @@ -453,12 +453,12 @@ static void DAC1064_restore_2(WPMINFO2) { #ifdef DEBUG dprintk(KERN_DEBUG "DAC1064regs "); for (i = 0; i < sizeof(MGA1064_DAC_regs); i++) { - dprintk("R%02X=%02X ", MGA1064_DAC_regs[i], ACCESS_FBINFO(hw).DACreg[i]); + dprintk("R%02X=%02X ", MGA1064_DAC_regs[i], minfo->hw.DACreg[i]); if ((i & 0x7) == 0x7) dprintk(KERN_DEBUG "continuing... "); } dprintk(KERN_DEBUG "DAC1064clk "); for (i = 0; i < 6; i++) - dprintk("C%02X=%02X ", i, ACCESS_FBINFO(hw).DACclk[i]); + dprintk("C%02X=%02X ", i, minfo->hw.DACclk[i]); dprintk("\n"); #endif } @@ -475,7 +475,7 @@ static int m1064_compute(void* out, struct my_timming* m) { CRITBEGIN for (i = 0; i < 3; i++) - outDAC1064(PMINFO M1064_XPIXPLLCM + i, ACCESS_FBINFO(hw).DACclk[i]); + outDAC1064(PMINFO M1064_XPIXPLLCM + i, minfo->hw.DACclk[i]); for (tmout = 500000; tmout; tmout--) { if (inDAC1064(PMINFO M1064_XPIXPLLSTAT) & 0x40) break; @@ -519,7 +519,7 @@ static struct matrox_altout g450out = { #ifdef CONFIG_FB_MATROX_MYSTIQUE static int MGA1064_init(WPMINFO struct my_timming* m) { - struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); + struct matrox_hw_state *hw = &minfo->hw; DBG(__func__) @@ -541,7 +541,7 @@ static int MGA1064_init(WPMINFO struct my_timming* m) { #ifdef CONFIG_FB_MATROX_G static int MGAG100_init(WPMINFO struct my_timming* m) { - struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); + struct matrox_hw_state *hw = &minfo->hw; DBG(__func__) @@ -567,15 +567,15 @@ static void MGA1064_ramdac_init(WPMINFO2) { DBG(__func__) - /* ACCESS_FBINFO(features.DAC1064.vco_freq_min) = 120000; */ - ACCESS_FBINFO(features.pll.vco_freq_min) = 62000; - ACCESS_FBINFO(features.pll.ref_freq) = 14318; - ACCESS_FBINFO(features.pll.feed_div_min) = 100; - ACCESS_FBINFO(features.pll.feed_div_max) = 127; - ACCESS_FBINFO(features.pll.in_div_min) = 1; - ACCESS_FBINFO(features.pll.in_div_max) = 31; - ACCESS_FBINFO(features.pll.post_shift_max) = 3; - ACCESS_FBINFO(features.DAC1064.xvrefctrl) = DAC1064_XVREFCTRL_EXTERNAL; + /* minfo->features.DAC1064.vco_freq_min = 120000; */ + minfo->features.pll.vco_freq_min = 62000; + minfo->features.pll.ref_freq = 14318; + minfo->features.pll.feed_div_min = 100; + minfo->features.pll.feed_div_max = 127; + minfo->features.pll.in_div_min = 1; + minfo->features.pll.in_div_max = 31; + minfo->features.pll.post_shift_max = 3; + minfo->features.DAC1064.xvrefctrl = DAC1064_XVREFCTRL_EXTERNAL; /* maybe cmdline MCLK= ?, doc says gclk=44MHz, mclk=66MHz... it was 55/83 with old values */ DAC1064_setmclk(PMINFO DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV3 | DAC1064_OPT_SCLK_PLL, 133333); } @@ -638,7 +638,7 @@ static void MGAG100_setPixClock(CPMINFO int flags, int freq) { DBG(__func__) - DAC1064_calcclock(PMINFO freq, ACCESS_FBINFO(max_pixel_clock), &m, &n, &p); + DAC1064_calcclock(PMINFO freq, minfo->max_pixel_clock, &m, &n, &p); MGAG100_progPixClock(PMINFO flags, m, n, p); } #endif @@ -648,30 +648,30 @@ static int MGA1064_preinit(WPMINFO2) { static const int vxres_mystique[] = { 512, 640, 768, 800, 832, 960, 1024, 1152, 1280, 1600, 1664, 1920, 2048, 0}; - struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); + struct matrox_hw_state *hw = &minfo->hw; DBG(__func__) - /* ACCESS_FBINFO(capable.cfb4) = 0; ... preinitialized by 0 */ - ACCESS_FBINFO(capable.text) = 1; - ACCESS_FBINFO(capable.vxres) = vxres_mystique; + /* minfo->capable.cfb4 = 0; ... preinitialized by 0 */ + minfo->capable.text = 1; + minfo->capable.vxres = vxres_mystique; - ACCESS_FBINFO(outputs[0]).output = &m1064; - ACCESS_FBINFO(outputs[0]).src = ACCESS_FBINFO(outputs[0]).default_src; - ACCESS_FBINFO(outputs[0]).data = MINFO; - ACCESS_FBINFO(outputs[0]).mode = MATROXFB_OUTPUT_MODE_MONITOR; + minfo->outputs[0].output = &m1064; + minfo->outputs[0].src = minfo->outputs[0].default_src; + minfo->outputs[0].data = minfo; + minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR; - if (ACCESS_FBINFO(devflags.noinit)) + if (minfo->devflags.noinit) return 0; /* do not modify settings */ hw->MXoptionReg &= 0xC0000100; hw->MXoptionReg |= 0x00094E20; - if (ACCESS_FBINFO(devflags.novga)) + if (minfo->devflags.novga) hw->MXoptionReg &= ~0x00000100; - if (ACCESS_FBINFO(devflags.nobios)) + if (minfo->devflags.nobios) hw->MXoptionReg &= ~0x40000000; - if (ACCESS_FBINFO(devflags.nopciretry)) + if (minfo->devflags.nopciretry) hw->MXoptionReg |= 0x20000000; - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg); + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); mga_setr(M_SEQ_INDEX, 0x01, 0x20); mga_outl(M_CTLWTST, 0x00000000); udelay(200); @@ -692,14 +692,14 @@ static void MGA1064_reset(WPMINFO2) { #ifdef CONFIG_FB_MATROX_G static void g450_mclk_init(WPMINFO2) { /* switch all clocks to PCI source */ - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg | 4); - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION3_REG, ACCESS_FBINFO(values).reg.opt3 & ~0x00300C03); - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg); - - if (((ACCESS_FBINFO(values).reg.opt3 & 0x000003) == 0x000003) || - ((ACCESS_FBINFO(values).reg.opt3 & 0x000C00) == 0x000C00) || - ((ACCESS_FBINFO(values).reg.opt3 & 0x300000) == 0x300000)) { - matroxfb_g450_setclk(PMINFO ACCESS_FBINFO(values.pll.video), M_VIDEO_PLL); + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4); + pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3 & ~0x00300C03); + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); + + if (((minfo->values.reg.opt3 & 0x000003) == 0x000003) || + ((minfo->values.reg.opt3 & 0x000C00) == 0x000C00) || + ((minfo->values.reg.opt3 & 0x300000) == 0x300000)) { + matroxfb_g450_setclk(PMINFO minfo->values.pll.video, M_VIDEO_PLL); } else { unsigned long flags; unsigned int pwr; @@ -709,53 +709,53 @@ static void g450_mclk_init(WPMINFO2) { outDAC1064(PMINFO M1064_XPWRCTRL, pwr); matroxfb_DAC_unlock_irqrestore(flags); } - matroxfb_g450_setclk(PMINFO ACCESS_FBINFO(values.pll.system), M_SYSTEM_PLL); + matroxfb_g450_setclk(PMINFO minfo->values.pll.system, M_SYSTEM_PLL); /* switch clocks to their real PLL source(s) */ - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg | 4); - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION3_REG, ACCESS_FBINFO(values).reg.opt3); - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg); + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4); + pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3); + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); } static void g450_memory_init(WPMINFO2) { /* disable memory refresh */ - ACCESS_FBINFO(hw).MXoptionReg &= ~0x001F8000; - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg); + minfo->hw.MXoptionReg &= ~0x001F8000; + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); /* set memory interface parameters */ - ACCESS_FBINFO(hw).MXoptionReg &= ~0x00207E00; - ACCESS_FBINFO(hw).MXoptionReg |= 0x00207E00 & ACCESS_FBINFO(values).reg.opt; - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg); - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION2_REG, ACCESS_FBINFO(values).reg.opt2); + minfo->hw.MXoptionReg &= ~0x00207E00; + minfo->hw.MXoptionReg |= 0x00207E00 & minfo->values.reg.opt; + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); + pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, minfo->values.reg.opt2); - mga_outl(M_CTLWTST, ACCESS_FBINFO(values).reg.mctlwtst); + mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); /* first set up memory interface with disabled memory interface clocks */ - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_MEMMISC_REG, ACCESS_FBINFO(values).reg.memmisc & ~0x80000000U); - mga_outl(M_MEMRDBK, ACCESS_FBINFO(values).reg.memrdbk); - mga_outl(M_MACCESS, ACCESS_FBINFO(values).reg.maccess); + pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc & ~0x80000000U); + mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); + mga_outl(M_MACCESS, minfo->values.reg.maccess); /* start memory clocks */ - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_MEMMISC_REG, ACCESS_FBINFO(values).reg.memmisc | 0x80000000U); + pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc | 0x80000000U); udelay(200); - if (ACCESS_FBINFO(values).memory.ddr && (!ACCESS_FBINFO(values).memory.emrswen || !ACCESS_FBINFO(values).memory.dll)) { - mga_outl(M_MEMRDBK, ACCESS_FBINFO(values).reg.memrdbk & ~0x1000); + if (minfo->values.memory.ddr && (!minfo->values.memory.emrswen || !minfo->values.memory.dll)) { + mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk & ~0x1000); } - mga_outl(M_MACCESS, ACCESS_FBINFO(values).reg.maccess | 0x8000); + mga_outl(M_MACCESS, minfo->values.reg.maccess | 0x8000); udelay(200); - ACCESS_FBINFO(hw).MXoptionReg |= 0x001F8000 & ACCESS_FBINFO(values).reg.opt; - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg); + minfo->hw.MXoptionReg |= 0x001F8000 & minfo->values.reg.opt; + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); /* value is written to memory chips only if old != new */ mga_outl(M_PLNWT, 0); mga_outl(M_PLNWT, ~0); - if (ACCESS_FBINFO(values).reg.mctlwtst != ACCESS_FBINFO(values).reg.mctlwtst_core) { - mga_outl(M_CTLWTST, ACCESS_FBINFO(values).reg.mctlwtst_core); + if (minfo->values.reg.mctlwtst != minfo->values.reg.mctlwtst_core) { + mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst_core); } } @@ -765,17 +765,17 @@ static void g450_preinit(WPMINFO2) { u_int8_t curctl; u_int8_t c1ctl; - /* ACCESS_FBINFO(hw).MXoptionReg = minfo->values.reg.opt; */ - ACCESS_FBINFO(hw).MXoptionReg &= 0xC0000100; - ACCESS_FBINFO(hw).MXoptionReg |= 0x00000020; - if (ACCESS_FBINFO(devflags.novga)) - ACCESS_FBINFO(hw).MXoptionReg &= ~0x00000100; - if (ACCESS_FBINFO(devflags.nobios)) - ACCESS_FBINFO(hw).MXoptionReg &= ~0x40000000; - if (ACCESS_FBINFO(devflags.nopciretry)) - ACCESS_FBINFO(hw).MXoptionReg |= 0x20000000; - ACCESS_FBINFO(hw).MXoptionReg |= ACCESS_FBINFO(values).reg.opt & 0x03400040; - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg); + /* minfo->hw.MXoptionReg = minfo->values.reg.opt; */ + minfo->hw.MXoptionReg &= 0xC0000100; + minfo->hw.MXoptionReg |= 0x00000020; + if (minfo->devflags.novga) + minfo->hw.MXoptionReg &= ~0x00000100; + if (minfo->devflags.nobios) + minfo->hw.MXoptionReg &= ~0x40000000; + if (minfo->devflags.nopciretry) + minfo->hw.MXoptionReg |= 0x20000000; + minfo->hw.MXoptionReg |= minfo->values.reg.opt & 0x03400040; + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); /* Init system clocks */ @@ -812,7 +812,7 @@ static int MGAG100_preinit(WPMINFO2) { static const int vxres_g100[] = { 512, 640, 768, 800, 832, 960, 1024, 1152, 1280, 1600, 1664, 1920, 2048, 0}; - struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); + struct matrox_hw_state *hw = &minfo->hw; u_int32_t reg50; #if 0 @@ -822,68 +822,68 @@ static int MGAG100_preinit(WPMINFO2) { DBG(__func__) /* there are some instabilities if in_div > 19 && vco < 61000 */ - if (ACCESS_FBINFO(devflags.g450dac)) { - ACCESS_FBINFO(features.pll.vco_freq_min) = 130000; /* my sample: >118 */ + if (minfo->devflags.g450dac) { + minfo->features.pll.vco_freq_min = 130000; /* my sample: >118 */ } else { - ACCESS_FBINFO(features.pll.vco_freq_min) = 62000; + minfo->features.pll.vco_freq_min = 62000; } - if (!ACCESS_FBINFO(features.pll.ref_freq)) { - ACCESS_FBINFO(features.pll.ref_freq) = 27000; + if (!minfo->features.pll.ref_freq) { + minfo->features.pll.ref_freq = 27000; } - ACCESS_FBINFO(features.pll.feed_div_min) = 7; - ACCESS_FBINFO(features.pll.feed_div_max) = 127; - ACCESS_FBINFO(features.pll.in_div_min) = 1; - ACCESS_FBINFO(features.pll.in_div_max) = 31; - ACCESS_FBINFO(features.pll.post_shift_max) = 3; - ACCESS_FBINFO(features.DAC1064.xvrefctrl) = DAC1064_XVREFCTRL_G100_DEFAULT; - /* ACCESS_FBINFO(capable.cfb4) = 0; ... preinitialized by 0 */ - ACCESS_FBINFO(capable.text) = 1; - ACCESS_FBINFO(capable.vxres) = vxres_g100; - ACCESS_FBINFO(capable.plnwt) = ACCESS_FBINFO(devflags.accelerator) == FB_ACCEL_MATROX_MGAG100 - ? ACCESS_FBINFO(devflags.sgram) : 1; + minfo->features.pll.feed_div_min = 7; + minfo->features.pll.feed_div_max = 127; + minfo->features.pll.in_div_min = 1; + minfo->features.pll.in_div_max = 31; + minfo->features.pll.post_shift_max = 3; + minfo->features.DAC1064.xvrefctrl = DAC1064_XVREFCTRL_G100_DEFAULT; + /* minfo->capable.cfb4 = 0; ... preinitialized by 0 */ + minfo->capable.text = 1; + minfo->capable.vxres = vxres_g100; + minfo->capable.plnwt = minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG100 + ? minfo->devflags.sgram : 1; #ifdef CONFIG_FB_MATROX_G - if (ACCESS_FBINFO(devflags.g450dac)) { - ACCESS_FBINFO(outputs[0]).output = &g450out; + if (minfo->devflags.g450dac) { + minfo->outputs[0].output = &g450out; } else #endif { - ACCESS_FBINFO(outputs[0]).output = &m1064; + minfo->outputs[0].output = &m1064; } - ACCESS_FBINFO(outputs[0]).src = ACCESS_FBINFO(outputs[0]).default_src; - ACCESS_FBINFO(outputs[0]).data = MINFO; - ACCESS_FBINFO(outputs[0]).mode = MATROXFB_OUTPUT_MODE_MONITOR; + minfo->outputs[0].src = minfo->outputs[0].default_src; + minfo->outputs[0].data = minfo; + minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR; - if (ACCESS_FBINFO(devflags.g450dac)) { + if (minfo->devflags.g450dac) { /* we must do this always, BIOS does not do it for us and accelerator dies without it */ mga_outl(0x1C0C, 0); } - if (ACCESS_FBINFO(devflags.noinit)) + if (minfo->devflags.noinit) return 0; - if (ACCESS_FBINFO(devflags.g450dac)) { + if (minfo->devflags.g450dac) { g450_preinit(PMINFO2); return 0; } hw->MXoptionReg &= 0xC0000100; hw->MXoptionReg |= 0x00000020; - if (ACCESS_FBINFO(devflags.novga)) + if (minfo->devflags.novga) hw->MXoptionReg &= ~0x00000100; - if (ACCESS_FBINFO(devflags.nobios)) + if (minfo->devflags.nobios) hw->MXoptionReg &= ~0x40000000; - if (ACCESS_FBINFO(devflags.nopciretry)) + if (minfo->devflags.nopciretry) hw->MXoptionReg |= 0x20000000; - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg); + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); DAC1064_setmclk(PMINFO DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV3 | DAC1064_OPT_SCLK_PCI, 133333); - if (ACCESS_FBINFO(devflags.accelerator) == FB_ACCEL_MATROX_MGAG100) { - pci_read_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION2_REG, ®50); + if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG100) { + pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50); reg50 &= ~0x3000; - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION2_REG, reg50); + pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50); hw->MXoptionReg |= 0x1080; - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg); - mga_outl(M_CTLWTST, ACCESS_FBINFO(values).reg.mctlwtst); + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); + mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); udelay(100); mga_outb(0x1C05, 0x00); mga_outb(0x1C05, 0x80); @@ -893,68 +893,68 @@ static int MGAG100_preinit(WPMINFO2) { udelay(100); reg50 &= ~0xFF; reg50 |= 0x07; - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION2_REG, reg50); + pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50); /* it should help with G100 */ mga_outb(M_GRAPHICS_INDEX, 6); mga_outb(M_GRAPHICS_DATA, (mga_inb(M_GRAPHICS_DATA) & 3) | 4); mga_setr(M_EXTVGA_INDEX, 0x03, 0x81); mga_setr(M_EXTVGA_INDEX, 0x04, 0x00); - mga_writeb(ACCESS_FBINFO(video.vbase), 0x0000, 0xAA); - mga_writeb(ACCESS_FBINFO(video.vbase), 0x0800, 0x55); - mga_writeb(ACCESS_FBINFO(video.vbase), 0x4000, 0x55); + mga_writeb(minfo->video.vbase, 0x0000, 0xAA); + mga_writeb(minfo->video.vbase, 0x0800, 0x55); + mga_writeb(minfo->video.vbase, 0x4000, 0x55); #if 0 - if (mga_readb(ACCESS_FBINFO(video.vbase), 0x0000) != 0xAA) { + if (mga_readb(minfo->video.vbase, 0x0000) != 0xAA) { hw->MXoptionReg &= ~0x1000; } #endif hw->MXoptionReg |= 0x00078020; - } else if (ACCESS_FBINFO(devflags.accelerator) == FB_ACCEL_MATROX_MGAG200) { - pci_read_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION2_REG, ®50); + } else if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG200) { + pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50); reg50 &= ~0x3000; - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION2_REG, reg50); + pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50); - if (ACCESS_FBINFO(devflags.memtype) == -1) - hw->MXoptionReg |= ACCESS_FBINFO(values).reg.opt & 0x1C00; + if (minfo->devflags.memtype == -1) + hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00; else - hw->MXoptionReg |= (ACCESS_FBINFO(devflags.memtype) & 7) << 10; - if (ACCESS_FBINFO(devflags.sgram)) + hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10; + if (minfo->devflags.sgram) hw->MXoptionReg |= 0x4000; - mga_outl(M_CTLWTST, ACCESS_FBINFO(values).reg.mctlwtst); - mga_outl(M_MEMRDBK, ACCESS_FBINFO(values).reg.memrdbk); + mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); + mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); udelay(200); mga_outl(M_MACCESS, 0x00000000); mga_outl(M_MACCESS, 0x00008000); udelay(100); - mga_outw(M_MEMRDBK, ACCESS_FBINFO(values).reg.memrdbk); + mga_outw(M_MEMRDBK, minfo->values.reg.memrdbk); hw->MXoptionReg |= 0x00078020; } else { - pci_read_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION2_REG, ®50); + pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50); reg50 &= ~0x00000100; reg50 |= 0x00000000; - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION2_REG, reg50); + pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50); - if (ACCESS_FBINFO(devflags.memtype) == -1) - hw->MXoptionReg |= ACCESS_FBINFO(values).reg.opt & 0x1C00; + if (minfo->devflags.memtype == -1) + hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00; else - hw->MXoptionReg |= (ACCESS_FBINFO(devflags.memtype) & 7) << 10; - if (ACCESS_FBINFO(devflags.sgram)) + hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10; + if (minfo->devflags.sgram) hw->MXoptionReg |= 0x4000; - mga_outl(M_CTLWTST, ACCESS_FBINFO(values).reg.mctlwtst); - mga_outl(M_MEMRDBK, ACCESS_FBINFO(values).reg.memrdbk); + mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); + mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); udelay(200); mga_outl(M_MACCESS, 0x00000000); mga_outl(M_MACCESS, 0x00008000); udelay(100); - mga_outl(M_MEMRDBK, ACCESS_FBINFO(values).reg.memrdbk); + mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); hw->MXoptionReg |= 0x00040020; } - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg); + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); return 0; } static void MGAG100_reset(WPMINFO2) { u_int8_t b; - struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); + struct matrox_hw_state *hw = &minfo->hw; DBG(__func__) @@ -964,22 +964,22 @@ static void MGAG100_reset(WPMINFO2) { find 1014/22 (IBM/82351); /* if found and bridging Matrox, do some strange stuff */ pci_read_config_byte(ibm, PCI_SECONDARY_BUS, &b); - if (b == ACCESS_FBINFO(pcidev)->bus->number) { + if (b == minfo->pcidev->bus->number) { pci_write_config_byte(ibm, PCI_COMMAND+1, 0); /* disable back-to-back & SERR */ pci_write_config_byte(ibm, 0x41, 0xF4); /* ??? */ pci_write_config_byte(ibm, PCI_IO_BASE, 0xF0); /* ??? */ pci_write_config_byte(ibm, PCI_IO_LIMIT, 0x00); /* ??? */ } #endif - if (!ACCESS_FBINFO(devflags.noinit)) { + if (!minfo->devflags.noinit) { if (x7AF4 & 8) { hw->MXoptionReg |= 0x40; /* FIXME... */ - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg); + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); } mga_setr(M_EXTVGA_INDEX, 0x06, 0x00); } } - if (ACCESS_FBINFO(devflags.g450dac)) { + if (minfo->devflags.g450dac) { /* either leave MCLK as is... or they were set in preinit */ hw->DACclk[3] = inDAC1064(PMINFO DAC1064_XSYSPLLM); hw->DACclk[4] = inDAC1064(PMINFO DAC1064_XSYSPLLN); @@ -987,14 +987,14 @@ static void MGAG100_reset(WPMINFO2) { } else { DAC1064_setmclk(PMINFO DAC1064_OPT_RESERVED | DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV1 | DAC1064_OPT_SCLK_PLL, 133333); } - if (ACCESS_FBINFO(devflags.accelerator) == FB_ACCEL_MATROX_MGAG400) { - if (ACCESS_FBINFO(devflags.dfp_type) == -1) { - ACCESS_FBINFO(devflags.dfp_type) = inDAC1064(PMINFO 0x1F); + if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400) { + if (minfo->devflags.dfp_type == -1) { + minfo->devflags.dfp_type = inDAC1064(PMINFO 0x1F); } } - if (ACCESS_FBINFO(devflags.noinit)) + if (minfo->devflags.noinit) return; - if (ACCESS_FBINFO(devflags.g450dac)) { + if (minfo->devflags.g450dac) { } else { MGAG100_setPixClock(PMINFO 4, 25175); MGAG100_setPixClock(PMINFO 5, 28322); @@ -1011,7 +1011,7 @@ static void MGAG100_reset(WPMINFO2) { #ifdef CONFIG_FB_MATROX_MYSTIQUE static void MGA1064_restore(WPMINFO2) { int i; - struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); + struct matrox_hw_state *hw = &minfo->hw; CRITFLAGS @@ -1019,7 +1019,7 @@ static void MGA1064_restore(WPMINFO2) { CRITBEGIN - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg); + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); mga_outb(M_IEN, 0x00); mga_outb(M_CACHEFLUSH, 0x00); @@ -1027,7 +1027,7 @@ static void MGA1064_restore(WPMINFO2) { DAC1064_restore_1(PMINFO2); matroxfb_vgaHWrestore(PMINFO2); - ACCESS_FBINFO(crtc1.panpos) = -1; + minfo->crtc1.panpos = -1; for (i = 0; i < 6; i++) mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]); DAC1064_restore_2(PMINFO2); @@ -1037,7 +1037,7 @@ static void MGA1064_restore(WPMINFO2) { #ifdef CONFIG_FB_MATROX_G static void MGAG100_restore(WPMINFO2) { int i; - struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); + struct matrox_hw_state *hw = &minfo->hw; CRITFLAGS @@ -1045,16 +1045,16 @@ static void MGAG100_restore(WPMINFO2) { CRITBEGIN - pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg); + pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); CRITEND DAC1064_restore_1(PMINFO2); matroxfb_vgaHWrestore(PMINFO2); #ifdef CONFIG_FB_MATROX_32MB - if (ACCESS_FBINFO(devflags.support32MB)) + if (minfo->devflags.support32MB) mga_setr(M_EXTVGA_INDEX, 8, hw->CRTCEXT[8]); #endif - ACCESS_FBINFO(crtc1.panpos) = -1; + minfo->crtc1.panpos = -1; for (i = 0; i < 6; i++) mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]); DAC1064_restore_2(PMINFO2); |