diff options
Diffstat (limited to 'drivers/video')
61 files changed, 3596 insertions, 739 deletions
diff --git a/drivers/video/backlight/backlight.c b/drivers/video/backlight/backlight.c index bd2172c2d65..428089009cd 100644 --- a/drivers/video/backlight/backlight.c +++ b/drivers/video/backlight/backlight.c @@ -23,6 +23,7 @@ static struct list_head backlight_dev_list; static struct mutex backlight_dev_list_mutex; +static struct blocking_notifier_head backlight_notifier; static const char *const backlight_types[] = { [BACKLIGHT_RAW] = "raw", @@ -370,6 +371,9 @@ struct backlight_device *backlight_device_register(const char *name, list_add(&new_bd->entry, &backlight_dev_list); mutex_unlock(&backlight_dev_list_mutex); + blocking_notifier_call_chain(&backlight_notifier, + BACKLIGHT_REGISTERED, new_bd); + return new_bd; } EXPORT_SYMBOL(backlight_device_register); @@ -413,6 +417,10 @@ void backlight_device_unregister(struct backlight_device *bd) pmac_backlight = NULL; mutex_unlock(&pmac_backlight_mutex); #endif + + blocking_notifier_call_chain(&backlight_notifier, + BACKLIGHT_UNREGISTERED, bd); + mutex_lock(&bd->ops_lock); bd->ops = NULL; mutex_unlock(&bd->ops_lock); @@ -438,6 +446,36 @@ static int devm_backlight_device_match(struct device *dev, void *res, } /** + * backlight_register_notifier - get notified of backlight (un)registration + * @nb: notifier block with the notifier to call on backlight (un)registration + * + * @return 0 on success, otherwise a negative error code + * + * Register a notifier to get notified when backlight devices get registered + * or unregistered. + */ +int backlight_register_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&backlight_notifier, nb); +} +EXPORT_SYMBOL(backlight_register_notifier); + +/** + * backlight_unregister_notifier - unregister a backlight notifier + * @nb: notifier block to unregister + * + * @return 0 on success, otherwise a negative error code + * + * Register a notifier to get notified when backlight devices get registered + * or unregistered. + */ +int backlight_unregister_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(&backlight_notifier, nb); +} +EXPORT_SYMBOL(backlight_unregister_notifier); + +/** * devm_backlight_device_register - resource managed backlight_device_register() * @dev: the device to register * @name: the name of the device @@ -544,6 +582,8 @@ static int __init backlight_class_init(void) backlight_class->pm = &backlight_class_dev_pm_ops; INIT_LIST_HEAD(&backlight_dev_list); mutex_init(&backlight_dev_list_mutex); + BLOCKING_INIT_NOTIFIER_HEAD(&backlight_notifier); + return 0; } diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c index b75201ff46f..38ca88bc5c3 100644 --- a/drivers/video/backlight/pwm_bl.c +++ b/drivers/video/backlight/pwm_bl.c @@ -10,8 +10,8 @@ * published by the Free Software Foundation. */ +#include <linux/gpio/consumer.h> #include <linux/gpio.h> -#include <linux/of_gpio.h> #include <linux/module.h> #include <linux/kernel.h> #include <linux/init.h> @@ -32,8 +32,7 @@ struct pwm_bl_data { unsigned int *levels; bool enabled; struct regulator *power_supply; - int enable_gpio; - unsigned long enable_gpio_flags; + struct gpio_desc *enable_gpio; unsigned int scale; int (*notify)(struct device *, int brightness); @@ -54,12 +53,8 @@ static void pwm_backlight_power_on(struct pwm_bl_data *pb, int brightness) if (err < 0) dev_err(pb->dev, "failed to enable power supply\n"); - if (gpio_is_valid(pb->enable_gpio)) { - if (pb->enable_gpio_flags & PWM_BACKLIGHT_GPIO_ACTIVE_LOW) - gpio_set_value(pb->enable_gpio, 0); - else - gpio_set_value(pb->enable_gpio, 1); - } + if (pb->enable_gpio) + gpiod_set_value(pb->enable_gpio, 1); pwm_enable(pb->pwm); pb->enabled = true; @@ -73,12 +68,8 @@ static void pwm_backlight_power_off(struct pwm_bl_data *pb) pwm_config(pb->pwm, 0, pb->period); pwm_disable(pb->pwm); - if (gpio_is_valid(pb->enable_gpio)) { - if (pb->enable_gpio_flags & PWM_BACKLIGHT_GPIO_ACTIVE_LOW) - gpio_set_value(pb->enable_gpio, 1); - else - gpio_set_value(pb->enable_gpio, 0); - } + if (pb->enable_gpio) + gpiod_set_value(pb->enable_gpio, 0); regulator_disable(pb->power_supply); pb->enabled = false; @@ -148,7 +139,6 @@ static int pwm_backlight_parse_dt(struct device *dev, struct platform_pwm_backlight_data *data) { struct device_node *node = dev->of_node; - enum of_gpio_flags flags; struct property *prop; int length; u32 value; @@ -189,14 +179,6 @@ static int pwm_backlight_parse_dt(struct device *dev, data->max_brightness--; } - data->enable_gpio = of_get_named_gpio_flags(node, "enable-gpios", 0, - &flags); - if (data->enable_gpio == -EPROBE_DEFER) - return -EPROBE_DEFER; - - if (gpio_is_valid(data->enable_gpio) && (flags & OF_GPIO_ACTIVE_LOW)) - data->enable_gpio_flags |= PWM_BACKLIGHT_GPIO_ACTIVE_LOW; - return 0; } @@ -256,8 +238,6 @@ static int pwm_backlight_probe(struct platform_device *pdev) } else pb->scale = data->max_brightness; - pb->enable_gpio = data->enable_gpio; - pb->enable_gpio_flags = data->enable_gpio_flags; pb->notify = data->notify; pb->notify_after = data->notify_after; pb->check_fb = data->check_fb; @@ -265,26 +245,38 @@ static int pwm_backlight_probe(struct platform_device *pdev) pb->dev = &pdev->dev; pb->enabled = false; - if (gpio_is_valid(pb->enable_gpio)) { - unsigned long flags; - - if (pb->enable_gpio_flags & PWM_BACKLIGHT_GPIO_ACTIVE_LOW) - flags = GPIOF_OUT_INIT_HIGH; + pb->enable_gpio = devm_gpiod_get(&pdev->dev, "enable"); + if (IS_ERR(pb->enable_gpio)) { + ret = PTR_ERR(pb->enable_gpio); + if (ret == -ENOENT) + pb->enable_gpio = NULL; else - flags = GPIOF_OUT_INIT_LOW; + goto err_alloc; + } - ret = gpio_request_one(pb->enable_gpio, flags, "enable"); + /* + * Compatibility fallback for drivers still using the integer GPIO + * platform data. Must go away soon. + */ + if (!pb->enable_gpio && gpio_is_valid(data->enable_gpio)) { + ret = devm_gpio_request_one(&pdev->dev, data->enable_gpio, + GPIOF_OUT_INIT_HIGH, "enable"); if (ret < 0) { dev_err(&pdev->dev, "failed to request GPIO#%d: %d\n", - pb->enable_gpio, ret); + data->enable_gpio, ret); goto err_alloc; } + + pb->enable_gpio = gpio_to_desc(data->enable_gpio); } + if (pb->enable_gpio) + gpiod_direction_output(pb->enable_gpio, 1); + pb->power_supply = devm_regulator_get(&pdev->dev, "power"); if (IS_ERR(pb->power_supply)) { ret = PTR_ERR(pb->power_supply); - goto err_gpio; + goto err_alloc; } pb->pwm = devm_pwm_get(&pdev->dev, NULL); @@ -295,7 +287,7 @@ static int pwm_backlight_probe(struct platform_device *pdev) if (IS_ERR(pb->pwm)) { dev_err(&pdev->dev, "unable to request legacy PWM\n"); ret = PTR_ERR(pb->pwm); - goto err_gpio; + goto err_alloc; } } @@ -304,12 +296,15 @@ static int pwm_backlight_probe(struct platform_device *pdev) /* * The DT case will set the pwm_period_ns field to 0 and store the * period, parsed from the DT, in the PWM device. For the non-DT case, - * set the period from platform data. + * set the period from platform data if it has not already been set + * via the PWM lookup table. */ - if (data->pwm_period_ns > 0) + pb->period = pwm_get_period(pb->pwm); + if (!pb->period && (data->pwm_period_ns > 0)) { + pb->period = data->pwm_period_ns; pwm_set_period(pb->pwm, data->pwm_period_ns); + } - pb->period = pwm_get_period(pb->pwm); pb->lth_brightness = data->lth_brightness * (pb->period / pb->scale); memset(&props, 0, sizeof(struct backlight_properties)); @@ -320,7 +315,7 @@ static int pwm_backlight_probe(struct platform_device *pdev) if (IS_ERR(bl)) { dev_err(&pdev->dev, "failed to register backlight\n"); ret = PTR_ERR(bl); - goto err_gpio; + goto err_alloc; } if (data->dft_brightness > data->max_brightness) { @@ -336,9 +331,6 @@ static int pwm_backlight_probe(struct platform_device *pdev) platform_set_drvdata(pdev, bl); return 0; -err_gpio: - if (gpio_is_valid(pb->enable_gpio)) - gpio_free(pb->enable_gpio); err_alloc: if (data->exit) data->exit(&pdev->dev); @@ -359,6 +351,14 @@ static int pwm_backlight_remove(struct platform_device *pdev) return 0; } +static void pwm_backlight_shutdown(struct platform_device *pdev) +{ + struct backlight_device *bl = platform_get_drvdata(pdev); + struct pwm_bl_data *pb = bl_get_data(bl); + + pwm_backlight_power_off(pb); +} + #ifdef CONFIG_PM_SLEEP static int pwm_backlight_suspend(struct device *dev) { @@ -404,6 +404,7 @@ static struct platform_driver pwm_backlight_driver = { }, .probe = pwm_backlight_probe, .remove = pwm_backlight_remove, + .shutdown = pwm_backlight_shutdown, }; module_platform_driver(pwm_backlight_driver); diff --git a/drivers/video/console/fbcon.c b/drivers/video/console/fbcon.c index f447734b09b..57b1d44acbf 100644 --- a/drivers/video/console/fbcon.c +++ b/drivers/video/console/fbcon.c @@ -748,6 +748,7 @@ static int con2fb_release_oldinfo(struct vc_data *vc, struct fb_info *oldinfo, fbcon_del_cursor_timer(oldinfo); kfree(ops->cursor_state.mask); kfree(ops->cursor_data); + kfree(ops->cursor_src); kfree(ops->fontbuffer); kfree(oldinfo->fbcon_par); oldinfo->fbcon_par = NULL; diff --git a/drivers/video/console/vgacon.c b/drivers/video/console/vgacon.c index 9d8feac6763..f267284b423 100644 --- a/drivers/video/console/vgacon.c +++ b/drivers/video/console/vgacon.c @@ -87,7 +87,8 @@ static void vgacon_save_screen(struct vc_data *c); static int vgacon_scroll(struct vc_data *c, int t, int b, int dir, int lines); static void vgacon_invert_region(struct vc_data *c, u16 * p, int count); -static unsigned long vgacon_uni_pagedir[2]; +static struct uni_pagedir *vgacon_uni_pagedir; +static int vgacon_refcount; /* Description of the hardware situation */ static int vga_init_done __read_mostly; @@ -553,7 +554,7 @@ static const char *vgacon_startup(void) static void vgacon_init(struct vc_data *c, int init) { - unsigned long p; + struct uni_pagedir *p; /* * We cannot be loaded as a module, therefore init is always 1, @@ -575,12 +576,12 @@ static void vgacon_init(struct vc_data *c, int init) if (vga_512_chars) c->vc_hi_font_mask = 0x0800; p = *c->vc_uni_pagedir_loc; - if (c->vc_uni_pagedir_loc == &c->vc_uni_pagedir || - !--c->vc_uni_pagedir_loc[1]) + if (c->vc_uni_pagedir_loc != &vgacon_uni_pagedir) { con_free_unimap(c); - c->vc_uni_pagedir_loc = vgacon_uni_pagedir; - vgacon_uni_pagedir[1]++; - if (!vgacon_uni_pagedir[0] && p) + c->vc_uni_pagedir_loc = &vgacon_uni_pagedir; + vgacon_refcount++; + } + if (!vgacon_uni_pagedir && p) con_set_default_unimap(c); /* Only set the default if the user didn't deliberately override it */ @@ -597,7 +598,7 @@ static void vgacon_deinit(struct vc_data *c) vga_set_mem_top(c); } - if (!--vgacon_uni_pagedir[1]) + if (!--vgacon_refcount) con_free_unimap(c); c->vc_uni_pagedir_loc = &c->vc_uni_pagedir; con_set_default_unimap(c); diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig index e1f47272fde..59c98bfd5a8 100644 --- a/drivers/video/fbdev/Kconfig +++ b/drivers/video/fbdev/Kconfig @@ -360,6 +360,7 @@ config FB_CYBER2000_DDC config FB_CYBER2000_I2C bool "CyberPro 2000/2010/5000 I2C support" depends on FB_CYBER2000 && I2C && ARCH_NETWINDER + depends on I2C=y || FB_CYBER2000=m select I2C_ALGOBIT help Enable support for the I2C video decoder interface on the @@ -966,6 +967,7 @@ config FB_S1D13XXX config FB_ATMEL tristate "AT91/AT32 LCD Controller support" depends on FB && HAVE_FB_ATMEL + select FB_BACKLIGHT select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT @@ -1971,6 +1973,7 @@ config FB_W100 config FB_SH_MOBILE_LCDC tristate "SuperH Mobile LCDC framebuffer support" depends on FB && (SUPERH || ARCH_SHMOBILE) && HAVE_CLK + depends on FB_SH_MOBILE_MERAM || !FB_SH_MOBILE_MERAM select FB_SYS_FILLRECT select FB_SYS_COPYAREA select FB_SYS_IMAGEBLIT @@ -1993,7 +1996,7 @@ config FB_SH_MOBILE_HDMI config FB_TMIO tristate "Toshiba Mobile IO FrameBuffer support" - depends on FB && MFD_CORE + depends on FB && (MFD_TMIO || COMPILE_TEST) select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT @@ -2062,7 +2065,7 @@ config FB_S3C2410_DEBUG through sysfs config FB_NUC900 - bool "NUC900 LCD framebuffer support" + tristate "NUC900 LCD framebuffer support" depends on FB && ARCH_W90X900 select FB_CFB_FILLRECT select FB_CFB_COPYAREA @@ -2169,7 +2172,7 @@ config FB_XILINX config FB_GOLDFISH tristate "Goldfish Framebuffer" - depends on FB && HAS_DMA + depends on FB && HAS_DMA && (GOLDFISH || COMPILE_TEST) select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT @@ -2295,6 +2298,7 @@ endchoice config FB_MB862XX_I2C bool "Support I2C bus on MB862XX GDC" depends on FB_MB862XX && I2C + depends on FB_MB862XX=m || I2C=y default y help Selecting this option adds Coral-P(A)/Lime GDC I2C bus adapter @@ -2332,6 +2336,7 @@ config FB_MX3 select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT + select BACKLIGHT_CLASS_DEVICE default y help This is a framebuffer device for the i.MX31 LCD Controller. So diff --git a/drivers/video/fbdev/atafb.c b/drivers/video/fbdev/atafb.c index e21d1f58554..4953b657635 100644 --- a/drivers/video/fbdev/atafb.c +++ b/drivers/video/fbdev/atafb.c @@ -191,7 +191,7 @@ static struct fb_info fb_info = { }; static void *screen_base; /* base address of screen */ -static void *real_screen_base; /* (only for Overscan) */ +static unsigned long phys_screen_base; /* (only for Overscan) */ static int screen_len; @@ -213,7 +213,8 @@ static unsigned int external_yres; */ static unsigned int external_depth; static int external_pmode; -static void *external_addr; +static void *external_screen_base; +static unsigned long external_addr; static unsigned long external_len; static unsigned long external_vgaiobase; static unsigned int external_bitspercol = 6; @@ -592,7 +593,7 @@ static int tt_encode_fix(struct fb_fix_screeninfo *fix, struct atafb_par *par) int mode; strcpy(fix->id, "Atari Builtin"); - fix->smem_start = (unsigned long)real_screen_base; + fix->smem_start = phys_screen_base; fix->smem_len = screen_len; fix->type = FB_TYPE_INTERLEAVED_PLANES; fix->type_aux = 2; @@ -790,7 +791,7 @@ static void tt_get_par(struct atafb_par *par) addr = ((shifter.bas_hi & 0xff) << 16) | ((shifter.bas_md & 0xff) << 8) | ((shifter.bas_lo & 0xff)); - par->screen_base = phys_to_virt(addr); + par->screen_base = atari_stram_to_virt(addr); } static void tt_set_par(struct atafb_par *par) @@ -888,7 +889,7 @@ static int falcon_encode_fix(struct fb_fix_screeninfo *fix, struct atafb_par *par) { strcpy(fix->id, "Atari Builtin"); - fix->smem_start = (unsigned long)real_screen_base; + fix->smem_start = phys_screen_base; fix->smem_len = screen_len; fix->type = FB_TYPE_INTERLEAVED_PLANES; fix->type_aux = 2; @@ -1584,7 +1585,7 @@ static void falcon_get_par(struct atafb_par *par) addr = (shifter.bas_hi & 0xff) << 16 | (shifter.bas_md & 0xff) << 8 | (shifter.bas_lo & 0xff); - par->screen_base = phys_to_virt(addr); + par->screen_base = atari_stram_to_virt(addr); /* derived parameters */ hw->ste_mode = (hw->f_shift & 0x510) == 0 && hw->st_shift == 0x100; @@ -1814,7 +1815,7 @@ static int stste_encode_fix(struct fb_fix_screeninfo *fix, int mode; strcpy(fix->id, "Atari Builtin"); - fix->smem_start = (unsigned long)real_screen_base; + fix->smem_start = phys_screen_base; fix->smem_len = screen_len; fix->type = FB_TYPE_INTERLEAVED_PLANES; fix->type_aux = 2; @@ -1980,7 +1981,7 @@ static void stste_get_par(struct atafb_par *par) ((shifter.bas_md & 0xff) << 8); if (ATARIHW_PRESENT(EXTD_SHIFTER)) addr |= (shifter.bas_lo & 0xff); - par->screen_base = phys_to_virt(addr); + par->screen_base = atari_stram_to_virt(addr); } static void stste_set_par(struct atafb_par *par) @@ -2039,7 +2040,7 @@ static int stste_detect(void) static void stste_set_screen_base(void *s_base) { unsigned long addr; - addr = virt_to_phys(s_base); + addr = atari_stram_to_phys(s_base); /* Setup Screen Memory */ shifter.bas_hi = (unsigned char)((addr & 0xff0000) >> 16); shifter.bas_md = (unsigned char)((addr & 0x00ff00) >> 8); @@ -2113,7 +2114,7 @@ static void st_ovsc_switch(void) static int ext_encode_fix(struct fb_fix_screeninfo *fix, struct atafb_par *par) { strcpy(fix->id, "Unknown Extern"); - fix->smem_start = (unsigned long)external_addr; + fix->smem_start = external_addr; fix->smem_len = PAGE_ALIGN(external_len); if (external_depth == 1) { fix->type = FB_TYPE_PACKED_PIXELS; @@ -2213,7 +2214,7 @@ static int ext_encode_var(struct fb_var_screeninfo *var, struct atafb_par *par) static void ext_get_par(struct atafb_par *par) { - par->screen_base = external_addr; + par->screen_base = external_screen_base; } static void ext_set_par(struct atafb_par *par) @@ -2286,7 +2287,7 @@ static void set_screen_base(void *s_base) { unsigned long addr; - addr = virt_to_phys(s_base); + addr = atari_stram_to_phys(s_base); /* Setup Screen Memory */ shifter.bas_hi = (unsigned char)((addr & 0xff0000) >> 16); shifter.bas_md = (unsigned char)((addr & 0x00ff00) >> 8); @@ -2433,7 +2434,9 @@ static void atafb_set_disp(struct fb_info *info) atafb_get_var(&info->var, info); atafb_get_fix(&info->fix, info); - info->screen_base = (void *)info->fix.smem_start; + /* Note: smem_start derives from phys_screen_base, not screen_base! */ + info->screen_base = (external_addr ? external_screen_base : + atari_stram_to_virt(info->fix.smem_start)); } static int atafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, @@ -2904,7 +2907,7 @@ static void __init atafb_setup_ext(char *spec) external_yres = yres; external_depth = depth; external_pmode = planes; - external_addr = (void *)addr; + external_addr = addr; external_len = len; if (external_card_type == IS_MV300) { @@ -3166,30 +3169,30 @@ int __init atafb_init(void) memset(screen_base, 0, mem_req); pad = -(unsigned long)screen_base & (PAGE_SIZE - 1); screen_base += pad; - real_screen_base = screen_base + ovsc_offset; + phys_screen_base = atari_stram_to_phys(screen_base + ovsc_offset); screen_len = (mem_req - pad - ovsc_offset) & PAGE_MASK; st_ovsc_switch(); if (CPU_IS_040_OR_060) { /* On a '040+, the cache mode of video RAM must be set to * write-through also for internal video hardware! */ - cache_push(virt_to_phys(screen_base), screen_len); + cache_push(atari_stram_to_phys(screen_base), screen_len); kernel_set_cachemode(screen_base, screen_len, IOMAP_WRITETHROUGH); } - printk("atafb: screen_base %p real_screen_base %p screen_len %d\n", - screen_base, real_screen_base, screen_len); + printk("atafb: screen_base %p phys_screen_base %lx screen_len %d\n", + screen_base, phys_screen_base, screen_len); #ifdef ATAFB_EXT } else { /* Map the video memory (physical address given) to somewhere * in the kernel address space. */ - external_addr = ioremap_writethrough((unsigned long)external_addr, + external_screen_base = ioremap_writethrough(external_addr, external_len); if (external_vgaiobase) external_vgaiobase = (unsigned long)ioremap(external_vgaiobase, 0x10000); - screen_base = - real_screen_base = external_addr; + screen_base = external_screen_base; + phys_screen_base = external_addr; screen_len = external_len & PAGE_MASK; memset (screen_base, 0, external_len); } @@ -3235,8 +3238,8 @@ int __init atafb_init(void) if (register_framebuffer(&fb_info) < 0) { #ifdef ATAFB_EXT if (external_addr) { - iounmap(external_addr); - external_addr = NULL; + iounmap(external_screen_base); + external_addr = 0; } if (external_vgaiobase) { iounmap((void*)external_vgaiobase); diff --git a/drivers/video/fbdev/bf54x-lq043fb.c b/drivers/video/fbdev/bf54x-lq043fb.c index e2c42ad8515..adbef542c99 100644 --- a/drivers/video/fbdev/bf54x-lq043fb.c +++ b/drivers/video/fbdev/bf54x-lq043fb.c @@ -717,8 +717,6 @@ static int bfin_bf54x_remove(struct platform_device *pdev) #ifdef CONFIG_PM static int bfin_bf54x_suspend(struct platform_device *pdev, pm_message_t state) { - struct fb_info *fbinfo = platform_get_drvdata(pdev); - bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN); disable_dma(CH_EPPI0); bfin_write_EPPI0_STATUS(0xFFFF); diff --git a/drivers/video/fbdev/core/fbmem.c b/drivers/video/fbdev/core/fbmem.c index b6d5008f361..b5e85f6c1c2 100644 --- a/drivers/video/fbdev/core/fbmem.c +++ b/drivers/video/fbdev/core/fbmem.c @@ -433,7 +433,7 @@ static void fb_do_show_logo(struct fb_info *info, struct fb_image *image, image->dx += image->width + 8; } } else if (rotate == FB_ROTATE_UD) { - for (x = 0; x < num && image->dx >= 0; x++) { + for (x = 0; x < num; x++) { info->fbops->fb_imageblit(info, image); image->dx -= image->width + 8; } @@ -445,7 +445,7 @@ static void fb_do_show_logo(struct fb_info *info, struct fb_image *image, image->dy += image->height + 8; } } else if (rotate == FB_ROTATE_CCW) { - for (x = 0; x < num && image->dy >= 0; x++) { + for (x = 0; x < num; x++) { info->fbops->fb_imageblit(info, image); image->dy -= image->height + 8; } @@ -674,6 +674,7 @@ int fb_show_logo(struct fb_info *info, int rotate) int fb_prepare_logo(struct fb_info *info, int rotate) { return 0; } int fb_show_logo(struct fb_info *info, int rotate) { return 0; } #endif /* CONFIG_LOGO */ +EXPORT_SYMBOL(fb_prepare_logo); EXPORT_SYMBOL(fb_show_logo); static void *fb_seq_start(struct seq_file *m, loff_t *pos) @@ -1179,7 +1180,7 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, return -EFAULT; if (con2fb.console < 1 || con2fb.console > MAX_NR_CONSOLES) return -EINVAL; - if (con2fb.framebuffer < 0 || con2fb.framebuffer >= FB_MAX) + if (con2fb.framebuffer >= FB_MAX) return -EINVAL; if (!registered_fb[con2fb.framebuffer]) request_module("fb%d", con2fb.framebuffer); diff --git a/drivers/video/fbdev/core/fbmon.c b/drivers/video/fbdev/core/fbmon.c index c204ebe6187..5b0e313849b 100644 --- a/drivers/video/fbdev/core/fbmon.c +++ b/drivers/video/fbdev/core/fbmon.c @@ -1012,13 +1012,20 @@ void fb_edid_add_monspecs(unsigned char *edid, struct fb_monspecs *specs) while (pos < edid[2]) { u8 len = edid[pos] & 0x1f, type = (edid[pos] >> 5) & 7; pr_debug("Data block %u of %u bytes\n", type, len); - if (type == 2) + if (type == 2) { for (i = pos; i < pos + len; i++) { u8 idx = edid[pos + i] & 0x7f; svd[svd_n++] = idx; pr_debug("N%sative mode #%d\n", edid[pos + i] & 0x80 ? "" : "on-n", idx); } + } else if (type == 3 && len >= 3) { + /* Check Vendor Specific Data Block. For HDMI, + it is always 00-0C-03 for HDMI Licensing, LLC. */ + if (edid[pos + 1] == 3 && edid[pos + 2] == 0xc && + edid[pos + 3] == 0) + specs->misc |= FB_MISC_HDMI; + } pos += len + 1; } diff --git a/drivers/video/fbdev/da8xx-fb.c b/drivers/video/fbdev/da8xx-fb.c index 6b23508ff0a..a8484f768d0 100644 --- a/drivers/video/fbdev/da8xx-fb.c +++ b/drivers/video/fbdev/da8xx-fb.c @@ -242,6 +242,20 @@ static struct fb_videomode known_lcd_panels[] = { .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, .flag = 0, }, + [3] = { + /* Densitron 84-0023-001T */ + .name = "Densitron_84-0023-001T", + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6400), + .left_margin = 0, + .right_margin = 0, + .upper_margin = 0, + .lower_margin = 0, + .hsync_len = 30, + .vsync_len = 3, + .sync = 0, + }, }; static bool da8xx_fb_is_raster_enabled(void) diff --git a/drivers/video/fbdev/exynos/Kconfig b/drivers/video/fbdev/exynos/Kconfig index fcf2d48ac6d..1f16b4678c7 100644 --- a/drivers/video/fbdev/exynos/Kconfig +++ b/drivers/video/fbdev/exynos/Kconfig @@ -4,6 +4,7 @@ menuconfig EXYNOS_VIDEO bool "Exynos Video driver support" + depends on ARCH_S5PV210 || ARCH_EXYNOS help This enables support for EXYNOS Video device. @@ -15,7 +16,6 @@ if EXYNOS_VIDEO config EXYNOS_MIPI_DSI bool "EXYNOS MIPI DSI driver support." - depends on ARCH_S5PV210 || ARCH_EXYNOS select GENERIC_PHY help This enables support for MIPI-DSI device. diff --git a/drivers/video/fbdev/fb-puv3.c b/drivers/video/fbdev/fb-puv3.c index 6db9ebd042a..88fa2e70a0b 100644 --- a/drivers/video/fbdev/fb-puv3.c +++ b/drivers/video/fbdev/fb-puv3.c @@ -18,8 +18,10 @@ #include <linux/fb.h> #include <linux/init.h> #include <linux/console.h> +#include <linux/mm.h> #include <asm/sizes.h> +#include <asm/pgtable.h> #include <mach/hardware.h> /* Platform_data reserved for unifb registers. */ diff --git a/drivers/video/fbdev/gbefb.c b/drivers/video/fbdev/gbefb.c index 3ec65a878ac..4aa56ba78f3 100644 --- a/drivers/video/fbdev/gbefb.c +++ b/drivers/video/fbdev/gbefb.c @@ -1068,7 +1068,7 @@ static struct fb_ops gbefb_ops = { static ssize_t gbefb_show_memsize(struct device *dev, struct device_attribute *attr, char *buf) { - return snprintf(buf, PAGE_SIZE, "%d\n", gbe_mem_size); + return snprintf(buf, PAGE_SIZE, "%u\n", gbe_mem_size); } static DEVICE_ATTR(size, S_IRUGO, gbefb_show_memsize, NULL); diff --git a/drivers/video/fbdev/grvga.c b/drivers/video/fbdev/grvga.c index c078701f15f..2db5bb1a33e 100644 --- a/drivers/video/fbdev/grvga.c +++ b/drivers/video/fbdev/grvga.c @@ -514,9 +514,10 @@ free_fb: static int grvga_remove(struct platform_device *device) { struct fb_info *info = dev_get_drvdata(&device->dev); - struct grvga_par *par = info->par; + struct grvga_par *par; if (info) { + par = info->par; unregister_framebuffer(info); fb_dealloc_cmap(&info->cmap); diff --git a/drivers/video/fbdev/matrox/matroxfb_base.h b/drivers/video/fbdev/matrox/matroxfb_base.h index 556d96ce40b..89a8a89a5eb 100644 --- a/drivers/video/fbdev/matrox/matroxfb_base.h +++ b/drivers/video/fbdev/matrox/matroxfb_base.h @@ -698,7 +698,7 @@ void matroxfb_unregister_driver(struct matroxfb_driver* drv); #define mga_fifo(n) do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n)) -#define WaitTillIdle() do {} while (mga_inl(M_STATUS) & 0x10000) +#define WaitTillIdle() do { mga_inl(M_STATUS); do {} while (mga_inl(M_STATUS) & 0x10000); } while (0) /* code speedup */ #ifdef CONFIG_FB_MATROX_MILLENIUM diff --git a/drivers/video/fbdev/mbx/Makefile b/drivers/video/fbdev/mbx/Makefile index 16c1165cf9c..d7ae5a9bb37 100644 --- a/drivers/video/fbdev/mbx/Makefile +++ b/drivers/video/fbdev/mbx/Makefile @@ -1,4 +1,3 @@ # Makefile for the 2700G controller driver. -obj-$(CONFIG_FB_MBX) += mbxfb.o -obj-$(CONFIG_FB_MBX_DEBUG) += mbxfbdebugfs.o +obj-y += mbxfb.o diff --git a/drivers/video/fbdev/mbx/mbxdebugfs.c b/drivers/video/fbdev/mbx/mbxdebugfs.c index 4449f249b0e..e3bc00a7529 100644 --- a/drivers/video/fbdev/mbx/mbxdebugfs.c +++ b/drivers/video/fbdev/mbx/mbxdebugfs.c @@ -17,7 +17,7 @@ struct mbxfb_debugfs_data { static int open_file_generic(struct inode *inode, struct file *file) { - file->private_data = inode->u.generic_ip; + file->private_data = inode->i_private; return 0; } diff --git a/drivers/video/fbdev/mbx/mbxfb.c b/drivers/video/fbdev/mbx/mbxfb.c index f0a5392f5fd..2bd52ed8832 100644 --- a/drivers/video/fbdev/mbx/mbxfb.c +++ b/drivers/video/fbdev/mbx/mbxfb.c @@ -877,6 +877,8 @@ static int mbxfb_resume(struct platform_device *dev) #ifndef CONFIG_FB_MBX_DEBUG #define mbxfb_debugfs_init(x) do {} while(0) #define mbxfb_debugfs_remove(x) do {} while(0) +#else +#include "mbxdebugfs.c" #endif #define res_size(_r) (((_r)->end - (_r)->start) + 1) diff --git a/drivers/video/fbdev/mmp/Kconfig b/drivers/video/fbdev/mmp/Kconfig index d4a4ffc2474..f56a7e2e813 100644 --- a/drivers/video/fbdev/mmp/Kconfig +++ b/drivers/video/fbdev/mmp/Kconfig @@ -1,6 +1,6 @@ menuconfig MMP_DISP tristate "Marvell MMP Display Subsystem support" - depends on CPU_PXA910 || CPU_MMP2 || CPU_MMP3 || CPU_PXA988 + depends on CPU_PXA910 || CPU_MMP2 help Marvell Display Subsystem support. diff --git a/drivers/video/fbdev/mmp/fb/mmpfb.c b/drivers/video/fbdev/mmp/fb/mmpfb.c index 7ab31eb76a8..910fcc6ecec 100644 --- a/drivers/video/fbdev/mmp/fb/mmpfb.c +++ b/drivers/video/fbdev/mmp/fb/mmpfb.c @@ -554,8 +554,8 @@ static void fb_info_clear(struct fb_info *info) static int mmpfb_probe(struct platform_device *pdev) { struct mmp_buffer_driver_mach_info *mi; - struct fb_info *info = 0; - struct mmpfb_info *fbi = 0; + struct fb_info *info; + struct mmpfb_info *fbi; int ret, modes_num; mi = pdev->dev.platform_data; @@ -569,10 +569,6 @@ static int mmpfb_probe(struct platform_device *pdev) if (info == NULL) return -ENOMEM; fbi = info->par; - if (!fbi) { - ret = -EINVAL; - goto failed; - } /* init fb */ fbi->fb_info = info; @@ -667,7 +663,6 @@ failed_free_buff: fbi->fb_start_dma); failed_destroy_mutex: mutex_destroy(&fbi->access_ok); -failed: dev_err(fbi->dev, "mmp-fb: frame buffer device init failed\n"); framebuffer_release(info); diff --git a/drivers/video/fbdev/mmp/hw/Kconfig b/drivers/video/fbdev/mmp/hw/Kconfig index 02f109a20cd..c735d133895 100644 --- a/drivers/video/fbdev/mmp/hw/Kconfig +++ b/drivers/video/fbdev/mmp/hw/Kconfig @@ -2,12 +2,12 @@ if MMP_DISP config MMP_DISP_CONTROLLER bool "mmp display controller hw support" - depends on CPU_PXA910 || CPU_MMP2 || CPU_MMP3 || CPU_PXA988 + depends on CPU_PXA910 || CPU_MMP2 default n help Marvell MMP display hw controller support - this controller is used on Marvell PXA910, - MMP2, MMP3, PXA988 chips + this controller is used on Marvell PXA910 and + MMP2 chips config MMP_DISP_SPI bool "mmp display controller spi port" diff --git a/drivers/video/fbdev/mmp/hw/mmp_ctrl.h b/drivers/video/fbdev/mmp/hw/mmp_ctrl.h index 53301cfdb1a..56fdeab3435 100644 --- a/drivers/video/fbdev/mmp/hw/mmp_ctrl.h +++ b/drivers/video/fbdev/mmp/hw/mmp_ctrl.h @@ -167,11 +167,7 @@ struct lcd_regs { PN2_IOPAD_CONTROL) : LCD_TOP_CTRL) /* dither configure */ -#ifdef CONFIG_CPU_PXA988 -#define LCD_DITHER_CTRL (0x01EC) -#else #define LCD_DITHER_CTRL (0x00A0) -#endif #define DITHER_TBL_INDEX_SEL(s) ((s) << 16) #define DITHER_MODE2(m) ((m) << 12) @@ -186,15 +182,6 @@ struct lcd_regs { #define DITHER_EN1 (1) /* dither table data was fixed by video bpp of input and output*/ -#ifdef CONFIG_CPU_PXA988 -#define DITHER_TB_4X4_INDEX0 (0x6e4ca280) -#define DITHER_TB_4X4_INDEX1 (0x5d7f91b3) -#define DITHER_TB_4X8_INDEX0 (0xb391a280) -#define DITHER_TB_4X8_INDEX1 (0x7f5d6e4c) -#define DITHER_TB_4X8_INDEX2 (0x80a291b3) -#define DITHER_TB_4X8_INDEX3 (0x4c6e5d7f) -#define LCD_DITHER_TBL_DATA (0x01F0) -#else #define DITHER_TB_4X4_INDEX0 (0x3b19f7d5) #define DITHER_TB_4X4_INDEX1 (0x082ac4e6) #define DITHER_TB_4X8_INDEX0 (0xf7d508e6) @@ -202,7 +189,6 @@ struct lcd_regs { #define DITHER_TB_4X8_INDEX2 (0xc4e6d5f7) #define DITHER_TB_4X8_INDEX3 (0x082a193b) #define LCD_DITHER_TBL_DATA (0x00A4) -#endif /* Video Frame 0&1 start address registers */ #define LCD_SPU_DMA_START_ADDR_Y0 0x00C0 @@ -933,16 +919,9 @@ struct lcd_regs { #define LCD_PN2_SQULN2_CTRL (0x02F0) #define ALL_LAYER_ALPHA_SEL (0x02F4) -/* pxa988 has different MASTER_CTRL from MMP3/MMP2 */ -#ifdef CONFIG_CPU_PXA988 -#define TIMING_MASTER_CONTROL (0x01F4) -#define MASTER_ENH(id) (1 << ((id) + 5)) -#define MASTER_ENV(id) (1 << ((id) + 6)) -#else #define TIMING_MASTER_CONTROL (0x02F8) #define MASTER_ENH(id) (1 << (id)) #define MASTER_ENV(id) (1 << ((id) + 4)) -#endif #define DSI_START_SEL_SHIFT(id) (((id) << 1) + 8) #define timing_master_config(path, dsi_id, lcd_id) \ @@ -1312,19 +1291,8 @@ struct dsi_regs { #define DSI_PHY_TIME_3_CFG_CSR_TIME_REQRDY_MASK (0xff) #define DSI_PHY_TIME_3_CFG_CSR_TIME_REQRDY_SHIFT 0 -/* - * DSI timings - * PXA988 has diffrent ESC CLK with MMP2/MMP3 - * it will be used in dsi_set_dphy() in pxa688_phy.c - * as low power mode clock. - */ -#ifdef CONFIG_CPU_PXA988 -#define DSI_ESC_CLK 52 /* Unit: Mhz */ -#define DSI_ESC_CLK_T 19 /* Unit: ns */ -#else #define DSI_ESC_CLK 66 /* Unit: Mhz */ #define DSI_ESC_CLK_T 15 /* Unit: ns */ -#endif /* LVDS */ /* LVDS_PHY_CTRL */ diff --git a/drivers/video/fbdev/mx3fb.c b/drivers/video/fbdev/mx3fb.c index 142e860fb52..c645a0a0c34 100644 --- a/drivers/video/fbdev/mx3fb.c +++ b/drivers/video/fbdev/mx3fb.c @@ -27,6 +27,7 @@ #include <linux/clk.h> #include <linux/mutex.h> #include <linux/dma/ipu-dma.h> +#include <linux/backlight.h> #include <linux/platform_data/dma-imx.h> #include <linux/platform_data/video-mx3fb.h> @@ -241,6 +242,7 @@ struct mx3fb_data { void __iomem *reg_base; spinlock_t lock; struct device *dev; + struct backlight_device *bl; uint32_t h_start_width; uint32_t v_start_width; @@ -271,6 +273,71 @@ struct mx3fb_info { struct fb_var_screeninfo cur_var; /* current var info */ }; +static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value); +static u32 sdc_get_brightness(struct mx3fb_data *mx3fb); + +static int mx3fb_bl_get_brightness(struct backlight_device *bl) +{ + struct mx3fb_data *fbd = bl_get_data(bl); + + return sdc_get_brightness(fbd); +} + +static int mx3fb_bl_update_status(struct backlight_device *bl) +{ + struct mx3fb_data *fbd = bl_get_data(bl); + int brightness = bl->props.brightness; + + if (bl->props.power != FB_BLANK_UNBLANK) + brightness = 0; + if (bl->props.fb_blank != FB_BLANK_UNBLANK) + brightness = 0; + + fbd->backlight_level = (fbd->backlight_level & ~0xFF) | brightness; + + sdc_set_brightness(fbd, fbd->backlight_level); + + return 0; +} + +static const struct backlight_ops mx3fb_lcdc_bl_ops = { + .update_status = mx3fb_bl_update_status, + .get_brightness = mx3fb_bl_get_brightness, +}; + +static void mx3fb_init_backlight(struct mx3fb_data *fbd) +{ + struct backlight_properties props; + struct backlight_device *bl; + + if (fbd->bl) + return; + + memset(&props, 0, sizeof(struct backlight_properties)); + props.max_brightness = 0xff; + props.type = BACKLIGHT_RAW; + sdc_set_brightness(fbd, fbd->backlight_level); + + bl = backlight_device_register("mx3fb-bl", fbd->dev, fbd, + &mx3fb_lcdc_bl_ops, &props); + if (IS_ERR(bl)) { + dev_err(fbd->dev, "error %ld on backlight register\n", + PTR_ERR(bl)); + return; + } + + fbd->bl = bl; + bl->props.power = FB_BLANK_UNBLANK; + bl->props.fb_blank = FB_BLANK_UNBLANK; + bl->props.brightness = mx3fb_bl_get_brightness(bl); +} + +static void mx3fb_exit_backlight(struct mx3fb_data *fbd) +{ + if (fbd->bl) + backlight_device_unregister(fbd->bl); +} + static void mx3fb_dma_done(void *); /* Used fb-mode and bpp. Can be set on kernel command line, therefore file-static. */ @@ -628,6 +695,16 @@ static int sdc_set_global_alpha(struct mx3fb_data *mx3fb, bool enable, uint8_t a return 0; } +static u32 sdc_get_brightness(struct mx3fb_data *mx3fb) +{ + u32 brightness; + + brightness = mx3fb_read_reg(mx3fb, SDC_PWM_CTRL); + brightness = (brightness >> 16) & 0xFF; + + return brightness; +} + static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value) { dev_dbg(mx3fb->dev, "%s: value = %d\n", __func__, value); @@ -1496,7 +1573,7 @@ static int mx3fb_probe(struct platform_device *pdev) if (!sdc_reg) return -EINVAL; - mx3fb = kzalloc(sizeof(*mx3fb), GFP_KERNEL); + mx3fb = devm_kzalloc(&pdev->dev, sizeof(*mx3fb), GFP_KERNEL); if (!mx3fb) return -ENOMEM; @@ -1534,6 +1611,8 @@ static int mx3fb_probe(struct platform_device *pdev) if (ret < 0) goto eisdc0; + mx3fb_init_backlight(mx3fb); + return 0; eisdc0: @@ -1542,7 +1621,6 @@ ersdc0: dmaengine_put(); iounmap(mx3fb->reg_base); eremap: - kfree(mx3fb); dev_err(dev, "mx3fb: failed to register fb\n"); return ret; } @@ -1557,11 +1635,12 @@ static int mx3fb_remove(struct platform_device *dev) chan = &mx3_fbi->idmac_channel->dma_chan; release_fbi(fbi); + mx3fb_exit_backlight(mx3fb); + dma_release_channel(chan); dmaengine_put(); iounmap(mx3fb->reg_base); - kfree(mx3fb); return 0; } diff --git a/drivers/video/fbdev/omap/Kconfig b/drivers/video/fbdev/omap/Kconfig index 0bc3a936ce2..18c4cb0d569 100644 --- a/drivers/video/fbdev/omap/Kconfig +++ b/drivers/video/fbdev/omap/Kconfig @@ -39,6 +39,15 @@ config FB_OMAP_LCD_MIPID the Mobile Industry Processor Interface DBI-C/DCS specification. (Supported LCDs: Philips LPH8923, Sharp LS041Y3) +config FB_OMAP_LCD_H3 + bool "TPS65010 LCD controller on OMAP-H3" + depends on MACH_OMAP_H3 + depends on TPS65010 + default y + help + Say Y here if you want to have support for the LCD on the + H3 board. + config FB_OMAP_DMA_TUNE bool "Set DMA SDRAM access priority high" depends on FB_OMAP diff --git a/drivers/video/fbdev/omap/Makefile b/drivers/video/fbdev/omap/Makefile index 1927faffb5b..732e0718be5 100644 --- a/drivers/video/fbdev/omap/Makefile +++ b/drivers/video/fbdev/omap/Makefile @@ -10,17 +10,18 @@ objs-y$(CONFIG_FB_OMAP_LCDC_EXTERNAL) += sossi.o objs-y$(CONFIG_FB_OMAP_LCDC_HWA742) += hwa742.o -objs-y$(CONFIG_MACH_AMS_DELTA) += lcd_ams_delta.o -objs-y$(CONFIG_MACH_OMAP_H3) += lcd_h3.o -objs-y$(CONFIG_MACH_OMAP_PALMTE) += lcd_palmte.o -objs-y$(CONFIG_MACH_OMAP_PALMTT) += lcd_palmtt.o -objs-y$(CONFIG_MACH_OMAP_PALMZ71) += lcd_palmz71.o -objs-$(CONFIG_ARCH_OMAP16XX)$(CONFIG_MACH_OMAP_INNOVATOR) += lcd_inn1610.o -objs-$(CONFIG_ARCH_OMAP15XX)$(CONFIG_MACH_OMAP_INNOVATOR) += lcd_inn1510.o -objs-y$(CONFIG_MACH_OMAP_OSK) += lcd_osk.o - -objs-y$(CONFIG_FB_OMAP_LCD_MIPID) += lcd_mipid.o -objs-y$(CONFIG_MACH_HERALD) += lcd_htcherald.o +lcds-y$(CONFIG_MACH_AMS_DELTA) += lcd_ams_delta.o +lcds-y$(CONFIG_FB_OMAP_LCD_H3) += lcd_h3.o +lcds-y$(CONFIG_MACH_OMAP_PALMTE) += lcd_palmte.o +lcds-y$(CONFIG_MACH_OMAP_PALMTT) += lcd_palmtt.o +lcds-y$(CONFIG_MACH_OMAP_PALMZ71) += lcd_palmz71.o +lcds-$(CONFIG_ARCH_OMAP16XX)$(CONFIG_MACH_OMAP_INNOVATOR) += lcd_inn1610.o +lcds-$(CONFIG_ARCH_OMAP15XX)$(CONFIG_MACH_OMAP_INNOVATOR) += lcd_inn1510.o +lcds-y$(CONFIG_MACH_OMAP_OSK) += lcd_osk.o + +lcds-y$(CONFIG_FB_OMAP_LCD_MIPID) += lcd_mipid.o +lcds-y$(CONFIG_MACH_HERALD) += lcd_htcherald.o omapfb-objs := $(objs-yy) +obj-$(CONFIG_FB_OMAP) += $(lcds-yy) diff --git a/drivers/video/fbdev/omap/lcdc.c b/drivers/video/fbdev/omap/lcdc.c index b52f62595f6..6efa2591eaa 100644 --- a/drivers/video/fbdev/omap/lcdc.c +++ b/drivers/video/fbdev/omap/lcdc.c @@ -74,7 +74,6 @@ static struct omap_lcd_controller { void (*dma_callback)(void *data); void *dma_callback_data; - int fbmem_allocated; dma_addr_t vram_phys; void *vram_virt; unsigned long vram_size; @@ -611,42 +610,6 @@ static void lcdc_dma_handler(u16 status, void *data) lcdc.dma_callback(lcdc.dma_callback_data); } -static int mmap_kern(void) -{ - struct vm_struct *kvma; - struct vm_area_struct vma; - pgprot_t pgprot; - unsigned long vaddr; - - kvma = get_vm_area(lcdc.vram_size, VM_IOREMAP); - if (kvma == NULL) { - dev_err(lcdc.fbdev->dev, "can't get kernel vm area\n"); - return -ENOMEM; - } - vma.vm_mm = &init_mm; - - vaddr = (unsigned long)kvma->addr; - vma.vm_start = vaddr; - vma.vm_end = vaddr + lcdc.vram_size; - - pgprot = pgprot_writecombine(pgprot_kernel); - if (io_remap_pfn_range(&vma, vaddr, - lcdc.vram_phys >> PAGE_SHIFT, - lcdc.vram_size, pgprot) < 0) { - dev_err(lcdc.fbdev->dev, "kernel mmap for FB memory failed\n"); - return -EAGAIN; - } - - lcdc.vram_virt = (void *)vaddr; - - return 0; -} - -static void unmap_kern(void) -{ - vunmap(lcdc.vram_virt); -} - static int alloc_palette_ram(void) { lcdc.palette_virt = dma_alloc_writecombine(lcdc.fbdev->dev, @@ -703,8 +666,6 @@ static void free_fbmem(void) static int setup_fbmem(struct omapfb_mem_desc *req_md) { - int r; - if (!req_md->region_cnt) { dev_err(lcdc.fbdev->dev, "no memory regions defined\n"); return -EINVAL; @@ -715,31 +676,7 @@ static int setup_fbmem(struct omapfb_mem_desc *req_md) req_md->region_cnt = 1; } - if (req_md->region[0].paddr == 0) { - lcdc.fbmem_allocated = 1; - if ((r = alloc_fbmem(&req_md->region[0])) < 0) - return r; - return 0; - } - - lcdc.vram_phys = req_md->region[0].paddr; - lcdc.vram_size = req_md->region[0].size; - - if ((r = mmap_kern()) < 0) - return r; - - dev_dbg(lcdc.fbdev->dev, "vram at %08x size %08lx mapped to 0x%p\n", - lcdc.vram_phys, lcdc.vram_size, lcdc.vram_virt); - - return 0; -} - -static void cleanup_fbmem(void) -{ - if (lcdc.fbmem_allocated) - free_fbmem(); - else - unmap_kern(); + return alloc_fbmem(&req_md->region[0]); } static int omap_lcdc_init(struct omapfb_device *fbdev, int ext_mode, @@ -833,7 +770,7 @@ static void omap_lcdc_cleanup(void) { if (!lcdc.ext_mode) free_palette_ram(); - cleanup_fbmem(); + free_fbmem(); omap_free_lcd_dma(); free_irq(OMAP_LCDC_IRQ, lcdc.fbdev); clk_disable(lcdc.lcd_ck); diff --git a/drivers/video/fbdev/omap/omapfb_main.c b/drivers/video/fbdev/omap/omapfb_main.c index e4fc6d9b537..d8d028d9871 100644 --- a/drivers/video/fbdev/omap/omapfb_main.c +++ b/drivers/video/fbdev/omap/omapfb_main.c @@ -1823,6 +1823,7 @@ void omapfb_register_panel(struct lcd_panel *panel) if (fbdev_pdev != NULL) omapfb_do_probe(fbdev_pdev, fbdev_panel); } +EXPORT_SYMBOL_GPL(omapfb_register_panel); /* Called when the device is being detached from the driver */ static int omapfb_remove(struct platform_device *pdev) diff --git a/drivers/video/fbdev/omap2/Makefile b/drivers/video/fbdev/omap2/Makefile index bf8127df8c7..f8745ec369c 100644 --- a/drivers/video/fbdev/omap2/Makefile +++ b/drivers/video/fbdev/omap2/Makefile @@ -1,5 +1,5 @@ obj-$(CONFIG_OMAP2_VRFB) += vrfb.o -obj-$(CONFIG_OMAP2_DSS) += dss/ +obj-y += dss/ obj-y += displays-new/ obj-$(CONFIG_FB_OMAP2) += omapfb/ diff --git a/drivers/video/fbdev/omap2/displays-new/connector-hdmi.c b/drivers/video/fbdev/omap2/displays-new/connector-hdmi.c index 29ed21b9dce..4420ccb69aa 100644 --- a/drivers/video/fbdev/omap2/displays-new/connector-hdmi.c +++ b/drivers/video/fbdev/omap2/displays-new/connector-hdmi.c @@ -13,6 +13,7 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> +#include <linux/of_gpio.h> #include <drm/drm_edid.h> @@ -43,6 +44,8 @@ struct panel_drv_data { struct device *dev; struct omap_video_timings timings; + + int hpd_gpio; }; #define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev) @@ -161,7 +164,10 @@ static bool hdmic_detect(struct omap_dss_device *dssdev) struct panel_drv_data *ddata = to_panel_data(dssdev); struct omap_dss_device *in = ddata->in; - return in->ops.hdmi->detect(in); + if (gpio_is_valid(ddata->hpd_gpio)) + return gpio_get_value_cansleep(ddata->hpd_gpio); + else + return in->ops.hdmi->detect(in); } static int hdmic_audio_enable(struct omap_dss_device *dssdev) @@ -288,6 +294,8 @@ static int hdmic_probe_pdata(struct platform_device *pdev) pdata = dev_get_platdata(&pdev->dev); + ddata->hpd_gpio = -ENODEV; + in = omap_dss_find_output(pdata->source); if (in == NULL) { dev_err(&pdev->dev, "Failed to find video source\n"); @@ -307,6 +315,14 @@ static int hdmic_probe_of(struct platform_device *pdev) struct panel_drv_data *ddata = platform_get_drvdata(pdev); struct device_node *node = pdev->dev.of_node; struct omap_dss_device *in; + int gpio; + + /* HPD GPIO */ + gpio = of_get_named_gpio(node, "hpd-gpios", 0); + if (gpio_is_valid(gpio)) + ddata->hpd_gpio = gpio; + else + ddata->hpd_gpio = -ENODEV; in = omapdss_of_find_source_for_first_ep(node); if (IS_ERR(in)) { @@ -344,6 +360,13 @@ static int hdmic_probe(struct platform_device *pdev) return -ENODEV; } + if (gpio_is_valid(ddata->hpd_gpio)) { + r = devm_gpio_request_one(&pdev->dev, ddata->hpd_gpio, + GPIOF_DIR_IN, "hdmi_hpd"); + if (r) + goto err_reg; + } + ddata->timings = hdmic_default_timings; dssdev = &ddata->dssdev; diff --git a/drivers/video/fbdev/omap2/displays-new/panel-dpi.c b/drivers/video/fbdev/omap2/displays-new/panel-dpi.c index 5f8f7e7c81e..3636b61dc9b 100644 --- a/drivers/video/fbdev/omap2/displays-new/panel-dpi.c +++ b/drivers/video/fbdev/omap2/displays-new/panel-dpi.c @@ -13,9 +13,12 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/slab.h> +#include <linux/of.h> +#include <linux/of_gpio.h> #include <video/omapdss.h> #include <video/omap-panel-data.h> +#include <video/of_display_timing.h> struct panel_drv_data { struct omap_dss_device dssdev; @@ -25,8 +28,10 @@ struct panel_drv_data { struct omap_video_timings videomode; + /* used for non-DT boot, to be removed */ int backlight_gpio; - int enable_gpio; + + struct gpio_desc *enable_gpio; }; #define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev) @@ -70,15 +75,16 @@ static int panel_dpi_enable(struct omap_dss_device *dssdev) if (omapdss_device_is_enabled(dssdev)) return 0; - in->ops.dpi->set_data_lines(in, ddata->data_lines); + if (ddata->data_lines) + in->ops.dpi->set_data_lines(in, ddata->data_lines); in->ops.dpi->set_timings(in, &ddata->videomode); r = in->ops.dpi->enable(in); if (r) return r; - if (gpio_is_valid(ddata->enable_gpio)) - gpio_set_value_cansleep(ddata->enable_gpio, 1); + if (ddata->enable_gpio) + gpiod_set_value_cansleep(ddata->enable_gpio, 1); if (gpio_is_valid(ddata->backlight_gpio)) gpio_set_value_cansleep(ddata->backlight_gpio, 1); @@ -96,8 +102,8 @@ static void panel_dpi_disable(struct omap_dss_device *dssdev) if (!omapdss_device_is_enabled(dssdev)) return; - if (gpio_is_valid(ddata->enable_gpio)) - gpio_set_value_cansleep(ddata->enable_gpio, 0); + if (ddata->enable_gpio) + gpiod_set_value_cansleep(ddata->enable_gpio, 0); if (gpio_is_valid(ddata->backlight_gpio)) gpio_set_value_cansleep(ddata->backlight_gpio, 0); @@ -156,6 +162,7 @@ static int panel_dpi_probe_pdata(struct platform_device *pdev) struct panel_drv_data *ddata = platform_get_drvdata(pdev); struct omap_dss_device *dssdev, *in; struct videomode vm; + int r; pdata = dev_get_platdata(&pdev->dev); @@ -176,10 +183,65 @@ static int panel_dpi_probe_pdata(struct platform_device *pdev) dssdev = &ddata->dssdev; dssdev->name = pdata->name; - ddata->enable_gpio = pdata->enable_gpio; + r = devm_gpio_request_one(&pdev->dev, pdata->enable_gpio, + GPIOF_OUT_INIT_LOW, "panel enable"); + if (r) + goto err_gpio; + + ddata->enable_gpio = gpio_to_desc(pdata->enable_gpio); + ddata->backlight_gpio = pdata->backlight_gpio; return 0; + +err_gpio: + omap_dss_put_device(ddata->in); + return r; +} + +static int panel_dpi_probe_of(struct platform_device *pdev) +{ + struct panel_drv_data *ddata = platform_get_drvdata(pdev); + struct device_node *node = pdev->dev.of_node; + struct omap_dss_device *in; + int r; + struct display_timing timing; + struct videomode vm; + struct gpio_desc *gpio; + + gpio = devm_gpiod_get(&pdev->dev, "enable"); + + if (IS_ERR(gpio)) { + if (PTR_ERR(gpio) != -ENOENT) + return PTR_ERR(gpio); + else + gpio = NULL; + } else { + gpiod_direction_output(gpio, 0); + } + + ddata->enable_gpio = gpio; + + ddata->backlight_gpio = -ENOENT; + + r = of_get_display_timing(node, "panel-timing", &timing); + if (r) { + dev_err(&pdev->dev, "failed to get video timing\n"); + return r; + } + + videomode_from_timing(&timing, &vm); + videomode_to_omap_video_timings(&vm, &ddata->videomode); + + in = omapdss_of_find_source_for_first_ep(node); + if (IS_ERR(in)) { + dev_err(&pdev->dev, "failed to find video source\n"); + return PTR_ERR(in); + } + + ddata->in = in; + + return 0; } static int panel_dpi_probe(struct platform_device *pdev) @@ -198,17 +260,14 @@ static int panel_dpi_probe(struct platform_device *pdev) r = panel_dpi_probe_pdata(pdev); if (r) return r; + } else if (pdev->dev.of_node) { + r = panel_dpi_probe_of(pdev); + if (r) + return r; } else { return -ENODEV; } - if (gpio_is_valid(ddata->enable_gpio)) { - r = devm_gpio_request_one(&pdev->dev, ddata->enable_gpio, - GPIOF_OUT_INIT_LOW, "panel enable"); - if (r) - goto err_gpio; - } - if (gpio_is_valid(ddata->backlight_gpio)) { r = devm_gpio_request_one(&pdev->dev, ddata->backlight_gpio, GPIOF_OUT_INIT_LOW, "panel backlight"); @@ -254,12 +313,20 @@ static int __exit panel_dpi_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id panel_dpi_of_match[] = { + { .compatible = "omapdss,panel-dpi", }, + {}, +}; + +MODULE_DEVICE_TABLE(of, panel_dpi_of_match); + static struct platform_driver panel_dpi_driver = { .probe = panel_dpi_probe, .remove = __exit_p(panel_dpi_remove), .driver = { .name = "panel-dpi", .owner = THIS_MODULE, + .of_match_table = panel_dpi_of_match, }, }; diff --git a/drivers/video/fbdev/omap2/displays-new/panel-lgphilips-lb035q02.c b/drivers/video/fbdev/omap2/displays-new/panel-lgphilips-lb035q02.c index 2e6b513222d..cc5b5124e0b 100644 --- a/drivers/video/fbdev/omap2/displays-new/panel-lgphilips-lb035q02.c +++ b/drivers/video/fbdev/omap2/displays-new/panel-lgphilips-lb035q02.c @@ -50,9 +50,10 @@ struct panel_drv_data { struct omap_video_timings videomode; - int reset_gpio; + /* used for non-DT boot, to be removed */ int backlight_gpio; - int enable_gpio; + + struct gpio_desc *enable_gpio; }; #define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev) @@ -158,15 +159,16 @@ static int lb035q02_enable(struct omap_dss_device *dssdev) if (omapdss_device_is_enabled(dssdev)) return 0; - in->ops.dpi->set_data_lines(in, ddata->data_lines); + if (ddata->data_lines) + in->ops.dpi->set_data_lines(in, ddata->data_lines); in->ops.dpi->set_timings(in, &ddata->videomode); r = in->ops.dpi->enable(in); if (r) return r; - if (gpio_is_valid(ddata->enable_gpio)) - gpio_set_value_cansleep(ddata->enable_gpio, 1); + if (ddata->enable_gpio) + gpiod_set_value_cansleep(ddata->enable_gpio, 1); if (gpio_is_valid(ddata->backlight_gpio)) gpio_set_value_cansleep(ddata->backlight_gpio, 1); @@ -184,8 +186,8 @@ static void lb035q02_disable(struct omap_dss_device *dssdev) if (!omapdss_device_is_enabled(dssdev)) return; - if (gpio_is_valid(ddata->enable_gpio)) - gpio_set_value_cansleep(ddata->enable_gpio, 0); + if (ddata->enable_gpio) + gpiod_set_value_cansleep(ddata->enable_gpio, 0); if (gpio_is_valid(ddata->backlight_gpio)) gpio_set_value_cansleep(ddata->backlight_gpio, 0); @@ -243,6 +245,7 @@ static int lb035q02_probe_pdata(struct spi_device *spi) const struct panel_lb035q02_platform_data *pdata; struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev); struct omap_dss_device *dssdev, *in; + int r; pdata = dev_get_platdata(&spi->dev); @@ -260,10 +263,48 @@ static int lb035q02_probe_pdata(struct spi_device *spi) dssdev = &ddata->dssdev; dssdev->name = pdata->name; - ddata->enable_gpio = pdata->enable_gpio; + r = devm_gpio_request_one(&spi->dev, pdata->enable_gpio, + GPIOF_OUT_INIT_LOW, "panel enable"); + if (r) + goto err_gpio; + + ddata->enable_gpio = gpio_to_desc(pdata->enable_gpio); + ddata->backlight_gpio = pdata->backlight_gpio; return 0; +err_gpio: + omap_dss_put_device(ddata->in); + return r; +} + +static int lb035q02_probe_of(struct spi_device *spi) +{ + struct device_node *node = spi->dev.of_node; + struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev); + struct omap_dss_device *in; + struct gpio_desc *gpio; + + gpio = devm_gpiod_get(&spi->dev, "enable"); + if (IS_ERR(gpio)) { + dev_err(&spi->dev, "failed to parse enable gpio\n"); + return PTR_ERR(gpio); + } else { + gpiod_direction_output(gpio, 0); + ddata->enable_gpio = gpio; + } + + ddata->backlight_gpio = -ENOENT; + + in = omapdss_of_find_source_for_first_ep(node); + if (IS_ERR(in)) { + dev_err(&spi->dev, "failed to find video source\n"); + return PTR_ERR(in); + } + + ddata->in = in; + + return 0; } static int lb035q02_panel_spi_probe(struct spi_device *spi) @@ -284,17 +325,14 @@ static int lb035q02_panel_spi_probe(struct spi_device *spi) r = lb035q02_probe_pdata(spi); if (r) return r; + } else if (spi->dev.of_node) { + r = lb035q02_probe_of(spi); + if (r) + return r; } else { return -ENODEV; } - if (gpio_is_valid(ddata->enable_gpio)) { - r = devm_gpio_request_one(&spi->dev, ddata->enable_gpio, - GPIOF_OUT_INIT_LOW, "panel enable"); - if (r) - goto err_gpio; - } - if (gpio_is_valid(ddata->backlight_gpio)) { r = devm_gpio_request_one(&spi->dev, ddata->backlight_gpio, GPIOF_OUT_INIT_LOW, "panel backlight"); @@ -342,17 +380,26 @@ static int lb035q02_panel_spi_remove(struct spi_device *spi) return 0; } +static const struct of_device_id lb035q02_of_match[] = { + { .compatible = "omapdss,lgphilips,lb035q02", }, + {}, +}; + +MODULE_DEVICE_TABLE(of, lb035q02_of_match); + static struct spi_driver lb035q02_spi_driver = { .probe = lb035q02_panel_spi_probe, .remove = lb035q02_panel_spi_remove, .driver = { .name = "panel_lgphilips_lb035q02", .owner = THIS_MODULE, + .of_match_table = lb035q02_of_match, }, }; module_spi_driver(lb035q02_spi_driver); +MODULE_ALIAS("spi:lgphilips,lb035q02"); MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@ti.com>"); MODULE_DESCRIPTION("LG.Philips LB035Q02 LCD Panel driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/video/fbdev/omap2/displays-new/panel-nec-nl8048hl11.c b/drivers/video/fbdev/omap2/displays-new/panel-nec-nl8048hl11.c index 996fa004b48..3595f111aa3 100644 --- a/drivers/video/fbdev/omap2/displays-new/panel-nec-nl8048hl11.c +++ b/drivers/video/fbdev/omap2/displays-new/panel-nec-nl8048hl11.c @@ -16,6 +16,7 @@ #include <linux/spi/spi.h> #include <linux/fb.h> #include <linux/gpio.h> +#include <linux/of_gpio.h> #include <video/omapdss.h> #include <video/omap-panel-data.h> @@ -156,7 +157,8 @@ static int nec_8048_enable(struct omap_dss_device *dssdev) if (omapdss_device_is_enabled(dssdev)) return 0; - in->ops.dpi->set_data_lines(in, ddata->data_lines); + if (ddata->data_lines) + in->ops.dpi->set_data_lines(in, ddata->data_lines); in->ops.dpi->set_timings(in, &ddata->videomode); r = in->ops.dpi->enable(in); @@ -258,6 +260,34 @@ static int nec_8048_probe_pdata(struct spi_device *spi) return 0; } +static int nec_8048_probe_of(struct spi_device *spi) +{ + struct device_node *node = spi->dev.of_node; + struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev); + struct omap_dss_device *in; + int gpio; + + gpio = of_get_named_gpio(node, "reset-gpios", 0); + if (!gpio_is_valid(gpio)) { + dev_err(&spi->dev, "failed to parse enable gpio\n"); + return gpio; + } + ddata->res_gpio = gpio; + + /* XXX the panel spec doesn't mention any QVGA pin?? */ + ddata->qvga_gpio = -ENOENT; + + in = omapdss_of_find_source_for_first_ep(node); + if (IS_ERR(in)) { + dev_err(&spi->dev, "failed to find video source\n"); + return PTR_ERR(in); + } + + ddata->in = in; + + return 0; +} + static int nec_8048_probe(struct spi_device *spi) { struct panel_drv_data *ddata; @@ -289,6 +319,10 @@ static int nec_8048_probe(struct spi_device *spi) r = nec_8048_probe_pdata(spi); if (r) return r; + } else if (spi->dev.of_node) { + r = nec_8048_probe_of(spi); + if (r) + return r; } else { return -ENODEV; } @@ -377,11 +411,19 @@ static SIMPLE_DEV_PM_OPS(nec_8048_pm_ops, nec_8048_suspend, #define NEC_8048_PM_OPS NULL #endif +static const struct of_device_id nec_8048_of_match[] = { + { .compatible = "omapdss,nec,nl8048hl11", }, + {}, +}; + +MODULE_DEVICE_TABLE(of, nec_8048_of_match); + static struct spi_driver nec_8048_driver = { .driver = { .name = "panel-nec-nl8048hl11", .owner = THIS_MODULE, .pm = NEC_8048_PM_OPS, + .of_match_table = nec_8048_of_match, }, .probe = nec_8048_probe, .remove = nec_8048_remove, @@ -389,6 +431,7 @@ static struct spi_driver nec_8048_driver = { module_spi_driver(nec_8048_driver); +MODULE_ALIAS("spi:nec,nl8048hl11"); MODULE_AUTHOR("Erik Gilling <konkers@android.com>"); MODULE_DESCRIPTION("NEC-NL8048HL11 Driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/video/fbdev/omap2/displays-new/panel-sharp-ls037v7dw01.c b/drivers/video/fbdev/omap2/displays-new/panel-sharp-ls037v7dw01.c index b2f710be565..f1f72ce50a1 100644 --- a/drivers/video/fbdev/omap2/displays-new/panel-sharp-ls037v7dw01.c +++ b/drivers/video/fbdev/omap2/displays-new/panel-sharp-ls037v7dw01.c @@ -12,25 +12,28 @@ #include <linux/delay.h> #include <linux/gpio.h> #include <linux/module.h> +#include <linux/of.h> +#include <linux/of_gpio.h> #include <linux/platform_device.h> #include <linux/slab.h> - +#include <linux/regulator/consumer.h> #include <video/omapdss.h> #include <video/omap-panel-data.h> struct panel_drv_data { struct omap_dss_device dssdev; struct omap_dss_device *in; + struct regulator *vcc; int data_lines; struct omap_video_timings videomode; - int resb_gpio; - int ini_gpio; - int mo_gpio; - int lr_gpio; - int ud_gpio; + struct gpio_desc *resb_gpio; /* low = reset active min 20 us */ + struct gpio_desc *ini_gpio; /* high = power on */ + struct gpio_desc *mo_gpio; /* low = 480x640, high = 240x320 */ + struct gpio_desc *lr_gpio; /* high = conventional horizontal scanning */ + struct gpio_desc *ud_gpio; /* high = conventional vertical scanning */ }; static const struct omap_video_timings sharp_ls_timings = { @@ -95,21 +98,30 @@ static int sharp_ls_enable(struct omap_dss_device *dssdev) if (omapdss_device_is_enabled(dssdev)) return 0; - in->ops.dpi->set_data_lines(in, ddata->data_lines); + if (ddata->data_lines) + in->ops.dpi->set_data_lines(in, ddata->data_lines); in->ops.dpi->set_timings(in, &ddata->videomode); + if (ddata->vcc) { + r = regulator_enable(ddata->vcc); + if (r != 0) + return r; + } + r = in->ops.dpi->enable(in); - if (r) + if (r) { + regulator_disable(ddata->vcc); return r; + } /* wait couple of vsyncs until enabling the LCD */ msleep(50); - if (gpio_is_valid(ddata->resb_gpio)) - gpio_set_value_cansleep(ddata->resb_gpio, 1); + if (ddata->resb_gpio) + gpiod_set_value_cansleep(ddata->resb_gpio, 1); - if (gpio_is_valid(ddata->ini_gpio)) - gpio_set_value_cansleep(ddata->ini_gpio, 1); + if (ddata->ini_gpio) + gpiod_set_value_cansleep(ddata->ini_gpio, 1); dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; @@ -124,11 +136,11 @@ static void sharp_ls_disable(struct omap_dss_device *dssdev) if (!omapdss_device_is_enabled(dssdev)) return; - if (gpio_is_valid(ddata->ini_gpio)) - gpio_set_value_cansleep(ddata->ini_gpio, 0); + if (ddata->ini_gpio) + gpiod_set_value_cansleep(ddata->ini_gpio, 0); - if (gpio_is_valid(ddata->resb_gpio)) - gpio_set_value_cansleep(ddata->resb_gpio, 0); + if (ddata->resb_gpio) + gpiod_set_value_cansleep(ddata->resb_gpio, 0); /* wait at least 5 vsyncs after disabling the LCD */ @@ -136,6 +148,9 @@ static void sharp_ls_disable(struct omap_dss_device *dssdev) in->ops.dpi->disable(in); + if (ddata->vcc) + regulator_disable(ddata->vcc); + dssdev->state = OMAP_DSS_DISPLAY_DISABLED; } @@ -182,11 +197,32 @@ static struct omap_dss_driver sharp_ls_ops = { .get_resolution = omapdss_default_get_resolution, }; +static int sharp_ls_get_gpio(struct device *dev, int gpio, unsigned long flags, + char *desc, struct gpio_desc **gpiod) +{ + struct gpio_desc *gd; + int r; + + *gpiod = NULL; + + r = devm_gpio_request_one(dev, gpio, flags, desc); + if (r) + return r == -ENOENT ? 0 : r; + + gd = gpio_to_desc(gpio); + if (IS_ERR(gd)) + return PTR_ERR(gd) == -ENOENT ? 0 : PTR_ERR(gd); + + *gpiod = gd; + return 0; +} + static int sharp_ls_probe_pdata(struct platform_device *pdev) { const struct panel_sharp_ls037v7dw01_platform_data *pdata; struct panel_drv_data *ddata = platform_get_drvdata(pdev); struct omap_dss_device *dssdev, *in; + int r; pdata = dev_get_platdata(&pdev->dev); @@ -204,11 +240,95 @@ static int sharp_ls_probe_pdata(struct platform_device *pdev) dssdev = &ddata->dssdev; dssdev->name = pdata->name; - ddata->resb_gpio = pdata->resb_gpio; - ddata->ini_gpio = pdata->ini_gpio; - ddata->mo_gpio = pdata->mo_gpio; - ddata->lr_gpio = pdata->lr_gpio; - ddata->ud_gpio = pdata->ud_gpio; + r = sharp_ls_get_gpio(&pdev->dev, pdata->mo_gpio, GPIOF_OUT_INIT_LOW, + "lcd MO", &ddata->mo_gpio); + if (r) + return r; + r = sharp_ls_get_gpio(&pdev->dev, pdata->lr_gpio, GPIOF_OUT_INIT_HIGH, + "lcd LR", &ddata->lr_gpio); + if (r) + return r; + r = sharp_ls_get_gpio(&pdev->dev, pdata->ud_gpio, GPIOF_OUT_INIT_HIGH, + "lcd UD", &ddata->ud_gpio); + if (r) + return r; + r = sharp_ls_get_gpio(&pdev->dev, pdata->resb_gpio, GPIOF_OUT_INIT_LOW, + "lcd RESB", &ddata->resb_gpio); + if (r) + return r; + r = sharp_ls_get_gpio(&pdev->dev, pdata->ini_gpio, GPIOF_OUT_INIT_LOW, + "lcd INI", &ddata->ini_gpio); + if (r) + return r; + + return 0; +} + +static int sharp_ls_get_gpio_of(struct device *dev, int index, int val, + const char *desc, struct gpio_desc **gpiod) +{ + struct gpio_desc *gd; + int r; + + *gpiod = NULL; + + gd = devm_gpiod_get_index(dev, desc, index); + if (IS_ERR(gd)) + return PTR_ERR(gd) == -ENOENT ? 0 : PTR_ERR(gd); + + r = gpiod_direction_output(gd, val); + if (r) + return r; + + *gpiod = gd; + return 0; +} + +static int sharp_ls_probe_of(struct platform_device *pdev) +{ + struct panel_drv_data *ddata = platform_get_drvdata(pdev); + struct device_node *node = pdev->dev.of_node; + struct omap_dss_device *in; + int r; + + ddata->vcc = devm_regulator_get(&pdev->dev, "envdd"); + if (IS_ERR(ddata->vcc)) { + dev_err(&pdev->dev, "failed to get regulator\n"); + return PTR_ERR(ddata->vcc); + } + + /* lcd INI */ + r = sharp_ls_get_gpio_of(&pdev->dev, 0, 0, "enable", &ddata->ini_gpio); + if (r) + return r; + + /* lcd RESB */ + r = sharp_ls_get_gpio_of(&pdev->dev, 0, 0, "reset", &ddata->resb_gpio); + if (r) + return r; + + /* lcd MO */ + r = sharp_ls_get_gpio_of(&pdev->dev, 0, 0, "mode", &ddata->mo_gpio); + if (r) + return r; + + /* lcd LR */ + r = sharp_ls_get_gpio_of(&pdev->dev, 1, 1, "mode", &ddata->lr_gpio); + if (r) + return r; + + /* lcd UD */ + r = sharp_ls_get_gpio_of(&pdev->dev, 2, 1, "mode", &ddata->ud_gpio); + if (r) + return r; + + in = omapdss_of_find_source_for_first_ep(node); + if (IS_ERR(in)) { + dev_err(&pdev->dev, "failed to find video source\n"); + return PTR_ERR(in); + } + + ddata->in = in; return 0; } @@ -229,45 +349,14 @@ static int sharp_ls_probe(struct platform_device *pdev) r = sharp_ls_probe_pdata(pdev); if (r) return r; + } else if (pdev->dev.of_node) { + r = sharp_ls_probe_of(pdev); + if (r) + return r; } else { return -ENODEV; } - if (gpio_is_valid(ddata->mo_gpio)) { - r = devm_gpio_request_one(&pdev->dev, ddata->mo_gpio, - GPIOF_OUT_INIT_LOW, "lcd MO"); - if (r) - goto err_gpio; - } - - if (gpio_is_valid(ddata->lr_gpio)) { - r = devm_gpio_request_one(&pdev->dev, ddata->lr_gpio, - GPIOF_OUT_INIT_HIGH, "lcd LR"); - if (r) - goto err_gpio; - } - - if (gpio_is_valid(ddata->ud_gpio)) { - r = devm_gpio_request_one(&pdev->dev, ddata->ud_gpio, - GPIOF_OUT_INIT_HIGH, "lcd UD"); - if (r) - goto err_gpio; - } - - if (gpio_is_valid(ddata->resb_gpio)) { - r = devm_gpio_request_one(&pdev->dev, ddata->resb_gpio, - GPIOF_OUT_INIT_LOW, "lcd RESB"); - if (r) - goto err_gpio; - } - - if (gpio_is_valid(ddata->ini_gpio)) { - r = devm_gpio_request_one(&pdev->dev, ddata->ini_gpio, - GPIOF_OUT_INIT_LOW, "lcd INI"); - if (r) - goto err_gpio; - } - ddata->videomode = sharp_ls_timings; dssdev = &ddata->dssdev; @@ -287,7 +376,6 @@ static int sharp_ls_probe(struct platform_device *pdev) return 0; err_reg: -err_gpio: omap_dss_put_device(ddata->in); return r; } @@ -308,12 +396,20 @@ static int __exit sharp_ls_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id sharp_ls_of_match[] = { + { .compatible = "omapdss,sharp,ls037v7dw01", }, + {}, +}; + +MODULE_DEVICE_TABLE(of, sharp_ls_of_match); + static struct platform_driver sharp_ls_driver = { .probe = sharp_ls_probe, .remove = __exit_p(sharp_ls_remove), .driver = { .name = "panel-sharp-ls037v7dw01", .owner = THIS_MODULE, + .of_match_table = sharp_ls_of_match, }, }; diff --git a/drivers/video/fbdev/omap2/displays-new/panel-tpo-td028ttec1.c b/drivers/video/fbdev/omap2/displays-new/panel-tpo-td028ttec1.c index fae6adc005a..728808bccee 100644 --- a/drivers/video/fbdev/omap2/displays-new/panel-tpo-td028ttec1.c +++ b/drivers/video/fbdev/omap2/displays-new/panel-tpo-td028ttec1.c @@ -206,7 +206,8 @@ static int td028ttec1_panel_enable(struct omap_dss_device *dssdev) if (omapdss_device_is_enabled(dssdev)) return 0; - in->ops.dpi->set_data_lines(in, ddata->data_lines); + if (ddata->data_lines) + in->ops.dpi->set_data_lines(in, ddata->data_lines); in->ops.dpi->set_timings(in, &ddata->videomode); r = in->ops.dpi->enable(in); @@ -389,6 +390,23 @@ static int td028ttec1_panel_probe_pdata(struct spi_device *spi) return 0; } +static int td028ttec1_probe_of(struct spi_device *spi) +{ + struct device_node *node = spi->dev.of_node; + struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev); + struct omap_dss_device *in; + + in = omapdss_of_find_source_for_first_ep(node); + if (IS_ERR(in)) { + dev_err(&spi->dev, "failed to find video source\n"); + return PTR_ERR(in); + } + + ddata->in = in; + + return 0; +} + static int td028ttec1_panel_probe(struct spi_device *spi) { struct panel_drv_data *ddata; @@ -418,6 +436,10 @@ static int td028ttec1_panel_probe(struct spi_device *spi) r = td028ttec1_panel_probe_pdata(spi); if (r) return r; + } else if (spi->dev.of_node) { + r = td028ttec1_probe_of(spi); + if (r) + return r; } else { return -ENODEV; } @@ -463,6 +485,13 @@ static int td028ttec1_panel_remove(struct spi_device *spi) return 0; } +static const struct of_device_id td028ttec1_of_match[] = { + { .compatible = "omapdss,toppoly,td028ttec1", }, + {}, +}; + +MODULE_DEVICE_TABLE(of, td028ttec1_of_match); + static struct spi_driver td028ttec1_spi_driver = { .probe = td028ttec1_panel_probe, .remove = td028ttec1_panel_remove, @@ -470,11 +499,13 @@ static struct spi_driver td028ttec1_spi_driver = { .driver = { .name = "panel-tpo-td028ttec1", .owner = THIS_MODULE, + .of_match_table = td028ttec1_of_match, }, }; module_spi_driver(td028ttec1_spi_driver); +MODULE_ALIAS("spi:toppoly,td028ttec1"); MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>"); MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/video/fbdev/omap2/displays-new/panel-tpo-td043mtea1.c b/drivers/video/fbdev/omap2/displays-new/panel-tpo-td043mtea1.c index 875b40263b3..de78ab0caaa 100644 --- a/drivers/video/fbdev/omap2/displays-new/panel-tpo-td043mtea1.c +++ b/drivers/video/fbdev/omap2/displays-new/panel-tpo-td043mtea1.c @@ -17,6 +17,7 @@ #include <linux/gpio.h> #include <linux/err.h> #include <linux/slab.h> +#include <linux/of_gpio.h> #include <video/omapdss.h> #include <video/omap-panel-data.h> @@ -376,7 +377,8 @@ static int tpo_td043_enable(struct omap_dss_device *dssdev) if (omapdss_device_is_enabled(dssdev)) return 0; - in->ops.dpi->set_data_lines(in, ddata->data_lines); + if (ddata->data_lines) + in->ops.dpi->set_data_lines(in, ddata->data_lines); in->ops.dpi->set_timings(in, &ddata->videomode); r = in->ops.dpi->enable(in); @@ -489,6 +491,31 @@ static int tpo_td043_probe_pdata(struct spi_device *spi) return 0; } +static int tpo_td043_probe_of(struct spi_device *spi) +{ + struct device_node *node = spi->dev.of_node; + struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev); + struct omap_dss_device *in; + int gpio; + + gpio = of_get_named_gpio(node, "reset-gpios", 0); + if (!gpio_is_valid(gpio)) { + dev_err(&spi->dev, "failed to parse enable gpio\n"); + return gpio; + } + ddata->nreset_gpio = gpio; + + in = omapdss_of_find_source_for_first_ep(node); + if (IS_ERR(in)) { + dev_err(&spi->dev, "failed to find video source\n"); + return PTR_ERR(in); + } + + ddata->in = in; + + return 0; +} + static int tpo_td043_probe(struct spi_device *spi) { struct panel_drv_data *ddata; @@ -518,6 +545,10 @@ static int tpo_td043_probe(struct spi_device *spi) r = tpo_td043_probe_pdata(spi); if (r) return r; + } else if (spi->dev.of_node) { + r = tpo_td043_probe_of(spi); + if (r) + return r; } else { return -ENODEV; } @@ -629,11 +660,19 @@ static int tpo_td043_spi_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(tpo_td043_spi_pm, tpo_td043_spi_suspend, tpo_td043_spi_resume); +static const struct of_device_id tpo_td043_of_match[] = { + { .compatible = "omapdss,tpo,td043mtea1", }, + {}, +}; + +MODULE_DEVICE_TABLE(of, tpo_td043_of_match); + static struct spi_driver tpo_td043_spi_driver = { .driver = { .name = "panel-tpo-td043mtea1", .owner = THIS_MODULE, .pm = &tpo_td043_spi_pm, + .of_match_table = tpo_td043_of_match, }, .probe = tpo_td043_probe, .remove = tpo_td043_remove, @@ -641,6 +680,7 @@ static struct spi_driver tpo_td043_spi_driver = { module_spi_driver(tpo_td043_spi_driver); +MODULE_ALIAS("spi:tpo,td043mtea1"); MODULE_AUTHOR("Gražvydas Ignotas <notasas@gmail.com>"); MODULE_DESCRIPTION("TPO TD043MTEA1 LCD Driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/video/fbdev/omap2/dss/Kconfig b/drivers/video/fbdev/omap2/dss/Kconfig index dde4281663b..285bcd103dc 100644 --- a/drivers/video/fbdev/omap2/dss/Kconfig +++ b/drivers/video/fbdev/omap2/dss/Kconfig @@ -1,6 +1,10 @@ +config OMAP2_DSS_INIT + bool + menuconfig OMAP2_DSS tristate "OMAP2+ Display Subsystem support" select VIDEOMODE_HELPERS + select OMAP2_DSS_INIT help OMAP2+ Display Subsystem support. @@ -59,16 +63,32 @@ config OMAP2_DSS_VENC help OMAP Video Encoder support for S-Video and composite TV-out. +config OMAP2_DSS_HDMI_COMMON + bool + config OMAP4_DSS_HDMI - bool "HDMI support" + bool "HDMI support for OMAP4" default y + select OMAP2_DSS_HDMI_COMMON help - HDMI Interface. This adds the High Definition Multimedia Interface. - See http://www.hdmi.org/ for HDMI specification. + HDMI support for OMAP4 based SoCs. config OMAP4_DSS_HDMI_AUDIO bool +config OMAP5_DSS_HDMI + bool "HDMI support for OMAP5" + default n + select OMAP2_DSS_HDMI_COMMON + help + HDMI Interface for OMAP5 and similar cores. This adds the High + Definition Multimedia Interface. See http://www.hdmi.org/ for HDMI + specification. + +config OMAP5_DSS_HDMI_AUDIO + depends on OMAP5_DSS_HDMI + bool + config OMAP2_DSS_SDI bool "SDI support" default n diff --git a/drivers/video/fbdev/omap2/dss/Makefile b/drivers/video/fbdev/omap2/dss/Makefile index 8aec8bda27c..245f933060e 100644 --- a/drivers/video/fbdev/omap2/dss/Makefile +++ b/drivers/video/fbdev/omap2/dss/Makefile @@ -1,3 +1,4 @@ +obj-$(CONFIG_OMAP2_DSS_INIT) += omapdss-boot-init.o obj-$(CONFIG_OMAP2_DSS) += omapdss.o # Core DSS files omapdss-y := core.o dss.o dss_features.o dispc.o dispc_coefs.o display.o \ @@ -10,6 +11,8 @@ omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o -omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi4.o hdmi_common.o hdmi_wp.o hdmi_pll.o \ - hdmi_phy.o hdmi4_core.o +omapdss-$(CONFIG_OMAP2_DSS_HDMI_COMMON) += hdmi_common.o hdmi_wp.o hdmi_pll.o \ + hdmi_phy.o +omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi4.o hdmi4_core.o +omapdss-$(CONFIG_OMAP5_DSS_HDMI) += hdmi5.o hdmi5_core.o ccflags-$(CONFIG_OMAP2_DSS_DEBUG) += -DDEBUG diff --git a/drivers/video/fbdev/omap2/dss/core.c b/drivers/video/fbdev/omap2/dss/core.c index ffa45c894cd..6b74f73fb52 100644 --- a/drivers/video/fbdev/omap2/dss/core.c +++ b/drivers/video/fbdev/omap2/dss/core.c @@ -268,6 +268,9 @@ static int (*dss_output_drv_reg_funcs[])(void) __initdata = { #ifdef CONFIG_OMAP4_DSS_HDMI hdmi4_init_platform_driver, #endif +#ifdef CONFIG_OMAP5_DSS_HDMI + hdmi5_init_platform_driver, +#endif }; static void (*dss_output_drv_unreg_funcs[])(void) __exitdata = { @@ -289,6 +292,9 @@ static void (*dss_output_drv_unreg_funcs[])(void) __exitdata = { #ifdef CONFIG_OMAP4_DSS_HDMI hdmi4_uninit_platform_driver, #endif +#ifdef CONFIG_OMAP5_DSS_HDMI + hdmi5_uninit_platform_driver, +#endif }; static bool dss_output_drv_loaded[ARRAY_SIZE(dss_output_drv_reg_funcs)]; diff --git a/drivers/video/fbdev/omap2/dss/dispc.c b/drivers/video/fbdev/omap2/dss/dispc.c index f18397c33e8..7aa33b0f4a1 100644 --- a/drivers/video/fbdev/omap2/dss/dispc.c +++ b/drivers/video/fbdev/omap2/dss/dispc.c @@ -2577,9 +2577,9 @@ int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, channel = dispc_ovl_get_channel_out(plane); - DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> " - "%dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n", - plane, oi->paddr, oi->p_uv_addr, oi->screen_width, oi->pos_x, + DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->" + " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n", + plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height, oi->color_mode, oi->rotation, oi->mirror, channel, replication); @@ -2945,13 +2945,13 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, BUG(); } - l = dispc_read_reg(DISPC_POL_FREQ(channel)); - l |= FLD_VAL(onoff, 17, 17); - l |= FLD_VAL(rf, 16, 16); - l |= FLD_VAL(de_level, 15, 15); - l |= FLD_VAL(ipc, 14, 14); - l |= FLD_VAL(hsync_level, 13, 13); - l |= FLD_VAL(vsync_level, 12, 12); + l = FLD_VAL(onoff, 17, 17) | + FLD_VAL(rf, 16, 16) | + FLD_VAL(de_level, 15, 15) | + FLD_VAL(ipc, 14, 14) | + FLD_VAL(hsync_level, 13, 13) | + FLD_VAL(vsync_level, 12, 12); + dispc_write_reg(DISPC_POL_FREQ(channel), l); } @@ -3656,6 +3656,7 @@ static int __init dispc_init_features(struct platform_device *pdev) case OMAPDSS_VER_OMAP34xx_ES3: case OMAPDSS_VER_OMAP3630: case OMAPDSS_VER_AM35xx: + case OMAPDSS_VER_AM43xx: src = &omap34xx_rev3_0_dispc_feats; break; @@ -3829,6 +3830,7 @@ static const struct of_device_id dispc_of_match[] = { { .compatible = "ti,omap2-dispc", }, { .compatible = "ti,omap3-dispc", }, { .compatible = "ti,omap4-dispc", }, + { .compatible = "ti,omap5-dispc", }, {}, }; diff --git a/drivers/video/fbdev/omap2/dss/dpi.c b/drivers/video/fbdev/omap2/dss/dpi.c index 157921db447..9368972d696 100644 --- a/drivers/video/fbdev/omap2/dss/dpi.c +++ b/drivers/video/fbdev/omap2/dss/dpi.c @@ -67,6 +67,7 @@ static struct platform_device *dpi_get_dsidev(enum omap_channel channel) case OMAPDSS_VER_OMAP34xx_ES3: case OMAPDSS_VER_OMAP3630: case OMAPDSS_VER_AM35xx: + case OMAPDSS_VER_AM43xx: return NULL; case OMAPDSS_VER_OMAP4430_ES1: @@ -103,6 +104,8 @@ static enum omap_dss_clk_source dpi_get_alt_clk_src(enum omap_channel channel) return OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC; case OMAP_DSS_CHANNEL_LCD2: return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC; + case OMAP_DSS_CHANNEL_LCD3: + return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC; default: /* this shouldn't happen */ WARN_ON(1); @@ -595,6 +598,7 @@ static enum omap_channel dpi_get_channel(void) case OMAPDSS_VER_OMAP34xx_ES3: case OMAPDSS_VER_OMAP3630: case OMAPDSS_VER_AM35xx: + case OMAPDSS_VER_AM43xx: return OMAP_DSS_CHANNEL_LCD; case OMAPDSS_VER_OMAP4430_ES1: diff --git a/drivers/video/fbdev/omap2/dss/dsi.c b/drivers/video/fbdev/omap2/dss/dsi.c index 8be9b04d884..4755a34a542 100644 --- a/drivers/video/fbdev/omap2/dss/dsi.c +++ b/drivers/video/fbdev/omap2/dss/dsi.c @@ -1161,6 +1161,7 @@ static int dsi_regulator_init(struct platform_device *dsidev) { struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); struct regulator *vdds_dsi; + int r; if (dsi->vdds_dsi_reg != NULL) return 0; @@ -1173,6 +1174,15 @@ static int dsi_regulator_init(struct platform_device *dsidev) return PTR_ERR(vdds_dsi); } + if (regulator_can_change_voltage(vdds_dsi)) { + r = regulator_set_voltage(vdds_dsi, 1800000, 1800000); + if (r) { + devm_regulator_put(vdds_dsi); + DSSERR("can't set the DSI regulator voltage\n"); + return r; + } + } + dsi->vdds_dsi_reg = vdds_dsi; return 0; @@ -5122,6 +5132,7 @@ static enum omap_channel dsi_get_channel(int module_id) { switch (omapdss_get_version()) { case OMAPDSS_VER_OMAP24xx: + case OMAPDSS_VER_AM43xx: DSSWARN("DSI not supported\n"); return OMAP_DSS_CHANNEL_LCD; @@ -5723,9 +5734,16 @@ static const struct dsi_module_id_data dsi_of_data_omap4[] = { { }, }; +static const struct dsi_module_id_data dsi_of_data_omap5[] = { + { .address = 0x58004000, .id = 0, }, + { .address = 0x58009000, .id = 1, }, + { }, +}; + static const struct of_device_id dsi_of_match[] = { { .compatible = "ti,omap3-dsi", .data = dsi_of_data_omap3, }, { .compatible = "ti,omap4-dsi", .data = dsi_of_data_omap4, }, + { .compatible = "ti,omap5-dsi", .data = dsi_of_data_omap5, }, {}, }; diff --git a/drivers/video/fbdev/omap2/dss/dss.c b/drivers/video/fbdev/omap2/dss/dss.c index d55266c0e02..6daeb7ed44c 100644 --- a/drivers/video/fbdev/omap2/dss/dss.c +++ b/drivers/video/fbdev/omap2/dss/dss.c @@ -728,6 +728,13 @@ static const struct dss_features omap54xx_dss_feats __initconst = { .dpi_select_source = &dss_dpi_select_source_omap5, }; +static const struct dss_features am43xx_dss_feats __initconst = { + .fck_div_max = 0, + .dss_fck_multiplier = 0, + .parent_clk_name = NULL, + .dpi_select_source = &dss_dpi_select_source_omap2_omap3, +}; + static int __init dss_init_features(struct platform_device *pdev) { const struct dss_features *src; @@ -764,6 +771,10 @@ static int __init dss_init_features(struct platform_device *pdev) src = &omap54xx_dss_feats; break; + case OMAPDSS_VER_AM43xx: + src = &am43xx_dss_feats; + break; + default: return -ENODEV; } @@ -784,12 +795,8 @@ static int __init dss_init_ports(struct platform_device *pdev) return 0; port = omapdss_of_get_next_port(parent, NULL); - if (!port) { -#ifdef CONFIG_OMAP2_DSS_DPI - dpi_init_port(pdev, parent); -#endif + if (!port) return 0; - } do { u32 reg; @@ -813,7 +820,7 @@ static int __init dss_init_ports(struct platform_device *pdev) return 0; } -static void dss_uninit_ports(void) +static void __exit dss_uninit_ports(void) { #ifdef CONFIG_OMAP2_DSS_DPI dpi_uninit_port(); @@ -946,6 +953,7 @@ static const struct of_device_id dss_of_match[] = { { .compatible = "ti,omap2-dss", }, { .compatible = "ti,omap3-dss", }, { .compatible = "ti,omap4-dss", }, + { .compatible = "ti,omap5-dss", }, {}, }; diff --git a/drivers/video/fbdev/omap2/dss/dss.h b/drivers/video/fbdev/omap2/dss/dss.h index 560078fcb19..8ff22c134c6 100644 --- a/drivers/video/fbdev/omap2/dss/dss.h +++ b/drivers/video/fbdev/omap2/dss/dss.h @@ -419,6 +419,9 @@ void venc_uninit_platform_driver(void) __exit; int hdmi4_init_platform_driver(void) __init; void hdmi4_uninit_platform_driver(void) __exit; +int hdmi5_init_platform_driver(void) __init; +void hdmi5_uninit_platform_driver(void) __exit; + /* RFBI */ int rfbi_init_platform_driver(void) __init; void rfbi_uninit_platform_driver(void) __exit; diff --git a/drivers/video/fbdev/omap2/dss/dss_features.c b/drivers/video/fbdev/omap2/dss/dss_features.c index 7f8969191dc..15088df7bd1 100644 --- a/drivers/video/fbdev/omap2/dss/dss_features.c +++ b/drivers/video/fbdev/omap2/dss/dss_features.c @@ -93,6 +93,17 @@ static const struct dss_reg_field omap3_dss_reg_fields[] = { [FEAT_REG_DSIPLL_REGM_DSI] = { 26, 23 }, }; +static const struct dss_reg_field am43xx_dss_reg_fields[] = { + [FEAT_REG_FIRHINC] = { 12, 0 }, + [FEAT_REG_FIRVINC] = { 28, 16 }, + [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 }, + [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 }, + [FEAT_REG_FIFOSIZE] = { 10, 0 }, + [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, + [FEAT_REG_VERTICALACCU] = { 25, 16 }, + [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 }, +}; + static const struct dss_reg_field omap4_dss_reg_fields[] = { [FEAT_REG_FIRHINC] = { 12, 0 }, [FEAT_REG_FIRVINC] = { 28, 16 }, @@ -149,6 +160,11 @@ static const enum omap_display_type omap3630_dss_supported_displays[] = { OMAP_DISPLAY_TYPE_VENC, }; +static const enum omap_display_type am43xx_dss_supported_displays[] = { + /* OMAP_DSS_CHANNEL_LCD */ + OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI, +}; + static const enum omap_display_type omap4_dss_supported_displays[] = { /* OMAP_DSS_CHANNEL_LCD */ OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI, @@ -200,6 +216,11 @@ static const enum omap_dss_output_id omap3630_dss_supported_outputs[] = { OMAP_DSS_OUTPUT_VENC, }; +static const enum omap_dss_output_id am43xx_dss_supported_outputs[] = { + /* OMAP_DSS_CHANNEL_LCD */ + OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI, +}; + static const enum omap_dss_output_id omap4_dss_supported_outputs[] = { /* OMAP_DSS_CHANNEL_LCD */ OMAP_DSS_OUTPUT_DBI | OMAP_DSS_OUTPUT_DSI1, @@ -444,6 +465,13 @@ static const struct dss_param_range omap3_dss_param_range[] = { [FEAT_PARAM_LINEWIDTH] = { 1, 1024 }, }; +static const struct dss_param_range am43xx_dss_param_range[] = { + [FEAT_PARAM_DSS_FCK] = { 0, 200000000 }, + [FEAT_PARAM_DSS_PCD] = { 2, 255 }, + [FEAT_PARAM_DOWNSCALE] = { 1, 4 }, + [FEAT_PARAM_LINEWIDTH] = { 1, 1024 }, +}; + static const struct dss_param_range omap4_dss_param_range[] = { [FEAT_PARAM_DSS_FCK] = { 0, 186000000 }, [FEAT_PARAM_DSS_PCD] = { 1, 255 }, @@ -520,6 +548,21 @@ static const enum dss_feat_id am35xx_dss_feat_list[] = { FEAT_OMAP3_DSI_FIFO_BUG, }; +static const enum dss_feat_id am43xx_dss_feat_list[] = { + FEAT_LCDENABLEPOL, + FEAT_LCDENABLESIGNAL, + FEAT_PCKFREEENABLE, + FEAT_FUNCGATED, + FEAT_LINEBUFFERSPLIT, + FEAT_ROWREPEATENABLE, + FEAT_RESIZECONF, + FEAT_CPR, + FEAT_PRELOAD, + FEAT_FIR_COEF_V, + FEAT_ALPHA_FIXED_ZORDER, + FEAT_FIFO_MERGE, +}; + static const enum dss_feat_id omap3630_dss_feat_list[] = { FEAT_LCDENABLEPOL, FEAT_LCDENABLESIGNAL, @@ -595,6 +638,7 @@ static const enum dss_feat_id omap4_dss_feat_list[] = { static const enum dss_feat_id omap5_dss_feat_list[] = { FEAT_MGR_LCD2, + FEAT_MGR_LCD3, FEAT_CORE_CLK_DIV, FEAT_LCD_CLK_SRC, FEAT_DSI_DCS_CMD_CONFIG_VC, @@ -682,6 +726,26 @@ static const struct omap_dss_features am35xx_dss_features = { .burst_size_unit = 8, }; +static const struct omap_dss_features am43xx_dss_features = { + .reg_fields = am43xx_dss_reg_fields, + .num_reg_fields = ARRAY_SIZE(am43xx_dss_reg_fields), + + .features = am43xx_dss_feat_list, + .num_features = ARRAY_SIZE(am43xx_dss_feat_list), + + .num_mgrs = 1, + .num_ovls = 3, + .supported_displays = am43xx_dss_supported_displays, + .supported_outputs = am43xx_dss_supported_outputs, + .supported_color_modes = omap3_dss_supported_color_modes, + .overlay_caps = omap3430_dss_overlay_caps, + .clksrc_names = omap2_dss_clk_source_names, + .dss_params = am43xx_dss_param_range, + .supported_rotation_types = OMAP_DSS_ROT_DMA, + .buffer_size_unit = 1, + .burst_size_unit = 8, +}; + static const struct omap_dss_features omap3630_dss_features = { .reg_fields = omap3_dss_reg_fields, .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields), @@ -777,7 +841,7 @@ static const struct omap_dss_features omap5_dss_features = { .features = omap5_dss_feat_list, .num_features = ARRAY_SIZE(omap5_dss_feat_list), - .num_mgrs = 3, + .num_mgrs = 4, .num_ovls = 4, .supported_displays = omap5_dss_supported_displays, .supported_outputs = omap5_dss_supported_outputs, @@ -928,6 +992,10 @@ void dss_features_init(enum omapdss_version version) omap_current_dss_features = &am35xx_dss_features; break; + case OMAPDSS_VER_AM43xx: + omap_current_dss_features = &am43xx_dss_features; + break; + default: DSSWARN("Unsupported OMAP version"); break; diff --git a/drivers/video/fbdev/omap2/dss/hdmi.h b/drivers/video/fbdev/omap2/dss/hdmi.h index e25681ff5a7..fbee0781633 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi.h +++ b/drivers/video/fbdev/omap2/dss/hdmi.h @@ -80,6 +80,7 @@ #define HDMI_TXPHY_DIGITAL_CTRL 0x4 #define HDMI_TXPHY_POWER_CTRL 0x8 #define HDMI_TXPHY_PAD_CFG_CTRL 0xC +#define HDMI_TXPHY_BIST_CONTROL 0x1C enum hdmi_pll_pwr { HDMI_PLLPWRCMD_ALLOFF = 0, @@ -351,7 +352,8 @@ struct hdmi_pll_data { struct hdmi_phy_data { void __iomem *base; - int irq; + u8 lane_function[4]; + u8 lane_polarity[4]; }; struct hdmi_core_data { @@ -360,13 +362,13 @@ struct hdmi_core_data { struct hdmi_core_infoframe_avi avi_cfg; }; -static inline void hdmi_write_reg(void __iomem *base_addr, const u16 idx, +static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx, u32 val) { __raw_writel(val, base_addr + idx); } -static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx) +static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx) { return __raw_readl(base_addr + idx); } @@ -417,18 +419,19 @@ void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy); int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll); /* HDMI PHY funcs */ -int hdmi_phy_enable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp, - struct hdmi_config *cfg); -void hdmi_phy_disable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp); +int hdmi_phy_configure(struct hdmi_phy_data *phy, struct hdmi_config *cfg); void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s); int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy); +int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes); /* HDMI common funcs */ const struct hdmi_config *hdmi_default_timing(void); const struct hdmi_config *hdmi_get_timings(int mode, int code); struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing); +int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep, + struct hdmi_phy_data *phy); -#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) +#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || defined(CONFIG_OMAP5_DSS_HDMI_AUDIO) int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts); int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable); int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable); diff --git a/drivers/video/fbdev/omap2/dss/hdmi4.c b/drivers/video/fbdev/omap2/dss/hdmi4.c index f5f7944a1fd..626aad2bef4 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi4.c +++ b/drivers/video/fbdev/omap2/dss/hdmi4.c @@ -81,8 +81,40 @@ static void hdmi_runtime_put(void) WARN_ON(r < 0 && r != -ENOSYS); } +static irqreturn_t hdmi_irq_handler(int irq, void *data) +{ + struct hdmi_wp_data *wp = data; + u32 irqstatus; + + irqstatus = hdmi_wp_get_irqstatus(wp); + hdmi_wp_set_irqstatus(wp, irqstatus); + + if ((irqstatus & HDMI_IRQ_LINK_CONNECT) && + irqstatus & HDMI_IRQ_LINK_DISCONNECT) { + /* + * If we get both connect and disconnect interrupts at the same + * time, turn off the PHY, clear interrupts, and restart, which + * raises connect interrupt if a cable is connected, or nothing + * if cable is not connected. + */ + hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); + + hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | + HDMI_IRQ_LINK_DISCONNECT); + + hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); + } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) { + hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); + } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) { + hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); + } + + return IRQ_HANDLED; +} + static int hdmi_init_regulator(void) { + int r; struct regulator *reg; if (hdmi.vdda_hdmi_dac_reg != NULL) @@ -96,6 +128,15 @@ static int hdmi_init_regulator(void) return PTR_ERR(reg); } + if (regulator_can_change_voltage(reg)) { + r = regulator_set_voltage(reg, 1800000, 1800000); + if (r) { + devm_regulator_put(reg); + DSSWARN("can't set the regulator voltage\n"); + return r; + } + } + hdmi.vdda_hdmi_dac_reg = reg; return 0; @@ -140,11 +181,16 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev) struct omap_video_timings *p; struct omap_overlay_manager *mgr = hdmi.output.manager; unsigned long phy; + struct hdmi_wp_data *wp = &hdmi.wp; r = hdmi_power_on_core(dssdev); if (r) return r; + /* disable and clear irqs */ + hdmi_wp_clear_irqenable(wp, 0xffffffff); + hdmi_wp_set_irqstatus(wp, 0xffffffff); + p = &hdmi.cfg.timings; DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); @@ -161,12 +207,16 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev) goto err_pll_enable; } - r = hdmi_phy_enable(&hdmi.phy, &hdmi.wp, &hdmi.cfg); + r = hdmi_phy_configure(&hdmi.phy, &hdmi.cfg); if (r) { - DSSDBG("Failed to start PHY\n"); - goto err_phy_enable; + DSSDBG("Failed to configure PHY\n"); + goto err_phy_cfg; } + r = hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); + if (r) + goto err_phy_pwr; + hdmi4_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg); /* bypass TV gamma table */ @@ -183,13 +233,17 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev) if (r) goto err_mgr_enable; + hdmi_wp_set_irqenable(wp, + HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT); + return 0; err_mgr_enable: hdmi_wp_video_stop(&hdmi.wp); err_vid_enable: - hdmi_phy_disable(&hdmi.phy, &hdmi.wp); -err_phy_enable: +err_phy_cfg: + hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); +err_phy_pwr: hdmi_pll_disable(&hdmi.pll, &hdmi.wp); err_pll_enable: hdmi_power_off_core(dssdev); @@ -200,10 +254,14 @@ static void hdmi_power_off_full(struct omap_dss_device *dssdev) { struct omap_overlay_manager *mgr = hdmi.output.manager; + hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); + dss_mgr_disable(mgr); hdmi_wp_video_stop(&hdmi.wp); - hdmi_phy_disable(&hdmi.phy, &hdmi.wp); + + hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); + hdmi_pll_disable(&hdmi.pll, &hdmi.wp); hdmi_power_off_core(dssdev); @@ -600,15 +658,44 @@ static void __exit hdmi_uninit_output(struct platform_device *pdev) omapdss_unregister_output(out); } +static int hdmi_probe_of(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct device_node *ep; + int r; + + ep = omapdss_of_get_first_endpoint(node); + if (!ep) + return 0; + + r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy); + if (r) + goto err; + + of_node_put(ep); + return 0; + +err: + of_node_put(ep); + return r; +} + /* HDMI HW IP initialisation */ static int omapdss_hdmihw_probe(struct platform_device *pdev) { int r; + int irq; hdmi.pdev = pdev; mutex_init(&hdmi.lock); + if (pdev->dev.of_node) { + r = hdmi_probe_of(pdev); + if (r) + return r; + } + r = hdmi_wp_init(pdev, &hdmi.wp); if (r) return r; @@ -631,6 +718,20 @@ static int omapdss_hdmihw_probe(struct platform_device *pdev) return r; } + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + DSSERR("platform_get_irq failed\n"); + return -ENODEV; + } + + r = devm_request_threaded_irq(&pdev->dev, irq, + NULL, hdmi_irq_handler, + IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp); + if (r) { + DSSERR("HDMI IRQ request failed\n"); + return r; + } + pm_runtime_enable(&pdev->dev); hdmi_init_output(pdev); diff --git a/drivers/video/fbdev/omap2/dss/hdmi4_core.c b/drivers/video/fbdev/omap2/dss/hdmi4_core.c index 2eb04dcf807..8bde7b7e95f 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi4_core.c +++ b/drivers/video/fbdev/omap2/dss/hdmi4_core.c @@ -998,38 +998,20 @@ int hdmi4_audio_get_dma_port(u32 *offset, u32 *size) #endif -#define CORE_OFFSET 0x400 -#define CORE_SIZE 0xc00 - int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core) { struct resource *res; - struct resource temp_res; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); if (!res) { - DSSDBG("can't get CORE mem resource by name\n"); - /* - * if hwmod/DT doesn't have the memory resource information - * split into HDMI sub blocks by name, we try again by getting - * the platform's first resource. this code will be removed when - * the driver can get the mem resources by name - */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - DSSERR("can't get CORE mem resource\n"); - return -EINVAL; - } - - temp_res.start = res->start + CORE_OFFSET; - temp_res.end = temp_res.start + CORE_SIZE - 1; - res = &temp_res; + DSSERR("can't get CORE mem resource\n"); + return -EINVAL; } - core->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); - if (!core->base) { + core->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(core->base)) { DSSERR("can't ioremap CORE\n"); - return -ENOMEM; + return PTR_ERR(core->base); } return 0; diff --git a/drivers/video/fbdev/omap2/dss/hdmi5.c b/drivers/video/fbdev/omap2/dss/hdmi5.c new file mode 100644 index 00000000000..c468b9e1f29 --- /dev/null +++ b/drivers/video/fbdev/omap2/dss/hdmi5.c @@ -0,0 +1,829 @@ +/* + * HDMI driver for OMAP5 + * + * Copyright (C) 2014 Texas Instruments Incorporated + * + * Authors: + * Yong Zhi + * Mythri pk + * Archit Taneja <archit@ti.com> + * Tomi Valkeinen <tomi.valkeinen@ti.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#define DSS_SUBSYS_NAME "HDMI" + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/interrupt.h> +#include <linux/mutex.h> +#include <linux/delay.h> +#include <linux/string.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/clk.h> +#include <linux/gpio.h> +#include <linux/regulator/consumer.h> +#include <video/omapdss.h> + +#include "hdmi5_core.h" +#include "dss.h" +#include "dss_features.h" + +static struct { + struct mutex lock; + struct platform_device *pdev; + + struct hdmi_wp_data wp; + struct hdmi_pll_data pll; + struct hdmi_phy_data phy; + struct hdmi_core_data core; + + struct hdmi_config cfg; + + struct clk *sys_clk; + struct regulator *vdda_reg; + + bool core_enabled; + + struct omap_dss_device output; +} hdmi; + +static int hdmi_runtime_get(void) +{ + int r; + + DSSDBG("hdmi_runtime_get\n"); + + r = pm_runtime_get_sync(&hdmi.pdev->dev); + WARN_ON(r < 0); + if (r < 0) + return r; + + return 0; +} + +static void hdmi_runtime_put(void) +{ + int r; + + DSSDBG("hdmi_runtime_put\n"); + + r = pm_runtime_put_sync(&hdmi.pdev->dev); + WARN_ON(r < 0 && r != -ENOSYS); +} + +static irqreturn_t hdmi_irq_handler(int irq, void *data) +{ + struct hdmi_wp_data *wp = data; + u32 irqstatus; + + irqstatus = hdmi_wp_get_irqstatus(wp); + hdmi_wp_set_irqstatus(wp, irqstatus); + + if ((irqstatus & HDMI_IRQ_LINK_CONNECT) && + irqstatus & HDMI_IRQ_LINK_DISCONNECT) { + u32 v; + /* + * If we get both connect and disconnect interrupts at the same + * time, turn off the PHY, clear interrupts, and restart, which + * raises connect interrupt if a cable is connected, or nothing + * if cable is not connected. + */ + + hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); + + /* + * We always get bogus CONNECT & DISCONNECT interrupts when + * setting the PHY to LDOON. To ignore those, we force the RXDET + * line to 0 until the PHY power state has been changed. + */ + v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL); + v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */ + v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */ + hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v); + + hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | + HDMI_IRQ_LINK_DISCONNECT); + + hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); + + REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); + + } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) { + hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); + } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) { + hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); + } + + return IRQ_HANDLED; +} + +static int hdmi_init_regulator(void) +{ + int r; + struct regulator *reg; + + if (hdmi.vdda_reg != NULL) + return 0; + + reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); + if (IS_ERR(reg)) { + DSSERR("can't get VDDA regulator\n"); + return PTR_ERR(reg); + } + + if (regulator_can_change_voltage(reg)) { + r = regulator_set_voltage(reg, 1800000, 1800000); + if (r) { + devm_regulator_put(reg); + DSSWARN("can't set the regulator voltage\n"); + return r; + } + } + + hdmi.vdda_reg = reg; + + return 0; +} + +static int hdmi_power_on_core(struct omap_dss_device *dssdev) +{ + int r; + + r = regulator_enable(hdmi.vdda_reg); + if (r) + return r; + + r = hdmi_runtime_get(); + if (r) + goto err_runtime_get; + + /* Make selection of HDMI in DSS */ + dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); + + hdmi.core_enabled = true; + + return 0; + +err_runtime_get: + regulator_disable(hdmi.vdda_reg); + + return r; +} + +static void hdmi_power_off_core(struct omap_dss_device *dssdev) +{ + hdmi.core_enabled = false; + + hdmi_runtime_put(); + regulator_disable(hdmi.vdda_reg); +} + +static int hdmi_power_on_full(struct omap_dss_device *dssdev) +{ + int r; + struct omap_video_timings *p; + struct omap_overlay_manager *mgr = hdmi.output.manager; + unsigned long phy; + + r = hdmi_power_on_core(dssdev); + if (r) + return r; + + p = &hdmi.cfg.timings; + + DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); + + /* the functions below use kHz pixel clock. TODO: change to Hz */ + phy = p->pixelclock / 1000; + + hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), phy); + + /* disable and clear irqs */ + hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); + hdmi_wp_set_irqstatus(&hdmi.wp, + hdmi_wp_get_irqstatus(&hdmi.wp)); + + /* config the PLL and PHY hdmi_set_pll_pwrfirst */ + r = hdmi_pll_enable(&hdmi.pll, &hdmi.wp); + if (r) { + DSSDBG("Failed to lock PLL\n"); + goto err_pll_enable; + } + + r = hdmi_phy_configure(&hdmi.phy, &hdmi.cfg); + if (r) { + DSSDBG("Failed to start PHY\n"); + goto err_phy_cfg; + } + + r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON); + if (r) + goto err_phy_pwr; + + hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg); + + /* bypass TV gamma table */ + dispc_enable_gamma_table(0); + + /* tv size */ + dss_mgr_set_timings(mgr, p); + + r = hdmi_wp_video_start(&hdmi.wp); + if (r) + goto err_vid_enable; + + r = dss_mgr_enable(mgr); + if (r) + goto err_mgr_enable; + + hdmi_wp_set_irqenable(&hdmi.wp, + HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT); + + return 0; + +err_mgr_enable: + hdmi_wp_video_stop(&hdmi.wp); +err_vid_enable: + hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); +err_phy_pwr: +err_phy_cfg: + hdmi_pll_disable(&hdmi.pll, &hdmi.wp); +err_pll_enable: + hdmi_power_off_core(dssdev); + return -EIO; +} + +static void hdmi_power_off_full(struct omap_dss_device *dssdev) +{ + struct omap_overlay_manager *mgr = hdmi.output.manager; + + hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); + + dss_mgr_disable(mgr); + + hdmi_wp_video_stop(&hdmi.wp); + + hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); + + hdmi_pll_disable(&hdmi.pll, &hdmi.wp); + + hdmi_power_off_core(dssdev); +} + +static int hdmi_display_check_timing(struct omap_dss_device *dssdev, + struct omap_video_timings *timings) +{ + struct omap_dss_device *out = &hdmi.output; + + if (!dispc_mgr_timings_ok(out->dispc_channel, timings)) + return -EINVAL; + + return 0; +} + +static void hdmi_display_set_timing(struct omap_dss_device *dssdev, + struct omap_video_timings *timings) +{ + struct hdmi_cm cm; + const struct hdmi_config *t; + + mutex_lock(&hdmi.lock); + + cm = hdmi_get_code(timings); + hdmi.cfg.cm = cm; + + t = hdmi_get_timings(cm.mode, cm.code); + if (t != NULL) { + hdmi.cfg = *t; + + dispc_set_tv_pclk(t->timings.pixelclock); + } else { + hdmi.cfg.timings = *timings; + hdmi.cfg.cm.code = 0; + hdmi.cfg.cm.mode = HDMI_DVI; + + dispc_set_tv_pclk(timings->pixelclock); + } + + DSSDBG("using mode: %s, code %d\n", hdmi.cfg.cm.mode == HDMI_DVI ? + "DVI" : "HDMI", hdmi.cfg.cm.code); + + mutex_unlock(&hdmi.lock); +} + +static void hdmi_display_get_timings(struct omap_dss_device *dssdev, + struct omap_video_timings *timings) +{ + const struct hdmi_config *cfg; + struct hdmi_cm cm = hdmi.cfg.cm; + + cfg = hdmi_get_timings(cm.mode, cm.code); + if (cfg == NULL) + cfg = hdmi_default_timing(); + + memcpy(timings, &cfg->timings, sizeof(cfg->timings)); +} + +static void hdmi_dump_regs(struct seq_file *s) +{ + mutex_lock(&hdmi.lock); + + if (hdmi_runtime_get()) { + mutex_unlock(&hdmi.lock); + return; + } + + hdmi_wp_dump(&hdmi.wp, s); + hdmi_pll_dump(&hdmi.pll, s); + hdmi_phy_dump(&hdmi.phy, s); + hdmi5_core_dump(&hdmi.core, s); + + hdmi_runtime_put(); + mutex_unlock(&hdmi.lock); +} + +static int read_edid(u8 *buf, int len) +{ + int r; + int idlemode; + + mutex_lock(&hdmi.lock); + + r = hdmi_runtime_get(); + BUG_ON(r); + + idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2); + /* No-idle mode */ + REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); + + r = hdmi5_read_edid(&hdmi.core, buf, len); + + REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2); + + hdmi_runtime_put(); + mutex_unlock(&hdmi.lock); + + return r; +} + +static int hdmi_display_enable(struct omap_dss_device *dssdev) +{ + struct omap_dss_device *out = &hdmi.output; + int r = 0; + + DSSDBG("ENTER hdmi_display_enable\n"); + + mutex_lock(&hdmi.lock); + + if (out == NULL || out->manager == NULL) { + DSSERR("failed to enable display: no output/manager\n"); + r = -ENODEV; + goto err0; + } + + r = hdmi_power_on_full(dssdev); + if (r) { + DSSERR("failed to power on device\n"); + goto err0; + } + + mutex_unlock(&hdmi.lock); + return 0; + +err0: + mutex_unlock(&hdmi.lock); + return r; +} + +static void hdmi_display_disable(struct omap_dss_device *dssdev) +{ + DSSDBG("Enter hdmi_display_disable\n"); + + mutex_lock(&hdmi.lock); + + hdmi_power_off_full(dssdev); + + mutex_unlock(&hdmi.lock); +} + +static int hdmi_core_enable(struct omap_dss_device *dssdev) +{ + int r = 0; + + DSSDBG("ENTER omapdss_hdmi_core_enable\n"); + + mutex_lock(&hdmi.lock); + + r = hdmi_power_on_core(dssdev); + if (r) { + DSSERR("failed to power on device\n"); + goto err0; + } + + mutex_unlock(&hdmi.lock); + return 0; + +err0: + mutex_unlock(&hdmi.lock); + return r; +} + +static void hdmi_core_disable(struct omap_dss_device *dssdev) +{ + DSSDBG("Enter omapdss_hdmi_core_disable\n"); + + mutex_lock(&hdmi.lock); + + hdmi_power_off_core(dssdev); + + mutex_unlock(&hdmi.lock); +} + +static int hdmi_get_clocks(struct platform_device *pdev) +{ + struct clk *clk; + + clk = devm_clk_get(&pdev->dev, "sys_clk"); + if (IS_ERR(clk)) { + DSSERR("can't get sys_clk\n"); + return PTR_ERR(clk); + } + + hdmi.sys_clk = clk; + + return 0; +} + +static int hdmi_connect(struct omap_dss_device *dssdev, + struct omap_dss_device *dst) +{ + struct omap_overlay_manager *mgr; + int r; + + r = hdmi_init_regulator(); + if (r) + return r; + + mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel); + if (!mgr) + return -ENODEV; + + r = dss_mgr_connect(mgr, dssdev); + if (r) + return r; + + r = omapdss_output_set_device(dssdev, dst); + if (r) { + DSSERR("failed to connect output to new device: %s\n", + dst->name); + dss_mgr_disconnect(mgr, dssdev); + return r; + } + + return 0; +} + +static void hdmi_disconnect(struct omap_dss_device *dssdev, + struct omap_dss_device *dst) +{ + WARN_ON(dst != dssdev->dst); + + if (dst != dssdev->dst) + return; + + omapdss_output_unset_device(dssdev); + + if (dssdev->manager) + dss_mgr_disconnect(dssdev->manager, dssdev); +} + +static int hdmi_read_edid(struct omap_dss_device *dssdev, + u8 *edid, int len) +{ + bool need_enable; + int r; + + need_enable = hdmi.core_enabled == false; + + if (need_enable) { + r = hdmi_core_enable(dssdev); + if (r) + return r; + } + + r = read_edid(edid, len); + + if (need_enable) + hdmi_core_disable(dssdev); + + return r; +} + +#if defined(CONFIG_OMAP5_DSS_HDMI_AUDIO) +static int hdmi_audio_enable(struct omap_dss_device *dssdev) +{ + int r; + + mutex_lock(&hdmi.lock); + + if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) { + r = -EPERM; + goto err; + } + + r = hdmi_wp_audio_enable(&hdmi.wp, true); + if (r) + goto err; + + mutex_unlock(&hdmi.lock); + return 0; + +err: + mutex_unlock(&hdmi.lock); + return r; +} + +static void hdmi_audio_disable(struct omap_dss_device *dssdev) +{ + hdmi_wp_audio_enable(&hdmi.wp, false); +} + +static int hdmi_audio_start(struct omap_dss_device *dssdev) +{ + return hdmi_wp_audio_core_req_enable(&hdmi.wp, true); +} + +static void hdmi_audio_stop(struct omap_dss_device *dssdev) +{ + hdmi_wp_audio_core_req_enable(&hdmi.wp, false); +} + +static bool hdmi_audio_supported(struct omap_dss_device *dssdev) +{ + bool r; + + mutex_lock(&hdmi.lock); + + r = hdmi_mode_has_audio(hdmi.cfg.cm.mode); + + mutex_unlock(&hdmi.lock); + return r; +} + +static int hdmi_audio_config(struct omap_dss_device *dssdev, + struct omap_dss_audio *audio) +{ + int r; + u32 pclk = hdmi.cfg.timings.pixelclock; + + mutex_lock(&hdmi.lock); + + if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) { + r = -EPERM; + goto err; + } + + r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, audio, pclk); + if (r) + goto err; + + mutex_unlock(&hdmi.lock); + return 0; + +err: + mutex_unlock(&hdmi.lock); + return r; +} +#else +static int hdmi_audio_enable(struct omap_dss_device *dssdev) +{ + return -EPERM; +} + +static void hdmi_audio_disable(struct omap_dss_device *dssdev) +{ +} + +static int hdmi_audio_start(struct omap_dss_device *dssdev) +{ + return -EPERM; +} + +static void hdmi_audio_stop(struct omap_dss_device *dssdev) +{ +} + +static bool hdmi_audio_supported(struct omap_dss_device *dssdev) +{ + return false; +} + +static int hdmi_audio_config(struct omap_dss_device *dssdev, + struct omap_dss_audio *audio) +{ + return -EPERM; +} +#endif + +static const struct omapdss_hdmi_ops hdmi_ops = { + .connect = hdmi_connect, + .disconnect = hdmi_disconnect, + + .enable = hdmi_display_enable, + .disable = hdmi_display_disable, + + .check_timings = hdmi_display_check_timing, + .set_timings = hdmi_display_set_timing, + .get_timings = hdmi_display_get_timings, + + .read_edid = hdmi_read_edid, + + .audio_enable = hdmi_audio_enable, + .audio_disable = hdmi_audio_disable, + .audio_start = hdmi_audio_start, + .audio_stop = hdmi_audio_stop, + .audio_supported = hdmi_audio_supported, + .audio_config = hdmi_audio_config, +}; + +static void hdmi_init_output(struct platform_device *pdev) +{ + struct omap_dss_device *out = &hdmi.output; + + out->dev = &pdev->dev; + out->id = OMAP_DSS_OUTPUT_HDMI; + out->output_type = OMAP_DISPLAY_TYPE_HDMI; + out->name = "hdmi.0"; + out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT; + out->ops.hdmi = &hdmi_ops; + out->owner = THIS_MODULE; + + omapdss_register_output(out); +} + +static void __exit hdmi_uninit_output(struct platform_device *pdev) +{ + struct omap_dss_device *out = &hdmi.output; + + omapdss_unregister_output(out); +} + +static int hdmi_probe_of(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct device_node *ep; + int r; + + ep = omapdss_of_get_first_endpoint(node); + if (!ep) + return 0; + + r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy); + if (r) + goto err; + + of_node_put(ep); + return 0; + +err: + of_node_put(ep); + return r; +} + +/* HDMI HW IP initialisation */ +static int omapdss_hdmihw_probe(struct platform_device *pdev) +{ + int r; + int irq; + + hdmi.pdev = pdev; + + mutex_init(&hdmi.lock); + + if (pdev->dev.of_node) { + r = hdmi_probe_of(pdev); + if (r) + return r; + } + + r = hdmi_wp_init(pdev, &hdmi.wp); + if (r) + return r; + + r = hdmi_pll_init(pdev, &hdmi.pll); + if (r) + return r; + + r = hdmi_phy_init(pdev, &hdmi.phy); + if (r) + return r; + + r = hdmi5_core_init(pdev, &hdmi.core); + if (r) + return r; + + r = hdmi_get_clocks(pdev); + if (r) { + DSSERR("can't get clocks\n"); + return r; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + DSSERR("platform_get_irq failed\n"); + return -ENODEV; + } + + r = devm_request_threaded_irq(&pdev->dev, irq, + NULL, hdmi_irq_handler, + IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp); + if (r) { + DSSERR("HDMI IRQ request failed\n"); + return r; + } + + pm_runtime_enable(&pdev->dev); + + hdmi_init_output(pdev); + + dss_debugfs_create_file("hdmi", hdmi_dump_regs); + + return 0; +} + +static int __exit omapdss_hdmihw_remove(struct platform_device *pdev) +{ + hdmi_uninit_output(pdev); + + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static int hdmi_runtime_suspend(struct device *dev) +{ + clk_disable_unprepare(hdmi.sys_clk); + + dispc_runtime_put(); + + return 0; +} + +static int hdmi_runtime_resume(struct device *dev) +{ + int r; + + r = dispc_runtime_get(); + if (r < 0) + return r; + + clk_prepare_enable(hdmi.sys_clk); + + return 0; +} + +static const struct dev_pm_ops hdmi_pm_ops = { + .runtime_suspend = hdmi_runtime_suspend, + .runtime_resume = hdmi_runtime_resume, +}; + +static const struct of_device_id hdmi_of_match[] = { + { .compatible = "ti,omap5-hdmi", }, + {}, +}; + +static struct platform_driver omapdss_hdmihw_driver = { + .probe = omapdss_hdmihw_probe, + .remove = __exit_p(omapdss_hdmihw_remove), + .driver = { + .name = "omapdss_hdmi5", + .owner = THIS_MODULE, + .pm = &hdmi_pm_ops, + .of_match_table = hdmi_of_match, + }, +}; + +int __init hdmi5_init_platform_driver(void) +{ + return platform_driver_register(&omapdss_hdmihw_driver); +} + +void __exit hdmi5_uninit_platform_driver(void) +{ + platform_driver_unregister(&omapdss_hdmihw_driver); +} diff --git a/drivers/video/fbdev/omap2/dss/hdmi5_core.c b/drivers/video/fbdev/omap2/dss/hdmi5_core.c new file mode 100644 index 00000000000..7528c7a42aa --- /dev/null +++ b/drivers/video/fbdev/omap2/dss/hdmi5_core.c @@ -0,0 +1,922 @@ +/* + * OMAP5 HDMI CORE IP driver library + * + * Copyright (C) 2014 Texas Instruments Incorporated + * + * Authors: + * Yong Zhi + * Mythri pk + * Archit Taneja <archit@ti.com> + * Tomi Valkeinen <tomi.valkeinen@ti.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/string.h> +#include <linux/seq_file.h> +#include <drm/drm_edid.h> +#if defined(CONFIG_OMAP5_DSS_HDMI_AUDIO) +#include <sound/asound.h> +#include <sound/asoundef.h> +#endif + +#include "hdmi5_core.h" + +/* only 24 bit color depth used for now */ +static const struct csc_table csc_table_deepcolor[] = { + /* HDMI_DEEP_COLOR_24BIT */ + [0] = { 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32, }, + /* HDMI_DEEP_COLOR_30BIT */ + [1] = { 7015, 0, 0, 128, 0, 7015, 0, 128, 0, 0, 7015, 128, }, + /* HDMI_DEEP_COLOR_36BIT */ + [2] = { 7010, 0, 0, 512, 0, 7010, 0, 512, 0, 0, 7010, 512, }, + /* FULL RANGE */ + [3] = { 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0, }, +}; + +static void hdmi_core_ddc_init(struct hdmi_core_data *core) +{ + void __iomem *base = core->base; + const unsigned long long iclk = 266000000; /* DSS L3 ICLK */ + const unsigned ss_scl_high = 4000; /* ns */ + const unsigned ss_scl_low = 4700; /* ns */ + const unsigned fs_scl_high = 600; /* ns */ + const unsigned fs_scl_low = 1300; /* ns */ + const unsigned sda_hold = 300; /* ns */ + const unsigned sfr_div = 10; + unsigned long long sfr; + unsigned v; + + sfr = iclk / sfr_div; /* SFR_DIV */ + sfr /= 1000; /* SFR clock in kHz */ + + /* Reset */ + REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); + if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ, + 0, 0, 1) != 1) + DSSERR("HDMI I2CM reset failed\n"); + + /* Standard (0) or Fast (1) Mode */ + REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); + + /* Standard Mode SCL High counter */ + v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000); + REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, + (v >> 8) & 0xff, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, + v & 0xff, 7, 0); + + /* Standard Mode SCL Low counter */ + v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000); + REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, + (v >> 8) & 0xff, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, + v & 0xff, 7, 0); + + /* Fast Mode SCL High Counter */ + v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000); + REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, + (v >> 8) & 0xff, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, + v & 0xff, 7, 0); + + /* Fast Mode SCL Low Counter */ + v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000); + REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR, + (v >> 8) & 0xff, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR, + v & 0xff, 7, 0); + + /* SDA Hold Time */ + v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000); + REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0); + + REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0); + REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0); + + /* NACK_POL to high */ + REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7); + + /* NACK_MASK to unmasked */ + REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6); + + /* ARBITRATION_POL to high */ + REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3); + + /* ARBITRATION_MASK to unmasked */ + REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2); + + /* DONE_POL to high */ + REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3); + + /* DONE_MASK to unmasked */ + REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2); +} + +static void hdmi_core_ddc_uninit(struct hdmi_core_data *core) +{ + void __iomem *base = core->base; + + /* Mask I2C interrupts */ + REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6); + REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2); + REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2); +} + +static int hdmi_core_ddc_edid(struct hdmi_core_data *core, u8 *pedid, u8 ext) +{ + void __iomem *base = core->base; + u8 cur_addr; + char checksum = 0; + const int retries = 1000; + u8 seg_ptr = ext / 2; + u8 edidbase = ((ext % 2) * 0x80); + + REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0); + + /* + * TODO: We use polling here, although we probably should use proper + * interrupts. + */ + for (cur_addr = 0; cur_addr < 128; ++cur_addr) { + int i; + + /* clear ERROR and DONE */ + REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0); + + REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS, + edidbase + cur_addr, 7, 0); + + if (seg_ptr) + REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1); + else + REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0); + + for (i = 0; i < retries; ++i) { + u32 stat; + + stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0); + + /* I2CM_ERROR */ + if (stat & 1) { + DSSERR("HDMI I2C Master Error\n"); + return -EIO; + } + + /* I2CM_DONE */ + if (stat & (1 << 1)) + break; + + usleep_range(250, 1000); + } + + if (i == retries) { + DSSERR("HDMI I2C timeout reading EDID\n"); + return -EIO; + } + + pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0); + checksum += pedid[cur_addr]; + } + + return 0; + +} + +int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len) +{ + int r, n, i; + int max_ext_blocks = (len / 128) - 1; + + if (len < 128) + return -EINVAL; + + hdmi_core_ddc_init(core); + + r = hdmi_core_ddc_edid(core, edid, 0); + if (r) + goto out; + + n = edid[0x7e]; + + if (n > max_ext_blocks) + n = max_ext_blocks; + + for (i = 1; i <= n; i++) { + r = hdmi_core_ddc_edid(core, edid + i * EDID_LENGTH, i); + if (r) + goto out; + } + +out: + hdmi_core_ddc_uninit(core); + + return r ? r : len; +} + +void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s) +{ + +#define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\ + hdmi_read_reg(core->base, r)) + + DUMPCORE(HDMI_CORE_FC_INVIDCONF); + DUMPCORE(HDMI_CORE_FC_INHACTIV0); + DUMPCORE(HDMI_CORE_FC_INHACTIV1); + DUMPCORE(HDMI_CORE_FC_INHBLANK0); + DUMPCORE(HDMI_CORE_FC_INHBLANK1); + DUMPCORE(HDMI_CORE_FC_INVACTIV0); + DUMPCORE(HDMI_CORE_FC_INVACTIV1); + DUMPCORE(HDMI_CORE_FC_INVBLANK); + DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY0); + DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY1); + DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH0); + DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH1); + DUMPCORE(HDMI_CORE_FC_VSYNCINDELAY); + DUMPCORE(HDMI_CORE_FC_VSYNCINWIDTH); + DUMPCORE(HDMI_CORE_FC_CTRLDUR); + DUMPCORE(HDMI_CORE_FC_EXCTRLDUR); + DUMPCORE(HDMI_CORE_FC_EXCTRLSPAC); + DUMPCORE(HDMI_CORE_FC_CH0PREAM); + DUMPCORE(HDMI_CORE_FC_CH1PREAM); + DUMPCORE(HDMI_CORE_FC_CH2PREAM); + DUMPCORE(HDMI_CORE_FC_AVICONF0); + DUMPCORE(HDMI_CORE_FC_AVICONF1); + DUMPCORE(HDMI_CORE_FC_AVICONF2); + DUMPCORE(HDMI_CORE_FC_AVIVID); + DUMPCORE(HDMI_CORE_FC_PRCONF); + + DUMPCORE(HDMI_CORE_MC_CLKDIS); + DUMPCORE(HDMI_CORE_MC_SWRSTZREQ); + DUMPCORE(HDMI_CORE_MC_FLOWCTRL); + DUMPCORE(HDMI_CORE_MC_PHYRSTZ); + DUMPCORE(HDMI_CORE_MC_LOCKONCLOCK); + + DUMPCORE(HDMI_CORE_I2CM_SLAVE); + DUMPCORE(HDMI_CORE_I2CM_ADDRESS); + DUMPCORE(HDMI_CORE_I2CM_DATAO); + DUMPCORE(HDMI_CORE_I2CM_DATAI); + DUMPCORE(HDMI_CORE_I2CM_OPERATION); + DUMPCORE(HDMI_CORE_I2CM_INT); + DUMPCORE(HDMI_CORE_I2CM_CTLINT); + DUMPCORE(HDMI_CORE_I2CM_DIV); + DUMPCORE(HDMI_CORE_I2CM_SEGADDR); + DUMPCORE(HDMI_CORE_I2CM_SOFTRSTZ); + DUMPCORE(HDMI_CORE_I2CM_SEGPTR); + DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR); + DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR); + DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR); + DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR); + DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR); + DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR); + DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR); + DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR); + DUMPCORE(HDMI_CORE_I2CM_SDA_HOLD_ADDR); +} + +static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg, + struct hdmi_core_infoframe_avi *avi_cfg, + struct hdmi_config *cfg) +{ + DSSDBG("hdmi_core_init\n"); + + /* video core */ + video_cfg->data_enable_pol = 1; /* It is always 1*/ + video_cfg->v_fc_config.timings.hsync_level = cfg->timings.hsync_level; + video_cfg->v_fc_config.timings.x_res = cfg->timings.x_res; + video_cfg->v_fc_config.timings.hsw = cfg->timings.hsw - 1; + video_cfg->v_fc_config.timings.hbp = cfg->timings.hbp; + video_cfg->v_fc_config.timings.hfp = cfg->timings.hfp; + video_cfg->hblank = cfg->timings.hfp + + cfg->timings.hbp + cfg->timings.hsw - 1; + video_cfg->v_fc_config.timings.vsync_level = cfg->timings.vsync_level; + video_cfg->v_fc_config.timings.y_res = cfg->timings.y_res; + video_cfg->v_fc_config.timings.vsw = cfg->timings.vsw; + video_cfg->v_fc_config.timings.vfp = cfg->timings.vfp; + video_cfg->v_fc_config.timings.vbp = cfg->timings.vbp; + video_cfg->vblank_osc = 0; /* Always 0 - need to confirm */ + video_cfg->vblank = cfg->timings.vsw + + cfg->timings.vfp + cfg->timings.vbp; + video_cfg->v_fc_config.cm.mode = cfg->cm.mode; + video_cfg->v_fc_config.timings.interlace = cfg->timings.interlace; + + /* info frame */ + avi_cfg->db1_format = 0; + avi_cfg->db1_active_info = 0; + avi_cfg->db1_bar_info_dv = 0; + avi_cfg->db1_scan_info = 0; + avi_cfg->db2_colorimetry = 0; + avi_cfg->db2_aspect_ratio = 0; + avi_cfg->db2_active_fmt_ar = 0; + avi_cfg->db3_itc = 0; + avi_cfg->db3_ec = 0; + avi_cfg->db3_q_range = 0; + avi_cfg->db3_nup_scaling = 0; + avi_cfg->db4_videocode = 0; + avi_cfg->db5_pixel_repeat = 0; + avi_cfg->db6_7_line_eoftop = 0; + avi_cfg->db8_9_line_sofbottom = 0; + avi_cfg->db10_11_pixel_eofleft = 0; + avi_cfg->db12_13_pixel_sofright = 0; +} + +/* DSS_HDMI_CORE_VIDEO_CONFIG */ +static void hdmi_core_video_config(struct hdmi_core_data *core, + struct hdmi_core_vid_config *cfg) +{ + void __iomem *base = core->base; + unsigned char r = 0; + bool vsync_pol, hsync_pol; + + vsync_pol = + cfg->v_fc_config.timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH; + hsync_pol = + cfg->v_fc_config.timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH; + + /* Set hsync, vsync and data-enable polarity */ + r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF); + r = FLD_MOD(r, vsync_pol, 6, 6); + r = FLD_MOD(r, hsync_pol, 5, 5); + r = FLD_MOD(r, cfg->data_enable_pol, 4, 4); + r = FLD_MOD(r, cfg->vblank_osc, 1, 1); + r = FLD_MOD(r, cfg->v_fc_config.timings.interlace, 0, 0); + hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r); + + /* set x resolution */ + REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, + cfg->v_fc_config.timings.x_res >> 8, 4, 0); + REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0, + cfg->v_fc_config.timings.x_res & 0xFF, 7, 0); + + /* set y resolution */ + REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, + cfg->v_fc_config.timings.y_res >> 8, 4, 0); + REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0, + cfg->v_fc_config.timings.y_res & 0xFF, 7, 0); + + /* set horizontal blanking pixels */ + REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0); + REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0); + + /* set vertial blanking pixels */ + REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0); + + /* set horizontal sync offset */ + REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, + cfg->v_fc_config.timings.hfp >> 8, 4, 0); + REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, + cfg->v_fc_config.timings.hfp & 0xFF, 7, 0); + + /* set vertical sync offset */ + REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, + cfg->v_fc_config.timings.vfp, 7, 0); + + /* set horizontal sync pulse width */ + REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, + (cfg->v_fc_config.timings.hsw >> 8), 1, 0); + REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, + cfg->v_fc_config.timings.hsw & 0xFF, 7, 0); + + /* set vertical sync pulse width */ + REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, + cfg->v_fc_config.timings.vsw, 5, 0); + + /* select DVI mode */ + REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF, + cfg->v_fc_config.cm.mode, 3, 3); +} + +static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core) +{ + void __iomem *base = core->base; + int clr_depth = 0; /* 24 bit color depth */ + + /* COLOR_DEPTH */ + REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4); + /* BYPASS_EN */ + REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6); + /* PP_EN */ + REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5); + /* YCC422_EN */ + REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3); + /* PP_STUFFING */ + REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1); + /* YCC422_STUFFING */ + REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2); + /* OUTPUT_SELECTOR */ + REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0); +} + +static void hdmi_core_config_csc(struct hdmi_core_data *core) +{ + int clr_depth = 0; /* 24 bit color depth */ + + /* CSC_COLORDEPTH */ + REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4); +} + +static void hdmi_core_config_video_sampler(struct hdmi_core_data *core) +{ + int video_mapping = 1; /* for 24 bit color depth */ + + /* VIDEO_MAPPING */ + REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0); +} + +static void hdmi_core_aux_infoframe_avi_config(struct hdmi_core_data *core) +{ + void __iomem *base = core->base; + struct hdmi_core_infoframe_avi avi = core->avi_cfg; + + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF0, avi.db1_format, 1, 0); + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF0, avi.db1_active_info, 6, 6); + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF0, avi.db1_bar_info_dv, 3, 2); + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF0, avi.db1_scan_info, 5, 4); + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF1, avi.db2_colorimetry, 7, 6); + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF1, avi.db2_aspect_ratio, 5, 4); + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF1, avi.db2_active_fmt_ar, 3, 0); + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF2, avi.db3_itc, 7, 7); + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF2, avi.db3_ec, 6, 4); + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF2, avi.db3_q_range, 3, 2); + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF2, avi.db3_nup_scaling, 1, 0); + REG_FLD_MOD(base, HDMI_CORE_FC_AVIVID, avi.db4_videocode, 6, 0); + REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, avi.db5_pixel_repeat, 3, 0); +} + +static void hdmi_core_csc_config(struct hdmi_core_data *core, + struct csc_table csc_coeff) +{ + void __iomem *base = core->base; + + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0); + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0); + + REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0); +} + +static void hdmi_core_configure_range(struct hdmi_core_data *core) +{ + struct csc_table csc_coeff = { 0 }; + + /* support limited range with 24 bit color depth for now */ + csc_coeff = csc_table_deepcolor[0]; + core->avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_LR; + + hdmi_core_csc_config(core, csc_coeff); + hdmi_core_aux_infoframe_avi_config(core); +} + +static void hdmi_core_enable_video_path(struct hdmi_core_data *core) +{ + void __iomem *base = core->base; + + DSSDBG("hdmi_core_enable_video_path\n"); + + REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0); + REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0); + REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0); + REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1); +} + +static void hdmi_core_mask_interrupts(struct hdmi_core_data *core) +{ + void __iomem *base = core->base; + + /* Master IRQ mask */ + REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0); + + /* Mask all the interrupts in HDMI core */ + + REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0); + + REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2); + REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0); + + REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0); + + REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6); + REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2); + REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2); + + REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0); + + REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); + + /* Clear all the current interrupt bits */ + + REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0); + + REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0); + + REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0); + + REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0); + + REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); +} + +static void hdmi_core_enable_interrupts(struct hdmi_core_data *core) +{ + /* Unmute interrupts */ + REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0); +} + +int hdmi5_core_handle_irqs(struct hdmi_core_data *core) +{ + void __iomem *base = core->base; + + REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0); + + return 0; +} + +void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, + struct hdmi_config *cfg) +{ + struct omap_video_timings video_timing; + struct hdmi_video_format video_format; + struct hdmi_core_vid_config v_core_cfg; + struct hdmi_core_infoframe_avi *avi_cfg = &core->avi_cfg; + + hdmi_core_mask_interrupts(core); + + hdmi_core_init(&v_core_cfg, avi_cfg, cfg); + + hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); + + hdmi_wp_video_config_timing(wp, &video_timing); + + /* video config */ + video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; + + hdmi_wp_video_config_format(wp, &video_format); + + hdmi_wp_video_config_interface(wp, &video_timing); + + hdmi_core_configure_range(core); + + /* + * configure core video part, set software reset in the core + */ + v_core_cfg.packet_mode = HDMI_PACKETMODE24BITPERPIXEL; + + hdmi_core_video_config(core, &v_core_cfg); + + hdmi_core_config_video_packetizer(core); + hdmi_core_config_csc(core); + hdmi_core_config_video_sampler(core); + + /* + * configure packet info frame video see doc CEA861-D page 65 + */ + avi_cfg->db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB; + avi_cfg->db1_active_info = + HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF; + avi_cfg->db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO; + avi_cfg->db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0; + avi_cfg->db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO; + avi_cfg->db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO; + avi_cfg->db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME; + avi_cfg->db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO; + avi_cfg->db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601; + avi_cfg->db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT; + avi_cfg->db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO; + avi_cfg->db4_videocode = cfg->cm.code; + avi_cfg->db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO; + avi_cfg->db6_7_line_eoftop = 0; + avi_cfg->db8_9_line_sofbottom = 0; + avi_cfg->db10_11_pixel_eofleft = 0; + avi_cfg->db12_13_pixel_sofright = 0; + + hdmi_core_aux_infoframe_avi_config(core); + + hdmi_core_enable_video_path(core); + + hdmi_core_enable_interrupts(core); +} + + +#if defined(CONFIG_OMAP5_DSS_HDMI_AUDIO) + +static void hdmi5_core_audio_config(struct hdmi_core_data *core, + struct hdmi_core_audio_config *cfg) +{ + void __iomem *base = core->base; + u8 val; + + /* Mute audio before configuring */ + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4); + + /* Set the N parameter */ + REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0); + + /* + * CTS manual mode. Automatic mode is not supported when using audio + * parallel interface. + */ + REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4); + REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0); + REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0); + + /* Layout of Audio Sample Packets: 2-channel or multichannels */ + if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0); + else + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0); + + /* Configure IEC-609580 Validity bits */ + /* Channel 0 is valid */ + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0); + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4); + + if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) + val = 1; + else + val = 0; + + /* Channels 1, 2 setting */ + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1); + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5); + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2); + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6); + /* Channel 3 setting */ + if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) + val = 1; + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3); + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7); + + /* Configure IEC-60958 User bits */ + /* TODO: should be set by user. */ + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0); + + /* Configure IEC-60958 Channel Status word */ + /* CGMSA */ + val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA; + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4); + + /* Copyright */ + val = (cfg->iec60958_cfg->status[0] & + IEC958_AES0_CON_NOT_COPYRIGHT) >> 2; + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0); + + /* Category */ + hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1), + cfg->iec60958_cfg->status[1]); + + /* PCM audio mode */ + val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6; + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4); + + /* Source number */ + val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE; + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 4); + + /* Channel number right 0 */ + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0); + /* Channel number right 1*/ + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4); + /* Channel number right 2 */ + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0); + /* Channel number right 3*/ + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4); + /* Channel number left 0 */ + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0); + /* Channel number left 1*/ + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4); + /* Channel number left 2 */ + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0); + /* Channel number left 3*/ + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4); + + /* Clock accuracy and sample rate */ + hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7), + cfg->iec60958_cfg->status[3]); + + /* Original sample rate and word length */ + hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8), + cfg->iec60958_cfg->status[4]); + + /* Enable FIFO empty and full interrupts */ + REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2); + + /* Configure GPA */ + /* select HBR/SPDIF interfaces */ + if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) { + /* select HBR/SPDIF interfaces */ + REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); + /* enable two channels in GPA */ + REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0); + } else if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) { + /* select HBR/SPDIF interfaces */ + REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); + /* enable six channels in GPA */ + REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0); + } else { + /* select HBR/SPDIF interfaces */ + REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); + /* enable eight channels in GPA */ + REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0); + } + + /* disable HBR */ + REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0); + /* enable PCUV */ + REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1); + /* enable GPA FIFO full and empty mask */ + REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0); + /* set polarity of GPA FIFO empty interrupts */ + REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0); + + /* unmute audio */ + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4); +} + +static void hdmi5_core_audio_infoframe_cfg(struct hdmi_core_data *core, + struct snd_cea_861_aud_if *info_aud) +{ + void __iomem *base = core->base; + + /* channel count and coding type fields in AUDICONF0 are swapped */ + hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0, + (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) << 4 | + (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CT) >> 4); + + hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss); + hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca); + hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3, info_aud->db5_dminh_lsv); +} + +int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, + struct omap_dss_audio *audio, u32 pclk) +{ + struct hdmi_audio_format audio_format; + struct hdmi_audio_dma audio_dma; + struct hdmi_core_audio_config core_cfg; + int err, n, cts, channel_count; + unsigned int fs_nr; + bool word_length_16b = false; + + if (!audio || !audio->iec || !audio->cea || !core) + return -EINVAL; + + core_cfg.iec60958_cfg = audio->iec; + + if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) && + (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16)) + word_length_16b = true; + + /* only 16-bit word length supported atm */ + if (!word_length_16b) + return -EINVAL; + + switch (audio->iec->status[3] & IEC958_AES3_CON_FS) { + case IEC958_AES3_CON_FS_32000: + fs_nr = 32000; + break; + case IEC958_AES3_CON_FS_44100: + fs_nr = 44100; + break; + case IEC958_AES3_CON_FS_48000: + fs_nr = 48000; + break; + case IEC958_AES3_CON_FS_88200: + fs_nr = 88200; + break; + case IEC958_AES3_CON_FS_96000: + fs_nr = 96000; + break; + case IEC958_AES3_CON_FS_176400: + fs_nr = 176400; + break; + case IEC958_AES3_CON_FS_192000: + fs_nr = 192000; + break; + default: + return -EINVAL; + } + + err = hdmi_compute_acr(pclk, fs_nr, &n, &cts); + core_cfg.n = n; + core_cfg.cts = cts; + + /* Audio channels settings */ + channel_count = (audio->cea->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) + + 1; + + if (channel_count == 2) + core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH; + else if (channel_count == 6) + core_cfg.layout = HDMI_AUDIO_LAYOUT_6CH; + else + core_cfg.layout = HDMI_AUDIO_LAYOUT_8CH; + + /* DMA settings */ + if (word_length_16b) + audio_dma.transfer_size = 0x10; + else + audio_dma.transfer_size = 0x20; + audio_dma.block_size = 0xC0; + audio_dma.mode = HDMI_AUDIO_TRANSF_DMA; + audio_dma.fifo_threshold = 0x20; /* in number of samples */ + + /* audio FIFO format settings for 16-bit samples*/ + audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES; + audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS; + audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT; + + /* only LPCM atm */ + audio_format.type = HDMI_AUDIO_TYPE_LPCM; + + /* disable start/stop signals of IEC 60958 blocks */ + audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON; + + /* configure DMA and audio FIFO format*/ + hdmi_wp_audio_config_dma(wp, &audio_dma); + hdmi_wp_audio_config_format(wp, &audio_format); + + /* configure the core */ + hdmi5_core_audio_config(core, &core_cfg); + + /* configure CEA 861 audio infoframe */ + hdmi5_core_audio_infoframe_cfg(core, audio->cea); + + return 0; +} +#endif + +int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core) +{ + struct resource *res; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); + if (!res) { + DSSERR("can't get CORE IORESOURCE_MEM HDMI\n"); + return -EINVAL; + } + + core->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(core->base)) { + DSSERR("can't ioremap HDMI core\n"); + return PTR_ERR(core->base); + } + + return 0; +} diff --git a/drivers/video/fbdev/omap2/dss/hdmi5_core.h b/drivers/video/fbdev/omap2/dss/hdmi5_core.h new file mode 100644 index 00000000000..ce7e9f376f0 --- /dev/null +++ b/drivers/video/fbdev/omap2/dss/hdmi5_core.h @@ -0,0 +1,306 @@ +/* + * HDMI driver definition for TI OMAP5 processors. + * + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _HDMI5_CORE_H_ +#define _HDMI5_CORE_H_ + +#include "hdmi.h" + +/* HDMI IP Core System */ + +/* HDMI Identification */ +#define HDMI_CORE_DESIGN_ID 0x00000 +#define HDMI_CORE_REVISION_ID 0x00004 +#define HDMI_CORE_PRODUCT_ID0 0x00008 +#define HDMI_CORE_PRODUCT_ID1 0x0000C +#define HDMI_CORE_CONFIG0_ID 0x00010 +#define HDMI_CORE_CONFIG1_ID 0x00014 +#define HDMI_CORE_CONFIG2_ID 0x00018 +#define HDMI_CORE_CONFIG3_ID 0x0001C + +/* HDMI Interrupt */ +#define HDMI_CORE_IH_FC_STAT0 0x00400 +#define HDMI_CORE_IH_FC_STAT1 0x00404 +#define HDMI_CORE_IH_FC_STAT2 0x00408 +#define HDMI_CORE_IH_AS_STAT0 0x0040C +#define HDMI_CORE_IH_PHY_STAT0 0x00410 +#define HDMI_CORE_IH_I2CM_STAT0 0x00414 +#define HDMI_CORE_IH_CEC_STAT0 0x00418 +#define HDMI_CORE_IH_VP_STAT0 0x0041C +#define HDMI_CORE_IH_I2CMPHY_STAT0 0x00420 +#define HDMI_CORE_IH_MUTE 0x007FC + +/* HDMI Video Sampler */ +#define HDMI_CORE_TX_INVID0 0x00800 +#define HDMI_CORE_TX_INSTUFFING 0x00804 +#define HDMI_CORE_TX_RGYDATA0 0x00808 +#define HDMI_CORE_TX_RGYDATA1 0x0080C +#define HDMI_CORE_TX_RCRDATA0 0x00810 +#define HDMI_CORE_TX_RCRDATA1 0x00814 +#define HDMI_CORE_TX_BCBDATA0 0x00818 +#define HDMI_CORE_TX_BCBDATA1 0x0081C + +/* HDMI Video Packetizer */ +#define HDMI_CORE_VP_STATUS 0x02000 +#define HDMI_CORE_VP_PR_CD 0x02004 +#define HDMI_CORE_VP_STUFF 0x02008 +#define HDMI_CORE_VP_REMAP 0x0200C +#define HDMI_CORE_VP_CONF 0x02010 +#define HDMI_CORE_VP_STAT 0x02014 +#define HDMI_CORE_VP_INT 0x02018 +#define HDMI_CORE_VP_MASK 0x0201C +#define HDMI_CORE_VP_POL 0x02020 + +/* Frame Composer */ +#define HDMI_CORE_FC_INVIDCONF 0x04000 +#define HDMI_CORE_FC_INHACTIV0 0x04004 +#define HDMI_CORE_FC_INHACTIV1 0x04008 +#define HDMI_CORE_FC_INHBLANK0 0x0400C +#define HDMI_CORE_FC_INHBLANK1 0x04010 +#define HDMI_CORE_FC_INVACTIV0 0x04014 +#define HDMI_CORE_FC_INVACTIV1 0x04018 +#define HDMI_CORE_FC_INVBLANK 0x0401C +#define HDMI_CORE_FC_HSYNCINDELAY0 0x04020 +#define HDMI_CORE_FC_HSYNCINDELAY1 0x04024 +#define HDMI_CORE_FC_HSYNCINWIDTH0 0x04028 +#define HDMI_CORE_FC_HSYNCINWIDTH1 0x0402C +#define HDMI_CORE_FC_VSYNCINDELAY 0x04030 +#define HDMI_CORE_FC_VSYNCINWIDTH 0x04034 +#define HDMI_CORE_FC_INFREQ0 0x04038 +#define HDMI_CORE_FC_INFREQ1 0x0403C +#define HDMI_CORE_FC_INFREQ2 0x04040 +#define HDMI_CORE_FC_CTRLDUR 0x04044 +#define HDMI_CORE_FC_EXCTRLDUR 0x04048 +#define HDMI_CORE_FC_EXCTRLSPAC 0x0404C +#define HDMI_CORE_FC_CH0PREAM 0x04050 +#define HDMI_CORE_FC_CH1PREAM 0x04054 +#define HDMI_CORE_FC_CH2PREAM 0x04058 +#define HDMI_CORE_FC_AVICONF3 0x0405C +#define HDMI_CORE_FC_GCP 0x04060 +#define HDMI_CORE_FC_AVICONF0 0x04064 +#define HDMI_CORE_FC_AVICONF1 0x04068 +#define HDMI_CORE_FC_AVICONF2 0x0406C +#define HDMI_CORE_FC_AVIVID 0x04070 +#define HDMI_CORE_FC_AVIETB0 0x04074 +#define HDMI_CORE_FC_AVIETB1 0x04078 +#define HDMI_CORE_FC_AVISBB0 0x0407C +#define HDMI_CORE_FC_AVISBB1 0x04080 +#define HDMI_CORE_FC_AVIELB0 0x04084 +#define HDMI_CORE_FC_AVIELB1 0x04088 +#define HDMI_CORE_FC_AVISRB0 0x0408C +#define HDMI_CORE_FC_AVISRB1 0x04090 +#define HDMI_CORE_FC_AUDICONF0 0x04094 +#define HDMI_CORE_FC_AUDICONF1 0x04098 +#define HDMI_CORE_FC_AUDICONF2 0x0409C +#define HDMI_CORE_FC_AUDICONF3 0x040A0 +#define HDMI_CORE_FC_VSDIEEEID0 0x040A4 +#define HDMI_CORE_FC_VSDSIZE 0x040A8 +#define HDMI_CORE_FC_VSDIEEEID1 0x040C0 +#define HDMI_CORE_FC_VSDIEEEID2 0x040C4 +#define HDMI_CORE_FC_VSDPAYLOAD(n) (n * 4 + 0x040C8) +#define HDMI_CORE_FC_SPDVENDORNAME(n) (n * 4 + 0x04128) +#define HDMI_CORE_FC_SPDPRODUCTNAME(n) (n * 4 + 0x04148) +#define HDMI_CORE_FC_SPDDEVICEINF 0x04188 +#define HDMI_CORE_FC_AUDSCONF 0x0418C +#define HDMI_CORE_FC_AUDSSTAT 0x04190 +#define HDMI_CORE_FC_AUDSV 0x04194 +#define HDMI_CORE_FC_AUDSU 0x04198 +#define HDMI_CORE_FC_AUDSCHNLS(n) (n * 4 + 0x0419C) +#define HDMI_CORE_FC_CTRLQHIGH 0x041CC +#define HDMI_CORE_FC_CTRLQLOW 0x041D0 +#define HDMI_CORE_FC_ACP0 0x041D4 +#define HDMI_CORE_FC_ACP(n) ((16-n) * 4 + 0x04208) +#define HDMI_CORE_FC_ISCR1_0 0x04248 +#define HDMI_CORE_FC_ISCR1(n) ((16-n) * 4 + 0x0424C) +#define HDMI_CORE_FC_ISCR2(n) ((15-n) * 4 + 0x0428C) +#define HDMI_CORE_FC_DATAUTO0 0x042CC +#define HDMI_CORE_FC_DATAUTO1 0x042D0 +#define HDMI_CORE_FC_DATAUTO2 0x042D4 +#define HDMI_CORE_FC_DATMAN 0x042D8 +#define HDMI_CORE_FC_DATAUTO3 0x042DC +#define HDMI_CORE_FC_RDRB(n) (n * 4 + 0x042E0) +#define HDMI_CORE_FC_STAT0 0x04340 +#define HDMI_CORE_FC_INT0 0x04344 +#define HDMI_CORE_FC_MASK0 0x04348 +#define HDMI_CORE_FC_POL0 0x0434C +#define HDMI_CORE_FC_STAT1 0x04350 +#define HDMI_CORE_FC_INT1 0x04354 +#define HDMI_CORE_FC_MASK1 0x04358 +#define HDMI_CORE_FC_POL1 0x0435C +#define HDMI_CORE_FC_STAT2 0x04360 +#define HDMI_CORE_FC_INT2 0x04364 +#define HDMI_CORE_FC_MASK2 0x04368 +#define HDMI_CORE_FC_POL2 0x0436C +#define HDMI_CORE_FC_PRCONF 0x04380 +#define HDMI_CORE_FC_GMD_STAT 0x04400 +#define HDMI_CORE_FC_GMD_EN 0x04404 +#define HDMI_CORE_FC_GMD_UP 0x04408 +#define HDMI_CORE_FC_GMD_CONF 0x0440C +#define HDMI_CORE_FC_GMD_HB 0x04410 +#define HDMI_CORE_FC_GMD_PB(n) (n * 4 + 0x04414) +#define HDMI_CORE_FC_DBGFORCE 0x04800 +#define HDMI_CORE_FC_DBGAUD0CH0 0x04804 +#define HDMI_CORE_FC_DBGAUD1CH0 0x04808 +#define HDMI_CORE_FC_DBGAUD2CH0 0x0480C +#define HDMI_CORE_FC_DBGAUD0CH1 0x04810 +#define HDMI_CORE_FC_DBGAUD1CH1 0x04814 +#define HDMI_CORE_FC_DBGAUD2CH1 0x04818 +#define HDMI_CORE_FC_DBGAUD0CH2 0x0481C +#define HDMI_CORE_FC_DBGAUD1CH2 0x04820 +#define HDMI_CORE_FC_DBGAUD2CH2 0x04824 +#define HDMI_CORE_FC_DBGAUD0CH3 0x04828 +#define HDMI_CORE_FC_DBGAUD1CH3 0x0482C +#define HDMI_CORE_FC_DBGAUD2CH3 0x04830 +#define HDMI_CORE_FC_DBGAUD0CH4 0x04834 +#define HDMI_CORE_FC_DBGAUD1CH4 0x04838 +#define HDMI_CORE_FC_DBGAUD2CH4 0x0483C +#define HDMI_CORE_FC_DBGAUD0CH5 0x04840 +#define HDMI_CORE_FC_DBGAUD1CH5 0x04844 +#define HDMI_CORE_FC_DBGAUD2CH5 0x04848 +#define HDMI_CORE_FC_DBGAUD0CH6 0x0484C +#define HDMI_CORE_FC_DBGAUD1CH6 0x04850 +#define HDMI_CORE_FC_DBGAUD2CH6 0x04854 +#define HDMI_CORE_FC_DBGAUD0CH7 0x04858 +#define HDMI_CORE_FC_DBGAUD1CH7 0x0485C +#define HDMI_CORE_FC_DBGAUD2CH7 0x04860 +#define HDMI_CORE_FC_DBGTMDS0 0x04864 +#define HDMI_CORE_FC_DBGTMDS1 0x04868 +#define HDMI_CORE_FC_DBGTMDS2 0x0486C +#define HDMI_CORE_PHY_MASK0 0x0C018 +#define HDMI_CORE_PHY_I2CM_INT_ADDR 0x0C09C +#define HDMI_CORE_PHY_I2CM_CTLINT_ADDR 0x0C0A0 + +/* HDMI Audio */ +#define HDMI_CORE_AUD_CONF0 0x0C400 +#define HDMI_CORE_AUD_CONF1 0x0C404 +#define HDMI_CORE_AUD_INT 0x0C408 +#define HDMI_CORE_AUD_N1 0x0C800 +#define HDMI_CORE_AUD_N2 0x0C804 +#define HDMI_CORE_AUD_N3 0x0C808 +#define HDMI_CORE_AUD_CTS1 0x0C80C +#define HDMI_CORE_AUD_CTS2 0x0C810 +#define HDMI_CORE_AUD_CTS3 0x0C814 +#define HDMI_CORE_AUD_INCLKFS 0x0C818 +#define HDMI_CORE_AUD_CC08 0x0CC08 +#define HDMI_CORE_AUD_GP_CONF0 0x0D400 +#define HDMI_CORE_AUD_GP_CONF1 0x0D404 +#define HDMI_CORE_AUD_GP_CONF2 0x0D408 +#define HDMI_CORE_AUD_D010 0x0D010 +#define HDMI_CORE_AUD_GP_STAT 0x0D40C +#define HDMI_CORE_AUD_GP_INT 0x0D410 +#define HDMI_CORE_AUD_GP_POL 0x0D414 +#define HDMI_CORE_AUD_GP_MASK 0x0D418 + +/* HDMI Main Controller */ +#define HDMI_CORE_MC_CLKDIS 0x10004 +#define HDMI_CORE_MC_SWRSTZREQ 0x10008 +#define HDMI_CORE_MC_FLOWCTRL 0x10010 +#define HDMI_CORE_MC_PHYRSTZ 0x10014 +#define HDMI_CORE_MC_LOCKONCLOCK 0x10018 + +/* HDMI COLOR SPACE CONVERTER */ +#define HDMI_CORE_CSC_CFG 0x10400 +#define HDMI_CORE_CSC_SCALE 0x10404 +#define HDMI_CORE_CSC_COEF_A1_MSB 0x10408 +#define HDMI_CORE_CSC_COEF_A1_LSB 0x1040C +#define HDMI_CORE_CSC_COEF_A2_MSB 0x10410 +#define HDMI_CORE_CSC_COEF_A2_LSB 0x10414 +#define HDMI_CORE_CSC_COEF_A3_MSB 0x10418 +#define HDMI_CORE_CSC_COEF_A3_LSB 0x1041C +#define HDMI_CORE_CSC_COEF_A4_MSB 0x10420 +#define HDMI_CORE_CSC_COEF_A4_LSB 0x10424 +#define HDMI_CORE_CSC_COEF_B1_MSB 0x10428 +#define HDMI_CORE_CSC_COEF_B1_LSB 0x1042C +#define HDMI_CORE_CSC_COEF_B2_MSB 0x10430 +#define HDMI_CORE_CSC_COEF_B2_LSB 0x10434 +#define HDMI_CORE_CSC_COEF_B3_MSB 0x10438 +#define HDMI_CORE_CSC_COEF_B3_LSB 0x1043C +#define HDMI_CORE_CSC_COEF_B4_MSB 0x10440 +#define HDMI_CORE_CSC_COEF_B4_LSB 0x10444 +#define HDMI_CORE_CSC_COEF_C1_MSB 0x10448 +#define HDMI_CORE_CSC_COEF_C1_LSB 0x1044C +#define HDMI_CORE_CSC_COEF_C2_MSB 0x10450 +#define HDMI_CORE_CSC_COEF_C2_LSB 0x10454 +#define HDMI_CORE_CSC_COEF_C3_MSB 0x10458 +#define HDMI_CORE_CSC_COEF_C3_LSB 0x1045C +#define HDMI_CORE_CSC_COEF_C4_MSB 0x10460 +#define HDMI_CORE_CSC_COEF_C4_LSB 0x10464 + +/* HDMI HDCP */ +#define HDMI_CORE_HDCP_MASK 0x14020 + +/* HDMI CEC */ +#define HDMI_CORE_CEC_MASK 0x17408 + +/* HDMI I2C Master */ +#define HDMI_CORE_I2CM_SLAVE 0x157C8 +#define HDMI_CORE_I2CM_ADDRESS 0x157CC +#define HDMI_CORE_I2CM_DATAO 0x157D0 +#define HDMI_CORE_I2CM_DATAI 0X157D4 +#define HDMI_CORE_I2CM_OPERATION 0x157D8 +#define HDMI_CORE_I2CM_INT 0x157DC +#define HDMI_CORE_I2CM_CTLINT 0x157E0 +#define HDMI_CORE_I2CM_DIV 0x157E4 +#define HDMI_CORE_I2CM_SEGADDR 0x157E8 +#define HDMI_CORE_I2CM_SOFTRSTZ 0x157EC +#define HDMI_CORE_I2CM_SEGPTR 0x157F0 +#define HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR 0x157F4 +#define HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR 0x157F8 +#define HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR 0x157FC +#define HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR 0x15800 +#define HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR 0x15804 +#define HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR 0x15808 +#define HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR 0x1580C +#define HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR 0x15810 +#define HDMI_CORE_I2CM_SDA_HOLD_ADDR 0x15814 + +enum hdmi_core_packet_mode { + HDMI_PACKETMODERESERVEDVALUE = 0, + HDMI_PACKETMODE24BITPERPIXEL = 4, + HDMI_PACKETMODE30BITPERPIXEL = 5, + HDMI_PACKETMODE36BITPERPIXEL = 6, + HDMI_PACKETMODE48BITPERPIXEL = 7, +}; + +struct hdmi_core_vid_config { + struct hdmi_config v_fc_config; + enum hdmi_core_packet_mode packet_mode; + int data_enable_pol; + int vblank_osc; + int hblank; + int vblank; +}; + +struct csc_table { + u16 a1, a2, a3, a4; + u16 b1, b2, b3, b4; + u16 c1, c2, c3, c4; +}; + +int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len); +void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s); +int hdmi5_core_handle_irqs(struct hdmi_core_data *core); +void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, + struct hdmi_config *cfg); +int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core); + +#if defined(CONFIG_OMAP5_DSS_HDMI_AUDIO) +int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, + struct omap_dss_audio *audio, u32 pclk); +#endif +#endif diff --git a/drivers/video/fbdev/omap2/dss/hdmi_common.c b/drivers/video/fbdev/omap2/dss/hdmi_common.c index 0b12a3f62fe..9a2c39cf297 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi_common.c +++ b/drivers/video/fbdev/omap2/dss/hdmi_common.c @@ -17,6 +17,7 @@ #include <linux/kernel.h> #include <linux/err.h> +#include <linux/of.h> #include <video/omapdss.h> #include "hdmi.h" @@ -323,6 +324,46 @@ end: return cm; } +int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep, + struct hdmi_phy_data *phy) +{ + struct property *prop; + int r, len; + + prop = of_find_property(ep, "lanes", &len); + if (prop) { + u32 lanes[8]; + + if (len / sizeof(u32) != ARRAY_SIZE(lanes)) { + dev_err(&pdev->dev, "bad number of lanes\n"); + return -EINVAL; + } + + r = of_property_read_u32_array(ep, "lanes", lanes, + ARRAY_SIZE(lanes)); + if (r) { + dev_err(&pdev->dev, "failed to read lane data\n"); + return r; + } + + r = hdmi_phy_parse_lanes(phy, lanes); + if (r) { + dev_err(&pdev->dev, "failed to parse lane data\n"); + return r; + } + } else { + static const u32 default_lanes[] = { 0, 1, 2, 3, 4, 5, 6, 7 }; + + r = hdmi_phy_parse_lanes(phy, default_lanes); + if (WARN_ON(r)) { + dev_err(&pdev->dev, "failed to parse lane data\n"); + return r; + } + } + + return 0; +} + #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts) { diff --git a/drivers/video/fbdev/omap2/dss/hdmi_phy.c b/drivers/video/fbdev/omap2/dss/hdmi_phy.c index dd376ce8da0..e007ac892d7 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi_phy.c +++ b/drivers/video/fbdev/omap2/dss/hdmi_phy.c @@ -12,11 +12,22 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/platform_device.h> +#include <linux/slab.h> #include <video/omapdss.h> #include "dss.h" #include "hdmi.h" +struct hdmi_phy_features { + bool bist_ctrl; + bool calc_freqout; + bool ldo_voltage; + unsigned long dcofreq_min; + unsigned long max_phy; +}; + +static const struct hdmi_phy_features *phy_feat; + void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s) { #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\ @@ -26,53 +37,104 @@ void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s) DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL); DUMPPHY(HDMI_TXPHY_POWER_CTRL); DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL); + if (phy_feat->bist_ctrl) + DUMPPHY(HDMI_TXPHY_BIST_CONTROL); } -static irqreturn_t hdmi_irq_handler(int irq, void *data) +int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes) { - struct hdmi_wp_data *wp = data; - u32 irqstatus; - - irqstatus = hdmi_wp_get_irqstatus(wp); - hdmi_wp_set_irqstatus(wp, irqstatus); - - if ((irqstatus & HDMI_IRQ_LINK_CONNECT) && - irqstatus & HDMI_IRQ_LINK_DISCONNECT) { - /* - * If we get both connect and disconnect interrupts at the same - * time, turn off the PHY, clear interrupts, and restart, which - * raises connect interrupt if a cable is connected, or nothing - * if cable is not connected. - */ - hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); - - hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | - HDMI_IRQ_LINK_DISCONNECT); - - hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); - } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) { - hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); - } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) { - hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); + int i; + + for (i = 0; i < 8; i += 2) { + u8 lane, pol; + int dx, dy; + + dx = lanes[i]; + dy = lanes[i + 1]; + + if (dx < 0 || dx >= 8) + return -EINVAL; + + if (dy < 0 || dy >= 8) + return -EINVAL; + + if (dx & 1) { + if (dy != dx - 1) + return -EINVAL; + pol = 1; + } else { + if (dy != dx + 1) + return -EINVAL; + pol = 0; + } + + lane = dx / 2; + + phy->lane_function[lane] = i / 2; + phy->lane_polarity[lane] = pol; } - return IRQ_HANDLED; + return 0; } -int hdmi_phy_enable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp, - struct hdmi_config *cfg) +static void hdmi_phy_configure_lanes(struct hdmi_phy_data *phy) { - u16 r = 0; - u32 irqstatus; - - hdmi_wp_clear_irqenable(wp, 0xffffffff); - - irqstatus = hdmi_wp_get_irqstatus(wp); - hdmi_wp_set_irqstatus(wp, irqstatus); + static const u16 pad_cfg_list[] = { + 0x0123, + 0x0132, + 0x0312, + 0x0321, + 0x0231, + 0x0213, + 0x1023, + 0x1032, + 0x3012, + 0x3021, + 0x2031, + 0x2013, + 0x1203, + 0x1302, + 0x3102, + 0x3201, + 0x2301, + 0x2103, + 0x1230, + 0x1320, + 0x3120, + 0x3210, + 0x2310, + 0x2130, + }; + + u16 lane_cfg = 0; + int i; + unsigned lane_cfg_val; + u16 pol_val = 0; + + for (i = 0; i < 4; ++i) + lane_cfg |= phy->lane_function[i] << ((3 - i) * 4); + + pol_val |= phy->lane_polarity[0] << 0; + pol_val |= phy->lane_polarity[1] << 3; + pol_val |= phy->lane_polarity[2] << 2; + pol_val |= phy->lane_polarity[3] << 1; + + for (i = 0; i < ARRAY_SIZE(pad_cfg_list); ++i) + if (pad_cfg_list[i] == lane_cfg) + break; + + if (WARN_ON(i == ARRAY_SIZE(pad_cfg_list))) + i = 0; + + lane_cfg_val = i; + + REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22); + REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27); +} - r = hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); - if (r) - return r; +int hdmi_phy_configure(struct hdmi_phy_data *phy, struct hdmi_config *cfg) +{ + u8 freqout; /* * Read address 0 in order to get the SCP reset done completed @@ -81,79 +143,112 @@ int hdmi_phy_enable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp, hdmi_read_reg(phy->base, HDMI_TXPHY_TX_CTRL); /* + * In OMAP5+, the HFBITCLK must be divided by 2 before issuing the + * HDMI_PHYPWRCMD_LDOON command. + */ + if (phy_feat->bist_ctrl) + REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11); + + if (phy_feat->calc_freqout) { + /* DCOCLK/10 is pixel clock, compare pclk with DCOCLK_MIN/10 */ + u32 dco_min = phy_feat->dcofreq_min / 10; + u32 pclk = cfg->timings.pixelclock; + + if (pclk < dco_min) + freqout = 0; + else if ((pclk >= dco_min) && (pclk < phy_feat->max_phy)) + freqout = 1; + else + freqout = 2; + } else { + freqout = 1; + } + + /* * Write to phy address 0 to configure the clock * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field */ - REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30); + REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30); /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */ hdmi_write_reg(phy->base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000); /* Setup max LDO voltage */ - REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); + if (phy_feat->ldo_voltage) + REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); - /* Write to phy address 3 to change the polarity control */ - REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27); - - r = request_threaded_irq(phy->irq, NULL, hdmi_irq_handler, - IRQF_ONESHOT, "OMAP HDMI", wp); - if (r) { - DSSERR("HDMI IRQ request failed\n"); - hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); - return r; - } - - hdmi_wp_set_irqenable(wp, - HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT); + hdmi_phy_configure_lanes(phy); return 0; } -void hdmi_phy_disable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp) +static const struct hdmi_phy_features omap44xx_phy_feats = { + .bist_ctrl = false, + .calc_freqout = false, + .ldo_voltage = true, + .dcofreq_min = 500000000, + .max_phy = 185675000, +}; + +static const struct hdmi_phy_features omap54xx_phy_feats = { + .bist_ctrl = true, + .calc_freqout = true, + .ldo_voltage = false, + .dcofreq_min = 750000000, + .max_phy = 186000000, +}; + +static int hdmi_phy_init_features(struct platform_device *pdev) { - free_irq(phy->irq, wp); + struct hdmi_phy_features *dst; + const struct hdmi_phy_features *src; - hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); -} + dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL); + if (!dst) { + dev_err(&pdev->dev, "Failed to allocate HDMI PHY Features\n"); + return -ENOMEM; + } + + switch (omapdss_get_version()) { + case OMAPDSS_VER_OMAP4430_ES1: + case OMAPDSS_VER_OMAP4430_ES2: + case OMAPDSS_VER_OMAP4: + src = &omap44xx_phy_feats; + break; -#define PHY_OFFSET 0x300 -#define PHY_SIZE 0x100 + case OMAPDSS_VER_OMAP5: + src = &omap54xx_phy_feats; + break; + + default: + return -ENODEV; + } + + memcpy(dst, src, sizeof(*dst)); + phy_feat = dst; + + return 0; +} int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy) { + int r; struct resource *res; - struct resource temp_res; + + r = hdmi_phy_init_features(pdev); + if (r) + return r; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); if (!res) { - DSSDBG("can't get PHY mem resource by name\n"); - /* - * if hwmod/DT doesn't have the memory resource information - * split into HDMI sub blocks by name, we try again by getting - * the platform's first resource. this code will be removed when - * the driver can get the mem resources by name - */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - DSSERR("can't get PHY mem resource\n"); - return -EINVAL; - } - - temp_res.start = res->start + PHY_OFFSET; - temp_res.end = temp_res.start + PHY_SIZE - 1; - res = &temp_res; + DSSERR("can't get PHY mem resource\n"); + return -EINVAL; } - phy->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); - if (!phy->base) { + phy->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(phy->base)) { DSSERR("can't ioremap TX PHY\n"); - return -ENOMEM; - } - - phy->irq = platform_get_irq(pdev, 0); - if (phy->irq < 0) { - DSSERR("platform_get_irq failed\n"); - return -ENODEV; + return PTR_ERR(phy->base); } return 0; diff --git a/drivers/video/fbdev/omap2/dss/hdmi_pll.c b/drivers/video/fbdev/omap2/dss/hdmi_pll.c index 5fc71215c30..54df12a8d74 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi_pll.c +++ b/drivers/video/fbdev/omap2/dss/hdmi_pll.c @@ -23,6 +23,18 @@ #define HDMI_DEFAULT_REGN 16 #define HDMI_DEFAULT_REGM2 1 +struct hdmi_pll_features { + bool sys_reset; + /* this is a hack, need to replace it with a better computation of M2 */ + bool bound_dcofreq; + unsigned long fint_min, fint_max; + u16 regm_max; + unsigned long dcofreq_low_min, dcofreq_low_max; + unsigned long dcofreq_high_min, dcofreq_high_max; +}; + +static const struct hdmi_pll_features *pll_feat; + void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s) { #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\ @@ -57,7 +69,11 @@ void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy) refclk = clkin / pi->regn; - pi->regm2 = HDMI_DEFAULT_REGM2; + /* temorary hack to make sure DCO freq isn't calculated too low */ + if (pll_feat->bound_dcofreq && phy <= 65000) + pi->regm2 = 3; + else + pi->regm2 = HDMI_DEFAULT_REGM2; /* * multiplier is pixel_clk/ref_clk @@ -154,7 +170,7 @@ static int hdmi_pll_config(struct hdmi_pll_data *pll) static int hdmi_pll_reset(struct hdmi_pll_data *pll) { /* SYSRESET controlled by power FSM */ - REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, 0x0, 3, 3); + REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, pll_feat->sys_reset, 3, 3); /* READ 0x0 reset is in progress */ if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_STATUS, 0, 0, 1) @@ -194,38 +210,81 @@ void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp) hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); } -#define PLL_OFFSET 0x200 -#define PLL_SIZE 0x100 +static const struct hdmi_pll_features omap44xx_pll_feats = { + .sys_reset = false, + .bound_dcofreq = false, + .fint_min = 500000, + .fint_max = 2500000, + .regm_max = 4095, + .dcofreq_low_min = 500000000, + .dcofreq_low_max = 1000000000, + .dcofreq_high_min = 1000000000, + .dcofreq_high_max = 2000000000, +}; + +static const struct hdmi_pll_features omap54xx_pll_feats = { + .sys_reset = true, + .bound_dcofreq = true, + .fint_min = 620000, + .fint_max = 2500000, + .regm_max = 2046, + .dcofreq_low_min = 750000000, + .dcofreq_low_max = 1500000000, + .dcofreq_high_min = 1250000000, + .dcofreq_high_max = 2500000000UL, +}; + +static int hdmi_pll_init_features(struct platform_device *pdev) +{ + struct hdmi_pll_features *dst; + const struct hdmi_pll_features *src; + + dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL); + if (!dst) { + dev_err(&pdev->dev, "Failed to allocate HDMI PHY Features\n"); + return -ENOMEM; + } + + switch (omapdss_get_version()) { + case OMAPDSS_VER_OMAP4430_ES1: + case OMAPDSS_VER_OMAP4430_ES2: + case OMAPDSS_VER_OMAP4: + src = &omap44xx_pll_feats; + break; + + case OMAPDSS_VER_OMAP5: + src = &omap54xx_pll_feats; + break; + + default: + return -ENODEV; + } + + memcpy(dst, src, sizeof(*dst)); + pll_feat = dst; + + return 0; +} int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll) { + int r; struct resource *res; - struct resource temp_res; + + r = hdmi_pll_init_features(pdev); + if (r) + return r; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll"); if (!res) { - DSSDBG("can't get PLL mem resource by name\n"); - /* - * if hwmod/DT doesn't have the memory resource information - * split into HDMI sub blocks by name, we try again by getting - * the platform's first resource. this code will be removed when - * the driver can get the mem resources by name - */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - DSSERR("can't get PLL mem resource\n"); - return -EINVAL; - } - - temp_res.start = res->start + PLL_OFFSET; - temp_res.end = temp_res.start + PLL_SIZE - 1; - res = &temp_res; + DSSERR("can't get PLL mem resource\n"); + return -EINVAL; } - pll->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); - if (!pll->base) { + pll->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pll->base)) { DSSERR("can't ioremap PLLCTRL\n"); - return -ENOMEM; + return PTR_ERR(pll->base); } return 0; diff --git a/drivers/video/fbdev/omap2/dss/hdmi_wp.c b/drivers/video/fbdev/omap2/dss/hdmi_wp.c index f5f4ccf50d9..496327e2b21 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi_wp.c +++ b/drivers/video/fbdev/omap2/dss/hdmi_wp.c @@ -185,7 +185,7 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, timings->interlace = param->timings.interlace; } -#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) +#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || defined(CONFIG_OMAP5_DSS_HDMI_AUDIO) void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp, struct hdmi_audio_format *aud_fmt) { @@ -238,37 +238,20 @@ int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable) } #endif -#define WP_SIZE 0x200 - int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp) { struct resource *res; - struct resource temp_res; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wp"); if (!res) { - DSSDBG("can't get WP mem resource by name\n"); - /* - * if hwmod/DT doesn't have the memory resource information - * split into HDMI sub blocks by name, we try again by getting - * the platform's first resource. this code will be removed when - * the driver can get the mem resources by name - */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - DSSERR("can't get WP mem resource\n"); - return -EINVAL; - } - - temp_res.start = res->start; - temp_res.end = temp_res.start + WP_SIZE - 1; - res = &temp_res; + DSSERR("can't get WP mem resource\n"); + return -EINVAL; } - wp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); - if (!wp->base) { + wp->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(wp->base)) { DSSERR("can't ioremap HDMI WP\n"); - return -ENOMEM; + return PTR_ERR(wp->base); } return 0; diff --git a/drivers/video/fbdev/omap2/dss/omapdss-boot-init.c b/drivers/video/fbdev/omap2/dss/omapdss-boot-init.c new file mode 100644 index 00000000000..99af9e88b2d --- /dev/null +++ b/drivers/video/fbdev/omap2/dss/omapdss-boot-init.c @@ -0,0 +1,229 @@ +/* + * Copyright (C) 2014 Texas Instruments + * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * As omapdss panel drivers are omapdss specific, but we want to define the + * DT-data in generic manner, we convert the compatible strings of the panel and + * encoder nodes from "panel-foo" to "omapdss,panel-foo". This way we can have + * both correct DT data and omapdss specific drivers. + * + * When we get generic panel drivers to the kernel, this file will be removed. + */ + +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/of_graph.h> +#include <linux/slab.h> +#include <linux/list.h> + +static struct list_head dss_conv_list __initdata; + +static const char prefix[] __initconst = "omapdss,"; + +struct dss_conv_node { + struct list_head list; + struct device_node *node; + bool root; +}; + +static int __init omapdss_count_strings(const struct property *prop) +{ + const char *p = prop->value; + int l = 0, total = 0; + int i; + + for (i = 0; total < prop->length; total += l, p += l, i++) + l = strlen(p) + 1; + + return i; +} + +static void __init omapdss_update_prop(struct device_node *node, char *compat, + int len) +{ + struct property *prop; + + prop = kzalloc(sizeof(*prop), GFP_KERNEL); + if (!prop) + return; + + prop->name = "compatible"; + prop->value = compat; + prop->length = len; + + of_update_property(node, prop); +} + +static void __init omapdss_prefix_strcpy(char *dst, int dst_len, + const char *src, int src_len) +{ + size_t total = 0; + + while (total < src_len) { + size_t l = strlen(src) + 1; + + strcpy(dst, prefix); + dst += strlen(prefix); + + strcpy(dst, src); + dst += l; + + src += l; + total += l; + } +} + +/* prepend compatible property strings with "omapdss," */ +static void __init omapdss_omapify_node(struct device_node *node) +{ + struct property *prop; + char *new_compat; + int num_strs; + int new_len; + + prop = of_find_property(node, "compatible", NULL); + + if (!prop || !prop->value) + return; + + if (strnlen(prop->value, prop->length) >= prop->length) + return; + + /* is it already prefixed? */ + if (strncmp(prefix, prop->value, strlen(prefix)) == 0) + return; + + num_strs = omapdss_count_strings(prop); + + new_len = prop->length + strlen(prefix) * num_strs; + new_compat = kmalloc(new_len, GFP_KERNEL); + + omapdss_prefix_strcpy(new_compat, new_len, prop->value, prop->length); + + omapdss_update_prop(node, new_compat, new_len); +} + +static void __init omapdss_add_to_list(struct device_node *node, bool root) +{ + struct dss_conv_node *n = kmalloc(sizeof(struct dss_conv_node), + GFP_KERNEL); + n->node = node; + n->root = root; + list_add(&n->list, &dss_conv_list); +} + +static bool __init omapdss_list_contains(const struct device_node *node) +{ + struct dss_conv_node *n; + + list_for_each_entry(n, &dss_conv_list, list) { + if (n->node == node) + return true; + } + + return false; +} + +static void __init omapdss_walk_device(struct device_node *node, bool root) +{ + struct device_node *n; + + omapdss_add_to_list(node, root); + + /* + * of_graph_get_remote_port_parent() prints an error if there is no + * port/ports node. To avoid that, check first that there's the node. + */ + n = of_get_child_by_name(node, "ports"); + if (!n) + n = of_get_child_by_name(node, "port"); + if (!n) + return; + + of_node_put(n); + + n = NULL; + while ((n = of_graph_get_next_endpoint(node, n)) != NULL) { + struct device_node *pn; + + pn = of_graph_get_remote_port_parent(n); + + if (!pn) { + of_node_put(n); + continue; + } + + if (!of_device_is_available(pn) || omapdss_list_contains(pn)) { + of_node_put(pn); + of_node_put(n); + continue; + } + + omapdss_walk_device(pn, false); + + of_node_put(n); + } +} + +static const struct of_device_id omapdss_of_match[] __initconst = { + { .compatible = "ti,omap2-dss", }, + { .compatible = "ti,omap3-dss", }, + { .compatible = "ti,omap4-dss", }, + { .compatible = "ti,omap5-dss", }, + {}, +}; + +static int __init omapdss_boot_init(void) +{ + struct device_node *dss, *child; + + INIT_LIST_HEAD(&dss_conv_list); + + dss = of_find_matching_node(NULL, omapdss_of_match); + + if (dss == NULL || !of_device_is_available(dss)) + return 0; + + omapdss_walk_device(dss, true); + + for_each_available_child_of_node(dss, child) { + if (!of_find_property(child, "compatible", NULL)) { + of_node_put(child); + continue; + } + + omapdss_walk_device(child, true); + } + + while (!list_empty(&dss_conv_list)) { + struct dss_conv_node *n; + + n = list_first_entry(&dss_conv_list, struct dss_conv_node, + list); + + if (!n->root) + omapdss_omapify_node(n->node); + + list_del(&n->list); + of_node_put(n->node); + kfree(n); + } + + return 0; +} + +subsys_initcall(omapdss_boot_init); diff --git a/drivers/video/fbdev/omap2/dss/venc_panel.c b/drivers/video/fbdev/omap2/dss/venc_panel.c deleted file mode 100644 index af68cd444d7..00000000000 --- a/drivers/video/fbdev/omap2/dss/venc_panel.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Copyright (C) 2009 Nokia Corporation - * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> - * - * VENC panel driver - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <linux/kernel.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/mutex.h> -#include <linux/module.h> - -#include <video/omapdss.h> - -#include "dss.h" - -static struct { - struct mutex lock; -} venc_panel; - -static ssize_t display_output_type_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct omap_dss_device *dssdev = to_dss_device(dev); - const char *ret; - - switch (dssdev->phy.venc.type) { - case OMAP_DSS_VENC_TYPE_COMPOSITE: - ret = "composite"; - break; - case OMAP_DSS_VENC_TYPE_SVIDEO: - ret = "svideo"; - break; - default: - return -EINVAL; - } - - return snprintf(buf, PAGE_SIZE, "%s\n", ret); -} - -static ssize_t display_output_type_store(struct device *dev, - struct device_attribute *attr, const char *buf, size_t size) -{ - struct omap_dss_device *dssdev = to_dss_device(dev); - enum omap_dss_venc_type new_type; - - if (sysfs_streq("composite", buf)) - new_type = OMAP_DSS_VENC_TYPE_COMPOSITE; - else if (sysfs_streq("svideo", buf)) - new_type = OMAP_DSS_VENC_TYPE_SVIDEO; - else - return -EINVAL; - - mutex_lock(&venc_panel.lock); - - if (dssdev->phy.venc.type != new_type) { - dssdev->phy.venc.type = new_type; - omapdss_venc_set_type(dssdev, new_type); - if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { - omapdss_venc_display_disable(dssdev); - omapdss_venc_display_enable(dssdev); - } - } - - mutex_unlock(&venc_panel.lock); - - return size; -} - -static DEVICE_ATTR(output_type, S_IRUGO | S_IWUSR, - display_output_type_show, display_output_type_store); - -static int venc_panel_probe(struct omap_dss_device *dssdev) -{ - /* set default timings to PAL */ - const struct omap_video_timings default_timings = { - .x_res = 720, - .y_res = 574, - .pixelclock = 13500000, - .hsw = 64, - .hfp = 12, - .hbp = 68, - .vsw = 5, - .vfp = 5, - .vbp = 41, - - .vsync_level = OMAPDSS_SIG_ACTIVE_HIGH, - .hsync_level = OMAPDSS_SIG_ACTIVE_HIGH, - - .interlace = true, - }; - - mutex_init(&venc_panel.lock); - - dssdev->panel.timings = default_timings; - - return device_create_file(dssdev->dev, &dev_attr_output_type); -} - -static void venc_panel_remove(struct omap_dss_device *dssdev) -{ - device_remove_file(dssdev->dev, &dev_attr_output_type); -} - -static int venc_panel_enable(struct omap_dss_device *dssdev) -{ - int r; - - dev_dbg(dssdev->dev, "venc_panel_enable\n"); - - mutex_lock(&venc_panel.lock); - - if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) { - r = -EINVAL; - goto err; - } - - omapdss_venc_set_timings(dssdev, &dssdev->panel.timings); - omapdss_venc_set_type(dssdev, dssdev->phy.venc.type); - omapdss_venc_invert_vid_out_polarity(dssdev, - dssdev->phy.venc.invert_polarity); - - r = omapdss_venc_display_enable(dssdev); - if (r) - goto err; - - dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; - - mutex_unlock(&venc_panel.lock); - - return 0; -err: - mutex_unlock(&venc_panel.lock); - - return r; -} - -static void venc_panel_disable(struct omap_dss_device *dssdev) -{ - dev_dbg(dssdev->dev, "venc_panel_disable\n"); - - mutex_lock(&venc_panel.lock); - - if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED) - goto end; - - omapdss_venc_display_disable(dssdev); - - dssdev->state = OMAP_DSS_DISPLAY_DISABLED; -end: - mutex_unlock(&venc_panel.lock); -} - -static void venc_panel_set_timings(struct omap_dss_device *dssdev, - struct omap_video_timings *timings) -{ - dev_dbg(dssdev->dev, "venc_panel_set_timings\n"); - - mutex_lock(&venc_panel.lock); - - omapdss_venc_set_timings(dssdev, timings); - dssdev->panel.timings = *timings; - - mutex_unlock(&venc_panel.lock); -} - -static int venc_panel_check_timings(struct omap_dss_device *dssdev, - struct omap_video_timings *timings) -{ - dev_dbg(dssdev->dev, "venc_panel_check_timings\n"); - - return omapdss_venc_check_timings(dssdev, timings); -} - -static u32 venc_panel_get_wss(struct omap_dss_device *dssdev) -{ - dev_dbg(dssdev->dev, "venc_panel_get_wss\n"); - - return omapdss_venc_get_wss(dssdev); -} - -static int venc_panel_set_wss(struct omap_dss_device *dssdev, u32 wss) -{ - dev_dbg(dssdev->dev, "venc_panel_set_wss\n"); - - return omapdss_venc_set_wss(dssdev, wss); -} - -static struct omap_dss_driver venc_driver = { - .probe = venc_panel_probe, - .remove = venc_panel_remove, - - .enable = venc_panel_enable, - .disable = venc_panel_disable, - - .get_resolution = omapdss_default_get_resolution, - .get_recommended_bpp = omapdss_default_get_recommended_bpp, - - .set_timings = venc_panel_set_timings, - .check_timings = venc_panel_check_timings, - - .get_wss = venc_panel_get_wss, - .set_wss = venc_panel_set_wss, - - .driver = { - .name = "venc", - .owner = THIS_MODULE, - }, -}; - -int venc_panel_init(void) -{ - return omap_dss_register_driver(&venc_driver); -} - -void venc_panel_exit(void) -{ - omap_dss_unregister_driver(&venc_driver); -} diff --git a/drivers/video/fbdev/pxa3xx-gcu.c b/drivers/video/fbdev/pxa3xx-gcu.c index 417f9a27eb7..4df3657fe22 100644 --- a/drivers/video/fbdev/pxa3xx-gcu.c +++ b/drivers/video/fbdev/pxa3xx-gcu.c @@ -612,11 +612,9 @@ static int pxa3xx_gcu_probe(struct platform_device *pdev) /* handle IO resources */ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->mmio_base = devm_request_and_ioremap(dev, r); - if (IS_ERR(priv->mmio_base)) { - dev_err(dev, "failed to map I/O memory\n"); + priv->mmio_base = devm_ioremap_resource(dev, r); + if (IS_ERR(priv->mmio_base)) return PTR_ERR(priv->mmio_base); - } /* enable the clock */ priv->clk = devm_clk_get(dev, NULL); diff --git a/drivers/video/fbdev/s3fb.c b/drivers/video/fbdev/s3fb.c index 9a3f8f1c6aa..c43b969e1e2 100644 --- a/drivers/video/fbdev/s3fb.c +++ b/drivers/video/fbdev/s3fb.c @@ -1401,9 +1401,10 @@ err_enable_device: static void s3_pci_remove(struct pci_dev *dev) { struct fb_info *info = pci_get_drvdata(dev); - struct s3fb_info __maybe_unused *par = info->par; + struct s3fb_info __maybe_unused *par; if (info) { + par = info->par; #ifdef CONFIG_MTRR if (par->mtrr_reg >= 0) { diff --git a/drivers/video/fbdev/sm501fb.c b/drivers/video/fbdev/sm501fb.c index 1501979099d..c2c8eb66878 100644 --- a/drivers/video/fbdev/sm501fb.c +++ b/drivers/video/fbdev/sm501fb.c @@ -1215,7 +1215,7 @@ static ssize_t sm501fb_crtsrc_store(struct device *dev, } /* Prepare the device_attr for registration with sysfs later */ -static DEVICE_ATTR(crt_src, 0666, sm501fb_crtsrc_show, sm501fb_crtsrc_store); +static DEVICE_ATTR(crt_src, 0664, sm501fb_crtsrc_show, sm501fb_crtsrc_store); /* sm501fb_show_regs * diff --git a/drivers/video/fbdev/wm8505fb.c b/drivers/video/fbdev/wm8505fb.c index 537d199612a..d2fafbbcd7f 100644 --- a/drivers/video/fbdev/wm8505fb.c +++ b/drivers/video/fbdev/wm8505fb.c @@ -162,7 +162,7 @@ static ssize_t contrast_show(struct device *dev, struct fb_info *info = dev_get_drvdata(dev); struct wm8505fb_info *fbi = to_wm8505fb_info(info); - return sprintf(buf, "%d\n", fbi->contrast); + return sprintf(buf, "%u\n", fbi->contrast); } static ssize_t contrast_store(struct device *dev, diff --git a/drivers/video/of_display_timing.c b/drivers/video/of_display_timing.c index ba5b40f581f..987edf11003 100644 --- a/drivers/video/of_display_timing.c +++ b/drivers/video/of_display_timing.c @@ -115,10 +115,8 @@ int of_get_display_timing(struct device_node *np, const char *name, { struct device_node *timing_np; - if (!np) { - pr_err("%s: no devicenode given\n", of_node_full_name(np)); + if (!np) return -EINVAL; - } timing_np = of_get_child_by_name(np, name); if (!timing_np) { @@ -142,10 +140,8 @@ struct display_timings *of_get_display_timings(struct device_node *np) struct device_node *native_mode; struct display_timings *disp; - if (!np) { - pr_err("%s: no device node given\n", of_node_full_name(np)); + if (!np) return NULL; - } timings_np = of_get_child_by_name(np, "display-timings"); if (!timings_np) { @@ -164,7 +160,7 @@ struct display_timings *of_get_display_timings(struct device_node *np) entry = of_parse_phandle(timings_np, "native-mode", 0); /* assume first child as native mode if none provided */ if (!entry) - entry = of_get_next_child(np, NULL); + entry = of_get_next_child(timings_np, NULL); /* if there is no child, it is useless to go on */ if (!entry) { pr_err("%s: no timing specifications given\n", |