diff options
Diffstat (limited to 'drivers')
65 files changed, 8106 insertions, 6536 deletions
diff --git a/drivers/block/xsysace.c b/drivers/block/xsysace.c index 78ebfffc77e..4a7a059ebaf 100644 --- a/drivers/block/xsysace.c +++ b/drivers/block/xsysace.c @@ -1202,8 +1202,10 @@ static int __devexit ace_of_remove(struct of_device *op) } /* Match table for of_platform binding */ -static struct of_device_id __devinit ace_of_match[] = { - { .compatible = "xilinx,xsysace", }, +static struct of_device_id ace_of_match[] __devinitdata = { + { .compatible = "xlnx,opb-sysace-1.00.b", }, + { .compatible = "xlnx,opb-sysace-1.00.c", }, + { .compatible = "xlnx,xps-sysace-1.00.a", }, {}, }; MODULE_DEVICE_TABLE(of, ace_of_match); diff --git a/drivers/cdrom/viocd.c b/drivers/cdrom/viocd.c index 8473b9f1da9..cac06bc1754 100644 --- a/drivers/cdrom/viocd.c +++ b/drivers/cdrom/viocd.c @@ -558,7 +558,7 @@ static struct cdrom_device_ops viocd_dops = { .capability = CDC_CLOSE_TRAY | CDC_OPEN_TRAY | CDC_LOCK | CDC_SELECT_SPEED | CDC_SELECT_DISC | CDC_MULTI_SESSION | CDC_MCN | CDC_MEDIA_CHANGED | CDC_PLAY_AUDIO | CDC_RESET | CDC_DRIVE_STATUS | CDC_GENERIC_PACKET | CDC_CD_R | CDC_CD_RW | CDC_DVD | CDC_DVD_R | CDC_DVD_RAM | CDC_RAM }; -static int __init find_capability(const char *type) +static int find_capability(const char *type) { struct capability_entry *entry; diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig index 85bf9b2aa74..f01ac9a07bf 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig @@ -194,17 +194,6 @@ config MOXA_INTELLIO module will be called moxa. config MOXA_SMARTIO - tristate "Moxa SmartIO support (OBSOLETE)" - depends on SERIAL_NONSTANDARD - help - Say Y here if you have a Moxa SmartIO multiport serial card. - - This driver can also be built as a module ( = code which can be - inserted in and removed from the running kernel whenever you want). - The module will be called mxser. If you want to do that, say M - here. - -config MOXA_SMARTIO_NEW tristate "Moxa SmartIO support v. 2.0" depends on SERIAL_NONSTANDARD && (PCI || EISA || ISA) help @@ -215,7 +204,7 @@ config MOXA_SMARTIO_NEW changes finally resulting in PCI probing. This driver can also be built as a module. The module will be called - mxser_new. If you want to do that, say M here. + mxser. If you want to do that, say M here. config ISI tristate "Multi-Tech multiport card support (EXPERIMENTAL)" @@ -841,6 +830,16 @@ config DTLK To compile this driver as a module, choose M here: the module will be called dtlk. +config XILINX_HWICAP + tristate "Xilinx HWICAP Support" + depends on XILINX_VIRTEX + help + This option enables support for Xilinx Internal Configuration + Access Port (ICAP) driver. The ICAP is used on Xilinx Virtex + FPGA platforms to partially reconfigure the FPGA at runtime. + + If unsure, say N. + config R3964 tristate "Siemens R3964 line discipline" ---help--- diff --git a/drivers/char/Makefile b/drivers/char/Makefile index 96fc01eddef..5407b761561 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile @@ -33,7 +33,6 @@ obj-$(CONFIG_MOXA_INTELLIO) += moxa.o obj-$(CONFIG_A2232) += ser_a2232.o generic_serial.o obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o obj-$(CONFIG_MOXA_SMARTIO) += mxser.o -obj-$(CONFIG_MOXA_SMARTIO_NEW) += mxser_new.o obj-$(CONFIG_COMPUTONE) += ip2/ obj-$(CONFIG_RISCOM8) += riscom8.o obj-$(CONFIG_ISI) += isicom.o @@ -77,6 +76,7 @@ obj-$(CONFIG_EFI_RTC) += efirtc.o obj-$(CONFIG_SGI_DS1286) += ds1286.o obj-$(CONFIG_SGI_IP27_RTC) += ip27-rtc.o obj-$(CONFIG_DS1302) += ds1302.o +obj-$(CONFIG_XILINX_HWICAP) += xilinx_hwicap/ ifeq ($(CONFIG_GENERIC_NVRAM),y) obj-$(CONFIG_NVRAM) += generic_nvram.o else diff --git a/drivers/char/epca.h b/drivers/char/epca.h index a297238cd3b..3c77c02b5d6 100644 --- a/drivers/char/epca.h +++ b/drivers/char/epca.h @@ -77,7 +77,6 @@ static char *board_desc[] = #define ON 1 #define FEPTIMEOUT 200000 -#define SERIAL_TYPE_NORMAL 1 #define SERIAL_TYPE_INFO 3 #define EPCA_EVENT_HANGUP 1 #define EPCA_MAGIC 0x5c6df104L diff --git a/drivers/char/esp.c b/drivers/char/esp.c index 28607763ae6..c01e26d9ee5 100644 --- a/drivers/char/esp.c +++ b/drivers/char/esp.c @@ -111,9 +111,6 @@ static char serial_version[] __initdata = "2.2"; static struct tty_driver *esp_driver; -/* serial subtype definitions */ -#define SERIAL_TYPE_NORMAL 1 - /* * Serial driver configuration section. Here are the various options: * @@ -245,17 +242,6 @@ static void rs_start(struct tty_struct *tty) * ----------------------------------------------------------------------- */ -/* - * This routine is used by the interrupt handler to schedule - * processing in the software interrupt portion of the driver. - */ -static inline void rs_sched_event(struct esp_struct *info, - int event) -{ - info->event |= 1 << event; - schedule_work(&info->tqueue); -} - static DEFINE_SPINLOCK(pio_lock); static inline struct esp_pio_buffer *get_pio_buffer(void) @@ -477,7 +463,8 @@ static inline void transmit_chars_pio(struct esp_struct *info, } if (info->xmit_cnt < WAKEUP_CHARS) { - rs_sched_event(info, ESP_EVENT_WRITE_WAKEUP); + if (info->tty) + tty_wakeup(info->tty); #ifdef SERIAL_DEBUG_INTR printk("THRE..."); @@ -515,7 +502,8 @@ static inline void transmit_chars_dma(struct esp_struct *info, int num_bytes) info->xmit_tail = (info->xmit_tail + dma_bytes) & (ESP_XMIT_SIZE - 1); if (info->xmit_cnt < WAKEUP_CHARS) { - rs_sched_event(info, ESP_EVENT_WRITE_WAKEUP); + if (info->tty) + tty_wakeup(info->tty); #ifdef SERIAL_DEBUG_INTR printk("THRE..."); @@ -607,7 +595,7 @@ static inline void check_modem_status(struct esp_struct *info) #ifdef SERIAL_DEBUG_OPEN printk("scheduling hangup..."); #endif - schedule_work(&info->tqueue_hangup); + tty_hangup(info->tty); } } } @@ -723,41 +711,6 @@ static irqreturn_t rs_interrupt_single(int irq, void *dev_id) * ------------------------------------------------------------------- */ -static void do_softint(struct work_struct *work) -{ - struct esp_struct *info = - container_of(work, struct esp_struct, tqueue); - struct tty_struct *tty; - - tty = info->tty; - if (!tty) - return; - - if (test_and_clear_bit(ESP_EVENT_WRITE_WAKEUP, &info->event)) { - tty_wakeup(tty); - } -} - -/* - * This routine is called from the scheduler tqueue when the interrupt - * routine has signalled that a hangup has occurred. The path of - * hangup processing is: - * - * serial interrupt routine -> (scheduler tqueue) -> - * do_serial_hangup() -> tty->hangup() -> esp_hangup() - * - */ -static void do_serial_hangup(struct work_struct *work) -{ - struct esp_struct *info = - container_of(work, struct esp_struct, tqueue_hangup); - struct tty_struct *tty; - - tty = info->tty; - if (tty) - tty_hangup(tty); -} - /* * --------------------------------------------------------------- * Low level utility subroutines for the serial driver: routines to @@ -2041,7 +1994,6 @@ static void rs_close(struct tty_struct *tty, struct file * filp) tty->driver->flush_buffer(tty); tty_ldisc_flush(tty); tty->closing = 0; - info->event = 0; info->tty = NULL; if (info->blocked_open) { @@ -2109,7 +2061,6 @@ static void esp_hangup(struct tty_struct *tty) rs_flush_buffer(tty); shutdown(info); - info->event = 0; info->count = 0; info->flags &= ~ASYNC_NORMAL_ACTIVE; info->tty = NULL; @@ -2495,8 +2446,6 @@ static int __init espserial_init(void) info->magic = ESP_MAGIC; info->close_delay = 5*HZ/10; info->closing_wait = 30*HZ; - INIT_WORK(&info->tqueue, do_softint); - INIT_WORK(&info->tqueue_hangup, do_serial_hangup); info->config.rx_timeout = rx_timeout; info->config.flow_on = flow_on; info->config.flow_off = flow_off; diff --git a/drivers/char/i8k.c b/drivers/char/i8k.c index 179223a1741..8609b8236c6 100644 --- a/drivers/char/i8k.c +++ b/drivers/char/i8k.c @@ -113,6 +113,33 @@ static int i8k_smm(struct smm_regs *regs) int rc; int eax = regs->eax; +#if defined(CONFIG_X86_64) + asm("pushq %%rax\n\t" + "movl 0(%%rax),%%edx\n\t" + "pushq %%rdx\n\t" + "movl 4(%%rax),%%ebx\n\t" + "movl 8(%%rax),%%ecx\n\t" + "movl 12(%%rax),%%edx\n\t" + "movl 16(%%rax),%%esi\n\t" + "movl 20(%%rax),%%edi\n\t" + "popq %%rax\n\t" + "out %%al,$0xb2\n\t" + "out %%al,$0x84\n\t" + "xchgq %%rax,(%%rsp)\n\t" + "movl %%ebx,4(%%rax)\n\t" + "movl %%ecx,8(%%rax)\n\t" + "movl %%edx,12(%%rax)\n\t" + "movl %%esi,16(%%rax)\n\t" + "movl %%edi,20(%%rax)\n\t" + "popq %%rdx\n\t" + "movl %%edx,0(%%rax)\n\t" + "lahf\n\t" + "shrl $8,%%eax\n\t" + "andl $1,%%eax\n" + :"=a"(rc) + : "a"(regs) + : "%ebx", "%ecx", "%edx", "%esi", "%edi", "memory"); +#else asm("pushl %%eax\n\t" "movl 0(%%eax),%%edx\n\t" "push %%edx\n\t" @@ -137,7 +164,7 @@ static int i8k_smm(struct smm_regs *regs) "andl $1,%%eax\n":"=a"(rc) : "a"(regs) : "%ebx", "%ecx", "%edx", "%esi", "%edi", "memory"); - +#endif if (rc != 0 || (regs->eax & 0xffff) == 0xffff || regs->eax == eax) return -EINVAL; @@ -446,6 +473,13 @@ static struct dmi_system_id __initdata i8k_dmi_table[] = { DMI_MATCH(DMI_PRODUCT_NAME, "MM061"), }, }, + { + .ident = "Dell Inspiron 3", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "MP061"), + }, + }, { } }; diff --git a/drivers/char/ip2/ip2main.c b/drivers/char/ip2/ip2main.c index 0f49ccf02a7..b1d6cad8428 100644 --- a/drivers/char/ip2/ip2main.c +++ b/drivers/char/ip2/ip2main.c @@ -153,9 +153,6 @@ static char *pcVersion = "1.2.14"; static char *pcDriver_name = "ip2"; static char *pcIpl = "ip2ipl"; -/* Serial subtype definitions */ -#define SERIAL_TYPE_NORMAL 1 - // cheezy kludge or genius - you decide? int ip2_loadmain(int *, int *, unsigned char *, int); static unsigned char *Fip_firmware; diff --git a/drivers/char/istallion.c b/drivers/char/istallion.c index 1f27be1ec3d..c645455c3fd 100644 --- a/drivers/char/istallion.c +++ b/drivers/char/istallion.c @@ -627,7 +627,6 @@ static int stli_initopen(struct stlibrd *brdp, struct stliport *portp); static int stli_rawopen(struct stlibrd *brdp, struct stliport *portp, unsigned long arg, int wait); static int stli_rawclose(struct stlibrd *brdp, struct stliport *portp, unsigned long arg, int wait); static int stli_waitcarrier(struct stlibrd *brdp, struct stliport *portp, struct file *filp); -static void stli_dohangup(struct work_struct *); static int stli_setport(struct stliport *portp); static int stli_cmdwait(struct stlibrd *brdp, struct stliport *portp, unsigned long cmd, void *arg, int size, int copyback); static void stli_sendcmd(struct stlibrd *brdp, struct stliport *portp, unsigned long cmd, void *arg, int size, int copyback); @@ -1824,25 +1823,6 @@ static void stli_start(struct tty_struct *tty) /*****************************************************************************/ /* - * Scheduler called hang up routine. This is called from the scheduler, - * not direct from the driver "poll" routine. We can't call it there - * since the real local hangup code will enable/disable the board and - * other things that we can't do while handling the poll. Much easier - * to deal with it some time later (don't really care when, hangups - * aren't that time critical). - */ - -static void stli_dohangup(struct work_struct *ugly_api) -{ - struct stliport *portp = container_of(ugly_api, struct stliport, tqhangup); - if (portp->tty != NULL) { - tty_hangup(portp->tty); - } -} - -/*****************************************************************************/ - -/* * Hangup this port. This is pretty much like closing the port, only * a little more brutal. No waiting for data to drain. Shutdown the * port and maybe drop signals. This is rather tricky really. We want @@ -2405,7 +2385,7 @@ static int stli_hostcmd(struct stlibrd *brdp, struct stliport *portp) ((portp->sigs & TIOCM_CD) == 0)) { if (portp->flags & ASYNC_CHECK_CD) { if (tty) - schedule_work(&portp->tqhangup); + tty_hangup(tty); } } } @@ -2733,7 +2713,6 @@ static int stli_initports(struct stlibrd *brdp) portp->baud_base = STL_BAUDBASE; portp->close_delay = STL_CLOSEDELAY; portp->closing_wait = 30 * HZ; - INIT_WORK(&portp->tqhangup, stli_dohangup); init_waitqueue_head(&portp->open_wait); init_waitqueue_head(&portp->close_wait); init_waitqueue_head(&portp->raw_wait); diff --git a/drivers/char/mbcs.c b/drivers/char/mbcs.c index 3c5802ae171..f4716ad7348 100644 --- a/drivers/char/mbcs.c +++ b/drivers/char/mbcs.c @@ -23,6 +23,7 @@ #include <linux/device.h> #include <linux/mm.h> #include <linux/uio.h> +#include <linux/mutex.h> #include <asm/io.h> #include <asm/uaccess.h> #include <asm/system.h> @@ -281,7 +282,7 @@ static inline int mbcs_algo_start(struct mbcs_soft *soft) void *mmr_base = soft->mmr_base; union cm_control cm_control; - if (down_interruptible(&soft->algolock)) + if (mutex_lock_interruptible(&soft->algolock)) return -ERESTARTSYS; atomic_set(&soft->algo_done, 0); @@ -298,7 +299,7 @@ static inline int mbcs_algo_start(struct mbcs_soft *soft) cm_control.alg_go = 1; MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg); - up(&soft->algolock); + mutex_unlock(&soft->algolock); return 0; } @@ -309,7 +310,7 @@ do_mbcs_sram_dmawrite(struct mbcs_soft *soft, uint64_t hostAddr, { int rv = 0; - if (down_interruptible(&soft->dmawritelock)) + if (mutex_lock_interruptible(&soft->dmawritelock)) return -ERESTARTSYS; atomic_set(&soft->dmawrite_done, 0); @@ -335,7 +336,7 @@ do_mbcs_sram_dmawrite(struct mbcs_soft *soft, uint64_t hostAddr, *off += len; dmawrite_exit: - up(&soft->dmawritelock); + mutex_unlock(&soft->dmawritelock); return rv; } @@ -346,7 +347,7 @@ do_mbcs_sram_dmaread(struct mbcs_soft *soft, uint64_t hostAddr, { int rv = 0; - if (down_interruptible(&soft->dmareadlock)) + if (mutex_lock_interruptible(&soft->dmareadlock)) return -ERESTARTSYS; atomic_set(&soft->dmawrite_done, 0); @@ -371,7 +372,7 @@ do_mbcs_sram_dmaread(struct mbcs_soft *soft, uint64_t hostAddr, *off += len; dmaread_exit: - up(&soft->dmareadlock); + mutex_unlock(&soft->dmareadlock); return rv; } @@ -762,9 +763,9 @@ static int mbcs_probe(struct cx_dev *dev, const struct cx_device_id *id) init_waitqueue_head(&soft->dmaread_queue); init_waitqueue_head(&soft->algo_queue); - init_MUTEX(&soft->dmawritelock); - init_MUTEX(&soft->dmareadlock); - init_MUTEX(&soft->algolock); + mutex_init(&soft->dmawritelock); + mutex_init(&soft->dmareadlock); + mutex_init(&soft->algolock); mbcs_getdma_init(&soft->getdma); mbcs_putdma_init(&soft->putdma); diff --git a/drivers/char/mbcs.h b/drivers/char/mbcs.h index c9905a3c335..ba671589f4c 100644 --- a/drivers/char/mbcs.h +++ b/drivers/char/mbcs.h @@ -537,9 +537,9 @@ struct mbcs_soft { atomic_t dmawrite_done; atomic_t dmaread_done; atomic_t algo_done; - struct semaphore dmawritelock; - struct semaphore dmareadlock; - struct semaphore algolock; + struct mutex dmawritelock; + struct mutex dmareadlock; + struct mutex algolock; }; static int mbcs_open(struct inode *ip, struct file *fp); diff --git a/drivers/char/mxser.c b/drivers/char/mxser.c index 47420787a01..68c2e923469 100644 --- a/drivers/char/mxser.c +++ b/drivers/char/mxser.c @@ -1,41 +1,24 @@ /* * mxser.c -- MOXA Smartio/Industio family multiport serial driver. * - * Copyright (C) 1999-2001 Moxa Technologies (support@moxa.com.tw). + * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com). + * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com> * - * This code is loosely based on the Linux serial driver, written by - * Linus Torvalds, Theodore T'so and others. + * This code is loosely based on the 1.8 moxa driver which is based on + * Linux serial driver, written by Linus Torvalds, Theodore T'so and + * others. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Original release 10/26/00 - * - * 02/06/01 Support MOXA Industio family boards. - * 02/06/01 Support TIOCGICOUNT. - * 02/06/01 Fix the problem for connecting to serial mouse. - * 02/06/01 Fix the problem for H/W flow control. - * 02/06/01 Fix the compling warning when CONFIG_PCI - * don't be defined. - * * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox * <alan@redhat.com>. The original 1.8 code is available on www.moxa.com. * - Fixed x86_64 cleanness * - Fixed sleep with spinlock held in mxser_send_break */ - #include <linux/module.h> #include <linux/errno.h> #include <linux/signal.h> @@ -64,33 +47,37 @@ #include "mxser.h" -#define MXSER_VERSION "1.8" +#define MXSER_VERSION "2.0.3" /* 1.11 */ #define MXSERMAJOR 174 #define MXSERCUMAJOR 175 -#define MXSER_EVENT_TXLOW 1 -#define MXSER_EVENT_HANGUP 2 - #define MXSER_BOARDS 4 /* Max. boards */ -#define MXSER_PORTS 32 /* Max. ports */ #define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */ -#define MXSER_ISR_PASS_LIMIT 256 +#define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD) +#define MXSER_ISR_PASS_LIMIT 100 #define MXSER_ERR_IOADDR -1 #define MXSER_ERR_IRQ -2 #define MXSER_ERR_IRQ_CONFLIT -3 #define MXSER_ERR_VECTOR -4 -#define SERIAL_TYPE_NORMAL 1 -#define SERIAL_TYPE_CALLOUT 2 +/*CheckIsMoxaMust return value*/ +#define MOXA_OTHER_UART 0x00 +#define MOXA_MUST_MU150_HWID 0x01 +#define MOXA_MUST_MU860_HWID 0x02 #define WAKEUP_CHARS 256 #define UART_MCR_AFE 0x20 #define UART_LSR_SPECIAL 0x1E +#define PCI_DEVICE_ID_CB108 0x1080 +#define PCI_DEVICE_ID_CB114 0x1142 +#define PCI_DEVICE_ID_CP114UL 0x1143 +#define PCI_DEVICE_ID_CB134I 0x1341 +#define PCI_DEVICE_ID_CP138U 0x1380 +#define PCI_DEVICE_ID_POS104UL 0x1044 -#define IRQ_T(info) ((info->flags & ASYNC_SHARE_IRQ) ? IRQF_SHARED : IRQF_DISABLED) #define C168_ASIC_ID 1 #define C104_ASIC_ID 2 @@ -99,88 +86,11 @@ #define CI134_ASIC_ID 3 #define CI104J_ASIC_ID 5 -enum { - MXSER_BOARD_C168_ISA = 1, - MXSER_BOARD_C104_ISA, - MXSER_BOARD_CI104J, - MXSER_BOARD_C168_PCI, - MXSER_BOARD_C104_PCI, - MXSER_BOARD_C102_ISA, - MXSER_BOARD_CI132, - MXSER_BOARD_CI134, - MXSER_BOARD_CP132, - MXSER_BOARD_CP114, - MXSER_BOARD_CT114, - MXSER_BOARD_CP102, - MXSER_BOARD_CP104U, - MXSER_BOARD_CP168U, - MXSER_BOARD_CP132U, - MXSER_BOARD_CP134U, - MXSER_BOARD_CP104JU, - MXSER_BOARD_RC7000, - MXSER_BOARD_CP118U, - MXSER_BOARD_CP102UL, - MXSER_BOARD_CP102U, -}; - -static char *mxser_brdname[] = { - "C168 series", - "C104 series", - "CI-104J series", - "C168H/PCI series", - "C104H/PCI series", - "C102 series", - "CI-132 series", - "CI-134 series", - "CP-132 series", - "CP-114 series", - "CT-114 series", - "CP-102 series", - "CP-104U series", - "CP-168U series", - "CP-132U series", - "CP-134U series", - "CP-104JU series", - "Moxa UC7000 Serial", - "CP-118U series", - "CP-102UL series", - "CP-102U series", -}; - -static int mxser_numports[] = { - 8, /* C168-ISA */ - 4, /* C104-ISA */ - 4, /* CI104J */ - 8, /* C168-PCI */ - 4, /* C104-PCI */ - 2, /* C102-ISA */ - 2, /* CI132 */ - 4, /* CI134 */ - 2, /* CP132 */ - 4, /* CP114 */ - 4, /* CT114 */ - 2, /* CP102 */ - 4, /* CP104U */ - 8, /* CP168U */ - 2, /* CP132U */ - 4, /* CP134U */ - 4, /* CP104JU */ - 8, /* RC7000 */ - 8, /* CP118U */ - 2, /* CP102UL */ - 2, /* CP102U */ -}; - -#define UART_TYPE_NUM 2 - -static const unsigned int Gmoxa_uart_id[UART_TYPE_NUM] = { - MOXA_MUST_MU150_HWID, - MOXA_MUST_MU860_HWID -}; +#define MXSER_HIGHBAUD 1 +#define MXSER_HAS2 2 /* This is only for PCI */ -#define UART_INFO_NUM 3 -struct mxpciuart_info { +static const struct { int type; int tx_fifo; int rx_fifo; @@ -189,51 +99,85 @@ struct mxpciuart_info { int rx_trigger; int rx_low_water; long max_baud; -}; - -static const struct mxpciuart_info Gpci_uart_info[UART_INFO_NUM] = { +} Gpci_uart_info[] = { {MOXA_OTHER_UART, 16, 16, 16, 14, 14, 1, 921600L}, {MOXA_MUST_MU150_HWID, 64, 64, 64, 48, 48, 16, 230400L}, {MOXA_MUST_MU860_HWID, 128, 128, 128, 96, 96, 32, 921600L} }; +#define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info) +struct mxser_cardinfo { + char *name; + unsigned int nports; + unsigned int flags; +}; -#ifdef CONFIG_PCI +static const struct mxser_cardinfo mxser_cards[] = { +/* 0*/ { "C168 series", 8, }, + { "C104 series", 4, }, + { "CI-104J series", 4, }, + { "C168H/PCI series", 8, }, + { "C104H/PCI series", 4, }, +/* 5*/ { "C102 series", 4, MXSER_HAS2 }, /* C102-ISA */ + { "CI-132 series", 4, MXSER_HAS2 }, + { "CI-134 series", 4, }, + { "CP-132 series", 2, }, + { "CP-114 series", 4, }, +/*10*/ { "CT-114 series", 4, }, + { "CP-102 series", 2, MXSER_HIGHBAUD }, + { "CP-104U series", 4, }, + { "CP-168U series", 8, }, + { "CP-132U series", 2, }, +/*15*/ { "CP-134U series", 4, }, + { "CP-104JU series", 4, }, + { "Moxa UC7000 Serial", 8, }, /* RC7000 */ + { "CP-118U series", 8, }, + { "CP-102UL series", 2, }, +/*20*/ { "CP-102U series", 2, }, + { "CP-118EL series", 8, }, + { "CP-168EL series", 8, }, + { "CP-104EL series", 4, }, + { "CB-108 series", 8, }, +/*25*/ { "CB-114 series", 4, }, + { "CB-134I series", 4, }, + { "CP-138U series", 8, }, + { "POS-104UL series", 4, }, + { "CP-114UL series", 4, } +}; +/* driver_data correspond to the lines in the structure above + see also ISA probe function before you change something */ static struct pci_device_id mxser_pcibrds[] = { - {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_C168, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_C168_PCI}, - {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_C104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_C104_PCI}, - {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP132}, - {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP114}, - {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CT114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CT114}, - {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP102}, - {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104U, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP104U}, - {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168U, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP168U}, - {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132U, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP132U}, - {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134U, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP134U}, - {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104JU, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP104JU}, - {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_RC7000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_RC7000}, - {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118U, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP118U}, - {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102UL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP102UL}, - {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102U, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP102U}, - {0} + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168), .driver_data = 3 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104), .driver_data = 4 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132), .driver_data = 8 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114), .driver_data = 9 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114), .driver_data = 10 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102), .driver_data = 11 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U), .driver_data = 12 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U), .driver_data = 13 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U), .driver_data = 14 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U), .driver_data = 15 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 16 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000), .driver_data = 17 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U), .driver_data = 18 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 19 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U), .driver_data = 20 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 21 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 22 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 23 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108), .driver_data = 24 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114), .driver_data = 25 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I), .driver_data = 26 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U), .driver_data = 27 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL), .driver_data = 28 }, + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP114UL), .driver_data = 29 }, + { } }; - MODULE_DEVICE_TABLE(pci, mxser_pcibrds); - -#endif - -typedef struct _moxa_pci_info { - unsigned short busNum; - unsigned short devNum; - struct pci_dev *pdev; /* add by Victor Yu. 06-23-2003 */ -} moxa_pci_info; - static int ioaddr[MXSER_BOARDS] = { 0, 0, 0, 0 }; static int ttymajor = MXSERMAJOR; -static int calloutmajor = MXSERCUMAJOR; -static int verbose = 0; /* Variables for insmod */ @@ -241,8 +185,6 @@ MODULE_AUTHOR("Casper Yang"); MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver"); module_param_array(ioaddr, int, NULL, 0); module_param(ttymajor, int, 0); -module_param(calloutmajor, int, 0); -module_param(verbose, bool, 0); MODULE_LICENSE("GPL"); struct mxser_log { @@ -277,67 +219,69 @@ struct mxser_mon_ext { int iftype[32]; }; -struct mxser_hwconf { - int board_type; - int ports; - int irq; - int vector; - int vector_mask; - int uart_type; - int ioaddr[MXSER_PORTS_PER_BOARD]; - int baud_base[MXSER_PORTS_PER_BOARD]; - moxa_pci_info pciInfo; - int IsMoxaMustChipFlag; /* add by Victor Yu. 08-30-2002 */ - int MaxCanSetBaudRate[MXSER_PORTS_PER_BOARD]; /* add by Victor Yu. 09-04-2002 */ - int opmode_ioaddr[MXSER_PORTS_PER_BOARD]; /* add by Victor Yu. 01-05-2004 */ -}; +struct mxser_board; + +struct mxser_port { + struct mxser_board *board; + struct tty_struct *tty; + + unsigned long ioaddr; + unsigned long opmode_ioaddr; + int max_baud; -struct mxser_struct { - int port; - int base; /* port base address */ - int irq; /* port using irq no. */ - int vector; /* port irq vector */ - int vectormask; /* port vector mask */ int rx_high_water; int rx_trigger; /* Rx fifo trigger level */ int rx_low_water; int baud_base; /* max. speed */ - int flags; /* defined in tty.h */ int type; /* UART type */ - struct tty_struct *tty; - int read_status_mask; - int ignore_status_mask; - int xmit_fifo_size; - int custom_divisor; + int flags; /* defined in tty.h */ + int x_char; /* xon/xoff character */ - int close_delay; - unsigned short closing_wait; int IER; /* Interrupt Enable Register */ int MCR; /* Modem control register */ + + unsigned char stop_rx; + unsigned char ldisc_stop_rx; + + int custom_divisor; + int close_delay; + unsigned short closing_wait; + unsigned char err_shadow; unsigned long event; + int count; /* # of fd on device */ int blocked_open; /* # of blocked opens */ + struct async_icount icount; /* kernel counters for 4 input interrupts */ + int timeout; + + int read_status_mask; + int ignore_status_mask; + int xmit_fifo_size; unsigned char *xmit_buf; int xmit_head; int xmit_tail; int xmit_cnt; - struct work_struct tqueue; + struct ktermios normal_termios; - struct ktermios callout_termios; - wait_queue_head_t open_wait; - wait_queue_head_t close_wait; - wait_queue_head_t delta_msr_wait; - struct async_icount icount; /* kernel counters for the 4 input interrupts */ - int timeout; - int IsMoxaMustChipFlag; /* add by Victor Yu. 08-30-2002 */ - int MaxCanSetBaudRate; /* add by Victor Yu. 09-04-2002 */ - int opmode_ioaddr; /* add by Victor Yu. 01-05-2004 */ - unsigned char stop_rx; - unsigned char ldisc_stop_rx; - long realbaud; + struct mxser_mon mon_data; - unsigned char err_shadow; + spinlock_t slock; + wait_queue_head_t open_wait; + wait_queue_head_t delta_msr_wait; +}; + +struct mxser_board { + unsigned int idx; + int irq; + const struct mxser_cardinfo *info; + unsigned long vector; + unsigned long vector_mask; + + int chip_flag; + int uart_type; + + struct mxser_port ports[MXSER_PORTS_PER_BOARD]; }; struct mxser_mstatus { @@ -355,73 +299,16 @@ static int mxserBoardCAP[MXSER_BOARDS] = { /* 0x180, 0x280, 0x200, 0x320 */ }; +static struct mxser_board mxser_boards[MXSER_BOARDS]; static struct tty_driver *mxvar_sdriver; -static struct mxser_struct mxvar_table[MXSER_PORTS]; -static struct tty_struct *mxvar_tty[MXSER_PORTS + 1]; -static struct ktermios *mxvar_termios[MXSER_PORTS + 1]; -static struct ktermios *mxvar_termios_locked[MXSER_PORTS + 1]; static struct mxser_log mxvar_log; static int mxvar_diagflag; static unsigned char mxser_msr[MXSER_PORTS + 1]; static struct mxser_mon_ext mon_data_ext; static int mxser_set_baud_method[MXSER_PORTS + 1]; -static spinlock_t gm_lock; - -/* - * This is used to figure out the divisor speeds and the timeouts - */ - -static struct mxser_hwconf mxsercfg[MXSER_BOARDS]; - -/* - * static functions: - */ - -static void mxser_getcfg(int board, struct mxser_hwconf *hwconf); -static int mxser_init(void); - -/* static void mxser_poll(unsigned long); */ -static int mxser_get_ISA_conf(int, struct mxser_hwconf *); -static void mxser_do_softint(struct work_struct *); -static int mxser_open(struct tty_struct *, struct file *); -static void mxser_close(struct tty_struct *, struct file *); -static int mxser_write(struct tty_struct *, const unsigned char *, int); -static int mxser_write_room(struct tty_struct *); -static void mxser_flush_buffer(struct tty_struct *); -static int mxser_chars_in_buffer(struct tty_struct *); -static void mxser_flush_chars(struct tty_struct *); -static void mxser_put_char(struct tty_struct *, unsigned char); -static int mxser_ioctl(struct tty_struct *, struct file *, uint, ulong); -static int mxser_ioctl_special(unsigned int, void __user *); -static void mxser_throttle(struct tty_struct *); -static void mxser_unthrottle(struct tty_struct *); -static void mxser_set_termios(struct tty_struct *, struct ktermios *); -static void mxser_stop(struct tty_struct *); -static void mxser_start(struct tty_struct *); -static void mxser_hangup(struct tty_struct *); -static void mxser_rs_break(struct tty_struct *, int); -static irqreturn_t mxser_interrupt(int, void *); -static void mxser_receive_chars(struct mxser_struct *, int *); -static void mxser_transmit_chars(struct mxser_struct *); -static void mxser_check_modem_status(struct mxser_struct *, int); -static int mxser_block_til_ready(struct tty_struct *, struct file *, struct mxser_struct *); -static int mxser_startup(struct mxser_struct *); -static void mxser_shutdown(struct mxser_struct *); -static int mxser_change_speed(struct mxser_struct *, struct ktermios *old_termios); -static int mxser_get_serial_info(struct mxser_struct *, struct serial_struct __user *); -static int mxser_set_serial_info(struct mxser_struct *, struct serial_struct __user *); -static int mxser_get_lsr_info(struct mxser_struct *, unsigned int __user *); -static void mxser_send_break(struct mxser_struct *, int); -static int mxser_tiocmget(struct tty_struct *, struct file *); -static int mxser_tiocmset(struct tty_struct *, struct file *, unsigned int, unsigned int); -static int mxser_set_baud(struct mxser_struct *info, long newspd); -static void mxser_wait_until_sent(struct tty_struct *tty, int timeout); - -static void mxser_startrx(struct tty_struct *tty); -static void mxser_stoprx(struct tty_struct *tty); #ifdef CONFIG_PCI -static int CheckIsMoxaMust(int io) +static int __devinit CheckIsMoxaMust(unsigned long io) { u8 oldmcr, hwid; int i; @@ -437,90 +324,15 @@ static int CheckIsMoxaMust(int io) } GET_MOXA_MUST_HARDWARE_ID(io, &hwid); - for (i = 0; i < UART_TYPE_NUM; i++) { - if (hwid == Gmoxa_uart_id[i]) + for (i = 1; i < UART_INFO_NUM; i++) { /* 0 = OTHER_UART */ + if (hwid == Gpci_uart_info[i].type) return (int)hwid; } return MOXA_OTHER_UART; } #endif -/* above is modified by Victor Yu. 08-15-2002 */ - -static const struct tty_operations mxser_ops = { - .open = mxser_open, - .close = mxser_close, - .write = mxser_write, - .put_char = mxser_put_char, - .flush_chars = mxser_flush_chars, - .write_room = mxser_write_room, - .chars_in_buffer = mxser_chars_in_buffer, - .flush_buffer = mxser_flush_buffer, - .ioctl = mxser_ioctl, - .throttle = mxser_throttle, - .unthrottle = mxser_unthrottle, - .set_termios = mxser_set_termios, - .stop = mxser_stop, - .start = mxser_start, - .hangup = mxser_hangup, - .break_ctl = mxser_rs_break, - .wait_until_sent = mxser_wait_until_sent, - .tiocmget = mxser_tiocmget, - .tiocmset = mxser_tiocmset, -}; - -/* - * The MOXA Smartio/Industio serial driver boot-time initialization code! - */ - -static int __init mxser_module_init(void) -{ - int ret; - - if (verbose) - printk(KERN_DEBUG "Loading module mxser ...\n"); - ret = mxser_init(); - if (verbose) - printk(KERN_DEBUG "Done.\n"); - return ret; -} - -static void __exit mxser_module_exit(void) -{ - int i, err; - - if (verbose) - printk(KERN_DEBUG "Unloading module mxser ...\n"); - - err = tty_unregister_driver(mxvar_sdriver); - if (!err) - put_tty_driver(mxvar_sdriver); - else - printk(KERN_ERR "Couldn't unregister MOXA Smartio/Industio family serial driver\n"); - - for (i = 0; i < MXSER_BOARDS; i++) { - struct pci_dev *pdev; - - if (mxsercfg[i].board_type == -1) - continue; - else { - pdev = mxsercfg[i].pciInfo.pdev; - free_irq(mxsercfg[i].irq, &mxvar_table[i * MXSER_PORTS_PER_BOARD]); - if (pdev != NULL) { /* PCI */ - release_region(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2)); - release_region(pci_resource_start(pdev, 3), pci_resource_len(pdev, 3)); - pci_dev_put(pdev); - } else { - release_region(mxsercfg[i].ioaddr[0], 8 * mxsercfg[i].ports); - release_region(mxsercfg[i].vector, 1); - } - } - } - if (verbose) - printk(KERN_DEBUG "Done.\n"); -} - -static void process_txrx_fifo(struct mxser_struct *info) +static void process_txrx_fifo(struct mxser_port *info) { int i; @@ -529,424 +341,548 @@ static void process_txrx_fifo(struct mxser_struct *info) info->rx_high_water = 1; info->rx_low_water = 1; info->xmit_fifo_size = 1; - } else { - for (i = 0; i < UART_INFO_NUM; i++) { - if (info->IsMoxaMustChipFlag == Gpci_uart_info[i].type) { + } else + for (i = 0; i < UART_INFO_NUM; i++) + if (info->board->chip_flag == Gpci_uart_info[i].type) { info->rx_trigger = Gpci_uart_info[i].rx_trigger; info->rx_low_water = Gpci_uart_info[i].rx_low_water; info->rx_high_water = Gpci_uart_info[i].rx_high_water; info->xmit_fifo_size = Gpci_uart_info[i].xmit_fifo_size; break; } - } - } } -static int mxser_initbrd(int board, struct mxser_hwconf *hwconf) +static unsigned char mxser_get_msr(int baseaddr, int mode, int port) { - struct mxser_struct *info; - int retval; - int i, n; + unsigned char status = 0; - n = board * MXSER_PORTS_PER_BOARD; - info = &mxvar_table[n]; - /*if (verbose) */ { - printk(KERN_DEBUG " ttyMI%d - ttyMI%d ", - n, n + hwconf->ports - 1); - printk(" max. baud rate = %d bps.\n", - hwconf->MaxCanSetBaudRate[0]); - } - - for (i = 0; i < hwconf->ports; i++, n++, info++) { - info->port = n; - info->base = hwconf->ioaddr[i]; - info->irq = hwconf->irq; - info->vector = hwconf->vector; - info->vectormask = hwconf->vector_mask; - info->opmode_ioaddr = hwconf->opmode_ioaddr[i]; /* add by Victor Yu. 01-05-2004 */ - info->stop_rx = 0; - info->ldisc_stop_rx = 0; + status = inb(baseaddr + UART_MSR); - info->IsMoxaMustChipFlag = hwconf->IsMoxaMustChipFlag; - /* Enhance mode enabled here */ - if (info->IsMoxaMustChipFlag != MOXA_OTHER_UART) { - ENABLE_MOXA_MUST_ENCHANCE_MODE(info->base); - } + mxser_msr[port] &= 0x0F; + mxser_msr[port] |= status; + status = mxser_msr[port]; + if (mode) + mxser_msr[port] = 0; - info->flags = ASYNC_SHARE_IRQ; - info->type = hwconf->uart_type; - info->baud_base = hwconf->baud_base[i]; + return status; +} - info->MaxCanSetBaudRate = hwconf->MaxCanSetBaudRate[i]; +static int mxser_block_til_ready(struct tty_struct *tty, struct file *filp, + struct mxser_port *port) +{ + DECLARE_WAITQUEUE(wait, current); + int retval; + int do_clocal = 0; + unsigned long flags; - process_txrx_fifo(info); + /* + * If non-blocking mode is set, or the port is not enabled, + * then make the check up front and then exit. + */ + if ((filp->f_flags & O_NONBLOCK) || + test_bit(TTY_IO_ERROR, &tty->flags)) { + port->flags |= ASYNC_NORMAL_ACTIVE; + return 0; + } + if (tty->termios->c_cflag & CLOCAL) + do_clocal = 1; - info->custom_divisor = hwconf->baud_base[i] * 16; - info->close_delay = 5 * HZ / 10; - info->closing_wait = 30 * HZ; - INIT_WORK(&info->tqueue, mxser_do_softint); - info->normal_termios = mxvar_sdriver->init_termios; - init_waitqueue_head(&info->open_wait); - init_waitqueue_head(&info->close_wait); - init_waitqueue_head(&info->delta_msr_wait); - memset(&info->mon_data, 0, sizeof(struct mxser_mon)); - info->err_shadow = 0; - spin_lock_init(&info->slock); - } /* - * Allocate the IRQ if necessary + * Block waiting for the carrier detect and the line to become + * free (i.e., not in use by the callout). While we are in + * this loop, port->count is dropped by one, so that + * mxser_close() knows when to free things. We restore it upon + * exit, either normal or abnormal. */ + retval = 0; + add_wait_queue(&port->open_wait, &wait); - - /* before set INT ISR, disable all int */ - for (i = 0; i < hwconf->ports; i++) { - outb(inb(hwconf->ioaddr[i] + UART_IER) & 0xf0, - hwconf->ioaddr[i] + UART_IER); + spin_lock_irqsave(&port->slock, flags); + if (!tty_hung_up_p(filp)) + port->count--; + spin_unlock_irqrestore(&port->slock, flags); + port->blocked_open++; + while (1) { + spin_lock_irqsave(&port->slock, flags); + outb(inb(port->ioaddr + UART_MCR) | + UART_MCR_DTR | UART_MCR_RTS, port->ioaddr + UART_MCR); + spin_unlock_irqrestore(&port->slock, flags); + set_current_state(TASK_INTERRUPTIBLE); + if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)) { + if (port->flags & ASYNC_HUP_NOTIFY) + retval = -EAGAIN; + else + retval = -ERESTARTSYS; + break; + } + if (!(port->flags & ASYNC_CLOSING) && + (do_clocal || + (inb(port->ioaddr + UART_MSR) & UART_MSR_DCD))) + break; + if (signal_pending(current)) { + retval = -ERESTARTSYS; + break; + } + schedule(); } - - n = board * MXSER_PORTS_PER_BOARD; - info = &mxvar_table[n]; - - retval = request_irq(hwconf->irq, mxser_interrupt, IRQ_T(info), - "mxser", info); - if (retval) { - printk(KERN_ERR "Board %d: %s", - board, mxser_brdname[hwconf->board_type - 1]); - printk(" Request irq failed, IRQ (%d) may conflict with" - " another device.\n", info->irq); + set_current_state(TASK_RUNNING); + remove_wait_queue(&port->open_wait, &wait); + if (!tty_hung_up_p(filp)) + port->count++; + port->blocked_open--; + if (retval) return retval; - } + port->flags |= ASYNC_NORMAL_ACTIVE; return 0; } -static void mxser_getcfg(int board, struct mxser_hwconf *hwconf) +static int mxser_set_baud(struct mxser_port *info, long newspd) { - mxsercfg[board] = *hwconf; -} + int quot = 0, baud; + unsigned char cval; -#ifdef CONFIG_PCI -static int mxser_get_PCI_conf(int busnum, int devnum, int board_type, struct mxser_hwconf *hwconf) -{ - int i, j; - /* unsigned int val; */ - unsigned int ioaddress; - struct pci_dev *pdev = hwconf->pciInfo.pdev; + if (!info->tty || !info->tty->termios) + return -1; - /* io address */ - hwconf->board_type = board_type; - hwconf->ports = mxser_numports[board_type - 1]; - ioaddress = pci_resource_start(pdev, 2); - request_region(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2), - "mxser(IO)"); + if (!(info->ioaddr)) + return -1; - for (i = 0; i < hwconf->ports; i++) - hwconf->ioaddr[i] = ioaddress + 8 * i; + if (newspd > info->max_baud) + return -1; - /* vector */ - ioaddress = pci_resource_start(pdev, 3); - request_region(pci_resource_start(pdev, 3), pci_resource_len(pdev, 3), - "mxser(vector)"); - hwconf->vector = ioaddress; + if (newspd == 134) { + quot = 2 * info->baud_base / 269; + tty_encode_baud_rate(info->tty, 134, 134); + } else if (newspd) { + quot = info->baud_base / newspd; + if (quot == 0) + quot = 1; + baud = info->baud_base/quot; + tty_encode_baud_rate(info->tty, baud, baud); + } else { + quot = 0; + } - /* irq */ - hwconf->irq = hwconf->pciInfo.pdev->irq; + info->timeout = ((info->xmit_fifo_size * HZ * 10 * quot) / info->baud_base); + info->timeout += HZ / 50; /* Add .02 seconds of slop */ - hwconf->IsMoxaMustChipFlag = CheckIsMoxaMust(hwconf->ioaddr[0]); - hwconf->uart_type = PORT_16550A; - hwconf->vector_mask = 0; + if (quot) { + info->MCR |= UART_MCR_DTR; + outb(info->MCR, info->ioaddr + UART_MCR); + } else { + info->MCR &= ~UART_MCR_DTR; + outb(info->MCR, info->ioaddr + UART_MCR); + return 0; + } + cval = inb(info->ioaddr + UART_LCR); - for (i = 0; i < hwconf->ports; i++) { - for (j = 0; j < UART_INFO_NUM; j++) { - if (Gpci_uart_info[j].type == hwconf->IsMoxaMustChipFlag) { - hwconf->MaxCanSetBaudRate[i] = Gpci_uart_info[j].max_baud; + outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */ - /* exception....CP-102 */ - if (board_type == MXSER_BOARD_CP102) - hwconf->MaxCanSetBaudRate[i] = 921600; - break; - } - } - } + outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */ + outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */ + outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */ - if (hwconf->IsMoxaMustChipFlag == MOXA_MUST_MU860_HWID) { - for (i = 0; i < hwconf->ports; i++) { - if (i < 4) - hwconf->opmode_ioaddr[i] = ioaddress + 4; - else - hwconf->opmode_ioaddr[i] = ioaddress + 0x0c; - } - outb(0, ioaddress + 4); /* default set to RS232 mode */ - outb(0, ioaddress + 0x0c); /* default set to RS232 mode */ - } +#ifdef BOTHER + if (C_BAUD(info->tty) == BOTHER) { + quot = info->baud_base % newspd; + quot *= 8; + if (quot % newspd > newspd / 2) { + quot /= newspd; + quot++; + } else + quot /= newspd; + + SET_MOXA_MUST_ENUM_VALUE(info->ioaddr, quot); + } else +#endif + SET_MOXA_MUST_ENUM_VALUE(info->ioaddr, 0); - for (i = 0; i < hwconf->ports; i++) { - hwconf->vector_mask |= (1 << i); - hwconf->baud_base[i] = 921600; - } return 0; } -#endif -static int mxser_init(void) +/* + * This routine is called to set the UART divisor registers to match + * the specified baud rate for a serial port. + */ +static int mxser_change_speed(struct mxser_port *info, + struct ktermios *old_termios) { - int i, m, retval, b, n; - struct pci_dev *pdev = NULL; - int index; - unsigned char busnum, devnum; - struct mxser_hwconf hwconf; - - mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1); - if (!mxvar_sdriver) - return -ENOMEM; - spin_lock_init(&gm_lock); - - for (i = 0; i < MXSER_BOARDS; i++) { - mxsercfg[i].board_type = -1; - } + unsigned cflag, cval, fcr; + int ret = 0; + unsigned char status; - printk(KERN_INFO "MOXA Smartio/Industio family driver version %s\n", - MXSER_VERSION); + if (!info->tty || !info->tty->termios) + return ret; + cflag = info->tty->termios->c_cflag; + if (!(info->ioaddr)) + return ret; - /* Initialize the tty_driver structure */ - memset(mxvar_sdriver, 0, sizeof(struct tty_driver)); - mxvar_sdriver->owner = THIS_MODULE; - mxvar_sdriver->magic = TTY_DRIVER_MAGIC; - mxvar_sdriver->name = "ttyMI"; - mxvar_sdriver->major = ttymajor; - mxvar_sdriver->minor_start = 0; - mxvar_sdriver->num = MXSER_PORTS + 1; - mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL; - mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL; - mxvar_sdriver->init_termios = tty_std_termios; - mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL; - mxvar_sdriver->init_termios.c_ispeed = 9600; - mxvar_sdriver->init_termios.c_ospeed = 9600; - mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW; - tty_set_operations(mxvar_sdriver, &mxser_ops); - mxvar_sdriver->ttys = mxvar_tty; - mxvar_sdriver->termios = mxvar_termios; - mxvar_sdriver->termios_locked = mxvar_termios_locked; + if (mxser_set_baud_method[info->tty->index] == 0) + mxser_set_baud(info, tty_get_baud_rate(info->tty)); - mxvar_diagflag = 0; - memset(mxvar_table, 0, MXSER_PORTS * sizeof(struct mxser_struct)); - memset(&mxvar_log, 0, sizeof(struct mxser_log)); + /* byte size and parity */ + switch (cflag & CSIZE) { + case CS5: + cval = 0x00; + break; + case CS6: + cval = 0x01; + break; + case CS7: + cval = 0x02; + break; + case CS8: + cval = 0x03; + break; + default: + cval = 0x00; + break; /* too keep GCC shut... */ + } + if (cflag & CSTOPB) + cval |= 0x04; + if (cflag & PARENB) + cval |= UART_LCR_PARITY; + if (!(cflag & PARODD)) + cval |= UART_LCR_EPAR; + if (cflag & CMSPAR) + cval |= UART_LCR_SPAR; - memset(&mxser_msr, 0, sizeof(unsigned char) * (MXSER_PORTS + 1)); - memset(&mon_data_ext, 0, sizeof(struct mxser_mon_ext)); - memset(&mxser_set_baud_method, 0, sizeof(int) * (MXSER_PORTS + 1)); - memset(&hwconf, 0, sizeof(struct mxser_hwconf)); + if ((info->type == PORT_8250) || (info->type == PORT_16450)) { + if (info->board->chip_flag) { + fcr = UART_FCR_ENABLE_FIFO; + fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; + SET_MOXA_MUST_FIFO_VALUE(info); + } else + fcr = 0; + } else { + fcr = UART_FCR_ENABLE_FIFO; + if (info->board->chip_flag) { + fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; + SET_MOXA_MUST_FIFO_VALUE(info); + } else { + switch (info->rx_trigger) { + case 1: + fcr |= UART_FCR_TRIGGER_1; + break; + case 4: + fcr |= UART_FCR_TRIGGER_4; + break; + case 8: + fcr |= UART_FCR_TRIGGER_8; + break; + default: + fcr |= UART_FCR_TRIGGER_14; + break; + } + } + } - m = 0; - /* Start finding ISA boards here */ - for (b = 0; b < MXSER_BOARDS && m < MXSER_BOARDS; b++) { - int cap; - - if (!(cap = mxserBoardCAP[b])) - continue; - - retval = mxser_get_ISA_conf(cap, &hwconf); - - if (retval != 0) - printk(KERN_INFO "Found MOXA %s board (CAP=0x%x)\n", - mxser_brdname[hwconf.board_type - 1], ioaddr[b]); - - if (retval <= 0) { - if (retval == MXSER_ERR_IRQ) - printk(KERN_ERR "Invalid interrupt number, " - "board not configured\n"); - else if (retval == MXSER_ERR_IRQ_CONFLIT) - printk(KERN_ERR "Invalid interrupt number, " - "board not configured\n"); - else if (retval == MXSER_ERR_VECTOR) - printk(KERN_ERR "Invalid interrupt vector, " - "board not configured\n"); - else if (retval == MXSER_ERR_IOADDR) - printk(KERN_ERR "Invalid I/O address, " - "board not configured\n"); - - continue; + /* CTS flow control flag and modem status interrupts */ + info->IER &= ~UART_IER_MSI; + info->MCR &= ~UART_MCR_AFE; + if (cflag & CRTSCTS) { + info->flags |= ASYNC_CTS_FLOW; + info->IER |= UART_IER_MSI; + if ((info->type == PORT_16550A) || (info->board->chip_flag)) { + info->MCR |= UART_MCR_AFE; + } else { + status = inb(info->ioaddr + UART_MSR); + if (info->tty->hw_stopped) { + if (status & UART_MSR_CTS) { + info->tty->hw_stopped = 0; + if (info->type != PORT_16550A && + !info->board->chip_flag) { + outb(info->IER & ~UART_IER_THRI, + info->ioaddr + + UART_IER); + info->IER |= UART_IER_THRI; + outb(info->IER, info->ioaddr + + UART_IER); + } + tty_wakeup(info->tty); + } + } else { + if (!(status & UART_MSR_CTS)) { + info->tty->hw_stopped = 1; + if ((info->type != PORT_16550A) && + (!info->board->chip_flag)) { + info->IER &= ~UART_IER_THRI; + outb(info->IER, info->ioaddr + + UART_IER); + } + } + } } + } else { + info->flags &= ~ASYNC_CTS_FLOW; + } + outb(info->MCR, info->ioaddr + UART_MCR); + if (cflag & CLOCAL) { + info->flags &= ~ASYNC_CHECK_CD; + } else { + info->flags |= ASYNC_CHECK_CD; + info->IER |= UART_IER_MSI; + } + outb(info->IER, info->ioaddr + UART_IER); - hwconf.pciInfo.busNum = 0; - hwconf.pciInfo.devNum = 0; - hwconf.pciInfo.pdev = NULL; + /* + * Set up parity check flag + */ + info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; + if (I_INPCK(info->tty)) + info->read_status_mask |= UART_LSR_FE | UART_LSR_PE; + if (I_BRKINT(info->tty) || I_PARMRK(info->tty)) + info->read_status_mask |= UART_LSR_BI; + + info->ignore_status_mask = 0; - mxser_getcfg(m, &hwconf); + if (I_IGNBRK(info->tty)) { + info->ignore_status_mask |= UART_LSR_BI; + info->read_status_mask |= UART_LSR_BI; /* - * init mxsercfg first, - * or mxsercfg data is not correct on ISR. + * If we're ignore parity and break indicators, ignore + * overruns too. (For real raw support). */ - /* mxser_initbrd will hook ISR. */ - if (mxser_initbrd(m, &hwconf) < 0) - continue; - - m++; + if (I_IGNPAR(info->tty)) { + info->ignore_status_mask |= + UART_LSR_OE | + UART_LSR_PE | + UART_LSR_FE; + info->read_status_mask |= + UART_LSR_OE | + UART_LSR_PE | + UART_LSR_FE; + } + } + if (info->board->chip_flag) { + SET_MOXA_MUST_XON1_VALUE(info->ioaddr, START_CHAR(info->tty)); + SET_MOXA_MUST_XOFF1_VALUE(info->ioaddr, STOP_CHAR(info->tty)); + if (I_IXON(info->tty)) { + ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr); + } else { + DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr); + } + if (I_IXOFF(info->tty)) { + ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->ioaddr); + } else { + DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->ioaddr); + } } - /* Start finding ISA boards from module arg */ - for (b = 0; b < MXSER_BOARDS && m < MXSER_BOARDS; b++) { - int cap; - if (!(cap = ioaddr[b])) - continue; + outb(fcr, info->ioaddr + UART_FCR); /* set fcr */ + outb(cval, info->ioaddr + UART_LCR); - retval = mxser_get_ISA_conf(cap, &hwconf); + return ret; +} - if (retval != 0) - printk(KERN_INFO "Found MOXA %s board (CAP=0x%x)\n", - mxser_brdname[hwconf.board_type - 1], ioaddr[b]); +static void mxser_check_modem_status(struct mxser_port *port, int status) +{ + /* update input line counters */ + if (status & UART_MSR_TERI) + port->icount.rng++; + if (status & UART_MSR_DDSR) + port->icount.dsr++; + if (status & UART_MSR_DDCD) + port->icount.dcd++; + if (status & UART_MSR_DCTS) + port->icount.cts++; + port->mon_data.modem_status = status; + wake_up_interruptible(&port->delta_msr_wait); - if (retval <= 0) { - if (retval == MXSER_ERR_IRQ) - printk(KERN_ERR "Invalid interrupt number, " - "board not configured\n"); - else if (retval == MXSER_ERR_IRQ_CONFLIT) - printk(KERN_ERR "Invalid interrupt number, " - "board not configured\n"); - else if (retval == MXSER_ERR_VECTOR) - printk(KERN_ERR "Invalid interrupt vector, " - "board not configured\n"); - else if (retval == MXSER_ERR_IOADDR) - printk(KERN_ERR "Invalid I/O address, " - "board not configured\n"); + if ((port->flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) { + if (status & UART_MSR_DCD) + wake_up_interruptible(&port->open_wait); + } - continue; + if (port->flags & ASYNC_CTS_FLOW) { + if (port->tty->hw_stopped) { + if (status & UART_MSR_CTS) { + port->tty->hw_stopped = 0; + + if ((port->type != PORT_16550A) && + (!port->board->chip_flag)) { + outb(port->IER & ~UART_IER_THRI, + port->ioaddr + UART_IER); + port->IER |= UART_IER_THRI; + outb(port->IER, port->ioaddr + + UART_IER); + } + tty_wakeup(port->tty); + } + } else { + if (!(status & UART_MSR_CTS)) { + port->tty->hw_stopped = 1; + if (port->type != PORT_16550A && + !port->board->chip_flag) { + port->IER &= ~UART_IER_THRI; + outb(port->IER, port->ioaddr + + UART_IER); + } + } } + } +} - hwconf.pciInfo.busNum = 0; - hwconf.pciInfo.devNum = 0; - hwconf.pciInfo.pdev = NULL; +static int mxser_startup(struct mxser_port *info) +{ + unsigned long page; + unsigned long flags; - mxser_getcfg(m, &hwconf); - /* - * init mxsercfg first, - * or mxsercfg data is not correct on ISR. - */ - /* mxser_initbrd will hook ISR. */ - if (mxser_initbrd(m, &hwconf) < 0) - continue; + page = __get_free_page(GFP_KERNEL); + if (!page) + return -ENOMEM; + + spin_lock_irqsave(&info->slock, flags); - m++; + if (info->flags & ASYNC_INITIALIZED) { + free_page(page); + spin_unlock_irqrestore(&info->slock, flags); + return 0; } - /* start finding PCI board here */ -#ifdef CONFIG_PCI - n = ARRAY_SIZE(mxser_pcibrds) - 1; - index = 0; - b = 0; - while (b < n) { - pdev = pci_get_device(mxser_pcibrds[b].vendor, - mxser_pcibrds[b].device, pdev); - if (pdev == NULL) { - b++; - continue; - } - hwconf.pciInfo.busNum = busnum = pdev->bus->number; - hwconf.pciInfo.devNum = devnum = PCI_SLOT(pdev->devfn) << 3; - hwconf.pciInfo.pdev = pdev; - printk(KERN_INFO "Found MOXA %s board(BusNo=%d,DevNo=%d)\n", - mxser_brdname[(int) (mxser_pcibrds[b].driver_data) - 1], - busnum, devnum >> 3); - index++; - if (m >= MXSER_BOARDS) - printk(KERN_ERR - "Too many Smartio/Industio family boards find " - "(maximum %d), board not configured\n", - MXSER_BOARDS); - else { - if (pci_enable_device(pdev)) { - printk(KERN_ERR "Moxa SmartI/O PCI enable " - "fail !\n"); - continue; - } - retval = mxser_get_PCI_conf(busnum, devnum, - (int)mxser_pcibrds[b].driver_data, - &hwconf); - if (retval < 0) { - if (retval == MXSER_ERR_IRQ) - printk(KERN_ERR - "Invalid interrupt number, " - "board not configured\n"); - else if (retval == MXSER_ERR_IRQ_CONFLIT) - printk(KERN_ERR - "Invalid interrupt number, " - "board not configured\n"); - else if (retval == MXSER_ERR_VECTOR) - printk(KERN_ERR - "Invalid interrupt vector, " - "board not configured\n"); - else if (retval == MXSER_ERR_IOADDR) - printk(KERN_ERR - "Invalid I/O address, " - "board not configured\n"); - continue; - } - mxser_getcfg(m, &hwconf); - /* init mxsercfg first, - * or mxsercfg data is not correct on ISR. - */ - /* mxser_initbrd will hook ISR. */ - if (mxser_initbrd(m, &hwconf) < 0) - continue; - m++; - /* Keep an extra reference if we succeeded. It will - be returned at unload time */ - pci_dev_get(pdev); - } + if (!info->ioaddr || !info->type) { + if (info->tty) + set_bit(TTY_IO_ERROR, &info->tty->flags); + free_page(page); + spin_unlock_irqrestore(&info->slock, flags); + return 0; } -#endif + if (info->xmit_buf) + free_page(page); + else + info->xmit_buf = (unsigned char *) page; - retval = tty_register_driver(mxvar_sdriver); - if (retval) { - printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family" - " driver !\n"); - put_tty_driver(mxvar_sdriver); + /* + * Clear the FIFO buffers and disable them + * (they will be reenabled in mxser_change_speed()) + */ + if (info->board->chip_flag) + outb((UART_FCR_CLEAR_RCVR | + UART_FCR_CLEAR_XMIT | + MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR); + else + outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT), + info->ioaddr + UART_FCR); - for (i = 0; i < MXSER_BOARDS; i++) { - if (mxsercfg[i].board_type == -1) - continue; - else { - free_irq(mxsercfg[i].irq, &mxvar_table[i * MXSER_PORTS_PER_BOARD]); - /* todo: release io, vector */ - } - } - return retval; + /* + * At this point there's no way the LSR could still be 0xFF; + * if it is, then bail out, because there's likely no UART + * here. + */ + if (inb(info->ioaddr + UART_LSR) == 0xff) { + spin_unlock_irqrestore(&info->slock, flags); + if (capable(CAP_SYS_ADMIN)) { + if (info->tty) + set_bit(TTY_IO_ERROR, &info->tty->flags); + return 0; + } else + return -ENODEV; } + /* + * Clear the interrupt registers. + */ + (void) inb(info->ioaddr + UART_LSR); + (void) inb(info->ioaddr + UART_RX); + (void) inb(info->ioaddr + UART_IIR); + (void) inb(info->ioaddr + UART_MSR); + + /* + * Now, initialize the UART + */ + outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */ + info->MCR = UART_MCR_DTR | UART_MCR_RTS; + outb(info->MCR, info->ioaddr + UART_MCR); + + /* + * Finally, enable interrupts + */ + info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; + + if (info->board->chip_flag) + info->IER |= MOXA_MUST_IER_EGDAI; + outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */ + + /* + * And clear the interrupt registers again for luck. + */ + (void) inb(info->ioaddr + UART_LSR); + (void) inb(info->ioaddr + UART_RX); + (void) inb(info->ioaddr + UART_IIR); + (void) inb(info->ioaddr + UART_MSR); + + if (info->tty) + clear_bit(TTY_IO_ERROR, &info->tty->flags); + info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; + + /* + * and set the speed of the serial port + */ + mxser_change_speed(info, NULL); + info->flags |= ASYNC_INITIALIZED; + spin_unlock_irqrestore(&info->slock, flags); + return 0; } -static void mxser_do_softint(struct work_struct *work) +/* + * This routine will shutdown a serial port; interrupts maybe disabled, and + * DTR is dropped if the hangup on close termio flag is on. + */ +static void mxser_shutdown(struct mxser_port *info) { - struct mxser_struct *info = - container_of(work, struct mxser_struct, tqueue); - struct tty_struct *tty; + unsigned long flags; - tty = info->tty; + if (!(info->flags & ASYNC_INITIALIZED)) + return; + + spin_lock_irqsave(&info->slock, flags); + + /* + * clear delta_msr_wait queue to avoid mem leaks: we may free the irq + * here so the queue might never be waken up + */ + wake_up_interruptible(&info->delta_msr_wait); - if (tty) { - if (test_and_clear_bit(MXSER_EVENT_TXLOW, &info->event)) - tty_wakeup(tty); - if (test_and_clear_bit(MXSER_EVENT_HANGUP, &info->event)) - tty_hangup(tty); + /* + * Free the IRQ, if necessary + */ + if (info->xmit_buf) { + free_page((unsigned long) info->xmit_buf); + info->xmit_buf = NULL; } -} -static unsigned char mxser_get_msr(int baseaddr, int mode, int port, struct mxser_struct *info) -{ - unsigned char status = 0; + info->IER = 0; + outb(0x00, info->ioaddr + UART_IER); - status = inb(baseaddr + UART_MSR); + if (!info->tty || (info->tty->termios->c_cflag & HUPCL)) + info->MCR &= ~(UART_MCR_DTR | UART_MCR_RTS); + outb(info->MCR, info->ioaddr + UART_MCR); - mxser_msr[port] &= 0x0F; - mxser_msr[port] |= status; - status = mxser_msr[port]; - if (mode) - mxser_msr[port] = 0; + /* clear Rx/Tx FIFO's */ + if (info->board->chip_flag) + outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | + MOXA_MUST_FCR_GDA_MODE_ENABLE, + info->ioaddr + UART_FCR); + else + outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, + info->ioaddr + UART_FCR); - return status; + /* read data port to reset things */ + (void) inb(info->ioaddr + UART_RX); + + if (info->tty) + set_bit(TTY_IO_ERROR, &info->tty->flags); + + info->flags &= ~ASYNC_INITIALIZED; + + if (info->board->chip_flag) + SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->ioaddr); + + spin_unlock_irqrestore(&info->slock, flags); } /* @@ -957,19 +893,17 @@ static unsigned char mxser_get_msr(int baseaddr, int mode, int port, struct mxse */ static int mxser_open(struct tty_struct *tty, struct file *filp) { - struct mxser_struct *info; + struct mxser_port *info; + unsigned long flags; int retval, line; - /* initialize driver_data in case something fails */ - tty->driver_data = NULL; - line = tty->index; if (line == MXSER_PORTS) return 0; if (line < 0 || line > MXSER_PORTS) return -ENODEV; - info = mxvar_table + line; - if (!info->base) + info = &mxser_boards[line / MXSER_PORTS_PER_BOARD].ports[line % MXSER_PORTS_PER_BOARD]; + if (!info->ioaddr) return -ENODEV; tty->driver_data = info; @@ -977,6 +911,9 @@ static int mxser_open(struct tty_struct *tty, struct file *filp) /* * Start up serial port */ + spin_lock_irqsave(&info->slock, flags); + info->count++; + spin_unlock_irqrestore(&info->slock, flags); retval = mxser_startup(info); if (retval) return retval; @@ -985,21 +922,6 @@ static int mxser_open(struct tty_struct *tty, struct file *filp) if (retval) return retval; - info->count++; - - if ((info->count == 1) && (info->flags & ASYNC_SPLIT_TERMIOS)) { - if (tty->driver->subtype == SERIAL_TYPE_NORMAL) - *tty->termios = info->normal_termios; - else - *tty->termios = info->callout_termios; - mxser_change_speed(info, NULL); - } - - /* - status = mxser_get_msr(info->base, 0, info->port); - mxser_check_modem_status(info, status); - */ - /* unmark here for very high baud rate (ex. 921600 bps) used */ tty->low_latency = 1; return 0; @@ -1013,11 +935,10 @@ static int mxser_open(struct tty_struct *tty, struct file *filp) */ static void mxser_close(struct tty_struct *tty, struct file *filp) { - struct mxser_struct *info = tty->driver_data; + struct mxser_port *info = tty->driver_data; unsigned long timeout; unsigned long flags; - struct tty_ldisc *ld; if (tty->index == MXSER_PORTS) return; @@ -1044,7 +965,7 @@ static void mxser_close(struct tty_struct *tty, struct file *filp) } if (--info->count < 0) { printk(KERN_ERR "mxser_close: bad serial port count for " - "ttys%d: %d\n", info->port, info->count); + "ttys%d: %d\n", tty->index, info->count); info->count = 0; } if (info->count) { @@ -1073,20 +994,18 @@ static void mxser_close(struct tty_struct *tty, struct file *filp) * line status register. */ info->IER &= ~UART_IER_RLSI; - if (info->IsMoxaMustChipFlag) + if (info->board->chip_flag) info->IER &= ~MOXA_MUST_RECV_ISR; -/* by William - info->read_status_mask &= ~UART_LSR_DR; -*/ + if (info->flags & ASYNC_INITIALIZED) { - outb(info->IER, info->base + UART_IER); + outb(info->IER, info->ioaddr + UART_IER); /* * Before we drop DTR, make sure the UART transmitter * has completely drained; this is especially * important if there is a transmit FIFO! */ timeout = jiffies + HZ; - while (!(inb(info->base + UART_LSR) & UART_LSR_TEMT)) { + while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) { schedule_timeout_interruptible(5); if (time_after(jiffies, timeout)) break; @@ -1096,14 +1015,9 @@ static void mxser_close(struct tty_struct *tty, struct file *filp) if (tty->driver->flush_buffer) tty->driver->flush_buffer(tty); - - ld = tty_ldisc_ref(tty); - if (ld) { - if (ld->flush_buffer) - ld->flush_buffer(tty); - tty_ldisc_deref(ld); - } - + + tty_ldisc_flush(tty); + tty->closing = 0; info->event = 0; info->tty = NULL; @@ -1114,14 +1028,12 @@ static void mxser_close(struct tty_struct *tty, struct file *filp) } info->flags &= ~(ASYNC_NORMAL_ACTIVE | ASYNC_CLOSING); - wake_up_interruptible(&info->close_wait); - } static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count) { int c, total = 0; - struct mxser_struct *info = tty->driver_data; + struct mxser_port *info = tty->driver_data; unsigned long flags; if (!info->xmit_buf) @@ -1145,13 +1057,15 @@ static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int cou total += c; } - if (info->xmit_cnt && !tty->stopped && !(info->IER & UART_IER_THRI)) { + if (info->xmit_cnt && !tty->stopped) { if (!tty->hw_stopped || (info->type == PORT_16550A) || - (info->IsMoxaMustChipFlag)) { + (info->board->chip_flag)) { spin_lock_irqsave(&info->slock, flags); + outb(info->IER & ~UART_IER_THRI, info->ioaddr + + UART_IER); info->IER |= UART_IER_THRI; - outb(info->IER, info->base + UART_IER); + outb(info->IER, info->ioaddr + UART_IER); spin_unlock_irqrestore(&info->slock, flags); } } @@ -1160,7 +1074,7 @@ static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int cou static void mxser_put_char(struct tty_struct *tty, unsigned char ch) { - struct mxser_struct *info = tty->driver_data; + struct mxser_port *info = tty->driver_data; unsigned long flags; if (!info->xmit_buf) @@ -1174,13 +1088,14 @@ static void mxser_put_char(struct tty_struct *tty, unsigned char ch) info->xmit_head &= SERIAL_XMIT_SIZE - 1; info->xmit_cnt++; spin_unlock_irqrestore(&info->slock, flags); - if (!tty->stopped && !(info->IER & UART_IER_THRI)) { + if (!tty->stopped) { if (!tty->hw_stopped || (info->type == PORT_16550A) || - info->IsMoxaMustChipFlag) { + info->board->chip_flag) { spin_lock_irqsave(&info->slock, flags); + outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); info->IER |= UART_IER_THRI; - outb(info->IER, info->base + UART_IER); + outb(info->IER, info->ioaddr + UART_IER); spin_unlock_irqrestore(&info->slock, flags); } } @@ -1189,7 +1104,7 @@ static void mxser_put_char(struct tty_struct *tty, unsigned char ch) static void mxser_flush_chars(struct tty_struct *tty) { - struct mxser_struct *info = tty->driver_data; + struct mxser_port *info = tty->driver_data; unsigned long flags; if (info->xmit_cnt <= 0 || @@ -1197,21 +1112,22 @@ static void mxser_flush_chars(struct tty_struct *tty) !info->xmit_buf || (tty->hw_stopped && (info->type != PORT_16550A) && - (!info->IsMoxaMustChipFlag) + (!info->board->chip_flag) )) return; spin_lock_irqsave(&info->slock, flags); + outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); info->IER |= UART_IER_THRI; - outb(info->IER, info->base + UART_IER); + outb(info->IER, info->ioaddr + UART_IER); spin_unlock_irqrestore(&info->slock, flags); } static int mxser_write_room(struct tty_struct *tty) { - struct mxser_struct *info = tty->driver_data; + struct mxser_port *info = tty->driver_data; int ret; ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1; @@ -1222,13 +1138,13 @@ static int mxser_write_room(struct tty_struct *tty) static int mxser_chars_in_buffer(struct tty_struct *tty) { - struct mxser_struct *info = tty->driver_data; + struct mxser_port *info = tty->driver_data; return info->xmit_cnt; } static void mxser_flush_buffer(struct tty_struct *tty) { - struct mxser_struct *info = tty->driver_data; + struct mxser_port *info = tty->driver_data; char fcr; unsigned long flags; @@ -1236,39 +1152,497 @@ static void mxser_flush_buffer(struct tty_struct *tty) spin_lock_irqsave(&info->slock, flags); info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; - /* below added by shinhay */ - fcr = inb(info->base + UART_FCR); + fcr = inb(info->ioaddr + UART_FCR); outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT), - info->base + UART_FCR); - outb(fcr, info->base + UART_FCR); + info->ioaddr + UART_FCR); + outb(fcr, info->ioaddr + UART_FCR); spin_unlock_irqrestore(&info->slock, flags); - /* above added by shinhay */ tty_wakeup(tty); } -static int mxser_ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg) +/* + * ------------------------------------------------------------ + * friends of mxser_ioctl() + * ------------------------------------------------------------ + */ +static int mxser_get_serial_info(struct mxser_port *info, + struct serial_struct __user *retinfo) { - struct mxser_struct *info = tty->driver_data; - int retval; - struct async_icount cprev, cnow; /* kernel counter temps */ + struct serial_struct tmp = { + .type = info->type, + .line = info->tty->index, + .port = info->ioaddr, + .irq = info->board->irq, + .flags = info->flags, + .baud_base = info->baud_base, + .close_delay = info->close_delay, + .closing_wait = info->closing_wait, + .custom_divisor = info->custom_divisor, + .hub6 = 0 + }; + if (copy_to_user(retinfo, &tmp, sizeof(*retinfo))) + return -EFAULT; + return 0; +} + +static int mxser_set_serial_info(struct mxser_port *info, + struct serial_struct __user *new_info) +{ + struct serial_struct new_serial; + speed_t baud; + unsigned long sl_flags; + unsigned int flags; + int retval = 0; + + if (!new_info || !info->ioaddr) + return -ENODEV; + if (copy_from_user(&new_serial, new_info, sizeof(new_serial))) + return -EFAULT; + + if (new_serial.irq != info->board->irq || + new_serial.port != info->ioaddr) + return -EINVAL; + + flags = info->flags & ASYNC_SPD_MASK; + + if (!capable(CAP_SYS_ADMIN)) { + if ((new_serial.baud_base != info->baud_base) || + (new_serial.close_delay != info->close_delay) || + ((new_serial.flags & ~ASYNC_USR_MASK) != (info->flags & ~ASYNC_USR_MASK))) + return -EPERM; + info->flags = ((info->flags & ~ASYNC_USR_MASK) | + (new_serial.flags & ASYNC_USR_MASK)); + } else { + /* + * OK, past this point, all the error checking has been done. + * At this point, we start making changes..... + */ + info->flags = ((info->flags & ~ASYNC_FLAGS) | + (new_serial.flags & ASYNC_FLAGS)); + info->close_delay = new_serial.close_delay * HZ / 100; + info->closing_wait = new_serial.closing_wait * HZ / 100; + info->tty->low_latency = + (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; + info->tty->low_latency = 0; + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST && + (new_serial.baud_base != info->baud_base || + new_serial.custom_divisor != + info->custom_divisor)) { + baud = new_serial.baud_base / new_serial.custom_divisor; + tty_encode_baud_rate(info->tty, baud, baud); + } + } + + info->type = new_serial.type; + + process_txrx_fifo(info); + + if (info->flags & ASYNC_INITIALIZED) { + if (flags != (info->flags & ASYNC_SPD_MASK)) { + spin_lock_irqsave(&info->slock, sl_flags); + mxser_change_speed(info, NULL); + spin_unlock_irqrestore(&info->slock, sl_flags); + } + } else + retval = mxser_startup(info); + + return retval; +} + +/* + * mxser_get_lsr_info - get line status register info + * + * Purpose: Let user call ioctl() to get info when the UART physically + * is emptied. On bus types like RS485, the transmitter must + * release the bus after transmitting. This must be done when + * the transmit shift register is empty, not be done when the + * transmit holding register is empty. This functionality + * allows an RS485 driver to be written in user space. + */ +static int mxser_get_lsr_info(struct mxser_port *info, + unsigned int __user *value) +{ + unsigned char status; + unsigned int result; + unsigned long flags; + + spin_lock_irqsave(&info->slock, flags); + status = inb(info->ioaddr + UART_LSR); + spin_unlock_irqrestore(&info->slock, flags); + result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0); + return put_user(result, value); +} + +/* + * This routine sends a break character out the serial port. + */ +static void mxser_send_break(struct mxser_port *info, int duration) +{ + unsigned long flags; + + if (!info->ioaddr) + return; + set_current_state(TASK_INTERRUPTIBLE); + spin_lock_irqsave(&info->slock, flags); + outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC, + info->ioaddr + UART_LCR); + spin_unlock_irqrestore(&info->slock, flags); + schedule_timeout(duration); + spin_lock_irqsave(&info->slock, flags); + outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC, + info->ioaddr + UART_LCR); + spin_unlock_irqrestore(&info->slock, flags); +} + +static int mxser_tiocmget(struct tty_struct *tty, struct file *file) +{ + struct mxser_port *info = tty->driver_data; + unsigned char control, status; + unsigned long flags; + + + if (tty->index == MXSER_PORTS) + return -ENOIOCTLCMD; + if (test_bit(TTY_IO_ERROR, &tty->flags)) + return -EIO; + + control = info->MCR; + + spin_lock_irqsave(&info->slock, flags); + status = inb(info->ioaddr + UART_MSR); + if (status & UART_MSR_ANY_DELTA) + mxser_check_modem_status(info, status); + spin_unlock_irqrestore(&info->slock, flags); + return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) | + ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) | + ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) | + ((status & UART_MSR_RI) ? TIOCM_RNG : 0) | + ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) | + ((status & UART_MSR_CTS) ? TIOCM_CTS : 0); +} + +static int mxser_tiocmset(struct tty_struct *tty, struct file *file, + unsigned int set, unsigned int clear) +{ + struct mxser_port *info = tty->driver_data; + unsigned long flags; + + + if (tty->index == MXSER_PORTS) + return -ENOIOCTLCMD; + if (test_bit(TTY_IO_ERROR, &tty->flags)) + return -EIO; + + spin_lock_irqsave(&info->slock, flags); + + if (set & TIOCM_RTS) + info->MCR |= UART_MCR_RTS; + if (set & TIOCM_DTR) + info->MCR |= UART_MCR_DTR; + + if (clear & TIOCM_RTS) + info->MCR &= ~UART_MCR_RTS; + if (clear & TIOCM_DTR) + info->MCR &= ~UART_MCR_DTR; + + outb(info->MCR, info->ioaddr + UART_MCR); + spin_unlock_irqrestore(&info->slock, flags); + return 0; +} + +static int __init mxser_program_mode(int port) +{ + int id, i, j, n; + + outb(0, port); + outb(0, port); + outb(0, port); + (void)inb(port); + (void)inb(port); + outb(0, port); + (void)inb(port); + + id = inb(port + 1) & 0x1F; + if ((id != C168_ASIC_ID) && + (id != C104_ASIC_ID) && + (id != C102_ASIC_ID) && + (id != CI132_ASIC_ID) && + (id != CI134_ASIC_ID) && + (id != CI104J_ASIC_ID)) + return -1; + for (i = 0, j = 0; i < 4; i++) { + n = inb(port + 2); + if (n == 'M') { + j = 1; + } else if ((j == 1) && (n == 1)) { + j = 2; + break; + } else + j = 0; + } + if (j != 2) + id = -2; + return id; +} + +static void __init mxser_normal_mode(int port) +{ + int i, n; + + outb(0xA5, port + 1); + outb(0x80, port + 3); + outb(12, port + 0); /* 9600 bps */ + outb(0, port + 1); + outb(0x03, port + 3); /* 8 data bits */ + outb(0x13, port + 4); /* loop back mode */ + for (i = 0; i < 16; i++) { + n = inb(port + 5); + if ((n & 0x61) == 0x60) + break; + if ((n & 1) == 1) + (void)inb(port); + } + outb(0x00, port + 4); +} + +#define CHIP_SK 0x01 /* Serial Data Clock in Eprom */ +#define CHIP_DO 0x02 /* Serial Data Output in Eprom */ +#define CHIP_CS 0x04 /* Serial Chip Select in Eprom */ +#define CHIP_DI 0x08 /* Serial Data Input in Eprom */ +#define EN_CCMD 0x000 /* Chip's command register */ +#define EN0_RSARLO 0x008 /* Remote start address reg 0 */ +#define EN0_RSARHI 0x009 /* Remote start address reg 1 */ +#define EN0_RCNTLO 0x00A /* Remote byte count reg WR */ +#define EN0_RCNTHI 0x00B /* Remote byte count reg WR */ +#define EN0_DCFG 0x00E /* Data configuration reg WR */ +#define EN0_PORT 0x010 /* Rcv missed frame error counter RD */ +#define ENC_PAGE0 0x000 /* Select page 0 of chip registers */ +#define ENC_PAGE3 0x0C0 /* Select page 3 of chip registers */ +static int __init mxser_read_register(int port, unsigned short *regs) +{ + int i, k, value, id; + unsigned int j; + + id = mxser_program_mode(port); + if (id < 0) + return id; + for (i = 0; i < 14; i++) { + k = (i & 0x3F) | 0x180; + for (j = 0x100; j > 0; j >>= 1) { + outb(CHIP_CS, port); + if (k & j) { + outb(CHIP_CS | CHIP_DO, port); + outb(CHIP_CS | CHIP_DO | CHIP_SK, port); /* A? bit of read */ + } else { + outb(CHIP_CS, port); + outb(CHIP_CS | CHIP_SK, port); /* A? bit of read */ + } + } + (void)inb(port); + value = 0; + for (k = 0, j = 0x8000; k < 16; k++, j >>= 1) { + outb(CHIP_CS, port); + outb(CHIP_CS | CHIP_SK, port); + if (inb(port) & CHIP_DI) + value |= j; + } + regs[i] = value; + outb(0, port); + } + mxser_normal_mode(port); + return id; +} + +static int mxser_ioctl_special(unsigned int cmd, void __user *argp) +{ + struct mxser_port *port; + int result, status; + unsigned int i, j; + + switch (cmd) { + case MOXA_GET_MAJOR: + return put_user(ttymajor, (int __user *)argp); + + case MOXA_CHKPORTENABLE: + result = 0; + + for (i = 0; i < MXSER_BOARDS; i++) + for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) + if (mxser_boards[i].ports[j].ioaddr) + result |= (1 << i); + + return put_user(result, (unsigned long __user *)argp); + case MOXA_GETDATACOUNT: + if (copy_to_user(argp, &mxvar_log, sizeof(mxvar_log))) + return -EFAULT; + return 0; + case MOXA_GETMSTATUS: + for (i = 0; i < MXSER_BOARDS; i++) + for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) { + port = &mxser_boards[i].ports[j]; + + GMStatus[i].ri = 0; + if (!port->ioaddr) { + GMStatus[i].dcd = 0; + GMStatus[i].dsr = 0; + GMStatus[i].cts = 0; + continue; + } + + if (!port->tty || !port->tty->termios) + GMStatus[i].cflag = + port->normal_termios.c_cflag; + else + GMStatus[i].cflag = + port->tty->termios->c_cflag; + + status = inb(port->ioaddr + UART_MSR); + if (status & 0x80 /*UART_MSR_DCD */ ) + GMStatus[i].dcd = 1; + else + GMStatus[i].dcd = 0; + + if (status & 0x20 /*UART_MSR_DSR */ ) + GMStatus[i].dsr = 1; + else + GMStatus[i].dsr = 0; + + + if (status & 0x10 /*UART_MSR_CTS */ ) + GMStatus[i].cts = 1; + else + GMStatus[i].cts = 0; + } + if (copy_to_user(argp, GMStatus, + sizeof(struct mxser_mstatus) * MXSER_PORTS)) + return -EFAULT; + return 0; + case MOXA_ASPP_MON_EXT: { + int p, shiftbit; + unsigned long opmode; + unsigned cflag, iflag; + + for (i = 0; i < MXSER_BOARDS; i++) + for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) { + port = &mxser_boards[i].ports[j]; + if (!port->ioaddr) + continue; + + status = mxser_get_msr(port->ioaddr, 0, i); + + if (status & UART_MSR_TERI) + port->icount.rng++; + if (status & UART_MSR_DDSR) + port->icount.dsr++; + if (status & UART_MSR_DDCD) + port->icount.dcd++; + if (status & UART_MSR_DCTS) + port->icount.cts++; + + port->mon_data.modem_status = status; + mon_data_ext.rx_cnt[i] = port->mon_data.rxcnt; + mon_data_ext.tx_cnt[i] = port->mon_data.txcnt; + mon_data_ext.up_rxcnt[i] = + port->mon_data.up_rxcnt; + mon_data_ext.up_txcnt[i] = + port->mon_data.up_txcnt; + mon_data_ext.modem_status[i] = + port->mon_data.modem_status; + mon_data_ext.baudrate[i] = + tty_get_baud_rate(port->tty); + + if (!port->tty || !port->tty->termios) { + cflag = port->normal_termios.c_cflag; + iflag = port->normal_termios.c_iflag; + } else { + cflag = port->tty->termios->c_cflag; + iflag = port->tty->termios->c_iflag; + } + + mon_data_ext.databits[i] = cflag & CSIZE; + + mon_data_ext.stopbits[i] = cflag & CSTOPB; + + mon_data_ext.parity[i] = + cflag & (PARENB | PARODD | CMSPAR); + + mon_data_ext.flowctrl[i] = 0x00; + + if (cflag & CRTSCTS) + mon_data_ext.flowctrl[i] |= 0x03; + + if (iflag & (IXON | IXOFF)) + mon_data_ext.flowctrl[i] |= 0x0C; + + if (port->type == PORT_16550A) + mon_data_ext.fifo[i] = 1; + else + mon_data_ext.fifo[i] = 0; + + p = i % 4; + shiftbit = p * 2; + opmode = inb(port->opmode_ioaddr) >> shiftbit; + opmode &= OP_MODE_MASK; + + mon_data_ext.iftype[i] = opmode; + + } + if (copy_to_user(argp, &mon_data_ext, + sizeof(mon_data_ext))) + return -EFAULT; + + return 0; + + } default: + return -ENOIOCTLCMD; + } + return 0; +} + +static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg, + struct async_icount *cprev) +{ + struct async_icount cnow; + unsigned long flags; + int ret; + + spin_lock_irqsave(&info->slock, flags); + cnow = info->icount; /* atomic copy */ + spin_unlock_irqrestore(&info->slock, flags); + + ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) || + ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) || + ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) || + ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts)); + + *cprev = cnow; + + return ret; +} + +static int mxser_ioctl(struct tty_struct *tty, struct file *file, + unsigned int cmd, unsigned long arg) +{ + struct mxser_port *info = tty->driver_data; + struct async_icount cnow; struct serial_icounter_struct __user *p_cuser; - unsigned long templ; unsigned long flags; void __user *argp = (void __user *)arg; + int retval; if (tty->index == MXSER_PORTS) return mxser_ioctl_special(cmd, argp); - /* following add by Victor Yu. 01-05-2004 */ if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) { - int opmode, p; + int p; + unsigned long opmode; static unsigned char ModeMask[] = { 0xfc, 0xf3, 0xcf, 0x3f }; int shiftbit; unsigned char val, mask; - p = info->port % 4; + p = tty->index % 4; if (cmd == MOXA_SET_OP_MODE) { if (get_user(opmode, (int __user *) argp)) return -EFAULT; @@ -1287,17 +1661,16 @@ static int mxser_ioctl(struct tty_struct *tty, struct file *file, unsigned int c shiftbit = p * 2; opmode = inb(info->opmode_ioaddr) >> shiftbit; opmode &= OP_MODE_MASK; - if (copy_to_user(argp, &opmode, sizeof(int))) + if (put_user(opmode, (int __user *)argp)) return -EFAULT; } return 0; } - /* above add by Victor Yu. 01-05-2004 */ - if ((cmd != TIOCGSERIAL) && (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) { - if (tty->flags & (1 << TTY_IO_ERROR)) - return -EIO; - } + if (cmd != TIOCGSERIAL && cmd != TIOCMIWAIT && cmd != TIOCGICOUNT && + test_bit(TTY_IO_ERROR, &tty->flags)) + return -EIO; + switch (cmd) { case TCSBRK: /* SVID version: non-zero arg --> no break */ retval = tty_check_change(tty); @@ -1315,11 +1688,10 @@ static int mxser_ioctl(struct tty_struct *tty, struct file *file, unsigned int c mxser_send_break(info, arg ? arg * (HZ / 10) : HZ / 4); return 0; case TIOCGSOFTCAR: - return put_user(C_CLOCAL(tty) ? 1 : 0, (unsigned long __user *)argp); + return put_user(!!C_CLOCAL(tty), (unsigned long __user *)argp); case TIOCSSOFTCAR: - if (get_user(templ, (unsigned long __user *) argp)) + if (get_user(arg, (unsigned long __user *)argp)) return -EFAULT; - arg = templ; tty->termios->c_cflag = ((tty->termios->c_cflag & ~CLOCAL) | (arg ? CLOCAL : 0)); return 0; case TIOCGSERIAL: @@ -1339,30 +1711,19 @@ static int mxser_ioctl(struct tty_struct *tty, struct file *file, unsigned int c cnow = info->icount; /* note the counters on entry */ spin_unlock_irqrestore(&info->slock, flags); - wait_event_interruptible(info->delta_msr_wait, ({ - cprev = cnow; - spin_lock_irqsave(&info->slock, flags); - cnow = info->icount; /* atomic copy */ - spin_unlock_irqrestore(&info->slock, flags); - - ((arg & TIOCM_RNG) && (cnow.rng != cprev.rng)) || - ((arg & TIOCM_DSR) && (cnow.dsr != cprev.dsr)) || - ((arg & TIOCM_CD) && (cnow.dcd != cprev.dcd)) || - ((arg & TIOCM_CTS) && (cnow.cts != cprev.cts)); - })); - break; - /* - * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) - * Return: write counters to the user passed counter struct - * NB: both 1->0 and 0->1 transitions are counted except for - * RI where only 0->1 is counted. - */ + return wait_event_interruptible(info->delta_msr_wait, + mxser_cflags_changed(info, arg, &cnow)); + /* + * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) + * Return: write counters to the user passed counter struct + * NB: both 1->0 and 0->1 transitions are counted except for + * RI where only 0->1 is counted. + */ case TIOCGICOUNT: spin_lock_irqsave(&info->slock, flags); cnow = info->icount; spin_unlock_irqrestore(&info->slock, flags); p_cuser = argp; - /* modified by casper 1/11/2000 */ if (put_user(cnow.frame, &p_cuser->frame)) return -EFAULT; if (put_user(cnow.brk, &p_cuser->brk)) @@ -1384,240 +1745,65 @@ static int mxser_ioctl(struct tty_struct *tty, struct file *file, unsigned int c return 0; case MOXA_HighSpeedOn: return put_user(info->baud_base != 115200 ? 1 : 0, (int __user *)argp); - case MOXA_SDS_RSTICOUNTER: { - info->mon_data.rxcnt = 0; - info->mon_data.txcnt = 0; - return 0; - } -/* (above) added by James. */ - case MOXA_ASPP_SETBAUD:{ - long baud; - if (get_user(baud, (long __user *)argp)) - return -EFAULT; - mxser_set_baud(info, baud); - return 0; - } - case MOXA_ASPP_GETBAUD: - if (copy_to_user(argp, &info->realbaud, sizeof(long))) - return -EFAULT; - + case MOXA_SDS_RSTICOUNTER: + info->mon_data.rxcnt = 0; + info->mon_data.txcnt = 0; return 0; case MOXA_ASPP_OQUEUE:{ - int len, lsr; + int len, lsr; - len = mxser_chars_in_buffer(tty); + len = mxser_chars_in_buffer(tty); - lsr = inb(info->base + UART_LSR) & UART_LSR_TEMT; + lsr = inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT; - len += (lsr ? 0 : 1); + len += (lsr ? 0 : 1); - if (copy_to_user(argp, &len, sizeof(int))) - return -EFAULT; - - return 0; - } + return put_user(len, (int __user *)argp); + } case MOXA_ASPP_MON: { - int mcr, status; - - /* info->mon_data.ser_param = tty->termios->c_cflag; */ + int mcr, status; - status = mxser_get_msr(info->base, 1, info->port, info); - mxser_check_modem_status(info, status); - - mcr = inb(info->base + UART_MCR); - if (mcr & MOXA_MUST_MCR_XON_FLAG) - info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFHOLD; - else - info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFHOLD; - - if (mcr & MOXA_MUST_MCR_TX_XON) - info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFXENT; - else - info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFXENT; - - if (info->tty->hw_stopped) - info->mon_data.hold_reason |= NPPI_NOTIFY_CTSHOLD; - else - info->mon_data.hold_reason &= ~NPPI_NOTIFY_CTSHOLD; - - if (copy_to_user(argp, &info->mon_data, - sizeof(struct mxser_mon))) - return -EFAULT; - - return 0; - } - - case MOXA_ASPP_LSTATUS: { - if (copy_to_user(argp, &info->err_shadow, - sizeof(unsigned char))) - return -EFAULT; - - info->err_shadow = 0; - return 0; - } - case MOXA_SET_BAUD_METHOD: { - int method; - - if (get_user(method, (int __user *)argp)) - return -EFAULT; - mxser_set_baud_method[info->port] = method; - if (copy_to_user(argp, &method, sizeof(int))) - return -EFAULT; + status = mxser_get_msr(info->ioaddr, 1, tty->index); + mxser_check_modem_status(info, status); - return 0; - } - default: - return -ENOIOCTLCMD; - } - return 0; -} + mcr = inb(info->ioaddr + UART_MCR); + if (mcr & MOXA_MUST_MCR_XON_FLAG) + info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFHOLD; + else + info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFHOLD; -#ifndef CMSPAR -#define CMSPAR 010000000000 -#endif + if (mcr & MOXA_MUST_MCR_TX_XON) + info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFXENT; + else + info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFXENT; -static int mxser_ioctl_special(unsigned int cmd, void __user *argp) -{ - int i, result, status; + if (info->tty->hw_stopped) + info->mon_data.hold_reason |= NPPI_NOTIFY_CTSHOLD; + else + info->mon_data.hold_reason &= ~NPPI_NOTIFY_CTSHOLD; - switch (cmd) { - case MOXA_GET_CONF: - if (copy_to_user(argp, mxsercfg, - sizeof(struct mxser_hwconf) * 4)) + if (copy_to_user(argp, &info->mon_data, + sizeof(struct mxser_mon))) return -EFAULT; - return 0; - case MOXA_GET_MAJOR: - if (copy_to_user(argp, &ttymajor, sizeof(int))) - return -EFAULT; - return 0; - case MOXA_GET_CUMAJOR: - if (copy_to_user(argp, &calloutmajor, sizeof(int))) - return -EFAULT; return 0; - - case MOXA_CHKPORTENABLE: - result = 0; - for (i = 0; i < MXSER_PORTS; i++) { - if (mxvar_table[i].base) - result |= (1 << i); - } - return put_user(result, (unsigned long __user *)argp); - case MOXA_GETDATACOUNT: - if (copy_to_user(argp, &mxvar_log, sizeof(mxvar_log))) + } + case MOXA_ASPP_LSTATUS: { + if (put_user(info->err_shadow, (unsigned char __user *)argp)) return -EFAULT; - return 0; - case MOXA_GETMSTATUS: - for (i = 0; i < MXSER_PORTS; i++) { - GMStatus[i].ri = 0; - if (!mxvar_table[i].base) { - GMStatus[i].dcd = 0; - GMStatus[i].dsr = 0; - GMStatus[i].cts = 0; - continue; - } - - if (!mxvar_table[i].tty || !mxvar_table[i].tty->termios) - GMStatus[i].cflag = mxvar_table[i].normal_termios.c_cflag; - else - GMStatus[i].cflag = mxvar_table[i].tty->termios->c_cflag; - - status = inb(mxvar_table[i].base + UART_MSR); - if (status & 0x80 /*UART_MSR_DCD */ ) - GMStatus[i].dcd = 1; - else - GMStatus[i].dcd = 0; - - if (status & 0x20 /*UART_MSR_DSR */ ) - GMStatus[i].dsr = 1; - else - GMStatus[i].dsr = 0; - - if (status & 0x10 /*UART_MSR_CTS */ ) - GMStatus[i].cts = 1; - else - GMStatus[i].cts = 0; - } - if (copy_to_user(argp, GMStatus, - sizeof(struct mxser_mstatus) * MXSER_PORTS)) - return -EFAULT; + info->err_shadow = 0; return 0; - case MOXA_ASPP_MON_EXT: { - int status; - int opmode, p; - int shiftbit; - unsigned cflag, iflag; - - for (i = 0; i < MXSER_PORTS; i++) { - if (!mxvar_table[i].base) - continue; - - status = mxser_get_msr(mxvar_table[i].base, 0, - i, &(mxvar_table[i])); - /* - mxser_check_modem_status(&mxvar_table[i], - status); - */ - if (status & UART_MSR_TERI) - mxvar_table[i].icount.rng++; - if (status & UART_MSR_DDSR) - mxvar_table[i].icount.dsr++; - if (status & UART_MSR_DDCD) - mxvar_table[i].icount.dcd++; - if (status & UART_MSR_DCTS) - mxvar_table[i].icount.cts++; - - mxvar_table[i].mon_data.modem_status = status; - mon_data_ext.rx_cnt[i] = mxvar_table[i].mon_data.rxcnt; - mon_data_ext.tx_cnt[i] = mxvar_table[i].mon_data.txcnt; - mon_data_ext.up_rxcnt[i] = mxvar_table[i].mon_data.up_rxcnt; - mon_data_ext.up_txcnt[i] = mxvar_table[i].mon_data.up_txcnt; - mon_data_ext.modem_status[i] = mxvar_table[i].mon_data.modem_status; - mon_data_ext.baudrate[i] = mxvar_table[i].realbaud; - - if (!mxvar_table[i].tty || !mxvar_table[i].tty->termios) { - cflag = mxvar_table[i].normal_termios.c_cflag; - iflag = mxvar_table[i].normal_termios.c_iflag; - } else { - cflag = mxvar_table[i].tty->termios->c_cflag; - iflag = mxvar_table[i].tty->termios->c_iflag; - } - - mon_data_ext.databits[i] = cflag & CSIZE; - - mon_data_ext.stopbits[i] = cflag & CSTOPB; - - mon_data_ext.parity[i] = cflag & (PARENB | PARODD | CMSPAR); - - mon_data_ext.flowctrl[i] = 0x00; - - if (cflag & CRTSCTS) - mon_data_ext.flowctrl[i] |= 0x03; - - if (iflag & (IXON | IXOFF)) - mon_data_ext.flowctrl[i] |= 0x0C; - - if (mxvar_table[i].type == PORT_16550A) - mon_data_ext.fifo[i] = 1; - else - mon_data_ext.fifo[i] = 0; - - p = i % 4; - shiftbit = p * 2; - opmode = inb(mxvar_table[i].opmode_ioaddr) >> shiftbit; - opmode &= OP_MODE_MASK; - - mon_data_ext.iftype[i] = opmode; - - } - if (copy_to_user(argp, &mon_data_ext, sizeof(struct mxser_mon_ext))) - return -EFAULT; - - return 0; + } + case MOXA_SET_BAUD_METHOD: { + int method; - } + if (get_user(method, (int __user *)argp)) + return -EFAULT; + mxser_set_baud_method[tty->index] = method; + return put_user(method, (int __user *)argp); + } default: return -ENOIOCTLCMD; } @@ -1626,107 +1812,105 @@ static int mxser_ioctl_special(unsigned int cmd, void __user *argp) static void mxser_stoprx(struct tty_struct *tty) { - struct mxser_struct *info = tty->driver_data; - /* unsigned long flags; */ + struct mxser_port *info = tty->driver_data; info->ldisc_stop_rx = 1; if (I_IXOFF(tty)) { - /* MX_LOCK(&info->slock); */ - /* following add by Victor Yu. 09-02-2002 */ - if (info->IsMoxaMustChipFlag) { + if (info->board->chip_flag) { info->IER &= ~MOXA_MUST_RECV_ISR; - outb(info->IER, info->base + UART_IER); + outb(info->IER, info->ioaddr + UART_IER); } else { - /* above add by Victor Yu. 09-02-2002 */ info->x_char = STOP_CHAR(tty); - /* mask by Victor Yu. 09-02-2002 */ - /* outb(info->IER, 0); */ - outb(0, info->base + UART_IER); + outb(0, info->ioaddr + UART_IER); info->IER |= UART_IER_THRI; - /* force Tx interrupt */ - outb(info->IER, info->base + UART_IER); - } /* add by Victor Yu. 09-02-2002 */ - /* MX_UNLOCK(&info->slock); */ + outb(info->IER, info->ioaddr + UART_IER); + } } if (info->tty->termios->c_cflag & CRTSCTS) { - /* MX_LOCK(&info->slock); */ info->MCR &= ~UART_MCR_RTS; - outb(info->MCR, info->base + UART_MCR); - /* MX_UNLOCK(&info->slock); */ + outb(info->MCR, info->ioaddr + UART_MCR); } } -static void mxser_startrx(struct tty_struct *tty) +/* + * This routine is called by the upper-layer tty layer to signal that + * incoming characters should be throttled. + */ +static void mxser_throttle(struct tty_struct *tty) +{ + mxser_stoprx(tty); +} + +static void mxser_unthrottle(struct tty_struct *tty) { - struct mxser_struct *info = tty->driver_data; - /* unsigned long flags; */ + struct mxser_port *info = tty->driver_data; + /* startrx */ info->ldisc_stop_rx = 0; if (I_IXOFF(tty)) { if (info->x_char) info->x_char = 0; else { - /* MX_LOCK(&info->slock); */ - - /* following add by Victor Yu. 09-02-2002 */ - if (info->IsMoxaMustChipFlag) { + if (info->board->chip_flag) { info->IER |= MOXA_MUST_RECV_ISR; - outb(info->IER, info->base + UART_IER); + outb(info->IER, info->ioaddr + UART_IER); } else { - /* above add by Victor Yu. 09-02-2002 */ - info->x_char = START_CHAR(tty); - /* mask by Victor Yu. 09-02-2002 */ - /* outb(info->IER, 0); */ - /* add by Victor Yu. 09-02-2002 */ - outb(0, info->base + UART_IER); - /* force Tx interrupt */ + outb(0, info->ioaddr + UART_IER); info->IER |= UART_IER_THRI; - outb(info->IER, info->base + UART_IER); - } /* add by Victor Yu. 09-02-2002 */ - /* MX_UNLOCK(&info->slock); */ + outb(info->IER, info->ioaddr + UART_IER); + } } } if (info->tty->termios->c_cflag & CRTSCTS) { - /* MX_LOCK(&info->slock); */ info->MCR |= UART_MCR_RTS; - outb(info->MCR, info->base + UART_MCR); - /* MX_UNLOCK(&info->slock); */ + outb(info->MCR, info->ioaddr + UART_MCR); } } /* - * This routine is called by the upper-layer tty layer to signal that - * incoming characters should be throttled. + * mxser_stop() and mxser_start() + * + * This routines are called before setting or resetting tty->stopped. + * They enable or disable transmitter interrupts, as necessary. */ -static void mxser_throttle(struct tty_struct *tty) +static void mxser_stop(struct tty_struct *tty) { - /* struct mxser_struct *info = tty->driver_data; */ - /* unsigned long flags; */ + struct mxser_port *info = tty->driver_data; + unsigned long flags; - /* MX_LOCK(&info->slock); */ - mxser_stoprx(tty); - /* MX_UNLOCK(&info->slock); */ + spin_lock_irqsave(&info->slock, flags); + if (info->IER & UART_IER_THRI) { + info->IER &= ~UART_IER_THRI; + outb(info->IER, info->ioaddr + UART_IER); + } + spin_unlock_irqrestore(&info->slock, flags); } -static void mxser_unthrottle(struct tty_struct *tty) +static void mxser_start(struct tty_struct *tty) { - /* struct mxser_struct *info = tty->driver_data; */ - /* unsigned long flags; */ + struct mxser_port *info = tty->driver_data; + unsigned long flags; - /* MX_LOCK(&info->slock); */ - mxser_startrx(tty); - /* MX_UNLOCK(&info->slock); */ + spin_lock_irqsave(&info->slock, flags); + if (info->xmit_cnt && info->xmit_buf) { + outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); + info->IER |= UART_IER_THRI; + outb(info->IER, info->ioaddr + UART_IER); + } + spin_unlock_irqrestore(&info->slock, flags); } static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios) { - struct mxser_struct *info = tty->driver_data; + struct mxser_port *info = tty->driver_data; unsigned long flags; + spin_lock_irqsave(&info->slock, flags); mxser_change_speed(info, old_termios); + spin_unlock_irqrestore(&info->slock, flags); if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) { @@ -1734,61 +1918,27 @@ static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termi mxser_start(tty); } -/* Handle sw stopped */ + /* Handle sw stopped */ if ((old_termios->c_iflag & IXON) && !(tty->termios->c_iflag & IXON)) { tty->stopped = 0; - /* following add by Victor Yu. 09-02-2002 */ - if (info->IsMoxaMustChipFlag) { + if (info->board->chip_flag) { spin_lock_irqsave(&info->slock, flags); - DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->base); + DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr); spin_unlock_irqrestore(&info->slock, flags); } - /* above add by Victor Yu. 09-02-2002 */ mxser_start(tty); } } /* - * mxser_stop() and mxser_start() - * - * This routines are called before setting or resetting tty->stopped. - * They enable or disable transmitter interrupts, as necessary. - */ -static void mxser_stop(struct tty_struct *tty) -{ - struct mxser_struct *info = tty->driver_data; - unsigned long flags; - - spin_lock_irqsave(&info->slock, flags); - if (info->IER & UART_IER_THRI) { - info->IER &= ~UART_IER_THRI; - outb(info->IER, info->base + UART_IER); - } - spin_unlock_irqrestore(&info->slock, flags); -} - -static void mxser_start(struct tty_struct *tty) -{ - struct mxser_struct *info = tty->driver_data; - unsigned long flags; - - spin_lock_irqsave(&info->slock, flags); - if (info->xmit_cnt && info->xmit_buf && !(info->IER & UART_IER_THRI)) { - info->IER |= UART_IER_THRI; - outb(info->IER, info->base + UART_IER); - } - spin_unlock_irqrestore(&info->slock, flags); -} - -/* * mxser_wait_until_sent() --- wait until the transmitter is empty */ static void mxser_wait_until_sent(struct tty_struct *tty, int timeout) { - struct mxser_struct *info = tty->driver_data; + struct mxser_port *info = tty->driver_data; unsigned long orig_jiffies, char_time; int lsr; @@ -1829,7 +1979,7 @@ static void mxser_wait_until_sent(struct tty_struct *tty, int timeout) timeout, char_time); printk("jiff=%lu...", jiffies); #endif - while (!((lsr = inb(info->base + UART_LSR)) & UART_LSR_TEMT)) { + while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) { #ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT printk("lsr = %d (jiff=%lu)...", lsr, jiffies); #endif @@ -1846,13 +1996,12 @@ static void mxser_wait_until_sent(struct tty_struct *tty, int timeout) #endif } - /* * This routine is called by tty_hangup() when a hangup is signaled. */ -void mxser_hangup(struct tty_struct *tty) +static void mxser_hangup(struct tty_struct *tty) { - struct mxser_struct *info = tty->driver_data; + struct mxser_port *info = tty->driver_data; mxser_flush_buffer(tty); mxser_shutdown(info); @@ -1863,231 +2012,73 @@ void mxser_hangup(struct tty_struct *tty) wake_up_interruptible(&info->open_wait); } - -/* added by James 03-12-2004. */ /* * mxser_rs_break() --- routine which turns the break handling on or off */ static void mxser_rs_break(struct tty_struct *tty, int break_state) { - struct mxser_struct *info = tty->driver_data; + struct mxser_port *info = tty->driver_data; unsigned long flags; spin_lock_irqsave(&info->slock, flags); if (break_state == -1) - outb(inb(info->base + UART_LCR) | UART_LCR_SBC, - info->base + UART_LCR); + outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC, + info->ioaddr + UART_LCR); else - outb(inb(info->base + UART_LCR) & ~UART_LCR_SBC, - info->base + UART_LCR); + outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC, + info->ioaddr + UART_LCR); spin_unlock_irqrestore(&info->slock, flags); } -/* (above) added by James. */ - - -/* - * This is the serial driver's generic interrupt routine - */ -static irqreturn_t mxser_interrupt(int irq, void *dev_id) +static void mxser_receive_chars(struct mxser_port *port, int *status) { - int status, iir, i; - struct mxser_struct *info; - struct mxser_struct *port; - int max, irqbits, bits, msr; - int pass_counter = 0; - int handled = IRQ_NONE; - - port = NULL; - /* spin_lock(&gm_lock); */ - - for (i = 0; i < MXSER_BOARDS; i++) { - if (dev_id == &(mxvar_table[i * MXSER_PORTS_PER_BOARD])) { - port = dev_id; - break; - } - } - - if (i == MXSER_BOARDS) - goto irq_stop; - if (port == 0) - goto irq_stop; - max = mxser_numports[mxsercfg[i].board_type - 1]; - while (1) { - irqbits = inb(port->vector) & port->vectormask; - if (irqbits == port->vectormask) - break; - - handled = IRQ_HANDLED; - for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) { - if (irqbits == port->vectormask) - break; - if (bits & irqbits) - continue; - info = port + i; - - /* following add by Victor Yu. 09-13-2002 */ - iir = inb(info->base + UART_IIR); - if (iir & UART_IIR_NO_INT) - continue; - iir &= MOXA_MUST_IIR_MASK; - if (!info->tty) { - status = inb(info->base + UART_LSR); - outb(0x27, info->base + UART_FCR); - inb(info->base + UART_MSR); - continue; - } - - /* mask by Victor Yu. 09-13-2002 - if ( !info->tty || - (inb(info->base + UART_IIR) & UART_IIR_NO_INT) ) - continue; - */ - /* mask by Victor Yu. 09-02-2002 - status = inb(info->base + UART_LSR) & info->read_status_mask; - */ - - /* following add by Victor Yu. 09-02-2002 */ - status = inb(info->base + UART_LSR); - - if (status & UART_LSR_PE) - info->err_shadow |= NPPI_NOTIFY_PARITY; - if (status & UART_LSR_FE) - info->err_shadow |= NPPI_NOTIFY_FRAMING; - if (status & UART_LSR_OE) - info->err_shadow |= NPPI_NOTIFY_HW_OVERRUN; - if (status & UART_LSR_BI) - info->err_shadow |= NPPI_NOTIFY_BREAK; - - if (info->IsMoxaMustChipFlag) { - /* - if ( (status & 0x02) && !(status & 0x01) ) { - outb(info->base+UART_FCR, 0x23); - continue; - } - */ - if (iir == MOXA_MUST_IIR_GDA || - iir == MOXA_MUST_IIR_RDA || - iir == MOXA_MUST_IIR_RTO || - iir == MOXA_MUST_IIR_LSR) - mxser_receive_chars(info, &status); - - } else { - /* above add by Victor Yu. 09-02-2002 */ - - status &= info->read_status_mask; - if (status & UART_LSR_DR) - mxser_receive_chars(info, &status); - } - msr = inb(info->base + UART_MSR); - if (msr & UART_MSR_ANY_DELTA) { - mxser_check_modem_status(info, msr); - } - /* following add by Victor Yu. 09-13-2002 */ - if (info->IsMoxaMustChipFlag) { - if ((iir == 0x02) && (status & UART_LSR_THRE)) { - mxser_transmit_chars(info); - } - } else { - /* above add by Victor Yu. 09-13-2002 */ - - if (status & UART_LSR_THRE) { -/* 8-2-99 by William - if ( info->x_char || (info->xmit_cnt > 0) ) -*/ - mxser_transmit_chars(info); - } - } - } - if (pass_counter++ > MXSER_ISR_PASS_LIMIT) { - break; /* Prevent infinite loops */ - } - } - - irq_stop: - /* spin_unlock(&gm_lock); */ - return handled; -} - -static void mxser_receive_chars(struct mxser_struct *info, int *status) -{ - struct tty_struct *tty = info->tty; + struct tty_struct *tty = port->tty; unsigned char ch, gdl; int ignored = 0; int cnt = 0; int recv_room; int max = 256; - unsigned long flags; - - spin_lock_irqsave(&info->slock, flags); recv_room = tty->receive_room; - if ((recv_room == 0) && (!info->ldisc_stop_rx)) { - /* mxser_throttle(tty); */ + if ((recv_room == 0) && (!port->ldisc_stop_rx)) mxser_stoprx(tty); - /* return; */ - } - /* following add by Victor Yu. 09-02-2002 */ - if (info->IsMoxaMustChipFlag != MOXA_OTHER_UART) { + if (port->board->chip_flag != MOXA_OTHER_UART) { - if (*status & UART_LSR_SPECIAL) { + if (*status & UART_LSR_SPECIAL) goto intr_old; - } - /* following add by Victor Yu. 02-11-2004 */ - if (info->IsMoxaMustChipFlag == MOXA_MUST_MU860_HWID && + if (port->board->chip_flag == MOXA_MUST_MU860_HWID && (*status & MOXA_MUST_LSR_RERR)) goto intr_old; - /* above add by Victor Yu. 02-14-2004 */ if (*status & MOXA_MUST_LSR_RERR) goto intr_old; - gdl = inb(info->base + MOXA_MUST_GDL_REGISTER); + gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER); - /* add by Victor Yu. 02-11-2004 */ - if (info->IsMoxaMustChipFlag == MOXA_MUST_MU150_HWID) + if (port->board->chip_flag == MOXA_MUST_MU150_HWID) gdl &= MOXA_MUST_GDL_MASK; if (gdl >= recv_room) { - if (!info->ldisc_stop_rx) { - /* mxser_throttle(tty); */ + if (!port->ldisc_stop_rx) mxser_stoprx(tty); - } - /* return; */ } while (gdl--) { - ch = inb(info->base + UART_RX); + ch = inb(port->ioaddr + UART_RX); tty_insert_flip_char(tty, ch, 0); cnt++; - /* - if ((cnt >= HI_WATER) && (info->stop_rx == 0)) { - mxser_stoprx(tty); - info->stop_rx = 1; - break; - } */ } goto end_intr; } - intr_old: - /* above add by Victor Yu. 09-02-2002 */ +intr_old: do { if (max-- < 0) break; - /* - if ((cnt >= HI_WATER) && (info->stop_rx == 0)) { - mxser_stoprx(tty); - info->stop_rx=1; - break; - } - */ - ch = inb(info->base + UART_RX); - /* following add by Victor Yu. 09-02-2002 */ - if (info->IsMoxaMustChipFlag && (*status & UART_LSR_OE) /*&& !(*status&UART_LSR_DR) */ ) - outb(0x23, info->base + UART_FCR); - *status &= info->read_status_mask; - /* above add by Victor Yu. 09-02-2002 */ - if (*status & info->ignore_status_mask) { + ch = inb(port->ioaddr + UART_RX); + if (port->board->chip_flag && (*status & UART_LSR_OE)) + outb(0x23, port->ioaddr + UART_FCR); + *status &= port->read_status_mask; + if (*status & port->ignore_status_mask) { if (++ignored > 100) break; } else { @@ -2095,1038 +2086,652 @@ static void mxser_receive_chars(struct mxser_struct *info, int *status) if (*status & UART_LSR_SPECIAL) { if (*status & UART_LSR_BI) { flag = TTY_BREAK; -/* added by casper 1/11/2000 */ - info->icount.brk++; -/* */ - if (info->flags & ASYNC_SAK) + port->icount.brk++; + + if (port->flags & ASYNC_SAK) do_SAK(tty); } else if (*status & UART_LSR_PE) { flag = TTY_PARITY; -/* added by casper 1/11/2000 */ - info->icount.parity++; -/* */ + port->icount.parity++; } else if (*status & UART_LSR_FE) { flag = TTY_FRAME; -/* added by casper 1/11/2000 */ - info->icount.frame++; -/* */ + port->icount.frame++; } else if (*status & UART_LSR_OE) { flag = TTY_OVERRUN; -/* added by casper 1/11/2000 */ - info->icount.overrun++; -/* */ - } + port->icount.overrun++; + } else + flag = TTY_BREAK; } tty_insert_flip_char(tty, ch, flag); cnt++; if (cnt >= recv_room) { - if (!info->ldisc_stop_rx) { - /* mxser_throttle(tty); */ + if (!port->ldisc_stop_rx) mxser_stoprx(tty); - } break; } } - /* following add by Victor Yu. 09-02-2002 */ - if (info->IsMoxaMustChipFlag) + if (port->board->chip_flag) break; - /* above add by Victor Yu. 09-02-2002 */ - /* mask by Victor Yu. 09-02-2002 - *status = inb(info->base + UART_LSR) & info->read_status_mask; - */ - /* following add by Victor Yu. 09-02-2002 */ - *status = inb(info->base + UART_LSR); - /* above add by Victor Yu. 09-02-2002 */ + *status = inb(port->ioaddr + UART_LSR); } while (*status & UART_LSR_DR); -end_intr: /* add by Victor Yu. 09-02-2002 */ - mxvar_log.rxcnt[info->port] += cnt; - info->mon_data.rxcnt += cnt; - info->mon_data.up_rxcnt += cnt; - spin_unlock_irqrestore(&info->slock, flags); +end_intr: + mxvar_log.rxcnt[port->tty->index] += cnt; + port->mon_data.rxcnt += cnt; + port->mon_data.up_rxcnt += cnt; + /* + * We are called from an interrupt context with &port->slock + * being held. Drop it temporarily in order to prevent + * recursive locking. + */ + spin_unlock(&port->slock); tty_flip_buffer_push(tty); + spin_lock(&port->slock); } -static void mxser_transmit_chars(struct mxser_struct *info) +static void mxser_transmit_chars(struct mxser_port *port) { int count, cnt; - unsigned long flags; - spin_lock_irqsave(&info->slock, flags); - - if (info->x_char) { - outb(info->x_char, info->base + UART_TX); - info->x_char = 0; - mxvar_log.txcnt[info->port]++; - info->mon_data.txcnt++; - info->mon_data.up_txcnt++; - -/* added by casper 1/11/2000 */ - info->icount.tx++; -/* */ - spin_unlock_irqrestore(&info->slock, flags); + if (port->x_char) { + outb(port->x_char, port->ioaddr + UART_TX); + port->x_char = 0; + mxvar_log.txcnt[port->tty->index]++; + port->mon_data.txcnt++; + port->mon_data.up_txcnt++; + port->icount.tx++; return; } - if (info->xmit_buf == 0) { - spin_unlock_irqrestore(&info->slock, flags); + if (port->xmit_buf == NULL) return; - } - if ((info->xmit_cnt <= 0) || info->tty->stopped || - (info->tty->hw_stopped && - (info->type != PORT_16550A) && - (!info->IsMoxaMustChipFlag))) { - info->IER &= ~UART_IER_THRI; - outb(info->IER, info->base + UART_IER); - spin_unlock_irqrestore(&info->slock, flags); + if ((port->xmit_cnt <= 0) || port->tty->stopped || + (port->tty->hw_stopped && + (port->type != PORT_16550A) && + (!port->board->chip_flag))) { + port->IER &= ~UART_IER_THRI; + outb(port->IER, port->ioaddr + UART_IER); return; } - cnt = info->xmit_cnt; - count = info->xmit_fifo_size; + cnt = port->xmit_cnt; + count = port->xmit_fifo_size; do { - outb(info->xmit_buf[info->xmit_tail++], - info->base + UART_TX); - info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE - 1); - if (--info->xmit_cnt <= 0) + outb(port->xmit_buf[port->xmit_tail++], + port->ioaddr + UART_TX); + port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1); + if (--port->xmit_cnt <= 0) break; } while (--count > 0); - mxvar_log.txcnt[info->port] += (cnt - info->xmit_cnt); + mxvar_log.txcnt[port->tty->index] += (cnt - port->xmit_cnt); -/* added by James 03-12-2004. */ - info->mon_data.txcnt += (cnt - info->xmit_cnt); - info->mon_data.up_txcnt += (cnt - info->xmit_cnt); -/* (above) added by James. */ + port->mon_data.txcnt += (cnt - port->xmit_cnt); + port->mon_data.up_txcnt += (cnt - port->xmit_cnt); + port->icount.tx += (cnt - port->xmit_cnt); -/* added by casper 1/11/2000 */ - info->icount.tx += (cnt - info->xmit_cnt); -/* */ + if (port->xmit_cnt < WAKEUP_CHARS) + tty_wakeup(port->tty); - if (info->xmit_cnt < WAKEUP_CHARS) { - set_bit(MXSER_EVENT_TXLOW, &info->event); - schedule_work(&info->tqueue); + if (port->xmit_cnt <= 0) { + port->IER &= ~UART_IER_THRI; + outb(port->IER, port->ioaddr + UART_IER); } - if (info->xmit_cnt <= 0) { - info->IER &= ~UART_IER_THRI; - outb(info->IER, info->base + UART_IER); - } - spin_unlock_irqrestore(&info->slock, flags); } -static void mxser_check_modem_status(struct mxser_struct *info, int status) +/* + * This is the serial driver's generic interrupt routine + */ +static irqreturn_t mxser_interrupt(int irq, void *dev_id) { - /* update input line counters */ - if (status & UART_MSR_TERI) - info->icount.rng++; - if (status & UART_MSR_DDSR) - info->icount.dsr++; - if (status & UART_MSR_DDCD) - info->icount.dcd++; - if (status & UART_MSR_DCTS) - info->icount.cts++; - info->mon_data.modem_status = status; - wake_up_interruptible(&info->delta_msr_wait); - - if ((info->flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) { - if (status & UART_MSR_DCD) - wake_up_interruptible(&info->open_wait); - schedule_work(&info->tqueue); - } - - if (info->flags & ASYNC_CTS_FLOW) { - if (info->tty->hw_stopped) { - if (status & UART_MSR_CTS) { - info->tty->hw_stopped = 0; + int status, iir, i; + struct mxser_board *brd = NULL; + struct mxser_port *port; + int max, irqbits, bits, msr; + unsigned int int_cnt, pass_counter = 0; + int handled = IRQ_NONE; - if ((info->type != PORT_16550A) && - (!info->IsMoxaMustChipFlag)) { - info->IER |= UART_IER_THRI; - outb(info->IER, info->base + UART_IER); - } - set_bit(MXSER_EVENT_TXLOW, &info->event); - schedule_work(&info->tqueue); } - } else { - if (!(status & UART_MSR_CTS)) { - info->tty->hw_stopped = 1; - if ((info->type != PORT_16550A) && - (!info->IsMoxaMustChipFlag)) { - info->IER &= ~UART_IER_THRI; - outb(info->IER, info->base + UART_IER); - } - } + for (i = 0; i < MXSER_BOARDS; i++) + if (dev_id == &mxser_boards[i]) { + brd = dev_id; + break; } - } -} -static int mxser_block_til_ready(struct tty_struct *tty, struct file *filp, struct mxser_struct *info) -{ - DECLARE_WAITQUEUE(wait, current); - int retval; - int do_clocal = 0; - unsigned long flags; - - /* - * If non-blocking mode is set, or the port is not enabled, - * then make the check up front and then exit. - */ - if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) { - info->flags |= ASYNC_NORMAL_ACTIVE; - return 0; - } + if (i == MXSER_BOARDS) + goto irq_stop; + if (brd == NULL) + goto irq_stop; + max = brd->info->nports; + while (pass_counter++ < MXSER_ISR_PASS_LIMIT) { + irqbits = inb(brd->vector) & brd->vector_mask; + if (irqbits == brd->vector_mask) + break; - if (tty->termios->c_cflag & CLOCAL) - do_clocal = 1; + handled = IRQ_HANDLED; + for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) { + if (irqbits == brd->vector_mask) + break; + if (bits & irqbits) + continue; + port = &brd->ports[i]; + + int_cnt = 0; + spin_lock(&port->slock); + do { + iir = inb(port->ioaddr + UART_IIR); + if (iir & UART_IIR_NO_INT) + break; + iir &= MOXA_MUST_IIR_MASK; + if (!port->tty || + (port->flags & ASYNC_CLOSING) || + !(port->flags & + ASYNC_INITIALIZED)) { + status = inb(port->ioaddr + UART_LSR); + outb(0x27, port->ioaddr + UART_FCR); + inb(port->ioaddr + UART_MSR); + break; + } - /* - * Block waiting for the carrier detect and the line to become - * free (i.e., not in use by the callout). While we are in - * this loop, info->count is dropped by one, so that - * mxser_close() knows when to free things. We restore it upon - * exit, either normal or abnormal. - */ - retval = 0; - add_wait_queue(&info->open_wait, &wait); + status = inb(port->ioaddr + UART_LSR); + + if (status & UART_LSR_PE) + port->err_shadow |= NPPI_NOTIFY_PARITY; + if (status & UART_LSR_FE) + port->err_shadow |= NPPI_NOTIFY_FRAMING; + if (status & UART_LSR_OE) + port->err_shadow |= + NPPI_NOTIFY_HW_OVERRUN; + if (status & UART_LSR_BI) + port->err_shadow |= NPPI_NOTIFY_BREAK; + + if (port->board->chip_flag) { + if (iir == MOXA_MUST_IIR_GDA || + iir == MOXA_MUST_IIR_RDA || + iir == MOXA_MUST_IIR_RTO || + iir == MOXA_MUST_IIR_LSR) + mxser_receive_chars(port, + &status); - spin_lock_irqsave(&info->slock, flags); - if (!tty_hung_up_p(filp)) - info->count--; - spin_unlock_irqrestore(&info->slock, flags); - info->blocked_open++; - while (1) { - spin_lock_irqsave(&info->slock, flags); - outb(inb(info->base + UART_MCR) | - UART_MCR_DTR | UART_MCR_RTS, info->base + UART_MCR); - spin_unlock_irqrestore(&info->slock, flags); - set_current_state(TASK_INTERRUPTIBLE); - if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)) { - if (info->flags & ASYNC_HUP_NOTIFY) - retval = -EAGAIN; - else - retval = -ERESTARTSYS; - break; - } - if (!(info->flags & ASYNC_CLOSING) && - (do_clocal || - (inb(info->base + UART_MSR) & UART_MSR_DCD))) - break; - if (signal_pending(current)) { - retval = -ERESTARTSYS; - break; + } else { + status &= port->read_status_mask; + if (status & UART_LSR_DR) + mxser_receive_chars(port, + &status); + } + msr = inb(port->ioaddr + UART_MSR); + if (msr & UART_MSR_ANY_DELTA) + mxser_check_modem_status(port, msr); + + if (port->board->chip_flag) { + if (iir == 0x02 && (status & + UART_LSR_THRE)) + mxser_transmit_chars(port); + } else { + if (status & UART_LSR_THRE) + mxser_transmit_chars(port); + } + } while (int_cnt++ < MXSER_ISR_PASS_LIMIT); + spin_unlock(&port->slock); } - schedule(); } - set_current_state(TASK_RUNNING); - remove_wait_queue(&info->open_wait, &wait); - if (!tty_hung_up_p(filp)) - info->count++; - info->blocked_open--; - if (retval) - return retval; - info->flags |= ASYNC_NORMAL_ACTIVE; - return 0; -} -static int mxser_startup(struct mxser_struct *info) -{ - unsigned long page; - unsigned long flags; - - page = __get_free_page(GFP_KERNEL); - if (!page) - return -ENOMEM; - - spin_lock_irqsave(&info->slock, flags); - - if (info->flags & ASYNC_INITIALIZED) { - free_page(page); - spin_unlock_irqrestore(&info->slock, flags); - return 0; - } +irq_stop: + return handled; +} - if (!info->base || !info->type) { - if (info->tty) - set_bit(TTY_IO_ERROR, &info->tty->flags); - free_page(page); - spin_unlock_irqrestore(&info->slock, flags); - return 0; - } - if (info->xmit_buf) - free_page(page); - else - info->xmit_buf = (unsigned char *) page; +static const struct tty_operations mxser_ops = { + .open = mxser_open, + .close = mxser_close, + .write = mxser_write, + .put_char = mxser_put_char, + .flush_chars = mxser_flush_chars, + .write_room = mxser_write_room, + .chars_in_buffer = mxser_chars_in_buffer, + .flush_buffer = mxser_flush_buffer, + .ioctl = mxser_ioctl, + .throttle = mxser_throttle, + .unthrottle = mxser_unthrottle, + .set_termios = mxser_set_termios, + .stop = mxser_stop, + .start = mxser_start, + .hangup = mxser_hangup, + .break_ctl = mxser_rs_break, + .wait_until_sent = mxser_wait_until_sent, + .tiocmget = mxser_tiocmget, + .tiocmset = mxser_tiocmset, +}; - /* - * Clear the FIFO buffers and disable them - * (they will be reenabled in mxser_change_speed()) - */ - if (info->IsMoxaMustChipFlag) - outb((UART_FCR_CLEAR_RCVR | - UART_FCR_CLEAR_XMIT | - MOXA_MUST_FCR_GDA_MODE_ENABLE), info->base + UART_FCR); - else - outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT), - info->base + UART_FCR); +/* + * The MOXA Smartio/Industio serial driver boot-time initialization code! + */ - /* - * At this point there's no way the LSR could still be 0xFF; - * if it is, then bail out, because there's likely no UART - * here. - */ - if (inb(info->base + UART_LSR) == 0xff) { - spin_unlock_irqrestore(&info->slock, flags); - if (capable(CAP_SYS_ADMIN)) { - if (info->tty) - set_bit(TTY_IO_ERROR, &info->tty->flags); - return 0; - } else - return -ENODEV; +static void mxser_release_res(struct mxser_board *brd, struct pci_dev *pdev, + unsigned int irq) +{ + if (irq) + free_irq(brd->irq, brd); + if (pdev != NULL) { /* PCI */ +#ifdef CONFIG_PCI + pci_release_region(pdev, 2); + pci_release_region(pdev, 3); +#endif + } else { + release_region(brd->ports[0].ioaddr, 8 * brd->info->nports); + release_region(brd->vector, 1); } - - /* - * Clear the interrupt registers. - */ - (void) inb(info->base + UART_LSR); - (void) inb(info->base + UART_RX); - (void) inb(info->base + UART_IIR); - (void) inb(info->base + UART_MSR); - - /* - * Now, initialize the UART - */ - outb(UART_LCR_WLEN8, info->base + UART_LCR); /* reset DLAB */ - info->MCR = UART_MCR_DTR | UART_MCR_RTS; - outb(info->MCR, info->base + UART_MCR); - - /* - * Finally, enable interrupts - */ - info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; - /* info->IER = UART_IER_RLSI | UART_IER_RDI; */ - - /* following add by Victor Yu. 08-30-2002 */ - if (info->IsMoxaMustChipFlag) - info->IER |= MOXA_MUST_IER_EGDAI; - /* above add by Victor Yu. 08-30-2002 */ - outb(info->IER, info->base + UART_IER); /* enable interrupts */ - - /* - * And clear the interrupt registers again for luck. - */ - (void) inb(info->base + UART_LSR); - (void) inb(info->base + UART_RX); - (void) inb(info->base + UART_IIR); - (void) inb(info->base + UART_MSR); - - if (info->tty) - clear_bit(TTY_IO_ERROR, &info->tty->flags); - info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; - - /* - * and set the speed of the serial port - */ - spin_unlock_irqrestore(&info->slock, flags); - mxser_change_speed(info, NULL); - - info->flags |= ASYNC_INITIALIZED; - return 0; } -/* - * This routine will shutdown a serial port; interrupts maybe disabled, and - * DTR is dropped if the hangup on close termio flag is on. - */ -static void mxser_shutdown(struct mxser_struct *info) +static int __devinit mxser_initbrd(struct mxser_board *brd, + struct pci_dev *pdev) { - unsigned long flags; - - if (!(info->flags & ASYNC_INITIALIZED)) - return; - - spin_lock_irqsave(&info->slock, flags); - - /* - * clear delta_msr_wait queue to avoid mem leaks: we may free the irq - * here so the queue might never be waken up - */ - wake_up_interruptible(&info->delta_msr_wait); - - /* - * Free the IRQ, if necessary - */ - if (info->xmit_buf) { - free_page((unsigned long) info->xmit_buf); - info->xmit_buf = NULL; - } + struct mxser_port *info; + unsigned int i; + int retval; - info->IER = 0; - outb(0x00, info->base + UART_IER); + printk(KERN_INFO "max. baud rate = %d bps.\n", brd->ports[0].max_baud); - if (!info->tty || (info->tty->termios->c_cflag & HUPCL)) - info->MCR &= ~(UART_MCR_DTR | UART_MCR_RTS); - outb(info->MCR, info->base + UART_MCR); + for (i = 0; i < brd->info->nports; i++) { + info = &brd->ports[i]; + info->board = brd; + info->stop_rx = 0; + info->ldisc_stop_rx = 0; - /* clear Rx/Tx FIFO's */ - /* following add by Victor Yu. 08-30-2002 */ - if (info->IsMoxaMustChipFlag) - outb((UART_FCR_CLEAR_RCVR | - UART_FCR_CLEAR_XMIT | - MOXA_MUST_FCR_GDA_MODE_ENABLE), info->base + UART_FCR); - else - /* above add by Victor Yu. 08-30-2002 */ - outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT), - info->base + UART_FCR); + /* Enhance mode enabled here */ + if (brd->chip_flag != MOXA_OTHER_UART) + ENABLE_MOXA_MUST_ENCHANCE_MODE(info->ioaddr); - /* read data port to reset things */ - (void) inb(info->base + UART_RX); + info->flags = ASYNC_SHARE_IRQ; + info->type = brd->uart_type; - if (info->tty) - set_bit(TTY_IO_ERROR, &info->tty->flags); + process_txrx_fifo(info); - info->flags &= ~ASYNC_INITIALIZED; + info->custom_divisor = info->baud_base * 16; + info->close_delay = 5 * HZ / 10; + info->closing_wait = 30 * HZ; + info->normal_termios = mxvar_sdriver->init_termios; + init_waitqueue_head(&info->open_wait); + init_waitqueue_head(&info->delta_msr_wait); + memset(&info->mon_data, 0, sizeof(struct mxser_mon)); + info->err_shadow = 0; + spin_lock_init(&info->slock); - /* following add by Victor Yu. 09-23-2002 */ - if (info->IsMoxaMustChipFlag) - SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->base); - /* above add by Victor Yu. 09-23-2002 */ + /* before set INT ISR, disable all int */ + outb(inb(info->ioaddr + UART_IER) & 0xf0, + info->ioaddr + UART_IER); + } - spin_unlock_irqrestore(&info->slock, flags); + retval = request_irq(brd->irq, mxser_interrupt, IRQF_SHARED, "mxser", + brd); + if (retval) { + printk(KERN_ERR "Board %s: Request irq failed, IRQ (%d) may " + "conflict with another device.\n", + brd->info->name, brd->irq); + /* We hold resources, we need to release them. */ + mxser_release_res(brd, pdev, 0); + } + return retval; } -/* - * This routine is called to set the UART divisor registers to match - * the specified baud rate for a serial port. - */ -static int mxser_change_speed(struct mxser_struct *info, struct ktermios *old_termios) +static int __init mxser_get_ISA_conf(int cap, struct mxser_board *brd) { - unsigned cflag, cval, fcr; - int ret = 0; - unsigned char status; - long baud; - unsigned long flags; - - if (!info->tty || !info->tty->termios) - return ret; - cflag = info->tty->termios->c_cflag; - if (!(info->base)) - return ret; + int id, i, bits; + unsigned short regs[16], irq; + unsigned char scratch, scratch2; -#ifndef B921600 -#define B921600 (B460800 +1) -#endif - if (mxser_set_baud_method[info->port] == 0) { - baud = tty_get_baud_rate(info->tty); - mxser_set_baud(info, baud); - } + brd->chip_flag = MOXA_OTHER_UART; - /* byte size and parity */ - switch (cflag & CSIZE) { - case CS5: - cval = 0x00; + id = mxser_read_register(cap, regs); + switch (id) { + case C168_ASIC_ID: + brd->info = &mxser_cards[0]; break; - case CS6: - cval = 0x01; + case C104_ASIC_ID: + brd->info = &mxser_cards[1]; break; - case CS7: - cval = 0x02; + case CI104J_ASIC_ID: + brd->info = &mxser_cards[2]; break; - case CS8: - cval = 0x03; + case C102_ASIC_ID: + brd->info = &mxser_cards[5]; + break; + case CI132_ASIC_ID: + brd->info = &mxser_cards[6]; + break; + case CI134_ASIC_ID: + brd->info = &mxser_cards[7]; break; default: - cval = 0x00; - break; /* too keep GCC shut... */ + return 0; } - if (cflag & CSTOPB) - cval |= 0x04; - if (cflag & PARENB) - cval |= UART_LCR_PARITY; - if (!(cflag & PARODD)) - cval |= UART_LCR_EPAR; - if (cflag & CMSPAR) - cval |= UART_LCR_SPAR; - if ((info->type == PORT_8250) || (info->type == PORT_16450)) { - if (info->IsMoxaMustChipFlag) { - fcr = UART_FCR_ENABLE_FIFO; - fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; - SET_MOXA_MUST_FIFO_VALUE(info); - } else - fcr = 0; - } else { - fcr = UART_FCR_ENABLE_FIFO; - /* following add by Victor Yu. 08-30-2002 */ - if (info->IsMoxaMustChipFlag) { - fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; - SET_MOXA_MUST_FIFO_VALUE(info); - } else { - /* above add by Victor Yu. 08-30-2002 */ - switch (info->rx_trigger) { - case 1: - fcr |= UART_FCR_TRIGGER_1; - break; - case 4: - fcr |= UART_FCR_TRIGGER_4; - break; - case 8: - fcr |= UART_FCR_TRIGGER_8; - break; - default: - fcr |= UART_FCR_TRIGGER_14; - break; - } - } + irq = 0; + /* some ISA cards have 2 ports, but we want to see them as 4-port (why?) + Flag-hack checks if configuration should be read as 2-port here. */ + if (brd->info->nports == 2 || (brd->info->flags & MXSER_HAS2)) { + irq = regs[9] & 0xF000; + irq = irq | (irq >> 4); + if (irq != (regs[9] & 0xFF00)) + return MXSER_ERR_IRQ_CONFLIT; + } else if (brd->info->nports == 4) { + irq = regs[9] & 0xF000; + irq = irq | (irq >> 4); + irq = irq | (irq >> 8); + if (irq != regs[9]) + return MXSER_ERR_IRQ_CONFLIT; + } else if (brd->info->nports == 8) { + irq = regs[9] & 0xF000; + irq = irq | (irq >> 4); + irq = irq | (irq >> 8); + if ((irq != regs[9]) || (irq != regs[10])) + return MXSER_ERR_IRQ_CONFLIT; } - /* CTS flow control flag and modem status interrupts */ - info->IER &= ~UART_IER_MSI; - info->MCR &= ~UART_MCR_AFE; - if (cflag & CRTSCTS) { - info->flags |= ASYNC_CTS_FLOW; - info->IER |= UART_IER_MSI; - if ((info->type == PORT_16550A) || (info->IsMoxaMustChipFlag)) { - info->MCR |= UART_MCR_AFE; + if (!irq) + return MXSER_ERR_IRQ; + brd->irq = ((int)(irq & 0xF000) >> 12); + for (i = 0; i < 8; i++) + brd->ports[i].ioaddr = (int) regs[i + 1] & 0xFFF8; + if ((regs[12] & 0x80) == 0) + return MXSER_ERR_VECTOR; + brd->vector = (int)regs[11]; /* interrupt vector */ + if (id == 1) + brd->vector_mask = 0x00FF; + else + brd->vector_mask = 0x000F; + for (i = 7, bits = 0x0100; i >= 0; i--, bits <<= 1) { + if (regs[12] & bits) { + brd->ports[i].baud_base = 921600; + brd->ports[i].max_baud = 921600; } else { - status = inb(info->base + UART_MSR); - if (info->tty->hw_stopped) { - if (status & UART_MSR_CTS) { - info->tty->hw_stopped = 0; - if ((info->type != PORT_16550A) && - (!info->IsMoxaMustChipFlag)) { - info->IER |= UART_IER_THRI; - outb(info->IER, info->base + UART_IER); - } - set_bit(MXSER_EVENT_TXLOW, &info->event); - schedule_work(&info->tqueue); } - } else { - if (!(status & UART_MSR_CTS)) { - info->tty->hw_stopped = 1; - if ((info->type != PORT_16550A) && - (!info->IsMoxaMustChipFlag)) { - info->IER &= ~UART_IER_THRI; - outb(info->IER, info->base + UART_IER); - } - } - } + brd->ports[i].baud_base = 115200; + brd->ports[i].max_baud = 115200; } - } else { - info->flags &= ~ASYNC_CTS_FLOW; - } - outb(info->MCR, info->base + UART_MCR); - if (cflag & CLOCAL) { - info->flags &= ~ASYNC_CHECK_CD; - } else { - info->flags |= ASYNC_CHECK_CD; - info->IER |= UART_IER_MSI; } - outb(info->IER, info->base + UART_IER); - - /* - * Set up parity check flag - */ - info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; - if (I_INPCK(info->tty)) - info->read_status_mask |= UART_LSR_FE | UART_LSR_PE; - if (I_BRKINT(info->tty) || I_PARMRK(info->tty)) - info->read_status_mask |= UART_LSR_BI; - - info->ignore_status_mask = 0; + scratch2 = inb(cap + UART_LCR) & (~UART_LCR_DLAB); + outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR); + outb(0, cap + UART_EFR); /* EFR is the same as FCR */ + outb(scratch2, cap + UART_LCR); + outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR); + scratch = inb(cap + UART_IIR); - if (I_IGNBRK(info->tty)) { - info->ignore_status_mask |= UART_LSR_BI; - info->read_status_mask |= UART_LSR_BI; - /* - * If we're ignore parity and break indicators, ignore - * overruns too. (For real raw support). - */ - if (I_IGNPAR(info->tty)) { - info->ignore_status_mask |= - UART_LSR_OE | - UART_LSR_PE | - UART_LSR_FE; - info->read_status_mask |= - UART_LSR_OE | - UART_LSR_PE | - UART_LSR_FE; - } - } - /* following add by Victor Yu. 09-02-2002 */ - if (info->IsMoxaMustChipFlag) { - spin_lock_irqsave(&info->slock, flags); - SET_MOXA_MUST_XON1_VALUE(info->base, START_CHAR(info->tty)); - SET_MOXA_MUST_XOFF1_VALUE(info->base, STOP_CHAR(info->tty)); - if (I_IXON(info->tty)) { - ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->base); - } else { - DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->base); - } - if (I_IXOFF(info->tty)) { - ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->base); - } else { - DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->base); - } - /* - if ( I_IXANY(info->tty) ) { - info->MCR |= MOXA_MUST_MCR_XON_ANY; - ENABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(info->base); - } else { - info->MCR &= ~MOXA_MUST_MCR_XON_ANY; - DISABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(info->base); - } - */ - spin_unlock_irqrestore(&info->slock, flags); + if (scratch & 0xC0) + brd->uart_type = PORT_16550A; + else + brd->uart_type = PORT_16450; + if (!request_region(brd->ports[0].ioaddr, 8 * brd->info->nports, + "mxser(IO)")) + return MXSER_ERR_IOADDR; + if (!request_region(brd->vector, 1, "mxser(vector)")) { + release_region(brd->ports[0].ioaddr, 8 * brd->info->nports); + return MXSER_ERR_VECTOR; } - /* above add by Victor Yu. 09-02-2002 */ - - - outb(fcr, info->base + UART_FCR); /* set fcr */ - outb(cval, info->base + UART_LCR); - - return ret; + return brd->info->nports; } - -static int mxser_set_baud(struct mxser_struct *info, long newspd) +static int __devinit mxser_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) { - int quot = 0; - unsigned char cval; - int ret = 0; - unsigned long flags; - - if (!info->tty || !info->tty->termios) - return ret; - - if (!(info->base)) - return ret; +#ifdef CONFIG_PCI + struct mxser_board *brd; + unsigned int i, j; + unsigned long ioaddress; + int retval = -EINVAL; - if (newspd > info->MaxCanSetBaudRate) - return 0; + for (i = 0; i < MXSER_BOARDS; i++) + if (mxser_boards[i].info == NULL) + break; - info->realbaud = newspd; - if (newspd == 134) { - quot = (2 * info->baud_base / 269); - } else if (newspd) { - quot = info->baud_base / newspd; - if (quot == 0) - quot = 1; - } else { - quot = 0; + if (i >= MXSER_BOARDS) { + printk(KERN_ERR "Too many Smartio/Industio family boards found " + "(maximum %d), board not configured\n", MXSER_BOARDS); + goto err; } - info->timeout = ((info->xmit_fifo_size * HZ * 10 * quot) / info->baud_base); - info->timeout += HZ / 50; /* Add .02 seconds of slop */ + brd = &mxser_boards[i]; + brd->idx = i * MXSER_PORTS_PER_BOARD; + printk(KERN_INFO "Found MOXA %s board (BusNo=%d, DevNo=%d)\n", + mxser_cards[ent->driver_data].name, + pdev->bus->number, PCI_SLOT(pdev->devfn)); - if (quot) { - spin_lock_irqsave(&info->slock, flags); - info->MCR |= UART_MCR_DTR; - outb(info->MCR, info->base + UART_MCR); - spin_unlock_irqrestore(&info->slock, flags); - } else { - spin_lock_irqsave(&info->slock, flags); - info->MCR &= ~UART_MCR_DTR; - outb(info->MCR, info->base + UART_MCR); - spin_unlock_irqrestore(&info->slock, flags); - return ret; + retval = pci_enable_device(pdev); + if (retval) { + printk(KERN_ERR "Moxa SmartI/O PCI enable fail !\n"); + goto err; } - cval = inb(info->base + UART_LCR); - - outb(cval | UART_LCR_DLAB, info->base + UART_LCR); /* set DLAB */ - - outb(quot & 0xff, info->base + UART_DLL); /* LS of divisor */ - outb(quot >> 8, info->base + UART_DLM); /* MS of divisor */ - outb(cval, info->base + UART_LCR); /* reset DLAB */ - + /* io address */ + ioaddress = pci_resource_start(pdev, 2); + retval = pci_request_region(pdev, 2, "mxser(IO)"); + if (retval) + goto err; - return ret; -} + brd->info = &mxser_cards[ent->driver_data]; + for (i = 0; i < brd->info->nports; i++) + brd->ports[i].ioaddr = ioaddress + 8 * i; -/* - * ------------------------------------------------------------ - * friends of mxser_ioctl() - * ------------------------------------------------------------ - */ -static int mxser_get_serial_info(struct mxser_struct *info, struct serial_struct __user *retinfo) -{ - struct serial_struct tmp; + /* vector */ + ioaddress = pci_resource_start(pdev, 3); + retval = pci_request_region(pdev, 3, "mxser(vector)"); + if (retval) + goto err_relio; + brd->vector = ioaddress; - if (!retinfo) - return -EFAULT; - memset(&tmp, 0, sizeof(tmp)); - tmp.type = info->type; - tmp.line = info->port; - tmp.port = info->base; - tmp.irq = info->irq; - tmp.flags = info->flags; - tmp.baud_base = info->baud_base; - tmp.close_delay = info->close_delay; - tmp.closing_wait = info->closing_wait; - tmp.custom_divisor = info->custom_divisor; - tmp.hub6 = 0; - if (copy_to_user(retinfo, &tmp, sizeof(*retinfo))) - return -EFAULT; - return 0; -} + /* irq */ + brd->irq = pdev->irq; -static int mxser_set_serial_info(struct mxser_struct *info, struct serial_struct __user *new_info) -{ - struct serial_struct new_serial; - unsigned int flags; - int retval = 0; + brd->chip_flag = CheckIsMoxaMust(brd->ports[0].ioaddr); + brd->uart_type = PORT_16550A; + brd->vector_mask = 0; - if (!new_info || !info->base) - return -EFAULT; - if (copy_from_user(&new_serial, new_info, sizeof(new_serial))) - return -EFAULT; + for (i = 0; i < brd->info->nports; i++) { + for (j = 0; j < UART_INFO_NUM; j++) { + if (Gpci_uart_info[j].type == brd->chip_flag) { + brd->ports[i].max_baud = + Gpci_uart_info[j].max_baud; - if ((new_serial.irq != info->irq) || - (new_serial.port != info->base) || - (new_serial.custom_divisor != info->custom_divisor) || - (new_serial.baud_base != info->baud_base)) - return -EPERM; + /* exception....CP-102 */ + if (brd->info->flags & MXSER_HIGHBAUD) + brd->ports[i].max_baud = 921600; + break; + } + } + } - flags = info->flags & ASYNC_SPD_MASK; + if (brd->chip_flag == MOXA_MUST_MU860_HWID) { + for (i = 0; i < brd->info->nports; i++) { + if (i < 4) + brd->ports[i].opmode_ioaddr = ioaddress + 4; + else + brd->ports[i].opmode_ioaddr = ioaddress + 0x0c; + } + outb(0, ioaddress + 4); /* default set to RS232 mode */ + outb(0, ioaddress + 0x0c); /* default set to RS232 mode */ + } - if (!capable(CAP_SYS_ADMIN)) { - if ((new_serial.baud_base != info->baud_base) || - (new_serial.close_delay != info->close_delay) || - ((new_serial.flags & ~ASYNC_USR_MASK) != (info->flags & ~ASYNC_USR_MASK))) - return -EPERM; - info->flags = ((info->flags & ~ASYNC_USR_MASK) | - (new_serial.flags & ASYNC_USR_MASK)); - } else { - /* - * OK, past this point, all the error checking has been done. - * At this point, we start making changes..... - */ - info->flags = ((info->flags & ~ASYNC_FLAGS) | - (new_serial.flags & ASYNC_FLAGS)); - info->close_delay = new_serial.close_delay * HZ / 100; - info->closing_wait = new_serial.closing_wait * HZ / 100; - info->tty->low_latency = - (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; - info->tty->low_latency = 0; /* (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; */ + for (i = 0; i < brd->info->nports; i++) { + brd->vector_mask |= (1 << i); + brd->ports[i].baud_base = 921600; } - /* added by casper, 3/17/2000, for mouse */ - info->type = new_serial.type; + /* mxser_initbrd will hook ISR. */ + retval = mxser_initbrd(brd, pdev); + if (retval) + goto err_null; - process_txrx_fifo(info); + for (i = 0; i < brd->info->nports; i++) + tty_register_device(mxvar_sdriver, brd->idx + i, &pdev->dev); - if (info->flags & ASYNC_INITIALIZED) { - if (flags != (info->flags & ASYNC_SPD_MASK)) { - mxser_change_speed(info, NULL); - } - } else { - retval = mxser_startup(info); - } + pci_set_drvdata(pdev, brd); + + return 0; +err_relio: + pci_release_region(pdev, 2); +err_null: + brd->info = NULL; +err: return retval; +#else + return -ENODEV; +#endif } -/* - * mxser_get_lsr_info - get line status register info - * - * Purpose: Let user call ioctl() to get info when the UART physically - * is emptied. On bus types like RS485, the transmitter must - * release the bus after transmitting. This must be done when - * the transmit shift register is empty, not be done when the - * transmit holding register is empty. This functionality - * allows an RS485 driver to be written in user space. - */ -static int mxser_get_lsr_info(struct mxser_struct *info, unsigned int __user *value) +static void __devexit mxser_remove(struct pci_dev *pdev) { - unsigned char status; - unsigned int result; - unsigned long flags; + struct mxser_board *brd = pci_get_drvdata(pdev); + unsigned int i; - spin_lock_irqsave(&info->slock, flags); - status = inb(info->base + UART_LSR); - spin_unlock_irqrestore(&info->slock, flags); - result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0); - return put_user(result, value); -} + for (i = 0; i < brd->info->nports; i++) + tty_unregister_device(mxvar_sdriver, brd->idx + i); -/* - * This routine sends a break character out the serial port. - */ -static void mxser_send_break(struct mxser_struct *info, int duration) -{ - unsigned long flags; - - if (!info->base) - return; - set_current_state(TASK_INTERRUPTIBLE); - spin_lock_irqsave(&info->slock, flags); - outb(inb(info->base + UART_LCR) | UART_LCR_SBC, - info->base + UART_LCR); - spin_unlock_irqrestore(&info->slock, flags); - schedule_timeout(duration); - spin_lock_irqsave(&info->slock, flags); - outb(inb(info->base + UART_LCR) & ~UART_LCR_SBC, - info->base + UART_LCR); - spin_unlock_irqrestore(&info->slock, flags); + mxser_release_res(brd, pdev, 1); + brd->info = NULL; } -static int mxser_tiocmget(struct tty_struct *tty, struct file *file) -{ - struct mxser_struct *info = tty->driver_data; - unsigned char control, status; - unsigned long flags; +static struct pci_driver mxser_driver = { + .name = "mxser", + .id_table = mxser_pcibrds, + .probe = mxser_probe, + .remove = __devexit_p(mxser_remove) +}; +static int __init mxser_module_init(void) +{ + struct mxser_board *brd; + unsigned long cap; + unsigned int i, m, isaloop; + int retval, b; - if (tty->index == MXSER_PORTS) - return -ENOIOCTLCMD; - if (tty->flags & (1 << TTY_IO_ERROR)) - return -EIO; + pr_debug("Loading module mxser ...\n"); - control = info->MCR; + mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1); + if (!mxvar_sdriver) + return -ENOMEM; - spin_lock_irqsave(&info->slock, flags); - status = inb(info->base + UART_MSR); - if (status & UART_MSR_ANY_DELTA) - mxser_check_modem_status(info, status); - spin_unlock_irqrestore(&info->slock, flags); - return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) | - ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) | - ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) | - ((status & UART_MSR_RI) ? TIOCM_RNG : 0) | - ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) | - ((status & UART_MSR_CTS) ? TIOCM_CTS : 0); -} + printk(KERN_INFO "MOXA Smartio/Industio family driver version %s\n", + MXSER_VERSION); -static int mxser_tiocmset(struct tty_struct *tty, struct file *file, unsigned int set, unsigned int clear) -{ - struct mxser_struct *info = tty->driver_data; - unsigned long flags; + /* Initialize the tty_driver structure */ + mxvar_sdriver->owner = THIS_MODULE; + mxvar_sdriver->magic = TTY_DRIVER_MAGIC; + mxvar_sdriver->name = "ttyMI"; + mxvar_sdriver->major = ttymajor; + mxvar_sdriver->minor_start = 0; + mxvar_sdriver->num = MXSER_PORTS + 1; + mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL; + mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL; + mxvar_sdriver->init_termios = tty_std_termios; + mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL; + mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW|TTY_DRIVER_DYNAMIC_DEV; + tty_set_operations(mxvar_sdriver, &mxser_ops); + retval = tty_register_driver(mxvar_sdriver); + if (retval) { + printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family " + "tty driver !\n"); + goto err_put; + } - if (tty->index == MXSER_PORTS) - return -ENOIOCTLCMD; - if (tty->flags & (1 << TTY_IO_ERROR)) - return -EIO; + mxvar_diagflag = 0; - spin_lock_irqsave(&info->slock, flags); + m = 0; + /* Start finding ISA boards here */ + for (isaloop = 0; isaloop < 2; isaloop++) + for (b = 0; b < MXSER_BOARDS && m < MXSER_BOARDS; b++) { + if (!isaloop) + cap = mxserBoardCAP[b]; /* predefined */ + else + cap = ioaddr[b]; /* module param */ - if (set & TIOCM_RTS) - info->MCR |= UART_MCR_RTS; - if (set & TIOCM_DTR) - info->MCR |= UART_MCR_DTR; + if (!cap) + continue; - if (clear & TIOCM_RTS) - info->MCR &= ~UART_MCR_RTS; - if (clear & TIOCM_DTR) - info->MCR &= ~UART_MCR_DTR; + brd = &mxser_boards[m]; + retval = mxser_get_ISA_conf(cap, brd); - outb(info->MCR, info->base + UART_MCR); - spin_unlock_irqrestore(&info->slock, flags); - return 0; -} + if (retval != 0) + printk(KERN_INFO "Found MOXA %s board " + "(CAP=0x%x)\n", + brd->info->name, ioaddr[b]); + if (retval <= 0) { + if (retval == MXSER_ERR_IRQ) + printk(KERN_ERR "Invalid interrupt " + "number, board not " + "configured\n"); + else if (retval == MXSER_ERR_IRQ_CONFLIT) + printk(KERN_ERR "Invalid interrupt " + "number, board not " + "configured\n"); + else if (retval == MXSER_ERR_VECTOR) + printk(KERN_ERR "Invalid interrupt " + "vector, board not " + "configured\n"); + else if (retval == MXSER_ERR_IOADDR) + printk(KERN_ERR "Invalid I/O address, " + "board not configured\n"); -static int mxser_read_register(int, unsigned short *); -static int mxser_program_mode(int); -static void mxser_normal_mode(int); + brd->info = NULL; + continue; + } -static int mxser_get_ISA_conf(int cap, struct mxser_hwconf *hwconf) -{ - int id, i, bits; - unsigned short regs[16], irq; - unsigned char scratch, scratch2; + /* mxser_initbrd will hook ISR. */ + if (mxser_initbrd(brd, NULL) < 0) { + brd->info = NULL; + continue; + } - hwconf->IsMoxaMustChipFlag = MOXA_OTHER_UART; + brd->idx = m * MXSER_PORTS_PER_BOARD; + for (i = 0; i < brd->info->nports; i++) + tty_register_device(mxvar_sdriver, brd->idx + i, + NULL); - id = mxser_read_register(cap, regs); - if (id == C168_ASIC_ID) { - hwconf->board_type = MXSER_BOARD_C168_ISA; - hwconf->ports = 8; - } else if (id == C104_ASIC_ID) { - hwconf->board_type = MXSER_BOARD_C104_ISA; - hwconf->ports = 4; - } else if (id == C102_ASIC_ID) { - hwconf->board_type = MXSER_BOARD_C102_ISA; - hwconf->ports = 2; - } else if (id == CI132_ASIC_ID) { - hwconf->board_type = MXSER_BOARD_CI132; - hwconf->ports = 2; - } else if (id == CI134_ASIC_ID) { - hwconf->board_type = MXSER_BOARD_CI134; - hwconf->ports = 4; - } else if (id == CI104J_ASIC_ID) { - hwconf->board_type = MXSER_BOARD_CI104J; - hwconf->ports = 4; - } else - return 0; + m++; + } - irq = 0; - if (hwconf->ports == 2) { - irq = regs[9] & 0xF000; - irq = irq | (irq >> 4); - if (irq != (regs[9] & 0xFF00)) - return MXSER_ERR_IRQ_CONFLIT; - } else if (hwconf->ports == 4) { - irq = regs[9] & 0xF000; - irq = irq | (irq >> 4); - irq = irq | (irq >> 8); - if (irq != regs[9]) - return MXSER_ERR_IRQ_CONFLIT; - } else if (hwconf->ports == 8) { - irq = regs[9] & 0xF000; - irq = irq | (irq >> 4); - irq = irq | (irq >> 8); - if ((irq != regs[9]) || (irq != regs[10])) - return MXSER_ERR_IRQ_CONFLIT; + retval = pci_register_driver(&mxser_driver); + if (retval) { + printk(KERN_ERR "Can't register pci driver\n"); + if (!m) { + retval = -ENODEV; + goto err_unr; + } /* else: we have some ISA cards under control */ } - if (!irq) - return MXSER_ERR_IRQ; - hwconf->irq = ((int)(irq & 0xF000) >> 12); - for (i = 0; i < 8; i++) - hwconf->ioaddr[i] = (int) regs[i + 1] & 0xFFF8; - if ((regs[12] & 0x80) == 0) - return MXSER_ERR_VECTOR; - hwconf->vector = (int)regs[11]; /* interrupt vector */ - if (id == 1) - hwconf->vector_mask = 0x00FF; - else - hwconf->vector_mask = 0x000F; - for (i = 7, bits = 0x0100; i >= 0; i--, bits <<= 1) { - if (regs[12] & bits) { - hwconf->baud_base[i] = 921600; - hwconf->MaxCanSetBaudRate[i] = 921600; /* add by Victor Yu. 09-04-2002 */ - } else { - hwconf->baud_base[i] = 115200; - hwconf->MaxCanSetBaudRate[i] = 115200; /* add by Victor Yu. 09-04-2002 */ - } - } - scratch2 = inb(cap + UART_LCR) & (~UART_LCR_DLAB); - outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR); - outb(0, cap + UART_EFR); /* EFR is the same as FCR */ - outb(scratch2, cap + UART_LCR); - outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR); - scratch = inb(cap + UART_IIR); + pr_debug("Done.\n"); - if (scratch & 0xC0) - hwconf->uart_type = PORT_16550A; - else - hwconf->uart_type = PORT_16450; - if (id == 1) - hwconf->ports = 8; - else - hwconf->ports = 4; - request_region(hwconf->ioaddr[0], 8 * hwconf->ports, "mxser(IO)"); - request_region(hwconf->vector, 1, "mxser(vector)"); - return hwconf->ports; + return 0; +err_unr: + tty_unregister_driver(mxvar_sdriver); +err_put: + put_tty_driver(mxvar_sdriver); + return retval; } -#define CHIP_SK 0x01 /* Serial Data Clock in Eprom */ -#define CHIP_DO 0x02 /* Serial Data Output in Eprom */ -#define CHIP_CS 0x04 /* Serial Chip Select in Eprom */ -#define CHIP_DI 0x08 /* Serial Data Input in Eprom */ -#define EN_CCMD 0x000 /* Chip's command register */ -#define EN0_RSARLO 0x008 /* Remote start address reg 0 */ -#define EN0_RSARHI 0x009 /* Remote start address reg 1 */ -#define EN0_RCNTLO 0x00A /* Remote byte count reg WR */ -#define EN0_RCNTHI 0x00B /* Remote byte count reg WR */ -#define EN0_DCFG 0x00E /* Data configuration reg WR */ -#define EN0_PORT 0x010 /* Rcv missed frame error counter RD */ -#define ENC_PAGE0 0x000 /* Select page 0 of chip registers */ -#define ENC_PAGE3 0x0C0 /* Select page 3 of chip registers */ -static int mxser_read_register(int port, unsigned short *regs) +static void __exit mxser_module_exit(void) { - int i, k, value, id; - unsigned int j; - - id = mxser_program_mode(port); - if (id < 0) - return id; - for (i = 0; i < 14; i++) { - k = (i & 0x3F) | 0x180; - for (j = 0x100; j > 0; j >>= 1) { - outb(CHIP_CS, port); - if (k & j) { - outb(CHIP_CS | CHIP_DO, port); - outb(CHIP_CS | CHIP_DO | CHIP_SK, port); /* A? bit of read */ - } else { - outb(CHIP_CS, port); - outb(CHIP_CS | CHIP_SK, port); /* A? bit of read */ - } - } - (void)inb(port); - value = 0; - for (k = 0, j = 0x8000; k < 16; k++, j >>= 1) { - outb(CHIP_CS, port); - outb(CHIP_CS | CHIP_SK, port); - if (inb(port) & CHIP_DI) - value |= j; - } - regs[i] = value; - outb(0, port); - } - mxser_normal_mode(port); - return id; -} + unsigned int i, j; -static int mxser_program_mode(int port) -{ - int id, i, j, n; - /* unsigned long flags; */ + pr_debug("Unloading module mxser ...\n"); - spin_lock(&gm_lock); - outb(0, port); - outb(0, port); - outb(0, port); - (void)inb(port); - (void)inb(port); - outb(0, port); - (void)inb(port); - /* restore_flags(flags); */ - spin_unlock(&gm_lock); + pci_unregister_driver(&mxser_driver); - id = inb(port + 1) & 0x1F; - if ((id != C168_ASIC_ID) && - (id != C104_ASIC_ID) && - (id != C102_ASIC_ID) && - (id != CI132_ASIC_ID) && - (id != CI134_ASIC_ID) && - (id != CI104J_ASIC_ID)) - return -1; - for (i = 0, j = 0; i < 4; i++) { - n = inb(port + 2); - if (n == 'M') { - j = 1; - } else if ((j == 1) && (n == 1)) { - j = 2; - break; - } else - j = 0; - } - if (j != 2) - id = -2; - return id; -} + for (i = 0; i < MXSER_BOARDS; i++) /* ISA remains */ + if (mxser_boards[i].info != NULL) + for (j = 0; j < mxser_boards[i].info->nports; j++) + tty_unregister_device(mxvar_sdriver, + mxser_boards[i].idx + j); + tty_unregister_driver(mxvar_sdriver); + put_tty_driver(mxvar_sdriver); -static void mxser_normal_mode(int port) -{ - int i, n; + for (i = 0; i < MXSER_BOARDS; i++) + if (mxser_boards[i].info != NULL) + mxser_release_res(&mxser_boards[i], NULL, 1); - outb(0xA5, port + 1); - outb(0x80, port + 3); - outb(12, port + 0); /* 9600 bps */ - outb(0, port + 1); - outb(0x03, port + 3); /* 8 data bits */ - outb(0x13, port + 4); /* loop back mode */ - for (i = 0; i < 16; i++) { - n = inb(port + 5); - if ((n & 0x61) == 0x60) - break; - if ((n & 1) == 1) - (void)inb(port); - } - outb(0x00, port + 4); + pr_debug("Done.\n"); } module_init(mxser_module_init); diff --git a/drivers/char/mxser.h b/drivers/char/mxser.h index 1f4aa45ec00..84417111595 100644 --- a/drivers/char/mxser.h +++ b/drivers/char/mxser.h @@ -4,19 +4,17 @@ /* * Semi-public control interfaces */ - + /* * MOXA ioctls */ #define MOXA 0x400 #define MOXA_GETDATACOUNT (MOXA + 23) -#define MOXA_GET_CONF (MOXA + 35) #define MOXA_DIAGNOSE (MOXA + 50) #define MOXA_CHKPORTENABLE (MOXA + 60) #define MOXA_HighSpeedOn (MOXA + 61) #define MOXA_GET_MAJOR (MOXA + 63) -#define MOXA_GET_CUMAJOR (MOXA + 64) #define MOXA_GETMSTATUS (MOXA + 65) #define MOXA_SET_OP_MODE (MOXA + 66) #define MOXA_GET_OP_MODE (MOXA + 67) @@ -26,26 +24,14 @@ #define RS422_MODE 2 #define RS485_4WIRE_MODE 3 #define OP_MODE_MASK 3 -// above add by Victor Yu. 01-05-2004 - -#define TTY_THRESHOLD_THROTTLE 128 - -#define HI_WATER 768 - -// added by James. 03-11-2004. -#define MOXA_SDS_GETICOUNTER (MOXA + 68) -#define MOXA_SDS_RSTICOUNTER (MOXA + 69) -// (above) added by James. +#define MOXA_SDS_RSTICOUNTER (MOXA + 69) #define MOXA_ASPP_OQUEUE (MOXA + 70) -#define MOXA_ASPP_SETBAUD (MOXA + 71) -#define MOXA_ASPP_GETBAUD (MOXA + 72) #define MOXA_ASPP_MON (MOXA + 73) #define MOXA_ASPP_LSTATUS (MOXA + 74) #define MOXA_ASPP_MON_EXT (MOXA + 75) #define MOXA_SET_BAUD_METHOD (MOXA + 76) - /* --------------------------------------------------- */ #define NPPI_NOTIFY_PARITY 0x01 @@ -54,51 +40,46 @@ #define NPPI_NOTIFY_SW_OVERRUN 0x08 #define NPPI_NOTIFY_BREAK 0x10 -#define NPPI_NOTIFY_CTSHOLD 0x01 // Tx hold by CTS low -#define NPPI_NOTIFY_DSRHOLD 0x02 // Tx hold by DSR low -#define NPPI_NOTIFY_XOFFHOLD 0x08 // Tx hold by Xoff received -#define NPPI_NOTIFY_XOFFXENT 0x10 // Xoff Sent - -//CheckIsMoxaMust return value -#define MOXA_OTHER_UART 0x00 -#define MOXA_MUST_MU150_HWID 0x01 -#define MOXA_MUST_MU860_HWID 0x02 - -// follow just for Moxa Must chip define. -// -// when LCR register (offset 0x03) write following value, -// the Must chip will enter enchance mode. And write value -// on EFR (offset 0x02) bit 6,7 to change bank. +#define NPPI_NOTIFY_CTSHOLD 0x01 /* Tx hold by CTS low */ +#define NPPI_NOTIFY_DSRHOLD 0x02 /* Tx hold by DSR low */ +#define NPPI_NOTIFY_XOFFHOLD 0x08 /* Tx hold by Xoff received */ +#define NPPI_NOTIFY_XOFFXENT 0x10 /* Xoff Sent */ + +/* follow just for Moxa Must chip define. */ +/* */ +/* when LCR register (offset 0x03) write following value, */ +/* the Must chip will enter enchance mode. And write value */ +/* on EFR (offset 0x02) bit 6,7 to change bank. */ #define MOXA_MUST_ENTER_ENCHANCE 0xBF -// when enhance mode enable, access on general bank register +/* when enhance mode enable, access on general bank register */ #define MOXA_MUST_GDL_REGISTER 0x07 #define MOXA_MUST_GDL_MASK 0x7F #define MOXA_MUST_GDL_HAS_BAD_DATA 0x80 -#define MOXA_MUST_LSR_RERR 0x80 // error in receive FIFO -// enchance register bank select and enchance mode setting register -// when LCR register equal to 0xBF +#define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */ +/* enchance register bank select and enchance mode setting register */ +/* when LCR register equal to 0xBF */ #define MOXA_MUST_EFR_REGISTER 0x02 -// enchance mode enable +/* enchance mode enable */ #define MOXA_MUST_EFR_EFRB_ENABLE 0x10 -// enchance reister bank set 0, 1, 2 +/* enchance reister bank set 0, 1, 2 */ #define MOXA_MUST_EFR_BANK0 0x00 #define MOXA_MUST_EFR_BANK1 0x40 #define MOXA_MUST_EFR_BANK2 0x80 #define MOXA_MUST_EFR_BANK3 0xC0 #define MOXA_MUST_EFR_BANK_MASK 0xC0 -// set XON1 value register, when LCR=0xBF and change to bank0 +/* set XON1 value register, when LCR=0xBF and change to bank0 */ #define MOXA_MUST_XON1_REGISTER 0x04 -// set XON2 value register, when LCR=0xBF and change to bank0 +/* set XON2 value register, when LCR=0xBF and change to bank0 */ #define MOXA_MUST_XON2_REGISTER 0x05 -// set XOFF1 value register, when LCR=0xBF and change to bank0 +/* set XOFF1 value register, when LCR=0xBF and change to bank0 */ #define MOXA_MUST_XOFF1_REGISTER 0x06 -// set XOFF2 value register, when LCR=0xBF and change to bank0 +/* set XOFF2 value register, when LCR=0xBF and change to bank0 */ #define MOXA_MUST_XOFF2_REGISTER 0x07 #define MOXA_MUST_RBRTL_REGISTER 0x04 @@ -110,32 +91,32 @@ #define MOXA_MUST_ECR_REGISTER 0x06 #define MOXA_MUST_CSR_REGISTER 0x07 -// good data mode enable +/* good data mode enable */ #define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 -// only good data put into RxFIFO +/* only good data put into RxFIFO */ #define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 -// enable CTS interrupt +/* enable CTS interrupt */ #define MOXA_MUST_IER_ECTSI 0x80 -// enable RTS interrupt +/* enable RTS interrupt */ #define MOXA_MUST_IER_ERTSI 0x40 -// enable Xon/Xoff interrupt +/* enable Xon/Xoff interrupt */ #define MOXA_MUST_IER_XINT 0x20 -// enable GDA interrupt +/* enable GDA interrupt */ #define MOXA_MUST_IER_EGDAI 0x10 #define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI) -// GDA interrupt pending +/* GDA interrupt pending */ #define MOXA_MUST_IIR_GDA 0x1C #define MOXA_MUST_IIR_RDA 0x04 #define MOXA_MUST_IIR_RTO 0x0C #define MOXA_MUST_IIR_LSR 0x06 -// recieved Xon/Xoff or specical interrupt pending +/* recieved Xon/Xoff or specical interrupt pending */ #define MOXA_MUST_IIR_XSC 0x10 -// RTS/CTS change state interrupt pending +/* RTS/CTS change state interrupt pending */ #define MOXA_MUST_IIR_RTSCTS 0x20 #define MOXA_MUST_IIR_MASK 0x3E @@ -143,299 +124,164 @@ #define MOXA_MUST_MCR_XON_ANY 0x80 #define MOXA_MUST_MCR_TX_XON 0x08 - -// software flow control on chip mask value +/* software flow control on chip mask value */ #define MOXA_MUST_EFR_SF_MASK 0x0F -// send Xon1/Xoff1 +/* send Xon1/Xoff1 */ #define MOXA_MUST_EFR_SF_TX1 0x08 -// send Xon2/Xoff2 +/* send Xon2/Xoff2 */ #define MOXA_MUST_EFR_SF_TX2 0x04 -// send Xon1,Xon2/Xoff1,Xoff2 +/* send Xon1,Xon2/Xoff1,Xoff2 */ #define MOXA_MUST_EFR_SF_TX12 0x0C -// don't send Xon/Xoff +/* don't send Xon/Xoff */ #define MOXA_MUST_EFR_SF_TX_NO 0x00 -// Tx software flow control mask +/* Tx software flow control mask */ #define MOXA_MUST_EFR_SF_TX_MASK 0x0C -// don't receive Xon/Xoff +/* don't receive Xon/Xoff */ #define MOXA_MUST_EFR_SF_RX_NO 0x00 -// receive Xon1/Xoff1 +/* receive Xon1/Xoff1 */ #define MOXA_MUST_EFR_SF_RX1 0x02 -// receive Xon2/Xoff2 +/* receive Xon2/Xoff2 */ #define MOXA_MUST_EFR_SF_RX2 0x01 -// receive Xon1,Xon2/Xoff1,Xoff2 +/* receive Xon1,Xon2/Xoff1,Xoff2 */ #define MOXA_MUST_EFR_SF_RX12 0x03 -// Rx software flow control mask +/* Rx software flow control mask */ #define MOXA_MUST_EFR_SF_RX_MASK 0x03 -//#define MOXA_MUST_MIN_XOFFLIMIT 66 -//#define MOXA_MUST_MIN_XONLIMIT 20 -//#define ID1_RX_TRIG 120 - - -#define CHECK_MOXA_MUST_XOFFLIMIT(info) { \ - if ( (info)->IsMoxaMustChipFlag && \ - (info)->HandFlow.XoffLimit < MOXA_MUST_MIN_XOFFLIMIT ) { \ - (info)->HandFlow.XoffLimit = MOXA_MUST_MIN_XOFFLIMIT; \ - (info)->HandFlow.XonLimit = MOXA_MUST_MIN_XONLIMIT; \ - } \ -} - -#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ +#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \ + u8 __oldlcr, __efr; \ + __oldlcr = inb((baseio)+UART_LCR); \ outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr |= MOXA_MUST_EFR_EFRB_ENABLE; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} - -#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ + __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ + __efr |= MOXA_MUST_EFR_EFRB_ENABLE; \ + outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ + outb(__oldlcr, (baseio)+UART_LCR); \ +} while (0) + +#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \ + u8 __oldlcr, __efr; \ + __oldlcr = inb((baseio)+UART_LCR); \ outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} - -#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ + __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ + __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \ + outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ + outb(__oldlcr, (baseio)+UART_LCR); \ +} while (0) + +#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) do { \ + u8 __oldlcr, __efr; \ + __oldlcr = inb((baseio)+UART_LCR); \ outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ - __efr |= MOXA_MUST_EFR_BANK0; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ + __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ + __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ + __efr |= MOXA_MUST_EFR_BANK0; \ + outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} + outb(__oldlcr, (baseio)+UART_LCR); \ +} while (0) -#define SET_MOXA_MUST_XON2_VALUE(baseio, Value) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ +#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) do { \ + u8 __oldlcr, __efr; \ + __oldlcr = inb((baseio)+UART_LCR); \ outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ - __efr |= MOXA_MUST_EFR_BANK0; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb((u8)(Value), (baseio)+MOXA_MUST_XON2_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} - -#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ - __efr |= MOXA_MUST_EFR_BANK0; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ + __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ + __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ + __efr |= MOXA_MUST_EFR_BANK0; \ + outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} - -#define SET_MOXA_MUST_XOFF2_VALUE(baseio, Value) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ - __efr |= MOXA_MUST_EFR_BANK0; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb((u8)(Value), (baseio)+MOXA_MUST_XOFF2_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} - -#define SET_MOXA_MUST_RBRTL_VALUE(baseio, Value) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ - __efr |= MOXA_MUST_EFR_BANK1; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb((u8)(Value), (baseio)+MOXA_MUST_RBRTL_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} - -#define SET_MOXA_MUST_RBRTH_VALUE(baseio, Value) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ - __efr |= MOXA_MUST_EFR_BANK1; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb((u8)(Value), (baseio)+MOXA_MUST_RBRTH_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} - -#define SET_MOXA_MUST_RBRTI_VALUE(baseio, Value) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ + outb(__oldlcr, (baseio)+UART_LCR); \ +} while (0) + +#define SET_MOXA_MUST_FIFO_VALUE(info) do { \ + u8 __oldlcr, __efr; \ + __oldlcr = inb((info)->ioaddr+UART_LCR); \ + outb(MOXA_MUST_ENTER_ENCHANCE, (info)->ioaddr+UART_LCR);\ + __efr = inb((info)->ioaddr+MOXA_MUST_EFR_REGISTER); \ + __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ + __efr |= MOXA_MUST_EFR_BANK1; \ + outb(__efr, (info)->ioaddr+MOXA_MUST_EFR_REGISTER); \ + outb((u8)((info)->rx_high_water), (info)->ioaddr+ \ + MOXA_MUST_RBRTH_REGISTER); \ + outb((u8)((info)->rx_trigger), (info)->ioaddr+ \ + MOXA_MUST_RBRTI_REGISTER); \ + outb((u8)((info)->rx_low_water), (info)->ioaddr+ \ + MOXA_MUST_RBRTL_REGISTER); \ + outb(__oldlcr, (info)->ioaddr+UART_LCR); \ +} while (0) + +#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) do { \ + u8 __oldlcr, __efr; \ + __oldlcr = inb((baseio)+UART_LCR); \ outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ - __efr |= MOXA_MUST_EFR_BANK1; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb((u8)(Value), (baseio)+MOXA_MUST_RBRTI_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} - -#define SET_MOXA_MUST_THRTL_VALUE(baseio, Value) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ - __efr |= MOXA_MUST_EFR_BANK1; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb((u8)(Value), (baseio)+MOXA_MUST_THRTL_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} - -//#define MOXA_MUST_RBRL_VALUE 4 -#define SET_MOXA_MUST_FIFO_VALUE(info) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((info)->base+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (info)->base+UART_LCR); \ - __efr = inb((info)->base+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ - __efr |= MOXA_MUST_EFR_BANK1; \ - outb(__efr, (info)->base+MOXA_MUST_EFR_REGISTER); \ - outb((u8)((info)->rx_high_water), (info)->base+MOXA_MUST_RBRTH_REGISTER); \ - outb((u8)((info)->rx_trigger), (info)->base+MOXA_MUST_RBRTI_REGISTER); \ - outb((u8)((info)->rx_low_water), (info)->base+MOXA_MUST_RBRTL_REGISTER); \ - outb(__oldlcr, (info)->base+UART_LCR); \ -} - - - -#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ - __efr |= MOXA_MUST_EFR_BANK2; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ + __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ + __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ + __efr |= MOXA_MUST_EFR_BANK2; \ + outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} + outb(__oldlcr, (baseio)+UART_LCR); \ +} while (0) -#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ - __efr |= MOXA_MUST_EFR_BANK2; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} - -#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_SF_MASK; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} - -#define SET_MOXA_MUST_JUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_SF_MASK; \ - __efr |= MOXA_MUST_EFR_SF_TX1; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} - -#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ +#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) do { \ + u8 __oldlcr, __efr; \ + __oldlcr = inb((baseio)+UART_LCR); \ outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \ - __efr |= MOXA_MUST_EFR_SF_TX1; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} - -#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ + __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ + __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ + __efr |= MOXA_MUST_EFR_BANK2; \ + outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ + *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \ + outb(__oldlcr, (baseio)+UART_LCR); \ +} while (0) + +#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) do { \ + u8 __oldlcr, __efr; \ + __oldlcr = inb((baseio)+UART_LCR); \ outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} - -#define SET_MOXA_MUST_JUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ + __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ + __efr &= ~MOXA_MUST_EFR_SF_MASK; \ + outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ + outb(__oldlcr, (baseio)+UART_LCR); \ +} while (0) + +#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \ + u8 __oldlcr, __efr; \ + __oldlcr = inb((baseio)+UART_LCR); \ outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_SF_MASK; \ - __efr |= MOXA_MUST_EFR_SF_RX1; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} - -#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ + __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ + __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \ + __efr |= MOXA_MUST_EFR_SF_TX1; \ + outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ + outb(__oldlcr, (baseio)+UART_LCR); \ +} while (0) + +#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \ + u8 __oldlcr, __efr; \ + __oldlcr = inb((baseio)+UART_LCR); \ outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \ - __efr |= MOXA_MUST_EFR_SF_RX1; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} - -#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ + __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ + __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \ + outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ + outb(__oldlcr, (baseio)+UART_LCR); \ +} while (0) + +#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \ + u8 __oldlcr, __efr; \ + __oldlcr = inb((baseio)+UART_LCR); \ outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} - -#define ENABLE_MOXA_MUST_TX_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ + __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ + __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \ + __efr |= MOXA_MUST_EFR_SF_RX1; \ + outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ + outb(__oldlcr, (baseio)+UART_LCR); \ +} while (0) + +#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \ + u8 __oldlcr, __efr; \ + __oldlcr = inb((baseio)+UART_LCR); \ outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_SF_MASK; \ - __efr |= (MOXA_MUST_EFR_SF_RX1|MOXA_MUST_EFR_SF_TX1); \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} - -#define ENABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(baseio) { \ - u8 __oldmcr; \ - __oldmcr = inb((baseio)+UART_MCR); \ - __oldmcr |= MOXA_MUST_MCR_XON_ANY; \ - outb(__oldmcr, (baseio)+UART_MCR); \ -} - -#define DISABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(baseio) { \ - u8 __oldmcr; \ - __oldmcr = inb((baseio)+UART_MCR); \ - __oldmcr &= ~MOXA_MUST_MCR_XON_ANY; \ - outb(__oldmcr, (baseio)+UART_MCR); \ -} - -#define READ_MOXA_MUST_GDL(baseio) inb((baseio)+MOXA_MUST_GDL_REGISTER) + __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ + __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \ + outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ + outb(__oldlcr, (baseio)+UART_LCR); \ +} while (0) #endif diff --git a/drivers/char/mxser_new.c b/drivers/char/mxser_new.c deleted file mode 100644 index bf1bee4e1f5..00000000000 --- a/drivers/char/mxser_new.c +++ /dev/null @@ -1,2816 +0,0 @@ -/* - * mxser.c -- MOXA Smartio/Industio family multiport serial driver. - * - * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com.tw). - * Copyright (C) 2006-2007 Jiri Slaby <jirislaby@gmail.com> - * - * This code is loosely based on the 1.8 moxa driver which is based on - * Linux serial driver, written by Linus Torvalds, Theodore T'so and - * others. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox - * <alan@redhat.com>. The original 1.8 code is available on www.moxa.com. - * - Fixed x86_64 cleanness - * - Fixed sleep with spinlock held in mxser_send_break - */ - -#include <linux/module.h> -#include <linux/errno.h> -#include <linux/signal.h> -#include <linux/sched.h> -#include <linux/timer.h> -#include <linux/interrupt.h> -#include <linux/tty.h> -#include <linux/tty_flip.h> -#include <linux/serial.h> -#include <linux/serial_reg.h> -#include <linux/major.h> -#include <linux/string.h> -#include <linux/fcntl.h> -#include <linux/ptrace.h> -#include <linux/gfp.h> -#include <linux/ioport.h> -#include <linux/mm.h> -#include <linux/delay.h> -#include <linux/pci.h> -#include <linux/bitops.h> - -#include <asm/system.h> -#include <asm/io.h> -#include <asm/irq.h> -#include <asm/uaccess.h> - -#include "mxser_new.h" - -#define MXSER_VERSION "2.0.2" /* 1.10 */ -#define MXSERMAJOR 174 -#define MXSERCUMAJOR 175 - -#define MXSER_BOARDS 4 /* Max. boards */ -#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */ -#define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD) -#define MXSER_ISR_PASS_LIMIT 100 - -#define MXSER_ERR_IOADDR -1 -#define MXSER_ERR_IRQ -2 -#define MXSER_ERR_IRQ_CONFLIT -3 -#define MXSER_ERR_VECTOR -4 - -/*CheckIsMoxaMust return value*/ -#define MOXA_OTHER_UART 0x00 -#define MOXA_MUST_MU150_HWID 0x01 -#define MOXA_MUST_MU860_HWID 0x02 - -#define WAKEUP_CHARS 256 - -#define UART_MCR_AFE 0x20 -#define UART_LSR_SPECIAL 0x1E - -#define PCI_DEVICE_ID_CB108 0x1080 -#define PCI_DEVICE_ID_CB114 0x1142 -#define PCI_DEVICE_ID_CB134I 0x1341 -#define PCI_DEVICE_ID_CP138U 0x1380 -#define PCI_DEVICE_ID_POS104UL 0x1044 - - -#define C168_ASIC_ID 1 -#define C104_ASIC_ID 2 -#define C102_ASIC_ID 0xB -#define CI132_ASIC_ID 4 -#define CI134_ASIC_ID 3 -#define CI104J_ASIC_ID 5 - -#define MXSER_HIGHBAUD 1 -#define MXSER_HAS2 2 - -/* This is only for PCI */ -static const struct { - int type; - int tx_fifo; - int rx_fifo; - int xmit_fifo_size; - int rx_high_water; - int rx_trigger; - int rx_low_water; - long max_baud; -} Gpci_uart_info[] = { - {MOXA_OTHER_UART, 16, 16, 16, 14, 14, 1, 921600L}, - {MOXA_MUST_MU150_HWID, 64, 64, 64, 48, 48, 16, 230400L}, - {MOXA_MUST_MU860_HWID, 128, 128, 128, 96, 96, 32, 921600L} -}; -#define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info) - -struct mxser_cardinfo { - unsigned int nports; - char *name; - unsigned int flags; -}; - -static const struct mxser_cardinfo mxser_cards[] = { -/* 0*/ { 8, "C168 series", }, - { 4, "C104 series", }, - { 4, "CI-104J series", }, - { 8, "C168H/PCI series", }, - { 4, "C104H/PCI series", }, -/* 5*/ { 4, "C102 series", MXSER_HAS2 }, /* C102-ISA */ - { 4, "CI-132 series", MXSER_HAS2 }, - { 4, "CI-134 series", }, - { 2, "CP-132 series", }, - { 4, "CP-114 series", }, -/*10*/ { 4, "CT-114 series", }, - { 2, "CP-102 series", MXSER_HIGHBAUD }, - { 4, "CP-104U series", }, - { 8, "CP-168U series", }, - { 2, "CP-132U series", }, -/*15*/ { 4, "CP-134U series", }, - { 4, "CP-104JU series", }, - { 8, "Moxa UC7000 Serial", }, /* RC7000 */ - { 8, "CP-118U series", }, - { 2, "CP-102UL series", }, -/*20*/ { 2, "CP-102U series", }, - { 8, "CP-118EL series", }, - { 8, "CP-168EL series", }, - { 4, "CP-104EL series", }, - { 8, "CB-108 series", }, -/*25*/ { 4, "CB-114 series", }, - { 4, "CB-134I series", }, - { 8, "CP-138U series", }, - { 4, "POS-104UL series", } -}; - -/* driver_data correspond to the lines in the structure above - see also ISA probe function before you change something */ -static struct pci_device_id mxser_pcibrds[] = { - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168), .driver_data = 3 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104), .driver_data = 4 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132), .driver_data = 8 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114), .driver_data = 9 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114), .driver_data = 10 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102), .driver_data = 11 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U), .driver_data = 12 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U), .driver_data = 13 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U), .driver_data = 14 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U), .driver_data = 15 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 16 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000), .driver_data = 17 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U), .driver_data = 18 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 19 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U), .driver_data = 20 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 21 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 22 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 23 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108), .driver_data = 24 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114), .driver_data = 25 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I), .driver_data = 26 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U), .driver_data = 27 }, - { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL), .driver_data = 28 }, - { } -}; -MODULE_DEVICE_TABLE(pci, mxser_pcibrds); - -static int mxvar_baud_table[] = { - 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400, - 4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 -}; -static unsigned int mxvar_baud_table1[] = { - 0, B50, B75, B110, B134, B150, B200, B300, B600, B1200, B1800, B2400, - B4800, B9600, B19200, B38400, B57600, B115200, B230400, B460800, B921600 -}; -#define BAUD_TABLE_NO ARRAY_SIZE(mxvar_baud_table) - -#define B_SPEC B2000000 - -static int ioaddr[MXSER_BOARDS] = { 0, 0, 0, 0 }; -static int ttymajor = MXSERMAJOR; -static int calloutmajor = MXSERCUMAJOR; - -/* Variables for insmod */ - -MODULE_AUTHOR("Casper Yang"); -MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver"); -module_param_array(ioaddr, int, NULL, 0); -module_param(ttymajor, int, 0); -MODULE_LICENSE("GPL"); - -struct mxser_log { - int tick; - unsigned long rxcnt[MXSER_PORTS]; - unsigned long txcnt[MXSER_PORTS]; -}; - - -struct mxser_mon { - unsigned long rxcnt; - unsigned long txcnt; - unsigned long up_rxcnt; - unsigned long up_txcnt; - int modem_status; - unsigned char hold_reason; -}; - -struct mxser_mon_ext { - unsigned long rx_cnt[32]; - unsigned long tx_cnt[32]; - unsigned long up_rxcnt[32]; - unsigned long up_txcnt[32]; - int modem_status[32]; - - long baudrate[32]; - int databits[32]; - int stopbits[32]; - int parity[32]; - int flowctrl[32]; - int fifo[32]; - int iftype[32]; -}; - -struct mxser_board; - -struct mxser_port { - struct mxser_board *board; - struct tty_struct *tty; - - unsigned long ioaddr; - unsigned long opmode_ioaddr; - int max_baud; - - int rx_high_water; - int rx_trigger; /* Rx fifo trigger level */ - int rx_low_water; - int baud_base; /* max. speed */ - long realbaud; - int type; /* UART type */ - int flags; /* defined in tty.h */ - int speed; - - int x_char; /* xon/xoff character */ - int IER; /* Interrupt Enable Register */ - int MCR; /* Modem control register */ - - unsigned char stop_rx; - unsigned char ldisc_stop_rx; - - int custom_divisor; - int close_delay; - unsigned short closing_wait; - unsigned char err_shadow; - unsigned long event; - - int count; /* # of fd on device */ - int blocked_open; /* # of blocked opens */ - struct async_icount icount; /* kernel counters for 4 input interrupts */ - int timeout; - - int read_status_mask; - int ignore_status_mask; - int xmit_fifo_size; - unsigned char *xmit_buf; - int xmit_head; - int xmit_tail; - int xmit_cnt; - - struct ktermios normal_termios; - - struct mxser_mon mon_data; - - spinlock_t slock; - wait_queue_head_t open_wait; - wait_queue_head_t delta_msr_wait; -}; - -struct mxser_board { - unsigned int idx; - int irq; - const struct mxser_cardinfo *info; - unsigned long vector; - unsigned long vector_mask; - - int chip_flag; - int uart_type; - - struct mxser_port ports[MXSER_PORTS_PER_BOARD]; -}; - -struct mxser_mstatus { - tcflag_t cflag; - int cts; - int dsr; - int ri; - int dcd; -}; - -static struct mxser_mstatus GMStatus[MXSER_PORTS]; - -static int mxserBoardCAP[MXSER_BOARDS] = { - 0, 0, 0, 0 - /* 0x180, 0x280, 0x200, 0x320 */ -}; - -static struct mxser_board mxser_boards[MXSER_BOARDS]; -static struct tty_driver *mxvar_sdriver; -static struct mxser_log mxvar_log; -static int mxvar_diagflag; -static unsigned char mxser_msr[MXSER_PORTS + 1]; -static struct mxser_mon_ext mon_data_ext; -static int mxser_set_baud_method[MXSER_PORTS + 1]; - -#ifdef CONFIG_PCI -static int __devinit CheckIsMoxaMust(int io) -{ - u8 oldmcr, hwid; - int i; - - outb(0, io + UART_LCR); - DISABLE_MOXA_MUST_ENCHANCE_MODE(io); - oldmcr = inb(io + UART_MCR); - outb(0, io + UART_MCR); - SET_MOXA_MUST_XON1_VALUE(io, 0x11); - if ((hwid = inb(io + UART_MCR)) != 0) { - outb(oldmcr, io + UART_MCR); - return MOXA_OTHER_UART; - } - - GET_MOXA_MUST_HARDWARE_ID(io, &hwid); - for (i = 1; i < UART_INFO_NUM; i++) { /* 0 = OTHER_UART */ - if (hwid == Gpci_uart_info[i].type) - return (int)hwid; - } - return MOXA_OTHER_UART; -} -#endif - -static void process_txrx_fifo(struct mxser_port *info) -{ - int i; - - if ((info->type == PORT_16450) || (info->type == PORT_8250)) { - info->rx_trigger = 1; - info->rx_high_water = 1; - info->rx_low_water = 1; - info->xmit_fifo_size = 1; - } else - for (i = 0; i < UART_INFO_NUM; i++) - if (info->board->chip_flag == Gpci_uart_info[i].type) { - info->rx_trigger = Gpci_uart_info[i].rx_trigger; - info->rx_low_water = Gpci_uart_info[i].rx_low_water; - info->rx_high_water = Gpci_uart_info[i].rx_high_water; - info->xmit_fifo_size = Gpci_uart_info[i].xmit_fifo_size; - break; - } -} - -static unsigned char mxser_get_msr(int baseaddr, int mode, int port) -{ - unsigned char status = 0; - - status = inb(baseaddr + UART_MSR); - - mxser_msr[port] &= 0x0F; - mxser_msr[port] |= status; - status = mxser_msr[port]; - if (mode) - mxser_msr[port] = 0; - - return status; -} - -static int mxser_block_til_ready(struct tty_struct *tty, struct file *filp, - struct mxser_port *port) -{ - DECLARE_WAITQUEUE(wait, current); - int retval; - int do_clocal = 0; - unsigned long flags; - - /* - * If non-blocking mode is set, or the port is not enabled, - * then make the check up front and then exit. - */ - if ((filp->f_flags & O_NONBLOCK) || - test_bit(TTY_IO_ERROR, &tty->flags)) { - port->flags |= ASYNC_NORMAL_ACTIVE; - return 0; - } - - if (tty->termios->c_cflag & CLOCAL) - do_clocal = 1; - - /* - * Block waiting for the carrier detect and the line to become - * free (i.e., not in use by the callout). While we are in - * this loop, port->count is dropped by one, so that - * mxser_close() knows when to free things. We restore it upon - * exit, either normal or abnormal. - */ - retval = 0; - add_wait_queue(&port->open_wait, &wait); - - spin_lock_irqsave(&port->slock, flags); - if (!tty_hung_up_p(filp)) - port->count--; - spin_unlock_irqrestore(&port->slock, flags); - port->blocked_open++; - while (1) { - spin_lock_irqsave(&port->slock, flags); - outb(inb(port->ioaddr + UART_MCR) | - UART_MCR_DTR | UART_MCR_RTS, port->ioaddr + UART_MCR); - spin_unlock_irqrestore(&port->slock, flags); - set_current_state(TASK_INTERRUPTIBLE); - if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)) { - if (port->flags & ASYNC_HUP_NOTIFY) - retval = -EAGAIN; - else - retval = -ERESTARTSYS; - break; - } - if (!(port->flags & ASYNC_CLOSING) && - (do_clocal || - (inb(port->ioaddr + UART_MSR) & UART_MSR_DCD))) - break; - if (signal_pending(current)) { - retval = -ERESTARTSYS; - break; - } - schedule(); - } - set_current_state(TASK_RUNNING); - remove_wait_queue(&port->open_wait, &wait); - if (!tty_hung_up_p(filp)) - port->count++; - port->blocked_open--; - if (retval) - return retval; - port->flags |= ASYNC_NORMAL_ACTIVE; - return 0; -} - -static int mxser_set_baud(struct mxser_port *info, long newspd) -{ - unsigned int i; - int quot = 0; - unsigned char cval; - int ret = 0; - - if (!info->tty || !info->tty->termios) - return ret; - - if (!(info->ioaddr)) - return ret; - - if (newspd > info->max_baud) - return 0; - - info->realbaud = newspd; - for (i = 0; i < BAUD_TABLE_NO; i++) - if (newspd == mxvar_baud_table[i]) - break; - if (i == BAUD_TABLE_NO) { - quot = info->baud_base / info->speed; - if (info->speed <= 0 || info->speed > info->max_baud) - quot = 0; - } else { - if (newspd == 134) { - quot = (2 * info->baud_base / 269); - } else if (newspd) { - quot = info->baud_base / newspd; - if (quot == 0) - quot = 1; - } else { - quot = 0; - } - } - - info->timeout = ((info->xmit_fifo_size * HZ * 10 * quot) / info->baud_base); - info->timeout += HZ / 50; /* Add .02 seconds of slop */ - - if (quot) { - info->MCR |= UART_MCR_DTR; - outb(info->MCR, info->ioaddr + UART_MCR); - } else { - info->MCR &= ~UART_MCR_DTR; - outb(info->MCR, info->ioaddr + UART_MCR); - return ret; - } - - cval = inb(info->ioaddr + UART_LCR); - - outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */ - - outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */ - outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */ - outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */ - - if (i == BAUD_TABLE_NO) { - quot = info->baud_base % info->speed; - quot *= 8; - if ((quot % info->speed) > (info->speed / 2)) { - quot /= info->speed; - quot++; - } else { - quot /= info->speed; - } - SET_MOXA_MUST_ENUM_VALUE(info->ioaddr, quot); - } else - SET_MOXA_MUST_ENUM_VALUE(info->ioaddr, 0); - - return ret; -} - -/* - * This routine is called to set the UART divisor registers to match - * the specified baud rate for a serial port. - */ -static int mxser_change_speed(struct mxser_port *info, - struct ktermios *old_termios) -{ - unsigned cflag, cval, fcr; - int ret = 0; - unsigned char status; - long baud; - - if (!info->tty || !info->tty->termios) - return ret; - cflag = info->tty->termios->c_cflag; - if (!(info->ioaddr)) - return ret; - - if (mxser_set_baud_method[info->tty->index] == 0) { - if ((cflag & CBAUD) == B_SPEC) - baud = info->speed; - else - baud = tty_get_baud_rate(info->tty); - mxser_set_baud(info, baud); - } - - /* byte size and parity */ - switch (cflag & CSIZE) { - case CS5: - cval = 0x00; - break; - case CS6: - cval = 0x01; - break; - case CS7: - cval = 0x02; - break; - case CS8: - cval = 0x03; - break; - default: - cval = 0x00; - break; /* too keep GCC shut... */ - } - if (cflag & CSTOPB) - cval |= 0x04; - if (cflag & PARENB) - cval |= UART_LCR_PARITY; - if (!(cflag & PARODD)) - cval |= UART_LCR_EPAR; - if (cflag & CMSPAR) - cval |= UART_LCR_SPAR; - - if ((info->type == PORT_8250) || (info->type == PORT_16450)) { - if (info->board->chip_flag) { - fcr = UART_FCR_ENABLE_FIFO; - fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; - SET_MOXA_MUST_FIFO_VALUE(info); - } else - fcr = 0; - } else { - fcr = UART_FCR_ENABLE_FIFO; - if (info->board->chip_flag) { - fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; - SET_MOXA_MUST_FIFO_VALUE(info); - } else { - switch (info->rx_trigger) { - case 1: - fcr |= UART_FCR_TRIGGER_1; - break; - case 4: - fcr |= UART_FCR_TRIGGER_4; - break; - case 8: - fcr |= UART_FCR_TRIGGER_8; - break; - default: - fcr |= UART_FCR_TRIGGER_14; - break; - } - } - } - - /* CTS flow control flag and modem status interrupts */ - info->IER &= ~UART_IER_MSI; - info->MCR &= ~UART_MCR_AFE; - if (cflag & CRTSCTS) { - info->flags |= ASYNC_CTS_FLOW; - info->IER |= UART_IER_MSI; - if ((info->type == PORT_16550A) || (info->board->chip_flag)) { - info->MCR |= UART_MCR_AFE; - } else { - status = inb(info->ioaddr + UART_MSR); - if (info->tty->hw_stopped) { - if (status & UART_MSR_CTS) { - info->tty->hw_stopped = 0; - if (info->type != PORT_16550A && - !info->board->chip_flag) { - outb(info->IER & ~UART_IER_THRI, - info->ioaddr + - UART_IER); - info->IER |= UART_IER_THRI; - outb(info->IER, info->ioaddr + - UART_IER); - } - tty_wakeup(info->tty); - } - } else { - if (!(status & UART_MSR_CTS)) { - info->tty->hw_stopped = 1; - if ((info->type != PORT_16550A) && - (!info->board->chip_flag)) { - info->IER &= ~UART_IER_THRI; - outb(info->IER, info->ioaddr + - UART_IER); - } - } - } - } - } else { - info->flags &= ~ASYNC_CTS_FLOW; - } - outb(info->MCR, info->ioaddr + UART_MCR); - if (cflag & CLOCAL) { - info->flags &= ~ASYNC_CHECK_CD; - } else { - info->flags |= ASYNC_CHECK_CD; - info->IER |= UART_IER_MSI; - } - outb(info->IER, info->ioaddr + UART_IER); - - /* - * Set up parity check flag - */ - info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; - if (I_INPCK(info->tty)) - info->read_status_mask |= UART_LSR_FE | UART_LSR_PE; - if (I_BRKINT(info->tty) || I_PARMRK(info->tty)) - info->read_status_mask |= UART_LSR_BI; - - info->ignore_status_mask = 0; - - if (I_IGNBRK(info->tty)) { - info->ignore_status_mask |= UART_LSR_BI; - info->read_status_mask |= UART_LSR_BI; - /* - * If we're ignore parity and break indicators, ignore - * overruns too. (For real raw support). - */ - if (I_IGNPAR(info->tty)) { - info->ignore_status_mask |= - UART_LSR_OE | - UART_LSR_PE | - UART_LSR_FE; - info->read_status_mask |= - UART_LSR_OE | - UART_LSR_PE | - UART_LSR_FE; - } - } - if (info->board->chip_flag) { - SET_MOXA_MUST_XON1_VALUE(info->ioaddr, START_CHAR(info->tty)); - SET_MOXA_MUST_XOFF1_VALUE(info->ioaddr, STOP_CHAR(info->tty)); - if (I_IXON(info->tty)) { - ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr); - } else { - DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr); - } - if (I_IXOFF(info->tty)) { - ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->ioaddr); - } else { - DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->ioaddr); - } - } - - - outb(fcr, info->ioaddr + UART_FCR); /* set fcr */ - outb(cval, info->ioaddr + UART_LCR); - - return ret; -} - -static void mxser_check_modem_status(struct mxser_port *port, int status) -{ - /* update input line counters */ - if (status & UART_MSR_TERI) - port->icount.rng++; - if (status & UART_MSR_DDSR) - port->icount.dsr++; - if (status & UART_MSR_DDCD) - port->icount.dcd++; - if (status & UART_MSR_DCTS) - port->icount.cts++; - port->mon_data.modem_status = status; - wake_up_interruptible(&port->delta_msr_wait); - - if ((port->flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) { - if (status & UART_MSR_DCD) - wake_up_interruptible(&port->open_wait); - } - - if (port->flags & ASYNC_CTS_FLOW) { - if (port->tty->hw_stopped) { - if (status & UART_MSR_CTS) { - port->tty->hw_stopped = 0; - - if ((port->type != PORT_16550A) && - (!port->board->chip_flag)) { - outb(port->IER & ~UART_IER_THRI, - port->ioaddr + UART_IER); - port->IER |= UART_IER_THRI; - outb(port->IER, port->ioaddr + - UART_IER); - } - tty_wakeup(port->tty); - } - } else { - if (!(status & UART_MSR_CTS)) { - port->tty->hw_stopped = 1; - if (port->type != PORT_16550A && - !port->board->chip_flag) { - port->IER &= ~UART_IER_THRI; - outb(port->IER, port->ioaddr + - UART_IER); - } - } - } - } -} - -static int mxser_startup(struct mxser_port *info) -{ - unsigned long page; - unsigned long flags; - - page = __get_free_page(GFP_KERNEL); - if (!page) - return -ENOMEM; - - spin_lock_irqsave(&info->slock, flags); - - if (info->flags & ASYNC_INITIALIZED) { - free_page(page); - spin_unlock_irqrestore(&info->slock, flags); - return 0; - } - - if (!info->ioaddr || !info->type) { - if (info->tty) - set_bit(TTY_IO_ERROR, &info->tty->flags); - free_page(page); - spin_unlock_irqrestore(&info->slock, flags); - return 0; - } - if (info->xmit_buf) - free_page(page); - else - info->xmit_buf = (unsigned char *) page; - - /* - * Clear the FIFO buffers and disable them - * (they will be reenabled in mxser_change_speed()) - */ - if (info->board->chip_flag) - outb((UART_FCR_CLEAR_RCVR | - UART_FCR_CLEAR_XMIT | - MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR); - else - outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT), - info->ioaddr + UART_FCR); - - /* - * At this point there's no way the LSR could still be 0xFF; - * if it is, then bail out, because there's likely no UART - * here. - */ - if (inb(info->ioaddr + UART_LSR) == 0xff) { - spin_unlock_irqrestore(&info->slock, flags); - if (capable(CAP_SYS_ADMIN)) { - if (info->tty) - set_bit(TTY_IO_ERROR, &info->tty->flags); - return 0; - } else - return -ENODEV; - } - - /* - * Clear the interrupt registers. - */ - (void) inb(info->ioaddr + UART_LSR); - (void) inb(info->ioaddr + UART_RX); - (void) inb(info->ioaddr + UART_IIR); - (void) inb(info->ioaddr + UART_MSR); - - /* - * Now, initialize the UART - */ - outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */ - info->MCR = UART_MCR_DTR | UART_MCR_RTS; - outb(info->MCR, info->ioaddr + UART_MCR); - - /* - * Finally, enable interrupts - */ - info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; - - if (info->board->chip_flag) - info->IER |= MOXA_MUST_IER_EGDAI; - outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */ - - /* - * And clear the interrupt registers again for luck. - */ - (void) inb(info->ioaddr + UART_LSR); - (void) inb(info->ioaddr + UART_RX); - (void) inb(info->ioaddr + UART_IIR); - (void) inb(info->ioaddr + UART_MSR); - - if (info->tty) - clear_bit(TTY_IO_ERROR, &info->tty->flags); - info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; - - /* - * and set the speed of the serial port - */ - mxser_change_speed(info, NULL); - info->flags |= ASYNC_INITIALIZED; - spin_unlock_irqrestore(&info->slock, flags); - - return 0; -} - -/* - * This routine will shutdown a serial port; interrupts maybe disabled, and - * DTR is dropped if the hangup on close termio flag is on. - */ -static void mxser_shutdown(struct mxser_port *info) -{ - unsigned long flags; - - if (!(info->flags & ASYNC_INITIALIZED)) - return; - - spin_lock_irqsave(&info->slock, flags); - - /* - * clear delta_msr_wait queue to avoid mem leaks: we may free the irq - * here so the queue might never be waken up - */ - wake_up_interruptible(&info->delta_msr_wait); - - /* - * Free the IRQ, if necessary - */ - if (info->xmit_buf) { - free_page((unsigned long) info->xmit_buf); - info->xmit_buf = NULL; - } - - info->IER = 0; - outb(0x00, info->ioaddr + UART_IER); - - if (!info->tty || (info->tty->termios->c_cflag & HUPCL)) - info->MCR &= ~(UART_MCR_DTR | UART_MCR_RTS); - outb(info->MCR, info->ioaddr + UART_MCR); - - /* clear Rx/Tx FIFO's */ - if (info->board->chip_flag) - outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | - MOXA_MUST_FCR_GDA_MODE_ENABLE, - info->ioaddr + UART_FCR); - else - outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, - info->ioaddr + UART_FCR); - - /* read data port to reset things */ - (void) inb(info->ioaddr + UART_RX); - - if (info->tty) - set_bit(TTY_IO_ERROR, &info->tty->flags); - - info->flags &= ~ASYNC_INITIALIZED; - - if (info->board->chip_flag) - SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->ioaddr); - - spin_unlock_irqrestore(&info->slock, flags); -} - -/* - * This routine is called whenever a serial port is opened. It - * enables interrupts for a serial port, linking in its async structure into - * the IRQ chain. It also performs the serial-specific - * initialization for the tty structure. - */ -static int mxser_open(struct tty_struct *tty, struct file *filp) -{ - struct mxser_port *info; - unsigned long flags; - int retval, line; - - line = tty->index; - if (line == MXSER_PORTS) - return 0; - if (line < 0 || line > MXSER_PORTS) - return -ENODEV; - info = &mxser_boards[line / MXSER_PORTS_PER_BOARD].ports[line % MXSER_PORTS_PER_BOARD]; - if (!info->ioaddr) - return -ENODEV; - - tty->driver_data = info; - info->tty = tty; - /* - * Start up serial port - */ - spin_lock_irqsave(&info->slock, flags); - info->count++; - spin_unlock_irqrestore(&info->slock, flags); - retval = mxser_startup(info); - if (retval) - return retval; - - retval = mxser_block_til_ready(tty, filp, info); - if (retval) - return retval; - - /* unmark here for very high baud rate (ex. 921600 bps) used */ - tty->low_latency = 1; - return 0; -} - -/* - * This routine is called when the serial port gets closed. First, we - * wait for the last remaining data to be sent. Then, we unlink its - * async structure from the interrupt chain if necessary, and we free - * that IRQ if nothing is left in the chain. - */ -static void mxser_close(struct tty_struct *tty, struct file *filp) -{ - struct mxser_port *info = tty->driver_data; - - unsigned long timeout; - unsigned long flags; - - if (tty->index == MXSER_PORTS) - return; - if (!info) - return; - - spin_lock_irqsave(&info->slock, flags); - - if (tty_hung_up_p(filp)) { - spin_unlock_irqrestore(&info->slock, flags); - return; - } - if ((tty->count == 1) && (info->count != 1)) { - /* - * Uh, oh. tty->count is 1, which means that the tty - * structure will be freed. Info->count should always - * be one in these conditions. If it's greater than - * one, we've got real problems, since it means the - * serial port won't be shutdown. - */ - printk(KERN_ERR "mxser_close: bad serial port count; " - "tty->count is 1, info->count is %d\n", info->count); - info->count = 1; - } - if (--info->count < 0) { - printk(KERN_ERR "mxser_close: bad serial port count for " - "ttys%d: %d\n", tty->index, info->count); - info->count = 0; - } - if (info->count) { - spin_unlock_irqrestore(&info->slock, flags); - return; - } - info->flags |= ASYNC_CLOSING; - spin_unlock_irqrestore(&info->slock, flags); - /* - * Save the termios structure, since this port may have - * separate termios for callout and dialin. - */ - if (info->flags & ASYNC_NORMAL_ACTIVE) - info->normal_termios = *tty->termios; - /* - * Now we wait for the transmit buffer to clear; and we notify - * the line discipline to only process XON/XOFF characters. - */ - tty->closing = 1; - if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) - tty_wait_until_sent(tty, info->closing_wait); - /* - * At this point we stop accepting input. To do this, we - * disable the receive line status interrupts, and tell the - * interrupt driver to stop checking the data ready bit in the - * line status register. - */ - info->IER &= ~UART_IER_RLSI; - if (info->board->chip_flag) - info->IER &= ~MOXA_MUST_RECV_ISR; - - if (info->flags & ASYNC_INITIALIZED) { - outb(info->IER, info->ioaddr + UART_IER); - /* - * Before we drop DTR, make sure the UART transmitter - * has completely drained; this is especially - * important if there is a transmit FIFO! - */ - timeout = jiffies + HZ; - while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) { - schedule_timeout_interruptible(5); - if (time_after(jiffies, timeout)) - break; - } - } - mxser_shutdown(info); - - if (tty->driver->flush_buffer) - tty->driver->flush_buffer(tty); - - tty_ldisc_flush(tty); - - tty->closing = 0; - info->event = 0; - info->tty = NULL; - if (info->blocked_open) { - if (info->close_delay) - schedule_timeout_interruptible(info->close_delay); - wake_up_interruptible(&info->open_wait); - } - - info->flags &= ~(ASYNC_NORMAL_ACTIVE | ASYNC_CLOSING); -} - -static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count) -{ - int c, total = 0; - struct mxser_port *info = tty->driver_data; - unsigned long flags; - - if (!info->xmit_buf) - return 0; - - while (1) { - c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1, - SERIAL_XMIT_SIZE - info->xmit_head)); - if (c <= 0) - break; - - memcpy(info->xmit_buf + info->xmit_head, buf, c); - spin_lock_irqsave(&info->slock, flags); - info->xmit_head = (info->xmit_head + c) & - (SERIAL_XMIT_SIZE - 1); - info->xmit_cnt += c; - spin_unlock_irqrestore(&info->slock, flags); - - buf += c; - count -= c; - total += c; - } - - if (info->xmit_cnt && !tty->stopped) { - if (!tty->hw_stopped || - (info->type == PORT_16550A) || - (info->board->chip_flag)) { - spin_lock_irqsave(&info->slock, flags); - outb(info->IER & ~UART_IER_THRI, info->ioaddr + - UART_IER); - info->IER |= UART_IER_THRI; - outb(info->IER, info->ioaddr + UART_IER); - spin_unlock_irqrestore(&info->slock, flags); - } - } - return total; -} - -static void mxser_put_char(struct tty_struct *tty, unsigned char ch) -{ - struct mxser_port *info = tty->driver_data; - unsigned long flags; - - if (!info->xmit_buf) - return; - - if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1) - return; - - spin_lock_irqsave(&info->slock, flags); - info->xmit_buf[info->xmit_head++] = ch; - info->xmit_head &= SERIAL_XMIT_SIZE - 1; - info->xmit_cnt++; - spin_unlock_irqrestore(&info->slock, flags); - if (!tty->stopped) { - if (!tty->hw_stopped || - (info->type == PORT_16550A) || - info->board->chip_flag) { - spin_lock_irqsave(&info->slock, flags); - outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); - info->IER |= UART_IER_THRI; - outb(info->IER, info->ioaddr + UART_IER); - spin_unlock_irqrestore(&info->slock, flags); - } - } -} - - -static void mxser_flush_chars(struct tty_struct *tty) -{ - struct mxser_port *info = tty->driver_data; - unsigned long flags; - - if (info->xmit_cnt <= 0 || - tty->stopped || - !info->xmit_buf || - (tty->hw_stopped && - (info->type != PORT_16550A) && - (!info->board->chip_flag) - )) - return; - - spin_lock_irqsave(&info->slock, flags); - - outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); - info->IER |= UART_IER_THRI; - outb(info->IER, info->ioaddr + UART_IER); - - spin_unlock_irqrestore(&info->slock, flags); -} - -static int mxser_write_room(struct tty_struct *tty) -{ - struct mxser_port *info = tty->driver_data; - int ret; - - ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1; - if (ret < 0) - ret = 0; - return ret; -} - -static int mxser_chars_in_buffer(struct tty_struct *tty) -{ - struct mxser_port *info = tty->driver_data; - return info->xmit_cnt; -} - -static void mxser_flush_buffer(struct tty_struct *tty) -{ - struct mxser_port *info = tty->driver_data; - char fcr; - unsigned long flags; - - - spin_lock_irqsave(&info->slock, flags); - info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; - - fcr = inb(info->ioaddr + UART_FCR); - outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT), - info->ioaddr + UART_FCR); - outb(fcr, info->ioaddr + UART_FCR); - - spin_unlock_irqrestore(&info->slock, flags); - - tty_wakeup(tty); -} - -/* - * ------------------------------------------------------------ - * friends of mxser_ioctl() - * ------------------------------------------------------------ - */ -static int mxser_get_serial_info(struct mxser_port *info, - struct serial_struct __user *retinfo) -{ - struct serial_struct tmp; - - if (!retinfo) - return -EFAULT; - memset(&tmp, 0, sizeof(tmp)); - tmp.type = info->type; - tmp.line = info->tty->index; - tmp.port = info->ioaddr; - tmp.irq = info->board->irq; - tmp.flags = info->flags; - tmp.baud_base = info->baud_base; - tmp.close_delay = info->close_delay; - tmp.closing_wait = info->closing_wait; - tmp.custom_divisor = info->custom_divisor; - tmp.hub6 = 0; - if (copy_to_user(retinfo, &tmp, sizeof(*retinfo))) - return -EFAULT; - return 0; -} - -static int mxser_set_serial_info(struct mxser_port *info, - struct serial_struct __user *new_info) -{ - struct serial_struct new_serial; - unsigned long sl_flags; - unsigned int flags; - int retval = 0; - - if (!new_info || !info->ioaddr) - return -EFAULT; - if (copy_from_user(&new_serial, new_info, sizeof(new_serial))) - return -EFAULT; - - if ((new_serial.irq != info->board->irq) || - (new_serial.port != info->ioaddr) || - (new_serial.custom_divisor != info->custom_divisor) || - (new_serial.baud_base != info->baud_base)) - return -EPERM; - - flags = info->flags & ASYNC_SPD_MASK; - - if (!capable(CAP_SYS_ADMIN)) { - if ((new_serial.baud_base != info->baud_base) || - (new_serial.close_delay != info->close_delay) || - ((new_serial.flags & ~ASYNC_USR_MASK) != (info->flags & ~ASYNC_USR_MASK))) - return -EPERM; - info->flags = ((info->flags & ~ASYNC_USR_MASK) | - (new_serial.flags & ASYNC_USR_MASK)); - } else { - /* - * OK, past this point, all the error checking has been done. - * At this point, we start making changes..... - */ - info->flags = ((info->flags & ~ASYNC_FLAGS) | - (new_serial.flags & ASYNC_FLAGS)); - info->close_delay = new_serial.close_delay * HZ / 100; - info->closing_wait = new_serial.closing_wait * HZ / 100; - info->tty->low_latency = - (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; - info->tty->low_latency = 0; - } - - info->type = new_serial.type; - - process_txrx_fifo(info); - - if (info->flags & ASYNC_INITIALIZED) { - if (flags != (info->flags & ASYNC_SPD_MASK)) { - spin_lock_irqsave(&info->slock, sl_flags); - mxser_change_speed(info, NULL); - spin_unlock_irqrestore(&info->slock, sl_flags); - } - } else - retval = mxser_startup(info); - - return retval; -} - -/* - * mxser_get_lsr_info - get line status register info - * - * Purpose: Let user call ioctl() to get info when the UART physically - * is emptied. On bus types like RS485, the transmitter must - * release the bus after transmitting. This must be done when - * the transmit shift register is empty, not be done when the - * transmit holding register is empty. This functionality - * allows an RS485 driver to be written in user space. - */ -static int mxser_get_lsr_info(struct mxser_port *info, - unsigned int __user *value) -{ - unsigned char status; - unsigned int result; - unsigned long flags; - - spin_lock_irqsave(&info->slock, flags); - status = inb(info->ioaddr + UART_LSR); - spin_unlock_irqrestore(&info->slock, flags); - result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0); - return put_user(result, value); -} - -/* - * This routine sends a break character out the serial port. - */ -static void mxser_send_break(struct mxser_port *info, int duration) -{ - unsigned long flags; - - if (!info->ioaddr) - return; - set_current_state(TASK_INTERRUPTIBLE); - spin_lock_irqsave(&info->slock, flags); - outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC, - info->ioaddr + UART_LCR); - spin_unlock_irqrestore(&info->slock, flags); - schedule_timeout(duration); - spin_lock_irqsave(&info->slock, flags); - outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC, - info->ioaddr + UART_LCR); - spin_unlock_irqrestore(&info->slock, flags); -} - -static int mxser_tiocmget(struct tty_struct *tty, struct file *file) -{ - struct mxser_port *info = tty->driver_data; - unsigned char control, status; - unsigned long flags; - - - if (tty->index == MXSER_PORTS) - return -ENOIOCTLCMD; - if (test_bit(TTY_IO_ERROR, &tty->flags)) - return -EIO; - - control = info->MCR; - - spin_lock_irqsave(&info->slock, flags); - status = inb(info->ioaddr + UART_MSR); - if (status & UART_MSR_ANY_DELTA) - mxser_check_modem_status(info, status); - spin_unlock_irqrestore(&info->slock, flags); - return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) | - ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) | - ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) | - ((status & UART_MSR_RI) ? TIOCM_RNG : 0) | - ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) | - ((status & UART_MSR_CTS) ? TIOCM_CTS : 0); -} - -static int mxser_tiocmset(struct tty_struct *tty, struct file *file, - unsigned int set, unsigned int clear) -{ - struct mxser_port *info = tty->driver_data; - unsigned long flags; - - - if (tty->index == MXSER_PORTS) - return -ENOIOCTLCMD; - if (test_bit(TTY_IO_ERROR, &tty->flags)) - return -EIO; - - spin_lock_irqsave(&info->slock, flags); - - if (set & TIOCM_RTS) - info->MCR |= UART_MCR_RTS; - if (set & TIOCM_DTR) - info->MCR |= UART_MCR_DTR; - - if (clear & TIOCM_RTS) - info->MCR &= ~UART_MCR_RTS; - if (clear & TIOCM_DTR) - info->MCR &= ~UART_MCR_DTR; - - outb(info->MCR, info->ioaddr + UART_MCR); - spin_unlock_irqrestore(&info->slock, flags); - return 0; -} - -static int __init mxser_program_mode(int port) -{ - int id, i, j, n; - - outb(0, port); - outb(0, port); - outb(0, port); - (void)inb(port); - (void)inb(port); - outb(0, port); - (void)inb(port); - - id = inb(port + 1) & 0x1F; - if ((id != C168_ASIC_ID) && - (id != C104_ASIC_ID) && - (id != C102_ASIC_ID) && - (id != CI132_ASIC_ID) && - (id != CI134_ASIC_ID) && - (id != CI104J_ASIC_ID)) - return -1; - for (i = 0, j = 0; i < 4; i++) { - n = inb(port + 2); - if (n == 'M') { - j = 1; - } else if ((j == 1) && (n == 1)) { - j = 2; - break; - } else - j = 0; - } - if (j != 2) - id = -2; - return id; -} - -static void __init mxser_normal_mode(int port) -{ - int i, n; - - outb(0xA5, port + 1); - outb(0x80, port + 3); - outb(12, port + 0); /* 9600 bps */ - outb(0, port + 1); - outb(0x03, port + 3); /* 8 data bits */ - outb(0x13, port + 4); /* loop back mode */ - for (i = 0; i < 16; i++) { - n = inb(port + 5); - if ((n & 0x61) == 0x60) - break; - if ((n & 1) == 1) - (void)inb(port); - } - outb(0x00, port + 4); -} - -#define CHIP_SK 0x01 /* Serial Data Clock in Eprom */ -#define CHIP_DO 0x02 /* Serial Data Output in Eprom */ -#define CHIP_CS 0x04 /* Serial Chip Select in Eprom */ -#define CHIP_DI 0x08 /* Serial Data Input in Eprom */ -#define EN_CCMD 0x000 /* Chip's command register */ -#define EN0_RSARLO 0x008 /* Remote start address reg 0 */ -#define EN0_RSARHI 0x009 /* Remote start address reg 1 */ -#define EN0_RCNTLO 0x00A /* Remote byte count reg WR */ -#define EN0_RCNTHI 0x00B /* Remote byte count reg WR */ -#define EN0_DCFG 0x00E /* Data configuration reg WR */ -#define EN0_PORT 0x010 /* Rcv missed frame error counter RD */ -#define ENC_PAGE0 0x000 /* Select page 0 of chip registers */ -#define ENC_PAGE3 0x0C0 /* Select page 3 of chip registers */ -static int __init mxser_read_register(int port, unsigned short *regs) -{ - int i, k, value, id; - unsigned int j; - - id = mxser_program_mode(port); - if (id < 0) - return id; - for (i = 0; i < 14; i++) { - k = (i & 0x3F) | 0x180; - for (j = 0x100; j > 0; j >>= 1) { - outb(CHIP_CS, port); - if (k & j) { - outb(CHIP_CS | CHIP_DO, port); - outb(CHIP_CS | CHIP_DO | CHIP_SK, port); /* A? bit of read */ - } else { - outb(CHIP_CS, port); - outb(CHIP_CS | CHIP_SK, port); /* A? bit of read */ - } - } - (void)inb(port); - value = 0; - for (k = 0, j = 0x8000; k < 16; k++, j >>= 1) { - outb(CHIP_CS, port); - outb(CHIP_CS | CHIP_SK, port); - if (inb(port) & CHIP_DI) - value |= j; - } - regs[i] = value; - outb(0, port); - } - mxser_normal_mode(port); - return id; -} - -static int mxser_ioctl_special(unsigned int cmd, void __user *argp) -{ - struct mxser_port *port; - int result, status; - unsigned int i, j; - - switch (cmd) { - case MOXA_GET_CONF: -/* if (copy_to_user(argp, mxsercfg, - sizeof(struct mxser_hwconf) * 4)) - return -EFAULT; - return 0;*/ - return -ENXIO; - case MOXA_GET_MAJOR: - if (copy_to_user(argp, &ttymajor, sizeof(int))) - return -EFAULT; - return 0; - - case MOXA_GET_CUMAJOR: - if (copy_to_user(argp, &calloutmajor, sizeof(int))) - return -EFAULT; - return 0; - - case MOXA_CHKPORTENABLE: - result = 0; - - for (i = 0; i < MXSER_BOARDS; i++) - for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) - if (mxser_boards[i].ports[j].ioaddr) - result |= (1 << i); - - return put_user(result, (unsigned long __user *)argp); - case MOXA_GETDATACOUNT: - if (copy_to_user(argp, &mxvar_log, sizeof(mxvar_log))) - return -EFAULT; - return 0; - case MOXA_GETMSTATUS: - for (i = 0; i < MXSER_BOARDS; i++) - for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) { - port = &mxser_boards[i].ports[j]; - - GMStatus[i].ri = 0; - if (!port->ioaddr) { - GMStatus[i].dcd = 0; - GMStatus[i].dsr = 0; - GMStatus[i].cts = 0; - continue; - } - - if (!port->tty || !port->tty->termios) - GMStatus[i].cflag = - port->normal_termios.c_cflag; - else - GMStatus[i].cflag = - port->tty->termios->c_cflag; - - status = inb(port->ioaddr + UART_MSR); - if (status & 0x80 /*UART_MSR_DCD */ ) - GMStatus[i].dcd = 1; - else - GMStatus[i].dcd = 0; - - if (status & 0x20 /*UART_MSR_DSR */ ) - GMStatus[i].dsr = 1; - else - GMStatus[i].dsr = 0; - - - if (status & 0x10 /*UART_MSR_CTS */ ) - GMStatus[i].cts = 1; - else - GMStatus[i].cts = 0; - } - if (copy_to_user(argp, GMStatus, - sizeof(struct mxser_mstatus) * MXSER_PORTS)) - return -EFAULT; - return 0; - case MOXA_ASPP_MON_EXT: { - int p, shiftbit; - unsigned long opmode; - unsigned cflag, iflag; - - for (i = 0; i < MXSER_BOARDS; i++) - for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) { - port = &mxser_boards[i].ports[j]; - if (!port->ioaddr) - continue; - - status = mxser_get_msr(port->ioaddr, 0, i); - - if (status & UART_MSR_TERI) - port->icount.rng++; - if (status & UART_MSR_DDSR) - port->icount.dsr++; - if (status & UART_MSR_DDCD) - port->icount.dcd++; - if (status & UART_MSR_DCTS) - port->icount.cts++; - - port->mon_data.modem_status = status; - mon_data_ext.rx_cnt[i] = port->mon_data.rxcnt; - mon_data_ext.tx_cnt[i] = port->mon_data.txcnt; - mon_data_ext.up_rxcnt[i] = - port->mon_data.up_rxcnt; - mon_data_ext.up_txcnt[i] = - port->mon_data.up_txcnt; - mon_data_ext.modem_status[i] = - port->mon_data.modem_status; - mon_data_ext.baudrate[i] = port->realbaud; - - if (!port->tty || !port->tty->termios) { - cflag = port->normal_termios.c_cflag; - iflag = port->normal_termios.c_iflag; - } else { - cflag = port->tty->termios->c_cflag; - iflag = port->tty->termios->c_iflag; - } - - mon_data_ext.databits[i] = cflag & CSIZE; - - mon_data_ext.stopbits[i] = cflag & CSTOPB; - - mon_data_ext.parity[i] = - cflag & (PARENB | PARODD | CMSPAR); - - mon_data_ext.flowctrl[i] = 0x00; - - if (cflag & CRTSCTS) - mon_data_ext.flowctrl[i] |= 0x03; - - if (iflag & (IXON | IXOFF)) - mon_data_ext.flowctrl[i] |= 0x0C; - - if (port->type == PORT_16550A) - mon_data_ext.fifo[i] = 1; - else - mon_data_ext.fifo[i] = 0; - - p = i % 4; - shiftbit = p * 2; - opmode = inb(port->opmode_ioaddr) >> shiftbit; - opmode &= OP_MODE_MASK; - - mon_data_ext.iftype[i] = opmode; - - } - if (copy_to_user(argp, &mon_data_ext, - sizeof(mon_data_ext))) - return -EFAULT; - - return 0; - - } default: - return -ENOIOCTLCMD; - } - return 0; -} - -static int mxser_ioctl(struct tty_struct *tty, struct file *file, - unsigned int cmd, unsigned long arg) -{ - struct mxser_port *info = tty->driver_data; - struct async_icount cprev, cnow; /* kernel counter temps */ - struct serial_icounter_struct __user *p_cuser; - unsigned long templ; - unsigned long flags; - unsigned int i; - void __user *argp = (void __user *)arg; - int retval; - - if (tty->index == MXSER_PORTS) - return mxser_ioctl_special(cmd, argp); - - if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) { - int p; - unsigned long opmode; - static unsigned char ModeMask[] = { 0xfc, 0xf3, 0xcf, 0x3f }; - int shiftbit; - unsigned char val, mask; - - p = tty->index % 4; - if (cmd == MOXA_SET_OP_MODE) { - if (get_user(opmode, (int __user *) argp)) - return -EFAULT; - if (opmode != RS232_MODE && - opmode != RS485_2WIRE_MODE && - opmode != RS422_MODE && - opmode != RS485_4WIRE_MODE) - return -EFAULT; - mask = ModeMask[p]; - shiftbit = p * 2; - val = inb(info->opmode_ioaddr); - val &= mask; - val |= (opmode << shiftbit); - outb(val, info->opmode_ioaddr); - } else { - shiftbit = p * 2; - opmode = inb(info->opmode_ioaddr) >> shiftbit; - opmode &= OP_MODE_MASK; - if (copy_to_user(argp, &opmode, sizeof(int))) - return -EFAULT; - } - return 0; - } - - if (cmd == MOXA_SET_SPECIAL_BAUD_RATE) { - int speed; - - if (get_user(speed, (int __user *)argp)) - return -EFAULT; - if (speed <= 0 || speed > info->max_baud) - return -EFAULT; - if (!info->tty || !info->tty->termios || !info->ioaddr) - return 0; - info->tty->termios->c_cflag &= ~(CBAUD | CBAUDEX); - for (i = 0; i < BAUD_TABLE_NO; i++) - if (speed == mxvar_baud_table[i]) - break; - if (i == BAUD_TABLE_NO) { - info->tty->termios->c_cflag |= B_SPEC; - } else if (speed != 0) - info->tty->termios->c_cflag |= mxvar_baud_table1[i]; - - info->speed = speed; - spin_lock_irqsave(&info->slock, flags); - mxser_change_speed(info, NULL); - spin_unlock_irqrestore(&info->slock, flags); - - return 0; - } else if (cmd == MOXA_GET_SPECIAL_BAUD_RATE) { - if (copy_to_user(argp, &info->speed, sizeof(int))) - return -EFAULT; - return 0; - } - - if (cmd != TIOCGSERIAL && cmd != TIOCMIWAIT && cmd != TIOCGICOUNT && - test_bit(TTY_IO_ERROR, &tty->flags)) - return -EIO; - - switch (cmd) { - case TCSBRK: /* SVID version: non-zero arg --> no break */ - retval = tty_check_change(tty); - if (retval) - return retval; - tty_wait_until_sent(tty, 0); - if (!arg) - mxser_send_break(info, HZ / 4); /* 1/4 second */ - return 0; - case TCSBRKP: /* support for POSIX tcsendbreak() */ - retval = tty_check_change(tty); - if (retval) - return retval; - tty_wait_until_sent(tty, 0); - mxser_send_break(info, arg ? arg * (HZ / 10) : HZ / 4); - return 0; - case TIOCGSOFTCAR: - return put_user(C_CLOCAL(tty) ? 1 : 0, (unsigned long __user *)argp); - case TIOCSSOFTCAR: - if (get_user(templ, (unsigned long __user *) argp)) - return -EFAULT; - arg = templ; - tty->termios->c_cflag = ((tty->termios->c_cflag & ~CLOCAL) | (arg ? CLOCAL : 0)); - return 0; - case TIOCGSERIAL: - return mxser_get_serial_info(info, argp); - case TIOCSSERIAL: - return mxser_set_serial_info(info, argp); - case TIOCSERGETLSR: /* Get line status register */ - return mxser_get_lsr_info(info, argp); - /* - * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change - * - mask passed in arg for lines of interest - * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking) - * Caller should use TIOCGICOUNT to see which one it was - */ - case TIOCMIWAIT: - spin_lock_irqsave(&info->slock, flags); - cnow = info->icount; /* note the counters on entry */ - spin_unlock_irqrestore(&info->slock, flags); - - wait_event_interruptible(info->delta_msr_wait, ({ - cprev = cnow; - spin_lock_irqsave(&info->slock, flags); - cnow = info->icount; /* atomic copy */ - spin_unlock_irqrestore(&info->slock, flags); - - ((arg & TIOCM_RNG) && (cnow.rng != cprev.rng)) || - ((arg & TIOCM_DSR) && (cnow.dsr != cprev.dsr)) || - ((arg & TIOCM_CD) && (cnow.dcd != cprev.dcd)) || - ((arg & TIOCM_CTS) && (cnow.cts != cprev.cts)); - })); - break; - /* - * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) - * Return: write counters to the user passed counter struct - * NB: both 1->0 and 0->1 transitions are counted except for - * RI where only 0->1 is counted. - */ - case TIOCGICOUNT: - spin_lock_irqsave(&info->slock, flags); - cnow = info->icount; - spin_unlock_irqrestore(&info->slock, flags); - p_cuser = argp; - if (put_user(cnow.frame, &p_cuser->frame)) - return -EFAULT; - if (put_user(cnow.brk, &p_cuser->brk)) - return -EFAULT; - if (put_user(cnow.overrun, &p_cuser->overrun)) - return -EFAULT; - if (put_user(cnow.buf_overrun, &p_cuser->buf_overrun)) - return -EFAULT; - if (put_user(cnow.parity, &p_cuser->parity)) - return -EFAULT; - if (put_user(cnow.rx, &p_cuser->rx)) - return -EFAULT; - if (put_user(cnow.tx, &p_cuser->tx)) - return -EFAULT; - put_user(cnow.cts, &p_cuser->cts); - put_user(cnow.dsr, &p_cuser->dsr); - put_user(cnow.rng, &p_cuser->rng); - put_user(cnow.dcd, &p_cuser->dcd); - return 0; - case MOXA_HighSpeedOn: - return put_user(info->baud_base != 115200 ? 1 : 0, (int __user *)argp); - case MOXA_SDS_RSTICOUNTER: - info->mon_data.rxcnt = 0; - info->mon_data.txcnt = 0; - return 0; - case MOXA_ASPP_SETBAUD:{ - long baud; - if (get_user(baud, (long __user *)argp)) - return -EFAULT; - spin_lock_irqsave(&info->slock, flags); - mxser_set_baud(info, baud); - spin_unlock_irqrestore(&info->slock, flags); - return 0; - } - case MOXA_ASPP_GETBAUD: - if (copy_to_user(argp, &info->realbaud, sizeof(long))) - return -EFAULT; - - return 0; - - case MOXA_ASPP_OQUEUE:{ - int len, lsr; - - len = mxser_chars_in_buffer(tty); - - lsr = inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT; - - len += (lsr ? 0 : 1); - - if (copy_to_user(argp, &len, sizeof(int))) - return -EFAULT; - - return 0; - } - case MOXA_ASPP_MON: { - int mcr, status; - - status = mxser_get_msr(info->ioaddr, 1, tty->index); - mxser_check_modem_status(info, status); - - mcr = inb(info->ioaddr + UART_MCR); - if (mcr & MOXA_MUST_MCR_XON_FLAG) - info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFHOLD; - else - info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFHOLD; - - if (mcr & MOXA_MUST_MCR_TX_XON) - info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFXENT; - else - info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFXENT; - - if (info->tty->hw_stopped) - info->mon_data.hold_reason |= NPPI_NOTIFY_CTSHOLD; - else - info->mon_data.hold_reason &= ~NPPI_NOTIFY_CTSHOLD; - - if (copy_to_user(argp, &info->mon_data, - sizeof(struct mxser_mon))) - return -EFAULT; - - return 0; - } - case MOXA_ASPP_LSTATUS: { - if (copy_to_user(argp, &info->err_shadow, - sizeof(unsigned char))) - return -EFAULT; - - info->err_shadow = 0; - return 0; - } - case MOXA_SET_BAUD_METHOD: { - int method; - - if (get_user(method, (int __user *)argp)) - return -EFAULT; - mxser_set_baud_method[tty->index] = method; - if (copy_to_user(argp, &method, sizeof(int))) - return -EFAULT; - - return 0; - } - default: - return -ENOIOCTLCMD; - } - return 0; -} - -static void mxser_stoprx(struct tty_struct *tty) -{ - struct mxser_port *info = tty->driver_data; - - info->ldisc_stop_rx = 1; - if (I_IXOFF(tty)) { - if (info->board->chip_flag) { - info->IER &= ~MOXA_MUST_RECV_ISR; - outb(info->IER, info->ioaddr + UART_IER); - } else { - info->x_char = STOP_CHAR(tty); - outb(0, info->ioaddr + UART_IER); - info->IER |= UART_IER_THRI; - outb(info->IER, info->ioaddr + UART_IER); - } - } - - if (info->tty->termios->c_cflag & CRTSCTS) { - info->MCR &= ~UART_MCR_RTS; - outb(info->MCR, info->ioaddr + UART_MCR); - } -} - -/* - * This routine is called by the upper-layer tty layer to signal that - * incoming characters should be throttled. - */ -static void mxser_throttle(struct tty_struct *tty) -{ - mxser_stoprx(tty); -} - -static void mxser_unthrottle(struct tty_struct *tty) -{ - struct mxser_port *info = tty->driver_data; - - /* startrx */ - info->ldisc_stop_rx = 0; - if (I_IXOFF(tty)) { - if (info->x_char) - info->x_char = 0; - else { - if (info->board->chip_flag) { - info->IER |= MOXA_MUST_RECV_ISR; - outb(info->IER, info->ioaddr + UART_IER); - } else { - info->x_char = START_CHAR(tty); - outb(0, info->ioaddr + UART_IER); - info->IER |= UART_IER_THRI; - outb(info->IER, info->ioaddr + UART_IER); - } - } - } - - if (info->tty->termios->c_cflag & CRTSCTS) { - info->MCR |= UART_MCR_RTS; - outb(info->MCR, info->ioaddr + UART_MCR); - } -} - -/* - * mxser_stop() and mxser_start() - * - * This routines are called before setting or resetting tty->stopped. - * They enable or disable transmitter interrupts, as necessary. - */ -static void mxser_stop(struct tty_struct *tty) -{ - struct mxser_port *info = tty->driver_data; - unsigned long flags; - - spin_lock_irqsave(&info->slock, flags); - if (info->IER & UART_IER_THRI) { - info->IER &= ~UART_IER_THRI; - outb(info->IER, info->ioaddr + UART_IER); - } - spin_unlock_irqrestore(&info->slock, flags); -} - -static void mxser_start(struct tty_struct *tty) -{ - struct mxser_port *info = tty->driver_data; - unsigned long flags; - - spin_lock_irqsave(&info->slock, flags); - if (info->xmit_cnt && info->xmit_buf) { - outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); - info->IER |= UART_IER_THRI; - outb(info->IER, info->ioaddr + UART_IER); - } - spin_unlock_irqrestore(&info->slock, flags); -} - -static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios) -{ - struct mxser_port *info = tty->driver_data; - unsigned long flags; - - spin_lock_irqsave(&info->slock, flags); - mxser_change_speed(info, old_termios); - spin_unlock_irqrestore(&info->slock, flags); - - if ((old_termios->c_cflag & CRTSCTS) && - !(tty->termios->c_cflag & CRTSCTS)) { - tty->hw_stopped = 0; - mxser_start(tty); - } - - /* Handle sw stopped */ - if ((old_termios->c_iflag & IXON) && - !(tty->termios->c_iflag & IXON)) { - tty->stopped = 0; - - if (info->board->chip_flag) { - spin_lock_irqsave(&info->slock, flags); - DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr); - spin_unlock_irqrestore(&info->slock, flags); - } - - mxser_start(tty); - } -} - -/* - * mxser_wait_until_sent() --- wait until the transmitter is empty - */ -static void mxser_wait_until_sent(struct tty_struct *tty, int timeout) -{ - struct mxser_port *info = tty->driver_data; - unsigned long orig_jiffies, char_time; - int lsr; - - if (info->type == PORT_UNKNOWN) - return; - - if (info->xmit_fifo_size == 0) - return; /* Just in case.... */ - - orig_jiffies = jiffies; - /* - * Set the check interval to be 1/5 of the estimated time to - * send a single character, and make it at least 1. The check - * interval should also be less than the timeout. - * - * Note: we have to use pretty tight timings here to satisfy - * the NIST-PCTS. - */ - char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size; - char_time = char_time / 5; - if (char_time == 0) - char_time = 1; - if (timeout && timeout < char_time) - char_time = timeout; - /* - * If the transmitter hasn't cleared in twice the approximate - * amount of time to send the entire FIFO, it probably won't - * ever clear. This assumes the UART isn't doing flow - * control, which is currently the case. Hence, if it ever - * takes longer than info->timeout, this is probably due to a - * UART bug of some kind. So, we clamp the timeout parameter at - * 2*info->timeout. - */ - if (!timeout || timeout > 2 * info->timeout) - timeout = 2 * info->timeout; -#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT - printk(KERN_DEBUG "In rs_wait_until_sent(%d) check=%lu...", - timeout, char_time); - printk("jiff=%lu...", jiffies); -#endif - while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) { -#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT - printk("lsr = %d (jiff=%lu)...", lsr, jiffies); -#endif - schedule_timeout_interruptible(char_time); - if (signal_pending(current)) - break; - if (timeout && time_after(jiffies, orig_jiffies + timeout)) - break; - } - set_current_state(TASK_RUNNING); - -#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT - printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies); -#endif -} - -/* - * This routine is called by tty_hangup() when a hangup is signaled. - */ -static void mxser_hangup(struct tty_struct *tty) -{ - struct mxser_port *info = tty->driver_data; - - mxser_flush_buffer(tty); - mxser_shutdown(info); - info->event = 0; - info->count = 0; - info->flags &= ~ASYNC_NORMAL_ACTIVE; - info->tty = NULL; - wake_up_interruptible(&info->open_wait); -} - -/* - * mxser_rs_break() --- routine which turns the break handling on or off - */ -static void mxser_rs_break(struct tty_struct *tty, int break_state) -{ - struct mxser_port *info = tty->driver_data; - unsigned long flags; - - spin_lock_irqsave(&info->slock, flags); - if (break_state == -1) - outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC, - info->ioaddr + UART_LCR); - else - outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC, - info->ioaddr + UART_LCR); - spin_unlock_irqrestore(&info->slock, flags); -} - -static void mxser_receive_chars(struct mxser_port *port, int *status) -{ - struct tty_struct *tty = port->tty; - unsigned char ch, gdl; - int ignored = 0; - int cnt = 0; - int recv_room; - int max = 256; - - recv_room = tty->receive_room; - if ((recv_room == 0) && (!port->ldisc_stop_rx)) - mxser_stoprx(tty); - - if (port->board->chip_flag != MOXA_OTHER_UART) { - - if (*status & UART_LSR_SPECIAL) - goto intr_old; - if (port->board->chip_flag == MOXA_MUST_MU860_HWID && - (*status & MOXA_MUST_LSR_RERR)) - goto intr_old; - if (*status & MOXA_MUST_LSR_RERR) - goto intr_old; - - gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER); - - if (port->board->chip_flag == MOXA_MUST_MU150_HWID) - gdl &= MOXA_MUST_GDL_MASK; - if (gdl >= recv_room) { - if (!port->ldisc_stop_rx) - mxser_stoprx(tty); - } - while (gdl--) { - ch = inb(port->ioaddr + UART_RX); - tty_insert_flip_char(tty, ch, 0); - cnt++; - } - goto end_intr; - } -intr_old: - - do { - if (max-- < 0) - break; - - ch = inb(port->ioaddr + UART_RX); - if (port->board->chip_flag && (*status & UART_LSR_OE)) - outb(0x23, port->ioaddr + UART_FCR); - *status &= port->read_status_mask; - if (*status & port->ignore_status_mask) { - if (++ignored > 100) - break; - } else { - char flag = 0; - if (*status & UART_LSR_SPECIAL) { - if (*status & UART_LSR_BI) { - flag = TTY_BREAK; - port->icount.brk++; - - if (port->flags & ASYNC_SAK) - do_SAK(tty); - } else if (*status & UART_LSR_PE) { - flag = TTY_PARITY; - port->icount.parity++; - } else if (*status & UART_LSR_FE) { - flag = TTY_FRAME; - port->icount.frame++; - } else if (*status & UART_LSR_OE) { - flag = TTY_OVERRUN; - port->icount.overrun++; - } else - flag = TTY_BREAK; - } - tty_insert_flip_char(tty, ch, flag); - cnt++; - if (cnt >= recv_room) { - if (!port->ldisc_stop_rx) - mxser_stoprx(tty); - break; - } - - } - - if (port->board->chip_flag) - break; - - *status = inb(port->ioaddr + UART_LSR); - } while (*status & UART_LSR_DR); - -end_intr: - mxvar_log.rxcnt[port->tty->index] += cnt; - port->mon_data.rxcnt += cnt; - port->mon_data.up_rxcnt += cnt; - - /* - * We are called from an interrupt context with &port->slock - * being held. Drop it temporarily in order to prevent - * recursive locking. - */ - spin_unlock(&port->slock); - tty_flip_buffer_push(tty); - spin_lock(&port->slock); -} - -static void mxser_transmit_chars(struct mxser_port *port) -{ - int count, cnt; - - if (port->x_char) { - outb(port->x_char, port->ioaddr + UART_TX); - port->x_char = 0; - mxvar_log.txcnt[port->tty->index]++; - port->mon_data.txcnt++; - port->mon_data.up_txcnt++; - port->icount.tx++; - return; - } - - if (port->xmit_buf == 0) - return; - - if ((port->xmit_cnt <= 0) || port->tty->stopped || - (port->tty->hw_stopped && - (port->type != PORT_16550A) && - (!port->board->chip_flag))) { - port->IER &= ~UART_IER_THRI; - outb(port->IER, port->ioaddr + UART_IER); - return; - } - - cnt = port->xmit_cnt; - count = port->xmit_fifo_size; - do { - outb(port->xmit_buf[port->xmit_tail++], - port->ioaddr + UART_TX); - port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1); - if (--port->xmit_cnt <= 0) - break; - } while (--count > 0); - mxvar_log.txcnt[port->tty->index] += (cnt - port->xmit_cnt); - - port->mon_data.txcnt += (cnt - port->xmit_cnt); - port->mon_data.up_txcnt += (cnt - port->xmit_cnt); - port->icount.tx += (cnt - port->xmit_cnt); - - if (port->xmit_cnt < WAKEUP_CHARS) - tty_wakeup(port->tty); - - if (port->xmit_cnt <= 0) { - port->IER &= ~UART_IER_THRI; - outb(port->IER, port->ioaddr + UART_IER); - } -} - -/* - * This is the serial driver's generic interrupt routine - */ -static irqreturn_t mxser_interrupt(int irq, void *dev_id) -{ - int status, iir, i; - struct mxser_board *brd = NULL; - struct mxser_port *port; - int max, irqbits, bits, msr; - unsigned int int_cnt, pass_counter = 0; - int handled = IRQ_NONE; - - for (i = 0; i < MXSER_BOARDS; i++) - if (dev_id == &mxser_boards[i]) { - brd = dev_id; - break; - } - - if (i == MXSER_BOARDS) - goto irq_stop; - if (brd == NULL) - goto irq_stop; - max = brd->info->nports; - while (pass_counter++ < MXSER_ISR_PASS_LIMIT) { - irqbits = inb(brd->vector) & brd->vector_mask; - if (irqbits == brd->vector_mask) - break; - - handled = IRQ_HANDLED; - for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) { - if (irqbits == brd->vector_mask) - break; - if (bits & irqbits) - continue; - port = &brd->ports[i]; - - int_cnt = 0; - spin_lock(&port->slock); - do { - iir = inb(port->ioaddr + UART_IIR); - if (iir & UART_IIR_NO_INT) - break; - iir &= MOXA_MUST_IIR_MASK; - if (!port->tty || - (port->flags & ASYNC_CLOSING) || - !(port->flags & - ASYNC_INITIALIZED)) { - status = inb(port->ioaddr + UART_LSR); - outb(0x27, port->ioaddr + UART_FCR); - inb(port->ioaddr + UART_MSR); - break; - } - - status = inb(port->ioaddr + UART_LSR); - - if (status & UART_LSR_PE) - port->err_shadow |= NPPI_NOTIFY_PARITY; - if (status & UART_LSR_FE) - port->err_shadow |= NPPI_NOTIFY_FRAMING; - if (status & UART_LSR_OE) - port->err_shadow |= - NPPI_NOTIFY_HW_OVERRUN; - if (status & UART_LSR_BI) - port->err_shadow |= NPPI_NOTIFY_BREAK; - - if (port->board->chip_flag) { - if (iir == MOXA_MUST_IIR_GDA || - iir == MOXA_MUST_IIR_RDA || - iir == MOXA_MUST_IIR_RTO || - iir == MOXA_MUST_IIR_LSR) - mxser_receive_chars(port, - &status); - - } else { - status &= port->read_status_mask; - if (status & UART_LSR_DR) - mxser_receive_chars(port, - &status); - } - msr = inb(port->ioaddr + UART_MSR); - if (msr & UART_MSR_ANY_DELTA) - mxser_check_modem_status(port, msr); - - if (port->board->chip_flag) { - if (iir == 0x02 && (status & - UART_LSR_THRE)) - mxser_transmit_chars(port); - } else { - if (status & UART_LSR_THRE) - mxser_transmit_chars(port); - } - } while (int_cnt++ < MXSER_ISR_PASS_LIMIT); - spin_unlock(&port->slock); - } - } - -irq_stop: - return handled; -} - -static const struct tty_operations mxser_ops = { - .open = mxser_open, - .close = mxser_close, - .write = mxser_write, - .put_char = mxser_put_char, - .flush_chars = mxser_flush_chars, - .write_room = mxser_write_room, - .chars_in_buffer = mxser_chars_in_buffer, - .flush_buffer = mxser_flush_buffer, - .ioctl = mxser_ioctl, - .throttle = mxser_throttle, - .unthrottle = mxser_unthrottle, - .set_termios = mxser_set_termios, - .stop = mxser_stop, - .start = mxser_start, - .hangup = mxser_hangup, - .break_ctl = mxser_rs_break, - .wait_until_sent = mxser_wait_until_sent, - .tiocmget = mxser_tiocmget, - .tiocmset = mxser_tiocmset, -}; - -/* - * The MOXA Smartio/Industio serial driver boot-time initialization code! - */ - -static void mxser_release_res(struct mxser_board *brd, struct pci_dev *pdev, - unsigned int irq) -{ - if (irq) - free_irq(brd->irq, brd); - if (pdev != NULL) { /* PCI */ -#ifdef CONFIG_PCI - pci_release_region(pdev, 2); - pci_release_region(pdev, 3); -#endif - } else { - release_region(brd->ports[0].ioaddr, 8 * brd->info->nports); - release_region(brd->vector, 1); - } -} - -static int __devinit mxser_initbrd(struct mxser_board *brd, - struct pci_dev *pdev) -{ - struct mxser_port *info; - unsigned int i; - int retval; - - printk(KERN_INFO "max. baud rate = %d bps.\n", brd->ports[0].max_baud); - - for (i = 0; i < brd->info->nports; i++) { - info = &brd->ports[i]; - info->board = brd; - info->stop_rx = 0; - info->ldisc_stop_rx = 0; - - /* Enhance mode enabled here */ - if (brd->chip_flag != MOXA_OTHER_UART) - ENABLE_MOXA_MUST_ENCHANCE_MODE(info->ioaddr); - - info->flags = ASYNC_SHARE_IRQ; - info->type = brd->uart_type; - - process_txrx_fifo(info); - - info->custom_divisor = info->baud_base * 16; - info->close_delay = 5 * HZ / 10; - info->closing_wait = 30 * HZ; - info->normal_termios = mxvar_sdriver->init_termios; - init_waitqueue_head(&info->open_wait); - init_waitqueue_head(&info->delta_msr_wait); - info->speed = 9600; - memset(&info->mon_data, 0, sizeof(struct mxser_mon)); - info->err_shadow = 0; - spin_lock_init(&info->slock); - - /* before set INT ISR, disable all int */ - outb(inb(info->ioaddr + UART_IER) & 0xf0, - info->ioaddr + UART_IER); - } - - retval = request_irq(brd->irq, mxser_interrupt, IRQF_SHARED, "mxser", - brd); - if (retval) { - printk(KERN_ERR "Board %s: Request irq failed, IRQ (%d) may " - "conflict with another device.\n", - brd->info->name, brd->irq); - /* We hold resources, we need to release them. */ - mxser_release_res(brd, pdev, 0); - } - return retval; -} - -static int __init mxser_get_ISA_conf(int cap, struct mxser_board *brd) -{ - int id, i, bits; - unsigned short regs[16], irq; - unsigned char scratch, scratch2; - - brd->chip_flag = MOXA_OTHER_UART; - - id = mxser_read_register(cap, regs); - switch (id) { - case C168_ASIC_ID: - brd->info = &mxser_cards[0]; - break; - case C104_ASIC_ID: - brd->info = &mxser_cards[1]; - break; - case CI104J_ASIC_ID: - brd->info = &mxser_cards[2]; - break; - case C102_ASIC_ID: - brd->info = &mxser_cards[5]; - break; - case CI132_ASIC_ID: - brd->info = &mxser_cards[6]; - break; - case CI134_ASIC_ID: - brd->info = &mxser_cards[7]; - break; - default: - return 0; - } - - irq = 0; - /* some ISA cards have 2 ports, but we want to see them as 4-port (why?) - Flag-hack checks if configuration should be read as 2-port here. */ - if (brd->info->nports == 2 || (brd->info->flags & MXSER_HAS2)) { - irq = regs[9] & 0xF000; - irq = irq | (irq >> 4); - if (irq != (regs[9] & 0xFF00)) - return MXSER_ERR_IRQ_CONFLIT; - } else if (brd->info->nports == 4) { - irq = regs[9] & 0xF000; - irq = irq | (irq >> 4); - irq = irq | (irq >> 8); - if (irq != regs[9]) - return MXSER_ERR_IRQ_CONFLIT; - } else if (brd->info->nports == 8) { - irq = regs[9] & 0xF000; - irq = irq | (irq >> 4); - irq = irq | (irq >> 8); - if ((irq != regs[9]) || (irq != regs[10])) - return MXSER_ERR_IRQ_CONFLIT; - } - - if (!irq) - return MXSER_ERR_IRQ; - brd->irq = ((int)(irq & 0xF000) >> 12); - for (i = 0; i < 8; i++) - brd->ports[i].ioaddr = (int) regs[i + 1] & 0xFFF8; - if ((regs[12] & 0x80) == 0) - return MXSER_ERR_VECTOR; - brd->vector = (int)regs[11]; /* interrupt vector */ - if (id == 1) - brd->vector_mask = 0x00FF; - else - brd->vector_mask = 0x000F; - for (i = 7, bits = 0x0100; i >= 0; i--, bits <<= 1) { - if (regs[12] & bits) { - brd->ports[i].baud_base = 921600; - brd->ports[i].max_baud = 921600; - } else { - brd->ports[i].baud_base = 115200; - brd->ports[i].max_baud = 115200; - } - } - scratch2 = inb(cap + UART_LCR) & (~UART_LCR_DLAB); - outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR); - outb(0, cap + UART_EFR); /* EFR is the same as FCR */ - outb(scratch2, cap + UART_LCR); - outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR); - scratch = inb(cap + UART_IIR); - - if (scratch & 0xC0) - brd->uart_type = PORT_16550A; - else - brd->uart_type = PORT_16450; - if (!request_region(brd->ports[0].ioaddr, 8 * brd->info->nports, - "mxser(IO)")) - return MXSER_ERR_IOADDR; - if (!request_region(brd->vector, 1, "mxser(vector)")) { - release_region(brd->ports[0].ioaddr, 8 * brd->info->nports); - return MXSER_ERR_VECTOR; - } - return brd->info->nports; -} - -static int __devinit mxser_probe(struct pci_dev *pdev, - const struct pci_device_id *ent) -{ -#ifdef CONFIG_PCI - struct mxser_board *brd; - unsigned int i, j; - unsigned long ioaddress; - int retval = -EINVAL; - - for (i = 0; i < MXSER_BOARDS; i++) - if (mxser_boards[i].info == NULL) - break; - - if (i >= MXSER_BOARDS) { - printk(KERN_ERR "Too many Smartio/Industio family boards found " - "(maximum %d), board not configured\n", MXSER_BOARDS); - goto err; - } - - brd = &mxser_boards[i]; - brd->idx = i * MXSER_PORTS_PER_BOARD; - printk(KERN_INFO "Found MOXA %s board (BusNo=%d, DevNo=%d)\n", - mxser_cards[ent->driver_data].name, - pdev->bus->number, PCI_SLOT(pdev->devfn)); - - retval = pci_enable_device(pdev); - if (retval) { - printk(KERN_ERR "Moxa SmartI/O PCI enable fail !\n"); - goto err; - } - - /* io address */ - ioaddress = pci_resource_start(pdev, 2); - retval = pci_request_region(pdev, 2, "mxser(IO)"); - if (retval) - goto err; - - brd->info = &mxser_cards[ent->driver_data]; - for (i = 0; i < brd->info->nports; i++) - brd->ports[i].ioaddr = ioaddress + 8 * i; - - /* vector */ - ioaddress = pci_resource_start(pdev, 3); - retval = pci_request_region(pdev, 3, "mxser(vector)"); - if (retval) - goto err_relio; - brd->vector = ioaddress; - - /* irq */ - brd->irq = pdev->irq; - - brd->chip_flag = CheckIsMoxaMust(brd->ports[0].ioaddr); - brd->uart_type = PORT_16550A; - brd->vector_mask = 0; - - for (i = 0; i < brd->info->nports; i++) { - for (j = 0; j < UART_INFO_NUM; j++) { - if (Gpci_uart_info[j].type == brd->chip_flag) { - brd->ports[i].max_baud = - Gpci_uart_info[j].max_baud; - - /* exception....CP-102 */ - if (brd->info->flags & MXSER_HIGHBAUD) - brd->ports[i].max_baud = 921600; - break; - } - } - } - - if (brd->chip_flag == MOXA_MUST_MU860_HWID) { - for (i = 0; i < brd->info->nports; i++) { - if (i < 4) - brd->ports[i].opmode_ioaddr = ioaddress + 4; - else - brd->ports[i].opmode_ioaddr = ioaddress + 0x0c; - } - outb(0, ioaddress + 4); /* default set to RS232 mode */ - outb(0, ioaddress + 0x0c); /* default set to RS232 mode */ - } - - for (i = 0; i < brd->info->nports; i++) { - brd->vector_mask |= (1 << i); - brd->ports[i].baud_base = 921600; - } - - /* mxser_initbrd will hook ISR. */ - retval = mxser_initbrd(brd, pdev); - if (retval) - goto err_null; - - for (i = 0; i < brd->info->nports; i++) - tty_register_device(mxvar_sdriver, brd->idx + i, &pdev->dev); - - pci_set_drvdata(pdev, brd); - - return 0; -err_relio: - pci_release_region(pdev, 2); -err_null: - brd->info = NULL; -err: - return retval; -#else - return -ENODEV; -#endif -} - -static void __devexit mxser_remove(struct pci_dev *pdev) -{ - struct mxser_board *brd = pci_get_drvdata(pdev); - unsigned int i; - - for (i = 0; i < brd->info->nports; i++) - tty_unregister_device(mxvar_sdriver, brd->idx + i); - - mxser_release_res(brd, pdev, 1); - brd->info = NULL; -} - -static struct pci_driver mxser_driver = { - .name = "mxser", - .id_table = mxser_pcibrds, - .probe = mxser_probe, - .remove = __devexit_p(mxser_remove) -}; - -static int __init mxser_module_init(void) -{ - struct mxser_board *brd; - unsigned long cap; - unsigned int i, m, isaloop; - int retval, b; - - pr_debug("Loading module mxser ...\n"); - - mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1); - if (!mxvar_sdriver) - return -ENOMEM; - - printk(KERN_INFO "MOXA Smartio/Industio family driver version %s\n", - MXSER_VERSION); - - /* Initialize the tty_driver structure */ - mxvar_sdriver->owner = THIS_MODULE; - mxvar_sdriver->magic = TTY_DRIVER_MAGIC; - mxvar_sdriver->name = "ttyMI"; - mxvar_sdriver->major = ttymajor; - mxvar_sdriver->minor_start = 0; - mxvar_sdriver->num = MXSER_PORTS + 1; - mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL; - mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL; - mxvar_sdriver->init_termios = tty_std_termios; - mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL; - mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW|TTY_DRIVER_DYNAMIC_DEV; - tty_set_operations(mxvar_sdriver, &mxser_ops); - - retval = tty_register_driver(mxvar_sdriver); - if (retval) { - printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family " - "tty driver !\n"); - goto err_put; - } - - mxvar_diagflag = 0; - - m = 0; - /* Start finding ISA boards here */ - for (isaloop = 0; isaloop < 2; isaloop++) - for (b = 0; b < MXSER_BOARDS && m < MXSER_BOARDS; b++) { - if (!isaloop) - cap = mxserBoardCAP[b]; /* predefined */ - else - cap = ioaddr[b]; /* module param */ - - if (!cap) - continue; - - brd = &mxser_boards[m]; - retval = mxser_get_ISA_conf(cap, brd); - - if (retval != 0) - printk(KERN_INFO "Found MOXA %s board " - "(CAP=0x%x)\n", - brd->info->name, ioaddr[b]); - - if (retval <= 0) { - if (retval == MXSER_ERR_IRQ) - printk(KERN_ERR "Invalid interrupt " - "number, board not " - "configured\n"); - else if (retval == MXSER_ERR_IRQ_CONFLIT) - printk(KERN_ERR "Invalid interrupt " - "number, board not " - "configured\n"); - else if (retval == MXSER_ERR_VECTOR) - printk(KERN_ERR "Invalid interrupt " - "vector, board not " - "configured\n"); - else if (retval == MXSER_ERR_IOADDR) - printk(KERN_ERR "Invalid I/O address, " - "board not configured\n"); - - brd->info = NULL; - continue; - } - - /* mxser_initbrd will hook ISR. */ - if (mxser_initbrd(brd, NULL) < 0) { - brd->info = NULL; - continue; - } - - brd->idx = m * MXSER_PORTS_PER_BOARD; - for (i = 0; i < brd->info->nports; i++) - tty_register_device(mxvar_sdriver, brd->idx + i, - NULL); - - m++; - } - - retval = pci_register_driver(&mxser_driver); - if (retval) { - printk(KERN_ERR "Can't register pci driver\n"); - if (!m) { - retval = -ENODEV; - goto err_unr; - } /* else: we have some ISA cards under control */ - } - - pr_debug("Done.\n"); - - return 0; -err_unr: - tty_unregister_driver(mxvar_sdriver); -err_put: - put_tty_driver(mxvar_sdriver); - return retval; -} - -static void __exit mxser_module_exit(void) -{ - unsigned int i, j; - - pr_debug("Unloading module mxser ...\n"); - - pci_unregister_driver(&mxser_driver); - - for (i = 0; i < MXSER_BOARDS; i++) /* ISA remains */ - if (mxser_boards[i].info != NULL) - for (j = 0; j < mxser_boards[i].info->nports; j++) - tty_unregister_device(mxvar_sdriver, - mxser_boards[i].idx + j); - tty_unregister_driver(mxvar_sdriver); - put_tty_driver(mxvar_sdriver); - - for (i = 0; i < MXSER_BOARDS; i++) - if (mxser_boards[i].info != NULL) - mxser_release_res(&mxser_boards[i], NULL, 1); - - pr_debug("Done.\n"); -} - -module_init(mxser_module_init); -module_exit(mxser_module_exit); diff --git a/drivers/char/mxser_new.h b/drivers/char/mxser_new.h deleted file mode 100644 index d42f7766c65..00000000000 --- a/drivers/char/mxser_new.h +++ /dev/null @@ -1,293 +0,0 @@ -#ifndef _MXSER_H -#define _MXSER_H - -/* - * Semi-public control interfaces - */ - -/* - * MOXA ioctls - */ - -#define MOXA 0x400 -#define MOXA_GETDATACOUNT (MOXA + 23) -#define MOXA_GET_CONF (MOXA + 35) -#define MOXA_DIAGNOSE (MOXA + 50) -#define MOXA_CHKPORTENABLE (MOXA + 60) -#define MOXA_HighSpeedOn (MOXA + 61) -#define MOXA_GET_MAJOR (MOXA + 63) -#define MOXA_GET_CUMAJOR (MOXA + 64) -#define MOXA_GETMSTATUS (MOXA + 65) -#define MOXA_SET_OP_MODE (MOXA + 66) -#define MOXA_GET_OP_MODE (MOXA + 67) - -#define RS232_MODE 0 -#define RS485_2WIRE_MODE 1 -#define RS422_MODE 2 -#define RS485_4WIRE_MODE 3 -#define OP_MODE_MASK 3 - -#define MOXA_SDS_RSTICOUNTER (MOXA + 69) -#define MOXA_ASPP_OQUEUE (MOXA + 70) -#define MOXA_ASPP_SETBAUD (MOXA + 71) -#define MOXA_ASPP_GETBAUD (MOXA + 72) -#define MOXA_ASPP_MON (MOXA + 73) -#define MOXA_ASPP_LSTATUS (MOXA + 74) -#define MOXA_ASPP_MON_EXT (MOXA + 75) -#define MOXA_SET_BAUD_METHOD (MOXA + 76) -#define MOXA_SET_SPECIAL_BAUD_RATE (MOXA + 77) -#define MOXA_GET_SPECIAL_BAUD_RATE (MOXA + 78) - -/* --------------------------------------------------- */ - -#define NPPI_NOTIFY_PARITY 0x01 -#define NPPI_NOTIFY_FRAMING 0x02 -#define NPPI_NOTIFY_HW_OVERRUN 0x04 -#define NPPI_NOTIFY_SW_OVERRUN 0x08 -#define NPPI_NOTIFY_BREAK 0x10 - -#define NPPI_NOTIFY_CTSHOLD 0x01 /* Tx hold by CTS low */ -#define NPPI_NOTIFY_DSRHOLD 0x02 /* Tx hold by DSR low */ -#define NPPI_NOTIFY_XOFFHOLD 0x08 /* Tx hold by Xoff received */ -#define NPPI_NOTIFY_XOFFXENT 0x10 /* Xoff Sent */ - -/* follow just for Moxa Must chip define. */ -/* */ -/* when LCR register (offset 0x03) write following value, */ -/* the Must chip will enter enchance mode. And write value */ -/* on EFR (offset 0x02) bit 6,7 to change bank. */ -#define MOXA_MUST_ENTER_ENCHANCE 0xBF - -/* when enhance mode enable, access on general bank register */ -#define MOXA_MUST_GDL_REGISTER 0x07 -#define MOXA_MUST_GDL_MASK 0x7F -#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80 - -#define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */ -/* enchance register bank select and enchance mode setting register */ -/* when LCR register equal to 0xBF */ -#define MOXA_MUST_EFR_REGISTER 0x02 -/* enchance mode enable */ -#define MOXA_MUST_EFR_EFRB_ENABLE 0x10 -/* enchance reister bank set 0, 1, 2 */ -#define MOXA_MUST_EFR_BANK0 0x00 -#define MOXA_MUST_EFR_BANK1 0x40 -#define MOXA_MUST_EFR_BANK2 0x80 -#define MOXA_MUST_EFR_BANK3 0xC0 -#define MOXA_MUST_EFR_BANK_MASK 0xC0 - -/* set XON1 value register, when LCR=0xBF and change to bank0 */ -#define MOXA_MUST_XON1_REGISTER 0x04 - -/* set XON2 value register, when LCR=0xBF and change to bank0 */ -#define MOXA_MUST_XON2_REGISTER 0x05 - -/* set XOFF1 value register, when LCR=0xBF and change to bank0 */ -#define MOXA_MUST_XOFF1_REGISTER 0x06 - -/* set XOFF2 value register, when LCR=0xBF and change to bank0 */ -#define MOXA_MUST_XOFF2_REGISTER 0x07 - -#define MOXA_MUST_RBRTL_REGISTER 0x04 -#define MOXA_MUST_RBRTH_REGISTER 0x05 -#define MOXA_MUST_RBRTI_REGISTER 0x06 -#define MOXA_MUST_THRTL_REGISTER 0x07 -#define MOXA_MUST_ENUM_REGISTER 0x04 -#define MOXA_MUST_HWID_REGISTER 0x05 -#define MOXA_MUST_ECR_REGISTER 0x06 -#define MOXA_MUST_CSR_REGISTER 0x07 - -/* good data mode enable */ -#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 -/* only good data put into RxFIFO */ -#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 - -/* enable CTS interrupt */ -#define MOXA_MUST_IER_ECTSI 0x80 -/* enable RTS interrupt */ -#define MOXA_MUST_IER_ERTSI 0x40 -/* enable Xon/Xoff interrupt */ -#define MOXA_MUST_IER_XINT 0x20 -/* enable GDA interrupt */ -#define MOXA_MUST_IER_EGDAI 0x10 - -#define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI) - -/* GDA interrupt pending */ -#define MOXA_MUST_IIR_GDA 0x1C -#define MOXA_MUST_IIR_RDA 0x04 -#define MOXA_MUST_IIR_RTO 0x0C -#define MOXA_MUST_IIR_LSR 0x06 - -/* recieved Xon/Xoff or specical interrupt pending */ -#define MOXA_MUST_IIR_XSC 0x10 - -/* RTS/CTS change state interrupt pending */ -#define MOXA_MUST_IIR_RTSCTS 0x20 -#define MOXA_MUST_IIR_MASK 0x3E - -#define MOXA_MUST_MCR_XON_FLAG 0x40 -#define MOXA_MUST_MCR_XON_ANY 0x80 -#define MOXA_MUST_MCR_TX_XON 0x08 - -/* software flow control on chip mask value */ -#define MOXA_MUST_EFR_SF_MASK 0x0F -/* send Xon1/Xoff1 */ -#define MOXA_MUST_EFR_SF_TX1 0x08 -/* send Xon2/Xoff2 */ -#define MOXA_MUST_EFR_SF_TX2 0x04 -/* send Xon1,Xon2/Xoff1,Xoff2 */ -#define MOXA_MUST_EFR_SF_TX12 0x0C -/* don't send Xon/Xoff */ -#define MOXA_MUST_EFR_SF_TX_NO 0x00 -/* Tx software flow control mask */ -#define MOXA_MUST_EFR_SF_TX_MASK 0x0C -/* don't receive Xon/Xoff */ -#define MOXA_MUST_EFR_SF_RX_NO 0x00 -/* receive Xon1/Xoff1 */ -#define MOXA_MUST_EFR_SF_RX1 0x02 -/* receive Xon2/Xoff2 */ -#define MOXA_MUST_EFR_SF_RX2 0x01 -/* receive Xon1,Xon2/Xoff1,Xoff2 */ -#define MOXA_MUST_EFR_SF_RX12 0x03 -/* Rx software flow control mask */ -#define MOXA_MUST_EFR_SF_RX_MASK 0x03 - -#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr |= MOXA_MUST_EFR_EFRB_ENABLE; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} while (0) - -#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} while (0) - -#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) do { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ - __efr |= MOXA_MUST_EFR_BANK0; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} while (0) - -#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) do { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ - __efr |= MOXA_MUST_EFR_BANK0; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} while (0) - -#define SET_MOXA_MUST_FIFO_VALUE(info) do { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((info)->ioaddr+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (info)->ioaddr+UART_LCR);\ - __efr = inb((info)->ioaddr+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ - __efr |= MOXA_MUST_EFR_BANK1; \ - outb(__efr, (info)->ioaddr+MOXA_MUST_EFR_REGISTER); \ - outb((u8)((info)->rx_high_water), (info)->ioaddr+ \ - MOXA_MUST_RBRTH_REGISTER); \ - outb((u8)((info)->rx_trigger), (info)->ioaddr+ \ - MOXA_MUST_RBRTI_REGISTER); \ - outb((u8)((info)->rx_low_water), (info)->ioaddr+ \ - MOXA_MUST_RBRTL_REGISTER); \ - outb(__oldlcr, (info)->ioaddr+UART_LCR); \ -} while (0) - -#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) do { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ - __efr |= MOXA_MUST_EFR_BANK2; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} while (0) - -#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) do { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ - __efr |= MOXA_MUST_EFR_BANK2; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} while (0) - -#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) do { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_SF_MASK; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} while (0) - -#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \ - __efr |= MOXA_MUST_EFR_SF_TX1; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} while (0) - -#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} while (0) - -#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \ - __efr |= MOXA_MUST_EFR_SF_RX1; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} while (0) - -#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \ - u8 __oldlcr, __efr; \ - __oldlcr = inb((baseio)+UART_LCR); \ - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ - __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \ - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ - outb(__oldlcr, (baseio)+UART_LCR); \ -} while (0) - -#endif diff --git a/drivers/char/riscom8.c b/drivers/char/riscom8.c index d130b87d8ed..8fc4fe4e38f 100644 --- a/drivers/char/riscom8.c +++ b/drivers/char/riscom8.c @@ -78,8 +78,6 @@ ASYNC_SPD_HI | ASYNC_SPEED_VHI | ASYNC_SESSION_LOCKOUT | \ ASYNC_PGRP_LOCKOUT | ASYNC_CALLOUT_NOHUP) -#define RS_EVENT_WRITE_WAKEUP 0 - static struct tty_driver *riscom_driver; static DEFINE_SPINLOCK(riscom_lock); @@ -314,12 +312,6 @@ out_release: * */ -static inline void rc_mark_event(struct riscom_port * port, int event) -{ - set_bit(event, &port->event); - schedule_work(&port->tqueue); -} - static inline struct riscom_port * rc_get_port(struct riscom_board const * bp, unsigned char const * what) { @@ -486,7 +478,7 @@ static inline void rc_transmit(struct riscom_board const * bp) rc_out(bp, CD180_IER, port->IER); } if (port->xmit_cnt <= port->wakeup_chars) - rc_mark_event(port, RS_EVENT_WRITE_WAKEUP); + tty_wakeup(tty); } static inline void rc_check_modem(struct riscom_board const * bp) @@ -505,7 +497,7 @@ static inline void rc_check_modem(struct riscom_board const * bp) if (rc_in(bp, CD180_MSVR) & MSVR_CD) wake_up_interruptible(&port->open_wait); else - schedule_work(&port->tqueue_hangup); + tty_hangup(tty); } #ifdef RISCOM_BRAIN_DAMAGED_CTS @@ -514,7 +506,7 @@ static inline void rc_check_modem(struct riscom_board const * bp) tty->hw_stopped = 0; port->IER |= IER_TXRDY; if (port->xmit_cnt <= port->wakeup_chars) - rc_mark_event(port, RS_EVENT_WRITE_WAKEUP); + tty_wakeup(tty); } else { tty->hw_stopped = 1; port->IER &= ~IER_TXRDY; @@ -526,7 +518,7 @@ static inline void rc_check_modem(struct riscom_board const * bp) tty->hw_stopped = 0; port->IER |= IER_TXRDY; if (port->xmit_cnt <= port->wakeup_chars) - rc_mark_event(port, RS_EVENT_WRITE_WAKEUP); + tty_wakeup(tty); } else { tty->hw_stopped = 1; port->IER &= ~IER_TXRDY; @@ -1091,7 +1083,6 @@ static void rc_close(struct tty_struct * tty, struct file * filp) tty_ldisc_flush(tty); tty->closing = 0; - port->event = 0; port->tty = NULL; if (port->blocked_open) { if (port->close_delay) { @@ -1526,25 +1517,6 @@ static void rc_start(struct tty_struct * tty) spin_unlock_irqrestore(&riscom_lock, flags); } -/* - * This routine is called from the work queue when the interrupt - * routine has signalled that a hangup has occurred. The path of - * hangup processing is: - * - * serial interrupt routine -> (workqueue) -> - * do_rc_hangup() -> tty->hangup() -> rc_hangup() - * - */ -static void do_rc_hangup(struct work_struct *ugly_api) -{ - struct riscom_port *port = container_of(ugly_api, struct riscom_port, tqueue_hangup); - struct tty_struct *tty; - - tty = port->tty; - if (tty) - tty_hangup(tty); /* FIXME: module removal race still here */ -} - static void rc_hangup(struct tty_struct * tty) { struct riscom_port *port = (struct riscom_port *)tty->driver_data; @@ -1556,7 +1528,6 @@ static void rc_hangup(struct tty_struct * tty) bp = port_Board(port); rc_shutdown_port(bp, port); - port->event = 0; port->count = 0; port->flags &= ~ASYNC_NORMAL_ACTIVE; port->tty = NULL; @@ -1586,18 +1557,6 @@ static void rc_set_termios(struct tty_struct * tty, struct ktermios * old_termio } } -static void do_softint(struct work_struct *ugly_api) -{ - struct riscom_port *port = container_of(ugly_api, struct riscom_port, tqueue); - struct tty_struct *tty; - - if(!(tty = port->tty)) - return; - - if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &port->event)) - tty_wakeup(tty); -} - static const struct tty_operations riscom_ops = { .open = rc_open, .close = rc_close, @@ -1618,7 +1577,7 @@ static const struct tty_operations riscom_ops = { .tiocmset = rc_tiocmset, }; -static inline int rc_init_drivers(void) +static int __init rc_init_drivers(void) { int error; int i; @@ -1650,8 +1609,6 @@ static inline int rc_init_drivers(void) memset(rc_port, 0, sizeof(rc_port)); for (i = 0; i < RC_NPORT * RC_NBOARD; i++) { rc_port[i].magic = RISCOM8_MAGIC; - INIT_WORK(&rc_port[i].tqueue, do_softint); - INIT_WORK(&rc_port[i].tqueue_hangup, do_rc_hangup); rc_port[i].close_delay = 50 * HZ/100; rc_port[i].closing_wait = 3000 * HZ/100; init_waitqueue_head(&rc_port[i].open_wait); diff --git a/drivers/char/riscom8.h b/drivers/char/riscom8.h index 9cc1313d5e6..cdfdf439447 100644 --- a/drivers/char/riscom8.h +++ b/drivers/char/riscom8.h @@ -71,7 +71,6 @@ struct riscom_port { struct tty_struct * tty; int count; int blocked_open; - unsigned long event; /* long req'd for set_bit --RR */ int timeout; int close_delay; unsigned char * xmit_buf; @@ -81,8 +80,6 @@ struct riscom_port { int xmit_cnt; wait_queue_head_t open_wait; wait_queue_head_t close_wait; - struct work_struct tqueue; - struct work_struct tqueue_hangup; short wakeup_chars; short break_length; unsigned short closing_wait; diff --git a/drivers/char/rocket.c b/drivers/char/rocket.c index d83419c3857..68c289fe2dc 100644 --- a/drivers/char/rocket.c +++ b/drivers/char/rocket.c @@ -40,12 +40,6 @@ */ /****** Defines ******/ -#ifdef PCI_NUM_RESOURCES -#define PCI_BASE_ADDRESS(dev, r) ((dev)->resource[r].start) -#else -#define PCI_BASE_ADDRESS(dev, r) ((dev)->base_address[r]) -#endif - #define ROCKET_PARANOIA_CHECK #define ROCKET_DISABLE_SIMUSAGE @@ -305,8 +299,8 @@ static inline int rocket_paranoia_check(struct r_port *info, if (!info) return 1; if (info->magic != RPORT_MAGIC) { - printk(KERN_INFO "Warning: bad magic number for rocketport struct in %s\n", - routine); + printk(KERN_WARNING "Warning: bad magic number for rocketport " + "struct in %s\n", routine); return 1; } #endif @@ -328,7 +322,7 @@ static void rp_do_receive(struct r_port *info, ToRecv = sGetRxCnt(cp); #ifdef ROCKET_DEBUG_INTR - printk(KERN_INFO "rp_do_receive(%d)...", ToRecv); + printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv); #endif if (ToRecv == 0) return; @@ -341,7 +335,7 @@ static void rp_do_receive(struct r_port *info, if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) { if (!(ChanStatus & STATMODE)) { #ifdef ROCKET_DEBUG_RECEIVE - printk(KERN_INFO "Entering STATMODE..."); + printk(KERN_INFO "Entering STATMODE...\n"); #endif ChanStatus |= STATMODE; sEnRxStatusMode(cp); @@ -355,15 +349,15 @@ static void rp_do_receive(struct r_port *info, */ if (ChanStatus & STATMODE) { #ifdef ROCKET_DEBUG_RECEIVE - printk(KERN_INFO "Ignore %x, read %x...", info->ignore_status_mask, - info->read_status_mask); + printk(KERN_INFO "Ignore %x, read %x...\n", + info->ignore_status_mask, info->read_status_mask); #endif while (ToRecv) { char flag; CharNStat = sInW(sGetTxRxDataIO(cp)); #ifdef ROCKET_DEBUG_RECEIVE - printk(KERN_INFO "%x...", CharNStat); + printk(KERN_INFO "%x...\n", CharNStat); #endif if (CharNStat & STMBREAKH) CharNStat &= ~(STMFRAMEH | STMPARITYH); @@ -435,12 +429,13 @@ static void rp_do_transmit(struct r_port *info) unsigned long flags; #ifdef ROCKET_DEBUG_INTR - printk(KERN_INFO "rp_do_transmit "); + printk(KERN_DEBUG "%s\n", __func__); #endif if (!info) return; if (!info->tty) { - printk(KERN_INFO "rp: WARNING rp_do_transmit called with info->tty==NULL\n"); + printk(KERN_WARNING "rp: WARNING %s called with " + "info->tty==NULL\n", __func__); clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]); return; } @@ -464,7 +459,7 @@ static void rp_do_transmit(struct r_port *info) info->xmit_cnt -= c; info->xmit_fifo_room -= c; #ifdef ROCKET_DEBUG_INTR - printk(KERN_INFO "tx %d chars...", c); + printk(KERN_INFO "tx %d chars...\n", c); #endif } @@ -481,7 +476,7 @@ static void rp_do_transmit(struct r_port *info) spin_unlock_irqrestore(&info->slock, flags); #ifdef ROCKET_DEBUG_INTR - printk(KERN_INFO "(%d,%d,%d,%d)...", info->xmit_cnt, info->xmit_head, + printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head, info->xmit_tail, info->xmit_fifo_room); #endif } @@ -501,11 +496,13 @@ static void rp_handle_port(struct r_port *info) return; if ((info->flags & ROCKET_INITIALIZED) == 0) { - printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->flags & NOT_INIT\n"); + printk(KERN_WARNING "rp: WARNING: rp_handle_port called with " + "info->flags & NOT_INIT\n"); return; } if (!info->tty) { - printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->tty==NULL\n"); + printk(KERN_WARNING "rp: WARNING: rp_handle_port called with " + "info->tty==NULL\n"); return; } cp = &info->channel; @@ -513,7 +510,7 @@ static void rp_handle_port(struct r_port *info) IntMask = sGetChanIntID(cp) & info->intmask; #ifdef ROCKET_DEBUG_INTR - printk(KERN_INFO "rp_interrupt %02x...", IntMask); + printk(KERN_INFO "rp_interrupt %02x...\n", IntMask); #endif ChanStatus = sGetChanStatus(cp); if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */ @@ -521,7 +518,7 @@ static void rp_handle_port(struct r_port *info) } if (IntMask & DELTA_CD) { /* CD change */ #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP)) - printk(KERN_INFO "ttyR%d CD now %s...", info->line, + printk(KERN_INFO "ttyR%d CD now %s...\n", info->line, (ChanStatus & CD_ACT) ? "on" : "off"); #endif if (!(ChanStatus & CD_ACT) && info->cd_status) { @@ -638,7 +635,8 @@ static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev) /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */ info = kzalloc(sizeof (struct r_port), GFP_KERNEL); if (!info) { - printk(KERN_INFO "Couldn't allocate info struct for line #%d\n", line); + printk(KERN_ERR "Couldn't allocate info struct for line #%d\n", + line); return; } @@ -668,7 +666,8 @@ static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev) info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR; if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) { - printk(KERN_INFO "RocketPort sInitChan(%d, %d, %d) failed!\n", board, aiop, chan); + printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n", + board, aiop, chan); kfree(info); return; } @@ -976,7 +975,7 @@ static int rp_open(struct tty_struct *tty, struct file *filp) CHANNEL_t *cp; unsigned long page; - line = TTY_GET_LINE(tty); + line = tty->index; if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL)) return -ENXIO; @@ -1007,7 +1006,8 @@ static int rp_open(struct tty_struct *tty, struct file *filp) atomic_inc(&rp_num_ports_open); #ifdef ROCKET_DEBUG_OPEN - printk(KERN_INFO "rocket mod++ = %d...", atomic_read(&rp_num_ports_open)); + printk(KERN_INFO "rocket mod++ = %d...\n", + atomic_read(&rp_num_ports_open)); #endif } #ifdef ROCKET_DEBUG_OPEN @@ -1103,13 +1103,13 @@ static void rp_close(struct tty_struct *tty, struct file *filp) * one, we've got real problems, since it means the * serial port won't be shutdown. */ - printk(KERN_INFO "rp_close: bad serial port count; tty->count is 1, " - "info->count is %d\n", info->count); + printk(KERN_WARNING "rp_close: bad serial port count; " + "tty->count is 1, info->count is %d\n", info->count); info->count = 1; } if (--info->count < 0) { - printk(KERN_INFO "rp_close: bad serial port count for ttyR%d: %d\n", - info->line, info->count); + printk(KERN_WARNING "rp_close: bad serial port count for " + "ttyR%d: %d\n", info->line, info->count); info->count = 0; } if (info->count) { @@ -1160,8 +1160,7 @@ static void rp_close(struct tty_struct *tty, struct file *filp) if (C_HUPCL(tty)) sClrDTR(cp); - if (TTY_DRIVER_FLUSH_BUFFER_EXISTS(tty)) - TTY_DRIVER_FLUSH_BUFFER(tty); + rp_flush_buffer(tty); tty_ldisc_flush(tty); @@ -1184,7 +1183,8 @@ static void rp_close(struct tty_struct *tty, struct file *filp) atomic_dec(&rp_num_ports_open); #ifdef ROCKET_DEBUG_OPEN - printk(KERN_INFO "rocket mod-- = %d...", atomic_read(&rp_num_ports_open)); + printk(KERN_INFO "rocket mod-- = %d...\n", + atomic_read(&rp_num_ports_open)); printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line); #endif @@ -1569,9 +1569,9 @@ static void rp_wait_until_sent(struct tty_struct *tty, int timeout) orig_jiffies = jiffies; #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT - printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...", timeout, + printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout, jiffies); - printk(KERN_INFO "cps=%d...", info->cps); + printk(KERN_INFO "cps=%d...\n", info->cps); #endif while (1) { txcnt = sGetTxCnt(cp); @@ -1592,7 +1592,8 @@ static void rp_wait_until_sent(struct tty_struct *tty, int timeout) if (check_time == 0) check_time = 1; #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT - printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...", txcnt, jiffies, check_time); + printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt, + jiffies, check_time); #endif msleep_interruptible(jiffies_to_msecs(check_time)); if (signal_pending(current)) @@ -1616,7 +1617,7 @@ static void rp_hangup(struct tty_struct *tty) return; #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP)) - printk(KERN_INFO "rp_hangup of ttyR%d...", info->line); + printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line); #endif rp_flush_buffer(tty); if (info->flags & ROCKET_CLOSING) @@ -1664,7 +1665,7 @@ static void rp_put_char(struct tty_struct *tty, unsigned char ch) mutex_lock(&info->write_mtx); #ifdef ROCKET_DEBUG_WRITE - printk(KERN_INFO "rp_put_char %c...", ch); + printk(KERN_INFO "rp_put_char %c...\n", ch); #endif spin_lock_irqsave(&info->slock, flags); @@ -1709,7 +1710,7 @@ static int rp_write(struct tty_struct *tty, return -ERESTARTSYS; #ifdef ROCKET_DEBUG_WRITE - printk(KERN_INFO "rp_write %d chars...", count); + printk(KERN_INFO "rp_write %d chars...\n", count); #endif cp = &info->channel; @@ -1798,7 +1799,7 @@ static int rp_write_room(struct tty_struct *tty) if (ret < 0) ret = 0; #ifdef ROCKET_DEBUG_WRITE - printk(KERN_INFO "rp_write_room returns %d...", ret); + printk(KERN_INFO "rp_write_room returns %d...\n", ret); #endif return ret; } @@ -1818,7 +1819,7 @@ static int rp_chars_in_buffer(struct tty_struct *tty) cp = &info->channel; #ifdef ROCKET_DEBUG_WRITE - printk(KERN_INFO "rp_chars_in_buffer returns %d...", info->xmit_cnt); + printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt); #endif return info->xmit_cnt; } @@ -2161,14 +2162,11 @@ static __init int register_PCI(int i, struct pci_dev *dev) for (aiop = 0; aiop < max_num_aiops; aiop++) ctlp->AiopNumChan[aiop] = ports_per_aiop; - printk("Comtrol PCI controller #%d ID 0x%x found in bus:slot:fn %s at address %04lx, " - "%d AIOP(s) (%s)\n", i, dev->device, pci_name(dev), - rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString); - printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n", - rocketModel[i].modelString, - rocketModel[i].startingPortNumber, - rocketModel[i].startingPortNumber + - rocketModel[i].numPorts - 1); + dev_info(&dev->dev, "comtrol PCI controller #%d found at " + "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n", + i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString, + rocketModel[i].startingPortNumber, + rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1); if (num_aiops <= 0) { rcktpt_io_addr[i] = 0; @@ -2191,10 +2189,10 @@ static __init int register_PCI(int i, struct pci_dev *dev) num_chan = ports_per_aiop; for (chan = 0; chan < num_chan; chan++) sPCIModemReset(ctlp, chan, 1); - mdelay(500); + msleep(500); for (chan = 0; chan < num_chan; chan++) sPCIModemReset(ctlp, chan, 0); - mdelay(500); + msleep(500); rmSpeakerReset(ctlp, rocketModel[i].model); } return (1); @@ -2240,7 +2238,9 @@ static int __init init_ISA(int i) /* Reserve the IO region */ if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) { - printk(KERN_INFO "Unable to reserve IO region for configured ISA RocketPort at address 0x%lx, board not installed...\n", rcktpt_io_addr[i]); + printk(KERN_ERR "Unable to reserve IO region for configured " + "ISA RocketPort at address 0x%lx, board not " + "installed...\n", rcktpt_io_addr[i]); rcktpt_io_addr[i] = 0; return (0); } @@ -2309,10 +2309,10 @@ static int __init init_ISA(int i) total_num_chan = num_chan; for (chan = 0; chan < num_chan; chan++) sModemReset(ctlp, chan, 1); - mdelay(500); + msleep(500); for (chan = 0; chan < num_chan; chan++) sModemReset(ctlp, chan, 0); - mdelay(500); + msleep(500); strcpy(rocketModel[i].modelString, "RocketModem ISA"); } else { strcpy(rocketModel[i].modelString, "RocketPort ISA"); @@ -2480,7 +2480,7 @@ static void rp_cleanup_module(void) retval = tty_unregister_driver(rocket_driver); if (retval) - printk(KERN_INFO "Error %d while trying to unregister " + printk(KERN_ERR "Error %d while trying to unregister " "rocketport driver\n", -retval); for (i = 0; i < MAX_RP_PORTS; i++) diff --git a/drivers/char/rocket_int.h b/drivers/char/rocket_int.h index 55b8f2d71a9..f3a75791b81 100644 --- a/drivers/char/rocket_int.h +++ b/drivers/char/rocket_int.h @@ -42,7 +42,7 @@ typedef unsigned int DWordIO_t; static inline void sOutB(unsigned short port, unsigned char value) { #ifdef ROCKET_DEBUG_IO - printk("sOutB(%x, %x)...", port, value); + printk(KERN_DEBUG "sOutB(%x, %x)...\n", port, value); #endif outb_p(value, port); } @@ -50,7 +50,7 @@ static inline void sOutB(unsigned short port, unsigned char value) static inline void sOutW(unsigned short port, unsigned short value) { #ifdef ROCKET_DEBUG_IO - printk("sOutW(%x, %x)...", port, value); + printk(KERN_DEBUG "sOutW(%x, %x)...\n", port, value); #endif outw_p(value, port); } @@ -58,7 +58,7 @@ static inline void sOutW(unsigned short port, unsigned short value) static inline void sOutDW(unsigned short port, unsigned long value) { #ifdef ROCKET_DEBUG_IO - printk("sOutDW(%x, %lx)...", port, value); + printk(KERN_DEBUG "sOutDW(%x, %lx)...\n", port, value); #endif outl_p(cpu_to_le32(value), port); } @@ -105,12 +105,6 @@ static inline unsigned short sInW(unsigned short port) #define AIOPID_NULL -1 /* no AIOP or channel exists */ #define AIOPID_0001 0x0001 /* AIOP release 1 */ -#define NULLDEV -1 /* identifies non-existant device */ -#define NULLCTL -1 /* identifies non-existant controller */ -#define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */ -#define NULLAIOP -1 /* identifies non-existant AIOP */ -#define NULLCHAN -1 /* identifies non-existant channel */ - /************************************************************************ Global Register Offsets - Direct Access - Fixed values ************************************************************************/ @@ -1187,9 +1181,6 @@ struct r_port { #define ROCKET_CLOSING 0x40000000 /* Serial port is closing */ #define ROCKET_NORMAL_ACTIVE 0x20000000 /* Normal port is active */ -/* tty subtypes */ -#define SERIAL_TYPE_NORMAL 1 - /* * Assigned major numbers for the Comtrol Rocketport */ @@ -1240,12 +1231,3 @@ struct r_port { /* Compact PCI device */ #define PCI_DEVICE_ID_CRP16INTF 0x0903 /* Rocketport Compact PCI 16 port w/external I/F */ -#define TTY_GET_LINE(t) t->index -#define TTY_DRIVER_MINOR_START(t) t->driver->minor_start -#define TTY_DRIVER_SUBTYPE(t) t->driver->subtype -#define TTY_DRIVER_NAME(t) t->driver->name -#define TTY_DRIVER_NAME_BASE(t) t->driver->name_base -#define TTY_DRIVER_FLUSH_BUFFER_EXISTS(t) t->driver->flush_buffer -#define TTY_DRIVER_FLUSH_BUFFER(t) t->driver->flush_buffer(t) - - diff --git a/drivers/char/serial167.c b/drivers/char/serial167.c index f1497cecffd..df8cd0ca97e 100644 --- a/drivers/char/serial167.c +++ b/drivers/char/serial167.c @@ -90,8 +90,6 @@ #define STD_COM_FLAGS (0) -#define SERIAL_TYPE_NORMAL 1 - static struct tty_driver *cy_serial_driver; extern int serial_console; static struct cyclades_port *serial_console_info = NULL; @@ -359,18 +357,6 @@ static void cy_start(struct tty_struct *tty) local_irq_restore(flags); } /* cy_start */ -/* - * This routine is used by the interrupt handler to schedule - * processing in the software interrupt portion of the driver - * (also known as the "bottom half"). This can be called any - * number of times for any channel without harm. - */ -static inline void cy_sched_event(struct cyclades_port *info, int event) -{ - info->event |= 1 << event; /* remember what kind of event and who */ - schedule_work(&info->tqueue); -} /* cy_sched_event */ - /* The real interrupt service routines are called whenever the card wants its hand held--chars received, out buffer empty, modem change, etc. @@ -485,10 +471,12 @@ static irqreturn_t cd2401_modem_interrupt(int irq, void *dev_id) && (info->flags & ASYNC_CHECK_CD)) { if (mdm_status & CyDCD) { /* CP('!'); */ - cy_sched_event(info, Cy_EVENT_OPEN_WAKEUP); + wake_up_interruptible(&info->open_wait); } else { /* CP('@'); */ - cy_sched_event(info, Cy_EVENT_HANGUP); + tty_hangup(info->tty); + wake_up_interruptible(&info->open_wait); + info->flags &= ~ASYNC_NORMAL_ACTIVE; } } if ((mdm_change & CyCTS) @@ -498,8 +486,7 @@ static irqreturn_t cd2401_modem_interrupt(int irq, void *dev_id) /* !!! cy_start isn't used because... */ info->tty->stopped = 0; base_addr[CyIER] |= CyTxMpty; - cy_sched_event(info, - Cy_EVENT_WRITE_WAKEUP); + tty_wakeup(info->tty); } } else { if (!(mdm_status & CyCTS)) { @@ -545,9 +532,6 @@ static irqreturn_t cd2401_tx_interrupt(int irq, void *dev_id) info->last_active = jiffies; if (info->tty == 0) { base_addr[CyIER] &= ~(CyTxMpty | CyTxRdy); - if (info->xmit_cnt < WAKEUP_CHARS) { - cy_sched_event(info, Cy_EVENT_WRITE_WAKEUP); - } base_addr[CyTEOIR] = CyNOTRANS; return IRQ_HANDLED; } @@ -629,9 +613,9 @@ static irqreturn_t cd2401_tx_interrupt(int irq, void *dev_id) } } - if (info->xmit_cnt < WAKEUP_CHARS) { - cy_sched_event(info, Cy_EVENT_WRITE_WAKEUP); - } + if (info->xmit_cnt < WAKEUP_CHARS) + tty_wakeup(info->tty); + base_addr[CyTEOIR] = (char_count != saved_cnt) ? 0 : CyNOTRANS; return IRQ_HANDLED; } /* cy_tx_interrupt */ @@ -692,49 +676,6 @@ static irqreturn_t cd2401_rx_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } /* cy_rx_interrupt */ -/* - * This routine is used to handle the "bottom half" processing for the - * serial driver, known also the "software interrupt" processing. - * This processing is done at the kernel interrupt level, after the - * cy#/_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This - * is where time-consuming activities which can not be done in the - * interrupt driver proper are done; the interrupt driver schedules - * them using cy_sched_event(), and they get done here. - * - * This is done through one level of indirection--the task queue. - * When a hardware interrupt service routine wants service by the - * driver's bottom half, it enqueues the appropriate tq_struct (one - * per port) to the keventd work queue and sets a request flag - * that the work queue be processed. - * - * Although this may seem unwieldy, it gives the system a way to - * pass an argument (in this case the pointer to the cyclades_port - * structure) to the bottom half of the driver. Previous kernels - * had to poll every port to see if that port needed servicing. - */ -static void do_softint(struct work_struct *ugly_api) -{ - struct cyclades_port *info = - container_of(ugly_api, struct cyclades_port, tqueue); - struct tty_struct *tty; - - tty = info->tty; - if (!tty) - return; - - if (test_and_clear_bit(Cy_EVENT_HANGUP, &info->event)) { - tty_hangup(info->tty); - wake_up_interruptible(&info->open_wait); - info->flags &= ~ASYNC_NORMAL_ACTIVE; - } - if (test_and_clear_bit(Cy_EVENT_OPEN_WAKEUP, &info->event)) { - wake_up_interruptible(&info->open_wait); - } - if (test_and_clear_bit(Cy_EVENT_WRITE_WAKEUP, &info->event)) { - tty_wakeup(tty); - } -} /* do_softint */ - /* This is called whenever a port becomes active; interrupts are enabled and DTR & RTS are turned on. */ @@ -1745,7 +1686,6 @@ static void cy_close(struct tty_struct *tty, struct file *filp) if (tty->driver->flush_buffer) tty->driver->flush_buffer(tty); tty_ldisc_flush(tty); - info->event = 0; info->tty = NULL; if (info->blocked_open) { if (info->close_delay) { @@ -2236,7 +2176,6 @@ static int __init serial167_init(void) info->rco = baud_co[DefSpeed] >> 5; /* Rx CO */ info->close_delay = 0; info->x_char = 0; - info->event = 0; info->count = 0; #ifdef SERIAL_DEBUG_COUNT printk("cyc: %d: setting count to 0\n", @@ -2245,7 +2184,6 @@ static int __init serial167_init(void) info->blocked_open = 0; info->default_threshold = 0; info->default_timeout = 0; - INIT_WORK(&info->tqueue, do_softint); init_waitqueue_head(&info->open_wait); init_waitqueue_head(&info->close_wait); /* info->session */ diff --git a/drivers/char/specialix.c b/drivers/char/specialix.c index 455855631ae..c0e08c7bca2 100644 --- a/drivers/char/specialix.c +++ b/drivers/char/specialix.c @@ -178,9 +178,6 @@ static int sx_poll = HZ; ASYNC_SPD_HI | ASYNC_SPEED_VHI | ASYNC_SESSION_LOCKOUT | \ ASYNC_PGRP_LOCKOUT | ASYNC_CALLOUT_NOHUP) -#undef RS_EVENT_WRITE_WAKEUP -#define RS_EVENT_WRITE_WAKEUP 0 - static struct tty_driver *specialix_driver; static struct specialix_board sx_board[SX_NBOARD] = { @@ -602,17 +599,6 @@ static int sx_probe(struct specialix_board *bp) * Interrupt processing routines. * */ -static inline void sx_mark_event(struct specialix_port * port, int event) -{ - func_enter(); - - set_bit(event, &port->event); - schedule_work(&port->tqueue); - - func_exit(); -} - - static inline struct specialix_port * sx_get_port(struct specialix_board * bp, unsigned char const * what) { @@ -809,7 +795,7 @@ static inline void sx_transmit(struct specialix_board * bp) sx_out(bp, CD186x_IER, port->IER); } if (port->xmit_cnt <= port->wakeup_chars) - sx_mark_event(port, RS_EVENT_WRITE_WAKEUP); + tty_wakeup(tty); func_exit(); } @@ -839,7 +825,7 @@ static inline void sx_check_modem(struct specialix_board * bp) wake_up_interruptible(&port->open_wait); } else { dprintk (SX_DEBUG_SIGNALS, "Sending HUP.\n"); - schedule_work(&port->tqueue_hangup); + tty_hangup(tty); } } @@ -849,7 +835,7 @@ static inline void sx_check_modem(struct specialix_board * bp) tty->hw_stopped = 0; port->IER |= IER_TXRDY; if (port->xmit_cnt <= port->wakeup_chars) - sx_mark_event(port, RS_EVENT_WRITE_WAKEUP); + tty_wakeup(tty); } else { tty->hw_stopped = 1; port->IER &= ~IER_TXRDY; @@ -861,7 +847,7 @@ static inline void sx_check_modem(struct specialix_board * bp) tty->hw_stopped = 0; port->IER |= IER_TXRDY; if (port->xmit_cnt <= port->wakeup_chars) - sx_mark_event(port, RS_EVENT_WRITE_WAKEUP); + tty_wakeup(tty); } else { tty->hw_stopped = 1; port->IER &= ~IER_TXRDY; @@ -1618,7 +1604,6 @@ static void sx_close(struct tty_struct * tty, struct file * filp) tty_ldisc_flush(tty); spin_lock_irqsave(&port->lock, flags); tty->closing = 0; - port->event = 0; port->tty = NULL; spin_unlock_irqrestore(&port->lock, flags); if (port->blocked_open) { @@ -2235,32 +2220,6 @@ static void sx_start(struct tty_struct * tty) func_exit(); } - -/* - * This routine is called from the work-queue when the interrupt - * routine has signalled that a hangup has occurred. The path of - * hangup processing is: - * - * serial interrupt routine -> (workqueue) -> - * do_sx_hangup() -> tty->hangup() -> sx_hangup() - * - */ -static void do_sx_hangup(struct work_struct *work) -{ - struct specialix_port *port = - container_of(work, struct specialix_port, tqueue_hangup); - struct tty_struct *tty; - - func_enter(); - - tty = port->tty; - if (tty) - tty_hangup(tty); /* FIXME: module removal race here */ - - func_exit(); -} - - static void sx_hangup(struct tty_struct * tty) { struct specialix_port *port = (struct specialix_port *)tty->driver_data; @@ -2278,7 +2237,6 @@ static void sx_hangup(struct tty_struct * tty) sx_shutdown_port(bp, port); spin_lock_irqsave(&port->lock, flags); - port->event = 0; bp->count -= port->count; if (bp->count < 0) { printk(KERN_ERR "sx%d: sx_hangup: bad board count: %d port: %d\n", @@ -2320,26 +2278,6 @@ static void sx_set_termios(struct tty_struct * tty, struct ktermios * old_termio } } - -static void do_softint(struct work_struct *work) -{ - struct specialix_port *port = - container_of(work, struct specialix_port, tqueue); - struct tty_struct *tty; - - func_enter(); - - if(!(tty = port->tty)) { - func_exit(); - return; - } - - if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &port->event)) - tty_wakeup(tty); - - func_exit(); -} - static const struct tty_operations sx_ops = { .open = sx_open, .close = sx_close, @@ -2397,8 +2335,6 @@ static int sx_init_drivers(void) memset(sx_port, 0, sizeof(sx_port)); for (i = 0; i < SX_NPORT * SX_NBOARD; i++) { sx_port[i].magic = SPECIALIX_MAGIC; - INIT_WORK(&sx_port[i].tqueue, do_softint); - INIT_WORK(&sx_port[i].tqueue_hangup, do_sx_hangup); sx_port[i].close_delay = 50 * HZ/100; sx_port[i].closing_wait = 3000 * HZ/100; init_waitqueue_head(&sx_port[i].open_wait); diff --git a/drivers/char/specialix_io8.h b/drivers/char/specialix_io8.h index 895bd90de36..3f2f85bdf51 100644 --- a/drivers/char/specialix_io8.h +++ b/drivers/char/specialix_io8.h @@ -112,7 +112,6 @@ struct specialix_port { struct tty_struct * tty; int count; int blocked_open; - ulong event; int timeout; int close_delay; unsigned char * xmit_buf; @@ -122,8 +121,6 @@ struct specialix_port { int xmit_cnt; wait_queue_head_t open_wait; wait_queue_head_t close_wait; - struct work_struct tqueue; - struct work_struct tqueue_hangup; short wakeup_chars; short break_length; unsigned short closing_wait; diff --git a/drivers/char/stallion.c b/drivers/char/stallion.c index 45758d5b56e..feac54e32a1 100644 --- a/drivers/char/stallion.c +++ b/drivers/char/stallion.c @@ -145,8 +145,7 @@ static struct stlbrd *stl_brds[STL_MAXBRDS]; */ #define ASYI_TXBUSY 1 #define ASYI_TXLOW 2 -#define ASYI_DCDCHANGE 3 -#define ASYI_TXFLOWED 4 +#define ASYI_TXFLOWED 3 /* * Define an array of board names as printable strings. Handy for @@ -610,6 +609,23 @@ static const struct file_operations stl_fsiomem = { static struct class *stallion_class; +static void stl_cd_change(struct stlport *portp) +{ + unsigned int oldsigs = portp->sigs; + + if (!portp->tty) + return; + + portp->sigs = stl_getsignals(portp); + + if ((portp->sigs & TIOCM_CD) && ((oldsigs & TIOCM_CD) == 0)) + wake_up_interruptible(&portp->open_wait); + + if ((oldsigs & TIOCM_CD) && ((portp->sigs & TIOCM_CD) == 0)) + if (portp->flags & ASYNC_CHECK_CD) + tty_hangup(portp->tty); +} + /* * Check for any arguments passed in on the module load command line. */ @@ -1771,41 +1787,6 @@ static int stl_echpci64intr(struct stlbrd *brdp) /*****************************************************************************/ /* - * Service an off-level request for some channel. - */ -static void stl_offintr(struct work_struct *work) -{ - struct stlport *portp = container_of(work, struct stlport, tqueue); - struct tty_struct *tty; - unsigned int oldsigs; - - pr_debug("stl_offintr(portp=%p)\n", portp); - - if (portp == NULL) - return; - - tty = portp->tty; - if (tty == NULL) - return; - - if (test_bit(ASYI_TXLOW, &portp->istate)) - tty_wakeup(tty); - - if (test_bit(ASYI_DCDCHANGE, &portp->istate)) { - clear_bit(ASYI_DCDCHANGE, &portp->istate); - oldsigs = portp->sigs; - portp->sigs = stl_getsignals(portp); - if ((portp->sigs & TIOCM_CD) && ((oldsigs & TIOCM_CD) == 0)) - wake_up_interruptible(&portp->open_wait); - if ((oldsigs & TIOCM_CD) && ((portp->sigs & TIOCM_CD) == 0)) - if (portp->flags & ASYNC_CHECK_CD) - tty_hangup(tty); /* FIXME: module removal race here - AKPM */ - } -} - -/*****************************************************************************/ - -/* * Initialize all the ports on a panel. */ @@ -1840,7 +1821,6 @@ static int __devinit stl_initports(struct stlbrd *brdp, struct stlpanel *panelp) portp->baud_base = STL_BAUDBASE; portp->close_delay = STL_CLOSEDELAY; portp->closing_wait = 30 * HZ; - INIT_WORK(&portp->tqueue, stl_offintr); init_waitqueue_head(&portp->open_wait); init_waitqueue_head(&portp->close_wait); portp->stats.brd = portp->brdnr; @@ -3530,7 +3510,8 @@ static void stl_cd1400txisr(struct stlpanel *panelp, int ioaddr) if ((len == 0) || ((len < STL_TXBUFLOW) && (test_bit(ASYI_TXLOW, &portp->istate) == 0))) { set_bit(ASYI_TXLOW, &portp->istate); - schedule_work(&portp->tqueue); + if (portp->tty) + tty_wakeup(portp->tty); } if (len == 0) { @@ -3546,7 +3527,8 @@ static void stl_cd1400txisr(struct stlpanel *panelp, int ioaddr) } else { len = min(len, CD1400_TXFIFOSIZE); portp->stats.txtotal += len; - stlen = min(len, ((portp->tx.buf + STL_TXBUFSIZE) - tail)); + stlen = min_t(unsigned int, len, + (portp->tx.buf + STL_TXBUFSIZE) - tail); outb((TDR + portp->uartaddr), ioaddr); outsb((ioaddr + EREG_DATA), tail, stlen); len -= stlen; @@ -3599,7 +3581,7 @@ static void stl_cd1400rxisr(struct stlpanel *panelp, int ioaddr) outb((RDCR + portp->uartaddr), ioaddr); len = inb(ioaddr + EREG_DATA); if (tty == NULL || (buflen = tty_buffer_request_room(tty, len)) == 0) { - len = min(len, sizeof(stl_unwanted)); + len = min_t(unsigned int, len, sizeof(stl_unwanted)); outb((RDSR + portp->uartaddr), ioaddr); insb((ioaddr + EREG_DATA), &stl_unwanted[0], len); portp->stats.rxlost += len; @@ -3692,8 +3674,7 @@ static void stl_cd1400mdmisr(struct stlpanel *panelp, int ioaddr) outb((MISR + portp->uartaddr), ioaddr); misr = inb(ioaddr + EREG_DATA); if (misr & MISR_DCD) { - set_bit(ASYI_DCDCHANGE, &portp->istate); - schedule_work(&portp->tqueue); + stl_cd_change(portp); portp->stats.modem++; } @@ -4447,7 +4428,8 @@ static void stl_sc26198txisr(struct stlport *portp) if ((len == 0) || ((len < STL_TXBUFLOW) && (test_bit(ASYI_TXLOW, &portp->istate) == 0))) { set_bit(ASYI_TXLOW, &portp->istate); - schedule_work(&portp->tqueue); + if (portp->tty) + tty_wakeup(portp->tty); } if (len == 0) { @@ -4465,7 +4447,8 @@ static void stl_sc26198txisr(struct stlport *portp) } else { len = min(len, SC26198_TXFIFOSIZE); portp->stats.txtotal += len; - stlen = min(len, ((portp->tx.buf + STL_TXBUFSIZE) - tail)); + stlen = min_t(unsigned int, len, + (portp->tx.buf + STL_TXBUFSIZE) - tail); outb(GTXFIFO, (ioaddr + XP_ADDR)); outsb((ioaddr + XP_DATA), tail, stlen); len -= stlen; @@ -4506,7 +4489,7 @@ static void stl_sc26198rxisr(struct stlport *portp, unsigned int iack) if ((iack & IVR_TYPEMASK) == IVR_RXDATA) { if (tty == NULL || (buflen = tty_buffer_request_room(tty, len)) == 0) { - len = min(len, sizeof(stl_unwanted)); + len = min_t(unsigned int, len, sizeof(stl_unwanted)); outb(GRXFIFO, (ioaddr + XP_ADDR)); insb((ioaddr + XP_DATA), &stl_unwanted[0], len); portp->stats.rxlost += len; @@ -4647,8 +4630,7 @@ static void stl_sc26198otherisr(struct stlport *portp, unsigned int iack) case CIR_SUBCOS: ipr = stl_sc26198getreg(portp, IPR); if (ipr & IPR_DCDCHANGE) { - set_bit(ASYI_DCDCHANGE, &portp->istate); - schedule_work(&portp->tqueue); + stl_cd_change(portp); portp->stats.modem++; } break; diff --git a/drivers/char/sx.h b/drivers/char/sx.h index 70d9783c732..87c2defdead 100644 --- a/drivers/char/sx.h +++ b/drivers/char/sx.h @@ -88,8 +88,6 @@ struct vpd_prom { #define IS_CF_BOARD(board) (board->flags & (SX_CFISA_BOARD | SX_CFPCI_BOARD)) -#define SERIAL_TYPE_NORMAL 1 - /* The SI processor clock is required to calculate the cc_int_count register value for the SI cards. */ #define SI_PROCESSOR_CLOCK 25000000 diff --git a/drivers/char/xilinx_hwicap/Makefile b/drivers/char/xilinx_hwicap/Makefile new file mode 100644 index 00000000000..5491cbc42f4 --- /dev/null +++ b/drivers/char/xilinx_hwicap/Makefile @@ -0,0 +1,7 @@ +# +# Makefile for the Xilinx OPB hwicap driver +# + +obj-$(CONFIG_XILINX_HWICAP) += xilinx_hwicap_m.o + +xilinx_hwicap_m-y := xilinx_hwicap.o fifo_icap.o buffer_icap.o diff --git a/drivers/char/xilinx_hwicap/buffer_icap.c b/drivers/char/xilinx_hwicap/buffer_icap.c new file mode 100644 index 00000000000..dfea2bde162 --- /dev/null +++ b/drivers/char/xilinx_hwicap/buffer_icap.c @@ -0,0 +1,380 @@ +/***************************************************************************** + * + * Author: Xilinx, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" + * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND + * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, + * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, + * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION + * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, + * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE + * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY + * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE + * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR + * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF + * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. + * + * Xilinx products are not intended for use in life support appliances, + * devices, or systems. Use in such applications is expressly prohibited. + * + * (c) Copyright 2003-2008 Xilinx Inc. + * All rights reserved. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + *****************************************************************************/ + +#include "buffer_icap.h" + +/* Indicates how many bytes will fit in a buffer. (1 BRAM) */ +#define XHI_MAX_BUFFER_BYTES 2048 +#define XHI_MAX_BUFFER_INTS (XHI_MAX_BUFFER_BYTES >> 2) + +/* File access and error constants */ +#define XHI_DEVICE_READ_ERROR -1 +#define XHI_DEVICE_WRITE_ERROR -2 +#define XHI_BUFFER_OVERFLOW_ERROR -3 + +#define XHI_DEVICE_READ 0x1 +#define XHI_DEVICE_WRITE 0x0 + +/* Constants for checking transfer status */ +#define XHI_CYCLE_DONE 0 +#define XHI_CYCLE_EXECUTING 1 + +/* buffer_icap register offsets */ + +/* Size of transfer, read & write */ +#define XHI_SIZE_REG_OFFSET 0x800L +/* offset into bram, read & write */ +#define XHI_BRAM_OFFSET_REG_OFFSET 0x804L +/* Read not Configure, direction of transfer. Write only */ +#define XHI_RNC_REG_OFFSET 0x808L +/* Indicates transfer complete. Read only */ +#define XHI_STATUS_REG_OFFSET 0x80CL + +/* Constants for setting the RNC register */ +#define XHI_CONFIGURE 0x0UL +#define XHI_READBACK 0x1UL + +/* Constants for the Done register */ +#define XHI_NOT_FINISHED 0x0UL +#define XHI_FINISHED 0x1UL + +#define XHI_BUFFER_START 0 + +/** + * buffer_icap_get_status: Get the contents of the status register. + * @parameter base_address: is the base address of the device + * + * The status register contains the ICAP status and the done bit. + * + * D8 - cfgerr + * D7 - dalign + * D6 - rip + * D5 - in_abort_l + * D4 - Always 1 + * D3 - Always 1 + * D2 - Always 1 + * D1 - Always 1 + * D0 - Done bit + **/ +static inline u32 buffer_icap_get_status(void __iomem *base_address) +{ + return in_be32(base_address + XHI_STATUS_REG_OFFSET); +} + +/** + * buffer_icap_get_bram: Reads data from the storage buffer bram. + * @parameter base_address: contains the base address of the component. + * @parameter offset: The word offset from which the data should be read. + * + * A bram is used as a configuration memory cache. One frame of data can + * be stored in this "storage buffer". + **/ +static inline u32 buffer_icap_get_bram(void __iomem *base_address, + u32 offset) +{ + return in_be32(base_address + (offset << 2)); +} + +/** + * buffer_icap_busy: Return true if the icap device is busy + * @parameter base_address: is the base address of the device + * + * The queries the low order bit of the status register, which + * indicates whether the current configuration or readback operation + * has completed. + **/ +static inline bool buffer_icap_busy(void __iomem *base_address) +{ + return (buffer_icap_get_status(base_address) & 1) == XHI_NOT_FINISHED; +} + +/** + * buffer_icap_busy: Return true if the icap device is not busy + * @parameter base_address: is the base address of the device + * + * The queries the low order bit of the status register, which + * indicates whether the current configuration or readback operation + * has completed. + **/ +static inline bool buffer_icap_done(void __iomem *base_address) +{ + return (buffer_icap_get_status(base_address) & 1) == XHI_FINISHED; +} + +/** + * buffer_icap_set_size: Set the size register. + * @parameter base_address: is the base address of the device + * @parameter data: The size in bytes. + * + * The size register holds the number of 8 bit bytes to transfer between + * bram and the icap (or icap to bram). + **/ +static inline void buffer_icap_set_size(void __iomem *base_address, + u32 data) +{ + out_be32(base_address + XHI_SIZE_REG_OFFSET, data); +} + +/** + * buffer_icap_mSetoffsetReg: Set the bram offset register. + * @parameter base_address: contains the base address of the device. + * @parameter data: is the value to be written to the data register. + * + * The bram offset register holds the starting bram address to transfer + * data from during configuration or write data to during readback. + **/ +static inline void buffer_icap_set_offset(void __iomem *base_address, + u32 data) +{ + out_be32(base_address + XHI_BRAM_OFFSET_REG_OFFSET, data); +} + +/** + * buffer_icap_set_rnc: Set the RNC (Readback not Configure) register. + * @parameter base_address: contains the base address of the device. + * @parameter data: is the value to be written to the data register. + * + * The RNC register determines the direction of the data transfer. It + * controls whether a configuration or readback take place. Writing to + * this register initiates the transfer. A value of 1 initiates a + * readback while writing a value of 0 initiates a configuration. + **/ +static inline void buffer_icap_set_rnc(void __iomem *base_address, + u32 data) +{ + out_be32(base_address + XHI_RNC_REG_OFFSET, data); +} + +/** + * buffer_icap_set_bram: Write data to the storage buffer bram. + * @parameter base_address: contains the base address of the component. + * @parameter offset: The word offset at which the data should be written. + * @parameter data: The value to be written to the bram offset. + * + * A bram is used as a configuration memory cache. One frame of data can + * be stored in this "storage buffer". + **/ +static inline void buffer_icap_set_bram(void __iomem *base_address, + u32 offset, u32 data) +{ + out_be32(base_address + (offset << 2), data); +} + +/** + * buffer_icap_device_read: Transfer bytes from ICAP to the storage buffer. + * @parameter drvdata: a pointer to the drvdata. + * @parameter offset: The storage buffer start address. + * @parameter count: The number of words (32 bit) to read from the + * device (ICAP). + **/ +static int buffer_icap_device_read(struct hwicap_drvdata *drvdata, + u32 offset, u32 count) +{ + + s32 retries = 0; + void __iomem *base_address = drvdata->base_address; + + if (buffer_icap_busy(base_address)) + return -EBUSY; + + if ((offset + count) > XHI_MAX_BUFFER_INTS) + return -EINVAL; + + /* setSize count*4 to get bytes. */ + buffer_icap_set_size(base_address, (count << 2)); + buffer_icap_set_offset(base_address, offset); + buffer_icap_set_rnc(base_address, XHI_READBACK); + + while (buffer_icap_busy(base_address)) { + retries++; + if (retries > XHI_MAX_RETRIES) + return -EBUSY; + } + return 0; + +}; + +/** + * buffer_icap_device_write: Transfer bytes from ICAP to the storage buffer. + * @parameter drvdata: a pointer to the drvdata. + * @parameter offset: The storage buffer start address. + * @parameter count: The number of words (32 bit) to read from the + * device (ICAP). + **/ +static int buffer_icap_device_write(struct hwicap_drvdata *drvdata, + u32 offset, u32 count) +{ + + s32 retries = 0; + void __iomem *base_address = drvdata->base_address; + + if (buffer_icap_busy(base_address)) + return -EBUSY; + + if ((offset + count) > XHI_MAX_BUFFER_INTS) + return -EINVAL; + + /* setSize count*4 to get bytes. */ + buffer_icap_set_size(base_address, count << 2); + buffer_icap_set_offset(base_address, offset); + buffer_icap_set_rnc(base_address, XHI_CONFIGURE); + + while (buffer_icap_busy(base_address)) { + retries++; + if (retries > XHI_MAX_RETRIES) + return -EBUSY; + } + return 0; + +}; + +/** + * buffer_icap_reset: Reset the logic of the icap device. + * @parameter drvdata: a pointer to the drvdata. + * + * Writing to the status register resets the ICAP logic in an internal + * version of the core. For the version of the core published in EDK, + * this is a noop. + **/ +void buffer_icap_reset(struct hwicap_drvdata *drvdata) +{ + out_be32(drvdata->base_address + XHI_STATUS_REG_OFFSET, 0xFEFE); +} + +/** + * buffer_icap_set_configuration: Load a partial bitstream from system memory. + * @parameter drvdata: a pointer to the drvdata. + * @parameter data: Kernel address of the partial bitstream. + * @parameter size: the size of the partial bitstream in 32 bit words. + **/ +int buffer_icap_set_configuration(struct hwicap_drvdata *drvdata, u32 *data, + u32 size) +{ + int status; + s32 buffer_count = 0; + s32 num_writes = 0; + bool dirty = 0; + u32 i; + void __iomem *base_address = drvdata->base_address; + + /* Loop through all the data */ + for (i = 0, buffer_count = 0; i < size; i++) { + + /* Copy data to bram */ + buffer_icap_set_bram(base_address, buffer_count, data[i]); + dirty = 1; + + if (buffer_count < XHI_MAX_BUFFER_INTS - 1) { + buffer_count++; + continue; + } + + /* Write data to ICAP */ + status = buffer_icap_device_write( + drvdata, + XHI_BUFFER_START, + XHI_MAX_BUFFER_INTS); + if (status != 0) { + /* abort. */ + buffer_icap_reset(drvdata); + return status; + } + + buffer_count = 0; + num_writes++; + dirty = 0; + } + + /* Write unwritten data to ICAP */ + if (dirty) { + /* Write data to ICAP */ + status = buffer_icap_device_write(drvdata, XHI_BUFFER_START, + buffer_count); + if (status != 0) { + /* abort. */ + buffer_icap_reset(drvdata); + } + return status; + } + + return 0; +}; + +/** + * buffer_icap_get_configuration: Read configuration data from the device. + * @parameter drvdata: a pointer to the drvdata. + * @parameter data: Address of the data representing the partial bitstream + * @parameter size: the size of the partial bitstream in 32 bit words. + **/ +int buffer_icap_get_configuration(struct hwicap_drvdata *drvdata, u32 *data, + u32 size) +{ + int status; + s32 buffer_count = 0; + s32 read_count = 0; + u32 i; + void __iomem *base_address = drvdata->base_address; + + /* Loop through all the data */ + for (i = 0, buffer_count = XHI_MAX_BUFFER_INTS; i < size; i++) { + if (buffer_count == XHI_MAX_BUFFER_INTS) { + u32 words_remaining = size - i; + u32 words_to_read = + words_remaining < + XHI_MAX_BUFFER_INTS ? words_remaining : + XHI_MAX_BUFFER_INTS; + + /* Read data from ICAP */ + status = buffer_icap_device_read( + drvdata, + XHI_BUFFER_START, + words_to_read); + if (status != 0) { + /* abort. */ + buffer_icap_reset(drvdata); + return status; + } + + buffer_count = 0; + read_count++; + } + + /* Copy data from bram */ + data[i] = buffer_icap_get_bram(base_address, buffer_count); + buffer_count++; + } + + return 0; +}; diff --git a/drivers/char/xilinx_hwicap/buffer_icap.h b/drivers/char/xilinx_hwicap/buffer_icap.h new file mode 100644 index 00000000000..03184959fa0 --- /dev/null +++ b/drivers/char/xilinx_hwicap/buffer_icap.h @@ -0,0 +1,57 @@ +/***************************************************************************** + * + * Author: Xilinx, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" + * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND + * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, + * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, + * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION + * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, + * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE + * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY + * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE + * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR + * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF + * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. + * + * Xilinx products are not intended for use in life support appliances, + * devices, or systems. Use in such applications is expressly prohibited. + * + * (c) Copyright 2003-2008 Xilinx Inc. + * All rights reserved. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + *****************************************************************************/ + +#ifndef XILINX_BUFFER_ICAP_H_ /* prevent circular inclusions */ +#define XILINX_BUFFER_ICAP_H_ /* by using protection macros */ + +#include <linux/types.h> +#include <linux/cdev.h> +#include <linux/version.h> +#include <linux/platform_device.h> + +#include <asm/io.h> +#include "xilinx_hwicap.h" + +void buffer_icap_reset(struct hwicap_drvdata *drvdata); + +/* Loads a partial bitstream from system memory. */ +int buffer_icap_set_configuration(struct hwicap_drvdata *drvdata, u32 *data, + u32 Size); + +/* Loads a partial bitstream from system memory. */ +int buffer_icap_get_configuration(struct hwicap_drvdata *drvdata, u32 *data, + u32 Size); + +#endif diff --git a/drivers/char/xilinx_hwicap/fifo_icap.c b/drivers/char/xilinx_hwicap/fifo_icap.c new file mode 100644 index 00000000000..0988314694a --- /dev/null +++ b/drivers/char/xilinx_hwicap/fifo_icap.c @@ -0,0 +1,381 @@ +/***************************************************************************** + * + * Author: Xilinx, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" + * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND + * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, + * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, + * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION + * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, + * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE + * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY + * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE + * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR + * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF + * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. + * + * Xilinx products are not intended for use in life support appliances, + * devices, or systems. Use in such applications is expressly prohibited. + * + * (c) Copyright 2007-2008 Xilinx Inc. + * All rights reserved. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + *****************************************************************************/ + +#include "fifo_icap.h" + +/* Register offsets for the XHwIcap device. */ +#define XHI_GIER_OFFSET 0x1C /* Device Global Interrupt Enable Reg */ +#define XHI_IPISR_OFFSET 0x20 /* Interrupt Status Register */ +#define XHI_IPIER_OFFSET 0x28 /* Interrupt Enable Register */ +#define XHI_WF_OFFSET 0x100 /* Write FIFO */ +#define XHI_RF_OFFSET 0x104 /* Read FIFO */ +#define XHI_SZ_OFFSET 0x108 /* Size Register */ +#define XHI_CR_OFFSET 0x10C /* Control Register */ +#define XHI_SR_OFFSET 0x110 /* Status Register */ +#define XHI_WFV_OFFSET 0x114 /* Write FIFO Vacancy Register */ +#define XHI_RFO_OFFSET 0x118 /* Read FIFO Occupancy Register */ + +/* Device Global Interrupt Enable Register (GIER) bit definitions */ + +#define XHI_GIER_GIE_MASK 0x80000000 /* Global Interrupt enable Mask */ + +/** + * HwIcap Device Interrupt Status/Enable Registers + * + * Interrupt Status Register (IPISR) : This register holds the + * interrupt status flags for the device. These bits are toggle on + * write. + * + * Interrupt Enable Register (IPIER) : This register is used to enable + * interrupt sources for the device. + * Writing a '1' to a bit enables the corresponding interrupt. + * Writing a '0' to a bit disables the corresponding interrupt. + * + * IPISR/IPIER registers have the same bit definitions and are only defined + * once. + */ +#define XHI_IPIXR_RFULL_MASK 0x00000008 /* Read FIFO Full */ +#define XHI_IPIXR_WEMPTY_MASK 0x00000004 /* Write FIFO Empty */ +#define XHI_IPIXR_RDP_MASK 0x00000002 /* Read FIFO half full */ +#define XHI_IPIXR_WRP_MASK 0x00000001 /* Write FIFO half full */ +#define XHI_IPIXR_ALL_MASK 0x0000000F /* Mask of all interrupts */ + +/* Control Register (CR) */ +#define XHI_CR_SW_RESET_MASK 0x00000008 /* SW Reset Mask */ +#define XHI_CR_FIFO_CLR_MASK 0x00000004 /* FIFO Clear Mask */ +#define XHI_CR_READ_MASK 0x00000002 /* Read from ICAP to FIFO */ +#define XHI_CR_WRITE_MASK 0x00000001 /* Write from FIFO to ICAP */ + +/* Status Register (SR) */ +#define XHI_SR_CFGERR_N_MASK 0x00000100 /* Config Error Mask */ +#define XHI_SR_DALIGN_MASK 0x00000080 /* Data Alignment Mask */ +#define XHI_SR_RIP_MASK 0x00000040 /* Read back Mask */ +#define XHI_SR_IN_ABORT_N_MASK 0x00000020 /* Select Map Abort Mask */ +#define XHI_SR_DONE_MASK 0x00000001 /* Done bit Mask */ + + +#define XHI_WFO_MAX_VACANCY 1024 /* Max Write FIFO Vacancy, in words */ +#define XHI_RFO_MAX_OCCUPANCY 256 /* Max Read FIFO Occupancy, in words */ +/* The maximum amount we can request from fifo_icap_get_configuration + at once, in bytes. */ +#define XHI_MAX_READ_TRANSACTION_WORDS 0xFFF + + +/** + * fifo_icap_fifo_write: Write data to the write FIFO. + * @parameter drvdata: a pointer to the drvdata. + * @parameter data: the 32-bit value to be written to the FIFO. + * + * This function will silently fail if the fifo is full. + **/ +static inline void fifo_icap_fifo_write(struct hwicap_drvdata *drvdata, + u32 data) +{ + dev_dbg(drvdata->dev, "fifo_write: %x\n", data); + out_be32(drvdata->base_address + XHI_WF_OFFSET, data); +} + +/** + * fifo_icap_fifo_read: Read data from the Read FIFO. + * @parameter drvdata: a pointer to the drvdata. + * + * This function will silently fail if the fifo is empty. + **/ +static inline u32 fifo_icap_fifo_read(struct hwicap_drvdata *drvdata) +{ + u32 data = in_be32(drvdata->base_address + XHI_RF_OFFSET); + dev_dbg(drvdata->dev, "fifo_read: %x\n", data); + return data; +} + +/** + * fifo_icap_set_read_size: Set the the size register. + * @parameter drvdata: a pointer to the drvdata. + * @parameter data: the size of the following read transaction, in words. + **/ +static inline void fifo_icap_set_read_size(struct hwicap_drvdata *drvdata, + u32 data) +{ + out_be32(drvdata->base_address + XHI_SZ_OFFSET, data); +} + +/** + * fifo_icap_start_config: Initiate a configuration (write) to the device. + * @parameter drvdata: a pointer to the drvdata. + **/ +static inline void fifo_icap_start_config(struct hwicap_drvdata *drvdata) +{ + out_be32(drvdata->base_address + XHI_CR_OFFSET, XHI_CR_WRITE_MASK); + dev_dbg(drvdata->dev, "configuration started\n"); +} + +/** + * fifo_icap_start_readback: Initiate a readback from the device. + * @parameter drvdata: a pointer to the drvdata. + **/ +static inline void fifo_icap_start_readback(struct hwicap_drvdata *drvdata) +{ + out_be32(drvdata->base_address + XHI_CR_OFFSET, XHI_CR_READ_MASK); + dev_dbg(drvdata->dev, "readback started\n"); +} + +/** + * fifo_icap_busy: Return true if the ICAP is still processing a transaction. + * @parameter drvdata: a pointer to the drvdata. + **/ +static inline u32 fifo_icap_busy(struct hwicap_drvdata *drvdata) +{ + u32 status = in_be32(drvdata->base_address + XHI_SR_OFFSET); + dev_dbg(drvdata->dev, "Getting status = %x\n", status); + return (status & XHI_SR_DONE_MASK) ? 0 : 1; +} + +/** + * fifo_icap_write_fifo_vacancy: Query the write fifo available space. + * @parameter drvdata: a pointer to the drvdata. + * + * Return the number of words that can be safely pushed into the write fifo. + **/ +static inline u32 fifo_icap_write_fifo_vacancy( + struct hwicap_drvdata *drvdata) +{ + return in_be32(drvdata->base_address + XHI_WFV_OFFSET); +} + +/** + * fifo_icap_read_fifo_occupancy: Query the read fifo available data. + * @parameter drvdata: a pointer to the drvdata. + * + * Return the number of words that can be safely read from the read fifo. + **/ +static inline u32 fifo_icap_read_fifo_occupancy( + struct hwicap_drvdata *drvdata) +{ + return in_be32(drvdata->base_address + XHI_RFO_OFFSET); +} + +/** + * fifo_icap_set_configuration: Send configuration data to the ICAP. + * @parameter drvdata: a pointer to the drvdata. + * @parameter frame_buffer: a pointer to the data to be written to the + * ICAP device. + * @parameter num_words: the number of words (32 bit) to write to the ICAP + * device. + + * This function writes the given user data to the Write FIFO in + * polled mode and starts the transfer of the data to + * the ICAP device. + **/ +int fifo_icap_set_configuration(struct hwicap_drvdata *drvdata, + u32 *frame_buffer, u32 num_words) +{ + + u32 write_fifo_vacancy = 0; + u32 retries = 0; + u32 remaining_words; + + dev_dbg(drvdata->dev, "fifo_set_configuration\n"); + + /* + * Check if the ICAP device is Busy with the last Read/Write + */ + if (fifo_icap_busy(drvdata)) + return -EBUSY; + + /* + * Set up the buffer pointer and the words to be transferred. + */ + remaining_words = num_words; + + while (remaining_words > 0) { + /* + * Wait until we have some data in the fifo. + */ + while (write_fifo_vacancy == 0) { + write_fifo_vacancy = + fifo_icap_write_fifo_vacancy(drvdata); + retries++; + if (retries > XHI_MAX_RETRIES) + return -EIO; + } + + /* + * Write data into the Write FIFO. + */ + while ((write_fifo_vacancy != 0) && + (remaining_words > 0)) { + fifo_icap_fifo_write(drvdata, *frame_buffer); + + remaining_words--; + write_fifo_vacancy--; + frame_buffer++; + } + /* Start pushing whatever is in the FIFO into the ICAP. */ + fifo_icap_start_config(drvdata); + } + + /* Wait until the write has finished. */ + while (fifo_icap_busy(drvdata)) { + retries++; + if (retries > XHI_MAX_RETRIES) + break; + } + + dev_dbg(drvdata->dev, "done fifo_set_configuration\n"); + + /* + * If the requested number of words have not been read from + * the device then indicate failure. + */ + if (remaining_words != 0) + return -EIO; + + return 0; +} + +/** + * fifo_icap_get_configuration: Read configuration data from the device. + * @parameter drvdata: a pointer to the drvdata. + * @parameter data: Address of the data representing the partial bitstream + * @parameter size: the size of the partial bitstream in 32 bit words. + * + * This function reads the specified number of words from the ICAP device in + * the polled mode. + */ +int fifo_icap_get_configuration(struct hwicap_drvdata *drvdata, + u32 *frame_buffer, u32 num_words) +{ + + u32 read_fifo_occupancy = 0; + u32 retries = 0; + u32 *data = frame_buffer; + u32 remaining_words; + u32 words_to_read; + + dev_dbg(drvdata->dev, "fifo_get_configuration\n"); + + /* + * Check if the ICAP device is Busy with the last Write/Read + */ + if (fifo_icap_busy(drvdata)) + return -EBUSY; + + remaining_words = num_words; + + while (remaining_words > 0) { + words_to_read = remaining_words; + /* The hardware has a limit on the number of words + that can be read at one time. */ + if (words_to_read > XHI_MAX_READ_TRANSACTION_WORDS) + words_to_read = XHI_MAX_READ_TRANSACTION_WORDS; + + remaining_words -= words_to_read; + + fifo_icap_set_read_size(drvdata, words_to_read); + fifo_icap_start_readback(drvdata); + + while (words_to_read > 0) { + /* Wait until we have some data in the fifo. */ + while (read_fifo_occupancy == 0) { + read_fifo_occupancy = + fifo_icap_read_fifo_occupancy(drvdata); + retries++; + if (retries > XHI_MAX_RETRIES) + return -EIO; + } + + if (read_fifo_occupancy > words_to_read) + read_fifo_occupancy = words_to_read; + + words_to_read -= read_fifo_occupancy; + + /* Read the data from the Read FIFO. */ + while (read_fifo_occupancy != 0) { + *data++ = fifo_icap_fifo_read(drvdata); + read_fifo_occupancy--; + } + } + } + + dev_dbg(drvdata->dev, "done fifo_get_configuration\n"); + + return 0; +} + +/** + * buffer_icap_reset: Reset the logic of the icap device. + * @parameter drvdata: a pointer to the drvdata. + * + * This function forces the software reset of the complete HWICAP device. + * All the registers will return to the default value and the FIFO is also + * flushed as a part of this software reset. + */ +void fifo_icap_reset(struct hwicap_drvdata *drvdata) +{ + u32 reg_data; + /* + * Reset the device by setting/clearing the RESET bit in the + * Control Register. + */ + reg_data = in_be32(drvdata->base_address + XHI_CR_OFFSET); + + out_be32(drvdata->base_address + XHI_CR_OFFSET, + reg_data | XHI_CR_SW_RESET_MASK); + + out_be32(drvdata->base_address + XHI_CR_OFFSET, + reg_data & (~XHI_CR_SW_RESET_MASK)); + +} + +/** + * fifo_icap_flush_fifo: This function flushes the FIFOs in the device. + * @parameter drvdata: a pointer to the drvdata. + */ +void fifo_icap_flush_fifo(struct hwicap_drvdata *drvdata) +{ + u32 reg_data; + /* + * Flush the FIFO by setting/clearing the FIFO Clear bit in the + * Control Register. + */ + reg_data = in_be32(drvdata->base_address + XHI_CR_OFFSET); + + out_be32(drvdata->base_address + XHI_CR_OFFSET, + reg_data | XHI_CR_FIFO_CLR_MASK); + + out_be32(drvdata->base_address + XHI_CR_OFFSET, + reg_data & (~XHI_CR_FIFO_CLR_MASK)); +} + diff --git a/drivers/char/xilinx_hwicap/fifo_icap.h b/drivers/char/xilinx_hwicap/fifo_icap.h new file mode 100644 index 00000000000..4d3068dd040 --- /dev/null +++ b/drivers/char/xilinx_hwicap/fifo_icap.h @@ -0,0 +1,62 @@ +/***************************************************************************** + * + * Author: Xilinx, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" + * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND + * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, + * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, + * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION + * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, + * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE + * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY + * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE + * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR + * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF + * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. + * + * Xilinx products are not intended for use in life support appliances, + * devices, or systems. Use in such applications is expressly prohibited. + * + * (c) Copyright 2007-2008 Xilinx Inc. + * All rights reserved. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + *****************************************************************************/ + +#ifndef XILINX_FIFO_ICAP_H_ /* prevent circular inclusions */ +#define XILINX_FIFO_ICAP_H_ /* by using protection macros */ + +#include <linux/types.h> +#include <linux/cdev.h> +#include <linux/version.h> +#include <linux/platform_device.h> + +#include <asm/io.h> +#include "xilinx_hwicap.h" + +/* Reads integers from the device into the storage buffer. */ +int fifo_icap_get_configuration( + struct hwicap_drvdata *drvdata, + u32 *FrameBuffer, + u32 NumWords); + +/* Writes integers to the device from the storage buffer. */ +int fifo_icap_set_configuration( + struct hwicap_drvdata *drvdata, + u32 *FrameBuffer, + u32 NumWords); + +void fifo_icap_reset(struct hwicap_drvdata *drvdata); +void fifo_icap_flush_fifo(struct hwicap_drvdata *drvdata); + +#endif diff --git a/drivers/char/xilinx_hwicap/xilinx_hwicap.c b/drivers/char/xilinx_hwicap/xilinx_hwicap.c new file mode 100644 index 00000000000..24f6aef0fd3 --- /dev/null +++ b/drivers/char/xilinx_hwicap/xilinx_hwicap.c @@ -0,0 +1,904 @@ +/***************************************************************************** + * + * Author: Xilinx, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" + * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND + * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, + * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, + * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION + * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, + * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE + * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY + * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE + * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR + * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF + * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. + * + * Xilinx products are not intended for use in life support appliances, + * devices, or systems. Use in such applications is expressly prohibited. + * + * (c) Copyright 2002 Xilinx Inc., Systems Engineering Group + * (c) Copyright 2004 Xilinx Inc., Systems Engineering Group + * (c) Copyright 2007-2008 Xilinx Inc. + * All rights reserved. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + *****************************************************************************/ + +/* + * This is the code behind /dev/xilinx_icap -- it allows a user-space + * application to use the Xilinx ICAP subsystem. + * + * The following operations are possible: + * + * open open the port and initialize for access. + * release release port + * write Write a bitstream to the configuration processor. + * read Read a data stream from the configuration processor. + * + * After being opened, the port is initialized and accessed to avoid a + * corrupted first read which may occur with some hardware. The port + * is left in a desynched state, requiring that a synch sequence be + * transmitted before any valid configuration data. A user will have + * exclusive access to the device while it remains open, and the state + * of the ICAP cannot be guaranteed after the device is closed. Note + * that a complete reset of the core and the state of the ICAP cannot + * be performed on many versions of the cores, hence users of this + * device should avoid making inconsistent accesses to the device. In + * particular, accessing the read interface, without first generating + * a write containing a readback packet can leave the ICAP in an + * inaccessible state. + * + * Note that in order to use the read interface, it is first necessary + * to write a request packet to the write interface. i.e., it is not + * possible to simply readback the bitstream (or any configuration + * bits) from a device without specifically requesting them first. + * The code to craft such packets is intended to be part of the + * user-space application code that uses this device. The simplest + * way to use this interface is simply: + * + * cp foo.bit /dev/xilinx_icap + * + * Note that unless foo.bit is an appropriately constructed partial + * bitstream, this has a high likelyhood of overwriting the design + * currently programmed in the FPGA. + */ + +#include <linux/version.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/ioport.h> +#include <linux/interrupt.h> +#include <linux/fcntl.h> +#include <linux/init.h> +#include <linux/poll.h> +#include <linux/proc_fs.h> +#include <asm/semaphore.h> +#include <linux/sysctl.h> +#include <linux/version.h> +#include <linux/fs.h> +#include <linux/cdev.h> +#include <linux/platform_device.h> + +#include <asm/io.h> +#include <asm/uaccess.h> +#include <asm/system.h> + +#ifdef CONFIG_OF +/* For open firmware. */ +#include <linux/of_device.h> +#include <linux/of_platform.h> +#endif + +#include "xilinx_hwicap.h" +#include "buffer_icap.h" +#include "fifo_icap.h" + +#define DRIVER_NAME "xilinx_icap" + +#define HWICAP_REGS (0x10000) + +/* dynamically allocate device number */ +static int xhwicap_major; +static int xhwicap_minor; +#define HWICAP_DEVICES 1 + +module_param(xhwicap_major, int, S_IRUGO); +module_param(xhwicap_minor, int, S_IRUGO); + +/* An array, which is set to true when the device is registered. */ +static bool probed_devices[HWICAP_DEVICES]; + +static struct class *icap_class; + +#define UNIMPLEMENTED 0xFFFF + +static const struct config_registers v2_config_registers = { + .CRC = 0, + .FAR = 1, + .FDRI = 2, + .FDRO = 3, + .CMD = 4, + .CTL = 5, + .MASK = 6, + .STAT = 7, + .LOUT = 8, + .COR = 9, + .MFWR = 10, + .FLR = 11, + .KEY = 12, + .CBC = 13, + .IDCODE = 14, + .AXSS = UNIMPLEMENTED, + .C0R_1 = UNIMPLEMENTED, + .CSOB = UNIMPLEMENTED, + .WBSTAR = UNIMPLEMENTED, + .TIMER = UNIMPLEMENTED, + .BOOTSTS = UNIMPLEMENTED, + .CTL_1 = UNIMPLEMENTED, +}; + +static const struct config_registers v4_config_registers = { + .CRC = 0, + .FAR = 1, + .FDRI = 2, + .FDRO = 3, + .CMD = 4, + .CTL = 5, + .MASK = 6, + .STAT = 7, + .LOUT = 8, + .COR = 9, + .MFWR = 10, + .FLR = UNIMPLEMENTED, + .KEY = UNIMPLEMENTED, + .CBC = 11, + .IDCODE = 12, + .AXSS = 13, + .C0R_1 = UNIMPLEMENTED, + .CSOB = UNIMPLEMENTED, + .WBSTAR = UNIMPLEMENTED, + .TIMER = UNIMPLEMENTED, + .BOOTSTS = UNIMPLEMENTED, + .CTL_1 = UNIMPLEMENTED, +}; +static const struct config_registers v5_config_registers = { + .CRC = 0, + .FAR = 1, + .FDRI = 2, + .FDRO = 3, + .CMD = 4, + .CTL = 5, + .MASK = 6, + .STAT = 7, + .LOUT = 8, + .COR = 9, + .MFWR = 10, + .FLR = UNIMPLEMENTED, + .KEY = UNIMPLEMENTED, + .CBC = 11, + .IDCODE = 12, + .AXSS = 13, + .C0R_1 = 14, + .CSOB = 15, + .WBSTAR = 16, + .TIMER = 17, + .BOOTSTS = 18, + .CTL_1 = 19, +}; + +/** + * hwicap_command_desync: Send a DESYNC command to the ICAP port. + * @parameter drvdata: a pointer to the drvdata. + * + * This command desynchronizes the ICAP After this command, a + * bitstream containing a NULL packet, followed by a SYNCH packet is + * required before the ICAP will recognize commands. + */ +int hwicap_command_desync(struct hwicap_drvdata *drvdata) +{ + u32 buffer[4]; + u32 index = 0; + + /* + * Create the data to be written to the ICAP. + */ + buffer[index++] = hwicap_type_1_write(drvdata->config_regs->CMD) | 1; + buffer[index++] = XHI_CMD_DESYNCH; + buffer[index++] = XHI_NOOP_PACKET; + buffer[index++] = XHI_NOOP_PACKET; + + /* + * Write the data to the FIFO and intiate the transfer of data present + * in the FIFO to the ICAP device. + */ + return drvdata->config->set_configuration(drvdata, + &buffer[0], index); +} + +/** + * hwicap_command_capture: Send a CAPTURE command to the ICAP port. + * @parameter drvdata: a pointer to the drvdata. + * + * This command captures all of the flip flop states so they will be + * available during readback. One can use this command instead of + * enabling the CAPTURE block in the design. + */ +int hwicap_command_capture(struct hwicap_drvdata *drvdata) +{ + u32 buffer[7]; + u32 index = 0; + + /* + * Create the data to be written to the ICAP. + */ + buffer[index++] = XHI_DUMMY_PACKET; + buffer[index++] = XHI_SYNC_PACKET; + buffer[index++] = XHI_NOOP_PACKET; + buffer[index++] = hwicap_type_1_write(drvdata->config_regs->CMD) | 1; + buffer[index++] = XHI_CMD_GCAPTURE; + buffer[index++] = XHI_DUMMY_PACKET; + buffer[index++] = XHI_DUMMY_PACKET; + + /* + * Write the data to the FIFO and intiate the transfer of data + * present in the FIFO to the ICAP device. + */ + return drvdata->config->set_configuration(drvdata, + &buffer[0], index); + +} + +/** + * hwicap_get_configuration_register: Query a configuration register. + * @parameter drvdata: a pointer to the drvdata. + * @parameter reg: a constant which represents the configuration + * register value to be returned. + * Examples: XHI_IDCODE, XHI_FLR. + * @parameter RegData: returns the value of the register. + * + * Sends a query packet to the ICAP and then receives the response. + * The icap is left in Synched state. + */ +int hwicap_get_configuration_register(struct hwicap_drvdata *drvdata, + u32 reg, u32 *RegData) +{ + int status; + u32 buffer[6]; + u32 index = 0; + + /* + * Create the data to be written to the ICAP. + */ + buffer[index++] = XHI_DUMMY_PACKET; + buffer[index++] = XHI_SYNC_PACKET; + buffer[index++] = XHI_NOOP_PACKET; + buffer[index++] = hwicap_type_1_read(reg) | 1; + buffer[index++] = XHI_NOOP_PACKET; + buffer[index++] = XHI_NOOP_PACKET; + + /* + * Write the data to the FIFO and intiate the transfer of data present + * in the FIFO to the ICAP device. + */ + status = drvdata->config->set_configuration(drvdata, + &buffer[0], index); + if (status) + return status; + + /* + * Read the configuration register + */ + status = drvdata->config->get_configuration(drvdata, RegData, 1); + if (status) + return status; + + return 0; +} + +int hwicap_initialize_hwicap(struct hwicap_drvdata *drvdata) +{ + int status; + u32 idcode; + + dev_dbg(drvdata->dev, "initializing\n"); + + /* Abort any current transaction, to make sure we have the + * ICAP in a good state. */ + dev_dbg(drvdata->dev, "Reset...\n"); + drvdata->config->reset(drvdata); + + dev_dbg(drvdata->dev, "Desync...\n"); + status = hwicap_command_desync(drvdata); + if (status) + return status; + + /* Attempt to read the IDCODE from ICAP. This + * may not be returned correctly, due to the design of the + * hardware. + */ + dev_dbg(drvdata->dev, "Reading IDCODE...\n"); + status = hwicap_get_configuration_register( + drvdata, drvdata->config_regs->IDCODE, &idcode); + dev_dbg(drvdata->dev, "IDCODE = %x\n", idcode); + if (status) + return status; + + dev_dbg(drvdata->dev, "Desync...\n"); + status = hwicap_command_desync(drvdata); + if (status) + return status; + + return 0; +} + +static ssize_t +hwicap_read(struct file *file, char *buf, size_t count, loff_t *ppos) +{ + struct hwicap_drvdata *drvdata = file->private_data; + ssize_t bytes_to_read = 0; + u32 *kbuf; + u32 words; + u32 bytes_remaining; + int status; + + if (down_interruptible(&drvdata->sem)) + return -ERESTARTSYS; + + if (drvdata->read_buffer_in_use) { + /* If there are leftover bytes in the buffer, just */ + /* return them and don't try to read more from the */ + /* ICAP device. */ + bytes_to_read = + (count < drvdata->read_buffer_in_use) ? count : + drvdata->read_buffer_in_use; + + /* Return the data currently in the read buffer. */ + if (copy_to_user(buf, drvdata->read_buffer, bytes_to_read)) { + status = -EFAULT; + goto error; + } + drvdata->read_buffer_in_use -= bytes_to_read; + memcpy(drvdata->read_buffer + bytes_to_read, + drvdata->read_buffer, 4 - bytes_to_read); + } else { + /* Get new data from the ICAP, and return was was requested. */ + kbuf = (u32 *) get_zeroed_page(GFP_KERNEL); + if (!kbuf) { + status = -ENOMEM; + goto error; + } + + /* The ICAP device is only able to read complete */ + /* words. If a number of bytes that do not correspond */ + /* to complete words is requested, then we read enough */ + /* words to get the required number of bytes, and then */ + /* save the remaining bytes for the next read. */ + + /* Determine the number of words to read, rounding up */ + /* if necessary. */ + words = ((count + 3) >> 2); + bytes_to_read = words << 2; + + if (bytes_to_read > PAGE_SIZE) + bytes_to_read = PAGE_SIZE; + + /* Ensure we only read a complete number of words. */ + bytes_remaining = bytes_to_read & 3; + bytes_to_read &= ~3; + words = bytes_to_read >> 2; + + status = drvdata->config->get_configuration(drvdata, + kbuf, words); + + /* If we didn't read correctly, then bail out. */ + if (status) { + free_page((unsigned long)kbuf); + goto error; + } + + /* If we fail to return the data to the user, then bail out. */ + if (copy_to_user(buf, kbuf, bytes_to_read)) { + free_page((unsigned long)kbuf); + status = -EFAULT; + goto error; + } + memcpy(kbuf, drvdata->read_buffer, bytes_remaining); + drvdata->read_buffer_in_use = bytes_remaining; + free_page((unsigned long)kbuf); + } + status = bytes_to_read; + error: + up(&drvdata->sem); + return status; +} + +static ssize_t +hwicap_write(struct file *file, const char *buf, + size_t count, loff_t *ppos) +{ + struct hwicap_drvdata *drvdata = file->private_data; + ssize_t written = 0; + ssize_t left = count; + u32 *kbuf; + ssize_t len; + ssize_t status; + + if (down_interruptible(&drvdata->sem)) + return -ERESTARTSYS; + + left += drvdata->write_buffer_in_use; + + /* Only write multiples of 4 bytes. */ + if (left < 4) { + status = 0; + goto error; + } + + kbuf = (u32 *) __get_free_page(GFP_KERNEL); + if (!kbuf) { + status = -ENOMEM; + goto error; + } + + while (left > 3) { + /* only write multiples of 4 bytes, so there might */ + /* be as many as 3 bytes left (at the end). */ + len = left; + + if (len > PAGE_SIZE) + len = PAGE_SIZE; + len &= ~3; + + if (drvdata->write_buffer_in_use) { + memcpy(kbuf, drvdata->write_buffer, + drvdata->write_buffer_in_use); + if (copy_from_user( + (((char *)kbuf) + (drvdata->write_buffer_in_use)), + buf + written, + len - (drvdata->write_buffer_in_use))) { + free_page((unsigned long)kbuf); + status = -EFAULT; + goto error; + } + } else { + if (copy_from_user(kbuf, buf + written, len)) { + free_page((unsigned long)kbuf); + status = -EFAULT; + goto error; + } + } + + status = drvdata->config->set_configuration(drvdata, + kbuf, len >> 2); + + if (status) { + free_page((unsigned long)kbuf); + status = -EFAULT; + goto error; + } + if (drvdata->write_buffer_in_use) { + len -= drvdata->write_buffer_in_use; + left -= drvdata->write_buffer_in_use; + drvdata->write_buffer_in_use = 0; + } + written += len; + left -= len; + } + if ((left > 0) && (left < 4)) { + if (!copy_from_user(drvdata->write_buffer, + buf + written, left)) { + drvdata->write_buffer_in_use = left; + written += left; + left = 0; + } + } + + free_page((unsigned long)kbuf); + status = written; + error: + up(&drvdata->sem); + return status; +} + +static int hwicap_open(struct inode *inode, struct file *file) +{ + struct hwicap_drvdata *drvdata; + int status; + + drvdata = container_of(inode->i_cdev, struct hwicap_drvdata, cdev); + + if (down_interruptible(&drvdata->sem)) + return -ERESTARTSYS; + + if (drvdata->is_open) { + status = -EBUSY; + goto error; + } + + status = hwicap_initialize_hwicap(drvdata); + if (status) { + dev_err(drvdata->dev, "Failed to open file"); + goto error; + } + + file->private_data = drvdata; + drvdata->write_buffer_in_use = 0; + drvdata->read_buffer_in_use = 0; + drvdata->is_open = 1; + + error: + up(&drvdata->sem); + return status; +} + +static int hwicap_release(struct inode *inode, struct file *file) +{ + struct hwicap_drvdata *drvdata = file->private_data; + int i; + int status = 0; + + if (down_interruptible(&drvdata->sem)) + return -ERESTARTSYS; + + if (drvdata->write_buffer_in_use) { + /* Flush write buffer. */ + for (i = drvdata->write_buffer_in_use; i < 4; i++) + drvdata->write_buffer[i] = 0; + + status = drvdata->config->set_configuration(drvdata, + (u32 *) drvdata->write_buffer, 1); + if (status) + goto error; + } + + status = hwicap_command_desync(drvdata); + if (status) + goto error; + + error: + drvdata->is_open = 0; + up(&drvdata->sem); + return status; +} + +static struct file_operations hwicap_fops = { + .owner = THIS_MODULE, + .write = hwicap_write, + .read = hwicap_read, + .open = hwicap_open, + .release = hwicap_release, +}; + +static int __devinit hwicap_setup(struct device *dev, int id, + const struct resource *regs_res, + const struct hwicap_driver_config *config, + const struct config_registers *config_regs) +{ + dev_t devt; + struct hwicap_drvdata *drvdata = NULL; + int retval = 0; + + dev_info(dev, "Xilinx icap port driver\n"); + + if (id < 0) { + for (id = 0; id < HWICAP_DEVICES; id++) + if (!probed_devices[id]) + break; + } + if (id < 0 || id >= HWICAP_DEVICES) { + dev_err(dev, "%s%i too large\n", DRIVER_NAME, id); + return -EINVAL; + } + if (probed_devices[id]) { + dev_err(dev, "cannot assign to %s%i; it is already in use\n", + DRIVER_NAME, id); + return -EBUSY; + } + + probed_devices[id] = 1; + + devt = MKDEV(xhwicap_major, xhwicap_minor + id); + + drvdata = kmalloc(sizeof(struct hwicap_drvdata), GFP_KERNEL); + if (!drvdata) { + dev_err(dev, "Couldn't allocate device private record\n"); + return -ENOMEM; + } + memset((void *)drvdata, 0, sizeof(struct hwicap_drvdata)); + dev_set_drvdata(dev, (void *)drvdata); + + if (!regs_res) { + dev_err(dev, "Couldn't get registers resource\n"); + retval = -EFAULT; + goto failed1; + } + + drvdata->mem_start = regs_res->start; + drvdata->mem_end = regs_res->end; + drvdata->mem_size = regs_res->end - regs_res->start + 1; + + if (!request_mem_region(drvdata->mem_start, + drvdata->mem_size, DRIVER_NAME)) { + dev_err(dev, "Couldn't lock memory region at %p\n", + (void *)regs_res->start); + retval = -EBUSY; + goto failed1; + } + + drvdata->devt = devt; + drvdata->dev = dev; + drvdata->base_address = ioremap(drvdata->mem_start, drvdata->mem_size); + if (!drvdata->base_address) { + dev_err(dev, "ioremap() failed\n"); + goto failed2; + } + + drvdata->config = config; + drvdata->config_regs = config_regs; + + init_MUTEX(&drvdata->sem); + drvdata->is_open = 0; + + dev_info(dev, "ioremap %lx to %p with size %x\n", + (unsigned long int)drvdata->mem_start, + drvdata->base_address, drvdata->mem_size); + + cdev_init(&drvdata->cdev, &hwicap_fops); + drvdata->cdev.owner = THIS_MODULE; + retval = cdev_add(&drvdata->cdev, devt, 1); + if (retval) { + dev_err(dev, "cdev_add() failed\n"); + goto failed3; + } + /* devfs_mk_cdev(devt, S_IFCHR|S_IRUGO|S_IWUGO, DRIVER_NAME); */ + class_device_create(icap_class, NULL, devt, NULL, DRIVER_NAME); + return 0; /* success */ + + failed3: + iounmap(drvdata->base_address); + + failed2: + release_mem_region(regs_res->start, drvdata->mem_size); + + failed1: + kfree(drvdata); + + return retval; +} + +static struct hwicap_driver_config buffer_icap_config = { + .get_configuration = buffer_icap_get_configuration, + .set_configuration = buffer_icap_set_configuration, + .reset = buffer_icap_reset, +}; + +static struct hwicap_driver_config fifo_icap_config = { + .get_configuration = fifo_icap_get_configuration, + .set_configuration = fifo_icap_set_configuration, + .reset = fifo_icap_reset, +}; + +static int __devexit hwicap_remove(struct device *dev) +{ + struct hwicap_drvdata *drvdata; + + drvdata = (struct hwicap_drvdata *)dev_get_drvdata(dev); + + if (!drvdata) + return 0; + + class_device_destroy(icap_class, drvdata->devt); + cdev_del(&drvdata->cdev); + iounmap(drvdata->base_address); + release_mem_region(drvdata->mem_start, drvdata->mem_size); + kfree(drvdata); + dev_set_drvdata(dev, NULL); + probed_devices[MINOR(dev->devt)-xhwicap_minor] = 0; + + return 0; /* success */ +} + +static int __devinit hwicap_drv_probe(struct platform_device *pdev) +{ + struct resource *res; + const struct config_registers *regs; + const char *family; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + /* It's most likely that we're using V4, if the family is not + specified */ + regs = &v4_config_registers; + family = pdev->dev.platform_data; + + if (family) { + if (!strcmp(family, "virtex2p")) { + regs = &v2_config_registers; + } else if (!strcmp(family, "virtex4")) { + regs = &v4_config_registers; + } else if (!strcmp(family, "virtex5")) { + regs = &v5_config_registers; + } + } + + return hwicap_setup(&pdev->dev, pdev->id, res, + &buffer_icap_config, regs); +} + +static int __devexit hwicap_drv_remove(struct platform_device *pdev) +{ + return hwicap_remove(&pdev->dev); +} + +static struct platform_driver hwicap_platform_driver = { + .probe = hwicap_drv_probe, + .remove = hwicap_drv_remove, + .driver = { + .owner = THIS_MODULE, + .name = DRIVER_NAME, + }, +}; + +/* --------------------------------------------------------------------- + * OF bus binding + */ + +#if defined(CONFIG_OF) +static int __devinit +hwicap_of_probe(struct of_device *op, const struct of_device_id *match) +{ + struct resource res; + const unsigned int *id; + const char *family; + int rc; + const struct hwicap_driver_config *config = match->data; + const struct config_registers *regs; + + dev_dbg(&op->dev, "hwicap_of_probe(%p, %p)\n", op, match); + + rc = of_address_to_resource(op->node, 0, &res); + if (rc) { + dev_err(&op->dev, "invalid address\n"); + return rc; + } + + id = of_get_property(op->node, "port-number", NULL); + + /* It's most likely that we're using V4, if the family is not + specified */ + regs = &v4_config_registers; + family = of_get_property(op->node, "xlnx,family", NULL); + + if (family) { + if (!strcmp(family, "virtex2p")) { + regs = &v2_config_registers; + } else if (!strcmp(family, "virtex4")) { + regs = &v4_config_registers; + } else if (!strcmp(family, "virtex5")) { + regs = &v5_config_registers; + } + } + return hwicap_setup(&op->dev, id ? *id : -1, &res, config, + regs); +} + +static int __devexit hwicap_of_remove(struct of_device *op) +{ + return hwicap_remove(&op->dev); +} + +/* Match table for of_platform binding */ +static const struct of_device_id __devinit hwicap_of_match[] = { + { .compatible = "xlnx,opb-hwicap-1.00.b", .data = &buffer_icap_config}, + { .compatible = "xlnx,xps-hwicap-1.00.a", .data = &fifo_icap_config}, + {}, +}; +MODULE_DEVICE_TABLE(of, hwicap_of_match); + +static struct of_platform_driver hwicap_of_driver = { + .owner = THIS_MODULE, + .name = DRIVER_NAME, + .match_table = hwicap_of_match, + .probe = hwicap_of_probe, + .remove = __devexit_p(hwicap_of_remove), + .driver = { + .name = DRIVER_NAME, + }, +}; + +/* Registration helpers to keep the number of #ifdefs to a minimum */ +static inline int __devinit hwicap_of_register(void) +{ + pr_debug("hwicap: calling of_register_platform_driver()\n"); + return of_register_platform_driver(&hwicap_of_driver); +} + +static inline void __devexit hwicap_of_unregister(void) +{ + of_unregister_platform_driver(&hwicap_of_driver); +} +#else /* CONFIG_OF */ +/* CONFIG_OF not enabled; do nothing helpers */ +static inline int __devinit hwicap_of_register(void) { return 0; } +static inline void __devexit hwicap_of_unregister(void) { } +#endif /* CONFIG_OF */ + +static int __devinit hwicap_module_init(void) +{ + dev_t devt; + int retval; + + icap_class = class_create(THIS_MODULE, "xilinx_config"); + + if (xhwicap_major) { + devt = MKDEV(xhwicap_major, xhwicap_minor); + retval = register_chrdev_region( + devt, + HWICAP_DEVICES, + DRIVER_NAME); + if (retval < 0) + return retval; + } else { + retval = alloc_chrdev_region(&devt, + xhwicap_minor, + HWICAP_DEVICES, + DRIVER_NAME); + if (retval < 0) + return retval; + xhwicap_major = MAJOR(devt); + } + + retval = platform_driver_register(&hwicap_platform_driver); + + if (retval) + goto failed1; + + retval = hwicap_of_register(); + + if (retval) + goto failed2; + + return retval; + + failed2: + platform_driver_unregister(&hwicap_platform_driver); + + failed1: + unregister_chrdev_region(devt, HWICAP_DEVICES); + + return retval; +} + +static void __devexit hwicap_module_cleanup(void) +{ + dev_t devt = MKDEV(xhwicap_major, xhwicap_minor); + + class_destroy(icap_class); + + platform_driver_unregister(&hwicap_platform_driver); + + hwicap_of_unregister(); + + unregister_chrdev_region(devt, HWICAP_DEVICES); +} + +module_init(hwicap_module_init); +module_exit(hwicap_module_cleanup); + +MODULE_AUTHOR("Xilinx, Inc; Xilinx Research Labs Group"); +MODULE_DESCRIPTION("Xilinx ICAP Port Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/char/xilinx_hwicap/xilinx_hwicap.h b/drivers/char/xilinx_hwicap/xilinx_hwicap.h new file mode 100644 index 00000000000..ae771cac162 --- /dev/null +++ b/drivers/char/xilinx_hwicap/xilinx_hwicap.h @@ -0,0 +1,193 @@ +/***************************************************************************** + * + * Author: Xilinx, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" + * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND + * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, + * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, + * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION + * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, + * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE + * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY + * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE + * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR + * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF + * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. + * + * Xilinx products are not intended for use in life support appliances, + * devices, or systems. Use in such applications is expressly prohibited. + * + * (c) Copyright 2003-2007 Xilinx Inc. + * All rights reserved. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + *****************************************************************************/ + +#ifndef XILINX_HWICAP_H_ /* prevent circular inclusions */ +#define XILINX_HWICAP_H_ /* by using protection macros */ + +#include <linux/types.h> +#include <linux/cdev.h> +#include <linux/version.h> +#include <linux/platform_device.h> + +#include <asm/io.h> + +struct hwicap_drvdata { + u32 write_buffer_in_use; /* Always in [0,3] */ + u8 write_buffer[4]; + u32 read_buffer_in_use; /* Always in [0,3] */ + u8 read_buffer[4]; + u32 mem_start; /* phys. address of the control registers */ + u32 mem_end; /* phys. address of the control registers */ + u32 mem_size; + void __iomem *base_address;/* virt. address of the control registers */ + + struct device *dev; + struct cdev cdev; /* Char device structure */ + dev_t devt; + + const struct hwicap_driver_config *config; + const struct config_registers *config_regs; + void *private_data; + bool is_open; + struct semaphore sem; +}; + +struct hwicap_driver_config { + int (*get_configuration)(struct hwicap_drvdata *drvdata, u32 *data, + u32 size); + int (*set_configuration)(struct hwicap_drvdata *drvdata, u32 *data, + u32 size); + void (*reset)(struct hwicap_drvdata *drvdata); +}; + +/* Number of times to poll the done regsiter */ +#define XHI_MAX_RETRIES 10 + +/************ Constant Definitions *************/ + +#define XHI_PAD_FRAMES 0x1 + +/* Mask for calculating configuration packet headers */ +#define XHI_WORD_COUNT_MASK_TYPE_1 0x7FFUL +#define XHI_WORD_COUNT_MASK_TYPE_2 0x1FFFFFUL +#define XHI_TYPE_MASK 0x7 +#define XHI_REGISTER_MASK 0xF +#define XHI_OP_MASK 0x3 + +#define XHI_TYPE_SHIFT 29 +#define XHI_REGISTER_SHIFT 13 +#define XHI_OP_SHIFT 27 + +#define XHI_TYPE_1 1 +#define XHI_TYPE_2 2 +#define XHI_OP_WRITE 2 +#define XHI_OP_READ 1 + +/* Address Block Types */ +#define XHI_FAR_CLB_BLOCK 0 +#define XHI_FAR_BRAM_BLOCK 1 +#define XHI_FAR_BRAM_INT_BLOCK 2 + +struct config_registers { + u32 CRC; + u32 FAR; + u32 FDRI; + u32 FDRO; + u32 CMD; + u32 CTL; + u32 MASK; + u32 STAT; + u32 LOUT; + u32 COR; + u32 MFWR; + u32 FLR; + u32 KEY; + u32 CBC; + u32 IDCODE; + u32 AXSS; + u32 C0R_1; + u32 CSOB; + u32 WBSTAR; + u32 TIMER; + u32 BOOTSTS; + u32 CTL_1; +}; + +/* Configuration Commands */ +#define XHI_CMD_NULL 0 +#define XHI_CMD_WCFG 1 +#define XHI_CMD_MFW 2 +#define XHI_CMD_DGHIGH 3 +#define XHI_CMD_RCFG 4 +#define XHI_CMD_START 5 +#define XHI_CMD_RCAP 6 +#define XHI_CMD_RCRC 7 +#define XHI_CMD_AGHIGH 8 +#define XHI_CMD_SWITCH 9 +#define XHI_CMD_GRESTORE 10 +#define XHI_CMD_SHUTDOWN 11 +#define XHI_CMD_GCAPTURE 12 +#define XHI_CMD_DESYNCH 13 +#define XHI_CMD_IPROG 15 /* Only in Virtex5 */ +#define XHI_CMD_CRCC 16 /* Only in Virtex5 */ +#define XHI_CMD_LTIMER 17 /* Only in Virtex5 */ + +/* Packet constants */ +#define XHI_SYNC_PACKET 0xAA995566UL +#define XHI_DUMMY_PACKET 0xFFFFFFFFUL +#define XHI_NOOP_PACKET (XHI_TYPE_1 << XHI_TYPE_SHIFT) +#define XHI_TYPE_2_READ ((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \ + (XHI_OP_READ << XHI_OP_SHIFT)) + +#define XHI_TYPE_2_WRITE ((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \ + (XHI_OP_WRITE << XHI_OP_SHIFT)) + +#define XHI_TYPE2_CNT_MASK 0x07FFFFFF + +#define XHI_TYPE_1_PACKET_MAX_WORDS 2047UL +#define XHI_TYPE_1_HEADER_BYTES 4 +#define XHI_TYPE_2_HEADER_BYTES 8 + +/* Constant to use for CRC check when CRC has been disabled */ +#define XHI_DISABLED_AUTO_CRC 0x0000DEFCUL + +/** + * hwicap_type_1_read: Generates a Type 1 read packet header. + * @parameter: Register is the address of the register to be read back. + * + * Generates a Type 1 read packet header, which is used to indirectly + * read registers in the configuration logic. This packet must then + * be sent through the icap device, and a return packet received with + * the information. + **/ +static inline u32 hwicap_type_1_read(u32 Register) +{ + return (XHI_TYPE_1 << XHI_TYPE_SHIFT) | + (Register << XHI_REGISTER_SHIFT) | + (XHI_OP_READ << XHI_OP_SHIFT); +} + +/** + * hwicap_type_1_write: Generates a Type 1 write packet header + * @parameter: Register is the address of the register to be read back. + **/ +static inline u32 hwicap_type_1_write(u32 Register) +{ + return (XHI_TYPE_1 << XHI_TYPE_SHIFT) | + (Register << XHI_REGISTER_SHIFT) | + (XHI_OP_WRITE << XHI_OP_SHIFT); +} + +#endif diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig index 721f86f4f00..c159ae64eeb 100644 --- a/drivers/cpufreq/Kconfig +++ b/drivers/cpufreq/Kconfig @@ -9,9 +9,6 @@ config CPU_FREQ clock speed, you need to either enable a dynamic cpufreq governor (see below) after boot, or use a userspace tool. - To compile this driver as a module, choose M here: the - module will be called cpufreq. - For details, take a look at <file:Documentation/cpu-freq>. If in doubt, say N. diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index b730d670952..64926aa990d 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -287,7 +287,7 @@ static void adjust_jiffies(unsigned long val, struct cpufreq_freqs *ci) if (!l_p_j_ref_freq) { l_p_j_ref = loops_per_jiffy; l_p_j_ref_freq = ci->old; - dprintk("saving %lu as reference value for loops_per_jiffy;" + dprintk("saving %lu as reference value for loops_per_jiffy; " "freq is %u kHz\n", l_p_j_ref, l_p_j_ref_freq); } if ((val == CPUFREQ_PRECHANGE && ci->old < ci->new) || @@ -295,7 +295,7 @@ static void adjust_jiffies(unsigned long val, struct cpufreq_freqs *ci) (val == CPUFREQ_RESUMECHANGE || val == CPUFREQ_SUSPENDCHANGE)) { loops_per_jiffy = cpufreq_scale(l_p_j_ref, l_p_j_ref_freq, ci->new); - dprintk("scaling loops_per_jiffy to %lu" + dprintk("scaling loops_per_jiffy to %lu " "for frequency %u kHz\n", loops_per_jiffy, ci->new); } } @@ -601,6 +601,31 @@ static ssize_t show_affected_cpus (struct cpufreq_policy * policy, char *buf) return i; } +static ssize_t store_scaling_setspeed(struct cpufreq_policy *policy, + const char *buf, size_t count) +{ + unsigned int freq = 0; + unsigned int ret; + + if (!policy->governor->store_setspeed) + return -EINVAL; + + ret = sscanf(buf, "%u", &freq); + if (ret != 1) + return -EINVAL; + + policy->governor->store_setspeed(policy, freq); + + return count; +} + +static ssize_t show_scaling_setspeed(struct cpufreq_policy *policy, char *buf) +{ + if (!policy->governor->show_setspeed) + return sprintf(buf, "<unsupported>\n"); + + return policy->governor->show_setspeed(policy, buf); +} #define define_one_ro(_name) \ static struct freq_attr _name = \ @@ -624,6 +649,7 @@ define_one_ro(affected_cpus); define_one_rw(scaling_min_freq); define_one_rw(scaling_max_freq); define_one_rw(scaling_governor); +define_one_rw(scaling_setspeed); static struct attribute * default_attrs[] = { &cpuinfo_min_freq.attr, @@ -634,6 +660,7 @@ static struct attribute * default_attrs[] = { &scaling_governor.attr, &scaling_driver.attr, &scaling_available_governors.attr, + &scaling_setspeed.attr, NULL }; @@ -1313,7 +1340,7 @@ static int cpufreq_resume(struct sys_device * sysdev) struct cpufreq_freqs freqs; if (!(cpufreq_driver->flags & CPUFREQ_PM_NO_WARN)) - dprintk("Warning: CPU frequency" + dprintk("Warning: CPU frequency " "is %u, cpufreq assumed %u kHz.\n", cur_freq, cpu_policy->cur); diff --git a/drivers/cpufreq/cpufreq_userspace.c b/drivers/cpufreq/cpufreq_userspace.c index f8cdde4bf6c..cb2ac01a41a 100644 --- a/drivers/cpufreq/cpufreq_userspace.c +++ b/drivers/cpufreq/cpufreq_userspace.c @@ -65,12 +65,12 @@ static struct notifier_block userspace_cpufreq_notifier_block = { /** * cpufreq_set - set the CPU frequency + * @policy: pointer to policy struct where freq is being set * @freq: target frequency in kHz - * @cpu: CPU for which the frequency is to be set * * Sets the CPU frequency to freq. */ -static int cpufreq_set(unsigned int freq, struct cpufreq_policy *policy) +static int cpufreq_set(struct cpufreq_policy *policy, unsigned int freq) { int ret = -EINVAL; @@ -102,34 +102,11 @@ static int cpufreq_set(unsigned int freq, struct cpufreq_policy *policy) } -/************************** sysfs interface ************************/ -static ssize_t show_speed (struct cpufreq_policy *policy, char *buf) +static ssize_t show_speed(struct cpufreq_policy *policy, char *buf) { - return sprintf (buf, "%u\n", cpu_cur_freq[policy->cpu]); + return sprintf(buf, "%u\n", cpu_cur_freq[policy->cpu]); } -static ssize_t -store_speed (struct cpufreq_policy *policy, const char *buf, size_t count) -{ - unsigned int freq = 0; - unsigned int ret; - - ret = sscanf (buf, "%u", &freq); - if (ret != 1) - return -EINVAL; - - cpufreq_set(freq, policy); - - return count; -} - -static struct freq_attr freq_attr_scaling_setspeed = -{ - .attr = { .name = "scaling_setspeed", .mode = 0644 }, - .show = show_speed, - .store = store_speed, -}; - static int cpufreq_governor_userspace(struct cpufreq_policy *policy, unsigned int event) { @@ -142,10 +119,6 @@ static int cpufreq_governor_userspace(struct cpufreq_policy *policy, return -EINVAL; BUG_ON(!policy->cur); mutex_lock(&userspace_mutex); - rc = sysfs_create_file (&policy->kobj, - &freq_attr_scaling_setspeed.attr); - if (rc) - goto start_out; if (cpus_using_userspace_governor == 0) { cpufreq_register_notifier( @@ -160,7 +133,7 @@ static int cpufreq_governor_userspace(struct cpufreq_policy *policy, cpu_cur_freq[cpu] = policy->cur; cpu_set_freq[cpu] = policy->cur; dprintk("managing cpu %u started (%u - %u kHz, currently %u kHz)\n", cpu, cpu_min_freq[cpu], cpu_max_freq[cpu], cpu_cur_freq[cpu]); -start_out: + mutex_unlock(&userspace_mutex); break; case CPUFREQ_GOV_STOP: @@ -176,7 +149,6 @@ start_out: cpu_min_freq[cpu] = 0; cpu_max_freq[cpu] = 0; cpu_set_freq[cpu] = 0; - sysfs_remove_file (&policy->kobj, &freq_attr_scaling_setspeed.attr); dprintk("managing cpu %u stopped\n", cpu); mutex_unlock(&userspace_mutex); break; @@ -211,6 +183,8 @@ start_out: struct cpufreq_governor cpufreq_gov_userspace = { .name = "userspace", .governor = cpufreq_governor_userspace, + .store_setspeed = cpufreq_set, + .show_setspeed = show_speed, .owner = THIS_MODULE, }; EXPORT_SYMBOL(cpufreq_gov_userspace); diff --git a/drivers/cpufreq/freq_table.c b/drivers/cpufreq/freq_table.c index 5409f3afb3f..ae6cd60d5c1 100644 --- a/drivers/cpufreq/freq_table.c +++ b/drivers/cpufreq/freq_table.c @@ -171,7 +171,7 @@ EXPORT_SYMBOL_GPL(cpufreq_frequency_table_target); static struct cpufreq_frequency_table *show_table[NR_CPUS]; /** - * show_scaling_governor - show the current policy for the specified CPU + * show_available_freqs - show available frequencies for the specified CPU */ static ssize_t show_available_freqs (struct cpufreq_policy *policy, char *buf) { diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 98b6b4fb425..2b382990fe5 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -97,7 +97,7 @@ config EDAC_I82975X config EDAC_I3000 tristate "Intel 3000/3010" - depends on EDAC_MM_EDAC && PCI && X86_32 + depends on EDAC_MM_EDAC && PCI && X86 help Support for error detection and correction on the Intel 3000 and 3010 server chipsets. @@ -123,6 +123,20 @@ config EDAC_I5000 Support for error detection and correction the Intel Greekcreek/Blackford chipsets. +config EDAC_MPC85XX + tristate "Freescale MPC85xx" + depends on EDAC_MM_EDAC && FSL_SOC && MPC85xx + help + Support for error detection and correction on the Freescale + MPC8560, MPC8540, MPC8548 + +config EDAC_MV64X60 + tristate "Marvell MV64x60" + depends on EDAC_MM_EDAC && MV64X60 + help + Support for error detection and correction on the Marvell + MV64360 and MV64460 chipsets. + config EDAC_PASEMI tristate "PA Semi PWRficient" depends on EDAC_MM_EDAC && PCI @@ -131,5 +145,12 @@ config EDAC_PASEMI Support for error detection and correction on PA Semi PWRficient. +config EDAC_CELL + tristate "Cell Broadband Engine memory controller" + depends on EDAC_MM_EDAC && PPC_CELL_NATIVE + help + Support for error detection and correction on the + Cell Broadband Engine internal memory controller + on platform without a hypervisor endif # EDAC diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 02c09f0ff15..83807731d4a 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -28,4 +28,7 @@ obj-$(CONFIG_EDAC_I3000) += i3000_edac.o obj-$(CONFIG_EDAC_I82860) += i82860_edac.o obj-$(CONFIG_EDAC_R82600) += r82600_edac.o obj-$(CONFIG_EDAC_PASEMI) += pasemi_edac.o +obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac.o +obj-$(CONFIG_EDAC_MV64X60) += mv64x60_edac.o +obj-$(CONFIG_EDAC_CELL) += cell_edac.o diff --git a/drivers/edac/cell_edac.c b/drivers/edac/cell_edac.c new file mode 100644 index 00000000000..b54112ffd28 --- /dev/null +++ b/drivers/edac/cell_edac.c @@ -0,0 +1,258 @@ +/* + * Cell MIC driver for ECC counting + * + * Copyright 2007 Benjamin Herrenschmidt, IBM Corp. + * <benh@kernel.crashing.org> + * + * This file may be distributed under the terms of the + * GNU General Public License. + */ +#undef DEBUG + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/stop_machine.h> +#include <linux/io.h> +#include <asm/machdep.h> +#include <asm/cell-regs.h> + +#include "edac_core.h" + +struct cell_edac_priv +{ + struct cbe_mic_tm_regs __iomem *regs; + int node; + int chanmask; +#ifdef DEBUG + u64 prev_fir; +#endif +}; + +static void cell_edac_count_ce(struct mem_ctl_info *mci, int chan, u64 ar) +{ + struct cell_edac_priv *priv = mci->pvt_info; + struct csrow_info *csrow = &mci->csrows[0]; + unsigned long address, pfn, offset; + + dev_dbg(mci->dev, "ECC CE err on node %d, channel %d, ar = 0x%016lx\n", + priv->node, chan, ar); + + /* Address decoding is likely a bit bogus, to dbl check */ + address = (ar & 0xffffffffe0000000ul) >> 29; + if (priv->chanmask == 0x3) + address = (address << 1) | chan; + pfn = address >> PAGE_SHIFT; + offset = address & ~PAGE_MASK; + + /* TODO: Decoding of the error addresss */ + edac_mc_handle_ce(mci, csrow->first_page + pfn, offset, + 0, 0, chan, ""); +} + +static void cell_edac_count_ue(struct mem_ctl_info *mci, int chan, u64 ar) +{ + struct cell_edac_priv *priv = mci->pvt_info; + struct csrow_info *csrow = &mci->csrows[0]; + unsigned long address, pfn, offset; + + dev_dbg(mci->dev, "ECC UE err on node %d, channel %d, ar = 0x%016lx\n", + priv->node, chan, ar); + + /* Address decoding is likely a bit bogus, to dbl check */ + address = (ar & 0xffffffffe0000000ul) >> 29; + if (priv->chanmask == 0x3) + address = (address << 1) | chan; + pfn = address >> PAGE_SHIFT; + offset = address & ~PAGE_MASK; + + /* TODO: Decoding of the error addresss */ + edac_mc_handle_ue(mci, csrow->first_page + pfn, offset, 0, ""); +} + +static void cell_edac_check(struct mem_ctl_info *mci) +{ + struct cell_edac_priv *priv = mci->pvt_info; + u64 fir, addreg, clear = 0; + + fir = in_be64(&priv->regs->mic_fir); +#ifdef DEBUG + if (fir != priv->prev_fir) { + dev_dbg(mci->dev, "fir change : 0x%016lx\n", fir); + priv->prev_fir = fir; + } +#endif + if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_SINGLE_0_ERR)) { + addreg = in_be64(&priv->regs->mic_df_ecc_address_0); + clear |= CBE_MIC_FIR_ECC_SINGLE_0_RESET; + cell_edac_count_ce(mci, 0, addreg); + } + if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_SINGLE_1_ERR)) { + addreg = in_be64(&priv->regs->mic_df_ecc_address_1); + clear |= CBE_MIC_FIR_ECC_SINGLE_1_RESET; + cell_edac_count_ce(mci, 1, addreg); + } + if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_MULTI_0_ERR)) { + addreg = in_be64(&priv->regs->mic_df_ecc_address_0); + clear |= CBE_MIC_FIR_ECC_MULTI_0_RESET; + cell_edac_count_ue(mci, 0, addreg); + } + if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_MULTI_1_ERR)) { + addreg = in_be64(&priv->regs->mic_df_ecc_address_1); + clear |= CBE_MIC_FIR_ECC_MULTI_1_RESET; + cell_edac_count_ue(mci, 1, addreg); + } + + /* The procedure for clearing FIR bits is a bit ... weird */ + if (clear) { + fir &= ~(CBE_MIC_FIR_ECC_ERR_MASK | CBE_MIC_FIR_ECC_SET_MASK); + fir |= CBE_MIC_FIR_ECC_RESET_MASK; + fir &= ~clear; + out_be64(&priv->regs->mic_fir, fir); + (void)in_be64(&priv->regs->mic_fir); + + mb(); /* sync up */ +#ifdef DEBUG + fir = in_be64(&priv->regs->mic_fir); + dev_dbg(mci->dev, "fir clear : 0x%016lx\n", fir); +#endif + } +} + +static void __devinit cell_edac_init_csrows(struct mem_ctl_info *mci) +{ + struct csrow_info *csrow = &mci->csrows[0]; + struct cell_edac_priv *priv = mci->pvt_info; + struct device_node *np; + + for (np = NULL; + (np = of_find_node_by_name(np, "memory")) != NULL;) { + struct resource r; + + /* We "know" that the Cell firmware only creates one entry + * in the "memory" nodes. If that changes, this code will + * need to be adapted. + */ + if (of_address_to_resource(np, 0, &r)) + continue; + if (of_node_to_nid(np) != priv->node) + continue; + csrow->first_page = r.start >> PAGE_SHIFT; + csrow->nr_pages = (r.end - r.start + 1) >> PAGE_SHIFT; + csrow->last_page = csrow->first_page + csrow->nr_pages - 1; + csrow->mtype = MEM_XDR; + csrow->edac_mode = EDAC_FLAG_EC | EDAC_FLAG_SECDED; + dev_dbg(mci->dev, + "Initialized on node %d, chanmask=0x%x," + " first_page=0x%lx, nr_pages=0x%x\n", + priv->node, priv->chanmask, + csrow->first_page, csrow->nr_pages); + break; + } +} + +static int __devinit cell_edac_probe(struct platform_device *pdev) +{ + struct cbe_mic_tm_regs __iomem *regs; + struct mem_ctl_info *mci; + struct cell_edac_priv *priv; + u64 reg; + int rc, chanmask; + + regs = cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(pdev->id)); + if (regs == NULL) + return -ENODEV; + + /* Get channel population */ + reg = in_be64(®s->mic_mnt_cfg); + dev_dbg(&pdev->dev, "MIC_MNT_CFG = 0x%016lx\n", reg); + chanmask = 0; + if (reg & CBE_MIC_MNT_CFG_CHAN_0_POP) + chanmask |= 0x1; + if (reg & CBE_MIC_MNT_CFG_CHAN_1_POP) + chanmask |= 0x2; + if (chanmask == 0) { + dev_warn(&pdev->dev, + "Yuck ! No channel populated ? Aborting !\n"); + return -ENODEV; + } + dev_dbg(&pdev->dev, "Initial FIR = 0x%016lx\n", + in_be64(®s->mic_fir)); + + /* Allocate & init EDAC MC data structure */ + mci = edac_mc_alloc(sizeof(struct cell_edac_priv), 1, + chanmask == 3 ? 2 : 1, pdev->id); + if (mci == NULL) + return -ENOMEM; + priv = mci->pvt_info; + priv->regs = regs; + priv->node = pdev->id; + priv->chanmask = chanmask; + mci->dev = &pdev->dev; + mci->mtype_cap = MEM_FLAG_XDR; + mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; + mci->edac_cap = EDAC_FLAG_EC | EDAC_FLAG_SECDED; + mci->mod_name = "cell_edac"; + mci->ctl_name = "MIC"; + mci->dev_name = pdev->dev.bus_id; + mci->edac_check = cell_edac_check; + cell_edac_init_csrows(mci); + + /* Register with EDAC core */ + rc = edac_mc_add_mc(mci); + if (rc) { + dev_err(&pdev->dev, "failed to register with EDAC core\n"); + edac_mc_free(mci); + return rc; + } + + return 0; +} + +static int __devexit cell_edac_remove(struct platform_device *pdev) +{ + struct mem_ctl_info *mci = edac_mc_del_mc(&pdev->dev); + if (mci) + edac_mc_free(mci); + return 0; +} + +static struct platform_driver cell_edac_driver = { + .driver = { + .name = "cbe-mic", + .owner = THIS_MODULE, + }, + .probe = cell_edac_probe, + .remove = cell_edac_remove, +}; + +static int __init cell_edac_init(void) +{ + /* Sanity check registers data structure */ + BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs, + mic_df_ecc_address_0) != 0xf8); + BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs, + mic_df_ecc_address_1) != 0x1b8); + BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs, + mic_df_config) != 0x218); + BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs, + mic_fir) != 0x230); + BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs, + mic_mnt_cfg) != 0x210); + BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs, + mic_exc) != 0x208); + + return platform_driver_register(&cell_edac_driver); +} + +static void __exit cell_edac_exit(void) +{ + platform_driver_unregister(&cell_edac_driver); +} + +module_init(cell_edac_init); +module_exit(cell_edac_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>"); +MODULE_DESCRIPTION("ECC counting for Cell MIC"); diff --git a/drivers/edac/edac_core.h b/drivers/edac/edac_core.h index 2d23e304f5e..a9aa845dbe7 100644 --- a/drivers/edac/edac_core.h +++ b/drivers/edac/edac_core.h @@ -136,6 +136,7 @@ enum mem_type { MEM_DDR2, /* DDR2 RAM */ MEM_FB_DDR2, /* fully buffered DDR2 */ MEM_RDDR2, /* Registered DDR2 RAM */ + MEM_XDR, /* Rambus XDR */ }; #define MEM_FLAG_EMPTY BIT(MEM_EMPTY) @@ -152,6 +153,7 @@ enum mem_type { #define MEM_FLAG_DDR2 BIT(MEM_DDR2) #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2) #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2) +#define MEM_FLAG_XDR BIT(MEM_XDR) /* chipset Error Detection and Correction capabilities and mode */ enum edac_type { diff --git a/drivers/edac/edac_device.c b/drivers/edac/edac_device.c index f3690a697cf..b9552bc03de 100644 --- a/drivers/edac/edac_device.c +++ b/drivers/edac/edac_device.c @@ -155,6 +155,10 @@ struct edac_device_ctl_info *edac_device_alloc_ctl_info( dev_ctl->instances = dev_inst; dev_ctl->pvt_info = pvt; + /* Default logging of CEs and UEs */ + dev_ctl->log_ce = 1; + dev_ctl->log_ue = 1; + /* Name of this edac device */ snprintf(dev_ctl->name,sizeof(dev_ctl->name),"%s",edac_device_name); @@ -436,7 +440,7 @@ static void edac_device_workq_function(struct work_struct *work_req) */ if (edac_dev->poll_msec == 1000) queue_delayed_work(edac_workqueue, &edac_dev->work, - round_jiffies(edac_dev->delay)); + round_jiffies_relative(edac_dev->delay)); else queue_delayed_work(edac_workqueue, &edac_dev->work, edac_dev->delay); @@ -468,7 +472,7 @@ void edac_device_workq_setup(struct edac_device_ctl_info *edac_dev, */ if (edac_dev->poll_msec == 1000) queue_delayed_work(edac_workqueue, &edac_dev->work, - round_jiffies(edac_dev->delay)); + round_jiffies_relative(edac_dev->delay)); else queue_delayed_work(edac_workqueue, &edac_dev->work, edac_dev->delay); diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c index 9aac88027fb..021d1879514 100644 --- a/drivers/edac/edac_mc_sysfs.c +++ b/drivers/edac/edac_mc_sysfs.c @@ -73,7 +73,8 @@ static const char *mem_types[] = { [MEM_RMBS] = "RMBS", [MEM_DDR2] = "Unbuffered-DDR2", [MEM_FB_DDR2] = "FullyBuffered-DDR2", - [MEM_RDDR2] = "Registered-DDR2" + [MEM_RDDR2] = "Registered-DDR2", + [MEM_XDR] = "XDR" }; static const char *dev_types[] = { diff --git a/drivers/edac/edac_pci.c b/drivers/edac/edac_pci.c index e0b47b74ec4..32be43576a8 100644 --- a/drivers/edac/edac_pci.c +++ b/drivers/edac/edac_pci.c @@ -246,7 +246,7 @@ static void edac_pci_workq_function(struct work_struct *work_req) /* if we are on a one second period, then use round */ msec = edac_pci_get_poll_msec(); if (msec == 1000) - delay = round_jiffies(msecs_to_jiffies(msec)); + delay = round_jiffies_relative(msecs_to_jiffies(msec)); else delay = msecs_to_jiffies(msec); diff --git a/drivers/edac/edac_pci_sysfs.c b/drivers/edac/edac_pci_sysfs.c index 5b075da9914..71c3195d370 100644 --- a/drivers/edac/edac_pci_sysfs.c +++ b/drivers/edac/edac_pci_sysfs.c @@ -558,8 +558,10 @@ static void edac_pci_dev_parity_test(struct pci_dev *dev) debugf4("PCI STATUS= 0x%04x %s\n", status, dev->dev.bus_id); - /* check the status reg for errors */ - if (status) { + /* check the status reg for errors on boards NOT marked as broken + * if broken, we cannot trust any of the status bits + */ + if (status && !dev->broken_parity_status) { if (status & (PCI_STATUS_SIG_SYSTEM_ERROR)) { edac_printk(KERN_CRIT, EDAC_PCI, "Signaled System Error on %s\n", @@ -593,8 +595,10 @@ static void edac_pci_dev_parity_test(struct pci_dev *dev) debugf4("PCI SEC_STATUS= 0x%04x %s\n", status, dev->dev.bus_id); - /* check the secondary status reg for errors */ - if (status) { + /* check the secondary status reg for errors, + * on NOT broken boards + */ + if (status && !dev->broken_parity_status) { if (status & (PCI_STATUS_SIG_SYSTEM_ERROR)) { edac_printk(KERN_CRIT, EDAC_PCI, "Bridge " "Signaled System Error on %s\n", diff --git a/drivers/edac/i3000_edac.c b/drivers/edac/i3000_edac.c index e895f9f887a..5d4292811c1 100644 --- a/drivers/edac/i3000_edac.c +++ b/drivers/edac/i3000_edac.c @@ -14,6 +14,7 @@ #include <linux/pci.h> #include <linux/pci_ids.h> #include <linux/slab.h> +#include <linux/edac.h> #include "edac_core.h" #define I3000_REVISION "1.1" @@ -30,105 +31,139 @@ #define I3000_MCHBAR_MASK 0xffffc000 #define I3000_MMR_WINDOW_SIZE 16384 -#define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b) - * - * 7:1 reserved - * 0 bit 32 of address - */ -#define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b) - * - * 31:7 address - * 6:1 reserved - * 0 Error channel 0/1 - */ -#define I3000_DEAP_GRAIN (1 << 7) -#define I3000_DEAP_PFN(edeap, deap) ((((edeap) & 1) << (32 - PAGE_SHIFT)) | \ - ((deap) >> PAGE_SHIFT)) -#define I3000_DEAP_OFFSET(deap) ((deap) & ~(I3000_DEAP_GRAIN-1) & ~PAGE_MASK) -#define I3000_DEAP_CHANNEL(deap) ((deap) & 1) - -#define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b) - * - * 7:0 DRAM ECC Syndrome - */ - -#define I3000_ERRSTS 0xc8 /* Error Status Register (16b) - * - * 15:12 reserved - * 11 MCH Thermal Sensor Event for SMI/SCI/SERR - * 10 reserved - * 9 LOCK to non-DRAM Memory Flag (LCKF) - * 8 Received Refresh Timeout Flag (RRTOF) - * 7:2 reserved - * 1 Multiple-bit DRAM ECC Error Flag (DMERR) - * 0 Single-bit DRAM ECC Error Flag (DSERR) - */ +#define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b) + * + * 7:1 reserved + * 0 bit 32 of address + */ +#define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b) + * + * 31:7 address + * 6:1 reserved + * 0 Error channel 0/1 + */ +#define I3000_DEAP_GRAIN (1 << 7) + +/* + * Helper functions to decode the DEAP/EDEAP hardware registers. + * + * The type promotion here is deliberate; we're deriving an + * unsigned long pfn and offset from hardware regs which are u8/u32. + */ + +static inline unsigned long deap_pfn(u8 edeap, u32 deap) +{ + deap >>= PAGE_SHIFT; + deap |= (edeap & 1) << (32 - PAGE_SHIFT); + return deap; +} + +static inline unsigned long deap_offset(u32 deap) +{ + return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK; +} + +static inline int deap_channel(u32 deap) +{ + return deap & 1; +} + +#define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b) + * + * 7:0 DRAM ECC Syndrome + */ + +#define I3000_ERRSTS 0xc8 /* Error Status Register (16b) + * + * 15:12 reserved + * 11 MCH Thermal Sensor Event + * for SMI/SCI/SERR + * 10 reserved + * 9 LOCK to non-DRAM Memory Flag (LCKF) + * 8 Received Refresh Timeout Flag (RRTOF) + * 7:2 reserved + * 1 Multi-bit DRAM ECC Error Flag (DMERR) + * 0 Single-bit DRAM ECC Error Flag (DSERR) + */ #define I3000_ERRSTS_BITS 0x0b03 /* bits which indicate errors */ #define I3000_ERRSTS_UE 0x0002 #define I3000_ERRSTS_CE 0x0001 -#define I3000_ERRCMD 0xca /* Error Command (16b) - * - * 15:12 reserved - * 11 SERR on MCH Thermal Sensor Event (TSESERR) - * 10 reserved - * 9 SERR on LOCK to non-DRAM Memory (LCKERR) - * 8 SERR on DRAM Refresh Timeout (DRTOERR) - * 7:2 reserved - * 1 SERR Multiple-Bit DRAM ECC Error (DMERR) - * 0 SERR on Single-Bit ECC Error (DSERR) - */ +#define I3000_ERRCMD 0xca /* Error Command (16b) + * + * 15:12 reserved + * 11 SERR on MCH Thermal Sensor Event + * (TSESERR) + * 10 reserved + * 9 SERR on LOCK to non-DRAM Memory + * (LCKERR) + * 8 SERR on DRAM Refresh Timeout + * (DRTOERR) + * 7:2 reserved + * 1 SERR Multi-Bit DRAM ECC Error + * (DMERR) + * 0 SERR on Single-Bit ECC Error + * (DSERR) + */ /* Intel MMIO register space - device 0 function 0 - MMR space */ #define I3000_DRB_SHIFT 25 /* 32MiB grain */ -#define I3000_C0DRB 0x100 /* Channel 0 DRAM Rank Boundary (8b x 4) - * - * 7:0 Channel 0 DRAM Rank Boundary Address - */ -#define I3000_C1DRB 0x180 /* Channel 1 DRAM Rank Boundary (8b x 4) - * - * 7:0 Channel 1 DRAM Rank Boundary Address - */ - -#define I3000_C0DRA 0x108 /* Channel 0 DRAM Rank Attribute (8b x 2) - * - * 7 reserved - * 6:4 DRAM odd Rank Attribute - * 3 reserved - * 2:0 DRAM even Rank Attribute - * - * Each attribute defines the page - * size of the corresponding rank: - * 000: unpopulated - * 001: reserved - * 010: 4 KB - * 011: 8 KB - * 100: 16 KB - * Others: reserved - */ -#define I3000_C1DRA 0x188 /* Channel 1 DRAM Rank Attribute (8b x 2) */ -#define ODD_RANK_ATTRIB(dra) (((dra) & 0x70) >> 4) -#define EVEN_RANK_ATTRIB(dra) ((dra) & 0x07) - -#define I3000_C0DRC0 0x120 /* DRAM Controller Mode 0 (32b) - * - * 31:30 reserved - * 29 Initialization Complete (IC) - * 28:11 reserved - * 10:8 Refresh Mode Select (RMS) - * 7 reserved - * 6:4 Mode Select (SMS) - * 3:2 reserved - * 1:0 DRAM Type (DT) - */ - -#define I3000_C0DRC1 0x124 /* DRAM Controller Mode 1 (32b) - * - * 31 Enhanced Addressing Enable (ENHADE) - * 30:0 reserved - */ +#define I3000_C0DRB 0x100 /* Channel 0 DRAM Rank Boundary (8b x 4) + * + * 7:0 Channel 0 DRAM Rank Boundary Address + */ +#define I3000_C1DRB 0x180 /* Channel 1 DRAM Rank Boundary (8b x 4) + * + * 7:0 Channel 1 DRAM Rank Boundary Address + */ + +#define I3000_C0DRA 0x108 /* Channel 0 DRAM Rank Attribute (8b x 2) + * + * 7 reserved + * 6:4 DRAM odd Rank Attribute + * 3 reserved + * 2:0 DRAM even Rank Attribute + * + * Each attribute defines the page + * size of the corresponding rank: + * 000: unpopulated + * 001: reserved + * 010: 4 KB + * 011: 8 KB + * 100: 16 KB + * Others: reserved + */ +#define I3000_C1DRA 0x188 /* Channel 1 DRAM Rank Attribute (8b x 2) */ + +static inline unsigned char odd_rank_attrib(unsigned char dra) +{ + return (dra & 0x70) >> 4; +} + +static inline unsigned char even_rank_attrib(unsigned char dra) +{ + return dra & 0x07; +} + +#define I3000_C0DRC0 0x120 /* DRAM Controller Mode 0 (32b) + * + * 31:30 reserved + * 29 Initialization Complete (IC) + * 28:11 reserved + * 10:8 Refresh Mode Select (RMS) + * 7 reserved + * 6:4 Mode Select (SMS) + * 3:2 reserved + * 1:0 DRAM Type (DT) + */ + +#define I3000_C0DRC1 0x124 /* DRAM Controller Mode 1 (32b) + * + * 31 Enhanced Addressing Enable (ENHADE) + * 30:0 reserved + */ enum i3000p_chips { I3000 = 0, @@ -187,7 +222,8 @@ static void i3000_get_error_info(struct mem_ctl_info *mci, pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn); } - /* Clear any error bits. + /* + * Clear any error bits. * (Yes, we really clear bits by writing 1 to them.) */ pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS, @@ -198,8 +234,8 @@ static int i3000_process_error_info(struct mem_ctl_info *mci, struct i3000_error_info *info, int handle_errors) { - int row, multi_chan; - int pfn, offset, channel; + int row, multi_chan, channel; + unsigned long pfn, offset; multi_chan = mci->csrows[0].nr_channels - 1; @@ -214,9 +250,9 @@ static int i3000_process_error_info(struct mem_ctl_info *mci, info->errsts = info->errsts2; } - pfn = I3000_DEAP_PFN(info->edeap, info->deap); - offset = I3000_DEAP_OFFSET(info->deap); - channel = I3000_DEAP_CHANNEL(info->deap); + pfn = deap_pfn(info->edeap, info->deap); + offset = deap_offset(info->deap); + channel = deap_channel(info->deap); row = edac_mc_find_csrow_by_page(mci, pfn); @@ -245,16 +281,18 @@ static int i3000_is_interleaved(const unsigned char *c0dra, { int i; - /* If the channels aren't populated identically then + /* + * If the channels aren't populated identically then * we're not interleaved. */ for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++) - if (ODD_RANK_ATTRIB(c0dra[i]) != ODD_RANK_ATTRIB(c1dra[i]) || - EVEN_RANK_ATTRIB(c0dra[i]) != - EVEN_RANK_ATTRIB(c1dra[i])) + if (odd_rank_attrib(c0dra[i]) != odd_rank_attrib(c1dra[i]) || + even_rank_attrib(c0dra[i]) != + even_rank_attrib(c1dra[i])) return 0; - /* If the rank boundaries for the two channels are different + /* + * If the rank boundaries for the two channels are different * then we're not interleaved. */ for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) @@ -288,6 +326,15 @@ static int i3000_probe1(struct pci_dev *pdev, int dev_idx) return -ENODEV; } + switch (edac_op_state) { + case EDAC_OPSTATE_POLL: + case EDAC_OPSTATE_NMI: + break; + default: + edac_op_state = EDAC_OPSTATE_POLL; + break; + } + c0dra[0] = readb(window + I3000_C0DRA + 0); /* ranks 0,1 */ c0dra[1] = readb(window + I3000_C0DRA + 1); /* ranks 2,3 */ c1dra[0] = readb(window + I3000_C1DRA + 0); /* ranks 0,1 */ @@ -300,7 +347,8 @@ static int i3000_probe1(struct pci_dev *pdev, int dev_idx) iounmap(window); - /* Figure out how many channels we have. + /* + * Figure out how many channels we have. * * If we have what the datasheet calls "asymmetric channels" * (essentially the same as what was called "virtual single @@ -363,7 +411,8 @@ static int i3000_probe1(struct pci_dev *pdev, int dev_idx) csrow->edac_mode = EDAC_UNKNOWN; } - /* Clear any error bits. + /* + * Clear any error bits. * (Yes, we really clear bits by writing 1 to them.) */ pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS, @@ -390,7 +439,7 @@ static int i3000_probe1(struct pci_dev *pdev, int dev_idx) debugf3("MC: %s(): success\n", __func__); return 0; - fail: +fail: if (mci) edac_mc_free(mci); @@ -409,7 +458,7 @@ static int __devinit i3000_init_one(struct pci_dev *pdev, return -EIO; rc = i3000_probe1(pdev, ent->driver_data); - if (mci_pdev == NULL) + if (!mci_pdev) mci_pdev = pci_dev_get(pdev); return rc; @@ -424,7 +473,8 @@ static void __devexit i3000_remove_one(struct pci_dev *pdev) if (i3000_pci) edac_pci_release_generic_ctl(i3000_pci); - if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) + mci = edac_mc_del_mc(&pdev->dev); + if (!mci) return; edac_mc_free(mci); @@ -457,7 +507,7 @@ static int __init i3000_init(void) if (pci_rc < 0) goto fail0; - if (mci_pdev == NULL) { + if (!mci_pdev) { i3000_registered = 0; mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3000_HB, NULL); @@ -504,3 +554,6 @@ module_exit(i3000_exit); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott"); MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers"); + +module_param(edac_op_state, int, 0444); +MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c new file mode 100644 index 00000000000..065732ddf40 --- /dev/null +++ b/drivers/edac/mpc85xx_edac.c @@ -0,0 +1,1043 @@ +/* + * Freescale MPC85xx Memory Controller kenel module + * + * Author: Dave Jiang <djiang@mvista.com> + * + * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + */ +#include <linux/module.h> +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/interrupt.h> +#include <linux/ctype.h> +#include <linux/io.h> +#include <linux/mod_devicetable.h> +#include <linux/edac.h> + +#include <linux/of_platform.h> +#include <linux/of_device.h> +#include <asm/mpc85xx.h> +#include "edac_module.h" +#include "edac_core.h" +#include "mpc85xx_edac.h" + +static int edac_dev_idx; +static int edac_pci_idx; +static int edac_mc_idx; + +static u32 orig_ddr_err_disable; +static u32 orig_ddr_err_sbe; + +/* + * PCI Err defines + */ +#ifdef CONFIG_PCI +static u32 orig_pci_err_cap_dr; +static u32 orig_pci_err_en; +#endif + +static u32 orig_l2_err_disable; +static u32 orig_hid1; + +static const char *mpc85xx_ctl_name = "MPC85xx"; + +/************************ MC SYSFS parts ***********************************/ + +static ssize_t mpc85xx_mc_inject_data_hi_show(struct mem_ctl_info *mci, + char *data) +{ + struct mpc85xx_mc_pdata *pdata = mci->pvt_info; + return sprintf(data, "0x%08x", + in_be32(pdata->mc_vbase + + MPC85XX_MC_DATA_ERR_INJECT_HI)); +} + +static ssize_t mpc85xx_mc_inject_data_lo_show(struct mem_ctl_info *mci, + char *data) +{ + struct mpc85xx_mc_pdata *pdata = mci->pvt_info; + return sprintf(data, "0x%08x", + in_be32(pdata->mc_vbase + + MPC85XX_MC_DATA_ERR_INJECT_LO)); +} + +static ssize_t mpc85xx_mc_inject_ctrl_show(struct mem_ctl_info *mci, char *data) +{ + struct mpc85xx_mc_pdata *pdata = mci->pvt_info; + return sprintf(data, "0x%08x", + in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT)); +} + +static ssize_t mpc85xx_mc_inject_data_hi_store(struct mem_ctl_info *mci, + const char *data, size_t count) +{ + struct mpc85xx_mc_pdata *pdata = mci->pvt_info; + if (isdigit(*data)) { + out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI, + simple_strtoul(data, NULL, 0)); + return count; + } + return 0; +} + +static ssize_t mpc85xx_mc_inject_data_lo_store(struct mem_ctl_info *mci, + const char *data, size_t count) +{ + struct mpc85xx_mc_pdata *pdata = mci->pvt_info; + if (isdigit(*data)) { + out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO, + simple_strtoul(data, NULL, 0)); + return count; + } + return 0; +} + +static ssize_t mpc85xx_mc_inject_ctrl_store(struct mem_ctl_info *mci, + const char *data, size_t count) +{ + struct mpc85xx_mc_pdata *pdata = mci->pvt_info; + if (isdigit(*data)) { + out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT, + simple_strtoul(data, NULL, 0)); + return count; + } + return 0; +} + +static struct mcidev_sysfs_attribute mpc85xx_mc_sysfs_attributes[] = { + { + .attr = { + .name = "inject_data_hi", + .mode = (S_IRUGO | S_IWUSR) + }, + .show = mpc85xx_mc_inject_data_hi_show, + .store = mpc85xx_mc_inject_data_hi_store}, + { + .attr = { + .name = "inject_data_lo", + .mode = (S_IRUGO | S_IWUSR) + }, + .show = mpc85xx_mc_inject_data_lo_show, + .store = mpc85xx_mc_inject_data_lo_store}, + { + .attr = { + .name = "inject_ctrl", + .mode = (S_IRUGO | S_IWUSR) + }, + .show = mpc85xx_mc_inject_ctrl_show, + .store = mpc85xx_mc_inject_ctrl_store}, + + /* End of list */ + { + .attr = {.name = NULL} + } +}; + +static void mpc85xx_set_mc_sysfs_attributes(struct mem_ctl_info *mci) +{ + mci->mc_driver_sysfs_attributes = mpc85xx_mc_sysfs_attributes; +} + +/**************************** PCI Err device ***************************/ +#ifdef CONFIG_PCI + +static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci) +{ + struct mpc85xx_pci_pdata *pdata = pci->pvt_info; + u32 err_detect; + + err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); + + /* master aborts can happen during PCI config cycles */ + if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) { + out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); + return; + } + + printk(KERN_ERR "PCI error(s) detected\n"); + printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect); + + printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n", + in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); + printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n", + in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); + printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n", + in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); + printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n", + in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); + printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n", + in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); + + /* clear error bits */ + out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); + + if (err_detect & PCI_EDE_PERR_MASK) + edac_pci_handle_pe(pci, pci->ctl_name); + + if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK) + edac_pci_handle_npe(pci, pci->ctl_name); +} + +static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id) +{ + struct edac_pci_ctl_info *pci = dev_id; + struct mpc85xx_pci_pdata *pdata = pci->pvt_info; + u32 err_detect; + + err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); + + if (!err_detect) + return IRQ_NONE; + + mpc85xx_pci_check(pci); + + return IRQ_HANDLED; +} + +static int __devinit mpc85xx_pci_err_probe(struct platform_device *pdev) +{ + struct edac_pci_ctl_info *pci; + struct mpc85xx_pci_pdata *pdata; + struct resource *r; + int res = 0; + + if (!devres_open_group(&pdev->dev, mpc85xx_pci_err_probe, GFP_KERNEL)) + return -ENOMEM; + + pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err"); + if (!pci) + return -ENOMEM; + + pdata = pci->pvt_info; + pdata->name = "mpc85xx_pci_err"; + pdata->irq = NO_IRQ; + platform_set_drvdata(pdev, pci); + pci->dev = &pdev->dev; + pci->mod_name = EDAC_MOD_STR; + pci->ctl_name = pdata->name; + pci->dev_name = pdev->dev.bus_id; + + if (edac_op_state == EDAC_OPSTATE_POLL) + pci->edac_check = mpc85xx_pci_check; + + pdata->edac_idx = edac_pci_idx++; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + printk(KERN_ERR "%s: Unable to get resource for " + "PCI err regs\n", __func__); + goto err; + } + + if (!devm_request_mem_region(&pdev->dev, r->start, + r->end - r->start + 1, pdata->name)) { + printk(KERN_ERR "%s: Error while requesting mem region\n", + __func__); + res = -EBUSY; + goto err; + } + + pdata->pci_vbase = devm_ioremap(&pdev->dev, r->start, + r->end - r->start + 1); + if (!pdata->pci_vbase) { + printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__); + res = -ENOMEM; + goto err; + } + + orig_pci_err_cap_dr = + in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR); + + /* PCI master abort is expected during config cycles */ + out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40); + + orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); + + /* disable master abort reporting */ + out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40); + + /* clear error bits */ + out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0); + + if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { + debugf3("%s(): failed edac_pci_add_device()\n", __func__); + goto err; + } + + if (edac_op_state == EDAC_OPSTATE_INT) { + pdata->irq = platform_get_irq(pdev, 0); + res = devm_request_irq(&pdev->dev, pdata->irq, + mpc85xx_pci_isr, IRQF_DISABLED, + "[EDAC] PCI err", pci); + if (res < 0) { + printk(KERN_ERR + "%s: Unable to requiest irq %d for " + "MPC85xx PCI err\n", __func__, pdata->irq); + res = -ENODEV; + goto err2; + } + + printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n", + pdata->irq); + } + + devres_remove_group(&pdev->dev, mpc85xx_pci_err_probe); + debugf3("%s(): success\n", __func__); + printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n"); + + return 0; + +err2: + edac_pci_del_device(&pdev->dev); +err: + edac_pci_free_ctl_info(pci); + devres_release_group(&pdev->dev, mpc85xx_pci_err_probe); + return res; +} + +static int mpc85xx_pci_err_remove(struct platform_device *pdev) +{ + struct edac_pci_ctl_info *pci = platform_get_drvdata(pdev); + struct mpc85xx_pci_pdata *pdata = pci->pvt_info; + + debugf0("%s()\n", __func__); + + out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, + orig_pci_err_cap_dr); + + out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en); + + edac_pci_del_device(pci->dev); + + if (edac_op_state == EDAC_OPSTATE_INT) + irq_dispose_mapping(pdata->irq); + + edac_pci_free_ctl_info(pci); + + return 0; +} + +static struct platform_driver mpc85xx_pci_err_driver = { + .probe = mpc85xx_pci_err_probe, + .remove = __devexit_p(mpc85xx_pci_err_remove), + .driver = { + .name = "mpc85xx_pci_err", + } +}; + +#endif /* CONFIG_PCI */ + +/**************************** L2 Err device ***************************/ + +/************************ L2 SYSFS parts ***********************************/ + +static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info + *edac_dev, char *data) +{ + struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; + return sprintf(data, "0x%08x", + in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI)); +} + +static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info + *edac_dev, char *data) +{ + struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; + return sprintf(data, "0x%08x", + in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO)); +} + +static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info + *edac_dev, char *data) +{ + struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; + return sprintf(data, "0x%08x", + in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL)); +} + +static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info + *edac_dev, const char *data, + size_t count) +{ + struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; + if (isdigit(*data)) { + out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI, + simple_strtoul(data, NULL, 0)); + return count; + } + return 0; +} + +static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info + *edac_dev, const char *data, + size_t count) +{ + struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; + if (isdigit(*data)) { + out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO, + simple_strtoul(data, NULL, 0)); + return count; + } + return 0; +} + +static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info + *edac_dev, const char *data, + size_t count) +{ + struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; + if (isdigit(*data)) { + out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL, + simple_strtoul(data, NULL, 0)); + return count; + } + return 0; +} + +static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = { + { + .attr = { + .name = "inject_data_hi", + .mode = (S_IRUGO | S_IWUSR) + }, + .show = mpc85xx_l2_inject_data_hi_show, + .store = mpc85xx_l2_inject_data_hi_store}, + { + .attr = { + .name = "inject_data_lo", + .mode = (S_IRUGO | S_IWUSR) + }, + .show = mpc85xx_l2_inject_data_lo_show, + .store = mpc85xx_l2_inject_data_lo_store}, + { + .attr = { + .name = "inject_ctrl", + .mode = (S_IRUGO | S_IWUSR) + }, + .show = mpc85xx_l2_inject_ctrl_show, + .store = mpc85xx_l2_inject_ctrl_store}, + + /* End of list */ + { + .attr = {.name = NULL} + } +}; + +static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info + *edac_dev) +{ + edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes; +} + +/***************************** L2 ops ***********************************/ + +static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev) +{ + struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; + u32 err_detect; + + err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); + + if (!(err_detect & L2_EDE_MASK)) + return; + + printk(KERN_ERR "ECC Error in CPU L2 cache\n"); + printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect); + printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n", + in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI)); + printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n", + in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO)); + printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n", + in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC)); + printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n", + in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR)); + printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n", + in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR)); + + /* clear error detect register */ + out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect); + + if (err_detect & L2_EDE_CE_MASK) + edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); + + if (err_detect & L2_EDE_UE_MASK) + edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); +} + +static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id) +{ + struct edac_device_ctl_info *edac_dev = dev_id; + struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; + u32 err_detect; + + err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); + + if (!(err_detect & L2_EDE_MASK)) + return IRQ_NONE; + + mpc85xx_l2_check(edac_dev); + + return IRQ_HANDLED; +} + +static int __devinit mpc85xx_l2_err_probe(struct of_device *op, + const struct of_device_id *match) +{ + struct edac_device_ctl_info *edac_dev; + struct mpc85xx_l2_pdata *pdata; + struct resource r; + int res; + + if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL)) + return -ENOMEM; + + edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata), + "cpu", 1, "L", 1, 2, NULL, 0, + edac_dev_idx); + if (!edac_dev) { + devres_release_group(&op->dev, mpc85xx_l2_err_probe); + return -ENOMEM; + } + + pdata = edac_dev->pvt_info; + pdata->name = "mpc85xx_l2_err"; + pdata->irq = NO_IRQ; + edac_dev->dev = &op->dev; + dev_set_drvdata(edac_dev->dev, edac_dev); + edac_dev->ctl_name = pdata->name; + edac_dev->dev_name = pdata->name; + + res = of_address_to_resource(op->node, 0, &r); + if (res) { + printk(KERN_ERR "%s: Unable to get resource for " + "L2 err regs\n", __func__); + goto err; + } + + /* we only need the error registers */ + r.start += 0xe00; + + if (!devm_request_mem_region(&op->dev, r.start, + r.end - r.start + 1, pdata->name)) { + printk(KERN_ERR "%s: Error while requesting mem region\n", + __func__); + res = -EBUSY; + goto err; + } + + pdata->l2_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1); + if (!pdata->l2_vbase) { + printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__); + res = -ENOMEM; + goto err; + } + + out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0); + + orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS); + + /* clear the err_dis */ + out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0); + + edac_dev->mod_name = EDAC_MOD_STR; + + if (edac_op_state == EDAC_OPSTATE_POLL) + edac_dev->edac_check = mpc85xx_l2_check; + + mpc85xx_set_l2_sysfs_attributes(edac_dev); + + pdata->edac_idx = edac_dev_idx++; + + if (edac_device_add_device(edac_dev) > 0) { + debugf3("%s(): failed edac_device_add_device()\n", __func__); + goto err; + } + + if (edac_op_state == EDAC_OPSTATE_INT) { + pdata->irq = irq_of_parse_and_map(op->node, 0); + res = devm_request_irq(&op->dev, pdata->irq, + mpc85xx_l2_isr, IRQF_DISABLED, + "[EDAC] L2 err", edac_dev); + if (res < 0) { + printk(KERN_ERR + "%s: Unable to requiest irq %d for " + "MPC85xx L2 err\n", __func__, pdata->irq); + irq_dispose_mapping(pdata->irq); + res = -ENODEV; + goto err2; + } + + printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n", + pdata->irq); + + edac_dev->op_state = OP_RUNNING_INTERRUPT; + + out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK); + } + + devres_remove_group(&op->dev, mpc85xx_l2_err_probe); + + debugf3("%s(): success\n", __func__); + printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n"); + + return 0; + +err2: + edac_device_del_device(&op->dev); +err: + devres_release_group(&op->dev, mpc85xx_l2_err_probe); + edac_device_free_ctl_info(edac_dev); + return res; +} + +static int mpc85xx_l2_err_remove(struct of_device *op) +{ + struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev); + struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; + + debugf0("%s()\n", __func__); + + if (edac_op_state == EDAC_OPSTATE_INT) { + out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0); + irq_dispose_mapping(pdata->irq); + } + + out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable); + edac_device_del_device(&op->dev); + edac_device_free_ctl_info(edac_dev); + return 0; +} + +static struct of_device_id mpc85xx_l2_err_of_match[] = { + { + .compatible = "fsl,8540-l2-cache-controller", + }, + { + .compatible = "fsl,8541-l2-cache-controller", + }, + { + .compatible = "fsl,8544-l2-cache-controller", + }, + { + .compatible = "fsl,8548-l2-cache-controller", + }, + { + .compatible = "fsl,8555-l2-cache-controller", + }, + { + .compatible = "fsl,8568-l2-cache-controller", + }, + {}, +}; + +static struct of_platform_driver mpc85xx_l2_err_driver = { + .owner = THIS_MODULE, + .name = "mpc85xx_l2_err", + .match_table = mpc85xx_l2_err_of_match, + .probe = mpc85xx_l2_err_probe, + .remove = mpc85xx_l2_err_remove, + .driver = { + .name = "mpc85xx_l2_err", + .owner = THIS_MODULE, + }, +}; + +/**************************** MC Err device ***************************/ + +static void mpc85xx_mc_check(struct mem_ctl_info *mci) +{ + struct mpc85xx_mc_pdata *pdata = mci->pvt_info; + struct csrow_info *csrow; + u32 err_detect; + u32 syndrome; + u32 err_addr; + u32 pfn; + int row_index; + + err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); + if (err_detect) + return; + + mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n", + err_detect); + + /* no more processing if not ECC bit errors */ + if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) { + out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); + return; + } + + syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC); + err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS); + pfn = err_addr >> PAGE_SHIFT; + + for (row_index = 0; row_index < mci->nr_csrows; row_index++) { + csrow = &mci->csrows[row_index]; + if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page)) + break; + } + + mpc85xx_mc_printk(mci, KERN_ERR, "Capture Data High: %#8.8x\n", + in_be32(pdata->mc_vbase + + MPC85XX_MC_CAPTURE_DATA_HI)); + mpc85xx_mc_printk(mci, KERN_ERR, "Capture Data Low: %#8.8x\n", + in_be32(pdata->mc_vbase + + MPC85XX_MC_CAPTURE_DATA_LO)); + mpc85xx_mc_printk(mci, KERN_ERR, "syndrome: %#8.8x\n", syndrome); + mpc85xx_mc_printk(mci, KERN_ERR, "err addr: %#8.8x\n", err_addr); + mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn); + + /* we are out of range */ + if (row_index == mci->nr_csrows) + mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n"); + + if (err_detect & DDR_EDE_SBE) + edac_mc_handle_ce(mci, pfn, err_addr & PAGE_MASK, + syndrome, row_index, 0, mci->ctl_name); + + if (err_detect & DDR_EDE_MBE) + edac_mc_handle_ue(mci, pfn, err_addr & PAGE_MASK, + row_index, mci->ctl_name); + + out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); +} + +static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id) +{ + struct mem_ctl_info *mci = dev_id; + struct mpc85xx_mc_pdata *pdata = mci->pvt_info; + u32 err_detect; + + err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); + if (!err_detect) + return IRQ_NONE; + + mpc85xx_mc_check(mci); + + return IRQ_HANDLED; +} + +static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci) +{ + struct mpc85xx_mc_pdata *pdata = mci->pvt_info; + struct csrow_info *csrow; + u32 sdram_ctl; + u32 sdtype; + enum mem_type mtype; + u32 cs_bnds; + int index; + + sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); + + sdtype = sdram_ctl & DSC_SDTYPE_MASK; + if (sdram_ctl & DSC_RD_EN) { + switch (sdtype) { + case DSC_SDTYPE_DDR: + mtype = MEM_RDDR; + break; + case DSC_SDTYPE_DDR2: + mtype = MEM_RDDR2; + break; + default: + mtype = MEM_UNKNOWN; + break; + } + } else { + switch (sdtype) { + case DSC_SDTYPE_DDR: + mtype = MEM_DDR; + break; + case DSC_SDTYPE_DDR2: + mtype = MEM_DDR2; + break; + default: + mtype = MEM_UNKNOWN; + break; + } + } + + for (index = 0; index < mci->nr_csrows; index++) { + u32 start; + u32 end; + + csrow = &mci->csrows[index]; + cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 + + (index * MPC85XX_MC_CS_BNDS_OFS)); + start = (cs_bnds & 0xfff0000) << 4; + end = ((cs_bnds & 0xfff) << 20); + if (start) + start |= 0xfffff; + if (end) + end |= 0xfffff; + + if (start == end) + continue; /* not populated */ + + csrow->first_page = start >> PAGE_SHIFT; + csrow->last_page = end >> PAGE_SHIFT; + csrow->nr_pages = csrow->last_page + 1 - csrow->first_page; + csrow->grain = 8; + csrow->mtype = mtype; + csrow->dtype = DEV_UNKNOWN; + if (sdram_ctl & DSC_X32_EN) + csrow->dtype = DEV_X32; + csrow->edac_mode = EDAC_SECDED; + } +} + +static int __devinit mpc85xx_mc_err_probe(struct of_device *op, + const struct of_device_id *match) +{ + struct mem_ctl_info *mci; + struct mpc85xx_mc_pdata *pdata; + struct resource r; + u32 sdram_ctl; + int res; + + if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL)) + return -ENOMEM; + + mci = edac_mc_alloc(sizeof(*pdata), 4, 1, edac_mc_idx); + if (!mci) { + devres_release_group(&op->dev, mpc85xx_mc_err_probe); + return -ENOMEM; + } + + pdata = mci->pvt_info; + pdata->name = "mpc85xx_mc_err"; + pdata->irq = NO_IRQ; + mci->dev = &op->dev; + pdata->edac_idx = edac_mc_idx++; + dev_set_drvdata(mci->dev, mci); + mci->ctl_name = pdata->name; + mci->dev_name = pdata->name; + + res = of_address_to_resource(op->node, 0, &r); + if (res) { + printk(KERN_ERR "%s: Unable to get resource for MC err regs\n", + __func__); + goto err; + } + + if (!devm_request_mem_region(&op->dev, r.start, + r.end - r.start + 1, pdata->name)) { + printk(KERN_ERR "%s: Error while requesting mem region\n", + __func__); + res = -EBUSY; + goto err; + } + + pdata->mc_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1); + if (!pdata->mc_vbase) { + printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__); + res = -ENOMEM; + goto err; + } + + sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); + if (!(sdram_ctl & DSC_ECC_EN)) { + /* no ECC */ + printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__); + res = -ENODEV; + goto err; + } + + debugf3("%s(): init mci\n", __func__); + mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 | + MEM_FLAG_DDR | MEM_FLAG_DDR2; + mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; + mci->edac_cap = EDAC_FLAG_SECDED; + mci->mod_name = EDAC_MOD_STR; + mci->mod_ver = MPC85XX_REVISION; + + if (edac_op_state == EDAC_OPSTATE_POLL) + mci->edac_check = mpc85xx_mc_check; + + mci->ctl_page_to_phys = NULL; + + mci->scrub_mode = SCRUB_SW_SRC; + + mpc85xx_set_mc_sysfs_attributes(mci); + + mpc85xx_init_csrows(mci); + +#ifdef CONFIG_EDAC_DEBUG + edac_mc_register_mcidev_debug((struct attribute **)debug_attr); +#endif + + /* store the original error disable bits */ + orig_ddr_err_disable = + in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE); + out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0); + + /* clear all error bits */ + out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0); + + if (edac_mc_add_mc(mci)) { + debugf3("%s(): failed edac_mc_add_mc()\n", __func__); + goto err; + } + + if (edac_op_state == EDAC_OPSTATE_INT) { + out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, + DDR_EIE_MBEE | DDR_EIE_SBEE); + + /* store the original error management threshold */ + orig_ddr_err_sbe = in_be32(pdata->mc_vbase + + MPC85XX_MC_ERR_SBE) & 0xff0000; + + /* set threshold to 1 error per interrupt */ + out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000); + + /* register interrupts */ + pdata->irq = irq_of_parse_and_map(op->node, 0); + res = devm_request_irq(&op->dev, pdata->irq, + mpc85xx_mc_isr, IRQF_DISABLED, + "[EDAC] MC err", mci); + if (res < 0) { + printk(KERN_ERR "%s: Unable to request irq %d for " + "MPC85xx DRAM ERR\n", __func__, pdata->irq); + irq_dispose_mapping(pdata->irq); + res = -ENODEV; + goto err2; + } + + printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n", + pdata->irq); + } + + devres_remove_group(&op->dev, mpc85xx_mc_err_probe); + debugf3("%s(): success\n", __func__); + printk(KERN_INFO EDAC_MOD_STR " MC err registered\n"); + + return 0; + +err2: + edac_mc_del_mc(&op->dev); +err: + devres_release_group(&op->dev, mpc85xx_mc_err_probe); + edac_mc_free(mci); + return res; +} + +static int mpc85xx_mc_err_remove(struct of_device *op) +{ + struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); + struct mpc85xx_mc_pdata *pdata = mci->pvt_info; + + debugf0("%s()\n", __func__); + + if (edac_op_state == EDAC_OPSTATE_INT) { + out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0); + irq_dispose_mapping(pdata->irq); + } + + out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, + orig_ddr_err_disable); + out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe); + + edac_mc_del_mc(&op->dev); + edac_mc_free(mci); + return 0; +} + +static struct of_device_id mpc85xx_mc_err_of_match[] = { + { + .compatible = "fsl,8540-memory-controller", + }, + { + .compatible = "fsl,8541-memory-controller", + }, + { + .compatible = "fsl,8544-memory-controller", + }, + { + .compatible = "fsl,8548-memory-controller", + }, + { + .compatible = "fsl,8555-memory-controller", + }, + { + .compatible = "fsl,8568-memory-controller", + }, + {}, +}; + +static struct of_platform_driver mpc85xx_mc_err_driver = { + .owner = THIS_MODULE, + .name = "mpc85xx_mc_err", + .match_table = mpc85xx_mc_err_of_match, + .probe = mpc85xx_mc_err_probe, + .remove = mpc85xx_mc_err_remove, + .driver = { + .name = "mpc85xx_mc_err", + .owner = THIS_MODULE, + }, +}; + +static int __init mpc85xx_mc_init(void) +{ + int res = 0; + + printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, " + "(C) 2006 Montavista Software\n"); + + /* make sure error reporting method is sane */ + switch (edac_op_state) { + case EDAC_OPSTATE_POLL: + case EDAC_OPSTATE_INT: + break; + default: + edac_op_state = EDAC_OPSTATE_INT; + break; + } + + res = of_register_platform_driver(&mpc85xx_mc_err_driver); + if (res) + printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n"); + + res = of_register_platform_driver(&mpc85xx_l2_err_driver); + if (res) + printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n"); + +#ifdef CONFIG_PCI + res = platform_driver_register(&mpc85xx_pci_err_driver); + if (res) + printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n"); +#endif + + /* + * need to clear HID1[RFXE] to disable machine check int + * so we can catch it + */ + if (edac_op_state == EDAC_OPSTATE_INT) { + orig_hid1 = mfspr(SPRN_HID1); + mtspr(SPRN_HID1, (orig_hid1 & ~0x20000)); + } + + return 0; +} + +module_init(mpc85xx_mc_init); + +static void __exit mpc85xx_mc_exit(void) +{ + mtspr(SPRN_HID1, orig_hid1); +#ifdef CONFIG_PCI + platform_driver_unregister(&mpc85xx_pci_err_driver); +#endif + of_unregister_platform_driver(&mpc85xx_l2_err_driver); + of_unregister_platform_driver(&mpc85xx_mc_err_driver); +} + +module_exit(mpc85xx_mc_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Montavista Software, Inc."); +module_param(edac_op_state, int, 0444); +MODULE_PARM_DESC(edac_op_state, + "EDAC Error Reporting state: 0=Poll, 2=Interrupt"); diff --git a/drivers/edac/mpc85xx_edac.h b/drivers/edac/mpc85xx_edac.h new file mode 100644 index 00000000000..135b3539a03 --- /dev/null +++ b/drivers/edac/mpc85xx_edac.h @@ -0,0 +1,162 @@ +/* + * Freescale MPC85xx Memory Controller kenel module + * Author: Dave Jiang <djiang@mvista.com> + * + * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + */ +#ifndef _MPC85XX_EDAC_H_ +#define _MPC85XX_EDAC_H_ + +#define MPC85XX_REVISION " Ver: 2.0.0 " __DATE__ +#define EDAC_MOD_STR "MPC85xx_edac" + +#define mpc85xx_printk(level, fmt, arg...) \ + edac_printk(level, "MPC85xx", fmt, ##arg) + +#define mpc85xx_mc_printk(mci, level, fmt, arg...) \ + edac_mc_chipset_printk(mci, level, "MPC85xx", fmt, ##arg) + +/* + * DRAM error defines + */ + +/* DDR_SDRAM_CFG */ +#define MPC85XX_MC_DDR_SDRAM_CFG 0x0110 +#define MPC85XX_MC_CS_BNDS_0 0x0000 +#define MPC85XX_MC_CS_BNDS_1 0x0008 +#define MPC85XX_MC_CS_BNDS_2 0x0010 +#define MPC85XX_MC_CS_BNDS_3 0x0018 +#define MPC85XX_MC_CS_BNDS_OFS 0x0008 + +#define MPC85XX_MC_DATA_ERR_INJECT_HI 0x0e00 +#define MPC85XX_MC_DATA_ERR_INJECT_LO 0x0e04 +#define MPC85XX_MC_ECC_ERR_INJECT 0x0e08 +#define MPC85XX_MC_CAPTURE_DATA_HI 0x0e20 +#define MPC85XX_MC_CAPTURE_DATA_LO 0x0e24 +#define MPC85XX_MC_CAPTURE_ECC 0x0e28 +#define MPC85XX_MC_ERR_DETECT 0x0e40 +#define MPC85XX_MC_ERR_DISABLE 0x0e44 +#define MPC85XX_MC_ERR_INT_EN 0x0e48 +#define MPC85XX_MC_CAPTURE_ATRIBUTES 0x0e4c +#define MPC85XX_MC_CAPTURE_ADDRESS 0x0e50 +#define MPC85XX_MC_ERR_SBE 0x0e58 + +#define DSC_MEM_EN 0x80000000 +#define DSC_ECC_EN 0x20000000 +#define DSC_RD_EN 0x10000000 + +#define DSC_SDTYPE_MASK 0x07000000 + +#define DSC_SDTYPE_DDR 0x02000000 +#define DSC_SDTYPE_DDR2 0x03000000 +#define DSC_X32_EN 0x00000020 + +/* Err_Int_En */ +#define DDR_EIE_MSEE 0x1 /* memory select */ +#define DDR_EIE_SBEE 0x4 /* single-bit ECC error */ +#define DDR_EIE_MBEE 0x8 /* multi-bit ECC error */ + +/* Err_Detect */ +#define DDR_EDE_MSE 0x1 /* memory select */ +#define DDR_EDE_SBE 0x4 /* single-bit ECC error */ +#define DDR_EDE_MBE 0x8 /* multi-bit ECC error */ +#define DDR_EDE_MME 0x80000000 /* multiple memory errors */ + +/* Err_Disable */ +#define DDR_EDI_MSED 0x1 /* memory select disable */ +#define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */ +#define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */ + +/* + * L2 Err defines + */ +#define MPC85XX_L2_ERRINJHI 0x0000 +#define MPC85XX_L2_ERRINJLO 0x0004 +#define MPC85XX_L2_ERRINJCTL 0x0008 +#define MPC85XX_L2_CAPTDATAHI 0x0020 +#define MPC85XX_L2_CAPTDATALO 0x0024 +#define MPC85XX_L2_CAPTECC 0x0028 +#define MPC85XX_L2_ERRDET 0x0040 +#define MPC85XX_L2_ERRDIS 0x0044 +#define MPC85XX_L2_ERRINTEN 0x0048 +#define MPC85XX_L2_ERRATTR 0x004c +#define MPC85XX_L2_ERRADDR 0x0050 +#define MPC85XX_L2_ERRCTL 0x0058 + +/* Error Interrupt Enable */ +#define L2_EIE_L2CFGINTEN 0x1 +#define L2_EIE_SBECCINTEN 0x4 +#define L2_EIE_MBECCINTEN 0x8 +#define L2_EIE_TPARINTEN 0x10 +#define L2_EIE_MASK (L2_EIE_L2CFGINTEN | L2_EIE_SBECCINTEN | \ + L2_EIE_MBECCINTEN | L2_EIE_TPARINTEN) + +/* Error Detect */ +#define L2_EDE_L2CFGERR 0x1 +#define L2_EDE_SBECCERR 0x4 +#define L2_EDE_MBECCERR 0x8 +#define L2_EDE_TPARERR 0x10 +#define L2_EDE_MULL2ERR 0x80000000 + +#define L2_EDE_CE_MASK L2_EDE_SBECCERR +#define L2_EDE_UE_MASK (L2_EDE_L2CFGERR | L2_EDE_MBECCERR | \ + L2_EDE_TPARERR) +#define L2_EDE_MASK (L2_EDE_L2CFGERR | L2_EDE_SBECCERR | \ + L2_EDE_MBECCERR | L2_EDE_TPARERR | L2_EDE_MULL2ERR) + +/* + * PCI Err defines + */ +#define PCI_EDE_TOE 0x00000001 +#define PCI_EDE_SCM 0x00000002 +#define PCI_EDE_IRMSV 0x00000004 +#define PCI_EDE_ORMSV 0x00000008 +#define PCI_EDE_OWMSV 0x00000010 +#define PCI_EDE_TGT_ABRT 0x00000020 +#define PCI_EDE_MST_ABRT 0x00000040 +#define PCI_EDE_TGT_PERR 0x00000080 +#define PCI_EDE_MST_PERR 0x00000100 +#define PCI_EDE_RCVD_SERR 0x00000200 +#define PCI_EDE_ADDR_PERR 0x00000400 +#define PCI_EDE_MULTI_ERR 0x80000000 + +#define PCI_EDE_PERR_MASK (PCI_EDE_TGT_PERR | PCI_EDE_MST_PERR | \ + PCI_EDE_ADDR_PERR) + +#define MPC85XX_PCI_ERR_DR 0x0000 +#define MPC85XX_PCI_ERR_CAP_DR 0x0004 +#define MPC85XX_PCI_ERR_EN 0x0008 +#define MPC85XX_PCI_ERR_ATTRIB 0x000c +#define MPC85XX_PCI_ERR_ADDR 0x0010 +#define MPC85XX_PCI_ERR_EXT_ADDR 0x0014 +#define MPC85XX_PCI_ERR_DL 0x0018 +#define MPC85XX_PCI_ERR_DH 0x001c +#define MPC85XX_PCI_GAS_TIMR 0x0020 +#define MPC85XX_PCI_PCIX_TIMR 0x0024 + +struct mpc85xx_mc_pdata { + char *name; + int edac_idx; + void __iomem *mc_vbase; + int irq; +}; + +struct mpc85xx_l2_pdata { + char *name; + int edac_idx; + void __iomem *l2_vbase; + int irq; +}; + +struct mpc85xx_pci_pdata { + char *name; + int edac_idx; + void __iomem *pci_vbase; + int irq; +}; + +#endif diff --git a/drivers/edac/mv64x60_edac.c b/drivers/edac/mv64x60_edac.c new file mode 100644 index 00000000000..bf071f140a0 --- /dev/null +++ b/drivers/edac/mv64x60_edac.c @@ -0,0 +1,855 @@ +/* + * Marvell MV64x60 Memory Controller kernel module for PPC platforms + * + * Author: Dave Jiang <djiang@mvista.com> + * + * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/edac.h> + +#include "edac_core.h" +#include "edac_module.h" +#include "mv64x60_edac.h" + +static const char *mv64x60_ctl_name = "MV64x60"; +static int edac_dev_idx; +static int edac_pci_idx; +static int edac_mc_idx; + +/*********************** PCI err device **********************************/ +#ifdef CONFIG_PCI +static void mv64x60_pci_check(struct edac_pci_ctl_info *pci) +{ + struct mv64x60_pci_pdata *pdata = pci->pvt_info; + u32 cause; + + cause = in_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_CAUSE); + if (!cause) + return; + + printk(KERN_ERR "Error in PCI %d Interface\n", pdata->pci_hose); + printk(KERN_ERR "Cause register: 0x%08x\n", cause); + printk(KERN_ERR "Address Low: 0x%08x\n", + in_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_ADDR_LO)); + printk(KERN_ERR "Address High: 0x%08x\n", + in_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_ADDR_HI)); + printk(KERN_ERR "Attribute: 0x%08x\n", + in_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_ATTR)); + printk(KERN_ERR "Command: 0x%08x\n", + in_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_CMD)); + out_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_CAUSE, ~cause); + + if (cause & MV64X60_PCI_PE_MASK) + edac_pci_handle_pe(pci, pci->ctl_name); + + if (!(cause & MV64X60_PCI_PE_MASK)) + edac_pci_handle_npe(pci, pci->ctl_name); +} + +static irqreturn_t mv64x60_pci_isr(int irq, void *dev_id) +{ + struct edac_pci_ctl_info *pci = dev_id; + struct mv64x60_pci_pdata *pdata = pci->pvt_info; + u32 val; + + val = in_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_CAUSE); + if (!val) + return IRQ_NONE; + + mv64x60_pci_check(pci); + + return IRQ_HANDLED; +} + +static int __devinit mv64x60_pci_err_probe(struct platform_device *pdev) +{ + struct edac_pci_ctl_info *pci; + struct mv64x60_pci_pdata *pdata; + struct resource *r; + int res = 0; + + if (!devres_open_group(&pdev->dev, mv64x60_pci_err_probe, GFP_KERNEL)) + return -ENOMEM; + + pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mv64x60_pci_err"); + if (!pci) + return -ENOMEM; + + pdata = pci->pvt_info; + + pdata->pci_hose = pdev->id; + pdata->name = "mpc85xx_pci_err"; + pdata->irq = NO_IRQ; + platform_set_drvdata(pdev, pci); + pci->dev = &pdev->dev; + pci->dev_name = pdev->dev.bus_id; + pci->mod_name = EDAC_MOD_STR; + pci->ctl_name = pdata->name; + + if (edac_op_state == EDAC_OPSTATE_POLL) + pci->edac_check = mv64x60_pci_check; + + pdata->edac_idx = edac_pci_idx++; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + printk(KERN_ERR "%s: Unable to get resource for " + "PCI err regs\n", __func__); + res = -ENOENT; + goto err; + } + + if (!devm_request_mem_region(&pdev->dev, + r->start, + r->end - r->start + 1, + pdata->name)) { + printk(KERN_ERR "%s: Error while requesting mem region\n", + __func__); + res = -EBUSY; + goto err; + } + + pdata->pci_vbase = devm_ioremap(&pdev->dev, + r->start, + r->end - r->start + 1); + if (!pdata->pci_vbase) { + printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__); + res = -ENOMEM; + goto err; + } + + out_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_CAUSE, 0); + out_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_MASK, 0); + out_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_MASK, + MV64X60_PCIx_ERR_MASK_VAL); + + if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { + debugf3("%s(): failed edac_pci_add_device()\n", __func__); + goto err; + } + + if (edac_op_state == EDAC_OPSTATE_INT) { + pdata->irq = platform_get_irq(pdev, 0); + res = devm_request_irq(&pdev->dev, + pdata->irq, + mv64x60_pci_isr, + IRQF_DISABLED, + "[EDAC] PCI err", + pci); + if (res < 0) { + printk(KERN_ERR "%s: Unable to request irq %d for " + "MV64x60 PCI ERR\n", __func__, pdata->irq); + res = -ENODEV; + goto err2; + } + printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n", + pdata->irq); + } + + devres_remove_group(&pdev->dev, mv64x60_pci_err_probe); + + /* get this far and it's successful */ + debugf3("%s(): success\n", __func__); + + return 0; + +err2: + edac_pci_del_device(&pdev->dev); +err: + edac_pci_free_ctl_info(pci); + devres_release_group(&pdev->dev, mv64x60_pci_err_probe); + return res; +} + +static int mv64x60_pci_err_remove(struct platform_device *pdev) +{ + struct edac_pci_ctl_info *pci = platform_get_drvdata(pdev); + + debugf0("%s()\n", __func__); + + edac_pci_del_device(&pdev->dev); + + edac_pci_free_ctl_info(pci); + + return 0; +} + +static struct platform_driver mv64x60_pci_err_driver = { + .probe = mv64x60_pci_err_probe, + .remove = __devexit_p(mv64x60_pci_err_remove), + .driver = { + .name = "mv64x60_pci_err", + } +}; + +#endif /* CONFIG_PCI */ + +/*********************** SRAM err device **********************************/ +static void mv64x60_sram_check(struct edac_device_ctl_info *edac_dev) +{ + struct mv64x60_sram_pdata *pdata = edac_dev->pvt_info; + u32 cause; + + cause = in_le32(pdata->sram_vbase + MV64X60_SRAM_ERR_CAUSE); + if (!cause) + return; + + printk(KERN_ERR "Error in internal SRAM\n"); + printk(KERN_ERR "Cause register: 0x%08x\n", cause); + printk(KERN_ERR "Address Low: 0x%08x\n", + in_le32(pdata->sram_vbase + MV64X60_SRAM_ERR_ADDR_LO)); + printk(KERN_ERR "Address High: 0x%08x\n", + in_le32(pdata->sram_vbase + MV64X60_SRAM_ERR_ADDR_HI)); + printk(KERN_ERR "Data Low: 0x%08x\n", + in_le32(pdata->sram_vbase + MV64X60_SRAM_ERR_DATA_LO)); + printk(KERN_ERR "Data High: 0x%08x\n", + in_le32(pdata->sram_vbase + MV64X60_SRAM_ERR_DATA_HI)); + printk(KERN_ERR "Parity: 0x%08x\n", + in_le32(pdata->sram_vbase + MV64X60_SRAM_ERR_PARITY)); + out_le32(pdata->sram_vbase + MV64X60_SRAM_ERR_CAUSE, 0); + + edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); +} + +static irqreturn_t mv64x60_sram_isr(int irq, void *dev_id) +{ + struct edac_device_ctl_info *edac_dev = dev_id; + struct mv64x60_sram_pdata *pdata = edac_dev->pvt_info; + u32 cause; + + cause = in_le32(pdata->sram_vbase + MV64X60_SRAM_ERR_CAUSE); + if (!cause) + return IRQ_NONE; + + mv64x60_sram_check(edac_dev); + + return IRQ_HANDLED; +} + +static int __devinit mv64x60_sram_err_probe(struct platform_device *pdev) +{ + struct edac_device_ctl_info *edac_dev; + struct mv64x60_sram_pdata *pdata; + struct resource *r; + int res = 0; + + if (!devres_open_group(&pdev->dev, mv64x60_sram_err_probe, GFP_KERNEL)) + return -ENOMEM; + + edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata), + "sram", 1, NULL, 0, 0, NULL, 0, + edac_dev_idx); + if (!edac_dev) { + devres_release_group(&pdev->dev, mv64x60_sram_err_probe); + return -ENOMEM; + } + + pdata = edac_dev->pvt_info; + pdata->name = "mv64x60_sram_err"; + pdata->irq = NO_IRQ; + edac_dev->dev = &pdev->dev; + platform_set_drvdata(pdev, edac_dev); + edac_dev->dev_name = pdev->dev.bus_id; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + printk(KERN_ERR "%s: Unable to get resource for " + "SRAM err regs\n", __func__); + res = -ENOENT; + goto err; + } + + if (!devm_request_mem_region(&pdev->dev, + r->start, + r->end - r->start + 1, + pdata->name)) { + printk(KERN_ERR "%s: Error while request mem region\n", + __func__); + res = -EBUSY; + goto err; + } + + pdata->sram_vbase = devm_ioremap(&pdev->dev, + r->start, + r->end - r->start + 1); + if (!pdata->sram_vbase) { + printk(KERN_ERR "%s: Unable to setup SRAM err regs\n", + __func__); + res = -ENOMEM; + goto err; + } + + /* setup SRAM err registers */ + out_le32(pdata->sram_vbase + MV64X60_SRAM_ERR_CAUSE, 0); + + edac_dev->mod_name = EDAC_MOD_STR; + edac_dev->ctl_name = pdata->name; + + if (edac_op_state == EDAC_OPSTATE_POLL) + edac_dev->edac_check = mv64x60_sram_check; + + pdata->edac_idx = edac_dev_idx++; + + if (edac_device_add_device(edac_dev) > 0) { + debugf3("%s(): failed edac_device_add_device()\n", __func__); + goto err; + } + + if (edac_op_state == EDAC_OPSTATE_INT) { + pdata->irq = platform_get_irq(pdev, 0); + res = devm_request_irq(&pdev->dev, + pdata->irq, + mv64x60_sram_isr, + IRQF_DISABLED, + "[EDAC] SRAM err", + edac_dev); + if (res < 0) { + printk(KERN_ERR + "%s: Unable to request irq %d for " + "MV64x60 SRAM ERR\n", __func__, pdata->irq); + res = -ENODEV; + goto err2; + } + + printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for SRAM Err\n", + pdata->irq); + } + + devres_remove_group(&pdev->dev, mv64x60_sram_err_probe); + + /* get this far and it's successful */ + debugf3("%s(): success\n", __func__); + + return 0; + +err2: + edac_device_del_device(&pdev->dev); +err: + devres_release_group(&pdev->dev, mv64x60_sram_err_probe); + edac_device_free_ctl_info(edac_dev); + return res; +} + +static int mv64x60_sram_err_remove(struct platform_device *pdev) +{ + struct edac_device_ctl_info *edac_dev = platform_get_drvdata(pdev); + + debugf0("%s()\n", __func__); + + edac_device_del_device(&pdev->dev); + edac_device_free_ctl_info(edac_dev); + + return 0; +} + +static struct platform_driver mv64x60_sram_err_driver = { + .probe = mv64x60_sram_err_probe, + .remove = mv64x60_sram_err_remove, + .driver = { + .name = "mv64x60_sram_err", + } +}; + +/*********************** CPU err device **********************************/ +static void mv64x60_cpu_check(struct edac_device_ctl_info *edac_dev) +{ + struct mv64x60_cpu_pdata *pdata = edac_dev->pvt_info; + u32 cause; + + cause = in_le32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_CAUSE) & + MV64x60_CPU_CAUSE_MASK; + if (!cause) + return; + + printk(KERN_ERR "Error on CPU interface\n"); + printk(KERN_ERR "Cause register: 0x%08x\n", cause); + printk(KERN_ERR "Address Low: 0x%08x\n", + in_le32(pdata->cpu_vbase[0] + MV64x60_CPU_ERR_ADDR_LO)); + printk(KERN_ERR "Address High: 0x%08x\n", + in_le32(pdata->cpu_vbase[0] + MV64x60_CPU_ERR_ADDR_HI)); + printk(KERN_ERR "Data Low: 0x%08x\n", + in_le32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_DATA_LO)); + printk(KERN_ERR "Data High: 0x%08x\n", + in_le32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_DATA_HI)); + printk(KERN_ERR "Parity: 0x%08x\n", + in_le32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_PARITY)); + out_le32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_CAUSE, 0); + + edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); +} + +static irqreturn_t mv64x60_cpu_isr(int irq, void *dev_id) +{ + struct edac_device_ctl_info *edac_dev = dev_id; + struct mv64x60_cpu_pdata *pdata = edac_dev->pvt_info; + u32 cause; + + cause = in_le32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_CAUSE) & + MV64x60_CPU_CAUSE_MASK; + if (!cause) + return IRQ_NONE; + + mv64x60_cpu_check(edac_dev); + + return IRQ_HANDLED; +} + +static int __devinit mv64x60_cpu_err_probe(struct platform_device *pdev) +{ + struct edac_device_ctl_info *edac_dev; + struct resource *r; + struct mv64x60_cpu_pdata *pdata; + int res = 0; + + if (!devres_open_group(&pdev->dev, mv64x60_cpu_err_probe, GFP_KERNEL)) + return -ENOMEM; + + edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata), + "cpu", 1, NULL, 0, 0, NULL, 0, + edac_dev_idx); + if (!edac_dev) { + devres_release_group(&pdev->dev, mv64x60_cpu_err_probe); + return -ENOMEM; + } + + pdata = edac_dev->pvt_info; + pdata->name = "mv64x60_cpu_err"; + pdata->irq = NO_IRQ; + edac_dev->dev = &pdev->dev; + platform_set_drvdata(pdev, edac_dev); + edac_dev->dev_name = pdev->dev.bus_id; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + printk(KERN_ERR "%s: Unable to get resource for " + "CPU err regs\n", __func__); + res = -ENOENT; + goto err; + } + + if (!devm_request_mem_region(&pdev->dev, + r->start, + r->end - r->start + 1, + pdata->name)) { + printk(KERN_ERR "%s: Error while requesting mem region\n", + __func__); + res = -EBUSY; + goto err; + } + + pdata->cpu_vbase[0] = devm_ioremap(&pdev->dev, + r->start, + r->end - r->start + 1); + if (!pdata->cpu_vbase[0]) { + printk(KERN_ERR "%s: Unable to setup CPU err regs\n", __func__); + res = -ENOMEM; + goto err; + } + + r = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!r) { + printk(KERN_ERR "%s: Unable to get resource for " + "CPU err regs\n", __func__); + res = -ENOENT; + goto err; + } + + if (!devm_request_mem_region(&pdev->dev, + r->start, + r->end - r->start + 1, + pdata->name)) { + printk(KERN_ERR "%s: Error while requesting mem region\n", + __func__); + res = -EBUSY; + goto err; + } + + pdata->cpu_vbase[1] = devm_ioremap(&pdev->dev, + r->start, + r->end - r->start + 1); + if (!pdata->cpu_vbase[1]) { + printk(KERN_ERR "%s: Unable to setup CPU err regs\n", __func__); + res = -ENOMEM; + goto err; + } + + /* setup CPU err registers */ + out_le32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_CAUSE, 0); + out_le32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_MASK, 0); + out_le32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_MASK, 0x000000ff); + + edac_dev->mod_name = EDAC_MOD_STR; + edac_dev->ctl_name = pdata->name; + if (edac_op_state == EDAC_OPSTATE_POLL) + edac_dev->edac_check = mv64x60_cpu_check; + + pdata->edac_idx = edac_dev_idx++; + + if (edac_device_add_device(edac_dev) > 0) { + debugf3("%s(): failed edac_device_add_device()\n", __func__); + goto err; + } + + if (edac_op_state == EDAC_OPSTATE_INT) { + pdata->irq = platform_get_irq(pdev, 0); + res = devm_request_irq(&pdev->dev, + pdata->irq, + mv64x60_cpu_isr, + IRQF_DISABLED, + "[EDAC] CPU err", + edac_dev); + if (res < 0) { + printk(KERN_ERR + "%s: Unable to request irq %d for MV64x60 " + "CPU ERR\n", __func__, pdata->irq); + res = -ENODEV; + goto err2; + } + + printk(KERN_INFO EDAC_MOD_STR + " acquired irq %d for CPU Err\n", pdata->irq); + } + + devres_remove_group(&pdev->dev, mv64x60_cpu_err_probe); + + /* get this far and it's successful */ + debugf3("%s(): success\n", __func__); + + return 0; + +err2: + edac_device_del_device(&pdev->dev); +err: + devres_release_group(&pdev->dev, mv64x60_cpu_err_probe); + edac_device_free_ctl_info(edac_dev); + return res; +} + +static int mv64x60_cpu_err_remove(struct platform_device *pdev) +{ + struct edac_device_ctl_info *edac_dev = platform_get_drvdata(pdev); + + debugf0("%s()\n", __func__); + + edac_device_del_device(&pdev->dev); + edac_device_free_ctl_info(edac_dev); + return 0; +} + +static struct platform_driver mv64x60_cpu_err_driver = { + .probe = mv64x60_cpu_err_probe, + .remove = mv64x60_cpu_err_remove, + .driver = { + .name = "mv64x60_cpu_err", + } +}; + +/*********************** DRAM err device **********************************/ + +static void mv64x60_mc_check(struct mem_ctl_info *mci) +{ + struct mv64x60_mc_pdata *pdata = mci->pvt_info; + u32 reg; + u32 err_addr; + u32 sdram_ecc; + u32 comp_ecc; + u32 syndrome; + + reg = in_le32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ADDR); + if (!reg) + return; + + err_addr = reg & ~0x3; + sdram_ecc = in_le32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ECC_RCVD); + comp_ecc = in_le32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ECC_CALC); + syndrome = sdram_ecc ^ comp_ecc; + + /* first bit clear in ECC Err Reg, 1 bit error, correctable by HW */ + if (!(reg & 0x1)) + edac_mc_handle_ce(mci, err_addr >> PAGE_SHIFT, + err_addr & PAGE_MASK, syndrome, 0, 0, + mci->ctl_name); + else /* 2 bit error, UE */ + edac_mc_handle_ue(mci, err_addr >> PAGE_SHIFT, + err_addr & PAGE_MASK, 0, mci->ctl_name); + + /* clear the error */ + out_le32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ADDR, 0); +} + +static irqreturn_t mv64x60_mc_isr(int irq, void *dev_id) +{ + struct mem_ctl_info *mci = dev_id; + struct mv64x60_mc_pdata *pdata = mci->pvt_info; + u32 reg; + + reg = in_le32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ADDR); + if (!reg) + return IRQ_NONE; + + /* writing 0's to the ECC err addr in check function clears irq */ + mv64x60_mc_check(mci); + + return IRQ_HANDLED; +} + +static void get_total_mem(struct mv64x60_mc_pdata *pdata) +{ + struct device_node *np = NULL; + const unsigned int *reg; + + np = of_find_node_by_type(NULL, "memory"); + if (!np) + return; + + reg = get_property(np, "reg", NULL); + + pdata->total_mem = reg[1]; +} + +static void mv64x60_init_csrows(struct mem_ctl_info *mci, + struct mv64x60_mc_pdata *pdata) +{ + struct csrow_info *csrow; + u32 devtype; + u32 ctl; + + get_total_mem(pdata); + + ctl = in_le32(pdata->mc_vbase + MV64X60_SDRAM_CONFIG); + + csrow = &mci->csrows[0]; + csrow->first_page = 0; + csrow->nr_pages = pdata->total_mem >> PAGE_SHIFT; + csrow->last_page = csrow->first_page + csrow->nr_pages - 1; + csrow->grain = 8; + + csrow->mtype = (ctl & MV64X60_SDRAM_REGISTERED) ? MEM_RDDR : MEM_DDR; + + devtype = (ctl >> 20) & 0x3; + switch (devtype) { + case 0x0: + csrow->dtype = DEV_X32; + break; + case 0x2: /* could be X8 too, but no way to tell */ + csrow->dtype = DEV_X16; + break; + case 0x3: + csrow->dtype = DEV_X4; + break; + default: + csrow->dtype = DEV_UNKNOWN; + break; + } + + csrow->edac_mode = EDAC_SECDED; +} + +static int __devinit mv64x60_mc_err_probe(struct platform_device *pdev) +{ + struct mem_ctl_info *mci; + struct mv64x60_mc_pdata *pdata; + struct resource *r; + u32 ctl; + int res = 0; + + if (!devres_open_group(&pdev->dev, mv64x60_mc_err_probe, GFP_KERNEL)) + return -ENOMEM; + + mci = edac_mc_alloc(sizeof(struct mv64x60_mc_pdata), 1, 1, edac_mc_idx); + if (!mci) { + printk(KERN_ERR "%s: No memory for CPU err\n", __func__); + devres_release_group(&pdev->dev, mv64x60_mc_err_probe); + return -ENOMEM; + } + + pdata = mci->pvt_info; + mci->dev = &pdev->dev; + platform_set_drvdata(pdev, mci); + pdata->name = "mv64x60_mc_err"; + pdata->irq = NO_IRQ; + mci->dev_name = pdev->dev.bus_id; + pdata->edac_idx = edac_mc_idx++; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + printk(KERN_ERR "%s: Unable to get resource for " + "MC err regs\n", __func__); + res = -ENOENT; + goto err; + } + + if (!devm_request_mem_region(&pdev->dev, + r->start, + r->end - r->start + 1, + pdata->name)) { + printk(KERN_ERR "%s: Error while requesting mem region\n", + __func__); + res = -EBUSY; + goto err; + } + + pdata->mc_vbase = devm_ioremap(&pdev->dev, + r->start, + r->end - r->start + 1); + if (!pdata->mc_vbase) { + printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__); + res = -ENOMEM; + goto err; + } + + ctl = in_le32(pdata->mc_vbase + MV64X60_SDRAM_CONFIG); + if (!(ctl & MV64X60_SDRAM_ECC)) { + /* Non-ECC RAM? */ + printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__); + res = -ENODEV; + goto err2; + } + + debugf3("%s(): init mci\n", __func__); + mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR; + mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; + mci->edac_cap = EDAC_FLAG_SECDED; + mci->mod_name = EDAC_MOD_STR; + mci->mod_ver = MV64x60_REVISION; + mci->ctl_name = mv64x60_ctl_name; + + if (edac_op_state == EDAC_OPSTATE_POLL) + mci->edac_check = mv64x60_mc_check; + + mci->ctl_page_to_phys = NULL; + + mci->scrub_mode = SCRUB_SW_SRC; + + mv64x60_init_csrows(mci, pdata); + + /* setup MC registers */ + out_le32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ADDR, 0); + ctl = in_le32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ECC_CNTL); + ctl = (ctl & 0xff00ffff) | 0x10000; + out_le32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ECC_CNTL, ctl); + + if (edac_mc_add_mc(mci)) { + debugf3("%s(): failed edac_mc_add_mc()\n", __func__); + goto err; + } + + if (edac_op_state == EDAC_OPSTATE_INT) { + /* acquire interrupt that reports errors */ + pdata->irq = platform_get_irq(pdev, 0); + res = devm_request_irq(&pdev->dev, + pdata->irq, + mv64x60_mc_isr, + IRQF_DISABLED, + "[EDAC] MC err", + mci); + if (res < 0) { + printk(KERN_ERR "%s: Unable to request irq %d for " + "MV64x60 DRAM ERR\n", __func__, pdata->irq); + res = -ENODEV; + goto err2; + } + + printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC Err\n", + pdata->irq); + } + + /* get this far and it's successful */ + debugf3("%s(): success\n", __func__); + + return 0; + +err2: + edac_mc_del_mc(&pdev->dev); +err: + devres_release_group(&pdev->dev, mv64x60_mc_err_probe); + edac_mc_free(mci); + return res; +} + +static int mv64x60_mc_err_remove(struct platform_device *pdev) +{ + struct mem_ctl_info *mci = platform_get_drvdata(pdev); + + debugf0("%s()\n", __func__); + + edac_mc_del_mc(&pdev->dev); + edac_mc_free(mci); + return 0; +} + +static struct platform_driver mv64x60_mc_err_driver = { + .probe = mv64x60_mc_err_probe, + .remove = mv64x60_mc_err_remove, + .driver = { + .name = "mv64x60_mc_err", + } +}; + +static int __init mv64x60_edac_init(void) +{ + int ret = 0; + + printk(KERN_INFO "Marvell MV64x60 EDAC driver " MV64x60_REVISION "\n"); + printk(KERN_INFO "\t(C) 2006-2007 MontaVista Software\n"); + /* make sure error reporting method is sane */ + switch (edac_op_state) { + case EDAC_OPSTATE_POLL: + case EDAC_OPSTATE_INT: + break; + default: + edac_op_state = EDAC_OPSTATE_INT; + break; + } + + ret = platform_driver_register(&mv64x60_mc_err_driver); + if (ret) + printk(KERN_WARNING EDAC_MOD_STR "MC err failed to register\n"); + + ret = platform_driver_register(&mv64x60_cpu_err_driver); + if (ret) + printk(KERN_WARNING EDAC_MOD_STR + "CPU err failed to register\n"); + + ret = platform_driver_register(&mv64x60_sram_err_driver); + if (ret) + printk(KERN_WARNING EDAC_MOD_STR + "SRAM err failed to register\n"); + +#ifdef CONFIG_PCI + ret = platform_driver_register(&mv64x60_pci_err_driver); + if (ret) + printk(KERN_WARNING EDAC_MOD_STR + "PCI err failed to register\n"); +#endif + + return ret; +} +module_init(mv64x60_edac_init); + +static void __exit mv64x60_edac_exit(void) +{ +#ifdef CONFIG_PCI + platform_driver_unregister(&mv64x60_pci_err_driver); +#endif + platform_driver_unregister(&mv64x60_sram_err_driver); + platform_driver_unregister(&mv64x60_cpu_err_driver); + platform_driver_unregister(&mv64x60_mc_err_driver); +} +module_exit(mv64x60_edac_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Montavista Software, Inc."); +module_param(edac_op_state, int, 0444); +MODULE_PARM_DESC(edac_op_state, + "EDAC Error Reporting state: 0=Poll, 2=Interrupt"); diff --git a/drivers/edac/mv64x60_edac.h b/drivers/edac/mv64x60_edac.h new file mode 100644 index 00000000000..e042e2daa8f --- /dev/null +++ b/drivers/edac/mv64x60_edac.h @@ -0,0 +1,114 @@ +/* + * EDAC defs for Marvell MV64x60 bridge chip + * + * Author: Dave Jiang <djiang@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + */ +#ifndef _MV64X60_EDAC_H_ +#define _MV64X60_EDAC_H_ + +#define MV64x60_REVISION " Ver: 2.0.0 " __DATE__ +#define EDAC_MOD_STR "MV64x60_edac" + +#define mv64x60_printk(level, fmt, arg...) \ + edac_printk(level, "MV64x60", fmt, ##arg) + +#define mv64x60_mc_printk(mci, level, fmt, arg...) \ + edac_mc_chipset_printk(mci, level, "MV64x60", fmt, ##arg) + +/* CPU Error Report Registers */ +#define MV64x60_CPU_ERR_ADDR_LO 0x00 /* 0x0070 */ +#define MV64x60_CPU_ERR_ADDR_HI 0x08 /* 0x0078 */ +#define MV64x60_CPU_ERR_DATA_LO 0x00 /* 0x0128 */ +#define MV64x60_CPU_ERR_DATA_HI 0x08 /* 0x0130 */ +#define MV64x60_CPU_ERR_PARITY 0x10 /* 0x0138 */ +#define MV64x60_CPU_ERR_CAUSE 0x18 /* 0x0140 */ +#define MV64x60_CPU_ERR_MASK 0x20 /* 0x0148 */ + +#define MV64x60_CPU_CAUSE_MASK 0x07ffffff + +/* SRAM Error Report Registers */ +#define MV64X60_SRAM_ERR_CAUSE 0x08 /* 0x0388 */ +#define MV64X60_SRAM_ERR_ADDR_LO 0x10 /* 0x0390 */ +#define MV64X60_SRAM_ERR_ADDR_HI 0x78 /* 0x03f8 */ +#define MV64X60_SRAM_ERR_DATA_LO 0x18 /* 0x0398 */ +#define MV64X60_SRAM_ERR_DATA_HI 0x20 /* 0x03a0 */ +#define MV64X60_SRAM_ERR_PARITY 0x28 /* 0x03a8 */ + +/* SDRAM Controller Registers */ +#define MV64X60_SDRAM_CONFIG 0x00 /* 0x1400 */ +#define MV64X60_SDRAM_ERR_DATA_HI 0x40 /* 0x1440 */ +#define MV64X60_SDRAM_ERR_DATA_LO 0x44 /* 0x1444 */ +#define MV64X60_SDRAM_ERR_ECC_RCVD 0x48 /* 0x1448 */ +#define MV64X60_SDRAM_ERR_ECC_CALC 0x4c /* 0x144c */ +#define MV64X60_SDRAM_ERR_ADDR 0x50 /* 0x1450 */ +#define MV64X60_SDRAM_ERR_ECC_CNTL 0x54 /* 0x1454 */ +#define MV64X60_SDRAM_ERR_ECC_ERR_CNT 0x58 /* 0x1458 */ + +#define MV64X60_SDRAM_REGISTERED 0x20000 +#define MV64X60_SDRAM_ECC 0x40000 + +#ifdef CONFIG_PCI +/* + * Bit 0 of MV64x60_PCIx_ERR_MASK does not exist on the 64360 and because of + * errata FEr-#11 and FEr-##16 for the 64460, it should be 0 on that chip as + * well. IOW, don't set bit 0. + */ +#define MV64X60_PCIx_ERR_MASK_VAL 0x00a50c24 + +/* Register offsets from PCIx error address low register */ +#define MV64X60_PCI_ERROR_ADDR_LO 0x00 +#define MV64X60_PCI_ERROR_ADDR_HI 0x04 +#define MV64X60_PCI_ERROR_ATTR 0x08 +#define MV64X60_PCI_ERROR_CMD 0x10 +#define MV64X60_PCI_ERROR_CAUSE 0x18 +#define MV64X60_PCI_ERROR_MASK 0x1c + +#define MV64X60_PCI_ERR_SWrPerr 0x0002 +#define MV64X60_PCI_ERR_SRdPerr 0x0004 +#define MV64X60_PCI_ERR_MWrPerr 0x0020 +#define MV64X60_PCI_ERR_MRdPerr 0x0040 + +#define MV64X60_PCI_PE_MASK (MV64X60_PCI_ERR_SWrPerr | \ + MV64X60_PCI_ERR_SRdPerr | \ + MV64X60_PCI_ERR_MWrPerr | \ + MV64X60_PCI_ERR_MRdPerr) + +struct mv64x60_pci_pdata { + int pci_hose; + void __iomem *pci_vbase; + char *name; + int irq; + int edac_idx; +}; + +#endif /* CONFIG_PCI */ + +struct mv64x60_mc_pdata { + void __iomem *mc_vbase; + int total_mem; + char *name; + int irq; + int edac_idx; +}; + +struct mv64x60_cpu_pdata { + void __iomem *cpu_vbase[2]; + char *name; + int irq; + int edac_idx; +}; + +struct mv64x60_sram_pdata { + void __iomem *sram_vbase; + char *name; + int irq; + int edac_idx; +}; + +#endif diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 25716193a53..0c886c88238 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -15,6 +15,13 @@ config MFD_SM501 interface. The device may be connected by PCI or local bus with varying functions enabled. +config MFD_ASIC3 + bool "Support for Compaq ASIC3" + depends on GENERIC_HARDIRQS && ARM + ---help--- + This driver supports the ASIC3 multifunction chip found on many + PDAs (mainly iPAQ and HTC based ones) + endmenu menu "Multimedia Capabilities Port drivers" diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 51432091b32..521cd5cb68a 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_MFD_SM501) += sm501.o +obj-$(CONFIG_MFD_ASIC3) += asic3.o obj-$(CONFIG_MCP) += mcp-core.o obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o diff --git a/drivers/mfd/asic3.c b/drivers/mfd/asic3.c new file mode 100644 index 00000000000..63fb1ff3ad1 --- /dev/null +++ b/drivers/mfd/asic3.c @@ -0,0 +1,588 @@ +/* + * driver/mfd/asic3.c + * + * Compaq ASIC3 support. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Copyright 2001 Compaq Computer Corporation. + * Copyright 2004-2005 Phil Blundell + * Copyright 2007 OpenedHand Ltd. + * + * Authors: Phil Blundell <pb@handhelds.org>, + * Samuel Ortiz <sameo@openedhand.com> + * + */ + +#include <linux/version.h> +#include <linux/kernel.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/spinlock.h> +#include <linux/platform_device.h> + +#include <linux/mfd/asic3.h> + +static inline void asic3_write_register(struct asic3 *asic, + unsigned int reg, u32 value) +{ + iowrite16(value, (unsigned long)asic->mapping + + (reg >> asic->bus_shift)); +} + +static inline u32 asic3_read_register(struct asic3 *asic, + unsigned int reg) +{ + return ioread16((unsigned long)asic->mapping + + (reg >> asic->bus_shift)); +} + +/* IRQs */ +#define MAX_ASIC_ISR_LOOPS 20 +#define ASIC3_GPIO_Base_INCR \ + (ASIC3_GPIO_B_Base - ASIC3_GPIO_A_Base) + +static void asic3_irq_flip_edge(struct asic3 *asic, + u32 base, int bit) +{ + u16 edge; + unsigned long flags; + + spin_lock_irqsave(&asic->lock, flags); + edge = asic3_read_register(asic, + base + ASIC3_GPIO_EdgeTrigger); + edge ^= bit; + asic3_write_register(asic, + base + ASIC3_GPIO_EdgeTrigger, edge); + spin_unlock_irqrestore(&asic->lock, flags); +} + +static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc) +{ + int iter, i; + unsigned long flags; + struct asic3 *asic; + + desc->chip->ack(irq); + + asic = desc->handler_data; + + for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) { + u32 status; + int bank; + + spin_lock_irqsave(&asic->lock, flags); + status = asic3_read_register(asic, + ASIC3_OFFSET(INTR, PIntStat)); + spin_unlock_irqrestore(&asic->lock, flags); + + /* Check all ten register bits */ + if ((status & 0x3ff) == 0) + break; + + /* Handle GPIO IRQs */ + for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) { + if (status & (1 << bank)) { + unsigned long base, istat; + + base = ASIC3_GPIO_A_Base + + bank * ASIC3_GPIO_Base_INCR; + + spin_lock_irqsave(&asic->lock, flags); + istat = asic3_read_register(asic, + base + + ASIC3_GPIO_IntStatus); + /* Clearing IntStatus */ + asic3_write_register(asic, + base + + ASIC3_GPIO_IntStatus, 0); + spin_unlock_irqrestore(&asic->lock, flags); + + for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) { + int bit = (1 << i); + unsigned int irqnr; + + if (!(istat & bit)) + continue; + + irqnr = asic->irq_base + + (ASIC3_GPIOS_PER_BANK * bank) + + i; + desc = irq_desc + irqnr; + desc->handle_irq(irqnr, desc); + if (asic->irq_bothedge[bank] & bit) + asic3_irq_flip_edge(asic, base, + bit); + } + } + } + + /* Handle remaining IRQs in the status register */ + for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) { + /* They start at bit 4 and go up */ + if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) { + desc = irq_desc + + i; + desc->handle_irq(asic->irq_base + i, + desc); + } + } + } + + if (iter >= MAX_ASIC_ISR_LOOPS) + printk(KERN_ERR "%s: interrupt processing overrun\n", + __FUNCTION__); +} + +static inline int asic3_irq_to_bank(struct asic3 *asic, int irq) +{ + int n; + + n = (irq - asic->irq_base) >> 4; + + return (n * (ASIC3_GPIO_B_Base - ASIC3_GPIO_A_Base)); +} + +static inline int asic3_irq_to_index(struct asic3 *asic, int irq) +{ + return (irq - asic->irq_base) & 0xf; +} + +static void asic3_mask_gpio_irq(unsigned int irq) +{ + struct asic3 *asic = get_irq_chip_data(irq); + u32 val, bank, index; + unsigned long flags; + + bank = asic3_irq_to_bank(asic, irq); + index = asic3_irq_to_index(asic, irq); + + spin_lock_irqsave(&asic->lock, flags); + val = asic3_read_register(asic, bank + ASIC3_GPIO_Mask); + val |= 1 << index; + asic3_write_register(asic, bank + ASIC3_GPIO_Mask, val); + spin_unlock_irqrestore(&asic->lock, flags); +} + +static void asic3_mask_irq(unsigned int irq) +{ + struct asic3 *asic = get_irq_chip_data(irq); + int regval; + unsigned long flags; + + spin_lock_irqsave(&asic->lock, flags); + regval = asic3_read_register(asic, + ASIC3_INTR_Base + + ASIC3_INTR_IntMask); + + regval &= ~(ASIC3_INTMASK_MASK0 << + (irq - (asic->irq_base + ASIC3_NUM_GPIOS))); + + asic3_write_register(asic, + ASIC3_INTR_Base + + ASIC3_INTR_IntMask, + regval); + spin_unlock_irqrestore(&asic->lock, flags); +} + +static void asic3_unmask_gpio_irq(unsigned int irq) +{ + struct asic3 *asic = get_irq_chip_data(irq); + u32 val, bank, index; + unsigned long flags; + + bank = asic3_irq_to_bank(asic, irq); + index = asic3_irq_to_index(asic, irq); + + spin_lock_irqsave(&asic->lock, flags); + val = asic3_read_register(asic, bank + ASIC3_GPIO_Mask); + val &= ~(1 << index); + asic3_write_register(asic, bank + ASIC3_GPIO_Mask, val); + spin_unlock_irqrestore(&asic->lock, flags); +} + +static void asic3_unmask_irq(unsigned int irq) +{ + struct asic3 *asic = get_irq_chip_data(irq); + int regval; + unsigned long flags; + + spin_lock_irqsave(&asic->lock, flags); + regval = asic3_read_register(asic, + ASIC3_INTR_Base + + ASIC3_INTR_IntMask); + + regval |= (ASIC3_INTMASK_MASK0 << + (irq - (asic->irq_base + ASIC3_NUM_GPIOS))); + + asic3_write_register(asic, + ASIC3_INTR_Base + + ASIC3_INTR_IntMask, + regval); + spin_unlock_irqrestore(&asic->lock, flags); +} + +static int asic3_gpio_irq_type(unsigned int irq, unsigned int type) +{ + struct asic3 *asic = get_irq_chip_data(irq); + u32 bank, index; + u16 trigger, level, edge, bit; + unsigned long flags; + + bank = asic3_irq_to_bank(asic, irq); + index = asic3_irq_to_index(asic, irq); + bit = 1<<index; + + spin_lock_irqsave(&asic->lock, flags); + level = asic3_read_register(asic, + bank + ASIC3_GPIO_LevelTrigger); + edge = asic3_read_register(asic, + bank + ASIC3_GPIO_EdgeTrigger); + trigger = asic3_read_register(asic, + bank + ASIC3_GPIO_TriggerType); + asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit; + + if (type == IRQT_RISING) { + trigger |= bit; + edge |= bit; + } else if (type == IRQT_FALLING) { + trigger |= bit; + edge &= ~bit; + } else if (type == IRQT_BOTHEDGE) { + trigger |= bit; + if (asic3_gpio_get_value(asic, irq - asic->irq_base)) + edge &= ~bit; + else + edge |= bit; + asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit; + } else if (type == IRQT_LOW) { + trigger &= ~bit; + level &= ~bit; + } else if (type == IRQT_HIGH) { + trigger &= ~bit; + level |= bit; + } else { + /* + * if type == IRQT_NOEDGE, we should mask interrupts, but + * be careful to not unmask them if mask was also called. + * Probably need internal state for mask. + */ + printk(KERN_NOTICE "asic3: irq type not changed.\n"); + } + asic3_write_register(asic, bank + ASIC3_GPIO_LevelTrigger, + level); + asic3_write_register(asic, bank + ASIC3_GPIO_EdgeTrigger, + edge); + asic3_write_register(asic, bank + ASIC3_GPIO_TriggerType, + trigger); + spin_unlock_irqrestore(&asic->lock, flags); + return 0; +} + +static struct irq_chip asic3_gpio_irq_chip = { + .name = "ASIC3-GPIO", + .ack = asic3_mask_gpio_irq, + .mask = asic3_mask_gpio_irq, + .unmask = asic3_unmask_gpio_irq, + .set_type = asic3_gpio_irq_type, +}; + +static struct irq_chip asic3_irq_chip = { + .name = "ASIC3", + .ack = asic3_mask_irq, + .mask = asic3_mask_irq, + .unmask = asic3_unmask_irq, +}; + +static int asic3_irq_probe(struct platform_device *pdev) +{ + struct asic3 *asic = platform_get_drvdata(pdev); + unsigned long clksel = 0; + unsigned int irq, irq_base; + + asic->irq_nr = platform_get_irq(pdev, 0); + if (asic->irq_nr < 0) + return asic->irq_nr; + + /* turn on clock to IRQ controller */ + clksel |= CLOCK_SEL_CX; + asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), + clksel); + + irq_base = asic->irq_base; + + for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) { + if (irq < asic->irq_base + ASIC3_NUM_GPIOS) + set_irq_chip(irq, &asic3_gpio_irq_chip); + else + set_irq_chip(irq, &asic3_irq_chip); + + set_irq_chip_data(irq, asic); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + } + + asic3_write_register(asic, ASIC3_OFFSET(INTR, IntMask), + ASIC3_INTMASK_GINTMASK); + + set_irq_chained_handler(asic->irq_nr, asic3_irq_demux); + set_irq_type(asic->irq_nr, IRQT_RISING); + set_irq_data(asic->irq_nr, asic); + + return 0; +} + +static void asic3_irq_remove(struct platform_device *pdev) +{ + struct asic3 *asic = platform_get_drvdata(pdev); + unsigned int irq, irq_base; + + irq_base = asic->irq_base; + + for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) { + set_irq_flags(irq, 0); + set_irq_handler(irq, NULL); + set_irq_chip(irq, NULL); + set_irq_chip_data(irq, NULL); + } + set_irq_chained_handler(asic->irq_nr, NULL); +} + +/* GPIOs */ +static inline u32 asic3_get_gpio(struct asic3 *asic, unsigned int base, + unsigned int function) +{ + return asic3_read_register(asic, base + function); +} + +static void asic3_set_gpio(struct asic3 *asic, unsigned int base, + unsigned int function, u32 bits, u32 val) +{ + unsigned long flags; + + spin_lock_irqsave(&asic->lock, flags); + val |= (asic3_read_register(asic, base + function) & ~bits); + + asic3_write_register(asic, base + function, val); + spin_unlock_irqrestore(&asic->lock, flags); +} + +#define asic3_get_gpio_a(asic, fn) \ + asic3_get_gpio(asic, ASIC3_GPIO_A_Base, ASIC3_GPIO_##fn) +#define asic3_get_gpio_b(asic, fn) \ + asic3_get_gpio(asic, ASIC3_GPIO_B_Base, ASIC3_GPIO_##fn) +#define asic3_get_gpio_c(asic, fn) \ + asic3_get_gpio(asic, ASIC3_GPIO_C_Base, ASIC3_GPIO_##fn) +#define asic3_get_gpio_d(asic, fn) \ + asic3_get_gpio(asic, ASIC3_GPIO_D_Base, ASIC3_GPIO_##fn) + +#define asic3_set_gpio_a(asic, fn, bits, val) \ + asic3_set_gpio(asic, ASIC3_GPIO_A_Base, ASIC3_GPIO_##fn, bits, val) +#define asic3_set_gpio_b(asic, fn, bits, val) \ + asic3_set_gpio(asic, ASIC3_GPIO_B_Base, ASIC3_GPIO_##fn, bits, val) +#define asic3_set_gpio_c(asic, fn, bits, val) \ + asic3_set_gpio(asic, ASIC3_GPIO_C_Base, ASIC3_GPIO_##fn, bits, val) +#define asic3_set_gpio_d(asic, fn, bits, val) \ + asic3_set_gpio(asic, ASIC3_GPIO_D_Base, ASIC3_GPIO_##fn, bits, val) + +#define asic3_set_gpio_banks(asic, fn, bits, pdata, field) \ + do { \ + asic3_set_gpio_a((asic), fn, (bits), (pdata)->gpio_a.field); \ + asic3_set_gpio_b((asic), fn, (bits), (pdata)->gpio_b.field); \ + asic3_set_gpio_c((asic), fn, (bits), (pdata)->gpio_c.field); \ + asic3_set_gpio_d((asic), fn, (bits), (pdata)->gpio_d.field); \ + } while (0) + +int asic3_gpio_get_value(struct asic3 *asic, unsigned gpio) +{ + u32 mask = ASIC3_GPIO_bit(gpio); + + switch (gpio >> 4) { + case ASIC3_GPIO_BANK_A: + return asic3_get_gpio_a(asic, Status) & mask; + case ASIC3_GPIO_BANK_B: + return asic3_get_gpio_b(asic, Status) & mask; + case ASIC3_GPIO_BANK_C: + return asic3_get_gpio_c(asic, Status) & mask; + case ASIC3_GPIO_BANK_D: + return asic3_get_gpio_d(asic, Status) & mask; + default: + printk(KERN_ERR "%s: invalid GPIO value 0x%x", + __FUNCTION__, gpio); + return -EINVAL; + } +} +EXPORT_SYMBOL(asic3_gpio_get_value); + +void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val) +{ + u32 mask = ASIC3_GPIO_bit(gpio); + u32 bitval = 0; + if (val) + bitval = mask; + + switch (gpio >> 4) { + case ASIC3_GPIO_BANK_A: + asic3_set_gpio_a(asic, Out, mask, bitval); + return; + case ASIC3_GPIO_BANK_B: + asic3_set_gpio_b(asic, Out, mask, bitval); + return; + case ASIC3_GPIO_BANK_C: + asic3_set_gpio_c(asic, Out, mask, bitval); + return; + case ASIC3_GPIO_BANK_D: + asic3_set_gpio_d(asic, Out, mask, bitval); + return; + default: + printk(KERN_ERR "%s: invalid GPIO value 0x%x", + __FUNCTION__, gpio); + return; + } +} +EXPORT_SYMBOL(asic3_gpio_set_value); + +static int asic3_gpio_probe(struct platform_device *pdev) +{ + struct asic3_platform_data *pdata = pdev->dev.platform_data; + struct asic3 *asic = platform_get_drvdata(pdev); + + asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, Mask), 0xffff); + asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, Mask), 0xffff); + asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, Mask), 0xffff); + asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, Mask), 0xffff); + + asic3_set_gpio_a(asic, SleepMask, 0xffff, 0xffff); + asic3_set_gpio_b(asic, SleepMask, 0xffff, 0xffff); + asic3_set_gpio_c(asic, SleepMask, 0xffff, 0xffff); + asic3_set_gpio_d(asic, SleepMask, 0xffff, 0xffff); + + if (pdata) { + asic3_set_gpio_banks(asic, Out, 0xffff, pdata, init); + asic3_set_gpio_banks(asic, Direction, 0xffff, pdata, dir); + asic3_set_gpio_banks(asic, SleepMask, 0xffff, pdata, + sleep_mask); + asic3_set_gpio_banks(asic, SleepOut, 0xffff, pdata, sleep_out); + asic3_set_gpio_banks(asic, BattFaultOut, 0xffff, pdata, + batt_fault_out); + asic3_set_gpio_banks(asic, SleepConf, 0xffff, pdata, + sleep_conf); + asic3_set_gpio_banks(asic, AltFunction, 0xffff, pdata, + alt_function); + } + + return 0; +} + +static void asic3_gpio_remove(struct platform_device *pdev) +{ + return; +} + + +/* Core */ +static int asic3_probe(struct platform_device *pdev) +{ + struct asic3_platform_data *pdata = pdev->dev.platform_data; + struct asic3 *asic; + struct resource *mem; + unsigned long clksel; + int ret; + + asic = kzalloc(sizeof(struct asic3), GFP_KERNEL); + if (!asic) + return -ENOMEM; + + spin_lock_init(&asic->lock); + platform_set_drvdata(pdev, asic); + asic->dev = &pdev->dev; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) { + ret = -ENOMEM; + printk(KERN_ERR "asic3: no MEM resource\n"); + goto err_out_1; + } + + asic->mapping = ioremap(mem->start, PAGE_SIZE); + if (!asic->mapping) { + ret = -ENOMEM; + printk(KERN_ERR "asic3: couldn't ioremap\n"); + goto err_out_1; + } + + asic->irq_base = pdata->irq_base; + + if (pdata && pdata->bus_shift) + asic->bus_shift = 2 - pdata->bus_shift; + else + asic->bus_shift = 0; + + clksel = 0; + asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel); + + ret = asic3_irq_probe(pdev); + if (ret < 0) { + printk(KERN_ERR "asic3: couldn't probe IRQs\n"); + goto err_out_2; + } + asic3_gpio_probe(pdev); + + if (pdata->children) { + int i; + for (i = 0; i < pdata->n_children; i++) { + pdata->children[i]->dev.parent = &pdev->dev; + platform_device_register(pdata->children[i]); + } + } + + printk(KERN_INFO "ASIC3 Core driver\n"); + + return 0; + + err_out_2: + iounmap(asic->mapping); + err_out_1: + kfree(asic); + + return ret; +} + +static int asic3_remove(struct platform_device *pdev) +{ + struct asic3 *asic = platform_get_drvdata(pdev); + + asic3_gpio_remove(pdev); + asic3_irq_remove(pdev); + + asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0); + + iounmap(asic->mapping); + + kfree(asic); + + return 0; +} + +static void asic3_shutdown(struct platform_device *pdev) +{ +} + +static struct platform_driver asic3_device_driver = { + .driver = { + .name = "asic3", + }, + .probe = asic3_probe, + .remove = __devexit_p(asic3_remove), + .shutdown = asic3_shutdown, +}; + +static int __init asic3_init(void) +{ + int retval = 0; + retval = platform_driver_register(&asic3_device_driver); + return retval; +} + +subsys_initcall(asic3_init); diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 7d170cd381c..9cc25fd80b6 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1737,10 +1737,8 @@ config SC92031 config CPMAC tristate "TI AR7 CPMAC Ethernet support (EXPERIMENTAL)" - depends on NET_ETHERNET && EXPERIMENTAL && AR7 + depends on NET_ETHERNET && EXPERIMENTAL && AR7 && BROKEN select PHYLIB - select FIXED_PHY - select FIXED_MII_100_FDX help TI AR7 CPMAC Ethernet support diff --git a/drivers/net/cpmac.c b/drivers/net/cpmac.c index 6ccebb830ff..c85194f2cd2 100644 --- a/drivers/net/cpmac.c +++ b/drivers/net/cpmac.c @@ -845,15 +845,6 @@ static void cpmac_adjust_link(struct net_device *dev) spin_unlock(&priv->lock); } -static int cpmac_link_update(struct net_device *dev, - struct fixed_phy_status *status) -{ - status->link = 1; - status->speed = 100; - status->duplex = 1; - return 0; -} - static int cpmac_open(struct net_device *dev) { int i, size, res; @@ -996,11 +987,11 @@ static int external_switch; static int __devinit cpmac_probe(struct platform_device *pdev) { int rc, phy_id, i; + int mdio_bus_id = cpmac_mii.id; struct resource *mem; struct cpmac_priv *priv; struct net_device *dev; struct plat_cpmac_data *pdata; - struct fixed_info *fixed_phy; DECLARE_MAC_BUF(mac); pdata = pdev->dev.platform_data; @@ -1014,9 +1005,23 @@ static int __devinit cpmac_probe(struct platform_device *pdev) } if (phy_id == PHY_MAX_ADDR) { - if (external_switch || dumb_switch) + if (external_switch || dumb_switch) { + struct fixed_phy_status status = {}; + + mdio_bus_id = 0; + + /* + * FIXME: this should be in the platform code! + * Since there is not platform code at all (that is, + * no mainline users of that driver), place it here + * for now. + */ phy_id = 0; - else { + status.link = 1; + status.duplex = 1; + status.speed = 100; + fixed_phy_add(PHY_POLL, phy_id, &status); + } else { printk(KERN_ERR "cpmac: no PHY present\n"); return -ENODEV; } @@ -1060,32 +1065,8 @@ static int __devinit cpmac_probe(struct platform_device *pdev) priv->msg_enable = netif_msg_init(debug_level, 0xff); memcpy(dev->dev_addr, pdata->dev_addr, sizeof(dev->dev_addr)); - if (phy_id == 31) { - snprintf(priv->phy_name, BUS_ID_SIZE, PHY_ID_FMT, cpmac_mii.id, - phy_id); - } else { - /* Let's try to get a free fixed phy... */ - for (i = 0; i < MAX_PHY_AMNT; i++) { - fixed_phy = fixed_mdio_get_phydev(i); - if (!fixed_phy) - continue; - if (!fixed_phy->phydev->attached_dev) { - strncpy(priv->phy_name, - fixed_phy->phydev->dev.bus_id, - BUS_ID_SIZE); - fixed_mdio_set_link_update(fixed_phy->phydev, - &cpmac_link_update); - goto phy_found; - } - } - if (netif_msg_drv(priv)) - printk(KERN_ERR "%s: Could not find fixed PHY\n", - dev->name); - rc = -ENODEV; - goto fail; - } + snprintf(priv->phy_name, BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id); -phy_found: priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link, 0, PHY_INTERFACE_MODE_MII); if (IS_ERR(priv->phy)) { diff --git a/drivers/of/base.c b/drivers/of/base.c index b306fef1ac4..80c9deca5f3 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -138,6 +138,31 @@ struct device_node *of_get_parent(const struct device_node *node) EXPORT_SYMBOL(of_get_parent); /** + * of_get_next_parent - Iterate to a node's parent + * @node: Node to get parent of + * + * This is like of_get_parent() except that it drops the + * refcount on the passed node, making it suitable for iterating + * through a node's parents. + * + * Returns a node pointer with refcount incremented, use + * of_node_put() on it when done. + */ +struct device_node *of_get_next_parent(struct device_node *node) +{ + struct device_node *parent; + + if (!node) + return NULL; + + read_lock(&devtree_lock); + parent = of_node_get(node->parent); + of_node_put(node); + read_unlock(&devtree_lock); + return parent; +} + +/** * of_get_next_child - Iterate a node childs * @node: parent node * @prev: previous child of the parent node, or NULL to get first diff --git a/drivers/of/platform.c b/drivers/of/platform.c index b47bb2d7476..ca09a63a64d 100644 --- a/drivers/of/platform.c +++ b/drivers/of/platform.c @@ -85,6 +85,15 @@ static int of_platform_device_resume(struct device * dev) return error; } +static void of_platform_device_shutdown(struct device *dev) +{ + struct of_device *of_dev = to_of_device(dev); + struct of_platform_driver *drv = to_of_platform_driver(dev->driver); + + if (dev->driver && drv->shutdown) + drv->shutdown(of_dev); +} + int of_bus_type_init(struct bus_type *bus, const char *name) { bus->name = name; @@ -93,6 +102,7 @@ int of_bus_type_init(struct bus_type *bus, const char *name) bus->remove = of_platform_device_remove; bus->suspend = of_platform_device_suspend; bus->resume = of_platform_device_resume; + bus->shutdown = of_platform_device_shutdown; return bus_register(bus); } diff --git a/drivers/power/power_supply_sysfs.c b/drivers/power/power_supply_sysfs.c index d4824840c5b..13399d133b9 100644 --- a/drivers/power/power_supply_sysfs.c +++ b/drivers/power/power_supply_sysfs.c @@ -106,7 +106,6 @@ static struct device_attribute power_supply_attrs[] = { POWER_SUPPLY_ATTR(energy_now), POWER_SUPPLY_ATTR(energy_avg), POWER_SUPPLY_ATTR(capacity), - POWER_SUPPLY_ATTR(capacity_level), POWER_SUPPLY_ATTR(temp), POWER_SUPPLY_ATTR(temp_ambient), POWER_SUPPLY_ATTR(time_to_empty_now), diff --git a/drivers/serial/68328serial.c b/drivers/serial/68328serial.c index 0d99120ab5a..2b8a410e095 100644 --- a/drivers/serial/68328serial.c +++ b/drivers/serial/68328serial.c @@ -84,9 +84,6 @@ extern wait_queue_head_t keypress_wait; struct tty_driver *serial_driver; -/* serial subtype definitions */ -#define SERIAL_TYPE_NORMAL 1 - /* number of characters left in xmit buffer before we ask for more */ #define WAKEUP_CHARS 256 diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 6a44fb1dc16..84a054d7e98 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -465,20 +465,24 @@ config SERIAL_DZ bool "DECstation DZ serial driver" depends on MACH_DECSTATION && 32BIT select SERIAL_CORE - help - DZ11-family serial controllers for VAXstations, including the - DC7085, M7814, and M7819. + default y + ---help--- + DZ11-family serial controllers for DECstations and VAXstations, + including the DC7085, M7814, and M7819. config SERIAL_DZ_CONSOLE bool "Support console on DECstation DZ serial driver" depends on SERIAL_DZ=y select SERIAL_CORE_CONSOLE - help + default y + ---help--- If you say Y here, it will be possible to use a serial port as the system console (the system console is the device which receives all kernel messages and warnings and which allows logins in single user - mode). Note that the firmware uses ttyS0 as the serial console on - the Maxine and ttyS2 on the others. + mode). + + Note that the firmware uses ttyS3 as the serial console on + DECstations that use this driver. If unsure, say Y. @@ -1138,17 +1142,17 @@ config SERIAL_SGI_L1_CONSOLE say Y. Otherwise, say N. config SERIAL_MPC52xx - tristate "Freescale MPC52xx family PSC serial support" - depends on PPC_MPC52xx + tristate "Freescale MPC52xx/MPC512x family PSC serial support" + depends on PPC_MPC52xx || PPC_MPC512x select SERIAL_CORE help - This drivers support the MPC52xx PSC serial ports. If you would - like to use them, you must answer Y or M to this option. Not that + This driver supports MPC52xx and MPC512x PSC serial ports. If you would + like to use them, you must answer Y or M to this option. Note that for use as console, it must be included in kernel and not as a module. config SERIAL_MPC52xx_CONSOLE - bool "Console on a Freescale MPC52xx family PSC serial port" + bool "Console on a Freescale MPC52xx/MPC512x family PSC serial port" depends on SERIAL_MPC52xx=y select SERIAL_CORE_CONSOLE help @@ -1156,7 +1160,7 @@ config SERIAL_MPC52xx_CONSOLE of the Freescale MPC52xx family as a console. config SERIAL_MPC52xx_CONSOLE_BAUD - int "Freescale MPC52xx family PSC serial port baud" + int "Freescale MPC52xx/MPC512x family PSC serial port baud" depends on SERIAL_MPC52xx_CONSOLE=y default "9600" help diff --git a/drivers/serial/crisv10.c b/drivers/serial/crisv10.c index a4e23cf4790..383c4e660cd 100644 --- a/drivers/serial/crisv10.c +++ b/drivers/serial/crisv10.c @@ -68,11 +68,6 @@ static char *serial_version = "$Revision: 1.25 $"; struct tty_driver *serial_driver; -/* serial subtype definitions */ -#ifndef SERIAL_TYPE_NORMAL -#define SERIAL_TYPE_NORMAL 1 -#endif - /* number of characters left in xmit buffer before we ask for more */ #define WAKEUP_CHARS 256 diff --git a/drivers/serial/dz.c b/drivers/serial/dz.c index bbae5a22021..116211fcd36 100644 --- a/drivers/serial/dz.c +++ b/drivers/serial/dz.c @@ -6,7 +6,7 @@ * * Email: olivier.lebaillif@ifrsys.com * - * Copyright (C) 2004, 2006 Maciej W. Rozycki + * Copyright (C) 2004, 2006, 2007 Maciej W. Rozycki * * [31-AUG-98] triemer * Changed IRQ to use Harald's dec internals interrupts.h @@ -32,38 +32,63 @@ #define SUPPORT_SYSRQ #endif +#include <linux/bitops.h> +#include <linux/compiler.h> +#include <linux/console.h> #include <linux/delay.h> -#include <linux/module.h> -#include <linux/interrupt.h> +#include <linux/errno.h> #include <linux/init.h> -#include <linux/console.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/kernel.h> +#include <linux/major.h> +#include <linux/module.h> +#include <linux/serial.h> +#include <linux/serial_core.h> #include <linux/sysrq.h> #include <linux/tty.h> -#include <linux/tty_flip.h> -#include <linux/serial_core.h> -#include <linux/serial.h> +#include <asm/atomic.h> #include <asm/bootinfo.h> +#include <asm/io.h> +#include <asm/system.h> + #include <asm/dec/interrupts.h> #include <asm/dec/kn01.h> #include <asm/dec/kn02.h> #include <asm/dec/machtype.h> #include <asm/dec/prom.h> -#include <asm/irq.h> -#include <asm/system.h> -#include <asm/uaccess.h> +#include <asm/dec/system.h> #include "dz.h" -static char *dz_name = "DECstation DZ serial driver version "; -static char *dz_version = "1.03"; + +MODULE_DESCRIPTION("DECstation DZ serial driver"); +MODULE_LICENSE("GPL"); + + +static char dz_name[] __initdata = "DECstation DZ serial driver version "; +static char dz_version[] __initdata = "1.04"; struct dz_port { + struct dz_mux *mux; struct uart_port port; unsigned int cflag; }; -static struct dz_port dz_ports[DZ_NB_PORT]; +struct dz_mux { + struct dz_port dport[DZ_NB_PORT]; + atomic_t map_guard; + atomic_t irq_guard; + int initialised; +}; + +static struct dz_mux dz_mux; + +static inline struct dz_port *to_dport(struct uart_port *uport) +{ + return container_of(uport, struct dz_port, port); +} /* * ------------------------------------------------------------ @@ -74,21 +99,18 @@ static struct dz_port dz_ports[DZ_NB_PORT]; * ------------------------------------------------------------ */ -static inline unsigned short dz_in(struct dz_port *dport, unsigned offset) +static u16 dz_in(struct dz_port *dport, unsigned offset) { - volatile unsigned short *addr = - (volatile unsigned short *) (dport->port.membase + offset); + void __iomem *addr = dport->port.membase + offset; - return *addr; + return readw(addr); } -static inline void dz_out(struct dz_port *dport, unsigned offset, - unsigned short value) +static void dz_out(struct dz_port *dport, unsigned offset, u16 value) { - volatile unsigned short *addr = - (volatile unsigned short *) (dport->port.membase + offset); + void __iomem *addr = dport->port.membase + offset; - *addr = value; + writew(value, addr); } /* @@ -103,42 +125,33 @@ static inline void dz_out(struct dz_port *dport, unsigned offset, static void dz_stop_tx(struct uart_port *uport) { - struct dz_port *dport = (struct dz_port *)uport; - unsigned short tmp, mask = 1 << dport->port.line; - unsigned long flags; + struct dz_port *dport = to_dport(uport); + u16 tmp, mask = 1 << dport->port.line; - spin_lock_irqsave(&dport->port.lock, flags); tmp = dz_in(dport, DZ_TCR); /* read the TX flag */ tmp &= ~mask; /* clear the TX flag */ dz_out(dport, DZ_TCR, tmp); - spin_unlock_irqrestore(&dport->port.lock, flags); } static void dz_start_tx(struct uart_port *uport) { - struct dz_port *dport = (struct dz_port *)uport; - unsigned short tmp, mask = 1 << dport->port.line; - unsigned long flags; + struct dz_port *dport = to_dport(uport); + u16 tmp, mask = 1 << dport->port.line; - spin_lock_irqsave(&dport->port.lock, flags); tmp = dz_in(dport, DZ_TCR); /* read the TX flag */ tmp |= mask; /* set the TX flag */ dz_out(dport, DZ_TCR, tmp); - spin_unlock_irqrestore(&dport->port.lock, flags); } static void dz_stop_rx(struct uart_port *uport) { - struct dz_port *dport = (struct dz_port *)uport; - unsigned long flags; + struct dz_port *dport = to_dport(uport); - spin_lock_irqsave(&dport->port.lock, flags); - dport->cflag &= ~DZ_CREAD; - dz_out(dport, DZ_LPR, dport->cflag | dport->port.line); - spin_unlock_irqrestore(&dport->port.lock, flags); + dport->cflag &= ~DZ_RXENAB; + dz_out(dport, DZ_LPR, dport->cflag); } -static void dz_enable_ms(struct uart_port *port) +static void dz_enable_ms(struct uart_port *uport) { /* nothing to do */ } @@ -170,73 +183,73 @@ static void dz_enable_ms(struct uart_port *port) * This routine deals with inputs from any lines. * ------------------------------------------------------------ */ -static inline void dz_receive_chars(struct dz_port *dport_in) +static inline void dz_receive_chars(struct dz_mux *mux) { - struct dz_port *dport; + struct uart_port *uport; + struct dz_port *dport = &mux->dport[0]; struct tty_struct *tty = NULL; struct uart_icount *icount; int lines_rx[DZ_NB_PORT] = { [0 ... DZ_NB_PORT - 1] = 0 }; - unsigned short status; unsigned char ch, flag; + u16 status; int i; - while ((status = dz_in(dport_in, DZ_RBUF)) & DZ_DVAL) { - dport = &dz_ports[LINE(status)]; - tty = dport->port.info->tty; /* point to the proper dev */ + while ((status = dz_in(dport, DZ_RBUF)) & DZ_DVAL) { + dport = &mux->dport[LINE(status)]; + uport = &dport->port; + tty = uport->info->tty; /* point to the proper dev */ ch = UCHAR(status); /* grab the char */ + flag = TTY_NORMAL; - icount = &dport->port.icount; + icount = &uport->icount; icount->rx++; - flag = TTY_NORMAL; - if (status & DZ_FERR) { /* frame error */ + if (unlikely(status & (DZ_OERR | DZ_FERR | DZ_PERR))) { + /* - * There is no separate BREAK status bit, so - * treat framing errors as BREAKs for Magic SysRq - * and SAK; normally, otherwise. + * There is no separate BREAK status bit, so treat + * null characters with framing errors as BREAKs; + * normally, otherwise. For this move the Framing + * Error bit to a simulated BREAK bit. */ - if (uart_handle_break(&dport->port)) - continue; - if (dport->port.flags & UPF_SAK) + if (!ch) { + status |= (status & DZ_FERR) >> + (ffs(DZ_FERR) - ffs(DZ_BREAK)); + status &= ~DZ_FERR; + } + + /* Handle SysRq/SAK & keep track of the statistics. */ + if (status & DZ_BREAK) { + icount->brk++; + if (uart_handle_break(uport)) + continue; + } else if (status & DZ_FERR) + icount->frame++; + else if (status & DZ_PERR) + icount->parity++; + if (status & DZ_OERR) + icount->overrun++; + + status &= uport->read_status_mask; + if (status & DZ_BREAK) flag = TTY_BREAK; - else + else if (status & DZ_FERR) flag = TTY_FRAME; - } else if (status & DZ_OERR) /* overrun error */ - flag = TTY_OVERRUN; - else if (status & DZ_PERR) /* parity error */ - flag = TTY_PARITY; - - /* keep track of the statistics */ - switch (flag) { - case TTY_FRAME: - icount->frame++; - break; - case TTY_PARITY: - icount->parity++; - break; - case TTY_OVERRUN: - icount->overrun++; - break; - case TTY_BREAK: - icount->brk++; - break; - default: - break; + else if (status & DZ_PERR) + flag = TTY_PARITY; + } - if (uart_handle_sysrq_char(&dport->port, ch)) + if (uart_handle_sysrq_char(uport, ch)) continue; - if ((status & dport->port.ignore_status_mask) == 0) { - uart_insert_char(&dport->port, - status, DZ_OERR, ch, flag); - lines_rx[LINE(status)] = 1; - } + uart_insert_char(uport, status, DZ_OERR, ch, flag); + lines_rx[LINE(status)] = 1; } for (i = 0; i < DZ_NB_PORT; i++) if (lines_rx[i]) - tty_flip_buffer_push(dz_ports[i].port.info->tty); + tty_flip_buffer_push(mux->dport[i].port.info->tty); } /* @@ -246,15 +259,15 @@ static inline void dz_receive_chars(struct dz_port *dport_in) * This routine deals with outputs to any lines. * ------------------------------------------------------------ */ -static inline void dz_transmit_chars(struct dz_port *dport_in) +static inline void dz_transmit_chars(struct dz_mux *mux) { - struct dz_port *dport; + struct dz_port *dport = &mux->dport[0]; struct circ_buf *xmit; - unsigned short status; unsigned char tmp; + u16 status; - status = dz_in(dport_in, DZ_CSR); - dport = &dz_ports[LINE(status)]; + status = dz_in(dport, DZ_CSR); + dport = &mux->dport[LINE(status)]; xmit = &dport->port.info->xmit; if (dport->port.x_char) { /* XON/XOFF chars */ @@ -265,7 +278,9 @@ static inline void dz_transmit_chars(struct dz_port *dport_in) } /* If nothing to do or stopped or hardware stopped. */ if (uart_circ_empty(xmit) || uart_tx_stopped(&dport->port)) { + spin_lock(&dport->port.lock); dz_stop_tx(&dport->port); + spin_unlock(&dport->port.lock); return; } @@ -282,8 +297,11 @@ static inline void dz_transmit_chars(struct dz_port *dport_in) uart_write_wakeup(&dport->port); /* Are we are done. */ - if (uart_circ_empty(xmit)) + if (uart_circ_empty(xmit)) { + spin_lock(&dport->port.lock); dz_stop_tx(&dport->port); + spin_unlock(&dport->port.lock); + } } /* @@ -301,7 +319,7 @@ static inline void check_modem_status(struct dz_port *dport) * 1. No status change interrupt; use a timer. * 2. Handle the 3100/5000 as appropriate. --macro */ - unsigned short status; + u16 status; /* If not the modem line just return. */ if (dport->port.line != DZ_MODEM) @@ -322,19 +340,20 @@ static inline void check_modem_status(struct dz_port *dport) * It deals with the multiple ports. * ------------------------------------------------------------ */ -static irqreturn_t dz_interrupt(int irq, void *dev) +static irqreturn_t dz_interrupt(int irq, void *dev_id) { - struct dz_port *dport = dev; - unsigned short status; + struct dz_mux *mux = dev_id; + struct dz_port *dport = &mux->dport[0]; + u16 status; /* get the reason why we just got an irq */ status = dz_in(dport, DZ_CSR); if ((status & (DZ_RDONE | DZ_RIE)) == (DZ_RDONE | DZ_RIE)) - dz_receive_chars(dport); + dz_receive_chars(mux); if ((status & (DZ_TRDY | DZ_TIE)) == (DZ_TRDY | DZ_TIE)) - dz_transmit_chars(dport); + dz_transmit_chars(mux); return IRQ_HANDLED; } @@ -350,7 +369,7 @@ static unsigned int dz_get_mctrl(struct uart_port *uport) /* * FIXME: Handle the 3100/5000 as appropriate. --macro */ - struct dz_port *dport = (struct dz_port *)uport; + struct dz_port *dport = to_dport(uport); unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; if (dport->port.line == DZ_MODEM) { @@ -366,8 +385,8 @@ static void dz_set_mctrl(struct uart_port *uport, unsigned int mctrl) /* * FIXME: Handle the 3100/5000 as appropriate. --macro */ - struct dz_port *dport = (struct dz_port *)uport; - unsigned short tmp; + struct dz_port *dport = to_dport(uport); + u16 tmp; if (dport->port.line == DZ_MODEM) { tmp = dz_in(dport, DZ_TCR); @@ -388,15 +407,30 @@ static void dz_set_mctrl(struct uart_port *uport, unsigned int mctrl) */ static int dz_startup(struct uart_port *uport) { - struct dz_port *dport = (struct dz_port *)uport; + struct dz_port *dport = to_dport(uport); + struct dz_mux *mux = dport->mux; unsigned long flags; - unsigned short tmp; + int irq_guard; + int ret; + u16 tmp; + + irq_guard = atomic_add_return(1, &mux->irq_guard); + if (irq_guard != 1) + return 0; + + ret = request_irq(dport->port.irq, dz_interrupt, + IRQF_SHARED, "dz", mux); + if (ret) { + atomic_add(-1, &mux->irq_guard); + printk(KERN_ERR "dz: Cannot get IRQ %d!\n", dport->port.irq); + return ret; + } spin_lock_irqsave(&dport->port.lock, flags); - /* enable the interrupt and the scanning */ + /* Enable interrupts. */ tmp = dz_in(dport, DZ_CSR); - tmp |= DZ_RIE | DZ_TIE | DZ_MSE; + tmp |= DZ_RIE | DZ_TIE; dz_out(dport, DZ_CSR, tmp); spin_unlock_irqrestore(&dport->port.lock, flags); @@ -414,7 +448,25 @@ static int dz_startup(struct uart_port *uport) */ static void dz_shutdown(struct uart_port *uport) { - dz_stop_tx(uport); + struct dz_port *dport = to_dport(uport); + struct dz_mux *mux = dport->mux; + unsigned long flags; + int irq_guard; + u16 tmp; + + spin_lock_irqsave(&dport->port.lock, flags); + dz_stop_tx(&dport->port); + spin_unlock_irqrestore(&dport->port.lock, flags); + + irq_guard = atomic_add_return(-1, &mux->irq_guard); + if (!irq_guard) { + /* Disable interrupts. */ + tmp = dz_in(dport, DZ_CSR); + tmp &= ~(DZ_RIE | DZ_TIE); + dz_out(dport, DZ_CSR, tmp); + + free_irq(dport->port.irq, mux); + } } /* @@ -431,7 +483,7 @@ static void dz_shutdown(struct uart_port *uport) */ static unsigned int dz_tx_empty(struct uart_port *uport) { - struct dz_port *dport = (struct dz_port *)uport; + struct dz_port *dport = to_dport(uport); unsigned short tmp, mask = 1 << dport->port.line; tmp = dz_in(dport, DZ_TCR); @@ -446,7 +498,7 @@ static void dz_break_ctl(struct uart_port *uport, int break_state) * FIXME: Can't access BREAK bits in TDR easily; * reuse the code for polled TX. --macro */ - struct dz_port *dport = (struct dz_port *)uport; + struct dz_port *dport = to_dport(uport); unsigned long flags; unsigned short tmp, mask = 1 << dport->port.line; @@ -460,12 +512,69 @@ static void dz_break_ctl(struct uart_port *uport, int break_state) spin_unlock_irqrestore(&uport->lock, flags); } +static int dz_encode_baud_rate(unsigned int baud) +{ + switch (baud) { + case 50: + return DZ_B50; + case 75: + return DZ_B75; + case 110: + return DZ_B110; + case 134: + return DZ_B134; + case 150: + return DZ_B150; + case 300: + return DZ_B300; + case 600: + return DZ_B600; + case 1200: + return DZ_B1200; + case 1800: + return DZ_B1800; + case 2000: + return DZ_B2000; + case 2400: + return DZ_B2400; + case 3600: + return DZ_B3600; + case 4800: + return DZ_B4800; + case 7200: + return DZ_B7200; + case 9600: + return DZ_B9600; + default: + return -1; + } +} + + +static void dz_reset(struct dz_port *dport) +{ + struct dz_mux *mux = dport->mux; + + if (mux->initialised) + return; + + dz_out(dport, DZ_CSR, DZ_CLR); + while (dz_in(dport, DZ_CSR) & DZ_CLR); + iob(); + + /* Enable scanning. */ + dz_out(dport, DZ_CSR, DZ_MSE); + + mux->initialised = 1; +} + static void dz_set_termios(struct uart_port *uport, struct ktermios *termios, struct ktermios *old_termios) { - struct dz_port *dport = (struct dz_port *)uport; + struct dz_port *dport = to_dport(uport); unsigned long flags; unsigned int cflag, baud; + int bflag; cflag = dport->port.line; @@ -492,105 +601,127 @@ static void dz_set_termios(struct uart_port *uport, struct ktermios *termios, cflag |= DZ_PARODD; baud = uart_get_baud_rate(uport, termios, old_termios, 50, 9600); - switch (baud) { - case 50: - cflag |= DZ_B50; - break; - case 75: - cflag |= DZ_B75; - break; - case 110: - cflag |= DZ_B110; - break; - case 134: - cflag |= DZ_B134; - break; - case 150: - cflag |= DZ_B150; - break; - case 300: - cflag |= DZ_B300; - break; - case 600: - cflag |= DZ_B600; - break; - case 1200: - cflag |= DZ_B1200; - break; - case 1800: - cflag |= DZ_B1800; - break; - case 2000: - cflag |= DZ_B2000; - break; - case 2400: - cflag |= DZ_B2400; - break; - case 3600: - cflag |= DZ_B3600; - break; - case 4800: - cflag |= DZ_B4800; - break; - case 7200: - cflag |= DZ_B7200; - break; - case 9600: - default: - cflag |= DZ_B9600; + bflag = dz_encode_baud_rate(baud); + if (bflag < 0) { /* Try to keep unchanged. */ + baud = uart_get_baud_rate(uport, old_termios, NULL, 50, 9600); + bflag = dz_encode_baud_rate(baud); + if (bflag < 0) { /* Resort to 9600. */ + baud = 9600; + bflag = DZ_B9600; + } + tty_termios_encode_baud_rate(termios, baud, baud); } + cflag |= bflag; if (termios->c_cflag & CREAD) cflag |= DZ_RXENAB; spin_lock_irqsave(&dport->port.lock, flags); - dz_out(dport, DZ_LPR, cflag | dport->port.line); + uart_update_timeout(uport, termios->c_cflag, baud); + + dz_out(dport, DZ_LPR, cflag); dport->cflag = cflag; /* setup accept flag */ dport->port.read_status_mask = DZ_OERR; if (termios->c_iflag & INPCK) dport->port.read_status_mask |= DZ_FERR | DZ_PERR; + if (termios->c_iflag & (BRKINT | PARMRK)) + dport->port.read_status_mask |= DZ_BREAK; /* characters to ignore */ uport->ignore_status_mask = 0; + if ((termios->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) + dport->port.ignore_status_mask |= DZ_OERR; if (termios->c_iflag & IGNPAR) dport->port.ignore_status_mask |= DZ_FERR | DZ_PERR; + if (termios->c_iflag & IGNBRK) + dport->port.ignore_status_mask |= DZ_BREAK; spin_unlock_irqrestore(&dport->port.lock, flags); } -static const char *dz_type(struct uart_port *port) +static const char *dz_type(struct uart_port *uport) { return "DZ"; } -static void dz_release_port(struct uart_port *port) +static void dz_release_port(struct uart_port *uport) { - /* nothing to do */ + struct dz_mux *mux = to_dport(uport)->mux; + int map_guard; + + iounmap(uport->membase); + uport->membase = NULL; + + map_guard = atomic_add_return(-1, &mux->map_guard); + if (!map_guard) + release_mem_region(uport->mapbase, dec_kn_slot_size); } -static int dz_request_port(struct uart_port *port) +static int dz_map_port(struct uart_port *uport) { + if (!uport->membase) + uport->membase = ioremap_nocache(uport->mapbase, + dec_kn_slot_size); + if (!uport->membase) { + printk(KERN_ERR "dz: Cannot map MMIO\n"); + return -ENOMEM; + } return 0; } -static void dz_config_port(struct uart_port *port, int flags) +static int dz_request_port(struct uart_port *uport) { - if (flags & UART_CONFIG_TYPE) - port->type = PORT_DZ; + struct dz_mux *mux = to_dport(uport)->mux; + int map_guard; + int ret; + + map_guard = atomic_add_return(1, &mux->map_guard); + if (map_guard == 1) { + if (!request_mem_region(uport->mapbase, dec_kn_slot_size, + "dz")) { + atomic_add(-1, &mux->map_guard); + printk(KERN_ERR + "dz: Unable to reserve MMIO resource\n"); + return -EBUSY; + } + } + ret = dz_map_port(uport); + if (ret) { + map_guard = atomic_add_return(-1, &mux->map_guard); + if (!map_guard) + release_mem_region(uport->mapbase, dec_kn_slot_size); + return ret; + } + return 0; +} + +static void dz_config_port(struct uart_port *uport, int flags) +{ + struct dz_port *dport = to_dport(uport); + + if (flags & UART_CONFIG_TYPE) { + if (dz_request_port(uport)) + return; + + uport->type = PORT_DZ; + + dz_reset(dport); + } } /* - * verify the new serial_struct (for TIOCSSERIAL). + * Verify the new serial_struct (for TIOCSSERIAL). */ -static int dz_verify_port(struct uart_port *port, struct serial_struct *ser) +static int dz_verify_port(struct uart_port *uport, struct serial_struct *ser) { int ret = 0; + if (ser->type != PORT_UNKNOWN && ser->type != PORT_DZ) ret = -EINVAL; - if (ser->irq != port->irq) + if (ser->irq != uport->irq) ret = -EINVAL; return ret; } @@ -617,40 +748,32 @@ static struct uart_ops dz_ops = { static void __init dz_init_ports(void) { static int first = 1; - struct dz_port *dport; unsigned long base; - int i; + int line; if (!first) return; first = 0; - if (mips_machtype == MACH_DS23100 || - mips_machtype == MACH_DS5100) - base = CKSEG1ADDR(KN01_SLOT_BASE + KN01_DZ11); + if (mips_machtype == MACH_DS23100 || mips_machtype == MACH_DS5100) + base = dec_kn_slot_base + KN01_DZ11; else - base = CKSEG1ADDR(KN02_SLOT_BASE + KN02_DZ11); - - for (i = 0, dport = dz_ports; i < DZ_NB_PORT; i++, dport++) { - spin_lock_init(&dport->port.lock); - dport->port.membase = (char *) base; - dport->port.iotype = UPIO_MEM; - dport->port.irq = dec_interrupt[DEC_IRQ_DZ11]; - dport->port.line = i; - dport->port.fifosize = 1; - dport->port.ops = &dz_ops; - dport->port.flags = UPF_BOOT_AUTOCONF; - } -} + base = dec_kn_slot_base + KN02_DZ11; -static void dz_reset(struct dz_port *dport) -{ - dz_out(dport, DZ_CSR, DZ_CLR); - while (dz_in(dport, DZ_CSR) & DZ_CLR); - iob(); + for (line = 0; line < DZ_NB_PORT; line++) { + struct dz_port *dport = &dz_mux.dport[line]; + struct uart_port *uport = &dport->port; - /* enable scanning */ - dz_out(dport, DZ_CSR, DZ_MSE); + dport->mux = &dz_mux; + + uport->irq = dec_interrupt[DEC_IRQ_DZ11]; + uport->fifosize = 1; + uport->iotype = UPIO_MEM; + uport->flags = UPF_BOOT_AUTOCONF; + uport->ops = &dz_ops; + uport->line = line; + uport->mapbase = base; + } } #ifdef CONFIG_SERIAL_DZ_CONSOLE @@ -670,7 +793,7 @@ static void dz_reset(struct dz_port *dport) */ static void dz_console_putchar(struct uart_port *uport, int ch) { - struct dz_port *dport = (struct dz_port *)uport; + struct dz_port *dport = to_dport(uport); unsigned long flags; unsigned short csr, tcr, trdy, mask; int loops = 10000; @@ -685,7 +808,7 @@ static void dz_console_putchar(struct uart_port *uport, int ch) iob(); spin_unlock_irqrestore(&dport->port.lock, flags); - while (loops--) { + do { trdy = dz_in(dport, DZ_CSR); if (!(trdy & DZ_TRDY)) continue; @@ -696,7 +819,7 @@ static void dz_console_putchar(struct uart_port *uport, int ch) dz_out(dport, DZ_TCR, mask); iob(); udelay(2); - } + } while (loops--); if (loops) /* Cannot send otherwise. */ dz_out(dport, DZ_TDR, ch); @@ -717,7 +840,7 @@ static void dz_console_print(struct console *co, const char *str, unsigned int count) { - struct dz_port *dport = &dz_ports[co->index]; + struct dz_port *dport = &dz_mux.dport[co->index]; #ifdef DEBUG_DZ prom_printf((char *) str); #endif @@ -726,22 +849,28 @@ static void dz_console_print(struct console *co, static int __init dz_console_setup(struct console *co, char *options) { - struct dz_port *dport = &dz_ports[co->index]; + struct dz_port *dport = &dz_mux.dport[co->index]; + struct uart_port *uport = &dport->port; int baud = 9600; int bits = 8; int parity = 'n'; int flow = 'n'; + int ret; - if (options) - uart_parse_options(options, &baud, &parity, &bits, &flow); + ret = dz_map_port(uport); + if (ret) + return ret; dz_reset(dport); + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + return uart_set_options(&dport->port, co, baud, parity, bits, flow); } static struct uart_driver dz_reg; -static struct console dz_sercons = { +static struct console dz_console = { .name = "ttyS", .write = dz_console_print, .device = uart_console_device, @@ -755,7 +884,7 @@ static int __init dz_serial_console_init(void) { if (!IOASIC) { dz_init_ports(); - register_console(&dz_sercons); + register_console(&dz_console); return 0; } else return -ENXIO; @@ -763,7 +892,7 @@ static int __init dz_serial_console_init(void) console_initcall(dz_serial_console_init); -#define SERIAL_DZ_CONSOLE &dz_sercons +#define SERIAL_DZ_CONSOLE &dz_console #else #define SERIAL_DZ_CONSOLE NULL #endif /* CONFIG_SERIAL_DZ_CONSOLE */ @@ -789,26 +918,14 @@ static int __init dz_init(void) dz_init_ports(); -#ifndef CONFIG_SERIAL_DZ_CONSOLE - /* reset the chip */ - dz_reset(&dz_ports[0]); -#endif - - if (request_irq(dz_ports[0].port.irq, dz_interrupt, - IRQF_DISABLED, "DZ", &dz_ports[0])) - panic("Unable to register DZ interrupt"); - ret = uart_register_driver(&dz_reg); - if (ret != 0) + if (ret) return ret; for (i = 0; i < DZ_NB_PORT; i++) - uart_add_one_port(&dz_reg, &dz_ports[i].port); + uart_add_one_port(&dz_reg, &dz_mux.dport[i].port); - return ret; + return 0; } module_init(dz_init); - -MODULE_DESCRIPTION("DECstation DZ serial driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/serial/dz.h b/drivers/serial/dz.h index 9674d4e4987..faf169ed27b 100644 --- a/drivers/serial/dz.h +++ b/drivers/serial/dz.h @@ -33,6 +33,8 @@ #define DZ_FERR 0x2000 /* Frame error indicator */ #define DZ_PERR 0x1000 /* Parity error indicator */ +#define DZ_BREAK 0x0800 /* BREAK event software flag */ + #define LINE(x) ((x & DZ_LINE_MASK) >> 8) /* Get the line number from the input buffer */ #define UCHAR(x) ((unsigned char)(x & DZ_RBUF_MASK)) @@ -107,8 +109,8 @@ #define DZ_B7200 0x0D00 #define DZ_B9600 0x0E00 -#define DZ_CREAD 0x1000 /* Enable receiver */ -#define DZ_RXENAB 0x1000 /* enable receive char */ +#define DZ_RXENAB 0x1000 /* Receiver Enable */ + /* * Addresses for the DZ registers */ @@ -124,9 +126,4 @@ #define DZ_XMIT_SIZE 4096 /* buffer size */ #define DZ_WAKEUP_CHARS DZ_XMIT_SIZE/4 -#ifdef MODULE -int init_module (void) -void cleanup_module (void) -#endif - #endif /* DZ_SERIAL_H */ diff --git a/drivers/serial/mpc52xx_uart.c b/drivers/serial/mpc52xx_uart.c index 3c4d29e59b2..a638f23c6c6 100644 --- a/drivers/serial/mpc52xx_uart.c +++ b/drivers/serial/mpc52xx_uart.c @@ -16,6 +16,9 @@ * Some of the code has been inspired/copied from the 2.4 code written * by Dale Farnsworth <dfarnsworth@mvista.com>. * + * Copyright (C) 2008 Freescale Semiconductor Inc. + * John Rigby <jrigby@gmail.com> + * Added support for MPC5121 * Copyright (C) 2006 Secret Lab Technologies Ltd. * Grant Likely <grant.likely@secretlab.ca> * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com> @@ -67,7 +70,6 @@ #include <linux/serial.h> #include <linux/sysrq.h> #include <linux/console.h> - #include <linux/delay.h> #include <linux/io.h> @@ -79,6 +81,7 @@ #endif #include <asm/mpc52xx.h> +#include <asm/mpc512x.h> #include <asm/mpc52xx_psc.h> #if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) @@ -111,8 +114,8 @@ static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM]; static void mpc52xx_uart_of_enumerate(void); #endif + #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase)) -#define FIFO(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1)) /* Forward declaration of the interruption handling routine */ @@ -128,15 +131,301 @@ static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id); #define uart_console(port) (0) #endif +/* ======================================================================== */ +/* PSC fifo operations for isolating differences between 52xx and 512x */ +/* ======================================================================== */ + +struct psc_ops { + void (*fifo_init)(struct uart_port *port); + int (*raw_rx_rdy)(struct uart_port *port); + int (*raw_tx_rdy)(struct uart_port *port); + int (*rx_rdy)(struct uart_port *port); + int (*tx_rdy)(struct uart_port *port); + int (*tx_empty)(struct uart_port *port); + void (*stop_rx)(struct uart_port *port); + void (*start_tx)(struct uart_port *port); + void (*stop_tx)(struct uart_port *port); + void (*rx_clr_irq)(struct uart_port *port); + void (*tx_clr_irq)(struct uart_port *port); + void (*write_char)(struct uart_port *port, unsigned char c); + unsigned char (*read_char)(struct uart_port *port); + void (*cw_disable_ints)(struct uart_port *port); + void (*cw_restore_ints)(struct uart_port *port); + unsigned long (*getuartclk)(void *p); +}; + +#ifdef CONFIG_PPC_MPC52xx +#define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1)) +static void mpc52xx_psc_fifo_init(struct uart_port *port) +{ + struct mpc52xx_psc __iomem *psc = PSC(port); + struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port); + + /* /32 prescaler */ + out_be16(&psc->mpc52xx_psc_clock_select, 0xdd00); + + out_8(&fifo->rfcntl, 0x00); + out_be16(&fifo->rfalarm, 0x1ff); + out_8(&fifo->tfcntl, 0x07); + out_be16(&fifo->tfalarm, 0x80); + + port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY; + out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); +} + +static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port) +{ + return in_be16(&PSC(port)->mpc52xx_psc_status) + & MPC52xx_PSC_SR_RXRDY; +} + +static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port) +{ + return in_be16(&PSC(port)->mpc52xx_psc_status) + & MPC52xx_PSC_SR_TXRDY; +} + + +static int mpc52xx_psc_rx_rdy(struct uart_port *port) +{ + return in_be16(&PSC(port)->mpc52xx_psc_isr) + & port->read_status_mask + & MPC52xx_PSC_IMR_RXRDY; +} + +static int mpc52xx_psc_tx_rdy(struct uart_port *port) +{ + return in_be16(&PSC(port)->mpc52xx_psc_isr) + & port->read_status_mask + & MPC52xx_PSC_IMR_TXRDY; +} + +static int mpc52xx_psc_tx_empty(struct uart_port *port) +{ + return in_be16(&PSC(port)->mpc52xx_psc_status) + & MPC52xx_PSC_SR_TXEMP; +} + +static void mpc52xx_psc_start_tx(struct uart_port *port) +{ + port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY; + out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); +} + +static void mpc52xx_psc_stop_tx(struct uart_port *port) +{ + port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY; + out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); +} + +static void mpc52xx_psc_stop_rx(struct uart_port *port) +{ + port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY; + out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); +} + +static void mpc52xx_psc_rx_clr_irq(struct uart_port *port) +{ +} + +static void mpc52xx_psc_tx_clr_irq(struct uart_port *port) +{ +} + +static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c) +{ + out_8(&PSC(port)->mpc52xx_psc_buffer_8, c); +} + +static unsigned char mpc52xx_psc_read_char(struct uart_port *port) +{ + return in_8(&PSC(port)->mpc52xx_psc_buffer_8); +} + +static void mpc52xx_psc_cw_disable_ints(struct uart_port *port) +{ + out_be16(&PSC(port)->mpc52xx_psc_imr, 0); +} + +static void mpc52xx_psc_cw_restore_ints(struct uart_port *port) +{ + out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); +} + +/* Search for bus-frequency property in this node or a parent */ +static unsigned long mpc52xx_getuartclk(void *p) +{ #if defined(CONFIG_PPC_MERGE) -static struct of_device_id mpc52xx_uart_of_match[] = { - { .type = "serial", .compatible = "fsl,mpc5200-psc-uart", }, - { .type = "serial", .compatible = "mpc5200-psc-uart", }, /* lite5200 */ - { .type = "serial", .compatible = "mpc5200-serial", }, /* efika */ - {}, + /* + * 5200 UARTs have a / 32 prescaler + * but the generic serial code assumes 16 + * so return ipb freq / 2 + */ + return mpc52xx_find_ipb_freq(p) / 2; +#else + pr_debug("unexpected call to mpc52xx_getuartclk with arch/ppc\n"); + return NULL; +#endif +} + +static struct psc_ops mpc52xx_psc_ops = { + .fifo_init = mpc52xx_psc_fifo_init, + .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy, + .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy, + .rx_rdy = mpc52xx_psc_rx_rdy, + .tx_rdy = mpc52xx_psc_tx_rdy, + .tx_empty = mpc52xx_psc_tx_empty, + .stop_rx = mpc52xx_psc_stop_rx, + .start_tx = mpc52xx_psc_start_tx, + .stop_tx = mpc52xx_psc_stop_tx, + .rx_clr_irq = mpc52xx_psc_rx_clr_irq, + .tx_clr_irq = mpc52xx_psc_tx_clr_irq, + .write_char = mpc52xx_psc_write_char, + .read_char = mpc52xx_psc_read_char, + .cw_disable_ints = mpc52xx_psc_cw_disable_ints, + .cw_restore_ints = mpc52xx_psc_cw_restore_ints, + .getuartclk = mpc52xx_getuartclk, +}; + +#endif /* CONFIG_MPC52xx */ + +#ifdef CONFIG_PPC_MPC512x +#define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1)) +static void mpc512x_psc_fifo_init(struct uart_port *port) +{ + out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE); + out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); + out_be32(&FIFO_512x(port)->txalarm, 1); + out_be32(&FIFO_512x(port)->tximr, 0); + + out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE); + out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); + out_be32(&FIFO_512x(port)->rxalarm, 1); + out_be32(&FIFO_512x(port)->rximr, 0); + + out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM); + out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM); +} + +static int mpc512x_psc_raw_rx_rdy(struct uart_port *port) +{ + return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY); +} + +static int mpc512x_psc_raw_tx_rdy(struct uart_port *port) +{ + return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL); +} + +static int mpc512x_psc_rx_rdy(struct uart_port *port) +{ + return in_be32(&FIFO_512x(port)->rxsr) + & in_be32(&FIFO_512x(port)->rximr) + & MPC512x_PSC_FIFO_ALARM; +} + +static int mpc512x_psc_tx_rdy(struct uart_port *port) +{ + return in_be32(&FIFO_512x(port)->txsr) + & in_be32(&FIFO_512x(port)->tximr) + & MPC512x_PSC_FIFO_ALARM; +} + +static int mpc512x_psc_tx_empty(struct uart_port *port) +{ + return in_be32(&FIFO_512x(port)->txsr) + & MPC512x_PSC_FIFO_EMPTY; +} + +static void mpc512x_psc_stop_rx(struct uart_port *port) +{ + unsigned long rx_fifo_imr; + + rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr); + rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; + out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr); +} + +static void mpc512x_psc_start_tx(struct uart_port *port) +{ + unsigned long tx_fifo_imr; + + tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); + tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM; + out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); +} + +static void mpc512x_psc_stop_tx(struct uart_port *port) +{ + unsigned long tx_fifo_imr; + + tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); + tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; + out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); +} + +static void mpc512x_psc_rx_clr_irq(struct uart_port *port) +{ + out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr)); +} + +static void mpc512x_psc_tx_clr_irq(struct uart_port *port) +{ + out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr)); +} + +static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c) +{ + out_8(&FIFO_512x(port)->txdata_8, c); +} + +static unsigned char mpc512x_psc_read_char(struct uart_port *port) +{ + return in_8(&FIFO_512x(port)->rxdata_8); +} + +static void mpc512x_psc_cw_disable_ints(struct uart_port *port) +{ + port->read_status_mask = + in_be32(&FIFO_512x(port)->tximr) << 16 | + in_be32(&FIFO_512x(port)->rximr); + out_be32(&FIFO_512x(port)->tximr, 0); + out_be32(&FIFO_512x(port)->rximr, 0); +} + +static void mpc512x_psc_cw_restore_ints(struct uart_port *port) +{ + out_be32(&FIFO_512x(port)->tximr, + (port->read_status_mask >> 16) & 0x7f); + out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f); +} + +static unsigned long mpc512x_getuartclk(void *p) +{ + return mpc512x_find_ips_freq(p); +} + +static struct psc_ops mpc512x_psc_ops = { + .fifo_init = mpc512x_psc_fifo_init, + .raw_rx_rdy = mpc512x_psc_raw_rx_rdy, + .raw_tx_rdy = mpc512x_psc_raw_tx_rdy, + .rx_rdy = mpc512x_psc_rx_rdy, + .tx_rdy = mpc512x_psc_tx_rdy, + .tx_empty = mpc512x_psc_tx_empty, + .stop_rx = mpc512x_psc_stop_rx, + .start_tx = mpc512x_psc_start_tx, + .stop_tx = mpc512x_psc_stop_tx, + .rx_clr_irq = mpc512x_psc_rx_clr_irq, + .tx_clr_irq = mpc512x_psc_tx_clr_irq, + .write_char = mpc512x_psc_write_char, + .read_char = mpc512x_psc_read_char, + .cw_disable_ints = mpc512x_psc_cw_disable_ints, + .cw_restore_ints = mpc512x_psc_cw_restore_ints, + .getuartclk = mpc512x_getuartclk, }; #endif +static struct psc_ops *psc_ops; /* ======================================================================== */ /* UART operations */ @@ -145,8 +434,7 @@ static struct of_device_id mpc52xx_uart_of_match[] = { static unsigned int mpc52xx_uart_tx_empty(struct uart_port *port) { - int status = in_be16(&PSC(port)->mpc52xx_psc_status); - return (status & MPC52xx_PSC_SR_TXEMP) ? TIOCSER_TEMT : 0; + return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0; } static void @@ -166,16 +454,14 @@ static void mpc52xx_uart_stop_tx(struct uart_port *port) { /* port->lock taken by caller */ - port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY; - out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); + psc_ops->stop_tx(port); } static void mpc52xx_uart_start_tx(struct uart_port *port) { /* port->lock taken by caller */ - port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY; - out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); + psc_ops->start_tx(port); } static void @@ -188,8 +474,7 @@ mpc52xx_uart_send_xchar(struct uart_port *port, char ch) if (ch) { /* Make sure tx interrupts are on */ /* Truly necessary ??? They should be anyway */ - port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY; - out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); + psc_ops->start_tx(port); } spin_unlock_irqrestore(&port->lock, flags); @@ -199,8 +484,7 @@ static void mpc52xx_uart_stop_rx(struct uart_port *port) { /* port->lock taken by caller */ - port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY; - out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); + psc_ops->stop_rx(port); } static void @@ -227,12 +511,12 @@ static int mpc52xx_uart_startup(struct uart_port *port) { struct mpc52xx_psc __iomem *psc = PSC(port); - struct mpc52xx_psc_fifo __iomem *fifo = FIFO(port); int ret; /* Request IRQ */ ret = request_irq(port->irq, mpc52xx_uart_int, - IRQF_DISABLED | IRQF_SAMPLE_RANDOM, "mpc52xx_psc_uart", port); + IRQF_DISABLED | IRQF_SAMPLE_RANDOM | IRQF_SHARED, + "mpc52xx_psc_uart", port); if (ret) return ret; @@ -242,15 +526,7 @@ mpc52xx_uart_startup(struct uart_port *port) out_be32(&psc->sicr, 0); /* UART mode DCD ignored */ - out_be16(&psc->mpc52xx_psc_clock_select, 0xdd00); /* /16 prescaler on */ - - out_8(&fifo->rfcntl, 0x00); - out_be16(&fifo->rfalarm, 0x1ff); - out_8(&fifo->tfcntl, 0x07); - out_be16(&fifo->tfalarm, 0x80); - - port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY; - out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); + psc_ops->fifo_init(port); out_8(&psc->command, MPC52xx_PSC_TX_ENABLE); out_8(&psc->command, MPC52xx_PSC_RX_ENABLE); @@ -333,8 +609,7 @@ mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new, * boot for the console, all stuff is not yet ready to receive at that * time and that just makes the kernel oops */ /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */ - while (!(in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXEMP) && - --j) + while (!mpc52xx_uart_tx_empty(port) && --j) udelay(1); if (!j) @@ -462,11 +737,9 @@ mpc52xx_uart_int_rx_chars(struct uart_port *port) unsigned short status; /* While we can read, do so ! */ - while ((status = in_be16(&PSC(port)->mpc52xx_psc_status)) & - MPC52xx_PSC_SR_RXRDY) { - + while (psc_ops->raw_rx_rdy(port)) { /* Get the char */ - ch = in_8(&PSC(port)->mpc52xx_psc_buffer_8); + ch = psc_ops->read_char(port); /* Handle sysreq char */ #ifdef SUPPORT_SYSRQ @@ -481,6 +754,8 @@ mpc52xx_uart_int_rx_chars(struct uart_port *port) flag = TTY_NORMAL; port->icount.rx++; + status = in_be16(&PSC(port)->mpc52xx_psc_status); + if (status & (MPC52xx_PSC_SR_PE | MPC52xx_PSC_SR_FE | MPC52xx_PSC_SR_RB)) { @@ -510,7 +785,7 @@ mpc52xx_uart_int_rx_chars(struct uart_port *port) tty_flip_buffer_push(tty); - return in_be16(&PSC(port)->mpc52xx_psc_status) & MPC52xx_PSC_SR_RXRDY; + return psc_ops->raw_rx_rdy(port); } static inline int @@ -520,7 +795,7 @@ mpc52xx_uart_int_tx_chars(struct uart_port *port) /* Process out of band chars */ if (port->x_char) { - out_8(&PSC(port)->mpc52xx_psc_buffer_8, port->x_char); + psc_ops->write_char(port, port->x_char); port->icount.tx++; port->x_char = 0; return 1; @@ -533,8 +808,8 @@ mpc52xx_uart_int_tx_chars(struct uart_port *port) } /* Send chars */ - while (in_be16(&PSC(port)->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXRDY) { - out_8(&PSC(port)->mpc52xx_psc_buffer_8, xmit->buf[xmit->tail]); + while (psc_ops->raw_tx_rdy(port)) { + psc_ops->write_char(port, xmit->buf[xmit->tail]); xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); port->icount.tx++; if (uart_circ_empty(xmit)) @@ -560,7 +835,6 @@ mpc52xx_uart_int(int irq, void *dev_id) struct uart_port *port = dev_id; unsigned long pass = ISR_PASS_LIMIT; unsigned int keepgoing; - unsigned short status; spin_lock(&port->lock); @@ -569,18 +843,12 @@ mpc52xx_uart_int(int irq, void *dev_id) /* If we don't find anything to do, we stop */ keepgoing = 0; - /* Read status */ - status = in_be16(&PSC(port)->mpc52xx_psc_isr); - status &= port->read_status_mask; - - /* Do we need to receive chars ? */ - /* For this RX interrupts must be on and some chars waiting */ - if (status & MPC52xx_PSC_IMR_RXRDY) + psc_ops->rx_clr_irq(port); + if (psc_ops->rx_rdy(port)) keepgoing |= mpc52xx_uart_int_rx_chars(port); - /* Do we need to send chars ? */ - /* For this, TX must be ready and TX interrupt enabled */ - if (status & MPC52xx_PSC_IMR_TXRDY) + psc_ops->tx_clr_irq(port); + if (psc_ops->tx_rdy(port)) keepgoing |= mpc52xx_uart_int_tx_chars(port); /* Limit number of iteration */ @@ -647,36 +915,33 @@ static void mpc52xx_console_write(struct console *co, const char *s, unsigned int count) { struct uart_port *port = &mpc52xx_uart_ports[co->index]; - struct mpc52xx_psc __iomem *psc = PSC(port); unsigned int i, j; /* Disable interrupts */ - out_be16(&psc->mpc52xx_psc_imr, 0); + psc_ops->cw_disable_ints(port); /* Wait the TX buffer to be empty */ j = 5000000; /* Maximum wait */ - while (!(in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXEMP) && - --j) + while (!mpc52xx_uart_tx_empty(port) && --j) udelay(1); /* Write all the chars */ for (i = 0; i < count; i++, s++) { /* Line return handling */ if (*s == '\n') - out_8(&psc->mpc52xx_psc_buffer_8, '\r'); + psc_ops->write_char(port, '\r'); /* Send the char */ - out_8(&psc->mpc52xx_psc_buffer_8, *s); + psc_ops->write_char(port, *s); /* Wait the TX buffer to be empty */ j = 20000; /* Maximum wait */ - while (!(in_be16(&psc->mpc52xx_psc_status) & - MPC52xx_PSC_SR_TXEMP) && --j) + while (!mpc52xx_uart_tx_empty(port) && --j) udelay(1); } /* Restore interrupt state */ - out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); + psc_ops->cw_restore_ints(port); } #if !defined(CONFIG_PPC_MERGE) @@ -721,7 +986,7 @@ mpc52xx_console_setup(struct console *co, char *options) { struct uart_port *port = &mpc52xx_uart_ports[co->index]; struct device_node *np = mpc52xx_uart_nodes[co->index]; - unsigned int ipb_freq; + unsigned int uartclk; struct resource res; int ret; @@ -753,17 +1018,16 @@ mpc52xx_console_setup(struct console *co, char *options) return ret; } - /* Search for bus-frequency property in this node or a parent */ - ipb_freq = mpc52xx_find_ipb_freq(np); - if (ipb_freq == 0) { - pr_debug("Could not find IPB bus frequency!\n"); + uartclk = psc_ops->getuartclk(np); + if (uartclk == 0) { + pr_debug("Could not find uart clock frequency!\n"); return -EINVAL; } /* Basic port init. Needed since we use some uart_??? func before * real init for early access */ spin_lock_init(&port->lock); - port->uartclk = ipb_freq / 2; + port->uartclk = uartclk; port->ops = &mpc52xx_uart_ops; port->mapbase = res.start; port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc)); @@ -945,11 +1209,25 @@ static struct platform_driver mpc52xx_uart_platform_driver = { /* OF Platform Driver */ /* ======================================================================== */ +static struct of_device_id mpc52xx_uart_of_match[] = { +#ifdef CONFIG_PPC_MPC52xx + { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, + /* binding used by old lite5200 device trees: */ + { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, + /* binding used by efika: */ + { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, }, +#endif +#ifdef CONFIG_PPC_MPC512x + { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, }, + {}, +#endif +}; + static int __devinit mpc52xx_uart_of_probe(struct of_device *op, const struct of_device_id *match) { int idx = -1; - unsigned int ipb_freq; + unsigned int uartclk; struct uart_port *port = NULL; struct resource res; int ret; @@ -965,10 +1243,9 @@ mpc52xx_uart_of_probe(struct of_device *op, const struct of_device_id *match) pr_debug("Found %s assigned to ttyPSC%x\n", mpc52xx_uart_nodes[idx]->full_name, idx); - /* Search for bus-frequency property in this node or a parent */ - ipb_freq = mpc52xx_find_ipb_freq(op->node); - if (ipb_freq == 0) { - dev_dbg(&op->dev, "Could not find IPB bus frequency!\n"); + uartclk = psc_ops->getuartclk(op->node); + if (uartclk == 0) { + dev_dbg(&op->dev, "Could not find uart clock frequency!\n"); return -EINVAL; } @@ -976,7 +1253,7 @@ mpc52xx_uart_of_probe(struct of_device *op, const struct of_device_id *match) port = &mpc52xx_uart_ports[idx]; spin_lock_init(&port->lock); - port->uartclk = ipb_freq / 2; + port->uartclk = uartclk; port->fifosize = 512; port->iotype = UPIO_MEM; port->flags = UPF_BOOT_AUTOCONF | @@ -1080,15 +1357,19 @@ mpc52xx_uart_of_enumerate(void) static int enum_done; struct device_node *np; const unsigned int *devno; + const struct of_device_id *match; int i; if (enum_done) return; for_each_node_by_type(np, "serial") { - if (!of_match_node(mpc52xx_uart_of_match, np)) + match = of_match_node(mpc52xx_uart_of_match, np); + if (!match) continue; + psc_ops = match->data; + /* Is a particular device number requested? */ devno = of_get_property(np, "port-number", NULL); mpc52xx_uart_of_assign(np, devno ? *devno : -1); @@ -1149,6 +1430,7 @@ mpc52xx_uart_init(void) return ret; } #else + psc_ops = &mpc52xx_psc_ops; ret = platform_driver_register(&mpc52xx_uart_platform_driver); if (ret) { printk(KERN_ERR "%s: platform_driver_register failed (%i)\n", diff --git a/drivers/serial/uartlite.c b/drivers/serial/uartlite.c index bacf68dca01..4e06ab6bcb6 100644 --- a/drivers/serial/uartlite.c +++ b/drivers/serial/uartlite.c @@ -17,10 +17,21 @@ #include <linux/tty.h> #include <linux/delay.h> #include <linux/interrupt.h> +#include <linux/init.h> #include <asm/io.h> #if defined(CONFIG_OF) +#include <linux/of.h> #include <linux/of_device.h> #include <linux/of_platform.h> + +/* Match table for of_platform binding */ +static struct of_device_id ulite_of_match[] __devinitdata = { + { .compatible = "xlnx,opb-uartlite-1.00.b", }, + { .compatible = "xlnx,xps-uartlite-1.00.a", }, + {} +}; +MODULE_DEVICE_TABLE(of, ulite_of_match); + #endif #define ULITE_NAME "ttyUL" @@ -275,6 +286,9 @@ static void ulite_release_port(struct uart_port *port) static int ulite_request_port(struct uart_port *port) { + pr_debug("ulite console: port=%p; port->mapbase=%x\n", + port, port->mapbase); + if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) { dev_err(port->dev, "Memory region busy\n"); return -EBUSY; @@ -375,32 +389,6 @@ static void ulite_console_write(struct console *co, const char *s, spin_unlock_irqrestore(&port->lock, flags); } -#if defined(CONFIG_OF) -static inline void __init ulite_console_of_find_device(int id) -{ - struct device_node *np; - struct resource res; - const unsigned int *of_id; - int rc; - - for_each_compatible_node(np, NULL, "xilinx,uartlite") { - of_id = of_get_property(np, "port-number", NULL); - if ((!of_id) || (*of_id != id)) - continue; - - rc = of_address_to_resource(np, 0, &res); - if (rc) - continue; - - ulite_ports[id].mapbase = res.start; - of_node_put(np); - return; - } -} -#else /* CONFIG_OF */ -static inline void __init ulite_console_of_find_device(int id) { /* do nothing */ } -#endif /* CONFIG_OF */ - static int __init ulite_console_setup(struct console *co, char *options) { struct uart_port *port; @@ -414,11 +402,7 @@ static int __init ulite_console_setup(struct console *co, char *options) port = &ulite_ports[co->index]; - /* Check if it is an OF device */ - if (!port->mapbase) - ulite_console_of_find_device(co->index); - - /* Do we have a device now? */ + /* Has the device been initialized yet? */ if (!port->mapbase) { pr_debug("console on ttyUL%i not present\n", co->index); return -ENODEV; @@ -617,13 +601,6 @@ static int __devexit ulite_of_remove(struct of_device *op) return ulite_release(&op->dev); } -/* Match table for of_platform binding */ -static struct of_device_id __devinit ulite_of_match[] = { - { .type = "serial", .compatible = "xilinx,uartlite", }, - {}, -}; -MODULE_DEVICE_TABLE(of, ulite_of_match); - static struct of_platform_driver ulite_of_driver = { .owner = THIS_MODULE, .name = "uartlite", diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c index e38d3b7c3ad..7b3a8423f48 100644 --- a/drivers/video/xilinxfb.c +++ b/drivers/video/xilinxfb.c @@ -459,8 +459,8 @@ static int __devexit xilinxfb_of_remove(struct of_device *op) } /* Match table for of_platform binding */ -static struct of_device_id __devinit xilinxfb_of_match[] = { - { .compatible = "xilinx,ml300-fb", }, +static struct of_device_id xilinxfb_of_match[] __devinitdata = { + { .compatible = "xlnx,plb-tft-cntlr-ref-1.00.a", }, {}, }; MODULE_DEVICE_TABLE(of, xilinxfb_of_match); diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c index 5747997f8d7..688e435b4d9 100644 --- a/drivers/w1/masters/ds1wm.c +++ b/drivers/w1/masters/ds1wm.c @@ -361,11 +361,12 @@ static int ds1wm_probe(struct platform_device *pdev) goto err1; } ds1wm_data->irq = res->start; - ds1wm_data->active_high = (res->flags & IORESOURCE_IRQ_HIGHEDGE) ? - 1 : 0; + ds1wm_data->active_high = plat->active_high; - set_irq_type(ds1wm_data->irq, ds1wm_data->active_high ? - IRQ_TYPE_EDGE_RISING : IRQ_TYPE_EDGE_FALLING); + if (res->flags & IORESOURCE_IRQ_HIGHEDGE) + set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING); + if (res->flags & IORESOURCE_IRQ_LOWEDGE) + set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING); ret = request_irq(ds1wm_data->irq, ds1wm_isr, IRQF_DISABLED, "ds1wm", ds1wm_data); |