diff options
Diffstat (limited to 'include/asm-m32r')
| -rw-r--r-- | include/asm-m32r/div64.h | 39 | ||||
| -rw-r--r-- | include/asm-m32r/emergency-restart.h | 6 | ||||
| -rw-r--r-- | include/asm-m32r/ide.h | 2 | ||||
| -rw-r--r-- | include/asm-m32r/m32102.h | 1 | ||||
| -rw-r--r-- | include/asm-m32r/m32102peri.h | 468 | ||||
| -rw-r--r-- | include/asm-m32r/m32r.h | 5 | ||||
| -rw-r--r-- | include/asm-m32r/mappi3/mappi3_pld.h | 143 | ||||
| -rw-r--r-- | include/asm-m32r/mmzone.h | 3 | ||||
| -rw-r--r-- | include/asm-m32r/s1d13806.h | 199 | ||||
| -rw-r--r-- | include/asm-m32r/smp.h | 2 | ||||
| -rw-r--r-- | include/asm-m32r/thread_info.h | 2 | ||||
| -rw-r--r-- | include/asm-m32r/topology.h | 44 |
12 files changed, 359 insertions, 555 deletions
diff --git a/include/asm-m32r/div64.h b/include/asm-m32r/div64.h index 417a51bd552..6cd978cefb2 100644 --- a/include/asm-m32r/div64.h +++ b/include/asm-m32r/div64.h @@ -1,38 +1 @@ -#ifndef _ASM_M32R_DIV64 -#define _ASM_M32R_DIV64 - -/* $Id$ */ - -/* unsigned long long division. - * Input: - * unsigned long long n - * unsigned long base - * Output: - * n = n / base; - * return value = n % base; - */ -#define do_div(n, base) \ -({ \ - unsigned long _res, _high, _mid, _low; \ - \ - _low = (n) & 0xffffffffUL; \ - _high = (n) >> 32; \ - if (_high) { \ - _mid = (_high % (unsigned long)(base)) << 16; \ - _high = _high / (unsigned long)(base); \ - _mid += _low >> 16; \ - _low &= 0x0000ffffUL; \ - _low += (_mid % (unsigned long)(base)) << 16; \ - _mid = _mid / (unsigned long)(base); \ - _res = _low % (unsigned long)(base); \ - _low = _low / (unsigned long)(base); \ - n = _low + ((long long)_mid << 16) + \ - ((long long)_high << 32); \ - } else { \ - _res = _low % (unsigned long)(base); \ - n = (_low / (unsigned long)(base)); \ - } \ - _res; \ -}) - -#endif /* _ASM_M32R_DIV64 */ +#include <asm-generic/div64.h> diff --git a/include/asm-m32r/emergency-restart.h b/include/asm-m32r/emergency-restart.h new file mode 100644 index 00000000000..108d8c48e42 --- /dev/null +++ b/include/asm-m32r/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-m32r/ide.h b/include/asm-m32r/ide.h index be64f24e37e..194393bd8be 100644 --- a/include/asm-m32r/ide.h +++ b/include/asm-m32r/ide.h @@ -35,7 +35,7 @@ static __inline__ int ide_default_irq(unsigned long base) { switch (base) { -#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_MAPPI2) +#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3) case 0x1f0: return PLD_IRQ_CFIREQ; default: return 0; diff --git a/include/asm-m32r/m32102.h b/include/asm-m32r/m32102.h index b56034026bf..cb98101f4f6 100644 --- a/include/asm-m32r/m32102.h +++ b/include/asm-m32r/m32102.h @@ -175,6 +175,7 @@ #define M32R_ICU_CR5_PORTL (0x210+M32R_ICU_OFFSET) /* INT4 */ #define M32R_ICU_CR6_PORTL (0x214+M32R_ICU_OFFSET) /* INT5 */ #define M32R_ICU_CR7_PORTL (0x218+M32R_ICU_OFFSET) /* INT6 */ +#define M32R_ICU_CR8_PORTL (0x219+M32R_ICU_OFFSET) /* INT7 */ #define M32R_ICU_CR16_PORTL (0x23C+M32R_ICU_OFFSET) /* MFT0 */ #define M32R_ICU_CR17_PORTL (0x240+M32R_ICU_OFFSET) /* MFT1 */ #define M32R_ICU_CR18_PORTL (0x244+M32R_ICU_OFFSET) /* MFT2 */ diff --git a/include/asm-m32r/m32102peri.h b/include/asm-m32r/m32102peri.h deleted file mode 100644 index 3c12955ad0f..00000000000 --- a/include/asm-m32r/m32102peri.h +++ /dev/null @@ -1,468 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000,2001 by Hiroyuki Kondo - */ - -#ifndef __ASSEMBLY__ - -typedef void V; -typedef char B; -typedef short S; -typedef int W; -typedef long L; -typedef float F; -typedef double D; -typedef unsigned char UB; -typedef unsigned short US; -typedef unsigned int UW; -typedef unsigned long UL; -typedef const unsigned int CUW; - -/********************************* - -M32102 ICU - -*********************************/ -#define ICUISTS (UW *)0xa0EFF004 -#define ICUIREQ0 (UW *)0xa0EFF008 -#define ICUIREQ1 (UW *)0xa0EFF00C - -#define ICUSBICR (UW *)0xa0EFF018 -#define ICUIMASK (UW *)0xa0EFF01C - -#define ICUCR1 (UW *)0xa0EFF200 /* INT0 */ -#define ICUCR2 (UW *)0xa0EFF204 /* INT1 */ -#define ICUCR3 (UW *)0xa0EFF208 /* INT2 */ -#define ICUCR4 (UW *)0xa0EFF20C /* INT3 */ -#define ICUCR5 (UW *)0xa0EFF210 /* INT4 */ -#define ICUCR6 (UW *)0xa0EFF214 /* INT5 */ -#define ICUCR7 (UW *)0xa0EFF218 /* INT6 */ - -#define ICUCR16 (UW *)0xa0EFF23C /* MFT0 */ -#define ICUCR17 (UW *)0xa0EFF240 /* MFT1 */ -#define ICUCR18 (UW *)0xa0EFF244 /* MFT2 */ -#define ICUCR19 (UW *)0xa0EFF248 /* MFT3 */ -#define ICUCR20 (UW *)0xa0EFF24C /* MFT4 */ -#define ICUCR21 (UW *)0xa0EFF250 /* MFT5 */ - -#define ICUCR32 (UW *)0xa0EFF27C /* DMA0 */ -#define ICUCR33 (UW *)0xa0EFF280 /* DMA1 */ - -#define ICUCR48 (UW *)0xa0EFF2BC /* SIO0R */ -#define ICUCR49 (UW *)0xa0EFF2C0 /* SIO0S */ -#define ICUCR50 (UW *)0xa0EFF2C4 /* SIO1R */ -#define ICUCR51 (UW *)0xa0EFF2C8 /* SIO1S */ -#define ICUCR52 (UW *)0xa0EFF2CC /* SIO2R */ -#define ICUCR53 (UW *)0xa0EFF2D0 /* SIO2S */ -#define ICUCR54 (UW *)0xa0EFF2D4 /* SIO3R */ -#define ICUCR55 (UW *)0xa0EFF2D8 /* SIO3S */ -#define ICUCR56 (UW *)0xa0EFF2DC /* SIO4R */ -#define ICUCR57 (UW *)0xa0EFF2E0 /* SIO4S */ - -/********************************* - -M32102 MFT - -*********************************/ -#define MFTCR (US *)0xa0EFC002 -#define MFTRPR (UB *)0xa0EFC006 - -#define MFT0MOD (US *)0xa0EFC102 -#define MFT0BOS (US *)0xa0EFC106 -#define MFT0CUT (US *)0xa0EFC10A -#define MFT0RLD (US *)0xa0EFC10E -#define MFT0CRLD (US *)0xa0EFC112 - -#define MFT1MOD (US *)0xa0EFC202 -#define MFT1BOS (US *)0xa0EFC206 -#define MFT1CUT (US *)0xa0EFC20A -#define MFT1RLD (US *)0xa0EFC20E -#define MFT1CRLD (US *)0xa0EFC212 - -#define MFT2MOD (US *)0xa0EFC302 -#define MFT2BOS (US *)0xa0EFC306 -#define MFT2CUT (US *)0xa0EFC30A -#define MFT2RLD (US *)0xa0EFC30E -#define MFT2CRLD (US *)0xa0EFC312 - -#define MFT3MOD (US *)0xa0EFC402 -#define MFT3CUT (US *)0xa0EFC40A -#define MFT3RLD (US *)0xa0EFC40E -#define MFT3CRLD (US *)0xa0EFC412 - -#define MFT4MOD (US *)0xa0EFC502 -#define MFT4CUT (US *)0xa0EFC50A -#define MFT4RLD (US *)0xa0EFC50E -#define MFT4CRLD (US *)0xa0EFC512 - -#define MFT5MOD (US *)0xa0EFC602 -#define MFT5CUT (US *)0xa0EFC60A -#define MFT5RLD (US *)0xa0EFC60E -#define MFT5CRLD (US *)0xa0EFC612 - -/********************************* - -M32102 SIO - -*********************************/ - -#define SIO0CR (volatile int *)0xa0efd000 -#define SIO0MOD0 (volatile int *)0xa0efd004 -#define SIO0MOD1 (volatile int *)0xa0efd008 -#define SIO0STS (volatile int *)0xa0efd00c -#define SIO0IMASK (volatile int *)0xa0efd010 -#define SIO0BAUR (volatile int *)0xa0efd014 -#define SIO0RBAUR (volatile int *)0xa0efd018 -#define SIO0TXB (volatile int *)0xa0efd01c -#define SIO0RXB (volatile int *)0xa0efd020 - -#define SIO1CR (volatile int *)0xa0efd100 -#define SIO1MOD0 (volatile int *)0xa0efd104 -#define SIO1MOD1 (volatile int *)0xa0efd108 -#define SIO1STS (volatile int *)0xa0efd10c -#define SIO1IMASK (volatile int *)0xa0efd110 -#define SIO1BAUR (volatile int *)0xa0efd114 -#define SIO1RBAUR (volatile int *)0xa0efd118 -#define SIO1TXB (volatile int *)0xa0efd11c -#define SIO1RXB (volatile int *)0xa0efd120 -/********************************* - -M32102 PORT - -*********************************/ -#define PIEN (UB *)0xa0EF1003 /* input enable */ - -#define P0DATA (UB *)0xa0EF1020 /* data */ -#define P1DATA (UB *)0xa0EF1021 -#define P2DATA (UB *)0xa0EF1022 -#define P3DATA (UB *)0xa0EF1023 -#define P4DATA (UB *)0xa0EF1024 -#define P5DATA (UB *)0xa0EF1025 -#define P6DATA (UB *)0xa0EF1026 -#define P7DATA (UB *)0xa0EF1027 - -#define P0DIR (UB *)0xa0EF1040 /* direction */ -#define P1DIR (UB *)0xa0EF1041 -#define P2DIR (UB *)0xa0EF1042 -#define P3DIR (UB *)0xa0EF1043 -#define P4DIR (UB *)0xa0EF1044 -#define P5DIR (UB *)0xa0EF1045 -#define P6DIR (UB *)0xa0EF1046 -#define P7DIR (UB *)0xa0EF1047 - -#define P0MOD (US *)0xa0EF1060 /* mode control */ -#define P1MOD (US *)0xa0EF1062 -#define P2MOD (US *)0xa0EF1064 -#define P3MOD (US *)0xa0EF1066 -#define P4MOD (US *)0xa0EF1068 -#define P5MOD (US *)0xa0EF106A -#define P6MOD (US *)0xa0EF106C -#define P7MOD (US *)0xa0EF106E - -#define P0ODCR (UB *)0xa0EF1080 /* open-drain control */ -#define P1ODCR (UB *)0xa0EF1081 -#define P2ODCR (UB *)0xa0EF1082 -#define P3ODCR (UB *)0xa0EF1083 -#define P4ODCR (UB *)0xa0EF1084 -#define P5ODCR (UB *)0xa0EF1085 -#define P6ODCR (UB *)0xa0EF1086 -#define P7ODCR (UB *)0xa0EF1087 - -/********************************* - -M32102 Cache - -********************************/ - -#define MCCR (US *)0xFFFFFFFE - - -#else /* __ASSEMBLY__ */ - -;; -;; PIO 0x80ef1000 -;; - -#define PIEN 0xa0ef1000 - -#define P0DATA 0xa0ef1020 -#define P1DATA 0xa0ef1021 -#define P2DATA 0xa0ef1022 -#define P3DATA 0xa0ef1023 -#define P4DATA 0xa0ef1024 -#define P5DATA 0xa0ef1025 -#define P6DATA 0xa0ef1026 -#define P7DATA 0xa0ef1027 - -#define P0DIR 0xa0ef1040 -#define P1DIR 0xa0ef1041 -#define P2DIR 0xa0ef1042 -#define P3DIR 0xa0ef1043 -#define P4DIR 0xa0ef1044 -#define P5DIR 0xa0ef1045 -#define P6DIR 0xa0ef1046 -#define P7DIR 0xa0ef1047 - -#define P0MOD 0xa0ef1060 -#define P1MOD 0xa0ef1062 -#define P2MOD 0xa0ef1064 -#define P3MOD 0xa0ef1066 -#define P4MOD 0xa0ef1068 -#define P5MOD 0xa0ef106a -#define P6MOD 0xa0ef106c -#define P7MOD 0xa0ef106e -; -#define P0ODCR 0xa0ef1080 -#define P1ODCR 0xa0ef1081 -#define P2ODCR 0xa0ef1082 -#define P3ODCR 0xa0ef1083 -#define P4ODCR 0xa0ef1084 -#define P5ODCR 0xa0ef1085 -#define P6ODCR 0xa0ef1086 -#define P7ODCR 0xa0ef1087 - -;; -;; WDT 0xa0ef2000 -;; - -#define WDTCR 0xa0ef2000 - - -;; -;; CLK 0xa0ef4000 -;; - -#define CPUCLKCR 0xa0ef4000 -#define CLKMOD 0xa0ef4004 -#define PLLCR 0xa0ef4008 - - -;; -;; BSEL 0xa0ef5000 -;; - -#define BSEL0CR 0xa0ef5000 -#define BSEL1CR 0xa0ef5004 -#define BSEL2CR 0xa0ef5008 -#define BSEL3CR 0xa0ef500c -#define BSEL4CR 0xa0ef5010 -#define BSEL5CR 0xa0ef5014 - - -;; -;; SDRAMC 0xa0ef6000 -;; - -#define SDRF0 0xa0ef6000 -#define SDRF1 0xa0ef6004 -#define SDIR0 0xa0ef6008 -#define SDIR1 0xa0ef600c -#define SDBR 0xa0ef6010 - -;; CH0 -#define SD0ADR 0xa0ef6020 -#define SD0SZ 0xa0ef6022 -#define SD0ER 0xa0ef6024 -#define SD0TR 0xa0ef6028 -#define SD0MOD 0xa0ef602c - -;; CH1 -#define SD1ADR 0xa0ef6040 -#define SD1SZ 0xa0ef6042 -#define SD1ER 0xa0ef6044 -#define SD1TR 0xa0ef6048 -#define SD1MOD 0xa0ef604c - - -;; -;; DMAC 0xa0ef8000 -;; - -#define DMAEN 0xa0ef8000 -#define DMAISTS 0xa0ef8004 -#define DMAEDET 0xa0ef8008 -#define DMAASTS 0xa0ef800c - -;; CH0 -#define DMA0CR0 0xa0ef8100 -#define DMA0CR1 0xa0ef8104 -#define DMA0CSA 0xa0ef8108 -#define DMA0RSA 0xa0ef810c -#define DMA0CDA 0xa0ef8110 -#define DMA0RDA 0xa0ef8114 -#define DMA0CBCUT 0xa0ef8118 -#define DMA0RBCUT 0xa0ef811c - -;; CH1 -#define DMA1CR0 0xa0ef8200 -#define DMA1CR1 0xa0ef8204 -#define DMA1CSA 0xa0ef8208 -#define DMA1RSA 0xa0ef820c -#define DMA1CDA 0xa0ef8210 -#define DMA1RDA 0xa0ef8214 -#define DMA1CBCUT 0xa0ef8218 -#define DMA1RBCUT 0xa0ef821c - - -;; -;; MFT 0xa0efc000 -;; - -#define MFTCR 0xa0efc000 -#define MFTRPR 0xa0efc004 - -;; CH0 -#define MFT0MOD 0xa0efc100 -#define MFT0BOS 0xa0efc104 -#define MFT0CUT 0xa0efc108 -#define MFT0RLD 0xa0efc10c -#define MFT0CMPRLD 0xa0efc110 - -;; CH1 -#define MFT1MOD 0xa0efc200 -#define MFT1BOS 0xa0efc204 -#define MFT1CUT 0xa0efc208 -#define MFT1RLD 0xa0efc20c -#define MFT1CMPRLD 0xa0efc210 - -;; CH2 -#define MFT2MOD 0xa0efc300 -#define MFT2BOS 0xa0efc304 -#define MFT2CUT 0xa0efc308 -#define MFT2RLD 0xa0efc30c -#define MFT2CMPRLD 0xa0efc310 - -;; CH3 -#define MFT3MOD 0xa0efc400 -#define MFT3BOS 0xa0efc404 -#define MFT3CUT 0xa0efc408 -#define MFT3RLD 0xa0efc40c -#define MFT3CMPRLD 0xa0efc410 - -;; CH4 -#define MFT4MOD 0xa0efc500 -#define MFT4BOS 0xa0efc504 -#define MFT4CUT 0xa0efc508 -#define MFT4RLD 0xa0efc50c -#define MFT4CMPRLD 0xa0efc510 - -;; CH5 -#define MFT5MOD 0xa0efc600 -#define MFT5BOS 0xa0efc604 -#define MFT5CUT 0xa0efc608 -#define MFT5RLD 0xa0efc60c -#define MFT5CMPRLD 0xa0efc610 - - -;; -;; SIO 0xa0efd000 -;; - -;; CH0 -#define SIO0CR 0xa0efd000 -#define SIO0MOD0 0xa0efd004 -#define SIO0MOD1 0xa0efd008 -#define SIO0STS 0xa0efd00c -#define SIO0IMASK 0xa0efd010 -#define SIO0BAUR 0xa0efd014 -#define SIO0RBAUR 0xa0efd018 -#define SIO0TXB 0xa0efd01c -#define SIO0RXB 0xa0efd020 - -;; CH1 -#define SIO1CR 0xa0efd100 -#define SIO1MOD0 0xa0efd104 -#define SIO1MOD1 0xa0efd108 -#define SIO1STS 0xa0efd10c -#define SIO1IMASK 0xa0efd110 -#define SIO1BAUR 0xa0efd114 -#define SIO1RBAUR 0xa0efd118 -#define SIO1TXB 0xa0efd11c -#define SIO1RXB 0xa0efd120 - -;; CH2 -#define SIO2CR 0xa0efd200 -#define SIO2MOD0 0xa0efd204 -#define SIO2MOD1 0xa0efd208 -#define SIO2STS 0xa0efd20c -#define SIO2IMASK 0xa0efd210 -#define SIO2BAUR 0xa0efd214 -#define SIO2RBAUR 0xa0efd218 -#define SIO2TXB 0xa0efd21c -#define SIO2RXB 0xa0efd220 - -;; CH3 -#define SIO3CR 0xa0efd300 -#define SIO3MOD0 0xa0efd304 -#define SIO3MOD1 0xa0efd308 -#define SIO3STS 0xa0efd30c -#define SIO3IMASK 0xa0efd310 -#define SIO3BAUR 0xa0efd314 -#define SIO3RBAUR 0xa0efd318 -#define SIO3TXB 0xa0efd31c -#define SIO3RXB 0xa0efd320 - -;; CH4 -#define SIO4CR 0xa0efd400 -#define SIO4MOD0 0xa0efd404 -#define SIO4MOD1 0xa0efd408 -#define SIO4STS 0xa0efd40c -#define SIO4IMASK 0xa0efd410 -#define SIO4BAUR 0xa0efd414 -#define SIO4RBAUR 0xa0efd418 -#define SIO4TXB 0xa0efd41c -#define SIO4RXB 0xa0efd420 - - -;; -;; ICU 0xa0eff000 -;; - -#define ICUISTS 0xa0eff004 -#define ICUIREQ0 0xa0eff008 -#define ICUIREQ1 0xa0eff00c - -#define ICUSBICR 0xa0eff018 -#define ICUIMASK 0xa0eff01c - -#define ICUCR1 0xa0eff200 -#define ICUCR2 0xa0eff204 -#define ICUCR3 0xa0eff208 -#define ICUCR4 0xa0eff20c -#define ICUCR5 0xa0eff210 -#define ICUCR6 0xa0eff214 -#define ICUCR7 0xa0eff218 - -#define ICUCR16 0xa0eff23c -#define ICUCR17 0xa0eff240 -#define ICUCR18 0xa0eff244 -#define ICUCR19 0xa0eff248 -#define ICUCR20 0xa0eff24c -#define ICUCR21 0xa0eff250 - -#define ICUCR32 0xa0eff27c -#define ICUCR33 0xa0eff280 - -#define ICUCR48 0xa0eff2bc -#define ICUCR49 0xa0eff2c0 -#define ICUCR50 0xa0eff2c4 -#define ICUCR51 0xa0eff2c8 -#define ICUCR52 0xa0eff2cc -#define ICUCR53 0xa0eff2d0 -#define ICUCR54 0xa0eff2d4 -#define ICUCR55 0xa0eff2d8 -#define ICUCR56 0xa0eff2dc -#define ICUCR57 0xa0eff2e0 - -;; -;; CACHE -;; - -#define MCCR 0xfffffffc - - -#endif /* __ASSEMBLY__ */ diff --git a/include/asm-m32r/m32r.h b/include/asm-m32r/m32r.h index f116649bbef..ec142be0086 100644 --- a/include/asm-m32r/m32r.h +++ b/include/asm-m32r/m32r.h @@ -16,7 +16,6 @@ || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \ || defined(CONFIG_CHIP_OPSP) #include <asm/m32102.h> -#include <asm/m32102peri.h> #endif /* Platform type */ @@ -36,6 +35,10 @@ #include <asm/mappi2/mappi2_pld.h> #endif /* CONFIG_PLAT_MAPPI2 */ +#if defined(CONFIG_PLAT_MAPPI3) +#include <asm/mappi3/mappi3_pld.h> +#endif /* CONFIG_PLAT_MAPPI3 */ + #if defined(CONFIG_PLAT_USRV) #include <asm/m32700ut/m32700ut_pld.h> #endif diff --git a/include/asm-m32r/mappi3/mappi3_pld.h b/include/asm-m32r/mappi3/mappi3_pld.h new file mode 100644 index 00000000000..3f1551f7f01 --- /dev/null +++ b/include/asm-m32r/mappi3/mappi3_pld.h @@ -0,0 +1,143 @@ +/* + * include/asm/mappi3/mappi3_pld.h + * + * Definitions for Extended IO Logic on MAPPI3 board. + * based on m32700ut_pld.h + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file "COPYING" in the main directory of + * this archive for more details. + * + */ + +#ifndef _MAPPI3_PLD_H +#define _MAPPI3_PLD_H + +#ifndef __ASSEMBLY__ +/* FIXME: + * Some C functions use non-cache address, so can't define non-cache address. + */ +#define PLD_BASE (0x1c000000 /* + NONCACHE_OFFSET */) +#define __reg8 (volatile unsigned char *) +#define __reg16 (volatile unsigned short *) +#define __reg32 (volatile unsigned int *) +#else +#define PLD_BASE (0x1c000000 + NONCACHE_OFFSET) +#define __reg8 +#define __reg16 +#define __reg32 +#endif /* __ASSEMBLY__ */ + +/* CFC */ +#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000) +#define PLD_CFSTS __reg16(PLD_BASE + 0x0002) +#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004) +#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006) +#define PLD_CFCR0 __reg16(PLD_BASE + 0x000a) +#define PLD_CFCR1 __reg16(PLD_BASE + 0x000c) + +/* MMC */ +#define PLD_MMCCR __reg16(PLD_BASE + 0x4000) +#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002) +#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006) +#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a) +#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c) +#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e) +#define PLD_MMCDET __reg16(PLD_BASE + 0x4010) +#define PLD_MMCWP __reg16(PLD_BASE + 0x4012) +#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000) +#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000) +#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000) +#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006) + +/* Power Control of MMC and CF */ +#define PLD_CPCR __reg16(PLD_BASE + 0x14000) + + +/*==== ICU ====*/ +#define M32R_IRQ_PC104 (5) /* INT4(PC/104) */ +#define M32R_IRQ_I2C (28) /* I2C-BUS */ +#define PLD_IRQ_CFIREQ (6) /* INT5 CFC Card Interrupt */ +#define PLD_IRQ_CFC_INSERT (7) /* INT6 CFC Card Insert */ +#define PLD_IRQ_CFC_EJECT (8) /* INT7 CFC Card Eject */ +#define PLD_IRQ_MMCCARD (43) /* MMC Card Insert */ +#define PLD_IRQ_MMCIRQ (44) /* MMC Transfer Done */ + + +#if 0 +/* LED Control + * + * 1: DIP swich side + * 2: Reset switch side + */ +#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002) +#define PLD_IOLED_1_ON 0x001 +#define PLD_IOLED_1_OFF 0x000 +#define PLD_IOLED_2_ON 0x002 +#define PLD_IOLED_2_OFF 0x000 + +/* DIP Switch + * 0: Write-protect of Flash Memory (0:protected, 1:non-protected) + * 1: - + * 2: - + * 3: - + */ +#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004) +#define PLD_IOSWSTS_IOSW2 0x0200 +#define PLD_IOSWSTS_IOSW1 0x0100 +#define PLD_IOSWSTS_IOWP0 0x0001 + +#endif + +/* CRC */ +#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000) +#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002) +#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004) +#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006) +#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008) +#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a) + + +#if 0 +/* RTC */ +#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000) +#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002) +#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004) +#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006) +#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008) + +/* SIO0 */ +#define PLD_ESIO0CR __reg16(PLD_BASE + 0x20000) +#define PLD_ESIO0CR_TXEN 0x0001 +#define PLD_ESIO0CR_RXEN 0x0002 +#define PLD_ESIO0MOD0 __reg16(PLD_BASE + 0x20002) +#define PLD_ESIO0MOD0_CTSS 0x0040 +#define PLD_ESIO0MOD0_RTSS 0x0080 +#define PLD_ESIO0MOD1 __reg16(PLD_BASE + 0x20004) +#define PLD_ESIO0MOD1_LMFS 0x0010 +#define PLD_ESIO0STS __reg16(PLD_BASE + 0x20006) +#define PLD_ESIO0STS_TEMP 0x0001 +#define PLD_ESIO0STS_TXCP 0x0002 +#define PLD_ESIO0STS_RXCP 0x0004 +#define PLD_ESIO0STS_TXSC 0x0100 +#define PLD_ESIO0STS_RXSC 0x0200 +#define PLD_ESIO0STS_TXREADY (PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP) +#define PLD_ESIO0INTCR __reg16(PLD_BASE + 0x20008) +#define PLD_ESIO0INTCR_TXIEN 0x0002 +#define PLD_ESIO0INTCR_RXCEN 0x0004 +#define PLD_ESIO0BAUR __reg16(PLD_BASE + 0x2000a) +#define PLD_ESIO0TXB __reg16(PLD_BASE + 0x2000c) +#define PLD_ESIO0RXB __reg16(PLD_BASE + 0x2000e) + +/* SIM Card */ +#define PLD_SCCR __reg16(PLD_BASE + 0x38000) +#define PLD_SCMOD __reg16(PLD_BASE + 0x38004) +#define PLD_SCSTS __reg16(PLD_BASE + 0x38006) +#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008) +#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a) +#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c) +#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e) + +#endif + +#endif /* _MAPPI3_PLD.H */ diff --git a/include/asm-m32r/mmzone.h b/include/asm-m32r/mmzone.h index ebf0228fec4..d58878ec899 100644 --- a/include/asm-m32r/mmzone.h +++ b/include/asm-m32r/mmzone.h @@ -14,7 +14,6 @@ extern struct pglist_data *node_data[]; #define NODE_DATA(nid) (node_data[nid]) #define node_localnr(pfn, nid) ((pfn) - NODE_DATA(nid)->node_start_pfn) -#define node_mem_map(nid) (NODE_DATA(nid)->node_mem_map) #define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn) #define node_end_pfn(nid) \ ({ \ @@ -32,7 +31,7 @@ extern struct pglist_data *node_data[]; ({ \ unsigned long __pfn = pfn; \ int __node = pfn_to_nid(__pfn); \ - &node_mem_map(__node)[node_localnr(__pfn,__node)]; \ + &NODE_DATA(__node)->node_mem_map[node_localnr(__pfn,__node)]; \ }) #define page_to_pfn(pg) \ diff --git a/include/asm-m32r/s1d13806.h b/include/asm-m32r/s1d13806.h new file mode 100644 index 00000000000..248d36a82d7 --- /dev/null +++ b/include/asm-m32r/s1d13806.h @@ -0,0 +1,199 @@ +//---------------------------------------------------------------------------- +// +// File generated by S1D13806CFG.EXE +// +// Copyright (c) 2000,2001 Epson Research and Development, Inc. +// All rights reserved. +// +//---------------------------------------------------------------------------- + +// Panel: (active) 640x480 77Hz STN Single 8-bit (PCLK=CLKI=25.175MHz) +// Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=33.333MHz) + +#define SWIVEL_VIEW 0 /* 0:none, 1:90 not completed */ + +static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = { + + {0x0001,0x00}, // Miscellaneous Register + {0x01FC,0x00}, // Display Mode Register +#if defined(CONFIG_PLAT_MAPPI) + {0x0004,0x00}, // General IO Pins Configuration Register 0 + {0x0005,0x00}, // General IO Pins Configuration Register 1 + {0x0008,0x00}, // General IO Pins Control Register 0 + {0x0009,0x00}, // General IO Pins Control Register 1 + {0x0010,0x00}, // Memory Clock Configuration Register + {0x0014,0x00}, // LCD Pixel Clock Configuration Register + {0x0018,0x00}, // CRT/TV Pixel Clock Configuration Register + {0x001C,0x00}, // MediaPlug Clock Configuration Register +/* + * .. 10MHz: 0x00 + * .. 30MHz: 0x01 + * 30MHz ..: 0x02 + */ + {0x001E,0x02}, // CPU To Memory Wait State Select Register + {0x0021,0x02}, // DRAM Refresh Rate Register + {0x002A,0x11}, // DRAM Timings Control Register 0 + {0x002B,0x13}, // DRAM Timings Control Register 1 + {0x0020,0x80}, // Memory Configuration Register + {0x0030,0x25}, // Panel Type Register + {0x0031,0x00}, // MOD Rate Register + {0x0032,0x4F}, // LCD Horizontal Display Width Register + {0x0034,0x12}, // LCD Horizontal Non-Display Period Register + {0x0035,0x01}, // TFT FPLINE Start Position Register + {0x0036,0x0B}, // TFT FPLINE Pulse Width Register + {0x0038,0xDF}, // LCD Vertical Display Height Register 0 + {0x0039,0x01}, // LCD Vertical Display Height Register 1 + {0x003A,0x2C}, // LCD Vertical Non-Display Period Register + {0x003B,0x0A}, // TFT FPFRAME Start Position Register + {0x003C,0x01}, // TFT FPFRAME Pulse Width Register + + {0x0041,0x00}, // LCD Miscellaneous Register + {0x0042,0x00}, // LCD Display Start Address Register 0 + {0x0043,0x00}, // LCD Display Start Address Register 1 + {0x0044,0x00}, // LCD Display Start Address Register 2 + +#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3) + {0x0004,0x07}, // GPIO[0:7] direction + {0x0005,0x00}, // GPIO[8:12] direction + {0x0008,0x00}, // GPIO[0:7] data + {0x0009,0x00}, // GPIO[8:12] data + {0x0008,0x04}, // LCD panel Vcc on + {0x0008,0x05}, // LCD panel reset + {0x0010,0x01}, // Memory Clock Configuration Register + {0x0014,0x30}, // LCD Pixel Clock Configuration Register (CLKI 22MHz/4) + {0x0018,0x00}, // CRT/TV Pixel Clock Configuration Register + {0x001C,0x00}, // MediaPlug Clock Configuration Register(10MHz) + {0x001E,0x00}, // CPU To Memory Wait State Select Register + {0x0020,0x80}, // Memory Configuration Register + {0x0021,0x03}, // DRAM Refresh Rate Register + {0x002A,0x00}, // DRAM Timings Control Register 0 + {0x002B,0x01}, // DRAM Timings Control Register 1 + {0x0030,0x25}, // Panel Type Register + {0x0031,0x00}, // MOD Rate Register + {0x0032,0x1d}, // LCD Horizontal Display Width Register + {0x0034,0x05}, // LCD Horizontal Non-Display Period Register + {0x0035,0x01}, // TFT FPLINE Start Position Register + {0x0036,0x01}, // TFT FPLINE Pulse Width Register + {0x0038,0x3F}, // LCD Vertical Display Height Register 0 + {0x0039,0x01}, // LCD Vertical Display Height Register 1 + {0x003A,0x0b}, // LCD Vertical Non-Display Period Register + {0x003B,0x07}, // TFT FPFRAME Start Position Register + {0x003C,0x02}, // TFT FPFRAME Pulse Width Register + + {0x0041,0x00}, // LCD Miscellaneous Register +#if (SWIVEL_VIEW == 0) + {0x0042,0x00}, // LCD Display Start Address Register 0 + {0x0043,0x00}, // LCD Display Start Address Register 1 + {0x0044,0x00}, // LCD Display Start Address Register 2 + +#elif (SWIVEL_VIEW == 1) + // 1024 - W(320) = 0x2C0 + {0x0042,0xC0}, // LCD Display Start Address Register 0 + {0x0043,0x02}, // LCD Display Start Address Register 1 + {0x0044,0x00}, // LCD Display Start Address Register 2 + // 1024 + {0x0046,0x00}, // LCD Memory Address Offset Register 0 + {0x0047,0x02}, // LCD Memory Address Offset Register 1 +#else +#error unsupported SWIVEL_VIEW mode +#endif +#else +#error no platform configuration +#endif /* CONFIG_PLAT_XXX */ + + {0x0048,0x00}, // LCD Pixel Panning Register + {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register + {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register + {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register + {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register + {0x0053,0x01}, // CRT/TV HRTC Start Position Register + {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register + {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0 + {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1 + {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register + {0x0059,0x09}, // CRT/TV VRTC Start Position Register + {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register + {0x005B,0x10}, // TV Output Control Register + + {0x0062,0x00}, // CRT/TV Display Start Address Register 0 + {0x0063,0x00}, // CRT/TV Display Start Address Register 1 + {0x0064,0x00}, // CRT/TV Display Start Address Register 2 + + {0x0068,0x00}, // CRT/TV Pixel Panning Register + {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register + {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register + {0x0070,0x00}, // LCD Ink/Cursor Control Register + {0x0071,0x01}, // LCD Ink/Cursor Start Address Register + {0x0072,0x00}, // LCD Cursor X Position Register 0 + {0x0073,0x00}, // LCD Cursor X Position Register 1 + {0x0074,0x00}, // LCD Cursor Y Position Register 0 + {0x0075,0x00}, // LCD Cursor Y Position Register 1 + {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register + {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register + {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register + {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register + {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register + {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register + {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register + {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register + {0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register + {0x0082,0x00}, // CRT/TV Cursor X Position Register 0 + {0x0083,0x00}, // CRT/TV Cursor X Position Register 1 + {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0 + {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1 + {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register + {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register + {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register + {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register + {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register + {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register + {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register + {0x0100,0x00}, // BitBlt Control Register 0 + {0x0101,0x00}, // BitBlt Control Register 1 + {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register + {0x0103,0x00}, // BitBlt Operation Register + {0x0104,0x00}, // BitBlt Source Start Address Register 0 + {0x0105,0x00}, // BitBlt Source Start Address Register 1 + {0x0106,0x00}, // BitBlt Source Start Address Register 2 + {0x0108,0x00}, // BitBlt Destination Start Address Register 0 + {0x0109,0x00}, // BitBlt Destination Start Address Register 1 + {0x010A,0x00}, // BitBlt Destination Start Address Register 2 + {0x010C,0x00}, // BitBlt Memory Address Offset Register 0 + {0x010D,0x00}, // BitBlt Memory Address Offset Register 1 + {0x0110,0x00}, // BitBlt Width Register 0 + {0x0111,0x00}, // BitBlt Width Register 1 + {0x0112,0x00}, // BitBlt Height Register 0 + {0x0113,0x00}, // BitBlt Height Register 1 + {0x0114,0x00}, // BitBlt Background Color Register 0 + {0x0115,0x00}, // BitBlt Background Color Register 1 + {0x0118,0x00}, // BitBlt Foreground Color Register 0 + {0x0119,0x00}, // BitBlt Foreground Color Register 1 + {0x01E0,0x00}, // Look-Up Table Mode Register + {0x01E2,0x00}, // Look-Up Table Address Register + {0x01F0,0x10}, // Power Save Configuration Register + {0x01F1,0x00}, // Power Save Status Register + {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register +#if (SWIVEL_VIEW == 0) + {0x01FC,0x01}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT) +#elif (SWIVEL_VIEW == 1) + {0x01FC,0x41}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT) +#else +#error unsupported SWIVEL_VIEW mode +#endif /* SWIVEL_VIEW */ + +#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3) + {0x0008,0x07}, // LCD panel Vdd & Vg on +#endif + + {0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp) +#if defined(CONFIG_PLAT_MAPPI) + {0x0046,0x80}, // LCD Memory Address Offset Register 0 + {0x0047,0x02}, // LCD Memory Address Offset Register 1 +#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3) + {0x0046,0xf0}, // LCD Memory Address Offset Register 0 + {0x0047,0x00}, // LCD Memory Address Offset Register 1 +#endif + {0x0060,0x05}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp) + {0x0066,0x80}, // CRT/TV Memory Address Offset Register 0 // takeo + {0x0067,0x02}, // CRT/TV Memory Address Offset Register 1 +}; diff --git a/include/asm-m32r/smp.h b/include/asm-m32r/smp.h index 8cd4d0da4be..b9a20cdad65 100644 --- a/include/asm-m32r/smp.h +++ b/include/asm-m32r/smp.h @@ -66,7 +66,7 @@ extern volatile int cpu_2_physid[NR_CPUS]; #define physid_to_cpu(physid) physid_2_cpu[physid] #define cpu_to_physid(cpu_id) cpu_2_physid[cpu_id] -#define smp_processor_id() (current_thread_info()->cpu) +#define raw_smp_processor_id() (current_thread_info()->cpu) extern cpumask_t cpu_callout_map; #define cpu_possible_map cpu_callout_map diff --git a/include/asm-m32r/thread_info.h b/include/asm-m32r/thread_info.h index 9f3a0fcf6e2..7a6be7727a9 100644 --- a/include/asm-m32r/thread_info.h +++ b/include/asm-m32r/thread_info.h @@ -28,7 +28,7 @@ struct thread_info { unsigned long flags; /* low level flags */ unsigned long status; /* thread-synchronous flags */ __u32 cpu; /* current CPU */ - __s32 preempt_count; /* 0 => preemptable, <0 => BUG */ + int preempt_count; /* 0 => preemptable, <0 => BUG */ mm_segment_t addr_limit; /* thread address space: 0-0xBFFFFFFF for user-thread diff --git a/include/asm-m32r/topology.h b/include/asm-m32r/topology.h index 299a89d91bd..d607eb32bd7 100644 --- a/include/asm-m32r/topology.h +++ b/include/asm-m32r/topology.h @@ -1,48 +1,6 @@ -/* - * linux/include/asm-generic/topology.h - * - * Written by: Matthew Dobson, IBM Corporation - * - * Copyright (C) 2002, IBM Corp. - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Send feedback to <colpatch@us.ibm.com> - */ #ifndef _ASM_M32R_TOPOLOGY_H #define _ASM_M32R_TOPOLOGY_H -/* Other architectures wishing to use this simple topology API should fill - in the below functions as appropriate in their own <asm/topology.h> file. */ - -#define cpu_to_node(cpu) (0) - -#ifndef parent_node -#define parent_node(node) (0) -#endif -#ifndef node_to_cpumask -#define node_to_cpumask(node) (cpu_online_map) -#endif -#ifndef node_to_first_cpu -#define node_to_first_cpu(node) (0) -#endif -#ifndef pcibus_to_cpumask -#define pcibus_to_cpumask(bus) (cpu_online_map) -#endif +#include <asm-generic/topology.h> #endif /* _ASM_M32R_TOPOLOGY_H */ |