diff options
Diffstat (limited to 'include/linux/mfd')
| -rw-r--r-- | include/linux/mfd/abx500/ab8500-gpio.h | 33 | ||||
| -rw-r--r-- | include/linux/mfd/abx500/ab8500.h | 2 | ||||
| -rw-r--r-- | include/linux/mfd/arizona/registers.h | 198 | ||||
| -rw-r--r-- | include/linux/mfd/as3722.h | 5 | ||||
| -rw-r--r-- | include/linux/mfd/lp3943.h | 114 | ||||
| -rw-r--r-- | include/linux/mfd/max14577-private.h | 330 | ||||
| -rw-r--r-- | include/linux/mfd/max14577.h | 69 | ||||
| -rw-r--r-- | include/linux/mfd/max77686-private.h | 2 | ||||
| -rw-r--r-- | include/linux/mfd/max8997-private.h | 2 | ||||
| -rw-r--r-- | include/linux/mfd/max8998-private.h | 2 | ||||
| -rw-r--r-- | include/linux/mfd/mc13xxx.h | 2 | ||||
| -rw-r--r-- | include/linux/mfd/samsung/core.h | 6 | ||||
| -rw-r--r-- | include/linux/mfd/samsung/s5m8767.h | 18 | ||||
| -rw-r--r-- | include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 | ||||
| -rw-r--r-- | include/linux/mfd/ti_am335x_tscadc.h | 8 | ||||
| -rw-r--r-- | include/linux/mfd/tmio.h | 8 | ||||
| -rw-r--r-- | include/linux/mfd/tps6586x.h | 7 | ||||
| -rw-r--r-- | include/linux/mfd/tps65910.h | 5 |
18 files changed, 760 insertions, 52 deletions
diff --git a/include/linux/mfd/abx500/ab8500-gpio.h b/include/linux/mfd/abx500/ab8500-gpio.h deleted file mode 100644 index 172b2f201ae..00000000000 --- a/include/linux/mfd/abx500/ab8500-gpio.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright ST-Ericsson 2010. - * - * Author: Bibek Basu <bibek.basu@stericsson.com> - * Licensed under GPLv2. - */ - -#ifndef _AB8500_GPIO_H -#define _AB8500_GPIO_H - -/* - * Platform data to register a block: only the initial gpio/irq number. - * Array sizes are large enough to contain all AB8500 and AB9540 GPIO - * registers. - */ - -struct abx500_gpio_platform_data { - int gpio_base; -}; - -enum abx500_gpio_pull_updown { - ABX500_GPIO_PULL_DOWN = 0x0, - ABX500_GPIO_PULL_NONE = 0x1, - ABX500_GPIO_PULL_UP = 0x3, -}; - -enum abx500_gpio_vinsel { - ABX500_GPIO_VINSEL_VBAT = 0x0, - ABX500_GPIO_VINSEL_VIN_1V8 = 0x1, - ABX500_GPIO_VINSEL_VDD_BIF = 0x2, -}; - -#endif /* _AB8500_GPIO_H */ diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h index f4acd898dac..a86ca1406fb 100644 --- a/include/linux/mfd/abx500/ab8500.h +++ b/include/linux/mfd/abx500/ab8500.h @@ -368,7 +368,6 @@ struct ab8500 { }; struct ab8500_regulator_platform_data; -struct ab8500_gpio_platform_data; struct ab8500_codec_platform_data; struct ab8500_sysctrl_platform_data; @@ -382,7 +381,6 @@ struct ab8500_platform_data { int irq_base; void (*init) (struct ab8500 *); struct ab8500_regulator_platform_data *regulator; - struct abx500_gpio_platform_data *gpio; struct ab8500_codec_platform_data *codec; struct ab8500_sysctrl_platform_data *sysctrl; }; diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h index cb49417f8ba..fdf3aa376eb 100644 --- a/include/linux/mfd/arizona/registers.h +++ b/include/linux/mfd/arizona/registers.h @@ -139,6 +139,7 @@ #define ARIZONA_INPUT_ENABLES_STATUS 0x301 #define ARIZONA_INPUT_RATE 0x308 #define ARIZONA_INPUT_VOLUME_RAMP 0x309 +#define ARIZONA_HPF_CONTROL 0x30C #define ARIZONA_IN1L_CONTROL 0x310 #define ARIZONA_ADC_DIGITAL_VOLUME_1L 0x311 #define ARIZONA_DMIC1L_CONTROL 0x312 @@ -160,6 +161,7 @@ #define ARIZONA_IN4L_CONTROL 0x328 #define ARIZONA_ADC_DIGITAL_VOLUME_4L 0x329 #define ARIZONA_DMIC4L_CONTROL 0x32A +#define ARIZONA_IN4R_CONTROL 0x32C #define ARIZONA_ADC_DIGITAL_VOLUME_4R 0x32D #define ARIZONA_DMIC4R_CONTROL 0x32E #define ARIZONA_OUTPUT_ENABLES_1 0x400 @@ -224,6 +226,9 @@ #define ARIZONA_PDM_SPK1_CTRL_2 0x491 #define ARIZONA_PDM_SPK2_CTRL_1 0x492 #define ARIZONA_PDM_SPK2_CTRL_2 0x493 +#define ARIZONA_HP1_SHORT_CIRCUIT_CTRL 0x4A0 +#define ARIZONA_HP2_SHORT_CIRCUIT_CTRL 0x4A1 +#define ARIZONA_HP3_SHORT_CIRCUIT_CTRL 0x4A2 #define ARIZONA_SPK_CTRL_2 0x4B5 #define ARIZONA_SPK_CTRL_3 0x4B6 #define ARIZONA_DAC_COMP_1 0x4DC @@ -511,6 +516,38 @@ #define ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME 0x74D #define ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE 0x74E #define ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME 0x74F +#define ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE 0x750 +#define ARIZONA_AIF2TX3MIX_INPUT_1_VOLUME 0x751 +#define ARIZONA_AIF2TX3MIX_INPUT_2_SOURCE 0x752 +#define ARIZONA_AIF2TX3MIX_INPUT_2_VOLUME 0x753 +#define ARIZONA_AIF2TX3MIX_INPUT_3_SOURCE 0x754 +#define ARIZONA_AIF2TX3MIX_INPUT_3_VOLUME 0x755 +#define ARIZONA_AIF2TX3MIX_INPUT_4_SOURCE 0x756 +#define ARIZONA_AIF2TX3MIX_INPUT_4_VOLUME 0x757 +#define ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE 0x758 +#define ARIZONA_AIF2TX4MIX_INPUT_1_VOLUME 0x759 +#define ARIZONA_AIF2TX4MIX_INPUT_2_SOURCE 0x75A +#define ARIZONA_AIF2TX4MIX_INPUT_2_VOLUME 0x75B +#define ARIZONA_AIF2TX4MIX_INPUT_3_SOURCE 0x75C +#define ARIZONA_AIF2TX4MIX_INPUT_3_VOLUME 0x75D +#define ARIZONA_AIF2TX4MIX_INPUT_4_SOURCE 0x75E +#define ARIZONA_AIF2TX4MIX_INPUT_4_VOLUME 0x75F +#define ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE 0x760 +#define ARIZONA_AIF2TX5MIX_INPUT_1_VOLUME 0x761 +#define ARIZONA_AIF2TX5MIX_INPUT_2_SOURCE 0x762 +#define ARIZONA_AIF2TX5MIX_INPUT_2_VOLUME 0x763 +#define ARIZONA_AIF2TX5MIX_INPUT_3_SOURCE 0x764 +#define ARIZONA_AIF2TX5MIX_INPUT_3_VOLUME 0x765 +#define ARIZONA_AIF2TX5MIX_INPUT_4_SOURCE 0x766 +#define ARIZONA_AIF2TX5MIX_INPUT_4_VOLUME 0x767 +#define ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE 0x768 +#define ARIZONA_AIF2TX6MIX_INPUT_1_VOLUME 0x769 +#define ARIZONA_AIF2TX6MIX_INPUT_2_SOURCE 0x76A +#define ARIZONA_AIF2TX6MIX_INPUT_2_VOLUME 0x76B +#define ARIZONA_AIF2TX6MIX_INPUT_3_SOURCE 0x76C +#define ARIZONA_AIF2TX6MIX_INPUT_3_VOLUME 0x76D +#define ARIZONA_AIF2TX6MIX_INPUT_4_SOURCE 0x76E +#define ARIZONA_AIF2TX6MIX_INPUT_4_VOLUME 0x76F #define ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE 0x780 #define ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME 0x781 #define ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE 0x782 @@ -2196,6 +2233,15 @@ /* * R677 (0x2A5) - Mic Detect 3 */ +#define ARIZONA_MICD_LVL_0 0x0004 /* MICD_LVL - [2] */ +#define ARIZONA_MICD_LVL_1 0x0008 /* MICD_LVL - [3] */ +#define ARIZONA_MICD_LVL_2 0x0010 /* MICD_LVL - [4] */ +#define ARIZONA_MICD_LVL_3 0x0020 /* MICD_LVL - [5] */ +#define ARIZONA_MICD_LVL_4 0x0040 /* MICD_LVL - [6] */ +#define ARIZONA_MICD_LVL_5 0x0080 /* MICD_LVL - [7] */ +#define ARIZONA_MICD_LVL_6 0x0100 /* MICD_LVL - [8] */ +#define ARIZONA_MICD_LVL_7 0x0200 /* MICD_LVL - [9] */ +#define ARIZONA_MICD_LVL_8 0x0400 /* MICD_LVL - [10] */ #define ARIZONA_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */ #define ARIZONA_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */ #define ARIZONA_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */ @@ -2293,8 +2339,18 @@ #define ARIZONA_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */ /* + * R780 (0x30C) - HPF Control + */ +#define ARIZONA_IN_HPF_CUT_MASK 0x0007 /* IN_HPF_CUT [2:0] */ +#define ARIZONA_IN_HPF_CUT_SHIFT 0 /* IN_HPF_CUT [2:0] */ +#define ARIZONA_IN_HPF_CUT_WIDTH 3 /* IN_HPF_CUT [2:0] */ + +/* * R784 (0x310) - IN1L Control */ +#define ARIZONA_IN1L_HPF_MASK 0x8000 /* IN1L_HPF - [15] */ +#define ARIZONA_IN1L_HPF_SHIFT 15 /* IN1L_HPF - [15] */ +#define ARIZONA_IN1L_HPF_WIDTH 1 /* IN1L_HPF - [15] */ #define ARIZONA_IN1_OSR_MASK 0x6000 /* IN1_OSR - [14:13] */ #define ARIZONA_IN1_OSR_SHIFT 13 /* IN1_OSR - [14:13] */ #define ARIZONA_IN1_OSR_WIDTH 2 /* IN1_OSR - [14:13] */ @@ -2333,6 +2389,9 @@ /* * R788 (0x314) - IN1R Control */ +#define ARIZONA_IN1R_HPF_MASK 0x8000 /* IN1R_HPF - [15] */ +#define ARIZONA_IN1R_HPF_SHIFT 15 /* IN1R_HPF - [15] */ +#define ARIZONA_IN1R_HPF_WIDTH 1 /* IN1R_HPF - [15] */ #define ARIZONA_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */ #define ARIZONA_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */ #define ARIZONA_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */ @@ -2362,6 +2421,9 @@ /* * R792 (0x318) - IN2L Control */ +#define ARIZONA_IN2L_HPF_MASK 0x8000 /* IN2L_HPF - [15] */ +#define ARIZONA_IN2L_HPF_SHIFT 15 /* IN2L_HPF - [15] */ +#define ARIZONA_IN2L_HPF_WIDTH 1 /* IN2L_HPF - [15] */ #define ARIZONA_IN2_OSR_MASK 0x6000 /* IN2_OSR - [14:13] */ #define ARIZONA_IN2_OSR_SHIFT 13 /* IN2_OSR - [14:13] */ #define ARIZONA_IN2_OSR_WIDTH 2 /* IN2_OSR - [14:13] */ @@ -2400,6 +2462,9 @@ /* * R796 (0x31C) - IN2R Control */ +#define ARIZONA_IN2R_HPF_MASK 0x8000 /* IN2R_HPF - [15] */ +#define ARIZONA_IN2R_HPF_SHIFT 15 /* IN2R_HPF - [15] */ +#define ARIZONA_IN2R_HPF_WIDTH 1 /* IN2R_HPF - [15] */ #define ARIZONA_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */ #define ARIZONA_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */ #define ARIZONA_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */ @@ -2429,6 +2494,9 @@ /* * R800 (0x320) - IN3L Control */ +#define ARIZONA_IN3L_HPF_MASK 0x8000 /* IN3L_HPF - [15] */ +#define ARIZONA_IN3L_HPF_SHIFT 15 /* IN3L_HPF - [15] */ +#define ARIZONA_IN3L_HPF_WIDTH 1 /* IN3L_HPF - [15] */ #define ARIZONA_IN3_OSR_MASK 0x6000 /* IN3_OSR - [14:13] */ #define ARIZONA_IN3_OSR_SHIFT 13 /* IN3_OSR - [14:13] */ #define ARIZONA_IN3_OSR_WIDTH 2 /* IN3_OSR - [14:13] */ @@ -2467,6 +2535,9 @@ /* * R804 (0x324) - IN3R Control */ +#define ARIZONA_IN3R_HPF_MASK 0x8000 /* IN3R_HPF - [15] */ +#define ARIZONA_IN3R_HPF_SHIFT 15 /* IN3R_HPF - [15] */ +#define ARIZONA_IN3R_HPF_WIDTH 1 /* IN3R_HPF - [15] */ #define ARIZONA_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */ #define ARIZONA_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */ #define ARIZONA_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */ @@ -2496,6 +2567,9 @@ /* * R808 (0x328) - IN4 Control */ +#define ARIZONA_IN4L_HPF_MASK 0x8000 /* IN4L_HPF - [15] */ +#define ARIZONA_IN4L_HPF_SHIFT 15 /* IN4L_HPF - [15] */ +#define ARIZONA_IN4L_HPF_WIDTH 1 /* IN4L_HPF - [15] */ #define ARIZONA_IN4_OSR_MASK 0x6000 /* IN4_OSR - [14:13] */ #define ARIZONA_IN4_OSR_SHIFT 13 /* IN4_OSR - [14:13] */ #define ARIZONA_IN4_OSR_WIDTH 2 /* IN4_OSR - [14:13] */ @@ -2526,6 +2600,13 @@ #define ARIZONA_IN4L_DMIC_DLY_WIDTH 6 /* IN4L_DMIC_DLY - [5:0] */ /* + * R812 (0x32C) - IN4R Control + */ +#define ARIZONA_IN4R_HPF_MASK 0x8000 /* IN4R_HPF - [15] */ +#define ARIZONA_IN4R_HPF_SHIFT 15 /* IN4R_HPF - [15] */ +#define ARIZONA_IN4R_HPF_WIDTH 1 /* IN4R_HPF - [15] */ + +/* * R813 (0x32D) - ADC Digital Volume 4R */ #define ARIZONA_IN_VU 0x0200 /* IN_VU */ @@ -3138,6 +3219,10 @@ /* * R1088 (0x440) - DRE Enable */ +#define ARIZONA_DRE3R_ENA 0x0020 /* DRE3R_ENA */ +#define ARIZONA_DRE3R_ENA_MASK 0x0020 /* DRE3R_ENA */ +#define ARIZONA_DRE3R_ENA_SHIFT 5 /* DRE3R_ENA */ +#define ARIZONA_DRE3R_ENA_WIDTH 1 /* DRE3R_ENA */ #define ARIZONA_DRE3L_ENA 0x0010 /* DRE3L_ENA */ #define ARIZONA_DRE3L_ENA_MASK 0x0010 /* DRE3L_ENA */ #define ARIZONA_DRE3L_ENA_SHIFT 4 /* DRE3L_ENA */ @@ -3260,6 +3345,30 @@ #define ARIZONA_SPK2_FMT_WIDTH 1 /* SPK2_FMT */ /* + * R1184 (0x4A0) - HP1 Short Circuit Ctrl + */ +#define ARIZONA_HP1_SC_ENA 0x1000 /* HP1_SC_ENA */ +#define ARIZONA_HP1_SC_ENA_MASK 0x1000 /* HP1_SC_ENA */ +#define ARIZONA_HP1_SC_ENA_SHIFT 12 /* HP1_SC_ENA */ +#define ARIZONA_HP1_SC_ENA_WIDTH 1 /* HP1_SC_ENA */ + +/* + * R1185 (0x4A1) - HP2 Short Circuit Ctrl + */ +#define ARIZONA_HP2_SC_ENA 0x1000 /* HP2_SC_ENA */ +#define ARIZONA_HP2_SC_ENA_MASK 0x1000 /* HP2_SC_ENA */ +#define ARIZONA_HP2_SC_ENA_SHIFT 12 /* HP2_SC_ENA */ +#define ARIZONA_HP2_SC_ENA_WIDTH 1 /* HP2_SC_ENA */ + +/* + * R1186 (0x4A2) - HP3 Short Circuit Ctrl + */ +#define ARIZONA_HP3_SC_ENA 0x1000 /* HP3_SC_ENA */ +#define ARIZONA_HP3_SC_ENA_MASK 0x1000 /* HP3_SC_ENA */ +#define ARIZONA_HP3_SC_ENA_SHIFT 12 /* HP3_SC_ENA */ +#define ARIZONA_HP3_SC_ENA_WIDTH 1 /* HP3_SC_ENA */ + +/* * R1244 (0x4DC) - DAC comp 1 */ #define ARIZONA_OUT_COMP_COEFF_MASK 0xFFFF /* OUT_COMP_COEFF - [15:0] */ @@ -3726,6 +3835,35 @@ #define ARIZONA_AIF2TX2_SLOT_WIDTH 6 /* AIF2TX2_SLOT - [5:0] */ /* + * R1355 (0x54B) - AIF2 Frame Ctrl 5 + */ +#define ARIZONA_AIF2TX3_SLOT_MASK 0x003F /* AIF2TX3_SLOT - [5:0] */ +#define ARIZONA_AIF2TX3_SLOT_SHIFT 0 /* AIF2TX3_SLOT - [5:0] */ +#define ARIZONA_AIF2TX3_SLOT_WIDTH 6 /* AIF2TX3_SLOT - [5:0] */ + +/* + * R1356 (0x54C) - AIF2 Frame Ctrl 6 + */ +#define ARIZONA_AIF2TX4_SLOT_MASK 0x003F /* AIF2TX4_SLOT - [5:0] */ +#define ARIZONA_AIF2TX4_SLOT_SHIFT 0 /* AIF2TX4_SLOT - [5:0] */ +#define ARIZONA_AIF2TX4_SLOT_WIDTH 6 /* AIF2TX4_SLOT - [5:0] */ + + +/* + * R1357 (0x54D) - AIF2 Frame Ctrl 7 + */ +#define ARIZONA_AIF2TX5_SLOT_MASK 0x003F /* AIF2TX5_SLOT - [5:0] */ +#define ARIZONA_AIF2TX5_SLOT_SHIFT 0 /* AIF2TX5_SLOT - [5:0] */ +#define ARIZONA_AIF2TX5_SLOT_WIDTH 6 /* AIF2TX5_SLOT - [5:0] */ + +/* + * R1358 (0x54E) - AIF2 Frame Ctrl 8 + */ +#define ARIZONA_AIF2TX6_SLOT_MASK 0x003F /* AIF2TX6_SLOT - [5:0] */ +#define ARIZONA_AIF2TX6_SLOT_SHIFT 0 /* AIF2TX6_SLOT - [5:0] */ +#define ARIZONA_AIF2TX6_SLOT_WIDTH 6 /* AIF2TX6_SLOT - [5:0] */ + +/* * R1361 (0x551) - AIF2 Frame Ctrl 11 */ #define ARIZONA_AIF2RX1_SLOT_MASK 0x003F /* AIF2RX1_SLOT - [5:0] */ @@ -3740,8 +3878,52 @@ #define ARIZONA_AIF2RX2_SLOT_WIDTH 6 /* AIF2RX2_SLOT - [5:0] */ /* + * R1363 (0x553) - AIF2 Frame Ctrl 13 + */ +#define ARIZONA_AIF2RX3_SLOT_MASK 0x003F /* AIF2RX3_SLOT - [5:0] */ +#define ARIZONA_AIF2RX3_SLOT_SHIFT 0 /* AIF2RX3_SLOT - [5:0] */ +#define ARIZONA_AIF2RX3_SLOT_WIDTH 6 /* AIF2RX3_SLOT - [5:0] */ + +/* + * R1364 (0x554) - AIF2 Frame Ctrl 14 + */ +#define ARIZONA_AIF2RX4_SLOT_MASK 0x003F /* AIF2RX4_SLOT - [5:0] */ +#define ARIZONA_AIF2RX4_SLOT_SHIFT 0 /* AIF2RX4_SLOT - [5:0] */ +#define ARIZONA_AIF2RX4_SLOT_WIDTH 6 /* AIF2RX4_SLOT - [5:0] */ + +/* + * R1365 (0x555) - AIF2 Frame Ctrl 15 + */ +#define ARIZONA_AIF2RX5_SLOT_MASK 0x003F /* AIF2RX5_SLOT - [5:0] */ +#define ARIZONA_AIF2RX5_SLOT_SHIFT 0 /* AIF2RX5_SLOT - [5:0] */ +#define ARIZONA_AIF2RX5_SLOT_WIDTH 6 /* AIF2RX5_SLOT - [5:0] */ + +/* + * R1366 (0x556) - AIF2 Frame Ctrl 16 + */ +#define ARIZONA_AIF2RX6_SLOT_MASK 0x003F /* AIF2RX6_SLOT - [5:0] */ +#define ARIZONA_AIF2RX6_SLOT_SHIFT 0 /* AIF2RX6_SLOT - [5:0] */ +#define ARIZONA_AIF2RX6_SLOT_WIDTH 6 /* AIF2RX6_SLOT - [5:0] */ + +/* * R1369 (0x559) - AIF2 Tx Enables */ +#define ARIZONA_AIF2TX6_ENA 0x0020 /* AIF2TX6_ENA */ +#define ARIZONA_AIF2TX6_ENA_MASK 0x0020 /* AIF2TX6_ENA */ +#define ARIZONA_AIF2TX6_ENA_SHIFT 5 /* AIF2TX6_ENA */ +#define ARIZONA_AIF2TX6_ENA_WIDTH 1 /* AIF2TX6_ENA */ +#define ARIZONA_AIF2TX5_ENA 0x0010 /* AIF2TX5_ENA */ +#define ARIZONA_AIF2TX5_ENA_MASK 0x0010 /* AIF2TX5_ENA */ +#define ARIZONA_AIF2TX5_ENA_SHIFT 4 /* AIF2TX5_ENA */ +#define ARIZONA_AIF2TX5_ENA_WIDTH 1 /* AIF2TX5_ENA */ +#define ARIZONA_AIF2TX4_ENA 0x0008 /* AIF2TX4_ENA */ +#define ARIZONA_AIF2TX4_ENA_MASK 0x0008 /* AIF2TX4_ENA */ +#define ARIZONA_AIF2TX4_ENA_SHIFT 3 /* AIF2TX4_ENA */ +#define ARIZONA_AIF2TX4_ENA_WIDTH 1 /* AIF2TX4_ENA */ +#define ARIZONA_AIF2TX3_ENA 0x0004 /* AIF2TX3_ENA */ +#define ARIZONA_AIF2TX3_ENA_MASK 0x0004 /* AIF2TX3_ENA */ +#define ARIZONA_AIF2TX3_ENA_SHIFT 2 /* AIF2TX3_ENA */ +#define ARIZONA_AIF2TX3_ENA_WIDTH 1 /* AIF2TX3_ENA */ #define ARIZONA_AIF2TX2_ENA 0x0002 /* AIF2TX2_ENA */ #define ARIZONA_AIF2TX2_ENA_MASK 0x0002 /* AIF2TX2_ENA */ #define ARIZONA_AIF2TX2_ENA_SHIFT 1 /* AIF2TX2_ENA */ @@ -3754,6 +3936,22 @@ /* * R1370 (0x55A) - AIF2 Rx Enables */ +#define ARIZONA_AIF2RX6_ENA 0x0020 /* AIF2RX6_ENA */ +#define ARIZONA_AIF2RX6_ENA_MASK 0x0020 /* AIF2RX6_ENA */ +#define ARIZONA_AIF2RX6_ENA_SHIFT 5 /* AIF2RX6_ENA */ +#define ARIZONA_AIF2RX6_ENA_WIDTH 1 /* AIF2RX6_ENA */ +#define ARIZONA_AIF2RX5_ENA 0x0010 /* AIF2RX5_ENA */ +#define ARIZONA_AIF2RX5_ENA_MASK 0x0010 /* AIF2RX5_ENA */ +#define ARIZONA_AIF2RX5_ENA_SHIFT 4 /* AIF2RX5_ENA */ +#define ARIZONA_AIF2RX5_ENA_WIDTH 1 /* AIF2RX5_ENA */ +#define ARIZONA_AIF2RX4_ENA 0x0008 /* AIF2RX4_ENA */ +#define ARIZONA_AIF2RX4_ENA_MASK 0x0008 /* AIF2RX4_ENA */ +#define ARIZONA_AIF2RX4_ENA_SHIFT 3 /* AIF2RX4_ENA */ +#define ARIZONA_AIF2RX4_ENA_WIDTH 1 /* AIF2RX4_ENA */ +#define ARIZONA_AIF2RX3_ENA 0x0004 /* AIF2RX3_ENA */ +#define ARIZONA_AIF2RX3_ENA_MASK 0x0004 /* AIF2RX3_ENA */ +#define ARIZONA_AIF2RX3_ENA_SHIFT 2 /* AIF2RX3_ENA */ +#define ARIZONA_AIF2RX3_ENA_WIDTH 1 /* AIF2RX3_ENA */ #define ARIZONA_AIF2RX2_ENA 0x0002 /* AIF2RX2_ENA */ #define ARIZONA_AIF2RX2_ENA_MASK 0x0002 /* AIF2RX2_ENA */ #define ARIZONA_AIF2RX2_ENA_SHIFT 1 /* AIF2RX2_ENA */ diff --git a/include/linux/mfd/as3722.h b/include/linux/mfd/as3722.h index 16bf8a0dcd9..8d43e9f2a84 100644 --- a/include/linux/mfd/as3722.h +++ b/include/linux/mfd/as3722.h @@ -151,6 +151,7 @@ #define AS3722_ASIC_ID1_REG 0x90 #define AS3722_ASIC_ID2_REG 0x91 #define AS3722_LOCK_REG 0x9E +#define AS3722_FUSE7_REG 0xA7 #define AS3722_MAX_REGISTER 0xF4 #define AS3722_SD0_EXT_ENABLE_MASK 0x03 @@ -224,6 +225,7 @@ #define AS3722_SD_VSEL_MASK 0x7F #define AS3722_SD0_VSEL_MIN 0x01 #define AS3722_SD0_VSEL_MAX 0x5A +#define AS3722_SD0_VSEL_LOW_VOL_MAX 0x6E #define AS3722_SD2_VSEL_MIN 0x01 #define AS3722_SD2_VSEL_MAX 0x7F @@ -314,6 +316,7 @@ #define AS3722_GPIO_IOSF_GPIO_INTERRUPT_IN AS3722_GPIO_IOSF_VAL(3) #define AS3722_GPIO_IOSF_ISINK_PWM_IN AS3722_GPIO_IOSF_VAL(4) #define AS3722_GPIO_IOSF_VOLTAGE_STBY AS3722_GPIO_IOSF_VAL(5) +#define AS3722_GPIO_IOSF_SD0_OUT AS3722_GPIO_IOSF_VAL(6) #define AS3722_GPIO_IOSF_PWR_GOOD_OUT AS3722_GPIO_IOSF_VAL(7) #define AS3722_GPIO_IOSF_Q32K_OUT AS3722_GPIO_IOSF_VAL(8) #define AS3722_GPIO_IOSF_WATCHDOG_IN AS3722_GPIO_IOSF_VAL(9) @@ -341,6 +344,8 @@ #define AS3722_EXT_CONTROL_ENABLE2 0x2 #define AS3722_EXT_CONTROL_ENABLE3 0x3 +#define AS3722_FUSE7_SD0_LOW_VOLTAGE BIT(4) + /* Interrupt IDs */ enum as3722_irq { AS3722_IRQ_LID, diff --git a/include/linux/mfd/lp3943.h b/include/linux/mfd/lp3943.h new file mode 100644 index 00000000000..3490db78298 --- /dev/null +++ b/include/linux/mfd/lp3943.h @@ -0,0 +1,114 @@ +/* + * TI/National Semiconductor LP3943 Device + * + * Copyright 2013 Texas Instruments + * + * Author: Milo Kim <milo.kim@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __MFD_LP3943_H__ +#define __MFD_LP3943_H__ + +#include <linux/gpio.h> +#include <linux/pwm.h> +#include <linux/regmap.h> + +/* Registers */ +#define LP3943_REG_GPIO_A 0x00 +#define LP3943_REG_GPIO_B 0x01 +#define LP3943_REG_PRESCALE0 0x02 +#define LP3943_REG_PWM0 0x03 +#define LP3943_REG_PRESCALE1 0x04 +#define LP3943_REG_PWM1 0x05 +#define LP3943_REG_MUX0 0x06 +#define LP3943_REG_MUX1 0x07 +#define LP3943_REG_MUX2 0x08 +#define LP3943_REG_MUX3 0x09 + +/* Bit description for LP3943_REG_MUX0 ~ 3 */ +#define LP3943_GPIO_IN 0x00 +#define LP3943_GPIO_OUT_HIGH 0x00 +#define LP3943_GPIO_OUT_LOW 0x01 +#define LP3943_DIM_PWM0 0x02 +#define LP3943_DIM_PWM1 0x03 + +#define LP3943_NUM_PWMS 2 + +enum lp3943_pwm_output { + LP3943_PWM_OUT0, + LP3943_PWM_OUT1, + LP3943_PWM_OUT2, + LP3943_PWM_OUT3, + LP3943_PWM_OUT4, + LP3943_PWM_OUT5, + LP3943_PWM_OUT6, + LP3943_PWM_OUT7, + LP3943_PWM_OUT8, + LP3943_PWM_OUT9, + LP3943_PWM_OUT10, + LP3943_PWM_OUT11, + LP3943_PWM_OUT12, + LP3943_PWM_OUT13, + LP3943_PWM_OUT14, + LP3943_PWM_OUT15, +}; + +/* + * struct lp3943_pwm_map + * @output: Output pins which are mapped to each PWM channel + * @num_outputs: Number of outputs + */ +struct lp3943_pwm_map { + enum lp3943_pwm_output *output; + int num_outputs; +}; + +/* + * struct lp3943_platform_data + * @pwms: Output channel definitions for PWM channel 0 and 1 + */ +struct lp3943_platform_data { + struct lp3943_pwm_map *pwms[LP3943_NUM_PWMS]; +}; + +/* + * struct lp3943_reg_cfg + * @reg: Register address + * @mask: Register bit mask to be updated + * @shift: Register bit shift + */ +struct lp3943_reg_cfg { + u8 reg; + u8 mask; + u8 shift; +}; + +/* + * struct lp3943 + * @dev: Parent device pointer + * @regmap: Used for I2C communication on accessing registers + * @pdata: LP3943 platform specific data + * @mux_cfg: Register configuration for pin MUX + * @pin_used: Bit mask for output pin used. + * This bitmask is used for pin assignment management. + * 1 = pin used, 0 = available. + * Only LSB 16 bits are used, but it is unsigned long type + * for atomic bitwise operations. + */ +struct lp3943 { + struct device *dev; + struct regmap *regmap; + struct lp3943_platform_data *pdata; + const struct lp3943_reg_cfg *mux_cfg; + unsigned long pin_used; +}; + +int lp3943_read_byte(struct lp3943 *lp3943, u8 reg, u8 *read); +int lp3943_write_byte(struct lp3943 *lp3943, u8 reg, u8 data); +int lp3943_update_bits(struct lp3943 *lp3943, u8 reg, u8 mask, u8 data); +#endif diff --git a/include/linux/mfd/max14577-private.h b/include/linux/mfd/max14577-private.h new file mode 100644 index 00000000000..a3d0185196d --- /dev/null +++ b/include/linux/mfd/max14577-private.h @@ -0,0 +1,330 @@ +/* + * max14577-private.h - Common API for the Maxim 14577 internal sub chip + * + * Copyright (C) 2013 Samsung Electrnoics + * Chanwoo Choi <cw00.choi@samsung.com> + * Krzysztof Kozlowski <k.kozlowski@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAX14577_PRIVATE_H__ +#define __MAX14577_PRIVATE_H__ + +#include <linux/i2c.h> +#include <linux/regmap.h> + +#define MAX14577_REG_INVALID (0xff) + +/* Slave addr = 0x4A: Interrupt */ +enum max14577_reg { + MAX14577_REG_DEVICEID = 0x00, + MAX14577_REG_INT1 = 0x01, + MAX14577_REG_INT2 = 0x02, + MAX14577_REG_INT3 = 0x03, + MAX14577_REG_STATUS1 = 0x04, + MAX14577_REG_STATUS2 = 0x05, + MAX14577_REG_STATUS3 = 0x06, + MAX14577_REG_INTMASK1 = 0x07, + MAX14577_REG_INTMASK2 = 0x08, + MAX14577_REG_INTMASK3 = 0x09, + MAX14577_REG_CDETCTRL1 = 0x0A, + MAX14577_REG_RFU = 0x0B, + MAX14577_REG_CONTROL1 = 0x0C, + MAX14577_REG_CONTROL2 = 0x0D, + MAX14577_REG_CONTROL3 = 0x0E, + MAX14577_REG_CHGCTRL1 = 0x0F, + MAX14577_REG_CHGCTRL2 = 0x10, + MAX14577_REG_CHGCTRL3 = 0x11, + MAX14577_REG_CHGCTRL4 = 0x12, + MAX14577_REG_CHGCTRL5 = 0x13, + MAX14577_REG_CHGCTRL6 = 0x14, + MAX14577_REG_CHGCTRL7 = 0x15, + + MAX14577_REG_END, +}; + +/* Slave addr = 0x4A: MUIC */ +enum max14577_muic_reg { + MAX14577_MUIC_REG_STATUS1 = 0x04, + MAX14577_MUIC_REG_STATUS2 = 0x05, + MAX14577_MUIC_REG_CONTROL1 = 0x0C, + MAX14577_MUIC_REG_CONTROL3 = 0x0E, + + MAX14577_MUIC_REG_END, +}; + +enum max14577_muic_charger_type { + MAX14577_CHARGER_TYPE_NONE = 0, + MAX14577_CHARGER_TYPE_USB, + MAX14577_CHARGER_TYPE_DOWNSTREAM_PORT, + MAX14577_CHARGER_TYPE_DEDICATED_CHG, + MAX14577_CHARGER_TYPE_SPECIAL_500MA, + MAX14577_CHARGER_TYPE_SPECIAL_1A, + MAX14577_CHARGER_TYPE_RESERVED, + MAX14577_CHARGER_TYPE_DEAD_BATTERY = 7, +}; + +/* MAX14577 interrupts */ +#define INT1_ADC_MASK (0x1 << 0) +#define INT1_ADCLOW_MASK (0x1 << 1) +#define INT1_ADCERR_MASK (0x1 << 2) + +#define INT2_CHGTYP_MASK (0x1 << 0) +#define INT2_CHGDETRUN_MASK (0x1 << 1) +#define INT2_DCDTMR_MASK (0x1 << 2) +#define INT2_DBCHG_MASK (0x1 << 3) +#define INT2_VBVOLT_MASK (0x1 << 4) + +#define INT3_EOC_MASK (0x1 << 0) +#define INT3_CGMBC_MASK (0x1 << 1) +#define INT3_OVP_MASK (0x1 << 2) +#define INT3_MBCCHGERR_MASK (0x1 << 3) + +/* MAX14577 DEVICE ID register */ +#define DEVID_VENDORID_SHIFT 0 +#define DEVID_DEVICEID_SHIFT 3 +#define DEVID_VENDORID_MASK (0x07 << DEVID_VENDORID_SHIFT) +#define DEVID_DEVICEID_MASK (0x1f << DEVID_DEVICEID_SHIFT) + +/* MAX14577 STATUS1 register */ +#define STATUS1_ADC_SHIFT 0 +#define STATUS1_ADCLOW_SHIFT 5 +#define STATUS1_ADCERR_SHIFT 6 +#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT) +#define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT) +#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT) + +/* MAX14577 STATUS2 register */ +#define STATUS2_CHGTYP_SHIFT 0 +#define STATUS2_CHGDETRUN_SHIFT 3 +#define STATUS2_DCDTMR_SHIFT 4 +#define STATUS2_DBCHG_SHIFT 5 +#define STATUS2_VBVOLT_SHIFT 6 +#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT) +#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT) +#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT) +#define STATUS2_DBCHG_MASK (0x1 << STATUS2_DBCHG_SHIFT) +#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT) + +/* MAX14577 CONTROL1 register */ +#define COMN1SW_SHIFT 0 +#define COMP2SW_SHIFT 3 +#define MICEN_SHIFT 6 +#define IDBEN_SHIFT 7 +#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT) +#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT) +#define MICEN_MASK (0x1 << MICEN_SHIFT) +#define IDBEN_MASK (0x1 << IDBEN_SHIFT) +#define CLEAR_IDBEN_MICEN_MASK (COMN1SW_MASK | COMP2SW_MASK) +#define CTRL1_SW_USB ((1 << COMP2SW_SHIFT) \ + | (1 << COMN1SW_SHIFT)) +#define CTRL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \ + | (2 << COMN1SW_SHIFT)) +#define CTRL1_SW_UART ((3 << COMP2SW_SHIFT) \ + | (3 << COMN1SW_SHIFT)) +#define CTRL1_SW_OPEN ((0 << COMP2SW_SHIFT) \ + | (0 << COMN1SW_SHIFT)) + +/* MAX14577 CONTROL2 register */ +#define CTRL2_LOWPWR_SHIFT (0) +#define CTRL2_ADCEN_SHIFT (1) +#define CTRL2_CPEN_SHIFT (2) +#define CTRL2_SFOUTASRT_SHIFT (3) +#define CTRL2_SFOUTORD_SHIFT (4) +#define CTRL2_ACCDET_SHIFT (5) +#define CTRL2_USBCPINT_SHIFT (6) +#define CTRL2_RCPS_SHIFT (7) +#define CTRL2_LOWPWR_MASK (0x1 << CTRL2_LOWPWR_SHIFT) +#define CTRL2_ADCEN_MASK (0x1 << CTRL2_ADCEN_SHIFT) +#define CTRL2_CPEN_MASK (0x1 << CTRL2_CPEN_SHIFT) +#define CTRL2_SFOUTASRT_MASK (0x1 << CTRL2_SFOUTASRT_SHIFT) +#define CTRL2_SFOUTORD_MASK (0x1 << CTRL2_SFOUTORD_SHIFT) +#define CTRL2_ACCDET_MASK (0x1 << CTRL2_ACCDET_SHIFT) +#define CTRL2_USBCPINT_MASK (0x1 << CTRL2_USBCPINT_SHIFT) +#define CTRL2_RCPS_MASK (0x1 << CTR2_RCPS_SHIFT) + +#define CTRL2_CPEN1_LOWPWR0 ((1 << CTRL2_CPEN_SHIFT) | \ + (0 << CTRL2_LOWPWR_SHIFT)) +#define CTRL2_CPEN0_LOWPWR1 ((0 << CTRL2_CPEN_SHIFT) | \ + (1 << CTRL2_LOWPWR_SHIFT)) + +/* MAX14577 CONTROL3 register */ +#define CTRL3_JIGSET_SHIFT 0 +#define CTRL3_BOOTSET_SHIFT 2 +#define CTRL3_ADCDBSET_SHIFT 4 +#define CTRL3_JIGSET_MASK (0x3 << CTRL3_JIGSET_SHIFT) +#define CTRL3_BOOTSET_MASK (0x3 << CTRL3_BOOTSET_SHIFT) +#define CTRL3_ADCDBSET_MASK (0x3 << CTRL3_ADCDBSET_SHIFT) + +/* Slave addr = 0x4A: Charger */ +enum max14577_charger_reg { + MAX14577_CHG_REG_STATUS3 = 0x06, + MAX14577_CHG_REG_CHG_CTRL1 = 0x0F, + MAX14577_CHG_REG_CHG_CTRL2 = 0x10, + MAX14577_CHG_REG_CHG_CTRL3 = 0x11, + MAX14577_CHG_REG_CHG_CTRL4 = 0x12, + MAX14577_CHG_REG_CHG_CTRL5 = 0x13, + MAX14577_CHG_REG_CHG_CTRL6 = 0x14, + MAX14577_CHG_REG_CHG_CTRL7 = 0x15, + + MAX14577_CHG_REG_END, +}; + +/* MAX14577 STATUS3 register */ +#define STATUS3_EOC_SHIFT 0 +#define STATUS3_CGMBC_SHIFT 1 +#define STATUS3_OVP_SHIFT 2 +#define STATUS3_MBCCHGERR_SHIFT 3 +#define STATUS3_EOC_MASK (0x1 << STATUS3_EOC_SHIFT) +#define STATUS3_CGMBC_MASK (0x1 << STATUS3_CGMBC_SHIFT) +#define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT) +#define STATUS3_MBCCHGERR_MASK (0x1 << STATUS3_MBCCHGERR_SHIFT) + +/* MAX14577 CDETCTRL1 register */ +#define CDETCTRL1_CHGDETEN_SHIFT 0 +#define CDETCTRL1_CHGTYPMAN_SHIFT 1 +#define CDETCTRL1_DCDEN_SHIFT 2 +#define CDETCTRL1_DCD2SCT_SHIFT 3 +#define CDETCTRL1_DCHKTM_SHIFT 4 +#define CDETCTRL1_DBEXIT_SHIFT 5 +#define CDETCTRL1_DBIDLE_SHIFT 6 +#define CDETCTRL1_CDPDET_SHIFT 7 +#define CDETCTRL1_CHGDETEN_MASK (0x1 << CDETCTRL1_CHGDETEN_SHIFT) +#define CDETCTRL1_CHGTYPMAN_MASK (0x1 << CDETCTRL1_CHGTYPMAN_SHIFT) +#define CDETCTRL1_DCDEN_MASK (0x1 << CDETCTRL1_DCDEN_SHIFT) +#define CDETCTRL1_DCD2SCT_MASK (0x1 << CDETCTRL1_DCD2SCT_SHIFT) +#define CDETCTRL1_DCHKTM_MASK (0x1 << CDETCTRL1_DCHKTM_SHIFT) +#define CDETCTRL1_DBEXIT_MASK (0x1 << CDETCTRL1_DBEXIT_SHIFT) +#define CDETCTRL1_DBIDLE_MASK (0x1 << CDETCTRL1_DBIDLE_SHIFT) +#define CDETCTRL1_CDPDET_MASK (0x1 << CDETCTRL1_CDPDET_SHIFT) + +/* MAX14577 CHGCTRL1 register */ +#define CHGCTRL1_TCHW_SHIFT 4 +#define CHGCTRL1_TCHW_MASK (0x7 << CHGCTRL1_TCHW_SHIFT) + +/* MAX14577 CHGCTRL2 register */ +#define CHGCTRL2_MBCHOSTEN_SHIFT 6 +#define CHGCTRL2_MBCHOSTEN_MASK (0x1 << CHGCTRL2_MBCHOSTEN_SHIFT) +#define CHGCTRL2_VCHGR_RC_SHIFT 7 +#define CHGCTRL2_VCHGR_RC_MASK (0x1 << CHGCTRL2_VCHGR_RC_SHIFT) + +/* MAX14577 CHGCTRL3 register */ +#define CHGCTRL3_MBCCVWRC_SHIFT 0 +#define CHGCTRL3_MBCCVWRC_MASK (0xf << CHGCTRL3_MBCCVWRC_SHIFT) + +/* MAX14577 CHGCTRL4 register */ +#define CHGCTRL4_MBCICHWRCH_SHIFT 0 +#define CHGCTRL4_MBCICHWRCH_MASK (0xf << CHGCTRL4_MBCICHWRCH_SHIFT) +#define CHGCTRL4_MBCICHWRCL_SHIFT 4 +#define CHGCTRL4_MBCICHWRCL_MASK (0x1 << CHGCTRL4_MBCICHWRCL_SHIFT) + +/* MAX14577 CHGCTRL5 register */ +#define CHGCTRL5_EOCS_SHIFT 0 +#define CHGCTRL5_EOCS_MASK (0xf << CHGCTRL5_EOCS_SHIFT) + +/* MAX14577 CHGCTRL6 register */ +#define CHGCTRL6_AUTOSTOP_SHIFT 5 +#define CHGCTRL6_AUTOSTOP_MASK (0x1 << CHGCTRL6_AUTOSTOP_SHIFT) + +/* MAX14577 CHGCTRL7 register */ +#define CHGCTRL7_OTPCGHCVS_SHIFT 0 +#define CHGCTRL7_OTPCGHCVS_MASK (0x3 << CHGCTRL7_OTPCGHCVS_SHIFT) + +/* MAX14577 regulator current limits (as in CHGCTRL4 register), uA */ +#define MAX14577_REGULATOR_CURRENT_LIMIT_MIN 90000 +#define MAX14577_REGULATOR_CURRENT_LIMIT_HIGH_START 200000 +#define MAX14577_REGULATOR_CURRENT_LIMIT_HIGH_STEP 50000 +#define MAX14577_REGULATOR_CURRENT_LIMIT_MAX 950000 + +/* MAX14577 regulator SFOUT LDO voltage, fixed, uV */ +#define MAX14577_REGULATOR_SAFEOUT_VOLTAGE 4900000 + +enum max14577_irq_source { + MAX14577_IRQ_INT1 = 0, + MAX14577_IRQ_INT2, + MAX14577_IRQ_INT3, + + MAX14577_IRQ_REGS_NUM, +}; + +enum max14577_irq { + /* INT1 */ + MAX14577_IRQ_INT1_ADC, + MAX14577_IRQ_INT1_ADCLOW, + MAX14577_IRQ_INT1_ADCERR, + + /* INT2 */ + MAX14577_IRQ_INT2_CHGTYP, + MAX14577_IRQ_INT2_CHGDETRUN, + MAX14577_IRQ_INT2_DCDTMR, + MAX14577_IRQ_INT2_DBCHG, + MAX14577_IRQ_INT2_VBVOLT, + + /* INT3 */ + MAX14577_IRQ_INT3_EOC, + MAX14577_IRQ_INT3_CGMBC, + MAX14577_IRQ_INT3_OVP, + MAX14577_IRQ_INT3_MBCCHGERR, + + MAX14577_IRQ_NUM, +}; + +struct max14577 { + struct device *dev; + struct i2c_client *i2c; /* Slave addr = 0x4A */ + + struct regmap *regmap; + + struct regmap_irq_chip_data *irq_data; + int irq; + + /* Device ID */ + u8 vendor_id; /* Vendor Identification */ + u8 device_id; /* Chip Version */ +}; + +/* MAX14577 shared regmap API function */ +static inline int max14577_read_reg(struct regmap *map, u8 reg, u8 *dest) +{ + unsigned int val; + int ret; + + ret = regmap_read(map, reg, &val); + *dest = val; + + return ret; +} + +static inline int max14577_bulk_read(struct regmap *map, u8 reg, u8 *buf, + int count) +{ + return regmap_bulk_read(map, reg, buf, count); +} + +static inline int max14577_write_reg(struct regmap *map, u8 reg, u8 value) +{ + return regmap_write(map, reg, value); +} + +static inline int max14577_bulk_write(struct regmap *map, u8 reg, u8 *buf, + int count) +{ + return regmap_bulk_write(map, reg, buf, count); +} + +static inline int max14577_update_reg(struct regmap *map, u8 reg, u8 mask, + u8 val) +{ + return regmap_update_bits(map, reg, mask, val); +} + +#endif /* __MAX14577_PRIVATE_H__ */ diff --git a/include/linux/mfd/max14577.h b/include/linux/mfd/max14577.h new file mode 100644 index 00000000000..247b021dfaa --- /dev/null +++ b/include/linux/mfd/max14577.h @@ -0,0 +1,69 @@ +/* + * max14577.h - Driver for the Maxim 14577 + * + * Copyright (C) 2013 Samsung Electrnoics + * Chanwoo Choi <cw00.choi@samsung.com> + * Krzysztof Kozlowski <k.kozlowski@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * This driver is based on max8997.h + * + * MAX14577 has MUIC, Charger devices. + * The devices share the same I2C bus and interrupt line + * included in this mfd driver. + */ + +#ifndef __MAX14577_H__ +#define __MAX14577_H__ + +#include <linux/mfd/max14577-private.h> +#include <linux/regulator/consumer.h> + +/* + * MAX14577 Regulator + */ + +/* MAX14577 regulator IDs */ +enum max14577_regulators { + MAX14577_SAFEOUT = 0, + MAX14577_CHARGER, + + MAX14577_REG_MAX, +}; + +struct max14577_regulator_platform_data { + int id; + struct regulator_init_data *initdata; + struct device_node *of_node; +}; + +/* + * MAX14577 MFD platform data + */ +struct max14577_platform_data { + /* IRQ */ + int irq_base; + + /* current control GPIOs */ + int gpio_pogo_vbatt_en; + int gpio_pogo_vbus_en; + + /* current control GPIO control function */ + int (*set_gpio_pogo_vbatt_en) (int gpio_val); + int (*set_gpio_pogo_vbus_en) (int gpio_val); + + int (*set_gpio_pogo_cb) (int new_dev); + + struct max14577_regulator_platform_data *regulators; +}; + +#endif /* __MAX14577_H__ */ diff --git a/include/linux/mfd/max77686-private.h b/include/linux/mfd/max77686-private.h index d327d4971e4..8c75a9c8dfa 100644 --- a/include/linux/mfd/max77686-private.h +++ b/include/linux/mfd/max77686-private.h @@ -1,5 +1,5 @@ /* - * max77686.h - Voltage regulator driver for the Maxim 77686 + * max77686-private.h - Voltage regulator driver for the Maxim 77686 * * Copyright (C) 2012 Samsung Electrnoics * Chiwoong Byun <woong.byun@samsung.com> diff --git a/include/linux/mfd/max8997-private.h b/include/linux/mfd/max8997-private.h index fb465dfbb59..ad1ae7f345a 100644 --- a/include/linux/mfd/max8997-private.h +++ b/include/linux/mfd/max8997-private.h @@ -1,5 +1,5 @@ /* - * max8997.h - Voltage regulator driver for the Maxim 8997 + * max8997-private.h - Voltage regulator driver for the Maxim 8997 * * Copyright (C) 2010 Samsung Electrnoics * MyungJoo Ham <myungjoo.ham@samsung.com> diff --git a/include/linux/mfd/max8998-private.h b/include/linux/mfd/max8998-private.h index 84844e0a570..4ecb24b4b86 100644 --- a/include/linux/mfd/max8998-private.h +++ b/include/linux/mfd/max8998-private.h @@ -1,5 +1,5 @@ /* - * max8998.h - Voltage regulator driver for the Maxim 8998 + * max8998-private.h - Voltage regulator driver for the Maxim 8998 * * Copyright (C) 2009-2010 Samsung Electrnoics * Kyungmin Park <kyungmin.park@samsung.com> diff --git a/include/linux/mfd/mc13xxx.h b/include/linux/mfd/mc13xxx.h index ac2230561fc..ac39d910e70 100644 --- a/include/linux/mfd/mc13xxx.h +++ b/include/linux/mfd/mc13xxx.h @@ -21,8 +21,6 @@ int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val); int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset, u32 mask, u32 val); -int mc13xxx_get_flags(struct mc13xxx *mc13xxx); - int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq, irq_handler_t handler, const char *name, void *dev); int mc13xxx_irq_request_nounmask(struct mc13xxx *mc13xxx, int irq, diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h index cab2dd27907..41c9bde410c 100644 --- a/include/linux/mfd/samsung/core.h +++ b/include/linux/mfd/samsung/core.h @@ -59,12 +59,6 @@ int sec_irq_init(struct sec_pmic_dev *sec_pmic); void sec_irq_exit(struct sec_pmic_dev *sec_pmic); int sec_irq_resume(struct sec_pmic_dev *sec_pmic); -extern int sec_reg_read(struct sec_pmic_dev *sec_pmic, u8 reg, void *dest); -extern int sec_bulk_read(struct sec_pmic_dev *sec_pmic, u8 reg, int count, u8 *buf); -extern int sec_reg_write(struct sec_pmic_dev *sec_pmic, u8 reg, u8 value); -extern int sec_bulk_write(struct sec_pmic_dev *sec_pmic, u8 reg, int count, u8 *buf); -extern int sec_reg_update(struct sec_pmic_dev *sec_pmic, u8 reg, u8 val, u8 mask); - struct sec_platform_data { struct sec_regulator_data *regulators; struct sec_opmode_data *opmode; diff --git a/include/linux/mfd/samsung/s5m8767.h b/include/linux/mfd/samsung/s5m8767.h index 306a95fc558..2ab0b0f0364 100644 --- a/include/linux/mfd/samsung/s5m8767.h +++ b/include/linux/mfd/samsung/s5m8767.h @@ -183,6 +183,22 @@ enum s5m8767_regulators { S5M8767_REG_MAX, }; -#define S5M8767_ENCTRL_SHIFT 6 +#define S5M8767_ENCTRL_SHIFT 6 +#define S5M8767_ENCTRL_MASK (0x3 << S5M8767_ENCTRL_SHIFT) + +/* + * Values for BUCK_RAMP field in DVS_RAMP register, matching raw values + * in mV/us. + */ +enum s5m8767_dvs_buck_ramp_values { + S5M8767_DVS_BUCK_RAMP_5 = 0x4, + S5M8767_DVS_BUCK_RAMP_10 = 0x9, + S5M8767_DVS_BUCK_RAMP_12_5 = 0xb, + S5M8767_DVS_BUCK_RAMP_25 = 0xd, + S5M8767_DVS_BUCK_RAMP_50 = 0xe, + S5M8767_DVS_BUCK_RAMP_100 = 0xf, +}; +#define S5M8767_DVS_BUCK_RAMP_SHIFT 4 +#define S5M8767_DVS_BUCK_RAMP_MASK (0xf << S5M8767_DVS_BUCK_RAMP_SHIFT) #endif /* __LINUX_MFD_S5M8767_H */ diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index b6d36b38b99..866e355fa40 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -212,6 +212,7 @@ #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4) #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI0 (0x2 << 4) #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI1 (0x3 << 4) +#define IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT 2 #define IMX6Q_GPR3_HDMI_MUX_CTL_MASK (0x3 << 2) #define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI0 (0x0 << 2) #define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI1 (0x1 << 2) diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h index d498d98f0c2..fb96c84dada 100644 --- a/include/linux/mfd/ti_am335x_tscadc.h +++ b/include/linux/mfd/ti_am335x_tscadc.h @@ -159,6 +159,9 @@ struct ti_tscadc_dev { int adc_cell; /* -1 if not used */ struct mfd_cell cells[TSCADC_CELLS]; u32 reg_se_cache; + bool adc_waiting; + bool adc_in_use; + wait_queue_head_t reg_se_wait; spinlock_t reg_lock; unsigned int clk_div; @@ -176,8 +179,9 @@ static inline struct ti_tscadc_dev *ti_tscadc_dev_get(struct platform_device *p) return *tscadc_dev; } -void am335x_tsc_se_update(struct ti_tscadc_dev *tsadc); -void am335x_tsc_se_set(struct ti_tscadc_dev *tsadc, u32 val); +void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val); +void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val); void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val); +void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc); #endif diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h index b22883d6050..8f6f2e91e7a 100644 --- a/include/linux/mfd/tmio.h +++ b/include/linux/mfd/tmio.h @@ -76,6 +76,13 @@ */ #define TMIO_MMC_USE_GPIO_CD (1 << 5) +/* + * Some controllers doesn't have over 0x100 register. + * it is used to checking accessibility of + * CTL_SD_CARD_CLK_CTL / CTL_CLK_AND_WAIT_CTL + */ +#define TMIO_MMC_HAVE_HIGH_REG (1 << 6) + int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base); int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base); void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state); @@ -102,6 +109,7 @@ struct tmio_mmc_data { unsigned long capabilities; unsigned long capabilities2; unsigned long flags; + unsigned long bus_shift; u32 ocr_mask; /* available voltages */ struct tmio_mmc_dma *dma; struct device *dev; diff --git a/include/linux/mfd/tps6586x.h b/include/linux/mfd/tps6586x.h index 87994542573..cbecec2e353 100644 --- a/include/linux/mfd/tps6586x.h +++ b/include/linux/mfd/tps6586x.h @@ -13,6 +13,12 @@ #define TPS6586X_SLEW_RATE_SET 0x08 #define TPS6586X_SLEW_RATE_MASK 0x07 +/* VERSION CRC */ +#define TPS658621A 0x15 +#define TPS658621CD 0x2c +#define TPS658623 0x1b +#define TPS658643 0x03 + enum { TPS6586X_ID_SYS, TPS6586X_ID_SM_0, @@ -97,5 +103,6 @@ extern int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask); extern int tps6586x_update(struct device *dev, int reg, uint8_t val, uint8_t mask); extern int tps6586x_irq_get_virq(struct device *dev, int irq); +extern int tps6586x_get_version(struct device *dev); #endif /*__LINUX_MFD_TPS6586X_H */ diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h index 20e433e551e..16c2335c285 100644 --- a/include/linux/mfd/tps65910.h +++ b/include/linux/mfd/tps65910.h @@ -358,8 +358,6 @@ /*Register BBCH (0x80) register.RegisterDescription */ #define BBCH_BBSEL_MASK 0x06 #define BBCH_BBSEL_SHIFT 1 -#define BBCH_BBCHEN_MASK 0x01 -#define BBCH_BBCHEN_SHIFT 0 /*Register DCDCCTRL (0x80) register.RegisterDescription */ @@ -833,6 +831,7 @@ #define TPS65910_REG_VAUX2 10 #define TPS65910_REG_VAUX33 11 #define TPS65910_REG_VMMC 12 +#define TPS65910_REG_VBB 13 #define TPS65911_REG_VDDCTRL 4 #define TPS65911_REG_LDO1 5 @@ -845,7 +844,7 @@ #define TPS65911_REG_LDO8 12 /* Max number of TPS65910/11 regulators */ -#define TPS65910_NUM_REGS 13 +#define TPS65910_NUM_REGS 14 /* External sleep controls through EN1/EN2/EN3/SLEEP inputs */ #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 0x1 |