summaryrefslogtreecommitdiffstats
path: root/include/linux/mfd
diff options
context:
space:
mode:
Diffstat (limited to 'include/linux/mfd')
-rw-r--r--include/linux/mfd/88pm860x.h6
-rw-r--r--include/linux/mfd/abx500.h8
-rw-r--r--include/linux/mfd/asic3.h23
-rw-r--r--include/linux/mfd/core.h23
-rw-r--r--include/linux/mfd/max8997-private.h4
-rw-r--r--include/linux/mfd/pm8xxx/core.h81
-rw-r--r--include/linux/mfd/pm8xxx/irq.h59
-rw-r--r--include/linux/mfd/pm8xxx/pm8921.h31
-rw-r--r--include/linux/mfd/tps65910.h800
-rw-r--r--include/linux/mfd/twl4030-codec.h2
-rw-r--r--include/linux/mfd/wm831x/core.h26
-rw-r--r--include/linux/mfd/wm831x/pdata.h4
12 files changed, 1013 insertions, 54 deletions
diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h
index 8fba7972ff5..63b4fb8e3b6 100644
--- a/include/linux/mfd/88pm860x.h
+++ b/include/linux/mfd/88pm860x.h
@@ -330,6 +330,11 @@ struct pm860x_led_pdata {
unsigned long flags;
};
+struct pm860x_rtc_pdata {
+ int (*sync)(unsigned int ticks);
+ int vrtc;
+};
+
struct pm860x_touch_pdata {
int gpadc_prebias;
int slot_cycle;
@@ -349,6 +354,7 @@ struct pm860x_power_pdata {
struct pm860x_platform_data {
struct pm860x_backlight_pdata *backlight;
struct pm860x_led_pdata *led;
+ struct pm860x_rtc_pdata *rtc;
struct pm860x_touch_pdata *touch;
struct pm860x_power_pdata *power;
struct regulator_init_data *regulator;
diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h
index 7d9b6ae1c20..896b5e47f16 100644
--- a/include/linux/mfd/abx500.h
+++ b/include/linux/mfd/abx500.h
@@ -34,6 +34,13 @@
#define AB5500_2_0 0x21
#define AB5500_2_1 0x22
+/* AB8500 CIDs*/
+#define AB8500_CUTEARLY 0x00
+#define AB8500_CUT1P0 0x10
+#define AB8500_CUT1P1 0x11
+#define AB8500_CUT2P0 0x20
+#define AB8500_CUT3P0 0x30
+
/*
* AB3100, EVENTA1, A2 and A3 event register flags
* these are catenated into a single 32-bit flag in the code
@@ -186,6 +193,7 @@ struct abx500_init_settings {
struct ab3550_platform_data {
struct {unsigned int base; unsigned int count; } irq;
void *dev_data[AB3550_NUM_DEVICES];
+ size_t dev_data_sz[AB3550_NUM_DEVICES];
struct abx500_init_settings *init_settings;
unsigned int init_settings_sz;
};
diff --git a/include/linux/mfd/asic3.h b/include/linux/mfd/asic3.h
index de3c4ad19af..ed793b77a1c 100644
--- a/include/linux/mfd/asic3.h
+++ b/include/linux/mfd/asic3.h
@@ -16,6 +16,13 @@
#include <linux/types.h>
+struct led_classdev;
+struct asic3_led {
+ const char *name;
+ const char *default_trigger;
+ struct led_classdev *cdev;
+};
+
struct asic3_platform_data {
u16 *gpio_config;
unsigned int gpio_config_num;
@@ -23,6 +30,8 @@ struct asic3_platform_data {
unsigned int irq_base;
unsigned int gpio_base;
+
+ struct asic3_led *leds;
};
#define ASIC3_NUM_GPIO_BANKS 4
@@ -111,9 +120,9 @@ struct asic3_platform_data {
#define ASIC3_GPIOA11_PWM0 ASIC3_CONFIG_GPIO(11, 1, 1, 0)
#define ASIC3_GPIOA12_PWM1 ASIC3_CONFIG_GPIO(12, 1, 1, 0)
#define ASIC3_GPIOA15_CONTROL_CX ASIC3_CONFIG_GPIO(15, 1, 1, 0)
-#define ASIC3_GPIOC0_LED0 ASIC3_CONFIG_GPIO(32, 1, 1, 0)
-#define ASIC3_GPIOC1_LED1 ASIC3_CONFIG_GPIO(33, 1, 1, 0)
-#define ASIC3_GPIOC2_LED2 ASIC3_CONFIG_GPIO(34, 1, 1, 0)
+#define ASIC3_GPIOC0_LED0 ASIC3_CONFIG_GPIO(32, 1, 0, 0)
+#define ASIC3_GPIOC1_LED1 ASIC3_CONFIG_GPIO(33, 1, 0, 0)
+#define ASIC3_GPIOC2_LED2 ASIC3_CONFIG_GPIO(34, 1, 0, 0)
#define ASIC3_GPIOC3_SPI_RXD ASIC3_CONFIG_GPIO(35, 1, 0, 0)
#define ASIC3_GPIOC4_CF_nCD ASIC3_CONFIG_GPIO(36, 1, 0, 0)
#define ASIC3_GPIOC4_SPI_TXD ASIC3_CONFIG_GPIO(36, 1, 1, 0)
@@ -152,6 +161,7 @@ struct asic3_platform_data {
#define PWM_TIMEBASE_VALUE(x) ((x)&0xf) /* Low 4 bits sets time base */
#define PWM_TIMEBASE_ENABLE (1 << 4) /* Enable clock */
+#define ASIC3_NUM_LEDS 3
#define ASIC3_LED_0_Base 0x0700
#define ASIC3_LED_1_Base 0x0800
#define ASIC3_LED_2_Base 0x0900
@@ -287,10 +297,17 @@ struct asic3_platform_data {
*
*****************************************************************************/
#define ASIC3_SD_CONFIG_BASE 0x0400 /* Assumes 32 bit addressing */
+#define ASIC3_SD_CONFIG_SIZE 0x0200 /* Assumes 32 bit addressing */
#define ASIC3_SD_CTRL_BASE 0x1000
#define ASIC3_SDIO_CTRL_BASE 0x1200
#define ASIC3_MAP_SIZE_32BIT 0x2000
#define ASIC3_MAP_SIZE_16BIT 0x1000
+/* Functions needed by leds-asic3 */
+
+struct asic3;
+extern void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 val);
+extern u32 asic3_read_register(struct asic3 *asic, unsigned int reg);
+
#endif /* __ASIC3_H__ */
diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h
index aef23309a74..4e76163dd86 100644
--- a/include/linux/mfd/core.h
+++ b/include/linux/mfd/core.h
@@ -33,8 +33,9 @@ struct mfd_cell {
int (*suspend)(struct platform_device *dev);
int (*resume)(struct platform_device *dev);
- /* mfd_data can be used to pass data to client drivers */
- void *mfd_data;
+ /* platform data passed to the sub devices drivers */
+ void *platform_data;
+ size_t pdata_size;
/*
* These resources can be specified relative to the parent device.
@@ -89,24 +90,6 @@ static inline const struct mfd_cell *mfd_get_cell(struct platform_device *pdev)
return pdev->mfd_cell;
}
-/*
- * Given a platform device that's been created by mfd_add_devices(), fetch
- * the .mfd_data entry from the mfd_cell that created it.
- * Otherwise just return the platform_data pointer.
- * This maintains compatibility with platform drivers whose devices aren't
- * created by the mfd layer, and expect platform_data to contain what would've
- * otherwise been in mfd_data.
- */
-static inline void *mfd_get_data(struct platform_device *pdev)
-{
- const struct mfd_cell *cell = mfd_get_cell(pdev);
-
- if (cell)
- return cell->mfd_data;
- else
- return pdev->dev.platform_data;
-}
-
extern int mfd_add_devices(struct device *parent, int id,
struct mfd_cell *cells, int n_devs,
struct resource *mem_base,
diff --git a/include/linux/mfd/max8997-private.h b/include/linux/mfd/max8997-private.h
index 69d1010e2e5..5ff2400ad46 100644
--- a/include/linux/mfd/max8997-private.h
+++ b/include/linux/mfd/max8997-private.h
@@ -311,10 +311,6 @@ enum max8997_irq {
MAX8997_IRQ_NR,
};
-#define MAX8997_REG_BUCK1DVS(x) (MAX8997_REG_BUCK1DVS1 + (x) - 1)
-#define MAX8997_REG_BUCK2DVS(x) (MAX8997_REG_BUCK2DVS1 + (x) - 1)
-#define MAX8997_REG_BUCK5DVS(x) (MAX8997_REG_BUCK5DVS1 + (x) - 1)
-
#define MAX8997_NUM_GPIO 12
struct max8997_dev {
struct device *dev;
diff --git a/include/linux/mfd/pm8xxx/core.h b/include/linux/mfd/pm8xxx/core.h
new file mode 100644
index 00000000000..bd2f4f64e93
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/core.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PMIC 8xxx driver header file
+ *
+ */
+
+#ifndef __MFD_PM8XXX_CORE_H
+#define __MFD_PM8XXX_CORE_H
+
+#include <linux/mfd/core.h>
+
+struct pm8xxx_drvdata {
+ int (*pmic_readb) (const struct device *dev, u16 addr, u8 *val);
+ int (*pmic_writeb) (const struct device *dev, u16 addr, u8 val);
+ int (*pmic_read_buf) (const struct device *dev, u16 addr, u8 *buf,
+ int n);
+ int (*pmic_write_buf) (const struct device *dev, u16 addr, u8 *buf,
+ int n);
+ int (*pmic_read_irq_stat) (const struct device *dev, int irq);
+ void *pm_chip_data;
+};
+
+static inline int pm8xxx_readb(const struct device *dev, u16 addr, u8 *val)
+{
+ struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+ if (!dd)
+ return -EINVAL;
+ return dd->pmic_readb(dev, addr, val);
+}
+
+static inline int pm8xxx_writeb(const struct device *dev, u16 addr, u8 val)
+{
+ struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+ if (!dd)
+ return -EINVAL;
+ return dd->pmic_writeb(dev, addr, val);
+}
+
+static inline int pm8xxx_read_buf(const struct device *dev, u16 addr, u8 *buf,
+ int n)
+{
+ struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+ if (!dd)
+ return -EINVAL;
+ return dd->pmic_read_buf(dev, addr, buf, n);
+}
+
+static inline int pm8xxx_write_buf(const struct device *dev, u16 addr, u8 *buf,
+ int n)
+{
+ struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+ if (!dd)
+ return -EINVAL;
+ return dd->pmic_write_buf(dev, addr, buf, n);
+}
+
+static inline int pm8xxx_read_irq_stat(const struct device *dev, int irq)
+{
+ struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+ if (!dd)
+ return -EINVAL;
+ return dd->pmic_read_irq_stat(dev, irq);
+}
+
+#endif
diff --git a/include/linux/mfd/pm8xxx/irq.h b/include/linux/mfd/pm8xxx/irq.h
new file mode 100644
index 00000000000..4b21769f448
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/irq.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PMIC irq 8xxx driver header file
+ *
+ */
+
+#ifndef __MFD_PM8XXX_IRQ_H
+#define __MFD_PM8XXX_IRQ_H
+
+#include <linux/errno.h>
+#include <linux/err.h>
+
+struct pm8xxx_irq_core_data {
+ u32 rev;
+ int nirqs;
+};
+
+struct pm8xxx_irq_platform_data {
+ int irq_base;
+ struct pm8xxx_irq_core_data irq_cdata;
+ int devirq;
+ int irq_trigger_flag;
+};
+
+struct pm_irq_chip;
+
+#ifdef CONFIG_MFD_PM8XXX_IRQ
+int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq);
+struct pm_irq_chip * __devinit pm8xxx_irq_init(struct device *dev,
+ const struct pm8xxx_irq_platform_data *pdata);
+int __devexit pm8xxx_irq_exit(struct pm_irq_chip *chip);
+#else
+static inline int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq)
+{
+ return -ENXIO;
+}
+static inline struct pm_irq_chip * __devinit pm8xxx_irq_init(
+ const struct device *dev,
+ const struct pm8xxx_irq_platform_data *pdata)
+{
+ return ERR_PTR(-ENXIO);
+}
+static inline int __devexit pm8xxx_irq_exit(struct pm_irq_chip *chip)
+{
+ return -ENXIO;
+}
+#endif /* CONFIG_MFD_PM8XXX_IRQ */
+#endif /* __MFD_PM8XXX_IRQ_H */
diff --git a/include/linux/mfd/pm8xxx/pm8921.h b/include/linux/mfd/pm8xxx/pm8921.h
new file mode 100644
index 00000000000..d5517fd32d1
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/pm8921.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PMIC 8921 driver header file
+ *
+ */
+
+#ifndef __MFD_PM8921_H
+#define __MFD_PM8921_H
+
+#include <linux/device.h>
+#include <linux/mfd/pm8xxx/irq.h>
+
+#define PM8921_NR_IRQS 256
+
+struct pm8921_platform_data {
+ int irq_base;
+ struct pm8xxx_irq_platform_data *irq_pdata;
+};
+
+#endif
diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h
new file mode 100644
index 00000000000..8bb85b930c0
--- /dev/null
+++ b/include/linux/mfd/tps65910.h
@@ -0,0 +1,800 @@
+/*
+ * tps65910.h -- TI TPS6591x
+ *
+ * Copyright 2010-2011 Texas Instruments Inc.
+ *
+ * Author: Graeme Gregory <gg@slimlogic.co.uk>
+ * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
+ * Author: Arnaud Deconinck <a-deconinck@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __LINUX_MFD_TPS65910_H
+#define __LINUX_MFD_TPS65910_H
+
+/* TPS chip id list */
+#define TPS65910 0
+#define TPS65911 1
+
+/* TPS regulator type list */
+#define REGULATOR_LDO 0
+#define REGULATOR_DCDC 1
+
+/*
+ * List of registers for component TPS65910
+ *
+ */
+
+#define TPS65910_SECONDS 0x0
+#define TPS65910_MINUTES 0x1
+#define TPS65910_HOURS 0x2
+#define TPS65910_DAYS 0x3
+#define TPS65910_MONTHS 0x4
+#define TPS65910_YEARS 0x5
+#define TPS65910_WEEKS 0x6
+#define TPS65910_ALARM_SECONDS 0x8
+#define TPS65910_ALARM_MINUTES 0x9
+#define TPS65910_ALARM_HOURS 0xA
+#define TPS65910_ALARM_DAYS 0xB
+#define TPS65910_ALARM_MONTHS 0xC
+#define TPS65910_ALARM_YEARS 0xD
+#define TPS65910_RTC_CTRL 0x10
+#define TPS65910_RTC_STATUS 0x11
+#define TPS65910_RTC_INTERRUPTS 0x12
+#define TPS65910_RTC_COMP_LSB 0x13
+#define TPS65910_RTC_COMP_MSB 0x14
+#define TPS65910_RTC_RES_PROG 0x15
+#define TPS65910_RTC_RESET_STATUS 0x16
+#define TPS65910_BCK1 0x17
+#define TPS65910_BCK2 0x18
+#define TPS65910_BCK3 0x19
+#define TPS65910_BCK4 0x1A
+#define TPS65910_BCK5 0x1B
+#define TPS65910_PUADEN 0x1C
+#define TPS65910_REF 0x1D
+#define TPS65910_VRTC 0x1E
+#define TPS65910_VIO 0x20
+#define TPS65910_VDD1 0x21
+#define TPS65910_VDD1_OP 0x22
+#define TPS65910_VDD1_SR 0x23
+#define TPS65910_VDD2 0x24
+#define TPS65910_VDD2_OP 0x25
+#define TPS65910_VDD2_SR 0x26
+#define TPS65910_VDD3 0x27
+#define TPS65910_VDIG1 0x30
+#define TPS65910_VDIG2 0x31
+#define TPS65910_VAUX1 0x32
+#define TPS65910_VAUX2 0x33
+#define TPS65910_VAUX33 0x34
+#define TPS65910_VMMC 0x35
+#define TPS65910_VPLL 0x36
+#define TPS65910_VDAC 0x37
+#define TPS65910_THERM 0x38
+#define TPS65910_BBCH 0x39
+#define TPS65910_DCDCCTRL 0x3E
+#define TPS65910_DEVCTRL 0x3F
+#define TPS65910_DEVCTRL2 0x40
+#define TPS65910_SLEEP_KEEP_LDO_ON 0x41
+#define TPS65910_SLEEP_KEEP_RES_ON 0x42
+#define TPS65910_SLEEP_SET_LDO_OFF 0x43
+#define TPS65910_SLEEP_SET_RES_OFF 0x44
+#define TPS65910_EN1_LDO_ASS 0x45
+#define TPS65910_EN1_SMPS_ASS 0x46
+#define TPS65910_EN2_LDO_ASS 0x47
+#define TPS65910_EN2_SMPS_ASS 0x48
+#define TPS65910_EN3_LDO_ASS 0x49
+#define TPS65910_SPARE 0x4A
+#define TPS65910_INT_STS 0x50
+#define TPS65910_INT_MSK 0x51
+#define TPS65910_INT_STS2 0x52
+#define TPS65910_INT_MSK2 0x53
+#define TPS65910_INT_STS3 0x54
+#define TPS65910_INT_MSK3 0x55
+#define TPS65910_GPIO0 0x60
+#define TPS65910_GPIO1 0x61
+#define TPS65910_GPIO2 0x62
+#define TPS65910_GPIO3 0x63
+#define TPS65910_GPIO4 0x64
+#define TPS65910_GPIO5 0x65
+#define TPS65910_GPIO6 0x66
+#define TPS65910_GPIO7 0x67
+#define TPS65910_GPIO8 0x68
+#define TPS65910_JTAGVERNUM 0x80
+#define TPS65910_MAX_REGISTER 0x80
+
+/*
+ * List of registers specific to TPS65911
+ */
+#define TPS65911_VDDCTRL 0x27
+#define TPS65911_VDDCTRL_OP 0x28
+#define TPS65911_VDDCTRL_SR 0x29
+#define TPS65911_LDO1 0x30
+#define TPS65911_LDO2 0x31
+#define TPS65911_LDO5 0x32
+#define TPS65911_LDO8 0x33
+#define TPS65911_LDO7 0x34
+#define TPS65911_LDO6 0x35
+#define TPS65911_LDO4 0x36
+#define TPS65911_LDO3 0x37
+#define TPS65911_VMBCH 0x6A
+#define TPS65911_VMBCH2 0x6B
+
+/*
+ * List of register bitfields for component TPS65910
+ *
+ */
+
+
+/*Register BCK1 (0x80) register.RegisterDescription */
+#define BCK1_BCKUP_MASK 0xFF
+#define BCK1_BCKUP_SHIFT 0
+
+
+/*Register BCK2 (0x80) register.RegisterDescription */
+#define BCK2_BCKUP_MASK 0xFF
+#define BCK2_BCKUP_SHIFT 0
+
+
+/*Register BCK3 (0x80) register.RegisterDescription */
+#define BCK3_BCKUP_MASK 0xFF
+#define BCK3_BCKUP_SHIFT 0
+
+
+/*Register BCK4 (0x80) register.RegisterDescription */
+#define BCK4_BCKUP_MASK 0xFF
+#define BCK4_BCKUP_SHIFT 0
+
+
+/*Register BCK5 (0x80) register.RegisterDescription */
+#define BCK5_BCKUP_MASK 0xFF
+#define BCK5_BCKUP_SHIFT 0
+
+
+/*Register PUADEN (0x80) register.RegisterDescription */
+#define PUADEN_EN3P_MASK 0x80
+#define PUADEN_EN3P_SHIFT 7
+#define PUADEN_I2CCTLP_MASK 0x40
+#define PUADEN_I2CCTLP_SHIFT 6
+#define PUADEN_I2CSRP_MASK 0x20
+#define PUADEN_I2CSRP_SHIFT 5
+#define PUADEN_PWRONP_MASK 0x10
+#define PUADEN_PWRONP_SHIFT 4
+#define PUADEN_SLEEPP_MASK 0x08
+#define PUADEN_SLEEPP_SHIFT 3
+#define PUADEN_PWRHOLDP_MASK 0x04
+#define PUADEN_PWRHOLDP_SHIFT 2
+#define PUADEN_BOOT1P_MASK 0x02
+#define PUADEN_BOOT1P_SHIFT 1
+#define PUADEN_BOOT0P_MASK 0x01
+#define PUADEN_BOOT0P_SHIFT 0
+
+
+/*Register REF (0x80) register.RegisterDescription */
+#define REF_VMBCH_SEL_MASK 0x0C
+#define REF_VMBCH_SEL_SHIFT 2
+#define REF_ST_MASK 0x03
+#define REF_ST_SHIFT 0
+
+
+/*Register VRTC (0x80) register.RegisterDescription */
+#define VRTC_VRTC_OFFMASK_MASK 0x08
+#define VRTC_VRTC_OFFMASK_SHIFT 3
+#define VRTC_ST_MASK 0x03
+#define VRTC_ST_SHIFT 0
+
+
+/*Register VIO (0x80) register.RegisterDescription */
+#define VIO_ILMAX_MASK 0xC0
+#define VIO_ILMAX_SHIFT 6
+#define VIO_SEL_MASK 0x0C
+#define VIO_SEL_SHIFT 2
+#define VIO_ST_MASK 0x03
+#define VIO_ST_SHIFT 0
+
+
+/*Register VDD1 (0x80) register.RegisterDescription */
+#define VDD1_VGAIN_SEL_MASK 0xC0
+#define VDD1_VGAIN_SEL_SHIFT 6
+#define VDD1_ILMAX_MASK 0x20
+#define VDD1_ILMAX_SHIFT 5
+#define VDD1_TSTEP_MASK 0x1C
+#define VDD1_TSTEP_SHIFT 2
+#define VDD1_ST_MASK 0x03
+#define VDD1_ST_SHIFT 0
+
+
+/*Register VDD1_OP (0x80) register.RegisterDescription */
+#define VDD1_OP_CMD_MASK 0x80
+#define VDD1_OP_CMD_SHIFT 7
+#define VDD1_OP_SEL_MASK 0x7F
+#define VDD1_OP_SEL_SHIFT 0
+
+
+/*Register VDD1_SR (0x80) register.RegisterDescription */
+#define VDD1_SR_SEL_MASK 0x7F
+#define VDD1_SR_SEL_SHIFT 0
+
+
+/*Register VDD2 (0x80) register.RegisterDescription */
+#define VDD2_VGAIN_SEL_MASK 0xC0
+#define VDD2_VGAIN_SEL_SHIFT 6
+#define VDD2_ILMAX_MASK 0x20
+#define VDD2_ILMAX_SHIFT 5
+#define VDD2_TSTEP_MASK 0x1C
+#define VDD2_TSTEP_SHIFT 2
+#define VDD2_ST_MASK 0x03
+#define VDD2_ST_SHIFT 0
+
+
+/*Register VDD2_OP (0x80) register.RegisterDescription */
+#define VDD2_OP_CMD_MASK 0x80
+#define VDD2_OP_CMD_SHIFT 7
+#define VDD2_OP_SEL_MASK 0x7F
+#define VDD2_OP_SEL_SHIFT 0
+
+/*Register VDD2_SR (0x80) register.RegisterDescription */
+#define VDD2_SR_SEL_MASK 0x7F
+#define VDD2_SR_SEL_SHIFT 0
+
+
+/*Registers VDD1, VDD2 voltage values definitions */
+#define VDD1_2_NUM_VOLTS 73
+#define VDD1_2_MIN_VOLT 6000
+#define VDD1_2_OFFSET 125
+
+
+/*Register VDD3 (0x80) register.RegisterDescription */
+#define VDD3_CKINEN_MASK 0x04
+#define VDD3_CKINEN_SHIFT 2
+#define VDD3_ST_MASK 0x03
+#define VDD3_ST_SHIFT 0
+#define VDDCTRL_MIN_VOLT 6000
+#define VDDCTRL_OFFSET 125
+
+/*Registers VDIG (0x80) to VDAC register.RegisterDescription */
+#define LDO_SEL_MASK 0x0C
+#define LDO_SEL_SHIFT 2
+#define LDO_ST_MASK 0x03
+#define LDO_ST_SHIFT 0
+#define LDO_ST_ON_BIT 0x01
+#define LDO_ST_MODE_BIT 0x02
+
+
+/* Registers LDO1 to LDO8 in tps65910 */
+#define LDO1_SEL_MASK 0xFC
+#define LDO3_SEL_MASK 0x7C
+#define LDO_MIN_VOLT 1000
+#define LDO_MAX_VOLT 3300;
+
+
+/*Register VDIG1 (0x80) register.RegisterDescription */
+#define VDIG1_SEL_MASK 0x0C
+#define VDIG1_SEL_SHIFT 2
+#define VDIG1_ST_MASK 0x03
+#define VDIG1_ST_SHIFT 0
+
+
+/*Register VDIG2 (0x80) register.RegisterDescription */
+#define VDIG2_SEL_MASK 0x0C
+#define VDIG2_SEL_SHIFT 2
+#define VDIG2_ST_MASK 0x03
+#define VDIG2_ST_SHIFT 0
+
+
+/*Register VAUX1 (0x80) register.RegisterDescription */
+#define VAUX1_SEL_MASK 0x0C
+#define VAUX1_SEL_SHIFT 2
+#define VAUX1_ST_MASK 0x03
+#define VAUX1_ST_SHIFT 0
+
+
+/*Register VAUX2 (0x80) register.RegisterDescription */
+#define VAUX2_SEL_MASK 0x0C
+#define VAUX2_SEL_SHIFT 2
+#define VAUX2_ST_MASK 0x03
+#define VAUX2_ST_SHIFT 0
+
+
+/*Register VAUX33 (0x80) register.RegisterDescription */
+#define VAUX33_SEL_MASK 0x0C
+#define VAUX33_SEL_SHIFT 2
+#define VAUX33_ST_MASK 0x03
+#define VAUX33_ST_SHIFT 0
+
+
+/*Register VMMC (0x80) register.RegisterDescription */
+#define VMMC_SEL_MASK 0x0C
+#define VMMC_SEL_SHIFT 2
+#define VMMC_ST_MASK 0x03
+#define VMMC_ST_SHIFT 0
+
+
+/*Register VPLL (0x80) register.RegisterDescription */
+#define VPLL_SEL_MASK 0x0C
+#define VPLL_SEL_SHIFT 2
+#define VPLL_ST_MASK 0x03
+#define VPLL_ST_SHIFT 0
+
+
+/*Register VDAC (0x80) register.RegisterDescription */
+#define VDAC_SEL_MASK 0x0C
+#define VDAC_SEL_SHIFT 2
+#define VDAC_ST_MASK 0x03
+#define VDAC_ST_SHIFT 0
+
+
+/*Register THERM (0x80) register.RegisterDescription */
+#define THERM_THERM_HD_MASK 0x20
+#define THERM_THERM_HD_SHIFT 5
+#define THERM_THERM_TS_MASK 0x10
+#define THERM_THERM_TS_SHIFT 4
+#define THERM_THERM_HDSEL_MASK 0x0C
+#define THERM_THERM_HDSEL_SHIFT 2
+#define THERM_RSVD1_MASK 0x02
+#define THERM_RSVD1_SHIFT 1
+#define THERM_THERM_STATE_MASK 0x01
+#define THERM_THERM_STATE_SHIFT 0
+
+
+/*Register BBCH (0x80) register.RegisterDescription */
+#define BBCH_BBSEL_MASK 0x06
+#define BBCH_BBSEL_SHIFT 1
+#define BBCH_BBCHEN_MASK 0x01
+#define BBCH_BBCHEN_SHIFT 0
+
+
+/*Register DCDCCTRL (0x80) register.RegisterDescription */
+#define DCDCCTRL_VDD2_PSKIP_MASK 0x20
+#define DCDCCTRL_VDD2_PSKIP_SHIFT 5
+#define DCDCCTRL_VDD1_PSKIP_MASK 0x10
+#define DCDCCTRL_VDD1_PSKIP_SHIFT 4
+#define DCDCCTRL_VIO_PSKIP_MASK 0x08
+#define DCDCCTRL_VIO_PSKIP_SHIFT 3
+#define DCDCCTRL_DCDCCKEXT_MASK 0x04
+#define DCDCCTRL_DCDCCKEXT_SHIFT 2
+#define DCDCCTRL_DCDCCKSYNC_MASK 0x03
+#define DCDCCTRL_DCDCCKSYNC_SHIFT 0
+
+
+/*Register DEVCTRL (0x80) register.RegisterDescription */
+#define DEVCTRL_RTC_PWDN_MASK 0x40
+#define DEVCTRL_RTC_PWDN_SHIFT 6
+#define DEVCTRL_CK32K_CTRL_MASK 0x20
+#define DEVCTRL_CK32K_CTRL_SHIFT 5
+#define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10
+#define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4
+#define DEVCTRL_DEV_OFF_RST_MASK 0x08
+#define DEVCTRL_DEV_OFF_RST_SHIFT 3
+#define DEVCTRL_DEV_ON_MASK 0x04
+#define DEVCTRL_DEV_ON_SHIFT 2
+#define DEVCTRL_DEV_SLP_MASK 0x02
+#define DEVCTRL_DEV_SLP_SHIFT 1
+#define DEVCTRL_DEV_OFF_MASK 0x01
+#define DEVCTRL_DEV_OFF_SHIFT 0
+
+
+/*Register DEVCTRL2 (0x80) register.RegisterDescription */
+#define DEVCTRL2_TSLOT_LENGTH_MASK 0x30
+#define DEVCTRL2_TSLOT_LENGTH_SHIFT 4
+#define DEVCTRL2_SLEEPSIG_POL_MASK 0x08
+#define DEVCTRL2_SLEEPSIG_POL_SHIFT 3
+#define DEVCTRL2_PWON_LP_OFF_MASK 0x04
+#define DEVCTRL2_PWON_LP_OFF_SHIFT 2
+#define DEVCTRL2_PWON_LP_RST_MASK 0x02
+#define DEVCTRL2_PWON_LP_RST_SHIFT 1
+#define DEVCTRL2_IT_POL_MASK 0x01
+#define DEVCTRL2_IT_POL_SHIFT 0
+
+
+/*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */
+#define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80
+#define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7
+#define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40
+#define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6
+#define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20
+#define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5
+#define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10
+#define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4
+#define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08
+#define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3
+#define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04
+#define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2
+#define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02
+#define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1
+#define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01
+#define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0
+
+
+/*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */
+#define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80
+#define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7
+#define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40
+#define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6
+#define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20
+#define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5
+#define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10
+#define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4
+#define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08
+#define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3
+#define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04
+#define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2
+#define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02
+#define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1
+#define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01
+#define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0
+
+
+/*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */
+#define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80
+#define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7
+#define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40
+#define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6
+#define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20
+#define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5
+#define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10
+#define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4
+#define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08
+#define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3
+#define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04
+#define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2
+#define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02
+#define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1
+#define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01
+#define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0
+
+
+/*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */
+#define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80
+#define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7
+#define SLEEP_SET_RES_OFF_RSVD_MASK 0x60
+#define SLEEP_SET_RES_OFF_RSVD_SHIFT 5
+#define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10
+#define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4
+#define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08
+#define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3
+#define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04
+#define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2
+#define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02
+#define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1
+#define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01
+#define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0
+
+
+/*Register EN1_LDO_ASS (0x80) register.RegisterDescription */
+#define EN1_LDO_ASS_VDAC_EN1_MASK 0x80
+#define EN1_LDO_ASS_VDAC_EN1_SHIFT 7
+#define EN1_LDO_ASS_VPLL_EN1_MASK 0x40
+#define EN1_LDO_ASS_VPLL_EN1_SHIFT 6
+#define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20
+#define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5
+#define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10
+#define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4
+#define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08
+#define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3
+#define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04
+#define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2
+#define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02
+#define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1
+#define EN1_LDO_ASS_VMMC_EN1_MASK 0x01
+#define EN1_LDO_ASS_VMMC_EN1_SHIFT 0
+
+
+/*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */
+#define EN1_SMPS_ASS_RSVD_MASK 0xE0
+#define EN1_SMPS_ASS_RSVD_SHIFT 5
+#define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10
+#define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4
+#define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08
+#define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3
+#define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04
+#define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2
+#define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02
+#define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1
+#define EN1_SMPS_ASS_VIO_EN1_MASK 0x01
+#define EN1_SMPS_ASS_VIO_EN1_SHIFT 0
+
+
+/*Register EN2_LDO_ASS (0x80) register.RegisterDescription */
+#define EN2_LDO_ASS_VDAC_EN2_MASK 0x80
+#define EN2_LDO_ASS_VDAC_EN2_SHIFT 7
+#define EN2_LDO_ASS_VPLL_EN2_MASK 0x40
+#define EN2_LDO_ASS_VPLL_EN2_SHIFT 6
+#define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20
+#define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5
+#define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10
+#define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4
+#define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08
+#define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3
+#define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04
+#define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2
+#define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02
+#define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1
+#define EN2_LDO_ASS_VMMC_EN2_MASK 0x01
+#define EN2_LDO_ASS_VMMC_EN2_SHIFT 0
+
+
+/*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */
+#define EN2_SMPS_ASS_RSVD_MASK 0xE0
+#define EN2_SMPS_ASS_RSVD_SHIFT 5
+#define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10
+#define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4
+#define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08
+#define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3
+#define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04
+#define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2
+#define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02
+#define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1
+#define EN2_SMPS_ASS_VIO_EN2_MASK 0x01
+#define EN2_SMPS_ASS_VIO_EN2_SHIFT 0
+
+
+/*Register EN3_LDO_ASS (0x80) register.RegisterDescription */
+#define EN3_LDO_ASS_VDAC_EN3_MASK 0x80
+#define EN3_LDO_ASS_VDAC_EN3_SHIFT 7
+#define EN3_LDO_ASS_VPLL_EN3_MASK 0x40
+#define EN3_LDO_ASS_VPLL_EN3_SHIFT 6
+#define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20
+#define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5
+#define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10
+#define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4
+#define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08
+#define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3
+#define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04
+#define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2
+#define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02
+#define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1
+#define EN3_LDO_ASS_VMMC_EN3_MASK 0x01
+#define EN3_LDO_ASS_VMMC_EN3_SHIFT 0
+
+
+/*Register SPARE (0x80) register.RegisterDescription */
+#define SPARE_SPARE_MASK 0xFF
+#define SPARE_SPARE_SHIFT 0
+
+
+/*Register INT_STS (0x80) register.RegisterDescription */
+#define INT_STS_RTC_PERIOD_IT_MASK 0x80
+#define INT_STS_RTC_PERIOD_IT_SHIFT 7
+#define INT_STS_RTC_ALARM_IT_MASK 0x40
+#define INT_STS_RTC_ALARM_IT_SHIFT 6
+#define INT_STS_HOTDIE_IT_MASK 0x20
+#define INT_STS_HOTDIE_IT_SHIFT 5
+#define INT_STS_PWRHOLD_IT_MASK 0x10
+#define INT_STS_PWRHOLD_IT_SHIFT 4
+#define INT_STS_PWRON_LP_IT_MASK 0x08
+#define INT_STS_PWRON_LP_IT_SHIFT 3
+#define INT_STS_PWRON_IT_MASK 0x04
+#define INT_STS_PWRON_IT_SHIFT 2
+#define INT_STS_VMBHI_IT_MASK 0x02
+#define INT_STS_VMBHI_IT_SHIFT 1
+#define INT_STS_VMBDCH_IT_MASK 0x01
+#define INT_STS_VMBDCH_IT_SHIFT 0
+
+
+/*Register INT_MSK (0x80) register.RegisterDescription */
+#define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80
+#define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7
+#define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40
+#define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6
+#define INT_MSK_HOTDIE_IT_MSK_MASK 0x20
+#define INT_MSK_HOTDIE_IT_MSK_SHIFT 5
+#define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10
+#define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4
+#define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08
+#define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3
+#define INT_MSK_PWRON_IT_MSK_MASK 0x04
+#define INT_MSK_PWRON_IT_MSK_SHIFT 2
+#define INT_MSK_VMBHI_IT_MSK_MASK 0x02
+#define INT_MSK_VMBHI_IT_MSK_SHIFT 1
+#define INT_MSK_VMBDCH_IT_MSK_MASK 0x01
+#define INT_MSK_VMBDCH_IT_MSK_SHIFT 0
+
+
+/*Register INT_STS2 (0x80) register.RegisterDescription */
+#define INT_STS2_GPIO3_F_IT_MASK 0x80
+#define INT_STS2_GPIO3_F_IT_SHIFT 7
+#define INT_STS2_GPIO3_R_IT_MASK 0x40
+#define INT_STS2_GPIO3_R_IT_SHIFT 6
+#define INT_STS2_GPIO2_F_IT_MASK 0x20
+#define INT_STS2_GPIO2_F_IT_SHIFT 5
+#define INT_STS2_GPIO2_R_IT_MASK 0x10
+#define INT_STS2_GPIO2_R_IT_SHIFT 4
+#define INT_STS2_GPIO1_F_IT_MASK 0x08
+#define INT_STS2_GPIO1_F_IT_SHIFT 3
+#define INT_STS2_GPIO1_R_IT_MASK 0x04
+#define INT_STS2_GPIO1_R_IT_SHIFT 2
+#define INT_STS2_GPIO0_F_IT_MASK 0x02
+#define INT_STS2_GPIO0_F_IT_SHIFT 1
+#define INT_STS2_GPIO0_R_IT_MASK 0x01
+#define INT_STS2_GPIO0_R_IT_SHIFT 0
+
+
+/*Register INT_MSK2 (0x80) register.RegisterDescription */
+#define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80
+#define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7
+#define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40
+#define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6
+#define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20
+#define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5
+#define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10
+#define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4
+#define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08
+#define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3
+#define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04
+#define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2
+#define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02
+#define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1
+#define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01
+#define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0
+
+
+/*Register INT_STS3 (0x80) register.RegisterDescription */
+#define INT_STS3_GPIO5_F_IT_MASK 0x08
+#define INT_STS3_GPIO5_F_IT_SHIFT 3
+#define INT_STS3_GPIO5_R_IT_MASK 0x04
+#define INT_STS3_GPIO5_R_IT_SHIFT 2
+#define INT_STS3_GPIO4_F_IT_MASK 0x02
+#define INT_STS3_GPIO4_F_IT_SHIFT 1
+#define INT_STS3_GPIO4_R_IT_MASK 0x01
+#define INT_STS3_GPIO4_R_IT_SHIFT 0
+
+
+/*Register INT_MSK3 (0x80) register.RegisterDescription */
+#define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08
+#define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3
+#define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04
+#define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2
+#define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02
+#define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1
+#define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01
+#define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0
+
+
+/*Register GPIO (0x80) register.RegisterDescription */
+#define GPIO_DEB_MASK 0x10
+#define GPIO_DEB_SHIFT 4
+#define GPIO_PUEN_MASK 0x08
+#define GPIO_PUEN_SHIFT 3
+#define GPIO_CFG_MASK 0x04
+#define GPIO_CFG_SHIFT 2
+#define GPIO_STS_MASK 0x02
+#define GPIO_STS_SHIFT 1
+#define GPIO_SET_MASK 0x01
+#define GPIO_SET_SHIFT 0
+
+
+/*Register JTAGVERNUM (0x80) register.RegisterDescription */
+#define JTAGVERNUM_VERNUM_MASK 0x0F
+#define JTAGVERNUM_VERNUM_SHIFT 0
+
+
+/* Register VDDCTRL (0x27) bit definitions */
+#define VDDCTRL_ST_MASK 0x03
+#define VDDCTRL_ST_SHIFT 0
+
+
+/*Register VDDCTRL_OP (0x28) bit definitios */
+#define VDDCTRL_OP_CMD_MASK 0x80
+#define VDDCTRL_OP_CMD_SHIFT 7
+#define VDDCTRL_OP_SEL_MASK 0x7F
+#define VDDCTRL_OP_SEL_SHIFT 0
+
+
+/*Register VDDCTRL_SR (0x29) bit definitions */
+#define VDDCTRL_SR_SEL_MASK 0x7F
+#define VDDCTRL_SR_SEL_SHIFT 0
+
+
+/* IRQ Definitions */
+#define TPS65910_IRQ_VBAT_VMBDCH 0
+#define TPS65910_IRQ_VBAT_VMHI 1
+#define TPS65910_IRQ_PWRON 2
+#define TPS65910_IRQ_PWRON_LP 3
+#define TPS65910_IRQ_PWRHOLD 4
+#define TPS65910_IRQ_HOTDIE 5
+#define TPS65910_IRQ_RTC_ALARM 6
+#define TPS65910_IRQ_RTC_PERIOD 7
+#define TPS65910_IRQ_GPIO_R 8
+#define TPS65910_IRQ_GPIO_F 9
+#define TPS65910_NUM_IRQ 10
+
+#define TPS65911_IRQ_VBAT_VMBDCH 0
+#define TPS65911_IRQ_VBAT_VMBDCH2L 1
+#define TPS65911_IRQ_VBAT_VMBDCH2H 2
+#define TPS65911_IRQ_VBAT_VMHI 3
+#define TPS65911_IRQ_PWRON 4
+#define TPS65911_IRQ_PWRON_LP 5
+#define TPS65911_IRQ_PWRHOLD_F 6
+#define TPS65911_IRQ_PWRHOLD_R 7
+#define TPS65911_IRQ_HOTDIE 8
+#define TPS65911_IRQ_RTC_ALARM 9
+#define TPS65911_IRQ_RTC_PERIOD 10
+#define TPS65911_IRQ_GPIO0_R 11
+#define TPS65911_IRQ_GPIO0_F 12
+#define TPS65911_IRQ_GPIO1_R 13
+#define TPS65911_IRQ_GPIO1_F 14
+#define TPS65911_IRQ_GPIO2_R 15
+#define TPS65911_IRQ_GPIO2_F 16
+#define TPS65911_IRQ_GPIO3_R 17
+#define TPS65911_IRQ_GPIO3_F 18
+#define TPS65911_IRQ_GPIO4_R 19
+#define TPS65911_IRQ_GPIO4_F 20
+#define TPS65911_IRQ_GPIO5_R 21
+#define TPS65911_IRQ_GPIO5_F 22
+#define TPS65911_IRQ_WTCHDG 23
+#define TPS65911_IRQ_PWRDN 24
+
+#define TPS65911_NUM_IRQ 25
+
+
+/* GPIO Register Definitions */
+#define TPS65910_GPIO_DEB BIT(2)
+#define TPS65910_GPIO_PUEN BIT(3)
+#define TPS65910_GPIO_CFG BIT(2)
+#define TPS65910_GPIO_STS BIT(1)
+#define TPS65910_GPIO_SET BIT(0)
+
+/**
+ * struct tps65910_board
+ * Board platform data may be used to initialize regulators.
+ */
+
+struct tps65910_board {
+ int gpio_base;
+ int irq;
+ int irq_base;
+ int vmbch_threshold;
+ int vmbch2_threshold;
+ struct regulator_init_data *tps65910_pmic_init_data;
+};
+
+/**
+ * struct tps65910 - tps65910 sub-driver chip access routines
+ */
+
+struct tps65910 {
+ struct device *dev;
+ struct i2c_client *i2c_client;
+ struct mutex io_mutex;
+ unsigned int id;
+ int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest);
+ int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src);
+
+ /* Client devices */
+ struct tps65910_pmic *pmic;
+ struct tps65910_rtc *rtc;
+ struct tps65910_power *power;
+
+ /* GPIO Handling */
+ struct gpio_chip gpio;
+
+ /* IRQ Handling */
+ struct mutex irq_lock;
+ int chip_irq;
+ int irq_base;
+ int irq_num;
+ u32 irq_mask;
+};
+
+struct tps65910_platform_data {
+ int irq;
+ int irq_base;
+};
+
+int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
+int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
+void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base);
+int tps65910_irq_init(struct tps65910 *tps65910, int irq,
+ struct tps65910_platform_data *pdata);
+
+static inline int tps65910_chip_id(struct tps65910 *tps65910)
+{
+ return tps65910->id;
+}
+
+#endif /* __LINUX_MFD_TPS65910_H */
diff --git a/include/linux/mfd/twl4030-codec.h b/include/linux/mfd/twl4030-codec.h
index 2ec317c68e5..5cc16bbd1da 100644
--- a/include/linux/mfd/twl4030-codec.h
+++ b/include/linux/mfd/twl4030-codec.h
@@ -1,7 +1,7 @@
/*
* MFD driver for twl4030 codec submodule
*
- * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
+ * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*
* Copyright: (C) 2009 Nokia Corporation
*
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
index 903280d2186..0d515ee1c24 100644
--- a/include/linux/mfd/wm831x/core.h
+++ b/include/linux/mfd/wm831x/core.h
@@ -301,30 +301,4 @@ int wm831x_device_suspend(struct wm831x *wm831x);
int wm831x_irq_init(struct wm831x *wm831x, int irq);
void wm831x_irq_exit(struct wm831x *wm831x);
-static inline int __must_check wm831x_request_irq(struct wm831x *wm831x,
- unsigned int irq,
- irq_handler_t handler,
- unsigned long flags,
- const char *name,
- void *dev)
-{
- return request_threaded_irq(irq, NULL, handler, flags, name, dev);
-}
-
-static inline void wm831x_free_irq(struct wm831x *wm831x,
- unsigned int irq, void *dev)
-{
- free_irq(irq, dev);
-}
-
-static inline void wm831x_disable_irq(struct wm831x *wm831x, int irq)
-{
- disable_irq(irq);
-}
-
-static inline void wm831x_enable_irq(struct wm831x *wm831x, int irq)
-{
- enable_irq(irq);
-}
-
#endif
diff --git a/include/linux/mfd/wm831x/pdata.h b/include/linux/mfd/wm831x/pdata.h
index 632d1567a1b..ff42d700293 100644
--- a/include/linux/mfd/wm831x/pdata.h
+++ b/include/linux/mfd/wm831x/pdata.h
@@ -105,6 +105,9 @@ struct wm831x_watchdog_pdata {
#define WM831X_MAX_LDO 11
#define WM831X_MAX_ISINK 2
+#define WM831X_GPIO_CONFIGURE 0x10000
+#define WM831X_GPIO_NUM 16
+
struct wm831x_pdata {
/** Used to distinguish multiple WM831x chips */
int wm831x_num;
@@ -119,6 +122,7 @@ struct wm831x_pdata {
int irq_base;
int gpio_base;
+ int gpio_defaults[WM831X_GPIO_NUM];
struct wm831x_backlight_pdata *backlight;
struct wm831x_backup_pdata *backup;
struct wm831x_battery_pdata *battery;
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-03-12 01:25:39 +0000