diff options
Diffstat (limited to 'include/linux/spi')
| -rw-r--r-- | include/linux/spi/Kbuild | 1 | ||||
| -rw-r--r-- | include/linux/spi/mxs-spi.h | 150 | ||||
| -rw-r--r-- | include/linux/spi/spidev.h | 131 | ||||
| -rw-r--r-- | include/linux/spi/tsc2005.h | 2 |
4 files changed, 150 insertions, 134 deletions
diff --git a/include/linux/spi/Kbuild b/include/linux/spi/Kbuild deleted file mode 100644 index d375a082986..00000000000 --- a/include/linux/spi/Kbuild +++ /dev/null @@ -1 +0,0 @@ -header-y += spidev.h diff --git a/include/linux/spi/mxs-spi.h b/include/linux/spi/mxs-spi.h new file mode 100644 index 00000000000..61ae1306db2 --- /dev/null +++ b/include/linux/spi/mxs-spi.h @@ -0,0 +1,150 @@ +/* + * include/linux/spi/mxs-spi.h + * + * Freescale i.MX233/i.MX28 SPI controller register definition + * + * Copyright 2008 Embedded Alley Solutions, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __LINUX_SPI_MXS_SPI_H__ +#define __LINUX_SPI_MXS_SPI_H__ + +#include <linux/fsl/mxs-dma.h> + +#define ssp_is_old(host) ((host)->devid == IMX23_SSP) + +/* SSP registers */ +#define HW_SSP_CTRL0 0x000 +#define BM_SSP_CTRL0_RUN (1 << 29) +#define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) +#define BM_SSP_CTRL0_LOCK_CS (1 << 27) +#define BM_SSP_CTRL0_IGNORE_CRC (1 << 26) +#define BM_SSP_CTRL0_READ (1 << 25) +#define BM_SSP_CTRL0_DATA_XFER (1 << 24) +#define BP_SSP_CTRL0_BUS_WIDTH 22 +#define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22) +#define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) +#define BM_SSP_CTRL0_WAIT_FOR_CMD (1 << 20) +#define BM_SSP_CTRL0_LONG_RESP (1 << 19) +#define BM_SSP_CTRL0_GET_RESP (1 << 17) +#define BM_SSP_CTRL0_ENABLE (1 << 16) +#define BP_SSP_CTRL0_XFER_COUNT 0 +#define BM_SSP_CTRL0_XFER_COUNT 0xffff +#define HW_SSP_CMD0 0x010 +#define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) +#define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22) +#define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21) +#define BM_SSP_CMD0_APPEND_8CYC (1 << 20) +#define BP_SSP_CMD0_BLOCK_SIZE 16 +#define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16) +#define BP_SSP_CMD0_BLOCK_COUNT 8 +#define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8) +#define BP_SSP_CMD0_CMD 0 +#define BM_SSP_CMD0_CMD 0xff +#define HW_SSP_CMD1 0x020 +#define HW_SSP_XFER_SIZE 0x030 +#define HW_SSP_BLOCK_SIZE 0x040 +#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT 4 +#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4) +#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE 0 +#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE 0xf +#define HW_SSP_TIMING(h) (ssp_is_old(h) ? 0x050 : 0x070) +#define BP_SSP_TIMING_TIMEOUT 16 +#define BM_SSP_TIMING_TIMEOUT (0xffff << 16) +#define BP_SSP_TIMING_CLOCK_DIVIDE 8 +#define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8) +#define BF_SSP_TIMING_CLOCK_DIVIDE(v) \ + (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE) +#define BP_SSP_TIMING_CLOCK_RATE 0 +#define BM_SSP_TIMING_CLOCK_RATE 0xff +#define BF_SSP_TIMING_CLOCK_RATE(v) \ + (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE) +#define HW_SSP_CTRL1(h) (ssp_is_old(h) ? 0x060 : 0x080) +#define BM_SSP_CTRL1_SDIO_IRQ (1 << 31) +#define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30) +#define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29) +#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) +#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) +#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) +#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) +#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) +#define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23) +#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) +#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) +#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20) +#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) +#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) +#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) +#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) +#define BM_SSP_CTRL1_DMA_ENABLE (1 << 13) +#define BM_SSP_CTRL1_PHASE (1 << 10) +#define BM_SSP_CTRL1_POLARITY (1 << 9) +#define BP_SSP_CTRL1_WORD_LENGTH 4 +#define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4) +#define BF_SSP_CTRL1_WORD_LENGTH(v) \ + (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH) +#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3 +#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7 +#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xF +#define BP_SSP_CTRL1_SSP_MODE 0 +#define BM_SSP_CTRL1_SSP_MODE 0xf +#define BF_SSP_CTRL1_SSP_MODE(v) \ + (((v) << 0) & BM_SSP_CTRL1_SSP_MODE) +#define BV_SSP_CTRL1_SSP_MODE__SPI 0x0 +#define BV_SSP_CTRL1_SSP_MODE__SSI 0x1 +#define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3 +#define BV_SSP_CTRL1_SSP_MODE__MS 0x4 + +#define HW_SSP_DATA(h) (ssp_is_old(h) ? 0x070 : 0x090) + +#define HW_SSP_SDRESP0(h) (ssp_is_old(h) ? 0x080 : 0x0a0) +#define HW_SSP_SDRESP1(h) (ssp_is_old(h) ? 0x090 : 0x0b0) +#define HW_SSP_SDRESP2(h) (ssp_is_old(h) ? 0x0a0 : 0x0c0) +#define HW_SSP_SDRESP3(h) (ssp_is_old(h) ? 0x0b0 : 0x0d0) +#define HW_SSP_STATUS(h) (ssp_is_old(h) ? 0x0c0 : 0x100) +#define BM_SSP_STATUS_CARD_DETECT (1 << 28) +#define BM_SSP_STATUS_SDIO_IRQ (1 << 17) +#define BM_SSP_STATUS_FIFO_EMPTY (1 << 5) + +#define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field) + +#define SSP_PIO_NUM 3 + +enum mxs_ssp_id { + IMX23_SSP, + IMX28_SSP, +}; + +struct mxs_ssp { + struct device *dev; + void __iomem *base; + struct clk *clk; + unsigned int clk_rate; + enum mxs_ssp_id devid; + + int dma_channel; + struct dma_chan *dmach; + struct mxs_dma_data dma_data; + unsigned int dma_dir; + enum dma_transfer_direction slave_dirn; + u32 ssp_pio_words[SSP_PIO_NUM]; +}; + +void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate); + +#endif /* __LINUX_SPI_MXS_SPI_H__ */ diff --git a/include/linux/spi/spidev.h b/include/linux/spi/spidev.h deleted file mode 100644 index 52d9ed01855..00000000000 --- a/include/linux/spi/spidev.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * include/linux/spi/spidev.h - * - * Copyright (C) 2006 SWAPP - * Andrea Paterniani <a.paterniani@swapp-eng.it> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef SPIDEV_H -#define SPIDEV_H - -#include <linux/types.h> - -/* User space versions of kernel symbols for SPI clocking modes, - * matching <linux/spi/spi.h> - */ - -#define SPI_CPHA 0x01 -#define SPI_CPOL 0x02 - -#define SPI_MODE_0 (0|0) -#define SPI_MODE_1 (0|SPI_CPHA) -#define SPI_MODE_2 (SPI_CPOL|0) -#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) - -#define SPI_CS_HIGH 0x04 -#define SPI_LSB_FIRST 0x08 -#define SPI_3WIRE 0x10 -#define SPI_LOOP 0x20 -#define SPI_NO_CS 0x40 -#define SPI_READY 0x80 - -/*---------------------------------------------------------------------------*/ - -/* IOCTL commands */ - -#define SPI_IOC_MAGIC 'k' - -/** - * struct spi_ioc_transfer - describes a single SPI transfer - * @tx_buf: Holds pointer to userspace buffer with transmit data, or null. - * If no data is provided, zeroes are shifted out. - * @rx_buf: Holds pointer to userspace buffer for receive data, or null. - * @len: Length of tx and rx buffers, in bytes. - * @speed_hz: Temporary override of the device's bitrate. - * @bits_per_word: Temporary override of the device's wordsize. - * @delay_usecs: If nonzero, how long to delay after the last bit transfer - * before optionally deselecting the device before the next transfer. - * @cs_change: True to deselect device before starting the next transfer. - * - * This structure is mapped directly to the kernel spi_transfer structure; - * the fields have the same meanings, except of course that the pointers - * are in a different address space (and may be of different sizes in some - * cases, such as 32-bit i386 userspace over a 64-bit x86_64 kernel). - * Zero-initialize the structure, including currently unused fields, to - * accommodate potential future updates. - * - * SPI_IOC_MESSAGE gives userspace the equivalent of kernel spi_sync(). - * Pass it an array of related transfers, they'll execute together. - * Each transfer may be half duplex (either direction) or full duplex. - * - * struct spi_ioc_transfer mesg[4]; - * ... - * status = ioctl(fd, SPI_IOC_MESSAGE(4), mesg); - * - * So for example one transfer might send a nine bit command (right aligned - * in a 16-bit word), the next could read a block of 8-bit data before - * terminating that command by temporarily deselecting the chip; the next - * could send a different nine bit command (re-selecting the chip), and the - * last transfer might write some register values. - */ -struct spi_ioc_transfer { - __u64 tx_buf; - __u64 rx_buf; - - __u32 len; - __u32 speed_hz; - - __u16 delay_usecs; - __u8 bits_per_word; - __u8 cs_change; - __u32 pad; - - /* If the contents of 'struct spi_ioc_transfer' ever change - * incompatibly, then the ioctl number (currently 0) must change; - * ioctls with constant size fields get a bit more in the way of - * error checking than ones (like this) where that field varies. - * - * NOTE: struct layout is the same in 64bit and 32bit userspace. - */ -}; - -/* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */ -#define SPI_MSGSIZE(N) \ - ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \ - ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0) -#define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)]) - - -/* Read / Write of SPI mode (SPI_MODE_0..SPI_MODE_3) */ -#define SPI_IOC_RD_MODE _IOR(SPI_IOC_MAGIC, 1, __u8) -#define SPI_IOC_WR_MODE _IOW(SPI_IOC_MAGIC, 1, __u8) - -/* Read / Write SPI bit justification */ -#define SPI_IOC_RD_LSB_FIRST _IOR(SPI_IOC_MAGIC, 2, __u8) -#define SPI_IOC_WR_LSB_FIRST _IOW(SPI_IOC_MAGIC, 2, __u8) - -/* Read / Write SPI device word length (1..N) */ -#define SPI_IOC_RD_BITS_PER_WORD _IOR(SPI_IOC_MAGIC, 3, __u8) -#define SPI_IOC_WR_BITS_PER_WORD _IOW(SPI_IOC_MAGIC, 3, __u8) - -/* Read / Write SPI device default max speed hz */ -#define SPI_IOC_RD_MAX_SPEED_HZ _IOR(SPI_IOC_MAGIC, 4, __u32) -#define SPI_IOC_WR_MAX_SPEED_HZ _IOW(SPI_IOC_MAGIC, 4, __u32) - - - -#endif /* SPIDEV_H */ diff --git a/include/linux/spi/tsc2005.h b/include/linux/spi/tsc2005.h index d9b0c84220c..8f721e465e0 100644 --- a/include/linux/spi/tsc2005.h +++ b/include/linux/spi/tsc2005.h @@ -3,8 +3,6 @@ * * Copyright (C) 2009-2010 Nokia Corporation * - * Contact: Aaro Koskinen <aaro.koskinen@nokia.com> - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or |