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-rw-r--r--include/linux/ata_platform.h3
-rw-r--r--include/linux/mbus.h36
-rw-r--r--include/linux/sched.h6
3 files changed, 45 insertions, 0 deletions
diff --git a/include/linux/ata_platform.h b/include/linux/ata_platform.h
index b856a2a590d..9a26c83a2c9 100644
--- a/include/linux/ata_platform.h
+++ b/include/linux/ata_platform.h
@@ -27,7 +27,10 @@ extern int __devexit __pata_platform_remove(struct device *dev);
/*
* Marvell SATA private data
*/
+struct mbus_dram_target_info;
+
struct mv_sata_platform_data {
+ struct mbus_dram_target_info *dram;
int n_ports; /* number of sata ports */
};
diff --git a/include/linux/mbus.h b/include/linux/mbus.h
new file mode 100644
index 00000000000..c11ff293254
--- /dev/null
+++ b/include/linux/mbus.h
@@ -0,0 +1,36 @@
+/*
+ * Marvell MBUS common definitions.
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __LINUX_MBUS_H
+#define __LINUX_MBUS_H
+
+struct mbus_dram_target_info
+{
+ /*
+ * The 4-bit MBUS target ID of the DRAM controller.
+ */
+ u8 mbus_dram_target_id;
+
+ /*
+ * The base address, size, and MBUS attribute ID for each
+ * of the possible DRAM chip selects. Peripherals are
+ * required to support at least 4 decode windows.
+ */
+ int num_cs;
+ struct mbus_dram_window {
+ u8 cs_index;
+ u8 mbus_attr;
+ u32 base;
+ u32 size;
+ } cs[4];
+};
+
+
+#endif
diff --git a/include/linux/sched.h b/include/linux/sched.h
index fed07d03364..6a1e7afb099 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -1541,6 +1541,12 @@ static inline void idle_task_exit(void) {}
extern void sched_idle_next(void);
+#if defined(CONFIG_NO_HZ) && defined(CONFIG_SMP)
+extern void wake_up_idle_cpu(int cpu);
+#else
+static inline void wake_up_idle_cpu(int cpu) { }
+#endif
+
#ifdef CONFIG_SCHED_DEBUG
extern unsigned int sysctl_sched_latency;
extern unsigned int sysctl_sched_min_granularity;