diff options
Diffstat (limited to 'include/linux')
61 files changed, 2622 insertions, 324 deletions
diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 3f968665899..f53fea61f40 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -151,6 +151,7 @@ extern int ec_write(u8 addr, u8 val); extern int ec_transaction(u8 command, const u8 *wdata, unsigned wdata_len, u8 *rdata, unsigned rdata_len); +extern acpi_handle ec_get_handle(void); #if defined(CONFIG_ACPI_WMI) || defined(CONFIG_ACPI_WMI_MODULE) diff --git a/include/linux/apple_bl.h b/include/linux/apple_bl.h new file mode 100644 index 00000000000..47bedc0eee6 --- /dev/null +++ b/include/linux/apple_bl.h @@ -0,0 +1,26 @@ +/* + * apple_bl exported symbols + */ + +#ifndef _LINUX_APPLE_BL_H +#define _LINUX_APPLE_BL_H + +#ifdef CONFIG_BACKLIGHT_APPLE + +extern int apple_bl_register(void); +extern void apple_bl_unregister(void); + +#else /* !CONFIG_BACKLIGHT_APPLE */ + +static inline int apple_bl_register(void) +{ + return 0; +} + +static inline void apple_bl_unregister(void) +{ +} + +#endif /* !CONFIG_BACKLIGHT_APPLE */ + +#endif /* _LINUX_APPLE_BL_H */ diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h new file mode 100644 index 00000000000..5e4312b6f5c --- /dev/null +++ b/include/linux/clk-private.h @@ -0,0 +1,196 @@ +/* + * linux/include/linux/clk-private.h + * + * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> + * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __LINUX_CLK_PRIVATE_H +#define __LINUX_CLK_PRIVATE_H + +#include <linux/clk-provider.h> +#include <linux/list.h> + +/* + * WARNING: Do not include clk-private.h from any file that implements struct + * clk_ops. Doing so is a layering violation! + * + * This header exists only to allow for statically initialized clock data. Any + * static clock data must be defined in a separate file from the logic that + * implements the clock operations for that same data. + */ + +#ifdef CONFIG_COMMON_CLK + +struct clk { + const char *name; + const struct clk_ops *ops; + struct clk_hw *hw; + struct clk *parent; + char **parent_names; + struct clk **parents; + u8 num_parents; + unsigned long rate; + unsigned long new_rate; + unsigned long flags; + unsigned int enable_count; + unsigned int prepare_count; + struct hlist_head children; + struct hlist_node child_node; + unsigned int notifier_count; +#ifdef CONFIG_COMMON_CLK_DEBUG + struct dentry *dentry; +#endif +}; + +/* + * DOC: Basic clock implementations common to many platforms + * + * Each basic clock hardware type is comprised of a structure describing the + * clock hardware, implementations of the relevant callbacks in struct clk_ops, + * unique flags for that hardware type, a registration function and an + * alternative macro for static initialization + */ + +extern struct clk_ops clk_fixed_rate_ops; + +#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, \ + _fixed_rate_flags) \ + static struct clk _name; \ + static char *_name##_parent_names[] = {}; \ + static struct clk_fixed_rate _name##_hw = { \ + .hw = { \ + .clk = &_name, \ + }, \ + .fixed_rate = _rate, \ + .flags = _fixed_rate_flags, \ + }; \ + static struct clk _name = { \ + .name = #_name, \ + .ops = &clk_fixed_rate_ops, \ + .hw = &_name##_hw.hw, \ + .parent_names = _name##_parent_names, \ + .num_parents = \ + ARRAY_SIZE(_name##_parent_names), \ + .flags = _flags, \ + }; + +extern struct clk_ops clk_gate_ops; + +#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, \ + _flags, _reg, _bit_idx, \ + _gate_flags, _lock) \ + static struct clk _name; \ + static char *_name##_parent_names[] = { \ + _parent_name, \ + }; \ + static struct clk *_name##_parents[] = { \ + _parent_ptr, \ + }; \ + static struct clk_gate _name##_hw = { \ + .hw = { \ + .clk = &_name, \ + }, \ + .reg = _reg, \ + .bit_idx = _bit_idx, \ + .flags = _gate_flags, \ + .lock = _lock, \ + }; \ + static struct clk _name = { \ + .name = #_name, \ + .ops = &clk_gate_ops, \ + .hw = &_name##_hw.hw, \ + .parent_names = _name##_parent_names, \ + .num_parents = \ + ARRAY_SIZE(_name##_parent_names), \ + .parents = _name##_parents, \ + .flags = _flags, \ + }; + +extern struct clk_ops clk_divider_ops; + +#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \ + _flags, _reg, _shift, _width, \ + _divider_flags, _lock) \ + static struct clk _name; \ + static char *_name##_parent_names[] = { \ + _parent_name, \ + }; \ + static struct clk *_name##_parents[] = { \ + _parent_ptr, \ + }; \ + static struct clk_divider _name##_hw = { \ + .hw = { \ + .clk = &_name, \ + }, \ + .reg = _reg, \ + .shift = _shift, \ + .width = _width, \ + .flags = _divider_flags, \ + .lock = _lock, \ + }; \ + static struct clk _name = { \ + .name = #_name, \ + .ops = &clk_divider_ops, \ + .hw = &_name##_hw.hw, \ + .parent_names = _name##_parent_names, \ + .num_parents = \ + ARRAY_SIZE(_name##_parent_names), \ + .parents = _name##_parents, \ + .flags = _flags, \ + }; + +extern struct clk_ops clk_mux_ops; + +#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \ + _reg, _shift, _width, \ + _mux_flags, _lock) \ + static struct clk _name; \ + static struct clk_mux _name##_hw = { \ + .hw = { \ + .clk = &_name, \ + }, \ + .reg = _reg, \ + .shift = _shift, \ + .width = _width, \ + .flags = _mux_flags, \ + .lock = _lock, \ + }; \ + static struct clk _name = { \ + .name = #_name, \ + .ops = &clk_mux_ops, \ + .hw = &_name##_hw.hw, \ + .parent_names = _parent_names, \ + .num_parents = \ + ARRAY_SIZE(_parent_names), \ + .parents = _parents, \ + .flags = _flags, \ + }; + +/** + * __clk_init - initialize the data structures in a struct clk + * @dev: device initializing this clk, placeholder for now + * @clk: clk being initialized + * + * Initializes the lists in struct clk, queries the hardware for the + * parent and rate and sets them both. + * + * Any struct clk passed into __clk_init must have the following members + * populated: + * .name + * .ops + * .hw + * .parent_names + * .num_parents + * .flags + * + * It is not necessary to call clk_register if __clk_init is used directly with + * statically initialized clock data. + */ +void __clk_init(struct device *dev, struct clk *clk); + +#endif /* CONFIG_COMMON_CLK */ +#endif /* CLK_PRIVATE_H */ diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h new file mode 100644 index 00000000000..5508897ad37 --- /dev/null +++ b/include/linux/clk-provider.h @@ -0,0 +1,300 @@ +/* + * linux/include/linux/clk-provider.h + * + * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> + * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __LINUX_CLK_PROVIDER_H +#define __LINUX_CLK_PROVIDER_H + +#include <linux/clk.h> + +#ifdef CONFIG_COMMON_CLK + +/** + * struct clk_hw - handle for traversing from a struct clk to its corresponding + * hardware-specific structure. struct clk_hw should be declared within struct + * clk_foo and then referenced by the struct clk instance that uses struct + * clk_foo's clk_ops + * + * clk: pointer to the struct clk instance that points back to this struct + * clk_hw instance + */ +struct clk_hw { + struct clk *clk; +}; + +/* + * flags used across common struct clk. these flags should only affect the + * top-level framework. custom flags for dealing with hardware specifics + * belong in struct clk_foo + */ +#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ +#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ +#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ +#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ +#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ + +/** + * struct clk_ops - Callback operations for hardware clocks; these are to + * be provided by the clock implementation, and will be called by drivers + * through the clk_* api. + * + * @prepare: Prepare the clock for enabling. This must not return until + * the clock is fully prepared, and it's safe to call clk_enable. + * This callback is intended to allow clock implementations to + * do any initialisation that may sleep. Called with + * prepare_lock held. + * + * @unprepare: Release the clock from its prepared state. This will typically + * undo any work done in the @prepare callback. Called with + * prepare_lock held. + * + * @enable: Enable the clock atomically. This must not return until the + * clock is generating a valid clock signal, usable by consumer + * devices. Called with enable_lock held. This function must not + * sleep. + * + * @disable: Disable the clock atomically. Called with enable_lock held. + * This function must not sleep. + * + * @recalc_rate Recalculate the rate of this clock, by quering hardware. The + * parent rate is an input parameter. It is up to the caller to + * insure that the prepare_mutex is held across this call. + * Returns the calculated rate. Optional, but recommended - if + * this op is not set then clock rate will be initialized to 0. + * + * @round_rate: Given a target rate as input, returns the closest rate actually + * supported by the clock. + * + * @get_parent: Queries the hardware to determine the parent of a clock. The + * return value is a u8 which specifies the index corresponding to + * the parent clock. This index can be applied to either the + * .parent_names or .parents arrays. In short, this function + * translates the parent value read from hardware into an array + * index. Currently only called when the clock is initialized by + * __clk_init. This callback is mandatory for clocks with + * multiple parents. It is optional (and unnecessary) for clocks + * with 0 or 1 parents. + * + * @set_parent: Change the input source of this clock; for clocks with multiple + * possible parents specify a new parent by passing in the index + * as a u8 corresponding to the parent in either the .parent_names + * or .parents arrays. This function in affect translates an + * array index into the value programmed into the hardware. + * Returns 0 on success, -EERROR otherwise. + * + * @set_rate: Change the rate of this clock. If this callback returns + * CLK_SET_RATE_PARENT, the rate change will be propagated to the + * parent clock (which may propagate again if the parent clock + * also sets this flag). The requested rate of the parent is + * passed back from the callback in the second 'unsigned long *' + * argument. Note that it is up to the hardware clock's set_rate + * implementation to insure that clocks do not run out of spec + * when propgating the call to set_rate up to the parent. One way + * to do this is to gate the clock (via clk_disable and/or + * clk_unprepare) before calling clk_set_rate, then ungating it + * afterward. If your clock also has the CLK_GATE_SET_RATE flag + * set then this will insure safety. Returns 0 on success, + * -EERROR otherwise. + * + * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow + * implementations to split any work between atomic (enable) and sleepable + * (prepare) contexts. If enabling a clock requires code that might sleep, + * this must be done in clk_prepare. Clock enable code that will never be + * called in a sleepable context may be implement in clk_enable. + * + * Typically, drivers will call clk_prepare when a clock may be needed later + * (eg. when a device is opened), and clk_enable when the clock is actually + * required (eg. from an interrupt). Note that clk_prepare MUST have been + * called before clk_enable. + */ +struct clk_ops { + int (*prepare)(struct clk_hw *hw); + void (*unprepare)(struct clk_hw *hw); + int (*enable)(struct clk_hw *hw); + void (*disable)(struct clk_hw *hw); + int (*is_enabled)(struct clk_hw *hw); + unsigned long (*recalc_rate)(struct clk_hw *hw, + unsigned long parent_rate); + long (*round_rate)(struct clk_hw *hw, unsigned long, + unsigned long *); + int (*set_parent)(struct clk_hw *hw, u8 index); + u8 (*get_parent)(struct clk_hw *hw); + int (*set_rate)(struct clk_hw *hw, unsigned long); + void (*init)(struct clk_hw *hw); +}; + +/* + * DOC: Basic clock implementations common to many platforms + * + * Each basic clock hardware type is comprised of a structure describing the + * clock hardware, implementations of the relevant callbacks in struct clk_ops, + * unique flags for that hardware type, a registration function and an + * alternative macro for static initialization + */ + +/** + * struct clk_fixed_rate - fixed-rate clock + * @hw: handle between common and hardware-specific interfaces + * @fixed_rate: constant frequency of clock + */ +struct clk_fixed_rate { + struct clk_hw hw; + unsigned long fixed_rate; + u8 flags; +}; + +struct clk *clk_register_fixed_rate(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + unsigned long fixed_rate); + +/** + * struct clk_gate - gating clock + * + * @hw: handle between common and hardware-specific interfaces + * @reg: register controlling gate + * @bit_idx: single bit controlling gate + * @flags: hardware-specific flags + * @lock: register lock + * + * Clock which can gate its output. Implements .enable & .disable + * + * Flags: + * CLK_GATE_SET_DISABLE - by default this clock sets the bit at bit_idx to + * enable the clock. Setting this flag does the opposite: setting the bit + * disable the clock and clearing it enables the clock + */ +struct clk_gate { + struct clk_hw hw; + void __iomem *reg; + u8 bit_idx; + u8 flags; + spinlock_t *lock; + char *parent[1]; +}; + +#define CLK_GATE_SET_TO_DISABLE BIT(0) + +struct clk *clk_register_gate(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock); + +/** + * struct clk_divider - adjustable divider clock + * + * @hw: handle between common and hardware-specific interfaces + * @reg: register containing the divider + * @shift: shift to the divider bit field + * @width: width of the divider bit field + * @lock: register lock + * + * Clock with an adjustable divider affecting its output frequency. Implements + * .recalc_rate, .set_rate and .round_rate + * + * Flags: + * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the + * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is + * the raw value read from the register, with the value of zero considered + * invalid + * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from + * the hardware register + */ +struct clk_divider { + struct clk_hw hw; + void __iomem *reg; + u8 shift; + u8 width; + u8 flags; + spinlock_t *lock; + char *parent[1]; +}; + +#define CLK_DIVIDER_ONE_BASED BIT(0) +#define CLK_DIVIDER_POWER_OF_TWO BIT(1) + +struct clk *clk_register_divider(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags, spinlock_t *lock); + +/** + * struct clk_mux - multiplexer clock + * + * @hw: handle between common and hardware-specific interfaces + * @reg: register controlling multiplexer + * @shift: shift to multiplexer bit field + * @width: width of mutliplexer bit field + * @num_clks: number of parent clocks + * @lock: register lock + * + * Clock with multiple selectable parents. Implements .get_parent, .set_parent + * and .recalc_rate + * + * Flags: + * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 + * CLK_MUX_INDEX_BITWISE - register index is a single bit (power of two) + */ +struct clk_mux { + struct clk_hw hw; + void __iomem *reg; + u8 shift; + u8 width; + u8 flags; + spinlock_t *lock; +}; + +#define CLK_MUX_INDEX_ONE BIT(0) +#define CLK_MUX_INDEX_BIT BIT(1) + +struct clk *clk_register_mux(struct device *dev, const char *name, + char **parent_names, u8 num_parents, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_mux_flags, spinlock_t *lock); + +/** + * clk_register - allocate a new clock, register it and return an opaque cookie + * @dev: device that is registering this clock + * @name: clock name + * @ops: operations this clock supports + * @hw: link to hardware-specific clock data + * @parent_names: array of string names for all possible parents + * @num_parents: number of possible parents + * @flags: framework-level hints and quirks + * + * clk_register is the primary interface for populating the clock tree with new + * clock nodes. It returns a pointer to the newly allocated struct clk which + * cannot be dereferenced by driver code but may be used in conjuction with the + * rest of the clock API. + */ +struct clk *clk_register(struct device *dev, const char *name, + const struct clk_ops *ops, struct clk_hw *hw, + char **parent_names, u8 num_parents, unsigned long flags); + +/* helper functions */ +const char *__clk_get_name(struct clk *clk); +struct clk_hw *__clk_get_hw(struct clk *clk); +u8 __clk_get_num_parents(struct clk *clk); +struct clk *__clk_get_parent(struct clk *clk); +inline int __clk_get_enable_count(struct clk *clk); +inline int __clk_get_prepare_count(struct clk *clk); +unsigned long __clk_get_rate(struct clk *clk); +unsigned long __clk_get_flags(struct clk *clk); +int __clk_is_enabled(struct clk *clk); +struct clk *__clk_lookup(const char *name); + +/* + * FIXME clock api without lock protection + */ +int __clk_prepare(struct clk *clk); +void __clk_unprepare(struct clk *clk); +void __clk_reparent(struct clk *clk, struct clk *new_parent); +unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); + +#endif /* CONFIG_COMMON_CLK */ +#endif /* CLK_PROVIDER_H */ diff --git a/include/linux/clk.h b/include/linux/clk.h index b9d46fa154b..b0252726df6 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -3,6 +3,7 @@ * * Copyright (C) 2004 ARM Limited. * Written by Deep Blue Solutions Limited. + * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -12,18 +13,75 @@ #define __LINUX_CLK_H #include <linux/kernel.h> +#include <linux/notifier.h> struct device; -/* - * The base API. +struct clk; + +#ifdef CONFIG_COMMON_CLK + +/** + * DOC: clk notifier callback types + * + * PRE_RATE_CHANGE - called immediately before the clk rate is changed, + * to indicate that the rate change will proceed. Drivers must + * immediately terminate any operations that will be affected by the + * rate change. Callbacks may either return NOTIFY_DONE or + * NOTIFY_STOP. + * + * ABORT_RATE_CHANGE: called if the rate change failed for some reason + * after PRE_RATE_CHANGE. In this case, all registered notifiers on + * the clk will be called with ABORT_RATE_CHANGE. Callbacks must + * always return NOTIFY_DONE. + * + * POST_RATE_CHANGE - called after the clk rate change has successfully + * completed. Callbacks must always return NOTIFY_DONE. + * */ +#define PRE_RATE_CHANGE BIT(0) +#define POST_RATE_CHANGE BIT(1) +#define ABORT_RATE_CHANGE BIT(2) +/** + * struct clk_notifier - associate a clk with a notifier + * @clk: struct clk * to associate the notifier with + * @notifier_head: a blocking_notifier_head for this clk + * @node: linked list pointers + * + * A list of struct clk_notifier is maintained by the notifier code. + * An entry is created whenever code registers the first notifier on a + * particular @clk. Future notifiers on that @clk are added to the + * @notifier_head. + */ +struct clk_notifier { + struct clk *clk; + struct srcu_notifier_head notifier_head; + struct list_head node; +}; -/* - * struct clk - an machine class defined object / cookie. +/** + * struct clk_notifier_data - rate data to pass to the notifier callback + * @clk: struct clk * being changed + * @old_rate: previous rate of this clk + * @new_rate: new rate of this clk + * + * For a pre-notifier, old_rate is the clk's rate before this rate + * change, and new_rate is what the rate will be in the future. For a + * post-notifier, old_rate and new_rate are both set to the clk's + * current rate (this was done to optimize the implementation). */ -struct clk; +struct clk_notifier_data { + struct clk *clk; + unsigned long old_rate; + unsigned long new_rate; +}; + +int clk_notifier_register(struct clk *clk, struct notifier_block *nb); + +int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb); + +#endif /* !CONFIG_COMMON_CLK */ /** * clk_get - lookup and obtain a reference to a clock producer. diff --git a/include/linux/cnt32_to_63.h b/include/linux/cnt32_to_63.h index e3d8bf26e5e..aa629bce903 100644 --- a/include/linux/cnt32_to_63.h +++ b/include/linux/cnt32_to_63.h @@ -16,7 +16,6 @@ #include <linux/compiler.h> #include <linux/types.h> #include <asm/byteorder.h> -#include <asm/system.h> /* this is used only to give gcc a clue about good code generation */ union cnt32_to_63 { diff --git a/include/linux/debug_locks.h b/include/linux/debug_locks.h index 94f20c1488a..3bd46f76675 100644 --- a/include/linux/debug_locks.h +++ b/include/linux/debug_locks.h @@ -4,7 +4,6 @@ #include <linux/kernel.h> #include <linux/atomic.h> #include <linux/bug.h> -#include <asm/system.h> struct task_struct; diff --git a/include/linux/dma-buf.h b/include/linux/dma-buf.h index 887dcd48706..3efbfc2145c 100644 --- a/include/linux/dma-buf.h +++ b/include/linux/dma-buf.h @@ -29,6 +29,7 @@ #include <linux/scatterlist.h> #include <linux/list.h> #include <linux/dma-mapping.h> +#include <linux/fs.h> struct device; struct dma_buf; @@ -49,6 +50,17 @@ struct dma_buf_attachment; * @unmap_dma_buf: decreases usecount of buffer, might deallocate scatter * pages. * @release: release this buffer; to be called after the last dma_buf_put. + * @begin_cpu_access: [optional] called before cpu access to invalidate cpu + * caches and allocate backing storage (if not yet done) + * respectively pin the objet into memory. + * @end_cpu_access: [optional] called after cpu access to flush cashes. + * @kmap_atomic: maps a page from the buffer into kernel address + * space, users may not block until the subsequent unmap call. + * This callback must not sleep. + * @kunmap_atomic: [optional] unmaps a atomically mapped page from the buffer. + * This Callback must not sleep. + * @kmap: maps a page from the buffer into kernel address space. + * @kunmap: [optional] unmaps a page from the buffer. */ struct dma_buf_ops { int (*attach)(struct dma_buf *, struct device *, @@ -63,7 +75,8 @@ struct dma_buf_ops { struct sg_table * (*map_dma_buf)(struct dma_buf_attachment *, enum dma_data_direction); void (*unmap_dma_buf)(struct dma_buf_attachment *, - struct sg_table *); + struct sg_table *, + enum dma_data_direction); /* TODO: Add try_map_dma_buf version, to return immed with -EBUSY * if the call would block. */ @@ -71,6 +84,14 @@ struct dma_buf_ops { /* after final dma_buf_put() */ void (*release)(struct dma_buf *); + int (*begin_cpu_access)(struct dma_buf *, size_t, size_t, + enum dma_data_direction); + void (*end_cpu_access)(struct dma_buf *, size_t, size_t, + enum dma_data_direction); + void *(*kmap_atomic)(struct dma_buf *, unsigned long); + void (*kunmap_atomic)(struct dma_buf *, unsigned long, void *); + void *(*kmap)(struct dma_buf *, unsigned long); + void (*kunmap)(struct dma_buf *, unsigned long, void *); }; /** @@ -86,7 +107,7 @@ struct dma_buf { struct file *file; struct list_head attachments; const struct dma_buf_ops *ops; - /* mutex to serialize list manipulation and other ops */ + /* mutex to serialize list manipulation and attach/detach */ struct mutex lock; void *priv; }; @@ -109,20 +130,43 @@ struct dma_buf_attachment { void *priv; }; +/** + * get_dma_buf - convenience wrapper for get_file. + * @dmabuf: [in] pointer to dma_buf + * + * Increments the reference count on the dma-buf, needed in case of drivers + * that either need to create additional references to the dmabuf on the + * kernel side. For example, an exporter that needs to keep a dmabuf ptr + * so that subsequent exports don't create a new dmabuf. + */ +static inline void get_dma_buf(struct dma_buf *dmabuf) +{ + get_file(dmabuf->file); +} + #ifdef CONFIG_DMA_SHARED_BUFFER struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf, struct device *dev); void dma_buf_detach(struct dma_buf *dmabuf, struct dma_buf_attachment *dmabuf_attach); -struct dma_buf *dma_buf_export(void *priv, struct dma_buf_ops *ops, - size_t size, int flags); -int dma_buf_fd(struct dma_buf *dmabuf); +struct dma_buf *dma_buf_export(void *priv, const struct dma_buf_ops *ops, + size_t size, int flags); +int dma_buf_fd(struct dma_buf *dmabuf, int flags); struct dma_buf *dma_buf_get(int fd); void dma_buf_put(struct dma_buf *dmabuf); struct sg_table *dma_buf_map_attachment(struct dma_buf_attachment *, enum dma_data_direction); -void dma_buf_unmap_attachment(struct dma_buf_attachment *, struct sg_table *); +void dma_buf_unmap_attachment(struct dma_buf_attachment *, struct sg_table *, + enum dma_data_direction); +int dma_buf_begin_cpu_access(struct dma_buf *dma_buf, size_t start, size_t len, + enum dma_data_direction dir); +void dma_buf_end_cpu_access(struct dma_buf *dma_buf, size_t start, size_t len, + enum dma_data_direction dir); +void *dma_buf_kmap_atomic(struct dma_buf *, unsigned long); +void dma_buf_kunmap_atomic(struct dma_buf *, unsigned long, void *); +void *dma_buf_kmap(struct dma_buf *, unsigned long); +void dma_buf_kunmap(struct dma_buf *, unsigned long, void *); #else static inline struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf, @@ -138,13 +182,13 @@ static inline void dma_buf_detach(struct dma_buf *dmabuf, } static inline struct dma_buf *dma_buf_export(void *priv, - struct dma_buf_ops *ops, - size_t size, int flags) + const struct dma_buf_ops *ops, + size_t size, int flags) { return ERR_PTR(-ENODEV); } -static inline int dma_buf_fd(struct dma_buf *dmabuf) +static inline int dma_buf_fd(struct dma_buf *dmabuf, int flags) { return -ENODEV; } @@ -166,11 +210,44 @@ static inline struct sg_table *dma_buf_map_attachment( } static inline void dma_buf_unmap_attachment(struct dma_buf_attachment *attach, - struct sg_table *sg) + struct sg_table *sg, enum dma_data_direction dir) { return; } +static inline int dma_buf_begin_cpu_access(struct dma_buf *dmabuf, + size_t start, size_t len, + enum dma_data_direction dir) +{ + return -ENODEV; +} + +static inline void dma_buf_end_cpu_access(struct dma_buf *dmabuf, + size_t start, size_t len, + enum dma_data_direction dir) +{ +} + +static inline void *dma_buf_kmap_atomic(struct dma_buf *dmabuf, + unsigned long pnum) +{ + return NULL; +} + +static inline void dma_buf_kunmap_atomic(struct dma_buf *dmabuf, + unsigned long pnum, void *vaddr) +{ +} + +static inline void *dma_buf_kmap(struct dma_buf *dmabuf, unsigned long pnum) +{ + return NULL; +} + +static inline void dma_buf_kunmap(struct dma_buf *dmabuf, + unsigned long pnum, void *vaddr) +{ +} #endif /* CONFIG_DMA_SHARED_BUFFER */ #endif /* __DMA_BUF_H__ */ diff --git a/include/linux/edac.h b/include/linux/edac.h index ba317e2930a..c621d762bb2 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -70,25 +70,64 @@ enum dev_type { #define DEV_FLAG_X32 BIT(DEV_X32) #define DEV_FLAG_X64 BIT(DEV_X64) -/* memory types */ +/** + * enum mem_type - memory types. For a more detailed reference, please see + * http://en.wikipedia.org/wiki/DRAM + * + * @MEM_EMPTY Empty csrow + * @MEM_RESERVED: Reserved csrow type + * @MEM_UNKNOWN: Unknown csrow type + * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995. + * @MEM_EDO: EDO - Extended data out, used on systems up to 1998. + * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant. + * @MEM_SDR: SDR - Single data rate SDRAM + * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory + * They use 3 pins for chip select: Pins 0 and 2 are + * for rank 0; pins 1 and 3 are for rank 1, if the memory + * is dual-rank. + * @MEM_RDR: Registered SDR SDRAM + * @MEM_DDR: Double data rate SDRAM + * http://en.wikipedia.org/wiki/DDR_SDRAM + * @MEM_RDDR: Registered Double data rate SDRAM + * This is a variant of the DDR memories. + * A registered memory has a buffer inside it, hiding + * part of the memory details to the memory controller. + * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers. + * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F. + * Those memories are labed as "PC2-" instead of "PC" to + * differenciate from DDR. + * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205 + * and JESD206. + * Those memories are accessed per DIMM slot, and not by + * a chip select signal. + * @MEM_RDDR2: Registered DDR2 RAM + * This is a variant of the DDR2 memories. + * @MEM_XDR: Rambus XDR + * It is an evolution of the original RAMBUS memories, + * created to compete with DDR2. Weren't used on any + * x86 arch, but cell_edac PPC memory controller uses it. + * @MEM_DDR3: DDR3 RAM + * @MEM_RDDR3: Registered DDR3 RAM + * This is a variant of the DDR3 memories. + */ enum mem_type { - MEM_EMPTY = 0, /* Empty csrow */ - MEM_RESERVED, /* Reserved csrow type */ - MEM_UNKNOWN, /* Unknown csrow type */ - MEM_FPM, /* Fast page mode */ - MEM_EDO, /* Extended data out */ - MEM_BEDO, /* Burst Extended data out */ - MEM_SDR, /* Single data rate SDRAM */ - MEM_RDR, /* Registered single data rate SDRAM */ - MEM_DDR, /* Double data rate SDRAM */ - MEM_RDDR, /* Registered Double data rate SDRAM */ - MEM_RMBS, /* Rambus DRAM */ - MEM_DDR2, /* DDR2 RAM */ - MEM_FB_DDR2, /* fully buffered DDR2 */ - MEM_RDDR2, /* Registered DDR2 RAM */ - MEM_XDR, /* Rambus XDR */ - MEM_DDR3, /* DDR3 RAM */ - MEM_RDDR3, /* Registered DDR3 RAM */ + MEM_EMPTY = 0, + MEM_RESERVED, + MEM_UNKNOWN, + MEM_FPM, + MEM_EDO, + MEM_BEDO, + MEM_SDR, + MEM_RDR, + MEM_DDR, + MEM_RDDR, + MEM_RMBS, + MEM_DDR2, + MEM_FB_DDR2, + MEM_RDDR2, + MEM_XDR, + MEM_DDR3, + MEM_RDDR3, }; #define MEM_FLAG_EMPTY BIT(MEM_EMPTY) @@ -166,8 +205,9 @@ enum scrub_type { #define OP_OFFLINE 0x300 /* - * There are several things to be aware of that aren't at all obvious: + * Concepts used at the EDAC subsystem * + * There are several things to be aware of that aren't at all obvious: * * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc.. * @@ -176,36 +216,61 @@ enum scrub_type { * creating a common ground for discussion, terms and their definitions * will be established. * - * Memory devices: The individual chip on a memory stick. These devices - * commonly output 4 and 8 bits each. Grouping several - * of these in parallel provides 64 bits which is common - * for a memory stick. + * Memory devices: The individual DRAM chips on a memory stick. These + * devices commonly output 4 and 8 bits each (x4, x8). + * Grouping several of these in parallel provides the + * number of bits that the memory controller expects: + * typically 72 bits, in order to provide 64 bits + + * 8 bits of ECC data. * * Memory Stick: A printed circuit board that aggregates multiple - * memory devices in parallel. This is the atomic - * memory component that is purchaseable by Joe consumer - * and loaded into a memory socket. + * memory devices in parallel. In general, this is the + * Field Replaceable Unit (FRU) which gets replaced, in + * the case of excessive errors. Most often it is also + * called DIMM (Dual Inline Memory Module). + * + * Memory Socket: A physical connector on the motherboard that accepts + * a single memory stick. Also called as "slot" on several + * datasheets. * - * Socket: A physical connector on the motherboard that accepts - * a single memory stick. + * Channel: A memory controller channel, responsible to communicate + * with a group of DIMMs. Each channel has its own + * independent control (command) and data bus, and can + * be used independently or grouped with other channels. * - * Channel: Set of memory devices on a memory stick that must be - * grouped in parallel with one or more additional - * channels from other memory sticks. This parallel - * grouping of the output from multiple channels are - * necessary for the smallest granularity of memory access. - * Some memory controllers are capable of single channel - - * which means that memory sticks can be loaded - * individually. Other memory controllers are only - * capable of dual channel - which means that memory - * sticks must be loaded as pairs (see "socket set"). + * Branch: It is typically the highest hierarchy on a + * Fully-Buffered DIMM memory controller. + * Typically, it contains two channels. + * Two channels at the same branch can be used in single + * mode or in lockstep mode. + * When lockstep is enabled, the cacheline is doubled, + * but it generally brings some performance penalty. + * Also, it is generally not possible to point to just one + * memory stick when an error occurs, as the error + * correction code is calculated using two DIMMs instead + * of one. Due to that, it is capable of correcting more + * errors than on single mode. * - * Chip-select row: All of the memory devices that are selected together. - * for a single, minimum grain of memory access. - * This selects all of the parallel memory devices across - * all of the parallel channels. Common chip-select rows - * for single channel are 64 bits, for dual channel 128 - * bits. + * Single-channel: The data accessed by the memory controller is contained + * into one dimm only. E. g. if the data is 64 bits-wide, + * the data flows to the CPU using one 64 bits parallel + * access. + * Typically used with SDR, DDR, DDR2 and DDR3 memories. + * FB-DIMM and RAMBUS use a different concept for channel, + * so this concept doesn't apply there. + * + * Double-channel: The data size accessed by the memory controller is + * interlaced into two dimms, accessed at the same time. + * E. g. if the DIMM is 64 bits-wide (72 bits with ECC), + * the data flows to the CPU using a 128 bits parallel + * access. + * + * Chip-select row: This is the name of the DRAM signal used to select the + * DRAM ranks to be accessed. Common chip-select rows for + * single channel are 64 bits, for dual channel 128 bits. + * It may not be visible by the memory controller, as some + * DIMM types have a memory buffer that can hide direct + * access to it from the Memory Controller. * * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory. * Motherboards commonly drive two chip-select pins to @@ -218,8 +283,8 @@ enum scrub_type { * * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick. * A double-sided stick has two chip-select rows which - * access different sets of memory devices. The two - * rows cannot be accessed concurrently. "Double-sided" + * access different sets of memory devices. The two + * rows cannot be accessed concurrently. "Double-sided" * is irrespective of the memory devices being mounted * on both sides of the memory stick. * @@ -247,10 +312,22 @@ enum scrub_type { * PS - I enjoyed writing all that about as much as you enjoyed reading it. */ -struct channel_info { - int chan_idx; /* channel index */ - u32 ce_count; /* Correctable Errors for this CHANNEL */ - char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */ +/** + * struct rank_info - contains the information for one DIMM rank + * + * @chan_idx: channel number where the rank is (typically, 0 or 1) + * @ce_count: number of correctable errors for this rank + * @label: DIMM label. Different ranks for the same DIMM should be + * filled, on userspace, with the same label. + * FIXME: The core currently won't enforce it. + * @csrow: A pointer to the chip select row structure (the parent + * structure). The location of the rank is given by + * the (csrow->csrow_idx, chan_idx) vector. + */ +struct rank_info { + int chan_idx; + u32 ce_count; + char label[EDAC_MC_LABEL_LEN + 1]; struct csrow_info *csrow; /* the parent */ }; @@ -274,7 +351,7 @@ struct csrow_info { /* channel information for this csrow */ u32 nr_channels; - struct channel_info *channels; + struct rank_info *channels; }; struct mcidev_sysfs_group { diff --git a/include/linux/efi.h b/include/linux/efi.h index 47fbf6b3dc7..88ec80670d5 100644 --- a/include/linux/efi.h +++ b/include/linux/efi.h @@ -22,7 +22,6 @@ #include <linux/pstore.h> #include <asm/page.h> -#include <asm/system.h> #define EFI_SUCCESS 0 #define EFI_LOAD_ERROR ( 1 | (1UL << (BITS_PER_LONG-1))) diff --git a/include/linux/gpio.h b/include/linux/gpio.h index ed5a46707ad..6155ecf192b 100644 --- a/include/linux/gpio.h +++ b/include/linux/gpio.h @@ -14,6 +14,12 @@ #define GPIOF_OUT_INIT_LOW (GPIOF_DIR_OUT | GPIOF_INIT_LOW) #define GPIOF_OUT_INIT_HIGH (GPIOF_DIR_OUT | GPIOF_INIT_HIGH) +/* Gpio pin is open drain */ +#define GPIOF_OPEN_DRAIN (1 << 2) + +/* Gpio pin is open source */ +#define GPIOF_OPEN_SOURCE (1 << 3) + /** * struct gpio - a structure describing a GPIO with configuration * @gpio: the GPIO number diff --git a/include/linux/i2c-algo-bit.h b/include/linux/i2c-algo-bit.h index 584ffa0f328..63904ba6887 100644 --- a/include/linux/i2c-algo-bit.h +++ b/include/linux/i2c-algo-bit.h @@ -15,7 +15,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301 USA. */ /* ------------------------------------------------------------------------- */ /* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and even diff --git a/include/linux/i2c-algo-pcf.h b/include/linux/i2c-algo-pcf.h index 0f91a957a69..538e8f41a31 100644 --- a/include/linux/i2c-algo-pcf.h +++ b/include/linux/i2c-algo-pcf.h @@ -16,7 +16,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301 USA. */ /* ------------------------------------------------------------------------- */ /* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and even diff --git a/include/linux/i2c-dev.h b/include/linux/i2c-dev.h index fd53bfd2647..8a7406b2114 100644 --- a/include/linux/i2c-dev.h +++ b/include/linux/i2c-dev.h @@ -16,7 +16,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301 USA. */ #ifndef _LINUX_I2C_DEV_H diff --git a/include/linux/i2c-mux.h b/include/linux/i2c-mux.h index 34536effd65..747f0cde416 100644 --- a/include/linux/i2c-mux.h +++ b/include/linux/i2c-mux.h @@ -18,7 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA. */ #ifndef _LINUX_I2C_MUX_H diff --git a/include/linux/i2c-smbus.h b/include/linux/i2c-smbus.h index 63f57a8c8b3..017fb40f702 100644 --- a/include/linux/i2c-smbus.h +++ b/include/linux/i2c-smbus.h @@ -15,7 +15,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA. */ #ifndef _LINUX_I2C_SMBUS_H diff --git a/include/linux/i2c.h b/include/linux/i2c.h index 8e25a9167f1..195d8b3d9cf 100644 --- a/include/linux/i2c.h +++ b/include/linux/i2c.h @@ -17,7 +17,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301 USA. */ /* ------------------------------------------------------------------------- */ /* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h index 7fcab23c59c..2463b610033 100644 --- a/include/linux/i2c/twl.h +++ b/include/linux/i2c/twl.h @@ -761,7 +761,7 @@ struct twl_regulator_driver_data { /*----------------------------------------------------------------------*/ -int twl4030_sih_setup(int module); +int twl4030_sih_setup(struct device *dev, int module, int irq_base); /* Offsets to Power Registers */ #define TWL4030_VDAC_DEV_GRP 0x3B diff --git a/include/linux/ide.h b/include/linux/ide.h index 7afe15f916d..b17974917db 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -22,7 +22,6 @@ #include <acpi/acpi.h> #endif #include <asm/byteorder.h> -#include <asm/system.h> #include <asm/io.h> /* for request_sense */ diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h index 3f830e00511..2aea5d22db0 100644 --- a/include/linux/interrupt.h +++ b/include/linux/interrupt.h @@ -19,7 +19,6 @@ #include <linux/atomic.h> #include <asm/ptrace.h> -#include <asm/system.h> /* * These correspond to the IORESOURCE_IRQ_* defines in diff --git a/include/linux/kvm.h b/include/linux/kvm.h index 68e67e50d02..6c322a90b92 100644 --- a/include/linux/kvm.h +++ b/include/linux/kvm.h @@ -162,6 +162,7 @@ struct kvm_pit_config { #define KVM_EXIT_INTERNAL_ERROR 17 #define KVM_EXIT_OSI 18 #define KVM_EXIT_PAPR_HCALL 19 +#define KVM_EXIT_S390_UCONTROL 20 /* For KVM_EXIT_INTERNAL_ERROR */ #define KVM_INTERNAL_ERROR_EMULATION 1 @@ -249,6 +250,11 @@ struct kvm_run { #define KVM_S390_RESET_CPU_INIT 8 #define KVM_S390_RESET_IPL 16 __u64 s390_reset_flags; + /* KVM_EXIT_S390_UCONTROL */ + struct { + __u64 trans_exc_code; + __u32 pgm_code; + } s390_ucontrol; /* KVM_EXIT_DCR */ struct { __u32 dcrn; @@ -273,6 +279,20 @@ struct kvm_run { /* Fix the size of the union. */ char padding[256]; }; + + /* + * shared registers between kvm and userspace. + * kvm_valid_regs specifies the register classes set by the host + * kvm_dirty_regs specified the register classes dirtied by userspace + * struct kvm_sync_regs is architecture specific, as well as the + * bits for kvm_valid_regs and kvm_dirty_regs + */ + __u64 kvm_valid_regs; + __u64 kvm_dirty_regs; + union { + struct kvm_sync_regs regs; + char padding[1024]; + } s; }; /* for KVM_REGISTER_COALESCED_MMIO / KVM_UNREGISTER_COALESCED_MMIO */ @@ -431,6 +451,11 @@ struct kvm_ppc_pvinfo { #define KVMIO 0xAE +/* machine type bits, to be used as argument to KVM_CREATE_VM */ +#define KVM_VM_S390_UCONTROL 1 + +#define KVM_S390_SIE_PAGE_OFFSET 1 + /* * ioctls for /dev/kvm fds: */ @@ -555,9 +580,15 @@ struct kvm_ppc_pvinfo { #define KVM_CAP_PPC_SMT 64 #define KVM_CAP_PPC_RMA 65 #define KVM_CAP_MAX_VCPUS 66 /* returns max vcpus per vm */ +#define KVM_CAP_PPC_HIOR 67 #define KVM_CAP_PPC_PAPR 68 +#define KVM_CAP_SW_TLB 69 +#define KVM_CAP_ONE_REG 70 #define KVM_CAP_S390_GMAP 71 #define KVM_CAP_TSC_DEADLINE_TIMER 72 +#define KVM_CAP_S390_UCONTROL 73 +#define KVM_CAP_SYNC_REGS 74 +#define KVM_CAP_PCI_2_3 75 #ifdef KVM_CAP_IRQ_ROUTING @@ -637,6 +668,52 @@ struct kvm_clock_data { __u32 pad[9]; }; +#define KVM_MMU_FSL_BOOKE_NOHV 0 +#define KVM_MMU_FSL_BOOKE_HV 1 + +struct kvm_config_tlb { + __u64 params; + __u64 array; + __u32 mmu_type; + __u32 array_len; +}; + +struct kvm_dirty_tlb { + __u64 bitmap; + __u32 num_dirty; +}; + +/* Available with KVM_CAP_ONE_REG */ + +#define KVM_REG_ARCH_MASK 0xff00000000000000ULL +#define KVM_REG_GENERIC 0x0000000000000000ULL + +/* + * Architecture specific registers are to be defined in arch headers and + * ORed with the arch identifier. + */ +#define KVM_REG_PPC 0x1000000000000000ULL +#define KVM_REG_X86 0x2000000000000000ULL +#define KVM_REG_IA64 0x3000000000000000ULL +#define KVM_REG_ARM 0x4000000000000000ULL +#define KVM_REG_S390 0x5000000000000000ULL + +#define KVM_REG_SIZE_SHIFT 52 +#define KVM_REG_SIZE_MASK 0x00f0000000000000ULL +#define KVM_REG_SIZE_U8 0x0000000000000000ULL +#define KVM_REG_SIZE_U16 0x0010000000000000ULL +#define KVM_REG_SIZE_U32 0x0020000000000000ULL +#define KVM_REG_SIZE_U64 0x0030000000000000ULL +#define KVM_REG_SIZE_U128 0x0040000000000000ULL +#define KVM_REG_SIZE_U256 0x0050000000000000ULL +#define KVM_REG_SIZE_U512 0x0060000000000000ULL +#define KVM_REG_SIZE_U1024 0x0070000000000000ULL + +struct kvm_one_reg { + __u64 id; + __u64 addr; +}; + /* * ioctls for VM fds */ @@ -655,6 +732,17 @@ struct kvm_clock_data { struct kvm_userspace_memory_region) #define KVM_SET_TSS_ADDR _IO(KVMIO, 0x47) #define KVM_SET_IDENTITY_MAP_ADDR _IOW(KVMIO, 0x48, __u64) + +/* enable ucontrol for s390 */ +struct kvm_s390_ucas_mapping { + __u64 user_addr; + __u64 vcpu_addr; + __u64 length; +}; +#define KVM_S390_UCAS_MAP _IOW(KVMIO, 0x50, struct kvm_s390_ucas_mapping) +#define KVM_S390_UCAS_UNMAP _IOW(KVMIO, 0x51, struct kvm_s390_ucas_mapping) +#define KVM_S390_VCPU_FAULT _IOW(KVMIO, 0x52, unsigned long) + /* Device model IOC */ #define KVM_CREATE_IRQCHIP _IO(KVMIO, 0x60) #define KVM_IRQ_LINE _IOW(KVMIO, 0x61, struct kvm_irq_level) @@ -697,6 +785,9 @@ struct kvm_clock_data { /* Available with KVM_CAP_TSC_CONTROL */ #define KVM_SET_TSC_KHZ _IO(KVMIO, 0xa2) #define KVM_GET_TSC_KHZ _IO(KVMIO, 0xa3) +/* Available with KVM_CAP_PCI_2_3 */ +#define KVM_ASSIGN_SET_INTX_MASK _IOW(KVMIO, 0xa4, \ + struct kvm_assigned_pci_dev) /* * ioctls for vcpu fds @@ -763,8 +854,15 @@ struct kvm_clock_data { #define KVM_CREATE_SPAPR_TCE _IOW(KVMIO, 0xa8, struct kvm_create_spapr_tce) /* Available with KVM_CAP_RMA */ #define KVM_ALLOCATE_RMA _IOR(KVMIO, 0xa9, struct kvm_allocate_rma) +/* Available with KVM_CAP_SW_TLB */ +#define KVM_DIRTY_TLB _IOW(KVMIO, 0xaa, struct kvm_dirty_tlb) +/* Available with KVM_CAP_ONE_REG */ +#define KVM_GET_ONE_REG _IOW(KVMIO, 0xab, struct kvm_one_reg) +#define KVM_SET_ONE_REG _IOW(KVMIO, 0xac, struct kvm_one_reg) #define KVM_DEV_ASSIGN_ENABLE_IOMMU (1 << 0) +#define KVM_DEV_ASSIGN_PCI_2_3 (1 << 1) +#define KVM_DEV_ASSIGN_MASK_INTX (1 << 2) struct kvm_assigned_pci_dev { __u32 assigned_dev_id; diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index ca1b153585d..665a260c7e0 100644 --- a/include/linux/kvm_host.h +++ b/include/linux/kvm_host.h @@ -172,11 +172,6 @@ static inline int kvm_vcpu_exiting_guest_mode(struct kvm_vcpu *vcpu) */ #define KVM_MEM_MAX_NR_PAGES ((1UL << 31) - 1) -struct kvm_lpage_info { - unsigned long rmap_pde; - int write_count; -}; - struct kvm_memory_slot { gfn_t base_gfn; unsigned long npages; @@ -185,7 +180,7 @@ struct kvm_memory_slot { unsigned long *dirty_bitmap; unsigned long *dirty_bitmap_head; unsigned long nr_dirty_pages; - struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; + struct kvm_arch_memory_slot arch; unsigned long userspace_addr; int user_alloc; int id; @@ -377,6 +372,9 @@ int kvm_set_memory_region(struct kvm *kvm, int __kvm_set_memory_region(struct kvm *kvm, struct kvm_userspace_memory_region *mem, int user_alloc); +void kvm_arch_free_memslot(struct kvm_memory_slot *free, + struct kvm_memory_slot *dont); +int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages); int kvm_arch_prepare_memory_region(struct kvm *kvm, struct kvm_memory_slot *memslot, struct kvm_memory_slot old, @@ -386,6 +384,7 @@ void kvm_arch_commit_memory_region(struct kvm *kvm, struct kvm_userspace_memory_region *mem, struct kvm_memory_slot old, int user_alloc); +bool kvm_largepages_enabled(void); void kvm_disable_largepages(void); void kvm_arch_flush_shadow(struct kvm *kvm); @@ -451,6 +450,7 @@ long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg); long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg); +int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf); int kvm_dev_ioctl_check_extension(long ext); @@ -521,7 +521,7 @@ static inline void kvm_arch_free_vm(struct kvm *kvm) } #endif -int kvm_arch_init_vm(struct kvm *kvm); +int kvm_arch_init_vm(struct kvm *kvm, unsigned long type); void kvm_arch_destroy_vm(struct kvm *kvm); void kvm_free_all_assigned_devices(struct kvm *kvm); void kvm_arch_sync_events(struct kvm *kvm); @@ -547,6 +547,7 @@ struct kvm_assigned_dev_kernel { unsigned int entries_nr; int host_irq; bool host_irq_disabled; + bool pci_2_3; struct msix_entry *host_msix_entries; int guest_irq; struct msix_entry *guest_msix_entries; @@ -556,6 +557,7 @@ struct kvm_assigned_dev_kernel { struct pci_dev *dev; struct kvm *kvm; spinlock_t intx_lock; + spinlock_t intx_mask_lock; char irq_name[32]; struct pci_saved_state *pci_saved_state; }; @@ -651,11 +653,43 @@ static inline void kvm_guest_exit(void) current->flags &= ~PF_VCPU; } +/* + * search_memslots() and __gfn_to_memslot() are here because they are + * used in non-modular code in arch/powerpc/kvm/book3s_hv_rm_mmu.c. + * gfn_to_memslot() itself isn't here as an inline because that would + * bloat other code too much. + */ +static inline struct kvm_memory_slot * +search_memslots(struct kvm_memslots *slots, gfn_t gfn) +{ + struct kvm_memory_slot *memslot; + + kvm_for_each_memslot(memslot, slots) + if (gfn >= memslot->base_gfn && + gfn < memslot->base_gfn + memslot->npages) + return memslot; + + return NULL; +} + +static inline struct kvm_memory_slot * +__gfn_to_memslot(struct kvm_memslots *slots, gfn_t gfn) +{ + return search_memslots(slots, gfn); +} + static inline int memslot_id(struct kvm *kvm, gfn_t gfn) { return gfn_to_memslot(kvm, gfn)->id; } +static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) +{ + /* KVM_HPAGE_GFN_SHIFT(PT_PAGE_TABLE_LEVEL) must be 0. */ + return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - + (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); +} + static inline unsigned long gfn_to_hva_memslot(struct kvm_memory_slot *slot, gfn_t gfn) { @@ -702,12 +736,16 @@ static inline int mmu_notifier_retry(struct kvm_vcpu *vcpu, unsigned long mmu_se if (unlikely(vcpu->kvm->mmu_notifier_count)) return 1; /* - * Both reads happen under the mmu_lock and both values are - * modified under mmu_lock, so there's no need of smb_rmb() - * here in between, otherwise mmu_notifier_count should be - * read before mmu_notifier_seq, see - * mmu_notifier_invalidate_range_end write side. + * Ensure the read of mmu_notifier_count happens before the read + * of mmu_notifier_seq. This interacts with the smp_wmb() in + * mmu_notifier_invalidate_range_end to make sure that the caller + * either sees the old (non-zero) value of mmu_notifier_count or + * the new (incremented) value of mmu_notifier_seq. + * PowerPC Book3s HV KVM calls this under a per-page lock + * rather than under kvm->mmu_lock, for scalability, so + * can't rely on kvm->mmu_lock to keep things ordered. */ + smp_rmb(); if (vcpu->kvm->mmu_notifier_seq != mmu_seq) return 1; return 0; @@ -770,6 +808,13 @@ static inline bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) { return vcpu->kvm->bsp_vcpu_id == vcpu->vcpu_id; } + +bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu); + +#else + +static inline bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) { return true; } + #endif #ifdef __KVM_HAVE_DEVICE_ASSIGNMENT diff --git a/include/linux/llist.h b/include/linux/llist.h index 801b44b07aa..a5199f6d0e8 100644 --- a/include/linux/llist.h +++ b/include/linux/llist.h @@ -56,8 +56,7 @@ */ #include <linux/kernel.h> -#include <asm/system.h> -#include <asm/processor.h> +#include <asm/cmpxchg.h> struct llist_head { struct llist_node *first; diff --git a/include/linux/lsm_audit.h b/include/linux/lsm_audit.h index 88e78dedc2e..eab507f2b1c 100644 --- a/include/linux/lsm_audit.h +++ b/include/linux/lsm_audit.h @@ -21,7 +21,6 @@ #include <linux/path.h> #include <linux/key.h> #include <linux/skbuff.h> -#include <asm/system.h> /* Auxiliary data to use in generating the audit record. */ diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h index 92be3476c9f..84d071ade1d 100644 --- a/include/linux/mfd/88pm860x.h +++ b/include/linux/mfd/88pm860x.h @@ -263,6 +263,22 @@ enum { #define PM8607_PD_PREBIAS_MASK (0x1F << 0) #define PM8607_PD_PRECHG_MASK (7 << 5) +#define PM8606_REF_GP_OSC_OFF 0 +#define PM8606_REF_GP_OSC_ON 1 +#define PM8606_REF_GP_OSC_UNKNOWN 2 + +/* Clients of reference group and 8MHz oscillator in 88PM8606 */ +enum pm8606_ref_gp_and_osc_clients { + REF_GP_NO_CLIENTS = 0, + WLED1_DUTY = (1<<0), /*PF 0x02.7:0*/ + WLED2_DUTY = (1<<1), /*PF 0x04.7:0*/ + WLED3_DUTY = (1<<2), /*PF 0x06.7:0*/ + RGB1_ENABLE = (1<<3), /*PF 0x07.1*/ + RGB2_ENABLE = (1<<4), /*PF 0x07.2*/ + LDO_VBR_EN = (1<<5), /*PF 0x12.0*/ + REF_GP_MAX_CLIENT = 0xFFFF +}; + /* Interrupt Number in 88PM8607 */ enum { PM8607_IRQ_ONKEY, @@ -298,6 +314,7 @@ enum { struct pm860x_chip { struct device *dev; struct mutex irq_lock; + struct mutex osc_lock; struct i2c_client *client; struct i2c_client *companion; /* companion chip client */ struct regmap *regmap; @@ -305,12 +322,15 @@ struct pm860x_chip { int buck3_double; /* DVC ramp slope double */ unsigned short companion_addr; + unsigned short osc_vote; int id; int irq_mode; int irq_base; int core_irq; unsigned char chip_version; + unsigned char osc_status; + unsigned int wakeup_flag; }; enum { @@ -369,6 +389,9 @@ struct pm860x_platform_data { int num_regulators; }; +extern int pm8606_osc_enable(struct pm860x_chip *, unsigned short); +extern int pm8606_osc_disable(struct pm860x_chip *, unsigned short); + extern int pm860x_reg_read(struct i2c_client *, int); extern int pm860x_reg_write(struct i2c_client *, int, unsigned char); extern int pm860x_bulk_read(struct i2c_client *, int, int, unsigned char *); diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h index e20dd6ead1d..5fa697477b7 100644 --- a/include/linux/mfd/abx500.h +++ b/include/linux/mfd/abx500.h @@ -34,13 +34,6 @@ struct device; #define AB5500_1_1 0x21 #define AB5500_2_0 0x24 -/* AB8500 CIDs*/ -#define AB8500_CUT1P0 0x10 -#define AB8500_CUT1P1 0x11 -#define AB8500_CUT2P0 0x20 -#define AB8500_CUT3P0 0x30 -#define AB8500_CUT3P3 0x33 - /* * AB3100, EVENTA1, A2 and A3 event register flags * these are catenated into a single 32-bit flag in the code diff --git a/include/linux/mfd/abx500/ab8500-gpio.h b/include/linux/mfd/abx500/ab8500-gpio.h index 488a8c920a2..2387c207ea8 100644 --- a/include/linux/mfd/abx500/ab8500-gpio.h +++ b/include/linux/mfd/abx500/ab8500-gpio.h @@ -10,12 +10,14 @@ /* * Platform data to register a block: only the initial gpio/irq number. + * Array sizes are large enough to contain all AB8500 and AB9540 GPIO + * registers. */ struct ab8500_gpio_platform_data { int gpio_base; u32 irq_base; - u8 config_reg[7]; + u8 config_reg[8]; }; #endif /* _AB8500_GPIO_H */ diff --git a/include/linux/mfd/abx500/ab8500-sysctrl.h b/include/linux/mfd/abx500/ab8500-sysctrl.h index 10da0291f8f..10eb50973c3 100644 --- a/include/linux/mfd/abx500/ab8500-sysctrl.h +++ b/include/linux/mfd/abx500/ab8500-sysctrl.h @@ -71,6 +71,13 @@ static inline int ab8500_sysctrl_clear(u16 reg, u8 bits) #define AB8500_SWATCTRL 0x230 #define AB8500_HIQCLKCTRL 0x232 #define AB8500_VSIMSYSCLKCTRL 0x233 +#define AB9540_SYSCLK12BUFCTRL 0x234 +#define AB9540_SYSCLK12CONFCTRL 0x235 +#define AB9540_SYSCLK12BUFCTRL2 0x236 +#define AB9540_SYSCLK12BUF1VALID 0x237 +#define AB9540_SYSCLK12BUF2VALID 0x238 +#define AB9540_SYSCLK12BUF3VALID 0x239 +#define AB9540_SYSCLK12BUF4VALID 0x23A /* Bits */ #define AB8500_TURNONSTATUS_PORNVBAT BIT(0) @@ -251,4 +258,40 @@ static inline int ab8500_sysctrl_clear(u16 reg, u8 bits) #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6) #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7) +#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1ENA BIT(0) +#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2ENA BIT(1) +#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3ENA BIT(2) +#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4ENA BIT(3) +#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFENA_MASK 0x0F +#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1STRE BIT(4) +#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2STRE BIT(5) +#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3STRE BIT(6) +#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4STRE BIT(7) +#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFSTRE_MASK 0xF0 + +#define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0) +#define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1) +#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_MASK 0x0C +#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_SHIFT 2 +#define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4) +#define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5) +#define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6) + +#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF1PDENA BIT(0) +#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF2PDENA BIT(1) +#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF3PDENA BIT(2) +#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF4PDENA BIT(3) + +#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_MASK 0xFF +#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_SHIFT 0 + +#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_MASK 0xFF +#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_SHIFT 0 + +#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_MASK 0xFF +#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_SHIFT 0 + +#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_MASK 0xFF +#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_SHIFT 0 + #endif /* __AB8500_SYSCTRL_H */ diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h index dca94396190..fccc3002f27 100644 --- a/include/linux/mfd/abx500/ab8500.h +++ b/include/linux/mfd/abx500/ab8500.h @@ -12,6 +12,29 @@ struct device; /* + * AB IC versions + * + * AB8500_VERSION_AB8500 should be 0xFF but will never be read as need a + * non-supported multi-byte I2C access via PRCMU. Set to 0x00 to ease the + * print of version string. + */ +enum ab8500_version { + AB8500_VERSION_AB8500 = 0x0, + AB8500_VERSION_AB8505 = 0x1, + AB8500_VERSION_AB9540 = 0x2, + AB8500_VERSION_AB8540 = 0x3, + AB8500_VERSION_UNDEFINED, +}; + +/* AB8500 CIDs*/ +#define AB8500_CUTEARLY 0x00 +#define AB8500_CUT1P0 0x10 +#define AB8500_CUT1P1 0x11 +#define AB8500_CUT2P0 0x20 +#define AB8500_CUT3P0 0x30 +#define AB8500_CUT3P3 0x33 + +/* * AB8500 bank addresses */ #define AB8500_SYS_CTRL1_BLOCK 0x1 @@ -37,30 +60,34 @@ struct device; /* * Interrupts + * Values used to index into array ab8500_irq_regoffset[] defined in + * drivers/mdf/ab8500-core.c */ - -#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 -#define AB8500_INT_UN_PLUG_TV_DET 1 -#define AB8500_INT_PLUG_TV_DET 2 +/* Definitions for AB8500 and AB9540 */ +/* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */ +#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 /* not 8505/9540 */ +#define AB8500_INT_UN_PLUG_TV_DET 1 /* not 8505/9540 */ +#define AB8500_INT_PLUG_TV_DET 2 /* not 8505/9540 */ #define AB8500_INT_TEMP_WARM 3 #define AB8500_INT_PON_KEY2DB_F 4 #define AB8500_INT_PON_KEY2DB_R 5 #define AB8500_INT_PON_KEY1DB_F 6 #define AB8500_INT_PON_KEY1DB_R 7 +/* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */ #define AB8500_INT_BATT_OVV 8 -#define AB8500_INT_MAIN_CH_UNPLUG_DET 10 -#define AB8500_INT_MAIN_CH_PLUG_DET 11 -#define AB8500_INT_USB_ID_DET_F 12 -#define AB8500_INT_USB_ID_DET_R 13 +#define AB8500_INT_MAIN_CH_UNPLUG_DET 10 /* not 8505 */ +#define AB8500_INT_MAIN_CH_PLUG_DET 11 /* not 8505 */ #define AB8500_INT_VBUS_DET_F 14 #define AB8500_INT_VBUS_DET_R 15 +/* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */ #define AB8500_INT_VBUS_CH_DROP_END 16 #define AB8500_INT_RTC_60S 17 #define AB8500_INT_RTC_ALARM 18 #define AB8500_INT_BAT_CTRL_INDB 20 #define AB8500_INT_CH_WD_EXP 21 #define AB8500_INT_VBUS_OVV 22 -#define AB8500_INT_MAIN_CH_DROP_END 23 +#define AB8500_INT_MAIN_CH_DROP_END 23 /* not 8505/9540 */ +/* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */ #define AB8500_INT_CCN_CONV_ACC 24 #define AB8500_INT_INT_AUD 25 #define AB8500_INT_CCEOC 26 @@ -69,7 +96,8 @@ struct device; #define AB8500_INT_LOW_BAT_R 29 #define AB8500_INT_BUP_CHG_NOT_OK 30 #define AB8500_INT_BUP_CHG_OK 31 -#define AB8500_INT_GP_HW_ADC_CONV_END 32 +/* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */ +#define AB8500_INT_GP_HW_ADC_CONV_END 32 /* not 8505 */ #define AB8500_INT_ACC_DETECT_1DB_F 33 #define AB8500_INT_ACC_DETECT_1DB_R 34 #define AB8500_INT_ACC_DETECT_22DB_F 35 @@ -77,38 +105,43 @@ struct device; #define AB8500_INT_ACC_DETECT_21DB_F 37 #define AB8500_INT_ACC_DETECT_21DB_R 38 #define AB8500_INT_GP_SW_ADC_CONV_END 39 -#define AB8500_INT_GPIO6R 40 -#define AB8500_INT_GPIO7R 41 -#define AB8500_INT_GPIO8R 42 -#define AB8500_INT_GPIO9R 43 +/* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */ +#define AB8500_INT_GPIO6R 40 /* not 8505/9540 */ +#define AB8500_INT_GPIO7R 41 /* not 8505/9540 */ +#define AB8500_INT_GPIO8R 42 /* not 8505/9540 */ +#define AB8500_INT_GPIO9R 43 /* not 8505/9540 */ #define AB8500_INT_GPIO10R 44 #define AB8500_INT_GPIO11R 45 -#define AB8500_INT_GPIO12R 46 +#define AB8500_INT_GPIO12R 46 /* not 8505 */ #define AB8500_INT_GPIO13R 47 -#define AB8500_INT_GPIO24R 48 -#define AB8500_INT_GPIO25R 49 -#define AB8500_INT_GPIO36R 50 -#define AB8500_INT_GPIO37R 51 -#define AB8500_INT_GPIO38R 52 -#define AB8500_INT_GPIO39R 53 +/* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */ +#define AB8500_INT_GPIO24R 48 /* not 8505 */ +#define AB8500_INT_GPIO25R 49 /* not 8505 */ +#define AB8500_INT_GPIO36R 50 /* not 8505/9540 */ +#define AB8500_INT_GPIO37R 51 /* not 8505/9540 */ +#define AB8500_INT_GPIO38R 52 /* not 8505/9540 */ +#define AB8500_INT_GPIO39R 53 /* not 8505/9540 */ #define AB8500_INT_GPIO40R 54 #define AB8500_INT_GPIO41R 55 -#define AB8500_INT_GPIO6F 56 -#define AB8500_INT_GPIO7F 57 -#define AB8500_INT_GPIO8F 58 -#define AB8500_INT_GPIO9F 59 +/* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */ +#define AB8500_INT_GPIO6F 56 /* not 8505/9540 */ +#define AB8500_INT_GPIO7F 57 /* not 8505/9540 */ +#define AB8500_INT_GPIO8F 58 /* not 8505/9540 */ +#define AB8500_INT_GPIO9F 59 /* not 8505/9540 */ #define AB8500_INT_GPIO10F 60 #define AB8500_INT_GPIO11F 61 -#define AB8500_INT_GPIO12F 62 +#define AB8500_INT_GPIO12F 62 /* not 8505 */ #define AB8500_INT_GPIO13F 63 -#define AB8500_INT_GPIO24F 64 -#define AB8500_INT_GPIO25F 65 -#define AB8500_INT_GPIO36F 66 -#define AB8500_INT_GPIO37F 67 -#define AB8500_INT_GPIO38F 68 -#define AB8500_INT_GPIO39F 69 +/* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */ +#define AB8500_INT_GPIO24F 64 /* not 8505 */ +#define AB8500_INT_GPIO25F 65 /* not 8505 */ +#define AB8500_INT_GPIO36F 66 /* not 8505/9540 */ +#define AB8500_INT_GPIO37F 67 /* not 8505/9540 */ +#define AB8500_INT_GPIO38F 68 /* not 8505/9540 */ +#define AB8500_INT_GPIO39F 69 /* not 8505/9540 */ #define AB8500_INT_GPIO40F 70 #define AB8500_INT_GPIO41F 71 +/* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */ #define AB8500_INT_ADP_SOURCE_ERROR 72 #define AB8500_INT_ADP_SINK_ERROR 73 #define AB8500_INT_ADP_PROBE_PLUG 74 @@ -116,30 +149,67 @@ struct device; #define AB8500_INT_ADP_SENSE_OFF 76 #define AB8500_INT_USB_PHY_POWER_ERR 78 #define AB8500_INT_USB_LINK_STATUS 79 +/* ab8500_irq_regoffset[10] -> IT[Source|Latch|Mask]19 */ #define AB8500_INT_BTEMP_LOW 80 #define AB8500_INT_BTEMP_LOW_MEDIUM 81 #define AB8500_INT_BTEMP_MEDIUM_HIGH 82 #define AB8500_INT_BTEMP_HIGH 83 -#define AB8500_INT_USB_CHARGER_NOT_OK 89 +/* ab8500_irq_regoffset[11] -> IT[Source|Latch|Mask]20 */ +#define AB8500_INT_SRP_DETECT 88 +#define AB8500_INT_USB_CHARGER_NOT_OKR 89 #define AB8500_INT_ID_WAKEUP_R 90 #define AB8500_INT_ID_DET_R1R 92 #define AB8500_INT_ID_DET_R2R 93 #define AB8500_INT_ID_DET_R3R 94 #define AB8500_INT_ID_DET_R4R 95 +/* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */ #define AB8500_INT_ID_WAKEUP_F 96 #define AB8500_INT_ID_DET_R1F 98 #define AB8500_INT_ID_DET_R2F 99 #define AB8500_INT_ID_DET_R3F 100 #define AB8500_INT_ID_DET_R4F 101 -#define AB8500_INT_USB_CHG_DET_DONE 102 +#define AB8500_INT_CHAUTORESTARTAFTSEC 102 +#define AB8500_INT_CHSTOPBYSEC 103 +/* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */ #define AB8500_INT_USB_CH_TH_PROT_F 104 #define AB8500_INT_USB_CH_TH_PROT_R 105 -#define AB8500_INT_MAIN_CH_TH_PROT_F 106 -#define AB8500_INT_MAIN_CH_TH_PROT_R 107 -#define AB8500_INT_USB_CHARGER_NOT_OKF 111 +#define AB8500_INT_MAIN_CH_TH_PROT_F 106 /* not 8505/9540 */ +#define AB8500_INT_MAIN_CH_TH_PROT_R 107 /* not 8505/9540 */ +#define AB8500_INT_CHCURLIMNOHSCHIRP 109 +#define AB8500_INT_CHCURLIMHSCHIRP 110 +#define AB8500_INT_XTAL32K_KO 111 + +/* Definitions for AB9540 */ +/* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */ +#define AB9540_INT_GPIO50R 113 +#define AB9540_INT_GPIO51R 114 /* not 8505 */ +#define AB9540_INT_GPIO52R 115 +#define AB9540_INT_GPIO53R 116 +#define AB9540_INT_GPIO54R 117 /* not 8505 */ +#define AB9540_INT_IEXT_CH_RF_BFN_R 118 +#define AB9540_INT_IEXT_CH_RF_BFN_F 119 +/* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */ +#define AB9540_INT_GPIO50F 121 +#define AB9540_INT_GPIO51F 122 /* not 8505 */ +#define AB9540_INT_GPIO52F 123 +#define AB9540_INT_GPIO53F 124 +#define AB9540_INT_GPIO54F 125 /* not 8505 */ +/* + * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the + * entire platform. This is a "compile time" constant so this must be set to + * the largest possible value that may be encountered with different AB SOCs. + * Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540 + * which is larger. + */ #define AB8500_NR_IRQS 112 +#define AB8505_NR_IRQS 128 +#define AB9540_NR_IRQS 128 +/* This is set to the roof of any AB8500 chip variant IRQ counts */ +#define AB8500_MAX_NR_IRQS AB9540_NR_IRQS + #define AB8500_NUM_IRQ_REGS 14 +#define AB9540_NUM_IRQ_REGS 17 /** * struct ab8500 - ab8500 internal structure @@ -147,13 +217,18 @@ struct device; * @lock: read/write operations lock * @irq_lock: genirq bus lock * @irq: irq line + * @version: chip version id (e.g. ab8500 or ab9540) * @chip_id: chip revision id * @write: register write + * @write_masked: masked register write * @read: register read * @rx_buf: rx buf for SPI * @tx_buf: tx buf for SPI * @mask: cache of IRQ regs for bus lock * @oldmask: cache of previous IRQ regs for bus lock + * @mask_size: Actual number of valid entries in mask[], oldmask[] and + * irq_reg_offset + * @irq_reg_offset: Array of offsets into IRQ registers */ struct ab8500 { struct device *dev; @@ -162,16 +237,20 @@ struct ab8500 { int irq_base; int irq; + enum ab8500_version version; u8 chip_id; - int (*write) (struct ab8500 *a8500, u16 addr, u8 data); - int (*read) (struct ab8500 *a8500, u16 addr); + int (*write)(struct ab8500 *ab8500, u16 addr, u8 data); + int (*write_masked)(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data); + int (*read)(struct ab8500 *ab8500, u16 addr); unsigned long tx_buf[4]; unsigned long rx_buf[4]; - u8 mask[AB8500_NUM_IRQ_REGS]; - u8 oldmask[AB8500_NUM_IRQ_REGS]; + u8 *mask; + u8 *oldmask; + int mask_size; + const int *irq_reg_offset; }; struct regulator_reg_init; @@ -197,7 +276,52 @@ struct ab8500_platform_data { struct ab8500_gpio_platform_data *gpio; }; -extern int __devinit ab8500_init(struct ab8500 *ab8500); +extern int __devinit ab8500_init(struct ab8500 *ab8500, + enum ab8500_version version); extern int __devexit ab8500_exit(struct ab8500 *ab8500); +static inline int is_ab8500(struct ab8500 *ab) +{ + return ab->version == AB8500_VERSION_AB8500; +} + +static inline int is_ab8505(struct ab8500 *ab) +{ + return ab->version == AB8500_VERSION_AB8505; +} + +static inline int is_ab9540(struct ab8500 *ab) +{ + return ab->version == AB8500_VERSION_AB9540; +} + +static inline int is_ab8540(struct ab8500 *ab) +{ + return ab->version == AB8500_VERSION_AB8540; +} + +/* exclude also ab8505, ab9540... */ +static inline int is_ab8500_1p0_or_earlier(struct ab8500 *ab) +{ + return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P0)); +} + +/* exclude also ab8505, ab9540... */ +static inline int is_ab8500_1p1_or_earlier(struct ab8500 *ab) +{ + return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P1)); +} + +/* exclude also ab8505, ab9540... */ +static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab) +{ + return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0)); +} + +/* exclude also ab8505, ab9540... */ +static inline int is_ab8500_2p0(struct ab8500 *ab) +{ + return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0)); +} + #endif /* MFD_AB8500_H */ diff --git a/include/linux/mfd/anatop.h b/include/linux/mfd/anatop.h new file mode 100644 index 00000000000..22c1007d3ec --- /dev/null +++ b/include/linux/mfd/anatop.h @@ -0,0 +1,40 @@ +/* + * anatop.h - Anatop MFD driver + * + * Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> + * Copyright (C) 2012 Linaro + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __LINUX_MFD_ANATOP_H +#define __LINUX_MFD_ANATOP_H + +#include <linux/spinlock.h> + +/** + * anatop - MFD data + * @ioreg: ioremap register + * @reglock: spinlock for register read/write + */ +struct anatop { + void *ioreg; + spinlock_t reglock; +}; + +extern u32 anatop_get_bits(struct anatop *, u32, int, int); +extern void anatop_set_bits(struct anatop *, u32, int, int, u32); + +#endif /* __LINUX_MFD_ANATOP_H */ diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h index 5702d1be13b..7ffbd6e9e7f 100644 --- a/include/linux/mfd/da9052/da9052.h +++ b/include/linux/mfd/da9052/da9052.h @@ -76,8 +76,6 @@ enum da9052_chip_id { struct da9052_pdata; struct da9052 { - struct mutex io_lock; - struct device *dev; struct regmap *regmap; diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h index 60d27f7bfc1..b3a43b1263f 100644 --- a/include/linux/mfd/db8500-prcmu.h +++ b/include/linux/mfd/db8500-prcmu.h @@ -11,6 +11,24 @@ #define __MFD_DB8500_PRCMU_H #include <linux/interrupt.h> +#include <linux/bitops.h> + +/* + * Registers + */ +#define DB8500_PRCM_GPIOCR 0x138 +#define DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0 BIT(0) +#define DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD BIT(9) +#define DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 BIT(11) +#define DB8500_PRCM_GPIOCR_SPI2_SELECT BIT(23) + +#define DB8500_PRCM_LINE_VALUE 0x170 +#define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0 BIT(3) + +#define DB8500_PRCM_DSI_SW_RESET 0x324 +#define DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0) +#define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1) +#define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2) /* This portion previously known as <mach/prcmu-fw-defs_v1.h> */ @@ -421,40 +439,22 @@ enum auto_enable { /* End of file previously known as prcmu-fw-defs_v1.h */ /** - * enum hw_acc_dev - enum for hw accelerators - * @HW_ACC_SVAMMDSP: for SVAMMDSP - * @HW_ACC_SVAPIPE: for SVAPIPE - * @HW_ACC_SIAMMDSP: for SIAMMDSP - * @HW_ACC_SIAPIPE: for SIAPIPE - * @HW_ACC_SGA: for SGA - * @HW_ACC_B2R2: for B2R2 - * @HW_ACC_MCDE: for MCDE - * @HW_ACC_ESRAM1: for ESRAM1 - * @HW_ACC_ESRAM2: for ESRAM2 - * @HW_ACC_ESRAM3: for ESRAM3 - * @HW_ACC_ESRAM4: for ESRAM4 - * @NUM_HW_ACC: number of hardware accelerators - * - * Different hw accelerators which can be turned ON/ - * OFF or put into retention (MMDSPs and ESRAMs). - * Used with EPOD API. + * enum prcmu_power_status - results from set_power_state + * @PRCMU_SLEEP_OK: Sleep went ok + * @PRCMU_DEEP_SLEEP_OK: DeepSleep went ok + * @PRCMU_IDLE_OK: Idle went ok + * @PRCMU_DEEPIDLE_OK: DeepIdle went ok + * @PRCMU_PRCMU2ARMPENDINGIT_ER: Pending interrupt detected + * @PRCMU_ARMPENDINGIT_ER: Pending interrupt detected * - * NOTE! Deprecated, to be removed when all users switched over to use the - * regulator API. */ -enum hw_acc_dev { - HW_ACC_SVAMMDSP, - HW_ACC_SVAPIPE, - HW_ACC_SIAMMDSP, - HW_ACC_SIAPIPE, - HW_ACC_SGA, - HW_ACC_B2R2, - HW_ACC_MCDE, - HW_ACC_ESRAM1, - HW_ACC_ESRAM2, - HW_ACC_ESRAM3, - HW_ACC_ESRAM4, - NUM_HW_ACC +enum prcmu_power_status { + PRCMU_SLEEP_OK = 0xf3, + PRCMU_DEEP_SLEEP_OK = 0xf6, + PRCMU_IDLE_OK = 0xf0, + PRCMU_DEEPIDLE_OK = 0xe3, + PRCMU_PRCMU2ARMPENDINGIT_ER = 0x91, + PRCMU_ARMPENDINGIT_ER = 0x93, }; /* @@ -493,6 +493,20 @@ struct prcmu_auto_pm_config { u8 sva_policy; }; +#define PRCMU_FW_PROJECT_U8500 2 +#define PRCMU_FW_PROJECT_U9500 4 +#define PRCMU_FW_PROJECT_U8500_C2 7 +#define PRCMU_FW_PROJECT_U9500_C2 11 +#define PRCMU_FW_PROJECT_U8520 13 +#define PRCMU_FW_PROJECT_U8420 14 + +struct prcmu_fw_version { + u8 project; + u8 api_version; + u8 func_version; + u8 errata; +}; + #ifdef CONFIG_MFD_DB8500_PRCMU void db8500_prcmu_early_init(void); @@ -500,42 +514,41 @@ int prcmu_set_rc_a2p(enum romcode_write); enum romcode_read prcmu_get_rc_p2a(void); enum ap_pwrst prcmu_get_xp70_current_state(void); bool prcmu_has_arm_maxopp(void); -bool prcmu_is_u8400(void); -int prcmu_set_ape_opp(u8 opp); -int prcmu_get_ape_opp(void); +struct prcmu_fw_version *prcmu_get_fw_version(void); int prcmu_request_ape_opp_100_voltage(bool enable); int prcmu_release_usb_wakeup_state(void); -int prcmu_set_ddr_opp(u8 opp); -int prcmu_get_ddr_opp(void); -/* NOTE! Use regulator framework instead */ -int prcmu_set_hwacc(u16 hw_acc_dev, u8 state); void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, struct prcmu_auto_pm_config *idle); bool prcmu_is_auto_pm_enabled(void); int prcmu_config_clkout(u8 clkout, u8 source, u8 div); int prcmu_set_clock_divider(u8 clock, u8 divider); -int prcmu_config_hotdog(u8 threshold); -int prcmu_config_hotmon(u8 low, u8 high); -int prcmu_start_temp_sense(u16 cycles32k); -int prcmu_stop_temp_sense(void); +int db8500_prcmu_config_hotdog(u8 threshold); +int db8500_prcmu_config_hotmon(u8 low, u8 high); +int db8500_prcmu_start_temp_sense(u16 cycles32k); +int db8500_prcmu_stop_temp_sense(void); int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); void prcmu_ac_wake_req(void); void prcmu_ac_sleep_req(void); -void prcmu_modem_reset(void); -void prcmu_enable_spi2(void); -void prcmu_disable_spi2(void); +void db8500_prcmu_modem_reset(void); -int prcmu_config_a9wdog(u8 num, bool sleep_auto_off); -int prcmu_enable_a9wdog(u8 id); -int prcmu_disable_a9wdog(u8 id); -int prcmu_kick_a9wdog(u8 id); -int prcmu_load_a9wdog(u8 id, u32 val); +int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off); +int db8500_prcmu_enable_a9wdog(u8 id); +int db8500_prcmu_disable_a9wdog(u8 id); +int db8500_prcmu_kick_a9wdog(u8 id); +int db8500_prcmu_load_a9wdog(u8 id, u32 val); void db8500_prcmu_system_reset(u16 reset_code); int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll); +u8 db8500_prcmu_get_power_state_result(void); +int db8500_prcmu_gic_decouple(void); +int db8500_prcmu_gic_recouple(void); +int db8500_prcmu_copy_gic_settings(void); +bool db8500_prcmu_gic_pending_irq(void); +bool db8500_prcmu_pending_irq(void); +bool db8500_prcmu_is_cpu_in_wfi(int cpu); void db8500_prcmu_enable_wakeups(u32 wakeups); int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state); int db8500_prcmu_request_clock(u8 clock, bool enable); @@ -549,6 +562,14 @@ u16 db8500_prcmu_get_reset_code(void); bool db8500_prcmu_is_ac_wake_requested(void); int db8500_prcmu_set_arm_opp(u8 opp); int db8500_prcmu_get_arm_opp(void); +int db8500_prcmu_set_ape_opp(u8 opp); +int db8500_prcmu_get_ape_opp(void); +int db8500_prcmu_set_ddr_opp(u8 opp); +int db8500_prcmu_get_ddr_opp(void); + +u32 db8500_prcmu_read(unsigned int reg); +void db8500_prcmu_write(unsigned int reg, u32 value); +void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value); #else /* !CONFIG_MFD_DB8500_PRCMU */ @@ -574,17 +595,17 @@ static inline bool prcmu_has_arm_maxopp(void) return false; } -static inline bool prcmu_is_u8400(void) +static inline struct prcmu_fw_version *prcmu_get_fw_version(void) { - return false; + return NULL; } -static inline int prcmu_set_ape_opp(u8 opp) +static inline int db8500_prcmu_set_ape_opp(u8 opp) { return 0; } -static inline int prcmu_get_ape_opp(void) +static inline int db8500_prcmu_get_ape_opp(void) { return APE_100_OPP; } @@ -599,21 +620,16 @@ static inline int prcmu_release_usb_wakeup_state(void) return 0; } -static inline int prcmu_set_ddr_opp(u8 opp) +static inline int db8500_prcmu_set_ddr_opp(u8 opp) { return 0; } -static inline int prcmu_get_ddr_opp(void) +static inline int db8500_prcmu_get_ddr_opp(void) { return DDR_100_OPP; } -static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state) -{ - return 0; -} - static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, struct prcmu_auto_pm_config *idle) { @@ -634,22 +650,22 @@ static inline int prcmu_set_clock_divider(u8 clock, u8 divider) return 0; } -static inline int prcmu_config_hotdog(u8 threshold) +static inline int db8500_prcmu_config_hotdog(u8 threshold) { return 0; } -static inline int prcmu_config_hotmon(u8 low, u8 high) +static inline int db8500_prcmu_config_hotmon(u8 low, u8 high) { return 0; } -static inline int prcmu_start_temp_sense(u16 cycles32k) +static inline int db8500_prcmu_start_temp_sense(u16 cycles32k) { return 0; } -static inline int prcmu_stop_temp_sense(void) +static inline int db8500_prcmu_stop_temp_sense(void) { return 0; } @@ -668,22 +684,17 @@ static inline void prcmu_ac_wake_req(void) {} static inline void prcmu_ac_sleep_req(void) {} -static inline void prcmu_modem_reset(void) {} +static inline void db8500_prcmu_modem_reset(void) {} -static inline int prcmu_enable_spi2(void) -{ - return 0; -} +static inline void db8500_prcmu_system_reset(u16 reset_code) {} -static inline int prcmu_disable_spi2(void) +static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, + bool keep_ap_pll) { return 0; } -static inline void db8500_prcmu_system_reset(u16 reset_code) {} - -static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, - bool keep_ap_pll) +static inline u8 db8500_prcmu_get_power_state_result(void) { return 0; } @@ -729,27 +740,27 @@ static inline u16 db8500_prcmu_get_reset_code(void) return 0; } -static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) +static inline int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off) { return 0; } -static inline int prcmu_enable_a9wdog(u8 id) +static inline int db8500_prcmu_enable_a9wdog(u8 id) { return 0; } -static inline int prcmu_disable_a9wdog(u8 id) +static inline int db8500_prcmu_disable_a9wdog(u8 id) { return 0; } -static inline int prcmu_kick_a9wdog(u8 id) +static inline int db8500_prcmu_kick_a9wdog(u8 id) { return 0; } -static inline int prcmu_load_a9wdog(u8 id, u32 val) +static inline int db8500_prcmu_load_a9wdog(u8 id, u32 val) { return 0; } @@ -769,6 +780,16 @@ static inline int db8500_prcmu_get_arm_opp(void) return 0; } +static inline u32 db8500_prcmu_read(unsigned int reg) +{ + return 0; +} + +static inline void db8500_prcmu_write(unsigned int reg, u32 value) {} + +static inline void db8500_prcmu_write_masked(unsigned int reg, u32 mask, + u32 value) {} + #endif /* !CONFIG_MFD_DB8500_PRCMU */ #endif /* __MFD_DB8500_PRCMU_H */ diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h index bac942f959c..d7674eb7305 100644 --- a/include/linux/mfd/dbx500-prcmu.h +++ b/include/linux/mfd/dbx500-prcmu.h @@ -10,7 +10,7 @@ #include <linux/interrupt.h> #include <linux/notifier.h> -#include <asm/mach-types.h> +#include <linux/err.h> /* PRCMU Wakeup defines */ enum prcmu_wakeup_index { @@ -80,6 +80,29 @@ enum prcmu_wakeup_index { #define EPOD_STATE_ON_CLK_OFF 0x03 #define EPOD_STATE_ON 0x04 +/* DB5500 CLKOUT IDs */ +enum { + DB5500_CLKOUT0 = 0, + DB5500_CLKOUT1, +}; + +/* DB5500 CLKOUTx sources */ +enum { + DB5500_CLKOUT_REF_CLK_SEL0, + DB5500_CLKOUT_RTC_CLK0_SEL0, + DB5500_CLKOUT_ULP_CLK_SEL0, + DB5500_CLKOUT_STATIC0, + DB5500_CLKOUT_REFCLK, + DB5500_CLKOUT_ULPCLK, + DB5500_CLKOUT_ARMCLK, + DB5500_CLKOUT_SYSACC0CLK, + DB5500_CLKOUT_SOC0PLLCLK, + DB5500_CLKOUT_SOC1PLLCLK, + DB5500_CLKOUT_DDRPLLCLK, + DB5500_CLKOUT_TVCLK, + DB5500_CLKOUT_IRDACLK, +}; + /* * CLKOUT sources */ @@ -111,6 +134,7 @@ enum prcmu_clock { PRCMU_MSP1CLK, PRCMU_I2CCLK, PRCMU_SDMMCCLK, + PRCMU_SPARE1CLK, PRCMU_SLIMCLK, PRCMU_PER1CLK, PRCMU_PER2CLK, @@ -139,12 +163,20 @@ enum prcmu_clock { PRCMU_IRRCCLK, PRCMU_SIACLK, PRCMU_SVACLK, + PRCMU_ACLK, PRCMU_NUM_REG_CLOCKS, PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS, + PRCMU_CDCLK, PRCMU_TIMCLK, PRCMU_PLLSOC0, PRCMU_PLLSOC1, PRCMU_PLLDDR, + PRCMU_PLLDSI, + PRCMU_DSI0CLK, + PRCMU_DSI1CLK, + PRCMU_DSI0ESCCLK, + PRCMU_DSI1ESCCLK, + PRCMU_DSI2ESCCLK, }; /** @@ -153,12 +185,14 @@ enum prcmu_clock { * @APE_NO_CHANGE: The APE operating point is unchanged * @APE_100_OPP: The new APE operating point is ape100opp * @APE_50_OPP: 50% + * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%. */ enum ape_opp { APE_OPP_INIT = 0x00, APE_NO_CHANGE = 0x01, APE_100_OPP = 0x02, - APE_50_OPP = 0x03 + APE_50_OPP = 0x03, + APE_50_PARTLY_25_OPP = 0xFF, }; /** @@ -218,9 +252,11 @@ enum ddr_pwrst { #if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500) +#include <mach/id.h> + static inline void __init prcmu_early_init(void) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return db5500_prcmu_early_init(); else return db8500_prcmu_early_init(); @@ -229,7 +265,7 @@ static inline void __init prcmu_early_init(void) static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return db5500_prcmu_set_power_state(state, keep_ulp_clk, keep_ap_pll); else @@ -237,9 +273,65 @@ static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, keep_ap_pll); } +static inline u8 prcmu_get_power_state_result(void) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_get_power_state_result(); +} + +static inline int prcmu_gic_decouple(void) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_gic_decouple(); +} + +static inline int prcmu_gic_recouple(void) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_gic_recouple(); +} + +static inline bool prcmu_gic_pending_irq(void) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_gic_pending_irq(); +} + +static inline bool prcmu_is_cpu_in_wfi(int cpu) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_is_cpu_in_wfi(cpu); +} + +static inline int prcmu_copy_gic_settings(void) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_copy_gic_settings(); +} + +static inline bool prcmu_pending_irq(void) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_pending_irq(); +} + static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return -EINVAL; else return db8500_prcmu_set_epod(epod_id, epod_state); @@ -247,7 +339,7 @@ static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) static inline void prcmu_enable_wakeups(u32 wakeups) { - if (machine_is_u5500()) + if (cpu_is_u5500()) db5500_prcmu_enable_wakeups(wakeups); else db8500_prcmu_enable_wakeups(wakeups); @@ -260,7 +352,7 @@ static inline void prcmu_disable_wakeups(void) static inline void prcmu_config_abb_event_readout(u32 abb_events) { - if (machine_is_u5500()) + if (cpu_is_u5500()) db5500_prcmu_config_abb_event_readout(abb_events); else db8500_prcmu_config_abb_event_readout(abb_events); @@ -268,7 +360,7 @@ static inline void prcmu_config_abb_event_readout(u32 abb_events) static inline void prcmu_get_abb_event_buffer(void __iomem **buf) { - if (machine_is_u5500()) + if (cpu_is_u5500()) db5500_prcmu_get_abb_event_buffer(buf); else db8500_prcmu_get_abb_event_buffer(buf); @@ -276,25 +368,40 @@ static inline void prcmu_get_abb_event_buffer(void __iomem **buf) int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); +int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size); int prcmu_config_clkout(u8 clkout, u8 source, u8 div); static inline int prcmu_request_clock(u8 clock, bool enable) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return db5500_prcmu_request_clock(clock, enable); else return db8500_prcmu_request_clock(clock, enable); } -int prcmu_set_ape_opp(u8 opp); -int prcmu_get_ape_opp(void); -int prcmu_set_ddr_opp(u8 opp); -int prcmu_get_ddr_opp(void); +unsigned long prcmu_clock_rate(u8 clock); +long prcmu_round_clock_rate(u8 clock, unsigned long rate); +int prcmu_set_clock_rate(u8 clock, unsigned long rate); + +static inline int prcmu_set_ddr_opp(u8 opp) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_set_ddr_opp(opp); +} +static inline int prcmu_get_ddr_opp(void) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_get_ddr_opp(); +} static inline int prcmu_set_arm_opp(u8 opp) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return -EINVAL; else return db8500_prcmu_set_arm_opp(opp); @@ -302,15 +409,31 @@ static inline int prcmu_set_arm_opp(u8 opp) static inline int prcmu_get_arm_opp(void) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return -EINVAL; else return db8500_prcmu_get_arm_opp(); } +static inline int prcmu_set_ape_opp(u8 opp) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_set_ape_opp(opp); +} + +static inline int prcmu_get_ape_opp(void) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_get_ape_opp(); +} + static inline void prcmu_system_reset(u16 reset_code) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return db5500_prcmu_system_reset(reset_code); else return db8500_prcmu_system_reset(reset_code); @@ -318,7 +441,7 @@ static inline void prcmu_system_reset(u16 reset_code) static inline u16 prcmu_get_reset_code(void) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return db5500_prcmu_get_reset_code(); else return db8500_prcmu_get_reset_code(); @@ -326,10 +449,17 @@ static inline u16 prcmu_get_reset_code(void) void prcmu_ac_wake_req(void); void prcmu_ac_sleep_req(void); -void prcmu_modem_reset(void); +static inline void prcmu_modem_reset(void) +{ + if (cpu_is_u5500()) + return; + else + return db8500_prcmu_modem_reset(); +} + static inline bool prcmu_is_ac_wake_requested(void) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return db5500_prcmu_is_ac_wake_requested(); else return db8500_prcmu_is_ac_wake_requested(); @@ -337,7 +467,7 @@ static inline bool prcmu_is_ac_wake_requested(void) static inline int prcmu_set_display_clocks(void) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return db5500_prcmu_set_display_clocks(); else return db8500_prcmu_set_display_clocks(); @@ -345,7 +475,7 @@ static inline int prcmu_set_display_clocks(void) static inline int prcmu_disable_dsipll(void) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return db5500_prcmu_disable_dsipll(); else return db8500_prcmu_disable_dsipll(); @@ -353,7 +483,7 @@ static inline int prcmu_disable_dsipll(void) static inline int prcmu_enable_dsipll(void) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return db5500_prcmu_enable_dsipll(); else return db8500_prcmu_enable_dsipll(); @@ -361,11 +491,107 @@ static inline int prcmu_enable_dsipll(void) static inline int prcmu_config_esram0_deep_sleep(u8 state) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return -EINVAL; else return db8500_prcmu_config_esram0_deep_sleep(state); } + +static inline int prcmu_config_hotdog(u8 threshold) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_config_hotdog(threshold); +} + +static inline int prcmu_config_hotmon(u8 low, u8 high) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_config_hotmon(low, high); +} + +static inline int prcmu_start_temp_sense(u16 cycles32k) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_start_temp_sense(cycles32k); +} + +static inline int prcmu_stop_temp_sense(void) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_stop_temp_sense(); +} + +static inline u32 prcmu_read(unsigned int reg) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_read(reg); +} + +static inline void prcmu_write(unsigned int reg, u32 value) +{ + if (cpu_is_u5500()) + return; + else + db8500_prcmu_write(reg, value); +} + +static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) +{ + if (cpu_is_u5500()) + return; + else + db8500_prcmu_write_masked(reg, mask, value); +} + +static inline int prcmu_enable_a9wdog(u8 id) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_enable_a9wdog(id); +} + +static inline int prcmu_disable_a9wdog(u8 id) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_disable_a9wdog(id); +} + +static inline int prcmu_kick_a9wdog(u8 id) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_kick_a9wdog(id); +} + +static inline int prcmu_load_a9wdog(u8 id, u32 timeout) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_load_a9wdog(id, timeout); +} + +static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_config_a9wdog(num, sleep_auto_off); +} #else static inline void __init prcmu_early_init(void) {} @@ -395,6 +621,12 @@ static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) return -ENOSYS; } +static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, + u8 size) +{ + return -ENOSYS; +} + static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div) { return 0; @@ -405,6 +637,21 @@ static inline int prcmu_request_clock(u8 clock, bool enable) return 0; } +static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate) +{ + return 0; +} + +static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate) +{ + return 0; +} + +static inline unsigned long prcmu_clock_rate(u8 clock) +{ + return 0; +} + static inline int prcmu_set_ape_opp(u8 opp) { return 0; @@ -480,14 +727,133 @@ static inline void prcmu_get_abb_event_buffer(void __iomem **buf) *buf = NULL; } +static inline int prcmu_config_hotdog(u8 threshold) +{ + return 0; +} + +static inline int prcmu_config_hotmon(u8 low, u8 high) +{ + return 0; +} + +static inline int prcmu_start_temp_sense(u16 cycles32k) +{ + return 0; +} + +static inline int prcmu_stop_temp_sense(void) +{ + return 0; +} + +static inline u32 prcmu_read(unsigned int reg) +{ + return 0; +} + +static inline void prcmu_write(unsigned int reg, u32 value) {} + +static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {} + +#endif + +static inline void prcmu_set(unsigned int reg, u32 bits) +{ + prcmu_write_masked(reg, bits, bits); +} + +static inline void prcmu_clear(unsigned int reg, u32 bits) +{ + prcmu_write_masked(reg, bits, 0); +} + +#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500) + +/** + * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1. + */ +static inline void prcmu_enable_spi2(void) +{ + if (cpu_is_u8500()) + prcmu_set(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT); +} + +/** + * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1. + */ +static inline void prcmu_disable_spi2(void) +{ + if (cpu_is_u8500()) + prcmu_clear(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT); +} + +/** + * prcmu_enable_stm_mod_uart - Enables pin muxing for STMMOD + * and UARTMOD on OtherAlternateC3. + */ +static inline void prcmu_enable_stm_mod_uart(void) +{ + if (cpu_is_u8500()) { + prcmu_set(DB8500_PRCM_GPIOCR, + (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 | + DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0)); + } +} + +/** + * prcmu_disable_stm_mod_uart - Disables pin muxing for STMMOD + * and UARTMOD on OtherAlternateC3. + */ +static inline void prcmu_disable_stm_mod_uart(void) +{ + if (cpu_is_u8500()) { + prcmu_clear(DB8500_PRCM_GPIOCR, + (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 | + DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0)); + } +} + +/** + * prcmu_enable_stm_ape - Enables pin muxing for STM APE on OtherAlternateC1. + */ +static inline void prcmu_enable_stm_ape(void) +{ + if (cpu_is_u8500()) { + prcmu_set(DB8500_PRCM_GPIOCR, + DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD); + } +} + +/** + * prcmu_disable_stm_ape - Disables pin muxing for STM APE on OtherAlternateC1. + */ +static inline void prcmu_disable_stm_ape(void) +{ + if (cpu_is_u8500()) { + prcmu_clear(DB8500_PRCM_GPIOCR, + DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD); + } +} + +#else + +static inline void prcmu_enable_spi2(void) {} +static inline void prcmu_disable_spi2(void) {} +static inline void prcmu_enable_stm_mod_uart(void) {} +static inline void prcmu_disable_stm_mod_uart(void) {} +static inline void prcmu_enable_stm_ape(void) {} +static inline void prcmu_disable_stm_ape(void) {} + #endif /* PRCMU QoS APE OPP class */ #define PRCMU_QOS_APE_OPP 1 #define PRCMU_QOS_DDR_OPP 2 +#define PRCMU_QOS_ARM_OPP 3 #define PRCMU_QOS_DEFAULT_VALUE -1 -#ifdef CONFIG_UX500_PRCMU_QOS_POWER +#ifdef CONFIG_DBX500_PRCMU_QOS_POWER unsigned long prcmu_qos_get_cpufreq_opp_delay(void); void prcmu_qos_set_cpufreq_opp_delay(unsigned long); diff --git a/include/linux/mfd/mc13xxx.h b/include/linux/mfd/mc13xxx.h index b86ee45c8b0..10e038bac8d 100644 --- a/include/linux/mfd/mc13xxx.h +++ b/include/linux/mfd/mc13xxx.h @@ -38,7 +38,8 @@ int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq); int mc13xxx_get_flags(struct mc13xxx *mc13xxx); int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, - unsigned int mode, unsigned int channel, unsigned int *sample); + unsigned int mode, unsigned int channel, + u8 ato, bool atox, unsigned int *sample); #define MC13XXX_IRQ_ADCDONE 0 #define MC13XXX_IRQ_ADCBISDONE 1 @@ -157,6 +158,18 @@ struct mc13xxx_buttons_platform_data { unsigned short b3on_key; }; +struct mc13xxx_ts_platform_data { + /* Delay between Touchscreen polarization and ADC Conversion. + * Given in clock ticks of a 32 kHz clock which gives a granularity of + * about 30.5ms */ + u8 ato; + +#define MC13783_TS_ATO_FIRST false +#define MC13783_TS_ATO_EACH true + /* Use the ATO delay only for the first conversion or for each one */ + bool atox; +}; + struct mc13xxx_platform_data { #define MC13XXX_USE_TOUCHSCREEN (1 << 0) #define MC13XXX_USE_CODEC (1 << 1) @@ -167,6 +180,7 @@ struct mc13xxx_platform_data { struct mc13xxx_regulator_platform_data regulators; struct mc13xxx_leds_platform_data *leds; struct mc13xxx_buttons_platform_data *buttons; + struct mc13xxx_ts_platform_data touch; }; #define MC13XXX_ADC_MODE_TS 1 diff --git a/include/linux/mfd/rc5t583.h b/include/linux/mfd/rc5t583.h new file mode 100644 index 00000000000..a2c61609d21 --- /dev/null +++ b/include/linux/mfd/rc5t583.h @@ -0,0 +1,295 @@ +/* + * Core driver interface to access RICOH_RC5T583 power management chip. + * + * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. + * Author: Laxman dewangan <ldewangan@nvidia.com> + * + * Based on code + * Copyright (C) 2011 RICOH COMPANY,LTD + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + */ + +#ifndef __LINUX_MFD_RC5T583_H +#define __LINUX_MFD_RC5T583_H + +#include <linux/mutex.h> +#include <linux/types.h> + +#define RC5T583_MAX_REGS 0xF8 + +/* Maximum number of main interrupts */ +#define MAX_MAIN_INTERRUPT 5 +#define RC5T583_MAX_GPEDGE_REG 2 +#define RC5T583_MAX_INTERRUPT_MASK_REGS 9 + +/* Interrupt enable register */ +#define RC5T583_INT_EN_SYS1 0x19 +#define RC5T583_INT_EN_SYS2 0x1D +#define RC5T583_INT_EN_DCDC 0x41 +#define RC5T583_INT_EN_RTC 0xED +#define RC5T583_INT_EN_ADC1 0x90 +#define RC5T583_INT_EN_ADC2 0x91 +#define RC5T583_INT_EN_ADC3 0x92 + +/* Interrupt status registers (monitor regs in Ricoh)*/ +#define RC5T583_INTC_INTPOL 0xAD +#define RC5T583_INTC_INTEN 0xAE +#define RC5T583_INTC_INTMON 0xAF + +#define RC5T583_INT_MON_GRP 0xAF +#define RC5T583_INT_MON_SYS1 0x1B +#define RC5T583_INT_MON_SYS2 0x1F +#define RC5T583_INT_MON_DCDC 0x43 +#define RC5T583_INT_MON_RTC 0xEE + +/* Interrupt clearing registers */ +#define RC5T583_INT_IR_SYS1 0x1A +#define RC5T583_INT_IR_SYS2 0x1E +#define RC5T583_INT_IR_DCDC 0x42 +#define RC5T583_INT_IR_RTC 0xEE +#define RC5T583_INT_IR_ADCL 0x94 +#define RC5T583_INT_IR_ADCH 0x95 +#define RC5T583_INT_IR_ADCEND 0x96 +#define RC5T583_INT_IR_GPIOR 0xA9 +#define RC5T583_INT_IR_GPIOF 0xAA + +/* Sleep sequence registers */ +#define RC5T583_SLPSEQ1 0x21 +#define RC5T583_SLPSEQ2 0x22 +#define RC5T583_SLPSEQ3 0x23 +#define RC5T583_SLPSEQ4 0x24 +#define RC5T583_SLPSEQ5 0x25 +#define RC5T583_SLPSEQ6 0x26 +#define RC5T583_SLPSEQ7 0x27 +#define RC5T583_SLPSEQ8 0x28 +#define RC5T583_SLPSEQ9 0x29 +#define RC5T583_SLPSEQ10 0x2A +#define RC5T583_SLPSEQ11 0x2B + +/* Regulator registers */ +#define RC5T583_REG_DC0CTL 0x30 +#define RC5T583_REG_DC0DAC 0x31 +#define RC5T583_REG_DC0LATCTL 0x32 +#define RC5T583_REG_SR0CTL 0x33 + +#define RC5T583_REG_DC1CTL 0x34 +#define RC5T583_REG_DC1DAC 0x35 +#define RC5T583_REG_DC1LATCTL 0x36 +#define RC5T583_REG_SR1CTL 0x37 + +#define RC5T583_REG_DC2CTL 0x38 +#define RC5T583_REG_DC2DAC 0x39 +#define RC5T583_REG_DC2LATCTL 0x3A +#define RC5T583_REG_SR2CTL 0x3B + +#define RC5T583_REG_DC3CTL 0x3C +#define RC5T583_REG_DC3DAC 0x3D +#define RC5T583_REG_DC3LATCTL 0x3E +#define RC5T583_REG_SR3CTL 0x3F + + +#define RC5T583_REG_LDOEN1 0x50 +#define RC5T583_REG_LDOEN2 0x51 +#define RC5T583_REG_LDODIS1 0x52 +#define RC5T583_REG_LDODIS2 0x53 + +#define RC5T583_REG_LDO0DAC 0x54 +#define RC5T583_REG_LDO1DAC 0x55 +#define RC5T583_REG_LDO2DAC 0x56 +#define RC5T583_REG_LDO3DAC 0x57 +#define RC5T583_REG_LDO4DAC 0x58 +#define RC5T583_REG_LDO5DAC 0x59 +#define RC5T583_REG_LDO6DAC 0x5A +#define RC5T583_REG_LDO7DAC 0x5B +#define RC5T583_REG_LDO8DAC 0x5C +#define RC5T583_REG_LDO9DAC 0x5D + +#define RC5T583_REG_DC0DAC_DS 0x60 +#define RC5T583_REG_DC1DAC_DS 0x61 +#define RC5T583_REG_DC2DAC_DS 0x62 +#define RC5T583_REG_DC3DAC_DS 0x63 + +#define RC5T583_REG_LDO0DAC_DS 0x64 +#define RC5T583_REG_LDO1DAC_DS 0x65 +#define RC5T583_REG_LDO2DAC_DS 0x66 +#define RC5T583_REG_LDO3DAC_DS 0x67 +#define RC5T583_REG_LDO4DAC_DS 0x68 +#define RC5T583_REG_LDO5DAC_DS 0x69 +#define RC5T583_REG_LDO6DAC_DS 0x6A +#define RC5T583_REG_LDO7DAC_DS 0x6B +#define RC5T583_REG_LDO8DAC_DS 0x6C +#define RC5T583_REG_LDO9DAC_DS 0x6D + +/* GPIO register base address */ +#define RC5T583_GPIO_IOSEL 0xA0 +#define RC5T583_GPIO_PDEN 0xA1 +#define RC5T583_GPIO_IOOUT 0xA2 +#define RC5T583_GPIO_PGSEL 0xA3 +#define RC5T583_GPIO_GPINV 0xA4 +#define RC5T583_GPIO_GPDEB 0xA5 +#define RC5T583_GPIO_GPEDGE1 0xA6 +#define RC5T583_GPIO_GPEDGE2 0xA7 +#define RC5T583_GPIO_EN_INT 0xA8 +#define RC5T583_GPIO_MON_IOIN 0xAB +#define RC5T583_GPIO_GPOFUNC 0xAC + +/* RICOH_RC5T583 IRQ definitions */ +enum { + RC5T583_IRQ_ONKEY, + RC5T583_IRQ_ACOK, + RC5T583_IRQ_LIDOPEN, + RC5T583_IRQ_PREOT, + RC5T583_IRQ_CLKSTP, + RC5T583_IRQ_ONKEY_OFF, + RC5T583_IRQ_WD, + RC5T583_IRQ_EN_PWRREQ1, + RC5T583_IRQ_EN_PWRREQ2, + RC5T583_IRQ_PRE_VINDET, + + RC5T583_IRQ_DC0LIM, + RC5T583_IRQ_DC1LIM, + RC5T583_IRQ_DC2LIM, + RC5T583_IRQ_DC3LIM, + + RC5T583_IRQ_CTC, + RC5T583_IRQ_YALE, + RC5T583_IRQ_DALE, + RC5T583_IRQ_WALE, + + RC5T583_IRQ_AIN1L, + RC5T583_IRQ_AIN2L, + RC5T583_IRQ_AIN3L, + RC5T583_IRQ_VBATL, + RC5T583_IRQ_VIN3L, + RC5T583_IRQ_VIN8L, + RC5T583_IRQ_AIN1H, + RC5T583_IRQ_AIN2H, + RC5T583_IRQ_AIN3H, + RC5T583_IRQ_VBATH, + RC5T583_IRQ_VIN3H, + RC5T583_IRQ_VIN8H, + RC5T583_IRQ_ADCEND, + + RC5T583_IRQ_GPIO0, + RC5T583_IRQ_GPIO1, + RC5T583_IRQ_GPIO2, + RC5T583_IRQ_GPIO3, + RC5T583_IRQ_GPIO4, + RC5T583_IRQ_GPIO5, + RC5T583_IRQ_GPIO6, + RC5T583_IRQ_GPIO7, + + /* Should be last entry */ + RC5T583_MAX_IRQS, +}; + +/* Ricoh583 gpio definitions */ +enum { + RC5T583_GPIO0, + RC5T583_GPIO1, + RC5T583_GPIO2, + RC5T583_GPIO3, + RC5T583_GPIO4, + RC5T583_GPIO5, + RC5T583_GPIO6, + RC5T583_GPIO7, + + /* Should be last entry */ + RC5T583_MAX_GPIO, +}; + +enum { + RC5T583_DS_NONE, + RC5T583_DS_DC0, + RC5T583_DS_DC1, + RC5T583_DS_DC2, + RC5T583_DS_DC3, + RC5T583_DS_LDO0, + RC5T583_DS_LDO1, + RC5T583_DS_LDO2, + RC5T583_DS_LDO3, + RC5T583_DS_LDO4, + RC5T583_DS_LDO5, + RC5T583_DS_LDO6, + RC5T583_DS_LDO7, + RC5T583_DS_LDO8, + RC5T583_DS_LDO9, + RC5T583_DS_PSO0, + RC5T583_DS_PSO1, + RC5T583_DS_PSO2, + RC5T583_DS_PSO3, + RC5T583_DS_PSO4, + RC5T583_DS_PSO5, + RC5T583_DS_PSO6, + RC5T583_DS_PSO7, + + /* Should be last entry */ + RC5T583_DS_MAX, +}; + +/* + * Ricoh pmic RC5T583 supports sleep through two external controls. + * The output of gpios and regulator can be enable/disable through + * this external signals. + */ +enum { + RC5T583_EXT_PWRREQ1_CONTROL = 0x1, + RC5T583_EXT_PWRREQ2_CONTROL = 0x2, +}; + +struct rc5t583 { + struct device *dev; + struct regmap *regmap; + int chip_irq; + int irq_base; + struct mutex irq_lock; + unsigned long group_irq_en[MAX_MAIN_INTERRUPT]; + + /* For main interrupt bits in INTC */ + uint8_t intc_inten_reg; + + /* For group interrupt bits and address */ + uint8_t irq_en_reg[RC5T583_MAX_INTERRUPT_MASK_REGS]; + + /* For gpio edge */ + uint8_t gpedge_reg[RC5T583_MAX_GPEDGE_REG]; +}; + +/* + * rc5t583_platform_data: Platform data for ricoh rc5t583 pmu. + * The board specific data is provided through this structure. + * @irq_base: Irq base number on which this device registers their interrupts. + * @enable_shutdown: Enable shutdown through the input pin "shutdown". + */ + +struct rc5t583_platform_data { + int irq_base; + bool enable_shutdown; +}; + +int rc5t583_write(struct device *dev, u8 reg, uint8_t val); +int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val); +int rc5t583_set_bits(struct device *dev, unsigned int reg, + unsigned int bit_mask); +int rc5t583_clear_bits(struct device *dev, unsigned int reg, + unsigned int bit_mask); +int rc5t583_update(struct device *dev, unsigned int reg, + unsigned int val, unsigned int mask); +int rc5t583_ext_power_req_config(struct device *dev, int deepsleep_id, + int ext_pwr_req, int deepsleep_slot_nr); +int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base); +int rc5t583_irq_exit(struct rc5t583 *rc5t583); + +#endif diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h index 8c54de674b4..8516fd1eaab 100644 --- a/include/linux/mfd/stmpe.h +++ b/include/linux/mfd/stmpe.h @@ -28,6 +28,7 @@ enum stmpe_partnum { STMPE1601, STMPE2401, STMPE2403, + STMPE_NBR_PARTS }; /* diff --git a/include/linux/mfd/tps65090.h b/include/linux/mfd/tps65090.h new file mode 100644 index 00000000000..38e31c55adb --- /dev/null +++ b/include/linux/mfd/tps65090.h @@ -0,0 +1,46 @@ +/* + * Core driver interface for TI TPS65090 PMIC family + * + * Copyright (C) 2012 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ + +#ifndef __LINUX_MFD_TPS65090_H +#define __LINUX_MFD_TPS65090_H + +struct tps65090_subdev_info { + int id; + const char *name; + void *platform_data; +}; + +struct tps65090_platform_data { + int irq_base; + int num_subdevs; + struct tps65090_subdev_info *subdevs; +}; + +/* + * NOTE: the functions below are not intended for use outside + * of the TPS65090 sub-device drivers + */ +extern int tps65090_write(struct device *dev, int reg, uint8_t val); +extern int tps65090_read(struct device *dev, int reg, uint8_t *val); +extern int tps65090_set_bits(struct device *dev, int reg, uint8_t bit_num); +extern int tps65090_clr_bits(struct device *dev, int reg, uint8_t bit_num); + +#endif /*__LINUX_MFD_TPS65090_H */ diff --git a/include/linux/mfd/tps65217.h b/include/linux/mfd/tps65217.h new file mode 100644 index 00000000000..e030ef9a64e --- /dev/null +++ b/include/linux/mfd/tps65217.h @@ -0,0 +1,283 @@ +/* + * linux/mfd/tps65217.h + * + * Functions to access TPS65217 power management chip. + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __LINUX_MFD_TPS65217_H +#define __LINUX_MFD_TPS65217_H + +#include <linux/i2c.h> +#include <linux/regulator/driver.h> +#include <linux/regulator/machine.h> + +/* I2C ID for TPS65217 part */ +#define TPS65217_I2C_ID 0x24 + +/* All register addresses */ +#define TPS65217_REG_CHIPID 0X00 +#define TPS65217_REG_PPATH 0X01 +#define TPS65217_REG_INT 0X02 +#define TPS65217_REG_CHGCONFIG0 0X03 +#define TPS65217_REG_CHGCONFIG1 0X04 +#define TPS65217_REG_CHGCONFIG2 0X05 +#define TPS65217_REG_CHGCONFIG3 0X06 +#define TPS65217_REG_WLEDCTRL1 0X07 +#define TPS65217_REG_WLEDCTRL2 0X08 +#define TPS65217_REG_MUXCTRL 0X09 +#define TPS65217_REG_STATUS 0X0A +#define TPS65217_REG_PASSWORD 0X0B +#define TPS65217_REG_PGOOD 0X0C +#define TPS65217_REG_DEFPG 0X0D +#define TPS65217_REG_DEFDCDC1 0X0E +#define TPS65217_REG_DEFDCDC2 0X0F +#define TPS65217_REG_DEFDCDC3 0X10 +#define TPS65217_REG_DEFSLEW 0X11 +#define TPS65217_REG_DEFLDO1 0X12 +#define TPS65217_REG_DEFLDO2 0X13 +#define TPS65217_REG_DEFLS1 0X14 +#define TPS65217_REG_DEFLS2 0X15 +#define TPS65217_REG_ENABLE 0X16 +#define TPS65217_REG_DEFUVLO 0X18 +#define TPS65217_REG_SEQ1 0X19 +#define TPS65217_REG_SEQ2 0X1A +#define TPS65217_REG_SEQ3 0X1B +#define TPS65217_REG_SEQ4 0X1C +#define TPS65217_REG_SEQ5 0X1D +#define TPS65217_REG_SEQ6 0X1E + +/* Register field definitions */ +#define TPS65217_CHIPID_CHIP_MASK 0xF0 +#define TPS65217_CHIPID_REV_MASK 0x0F + +#define TPS65217_PPATH_ACSINK_ENABLE BIT(7) +#define TPS65217_PPATH_USBSINK_ENABLE BIT(6) +#define TPS65217_PPATH_AC_PW_ENABLE BIT(5) +#define TPS65217_PPATH_USB_PW_ENABLE BIT(4) +#define TPS65217_PPATH_AC_CURRENT_MASK 0x0C +#define TPS65217_PPATH_USB_CURRENT_MASK 0x03 + +#define TPS65217_INT_PBM BIT(6) +#define TPS65217_INT_ACM BIT(5) +#define TPS65217_INT_USBM BIT(4) +#define TPS65217_INT_PBI BIT(2) +#define TPS65217_INT_ACI BIT(1) +#define TPS65217_INT_USBI BIT(0) + +#define TPS65217_CHGCONFIG0_TREG BIT(7) +#define TPS65217_CHGCONFIG0_DPPM BIT(6) +#define TPS65217_CHGCONFIG0_TSUSP BIT(5) +#define TPS65217_CHGCONFIG0_TERMI BIT(4) +#define TPS65217_CHGCONFIG0_ACTIVE BIT(3) +#define TPS65217_CHGCONFIG0_CHGTOUT BIT(2) +#define TPS65217_CHGCONFIG0_PCHGTOUT BIT(1) +#define TPS65217_CHGCONFIG0_BATTEMP BIT(0) + +#define TPS65217_CHGCONFIG1_TMR_MASK 0xC0 +#define TPS65217_CHGCONFIG1_TMR_ENABLE BIT(5) +#define TPS65217_CHGCONFIG1_NTC_TYPE BIT(4) +#define TPS65217_CHGCONFIG1_RESET BIT(3) +#define TPS65217_CHGCONFIG1_TERM BIT(2) +#define TPS65217_CHGCONFIG1_SUSP BIT(1) +#define TPS65217_CHGCONFIG1_CHG_EN BIT(0) + +#define TPS65217_CHGCONFIG2_DYNTMR BIT(7) +#define TPS65217_CHGCONFIG2_VPREGHG BIT(6) +#define TPS65217_CHGCONFIG2_VOREG_MASK 0x30 + +#define TPS65217_CHGCONFIG3_ICHRG_MASK 0xC0 +#define TPS65217_CHGCONFIG3_DPPMTH_MASK 0x30 +#define TPS65217_CHGCONFIG2_PCHRGT BIT(3) +#define TPS65217_CHGCONFIG2_TERMIF 0x06 +#define TPS65217_CHGCONFIG2_TRANGE BIT(0) + +#define TPS65217_WLEDCTRL1_ISINK_ENABLE BIT(3) +#define TPS65217_WLEDCTRL1_ISEL BIT(2) +#define TPS65217_WLEDCTRL1_FDIM_MASK 0x03 + +#define TPS65217_WLEDCTRL2_DUTY_MASK 0x7F + +#define TPS65217_MUXCTRL_MUX_MASK 0x07 + +#define TPS65217_STATUS_OFF BIT(7) +#define TPS65217_STATUS_ACPWR BIT(3) +#define TPS65217_STATUS_USBPWR BIT(2) +#define TPS65217_STATUS_PB BIT(0) + +#define TPS65217_PASSWORD_REGS_UNLOCK 0x7D + +#define TPS65217_PGOOD_LDO3_PG BIT(6) +#define TPS65217_PGOOD_LDO4_PG BIT(5) +#define TPS65217_PGOOD_DC1_PG BIT(4) +#define TPS65217_PGOOD_DC2_PG BIT(3) +#define TPS65217_PGOOD_DC3_PG BIT(2) +#define TPS65217_PGOOD_LDO1_PG BIT(1) +#define TPS65217_PGOOD_LDO2_PG BIT(0) + +#define TPS65217_DEFPG_LDO1PGM BIT(3) +#define TPS65217_DEFPG_LDO2PGM BIT(2) +#define TPS65217_DEFPG_PGDLY_MASK 0x03 + +#define TPS65217_DEFDCDCX_XADJX BIT(7) +#define TPS65217_DEFDCDCX_DCDC_MASK 0x3F + +#define TPS65217_DEFSLEW_GO BIT(7) +#define TPS65217_DEFSLEW_GODSBL BIT(6) +#define TPS65217_DEFSLEW_PFM_EN1 BIT(5) +#define TPS65217_DEFSLEW_PFM_EN2 BIT(4) +#define TPS65217_DEFSLEW_PFM_EN3 BIT(3) +#define TPS65217_DEFSLEW_SLEW_MASK 0x07 + +#define TPS65217_DEFLDO1_LDO1_MASK 0x0F + +#define TPS65217_DEFLDO2_TRACK BIT(6) +#define TPS65217_DEFLDO2_LDO2_MASK 0x3F + +#define TPS65217_DEFLDO3_LDO3_EN BIT(5) +#define TPS65217_DEFLDO3_LDO3_MASK 0x1F + +#define TPS65217_DEFLDO4_LDO4_EN BIT(5) +#define TPS65217_DEFLDO4_LDO4_MASK 0x1F + +#define TPS65217_ENABLE_LS1_EN BIT(6) +#define TPS65217_ENABLE_LS2_EN BIT(5) +#define TPS65217_ENABLE_DC1_EN BIT(4) +#define TPS65217_ENABLE_DC2_EN BIT(3) +#define TPS65217_ENABLE_DC3_EN BIT(2) +#define TPS65217_ENABLE_LDO1_EN BIT(1) +#define TPS65217_ENABLE_LDO2_EN BIT(0) + +#define TPS65217_DEFUVLO_UVLOHYS BIT(2) +#define TPS65217_DEFUVLO_UVLO_MASK 0x03 + +#define TPS65217_SEQ1_DC1_SEQ_MASK 0xF0 +#define TPS65217_SEQ1_DC2_SEQ_MASK 0x0F + +#define TPS65217_SEQ2_DC3_SEQ_MASK 0xF0 +#define TPS65217_SEQ2_LDO1_SEQ_MASK 0x0F + +#define TPS65217_SEQ3_LDO2_SEQ_MASK 0xF0 +#define TPS65217_SEQ3_LDO3_SEQ_MASK 0x0F + +#define TPS65217_SEQ4_LDO4_SEQ_MASK 0xF0 + +#define TPS65217_SEQ5_DLY1_MASK 0xC0 +#define TPS65217_SEQ5_DLY2_MASK 0x30 +#define TPS65217_SEQ5_DLY3_MASK 0x0C +#define TPS65217_SEQ5_DLY4_MASK 0x03 + +#define TPS65217_SEQ6_DLY5_MASK 0xC0 +#define TPS65217_SEQ6_DLY6_MASK 0x30 +#define TPS65217_SEQ6_SEQUP BIT(2) +#define TPS65217_SEQ6_SEQDWN BIT(1) +#define TPS65217_SEQ6_INSTDWN BIT(0) + +#define TPS65217_MAX_REGISTER 0x1E +#define TPS65217_PROTECT_NONE 0 +#define TPS65217_PROTECT_L1 1 +#define TPS65217_PROTECT_L2 2 + + +enum tps65217_regulator_id { + /* DCDC's */ + TPS65217_DCDC_1, + TPS65217_DCDC_2, + TPS65217_DCDC_3, + /* LDOs */ + TPS65217_LDO_1, + TPS65217_LDO_2, + TPS65217_LDO_3, + TPS65217_LDO_4, +}; + +#define TPS65217_MAX_REG_ID TPS65217_LDO_4 + +/* Number of step-down converters available */ +#define TPS65217_NUM_DCDC 3 +/* Number of LDO voltage regulators available */ +#define TPS65217_NUM_LDO 4 +/* Number of total regulators available */ +#define TPS65217_NUM_REGULATOR (TPS65217_NUM_DCDC + TPS65217_NUM_LDO) + +/** + * struct tps65217_board - packages regulator init data + * @tps65217_regulator_data: regulator initialization values + * + * Board data may be used to initialize regulator. + */ +struct tps65217_board { + struct regulator_init_data *tps65217_init_data; +}; + +/** + * struct tps_info - packages regulator constraints + * @name: Voltage regulator name + * @min_uV: minimum micro volts + * @max_uV: minimum micro volts + * @vsel_to_uv: Function pointer to get voltage from selector + * @uv_to_vsel: Function pointer to get selector from voltage + * @table: Table for non-uniform voltage step-size + * @table_len: Length of the voltage table + * @enable_mask: Regulator enable mask bits + * @set_vout_reg: Regulator output voltage set register + * @set_vout_mask: Regulator output voltage set mask + * + * This data is used to check the regualtor voltage limits while setting. + */ +struct tps_info { + const char *name; + int min_uV; + int max_uV; + int (*vsel_to_uv)(unsigned int vsel); + int (*uv_to_vsel)(int uV, unsigned int *vsel); + const int *table; + unsigned int table_len; + unsigned int enable_mask; + unsigned int set_vout_reg; + unsigned int set_vout_mask; +}; + +/** + * struct tps65217 - tps65217 sub-driver chip access routines + * + * Device data may be used to access the TPS65217 chip + */ + +struct tps65217 { + struct device *dev; + struct tps65217_board *pdata; + struct regulator_desc desc[TPS65217_NUM_REGULATOR]; + struct regulator_dev *rdev[TPS65217_NUM_REGULATOR]; + struct tps_info *info[TPS65217_NUM_REGULATOR]; + struct regmap *regmap; + + /* Client devices */ + struct platform_device *regulator_pdev[TPS65217_NUM_REGULATOR]; +}; + +static inline struct tps65217 *dev_to_tps65217(struct device *dev) +{ + return dev_get_drvdata(dev); +} + +int tps65217_reg_read(struct tps65217 *tps, unsigned int reg, + unsigned int *val); +int tps65217_reg_write(struct tps65217 *tps, unsigned int reg, + unsigned int val, unsigned int level); +int tps65217_set_bits(struct tps65217 *tps, unsigned int reg, + unsigned int mask, unsigned int val, unsigned int level); +int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg, + unsigned int mask, unsigned int level); + +#endif /* __LINUX_MFD_TPS65217_H */ diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h index 76700b5eee9..1c6c2860d1a 100644 --- a/include/linux/mfd/tps65910.h +++ b/include/linux/mfd/tps65910.h @@ -17,6 +17,8 @@ #ifndef __LINUX_MFD_TPS65910_H #define __LINUX_MFD_TPS65910_H +#include <linux/gpio.h> + /* TPS chip id list */ #define TPS65910 0 #define TPS65911 1 @@ -657,6 +659,8 @@ /*Register GPIO (0x80) register.RegisterDescription */ +#define GPIO_SLEEP_MASK 0x80 +#define GPIO_SLEEP_SHIFT 7 #define GPIO_DEB_MASK 0x10 #define GPIO_DEB_SHIFT 4 #define GPIO_PUEN_MASK 0x08 @@ -740,6 +744,11 @@ #define TPS65910_GPIO_STS BIT(1) #define TPS65910_GPIO_SET BIT(0) +/* Max number of TPS65910/11 GPIOs */ +#define TPS65910_NUM_GPIO 6 +#define TPS65911_NUM_GPIO 9 +#define TPS6591X_MAX_NUM_GPIO 9 + /* Regulator Index Definitions */ #define TPS65910_REG_VRTC 0 #define TPS65910_REG_VIO 1 @@ -785,6 +794,7 @@ struct tps65910_board { int irq_base; int vmbch_threshold; int vmbch2_threshold; + bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO]; unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS]; struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS]; }; @@ -796,6 +806,7 @@ struct tps65910_board { struct tps65910 { struct device *dev; struct i2c_client *i2c_client; + struct regmap *regmap; struct mutex io_mutex; unsigned int id; int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest); diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h index dc3e0501168..893267bb622 100644 --- a/include/linux/mfd/wm8994/pdata.h +++ b/include/linux/mfd/wm8994/pdata.h @@ -22,7 +22,6 @@ struct wm8994_ldo_pdata { /** GPIOs to enable regulator, 0 or less if not available */ int enable; - const char *supply; const struct regulator_init_data *init_data; }; diff --git a/include/linux/mm.h b/include/linux/mm.h index 63006818426..d8738a464b9 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -1258,6 +1258,8 @@ static inline void pgtable_page_dtor(struct page *page) extern void free_area_init(unsigned long * zones_size); extern void free_area_init_node(int nid, unsigned long * zones_size, unsigned long zone_start_pfn, unsigned long *zholes_size); +extern void free_initmem(void); + #ifdef CONFIG_HAVE_MEMBLOCK_NODE_MAP /* * With CONFIG_HAVE_MEMBLOCK_NODE_MAP set, an architecture may initialise its diff --git a/include/linux/module.h b/include/linux/module.h index 4598bf03e98..fbcafe2ee13 100644 --- a/include/linux/module.h +++ b/include/linux/module.h @@ -21,8 +21,6 @@ #include <linux/percpu.h> #include <asm/module.h> -#include <trace/events/module.h> - /* Not Yet Implemented */ #define MODULE_SUPPORTED_DEVICE(name) @@ -452,33 +450,11 @@ void symbol_put_addr(void *addr); /* Sometimes we know we already have a refcount, and it's easier not to handle the error case (which only happens with rmmod --wait). */ -static inline void __module_get(struct module *module) -{ - if (module) { - preempt_disable(); - __this_cpu_inc(module->refptr->incs); - trace_module_get(module, _THIS_IP_); - preempt_enable(); - } -} - -static inline int try_module_get(struct module *module) -{ - int ret = 1; - - if (module) { - preempt_disable(); +extern void __module_get(struct module *module); - if (likely(module_is_live(module))) { - __this_cpu_inc(module->refptr->incs); - trace_module_get(module, _THIS_IP_); - } else - ret = 0; - - preempt_enable(); - } - return ret; -} +/* This is the Right Way to get a module: if it fails, it's being removed, + * so pretend it's not there. */ +extern bool try_module_get(struct module *module); extern void module_put(struct module *module); diff --git a/include/linux/moduleparam.h b/include/linux/moduleparam.h index c47f4d60db0..ea36486378d 100644 --- a/include/linux/moduleparam.h +++ b/include/linux/moduleparam.h @@ -47,14 +47,11 @@ struct kernel_param_ops { void (*free)(void *arg); }; -/* Flag bits for kernel_param.flags */ -#define KPARAM_ISBOOL 2 - struct kernel_param { const char *name; const struct kernel_param_ops *ops; u16 perm; - u16 flags; + s16 level; union { void *arg; const struct kparam_string *str; @@ -131,8 +128,40 @@ struct kparam_array * The ops can have NULL set or get functions. */ #define module_param_cb(name, ops, arg, perm) \ - __module_param_call(MODULE_PARAM_PREFIX, \ - name, ops, arg, __same_type((arg), bool *), perm) + __module_param_call(MODULE_PARAM_PREFIX, name, ops, arg, perm, 0) + +/** + * <level>_param_cb - general callback for a module/cmdline parameter + * to be evaluated before certain initcall level + * @name: a valid C identifier which is the parameter name. + * @ops: the set & get operations for this parameter. + * @perm: visibility in sysfs. + * + * The ops can have NULL set or get functions. + */ +#define __level_param_cb(name, ops, arg, perm, level) \ + __module_param_call(MODULE_PARAM_PREFIX, name, ops, arg, perm, level) + +#define core_param_cb(name, ops, arg, perm) \ + __level_param_cb(name, ops, arg, perm, 1) + +#define postcore_param_cb(name, ops, arg, perm) \ + __level_param_cb(name, ops, arg, perm, 2) + +#define arch_param_cb(name, ops, arg, perm) \ + __level_param_cb(name, ops, arg, perm, 3) + +#define subsys_param_cb(name, ops, arg, perm) \ + __level_param_cb(name, ops, arg, perm, 4) + +#define fs_param_cb(name, ops, arg, perm) \ + __level_param_cb(name, ops, arg, perm, 5) + +#define device_param_cb(name, ops, arg, perm) \ + __level_param_cb(name, ops, arg, perm, 6) + +#define late_param_cb(name, ops, arg, perm) \ + __level_param_cb(name, ops, arg, perm, 7) /* On alpha, ia64 and ppc64 relocations to global data cannot go into read-only sections (which is part of respective UNIX ABI on these @@ -146,7 +175,7 @@ struct kparam_array /* This is the fundamental function for registering boot/module parameters. */ -#define __module_param_call(prefix, name, ops, arg, isbool, perm) \ +#define __module_param_call(prefix, name, ops, arg, perm, level) \ /* Default value instead of permissions? */ \ static int __param_perm_check_##name __attribute__((unused)) = \ BUILD_BUG_ON_ZERO((perm) < 0 || (perm) > 0777 || ((perm) & 2)) \ @@ -155,8 +184,7 @@ struct kparam_array static struct kernel_param __moduleparam_const __param_##name \ __used \ __attribute__ ((unused,__section__ ("__param"),aligned(sizeof(void *)))) \ - = { __param_str_##name, ops, perm, isbool ? KPARAM_ISBOOL : 0, \ - { arg } } + = { __param_str_##name, ops, perm, level, { arg } } /* Obsolete - use module_param_cb() */ #define module_param_call(name, set, get, arg, perm) \ @@ -164,8 +192,7 @@ struct kparam_array { (void *)set, (void *)get }; \ __module_param_call(MODULE_PARAM_PREFIX, \ name, &__param_ops_##name, arg, \ - __same_type(arg, bool *), \ - (perm) + sizeof(__check_old_set_param(set))*0) + (perm) + sizeof(__check_old_set_param(set))*0, 0) /* We don't get oldget: it's often a new-style param_get_uint, etc. */ static inline int @@ -245,8 +272,7 @@ static inline void __kernel_param_unlock(void) */ #define core_param(name, var, type, perm) \ param_check_##type(name, &(var)); \ - __module_param_call("", name, ¶m_ops_##type, \ - &var, __same_type(var, bool), perm) + __module_param_call("", name, ¶m_ops_##type, &var, perm, 0) #endif /* !MODULE */ /** @@ -264,7 +290,7 @@ static inline void __kernel_param_unlock(void) = { len, string }; \ __module_param_call(MODULE_PARAM_PREFIX, name, \ ¶m_ops_string, \ - .str = &__param_string_##name, 0, perm); \ + .str = &__param_string_##name, perm, 0); \ __MODULE_PARM_TYPE(name, "string") /** @@ -292,6 +318,8 @@ extern int parse_args(const char *name, char *args, const struct kernel_param *params, unsigned num, + s16 level_min, + s16 level_max, int (*unknown)(char *param, char *val)); /* Called by module remove. */ @@ -403,7 +431,7 @@ extern int param_set_bint(const char *val, const struct kernel_param *kp); __module_param_call(MODULE_PARAM_PREFIX, name, \ ¶m_array_ops, \ .arr = &__param_arr_##name, \ - __same_type(array[0], bool), perm); \ + perm, 0); \ __MODULE_PARM_TYPE(name, "array of " #type) extern struct kernel_param_ops param_array_ops; diff --git a/include/linux/mtd/map.h b/include/linux/mtd/map.h index 94e924e2ecd..3595a0236b0 100644 --- a/include/linux/mtd/map.h +++ b/include/linux/mtd/map.h @@ -29,8 +29,8 @@ #include <linux/kernel.h> #include <asm/unaligned.h> -#include <asm/system.h> #include <asm/io.h> +#include <asm/barrier.h> #ifdef CONFIG_MTD_MAP_BANK_WIDTH_1 #define map_bankwidth(map) 1 diff --git a/include/linux/of.h b/include/linux/of.h index d46a18ffbeb..fa7fb1d9745 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -58,9 +58,6 @@ struct device_node { struct kref kref; unsigned long _flags; void *data; -#if defined(CONFIG_EEH) - struct eeh_dev *edev; -#endif #if defined(CONFIG_SPARC) char *path_component_name; unsigned int unique_id; @@ -75,13 +72,6 @@ struct of_phandle_args { uint32_t args[MAX_PHANDLE_ARGS]; }; -#if defined(CONFIG_EEH) -static inline struct eeh_dev *of_node_to_eeh_dev(struct device_node *dn) -{ - return dn->edev; -} -#endif - #ifdef CONFIG_OF_DYNAMIC extern struct device_node *of_node_get(struct device_node *node); extern void of_node_put(struct device_node *node); @@ -361,6 +351,22 @@ static inline int of_machine_is_compatible(const char *compat) #define of_match_node(_matches, _node) NULL #endif /* CONFIG_OF */ +/** + * of_property_read_bool - Findfrom a property + * @np: device node from which the property value is to be read. + * @propname: name of the property to be searched. + * + * Search for a property in a device node. + * Returns true if the property exist false otherwise. + */ +static inline bool of_property_read_bool(const struct device_node *np, + const char *propname) +{ + struct property *prop = of_find_property(np, propname, NULL); + + return prop ? true : false; +} + static inline int of_property_read_u32(const struct device_node *np, const char *propname, u32 *out_value) diff --git a/include/linux/of_gpio.h b/include/linux/of_gpio.h index b254052a49d..81733d12cbe 100644 --- a/include/linux/of_gpio.h +++ b/include/linux/of_gpio.h @@ -50,7 +50,8 @@ static inline struct of_mm_gpio_chip *to_of_mm_gpio_chip(struct gpio_chip *gc) extern int of_get_named_gpio_flags(struct device_node *np, const char *list_name, int index, enum of_gpio_flags *flags); -extern unsigned int of_gpio_count(struct device_node *np); +extern unsigned int of_gpio_named_count(struct device_node *np, + const char* propname); extern int of_mm_gpiochip_add(struct device_node *np, struct of_mm_gpio_chip *mm_gc); @@ -71,7 +72,8 @@ static inline int of_get_named_gpio_flags(struct device_node *np, return -ENOSYS; } -static inline unsigned int of_gpio_count(struct device_node *np) +static inline unsigned int of_gpio_named_count(struct device_node *np, + const char* propname) { return 0; } @@ -89,6 +91,27 @@ static inline void of_gpiochip_remove(struct gpio_chip *gc) { } #endif /* CONFIG_OF_GPIO */ /** + * of_gpio_count - Count GPIOs for a device + * @np: device node to count GPIOs for + * + * The function returns the count of GPIOs specified for a node. + * + * Note that the empty GPIO specifiers counts too. For example, + * + * gpios = <0 + * &pio1 1 2 + * 0 + * &pio2 3 4>; + * + * defines four GPIOs (so this function will return 4), two of which + * are not specified. + */ +static inline unsigned int of_gpio_count(struct device_node *np) +{ + return of_gpio_named_count(np, "gpios"); +} + +/** * of_get_gpio_flags() - Get a GPIO number and flags to use with GPIO API * @np: device node to get GPIO from * @index: index of the GPIO diff --git a/include/linux/of_mtd.h b/include/linux/of_mtd.h new file mode 100644 index 00000000000..bae1b6094c6 --- /dev/null +++ b/include/linux/of_mtd.h @@ -0,0 +1,19 @@ +/* + * Copyright 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * OF helpers for mtd. + * + * This file is released under the GPLv2 + */ + +#ifndef __LINUX_OF_MTD_H +#define __LINUX_OF_NET_H + +#ifdef CONFIG_OF_MTD +#include <linux/of.h> +extern const int of_get_nand_ecc_mode(struct device_node *np); +int of_get_nand_bus_width(struct device_node *np); +bool of_get_nand_on_flash_bbt(struct device_node *np); +#endif + +#endif /* __LINUX_OF_MTD_H */ diff --git a/include/linux/parport.h b/include/linux/parport.h index 38a423ed3c0..106c2ca9440 100644 --- a/include/linux/parport.h +++ b/include/linux/parport.h @@ -100,7 +100,6 @@ typedef enum { #include <linux/wait.h> #include <linux/irqreturn.h> #include <linux/semaphore.h> -#include <asm/system.h> #include <asm/ptrace.h> /* Define this later. */ diff --git a/include/linux/platform_data/atmel.h b/include/linux/platform_data/atmel.h new file mode 100644 index 00000000000..d056263545b --- /dev/null +++ b/include/linux/platform_data/atmel.h @@ -0,0 +1,27 @@ +/* + * atmel platform data + * + * GPL v2 Only + */ + +#ifndef __ATMEL_NAND_H__ +#define __ATMEL_NAND_H__ + +#include <linux/mtd/nand.h> + + /* NAND / SmartMedia */ +struct atmel_nand_data { + int enable_pin; /* chip enable */ + int det_pin; /* card detect */ + int rdy_pin; /* ready/busy */ + u8 rdy_pin_active_low; /* rdy_pin value is inverted */ + u8 ale; /* address line number connected to ALE */ + u8 cle; /* address line number connected to CLE */ + u8 bus_width_16; /* buswidth is 16 bit */ + u8 ecc_mode; /* ecc mode */ + u8 on_flash_bbt; /* bbt on flash */ + struct mtd_partition *parts; + unsigned int num_parts; +}; + +#endif /* __ATMEL_NAND_H__ */ diff --git a/include/linux/regulator/ab8500.h b/include/linux/regulator/ab8500.h index 76579f964a2..7bd73bbdfd1 100644 --- a/include/linux/regulator/ab8500.h +++ b/include/linux/regulator/ab8500.h @@ -26,7 +26,26 @@ enum ab8500_regulator_id { AB8500_NUM_REGULATORS, }; -/* AB8500 register initialization */ +/* AB9450 regulators */ +enum ab9540_regulator_id { + AB9540_LDO_AUX1, + AB9540_LDO_AUX2, + AB9540_LDO_AUX3, + AB9540_LDO_AUX4, + AB9540_LDO_INTCORE, + AB9540_LDO_TVOUT, + AB9540_LDO_USB, + AB9540_LDO_AUDIO, + AB9540_LDO_ANAMIC1, + AB9540_LDO_ANAMIC2, + AB9540_LDO_DMIC, + AB9540_LDO_ANA, + AB9540_SYSCLKREQ_2, + AB9540_SYSCLKREQ_4, + AB9540_NUM_REGULATORS, +}; + +/* AB8500 and AB9540 register initialization */ struct ab8500_regulator_reg_init { int id; u8 value; @@ -71,4 +90,53 @@ enum ab8500_regulator_reg { AB8500_NUM_REGULATOR_REGISTERS, }; + +/* AB9540 registers */ +enum ab9540_regulator_reg { + AB9540_REGUREQUESTCTRL1, + AB9540_REGUREQUESTCTRL2, + AB9540_REGUREQUESTCTRL3, + AB9540_REGUREQUESTCTRL4, + AB9540_REGUSYSCLKREQ1HPVALID1, + AB9540_REGUSYSCLKREQ1HPVALID2, + AB9540_REGUHWHPREQ1VALID1, + AB9540_REGUHWHPREQ1VALID2, + AB9540_REGUHWHPREQ2VALID1, + AB9540_REGUHWHPREQ2VALID2, + AB9540_REGUSWHPREQVALID1, + AB9540_REGUSWHPREQVALID2, + AB9540_REGUSYSCLKREQVALID1, + AB9540_REGUSYSCLKREQVALID2, + AB9540_REGUVAUX4REQVALID, + AB9540_REGUMISC1, + AB9540_VAUDIOSUPPLY, + AB9540_REGUCTRL1VAMIC, + AB9540_VSMPS1REGU, + AB9540_VSMPS2REGU, + AB9540_VSMPS3REGU, /* NOTE! PRCMU register */ + AB9540_VPLLVANAREGU, + AB9540_EXTSUPPLYREGU, + AB9540_VAUX12REGU, + AB9540_VRF1VAUX3REGU, + AB9540_VSMPS1SEL1, + AB9540_VSMPS1SEL2, + AB9540_VSMPS1SEL3, + AB9540_VSMPS2SEL1, + AB9540_VSMPS2SEL2, + AB9540_VSMPS2SEL3, + AB9540_VSMPS3SEL1, /* NOTE! PRCMU register */ + AB9540_VSMPS3SEL2, /* NOTE! PRCMU register */ + AB9540_VAUX1SEL, + AB9540_VAUX2SEL, + AB9540_VRF1VAUX3SEL, + AB9540_REGUCTRL2SPARE, + AB9540_VAUX4REQCTRL, + AB9540_VAUX4REGU, + AB9540_VAUX4SEL, + AB9540_REGUCTRLDISCH, + AB9540_REGUCTRLDISCH2, + AB9540_REGUCTRLDISCH3, + AB9540_NUM_REGULATOR_REGISTERS, +}; + #endif diff --git a/include/linux/rwsem.h b/include/linux/rwsem.h index 63d40655439..54bd7cd7ecb 100644 --- a/include/linux/rwsem.h +++ b/include/linux/rwsem.h @@ -14,7 +14,6 @@ #include <linux/list.h> #include <linux/spinlock.h> -#include <asm/system.h> #include <linux/atomic.h> struct rw_semaphore; diff --git a/include/linux/sched.h b/include/linux/sched.h index 0c3854b0d4b..81a173c0897 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -63,7 +63,6 @@ struct sched_param { #include <linux/nodemask.h> #include <linux/mm_types.h> -#include <asm/system.h> #include <asm/page.h> #include <asm/ptrace.h> #include <asm/cputime.h> diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index 192250bd49f..33370271b8b 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -501,7 +501,6 @@ struct sk_buff { */ #include <linux/slab.h> -#include <asm/system.h> /* * skb might have a dst pointer attached, refcounted or not. diff --git a/include/linux/slab.h b/include/linux/slab.h index 573c809c33d..a595dce6b0c 100644 --- a/include/linux/slab.h +++ b/include/linux/slab.h @@ -190,7 +190,7 @@ size_t ksize(const void *); #endif /** - * kcalloc - allocate memory for an array. The memory is set to zero. + * kmalloc_array - allocate memory for an array. * @n: number of elements. * @size: element size. * @flags: the type of memory to allocate. @@ -240,11 +240,22 @@ size_t ksize(const void *); * for general use, and so are not documented here. For a full list of * potential flags, always refer to linux/gfp.h. */ -static inline void *kcalloc(size_t n, size_t size, gfp_t flags) +static inline void *kmalloc_array(size_t n, size_t size, gfp_t flags) { if (size != 0 && n > ULONG_MAX / size) return NULL; - return __kmalloc(n * size, flags | __GFP_ZERO); + return __kmalloc(n * size, flags); +} + +/** + * kcalloc - allocate memory for an array. The memory is set to zero. + * @n: number of elements. + * @size: element size. + * @flags: the type of memory to allocate (see kmalloc). + */ +static inline void *kcalloc(size_t n, size_t size, gfp_t flags) +{ + return kmalloc_array(n, size, flags | __GFP_ZERO); } #if !defined(CONFIG_NUMA) && !defined(CONFIG_SLOB) diff --git a/include/linux/slub_def.h b/include/linux/slub_def.h index ca122b36aec..c2f8c8bc56e 100644 --- a/include/linux/slub_def.h +++ b/include/linux/slub_def.h @@ -22,7 +22,7 @@ enum stat_item { FREE_FROZEN, /* Freeing to frozen slab */ FREE_ADD_PARTIAL, /* Freeing moves slab to partial list */ FREE_REMOVE_PARTIAL, /* Freeing removes last object */ - ALLOC_FROM_PARTIAL, /* Cpu slab acquired from partial list */ + ALLOC_FROM_PARTIAL, /* Cpu slab acquired from node partial list */ ALLOC_SLAB, /* Cpu slab acquired from page allocator */ ALLOC_REFILL, /* Refill cpu slab from slab freelist */ ALLOC_NODE_MISMATCH, /* Switching cpu slab */ @@ -38,7 +38,9 @@ enum stat_item { CMPXCHG_DOUBLE_CPU_FAIL,/* Failure of this_cpu_cmpxchg_double */ CMPXCHG_DOUBLE_FAIL, /* Number of times that cmpxchg double did not match */ CPU_PARTIAL_ALLOC, /* Used cpu partial on alloc */ - CPU_PARTIAL_FREE, /* USed cpu partial on free */ + CPU_PARTIAL_FREE, /* Refill cpu partial on free */ + CPU_PARTIAL_NODE, /* Refill cpu partial from node partial */ + CPU_PARTIAL_DRAIN, /* Drain cpu partial to node partial */ NR_SLUB_STAT_ITEMS }; struct kmem_cache_cpu { diff --git a/include/linux/spi/orion_spi.h b/include/linux/spi/orion_spi.h index decf6d8c77b..b4d9fa6f797 100644 --- a/include/linux/spi/orion_spi.h +++ b/include/linux/spi/orion_spi.h @@ -11,7 +11,6 @@ struct orion_spi_info { u32 tclk; /* no <linux/clk.h> support yet */ - u32 enable_clock_fix; }; diff --git a/include/linux/spinlock.h b/include/linux/spinlock.h index 36323908726..7d537ced949 100644 --- a/include/linux/spinlock.h +++ b/include/linux/spinlock.h @@ -55,8 +55,8 @@ #include <linux/kernel.h> #include <linux/stringify.h> #include <linux/bottom_half.h> +#include <asm/barrier.h> -#include <asm/system.h> /* * Must define these before including other files, inline functions need them diff --git a/include/linux/stop_machine.h b/include/linux/stop_machine.h index c170edc3bf5..3b5e910d14c 100644 --- a/include/linux/stop_machine.h +++ b/include/linux/stop_machine.h @@ -5,7 +5,6 @@ #include <linux/cpumask.h> #include <linux/smp.h> #include <linux/list.h> -#include <asm/system.h> /* * stop_cpu[s]() is simplistic per-cpu maximum priority cpu diff --git a/include/linux/tty.h b/include/linux/tty.h index a91ff403b3b..9f47ab540f6 100644 --- a/include/linux/tty.h +++ b/include/linux/tty.h @@ -44,7 +44,6 @@ #include <linux/tty_ldisc.h> #include <linux/mutex.h> -#include <asm/system.h> /* diff --git a/include/linux/wait.h b/include/linux/wait.h index 7d9a9e990ce..1dee81c41ff 100644 --- a/include/linux/wait.h +++ b/include/linux/wait.h @@ -22,7 +22,6 @@ #include <linux/list.h> #include <linux/stddef.h> #include <linux/spinlock.h> -#include <asm/system.h> #include <asm/current.h> typedef struct __wait_queue wait_queue_t; diff --git a/include/linux/watchdog.h b/include/linux/watchdog.h index 43ba5b3ce2a..ac40716b44e 100644 --- a/include/linux/watchdog.h +++ b/include/linux/watchdog.h @@ -66,6 +66,7 @@ struct watchdog_device; * @ping: The routine that sends a keepalive ping to the watchdog device. * @status: The routine that shows the status of the watchdog device. * @set_timeout:The routine for setting the watchdog devices timeout value. + * @get_timeleft:The routine that get's the time that's left before a reset. * @ioctl: The routines that handles extra ioctl calls. * * The watchdog_ops structure contains a list of low-level operations @@ -82,6 +83,7 @@ struct watchdog_ops { int (*ping)(struct watchdog_device *); unsigned int (*status)(struct watchdog_device *); int (*set_timeout)(struct watchdog_device *, unsigned int); + unsigned int (*get_timeleft)(struct watchdog_device *); long (*ioctl)(struct watchdog_device *, unsigned int, unsigned long); }; @@ -127,7 +129,7 @@ struct watchdog_device { #endif /* Use the following function to set the nowayout feature */ -static inline void watchdog_set_nowayout(struct watchdog_device *wdd, int nowayout) +static inline void watchdog_set_nowayout(struct watchdog_device *wdd, bool nowayout) { if (nowayout) set_bit(WDOG_NO_WAY_OUT, &wdd->status); |