diff options
Diffstat (limited to 'include')
36 files changed, 341 insertions, 114 deletions
diff --git a/include/asm-arm/arch-aaec2000/entry-macro.S b/include/asm-arm/arch-aaec2000/entry-macro.S index 1eb3503bd16..83fdf68f6b7 100644 --- a/include/asm-arm/arch-aaec2000/entry-macro.S +++ b/include/asm-arm/arch-aaec2000/entry-macro.S @@ -15,6 +15,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp mov r4, #0xf8000000 add r4, r4, #0x00000500 diff --git a/include/asm-arm/arch-at91/entry-macro.S b/include/asm-arm/arch-at91/entry-macro.S index 76c8cccf73a..cc1d850a078 100644 --- a/include/asm-arm/arch-at91/entry-macro.S +++ b/include/asm-arm/arch-at91/entry-macro.S @@ -16,6 +16,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral ldr \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt) diff --git a/include/asm-arm/arch-at91rm9200/entry-macro.S b/include/asm-arm/arch-at91rm9200/entry-macro.S new file mode 100644 index 00000000000..0e0aadf2a17 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/entry-macro.S @@ -0,0 +1,32 @@ +/* + * include/asm-arm/arch-at91rm9200/entry-macro.S + * + * Copyright (C) 2003-2005 SAN People + * + * Low-level IRQ helper macros for AT91RM9200 platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <asm/hardware.h> +#include <asm/arch/at91_aic.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =(AT91_VA_BASE_SYS) @ base virtual address of SYS peripherals + ldr \irqnr, [\base, #AT91_AIC_IVR] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt) + ldr \irqstat, [\base, #AT91_AIC_ISR] @ read interrupt source number + teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt + streq \tmp, [\base, #AT91_AIC_EOICR] @ not going to be handled further, then ACK it now. + .endm + diff --git a/include/asm-arm/arch-cl7500/entry-macro.S b/include/asm-arm/arch-cl7500/entry-macro.S index c9e5395e510..0cfb89b229d 100644 --- a/include/asm-arm/arch-cl7500/entry-macro.S +++ b/include/asm-arm/arch-cl7500/entry-macro.S @@ -1,3 +1,8 @@ #include <asm/hardware.h> #include <asm/hardware/entry-macro-iomd.S> + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm diff --git a/include/asm-arm/arch-clps711x/entry-macro.S b/include/asm-arm/arch-clps711x/entry-macro.S index de4481dd8ba..cd8c5a0bc7b 100644 --- a/include/asm-arm/arch-clps711x/entry-macro.S +++ b/include/asm-arm/arch-clps711x/entry-macro.S @@ -13,6 +13,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + #if (INTSR2 - INTSR1) != (INTMR2 - INTMR1) #error INTSR stride != INTMR stride #endif diff --git a/include/asm-arm/arch-ebsa110/entry-macro.S b/include/asm-arm/arch-ebsa110/entry-macro.S index b12ca04f998..aa23c5d6c69 100644 --- a/include/asm-arm/arch-ebsa110/entry-macro.S +++ b/include/asm-arm/arch-ebsa110/entry-macro.S @@ -15,6 +15,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, stat, base, tmp mov \base, #IRQ_STAT ldrb \stat, [\base] @ get interrupts diff --git a/include/asm-arm/arch-ebsa285/entry-macro.S b/include/asm-arm/arch-ebsa285/entry-macro.S index ce812d4f4a3..4203dbf1066 100644 --- a/include/asm-arm/arch-ebsa285/entry-macro.S +++ b/include/asm-arm/arch-ebsa285/entry-macro.S @@ -14,6 +14,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .equ dc21285_high, ARMCSR_BASE & 0xff000000 .equ dc21285_low, ARMCSR_BASE & 0x00ffffff diff --git a/include/asm-arm/arch-ep93xx/entry-macro.S b/include/asm-arm/arch-ep93xx/entry-macro.S index 84140a28dfc..241ec221a04 100644 --- a/include/asm-arm/arch-ep93xx/entry-macro.S +++ b/include/asm-arm/arch-ep93xx/entry-macro.S @@ -14,6 +14,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ldr \base, =(EP93XX_AHB_VIRT_BASE) orr \base, \base, #0x000b0000 diff --git a/include/asm-arm/arch-h720x/entry-macro.S b/include/asm-arm/arch-h720x/entry-macro.S index 8f165648e2a..38dd63ae104 100644 --- a/include/asm-arm/arch-h720x/entry-macro.S +++ b/include/asm-arm/arch-h720x/entry-macro.S @@ -11,6 +11,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp #if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202) @ we could use the id register on H7202, but this is not diff --git a/include/asm-arm/arch-imx/entry-macro.S b/include/asm-arm/arch-imx/entry-macro.S index 61bb0bdc1b1..0b84e81031c 100644 --- a/include/asm-arm/arch-imx/entry-macro.S +++ b/include/asm-arm/arch-imx/entry-macro.S @@ -11,6 +11,13 @@ .macro disable_fiq .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + #define AITC_NIVECSR 0x40 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ldr \base, =IO_ADDRESS(IMX_AITC_BASE) diff --git a/include/asm-arm/arch-integrator/entry-macro.S b/include/asm-arm/arch-integrator/entry-macro.S index 69838d04f90..491af1a23de 100644 --- a/include/asm-arm/arch-integrator/entry-macro.S +++ b/include/asm-arm/arch-integrator/entry-macro.S @@ -13,6 +13,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp /* FIXME: should not be using soo many LDRs here */ ldr \base, =IO_ADDRESS(INTEGRATOR_IC_BASE) diff --git a/include/asm-arm/arch-iop13xx/entry-macro.S b/include/asm-arm/arch-iop13xx/entry-macro.S index 94c50283dc5..a624a7870c6 100644 --- a/include/asm-arm/arch-iop13xx/entry-macro.S +++ b/include/asm-arm/arch-iop13xx/entry-macro.S @@ -19,21 +19,27 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + mrc p15, 0, \tmp, c15, c1, 0 + orr \tmp, \tmp, #(1 << 6) + mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access + .endm + /* * Note: a 1-cycle window exists where iintvec will return the value * of iintbase, so we explicitly check for "bad zeros" */ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mrc p15, 0, \tmp, c15, c1, 0 - orr \tmp, \tmp, #(1 << 6) - mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access - mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC cmp \irqnr, #0 mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero adds \irqstat, \irqnr, #1 @ Check for 0xffffffff movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr + .endm - biceq \tmp, \tmp, #(1 << 6) - mcreq p15, 0, \tmp, c15, c1, 0 @ Disable cp6 access if no more interrupts + .macro arch_ret_to_user, tmp1, tmp2 + mrc p15, 0, \tmp1, c15, c1, 0 + ands \tmp2, \tmp1, #(1 << 6) + bicne \tmp1, \tmp1, #(1 << 6) + mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access .endm diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h index a88522a0ff8..d26b755a987 100644 --- a/include/asm-arm/arch-iop13xx/iop13xx.h +++ b/include/asm-arm/arch-iop13xx/iop13xx.h @@ -9,34 +9,6 @@ void iop13xx_init_irq(void); void iop13xx_map_io(void); void iop13xx_platform_init(void); void iop13xx_init_irq(void); -void iop13xx_init_time(unsigned long tickrate); -unsigned long iop13xx_gettimeoffset(void); - -/* handle cp6 access - * to do: handle access in entry-armv5.S and unify with - * the iop3xx implementation - * note: use iop13xx_cp6_enable_irq_save and iop13xx_cp6_irq_restore (irq.h) - * when interrupts are enabled - */ -static inline unsigned long iop13xx_cp6_save(void) -{ - u32 temp, cp_flags; - - asm volatile ( - "mrc p15, 0, %1, c15, c1, 0\n\t" - "orr %0, %1, #(1 << 6)\n\t" - "mcr p15, 0, %0, c15, c1, 0\n\t" - : "=r" (temp), "=r"(cp_flags)); - - return cp_flags; -} - -static inline void iop13xx_cp6_restore(unsigned long cp_flags) -{ - asm volatile ( - "mcr p15, 0, %0, c15, c1, 0\n\t" - : : "r" (cp_flags) ); -} /* CPUID CP6 R0 Page 0 */ static inline int iop13xx_cpu_id(void) @@ -479,14 +451,4 @@ static inline int iop13xx_cpu_id(void) #define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10) #define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) -#define IOP13XX_TMR_TC 0x01 -#define IOP13XX_TMR_EN 0x02 -#define IOP13XX_TMR_RELOAD 0x04 -#define IOP13XX_TMR_PRIVILEGED 0x08 - -#define IOP13XX_TMR_RATIO_1_1 0x00 -#define IOP13XX_TMR_RATIO_4_1 0x10 -#define IOP13XX_TMR_RATIO_8_1 0x20 -#define IOP13XX_TMR_RATIO_16_1 0x30 - #endif /* _IOP13XX_HW_H_ */ diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h index 442e35a4035..5c6fac2a400 100644 --- a/include/asm-arm/arch-iop13xx/irqs.h +++ b/include/asm-arm/arch-iop13xx/irqs.h @@ -3,8 +3,6 @@ #ifndef __ASSEMBLER__ #include <linux/types.h> -#include <asm/system.h> /* local_irq_save */ -#include <asm/arch/iop13xx.h> /* iop13xx_cp6_* */ /* INTPND0 CP6 R0 Page 3 */ @@ -41,21 +39,6 @@ static inline u32 read_intpnd_3(void) asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val)); return val; } - -static inline void -iop13xx_cp6_enable_irq_save(unsigned long *cp_flags, unsigned long *irq_flags) -{ - local_irq_save(*irq_flags); - *cp_flags = iop13xx_cp6_save(); -} - -static inline void -iop13xx_cp6_irq_restore(unsigned long *cp_flags, - unsigned long *irq_flags) -{ - iop13xx_cp6_restore(*cp_flags); - local_irq_restore(*irq_flags); -} #endif #define INTBASE 0 diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h index ee3a62530af..127827058e1 100644 --- a/include/asm-arm/arch-iop13xx/system.h +++ b/include/asm-arm/arch-iop13xx/system.h @@ -48,12 +48,10 @@ static inline void arch_reset(char mode) /* * Reset the internal bus (warning both cores are reset) */ - u32 cp_flags = iop13xx_cp6_save(); write_wdtcr(IOP13XX_WDTCR_EN_ARM); write_wdtcr(IOP13XX_WDTCR_EN); write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); write_wdtcr(0x1000); - iop13xx_cp6_restore(cp_flags); for(;;); } diff --git a/include/asm-arm/arch-iop13xx/time.h b/include/asm-arm/arch-iop13xx/time.h new file mode 100644 index 00000000000..77a837a02de --- /dev/null +++ b/include/asm-arm/arch-iop13xx/time.h @@ -0,0 +1,51 @@ +#ifndef _IOP13XX_TIME_H_ +#define _IOP13XX_TIME_H_ +#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0 + +#define IOP_TMR_EN 0x02 +#define IOP_TMR_RELOAD 0x04 +#define IOP_TMR_PRIVILEGED 0x08 +#define IOP_TMR_RATIO_1_1 0x00 + +void iop_init_time(unsigned long tickrate); +unsigned long iop_gettimeoffset(void); + +static inline void write_tmr0(u32 val) +{ + asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val)); +} + +static inline void write_tmr1(u32 val) +{ + asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val)); +} + +static inline u32 read_tcr0(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val)); + return val; +} + +static inline u32 read_tcr1(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val)); + return val; +} + +static inline void write_trr0(u32 val) +{ + asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val)); +} + +static inline void write_trr1(u32 val) +{ + asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val)); +} + +static inline void write_tisr(u32 val) +{ + asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val)); +} +#endif diff --git a/include/asm-arm/arch-iop32x/entry-macro.S b/include/asm-arm/arch-iop32x/entry-macro.S index 1500cbbd229..207db99dfbd 100644 --- a/include/asm-arm/arch-iop32x/entry-macro.S +++ b/include/asm-arm/arch-iop32x/entry-macro.S @@ -9,13 +9,28 @@ */ #include <asm/arch/iop32x.h> - .macro disable_fiq - .endm + .macro disable_fiq + .endm - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =IOP3XX_REG_ADDR(0x07D8) - ldr \irqstat, [\base] @ Read IINTSRC - cmp \irqstat, #0 - clzne \irqnr, \irqstat - rsbne \irqnr, \irqnr, #31 - .endm + .macro get_irqnr_preamble, base, tmp + mrc p15, 0, \tmp, c15, c1, 0 + orr \tmp, \tmp, #(1 << 6) + mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access + mrc p15, 0, \tmp, c15, c1, 0 + mov \tmp, \tmp + sub pc, pc, #4 @ cp_wait + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC + cmp \irqstat, #0 + clzne \irqnr, \irqstat + rsbne \irqnr, \irqnr, #31 + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + mrc p15, 0, \tmp1, c15, c1, 0 + ands \tmp2, \tmp1, #(1 << 6) + bicne \tmp1, \tmp1, #(1 << 6) + mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access + .endm diff --git a/include/asm-arm/arch-iop32x/time.h b/include/asm-arm/arch-iop32x/time.h new file mode 100644 index 00000000000..0f28c994962 --- /dev/null +++ b/include/asm-arm/arch-iop32x/time.h @@ -0,0 +1,4 @@ +#ifndef _IOP32X_TIME_H_ +#define _IOP32X_TIME_H_ +#define IRQ_IOP_TIMER0 IRQ_IOP32X_TIMER0 +#endif diff --git a/include/asm-arm/arch-iop33x/entry-macro.S b/include/asm-arm/arch-iop33x/entry-macro.S index 92b791702e3..b8e3d449e88 100644 --- a/include/asm-arm/arch-iop33x/entry-macro.S +++ b/include/asm-arm/arch-iop33x/entry-macro.S @@ -9,14 +9,29 @@ */ #include <asm/arch/iop33x.h> - .macro disable_fiq - .endm + .macro disable_fiq + .endm - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =IOP3XX_REG_ADDR(0x07C8) - ldr \irqstat, [\base] @ Read IINTVEC - cmp \irqstat, #0 - ldreq \irqstat, [\base] @ erratum 63 workaround - adds \irqnr, \irqstat, #1 - movne \irqnr, \irqstat, lsr #2 - .endm + .macro get_irqnr_preamble, base, tmp + mrc p15, 0, \tmp, c15, c1, 0 + orr \tmp, \tmp, #(1 << 6) + mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access + mrc p15, 0, \tmp, c15, c1, 0 + mov \tmp, \tmp + sub pc, pc, #4 @ cp_wait + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + mrc p6, 0, \irqstat, c14, c0, 0 @ Read IINTVEC + cmp \irqstat, #0 + mrceq p6, 0, \irqstat, c14, c0, 0 @ erratum 63 workaround + adds \irqnr, \irqstat, #1 + movne \irqnr, \irqstat, lsr #2 + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + mrc p15, 0, \tmp1, c15, c1, 0 + ands \tmp2, \tmp1, #(1 << 6) + bicne \tmp1, \tmp1, #(1 << 6) + mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access + .endm diff --git a/include/asm-arm/arch-iop33x/time.h b/include/asm-arm/arch-iop33x/time.h new file mode 100644 index 00000000000..4ac4d7664f8 --- /dev/null +++ b/include/asm-arm/arch-iop33x/time.h @@ -0,0 +1,4 @@ +#ifndef _IOP33X_TIME_H_ +#define _IOP33X_TIME_H_ +#define IRQ_IOP_TIMER0 IRQ_IOP33X_TIMER0 +#endif diff --git a/include/asm-arm/arch-ixp2000/entry-macro.S b/include/asm-arm/arch-ixp2000/entry-macro.S index 16e1e6124b3..11d512ad594 100644 --- a/include/asm-arm/arch-ixp2000/entry-macro.S +++ b/include/asm-arm/arch-ixp2000/entry-macro.S @@ -12,6 +12,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp mov \irqnr, #0x0 @clear out irqnr as default diff --git a/include/asm-arm/arch-ixp23xx/entry-macro.S b/include/asm-arm/arch-ixp23xx/entry-macro.S index 867761677b5..ec9dd6fc2d0 100644 --- a/include/asm-arm/arch-ixp23xx/entry-macro.S +++ b/include/asm-arm/arch-ixp23xx/entry-macro.S @@ -5,6 +5,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ldr \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET) ldr \irqnr, [\irqnr] @ get interrupt number diff --git a/include/asm-arm/arch-ixp4xx/entry-macro.S b/include/asm-arm/arch-ixp4xx/entry-macro.S index 27e124132e4..dadb568b7ef 100644 --- a/include/asm-arm/arch-ixp4xx/entry-macro.S +++ b/include/asm-arm/arch-ixp4xx/entry-macro.S @@ -12,6 +12,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET) ldr \irqstat, [\irqstat] @ get interrupts diff --git a/include/asm-arm/arch-l7200/entry-macro.S b/include/asm-arm/arch-l7200/entry-macro.S index 8b6342dc4be..63411d3e9df 100644 --- a/include/asm-arm/arch-l7200/entry-macro.S +++ b/include/asm-arm/arch-l7200/entry-macro.S @@ -14,6 +14,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp mov \irqstat, #irq_base_addr @ Virt addr IRQ regs add \irqstat, \irqstat, #0x00001000 @ Status reg diff --git a/include/asm-arm/arch-lh7a40x/entry-macro.S b/include/asm-arm/arch-lh7a40x/entry-macro.S index 9fc7f498812..502700604e0 100644 --- a/include/asm-arm/arch-lh7a40x/entry-macro.S +++ b/include/asm-arm/arch-lh7a40x/entry-macro.S @@ -26,6 +26,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp branch_irq_lh7a400: b 1000f diff --git a/include/asm-arm/arch-netx/entry-macro.S b/include/asm-arm/arch-netx/entry-macro.S index 658df4d60ff..83ad188a084 100644 --- a/include/asm-arm/arch-netx/entry-macro.S +++ b/include/asm-arm/arch-netx/entry-macro.S @@ -23,6 +23,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp mov \base, #io_p2v(0x00100000) add \base, \base, #0x000ff000 diff --git a/include/asm-arm/arch-omap/entry-macro.S b/include/asm-arm/arch-omap/entry-macro.S index 0ffb1185f1a..c90dff4828f 100644 --- a/include/asm-arm/arch-omap/entry-macro.S +++ b/include/asm-arm/arch-omap/entry-macro.S @@ -29,6 +29,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ldr \base, =IO_ADDRESS(OMAP_IH1_BASE) ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET] diff --git a/include/asm-arm/arch-pnx4008/entry-macro.S b/include/asm-arm/arch-pnx4008/entry-macro.S index c1c198e3680..f11731974e5 100644 --- a/include/asm-arm/arch-pnx4008/entry-macro.S +++ b/include/asm-arm/arch-pnx4008/entry-macro.S @@ -28,6 +28,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp /* decode the MIC interrupt numbers */ ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE) diff --git a/include/asm-arm/arch-pxa/entry-macro.S b/include/asm-arm/arch-pxa/entry-macro.S index 4985e33afc1..1d5fbb9b379 100644 --- a/include/asm-arm/arch-pxa/entry-macro.S +++ b/include/asm-arm/arch-pxa/entry-macro.S @@ -13,6 +13,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp #ifdef CONFIG_PXA27x mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S index 1a6eec86bd4..138838d4ad7 100644 --- a/include/asm-arm/arch-realview/entry-macro.S +++ b/include/asm-arm/arch-realview/entry-macro.S @@ -13,6 +13,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + /* * The interrupt numbering scheme is defined in the * interrupt controller spec. To wit: diff --git a/include/asm-arm/arch-rpc/entry-macro.S b/include/asm-arm/arch-rpc/entry-macro.S index c9e5395e510..0cfb89b229d 100644 --- a/include/asm-arm/arch-rpc/entry-macro.S +++ b/include/asm-arm/arch-rpc/entry-macro.S @@ -1,3 +1,8 @@ #include <asm/hardware.h> #include <asm/hardware/entry-macro-iomd.S> + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm diff --git a/include/asm-arm/arch-s3c2410/entry-macro.S b/include/asm-arm/arch-s3c2410/entry-macro.S index 1eb4e6b8d24..bbec0a8ff15 100644 --- a/include/asm-arm/arch-s3c2410/entry-macro.S +++ b/include/asm-arm/arch-s3c2410/entry-macro.S @@ -22,6 +22,12 @@ #include <asm/hardware.h> #include <asm/irq.h> + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp mov \base, #S3C24XX_VA_IRQ diff --git a/include/asm-arm/arch-sa1100/entry-macro.S b/include/asm-arm/arch-sa1100/entry-macro.S index 51fb50ce116..02896762934 100644 --- a/include/asm-arm/arch-sa1100/entry-macro.S +++ b/include/asm-arm/arch-sa1100/entry-macro.S @@ -11,6 +11,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp mov r4, #0xfa000000 @ ICIP = 0xfa050000 add r4, r4, #0x00050000 diff --git a/include/asm-arm/arch-shark/entry-macro.S b/include/asm-arm/arch-shark/entry-macro.S index a924f27fb8d..82463f30f3d 100644 --- a/include/asm-arm/arch-shark/entry-macro.S +++ b/include/asm-arm/arch-shark/entry-macro.S @@ -10,6 +10,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp mov r4, #0xe0000000 diff --git a/include/asm-arm/arch-versatile/entry-macro.S b/include/asm-arm/arch-versatile/entry-macro.S index feff771c0a0..0fae002637a 100644 --- a/include/asm-arm/arch-versatile/entry-macro.S +++ b/include/asm-arm/arch-versatile/entry-macro.S @@ -13,6 +13,12 @@ .macro disable_fiq .endm + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE) ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h index c91b546e20e..15141a9caca 100644 --- a/include/asm-arm/hardware/iop3xx.h +++ b/include/asm-arm/hardware/iop3xx.h @@ -188,14 +188,10 @@ extern void gpio_line_set(int line, int value); #define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014) #define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018) #define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c) -#define IOP3XX_TMR_TC 0x01 -#define IOP3XX_TMR_EN 0x02 -#define IOP3XX_TMR_RELOAD 0x04 -#define IOP3XX_TMR_PRIVILEGED 0x09 -#define IOP3XX_TMR_RATIO_1_1 0x00 -#define IOP3XX_TMR_RATIO_4_1 0x10 -#define IOP3XX_TMR_RATIO_8_1 0x20 -#define IOP3XX_TMR_RATIO_16_1 0x30 +#define IOP_TMR_EN 0x02 +#define IOP_TMR_RELOAD 0x04 +#define IOP_TMR_PRIVILEGED 0x08 +#define IOP_TMR_RATIO_1_1 0x00 /* Application accelerator unit */ #define IOP3XX_AAU_ACR (volatile u32 *)IOP3XX_REG_ADDR(0x0800) @@ -276,40 +272,52 @@ extern void gpio_line_set(int line, int value); #ifndef __ASSEMBLY__ void iop3xx_map_io(void); -void iop3xx_init_time(unsigned long); -unsigned long iop3xx_gettimeoffset(void); void iop_init_cp6_handler(void); +void iop_init_time(unsigned long tickrate); +unsigned long iop_gettimeoffset(void); -extern struct platform_device iop3xx_i2c0_device; -extern struct platform_device iop3xx_i2c1_device; +static inline void write_tmr0(u32 val) +{ + asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val)); +} + +static inline void write_tmr1(u32 val) +{ + asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val)); +} + +static inline u32 read_tcr0(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val)); + return val; +} -extern inline void iop3xx_cp6_enable(void) +static inline u32 read_tcr1(void) { - u32 temp; + u32 val; + asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val)); + return val; +} - asm volatile ( - "mrc p15, 0, %0, c15, c1, 0\n\t" - "orr %0, %0, #(1 << 6)\n\t" - "mcr p15, 0, %0, c15, c1, 0\n\t" - "mrc p15, 0, %0, c15, c1, 0\n\t" - "mov %0, %0\n\t" - "sub pc, pc, #4\n\t" - : "=r" (temp) ); +static inline void write_trr0(u32 val) +{ + asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val)); } -extern inline void iop3xx_cp6_disable(void) +static inline void write_trr1(u32 val) { - u32 temp; + asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val)); +} - asm volatile ( - "mrc p15, 0, %0, c15, c1, 0\n\t" - "bic %0, %0, #(1 << 6)\n\t" - "mcr p15, 0, %0, c15, c1, 0\n\t" - "mrc p15, 0, %0, c15, c1, 0\n\t" - "mov %0, %0\n\t" - "sub pc, pc, #4\n\t" - : "=r" (temp) ); +static inline void write_tisr(u32 val) +{ + asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val)); } + +extern struct platform_device iop3xx_i2c0_device; +extern struct platform_device iop3xx_i2c1_device; + #endif |