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-rw-r--r--include/asm-powerpc/i8259.h3
-rw-r--r--include/asm-powerpc/irq.h8
-rw-r--r--include/asm-powerpc/mpic.h25
3 files changed, 10 insertions, 26 deletions
diff --git a/include/asm-powerpc/i8259.h b/include/asm-powerpc/i8259.h
index 0392159e16e..ff31cb90325 100644
--- a/include/asm-powerpc/i8259.h
+++ b/include/asm-powerpc/i8259.h
@@ -4,11 +4,8 @@
#include <linux/irq.h>
-extern struct hw_interrupt_type i8259_pic;
-
extern void i8259_init(unsigned long intack_addr, int offset);
extern int i8259_irq(struct pt_regs *regs);
-extern int i8259_irq_cascade(struct pt_regs *regs, void *unused);
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_I8259_H */
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h
index eb5f33e1977..13fa2ef38dc 100644
--- a/include/asm-powerpc/irq.h
+++ b/include/asm-powerpc/irq.h
@@ -514,9 +514,12 @@ extern u64 ppc64_interrupt_controller;
#endif
+#ifndef CONFIG_PPC_MERGE
#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
/* pedantic: these are long because they are used with set_bit --RR */
extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
+#endif
+
extern atomic_t ppc_n_lost_interrupts;
#define virt_irq_create_mapping(x) (x)
@@ -579,9 +582,8 @@ extern struct thread_info *softirq_ctx[NR_CPUS];
extern void irq_ctx_init(void);
extern void call_do_softirq(struct thread_info *tp);
-extern int call___do_IRQ(int irq, struct pt_regs *regs,
- struct thread_info *tp);
-
+extern int call_handle_irq(int irq, void *p1, void *p2,
+ struct thread_info *tp, void *func);
#else
#define irq_ctx_init()
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
index f0d22ac34b9..a2277cb77dd 100644
--- a/include/asm-powerpc/mpic.h
+++ b/include/asm-powerpc/mpic.h
@@ -114,9 +114,6 @@
#define MPIC_VEC_TIMER_1 248
#define MPIC_VEC_TIMER_0 247
-/* Type definition of the cascade handler */
-typedef int (*mpic_cascade_t)(struct pt_regs *regs, void *data);
-
#ifdef CONFIG_MPIC_BROKEN_U3
/* Fixup table entry */
struct mpic_irq_fixup
@@ -133,9 +130,12 @@ struct mpic_irq_fixup
struct mpic
{
/* The "linux" controller struct */
- hw_irq_controller hc_irq;
+ struct irq_chip hc_irq;
+#ifdef CONFIG_MPIC_BROKEN_U3
+ struct irq_chip hc_ht_irq;
+#endif
#ifdef CONFIG_SMP
- hw_irq_controller hc_ipi;
+ struct irq_chip hc_ipi;
#endif
const char *name;
/* Flags */
@@ -153,10 +153,6 @@ struct mpic
unsigned int num_sources;
/* Number of CPUs */
unsigned int num_cpus;
- /* cascade handler */
- mpic_cascade_t cascade;
- void *cascade_data;
- unsigned int cascade_vec;
/* senses array */
unsigned char *senses;
unsigned int senses_count;
@@ -237,17 +233,6 @@ extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
*/
extern void mpic_init(struct mpic *mpic);
-/* Setup a cascade. Currently, only one cascade is supported this
- * way, though you can always do a normal request_irq() and add
- * other cascades this way. You should call this _after_ having
- * added all the ISUs
- *
- * @irq_no: "linux" irq number of the cascade (that is offset'ed vector)
- * @handler: cascade handler function
- */
-extern void mpic_setup_cascade(unsigned int irq_no, mpic_cascade_t hanlder,
- void *data);
-
/*
* All of the following functions must only be used after the
* ISUs have been assigned and the controller fully initialized