diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/drm/drm_pciids.h | 1 | ||||
| -rw-r--r-- | include/linux/clk/zynq.h | 24 | ||||
| -rw-r--r-- | include/linux/dma/ipu-dma.h | 177 | ||||
| -rw-r--r-- | include/linux/i2c-omap.h | 1 | ||||
| -rw-r--r-- | include/linux/of_address.h | 2 | ||||
| -rw-r--r-- | include/linux/omap-dma.h | 366 | ||||
| -rw-r--r-- | include/linux/platform_data/asoc-imx-ssi.h | 2 | ||||
| -rw-r--r-- | include/linux/platform_data/dma-imx.h | 4 | ||||
| -rw-r--r-- | include/linux/platform_data/dmtimer-omap.h | 31 | ||||
| -rw-r--r-- | include/linux/platform_data/gpio-omap.h | 1 | ||||
| -rw-r--r-- | include/linux/platform_data/uio_pruss.h | 3 | ||||
| -rw-r--r-- | include/linux/spi/ads7846.h | 5 | ||||
| -rw-r--r-- | include/linux/tegra-ahb.h | 19 | ||||
| -rw-r--r-- | include/net/xfrm.h | 2 | ||||
| -rw-r--r-- | include/scsi/scsi_device.h | 4 |
15 files changed, 636 insertions, 6 deletions
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h index af1cbaf535e..c5c35e62942 100644 --- a/include/drm/drm_pciids.h +++ b/include/drm/drm_pciids.h @@ -210,6 +210,7 @@ {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ diff --git a/include/linux/clk/zynq.h b/include/linux/clk/zynq.h new file mode 100644 index 00000000000..56be7cd9aa8 --- /dev/null +++ b/include/linux/clk/zynq.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2012 National Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __LINUX_CLK_ZYNQ_H_ +#define __LINUX_CLK_ZYNQ_H_ + +void __init xilinx_zynq_clocks_init(void __iomem *slcr); + +#endif diff --git a/include/linux/dma/ipu-dma.h b/include/linux/dma/ipu-dma.h new file mode 100644 index 00000000000..18031115c66 --- /dev/null +++ b/include/linux/dma/ipu-dma.h @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2008 + * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> + * + * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_DMA_IPU_DMA_H +#define __LINUX_DMA_IPU_DMA_H + +#include <linux/types.h> +#include <linux/dmaengine.h> + +/* IPU DMA Controller channel definitions. */ +enum ipu_channel { + IDMAC_IC_0 = 0, /* IC (encoding task) to memory */ + IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */ + IDMAC_ADC_0 = 1, + IDMAC_IC_2 = 2, + IDMAC_ADC_1 = 2, + IDMAC_IC_3 = 3, + IDMAC_IC_4 = 4, + IDMAC_IC_5 = 5, + IDMAC_IC_6 = 6, + IDMAC_IC_7 = 7, /* IC (sensor data) to memory */ + IDMAC_IC_8 = 8, + IDMAC_IC_9 = 9, + IDMAC_IC_10 = 10, + IDMAC_IC_11 = 11, + IDMAC_IC_12 = 12, + IDMAC_IC_13 = 13, + IDMAC_SDC_0 = 14, /* Background synchronous display data */ + IDMAC_SDC_1 = 15, /* Foreground data (overlay) */ + IDMAC_SDC_2 = 16, + IDMAC_SDC_3 = 17, + IDMAC_ADC_2 = 18, + IDMAC_ADC_3 = 19, + IDMAC_ADC_4 = 20, + IDMAC_ADC_5 = 21, + IDMAC_ADC_6 = 22, + IDMAC_ADC_7 = 23, + IDMAC_PF_0 = 24, + IDMAC_PF_1 = 25, + IDMAC_PF_2 = 26, + IDMAC_PF_3 = 27, + IDMAC_PF_4 = 28, + IDMAC_PF_5 = 29, + IDMAC_PF_6 = 30, + IDMAC_PF_7 = 31, +}; + +/* Order significant! */ +enum ipu_channel_status { + IPU_CHANNEL_FREE, + IPU_CHANNEL_INITIALIZED, + IPU_CHANNEL_READY, + IPU_CHANNEL_ENABLED, +}; + +#define IPU_CHANNELS_NUM 32 + +enum pixel_fmt { + /* 1 byte */ + IPU_PIX_FMT_GENERIC, + IPU_PIX_FMT_RGB332, + IPU_PIX_FMT_YUV420P, + IPU_PIX_FMT_YUV422P, + IPU_PIX_FMT_YUV420P2, + IPU_PIX_FMT_YVU422P, + /* 2 bytes */ + IPU_PIX_FMT_RGB565, + IPU_PIX_FMT_RGB666, + IPU_PIX_FMT_BGR666, + IPU_PIX_FMT_YUYV, + IPU_PIX_FMT_UYVY, + /* 3 bytes */ + IPU_PIX_FMT_RGB24, + IPU_PIX_FMT_BGR24, + /* 4 bytes */ + IPU_PIX_FMT_GENERIC_32, + IPU_PIX_FMT_RGB32, + IPU_PIX_FMT_BGR32, + IPU_PIX_FMT_ABGR32, + IPU_PIX_FMT_BGRA32, + IPU_PIX_FMT_RGBA32, +}; + +enum ipu_color_space { + IPU_COLORSPACE_RGB, + IPU_COLORSPACE_YCBCR, + IPU_COLORSPACE_YUV +}; + +/* + * Enumeration of IPU rotation modes + */ +enum ipu_rotate_mode { + /* Note the enum values correspond to BAM value */ + IPU_ROTATE_NONE = 0, + IPU_ROTATE_VERT_FLIP = 1, + IPU_ROTATE_HORIZ_FLIP = 2, + IPU_ROTATE_180 = 3, + IPU_ROTATE_90_RIGHT = 4, + IPU_ROTATE_90_RIGHT_VFLIP = 5, + IPU_ROTATE_90_RIGHT_HFLIP = 6, + IPU_ROTATE_90_LEFT = 7, +}; + +/* + * Enumeration of DI ports for ADC. + */ +enum display_port { + DISP0, + DISP1, + DISP2, + DISP3 +}; + +struct idmac_video_param { + unsigned short in_width; + unsigned short in_height; + uint32_t in_pixel_fmt; + unsigned short out_width; + unsigned short out_height; + uint32_t out_pixel_fmt; + unsigned short out_stride; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + enum display_port disp; + unsigned short out_left; + unsigned short out_top; +}; + +/* + * Union of initialization parameters for a logical channel. So far only video + * parameters are used. + */ +union ipu_channel_param { + struct idmac_video_param video; +}; + +struct idmac_tx_desc { + struct dma_async_tx_descriptor txd; + struct scatterlist *sg; /* scatterlist for this */ + unsigned int sg_len; /* tx-descriptor. */ + struct list_head list; +}; + +struct idmac_channel { + struct dma_chan dma_chan; + dma_cookie_t completed; /* last completed cookie */ + union ipu_channel_param params; + enum ipu_channel link; /* input channel, linked to the output */ + enum ipu_channel_status status; + void *client; /* Only one client per channel */ + unsigned int n_tx_desc; + struct idmac_tx_desc *desc; /* allocated tx-descriptors */ + struct scatterlist *sg[2]; /* scatterlist elements in buffer-0 and -1 */ + struct list_head free_list; /* free tx-descriptors */ + struct list_head queue; /* queued tx-descriptors */ + spinlock_t lock; /* protects sg[0,1], queue */ + struct mutex chan_mutex; /* protects status, cookie, free_list */ + bool sec_chan_en; + int active_buffer; + unsigned int eof_irq; + char eof_name[16]; /* EOF IRQ name for request_irq() */ +}; + +#define to_tx_desc(tx) container_of(tx, struct idmac_tx_desc, txd) +#define to_idmac_chan(c) container_of(c, struct idmac_channel, dma_chan) + +#endif /* __LINUX_DMA_IPU_DMA_H */ diff --git a/include/linux/i2c-omap.h b/include/linux/i2c-omap.h index df804ba73e0..92a0dc75bc7 100644 --- a/include/linux/i2c-omap.h +++ b/include/linux/i2c-omap.h @@ -34,6 +34,7 @@ struct omap_i2c_bus_platform_data { u32 clkrate; u32 rev; u32 flags; + void (*set_mpu_wkup_lat)(struct device *dev, long set); }; #endif diff --git a/include/linux/of_address.h b/include/linux/of_address.h index e20e3af68fb..0506eb53519 100644 --- a/include/linux/of_address.h +++ b/include/linux/of_address.h @@ -42,10 +42,12 @@ static inline struct device_node *of_find_matching_node_by_address( { return NULL; } +#ifndef of_iomap static inline void __iomem *of_iomap(struct device_node *device, int index) { return NULL; } +#endif static inline const __be32 *of_get_address(struct device_node *dev, int index, u64 *size, unsigned int *flags) { diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h index eb475a8ea25..7af25a9c9c5 100644 --- a/include/linux/omap-dma.h +++ b/include/linux/omap-dma.h @@ -19,4 +19,370 @@ static inline bool omap_dma_filter_fn(struct dma_chan *c, void *d) } #endif +/* + * Legacy OMAP DMA handling defines and functions + * + * NOTE: Do not use these any longer. + * + * Use the generic dmaengine functions as defined in + * include/linux/dmaengine.h. + * + * Copyright (C) 2003 Nokia Corporation + * Author: Juha Yrjölä <juha.yrjola@nokia.com> + * + */ + +#include <linux/platform_device.h> + +#define INT_DMA_LCD 25 + +#define OMAP1_DMA_TOUT_IRQ (1 << 0) +#define OMAP_DMA_DROP_IRQ (1 << 1) +#define OMAP_DMA_HALF_IRQ (1 << 2) +#define OMAP_DMA_FRAME_IRQ (1 << 3) +#define OMAP_DMA_LAST_IRQ (1 << 4) +#define OMAP_DMA_BLOCK_IRQ (1 << 5) +#define OMAP1_DMA_SYNC_IRQ (1 << 6) +#define OMAP2_DMA_PKT_IRQ (1 << 7) +#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8) +#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9) +#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10) +#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) + +#define OMAP_DMA_CCR_EN (1 << 7) +#define OMAP_DMA_CCR_RD_ACTIVE (1 << 9) +#define OMAP_DMA_CCR_WR_ACTIVE (1 << 10) +#define OMAP_DMA_CCR_SEL_SRC_DST_SYNC (1 << 24) +#define OMAP_DMA_CCR_BUFFERING_DISABLE (1 << 25) + +#define OMAP_DMA_DATA_TYPE_S8 0x00 +#define OMAP_DMA_DATA_TYPE_S16 0x01 +#define OMAP_DMA_DATA_TYPE_S32 0x02 + +#define OMAP_DMA_SYNC_ELEMENT 0x00 +#define OMAP_DMA_SYNC_FRAME 0x01 +#define OMAP_DMA_SYNC_BLOCK 0x02 +#define OMAP_DMA_SYNC_PACKET 0x03 + +#define OMAP_DMA_DST_SYNC_PREFETCH 0x02 +#define OMAP_DMA_SRC_SYNC 0x01 +#define OMAP_DMA_DST_SYNC 0x00 + +#define OMAP_DMA_PORT_EMIFF 0x00 +#define OMAP_DMA_PORT_EMIFS 0x01 +#define OMAP_DMA_PORT_OCP_T1 0x02 +#define OMAP_DMA_PORT_TIPB 0x03 +#define OMAP_DMA_PORT_OCP_T2 0x04 +#define OMAP_DMA_PORT_MPUI 0x05 + +#define OMAP_DMA_AMODE_CONSTANT 0x00 +#define OMAP_DMA_AMODE_POST_INC 0x01 +#define OMAP_DMA_AMODE_SINGLE_IDX 0x02 +#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03 + +#define DMA_DEFAULT_FIFO_DEPTH 0x10 +#define DMA_DEFAULT_ARB_RATE 0x01 +/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */ +#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */ +#define DMA_THREAD_RESERVE_ONET (0x01 << 12) +#define DMA_THREAD_RESERVE_TWOT (0x02 << 12) +#define DMA_THREAD_RESERVE_THREET (0x03 << 12) +#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */ +#define DMA_THREAD_FIFO_75 (0x01 << 14) +#define DMA_THREAD_FIFO_25 (0x02 << 14) +#define DMA_THREAD_FIFO_50 (0x03 << 14) + +/* DMA4_OCP_SYSCONFIG bits */ +#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12) +#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8) +#define DMA_SYSCONFIG_EMUFREE (1 << 5) +#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3) +#define DMA_SYSCONFIG_SOFTRESET (1 << 2) +#define DMA_SYSCONFIG_AUTOIDLE (1 << 0) + +#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12) +#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3) + +#define DMA_IDLEMODE_SMARTIDLE 0x2 +#define DMA_IDLEMODE_NO_IDLE 0x1 +#define DMA_IDLEMODE_FORCE_IDLE 0x0 + +/* Chaining modes*/ +#ifndef CONFIG_ARCH_OMAP1 +#define OMAP_DMA_STATIC_CHAIN 0x1 +#define OMAP_DMA_DYNAMIC_CHAIN 0x2 +#define OMAP_DMA_CHAIN_ACTIVE 0x1 +#define OMAP_DMA_CHAIN_INACTIVE 0x0 +#endif + +#define DMA_CH_PRIO_HIGH 0x1 +#define DMA_CH_PRIO_LOW 0x0 /* Def */ + +/* Errata handling */ +#define IS_DMA_ERRATA(id) (errata & (id)) +#define SET_DMA_ERRATA(id) (errata |= (id)) + +#define DMA_ERRATA_IFRAME_BUFFERING BIT(0x0) +#define DMA_ERRATA_PARALLEL_CHANNELS BIT(0x1) +#define DMA_ERRATA_i378 BIT(0x2) +#define DMA_ERRATA_i541 BIT(0x3) +#define DMA_ERRATA_i88 BIT(0x4) +#define DMA_ERRATA_3_3 BIT(0x5) +#define DMA_ROMCODE_BUG BIT(0x6) + +/* Attributes for OMAP DMA Contrller */ +#define DMA_LINKED_LCH BIT(0x0) +#define GLOBAL_PRIORITY BIT(0x1) +#define RESERVE_CHANNEL BIT(0x2) +#define IS_CSSA_32 BIT(0x3) +#define IS_CDSA_32 BIT(0x4) +#define IS_RW_PRIORITY BIT(0x5) +#define ENABLE_1510_MODE BIT(0x6) +#define SRC_PORT BIT(0x7) +#define DST_PORT BIT(0x8) +#define SRC_INDEX BIT(0x9) +#define DST_INDEX BIT(0xa) +#define IS_BURST_ONLY4 BIT(0xb) +#define CLEAR_CSR_ON_READ BIT(0xc) +#define IS_WORD_16 BIT(0xd) +#define ENABLE_16XX_MODE BIT(0xe) +#define HS_CHANNELS_RESERVED BIT(0xf) + +/* Defines for DMA Capabilities */ +#define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18) +#define DMA_HAS_CONSTANT_FILL_CAPS (0x1 << 19) +#define DMA_HAS_DESCRIPTOR_CAPS (0x3 << 20) + +enum omap_reg_offsets { + +GCR, GSCR, GRST1, HW_ID, +PCH2_ID, PCH0_ID, PCH1_ID, PCHG_ID, +PCHD_ID, CAPS_0, CAPS_1, CAPS_2, +CAPS_3, CAPS_4, PCH2_SR, PCH0_SR, +PCH1_SR, PCHD_SR, REVISION, IRQSTATUS_L0, +IRQSTATUS_L1, IRQSTATUS_L2, IRQSTATUS_L3, IRQENABLE_L0, +IRQENABLE_L1, IRQENABLE_L2, IRQENABLE_L3, SYSSTATUS, +OCP_SYSCONFIG, + +/* omap1+ specific */ +CPC, CCR2, LCH_CTRL, + +/* Common registers for all omap's */ +CSDP, CCR, CICR, CSR, +CEN, CFN, CSFI, CSEI, +CSAC, CDAC, CDEI, +CDFI, CLNK_CTRL, + +/* Channel specific registers */ +CSSA, CDSA, COLOR, +CCEN, CCFN, + +/* omap3630 and omap4 specific */ +CDP, CNDP, CCDN, + +}; + +enum omap_dma_burst_mode { + OMAP_DMA_DATA_BURST_DIS = 0, + OMAP_DMA_DATA_BURST_4, + OMAP_DMA_DATA_BURST_8, + OMAP_DMA_DATA_BURST_16, +}; + +enum end_type { + OMAP_DMA_LITTLE_ENDIAN = 0, + OMAP_DMA_BIG_ENDIAN +}; + +enum omap_dma_color_mode { + OMAP_DMA_COLOR_DIS = 0, + OMAP_DMA_CONSTANT_FILL, + OMAP_DMA_TRANSPARENT_COPY +}; + +enum omap_dma_write_mode { + OMAP_DMA_WRITE_NON_POSTED = 0, + OMAP_DMA_WRITE_POSTED, + OMAP_DMA_WRITE_LAST_NON_POSTED +}; + +enum omap_dma_channel_mode { + OMAP_DMA_LCH_2D = 0, + OMAP_DMA_LCH_G, + OMAP_DMA_LCH_P, + OMAP_DMA_LCH_PD +}; + +struct omap_dma_channel_params { + int data_type; /* data type 8,16,32 */ + int elem_count; /* number of elements in a frame */ + int frame_count; /* number of frames in a element */ + + int src_port; /* Only on OMAP1 REVISIT: Is this needed? */ + int src_amode; /* constant, post increment, indexed, + double indexed */ + unsigned long src_start; /* source address : physical */ + int src_ei; /* source element index */ + int src_fi; /* source frame index */ + + int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */ + int dst_amode; /* constant, post increment, indexed, + double indexed */ + unsigned long dst_start; /* source address : physical */ + int dst_ei; /* source element index */ + int dst_fi; /* source frame index */ + + int trigger; /* trigger attached if the channel is + synchronized */ + int sync_mode; /* sycn on element, frame , block or packet */ + int src_or_dst_synch; /* source synch(1) or destination synch(0) */ + + int ie; /* interrupt enabled */ + + unsigned char read_prio;/* read priority */ + unsigned char write_prio;/* write priority */ + +#ifndef CONFIG_ARCH_OMAP1 + enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */ +#endif +}; + +struct omap_dma_lch { + int next_lch; + int dev_id; + u16 saved_csr; + u16 enabled_irqs; + const char *dev_name; + void (*callback)(int lch, u16 ch_status, void *data); + void *data; + long flags; + /* required for Dynamic chaining */ + int prev_linked_ch; + int next_linked_ch; + int state; + int chain_id; + int status; +}; + +struct omap_dma_dev_attr { + u32 dev_caps; + u16 lch_count; + u16 chan_count; + struct omap_dma_lch *chan; +}; + +/* System DMA platform data structure */ +struct omap_system_dma_plat_info { + struct omap_dma_dev_attr *dma_attr; + u32 errata; + void (*disable_irq_lch)(int lch); + void (*show_dma_caps)(void); + void (*clear_lch_regs)(int lch); + void (*clear_dma)(int lch); + void (*dma_write)(u32 val, int reg, int lch); + u32 (*dma_read)(int reg, int lch); +}; + +#ifdef CONFIG_ARCH_OMAP2PLUS +#define dma_omap2plus() 1 +#else +#define dma_omap2plus() 0 #endif +#define dma_omap1() (!dma_omap2plus()) +#define dma_omap15xx() ((dma_omap1() && (d->dev_caps & ENABLE_1510_MODE))) +#define dma_omap16xx() ((dma_omap1() && (d->dev_caps & ENABLE_16XX_MODE))) + +extern void omap_set_dma_priority(int lch, int dst_port, int priority); +extern int omap_request_dma(int dev_id, const char *dev_name, + void (*callback)(int lch, u16 ch_status, void *data), + void *data, int *dma_ch); +extern void omap_enable_dma_irq(int ch, u16 irq_bits); +extern void omap_disable_dma_irq(int ch, u16 irq_bits); +extern void omap_free_dma(int ch); +extern void omap_start_dma(int lch); +extern void omap_stop_dma(int lch); +extern void omap_set_dma_transfer_params(int lch, int data_type, + int elem_count, int frame_count, + int sync_mode, + int dma_trigger, int src_or_dst_synch); +extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, + u32 color); +extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode); +extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode); + +extern void omap_set_dma_src_params(int lch, int src_port, int src_amode, + unsigned long src_start, + int src_ei, int src_fi); +extern void omap_set_dma_src_index(int lch, int eidx, int fidx); +extern void omap_set_dma_src_data_pack(int lch, int enable); +extern void omap_set_dma_src_burst_mode(int lch, + enum omap_dma_burst_mode burst_mode); + +extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, + unsigned long dest_start, + int dst_ei, int dst_fi); +extern void omap_set_dma_dest_index(int lch, int eidx, int fidx); +extern void omap_set_dma_dest_data_pack(int lch, int enable); +extern void omap_set_dma_dest_burst_mode(int lch, + enum omap_dma_burst_mode burst_mode); + +extern void omap_set_dma_params(int lch, + struct omap_dma_channel_params *params); + +extern void omap_dma_link_lch(int lch_head, int lch_queue); +extern void omap_dma_unlink_lch(int lch_head, int lch_queue); + +extern int omap_set_dma_callback(int lch, + void (*callback)(int lch, u16 ch_status, void *data), + void *data); +extern dma_addr_t omap_get_dma_src_pos(int lch); +extern dma_addr_t omap_get_dma_dst_pos(int lch); +extern void omap_clear_dma(int lch); +extern int omap_get_dma_active_status(int lch); +extern int omap_dma_running(void); +extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, + int tparams); +extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio, + unsigned char write_prio); +extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype); +extern void omap_set_dma_src_endian_type(int lch, enum end_type etype); +extern int omap_get_dma_index(int lch, int *ei, int *fi); + +void omap_dma_global_context_save(void); +void omap_dma_global_context_restore(void); + +extern void omap_dma_disable_irq(int lch); + +/* Chaining APIs */ +#ifndef CONFIG_ARCH_OMAP1 +extern int omap_request_dma_chain(int dev_id, const char *dev_name, + void (*callback) (int lch, u16 ch_status, + void *data), + int *chain_id, int no_of_chans, + int chain_mode, + struct omap_dma_channel_params params); +extern int omap_free_dma_chain(int chain_id); +extern int omap_dma_chain_a_transfer(int chain_id, int src_start, + int dest_start, int elem_count, + int frame_count, void *callbk_data); +extern int omap_start_dma_chain_transfers(int chain_id); +extern int omap_stop_dma_chain_transfers(int chain_id); +extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi); +extern int omap_get_dma_chain_dst_pos(int chain_id); +extern int omap_get_dma_chain_src_pos(int chain_id); + +extern int omap_modify_dma_chain_params(int chain_id, + struct omap_dma_channel_params params); +extern int omap_dma_chain_status(int chain_id); +#endif + +#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP) +#include <mach/lcd_dma.h> +#else +static inline int omap_lcd_dma_running(void) +{ + return 0; +} +#endif + +#endif /* __LINUX_OMAP_DMA_H */ diff --git a/include/linux/platform_data/asoc-imx-ssi.h b/include/linux/platform_data/asoc-imx-ssi.h index 63f3c280423..92c7fd72f63 100644 --- a/include/linux/platform_data/asoc-imx-ssi.h +++ b/include/linux/platform_data/asoc-imx-ssi.h @@ -17,5 +17,7 @@ struct imx_ssi_platform_data { void (*ac97_warm_reset)(struct snd_ac97 *ac97); }; +extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type); + #endif /* __MACH_SSI_H */ diff --git a/include/linux/platform_data/dma-imx.h b/include/linux/platform_data/dma-imx.h index 1b9080385b4..f6d30cc1cb7 100644 --- a/include/linux/platform_data/dma-imx.h +++ b/include/linux/platform_data/dma-imx.h @@ -61,7 +61,9 @@ static inline int imx_dma_is_ipu(struct dma_chan *chan) static inline int imx_dma_is_general_purpose(struct dma_chan *chan) { return strstr(dev_name(chan->device->dev), "sdma") || - !strcmp(dev_name(chan->device->dev), "imx-dma"); + !strcmp(dev_name(chan->device->dev), "imx1-dma") || + !strcmp(dev_name(chan->device->dev), "imx21-dma") || + !strcmp(dev_name(chan->device->dev), "imx27-dma"); } #endif diff --git a/include/linux/platform_data/dmtimer-omap.h b/include/linux/platform_data/dmtimer-omap.h new file mode 100644 index 00000000000..a19b78d826e --- /dev/null +++ b/include/linux/platform_data/dmtimer-omap.h @@ -0,0 +1,31 @@ +/* + * DMTIMER platform data for TI OMAP platforms + * + * Copyright (C) 2012 Texas Instruments + * Author: Jon Hunter <jon-hunter@ti.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __PLATFORM_DATA_DMTIMER_OMAP_H__ +#define __PLATFORM_DATA_DMTIMER_OMAP_H__ + +struct dmtimer_platform_data { + /* set_timer_src - Only used for OMAP1 devices */ + int (*set_timer_src)(struct platform_device *pdev, int source); + u32 timer_capability; + u32 timer_errata; + int (*get_context_loss_count)(struct device *); +}; + +#endif /* __PLATFORM_DATA_DMTIMER_OMAP_H__ */ diff --git a/include/linux/platform_data/gpio-omap.h b/include/linux/platform_data/gpio-omap.h index e8741c2678d..5d50b25a73d 100644 --- a/include/linux/platform_data/gpio-omap.h +++ b/include/linux/platform_data/gpio-omap.h @@ -26,7 +26,6 @@ #include <linux/io.h> #include <linux/platform_device.h> -#include <mach/irqs.h> #define OMAP1_MPUIO_BASE 0xfffb5000 diff --git a/include/linux/platform_data/uio_pruss.h b/include/linux/platform_data/uio_pruss.h index f39140aabc6..3d47d219827 100644 --- a/include/linux/platform_data/uio_pruss.h +++ b/include/linux/platform_data/uio_pruss.h @@ -20,6 +20,7 @@ /* To configure the PRUSS INTC base offset for UIO driver */ struct uio_pruss_pdata { - u32 pintc_base; + u32 pintc_base; + struct gen_pool *sram_pool; }; #endif /* _UIO_PRUSS_H_ */ diff --git a/include/linux/spi/ads7846.h b/include/linux/spi/ads7846.h index c64de9dd763..2f694f3846a 100644 --- a/include/linux/spi/ads7846.h +++ b/include/linux/spi/ads7846.h @@ -46,8 +46,9 @@ struct ads7846_platform_data { u16 debounce_rep; /* additional consecutive good readings * required after the first two */ int gpio_pendown; /* the GPIO used to decide the pendown - * state if get_pendown_state == NULL - */ + * state if get_pendown_state == NULL */ + int gpio_pendown_debounce; /* platform specific debounce time for + * the gpio_pendown */ int (*get_pendown_state)(void); int (*filter_init) (const struct ads7846_platform_data *pdata, void **filter_data); diff --git a/include/linux/tegra-ahb.h b/include/linux/tegra-ahb.h new file mode 100644 index 00000000000..f1cd075ceee --- /dev/null +++ b/include/linux/tegra-ahb.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __LINUX_AHB_H__ +#define __LINUX_AHB_H__ + +extern int tegra_ahb_enable_smmu(struct device_node *ahb); + +#endif /* __LINUX_AHB_H__ */ diff --git a/include/net/xfrm.h b/include/net/xfrm.h index 6f0ba01afe7..63445ede48b 100644 --- a/include/net/xfrm.h +++ b/include/net/xfrm.h @@ -1351,7 +1351,7 @@ struct xfrm6_tunnel { }; extern void xfrm_init(void); -extern void xfrm4_init(int rt_hash_size); +extern void xfrm4_init(void); extern int xfrm_state_init(struct net *net); extern void xfrm_state_fini(struct net *net); extern void xfrm4_state_init(void); diff --git a/include/scsi/scsi_device.h b/include/scsi/scsi_device.h index 88fae8d2015..55367b04dc9 100644 --- a/include/scsi/scsi_device.h +++ b/include/scsi/scsi_device.h @@ -135,6 +135,8 @@ struct scsi_device { * because we did a bus reset. */ unsigned use_10_for_rw:1; /* first try 10-byte read / write */ unsigned use_10_for_ms:1; /* first try 10-byte mode sense/select */ + unsigned no_report_opcodes:1; /* no REPORT SUPPORTED OPERATION CODES */ + unsigned no_write_same:1; /* no WRITE SAME command */ unsigned skip_ms_page_8:1; /* do not use MODE SENSE page 0x08 */ unsigned skip_ms_page_3f:1; /* do not use MODE SENSE page 0x3f */ unsigned skip_vpd_pages:1; /* do not read VPD pages */ @@ -362,6 +364,8 @@ extern int scsi_test_unit_ready(struct scsi_device *sdev, int timeout, int retries, struct scsi_sense_hdr *sshdr); extern int scsi_get_vpd_page(struct scsi_device *, u8 page, unsigned char *buf, int buf_len); +extern int scsi_report_opcode(struct scsi_device *sdev, unsigned char *buffer, + unsigned int len, unsigned char opcode); extern int scsi_device_set_state(struct scsi_device *sdev, enum scsi_device_state state); extern struct scsi_event *sdev_evt_alloc(enum scsi_device_event evt_type, |