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-rw-r--r--include/asm-arm/arch-iop13xx/iop13xx.h43
-rw-r--r--include/asm-arm/arch-iop13xx/system.h34
-rw-r--r--include/asm-arm/arch-iop13xx/uncompress.h3
-rw-r--r--include/asm-arm/arch-iop32x/uncompress.h2
-rw-r--r--include/asm-arm/arch-mxc/board-mx31ads.h142
-rw-r--r--include/asm-arm/arch-mxc/common.h20
-rw-r--r--include/asm-arm/arch-mxc/dma.h21
-rw-r--r--include/asm-arm/arch-mxc/entry-macro.S39
-rw-r--r--include/asm-arm/arch-mxc/hardware.h52
-rw-r--r--include/asm-arm/arch-mxc/io.h33
-rw-r--r--include/asm-arm/arch-mxc/irqs.h38
-rw-r--r--include/asm-arm/arch-mxc/memory.h36
-rw-r--r--include/asm-arm/arch-mxc/mx31.h335
-rw-r--r--include/asm-arm/arch-mxc/mxc.h149
-rw-r--r--include/asm-arm/arch-mxc/system.h50
-rw-r--r--include/asm-arm/arch-mxc/timex.h25
-rw-r--r--include/asm-arm/arch-mxc/uncompress.h79
-rw-r--r--include/asm-arm/arch-mxc/vmalloc.h36
-rw-r--r--include/asm-arm/arch-ns9xxx/regs-bbu.h28
-rw-r--r--include/asm-arm/arch-ns9xxx/regs-mem.h6
-rw-r--r--include/asm-arm/arch-ns9xxx/regs-sys.h2
-rw-r--r--include/asm-arm/arch-pxa/pm.h16
-rw-r--r--include/asm-arm/arch-s3c2400/map.h66
-rw-r--r--include/asm-arm/arch-s3c2400/memory.h23
-rw-r--r--include/asm-arm/arch-s3c2410/debug-macro.S84
-rw-r--r--include/asm-arm/arch-s3c2410/map.h85
-rw-r--r--include/asm-arm/arch-s3c2410/memory.h13
-rw-r--r--include/asm-arm/arch-s3c2410/regs-lcd.h2
-rw-r--r--include/asm-arm/arch-s3c2410/system.h2
-rw-r--r--include/asm-arm/arch-s3c2410/uncompress.h145
-rw-r--r--include/asm-arm/arch-sa1100/jornada720.h27
-rw-r--r--include/asm-arm/elf.h3
-rw-r--r--include/asm-arm/floppy.h18
-rw-r--r--include/asm-arm/hardware/iop3xx.h33
-rw-r--r--include/asm-arm/pgtable-nommu.h3
-rw-r--r--include/asm-arm/plat-s3c/debug-macro.S75
-rw-r--r--include/asm-arm/plat-s3c/iic.h (renamed from include/asm-arm/arch-s3c2410/iic.h)0
-rw-r--r--include/asm-arm/plat-s3c/map.h40
-rw-r--r--include/asm-arm/plat-s3c/nand.h (renamed from include/asm-arm/arch-s3c2410/nand.h)0
-rw-r--r--include/asm-arm/plat-s3c/regs-ac97.h (renamed from include/asm-arm/arch-s3c2410/regs-ac97.h)0
-rw-r--r--include/asm-arm/plat-s3c/regs-adc.h (renamed from include/asm-arm/arch-s3c2410/regs-adc.h)0
-rw-r--r--include/asm-arm/plat-s3c/regs-iic.h (renamed from include/asm-arm/arch-s3c2410/regs-iic.h)0
-rw-r--r--include/asm-arm/plat-s3c/regs-nand.h (renamed from include/asm-arm/arch-s3c2410/regs-nand.h)0
-rw-r--r--include/asm-arm/plat-s3c/regs-rtc.h (renamed from include/asm-arm/arch-s3c2410/regs-rtc.h)0
-rw-r--r--include/asm-arm/plat-s3c/regs-serial.h (renamed from include/asm-arm/arch-s3c2410/regs-serial.h)8
-rw-r--r--include/asm-arm/plat-s3c/regs-timer.h (renamed from include/asm-arm/arch-s3c2410/regs-timer.h)16
-rw-r--r--include/asm-arm/plat-s3c/regs-watchdog.h (renamed from include/asm-arm/arch-s3c2410/regs-watchdog.h)8
-rw-r--r--include/asm-arm/plat-s3c/uncompress.h155
-rw-r--r--include/asm-arm/plat-s3c24xx/regs-iis.h (renamed from include/asm-arm/arch-s3c2410/regs-iis.h)0
-rw-r--r--include/asm-arm/plat-s3c24xx/regs-spi.h (renamed from include/asm-arm/arch-s3c2410/regs-spi.h)0
-rw-r--r--include/asm-arm/plat-s3c24xx/regs-udc.h (renamed from include/asm-arm/arch-s3c2410/regs-udc.h)0
-rw-r--r--include/asm-arm/plat-s3c24xx/udc.h (renamed from include/asm-arm/arch-s3c2410/udc.h)0
-rw-r--r--include/asm-arm/thread_info.h1
-rw-r--r--include/asm-arm/unistd.h1
-rw-r--r--include/asm-arm/vfp.h4
55 files changed, 1670 insertions, 331 deletions
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h
index d4e4f828577..52b7fab7ef6 100644
--- a/include/asm-arm/arch-iop13xx/iop13xx.h
+++ b/include/asm-arm/arch-iop13xx/iop13xx.h
@@ -19,6 +19,39 @@ static inline int iop13xx_cpu_id(void)
return id;
}
+/* WDTCR CP6 R7 Page 9 */
+static inline u32 read_wdtcr(void)
+{
+ u32 val;
+ asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
+ return val;
+}
+static inline void write_wdtcr(u32 val)
+{
+ asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
+}
+
+/* WDTSR CP6 R8 Page 9 */
+static inline u32 read_wdtsr(void)
+{
+ u32 val;
+ asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
+ return val;
+}
+static inline void write_wdtsr(u32 val)
+{
+ asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
+}
+
+/* RCSR - Reset Cause Status Register */
+static inline u32 read_rcsr(void)
+{
+ u32 val;
+ asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val));
+ return val;
+}
+
+extern unsigned long get_iop_tick_rate(void);
#endif
/*
@@ -480,4 +513,14 @@ static inline int iop13xx_cpu_id(void)
#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
#define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180)
+
+/* Watchdog timer definitions */
+#define IOP_WDTCR_EN_ARM 0x1e1e1e1e
+#define IOP_WDTCR_EN 0xe1e1e1e1
+#define IOP_WDTCR_DIS_ARM 0x1f1f1f1f
+#define IOP_WDTCR_DIS 0xf1f1f1f1
+#define IOP_RCSR_WDT (1 << 5) /* reset caused by watchdog timer */
+#define IOP13XX_WDTSR_WRITE_EN (1 << 31) /* used to speed up reset requests */
+#define IOP13XX_WDTCR_IB_RESET (1 << 0)
+
#endif /* _IOP13XX_HW_H_ */
diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h
index 127827058e1..8575af8db78 100644
--- a/include/asm-arm/arch-iop13xx/system.h
+++ b/include/asm-arm/arch-iop13xx/system.h
@@ -13,43 +13,13 @@ static inline void arch_idle(void)
cpu_do_idle();
}
-/* WDTCR CP6 R7 Page 9 */
-static inline u32 read_wdtcr(void)
-{
- u32 val;
- asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
- return val;
-}
-static inline void write_wdtcr(u32 val)
-{
- asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
-}
-
-/* WDTSR CP6 R8 Page 9 */
-static inline u32 read_wdtsr(void)
-{
- u32 val;
- asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
- return val;
-}
-static inline void write_wdtsr(u32 val)
-{
- asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
-}
-
-#define IOP13XX_WDTCR_EN_ARM 0x1e1e1e1e
-#define IOP13XX_WDTCR_EN 0xe1e1e1e1
-#define IOP13XX_WDTCR_DIS_ARM 0x1f1f1f1f
-#define IOP13XX_WDTCR_DIS 0xf1f1f1f1
-#define IOP13XX_WDTSR_WRITE_EN (1 << 31)
-#define IOP13XX_WDTCR_IB_RESET (1 << 0)
static inline void arch_reset(char mode)
{
/*
* Reset the internal bus (warning both cores are reset)
*/
- write_wdtcr(IOP13XX_WDTCR_EN_ARM);
- write_wdtcr(IOP13XX_WDTCR_EN);
+ write_wdtcr(IOP_WDTCR_EN_ARM);
+ write_wdtcr(IOP_WDTCR_EN);
write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
write_wdtcr(0x1000);
diff --git a/include/asm-arm/arch-iop13xx/uncompress.h b/include/asm-arm/arch-iop13xx/uncompress.h
index b9525d59b7a..dd9c2934190 100644
--- a/include/asm-arm/arch-iop13xx/uncompress.h
+++ b/include/asm-arm/arch-iop13xx/uncompress.h
@@ -1,7 +1,6 @@
#include <asm/types.h>
#include <linux/serial_reg.h>
#include <asm/hardware.h>
-#include <asm/processor.h>
#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
@@ -9,7 +8,7 @@
static inline void putc(char c)
{
while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
- cpu_relax();
+ barrier();
UART_BASE[UART_TX] = c;
}
diff --git a/include/asm-arm/arch-iop32x/uncompress.h b/include/asm-arm/arch-iop32x/uncompress.h
index e64f52bf2bc..070f15818fe 100644
--- a/include/asm-arm/arch-iop32x/uncompress.h
+++ b/include/asm-arm/arch-iop32x/uncompress.h
@@ -26,7 +26,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
{
if (machine_is_iq80321())
uart_base = (volatile u8 *)IQ80321_UART;
- else if (machine_is_iq31244())
+ else if (machine_is_iq31244() || machine_is_em7210())
uart_base = (volatile u8 *)IQ31244_UART;
else
uart_base = (volatile u8 *)0xfe800000;
diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h
new file mode 100644
index 00000000000..be29b83ad4a
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-mx31ads.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
+#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
+
+/*!
+ * @name PBC Controller parameters
+ */
+/*! @{ */
+/*!
+ * Base address of PBC controller
+ */
+#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR)
+/* Offsets for the PBC Controller register */
+/*!
+ * PBC Board status register offset
+ */
+#define PBC_BSTAT 0x000002
+/*!
+ * PBC Board control register 1 set address.
+ */
+#define PBC_BCTRL1_SET 0x000004
+/*!
+ * PBC Board control register 1 clear address.
+ */
+#define PBC_BCTRL1_CLEAR 0x000006
+/*!
+ * PBC Board control register 2 set address.
+ */
+#define PBC_BCTRL2_SET 0x000008
+/*!
+ * PBC Board control register 2 clear address.
+ */
+#define PBC_BCTRL2_CLEAR 0x00000A
+/*!
+ * PBC Board control register 3 set address.
+ */
+#define PBC_BCTRL3_SET 0x00000C
+/*!
+ * PBC Board control register 3 clear address.
+ */
+#define PBC_BCTRL3_CLEAR 0x00000E
+/*!
+ * PBC Board control register 4 set address.
+ */
+#define PBC_BCTRL4_SET 0x000010
+/*!
+ * PBC Board control register 4 clear address.
+ */
+#define PBC_BCTRL4_CLEAR 0x000012
+/*!
+ * PBC Board status register 1.
+ */
+#define PBC_BSTAT1 0x000014
+/*!
+ * PBC Board interrupt status register.
+ */
+#define PBC_INTSTATUS 0x000016
+/*!
+ * PBC Board interrupt current status register.
+ */
+#define PBC_INTCURR_STATUS 0x000018
+/*!
+ * PBC Interrupt mask register set address.
+ */
+#define PBC_INTMASK_SET 0x00001A
+/*!
+ * PBC Interrupt mask register clear address.
+ */
+#define PBC_INTMASK_CLEAR 0x00001C
+
+/*!
+ * External UART A.
+ */
+#define PBC_SC16C652_UARTA 0x010000
+/*!
+ * External UART B.
+ */
+#define PBC_SC16C652_UARTB 0x010010
+/*!
+ * Ethernet Controller IO base address.
+ */
+#define PBC_CS8900A_IOBASE 0x020000
+/*!
+ * Ethernet Controller Memory base address.
+ */
+#define PBC_CS8900A_MEMBASE 0x021000
+/*!
+ * Ethernet Controller DMA base address.
+ */
+#define PBC_CS8900A_DMABASE 0x022000
+/*!
+ * External chip select 0.
+ */
+#define PBC_XCS0 0x040000
+/*!
+ * LCD Display enable.
+ */
+#define PBC_LCD_EN_B 0x060000
+/*!
+ * Code test debug enable.
+ */
+#define PBC_CODE_B 0x070000
+/*!
+ * PSRAM memory select.
+ */
+#define PBC_PSRAM_B 0x5000000
+
+#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
+#define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
+#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
+
+#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0)
+#define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1)
+#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
+#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
+#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
+#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
+#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
+#define EXPIO_INT_RES7 (MXC_EXP_IO_BASE + 7)
+#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
+#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
+#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
+#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
+#define EXPIO_INT_SYNTH_IRQ (MXC_EXP_IO_BASE + 12)
+#define EXPIO_INT_CE_INT1 (MXC_EXP_IO_BASE + 13)
+#define EXPIO_INT_CE_INT2 (MXC_EXP_IO_BASE + 14)
+#define EXPIO_INT_RES15 (MXC_EXP_IO_BASE + 15)
+
+#define MXC_MAX_EXP_IO_LINES 16
+
+#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/common.h b/include/asm-arm/arch-mxc/common.h
new file mode 100644
index 00000000000..23b4350edbd
--- /dev/null
+++ b/include/asm-arm/arch-mxc/common.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_COMMON_H__
+#define __ASM_ARCH_MXC_COMMON_H__
+
+struct sys_timer;
+
+extern void mxc_map_io(void);
+extern void mxc_init_irq(void);
+extern struct sys_timer mxc_timer;
+
+#endif
diff --git a/include/asm-arm/arch-mxc/dma.h b/include/asm-arm/arch-mxc/dma.h
new file mode 100644
index 00000000000..65e639d51d2
--- /dev/null
+++ b/include/asm-arm/arch-mxc/dma.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_DMA_H__
+#define __ASM_ARCH_MXC_DMA_H__
+
+/*!
+ * @file dma.h
+ * @brief This file contains Unified DMA API for all MXC platforms.
+ * The API is platform independent.
+ *
+ * @ingroup SDMA
+ */
+#endif
diff --git a/include/asm-arm/arch-mxc/entry-macro.S b/include/asm-arm/arch-mxc/entry-macro.S
new file mode 100644
index 00000000000..b542433afb1
--- /dev/null
+++ b/include/asm-arm/arch-mxc/entry-macro.S
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+ @ this macro disables fast irq (not implemented)
+ .macro disable_fiq
+ .endm
+
+ .macro get_irqnr_preamble, base, tmp
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
+ @ this macro checks which interrupt occured
+ @ and returns its number in irqnr
+ @ and returns if an interrupt occured in irqstat
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+ ldr \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR)
+ @ Load offset & priority of the highest priority
+ @ interrupt pending from AVIC_NIVECSR
+ ldr \irqstat, [\base, #0x40]
+ @ Shift to get the decoded IRQ number, using ASR so
+ @ 'no interrupt pending' becomes 0xffffffff
+ mov \irqnr, \irqstat, asr #16
+ @ set zero flag if IRQ + 1 == 0
+ adds \tmp, \irqnr, #1
+ .endm
+
+ @ irq priority table (not used)
+ .macro irq_prio_table
+ .endm
diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h
new file mode 100644
index 00000000000..3c09b92fef0
--- /dev/null
+++ b/include/asm-arm/arch-mxc/hardware.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*!
+ * @file hardware.h
+ * @brief This file contains the hardware definitions of the board.
+ *
+ * @ingroup System
+ */
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#define __ASM_ARCH_MXC_HARDWARE_H__
+
+#include <asm/sizes.h>
+
+#include <asm/arch/mx31.h>
+
+#include <asm/arch/mxc.h>
+
+#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM)
+
+/*
+ * ---------------------------------------------------------------------------
+ * Board specific defines
+ * ---------------------------------------------------------------------------
+ */
+#define MXC_EXP_IO_BASE (MXC_GPIO_INT_BASE + MXC_MAX_GPIO_LINES)
+
+#include <asm/arch/board-mx31ads.h>
+
+#ifndef MXC_MAX_EXP_IO_LINES
+#define MXC_MAX_EXP_IO_LINES 0
+#endif
+
+#define MXC_MAX_VIRTUAL_INTS 16
+#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
+#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE
+#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1)
+#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2)
+
+#define MXC_MAX_INTS (MXC_MAX_INT_LINES + \
+ MXC_MAX_GPIO_LINES + \
+ MXC_MAX_EXP_IO_LINES + \
+ MXC_MAX_VIRTUAL_INTS)
+
+#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-mxc/io.h b/include/asm-arm/arch-mxc/io.h
new file mode 100644
index 00000000000..cf6c83a4b9f
--- /dev/null
+++ b/include/asm-arm/arch-mxc/io.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*!
+ * @file io.h
+ * @brief This file contains some memory mapping macros.
+ * @note There is no real ISA or PCI buses. But have to define these macros
+ * for some drivers to compile.
+ *
+ * @ingroup System
+ */
+
+#ifndef __ASM_ARCH_MXC_IO_H__
+#define __ASM_ARCH_MXC_IO_H__
+
+/*! Allow IO space to be anywhere in the memory */
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*!
+ * io address mapping macro
+ */
+#define __io(a) ((void __iomem *)(a))
+
+#define __mem_pci(a) (a)
+
+#endif
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h
new file mode 100644
index 00000000000..e4686c6bc4b
--- /dev/null
+++ b/include/asm-arm/arch-mxc/irqs.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_IRQS_H__
+#define __ASM_ARCH_MXC_IRQS_H__
+
+#include <asm/hardware.h>
+
+/*!
+ * @file irqs.h
+ * @brief This file defines the number of normal interrupts and fast interrupts
+ *
+ * @ingroup Interrupt
+ */
+
+#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
+
+#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_GPIO_INT_BASE)
+#define MXC_GPIO_TO_IRQ(x) (MXC_GPIO_INT_BASE + x)
+
+/*!
+ * Number of normal interrupts
+ */
+#define NR_IRQS MXC_MAX_INTS
+
+/*!
+ * Number of fast interrupts
+ */
+#define NR_FIQS MXC_MAX_INTS
+
+#endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/include/asm-arm/arch-mxc/memory.h b/include/asm-arm/arch-mxc/memory.h
new file mode 100644
index 00000000000..c89aac83a40
--- /dev/null
+++ b/include/asm-arm/arch-mxc/memory.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_MEMORY_H__
+#define __ASM_ARCH_MXC_MEMORY_H__
+
+#include <asm/hardware.h>
+
+/*!
+ * @file memory.h
+ * @brief This file contains macros needed by the Linux kernel and drivers.
+ *
+ * @ingroup Memory
+ */
+
+/*!
+ * Virtual view <-> DMA view memory address translations
+ * This macro is used to translate the virtual address to an address
+ * suitable to be passed to set_dma_addr()
+ */
+#define __virt_to_bus(a) __virt_to_phys(a)
+
+/*!
+ * Used to convert an address for DMA operations to an address that the
+ * kernel can use.
+ */
+#define __bus_to_virt(a) __phys_to_virt(a)
+
+#endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h
new file mode 100644
index 00000000000..85c49c9e5d1
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mx31.h
@@ -0,0 +1,335 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_MX31_H__
+#define __ASM_ARCH_MXC_MX31_H__
+
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#error "Do not include directly."
+#endif
+
+/*!
+ * defines the hardware clock tick rate
+ */
+#define CLOCK_TICK_RATE 16625000
+
+/*
+ * MX31 memory map:
+ *
+ * Virt Phys Size What
+ * ---------------------------------------------------------------------------
+ * F8000000 1FFC0000 16K IRAM
+ * F9000000 30000000 256M L2CC
+ * FC000000 43F00000 1M AIPS 1
+ * FC100000 50000000 1M SPBA
+ * FC200000 53F00000 1M AIPS 2
+ * FC500000 60000000 128M ROMPATCH
+ * FC400000 68000000 128M AVIC
+ * 70000000 256M IPU (MAX M2)
+ * 80000000 256M CSD0 SDRAM/DDR
+ * 90000000 256M CSD1 SDRAM/DDR
+ * A0000000 128M CS0 Flash
+ * A8000000 128M CS1 Flash
+ * B0000000 32M CS2
+ * B2000000 32M CS3
+ * F4000000 B4000000 32M CS4
+ * B6000000 32M CS5
+ * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
+ * C0000000 64M PCMCIA/CF
+ */
+
+#define CS0_BASE_ADDR 0xA0000000
+#define CS1_BASE_ADDR 0xA8000000
+#define CS2_BASE_ADDR 0xB0000000
+#define CS3_BASE_ADDR 0xB2000000
+
+#define CS4_BASE_ADDR 0xB4000000
+#define CS4_BASE_ADDR_VIRT 0xF4000000
+#define CS4_SIZE SZ_32M
+
+#define CS5_BASE_ADDR 0xB6000000
+#define PCMCIA_MEM_BASE_ADDR 0xBC000000
+
+/*
+ * IRAM
+ */
+#define IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */
+#define IRAM_BASE_ADDR_VIRT 0xF8000000
+#define IRAM_SIZE SZ_16K
+
+/*
+ * L2CC
+ */
+#define L2CC_BASE_ADDR 0x30000000
+#define L2CC_BASE_ADDR_VIRT 0xF9000000
+#define L2CC_SIZE SZ_1M
+
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR 0x43F00000
+#define AIPS1_BASE_ADDR_VIRT 0xFC000000
+#define AIPS1_SIZE SZ_1M
+
+#define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000)
+#define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000)
+#define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000)
+#define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000)
+#define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000)
+#define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000)
+#define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
+#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
+#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
+#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
+#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
+#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
+#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
+#define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
+#define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
+#define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
+#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
+#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
+#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
+#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
+#define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
+#define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
+
+/*
+ * SPBA global module enabled #0
+ */
+#define SPBA0_BASE_ADDR 0x50000000
+#define SPBA0_BASE_ADDR_VIRT 0xFC100000
+#define SPBA0_SIZE SZ_1M
+
+#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
+#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
+#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
+#define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
+#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
+#define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000)
+#define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000)
+#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
+#define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
+#define MSHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
+#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR 0x53F00000
+#define AIPS2_BASE_ADDR_VIRT 0xFC200000
+#define AIPS2_SIZE SZ_1M
+#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
+#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
+#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000)
+#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
+#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
+#define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
+#define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
+#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
+#define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000)
+#define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000)
+#define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
+#define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
+#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
+#define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
+#define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
+#define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
+#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000)
+#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
+#define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
+#define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
+#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
+
+/*
+ * ROMP and AVIC
+ */
+#define ROMP_BASE_ADDR 0x60000000
+#define ROMP_BASE_ADDR_VIRT 0xFC500000
+#define ROMP_SIZE SZ_1M
+
+#define AVIC_BASE_ADDR 0x68000000
+#define AVIC_BASE_ADDR_VIRT 0xFC400000
+#define AVIC_SIZE SZ_1M
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define X_MEMC_BASE_ADDR 0xB8000000
+#define X_MEMC_BASE_ADDR_VIRT 0xFC320000
+#define X_MEMC_SIZE SZ_64K
+
+#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000)
+#define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
+#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
+#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
+#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
+#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
+
+/*
+ * Memory regions and CS
+ */
+#define IPU_MEM_BASE_ADDR 0x70000000
+#define CSD0_BASE_ADDR 0x80000000
+#define CSD1_BASE_ADDR 0x90000000
+#define CS0_BASE_ADDR 0xA0000000
+#define CS1_BASE_ADDR 0xA8000000
+#define CS2_BASE_ADDR 0xB0000000
+#define CS3_BASE_ADDR 0xB2000000
+
+#define CS4_BASE_ADDR 0xB4000000
+#define CS4_BASE_ADDR_VIRT 0xF4000000
+#define CS4_SIZE SZ_32M
+
+#define CS5_BASE_ADDR 0xB6000000
+#define PCMCIA_MEM_BASE_ADDR 0xBC000000
+
+/*!
+ * This macro defines the physical to virtual address mapping for all the
+ * peripheral modules. It is used by passing in the physical address as x
+ * and returning the virtual address. If the physical address is not mapped,
+ * it returns 0xDEADBEEF
+ */
+#define IO_ADDRESS(x) \
+ (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
+ ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
+ ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
+ ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
+ ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
+ ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
+ ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
+ ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
+ ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
+ 0xDEADBEEF)
+
+/*
+ * define the address mapping macros: in physical address order
+ */
+
+#define IRAM_IO_ADDRESS(x) \
+ (((x) - IRAM_BASE_ADDR) + IRAM_BASE_ADDR_VIRT)
+
+#define L2CC_IO_ADDRESS(x) \
+ (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
+
+#define AIPS1_IO_ADDRESS(x) \
+ (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
+
+#define SPBA0_IO_ADDRESS(x) \
+ (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
+
+#define AIPS2_IO_ADDRESS(x) \
+ (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
+
+#define ROMP_IO_ADDRESS(x) \
+ (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
+
+#define AVIC_IO_ADDRESS(x) \
+ (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
+
+#define CS4_IO_ADDRESS(x) \
+ (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
+
+#define X_MEMC_IO_ADDRESS(x) \
+ (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+
+#define PCMCIA_IO_ADDRESS(x) \
+ (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+
+/* Start of physical RAM - On many MX31 platforms, this is the first SDRAM bank (CSD0) */
+#define PHYS_OFFSET CSD0_BASE_ADDR
+
+/*
+ * Interrupt numbers
+ */
+#define MXC_INT_PEN_ADS7843 0
+#define MXC_INT_RESV1 1
+#define MXC_INT_CS8900A 2
+#define MXC_INT_I2C3 3
+#define MXC_INT_I2C2 4
+#define MXC_INT_MPEG4_ENCODER 5
+#define MXC_INT_RTIC 6
+#define MXC_INT_FIRI 7
+#define MXC_INT_MMC_SDHC2 8
+#define MXC_INT_MMC_SDHC1 9
+#define MXC_INT_I2C 10
+#define MXC_INT_SSI2 11
+#define MXC_INT_SSI1 12
+#define MXC_INT_CSPI2 13
+#define MXC_INT_CSPI1 14
+#define MXC_INT_ATA 15
+#define MXC_INT_MBX 16
+#define MXC_INT_CSPI3 17
+#define MXC_INT_UART3 18
+#define MXC_INT_IIM 19
+#define MXC_INT_SIM2 20
+#define MXC_INT_SIM1 21
+#define MXC_INT_RNGA 22
+#define MXC_INT_EVTMON 23
+#define MXC_INT_KPP 24
+#define MXC_INT_RTC 25
+#define MXC_INT_PWM 26
+#define MXC_INT_EPIT2 27
+#define MXC_INT_EPIT1 28
+#define MXC_INT_GPT 29
+#define MXC_INT_RESV30 30
+#define MXC_INT_RESV31 31
+#define MXC_INT_UART2 32
+#define MXC_INT_NANDFC 33
+#define MXC_INT_SDMA 34
+#define MXC_INT_USB1 35
+#define MXC_INT_USB2 36
+#define MXC_INT_USB3 37
+#define MXC_INT_USB4 38
+#define MXC_INT_MSHC1 39
+#define MXC_INT_MSHC2 40
+#define MXC_INT_IPU_ERR 41
+#define MXC_INT_IPU_SYN 42
+#define MXC_INT_RESV43 43
+#define MXC_INT_RESV44 44
+#define MXC_INT_UART1 45
+#define MXC_INT_UART4 46
+#define MXC_INT_UART5 47
+#define MXC_INT_ECT 48
+#define MXC_INT_SCC_SCM 49
+#define MXC_INT_SCC_SMN 50
+#define MXC_INT_GPIO2 51
+#define MXC_INT_GPIO1 52
+#define MXC_INT_CCM 53
+#define MXC_INT_PCMCIA 54
+#define MXC_INT_WDOG 55
+#define MXC_INT_GPIO3 56
+#define MXC_INT_RESV57 57
+#define MXC_INT_EXT_POWER 58
+#define MXC_INT_EXT_TEMPER 59
+#define MXC_INT_EXT_SENSOR60 60
+#define MXC_INT_EXT_SENSOR61 61
+#define MXC_INT_EXT_WDOG 62
+#define MXC_INT_EXT_TV 63
+
+#define MXC_MAX_INT_LINES 64
+
+#define MXC_GPIO_INT_BASE MXC_MAX_INT_LINES
+
+/*!
+ * Number of GPIO port as defined in the IC Spec
+ */
+#define GPIO_PORT_NUM 3
+/*!
+ * Number of GPIO pins per port
+ */
+#define GPIO_NUM_PIN 32
+
+#define PROD_SIGNATURE 0x1 /* For MX31 */
+
+#define SYSTEM_REV_MIN CHIP_REV_1_0
+#define SYSTEM_REV_NUM 3
+
+#endif /* __ASM_ARCH_MXC_MX31_H__ */
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
new file mode 100644
index 00000000000..0837f1f9ca3
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_H__
+#define __ASM_ARCH_MXC_H__
+
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#error "Do not include directly."
+#endif
+
+/*
+ *****************************************
+ * GPT Register definitions *
+ *****************************************
+ */
+#define MXC_GPT_GPTCR IO_ADDRESS(GPT1_BASE_ADDR + 0x00)
+#define MXC_GPT_GPTPR IO_ADDRESS(GPT1_BASE_ADDR + 0x04)
+#define MXC_GPT_GPTSR IO_ADDRESS(GPT1_BASE_ADDR + 0x08)
+#define MXC_GPT_GPTIR IO_ADDRESS(GPT1_BASE_ADDR + 0x0C)
+#define MXC_GPT_GPTOCR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x10)
+#define MXC_GPT_GPTOCR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x14)
+#define MXC_GPT_GPTOCR3 IO_ADDRESS(GPT1_BASE_ADDR + 0x18)
+#define MXC_GPT_GPTICR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x1C)
+#define MXC_GPT_GPTICR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
+#define MXC_GPT_GPTCNT IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
+
+/*!
+ * GPT Control register bit definitions
+ */
+#define GPTCR_FO3 (1 << 31)
+#define GPTCR_FO2 (1 << 30)
+#define GPTCR_FO1 (1 << 29)
+
+#define GPTCR_OM3_SHIFT 26
+#define GPTCR_OM3_MASK (7 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_DISCONNECTED (0 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_TOGGLE (1 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_CLEAR (2 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_SET (3 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_GENERATE_LOW (7 << GPTCR_OM3_SHIFT)
+
+#define GPTCR_OM2_SHIFT 23
+#define GPTCR_OM2_MASK (7 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_DISCONNECTED (0 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_TOGGLE (1 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_CLEAR (2 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_SET (3 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_GENERATE_LOW (7 << GPTCR_OM2_SHIFT)
+
+#define GPTCR_OM1_SHIFT 20
+#define GPTCR_OM1_MASK (7 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_DISCONNECTED (0 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_TOGGLE (1 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_CLEAR (2 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_SET (3 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_GENERATE_LOW (7 << GPTCR_OM1_SHIFT)
+
+#define GPTCR_IM2_SHIFT 18
+#define GPTCR_IM2_MASK (3 << GPTCR_IM2_SHIFT)
+#define GPTCR_IM2_CAPTURE_DISABLE (0 << GPTCR_IM2_SHIFT)
+#define GPTCR_IM2_CAPTURE_RISING (1 << GPTCR_IM2_SHIFT)
+#define GPTCR_IM2_CAPTURE_FALLING (2 << GPTCR_IM2_SHIFT)
+#define GPTCR_IM2_CAPTURE_BOTH (3 << GPTCR_IM2_SHIFT)
+
+#define GPTCR_IM1_SHIFT 16
+#define GPTCR_IM1_MASK (3 << GPTCR_IM1_SHIFT)
+#define GPTCR_IM1_CAPTURE_DISABLE (0 << GPTCR_IM1_SHIFT)
+#define GPTCR_IM1_CAPTURE_RISING (1 << GPTCR_IM1_SHIFT)
+#define GPTCR_IM1_CAPTURE_FALLING (2 << GPTCR_IM1_SHIFT)
+#define GPTCR_IM1_CAPTURE_BOTH (3 << GPTCR_IM1_SHIFT)
+
+#define GPTCR_SWR (1 << 15)
+#define GPTCR_FRR (1 << 9)
+
+#define GPTCR_CLKSRC_SHIFT 6
+#define GPTCR_CLKSRC_MASK (7 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_NOCLOCK (0 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_HIGHFREQ (2 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_CLKIN (3 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_CLK32K (7 << GPTCR_CLKSRC_SHIFT)
+
+#define GPTCR_STOPEN (1 << 5)
+#define GPTCR_DOZEN (1 << 4)
+#define GPTCR_WAITEN (1 << 3)
+#define GPTCR_DBGEN (1 << 2)
+
+#define GPTCR_ENMOD (1 << 1)
+#define GPTCR_ENABLE (1 << 0)
+
+#define GPTSR_OF1 (1 << 0)
+#define GPTSR_OF2 (1 << 1)
+#define GPTSR_OF3 (1 << 2)
+#define GPTSR_IF1 (1 << 3)
+#define GPTSR_IF2 (1 << 4)
+#define GPTSR_ROV (1 << 5)
+
+#define GPTIR_OF1IE GPTSR_OF1
+#define GPTIR_OF2IE GPTSR_OF2
+#define GPTIR_OF3IE GPTSR_OF3
+#define GPTIR_IF1IE GPTSR_IF1
+#define GPTIR_IF2IE GPTSR_IF2
+#define GPTIR_ROVIE GPTSR_ROV
+
+/*
+ *****************************************
+ * AVIC Registers *
+ *****************************************
+ */
+#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
+#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
+#define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */
+#define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */
+#define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */
+#define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */
+#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */
+#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */
+#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */
+#define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */
+#define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */
+#define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */
+#define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */
+#define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */
+#define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */
+#define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */
+#define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */
+#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */
+#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */
+#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */
+#define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */
+#define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */
+#define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */
+#define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */
+#define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */
+#define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */
+#define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */
+
+#define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20)
+#define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24)
+#define IIM_PROD_REV_SH 3
+#define IIM_PROD_REV_LEN 5
+
+#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/include/asm-arm/arch-mxc/system.h b/include/asm-arm/arch-mxc/system.h
new file mode 100644
index 00000000000..109956b41ac
--- /dev/null
+++ b/include/asm-arm/arch-mxc/system.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_MXC_SYSTEM_H__
+#define __ASM_ARCH_MXC_SYSTEM_H__
+
+/*!
+ * @file system.h
+ * @brief This file contains idle and reset functions.
+ *
+ * @ingroup System
+ */
+
+/*!
+ * This function puts the CPU into idle mode. It is called by default_idle()
+ * in process.c file.
+ */
+static inline void arch_idle(void)
+{
+ cpu_do_idle();
+}
+
+/*
+ * This function resets the system. It is called by machine_restart().
+ *
+ * @param mode indicates different kinds of resets
+ */
+static inline void arch_reset(char mode)
+{
+ cpu_reset(0);
+}
+
+#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */
diff --git a/include/asm-arm/arch-mxc/timex.h b/include/asm-arm/arch-mxc/timex.h
new file mode 100644
index 00000000000..59019fa58f8
--- /dev/null
+++ b/include/asm-arm/arch-mxc/timex.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_MXC_TIMEX_H__
+#define __ASM_ARCH_MXC_TIMEX_H__
+
+#include <asm/hardware.h> /* for CLOCK_TICK_RATE */
+
+#endif /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/include/asm-arm/arch-mxc/uncompress.h b/include/asm-arm/arch-mxc/uncompress.h
new file mode 100644
index 00000000000..ec5787d0e78
--- /dev/null
+++ b/include/asm-arm/arch-mxc/uncompress.h
@@ -0,0 +1,79 @@
+/*
+ * include/asm-arm/arch-mxc/uncompress.h
+ *
+ *
+ *
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
+#define __ASM_ARCH_MXC_UNCOMPRESS_H__
+
+#define __MXC_BOOT_UNCOMPRESS
+
+#include <asm/hardware.h>
+#include <asm/processor.h>
+
+#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
+
+#define USR2 0x98
+#define USR2_TXFE (1<<14)
+#define TXR 0x40
+#define UCR1 0x80
+#define UCR1_UARTEN 1
+
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader. We search for the first enabled
+ * port in the most probable order. If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ *
+ * This does not append a newline
+ */
+
+static void putc(int ch)
+{
+ static unsigned long serial_port = 0;
+
+ if (unlikely(serial_port == 0)) {
+ do {
+ serial_port = UART1_BASE_ADDR;
+ if (UART(UCR1) & UCR1_UARTEN)
+ break;
+ serial_port = UART2_BASE_ADDR;
+ if (UART(UCR1) & UCR1_UARTEN)
+ break;
+ return;
+ } while (0);
+ }
+
+ while (!(UART(USR2) & USR2_TXFE))
+ cpu_relax();
+
+ UART(TXR) = ch;
+}
+
+#define flush() do { } while (0)
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
+
+#endif /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */
diff --git a/include/asm-arm/arch-mxc/vmalloc.h b/include/asm-arm/arch-mxc/vmalloc.h
new file mode 100644
index 00000000000..83a73da895e
--- /dev/null
+++ b/include/asm-arm/arch-mxc/vmalloc.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2000 Russell King.
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_MXC_VMALLOC_H__
+#define __ASM_ARCH_MXC_VMALLOC_H__
+
+/*!
+ * @file vmalloc.h
+ *
+ * @brief This file contains platform specific macros for vmalloc.
+ *
+ * @ingroup System
+ */
+
+/*!
+ * vmalloc ending address
+ */
+#define VMALLOC_END 0xF4000000
+
+#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */
diff --git a/include/asm-arm/arch-ns9xxx/regs-bbu.h b/include/asm-arm/arch-ns9xxx/regs-bbu.h
index e2626954624..7ee194dc635 100644
--- a/include/asm-arm/arch-ns9xxx/regs-bbu.h
+++ b/include/asm-arm/arch-ns9xxx/regs-bbu.h
@@ -15,7 +15,31 @@
/* BBus Utility */
-/* GPIO Configuration Register */
-#define BBU_GC(x) __REG2(0x9060000c, (x))
+/* GPIO Configuration Registers block 1 */
+/* NOTE: the HRM starts counting at 1 for the GPIO registers, here the start is
+ * at 0 for each block. That is, BBU_GCONFb1(0) is GPIO Configuration Register
+ * #1, BBU_GCONFb2(0) is GPIO Configuration Register #8. */
+#define BBU_GCONFb1(x) __REG2(0x90600010, (x))
+#define BBU_GCONFb2(x) __REG2(0x90600100, (x))
+
+#define BBU_GCONFx_DIR(m) __REGBIT(3 + (((m) & 7) << 2))
+#define BBU_GCONFx_DIR_INPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 0)
+#define BBU_GCONFx_DIR_OUTPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 1)
+#define BBU_GCONFx_INV(m) __REGBIT(2 + (((m) & 7) << 2))
+#define BBU_GCONFx_INV_NO(m) __REGVAL(BBU_GCONFx_INV(m), 0)
+#define BBU_GCONFx_INV_YES(m) __REGVAL(BBU_GCONFx_INV(m), 1)
+#define BBU_GCONFx_FUNC(m) __REGBITS(1 + (((m) & 7) << 2), ((m) & 7) << 2)
+#define BBU_GCONFx_FUNC_0(m) __REGVAL(BBU_GCONFx_FUNC(m), 0)
+#define BBU_GCONFx_FUNC_1(m) __REGVAL(BBU_GCONFx_FUNC(m), 1)
+#define BBU_GCONFx_FUNC_2(m) __REGVAL(BBU_GCONFx_FUNC(m), 2)
+#define BBU_GCONFx_FUNC_3(m) __REGVAL(BBU_GCONFx_FUNC(m), 3)
+
+#define BBU_GCTRL1 __REG(0x90600030)
+#define BBU_GCTRL2 __REG(0x90600034)
+#define BBU_GCTRL3 __REG(0x90600120)
+
+#define BBU_GSTAT1 __REG(0x90600040)
+#define BBU_GSTAT2 __REG(0x90600044)
+#define BBU_GSTAT3 __REG(0x90600130)
#endif /* ifndef __ASM_ARCH_REGSBBU_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-mem.h b/include/asm-arm/arch-ns9xxx/regs-mem.h
index 8ed8448767b..fb455a0ed84 100644
--- a/include/asm-arm/arch-ns9xxx/regs-mem.h
+++ b/include/asm-arm/arch-ns9xxx/regs-mem.h
@@ -79,9 +79,9 @@
#define MEM_SMC(x) __REG2(0xa0700200, (x) << 3)
/* Static Memory Configuration Register x: Write protect */
-#define MEM_SMC_WSMC __REGBIT(20)
-#define MEM_SMC_WSMC_OFF __REGVAL(MEM_SMC_WSMC, 0)
-#define MEM_SMC_WSMC_ON __REGVAL(MEM_SMC_WSMC, 1)
+#define MEM_SMC_PSMC __REGBIT(20)
+#define MEM_SMC_PSMC_OFF __REGVAL(MEM_SMC_PSMC, 0)
+#define MEM_SMC_PSMC_ON __REGVAL(MEM_SMC_PSMC, 1)
/* Static Memory Configuration Register x: Buffer enable */
#define MEM_SMC_BSMC __REGBIT(19)
diff --git a/include/asm-arm/arch-ns9xxx/regs-sys.h b/include/asm-arm/arch-ns9xxx/regs-sys.h
index a42546aeb92..749262f8620 100644
--- a/include/asm-arm/arch-ns9xxx/regs-sys.h
+++ b/include/asm-arm/arch-ns9xxx/regs-sys.h
@@ -64,7 +64,7 @@
/* Timer x Control register: Timer enable */
#define SYS_TCx_TEN __REGBIT(15)
-#define SYS_TCx_TEN_DIS __REGVAL(SYS_TCx_TEN, 1)
+#define SYS_TCx_TEN_DIS __REGVAL(SYS_TCx_TEN, 0)
#define SYS_TCx_TEN_EN __REGVAL(SYS_TCx_TEN, 1)
/* Timer x Control register: CPU debug mode */
diff --git a/include/asm-arm/arch-pxa/pm.h b/include/asm-arm/arch-pxa/pm.h
index 52243a62c4e..6903db7fae1 100644
--- a/include/asm-arm/arch-pxa/pm.h
+++ b/include/asm-arm/arch-pxa/pm.h
@@ -7,5 +7,19 @@
*
*/
-extern int pxa_pm_prepare(suspend_state_t state);
+struct pxa_cpu_pm_fns {
+ int save_size;
+ void (*save)(unsigned long *);
+ void (*restore)(unsigned long *);
+ int (*valid)(suspend_state_t state);
+ void (*enter)(suspend_state_t state);
+};
+
+extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns;
+
+/* sleep.S */
+extern void pxa25x_cpu_suspend(unsigned int);
+extern void pxa27x_cpu_suspend(unsigned int);
+extern void pxa_cpu_resume(void);
+
extern int pxa_pm_enter(suspend_state_t state);
diff --git a/include/asm-arm/arch-s3c2400/map.h b/include/asm-arm/arch-s3c2400/map.h
new file mode 100644
index 00000000000..1184d907b31
--- /dev/null
+++ b/include/asm-arm/arch-s3c2400/map.h
@@ -0,0 +1,66 @@
+/* linux/include/asm-arm/arch-s3c2400/map.h
+ *
+ * Copyright 2003,2007 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * Copyright 2003, Lucas Correia Villa Real
+ *
+ * S3C2400 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C2400_PA_MEMCTRL (0x14000000)
+#define S3C2400_PA_USBHOST (0x14200000)
+#define S3C2400_PA_IRQ (0x14400000)
+#define S3C2400_PA_DMA (0x14600000)
+#define S3C2400_PA_CLKPWR (0x14800000)
+#define S3C2400_PA_LCD (0x14A00000)
+#define S3C2400_PA_UART (0x15000000)
+#define S3C2400_PA_TIMER (0x15100000)
+#define S3C2400_PA_USBDEV (0x15200140)
+#define S3C2400_PA_WATCHDOG (0x15300000)
+#define S3C2400_PA_IIC (0x15400000)
+#define S3C2400_PA_IIS (0x15508000)
+#define S3C2400_PA_GPIO (0x15600000)
+#define S3C2400_PA_RTC (0x15700040)
+#define S3C2400_PA_ADC (0x15800000)
+#define S3C2400_PA_SPI (0x15900000)
+
+#define S3C2400_PA_MMC (0x15A00000)
+#define S3C2400_SZ_MMC SZ_1M
+
+/* physical addresses of all the chip-select areas */
+
+#define S3C2400_CS0 (0x00000000)
+#define S3C2400_CS1 (0x02000000)
+#define S3C2400_CS2 (0x04000000)
+#define S3C2400_CS3 (0x06000000)
+#define S3C2400_CS4 (0x08000000)
+#define S3C2400_CS5 (0x0A000000)
+#define S3C2400_CS6 (0x0C000000)
+#define S3C2400_CS7 (0x0E000000)
+
+#define S3C2400_SDRAM_PA (S3C2400_CS6)
+
+/* Use a single interface for common resources between S3C24XX cpus */
+
+#define S3C24XX_PA_IRQ S3C2400_PA_IRQ
+#define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL
+#define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST
+#define S3C24XX_PA_DMA S3C2400_PA_DMA
+#define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR
+#define S3C24XX_PA_LCD S3C2400_PA_LCD
+#define S3C24XX_PA_UART S3C2400_PA_UART
+#define S3C24XX_PA_TIMER S3C2400_PA_TIMER
+#define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV
+#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
+#define S3C24XX_PA_IIC S3C2400_PA_IIC
+#define S3C24XX_PA_IIS S3C2400_PA_IIS
+#define S3C24XX_PA_GPIO S3C2400_PA_GPIO
+#define S3C24XX_PA_RTC S3C2400_PA_RTC
+#define S3C24XX_PA_ADC S3C2400_PA_ADC
+#define S3C24XX_PA_SPI S3C2400_PA_SPI
diff --git a/include/asm-arm/arch-s3c2400/memory.h b/include/asm-arm/arch-s3c2400/memory.h
new file mode 100644
index 00000000000..fb0381dde70
--- /dev/null
+++ b/include/asm-arm/arch-s3c2400/memory.h
@@ -0,0 +1,23 @@
+/* linux/include/asm-arm/arch-s3c2400/memory.h
+ * from linux/include/asm-arm/arch-rpc/memory.h
+ *
+ * Copyright 2007 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * Copyright (C) 1996,1997,1998 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET UL(0x0C000000)
+
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S
index 93064860e0e..9c8cd9abb82 100644
--- a/include/asm-arm/arch-s3c2410/debug-macro.S
+++ b/include/asm-arm/arch-s3c2410/debug-macro.S
@@ -13,32 +13,23 @@
*/
#include <asm/arch/map.h>
-#include <asm/arch/regs-serial.h>
#include <asm/arch/regs-gpio.h>
+#include <asm/plat-s3c/regs-serial.h>
#define S3C2410_UART1_OFF (0x4000)
#define SHIFT_2440TXF (14-9)
- .macro addruart, rx
+ .macro addruart, rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1
ldreq \rx, = S3C24XX_PA_UART
ldrne \rx, = S3C24XX_VA_UART
-#if CONFIG_DEBUG_S3C2410_UART != 0
- add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C2410_UART)
+#if CONFIG_DEBUG_S3C_UART != 0
+ add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
#endif
- .endm
+ .endm
- .macro senduart,rd,rx
- strb \rd, [\rx, # S3C2410_UTXH ]
- .endm
-
- .macro busyuart, rd, rx
- ldr \rd, [ \rx, # S3C2410_UFCON ]
- tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
- beq 1001f @
- @ FIFO enabled...
-1003:
+ .macro fifo_full_s3c24xx rd, rx
@ check for arm920 vs arm926. currently assume all arm926
@ devices have an 64 byte FIFO identical to the s3c2440
mrc p15, 0, \rd, c0, c0
@@ -57,25 +48,22 @@
ldr \rd, [ \rx, # S3C2410_UFSTAT ]
moveq \rd, \rd, lsr #SHIFT_2440TXF
tst \rd, #S3C2410_UFSTAT_TXFULL
- bne 1003b
- b 1002f
-
-1001:
- @ busy waiting for non fifo
- ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
- tst \rd, #S3C2410_UTRSTAT_TXFE
- beq 1001b
+ .endm
-1002: @ exit busyuart
- .endm
+ .macro fifo_full_s3c2410 rd, rx
+ ldr \rd, [ \rx, # S3C2410_UFSTAT ]
+ tst \rd, #S3C2410_UFSTAT_TXFULL
+ .endm
- .macro waituart,rd,rx
+/* fifo level reading */
- ldr \rd, [ \rx, # S3C2410_UFCON ]
- tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
- beq 1001f @
- @ FIFO enabled...
-1003:
+ .macro fifo_level_s3c24xx rd, rx
+ @ check for arm920 vs arm926. currently assume all arm926
+ @ devices have an 64 byte FIFO identical to the s3c2440
+ mrc p15, 0, \rd, c0, c0
+ and \rd, \rd, #0xff0
+ teq \rd, #0x260
+ beq 10000f
mrc p15, 0, \rd, c1, c0
tst \rd, #1
addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
@@ -85,18 +73,32 @@
and \rd, \rd, #0x00ff0000
teq \rd, #0x00440000 @ is it 2440?
+10000:
ldr \rd, [ \rx, # S3C2410_UFSTAT ]
andne \rd, \rd, #S3C2410_UFSTAT_TXMASK
andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK
- teq \rd, #0
- bne 1003b
- b 1002f
+ .endm
+
+ .macro fifo_level_s3c2410 rd, rx
+ ldr \rd, [ \rx, # S3C2410_UFSTAT ]
+ and \rd, \rd, #S3C2410_UFSTAT_TXMASK
+ .endm
+
+/* Select the correct implementation depending on the configuration. The
+ * S3C2440 will get selected by default, as these are the most widely
+ * used variants of these
+*/
+
+#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY)
+#define fifo_full fifo_full_s3c2410
+#define fifo_level fifo_level_s3c2410
+#warning 2410only
+#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY)
+#define fifo_full fifo_full_s3c24xx
+#define fifo_level fifo_level_s3c24xx
+#warning generic
+#endif
-1001:
- @ idle waiting for non fifo
- ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
- tst \rd, #S3C2410_UTRSTAT_TXFE
- beq 1001b
+/* include the reset of the code which will do the work */
-1002: @ exit busyuart
- .endm
+#include <asm/plat-s3c/debug-macro.S>
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
index 19e77f03804..b33ed3b05ef 100644
--- a/include/asm-arm/arch-s3c2410/map.h
+++ b/include/asm-arm/arch-s3c2410/map.h
@@ -13,58 +13,36 @@
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H
-/* we have a bit of a tight squeeze to fit all our registers from
- * 0xF00000000 upwards, since we use all of the nGCS space in some
- * capacity, and also need to fit the S3C2410 registers in as well...
- *
- * we try to ensure stuff like the IRQ registers are available for
- * an single MOVS instruction (ie, only 8 bits of set data)
- *
- * Note, we are trying to remove some of these from the implementation
- * as they are only useful to certain drivers...
- */
-
-#ifndef __ASSEMBLY__
-#define S3C2410_ADDR(x) ((void __iomem __force *)0xF0000000 + (x))
-#else
-#define S3C2410_ADDR(x) (0xF0000000 + (x))
-#endif
+#include <asm/plat-s3c/map.h>
-#define S3C2400_ADDR(x) S3C2410_ADDR(x)
+#define S3C2410_ADDR(x) S3C_ADDR(x)
/* interrupt controller is the first thing we put in, to make
* the assembly code for the irq detection easier
*/
-#define S3C24XX_VA_IRQ S3C2410_ADDR(0x00000000)
-#define S3C2400_PA_IRQ (0x14400000)
+#define S3C24XX_VA_IRQ S3C_VA_IRQ
#define S3C2410_PA_IRQ (0x4A000000)
#define S3C24XX_SZ_IRQ SZ_1M
/* memory controller registers */
-#define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000)
-#define S3C2400_PA_MEMCTRL (0x14000000)
+#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
#define S3C2410_PA_MEMCTRL (0x48000000)
#define S3C24XX_SZ_MEMCTRL SZ_1M
/* USB host controller */
-#define S3C2400_PA_USBHOST (0x14200000)
#define S3C2410_PA_USBHOST (0x49000000)
#define S3C24XX_SZ_USBHOST SZ_1M
/* DMA controller */
-#define S3C2400_PA_DMA (0x14600000)
#define S3C2410_PA_DMA (0x4B000000)
#define S3C24XX_SZ_DMA SZ_1M
/* Clock and Power management */
-#define S3C24XX_VA_CLKPWR S3C2410_ADDR(0x00200000)
-#define S3C2400_PA_CLKPWR (0x14800000)
+#define S3C24XX_VA_CLKPWR S3C_VA_SYS
#define S3C2410_PA_CLKPWR (0x4C000000)
#define S3C24XX_SZ_CLKPWR SZ_1M
/* LCD controller */
-#define S3C24XX_VA_LCD S3C2410_ADDR(0x00300000)
-#define S3C2400_PA_LCD (0x14A00000)
#define S3C2410_PA_LCD (0x4D000000)
#define S3C24XX_SZ_LCD SZ_1M
@@ -72,41 +50,30 @@
#define S3C2410_PA_NAND (0x4E000000)
#define S3C24XX_SZ_NAND SZ_1M
-/* MMC controller - available on the S3C2400 */
-#define S3C2400_PA_MMC (0x15A00000)
-#define S3C2400_SZ_MMC SZ_1M
-
/* UARTs */
-#define S3C24XX_VA_UART S3C2410_ADDR(0x00400000)
-#define S3C2400_PA_UART (0x15000000)
+#define S3C24XX_VA_UART S3C_VA_UART
#define S3C2410_PA_UART (0x50000000)
#define S3C24XX_SZ_UART SZ_1M
/* Timers */
-#define S3C24XX_VA_TIMER S3C2410_ADDR(0x00500000)
-#define S3C2400_PA_TIMER (0x15100000)
+#define S3C24XX_VA_TIMER S3C_VA_TIMER
#define S3C2410_PA_TIMER (0x51000000)
#define S3C24XX_SZ_TIMER SZ_1M
/* USB Device port */
-#define S3C24XX_VA_USBDEV S3C2410_ADDR(0x00600000)
-#define S3C2400_PA_USBDEV (0x15200140)
#define S3C2410_PA_USBDEV (0x52000000)
#define S3C24XX_SZ_USBDEV SZ_1M
/* Watchdog */
-#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000)
-#define S3C2400_PA_WATCHDOG (0x15300000)
+#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
#define S3C2410_PA_WATCHDOG (0x53000000)
#define S3C24XX_SZ_WATCHDOG SZ_1M
/* IIC hardware controller */
-#define S3C2400_PA_IIC (0x15400000)
#define S3C2410_PA_IIC (0x54000000)
#define S3C24XX_SZ_IIC SZ_1M
/* IIS controller */
-#define S3C2400_PA_IIS (0x15508000)
#define S3C2410_PA_IIS (0x55000000)
#define S3C24XX_SZ_IIS SZ_1M
@@ -116,27 +83,23 @@
* it is the same distance apart from the UART in the
* phsyical address space, as the initial mapping for the IO
* is done as a 1:1 maping. This puts it (currently) at
- * 0xF6800000, which is not in the way of any current mapping
+ * 0xFA800000, which is not in the way of any current mapping
* by the base system.
*/
-#define S3C2400_PA_GPIO (0x15600000)
#define S3C2410_PA_GPIO (0x56000000)
#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
#define S3C24XX_SZ_GPIO SZ_1M
/* RTC */
-#define S3C2400_PA_RTC (0x15700040)
#define S3C2410_PA_RTC (0x57000000)
#define S3C24XX_SZ_RTC SZ_1M
/* ADC */
-#define S3C2400_PA_ADC (0x15800000)
#define S3C2410_PA_ADC (0x58000000)
#define S3C24XX_SZ_ADC SZ_1M
/* SPI */
-#define S3C2400_PA_SPI (0x15900000)
#define S3C2410_PA_SPI (0x59000000)
#define S3C24XX_SZ_SPI SZ_1M
@@ -177,37 +140,8 @@
#define S3C2410_SDRAM_PA (S3C2410_CS6)
-#define S3C2400_CS0 (0x00000000)
-#define S3C2400_CS1 (0x02000000)
-#define S3C2400_CS2 (0x04000000)
-#define S3C2400_CS3 (0x06000000)
-#define S3C2400_CS4 (0x08000000)
-#define S3C2400_CS5 (0x0A000000)
-#define S3C2400_CS6 (0x0C000000)
-#define S3C2400_CS7 (0x0E000000)
-
-#define S3C2400_SDRAM_PA (S3C2400_CS6)
-
/* Use a single interface for common resources between S3C24XX cpus */
-#ifdef CONFIG_CPU_S3C2400
-#define S3C24XX_PA_IRQ S3C2400_PA_IRQ
-#define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL
-#define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST
-#define S3C24XX_PA_DMA S3C2400_PA_DMA
-#define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR
-#define S3C24XX_PA_LCD S3C2400_PA_LCD
-#define S3C24XX_PA_UART S3C2400_PA_UART
-#define S3C24XX_PA_TIMER S3C2400_PA_TIMER
-#define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV
-#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
-#define S3C24XX_PA_IIC S3C2400_PA_IIC
-#define S3C24XX_PA_IIS S3C2400_PA_IIS
-#define S3C24XX_PA_GPIO S3C2400_PA_GPIO
-#define S3C24XX_PA_RTC S3C2400_PA_RTC
-#define S3C24XX_PA_ADC S3C2400_PA_ADC
-#define S3C24XX_PA_SPI S3C2400_PA_SPI
-#else
#define S3C24XX_PA_IRQ S3C2410_PA_IRQ
#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST
@@ -224,7 +158,6 @@
#define S3C24XX_PA_RTC S3C2410_PA_RTC
#define S3C24XX_PA_ADC S3C2410_PA_ADC
#define S3C24XX_PA_SPI S3C2410_PA_SPI
-#endif
/* deal with the registers that move under the 2412/2413 */
diff --git a/include/asm-arm/arch-s3c2410/memory.h b/include/asm-arm/arch-s3c2410/memory.h
index 4be6a74c430..533e2436e70 100644
--- a/include/asm-arm/arch-s3c2410/memory.h
+++ b/include/asm-arm/arch-s3c2410/memory.h
@@ -11,20 +11,7 @@
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
-/*
- * DRAM starts at 0x30000000 for S3C2410/S3C2440
- * and at 0x0C000000 for S3C2400
- */
-#ifdef CONFIG_CPU_S3C2400
-#define PHYS_OFFSET UL(0x0C000000)
-#else
#define PHYS_OFFSET UL(0x30000000)
-#endif
-
-/*
- * These are exactly the same on the S3C2410 as the
- * physical memory view.
-*/
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h
index b7faeb04c0f..76fe5f69342 100644
--- a/include/asm-arm/arch-s3c2410/regs-lcd.h
+++ b/include/asm-arm/arch-s3c2410/regs-lcd.h
@@ -12,7 +12,7 @@
#ifndef ___ASM_ARCH_REGS_LCD_H
#define ___ASM_ARCH_REGS_LCD_H "$Id: lcd.h,v 1.3 2003/06/26 13:25:06 ben Exp $"
-#define S3C2410_LCDREG(x) ((x) + S3C24XX_VA_LCD)
+#define S3C2410_LCDREG(x) (x)
/* LCD control registers */
#define S3C2410_LCDCON1 S3C2410_LCDREG(0x00)
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
index 1c74ef17da3..63891786dfa 100644
--- a/include/asm-arm/arch-s3c2410/system.h
+++ b/include/asm-arm/arch-s3c2410/system.h
@@ -17,7 +17,7 @@
#include <asm/arch/idle.h>
#include <asm/arch/reset.h>
-#include <asm/arch/regs-watchdog.h>
+#include <asm/plat-s3c/regs-watchdog.h>
#include <asm/arch/regs-clock.h>
void (*s3c24xx_idle)(void);
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
index dcb2cef38f5..48a5731ee98 100644
--- a/include/asm-arm/arch-s3c2410/uncompress.h
+++ b/include/asm-arm/arch-s3c2410/uncompress.h
@@ -1,6 +1,7 @@
/* linux/include/asm-arm/arch-s3c2410/uncompress.h
*
- * Copyright (c) 2003 Simtec Electronics
+ * Copyright (c) 2003, 2007 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - uncompress code
@@ -13,153 +14,39 @@
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
-typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
-
-/* defines for UART registers */
-#include "asm/arch/regs-serial.h"
-#include "asm/arch/regs-gpio.h"
-#include "asm/arch/regs-watchdog.h"
-
+#include <asm/arch/regs-gpio.h>
#include <asm/arch/map.h>
/* working in physical space... */
#undef S3C2410_GPIOREG
-#undef S3C2410_WDOGREG
-
#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x)))
-#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
-/* how many bytes we allow into the FIFO at a time in FIFO mode */
-#define FIFO_MAX (14)
+#include <asm/plat-s3c/uncompress.h>
-#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C2410_LOWLEVEL_UART_PORT)
-
-static __inline__ void
-uart_wr(unsigned int reg, unsigned int val)
+static inline int is_arm926(void)
{
- volatile unsigned int *ptr;
-
- ptr = (volatile unsigned int *)(reg + uart_base);
- *ptr = val;
-}
+ unsigned int cpuid;
-static __inline__ unsigned int
-uart_rd(unsigned int reg)
-{
- volatile unsigned int *ptr;
+ asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid));
- ptr = (volatile unsigned int *)(reg + uart_base);
- return *ptr;
+ return ((cpuid & 0xff0) == 0x260);
}
-
-/* we can deal with the case the UARTs are being run
- * in FIFO mode, so that we don't hold up our execution
- * waiting for tx to happen...
-*/
-
-static void putc(int ch)
+static void arch_detect_cpu(void)
{
- int cpuid = S3C2410_GSTATUS1_2410;
+ unsigned int cpuid;
-#ifndef CONFIG_CPU_S3C2400
cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
cpuid &= S3C2410_GSTATUS1_IDMASK;
-#endif
-
- if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
- int level;
-
- while (1) {
- level = uart_rd(S3C2410_UFSTAT);
-
- if (cpuid == S3C2410_GSTATUS1_2440 ||
- cpuid == S3C2410_GSTATUS1_2442) {
- level &= S3C2440_UFSTAT_TXMASK;
- level >>= S3C2440_UFSTAT_TXSHIFT;
- } else {
- level &= S3C2410_UFSTAT_TXMASK;
- level >>= S3C2410_UFSTAT_TXSHIFT;
- }
-
- if (level < FIFO_MAX)
- break;
- }
+ if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 ||
+ cpuid == S3C2410_GSTATUS1_2442) {
+ fifo_mask = S3C2440_UFSTAT_TXMASK;
+ fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
} else {
- /* not using fifos */
-
- while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
- barrier();
+ fifo_mask = S3C2410_UFSTAT_TXMASK;
+ fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT;
}
-
- /* write byte to transmission register */
- uart_wr(S3C2410_UTXH, ch);
}
-static inline void flush(void)
-{
-}
-
-#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
-
-/* CONFIG_S3C2410_BOOT_WATCHDOG
- *
- * Simple boot-time watchdog setup, to reboot the system if there is
- * any problem with the boot process
-*/
-
-#ifdef CONFIG_S3C2410_BOOT_WATCHDOG
-
-#define WDOG_COUNT (0xff00)
-
-static inline void arch_decomp_wdog(void)
-{
- __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
-}
-
-static void arch_decomp_wdog_start(void)
-{
- __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
- __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
- __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
-}
-
-#else
-#define arch_decomp_wdog_start()
-#define arch_decomp_wdog()
-#endif
-
-#ifdef CONFIG_S3C2410_BOOT_ERROR_RESET
-
-static void arch_decomp_error(const char *x)
-{
- putstr("\n\n");
- putstr(x);
- putstr("\n\n -- System resetting\n");
-
- __raw_writel(0x4000, S3C2410_WTDAT);
- __raw_writel(0x4000, S3C2410_WTCNT);
- __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
-
- while(1);
-}
-
-#define arch_error arch_decomp_error
-#endif
-
-static void error(char *err);
-
-static void
-arch_decomp_setup(void)
-{
- /* we may need to setup the uart(s) here if we are not running
- * on an BAST... the BAST will have left the uarts configured
- * after calling linux.
- */
-
- arch_decomp_wdog_start();
-}
-
-
#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/include/asm-arm/arch-sa1100/jornada720.h b/include/asm-arm/arch-sa1100/jornada720.h
new file mode 100644
index 00000000000..45d2bb59f9d
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/jornada720.h
@@ -0,0 +1,27 @@
+/*
+ * include/asm-arm/arch-sa1100/jornada720.h
+ *
+ * This file contains SSP/MCU communication definitions for HP Jornada 710/720/728
+ *
+ * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
+ * Copyright (C) 2000 John Ankcorn <jca@lcs.mit.edu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+ /* HP Jornada 7xx microprocessor commands */
+#define GETBATTERYDATA 0xc0
+#define GETSCANKEYCODE 0x90
+#define GETTOUCHSAMPLES 0xa0
+#define GETCONTRAST 0xD0
+#define SETCONTRAST 0xD1
+#define GETBRIGHTNESS 0xD2
+#define SETBRIGHTNESS 0xD3
+#define CONTRASTOFF 0xD8
+#define BRIGHTNESSOFF 0xD9
+#define PWMOFF 0xDF
+#define TXDUMMY 0x11
+#define ERRORCODE 0x00
diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h
index d7a777f0508..ec1c685562c 100644
--- a/include/asm-arm/elf.h
+++ b/include/asm-arm/elf.h
@@ -1,13 +1,14 @@
#ifndef __ASMARM_ELF_H
#define __ASMARM_ELF_H
+#include <asm/hwcap.h>
+
#ifndef __ASSEMBLY__
/*
* ELF register definitions..
*/
#include <asm/ptrace.h>
#include <asm/user.h>
-#include <asm/hwcap.h>
typedef unsigned long elf_greg_t;
typedef unsigned long elf_freg_t[3];
diff --git a/include/asm-arm/floppy.h b/include/asm-arm/floppy.h
index 54b5ae44ed9..d595c15166a 100644
--- a/include/asm-arm/floppy.h
+++ b/include/asm-arm/floppy.h
@@ -30,15 +30,21 @@
#define fd_disable_irq() disable_irq(IRQ_FLOPPYDISK)
#define fd_enable_irq() enable_irq(IRQ_FLOPPYDISK)
+static inline int fd_dma_setup(void *data, unsigned int length,
+ unsigned int mode, unsigned long addr)
+{
+ set_dma_mode(DMA_FLOPPY, mode);
+ __set_dma_addr(DMA_FLOPPY, data);
+ set_dma_count(DMA_FLOPPY, length);
+ virtual_dma_port = addr;
+ enable_dma(DMA_FLOPPY);
+ return 0;
+}
+#define fd_dma_setup fd_dma_setup
+
#define fd_request_dma() request_dma(DMA_FLOPPY,"floppy")
#define fd_free_dma() free_dma(DMA_FLOPPY)
#define fd_disable_dma() disable_dma(DMA_FLOPPY)
-#define fd_enable_dma() enable_dma(DMA_FLOPPY)
-#define fd_clear_dma_ff() clear_dma_ff(DMA_FLOPPY)
-#define fd_set_dma_mode(mode) set_dma_mode(DMA_FLOPPY, (mode))
-#define fd_set_dma_addr(addr) set_dma_addr(DMA_FLOPPY, virt_to_bus((addr)))
-#define fd_set_dma_count(len) set_dma_count(DMA_FLOPPY, (len))
-#define fd_cacheflush(addr,sz)
/* need to clean up dma.h */
#define DMA_FLOPPYDISK DMA_FLOPPY
diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h
index 81ca5d3e2bf..fb90b421f31 100644
--- a/include/asm-arm/hardware/iop3xx.h
+++ b/include/asm-arm/hardware/iop3xx.h
@@ -194,6 +194,13 @@ extern int init_atu;
#define IOP_TMR_PRIVILEGED 0x08
#define IOP_TMR_RATIO_1_1 0x00
+/* Watchdog timer definitions */
+#define IOP_WDTCR_EN_ARM 0x1e1e1e1e
+#define IOP_WDTCR_EN 0xe1e1e1e1
+/* iop3xx does not support stopping the watchdog, so we just re-arm */
+#define IOP_WDTCR_DIS_ARM (IOP_WDTCR_EN_ARM)
+#define IOP_WDTCR_DIS (IOP_WDTCR_EN)
+
/* Application accelerator unit */
#define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800)
#define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7)
@@ -274,6 +281,32 @@ static inline void write_tisr(u32 val)
asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
}
+static inline u32 read_wdtcr(void)
+{
+ u32 val;
+ asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val));
+ return val;
+}
+static inline void write_wdtcr(u32 val)
+{
+ asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val));
+}
+
+extern unsigned long get_iop_tick_rate(void);
+
+/* only iop13xx has these registers, we define these to present a
+ * common register interface for the iop_wdt driver.
+ */
+#define IOP_RCSR_WDT (0)
+static inline u32 read_rcsr(void)
+{
+ return 0;
+}
+static inline void write_wdtsr(u32 val)
+{
+ do { } while (0);
+}
+
extern struct platform_device iop3xx_dma_0_channel;
extern struct platform_device iop3xx_dma_1_channel;
extern struct platform_device iop3xx_aau_channel;
diff --git a/include/asm-arm/pgtable-nommu.h b/include/asm-arm/pgtable-nommu.h
index 0c8be19fd66..b186bc820e3 100644
--- a/include/asm-arm/pgtable-nommu.h
+++ b/include/asm-arm/pgtable-nommu.h
@@ -102,7 +102,8 @@ extern int is_in_rom(unsigned long);
#define v4_tlb_fns (0)
#define v4wb_tlb_fns (0)
#define v4wbi_tlb_fns (0)
-#define v6_tlb_fns (0)
+#define v6wbi_tlb_fns (0)
+#define v7wbi_tlb_fns (0)
#define v3_user_fns (0)
#define v4_user_fns (0)
diff --git a/include/asm-arm/plat-s3c/debug-macro.S b/include/asm-arm/plat-s3c/debug-macro.S
new file mode 100644
index 00000000000..84c40b847da
--- /dev/null
+++ b/include/asm-arm/plat-s3c/debug-macro.S
@@ -0,0 +1,75 @@
+/* linux/include/asm-arm/plat-s3c/debug-macro.S
+ *
+ * Copyright 2005, 2007 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <asm/plat-s3c/regs-serial.h>
+
+/* The S3C2440 implementations are used by default as they are the
+ * most widely re-used */
+
+ .macro fifo_level_s3c2440 rd, rx
+ ldr \rd, [ \rx, # S3C2410_UFSTAT ]
+ and \rd, \rd, #S3C2440_UFSTAT_TXMASK
+ .endm
+
+#ifndef fifo_level
+#define fifo_level fifo_level_s3c2410
+#endif
+
+ .macro fifo_full_s3c2440 rd, rx
+ ldr \rd, [ \rx, # S3C2410_UFSTAT ]
+ tst \rd, #S3C2440_UFSTAT_TXFULL
+ .endm
+
+#ifndef fifo_full
+#define fifo_full fifo_full_s3c2440
+#endif
+
+ .macro senduart,rd,rx
+ strb \rd, [\rx, # S3C2410_UTXH ]
+ .endm
+
+ .macro busyuart, rd, rx
+ ldr \rd, [ \rx, # S3C2410_UFCON ]
+ tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
+ beq 1001f @
+ @ FIFO enabled...
+1003:
+ fifo_full \rd, \rx
+ bne 1003b
+ b 1002f
+
+1001:
+ @ busy waiting for non fifo
+ ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
+ tst \rd, #S3C2410_UTRSTAT_TXFE
+ beq 1001b
+
+1002: @ exit busyuart
+ .endm
+
+ .macro waituart,rd,rx
+ ldr \rd, [ \rx, # S3C2410_UFCON ]
+ tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
+ beq 1001f @
+ @ FIFO enabled...
+1003:
+ fifo_level \rd, \rx
+ teq \rd, #0
+ bne 1003b
+ b 1002f
+1001:
+ @ idle waiting for non fifo
+ ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
+ tst \rd, #S3C2410_UTRSTAT_TXFE
+ beq 1001b
+
+1002: @ exit busyuart
+ .endm
diff --git a/include/asm-arm/arch-s3c2410/iic.h b/include/asm-arm/plat-s3c/iic.h
index 71211c8b538..71211c8b538 100644
--- a/include/asm-arm/arch-s3c2410/iic.h
+++ b/include/asm-arm/plat-s3c/iic.h
diff --git a/include/asm-arm/plat-s3c/map.h b/include/asm-arm/plat-s3c/map.h
new file mode 100644
index 00000000000..95a82b0e84a
--- /dev/null
+++ b/include/asm-arm/plat-s3c/map.h
@@ -0,0 +1,40 @@
+/* linux/include/asm-arm/plat-s3c/map.h
+ *
+ * Copyright 2003, 2007 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - Memory map definitions (virtual addresses)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_MAP_H
+#define __ASM_PLAT_MAP_H __FILE__
+
+/* Fit all our registers in at 0xF4000000 upwards, trying to use as
+ * little of the VA space as possible so vmalloc and friends have a
+ * better chance of getting memory.
+ *
+ * we try to ensure stuff like the IRQ registers are available for
+ * an single MOVS instruction (ie, only 8 bits of set data)
+ */
+
+#define S3C_ADDR_BASE (0xF4000000)
+
+#ifndef __ASSEMBLY__
+#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x))
+#else
+#define S3C_ADDR(x) (S3C_ADDR_BASE + (x))
+#endif
+
+#define S3C_VA_IRQ S3C_ADDR(0x000000000) /* irq controller(s) */
+#define S3C_VA_SYS S3C_ADDR(0x001000000) /* system control */
+#define S3C_VA_MEM S3C_ADDR(0x002000000) /* system control */
+#define S3C_VA_TIMER S3C_ADDR(0x003000000) /* timer block */
+#define S3C_VA_WATCHDOG S3C_ADDR(0x004000000) /* watchdog */
+#define S3C_VA_UART S3C_ADDR(0x010000000) /* UART */
+
+#endif /* __ASM_PLAT_MAP_H */
diff --git a/include/asm-arm/arch-s3c2410/nand.h b/include/asm-arm/plat-s3c/nand.h
index 8816f7f9cee..8816f7f9cee 100644
--- a/include/asm-arm/arch-s3c2410/nand.h
+++ b/include/asm-arm/plat-s3c/nand.h
diff --git a/include/asm-arm/arch-s3c2410/regs-ac97.h b/include/asm-arm/plat-s3c/regs-ac97.h
index b004dee6bca..b004dee6bca 100644
--- a/include/asm-arm/arch-s3c2410/regs-ac97.h
+++ b/include/asm-arm/plat-s3c/regs-ac97.h
diff --git a/include/asm-arm/arch-s3c2410/regs-adc.h b/include/asm-arm/plat-s3c/regs-adc.h
index c7f231963e7..c7f231963e7 100644
--- a/include/asm-arm/arch-s3c2410/regs-adc.h
+++ b/include/asm-arm/plat-s3c/regs-adc.h
diff --git a/include/asm-arm/arch-s3c2410/regs-iic.h b/include/asm-arm/plat-s3c/regs-iic.h
index 2ae29522f25..2ae29522f25 100644
--- a/include/asm-arm/arch-s3c2410/regs-iic.h
+++ b/include/asm-arm/plat-s3c/regs-iic.h
diff --git a/include/asm-arm/arch-s3c2410/regs-nand.h b/include/asm-arm/plat-s3c/regs-nand.h
index b824d371ae0..b824d371ae0 100644
--- a/include/asm-arm/arch-s3c2410/regs-nand.h
+++ b/include/asm-arm/plat-s3c/regs-nand.h
diff --git a/include/asm-arm/arch-s3c2410/regs-rtc.h b/include/asm-arm/plat-s3c/regs-rtc.h
index 93b03c49710..93b03c49710 100644
--- a/include/asm-arm/arch-s3c2410/regs-rtc.h
+++ b/include/asm-arm/plat-s3c/regs-rtc.h
diff --git a/include/asm-arm/arch-s3c2410/regs-serial.h b/include/asm-arm/plat-s3c/regs-serial.h
index 8946702a87f..923e114db66 100644
--- a/include/asm-arm/arch-s3c2410/regs-serial.h
+++ b/include/asm-arm/plat-s3c/regs-serial.h
@@ -32,10 +32,10 @@
#ifndef __ASM_ARM_REGS_SERIAL_H
#define __ASM_ARM_REGS_SERIAL_H
-#define S3C24XX_VA_UART0 (S3C24XX_VA_UART)
-#define S3C24XX_VA_UART1 (S3C24XX_VA_UART + 0x4000 )
-#define S3C24XX_VA_UART2 (S3C24XX_VA_UART + 0x8000 )
-#define S3C24XX_VA_UART3 (S3C24XX_VA_UART + 0xC000 )
+#define S3C24XX_VA_UART0 (S3C_VA_UART)
+#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 )
+#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 )
+#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 )
#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
diff --git a/include/asm-arm/arch-s3c2410/regs-timer.h b/include/asm-arm/plat-s3c/regs-timer.h
index 6f8fe432fe3..8b0d594397b 100644
--- a/include/asm-arm/arch-s3c2410/regs-timer.h
+++ b/include/asm-arm/plat-s3c/regs-timer.h
@@ -14,12 +14,12 @@
#ifndef __ASM_ARCH_REGS_TIMER_H
#define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $"
-#define S3C2410_TIMERREG(x) (S3C24XX_VA_TIMER + (x))
-#define S3C2410_TIMERREG2(tmr,reg) S3C2410_TIMERREG((reg)+0x0c+((tmr)*0x0c))
+#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
+#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))
-#define S3C2410_TCFG0 S3C2410_TIMERREG(0x00)
-#define S3C2410_TCFG1 S3C2410_TIMERREG(0x04)
-#define S3C2410_TCON S3C2410_TIMERREG(0x08)
+#define S3C2410_TCFG0 S3C_TIMERREG(0x00)
+#define S3C2410_TCFG1 S3C_TIMERREG(0x04)
+#define S3C2410_TCON S3C_TIMERREG(0x08)
#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
@@ -71,9 +71,9 @@
/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
-#define S3C2410_TCNTB(tmr) S3C2410_TIMERREG2(tmr, 0x00)
-#define S3C2410_TCMPB(tmr) S3C2410_TIMERREG2(tmr, 0x04)
-#define S3C2410_TCNTO(tmr) S3C2410_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
+#define S3C2410_TCNTB(tmr) S3C_TIMERREG2(tmr, 0x00)
+#define S3C2410_TCMPB(tmr) S3C_TIMERREG2(tmr, 0x04)
+#define S3C2410_TCNTO(tmr) S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
#define S3C2410_TCON_T4RELOAD (1<<22)
#define S3C2410_TCON_T4MANUALUPD (1<<21)
diff --git a/include/asm-arm/arch-s3c2410/regs-watchdog.h b/include/asm-arm/plat-s3c/regs-watchdog.h
index a9c5d491bdb..56c4193b7a4 100644
--- a/include/asm-arm/arch-s3c2410/regs-watchdog.h
+++ b/include/asm-arm/plat-s3c/regs-watchdog.h
@@ -14,11 +14,11 @@
#ifndef __ASM_ARCH_REGS_WATCHDOG_H
#define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $"
-#define S3C2410_WDOGREG(x) ((x) + S3C24XX_VA_WATCHDOG)
+#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
-#define S3C2410_WTCON S3C2410_WDOGREG(0x00)
-#define S3C2410_WTDAT S3C2410_WDOGREG(0x04)
-#define S3C2410_WTCNT S3C2410_WDOGREG(0x08)
+#define S3C2410_WTCON S3C_WDOGREG(0x00)
+#define S3C2410_WTDAT S3C_WDOGREG(0x04)
+#define S3C2410_WTCNT S3C_WDOGREG(0x08)
/* the watchdog can either generate a reset pulse, or an
* interrupt.
diff --git a/include/asm-arm/plat-s3c/uncompress.h b/include/asm-arm/plat-s3c/uncompress.h
new file mode 100644
index 00000000000..b5e6208175d
--- /dev/null
+++ b/include/asm-arm/plat-s3c/uncompress.h
@@ -0,0 +1,155 @@
+/* linux/include/asm-arm/plat-s3c/uncompress.h
+ *
+ * Copyright 2003, 2007 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - uncompress code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_UNCOMPRESS_H
+#define __ASM_PLAT_UNCOMPRESS_H
+
+typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
+
+/* uart setup */
+
+static unsigned int fifo_mask;
+static unsigned int fifo_max;
+
+/* forward declerations */
+
+static void arch_detect_cpu(void);
+
+/* defines for UART registers */
+
+#include "asm/plat-s3c/regs-serial.h"
+#include "asm/plat-s3c/regs-watchdog.h"
+
+/* working in physical space... */
+#undef S3C2410_WDOGREG
+#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
+
+/* how many bytes we allow into the FIFO at a time in FIFO mode */
+#define FIFO_MAX (14)
+
+#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)
+
+static __inline__ void
+uart_wr(unsigned int reg, unsigned int val)
+{
+ volatile unsigned int *ptr;
+
+ ptr = (volatile unsigned int *)(reg + uart_base);
+ *ptr = val;
+}
+
+static __inline__ unsigned int
+uart_rd(unsigned int reg)
+{
+ volatile unsigned int *ptr;
+
+ ptr = (volatile unsigned int *)(reg + uart_base);
+ return *ptr;
+}
+
+/* we can deal with the case the UARTs are being run
+ * in FIFO mode, so that we don't hold up our execution
+ * waiting for tx to happen...
+*/
+
+static void putc(int ch)
+{
+ if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
+ int level;
+
+ while (1) {
+ level = uart_rd(S3C2410_UFSTAT);
+ level &= fifo_mask;
+
+ if (level < fifo_max)
+ break;
+ }
+
+ } else {
+ /* not using fifos */
+
+ while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
+ barrier();
+ }
+
+ /* write byte to transmission register */
+ uart_wr(S3C2410_UTXH, ch);
+}
+
+static inline void flush(void)
+{
+}
+
+#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
+
+/* CONFIG_S3C_BOOT_WATCHDOG
+ *
+ * Simple boot-time watchdog setup, to reboot the system if there is
+ * any problem with the boot process
+*/
+
+#ifdef CONFIG_S3C_BOOT_WATCHDOG
+
+#define WDOG_COUNT (0xff00)
+
+static inline void arch_decomp_wdog(void)
+{
+ __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
+}
+
+static void arch_decomp_wdog_start(void)
+{
+ __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
+ __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
+ __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
+}
+
+#else
+#define arch_decomp_wdog_start()
+#define arch_decomp_wdog()
+#endif
+
+#ifdef CONFIG_S3C_BOOT_ERROR_RESET
+
+static void arch_decomp_error(const char *x)
+{
+ putstr("\n\n");
+ putstr(x);
+ putstr("\n\n -- System resetting\n");
+
+ __raw_writel(0x4000, S3C2410_WTDAT);
+ __raw_writel(0x4000, S3C2410_WTCNT);
+ __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
+
+ while(1);
+}
+
+#define arch_error arch_decomp_error
+#endif
+
+static void error(char *err);
+
+static void
+arch_decomp_setup(void)
+{
+ /* we may need to setup the uart(s) here if we are not running
+ * on an BAST... the BAST will have left the uarts configured
+ * after calling linux.
+ */
+
+ arch_detect_cpu();
+ arch_decomp_wdog_start();
+}
+
+
+#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/plat-s3c24xx/regs-iis.h
index eaf77916a60..eaf77916a60 100644
--- a/include/asm-arm/arch-s3c2410/regs-iis.h
+++ b/include/asm-arm/plat-s3c24xx/regs-iis.h
diff --git a/include/asm-arm/arch-s3c2410/regs-spi.h b/include/asm-arm/plat-s3c24xx/regs-spi.h
index 4a499a13825..4a499a13825 100644
--- a/include/asm-arm/arch-s3c2410/regs-spi.h
+++ b/include/asm-arm/plat-s3c24xx/regs-spi.h
diff --git a/include/asm-arm/arch-s3c2410/regs-udc.h b/include/asm-arm/plat-s3c24xx/regs-udc.h
index e1e9805d2d9..e1e9805d2d9 100644
--- a/include/asm-arm/arch-s3c2410/regs-udc.h
+++ b/include/asm-arm/plat-s3c24xx/regs-udc.h
diff --git a/include/asm-arm/arch-s3c2410/udc.h b/include/asm-arm/plat-s3c24xx/udc.h
index b8aa6cb69b5..b8aa6cb69b5 100644
--- a/include/asm-arm/arch-s3c2410/udc.h
+++ b/include/asm-arm/plat-s3c24xx/udc.h
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
index eae85b09db2..69c65d56a6a 100644
--- a/include/asm-arm/thread_info.h
+++ b/include/asm-arm/thread_info.h
@@ -24,7 +24,6 @@
struct task_struct;
struct exec_domain;
-#include <asm/ptrace.h>
#include <asm/types.h>
#include <asm/domain.h>
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index bfdbebebdc1..d327b25c986 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -441,7 +441,6 @@
/*
* Unimplemented (or alternatively implemented) syscalls
*/
-#define __IGNORE_sync_file_range 1
#define __IGNORE_fadvise64_64 1
#endif /* __KERNEL__ */
diff --git a/include/asm-arm/vfp.h b/include/asm-arm/vfp.h
index 14c5e0946c4..bd6be9d7f77 100644
--- a/include/asm-arm/vfp.h
+++ b/include/asm-arm/vfp.h
@@ -26,8 +26,8 @@
#define FPSID_REV_MASK (0xF << FPSID_REV_BIT)
/* FPEXC bits */
-#define FPEXC_EXCEPTION (1<<31)
-#define FPEXC_ENABLE (1<<30)
+#define FPEXC_EX (1 << 31)
+#define FPEXC_EN (1 << 30)
/* FPSCR bits */
#define FPSCR_DEFAULT_NAN (1<<25)