diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-mips/mips-boards/maltaint.h | 58 | ||||
| -rw-r--r-- | include/asm-mips/rtlx.h | 56 | ||||
| -rw-r--r-- | include/asm-mips/system.h | 4 | ||||
| -rw-r--r-- | include/asm-mips/traps.h | 3 |
4 files changed, 119 insertions, 2 deletions
diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h index 376181882e8..da6cc2fbbc7 100644 --- a/include/asm-mips/mips-boards/maltaint.h +++ b/include/asm-mips/mips-boards/maltaint.h @@ -25,9 +25,63 @@ #ifndef _MIPS_MALTAINT_H #define _MIPS_MALTAINT_H -/* Number of IRQ supported on hw interrupt 0. */ -#define MALTAINT_END 16 +/* + * Interrupts 0..15 are used for Malta ISA compatible interrupts + */ +#define MALTA_INT_BASE 0 + +/* + * Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode) + */ +#define MIPSCPU_INT_BASE 16 + +/* CPU interrupt offsets */ +#define MIPSCPU_INT_SW0 0 +#define MIPSCPU_INT_SW1 1 +#define MIPSCPU_INT_MB0 2 +#define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0 +#define MIPSCPU_INT_MB1 3 +#define MIPSCPU_INT_SMI MIPSCPU_INT_MB1 +#define MIPSCPU_INT_MB2 4 +#define MIPSCPU_INT_MB3 5 +#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 +#define MIPSCPU_INT_MB4 6 +#define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4 +#define MIPSCPU_INT_CPUCTR 7 + +/* + * Interrupts 64..127 are used for Soc-it Classic interrupts + */ +#define MSC01C_INT_BASE 64 + +/* SOC-it Classic interrupt offsets */ +#define MSC01C_INT_TMR 0 +#define MSC01C_INT_PCI 1 + +/* + * Interrupts 64..127 are used for Soc-it EIC interrupts + */ +#define MSC01E_INT_BASE 64 + +/* SOC-it EIC interrupt offsets */ +#define MSC01E_INT_SW0 1 +#define MSC01E_INT_SW1 2 +#define MSC01E_INT_MB0 3 +#define MSC01E_INT_I8259A MSC01E_INT_MB0 +#define MSC01E_INT_MB1 4 +#define MSC01E_INT_SMI MSC01E_INT_MB1 +#define MSC01E_INT_MB2 5 +#define MSC01E_INT_MB3 6 +#define MSC01E_INT_COREHI MSC01E_INT_MB3 +#define MSC01E_INT_MB4 7 +#define MSC01E_INT_CORELO MSC01E_INT_MB4 +#define MSC01E_INT_TMR 8 +#define MSC01E_INT_PCI 9 +#define MSC01E_INT_PERFCTR 10 +#define MSC01E_INT_CPUCTR 11 +#ifndef __ASSEMBLY__ extern void maltaint_init(void); +#endif #endif /* !(_MIPS_MALTAINT_H) */ diff --git a/include/asm-mips/rtlx.h b/include/asm-mips/rtlx.h new file mode 100644 index 00000000000..83cdf6ab0d1 --- /dev/null +++ b/include/asm-mips/rtlx.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. + * + */ + +#ifndef _RTLX_H +#define _RTLX_H_ + +#define LX_NODE_BASE 10 + +#define MIPSCPU_INT_BASE 16 +#define MIPS_CPU_RTLX_IRQ 0 + +#define RTLX_VERSION 1 +#define RTLX_xID 0x12345600 +#define RTLX_ID (RTLX_xID | RTLX_VERSION) +#define RTLX_CHANNELS 8 + +enum rtlx_state { + RTLX_STATE_UNUSED = 0, + RTLX_STATE_INITIALISED, + RTLX_STATE_REMOTE_READY, + RTLX_STATE_OPENED +}; + +#define RTLX_BUFFER_SIZE 1024 +/* each channel supports read and write. + linux (vpe0) reads lx_buffer and writes rt_buffer + SP (vpe1) reads rt_buffer and writes lx_buffer +*/ +typedef struct rtlx_channel { + enum rtlx_state rt_state; + enum rtlx_state lx_state; + + int buffer_size; + + /* read and write indexes per buffer */ + int rt_write, rt_read; + char *rt_buffer; + + int lx_write, lx_read; + char *lx_buffer; + + void *queues; + +} rtlx_channel_t; + +typedef struct rtlx_info { + unsigned long id; + enum rtlx_state state; + + struct rtlx_channel channel[RTLX_CHANNELS]; + +} rtlx_info_t; + +#endif diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index 36f34d8ddfa..384f0bd854c 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -431,6 +431,10 @@ static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old, #define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr)))) +extern void set_handler (unsigned long offset, void *addr, unsigned long len); +extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len); +extern void *set_vi_handler (int n, void *addr); +extern void *set_vi_srs_handler (int n, void *addr, int regset); extern void *set_except_vector(int n, void *addr); extern void per_cpu_trap_init(void); diff --git a/include/asm-mips/traps.h b/include/asm-mips/traps.h index 17901226300..d02e019b012 100644 --- a/include/asm-mips/traps.h +++ b/include/asm-mips/traps.h @@ -21,4 +21,7 @@ extern void (*board_be_init)(void); extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup); +extern void (*board_nmi_handler_setup)(void); +extern void (*board_ejtag_handler_setup)(void); + #endif /* _ASM_TRAPS_H */ |