summaryrefslogtreecommitdiffstats
AgeCommit message (Collapse)Author
2013-02-13clk: tegra: fix driver to match DT bindingStephen Warren
enum tegra*_clk is intended to match the IDs listed in the Tegra clock bindings. There are a few mismatches, which this patch fixes: 1) pll_s and cop were left out of the Tegra20 enum. 2) spdif_in and spdif_out were swapped relative to the Tegra30 binding. 3) i2cslow was misnamed as i2c_slow, and a duplicate i2cslow clock added to the Tegra30 enum. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
2013-02-12clk: tegra: local arrays should be staticPeter De Schrijver
cclk_g_parents, cclk_lp_parents and sclk_parents are only accessed from within clk-tegra30.c. Declare them static to avoid namespace polution. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-02-12clk: tegra: Add missing spinlock for hclk and pclkPeter De Schrijver
The hclk and pclk clocks are controlled by the same register. Hence a lock is required to avoid corruption. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-02-12clk: tegra: Implement locking for super clockPeter De Schrijver
Although tegra_clk_register_super_mux() has a lock parameter, the lock is not actually used by the code. Fixed with this patch. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-02-12clk: tegra: fix wrong clock index between se to sata_coldJoseph Lo
The index of se should be 127. And the previous clock index was 125. So we need to set up the index for se to get the correct index between se to sata_cold. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-29ARM: dt: tegra30: Rename "smmu" to "iommu"Hiroshi Doyu
Use functional name for DT entry instead of h/w name. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-29ARM: dt: tegra20: Rename "gart" to "iommu"Hiroshi Doyu
Use functional name for DT entry instead of h/w name. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsiStephen Warren
No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: Add Toradex Iris carrier board DT with T20 512MB COMLucas Stach
This adds the device tree for the Toradex Iris carrier board used together with a Colibri T20 512MB COM. The Iris has the following features, in brackets the current status: - DVI and VGA output through DVI-I connector (DVI-D enabled and tested) - LVDS output - 1 USB host port (enabled and tested) - 1 USB OTG port (enabled) - 100 MBit Ethernet (enabled and tested) - 5 UART ports (2 on 10way headers enabled and tested) - 1 MicroSD Slot (enabled and tested) - Audio connectors (enabled, only HP out and Line-in tested) - i2c RTC - GPIO connector (enabled, only sparsely tested) - external i2c bus - 4 PWM out - analog in Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: Add Colibri T20 512MB COM device treeLucas Stach
This adds the device tree include file for the Toradex Colibri T20 Computer on Module (COM). It's only valid for the 512MB RAM version of the module, as the 256MB version needs different EMC tables and flash configuration. To make this clear the suffix -512 was added to the board compatible string. The Colibri T20 uses a Tegra20 SoC and has onboard USB Ethernet and AC97 sound. Still some things like onboard NAND support missing, but should be a good base for further development. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: move serial clock-frequency attr into the Tegra20 dtsiLucas Stach
No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: harmony: enable keyboard in DTLaxman Dewangan
Enable Tegra based keyboard interfacing for keys and provide all key mapping through DTS file. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: whistler: enable keyboard in DTLaxman Dewangan
Enable Tegra based keyboard controller and populate the key mapping for Whistler. With this patch, HOME, BACK, POWER and MENU keys will work. Still other keys which are in ROW3 and ROW4 will not work as it conflicts with KBC pins on SDIO2 pinmux. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: cardhu: register UARTCLaxman Dewangan
UARTC is used for the interfacing with bluetooth device. Register this UART channel as high speed serial channel so that it can use the APB DMA for data transfer. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: seaboard: enable keyboard in DTLaxman Dewangan
Enable Tegra based keyboard controller and populate the key matrix for seaboard. The key matrix was originally on driver code which is removed to have clean driver. The key mapping is now passed through dts file. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: add DT entry for KBC controllerLaxman Dewangan
NVIDIA's Tegra SoCs have the matrix keyboard controller which supports 16x8 type of matrix. The number of rows and columns are configurable. Add DT entry for KBC controller. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: added clocks property] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: swap cache-/interrupt-ctrlr nodes in DTStephen Warren
This ensures nodes are sorted in order of reg address. This makes it easier to compare against e.g. the U-Boot device trees, and is simply consistent and clean. While we're at it, remove the unit address from the cache-controller node name, since it's unique without it. Reported-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ASoC: tegra: add ac97 host controller to device treeLucas Stach
Add default entry for the AC97 host controller. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: DT: tegra: Add Tegra30 Beaver board supportBryan Wu
This patch adds support for Tegra30 Beaver board in upstream kernel. Beaver board is a Tegra30 SoC based development board, it has following features: - T30 or T33 SoC (Qual core ARM Cortex A9) - 2 GB DDR3L - 16 GB EMMC - 1 SD slot - 1 USB Standart A port and 1 USB micro AB port - PCI-E Gig Ethernet - Audio input/output - SATA port - HDMI output - UART and JTAG Signed-off-by: Bryan Wu <pengw@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: DT: tegra: Add board level compatible propertiesBryan Wu
The compatible properties of Tegra SoC based boards or machines need to be documented. This patch adds these board levle compatible properties into device tree binding document. Signed-off-by: Bryan Wu <pengw@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: paz00: enable HDMI portStephen Warren
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: ventana: enable HDMI portStephen Warren
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: seaboard: enable HDMI portStephen Warren
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: trimslice: add gpio-poweroff node to DTStephen Warren
... and disable tri-state from the pingroup that contains the poweroff GPIO. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: DT: tegra: Unify the description of Tegra20 boardsBryan Wu
Use engineering name 'Tegra20' instead of 'Tegra2' Signed-off-by: Bryan Wu <pengw@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: dts: add aliases and DMA requestor for serial controllerLaxman Dewangan
Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra20-hsuart. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra30: tegra30 gpio is not compatible with tegra20 gpioLaxman Dewangan
tegra30 gpio controller is not compatible with the tegra20 due to their bank stride i.e. Tegra20 bank stride is 0x80 where Tegra30 bank stride is 0x100. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: fixed typo syntax error] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: Add initial support for Tegra114 SoC.Hiroshi Doyu
Add new Tegra 114 SoC support. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: dt: tegra114: Add new board, PlutoHiroshi Doyu
Add a new evaluation board, Pluto for Tegra 114 family. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: dt: tegra114: Add new board, DalmoreHiroshi Doyu
Add a new evaluation board, Dalmore for Tegra 114 family. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: dt: tegra114: Add new SoC base, Tegra114 SoCHiroshi Doyu
Initial support for Tegra 114 SoC. This is expected to be included in the board DTS files, Tegra 114 SoC based evaluation board family. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: fuse: Add chip ID Tegra114 0x35Hiroshi Doyu
Add tegra_chip_id TEGRA114 0x35 Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28Merge branch 'for-3.9/scu-base-rework' into for-3.9/soc-t114Stephen Warren
Conflicts: arch/arm/mach-tegra/platsmp.c
2013-01-28ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down modeJoseph Lo
The "powered-down" cpuidle mode of Tegra20 needs the CPU0 be the last one core to go into this mode before other core. The coupled cpuidle framework can help to sync the MPCore to coupled state then go into "powered-down" idle mode together. The driver can just assume the MPCore come into "powered-down" mode at the same time. No need to take care if the CPU_0 goes into this mode along and only can put it into safe idle mode (WFI). The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI for waiting CPU0 in the same state. When the CPU0 requests powered-down state, it attempts to put the secondary CPU into reset to prevent it from waking up. Then power down both CPUs together and power off the cpu rail. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra20: flowctrl: add support for cpu_suspend_enter/exitJoseph Lo
The flow controller can help CPU to go into suspend mode (powered-down state). When CPU go into powered-down state, it needs some careful settings before getting into and after leaving. The enter and exit functions do that by configuring appropriate mode for flow controller. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28clk: tegra20: Implementing CPU low-power function for tegra_cpu_car_opsJoseph Lo
Implementing suspend, resume and rail_off_ready API for tegra_cpu_car_ops. These functions were used for CPU powered-down state maintenance. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra20: cpuidle: add powered-down state for secondary CPUJoseph Lo
The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: add pending SGI checking APIJoseph Lo
The "powered-down" CPU idle mode of Tegra cut off the vdd_cpu rail, it include the power of GIC. That caused the SGI (Software Generated Interrupt) been lost. Because the SGI can't wake up the CPU that in the "powered-down" CPU idle mode. We need to check if there is any pending SGI when go into "powered-down" CPU idle mode. This is important especially when applying the coupled cpuidle framework into "power-down" cpuidle dirver. Because the coupled cpuidle framework may have the chance that misses IPI_SINGLE_FUNC handling sometimes. For the PPI or SPI, something like the legacy peripheral interrupt. It still can be maintained by Tegra legacy interrupt controller. If there is any pending PPI or SPI when CPU in "powered-down" CPU idle mode. The CPU can be woken up immediately. So we don't need to take care the same situation for PPI or SPI. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28usb: host: tegra: don't touch EMC clockStephen Warren
Clock "emc" is for the External Memory Controller. The USB driver has no business touching this clock directly. Remove the code that does so. Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28usb: add APIs to access host registers from Tegra PHYVenu Byravarasu
As Tegra PHY driver needs to access one of the host registers, added few APIs. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> [swarren: moved assignment of phy->is_ulpi_phy to previous patch.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28USB: PHY: tegra: Get rid of instance number to differentiate PHY typeVenu Byravarasu
Tegra20 USB has 3 PHY instances: Instance 1 and 3 are UTMI. Instance 2 is ULPI. As instance number was used to differentiate ULPI from UTMI, used DT param to get this info and processed accordingly. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Acked-by: Felipe Balbi <balbi@ti.com> [swarren: moved assignment of phy->is_ulpi_phy into this patch out of next patch.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28USB: PHY: tegra: get rid of instance number to differentiate legacy controllerVenu Byravarasu
Tegra20 USB has 3 PHY instances. Instance 0 is based on legacy PHY interface and other two are standard interfaces. As instance number was used to differentiate legacy from standard interfaces, used DT param to get this info and processed accordingly. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: add clocks properties to USB PHY nodesStephen Warren
The patch to add USB PHY nodes to device tree was written before Tegra supported the clocks property in device tree. Now that it does, add the required clocks properties to these nodes. This will allow all clk_get_sys() calls in tegra_usb_phy.c to be replaced by clk_get(phy->dev, clock_name), as part of converting the PHY driver to a platform driver. Acked-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: add DT nodes for Tegra USB PHYVenu Byravarasu
Add DT nodes for Tegra USB PHY along with related documentation. Also added a phandle property to controller DT node, for referring to connected PHY instance. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28usb: phy: remove unused APIs from Tegra PHY.Venu Byravarasu
As tegra_usb_phy_clk_disable/enable() are not being used, removing them. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28usb: host: tegra: Resetting PORT0 based on information received via DT.Venu Byravarasu
Tegra USB host driver is using port instance number, to handle some of the hardware issues on SOC e.g. reset PORT0 twice etc. As instance number based handling looks ugly, making use of information passed through DT for achieving this. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: Add new DT property to USB node.Venu Byravarasu
As Tegra USB host driver is using instance number for resetting PORT0 twice, adding a new DT property for handling this. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28usb: phy: use kzalloc to allocate struct tegra_usb_phyVenu Byravarasu
Use kzalloc instead of kmalloc to allocate struct tegra_usb_phy. This ensures that all function pointers in member u_phy are initialized to NULL. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: remove USB address related macros from iomap.hVenu Byravarasu
USB register base address and sizes defined in iomap.h are not used in any files other than board-dt-tegra20.c. Hence removed those defines from header file and using the absolute values in board files. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28clk: tegra30: remove unused TEGRA_CLK_DUPLICATE()sPrashant Gaikwad
With device tree support added for Tegra clocks look up is done from device tree, remove unused TEGRA_CLK_DUPLICATE()s. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-01-15 10:16:50 +0000