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AgeCommit message (Expand)Author
2014-05-21drm/i915: Move buffer pinning and ring selection to intel_crtc_page_flip()Ville Syrjälä
2014-05-21drm/i915: Drop the excessive vblank waits from modeset codepathsVille Syrjälä
2014-05-21drm/i915: Wait for vblank in hsw_enable_ips()Ville Syrjälä
2014-05-21drm/i915: Fix mmio vs. CS flip race on ILK+Ville Syrjälä
2014-05-21drm/i915: drop encoder hot_plug calls at resumeJesse Barnes
2014-05-20drm/i915: Drop now misleading DDI comment from dp_link_downDaniel Vetter
2014-05-20drm/i915: shuffle panel codeJani Nikula
2014-05-20drm/i915: Clear GDSR after reset on ILKVille Syrjälä
2014-05-20drm/i915: Kill RMW from ILK reset codeVille Syrjälä
2014-05-20drm/i915: add missing unregister_oom_notifier to the error/unload pathImre Deak
2014-05-20drm/i915: Drop /** */ comments from i915_reg.hVille Syrjälä
2014-05-20drm/i915/chv: Add a bunch of pre production workaroundsVille Syrjälä
2014-05-20drm/i915/chv: Use RMW to toggle swing calc initVille Syrjälä
2014-05-20drm/i915/chv: Don't do group access reads from TX lanes eitherVille Syrjälä
2014-05-20drm/i915/chv: Don't use PCS group access readsVille Syrjälä
2014-05-20drm/i915/chv: Set soft reset override bit for data lane resetsVille Syrjälä
2014-05-20drm/i915/chv: Reset data lanes in encoder .post_disable() hookVille Syrjälä
2014-05-20drm/i915/chv: Turn off dclkp after the PLL has been disabledVille Syrjälä
2014-05-20drm/i915/chv: Move data lane deassert to encoder pre_enableVille Syrjälä
2014-05-20drm/i915/chv: Fix CHV PLL state trackingVille Syrjälä
2014-05-20drm/i915/chv: Register port D encoders and connectorsVille Syrjälä
2014-05-20drm/i915/chv: Fix PORT_TO_PIPE for CHVVille Syrjälä
2014-05-20drm/i915/chv: Bump num_pipes to 3Ville Syrjälä
2014-05-20drm/i915/chv: Add cursor pipe offsetsVille Syrjälä
2014-05-20drm/i915/chv: Fix gmbus for port DVille Syrjälä
2014-05-20drm/i915/chv: Configure crtc_mask correctly for CHVVille Syrjälä
2014-05-20drm/i915/chv: Make CHV irq handler loop until all interrupts are consumedVille Syrjälä
2014-05-20drrm/i915/chv: Use valleyview_pipestat_irq_handler() for CHVVille Syrjälä
2014-05-20drm/i915/chv: Clarify VLV/CHV PIPESTAT bits a bit moreVille Syrjälä
2014-05-20drm/i915/chv: Add CHV display supportRafael Barbalho
2014-05-20drm/i915/chv: Implement WaDisableSamplerPowerBypass for CHVRafael Barbalho
2014-05-20drm/i915/chv: Add some workaround notesVille Syrjälä
2014-05-20drm/i915/chv: Implement WaDisableSDEUnitClockGating:chvVille Syrjälä
2014-05-20drm/i915/chv: Implement WaDisableCSUnitClockGating:chvVille Syrjälä
2014-05-20drm/i915/chv: Implement WaDisableSemaphoreAndSyncFlipWait:chvVille Syrjälä
2014-05-20drm/i915/chv: Implement WaVSRefCountFullforceMissDisable:chv and WaDSRefCount...Ville Syrjälä
2014-05-20drm/i915/chv: Implement WaDisableThreadStallDopClockGating:chvVille Syrjälä
2014-05-20drm/i915/chv: Implement WaDisablePartialInstShootdown:chvVille Syrjälä
2014-05-20drm/i915: s/ironlake_/intel_ for the enable_share_dpll functionDaniel Vetter
2014-05-20drm/i915: Extract intel_prepare_shared_dpllDaniel Vetter
2014-05-20drm/i915: Only update shared dpll state when neededDaniel Vetter
2014-05-20drm/i915: Extract vlv_prepare_pllDaniel Vetter
2014-05-20drm/i915: Extract i9xx_set_pll_dividersDaniel Vetter
2014-05-20drm/i915: Shovel hw setup code out of hsw_crtc_mode_setDaniel Vetter
2014-05-20drm/i915: Shovel hw setup code out of ilk_crtc_mode_setDaniel Vetter
2014-05-20drm/i915: Move lowfreq_avail around a bit in ilk/hsw_crtc_mode_setDaniel Vetter
2014-05-20drm/i915: Shovel hw setup code out of i9xx_crtc_mode_setDaniel Vetter
2014-05-20drm/i915: Implement an oom-notifier for last resort shrinkingChris Wilson
2014-05-20drm/i915: Fix ILK GPU reset domain bitsVille Syrjälä
2014-05-20drm/i915: Fix ILK reset waitVille Syrjälä
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