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2013-02-17MIPS: ralink: add CPU interrupt controller to of_irq_idsGabor Juhos
Convert the ralink IRQ code to make use of the new MIPS IRQ controller OF mappings. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: David Daney <david.daney@cavium.com> Patchwork: http://patchwork.linux-mips.org/patch/4900/
2013-02-17MIPS: add irqdomain support for the CPU IRQ controllerGabor Juhos
Add code to load a irq_domain for the MIPS IRQ controller from a devicetree file. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: David Daney <david.daney@cavium.com> Patchwork: http://patchwork.linux-mips.org/patch/4902/
2013-02-17Document: devicetree: add OF documents for MIPS interrupt controllerJohn Crispin
Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: David Daney <david.daney@cavium.com> Patchwork: http://patchwork.linux-mips.org/patch/4901/
2013-02-17MIPS: ralink: adds default config fileJohn Crispin
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: ralink: adds Kbuild filesJohn Crispin
Add the Kbuild symbols and Makefiles needed to actually build the ralink code from this series Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4899/
2013-02-17MIPS: ralink: adds rt305x devicetreeJohn Crispin
This adds the devicetree file that describes the rt305x evaluation kit. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4898/
2013-02-17MIPS: ralink: adds support for RT305x SoC familyJohn Crispin
Add support code for rt3050, rt3052, rt3350, rt3352 and rt5350 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4896/
2013-02-17MIPS: ralink: adds early_printk supportJohn Crispin
Add the code needed to make early printk work. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4897/
2013-02-17MIPS: ralink: adds OF codeJohn Crispin
Until there is a generic MIPS way of handing the DTB over from bootloader to kernel we rely on a built in devicetrees. The OF code also remaps those register ranges that we use global in our drivers. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4895/
2013-02-17MIPS: ralink: adds clkdev codeJohn Crispin
These SoCs have a limited number of fixed rate clocks. Add support for the clk and clkdev api. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4894/
2013-02-17MIPS: ralink: adds prom and cmdline codeJohn Crispin
Add minimal code to handle commandlines. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4892/
2013-02-17MIPS: ralink: adds reset codeJohn Crispin
Resetting these SoCs requires no real magic. The code is straight forward. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4891/
2013-02-17MIPS: ralink: adds irq codeJohn Crispin
All of the Ralink Wifi SoC currently supported by this series share the same interrupt controller (INTC). Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4890/
2013-02-17MIPS: ralink: adds include filesJohn Crispin
Before we start adding the platform code we add the common include files. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4893/
2013-02-17Document: devicetree: add OF documents for lantiq serial portJohn Crispin
Signed-off-by: John Crispin <blogic@openwrt.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: devicetree-discuss@lists.ozlabs.org
2013-02-17MIPS: ath79: simplify MISC IRQ handlingGabor Juhos
The current code uses multiple if statements for demultiplexing the different interrupt sources. Additionally, the MISC interrupt controller has 32 interrupt sources and the current code does not handles all of them. Get rid of the if statements and process all interrupt sources in a loop to fix these issues. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4874/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: ath79: simplify ath79_gpio_function_* routinesGabor Juhos
Make ath79_gpio_function_{en,dis}able to be wrappers around ath79_gpio_function_setup. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4871/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: ath79: fix GPIO function selection for AR934x SoCsGabor Juhos
GPIO function selection is not working on the AR934x SoCs because the offset of the function selection register is different on those. Add a helper routine which returns the correct register address based on the SoC type, and use that in the 'ath79_gpio_function_*' routines. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4870/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Add new GIC clocksource.Steven J. Hill
Add new clocksource that uses the counter present on the MIPS Global Interrupt Controller. Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4681/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: dsp: Simplify the DSP macros.Steven J. Hill
Simplify the DSP macros for vanilla (non-microMIPS) kernels and toolchains that do not support the DSP ASEs. Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4687/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: dsp: Support toolchains without DSP ASE and microMIPS.Steven J. Hill
Add macros to support the DSP ASE with microMIPS kernels when the toolchain does not have support. Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4686/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: dsp: Add assembler support for DSP ASEs.Steven J. Hill
Newer toolchains support the DSP and DSP Rev2 instructions. This patch performs a check for that support and adds compiler and assembler flags for only the files that need use those instructions. Signed-off-by: Steven J. Hill <sjhill@mips.com> Acked-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4752/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Add support for the M14KEc core.Steven J. Hill
Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4682/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Clean-ups for MIPS Technologies Inc. generic header file.Steven J. Hill
Clean up standard header text and remove unused #define. Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4703/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: PCI: Multi-node PCI support for Netlogic XLPJayachandran C
On a multi-chip XLP board, each node can have 4 PCIe links. Update XLP PCI code to initialize PCIe on all the nodes. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4803/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: Fix for quad-XLP bootJayachandran C
On multi-chip boards, the first core on slave SoCs may take much more time to wakeup. Add code to wait for the core to come up before proceeding with the rest of the boot up. Update xlp_wakeup_core to also skip the boot node and the boot CPU initialization which is already complete. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4783/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: use preset loops per jiffyJayachandran C
Doing calibrate delay on a hardware thread will be inaccurate since it depends on the load on other threads in the core. It will also slow down the boot process when done for 128 hardware threads. Switch to a pre-computed loops per jiffy based on the core frequency. The value is computed based on the core frequency and roughly matches the value calculated by calibrate_delay(). Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4791/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: No hazards needed for XLR/XLSJayachandran C
TLB and COP0 hazards are handled in hardware for Netlogic XLR/XLS SoCs. Update hazards.h to pick more optimal set of definitions when compiling for XLR/XLS. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4788/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: PCI: Prevent hang on XLP reg readJayachandran C
Reading PCI extended register at 0x255 on a bridge will hang if there is no device connected on the link. Make PCI read routine skip this register. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4789/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: Use PIC timer as a clocksourceJayachandran C
The XLR/XLS/XLP PIC has a 8 countdown timers which run at the PIC frequencey. One of these can be used as a clocksource to provide timestamps that is common across cores. This can be used in place of the count/compare clocksource which is per-CPU. On XLR/XLS PIC registers are 32-bit, so we just use the lower 32-bits of the PIC counter. On XLP, the whole 64-bit can be used. Provide common macros and functions for PIC timer registers on XLR/XLS and XLP, and use them to register a PIC clocksource. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4786/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: Split XLP L1 i-cache among threadsJayachandran C
Since we now use r4k cache code for Netlogic XLP, it is better to split L1 icache among the active threads, so that threads won't step on each other while flushing icache. The L1 dcache is already split among the threads in the core. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4787/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: PCI: Byteswap not needed in little-endian modeJayachandran C
Rename function xlp_enable_pci_bswap() to xlp_config_pci_bswap(), which is a better description for its functionality. When compiled in big-endian mode, xlp_config_pci_bswap() will configure the PCIe links to byteswap. In little-endian mode, no swap configuration is needed for the PCIe controller, and the function is empty. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4802/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: Optimize EIMR/EIRR accesses in 32-bitJayachandran C
Provide functions ack_c0_eirr(), set_c0_eimr(), clear_c0_eimr() and read_c0_eirr_and_eimr() that do the EIMR and EIRR operations and update the interrupt handling code to use these functions. Also, use the EIMR register functions to mask interrupts in the irq code. The 64-bit interrupt request and mask registers (EIRR and EIMR) are accessed when the interrupts are off, and the common operations are to set or clear a bit in these registers. Using the 64-bit c0 access functions for these operations is not optimal in 32-bit, because it will disable/restore interrupts and split/join the 64-bit value during each register access. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4790/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: add XLS6xx to FMN configJayachandran C
Add support for XLS6xx CPUs to the Fast Message Network (FMN) configuration. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4785/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: lantiq: rework external irq codeJohn Crispin
This code makes the irqs used by the EIU loadable from the DT. Additionally we add a helper that allows the pinctrl layer to map external irqs to real irq numbers. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4818/
2013-02-17MIPS: lantiq: improve pci reset gpio handlingJohn Crispin
We need to make sure that the reset gpio is available and also set a sane default state. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4817/
2013-02-17MIPS: lantiq: add GPHY clock gate bitsJohn Crispin
Explicitly enable the clock gate of the internal GPHYs found on xrx200. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4816/
2013-02-17MIPS: lantiq: adds static clock for PP32John Crispin
The Lantiq DSL SoCs have an internal networking processor. Add code to read the static clock rate. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4815/
2013-02-17MIPS: lantiq: trivial typo fixJohn Crispin
"nodes" is written with a single "s" Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4814/
2013-02-17MIPS: show correct cpu name for 24KEcJohn Crispin
Make sure 24KEc is properly identified inside /proc/cpuinfo Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: use fallback sprom var for board_{rev,type}Hauke Mehrtens
An SoC normally do not define path variables for board_rev and board_type and the Broadcom SDK also uses the nvram values without a prefix in such cases. Do the same to fill these sprom attributes from nvram and do not leave them empty, because brcmsmac do not like this. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4679/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: select NO_EXCEPT_FILLHauke Mehrtens
The kernel is loaded to 0x80001000 so there is some space left for the exception handlers and the kernel do not have to reserve some extra space for them. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4747/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: select BOOT_RAWHauke Mehrtens
All the boot loaders I have seen are booting the kernel in raw mode by default. CFE seems to support elf kernel images too, but the default case is raw for the devices I know of. Select this option to make the kernel boot on most of the devices with the default options. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4746/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: trim the nvram values for parsingHauke Mehrtens
Some nvram values on some devices have a newline character at the end of the value, that caused read errors. Trim the string before reading the number. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4745/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: add bcm47xx prefix in front of nvram function namesHauke Mehrtens
The nvram functions are exported and used by some normal drivers. To prevent name clashes with ofter parts of the kernel code add a bcm47xx_ prefix in front of the function names and the header file name. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4744/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: handle different nvram sizesHauke Mehrtens
The old code just worked for nvram with a size of 0x8000 bytes. This patch adds support for reading nvram from partitions of 0xF000 and 0x10000 bytes. There is just 32KB space for the nvram, but most devices do not use the full size and this code reads the first 32KB in that case and prints a warning. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4743/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: rename early_nvram_init to nvram_initHauke Mehrtens
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4742/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: nvram add nand flash supportHauke Mehrtens
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4741/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: return error when init of nvram failedHauke Mehrtens
This makes it possible to handle the case of not being able to read the nvram ram. This could happen when the code searching for the specific flash chip have not run jet. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4740/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: use common error codes in nvram readsHauke Mehrtens
Instead of using our own error codes use some common codes. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4739/ Signed-off-by: John Crispin <blogic@openwrt.org>
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