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Conflicts:
arch/arm/mach-davinci/board-da830-evm.c
arch/arm/mach-davinci/board-da850-evm.c
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On Davinci SRAM is mapped as MT_DEVICE becasue of the section
mapping pre-requisite instead of intended MT_MEMORY_NONCACHED
Since the section mapping limitation gets fixed with first
patch in this series, the MT_MEMORY_NONCACHED can be used now.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patch removes davinci architecture code that has now been rendered
useless by the previous patches in the MDIO separation series.
In addition, the earlier phy_mask definitions have been replaced with
corresponding phy_id definitions.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Tested-by: Michael Williamson <michael.williamson@criticallink.com>
Tested-by: Caglar Akyuz <caglarakyuz@gmail.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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This patch adds mdio platform devices on SoCs that have the necessary
hardware. Clock lookup entries (aliases) have also been added, so that the
MDIO and EMAC drivers can independently enable/disable a shared underlying
clock. Further, the EMAC MMR region has been split down into separate MDIO
and EMAC regions.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Acked-by: David S. Miller <davem@davemloft.net>
Tested-by: Michael Williamson <michael.williamson@criticallink.com>
Tested-by: Caglar Akyuz <caglarakyuz@gmail.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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This patch modifies the EDMA driver to expect the channel
controller (CC) infomation passed on by the platform as a fixed
size (EDMA_MAX_CC) array of pointers to structures.
Doing so helps catch errors of the sort where the resource
structure has information for more channel controllers than
the number channel controller info structures defined.
Such insufficient platform data would lead to illegal memory
accesses.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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The register base address for the second serial port (UART1) was
wrong.
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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More complete AEMIF support for boards.
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Added PINMUX configurations for the CLKOUT0 .. CLKOUT2
functions, for boards that want to use these clocks.
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Board code may want to use them.
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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This patch modifies the pinmux implementation so as to ioremap() the pinmux
register area on first use.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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This patch implements the following:
- interrupt initialization uses ioremap() instead of passing a virtual address
via davinci_soc_info.
- machine definitions directly point to cp_intc_init() or davinci_irq_init()
- davinci_intc_type and davinci_intc_base now get initialized in controller
specific init functions instead of davinci_common_init()
- minor fix in davinci_irq_init() to use intc_irq_num instead of
DAVINCI_N_AINTC_IRQ
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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This patch modifies the psc and clock control code to use ioremap()ed
registers.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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This patch replaces the jtag id base info in davinci_soc_info with a physical
address which is then ioremap()ed within common code.
This patch (in combination with a similar change for PSC) will allow us to
eliminate the SYSCFG nastiness in DA8xx code.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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This patch modifies the gpio_base definition in davinci_soc_info to be a
physical address, which is then ioremap()ed by the gpio initialization
function.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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The earlier watchdog reset mechanism had a couple of limitations. First, it
embedded a reference to "davinci_wdt_device" inside common code. This
forced all derived platforms (da8xx and tnetv107x) to define such a device.
This also would have caused problems in including multiple socs in a single
build due to symbol redefinition.
With this patch, davinci_watchdog_reset() now takes the platform device as an
argument. The davinci_soc_info struct has been extended to include a reset
function and a watchdog platform_device. arch_reset() then uses these
elements to reset the system in a SoC specific fashion.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Pinmux registers are sequential, and do not need to be enumerated out as they
currently are. This reduces code volume and keeps things simple.
If some future SoC comes up with a discontiguous register map, PINMUX() can
then be expanded with local token pasting.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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This patch allows for gpio controllers that deviate from those found on
traditional davinci socs. davinci_soc_info has an added field to indicate the
soc-specific gpio controller type. The gpio initialization code then bails
out if necessary.
More elements (tnetv107x) to be added later into enum davinci_gpio_type.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Extended the MUX configuration to allow use of GPIO
terminals 64..57.
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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- Convert data/functions to static
- include headers for missing declarations
- pointer cleanups: struct foo *__iomem f --> struct foo __iomem *f;
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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IRQ 29 has two possible interrupts DDRINT and RTC, but having both in
the default priority table is confusing (and triggers a warning from
sparse.)
This patch removes the lower priority DDRINT from the default priority
table leaving the RTC setting as the default.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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This patch adds SPI init for DM365.
It does the following
1) Initializes SPI0
2) Defines resources to be used by SPI0
3) Adds platform data for SPI0
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Remove unneeded 'struct davinci_clk' wrapper around 'struct clk_lookup'
and use clkdev_add_table() to add the list of clocks in one go.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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This patch adds the generic Voice Codec support for the DM365 based
platforms.
Signed-off-by: Miguel Aguilar <miguel.aguilar@ridgerun.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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In DM365 Q0, Q1 and Q2 are used by codecs.
LSP drivers should use Q3.
This patch changes the default queue for DM365.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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This patch adds following changes:-
1) add sub device configuration data for TVP5146 used by vpfe capture
2) registers platform devices for vpfe_capture, isif and vpss
3) defines hardware resources for the devices listed under 2)
4) defines clock aliase for isif driver
5) adding setup_pinmux() for isif
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Adds the device_enable function to the DaVinci Keyscan platform data
to setup the PINMUX configuration.
It also removes #ifdef from the DM365 EVM board in order to load it
properly as a module.
Signed-off-by: Miguel Aguilar <miguel.aguilar@ridgerun.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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The general structures are defined at DM365 SoC file and the specific
platform data structure for the EVM is defined at board file.
Signed-off-by: Miguel Aguilar <miguel.aguilar@ridgerun.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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The general structures are defined at DM365 SoC file and the specific
platform data structure for the EVM is defined at board file.
Signed-off-by: Miguel Aguilar <miguel.aguilar@ridgerun.com>
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There have accumulated quite a lot of them after the code reorganizations...
In several cases I had to replace #include <linux/dma-mapping.h> which wasn't
needed directly but happened to #include <linux/err.h> which was needed.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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1) Registers the platform device for McBSP on dm365.
2) Add platform data to DM365 EVM board file.
3) Set i2c address for audio codec at DM365 EVM board file.
Signed-off-by: Miguel Aguilar <miguel.aguilar@ridgerun.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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The parent clock for the USB source clock is actually PLL1 aux clock,
not PLL2 sysclk1.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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This patch adds definitions for some DM365 IRQs that are used by
the codecs. Codecs will also use the IRQs.
Entries are being added to enable/disable IRQ's.
There is no use as such for these entires in the kernel itself.
Instead these will be used by the "linuxutils" package of the DVSDK.
For further information on IRQ muxing refer to
http://focus.ti.com/lit/ug/sprufg5a/sprufg5a.pdf
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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DM365 RBL has been updated. The variant number has changed for this
new revision of silicon. This patch adds support for the
new revision of DM365.
The name fields are also being updated to reflect the version
of the silicon.
Without this minor fix DM365 REV 1.2 will not boot up
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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The mask can hold only 8 bit values. This gave a
compilation warning. This patch rectifies the warning.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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EDMA queues in DM365 are a little different than those
on other DaVinci's. On DM365 Q0 and Q1 have the larger
FIFO size. We want Q0 and Q1 to be used by codecs and
DVSDK demos.
MMC driver is the only driver which uses the flag
'EVENTQ_DEFAULT'. So MMC driver should be using Q2 instead of
Q1 on DM365.
This patch allows us to declare a "default queue" from
SOC specific code. If it is not declared then the EDMA
driver assumes a default of queue 1.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Support DM365 GPIOs ... primarily by handling non-banked GPIO IRQs:
- Flag DM365 chips as using non-banked GPIO interrupts, using a
new soc_info field.
- Replace the gpio_to_irq() mapping logic. This now uses some
runtime infrastructure, keyed off that new soc_info field,
which doesn't handle irq_to_gpio().
- Provide a new irq_chip ... GPIO IRQs handled directly by AINTC
still need edge triggering managed by the GPIO controller.
DM365 chips no longer falsely report 104 GPIO IRQs as they boot.
Intelligence about IRQ muxing is missing, so for the moment this
only exposes the first eight DM365 GPIOs, which are never muxed.
The next eight are muxed, half with Ethernet (which uses most of
those pins anyway).
Tested on DM355 (10 unbanked IRQs _or_ 104 banked ones) and also
on DM365 (16 unbanked ones, only 8 made available).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Patch updates DM365 PINMUX by adding entries for Video, SPI 1 - 4,
PWM 0 - 3.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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The patch adds Support for EMAC in the DM365 SOC and
the DM365 EVM board.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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The patch adds base support for new TI SOC DM365, which s
similar to the dm355.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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