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2007-02-14[ARM] 4184/1: iop: cp6 access handler (undef_hook)Dan Williams
Enable svc access to cp6 via an undefined instruction hook. Do not enable access for usr code. This patch also makes iop13xx select PLAT_IOP, this requires a small change to drivers/i2c/busses/i2c-iop3xx.c. Per Lennert Buytenhek's note, the cp6 trap routine is moved to arch/arm/plat-iop Per Nicolas Pitre's note, the cp_wait is skipped since the latency to return to the faulting function is longer than cp_wait. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-30[ARM] 4077/1: iop13xx: fix __io() macroDan Williams
Since iop13xx defines the PCI I/O spaces with physical resource addresses the __io macro needs to perform the physical to virtual conversion. I incorrectly assumed that this would be handled by ioremap, but drivers (like e1000) directly dereference the address returned from __io. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-19[ARM] 4022/1: iop13xx: generic irq fixupsDan Williams
* use irq_chip * use handle_level_irq Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-18[ARM] 4056/1: iop13xx: fix resource.end off-by-one in flash setupLennert Buytenhek
The struct resource 'end' field is inclusive, the iop13xx flash setup code got this wrong. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-18[ARM] 4055/1: iop13xx: fix phys_io/io_pg_offst for iq81340mc/scLennert Buytenhek
The phys_io/io_pg_offst machine record variables were being set to bogus values, causing problems when enabling DEBUG_LL. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-07[ARM] 3995/1: iop13xx: add iop13xx supportDan Williams
The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz PCI-X interface, a x8 PCI-Express interface, and other peripherals to form a system-on-a-chip RAID subsystem engine. The iop342 processor replaces the SAS controller with a second Xscale core for dual core embedded applications. The iop341 processor is the single core version of iop342. This patch supports the two Intel customer reference platforms iq81340mc for external storage and iq81340sc for direct attach (HBA) development. The developer's manual is available here: ftp://download.intel.com/design/iio/docs/31503701.pdf Changelog: * removed virtual addresses from resource definitions * cleaned up some unnecessary #include's Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>