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Since we're now using addruart to establish the debug mapping, we can
remove the io_pg_offst and phys_io members of struct machine_desc.
The various declarations were removed using the following script:
grep -rl MACHINE_START arch/arm | xargs \
sed -i '/MACHINE_START/,/MACHINE_END/ { /\.\(phys_io\|io_pg_offst\)/d }'
[ Initial patch was from Jeremy Kerr, example script from Russell King ]
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Eric Miao <eric.miao at canonical.com>
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Rather than checking the MMU status in every instance of addruart, do it
once in kernel/debug.S, and change the existing addruart macros to
return both physical and virtual addresses. The main debug code can then
select the appropriate address to use.
This will also allow us to retreive the address of a uart for the MMU
state that we're not current in.
Updated with fixes for OMAP from Jason Wang <jason77.wang@gmail.com>
and Tony Lindgren <tony@atomide.com>, and fix for versatile express from
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>.
Signed-off-by: Jeremy Kerr <jeremy.kerr@canonical.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Jason Wang <jason77.wang@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tested-by: Kevin Hilman <khilman@deeprootsystems.com>
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This fixes the regression caused by the commit 6fee48cd330c68
("dma-mapping: arm: use generic pci_set_dma_mask and
pci_set_consistent_dma_mask").
ARM needs to clip the dma coherent mask for dmabounce devices. This
restores the old trick.
Note that strictly speaking, the DMA API doesn't allow architectures to do
such but I'm not sure it's worth adding the new API to set the dma mask
that allows architectures to clip it.
Reported-by: Krzysztof Halasa <khc@pm.waw.pl>
Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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* git://git.infradead.org/mtd-2.6:
mtd/nand_ids: Fix buswidth
mtd/m25p80: fix test for end of loop
mtd/m25p80: retlen is never NULL
MIPS: Fix gen_nand probe structures contents
gen_nand: Test if nr_chips field is valid
BFIN: Fix gen_nand probe structures contents
nand/denali: move all hardware initialization work to denali_hw_init
nand/denali: Add a page check in denali_read_page & denali_read_page_raw
nand/denali: use cpu_relax() while waiting for hardware interrupt
nand/denali: change read_status function method
nand/denali: Fixed check patch warnings
ARM: Fix gen_nand probe structures contents
mtd/nand_base: fix kernel-doc warnings & typos
nand/denali: use dev_xx debug function to replace nand_dbg_print and some printk
nand/denali: Fixed handle ECC error bugs
nand/denali: use iowrite32() to replace denali_write32()
nand/denali: Fixed probe function bugs
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These three platforms didn't properly fill nr_chips in gen_nand
registration and therefore depended on gen_nand bug fixed by commit
81cbb0b17796d81cbd92defe113cf2a7c7a21fbb ("mtd: gen_nand: fix support for
multiple chips")
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/chris/linux-2.6
* 'ixp4xx' of git://git.kernel.org/pub/scm/linux/kernel/git/chris/linux-2.6:
IXP4xx: Fix LL debugging on little-endian CPU.
IXP4xx: Fix sparse warnings in I/O primitives.
IXP4xx: Make mdio_bus struct static in the Ethernet driver.
IXP4xx: Fix ixp4xx_crypto little-endian operation.
IXP4xx: Prevent HSS transmitter lockup by disabling FRaMe signals.
ixp4xx/vulcan: add PCI support
ixp4xx: base support for Arcom Vulcan
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Conflicts:
arch/arm/mm/init.c
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Add one more parameter to hook_fault_code() to be able to set 'code'
field of struct fsr_info.
Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Since we no longer support discontigmem, node is always zero, so
remove this argument.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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IXP4xx only needs +3 offset for UART registers when running in big-endian mode.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Add PCI support for the Vulcan board, supporting USB and CF ports.
The PC/104 bus (actually a hack on the second CarBus slot) is not
currently supported.
Signed-off-by: Marc Zyngier <maz@misterjones.org>
Cc: Imre Kaloz <kaloz@openwrt.org>
Cc: Krzysztof Halasa <khc@pm.waw.pl>
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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This patch adds some basic support for the Arcom Vulcan (ixp425 based).
Supported devices include:
- XR16L551 serial ports
- External watchdog
- Flash
- SRAM
- 1-wire id
Signed-off-by: Marc Zyngier <maz@misterjones.org>
Cc: Imre Kaloz <kaloz@openwrt.org>
Cc: Krzysztof Halasa <khc@pm.waw.pl>
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Conflicts:
arch/arm/Kconfig
arch/arm/include/asm/system.h
arch/arm/mm/Kconfig
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These files include linux/bootmem.h without using anything from this
file; remove the unnecessary include.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
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This converts arm to the generic pci_set_dma_mask and
pci_set_consistent_dma_mask (removes HAVE_ARCH_PCI_SET_DMA_MASK for
dmabounce).
Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Looked-over-by: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Greg KH <greg@kroah.com>
Cc: Kay Sievers <kay.sievers@vrfy.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Conflicts:
arch/arm/Kconfig
arch/arm/mach-ux500/include/mach/debug-macro.S
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Makes it consistent with VMALLOC_START
Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Otherwise more complicated uart configuration won't be possible.
We can use r1 for tmp register for both head.S and debug.S.
NOTE: This patch depends on another patch to add the the tmp register
into all debug-macro.S files. That can be done with:
$ sed -i -e "s/addruart,rx|addruart, rx/addruart, rx, tmp/"
arch/arm/*/include/*/debug-macro.S
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add a better sched_clock() to the ixp4xx platform,
implemented via its clocksource support.
This is based on the sched_clock() I implemented for
the IOP platform. Tested on a ds101 ixp420 machine.
Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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PrPMC1100 is handled by IXDP425 platform code, there is no need for
duplicate set of macros. Remove them.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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IXP4xx CPUs can indirectly access the whole 4 GB PCI MMIO address space (using
the non-prefetch registers). Previously the available space depended on the CPU
variant, since one of the IXP43x platforms needed more than the usual 128 MB.
1 GB should be enough for everyone, and if not, we can trivially increase it.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Instead of including the heavy linux/mm.h for VMALLOC_START, test the addresses
against PCI MIN and MAX addresses. Indirect PCI uses 1:1 mapping for MMIO space
making this change possible.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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clarity.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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The indexes were signed, so negatives were possible.
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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The repetitive in/out functions must preserve order, not value.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Clock generators used by IXP4xx processors are usually 33.333 MHz, sometimes
33.33 MHz and few platforms use 33 MHz. The timers tick twice as fast,
that means 66.666, 66.66 or 66 MHz. Current 66.666666 MHz means 10 ppm
offset from the usual 66.666 MHz.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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The body of the mach-ixp4xx arch_idle() is mysteriously
disabled by an #if 0 .. #endif. Normally one would expect
to find a call to cpu_do_idle() there, but that call is
disabled, even though cpu_do_idle() is implemented for
XScale cores (and ixp4xx is one).
The explanation can be found in the ixp42x developer's manual
which states that the XScale core clock and power management
registers aren't implemented on ixp42x [3.5.2.2].
Also, the disabled code has suffered from bit rot:
- it checks hlt_counter which is obsolete, as that variable
and all related code now is private to kernel/process.c
- it passes too many parameters to cpu_do_idle()
So this patch:
- adds a comment before the #if 0 to explain why
cpu_do_idle() mustn't be called on ixp4xx
- removes the obsolete test of hlt_counter and the
obsolete parameter to cpu_do_idle()
This is purely a documentation fixup and changes no
generated code. Even so, it has been tested on an
ixp420 machine (ds101).
Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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This patch does a few simple cleanups of the ixp4xx timer
and clocksource/clockevent code in mach-ixp4xx/common.c:
- ixp4xx_clocksource_init() is static and always returns 0,
which is ignored by its only caller: make it return void
- ixp4xx_clockevent_init(): ditto
- ixp4xx_get_cycles() is only referenced locally: make it static
- use the ixp4xx_timer_irq.dev_id field to pass &clockevent_ixp4xx
to ixp4xx_timer_interrupt() via its dev_id parameter, allowing
the code in ixp4xx_timer_interrupt() to be smaller and faster
Tested on an ixp420 machine (ds101).
Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6: (1623 commits)
netxen: update copyright
netxen: fix tx timeout recovery
netxen: fix file firmware leak
netxen: improve pci memory access
netxen: change firmware write size
tg3: Fix return ring size breakage
netxen: build fix for INET=n
cdc-phonet: autoconfigure Phonet address
Phonet: back-end for autoconfigured addresses
Phonet: fix netlink address dump error handling
ipv6: Add IFA_F_DADFAILED flag
net: Add DEVTYPE support for Ethernet based devices
mv643xx_eth.c: remove unused txq_set_wrr()
ucc_geth: Fix hangs after switching from full to half duplex
ucc_geth: Rearrange some code to avoid forward declarations
phy/marvell: Make non-aneg speed/duplex forcing work for 88E1111 PHYs
drivers/net/phy: introduce missing kfree
drivers/net/wan: introduce missing kfree
net: force bridge module(s) to be GPL
Subject: [PATCH] appletalk: Fix skb leak when ipddp interface is not loaded
...
Fixed up trivial conflicts:
- arch/x86/include/asm/socket.h
converted to <asm-generic/socket.h> in the x86 tree. The generic
header has the same new #define's, so that works out fine.
- drivers/net/tun.c
fix conflict between 89f56d1e9 ("tun: reuse struct sock fields") that
switched over to using 'tun->socket.sk' instead of the redundantly
available (and thus removed) 'tun->sk', and 2b980dbd ("lsm: Add hooks
to the TUN driver") which added a new 'tun->sk' use.
Noted in 'next' by Stephen Rothwell.
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HSS usually uses external clocks, so it's not a big deal. Internal clock
is used for direct DTE-DTE connections and when the DCE doesn't provide
it's own clock.
This also depends on the oscillator frequency. Intel seems to have
calculated the clock register settings for 33.33 MHz (66.66 MHz timer
base). Their settings seem quite suboptimal both in terms of average
frequency (60 ppm is unacceptable for G.703 applications, their primary
intended usage(?)) and jitter.
Many (most?) platforms use a 33.333 MHz oscillator, a 10 ppm difference
from Intel's base.
Instead of creating static tables, I've created a procedure to program
the HSS clock register. The register consists of 3 parts (A, B, C).
The average frequency (= bit rate) is:
66.66x MHz / (A + (B + 1) / (C + 1))
The procedure aims at the closest average frequency, possibly at the
cost of increased jitter. Nobody would be able to directly drive an
unbufferred transmitter with a HSS anyway, and the frequency error is
what it really counts.
I've verified the above with an oscilloscope on IXP425. It seems IXP46x
and possibly IXP43x use a bit different clock generation algorithm - it
looks like the avg frequency is:
(on IXP465) 66.66x MHz / (A + B / (C + 1)).
Also they use much greater precomputed A and B - on IXP425 it would
simply result in more jitter, but I don't know how does it work on
IXP46x (perhaps 3 least significant bits aren't used?).
Anyway it looks that they were aiming for exactly +60 ppm or -60 ppm,
while <1 ppm is typically possible (with a synchronized clock, of
course).
The attached patch makes it possible to set almost any bit rate
(my IXP425 533 MHz quits at > 22 Mb/s if a single port is used, and the
minimum is ca. 65 Kb/s).
This is independent of MVIP (multi-E1/T1 on one HSS) mode.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
Signed-off-by: David S. Miller <davem@davemloft.net>
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2.6.31-rc kernels don't boot on my ixp4xx box (ds101), because the libata
driver doesn't find the PCI IDE controller any more. 2.6.30 was fine.
I traced this to a PCI update (1f82de10d6b1d845155363c895c552e61b36b51a)
in 2.6.30-git19. Diffing the kernel boot logs from 2.6.30-git18 and
2.6.30-git19 illustrates the breakage:
> --- dmesg-2.6.30-git18 2009-08-04 01:45:22.000000000 +0200
> +++ dmesg-2.6.30-git19 2009-08-04 01:45:46.000000000 +0200
> @@ -26,6 +26,13 @@
> pci 0000:00:02.2: PME# supported from D0 D1 D2 D3hot
> pci 0000:00:02.2: PME# disabled
> PCI: bus0: Fast back to back transfers disabled
> +pci 0000:00:01.0: BAR 0: can't allocate I/O resource [0x10000-0xffff]
> +pci 0000:00:01.0: BAR 1: can't allocate I/O resource [0x10000-0xffff]
> +pci 0000:00:01.0: BAR 2: can't allocate I/O resource [0x10000-0xffff]
> +pci 0000:00:01.0: BAR 3: can't allocate I/O resource [0x10000-0xffff]
> +pci 0000:00:01.0: BAR 4: can't allocate I/O resource [0x10000-0xffff]
> +pci 0000:00:02.0: BAR 4: can't allocate I/O resource [0x10000-0xffff]
> +pci 0000:00:02.1: BAR 4: can't allocate I/O resource [0x10000-0xffff]
> bio: create slab <bio-0> at 0
> SCSI subsystem initialized
> NET: Registered protocol family 2
> @@ -44,11 +51,7 @@
> console [ttyS0] enabled
> serial8250.0: ttyS1 at MMIO 0xc8001000 (irq = 13) is a XScale
> Driver 'sd' needs updating - please use bus_type methods
> -PCI: enabling device 0000:00:01.0 (0140 -> 0141)
> -scsi0 : pata_artop
> -scsi1 : pata_artop
> -ata1: PATA max UDMA/100 cmd 0x1050 ctl 0x1060 bmdma 0x1040 irq 28
> -ata2: PATA max UDMA/100 cmd 0x1058 ctl 0x1064 bmdma 0x1048 irq 28
> +pata_artop 0000:00:01.0: no available native port
> Using configured DiskOnChip probe address 0x50000000
> DiskOnChip found at 0x50000000
> NAND device: Manufacturer ID: 0x98, Chip ID: 0x73 (Toshiba NAND 16MiB 3,3V 8-bit)
The specific change in 1f82de10d6b1d845155363c895c552e61b36b51a responsible
for this failure turned out to be the following:
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -193,7 +193,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
> res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
> if (type == pci_bar_io) {
> l &= PCI_BASE_ADDRESS_IO_MASK;
> - mask = PCI_BASE_ADDRESS_IO_MASK & 0xffff;
> + mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
> } else {
> l &= PCI_BASE_ADDRESS_MEM_MASK;
> mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
Every arch except arm's ixp4xx defines IO_SPACE_LIMIT as an all-bits-one
bitmask, typically -1UL but sometimes only a 16-bit 0x0000ffff. But ixp4xx
defines it as 0xffff0000, which is now causing the PCI failures.
Russell King noted that ixp4xx has 64KB PCI IO space, so IO_SPACE_LIMIT
should be 0x0000ffff. This patch makes that change, which fixes the PCI
failures on my ixp4xx box.
Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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comments.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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