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2010-02-24OMAP3/4 clock: split into per-chip family filesPaul Walmsley
clock34xx_data.c now contains data for the OMAP34xx family, the OMAP36xx family, and the OMAP3517 family, so rename it to clock3xxx_data.c. Rename clock34xx.c to clock3xxx.c, and move the chip family-specific clock functions to clock34xx.c, clock36xx.c, or clock3517.c, as appropriate. So now "clock3xxx.*" refers to the OMAP3 superset. The main goal here is to prepare to compile chip family-specific clock functions only for kernel builds that target that chip family. To get to that point, we also need to add CONFIG_SOC_* options for those other chip families; that will be done in future patches, planned for 2.6.35. OMAP4 is also affected by this. It duplicated the OMAP3 non-CORE DPLL clkops structure. The OMAP4 variant of this clkops structure has been removed, and since there was nothing else currently in clock44xx.c, it too has been removed -- it can always be added back later when there is some content for it. (The OMAP4 clock autogeneration scripts have been updated accordingly.) Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Ranjith Lohithakshan <ranjithl@ti.com> Cc: Tony Lindgren <tony@atomide.com>
2010-02-24OMAP clock: drop .id field; ensure each clock has a unique namePaul Walmsley
After the clkdev conversion, the struct clk.id field became superfluous, so, drop it. Bring the clock names closer to the TRMs and ensure they are unique for debugfs. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, ↵Paul Walmsley
includes, documentation The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are one increment higher than they should be. See for example the OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL". Programming a 0 into the DPLL's M register bitfield is valid for OMAP2/3 and indicates that the DPLL should enter MN-bypass mode. Also, increase the minimum multiplier (M) value for the DPLL rate rounding code from 1 to 2, to ensure that it does not inadvertently put the DPLL into bypass. Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs does not make clear that the actual DPLL divider value (the "N") is the content of the appropriate register bitfield for the N value, _plus one_. (In other words, an N register bitfield of 0 indicates a DPLL divider value of 1.) This is only clearly documented in the OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167 "CM_CLKSEL_DPLL_USB". While here, update copyrights, add kerneldoc for struct dpll_data, drop the unused struct dpll_data.max_tolerance field, remove some unnecessary #includes in DPLL-related code, and replace the #include of <linux/module.h> with <linux/list.h>, which is what was really needed. The OMAP4 clock autogenerator script has been updated accordingly. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-24OMAP3 clock: add support for 192Mhz DPLL4M2 outputVishwanath BS
In 3630, DPLL4M2 output can be 96MHz or 192MHz (for SGX to run at 192). This patch has changes to support this feature. 96MHz clock is generated by dividing 192Mhz clock by 2 using CM_CLKSEL_CORE register. SGX can select Core Clock, 192MHz clock or CM_96M_FCLK as it's functional clock. In summary changes done are: 1. Added a feature called omap3_has_192mhz_clk and enabled for 3630 2. Added a new clock node called omap_192m_alwon_ck 3. Made omap_96m_alwon_fck to derive its clock from omap_192m_alwon_ck Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com> [paul@pwsan.com: fixed whitespace] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24OMAP3 clock: Introduce 3630 DPLL4 HSDivider changesVishwanath BS
Divider (M2, M3, M4, M5 and M6) field width has been increased by 1 bit in 3630. This patch has changes to accommodate this in CM dynamically based on chip version. Basically new clock nodes have been added for 3630 DPLL4 M2,M3,M4,M5 and M6 and value of these nodes are used if cpu type is 3630. Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> [paul@pwsan.com: updated to apply on 2.6.34 queue; comments added] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24OMAP3 clock: introduce DPLL4 JtypeRichard Woodruff
DPLL4 for 3630 introduces a changed block called j type dpll, requiring special divisor bits and additional reg fields. To allow for silicons to use this, this is introduced as a flag and is enabled for 3630 silicon. OMAP4 also has j type dpll for usb. Tested with 3630 ZOOM3 and OMAP3430 ZOOM2 Signed-off-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com> [paul@pwsan.com: added some comments; updated copyrights and credits; fixed some style issues] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24OMAP3630: Clock: Workaround for DPLL HS divider limitationMike Turquette
This patch implements a workaround for the DPLL HS divider limitation in OMAP3630 as given by Errata ID: i556. Errata: When PWRDN bit is set, it resets the internal HSDIVIDER divide-by value (Mx). The reset value gets loaded instead of the previous value. The following HSDIVIDERs exhibit above behavior: . DPLL4 : M6 / M5 / M4 / M3 / M2 (CM_CLKEN_PLL[31:26] register bits) . DPLL3 : M3 (CM_CLKEN_PLL[12] register bit). Work Around: It is mandatory to apply the following sequence to ensure the write value will be loaded in DPLL HSDIVIDER FSM: The global sequence when using PWRDN bit is the following: . Disable Mx HSDIVIDER clock output related functional clock enable bits (in CM_FCLKEN_xxx / CM_ICLKEN_xxx) . Enable PWRDN bit of HSDIVIDER . Disable PWRDN bit of HSDIVIDER . Read current HSDIVIDER register value . Write different value in HSDIVIDER register . Write expected value in HSDIVIDER register . Enable Mx HSDIVIDER clock output related functional clocks (CM_FCLKEN_xxx / CM_ICLKEN_xxx) Signed-off-by: Mike Turquette <mturquette@ti.com> Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Vijaykumar GN <vijaykumar.gn@ti.com> [paul@pwsan.com: updated patch to apply; made workaround function static; marked as being 36xx-specific] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24AM35xx: Add clock support for new modules on AM35xxRanjith Lohithakshan
This patch adds clock support for the following AM35xx modules - Ethernet MAC - CAN Controller (HECC) - New MUSB OTG Controller with integrated Phy - Video Processing Front End (VPFE) - Additional UART (UART4) Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-15omap3/4: Fix compile for multi-omap for clkops_noncore_dpll_opsTony Lindgren
Rename clkops_noncore_dpll_ops for omap3 and omap4. Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-29OMAP2/3/4 clock: rename and clean the omap2_clk_init() functionsPaul Walmsley
Rename the omap2_clk_init() in the OMAP2, 3, and 4 clock code to be omap2xxx_clk_init(), omap3xxx_clk_init(), etc. Remove all traces of the (commented) old virt_prcm_set code from omap3xxx_clk_init() and omap4xxx_clk_init(), since this will be handled with the OPP code that is cooking in the PM branch. After this patch, there should be very little else in the clock code that blocks a multi-OMAP 2+3 kernel. (OMAP2420+OMAP2430 still has some outstanding issues that need to be resolved; this is pending on some additions to the hwmod data.) Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-01-26OMAP clock: make the fixed divisor clock code available for all OMAPsPaul Walmsley
One of the OMAP1 clocks can use the fixed divisor recalculation code introduced in the OMAP2 clock code, so rename the omap2_fixed_divisor_recalc() function to omap_fixed_divisor_recalc() and make it available to all OMAPs. A followup patch converts the OMAP1 clock. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-01-26AM35xx: Clock table updates for AM3505/17Ranjith Lohithakshan
AM3505/17 though a OMAP3530 derivative have the following main differences - Removal of the following OMAP3 modules - IVA - ISP/CAM - Modem and D2D components (MAD2D, SAD2D) - USIM - SSI - Mailboxes - USB OTG - ICR - MSPRO - SmartReflex - SDRC replaced with EMIF4 Controller in the SDRC subsystem thus adding support for DDR2 memory devices - Addition of the following new modules - Ethernet MAC (CPGMAC) - CAN Controller (HECC) - New USB OTG Controller with integrated Phy - Video Processing Front End (VPFE) - Additional UART (UART4) - All security accelerators disabled on GP devices and not to be accessed or configured This patch defines CPU flags for AM3505/17 and update the clock table. Clock support for new modules will be added by subsequent patches. Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com> [paul@pwsan.com: updated for 2.6.34 clock layout] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-01-26OMAP3 clock: reorganize CK_* platform flagsPaul Walmsley
Add CK_* flags for the two new Sitara chips, AM3505 and AM3517, and the OMAP34xx die shrink, OMAP36xx/OMAP37xx. Introduce a new CK_* flag, CK_3XXX, that marks all clocks that are common to OMAP3 family chips. CK_343X now refers to clocks that are available only on OMAP34{1,2,3,4}0 (WTBU) and OMAP35{03,15,25,30} (any version). At some point, the RATE_IN_* flags should be updated also. While here, add some documentation describing the chip families covered by these clock flags. This patch is partially based on patches from Ranjith Lohithakshan <ranjithl@ti.com> and Vishwanath Sripathy <vishwanath.bs@ti.com>. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Ranjith Lohithakshan <ranjithl@ti.com> Cc: Vishwanath Sripathy <vishwanath.bs@ti.com>
2010-01-19OMAP3: clock: Remove unnecessarily .init initializers from OMAP3 clocksRussell King
The first thing that omap2_init_clksel_parent() does is check for a non-zero .clksel field in the struct clk. Therefore, it is pointless calling this function on clocks where the clksel field is unset. Remove init calls to omap2_init_clksel_parent() on clocks without a clksel field. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-01-08OMAP3 clock: Add capability to change rate of dpll4_m5_ckTuukka Toivonen
Add necessary definitions to clock framework to allow changing dpll4_m5_ck rate. This is used by the camera code. Signed-off-by: Jouni Högander <jouni.hogander@nokia.com> Signed-off-by: Tuukka Toivonen <tuukka.o.toivonen@nokia.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-01-08OMAP3 clock: McBSP 2, 3, 4 functional clock parent is PER_96M_FCLK, not ↵Paul Walmsley
CORE_96M_FCLK The correct parent of the McBSP 2, 3, and 4 functional clocks is PER_96M_FCLK, not CORE_96M_FCLK. Fix this in the OMAP clock tree. Reported by Nicole Chalhoub <n-chalhoub@ti.com>. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Nicole Chalhoub <n-chalhoub@ti.com>
2010-01-08OMAP3: clock: add clockdomains for UART1 & 2Kevin Hilman
UART1 & 2 were missing clockdomains resulting in broken omap_hwmod init for these devices. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-12-11OMAP3 clock: convert clock34xx.h to clock34xx_data.cPaul Walmsley
The OMAP3 clock code currently #includes a large .h file full of static data structures. Instead, define the data in a .c file. Russell King <linux@arm.linux.org.uk> proposed this new arrangement: http://marc.info/?l=linux-omap&m=125967425908895&w=2 Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Russell King <linux@arm.linux.org.uk>