summaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-prima2/Makefile
AgeCommit message (Collapse)Author
2012-08-28ARM: SIRF: make sirf irqchip driver optional since new SoCs will have GICBarry Song
New MARCO and POLO SoC use GIC, so make irq.c optional and enable it only if we enable ARCH_PRIMA2 in Kconfig Signed-off-by: Barry Song <Baohua.Song@csr.com>
2012-08-28ARM: PRIMA2: use DT_MACHINE_START and convert to generic boardBarry Song
we will have SiRFMarco and SiRFPolo, all of them will be in the generic board. Signed-off-by: Barry Song <Baohua.Song@csr.com>
2012-08-24clk: prima2: move from arch/arm/mach to drivers/clkBarry Song
Signed-off-by: Barry Song <Baohua.Song@csr.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2011-09-21ARM: CSR: PM: add sleep entry for SiRFprimaIIRongjun Ying
This patch adds suspend-to-mem support for prima2. It will make prima2 enter DEEPSLEEP mode while accepting PM_SUSPEND_MEM command. Signed-off-by: Rongjun Ying <rongjun.ying@csr.com> Signed-off-by: Barry Song <baohua.song@csr.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-09-11ARM: CSR: add rtc i/o bridge interface for SiRFprimaIIZhiwu Song
The module is a bridge between the RTC clock domain and the CPU interface clock domain. ARM access the register of SYSRTC, GPSRTC and PWRC through this module. Signed-off-by: Zhiwu Song <zhiwu.song@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-07-09ARM: CSR: initializing L2 cacheRongjun Ying
Signed-off-by: Rongjun Ying <rongjun.ying@csr.com> Signed-off-by: Barry Song <baohua.song@csr.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2011-07-09ARM: CSR: mapping early DEBUG_LL uartBarry Song
Signed-off-by: Barry Song <baohua.song@csr.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2011-07-09ARM: CSR: Adding CSR SiRFprimaII board supportBinghua Duan
SiRFprimaII is the latest generation application processor from CSR’s Multifunction SoC product family. Designed around an ARM cortex A9 core, high-speed memory bus, advanced 3D accelerator and full-HD multi-format video decoder, SiRFprimaII is able to meet the needs of complicated applications for modern multifunction devices that require heavy concurrent applications and fluid user experience. Integrated with GPS baseband, analog and PMU, this new platform is designed to provide a cost effective solution for Automotive and Consumer markets. This patch adds the basic support for this SoC and EVB board based on device tree. It is following the ZYNQ of Xilinx in some degree. Signed-off-by: Binghua Duan <Binghua.Duan@csr.com> Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com> Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com> Signed-off-by: Yuping Luo <Yuping.Luo@csr.com> Signed-off-by: Bin Shi <Bin.Shi@csr.com> Signed-off-by: Huayi Li <Huayi.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>